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-rw-r--r--drivers/gpu/drm/i915/intel_dp.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 8aecb072466..dcc7ae6d414 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1334,10 +1334,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
1334 u32 reg; 1334 u32 reg;
1335 uint32_t DP = intel_dp->DP; 1335 uint32_t DP = intel_dp->DP;
1336 1336
1337 /* Enable output, wait for it to become active */ 1337 /*
1338 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 1338 * On CPT we have to enable the port in training pattern 1, which
1339 POSTING_READ(intel_dp->output_reg); 1339 * will happen below in intel_dp_set_link_train. Otherwise, enable
1340 intel_wait_for_vblank(dev, intel_crtc->pipe); 1340 * the port and wait for it to become active.
1341 */
1342 if (!HAS_PCH_CPT(dev)) {
1343 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1344 POSTING_READ(intel_dp->output_reg);
1345 intel_wait_for_vblank(dev, intel_crtc->pipe);
1346 }
1341 1347
1342 /* Write the link configuration data */ 1348 /* Write the link configuration data */
1343 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, 1349 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,