2 files changed, 6 insertions, 1 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cd0ffa015c2..78f336e0083 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2039,6 +2039,11 @@
 #define PFA_CTL_1               0x68080
 #define PFB_CTL_1               0x68880
 #define  PF_ENABLE              (1<<31)
+#define  PF_FILTER_MASK         (3<<23)
+#define  PF_FILTER_PROGRAMMED   (0<<23)
+#define  PF_FILTER_MED_3x3      (1<<23)
+#define  PF_FILTER_EDGE_ENHANCE (2<<23)
+#define  PF_FILTER_EDGE_SOFTEN  (3<<23)
 #define PFA_WIN_SZ              0x68074
 #define PFB_WIN_SZ              0x68874
 #define PFA_WIN_POS             0x68070
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index db4c3870095..e189fd6dedc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1515,7 +1515,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
                 /* Enable panel fitting for LVDS */
                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                         temp = I915_READ(pf_ctl_reg);
-                        I915_WRITE(pf_ctl_reg, temp | PF_ENABLE);
+                        I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
 
                         /* currently full aspect */
                         I915_WRITE(pf_win_pos, 0);