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-rw-r--r--drivers/gpu/drm/Kconfig1
-rw-r--r--drivers/gpu/drm/drm_crtc_helper.c1
-rw-r--r--drivers/gpu/drm/drm_edid.c6
-rw-r--r--drivers/gpu/drm/drm_fb_helper.c8
-rw-r--r--drivers/gpu/drm/drm_gem.c2
-rw-r--r--drivers/gpu/drm/drm_mm.c9
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c4
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c3
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c5
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h53
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c10
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h30
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c341
-rw-r--r--drivers/gpu/drm/i915/intel_bios.c14
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c4
-rw-r--r--drivers/gpu/drm/i915/intel_display.c193
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c2
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c26
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c35
-rw-r--r--drivers/gpu/drm/radeon/Makefile2
-rw-r--r--drivers/gpu/drm/radeon/atom.c1
-rw-r--r--drivers/gpu/drm/radeon/atombios.h2
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c357
-rw-r--r--drivers/gpu/drm/radeon/mkregtable.c12
-rw-r--r--drivers/gpu/drm/radeon/r100.c42
-rw-r--r--drivers/gpu/drm/radeon/r300.c2
-rw-r--r--drivers/gpu/drm/radeon/r420.c2
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h9
-rw-r--r--drivers/gpu/drm/radeon/r520.c2
-rw-r--r--drivers/gpu/drm/radeon/r600.c108
-rw-r--r--drivers/gpu/drm/radeon/r600_blit.c58
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c5
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c18
-rw-r--r--drivers/gpu/drm/radeon/r600d.h14
-rw-r--r--drivers/gpu/drm/radeon/radeon.h12
-rw-r--r--drivers/gpu/drm/radeon/radeon_agp.c12
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h23
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c282
-rw-r--r--drivers/gpu/drm/radeon/radeon_benchmark.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_bios.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c287
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c211
-rw-r--r--drivers/gpu/drm/radeon/radeon_cursor.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c31
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c28
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c125
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c20
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c9
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c40
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c27
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h34
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c65
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h6
-rw-r--r--drivers/gpu/drm/radeon/radeon_test.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c6
-rw-r--r--drivers/gpu/drm/radeon/rs400.c2
-rw-r--r--drivers/gpu/drm/radeon/rs600.c20
-rw-r--r--drivers/gpu/drm/radeon/rs690.c2
-rw-r--r--drivers/gpu/drm/radeon/rv515.c9
-rw-r--r--drivers/gpu/drm/radeon/rv770.c59
-rw-r--r--drivers/gpu/drm/radeon/rv770d.h5
-rw-r--r--drivers/gpu/drm/ttm/ttm_tt.c1
63 files changed, 1946 insertions, 776 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index f831ea15929..96eddd17e05 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -92,6 +92,7 @@ config DRM_I830
92config DRM_I915 92config DRM_I915
93 tristate "i915 driver" 93 tristate "i915 driver"
94 depends on AGP_INTEL 94 depends on AGP_INTEL
95 select SHMEM
95 select DRM_KMS_HELPER 96 select DRM_KMS_HELPER
96 select FB_CFB_FILLRECT 97 select FB_CFB_FILLRECT
97 select FB_CFB_COPYAREA 98 select FB_CFB_COPYAREA
diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c
index 1fe4e1d344f..bbfd110a716 100644
--- a/drivers/gpu/drm/drm_crtc_helper.c
+++ b/drivers/gpu/drm/drm_crtc_helper.c
@@ -331,6 +331,7 @@ create_mode:
331 cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60, 331 cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60,
332 cmdline_mode->rb, cmdline_mode->interlace, 332 cmdline_mode->rb, cmdline_mode->interlace,
333 cmdline_mode->margins); 333 cmdline_mode->margins);
334 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
334 list_add(&mode->head, &connector->modes); 335 list_add(&mode->head, &connector->modes);
335 return mode; 336 return mode;
336} 337}
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index cea665d86dd..b54ba63d506 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -662,6 +662,12 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
662 return NULL; 662 return NULL;
663 } 663 }
664 664
665 /* Some EDIDs have bogus h/vtotal values */
666 if (mode->hsync_end > mode->htotal)
667 mode->htotal = mode->hsync_end + 1;
668 if (mode->vsync_end > mode->vtotal)
669 mode->vtotal = mode->vsync_end + 1;
670
665 drm_mode_set_name(mode); 671 drm_mode_set_name(mode);
666 672
667 if (pt->misc & DRM_EDID_PT_INTERLACED) 673 if (pt->misc & DRM_EDID_PT_INTERLACED)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 9c924614c41..65ef011fa8b 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -599,7 +599,7 @@ int drm_fb_helper_check_var(struct fb_var_screeninfo *var,
599 struct drm_framebuffer *fb = fb_helper->fb; 599 struct drm_framebuffer *fb = fb_helper->fb;
600 int depth; 600 int depth;
601 601
602 if (var->pixclock == -1 || !var->pixclock) 602 if (var->pixclock != 0)
603 return -EINVAL; 603 return -EINVAL;
604 604
605 /* Need to resize the fb object !!! */ 605 /* Need to resize the fb object !!! */
@@ -691,7 +691,7 @@ int drm_fb_helper_set_par(struct fb_info *info)
691 int ret; 691 int ret;
692 int i; 692 int i;
693 693
694 if (var->pixclock != -1) { 694 if (var->pixclock != 0) {
695 DRM_ERROR("PIXEL CLCOK SET\n"); 695 DRM_ERROR("PIXEL CLCOK SET\n");
696 return -EINVAL; 696 return -EINVAL;
697 } 697 }
@@ -707,7 +707,7 @@ int drm_fb_helper_set_par(struct fb_info *info)
707 707
708 if (crtc->fb == fb_helper->crtc_info[i].mode_set.fb) { 708 if (crtc->fb == fb_helper->crtc_info[i].mode_set.fb) {
709 mutex_lock(&dev->mode_config.mutex); 709 mutex_lock(&dev->mode_config.mutex);
710 ret = crtc->funcs->set_config(&fb_helper->crtc_info->mode_set); 710 ret = crtc->funcs->set_config(&fb_helper->crtc_info[i].mode_set);
711 mutex_unlock(&dev->mode_config.mutex); 711 mutex_unlock(&dev->mode_config.mutex);
712 if (ret) 712 if (ret)
713 return ret; 713 return ret;
@@ -904,7 +904,7 @@ int drm_fb_helper_single_fb_probe(struct drm_device *dev,
904 fb_helper->fb = fb; 904 fb_helper->fb = fb;
905 905
906 if (new_fb) { 906 if (new_fb) {
907 info->var.pixclock = -1; 907 info->var.pixclock = 0;
908 if (register_framebuffer(info) < 0) 908 if (register_framebuffer(info) < 0)
909 return -EINVAL; 909 return -EINVAL;
910 } else { 910 } else {
diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
index 80391995bde..e9dbb481c46 100644
--- a/drivers/gpu/drm/drm_gem.c
+++ b/drivers/gpu/drm/drm_gem.c
@@ -552,7 +552,7 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma)
552 vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND; 552 vma->vm_flags |= VM_RESERVED | VM_IO | VM_PFNMAP | VM_DONTEXPAND;
553 vma->vm_ops = obj->dev->driver->gem_vm_ops; 553 vma->vm_ops = obj->dev->driver->gem_vm_ops;
554 vma->vm_private_data = map->handle; 554 vma->vm_private_data = map->handle;
555 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); 555 vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
556 556
557 /* Take a ref for this mapping of the object, so that the fault 557 /* Take a ref for this mapping of the object, so that the fault
558 * handler can dereference the mmap offset's pointer to the object. 558 * handler can dereference the mmap offset's pointer to the object.
diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c
index c861d80fd77..97dc5a4f0de 100644
--- a/drivers/gpu/drm/drm_mm.c
+++ b/drivers/gpu/drm/drm_mm.c
@@ -103,6 +103,11 @@ static struct drm_mm_node *drm_mm_kmalloc(struct drm_mm *mm, int atomic)
103 return child; 103 return child;
104} 104}
105 105
106/* drm_mm_pre_get() - pre allocate drm_mm_node structure
107 * drm_mm: memory manager struct we are pre-allocating for
108 *
109 * Returns 0 on success or -ENOMEM if allocation fails.
110 */
106int drm_mm_pre_get(struct drm_mm *mm) 111int drm_mm_pre_get(struct drm_mm *mm)
107{ 112{
108 struct drm_mm_node *node; 113 struct drm_mm_node *node;
@@ -253,12 +258,14 @@ void drm_mm_put_block(struct drm_mm_node *cur)
253 prev_node->size += next_node->size; 258 prev_node->size += next_node->size;
254 list_del(&next_node->ml_entry); 259 list_del(&next_node->ml_entry);
255 list_del(&next_node->fl_entry); 260 list_del(&next_node->fl_entry);
261 spin_lock(&mm->unused_lock);
256 if (mm->num_unused < MM_UNUSED_TARGET) { 262 if (mm->num_unused < MM_UNUSED_TARGET) {
257 list_add(&next_node->fl_entry, 263 list_add(&next_node->fl_entry,
258 &mm->unused_nodes); 264 &mm->unused_nodes);
259 ++mm->num_unused; 265 ++mm->num_unused;
260 } else 266 } else
261 kfree(next_node); 267 kfree(next_node);
268 spin_unlock(&mm->unused_lock);
262 } else { 269 } else {
263 next_node->size += cur->size; 270 next_node->size += cur->size;
264 next_node->start = cur->start; 271 next_node->start = cur->start;
@@ -271,11 +278,13 @@ void drm_mm_put_block(struct drm_mm_node *cur)
271 list_add(&cur->fl_entry, &mm->fl_entry); 278 list_add(&cur->fl_entry, &mm->fl_entry);
272 } else { 279 } else {
273 list_del(&cur->ml_entry); 280 list_del(&cur->ml_entry);
281 spin_lock(&mm->unused_lock);
274 if (mm->num_unused < MM_UNUSED_TARGET) { 282 if (mm->num_unused < MM_UNUSED_TARGET) {
275 list_add(&cur->fl_entry, &mm->unused_nodes); 283 list_add(&cur->fl_entry, &mm->unused_nodes);
276 ++mm->num_unused; 284 ++mm->num_unused;
277 } else 285 } else
278 kfree(cur); 286 kfree(cur);
287 spin_unlock(&mm->unused_lock);
279 } 288 }
280} 289}
281 290
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index f8ce9a3a420..26bf0552b3c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -267,10 +267,10 @@ static void i915_dump_pages(struct seq_file *m, struct page **pages, int page_co
267 uint32_t *mem; 267 uint32_t *mem;
268 268
269 for (page = 0; page < page_count; page++) { 269 for (page = 0; page < page_count; page++) {
270 mem = kmap(pages[page]); 270 mem = kmap_atomic(pages[page], KM_USER0);
271 for (i = 0; i < PAGE_SIZE; i += 4) 271 for (i = 0; i < PAGE_SIZE; i += 4)
272 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]); 272 seq_printf(m, "%08x : %08x\n", i, mem[i / 4]);
273 kunmap(pages[page]); 273 kunmap_atomic(pages[page], KM_USER0);
274 } 274 }
275} 275}
276 276
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 92aeb918e0c..e5b138be45f 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1227,8 +1227,7 @@ static int i915_load_modeset_init(struct drm_device *dev,
1227 goto out; 1227 goto out;
1228 1228
1229 /* Try to set up FBC with a reasonable compressed buffer size */ 1229 /* Try to set up FBC with a reasonable compressed buffer size */
1230 if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev) || IS_GM45(dev)) && 1230 if (I915_HAS_FBC(dev) && i915_powersave) {
1231 i915_powersave) {
1232 int cfb_size; 1231 int cfb_size;
1233 1232
1234 /* Try to get an 8M buffer... */ 1233 /* Try to get an 8M buffer... */
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b93814c0d3e..7f436ec075f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -89,7 +89,8 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
89 pci_set_power_state(dev->pdev, PCI_D3hot); 89 pci_set_power_state(dev->pdev, PCI_D3hot);
90 } 90 }
91 91
92 dev_priv->suspended = 1; 92 /* Modeset on resume, not lid events */
93 dev_priv->modeset_on_lid = 0;
93 94
94 return 0; 95 return 0;
95} 96}
@@ -124,7 +125,7 @@ static int i915_resume(struct drm_device *dev)
124 drm_helper_resume_force_mode(dev); 125 drm_helper_resume_force_mode(dev);
125 } 126 }
126 127
127 dev_priv->suspended = 0; 128 dev_priv->modeset_on_lid = 0;
128 129
129 return ret; 130 return ret;
130} 131}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6035d3dae85..a725f659119 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -274,7 +274,7 @@ typedef struct drm_i915_private {
274 struct drm_i915_display_funcs display; 274 struct drm_i915_display_funcs display;
275 275
276 /* Register state */ 276 /* Register state */
277 bool suspended; 277 bool modeset_on_lid;
278 u8 saveLBB; 278 u8 saveLBB;
279 u32 saveDSPACNTR; 279 u32 saveDSPACNTR;
280 u32 saveDSPBCNTR; 280 u32 saveDSPBCNTR;
@@ -296,6 +296,13 @@ typedef struct drm_i915_private {
296 u32 saveVBLANK_A; 296 u32 saveVBLANK_A;
297 u32 saveVSYNC_A; 297 u32 saveVSYNC_A;
298 u32 saveBCLRPAT_A; 298 u32 saveBCLRPAT_A;
299 u32 saveTRANSACONF;
300 u32 saveTRANS_HTOTAL_A;
301 u32 saveTRANS_HBLANK_A;
302 u32 saveTRANS_HSYNC_A;
303 u32 saveTRANS_VTOTAL_A;
304 u32 saveTRANS_VBLANK_A;
305 u32 saveTRANS_VSYNC_A;
299 u32 savePIPEASTAT; 306 u32 savePIPEASTAT;
300 u32 saveDSPASTRIDE; 307 u32 saveDSPASTRIDE;
301 u32 saveDSPASIZE; 308 u32 saveDSPASIZE;
@@ -304,8 +311,11 @@ typedef struct drm_i915_private {
304 u32 saveDSPASURF; 311 u32 saveDSPASURF;
305 u32 saveDSPATILEOFF; 312 u32 saveDSPATILEOFF;
306 u32 savePFIT_PGM_RATIOS; 313 u32 savePFIT_PGM_RATIOS;
314 u32 saveBLC_HIST_CTL;
307 u32 saveBLC_PWM_CTL; 315 u32 saveBLC_PWM_CTL;
308 u32 saveBLC_PWM_CTL2; 316 u32 saveBLC_PWM_CTL2;
317 u32 saveBLC_CPU_PWM_CTL;
318 u32 saveBLC_CPU_PWM_CTL2;
309 u32 saveFPB0; 319 u32 saveFPB0;
310 u32 saveFPB1; 320 u32 saveFPB1;
311 u32 saveDPLL_B; 321 u32 saveDPLL_B;
@@ -317,6 +327,13 @@ typedef struct drm_i915_private {
317 u32 saveVBLANK_B; 327 u32 saveVBLANK_B;
318 u32 saveVSYNC_B; 328 u32 saveVSYNC_B;
319 u32 saveBCLRPAT_B; 329 u32 saveBCLRPAT_B;
330 u32 saveTRANSBCONF;
331 u32 saveTRANS_HTOTAL_B;
332 u32 saveTRANS_HBLANK_B;
333 u32 saveTRANS_HSYNC_B;
334 u32 saveTRANS_VTOTAL_B;
335 u32 saveTRANS_VBLANK_B;
336 u32 saveTRANS_VSYNC_B;
320 u32 savePIPEBSTAT; 337 u32 savePIPEBSTAT;
321 u32 saveDSPBSTRIDE; 338 u32 saveDSPBSTRIDE;
322 u32 saveDSPBSIZE; 339 u32 saveDSPBSIZE;
@@ -342,6 +359,7 @@ typedef struct drm_i915_private {
342 u32 savePFIT_CONTROL; 359 u32 savePFIT_CONTROL;
343 u32 save_palette_a[256]; 360 u32 save_palette_a[256];
344 u32 save_palette_b[256]; 361 u32 save_palette_b[256];
362 u32 saveDPFC_CB_BASE;
345 u32 saveFBC_CFB_BASE; 363 u32 saveFBC_CFB_BASE;
346 u32 saveFBC_LL_BASE; 364 u32 saveFBC_LL_BASE;
347 u32 saveFBC_CONTROL; 365 u32 saveFBC_CONTROL;
@@ -349,6 +367,12 @@ typedef struct drm_i915_private {
349 u32 saveIER; 367 u32 saveIER;
350 u32 saveIIR; 368 u32 saveIIR;
351 u32 saveIMR; 369 u32 saveIMR;
370 u32 saveDEIER;
371 u32 saveDEIMR;
372 u32 saveGTIER;
373 u32 saveGTIMR;
374 u32 saveFDI_RXA_IMR;
375 u32 saveFDI_RXB_IMR;
352 u32 saveCACHE_MODE_0; 376 u32 saveCACHE_MODE_0;
353 u32 saveD_STATE; 377 u32 saveD_STATE;
354 u32 saveDSPCLK_GATE_D; 378 u32 saveDSPCLK_GATE_D;
@@ -382,6 +406,26 @@ typedef struct drm_i915_private {
382 u32 savePIPEB_DP_LINK_M; 406 u32 savePIPEB_DP_LINK_M;
383 u32 savePIPEA_DP_LINK_N; 407 u32 savePIPEA_DP_LINK_N;
384 u32 savePIPEB_DP_LINK_N; 408 u32 savePIPEB_DP_LINK_N;
409 u32 saveFDI_RXA_CTL;
410 u32 saveFDI_TXA_CTL;
411 u32 saveFDI_RXB_CTL;
412 u32 saveFDI_TXB_CTL;
413 u32 savePFA_CTL_1;
414 u32 savePFB_CTL_1;
415 u32 savePFA_WIN_SZ;
416 u32 savePFB_WIN_SZ;
417 u32 savePFA_WIN_POS;
418 u32 savePFB_WIN_POS;
419 u32 savePCH_DREF_CONTROL;
420 u32 saveDISP_ARB_CTL;
421 u32 savePIPEA_DATA_M1;
422 u32 savePIPEA_DATA_N1;
423 u32 savePIPEA_LINK_M1;
424 u32 savePIPEA_LINK_N1;
425 u32 savePIPEB_DATA_M1;
426 u32 savePIPEB_DATA_N1;
427 u32 savePIPEB_LINK_M1;
428 u32 savePIPEB_LINK_N1;
385 429
386 struct { 430 struct {
387 struct drm_mm gtt_space; 431 struct drm_mm gtt_space;
@@ -492,6 +536,8 @@ typedef struct drm_i915_private {
492 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; 536 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
493 } mm; 537 } mm;
494 struct sdvo_device_mapping sdvo_mappings[2]; 538 struct sdvo_device_mapping sdvo_mappings[2];
539 /* indicate whether the LVDS_BORDER should be enabled or not */
540 unsigned int lvds_border_bits;
495 541
496 /* Reclocking support */ 542 /* Reclocking support */
497 bool render_reclock_avail; 543 bool render_reclock_avail;
@@ -981,7 +1027,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
981 1027
982#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev)) 1028#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
983#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev)) 1029#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
984#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev))) 1030#define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
1031 (IS_I9XX(dev) || IS_GM45(dev)) && \
1032 !IS_IGD(dev) && \
1033 !IS_IGDNG(dev))
985 1034
986#define PRIMARY_RINGBUFFER_SIZE (128*1024) 1035#define PRIMARY_RINGBUFFER_SIZE (128*1024)
987 1036
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c3ceffa46ea..aa7fd82aa6e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -254,10 +254,15 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
254{ 254{
255 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 255 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
256 int ret = IRQ_NONE; 256 int ret = IRQ_NONE;
257 u32 de_iir, gt_iir; 257 u32 de_iir, gt_iir, de_ier;
258 u32 new_de_iir, new_gt_iir; 258 u32 new_de_iir, new_gt_iir;
259 struct drm_i915_master_private *master_priv; 259 struct drm_i915_master_private *master_priv;
260 260
261 /* disable master interrupt before clearing iir */
262 de_ier = I915_READ(DEIER);
263 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
264 (void)I915_READ(DEIER);
265
261 de_iir = I915_READ(DEIIR); 266 de_iir = I915_READ(DEIIR);
262 gt_iir = I915_READ(GTIIR); 267 gt_iir = I915_READ(GTIIR);
263 268
@@ -290,6 +295,9 @@ irqreturn_t igdng_irq_handler(struct drm_device *dev)
290 gt_iir = new_gt_iir; 295 gt_iir = new_gt_iir;
291 } 296 }
292 297
298 I915_WRITE(DEIER, de_ier);
299 (void)I915_READ(DEIER);
300
293 return ret; 301 return ret;
294} 302}
295 303
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0466ddbeba3..1687edf6879 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -968,6 +968,8 @@
968#define LVDS_PORT_EN (1 << 31) 968#define LVDS_PORT_EN (1 << 31)
969/* Selects pipe B for LVDS data. Must be set on pre-965. */ 969/* Selects pipe B for LVDS data. Must be set on pre-965. */
970#define LVDS_PIPEB_SELECT (1 << 30) 970#define LVDS_PIPEB_SELECT (1 << 30)
971/* Enable border for unscaled (or aspect-scaled) display */
972#define LVDS_BORDER_ENABLE (1 << 15)
971/* 973/*
972 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per 974 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
973 * pixel. 975 * pixel.
@@ -1078,6 +1080,8 @@
1078#define BACKLIGHT_DUTY_CYCLE_SHIFT (0) 1080#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1079#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff) 1081#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1080 1082
1083#define BLC_HIST_CTL 0x61260
1084
1081/* TV port control */ 1085/* TV port control */
1082#define TV_CTL 0x68000 1086#define TV_CTL 0x68000
1083/** Enables the TV encoder */ 1087/** Enables the TV encoder */
@@ -1780,6 +1784,11 @@
1780#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 1784#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1781#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 1785#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1782#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0) 1786#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1787#define PIPE_BPC_MASK (7 << 5) /* Ironlake */
1788#define PIPE_8BPC (0 << 5)
1789#define PIPE_10BPC (1 << 5)
1790#define PIPE_6BPC (2 << 5)
1791#define PIPE_12BPC (3 << 5)
1783 1792
1784#define DSPARB 0x70030 1793#define DSPARB 0x70030
1785#define DSPARB_CSTART_MASK (0x7f << 7) 1794#define DSPARB_CSTART_MASK (0x7f << 7)
@@ -1790,17 +1799,29 @@
1790#define DSPARB_AEND_SHIFT 0 1799#define DSPARB_AEND_SHIFT 0
1791 1800
1792#define DSPFW1 0x70034 1801#define DSPFW1 0x70034
1802#define DSPFW_SR_SHIFT 23
1803#define DSPFW_CURSORB_SHIFT 16
1804#define DSPFW_PLANEB_SHIFT 8
1793#define DSPFW2 0x70038 1805#define DSPFW2 0x70038
1806#define DSPFW_CURSORA_MASK 0x00003f00
1807#define DSPFW_CURSORA_SHIFT 16
1794#define DSPFW3 0x7003c 1808#define DSPFW3 0x7003c
1809#define DSPFW_HPLL_SR_EN (1<<31)
1810#define DSPFW_CURSOR_SR_SHIFT 24
1795#define IGD_SELF_REFRESH_EN (1<<30) 1811#define IGD_SELF_REFRESH_EN (1<<30)
1796 1812
1797/* FIFO watermark sizes etc */ 1813/* FIFO watermark sizes etc */
1814#define G4X_FIFO_LINE_SIZE 64
1798#define I915_FIFO_LINE_SIZE 64 1815#define I915_FIFO_LINE_SIZE 64
1799#define I830_FIFO_LINE_SIZE 32 1816#define I830_FIFO_LINE_SIZE 32
1817
1818#define G4X_FIFO_SIZE 127
1800#define I945_FIFO_SIZE 127 /* 945 & 965 */ 1819#define I945_FIFO_SIZE 127 /* 945 & 965 */
1801#define I915_FIFO_SIZE 95 1820#define I915_FIFO_SIZE 95
1802#define I855GM_FIFO_SIZE 127 /* In cachelines */ 1821#define I855GM_FIFO_SIZE 127 /* In cachelines */
1803#define I830_FIFO_SIZE 95 1822#define I830_FIFO_SIZE 95
1823
1824#define G4X_MAX_WM 0x3f
1804#define I915_MAX_WM 0x3f 1825#define I915_MAX_WM 0x3f
1805 1826
1806#define IGD_DISPLAY_FIFO 512 /* in 64byte unit */ 1827#define IGD_DISPLAY_FIFO 512 /* in 64byte unit */
@@ -2030,6 +2051,11 @@
2030#define PFA_CTL_1 0x68080 2051#define PFA_CTL_1 0x68080
2031#define PFB_CTL_1 0x68880 2052#define PFB_CTL_1 0x68880
2032#define PF_ENABLE (1<<31) 2053#define PF_ENABLE (1<<31)
2054#define PF_FILTER_MASK (3<<23)
2055#define PF_FILTER_PROGRAMMED (0<<23)
2056#define PF_FILTER_MED_3x3 (1<<23)
2057#define PF_FILTER_EDGE_ENHANCE (2<<23)
2058#define PF_FILTER_EDGE_SOFTEN (3<<23)
2033#define PFA_WIN_SZ 0x68074 2059#define PFA_WIN_SZ 0x68074
2034#define PFB_WIN_SZ 0x68874 2060#define PFB_WIN_SZ 0x68874
2035#define PFA_WIN_POS 0x68070 2061#define PFA_WIN_POS 0x68070
@@ -2149,11 +2175,11 @@
2149#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13) 2175#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2150#define DREF_SSC_SOURCE_DISABLE (0<<11) 2176#define DREF_SSC_SOURCE_DISABLE (0<<11)
2151#define DREF_SSC_SOURCE_ENABLE (2<<11) 2177#define DREF_SSC_SOURCE_ENABLE (2<<11)
2152#define DREF_SSC_SOURCE_MASK (2<<11) 2178#define DREF_SSC_SOURCE_MASK (3<<11)
2153#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9) 2179#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2154#define DREF_NONSPREAD_CK505_ENABLE (1<<9) 2180#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2155#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9) 2181#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2156#define DREF_NONSPREAD_SOURCE_MASK (2<<9) 2182#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2157#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7) 2183#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2158#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7) 2184#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2159#define DREF_SSC4_DOWNSPREAD (0<<6) 2185#define DREF_SSC4_DOWNSPREAD (0<<6)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index bd6d8d91ca9..6eec8171a44 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -32,11 +32,15 @@
32static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) 32static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
33{ 33{
34 struct drm_i915_private *dev_priv = dev->dev_private; 34 struct drm_i915_private *dev_priv = dev->dev_private;
35 u32 dpll_reg;
35 36
36 if (pipe == PIPE_A) 37 if (IS_IGDNG(dev)) {
37 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE); 38 dpll_reg = (pipe == PIPE_A) ? PCH_DPLL_A: PCH_DPLL_B;
38 else 39 } else {
39 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE); 40 dpll_reg = (pipe == PIPE_A) ? DPLL_A: DPLL_B;
41 }
42
43 return (I915_READ(dpll_reg) & DPLL_VCO_ENABLE);
40} 44}
41 45
42static void i915_save_palette(struct drm_device *dev, enum pipe pipe) 46static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
@@ -49,6 +53,9 @@ static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
49 if (!i915_pipe_enabled(dev, pipe)) 53 if (!i915_pipe_enabled(dev, pipe))
50 return; 54 return;
51 55
56 if (IS_IGDNG(dev))
57 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
58
52 if (pipe == PIPE_A) 59 if (pipe == PIPE_A)
53 array = dev_priv->save_palette_a; 60 array = dev_priv->save_palette_a;
54 else 61 else
@@ -68,6 +75,9 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
68 if (!i915_pipe_enabled(dev, pipe)) 75 if (!i915_pipe_enabled(dev, pipe))
69 return; 76 return;
70 77
78 if (IS_IGDNG(dev))
79 reg = (pipe == PIPE_A) ? LGC_PALETTE_A : LGC_PALETTE_B;
80
71 if (pipe == PIPE_A) 81 if (pipe == PIPE_A)
72 array = dev_priv->save_palette_a; 82 array = dev_priv->save_palette_a;
73 else 83 else
@@ -229,13 +239,24 @@ static void i915_save_modeset_reg(struct drm_device *dev)
229 if (drm_core_check_feature(dev, DRIVER_MODESET)) 239 if (drm_core_check_feature(dev, DRIVER_MODESET))
230 return; 240 return;
231 241
242 if (IS_IGDNG(dev)) {
243 dev_priv->savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL);
244 dev_priv->saveDISP_ARB_CTL = I915_READ(DISP_ARB_CTL);
245 }
246
232 /* Pipe & plane A info */ 247 /* Pipe & plane A info */
233 dev_priv->savePIPEACONF = I915_READ(PIPEACONF); 248 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
234 dev_priv->savePIPEASRC = I915_READ(PIPEASRC); 249 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
235 dev_priv->saveFPA0 = I915_READ(FPA0); 250 if (IS_IGDNG(dev)) {
236 dev_priv->saveFPA1 = I915_READ(FPA1); 251 dev_priv->saveFPA0 = I915_READ(PCH_FPA0);
237 dev_priv->saveDPLL_A = I915_READ(DPLL_A); 252 dev_priv->saveFPA1 = I915_READ(PCH_FPA1);
238 if (IS_I965G(dev)) 253 dev_priv->saveDPLL_A = I915_READ(PCH_DPLL_A);
254 } else {
255 dev_priv->saveFPA0 = I915_READ(FPA0);
256 dev_priv->saveFPA1 = I915_READ(FPA1);
257 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
258 }
259 if (IS_I965G(dev) && !IS_IGDNG(dev))
239 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD); 260 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
240 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A); 261 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
241 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A); 262 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
@@ -243,7 +264,30 @@ static void i915_save_modeset_reg(struct drm_device *dev)
243 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A); 264 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
244 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A); 265 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
245 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A); 266 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
246 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 267 if (!IS_IGDNG(dev))
268 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
269
270 if (IS_IGDNG(dev)) {
271 dev_priv->savePIPEA_DATA_M1 = I915_READ(PIPEA_DATA_M1);
272 dev_priv->savePIPEA_DATA_N1 = I915_READ(PIPEA_DATA_N1);
273 dev_priv->savePIPEA_LINK_M1 = I915_READ(PIPEA_LINK_M1);
274 dev_priv->savePIPEA_LINK_N1 = I915_READ(PIPEA_LINK_N1);
275
276 dev_priv->saveFDI_TXA_CTL = I915_READ(FDI_TXA_CTL);
277 dev_priv->saveFDI_RXA_CTL = I915_READ(FDI_RXA_CTL);
278
279 dev_priv->savePFA_CTL_1 = I915_READ(PFA_CTL_1);
280 dev_priv->savePFA_WIN_SZ = I915_READ(PFA_WIN_SZ);
281 dev_priv->savePFA_WIN_POS = I915_READ(PFA_WIN_POS);
282
283 dev_priv->saveTRANSACONF = I915_READ(TRANSACONF);
284 dev_priv->saveTRANS_HTOTAL_A = I915_READ(TRANS_HTOTAL_A);
285 dev_priv->saveTRANS_HBLANK_A = I915_READ(TRANS_HBLANK_A);
286 dev_priv->saveTRANS_HSYNC_A = I915_READ(TRANS_HSYNC_A);
287 dev_priv->saveTRANS_VTOTAL_A = I915_READ(TRANS_VTOTAL_A);
288 dev_priv->saveTRANS_VBLANK_A = I915_READ(TRANS_VBLANK_A);
289 dev_priv->saveTRANS_VSYNC_A = I915_READ(TRANS_VSYNC_A);
290 }
247 291
248 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR); 292 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
249 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); 293 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
@@ -260,10 +304,16 @@ static void i915_save_modeset_reg(struct drm_device *dev)
260 /* Pipe & plane B info */ 304 /* Pipe & plane B info */
261 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 305 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
262 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC); 306 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
263 dev_priv->saveFPB0 = I915_READ(FPB0); 307 if (IS_IGDNG(dev)) {
264 dev_priv->saveFPB1 = I915_READ(FPB1); 308 dev_priv->saveFPB0 = I915_READ(PCH_FPB0);
265 dev_priv->saveDPLL_B = I915_READ(DPLL_B); 309 dev_priv->saveFPB1 = I915_READ(PCH_FPB1);
266 if (IS_I965G(dev)) 310 dev_priv->saveDPLL_B = I915_READ(PCH_DPLL_B);
311 } else {
312 dev_priv->saveFPB0 = I915_READ(FPB0);
313 dev_priv->saveFPB1 = I915_READ(FPB1);
314 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
315 }
316 if (IS_I965G(dev) && !IS_IGDNG(dev))
267 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD); 317 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
268 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B); 318 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
269 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B); 319 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
@@ -271,7 +321,30 @@ static void i915_save_modeset_reg(struct drm_device *dev)
271 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B); 321 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
272 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B); 322 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
273 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B); 323 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
274 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A); 324 if (!IS_IGDNG(dev))
325 dev_priv->saveBCLRPAT_B = I915_READ(BCLRPAT_B);
326
327 if (IS_IGDNG(dev)) {
328 dev_priv->savePIPEB_DATA_M1 = I915_READ(PIPEB_DATA_M1);
329 dev_priv->savePIPEB_DATA_N1 = I915_READ(PIPEB_DATA_N1);
330 dev_priv->savePIPEB_LINK_M1 = I915_READ(PIPEB_LINK_M1);
331 dev_priv->savePIPEB_LINK_N1 = I915_READ(PIPEB_LINK_N1);
332
333 dev_priv->saveFDI_TXB_CTL = I915_READ(FDI_TXB_CTL);
334 dev_priv->saveFDI_RXB_CTL = I915_READ(FDI_RXB_CTL);
335
336 dev_priv->savePFB_CTL_1 = I915_READ(PFB_CTL_1);
337 dev_priv->savePFB_WIN_SZ = I915_READ(PFB_WIN_SZ);
338 dev_priv->savePFB_WIN_POS = I915_READ(PFB_WIN_POS);
339
340 dev_priv->saveTRANSBCONF = I915_READ(TRANSBCONF);
341 dev_priv->saveTRANS_HTOTAL_B = I915_READ(TRANS_HTOTAL_B);
342 dev_priv->saveTRANS_HBLANK_B = I915_READ(TRANS_HBLANK_B);
343 dev_priv->saveTRANS_HSYNC_B = I915_READ(TRANS_HSYNC_B);
344 dev_priv->saveTRANS_VTOTAL_B = I915_READ(TRANS_VTOTAL_B);
345 dev_priv->saveTRANS_VBLANK_B = I915_READ(TRANS_VBLANK_B);
346 dev_priv->saveTRANS_VSYNC_B = I915_READ(TRANS_VSYNC_B);
347 }
275 348
276 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR); 349 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
277 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); 350 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
@@ -290,23 +363,46 @@ static void i915_save_modeset_reg(struct drm_device *dev)
290static void i915_restore_modeset_reg(struct drm_device *dev) 363static void i915_restore_modeset_reg(struct drm_device *dev)
291{ 364{
292 struct drm_i915_private *dev_priv = dev->dev_private; 365 struct drm_i915_private *dev_priv = dev->dev_private;
366 int dpll_a_reg, fpa0_reg, fpa1_reg;
367 int dpll_b_reg, fpb0_reg, fpb1_reg;
293 368
294 if (drm_core_check_feature(dev, DRIVER_MODESET)) 369 if (drm_core_check_feature(dev, DRIVER_MODESET))
295 return; 370 return;
296 371
372 if (IS_IGDNG(dev)) {
373 dpll_a_reg = PCH_DPLL_A;
374 dpll_b_reg = PCH_DPLL_B;
375 fpa0_reg = PCH_FPA0;
376 fpb0_reg = PCH_FPB0;
377 fpa1_reg = PCH_FPA1;
378 fpb1_reg = PCH_FPB1;
379 } else {
380 dpll_a_reg = DPLL_A;
381 dpll_b_reg = DPLL_B;
382 fpa0_reg = FPA0;
383 fpb0_reg = FPB0;
384 fpa1_reg = FPA1;
385 fpb1_reg = FPB1;
386 }
387
388 if (IS_IGDNG(dev)) {
389 I915_WRITE(PCH_DREF_CONTROL, dev_priv->savePCH_DREF_CONTROL);
390 I915_WRITE(DISP_ARB_CTL, dev_priv->saveDISP_ARB_CTL);
391 }
392
297 /* Pipe & plane A info */ 393 /* Pipe & plane A info */
298 /* Prime the clock */ 394 /* Prime the clock */
299 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) { 395 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
300 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A & 396 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
301 ~DPLL_VCO_ENABLE); 397 ~DPLL_VCO_ENABLE);
302 DRM_UDELAY(150); 398 DRM_UDELAY(150);
303 } 399 }
304 I915_WRITE(FPA0, dev_priv->saveFPA0); 400 I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
305 I915_WRITE(FPA1, dev_priv->saveFPA1); 401 I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
306 /* Actually enable it */ 402 /* Actually enable it */
307 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A); 403 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
308 DRM_UDELAY(150); 404 DRM_UDELAY(150);
309 if (IS_I965G(dev)) 405 if (IS_I965G(dev) && !IS_IGDNG(dev))
310 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD); 406 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
311 DRM_UDELAY(150); 407 DRM_UDELAY(150);
312 408
@@ -317,7 +413,30 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
317 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A); 413 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
318 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A); 414 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
319 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A); 415 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
320 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A); 416 if (!IS_IGDNG(dev))
417 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
418
419 if (IS_IGDNG(dev)) {
420 I915_WRITE(PIPEA_DATA_M1, dev_priv->savePIPEA_DATA_M1);
421 I915_WRITE(PIPEA_DATA_N1, dev_priv->savePIPEA_DATA_N1);
422 I915_WRITE(PIPEA_LINK_M1, dev_priv->savePIPEA_LINK_M1);
423 I915_WRITE(PIPEA_LINK_N1, dev_priv->savePIPEA_LINK_N1);
424
425 I915_WRITE(FDI_RXA_CTL, dev_priv->saveFDI_RXA_CTL);
426 I915_WRITE(FDI_TXA_CTL, dev_priv->saveFDI_TXA_CTL);
427
428 I915_WRITE(PFA_CTL_1, dev_priv->savePFA_CTL_1);
429 I915_WRITE(PFA_WIN_SZ, dev_priv->savePFA_WIN_SZ);
430 I915_WRITE(PFA_WIN_POS, dev_priv->savePFA_WIN_POS);
431
432 I915_WRITE(TRANSACONF, dev_priv->saveTRANSACONF);
433 I915_WRITE(TRANS_HTOTAL_A, dev_priv->saveTRANS_HTOTAL_A);
434 I915_WRITE(TRANS_HBLANK_A, dev_priv->saveTRANS_HBLANK_A);
435 I915_WRITE(TRANS_HSYNC_A, dev_priv->saveTRANS_HSYNC_A);
436 I915_WRITE(TRANS_VTOTAL_A, dev_priv->saveTRANS_VTOTAL_A);
437 I915_WRITE(TRANS_VBLANK_A, dev_priv->saveTRANS_VBLANK_A);
438 I915_WRITE(TRANS_VSYNC_A, dev_priv->saveTRANS_VSYNC_A);
439 }
321 440
322 /* Restore plane info */ 441 /* Restore plane info */
323 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); 442 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
@@ -339,16 +458,16 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
339 458
340 /* Pipe & plane B info */ 459 /* Pipe & plane B info */
341 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 460 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
342 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B & 461 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
343 ~DPLL_VCO_ENABLE); 462 ~DPLL_VCO_ENABLE);
344 DRM_UDELAY(150); 463 DRM_UDELAY(150);
345 } 464 }
346 I915_WRITE(FPB0, dev_priv->saveFPB0); 465 I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
347 I915_WRITE(FPB1, dev_priv->saveFPB1); 466 I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
348 /* Actually enable it */ 467 /* Actually enable it */
349 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B); 468 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
350 DRM_UDELAY(150); 469 DRM_UDELAY(150);
351 if (IS_I965G(dev)) 470 if (IS_I965G(dev) && !IS_IGDNG(dev))
352 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD); 471 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
353 DRM_UDELAY(150); 472 DRM_UDELAY(150);
354 473
@@ -359,7 +478,30 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
359 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B); 478 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
360 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B); 479 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
361 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B); 480 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
362 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B); 481 if (!IS_IGDNG(dev))
482 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
483
484 if (IS_IGDNG(dev)) {
485 I915_WRITE(PIPEB_DATA_M1, dev_priv->savePIPEB_DATA_M1);
486 I915_WRITE(PIPEB_DATA_N1, dev_priv->savePIPEB_DATA_N1);
487 I915_WRITE(PIPEB_LINK_M1, dev_priv->savePIPEB_LINK_M1);
488 I915_WRITE(PIPEB_LINK_N1, dev_priv->savePIPEB_LINK_N1);
489
490 I915_WRITE(FDI_RXB_CTL, dev_priv->saveFDI_RXB_CTL);
491 I915_WRITE(FDI_TXB_CTL, dev_priv->saveFDI_TXB_CTL);
492
493 I915_WRITE(PFB_CTL_1, dev_priv->savePFB_CTL_1);
494 I915_WRITE(PFB_WIN_SZ, dev_priv->savePFB_WIN_SZ);
495 I915_WRITE(PFB_WIN_POS, dev_priv->savePFB_WIN_POS);
496
497 I915_WRITE(TRANSBCONF, dev_priv->saveTRANSBCONF);
498 I915_WRITE(TRANS_HTOTAL_B, dev_priv->saveTRANS_HTOTAL_B);
499 I915_WRITE(TRANS_HBLANK_B, dev_priv->saveTRANS_HBLANK_B);
500 I915_WRITE(TRANS_HSYNC_B, dev_priv->saveTRANS_HSYNC_B);
501 I915_WRITE(TRANS_VTOTAL_B, dev_priv->saveTRANS_VTOTAL_B);
502 I915_WRITE(TRANS_VBLANK_B, dev_priv->saveTRANS_VBLANK_B);
503 I915_WRITE(TRANS_VSYNC_B, dev_priv->saveTRANS_VSYNC_B);
504 }
363 505
364 /* Restore plane info */ 506 /* Restore plane info */
365 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); 507 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
@@ -404,21 +546,43 @@ void i915_save_display(struct drm_device *dev)
404 dev_priv->saveCURSIZE = I915_READ(CURSIZE); 546 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
405 547
406 /* CRT state */ 548 /* CRT state */
407 dev_priv->saveADPA = I915_READ(ADPA); 549 if (IS_IGDNG(dev)) {
550 dev_priv->saveADPA = I915_READ(PCH_ADPA);
551 } else {
552 dev_priv->saveADPA = I915_READ(ADPA);
553 }
408 554
409 /* LVDS state */ 555 /* LVDS state */
410 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL); 556 if (IS_IGDNG(dev)) {
411 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); 557 dev_priv->savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
412 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); 558 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
413 if (IS_I965G(dev)) 559 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
414 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); 560 dev_priv->saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
415 if (IS_MOBILE(dev) && !IS_I830(dev)) 561 dev_priv->saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
416 dev_priv->saveLVDS = I915_READ(LVDS); 562 dev_priv->saveLVDS = I915_READ(PCH_LVDS);
417 if (!IS_I830(dev) && !IS_845G(dev)) 563 } else {
564 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
565 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
566 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
567 dev_priv->saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
568 if (IS_I965G(dev))
569 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
570 if (IS_MOBILE(dev) && !IS_I830(dev))
571 dev_priv->saveLVDS = I915_READ(LVDS);
572 }
573
574 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev))
418 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 575 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
419 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); 576
420 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); 577 if (IS_IGDNG(dev)) {
421 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR); 578 dev_priv->savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
579 dev_priv->savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
580 dev_priv->savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
581 } else {
582 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
583 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
584 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
585 }
422 586
423 /* Display Port state */ 587 /* Display Port state */
424 if (SUPPORTS_INTEGRATED_DP(dev)) { 588 if (SUPPORTS_INTEGRATED_DP(dev)) {
@@ -437,16 +601,23 @@ void i915_save_display(struct drm_device *dev)
437 /* FIXME: save TV & SDVO state */ 601 /* FIXME: save TV & SDVO state */
438 602
439 /* FBC state */ 603 /* FBC state */
440 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE); 604 if (IS_GM45(dev)) {
441 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE); 605 dev_priv->saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
442 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2); 606 } else {
443 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); 607 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
608 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
609 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
610 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
611 }
444 612
445 /* VGA state */ 613 /* VGA state */
446 dev_priv->saveVGA0 = I915_READ(VGA0); 614 dev_priv->saveVGA0 = I915_READ(VGA0);
447 dev_priv->saveVGA1 = I915_READ(VGA1); 615 dev_priv->saveVGA1 = I915_READ(VGA1);
448 dev_priv->saveVGA_PD = I915_READ(VGA_PD); 616 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
449 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 617 if (IS_IGDNG(dev))
618 dev_priv->saveVGACNTRL = I915_READ(CPU_VGACNTRL);
619 else
620 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
450 621
451 i915_save_vga(dev); 622 i915_save_vga(dev);
452} 623}
@@ -485,22 +656,41 @@ void i915_restore_display(struct drm_device *dev)
485 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE); 656 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
486 657
487 /* CRT state */ 658 /* CRT state */
488 I915_WRITE(ADPA, dev_priv->saveADPA); 659 if (IS_IGDNG(dev))
660 I915_WRITE(PCH_ADPA, dev_priv->saveADPA);
661 else
662 I915_WRITE(ADPA, dev_priv->saveADPA);
489 663
490 /* LVDS state */ 664 /* LVDS state */
491 if (IS_I965G(dev)) 665 if (IS_I965G(dev) && !IS_IGDNG(dev))
492 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2); 666 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
493 if (IS_MOBILE(dev) && !IS_I830(dev)) 667
668 if (IS_IGDNG(dev)) {
669 I915_WRITE(PCH_LVDS, dev_priv->saveLVDS);
670 } else if (IS_MOBILE(dev) && !IS_I830(dev))
494 I915_WRITE(LVDS, dev_priv->saveLVDS); 671 I915_WRITE(LVDS, dev_priv->saveLVDS);
495 if (!IS_I830(dev) && !IS_845G(dev)) 672
673 if (!IS_I830(dev) && !IS_845G(dev) && !IS_IGDNG(dev))
496 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL); 674 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
497 675
498 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); 676 if (IS_IGDNG(dev)) {
499 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); 677 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->saveBLC_PWM_CTL);
500 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS); 678 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->saveBLC_PWM_CTL2);
501 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS); 679 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->saveBLC_CPU_PWM_CTL);
502 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR); 680 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->saveBLC_CPU_PWM_CTL2);
503 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); 681 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
682 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
683 I915_WRITE(PCH_PP_DIVISOR, dev_priv->savePP_DIVISOR);
684 I915_WRITE(PCH_PP_CONTROL, dev_priv->savePP_CONTROL);
685 } else {
686 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
687 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
688 I915_WRITE(BLC_HIST_CTL, dev_priv->saveBLC_HIST_CTL);
689 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
690 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
691 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
692 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
693 }
504 694
505 /* Display Port state */ 695 /* Display Port state */
506 if (SUPPORTS_INTEGRATED_DP(dev)) { 696 if (SUPPORTS_INTEGRATED_DP(dev)) {
@@ -511,13 +701,22 @@ void i915_restore_display(struct drm_device *dev)
511 /* FIXME: restore TV & SDVO state */ 701 /* FIXME: restore TV & SDVO state */
512 702
513 /* FBC info */ 703 /* FBC info */
514 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE); 704 if (IS_GM45(dev)) {
515 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE); 705 g4x_disable_fbc(dev);
516 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2); 706 I915_WRITE(DPFC_CB_BASE, dev_priv->saveDPFC_CB_BASE);
517 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL); 707 } else {
708 i8xx_disable_fbc(dev);
709 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
710 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
711 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
712 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
713 }
518 714
519 /* VGA state */ 715 /* VGA state */
520 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 716 if (IS_IGDNG(dev))
717 I915_WRITE(CPU_VGACNTRL, dev_priv->saveVGACNTRL);
718 else
719 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
521 I915_WRITE(VGA0, dev_priv->saveVGA0); 720 I915_WRITE(VGA0, dev_priv->saveVGA0);
522 I915_WRITE(VGA1, dev_priv->saveVGA1); 721 I915_WRITE(VGA1, dev_priv->saveVGA1);
523 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD); 722 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
@@ -543,8 +742,17 @@ int i915_save_state(struct drm_device *dev)
543 i915_save_display(dev); 742 i915_save_display(dev);
544 743
545 /* Interrupt state */ 744 /* Interrupt state */
546 dev_priv->saveIER = I915_READ(IER); 745 if (IS_IGDNG(dev)) {
547 dev_priv->saveIMR = I915_READ(IMR); 746 dev_priv->saveDEIER = I915_READ(DEIER);
747 dev_priv->saveDEIMR = I915_READ(DEIMR);
748 dev_priv->saveGTIER = I915_READ(GTIER);
749 dev_priv->saveGTIMR = I915_READ(GTIMR);
750 dev_priv->saveFDI_RXA_IMR = I915_READ(FDI_RXA_IMR);
751 dev_priv->saveFDI_RXB_IMR = I915_READ(FDI_RXB_IMR);
752 } else {
753 dev_priv->saveIER = I915_READ(IER);
754 dev_priv->saveIMR = I915_READ(IMR);
755 }
548 756
549 /* Clock gating state */ 757 /* Clock gating state */
550 dev_priv->saveD_STATE = I915_READ(D_STATE); 758 dev_priv->saveD_STATE = I915_READ(D_STATE);
@@ -609,8 +817,17 @@ int i915_restore_state(struct drm_device *dev)
609 i915_restore_display(dev); 817 i915_restore_display(dev);
610 818
611 /* Interrupt state */ 819 /* Interrupt state */
612 I915_WRITE (IER, dev_priv->saveIER); 820 if (IS_IGDNG(dev)) {
613 I915_WRITE (IMR, dev_priv->saveIMR); 821 I915_WRITE(DEIER, dev_priv->saveDEIER);
822 I915_WRITE(DEIMR, dev_priv->saveDEIMR);
823 I915_WRITE(GTIER, dev_priv->saveGTIER);
824 I915_WRITE(GTIMR, dev_priv->saveGTIMR);
825 I915_WRITE(FDI_RXA_IMR, dev_priv->saveFDI_RXA_IMR);
826 I915_WRITE(FDI_RXB_IMR, dev_priv->saveFDI_RXB_IMR);
827 } else {
828 I915_WRITE (IER, dev_priv->saveIER);
829 I915_WRITE (IMR, dev_priv->saveIMR);
830 }
614 831
615 /* Clock gating state */ 832 /* Clock gating state */
616 I915_WRITE (D_STATE, dev_priv->saveD_STATE); 833 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 4337414846b..96cd256e60e 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -351,20 +351,18 @@ parse_driver_features(struct drm_i915_private *dev_priv,
351 struct drm_device *dev = dev_priv->dev; 351 struct drm_device *dev = dev_priv->dev;
352 struct bdb_driver_features *driver; 352 struct bdb_driver_features *driver;
353 353
354 /* set default for chips without eDP */
355 if (!SUPPORTS_EDP(dev)) {
356 dev_priv->edp_support = 0;
357 return;
358 }
359
360 driver = find_section(bdb, BDB_DRIVER_FEATURES); 354 driver = find_section(bdb, BDB_DRIVER_FEATURES);
361 if (!driver) 355 if (!driver)
362 return; 356 return;
363 357
364 if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP) 358 if (driver && SUPPORTS_EDP(dev) &&
359 driver->lvds_config == BDB_DRIVER_FEATURE_EDP) {
365 dev_priv->edp_support = 1; 360 dev_priv->edp_support = 1;
361 } else {
362 dev_priv->edp_support = 0;
363 }
366 364
367 if (driver->dual_frequency) 365 if (driver && driver->dual_frequency)
368 dev_priv->render_reclock_avail = true; 366 dev_priv->render_reclock_avail = true;
369} 367}
370 368
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 212e22740fc..e5051446c48 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -262,8 +262,8 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
262 } while (time_after(timeout, jiffies)); 262 } while (time_after(timeout, jiffies));
263 } 263 }
264 264
265 if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) == 265 if ((I915_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
266 CRT_HOTPLUG_MONITOR_COLOR) 266 CRT_HOTPLUG_MONITOR_NONE)
267 return true; 267 return true;
268 268
269 return false; 269 return false;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3c14240cc00..099f420de57 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -863,10 +863,8 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
863 struct drm_device *dev = crtc->dev; 863 struct drm_device *dev = crtc->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private; 864 struct drm_i915_private *dev_priv = dev->dev_private;
865 intel_clock_t clock; 865 intel_clock_t clock;
866 int max_n;
867 bool found;
868 int err_most = 47; 866 int err_most = 47;
869 found = false; 867 int err_min = 10000;
870 868
871 /* eDP has only 2 clock choice, no n/m/p setting */ 869 /* eDP has only 2 clock choice, no n/m/p setting */
872 if (HAS_eDP) 870 if (HAS_eDP)
@@ -890,10 +888,9 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
890 } 888 }
891 889
892 memset(best_clock, 0, sizeof(*best_clock)); 890 memset(best_clock, 0, sizeof(*best_clock));
893 max_n = limit->n.max;
894 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 891 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
895 /* based on hardware requriment prefer smaller n to precision */ 892 /* based on hardware requriment prefer smaller n to precision */
896 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 893 for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
897 /* based on hardware requirment prefere larger m1,m2 */ 894 /* based on hardware requirment prefere larger m1,m2 */
898 for (clock.m1 = limit->m1.max; 895 for (clock.m1 = limit->m1.max;
899 clock.m1 >= limit->m1.min; clock.m1--) { 896 clock.m1 >= limit->m1.min; clock.m1--) {
@@ -907,18 +904,18 @@ intel_igdng_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
907 this_err = abs((10000 - (target*10000/clock.dot))); 904 this_err = abs((10000 - (target*10000/clock.dot)));
908 if (this_err < err_most) { 905 if (this_err < err_most) {
909 *best_clock = clock; 906 *best_clock = clock;
910 err_most = this_err;
911 max_n = clock.n;
912 found = true;
913 /* found on first matching */ 907 /* found on first matching */
914 goto out; 908 goto out;
909 } else if (this_err < err_min) {
910 *best_clock = clock;
911 err_min = this_err;
915 } 912 }
916 } 913 }
917 } 914 }
918 } 915 }
919 } 916 }
920out: 917out:
921 return found; 918 return true;
922} 919}
923 920
924/* DisplayPort has only two frequencies, 162MHz and 270MHz */ 921/* DisplayPort has only two frequencies, 162MHz and 270MHz */
@@ -943,6 +940,7 @@ intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
943 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2); 940 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
944 clock.p = (clock.p1 * clock.p2); 941 clock.p = (clock.p1 * clock.p2);
945 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p; 942 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
943 clock.vco = 0;
946 memcpy(best_clock, &clock, sizeof(intel_clock_t)); 944 memcpy(best_clock, &clock, sizeof(intel_clock_t));
947 return true; 945 return true;
948} 946}
@@ -1260,9 +1258,11 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1260 return ret; 1258 return ret;
1261 } 1259 }
1262 1260
1263 /* Pre-i965 needs to install a fence for tiled scan-out */ 1261 /* Install a fence for tiled scan-out. Pre-i965 always needs a fence,
1264 if (!IS_I965G(dev) && 1262 * whereas 965+ only requires a fence if using framebuffer compression.
1265 obj_priv->fence_reg == I915_FENCE_REG_NONE && 1263 * For simplicity, we always install a fence as the cost is not that onerous.
1264 */
1265 if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1266 obj_priv->tiling_mode != I915_TILING_NONE) { 1266 obj_priv->tiling_mode != I915_TILING_NONE) {
1267 ret = i915_gem_object_get_fence_reg(obj); 1267 ret = i915_gem_object_get_fence_reg(obj);
1268 if (ret != 0) { 1268 if (ret != 0) {
@@ -1513,7 +1513,7 @@ static void igdng_crtc_dpms(struct drm_crtc *crtc, int mode)
1513 /* Enable panel fitting for LVDS */ 1513 /* Enable panel fitting for LVDS */
1514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { 1514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1515 temp = I915_READ(pf_ctl_reg); 1515 temp = I915_READ(pf_ctl_reg);
1516 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE); 1516 I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1517 1517
1518 /* currently full aspect */ 1518 /* currently full aspect */
1519 I915_WRITE(pf_win_pos, 0); 1519 I915_WRITE(pf_win_pos, 0);
@@ -1801,6 +1801,8 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1801 case DRM_MODE_DPMS_ON: 1801 case DRM_MODE_DPMS_ON:
1802 case DRM_MODE_DPMS_STANDBY: 1802 case DRM_MODE_DPMS_STANDBY:
1803 case DRM_MODE_DPMS_SUSPEND: 1803 case DRM_MODE_DPMS_SUSPEND:
1804 intel_update_watermarks(dev);
1805
1804 /* Enable the DPLL */ 1806 /* Enable the DPLL */
1805 temp = I915_READ(dpll_reg); 1807 temp = I915_READ(dpll_reg);
1806 if ((temp & DPLL_VCO_ENABLE) == 0) { 1808 if ((temp & DPLL_VCO_ENABLE) == 0) {
@@ -1838,7 +1840,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1838 1840
1839 /* Give the overlay scaler a chance to enable if it's on this pipe */ 1841 /* Give the overlay scaler a chance to enable if it's on this pipe */
1840 //intel_crtc_dpms_video(crtc, true); TODO 1842 //intel_crtc_dpms_video(crtc, true); TODO
1841 intel_update_watermarks(dev);
1842 break; 1843 break;
1843 case DRM_MODE_DPMS_OFF: 1844 case DRM_MODE_DPMS_OFF:
1844 intel_update_watermarks(dev); 1845 intel_update_watermarks(dev);
@@ -2082,7 +2083,7 @@ fdi_reduce_ratio(u32 *num, u32 *den)
2082#define LINK_N 0x80000 2083#define LINK_N 0x80000
2083 2084
2084static void 2085static void
2085igdng_compute_m_n(int bytes_per_pixel, int nlanes, 2086igdng_compute_m_n(int bits_per_pixel, int nlanes,
2086 int pixel_clock, int link_clock, 2087 int pixel_clock, int link_clock,
2087 struct fdi_m_n *m_n) 2088 struct fdi_m_n *m_n)
2088{ 2089{
@@ -2092,7 +2093,8 @@ igdng_compute_m_n(int bytes_per_pixel, int nlanes,
2092 2093
2093 temp = (u64) DATA_N * pixel_clock; 2094 temp = (u64) DATA_N * pixel_clock;
2094 temp = div_u64(temp, link_clock); 2095 temp = div_u64(temp, link_clock);
2095 m_n->gmch_m = div_u64(temp * bytes_per_pixel, nlanes); 2096 m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2097 m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2096 m_n->gmch_n = DATA_N; 2098 m_n->gmch_n = DATA_N;
2097 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); 2099 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2098 2100
@@ -2140,6 +2142,13 @@ static struct intel_watermark_params igd_cursor_hplloff_wm = {
2140 IGD_CURSOR_GUARD_WM, 2142 IGD_CURSOR_GUARD_WM,
2141 IGD_FIFO_LINE_SIZE 2143 IGD_FIFO_LINE_SIZE
2142}; 2144};
2145static struct intel_watermark_params g4x_wm_info = {
2146 G4X_FIFO_SIZE,
2147 G4X_MAX_WM,
2148 G4X_MAX_WM,
2149 2,
2150 G4X_FIFO_LINE_SIZE,
2151};
2143static struct intel_watermark_params i945_wm_info = { 2152static struct intel_watermark_params i945_wm_info = {
2144 I945_FIFO_SIZE, 2153 I945_FIFO_SIZE,
2145 I915_MAX_WM, 2154 I915_MAX_WM,
@@ -2430,17 +2439,74 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
2430 return size; 2439 return size;
2431} 2440}
2432 2441
2433static void g4x_update_wm(struct drm_device *dev, int unused, int unused2, 2442static void g4x_update_wm(struct drm_device *dev, int planea_clock,
2434 int unused3, int unused4) 2443 int planeb_clock, int sr_hdisplay, int pixel_size)
2435{ 2444{
2436 struct drm_i915_private *dev_priv = dev->dev_private; 2445 struct drm_i915_private *dev_priv = dev->dev_private;
2437 u32 fw_blc_self = I915_READ(FW_BLC_SELF); 2446 int total_size, cacheline_size;
2447 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2448 struct intel_watermark_params planea_params, planeb_params;
2449 unsigned long line_time_us;
2450 int sr_clock, sr_entries = 0, entries_required;
2438 2451
2439 if (i915_powersave) 2452 /* Create copies of the base settings for each pipe */
2440 fw_blc_self |= FW_BLC_SELF_EN; 2453 planea_params = planeb_params = g4x_wm_info;
2441 else 2454
2442 fw_blc_self &= ~FW_BLC_SELF_EN; 2455 /* Grab a couple of global values before we overwrite them */
2443 I915_WRITE(FW_BLC_SELF, fw_blc_self); 2456 total_size = planea_params.fifo_size;
2457 cacheline_size = planea_params.cacheline_size;
2458
2459 /*
2460 * Note: we need to make sure we don't overflow for various clock &
2461 * latency values.
2462 * clocks go from a few thousand to several hundred thousand.
2463 * latency is usually a few thousand
2464 */
2465 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2466 1000;
2467 entries_required /= G4X_FIFO_LINE_SIZE;
2468 planea_wm = entries_required + planea_params.guard_size;
2469
2470 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2471 1000;
2472 entries_required /= G4X_FIFO_LINE_SIZE;
2473 planeb_wm = entries_required + planeb_params.guard_size;
2474
2475 cursora_wm = cursorb_wm = 16;
2476 cursor_sr = 32;
2477
2478 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2479
2480 /* Calc sr entries for one plane configs */
2481 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2482 /* self-refresh has much higher latency */
2483 const static int sr_latency_ns = 12000;
2484
2485 sr_clock = planea_clock ? planea_clock : planeb_clock;
2486 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2487
2488 /* Use ns/us then divide to preserve precision */
2489 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2490 pixel_size * sr_hdisplay) / 1000;
2491 sr_entries = roundup(sr_entries / cacheline_size, 1);
2492 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2493 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2494 }
2495
2496 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2497 planea_wm, planeb_wm, sr_entries);
2498
2499 planea_wm &= 0x3f;
2500 planeb_wm &= 0x3f;
2501
2502 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2503 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2504 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2505 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2506 (cursora_wm << DSPFW_CURSORA_SHIFT));
2507 /* HPLL off in SR has some issues on G4x... disable it */
2508 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2509 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2444} 2510}
2445 2511
2446static void i965_update_wm(struct drm_device *dev, int unused, int unused2, 2512static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
@@ -2586,6 +2652,9 @@ static void intel_update_watermarks(struct drm_device *dev)
2586 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0; 2652 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2587 int enabled = 0, pixel_size = 0; 2653 int enabled = 0, pixel_size = 0;
2588 2654
2655 if (!dev_priv->display.update_wm)
2656 return;
2657
2589 /* Get the clock config from both planes */ 2658 /* Get the clock config from both planes */
2590 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 2659 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2591 intel_crtc = to_intel_crtc(crtc); 2660 intel_crtc = to_intel_crtc(crtc);
@@ -2763,7 +2832,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2763 2832
2764 /* FDI link */ 2833 /* FDI link */
2765 if (IS_IGDNG(dev)) { 2834 if (IS_IGDNG(dev)) {
2766 int lane, link_bw; 2835 int lane, link_bw, bpp;
2767 /* eDP doesn't require FDI link, so just set DP M/N 2836 /* eDP doesn't require FDI link, so just set DP M/N
2768 according to current link config */ 2837 according to current link config */
2769 if (is_edp) { 2838 if (is_edp) {
@@ -2782,10 +2851,72 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2782 lane = 4; 2851 lane = 4;
2783 link_bw = 270000; 2852 link_bw = 270000;
2784 } 2853 }
2785 igdng_compute_m_n(3, lane, target_clock, 2854
2855 /* determine panel color depth */
2856 temp = I915_READ(pipeconf_reg);
2857
2858 switch (temp & PIPE_BPC_MASK) {
2859 case PIPE_8BPC:
2860 bpp = 24;
2861 break;
2862 case PIPE_10BPC:
2863 bpp = 30;
2864 break;
2865 case PIPE_6BPC:
2866 bpp = 18;
2867 break;
2868 case PIPE_12BPC:
2869 bpp = 36;
2870 break;
2871 default:
2872 DRM_ERROR("unknown pipe bpc value\n");
2873 bpp = 24;
2874 }
2875
2876 igdng_compute_m_n(bpp, lane, target_clock,
2786 link_bw, &m_n); 2877 link_bw, &m_n);
2787 } 2878 }
2788 2879
2880 /* Ironlake: try to setup display ref clock before DPLL
2881 * enabling. This is only under driver's control after
2882 * PCH B stepping, previous chipset stepping should be
2883 * ignoring this setting.
2884 */
2885 if (IS_IGDNG(dev)) {
2886 temp = I915_READ(PCH_DREF_CONTROL);
2887 /* Always enable nonspread source */
2888 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
2889 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
2890 I915_WRITE(PCH_DREF_CONTROL, temp);
2891 POSTING_READ(PCH_DREF_CONTROL);
2892
2893 temp &= ~DREF_SSC_SOURCE_MASK;
2894 temp |= DREF_SSC_SOURCE_ENABLE;
2895 I915_WRITE(PCH_DREF_CONTROL, temp);
2896 POSTING_READ(PCH_DREF_CONTROL);
2897
2898 udelay(200);
2899
2900 if (is_edp) {
2901 if (dev_priv->lvds_use_ssc) {
2902 temp |= DREF_SSC1_ENABLE;
2903 I915_WRITE(PCH_DREF_CONTROL, temp);
2904 POSTING_READ(PCH_DREF_CONTROL);
2905
2906 udelay(200);
2907
2908 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
2909 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
2910 I915_WRITE(PCH_DREF_CONTROL, temp);
2911 POSTING_READ(PCH_DREF_CONTROL);
2912 } else {
2913 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
2914 I915_WRITE(PCH_DREF_CONTROL, temp);
2915 POSTING_READ(PCH_DREF_CONTROL);
2916 }
2917 }
2918 }
2919
2789 if (IS_IGD(dev)) { 2920 if (IS_IGD(dev)) {
2790 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2; 2921 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
2791 if (has_reduced_clock) 2922 if (has_reduced_clock)
@@ -2936,6 +3067,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
2936 3067
2937 lvds = I915_READ(lvds_reg); 3068 lvds = I915_READ(lvds_reg);
2938 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT; 3069 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3070 /* set the corresponsding LVDS_BORDER bit */
3071 lvds |= dev_priv->lvds_border_bits;
2939 /* Set the B0-B3 data pairs corresponding to whether we're going to 3072 /* Set the B0-B3 data pairs corresponding to whether we're going to
2940 * set the DPLLs for dual-channel mode or not. 3073 * set the DPLLs for dual-channel mode or not.
2941 */ 3074 */
@@ -4124,7 +4257,9 @@ void intel_init_clock_gating(struct drm_device *dev)
4124 * Disable clock gating reported to work incorrectly according to the 4257 * Disable clock gating reported to work incorrectly according to the
4125 * specs, but enable as much else as we can. 4258 * specs, but enable as much else as we can.
4126 */ 4259 */
4127 if (IS_G4X(dev)) { 4260 if (IS_IGDNG(dev)) {
4261 return;
4262 } else if (IS_G4X(dev)) {
4128 uint32_t dspclk_gate; 4263 uint32_t dspclk_gate;
4129 I915_WRITE(RENCLK_GATE_D1, 0); 4264 I915_WRITE(RENCLK_GATE_D1, 0);
4130 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | 4265 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
@@ -4212,7 +4347,9 @@ static void intel_init_display(struct drm_device *dev)
4212 i830_get_display_clock_speed; 4347 i830_get_display_clock_speed;
4213 4348
4214 /* For FIFO watermark updates */ 4349 /* For FIFO watermark updates */
4215 if (IS_G4X(dev)) 4350 if (IS_IGDNG(dev))
4351 dev_priv->display.update_wm = NULL;
4352 else if (IS_G4X(dev))
4216 dev_priv->display.update_wm = g4x_update_wm; 4353 dev_priv->display.update_wm = g4x_update_wm;
4217 else if (IS_I965G(dev)) 4354 else if (IS_I965G(dev))
4218 dev_priv->display.update_wm = i965_update_wm; 4355 dev_priv->display.update_wm = i965_update_wm;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f4856a51047..d83447557f9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -400,7 +400,7 @@ intel_dp_i2c_init(struct intel_output *intel_output, const char *name)
400{ 400{
401 struct intel_dp_priv *dp_priv = intel_output->dev_priv; 401 struct intel_dp_priv *dp_priv = intel_output->dev_priv;
402 402
403 DRM_ERROR("i2c_init %s\n", name); 403 DRM_DEBUG_KMS("i2c_init %s\n", name);
404 dp_priv->algo.running = false; 404 dp_priv->algo.running = false;
405 dp_priv->algo.address = 0; 405 dp_priv->algo.address = 0;
406 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch; 406 dp_priv->algo.aux_ch = intel_dp_i2c_aux_ch;
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 663ab6de0b5..c33451aec1b 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -77,14 +77,32 @@ static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
77 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv; 77 struct intel_hdmi_priv *hdmi_priv = intel_output->dev_priv;
78 u32 temp; 78 u32 temp;
79 79
80 if (mode != DRM_MODE_DPMS_ON) { 80 temp = I915_READ(hdmi_priv->sdvox_reg);
81 temp = I915_READ(hdmi_priv->sdvox_reg); 81
82 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
83 * we do this anyway which shows more stable in testing.
84 */
85 if (IS_IGDNG(dev)) {
82 I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE); 86 I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE);
87 POSTING_READ(hdmi_priv->sdvox_reg);
88 }
89
90 if (mode != DRM_MODE_DPMS_ON) {
91 temp &= ~SDVO_ENABLE;
83 } else { 92 } else {
84 temp = I915_READ(hdmi_priv->sdvox_reg); 93 temp |= SDVO_ENABLE;
85 I915_WRITE(hdmi_priv->sdvox_reg, temp | SDVO_ENABLE);
86 } 94 }
95
96 I915_WRITE(hdmi_priv->sdvox_reg, temp);
87 POSTING_READ(hdmi_priv->sdvox_reg); 97 POSTING_READ(hdmi_priv->sdvox_reg);
98
99 /* HW workaround, need to write this twice for issue that may result
100 * in first write getting masked.
101 */
102 if (IS_IGDNG(dev)) {
103 I915_WRITE(hdmi_priv->sdvox_reg, temp);
104 POSTING_READ(hdmi_priv->sdvox_reg);
105 }
88} 106}
89 107
90static void intel_hdmi_save(struct drm_connector *connector) 108static void intel_hdmi_save(struct drm_connector *connector)
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 98ae3d73577..05598ae10c4 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -380,7 +380,7 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
380 adjusted_mode->crtc_vblank_start + vsync_pos; 380 adjusted_mode->crtc_vblank_start + vsync_pos;
381 /* keep the vsync width constant */ 381 /* keep the vsync width constant */
382 adjusted_mode->crtc_vsync_end = 382 adjusted_mode->crtc_vsync_end =
383 adjusted_mode->crtc_vblank_start + vsync_width; 383 adjusted_mode->crtc_vsync_start + vsync_width;
384 border = 1; 384 border = 1;
385 break; 385 break;
386 case DRM_MODE_SCALE_ASPECT: 386 case DRM_MODE_SCALE_ASPECT:
@@ -526,6 +526,14 @@ out:
526 lvds_priv->pfit_control = pfit_control; 526 lvds_priv->pfit_control = pfit_control;
527 lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios; 527 lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios;
528 /* 528 /*
529 * When there exists the border, it means that the LVDS_BORDR
530 * should be enabled.
531 */
532 if (border)
533 dev_priv->lvds_border_bits |= LVDS_BORDER_ENABLE;
534 else
535 dev_priv->lvds_border_bits &= ~(LVDS_BORDER_ENABLE);
536 /*
529 * XXX: It would be nice to support lower refresh rates on the 537 * XXX: It would be nice to support lower refresh rates on the
530 * panels to reduce power consumption, and perhaps match the 538 * panels to reduce power consumption, and perhaps match the
531 * user's requested refresh rate. 539 * user's requested refresh rate.
@@ -656,6 +664,15 @@ static int intel_lvds_get_modes(struct drm_connector *connector)
656 return 0; 664 return 0;
657} 665}
658 666
667/*
668 * Lid events. Note the use of 'modeset_on_lid':
669 * - we set it on lid close, and reset it on open
670 * - we use it as a "only once" bit (ie we ignore
671 * duplicate events where it was already properly
672 * set/reset)
673 * - the suspend/resume paths will also set it to
674 * zero, since they restore the mode ("lid open").
675 */
659static int intel_lid_notify(struct notifier_block *nb, unsigned long val, 676static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
660 void *unused) 677 void *unused)
661{ 678{
@@ -663,13 +680,19 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
663 container_of(nb, struct drm_i915_private, lid_notifier); 680 container_of(nb, struct drm_i915_private, lid_notifier);
664 struct drm_device *dev = dev_priv->dev; 681 struct drm_device *dev = dev_priv->dev;
665 682
666 if (acpi_lid_open() && !dev_priv->suspended) { 683 if (!acpi_lid_open()) {
667 mutex_lock(&dev->mode_config.mutex); 684 dev_priv->modeset_on_lid = 1;
668 drm_helper_resume_force_mode(dev); 685 return NOTIFY_OK;
669 mutex_unlock(&dev->mode_config.mutex);
670 } 686 }
671 687
672 drm_sysfs_hotplug_event(dev_priv->dev); 688 if (!dev_priv->modeset_on_lid)
689 return NOTIFY_OK;
690
691 dev_priv->modeset_on_lid = 0;
692
693 mutex_lock(&dev->mode_config.mutex);
694 drm_helper_resume_force_mode(dev);
695 mutex_unlock(&dev->mode_config.mutex);
673 696
674 return NOTIFY_OK; 697 return NOTIFY_OK;
675} 698}
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index 09a28923f46..b5713eedd6e 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -49,7 +49,7 @@ radeon-y += radeon_device.o radeon_kms.o \
49 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ 49 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
50 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ 50 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
51 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ 51 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \
52 r600_blit_kms.o 52 r600_blit_kms.o radeon_pm.o
53 53
54radeon-$(CONFIG_COMPAT) += radeon_ioc32.o 54radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
55 55
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 901befe03da..d67c42555ab 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -107,6 +107,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
107 base += 3; 107 base += 3;
108 break; 108 break;
109 case ATOM_IIO_WRITE: 109 case ATOM_IIO_WRITE:
110 (void)ctx->card->reg_read(ctx->card, CU16(base + 1));
110 ctx->card->reg_write(ctx->card, CU16(base + 1), temp); 111 ctx->card->reg_write(ctx->card, CU16(base + 1), temp);
111 base += 3; 112 base += 3;
112 break; 113 break;
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 5d402086bc4..c11ddddfb3b 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -2314,7 +2314,7 @@ typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT {
2314 UCHAR ucSS_Step; 2314 UCHAR ucSS_Step;
2315 UCHAR ucSS_Delay; 2315 UCHAR ucSS_Delay;
2316 UCHAR ucSS_Id; 2316 UCHAR ucSS_Id;
2317 UCHAR ucRecommandedRef_Div; 2317 UCHAR ucRecommendedRef_Div;
2318 UCHAR ucSS_Range; /* it was reserved for V11 */ 2318 UCHAR ucSS_Range; /* it was reserved for V11 */
2319} ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 2319} ATOM_SPREAD_SPECTRUM_ASSIGNMENT;
2320 2320
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 14fa9701aeb..c15287a590f 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -31,10 +31,6 @@
31#include "atom.h" 31#include "atom.h"
32#include "atom-bits.h" 32#include "atom-bits.h"
33 33
34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing,
37 int32_t *pixel_clock);
38static void atombios_overscan_setup(struct drm_crtc *crtc, 34static void atombios_overscan_setup(struct drm_crtc *crtc,
39 struct drm_display_mode *mode, 35 struct drm_display_mode *mode,
40 struct drm_display_mode *adjusted_mode) 36 struct drm_display_mode *adjusted_mode)
@@ -248,18 +244,18 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
248 244
249 switch (mode) { 245 switch (mode) {
250 case DRM_MODE_DPMS_ON: 246 case DRM_MODE_DPMS_ON:
247 atombios_enable_crtc(crtc, 1);
251 if (ASIC_IS_DCE3(rdev)) 248 if (ASIC_IS_DCE3(rdev))
252 atombios_enable_crtc_memreq(crtc, 1); 249 atombios_enable_crtc_memreq(crtc, 1);
253 atombios_enable_crtc(crtc, 1);
254 atombios_blank_crtc(crtc, 0); 250 atombios_blank_crtc(crtc, 0);
255 break; 251 break;
256 case DRM_MODE_DPMS_STANDBY: 252 case DRM_MODE_DPMS_STANDBY:
257 case DRM_MODE_DPMS_SUSPEND: 253 case DRM_MODE_DPMS_SUSPEND:
258 case DRM_MODE_DPMS_OFF: 254 case DRM_MODE_DPMS_OFF:
259 atombios_blank_crtc(crtc, 1); 255 atombios_blank_crtc(crtc, 1);
260 atombios_enable_crtc(crtc, 0);
261 if (ASIC_IS_DCE3(rdev)) 256 if (ASIC_IS_DCE3(rdev))
262 atombios_enable_crtc_memreq(crtc, 0); 257 atombios_enable_crtc_memreq(crtc, 0);
258 atombios_enable_crtc(crtc, 0);
263 break; 259 break;
264 } 260 }
265 261
@@ -270,59 +266,147 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
270 266
271static void 267static void
272atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 268atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
273 SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param) 269 struct drm_display_mode *mode)
274{ 270{
271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
275 struct drm_device *dev = crtc->dev; 272 struct drm_device *dev = crtc->dev;
276 struct radeon_device *rdev = dev->dev_private; 273 struct radeon_device *rdev = dev->dev_private;
277 SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param; 274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
278 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
276 u16 misc = 0;
279 277
280 conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size); 278 memset(&args, 0, sizeof(args));
281 conv_param.usH_Blanking_Time = 279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
282 cpu_to_le16(crtc_param->usH_Blanking_Time); 280 args.usH_Blanking_Time =
283 conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size); 281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
284 conv_param.usV_Blanking_Time = 282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
285 cpu_to_le16(crtc_param->usV_Blanking_Time); 283 args.usV_Blanking_Time =
286 conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset); 284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
287 conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); 285 args.usH_SyncOffset =
288 conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset); 286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
289 conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); 287 args.usH_SyncWidth =
290 conv_param.susModeMiscInfo.usAccess = 288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
291 cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); 289 args.usV_SyncOffset =
292 conv_param.ucCRTC = crtc_param->ucCRTC; 290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
291 args.usV_SyncWidth =
292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
293 /*args.ucH_Border = mode->hborder;*/
294 /*args.ucV_Border = mode->vborder;*/
295
296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
297 misc |= ATOM_VSYNC_POLARITY;
298 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
299 misc |= ATOM_HSYNC_POLARITY;
300 if (mode->flags & DRM_MODE_FLAG_CSYNC)
301 misc |= ATOM_COMPOSITESYNC;
302 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
303 misc |= ATOM_INTERLACE;
304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 misc |= ATOM_DOUBLE_CLOCK_MODE;
306
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id;
293 309
294 printk("executing set crtc dtd timing\n"); 310 printk("executing set crtc dtd timing\n");
295 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); 311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
296} 312}
297 313
298void atombios_crtc_set_timing(struct drm_crtc *crtc, 314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
299 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION * 315 struct drm_display_mode *mode)
300 crtc_param)
301{ 316{
317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
302 struct drm_device *dev = crtc->dev; 318 struct drm_device *dev = crtc->dev;
303 struct radeon_device *rdev = dev->dev_private; 319 struct radeon_device *rdev = dev->dev_private;
304 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param; 320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
305 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
322 u16 misc = 0;
306 323
307 conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total); 324 memset(&args, 0, sizeof(args));
308 conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp); 325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
309 conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart); 326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
310 conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); 327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
311 conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total); 328 args.usH_SyncWidth =
312 conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp); 329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
313 conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart); 330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
314 conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); 331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
315 conv_param.susModeMiscInfo.usAccess = 332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
316 cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); 333 args.usV_SyncWidth =
317 conv_param.ucCRTC = crtc_param->ucCRTC; 334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
318 conv_param.ucOverscanRight = crtc_param->ucOverscanRight; 335
319 conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft; 336 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
320 conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom; 337 misc |= ATOM_VSYNC_POLARITY;
321 conv_param.ucOverscanTop = crtc_param->ucOverscanTop; 338 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
322 conv_param.ucReserved = crtc_param->ucReserved; 339 misc |= ATOM_HSYNC_POLARITY;
340 if (mode->flags & DRM_MODE_FLAG_CSYNC)
341 misc |= ATOM_COMPOSITESYNC;
342 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
343 misc |= ATOM_INTERLACE;
344 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
345 misc |= ATOM_DOUBLE_CLOCK_MODE;
346
347 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
348 args.ucCRTC = radeon_crtc->crtc_id;
323 349
324 printk("executing set crtc timing\n"); 350 printk("executing set crtc timing\n");
325 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); 351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
352}
353
354static void atombios_set_ss(struct drm_crtc *crtc, int enable)
355{
356 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
357 struct drm_device *dev = crtc->dev;
358 struct radeon_device *rdev = dev->dev_private;
359 struct drm_encoder *encoder = NULL;
360 struct radeon_encoder *radeon_encoder = NULL;
361 struct radeon_encoder_atom_dig *dig = NULL;
362 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
363 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION args;
364 ENABLE_LVDS_SS_PARAMETERS legacy_args;
365 uint16_t percentage = 0;
366 uint8_t type = 0, step = 0, delay = 0, range = 0;
367
368 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
369 if (encoder->crtc == crtc) {
370 radeon_encoder = to_radeon_encoder(encoder);
371 /* only enable spread spectrum on LVDS */
372 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
373 dig = radeon_encoder->enc_priv;
374 if (dig && dig->ss) {
375 percentage = dig->ss->percentage;
376 type = dig->ss->type;
377 step = dig->ss->step;
378 delay = dig->ss->delay;
379 range = dig->ss->range;
380 } else if (enable)
381 return;
382 } else if (enable)
383 return;
384 break;
385 }
386 }
387
388 if (!radeon_encoder)
389 return;
390
391 if (ASIC_IS_AVIVO(rdev)) {
392 memset(&args, 0, sizeof(args));
393 args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
394 args.ucSpreadSpectrumType = type;
395 args.ucSpreadSpectrumStep = step;
396 args.ucSpreadSpectrumDelay = delay;
397 args.ucSpreadSpectrumRange = range;
398 args.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
399 args.ucEnable = enable;
400 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
401 } else {
402 memset(&legacy_args, 0, sizeof(legacy_args));
403 legacy_args.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
404 legacy_args.ucSpreadSpectrumType = type;
405 legacy_args.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
406 legacy_args.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
407 legacy_args.ucEnable = enable;
408 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&legacy_args);
409 }
326} 410}
327 411
328void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 412void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
@@ -333,12 +417,13 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
333 struct drm_encoder *encoder = NULL; 417 struct drm_encoder *encoder = NULL;
334 struct radeon_encoder *radeon_encoder = NULL; 418 struct radeon_encoder *radeon_encoder = NULL;
335 uint8_t frev, crev; 419 uint8_t frev, crev;
336 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 420 int index;
337 SET_PIXEL_CLOCK_PS_ALLOCATION args; 421 SET_PIXEL_CLOCK_PS_ALLOCATION args;
338 PIXEL_CLOCK_PARAMETERS *spc1_ptr; 422 PIXEL_CLOCK_PARAMETERS *spc1_ptr;
339 PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr; 423 PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
340 PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr; 424 PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
341 uint32_t sclock = mode->clock; 425 uint32_t pll_clock = mode->clock;
426 uint32_t adjusted_clock;
342 uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 427 uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
343 struct radeon_pll *pll; 428 struct radeon_pll *pll;
344 int pll_flags = 0; 429 int pll_flags = 0;
@@ -346,8 +431,6 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
346 memset(&args, 0, sizeof(args)); 431 memset(&args, 0, sizeof(args));
347 432
348 if (ASIC_IS_AVIVO(rdev)) { 433 if (ASIC_IS_AVIVO(rdev)) {
349 uint32_t ss_cntl;
350
351 if ((rdev->family == CHIP_RS600) || 434 if ((rdev->family == CHIP_RS600) ||
352 (rdev->family == CHIP_RS690) || 435 (rdev->family == CHIP_RS690) ||
353 (rdev->family == CHIP_RS740)) 436 (rdev->family == CHIP_RS740))
@@ -358,15 +441,6 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
358 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 441 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
359 else 442 else
360 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 443 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
361
362 /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
363 if (radeon_crtc->crtc_id == 0) {
364 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
365 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
366 } else {
367 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
368 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
369 }
370 } else { 444 } else {
371 pll_flags |= RADEON_PLL_LEGACY; 445 pll_flags |= RADEON_PLL_LEGACY;
372 446
@@ -393,14 +467,43 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
393 } 467 }
394 } 468 }
395 469
470 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
471 * accordingly based on the encoder/transmitter to work around
472 * special hw requirements.
473 */
474 if (ASIC_IS_DCE3(rdev)) {
475 ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args;
476
477 if (!encoder)
478 return;
479
480 memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
481 adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
482 adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
483 adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
484
485 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
486 atom_execute_table(rdev->mode_info.atom_context,
487 index, (uint32_t *)&adjust_pll_args);
488 adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10;
489 } else {
490 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
491 if (ASIC_IS_AVIVO(rdev) &&
492 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
493 adjusted_clock = mode->clock * 2;
494 else
495 adjusted_clock = mode->clock;
496 }
497
396 if (radeon_crtc->crtc_id == 0) 498 if (radeon_crtc->crtc_id == 0)
397 pll = &rdev->clock.p1pll; 499 pll = &rdev->clock.p1pll;
398 else 500 else
399 pll = &rdev->clock.p2pll; 501 pll = &rdev->clock.p2pll;
400 502
401 radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div, 503 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
402 &ref_div, &post_div, pll_flags); 504 &ref_div, &post_div, pll_flags);
403 505
506 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
404 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 507 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
405 &crev); 508 &crev);
406 509
@@ -409,7 +512,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
409 switch (crev) { 512 switch (crev) {
410 case 1: 513 case 1:
411 spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput; 514 spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
412 spc1_ptr->usPixelClock = cpu_to_le16(sclock); 515 spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
413 spc1_ptr->usRefDiv = cpu_to_le16(ref_div); 516 spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
414 spc1_ptr->usFbDiv = cpu_to_le16(fb_div); 517 spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
415 spc1_ptr->ucFracFbDiv = frac_fb_div; 518 spc1_ptr->ucFracFbDiv = frac_fb_div;
@@ -422,7 +525,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
422 case 2: 525 case 2:
423 spc2_ptr = 526 spc2_ptr =
424 (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput; 527 (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
425 spc2_ptr->usPixelClock = cpu_to_le16(sclock); 528 spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
426 spc2_ptr->usRefDiv = cpu_to_le16(ref_div); 529 spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
427 spc2_ptr->usFbDiv = cpu_to_le16(fb_div); 530 spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
428 spc2_ptr->ucFracFbDiv = frac_fb_div; 531 spc2_ptr->ucFracFbDiv = frac_fb_div;
@@ -437,7 +540,7 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
437 return; 540 return;
438 spc3_ptr = 541 spc3_ptr =
439 (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput; 542 (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
440 spc3_ptr->usPixelClock = cpu_to_le16(sclock); 543 spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10);
441 spc3_ptr->usRefDiv = cpu_to_le16(ref_div); 544 spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
442 spc3_ptr->usFbDiv = cpu_to_le16(fb_div); 545 spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
443 spc3_ptr->ucFracFbDiv = frac_fb_div; 546 spc3_ptr->ucFracFbDiv = frac_fb_div;
@@ -527,6 +630,16 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
527 WREG32(AVIVO_D1VGA_CONTROL, 0); 630 WREG32(AVIVO_D1VGA_CONTROL, 0);
528 else 631 else
529 WREG32(AVIVO_D2VGA_CONTROL, 0); 632 WREG32(AVIVO_D2VGA_CONTROL, 0);
633
634 if (rdev->family >= CHIP_RV770) {
635 if (radeon_crtc->crtc_id) {
636 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
637 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
638 } else {
639 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
640 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
641 }
642 }
530 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 643 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
531 (u32) fb_location); 644 (u32) fb_location);
532 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 645 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
@@ -563,6 +676,10 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
563 radeon_fb = to_radeon_framebuffer(old_fb); 676 radeon_fb = to_radeon_framebuffer(old_fb);
564 radeon_gem_object_unpin(radeon_fb->obj); 677 radeon_gem_object_unpin(radeon_fb->obj);
565 } 678 }
679
680 /* Bytes per pixel may have changed */
681 radeon_bandwidth_update(rdev);
682
566 return 0; 683 return 0;
567} 684}
568 685
@@ -574,134 +691,24 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
574 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 691 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
575 struct drm_device *dev = crtc->dev; 692 struct drm_device *dev = crtc->dev;
576 struct radeon_device *rdev = dev->dev_private; 693 struct radeon_device *rdev = dev->dev_private;
577 struct drm_encoder *encoder;
578 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
579 int need_tv_timings = 0;
580 bool ret;
581 694
582 /* TODO color tiling */ 695 /* TODO color tiling */
583 memset(&crtc_timing, 0, sizeof(crtc_timing));
584
585 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
586 /* find tv std */
587 if (encoder->crtc == crtc) {
588 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
589
590 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
591 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
592 if (tv_dac) {
593 if (tv_dac->tv_std == TV_STD_NTSC ||
594 tv_dac->tv_std == TV_STD_NTSC_J ||
595 tv_dac->tv_std == TV_STD_PAL_M)
596 need_tv_timings = 1;
597 else
598 need_tv_timings = 2;
599 break;
600 }
601 }
602 }
603 }
604
605 crtc_timing.ucCRTC = radeon_crtc->crtc_id;
606 if (need_tv_timings) {
607 ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1,
608 &crtc_timing, &adjusted_mode->clock);
609 if (ret == false)
610 need_tv_timings = 0;
611 }
612
613 if (!need_tv_timings) {
614 crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
615 crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
616 crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
617 crtc_timing.usH_SyncWidth =
618 adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
619
620 crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
621 crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
622 crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
623 crtc_timing.usV_SyncWidth =
624 adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
625
626 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
627 crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
628
629 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
630 crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
631
632 if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
633 crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
634
635 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
636 crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
637
638 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
639 crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
640 }
641 696
697 atombios_set_ss(crtc, 0);
642 atombios_crtc_set_pll(crtc, adjusted_mode); 698 atombios_crtc_set_pll(crtc, adjusted_mode);
643 atombios_crtc_set_timing(crtc, &crtc_timing); 699 atombios_set_ss(crtc, 1);
700 atombios_crtc_set_timing(crtc, adjusted_mode);
644 701
645 if (ASIC_IS_AVIVO(rdev)) 702 if (ASIC_IS_AVIVO(rdev))
646 atombios_crtc_set_base(crtc, x, y, old_fb); 703 atombios_crtc_set_base(crtc, x, y, old_fb);
647 else { 704 else {
648 if (radeon_crtc->crtc_id == 0) { 705 if (radeon_crtc->crtc_id == 0)
649 SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing; 706 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
650 memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing));
651
652 /* setup FP shadow regs on R4xx */
653 crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id;
654 crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay;
655 crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay;
656 crtc_dtd_timing.usH_Blanking_Time =
657 adjusted_mode->crtc_hblank_end -
658 adjusted_mode->crtc_hdisplay;
659 crtc_dtd_timing.usV_Blanking_Time =
660 adjusted_mode->crtc_vblank_end -
661 adjusted_mode->crtc_vdisplay;
662 crtc_dtd_timing.usH_SyncOffset =
663 adjusted_mode->crtc_hsync_start -
664 adjusted_mode->crtc_hdisplay;
665 crtc_dtd_timing.usV_SyncOffset =
666 adjusted_mode->crtc_vsync_start -
667 adjusted_mode->crtc_vdisplay;
668 crtc_dtd_timing.usH_SyncWidth =
669 adjusted_mode->crtc_hsync_end -
670 adjusted_mode->crtc_hsync_start;
671 crtc_dtd_timing.usV_SyncWidth =
672 adjusted_mode->crtc_vsync_end -
673 adjusted_mode->crtc_vsync_start;
674 /* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */
675 /* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */
676
677 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
678 crtc_dtd_timing.susModeMiscInfo.usAccess |=
679 ATOM_VSYNC_POLARITY;
680
681 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
682 crtc_dtd_timing.susModeMiscInfo.usAccess |=
683 ATOM_HSYNC_POLARITY;
684
685 if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
686 crtc_dtd_timing.susModeMiscInfo.usAccess |=
687 ATOM_COMPOSITESYNC;
688
689 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
690 crtc_dtd_timing.susModeMiscInfo.usAccess |=
691 ATOM_INTERLACE;
692
693 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
694 crtc_dtd_timing.susModeMiscInfo.usAccess |=
695 ATOM_DOUBLE_CLOCK_MODE;
696
697 atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing);
698 }
699 radeon_crtc_set_base(crtc, x, y, old_fb); 707 radeon_crtc_set_base(crtc, x, y, old_fb);
700 radeon_legacy_atom_set_surface(crtc); 708 radeon_legacy_atom_set_surface(crtc);
701 } 709 }
702 atombios_overscan_setup(crtc, mode, adjusted_mode); 710 atombios_overscan_setup(crtc, mode, adjusted_mode);
703 atombios_scaler_setup(crtc); 711 atombios_scaler_setup(crtc);
704 radeon_bandwidth_update(rdev);
705 return 0; 712 return 0;
706} 713}
707 714
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
index fb211e585de..0d79577c157 100644
--- a/drivers/gpu/drm/radeon/mkregtable.c
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -561,7 +561,7 @@ struct table {
561 char *gpu_prefix; 561 char *gpu_prefix;
562}; 562};
563 563
564struct offset *offset_new(unsigned o) 564static struct offset *offset_new(unsigned o)
565{ 565{
566 struct offset *offset; 566 struct offset *offset;
567 567
@@ -573,12 +573,12 @@ struct offset *offset_new(unsigned o)
573 return offset; 573 return offset;
574} 574}
575 575
576void table_offset_add(struct table *t, struct offset *offset) 576static void table_offset_add(struct table *t, struct offset *offset)
577{ 577{
578 list_add_tail(&offset->list, &t->offsets); 578 list_add_tail(&offset->list, &t->offsets);
579} 579}
580 580
581void table_init(struct table *t) 581static void table_init(struct table *t)
582{ 582{
583 INIT_LIST_HEAD(&t->offsets); 583 INIT_LIST_HEAD(&t->offsets);
584 t->offset_max = 0; 584 t->offset_max = 0;
@@ -586,7 +586,7 @@ void table_init(struct table *t)
586 t->table = NULL; 586 t->table = NULL;
587} 587}
588 588
589void table_print(struct table *t) 589static void table_print(struct table *t)
590{ 590{
591 unsigned nlloop, i, j, n, c, id; 591 unsigned nlloop, i, j, n, c, id;
592 592
@@ -611,7 +611,7 @@ void table_print(struct table *t)
611 printf("};\n"); 611 printf("};\n");
612} 612}
613 613
614int table_build(struct table *t) 614static int table_build(struct table *t)
615{ 615{
616 struct offset *offset; 616 struct offset *offset;
617 unsigned i, m; 617 unsigned i, m;
@@ -631,7 +631,7 @@ int table_build(struct table *t)
631} 631}
632 632
633static char gpu_name[10]; 633static char gpu_name[10];
634int parser_auth(struct table *t, const char *filename) 634static int parser_auth(struct table *t, const char *filename)
635{ 635{
636 FILE *file; 636 FILE *file;
637 regex_t mask_rex; 637 regex_t mask_rex;
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 161094c07d9..c9e93eabcf1 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -186,7 +186,7 @@ static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
186 186
187int r100_irq_process(struct radeon_device *rdev) 187int r100_irq_process(struct radeon_device *rdev)
188{ 188{
189 uint32_t status; 189 uint32_t status, msi_rearm;
190 190
191 status = r100_irq_ack(rdev); 191 status = r100_irq_ack(rdev);
192 if (!status) { 192 if (!status) {
@@ -209,6 +209,21 @@ int r100_irq_process(struct radeon_device *rdev)
209 } 209 }
210 status = r100_irq_ack(rdev); 210 status = r100_irq_ack(rdev);
211 } 211 }
212 if (rdev->msi_enabled) {
213 switch (rdev->family) {
214 case CHIP_RS400:
215 case CHIP_RS480:
216 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
217 WREG32(RADEON_AIC_CNTL, msi_rearm);
218 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
219 break;
220 default:
221 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
222 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
223 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
224 break;
225 }
226 }
212 return IRQ_HANDLED; 227 return IRQ_HANDLED;
213} 228}
214 229
@@ -240,7 +255,7 @@ int r100_wb_init(struct radeon_device *rdev)
240 int r; 255 int r;
241 256
242 if (rdev->wb.wb_obj == NULL) { 257 if (rdev->wb.wb_obj == NULL) {
243 r = radeon_object_create(rdev, NULL, 4096, 258 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE,
244 true, 259 true,
245 RADEON_GEM_DOMAIN_GTT, 260 RADEON_GEM_DOMAIN_GTT,
246 false, &rdev->wb.wb_obj); 261 false, &rdev->wb.wb_obj);
@@ -563,19 +578,19 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
563 indirect1_start = 16; 578 indirect1_start = 16;
564 /* cp setup */ 579 /* cp setup */
565 WREG32(0x718, pre_write_timer | (pre_write_limit << 28)); 580 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
566 WREG32(RADEON_CP_RB_CNTL, 581 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
567#ifdef __BIG_ENDIAN
568 RADEON_BUF_SWAP_32BIT |
569#endif
570 REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
571 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | 582 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
572 REG_SET(RADEON_MAX_FETCH, max_fetch) | 583 REG_SET(RADEON_MAX_FETCH, max_fetch) |
573 RADEON_RB_NO_UPDATE); 584 RADEON_RB_NO_UPDATE);
585#ifdef __BIG_ENDIAN
586 tmp |= RADEON_BUF_SWAP_32BIT;
587#endif
588 WREG32(RADEON_CP_RB_CNTL, tmp);
589
574 /* Set ring address */ 590 /* Set ring address */
575 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); 591 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
576 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); 592 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
577 /* Force read & write ptr to 0 */ 593 /* Force read & write ptr to 0 */
578 tmp = RREG32(RADEON_CP_RB_CNTL);
579 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 594 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
580 WREG32(RADEON_CP_RB_RPTR_WR, 0); 595 WREG32(RADEON_CP_RB_RPTR_WR, 0);
581 WREG32(RADEON_CP_RB_WPTR, 0); 596 WREG32(RADEON_CP_RB_WPTR, 0);
@@ -2364,7 +2379,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2364 /* 2379 /*
2365 Find the total latency for the display data. 2380 Find the total latency for the display data.
2366 */ 2381 */
2367 disp_latency_overhead.full = rfixed_const(80); 2382 disp_latency_overhead.full = rfixed_const(8);
2368 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff); 2383 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2369 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full; 2384 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2370 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full; 2385 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
@@ -2562,8 +2577,11 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2562static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t) 2577static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2563{ 2578{
2564 DRM_ERROR("pitch %d\n", t->pitch); 2579 DRM_ERROR("pitch %d\n", t->pitch);
2580 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2565 DRM_ERROR("width %d\n", t->width); 2581 DRM_ERROR("width %d\n", t->width);
2582 DRM_ERROR("width_11 %d\n", t->width_11);
2566 DRM_ERROR("height %d\n", t->height); 2583 DRM_ERROR("height %d\n", t->height);
2584 DRM_ERROR("height_11 %d\n", t->height_11);
2567 DRM_ERROR("num levels %d\n", t->num_levels); 2585 DRM_ERROR("num levels %d\n", t->num_levels);
2568 DRM_ERROR("depth %d\n", t->txdepth); 2586 DRM_ERROR("depth %d\n", t->txdepth);
2569 DRM_ERROR("bpp %d\n", t->cpp); 2587 DRM_ERROR("bpp %d\n", t->cpp);
@@ -2623,15 +2641,17 @@ static int r100_cs_track_texture_check(struct radeon_device *rdev,
2623 else 2641 else
2624 w = track->textures[u].pitch / (1 << i); 2642 w = track->textures[u].pitch / (1 << i);
2625 } else { 2643 } else {
2626 w = track->textures[u].width / (1 << i); 2644 w = track->textures[u].width;
2627 if (rdev->family >= CHIP_RV515) 2645 if (rdev->family >= CHIP_RV515)
2628 w |= track->textures[u].width_11; 2646 w |= track->textures[u].width_11;
2647 w = w / (1 << i);
2629 if (track->textures[u].roundup_w) 2648 if (track->textures[u].roundup_w)
2630 w = roundup_pow_of_two(w); 2649 w = roundup_pow_of_two(w);
2631 } 2650 }
2632 h = track->textures[u].height / (1 << i); 2651 h = track->textures[u].height;
2633 if (rdev->family >= CHIP_RV515) 2652 if (rdev->family >= CHIP_RV515)
2634 h |= track->textures[u].height_11; 2653 h |= track->textures[u].height_11;
2654 h = h / (1 << i);
2635 if (track->textures[u].roundup_h) 2655 if (track->textures[u].roundup_h)
2636 h = roundup_pow_of_two(h); 2656 h = roundup_pow_of_two(h);
2637 size += w * h; 2657 size += w * h;
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index e08c4a8974c..2f43ee8e404 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -113,7 +113,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
113 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD; 113 tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
114 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); 114 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
115 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location); 115 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
116 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096; 116 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - RADEON_GPU_PAGE_SIZE;
117 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); 117 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
118 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); 118 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
119 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); 119 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 5c7fe52de30..1cefdbcc085 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -311,6 +311,8 @@ int r420_init(struct radeon_device *rdev)
311 } 311 }
312 /* Initialize clocks */ 312 /* Initialize clocks */
313 radeon_get_clock_info(rdev->ddev); 313 radeon_get_clock_info(rdev->ddev);
314 /* Initialize power management */
315 radeon_pm_init(rdev);
314 /* Get vram informations */ 316 /* Get vram informations */
315 r300_vram_info(rdev); 317 r300_vram_info(rdev);
316 /* Initialize memory controller (also test AGP) */ 318 /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index 868add6e166..7baa7395556 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -384,9 +384,16 @@
384# define AVIVO_D1GRPH_TILED (1 << 20) 384# define AVIVO_D1GRPH_TILED (1 << 20)
385# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21) 385# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1 << 21)
386 386
387/* The R7xx *_HIGH surface regs are backwards; the D1 regs are in the D2
388 * block and vice versa. This applies to GRPH, CUR, etc.
389 */
387#define AVIVO_D1GRPH_LUT_SEL 0x6108 390#define AVIVO_D1GRPH_LUT_SEL 0x6108
388#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110 391#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
392#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
393#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
389#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118 394#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
395#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
396#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
390#define AVIVO_D1GRPH_PITCH 0x6120 397#define AVIVO_D1GRPH_PITCH 0x6120
391#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124 398#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
392#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128 399#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
@@ -404,6 +411,8 @@
404# define AVIVO_D1CURSOR_MODE_MASK (3 << 8) 411# define AVIVO_D1CURSOR_MODE_MASK (3 << 8)
405# define AVIVO_D1CURSOR_MODE_24BPP 2 412# define AVIVO_D1CURSOR_MODE_24BPP 2
406#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408 413#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
414#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c
415#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c
407#define AVIVO_D1CUR_SIZE 0x6410 416#define AVIVO_D1CUR_SIZE 0x6410
408#define AVIVO_D1CUR_POSITION 0x6414 417#define AVIVO_D1CUR_POSITION 0x6414
409#define AVIVO_D1CUR_HOT_SPOT 0x6418 418#define AVIVO_D1CUR_HOT_SPOT 0x6418
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index a555b7b19b4..f7435185c0a 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -260,6 +260,8 @@ int r520_init(struct radeon_device *rdev)
260 } 260 }
261 /* Initialize clocks */ 261 /* Initialize clocks */
262 radeon_get_clock_info(rdev->ddev); 262 radeon_get_clock_info(rdev->ddev);
263 /* Initialize power management */
264 radeon_pm_init(rdev);
263 /* Get vram informations */ 265 /* Get vram informations */
264 r520_vram_info(rdev); 266 r520_vram_info(rdev);
265 /* Initialize memory controller (also test AGP) */ 267 /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 609719490ec..278f646bc18 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -339,11 +339,10 @@ int r600_mc_init(struct radeon_device *rdev)
339{ 339{
340 fixed20_12 a; 340 fixed20_12 a;
341 u32 tmp; 341 u32 tmp;
342 int chansize; 342 int chansize, numchan;
343 int r; 343 int r;
344 344
345 /* Get VRAM informations */ 345 /* Get VRAM informations */
346 rdev->mc.vram_width = 128;
347 rdev->mc.vram_is_ddr = true; 346 rdev->mc.vram_is_ddr = true;
348 tmp = RREG32(RAMCFG); 347 tmp = RREG32(RAMCFG);
349 if (tmp & CHANSIZE_OVERRIDE) { 348 if (tmp & CHANSIZE_OVERRIDE) {
@@ -353,17 +352,23 @@ int r600_mc_init(struct radeon_device *rdev)
353 } else { 352 } else {
354 chansize = 32; 353 chansize = 32;
355 } 354 }
356 if (rdev->family == CHIP_R600) { 355 tmp = RREG32(CHMAP);
357 rdev->mc.vram_width = 8 * chansize; 356 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
358 } else if (rdev->family == CHIP_RV670) { 357 case 0:
359 rdev->mc.vram_width = 4 * chansize; 358 default:
360 } else if ((rdev->family == CHIP_RV610) || 359 numchan = 1;
361 (rdev->family == CHIP_RV620)) { 360 break;
362 rdev->mc.vram_width = chansize; 361 case 1:
363 } else if ((rdev->family == CHIP_RV630) || 362 numchan = 2;
364 (rdev->family == CHIP_RV635)) { 363 break;
365 rdev->mc.vram_width = 2 * chansize; 364 case 2:
365 numchan = 4;
366 break;
367 case 3:
368 numchan = 8;
369 break;
366 } 370 }
371 rdev->mc.vram_width = numchan * chansize;
367 /* Could aper size report 0 ? */ 372 /* Could aper size report 0 ? */
368 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 373 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
369 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 374 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
@@ -404,35 +409,29 @@ int r600_mc_init(struct radeon_device *rdev)
404 rdev->mc.gtt_location = rdev->mc.mc_vram_size; 409 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
405 } 410 }
406 } else { 411 } else {
407 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) { 412 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
408 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) & 413 rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
409 0xFFFF) << 24; 414 0xFFFF) << 24;
410 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 415 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
411 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; 416 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
412 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { 417 /* Enough place after vram */
413 /* Enough place after vram */ 418 rdev->mc.gtt_location = tmp;
414 rdev->mc.gtt_location = tmp; 419 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
415 } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) { 420 /* Enough place before vram */
416 /* Enough place before vram */ 421 rdev->mc.gtt_location = 0;
422 } else {
423 /* Not enough place after or before shrink
424 * gart size
425 */
426 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
417 rdev->mc.gtt_location = 0; 427 rdev->mc.gtt_location = 0;
428 rdev->mc.gtt_size = rdev->mc.vram_location;
418 } else { 429 } else {
419 /* Not enough place after or before shrink 430 rdev->mc.gtt_location = tmp;
420 * gart size 431 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
421 */
422 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
423 rdev->mc.gtt_location = 0;
424 rdev->mc.gtt_size = rdev->mc.vram_location;
425 } else {
426 rdev->mc.gtt_location = tmp;
427 rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
428 }
429 } 432 }
430 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
431 } else {
432 rdev->mc.vram_location = 0x00000000UL;
433 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
434 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
435 } 433 }
434 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
436 } 435 }
437 rdev->mc.vram_start = rdev->mc.vram_location; 436 rdev->mc.vram_start = rdev->mc.vram_location;
438 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; 437 rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
@@ -859,7 +858,8 @@ void r600_gpu_init(struct radeon_device *rdev)
859 ((rdev->family) == CHIP_RV630) || 858 ((rdev->family) == CHIP_RV630) ||
860 ((rdev->family) == CHIP_RV610) || 859 ((rdev->family) == CHIP_RV610) ||
861 ((rdev->family) == CHIP_RV620) || 860 ((rdev->family) == CHIP_RV620) ||
862 ((rdev->family) == CHIP_RS780)) { 861 ((rdev->family) == CHIP_RS780) ||
862 ((rdev->family) == CHIP_RS880)) {
863 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); 863 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
864 } else { 864 } else {
865 WREG32(DB_DEBUG, 0); 865 WREG32(DB_DEBUG, 0);
@@ -876,7 +876,8 @@ void r600_gpu_init(struct radeon_device *rdev)
876 tmp = RREG32(SQ_MS_FIFO_SIZES); 876 tmp = RREG32(SQ_MS_FIFO_SIZES);
877 if (((rdev->family) == CHIP_RV610) || 877 if (((rdev->family) == CHIP_RV610) ||
878 ((rdev->family) == CHIP_RV620) || 878 ((rdev->family) == CHIP_RV620) ||
879 ((rdev->family) == CHIP_RS780)) { 879 ((rdev->family) == CHIP_RS780) ||
880 ((rdev->family) == CHIP_RS880)) {
880 tmp = (CACHE_FIFO_SIZE(0xa) | 881 tmp = (CACHE_FIFO_SIZE(0xa) |
881 FETCH_FIFO_HIWATER(0xa) | 882 FETCH_FIFO_HIWATER(0xa) |
882 DONE_FIFO_HIWATER(0xe0) | 883 DONE_FIFO_HIWATER(0xe0) |
@@ -919,7 +920,8 @@ void r600_gpu_init(struct radeon_device *rdev)
919 NUM_ES_STACK_ENTRIES(0)); 920 NUM_ES_STACK_ENTRIES(0));
920 } else if (((rdev->family) == CHIP_RV610) || 921 } else if (((rdev->family) == CHIP_RV610) ||
921 ((rdev->family) == CHIP_RV620) || 922 ((rdev->family) == CHIP_RV620) ||
922 ((rdev->family) == CHIP_RS780)) { 923 ((rdev->family) == CHIP_RS780) ||
924 ((rdev->family) == CHIP_RS880)) {
923 /* no vertex cache */ 925 /* no vertex cache */
924 sq_config &= ~VC_ENABLE; 926 sq_config &= ~VC_ENABLE;
925 927
@@ -976,7 +978,8 @@ void r600_gpu_init(struct radeon_device *rdev)
976 978
977 if (((rdev->family) == CHIP_RV610) || 979 if (((rdev->family) == CHIP_RV610) ||
978 ((rdev->family) == CHIP_RV620) || 980 ((rdev->family) == CHIP_RV620) ||
979 ((rdev->family) == CHIP_RS780)) { 981 ((rdev->family) == CHIP_RS780) ||
982 ((rdev->family) == CHIP_RS880)) {
980 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); 983 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
981 } else { 984 } else {
982 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); 985 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
@@ -1002,8 +1005,9 @@ void r600_gpu_init(struct radeon_device *rdev)
1002 tmp = rdev->config.r600.max_pipes * 16; 1005 tmp = rdev->config.r600.max_pipes * 16;
1003 switch (rdev->family) { 1006 switch (rdev->family) {
1004 case CHIP_RV610: 1007 case CHIP_RV610:
1005 case CHIP_RS780:
1006 case CHIP_RV620: 1008 case CHIP_RV620:
1009 case CHIP_RS780:
1010 case CHIP_RS880:
1007 tmp += 32; 1011 tmp += 32;
1008 break; 1012 break;
1009 case CHIP_RV670: 1013 case CHIP_RV670:
@@ -1044,8 +1048,9 @@ void r600_gpu_init(struct radeon_device *rdev)
1044 1048
1045 switch (rdev->family) { 1049 switch (rdev->family) {
1046 case CHIP_RV610: 1050 case CHIP_RV610:
1047 case CHIP_RS780:
1048 case CHIP_RV620: 1051 case CHIP_RV620:
1052 case CHIP_RS780:
1053 case CHIP_RS880:
1049 tmp = TC_L2_SIZE(8); 1054 tmp = TC_L2_SIZE(8);
1050 break; 1055 break;
1051 case CHIP_RV630: 1056 case CHIP_RV630:
@@ -1267,19 +1272,17 @@ int r600_cp_resume(struct radeon_device *rdev)
1267 1272
1268 /* Set ring buffer size */ 1273 /* Set ring buffer size */
1269 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 1274 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1275 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1270#ifdef __BIG_ENDIAN 1276#ifdef __BIG_ENDIAN
1271 WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE | 1277 tmp |= BUF_SWAP_32BIT;
1272 (drm_order(4096/8) << 8) | rb_bufsz);
1273#else
1274 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
1275#endif 1278#endif
1279 WREG32(CP_RB_CNTL, tmp);
1276 WREG32(CP_SEM_WAIT_TIMER, 0x4); 1280 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1277 1281
1278 /* Set the write pointer delay */ 1282 /* Set the write pointer delay */
1279 WREG32(CP_RB_WPTR_DELAY, 0); 1283 WREG32(CP_RB_WPTR_DELAY, 0);
1280 1284
1281 /* Initialize the ring buffer's read and write pointers */ 1285 /* Initialize the ring buffer's read and write pointers */
1282 tmp = RREG32(CP_RB_CNTL);
1283 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 1286 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1284 WREG32(CP_RB_RPTR_WR, 0); 1287 WREG32(CP_RB_RPTR_WR, 0);
1285 WREG32(CP_RB_WPTR, 0); 1288 WREG32(CP_RB_WPTR, 0);
@@ -1400,7 +1403,7 @@ int r600_wb_enable(struct radeon_device *rdev)
1400 int r; 1403 int r;
1401 1404
1402 if (rdev->wb.wb_obj == NULL) { 1405 if (rdev->wb.wb_obj == NULL) {
1403 r = radeon_object_create(rdev, NULL, 4096, true, 1406 r = radeon_object_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1404 RADEON_GEM_DOMAIN_GTT, false, &rdev->wb.wb_obj); 1407 RADEON_GEM_DOMAIN_GTT, false, &rdev->wb.wb_obj);
1405 if (r) { 1408 if (r) {
1406 dev_warn(rdev->dev, "failed to create WB buffer (%d).\n", r); 1409 dev_warn(rdev->dev, "failed to create WB buffer (%d).\n", r);
@@ -1450,8 +1453,8 @@ int r600_copy_blit(struct radeon_device *rdev,
1450 uint64_t src_offset, uint64_t dst_offset, 1453 uint64_t src_offset, uint64_t dst_offset,
1451 unsigned num_pages, struct radeon_fence *fence) 1454 unsigned num_pages, struct radeon_fence *fence)
1452{ 1455{
1453 r600_blit_prepare_copy(rdev, num_pages * 4096); 1456 r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1454 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096); 1457 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1455 r600_blit_done_copy(rdev, fence); 1458 r600_blit_done_copy(rdev, fence);
1456 return 0; 1459 return 0;
1457} 1460}
@@ -1632,10 +1635,13 @@ int r600_init(struct radeon_device *rdev)
1632 r600_scratch_init(rdev); 1635 r600_scratch_init(rdev);
1633 /* Initialize surface registers */ 1636 /* Initialize surface registers */
1634 radeon_surface_init(rdev); 1637 radeon_surface_init(rdev);
1638 /* Initialize clocks */
1635 radeon_get_clock_info(rdev->ddev); 1639 radeon_get_clock_info(rdev->ddev);
1636 r = radeon_clocks_init(rdev); 1640 r = radeon_clocks_init(rdev);
1637 if (r) 1641 if (r)
1638 return r; 1642 return r;
1643 /* Initialize power management */
1644 radeon_pm_init(rdev);
1639 /* Fence driver */ 1645 /* Fence driver */
1640 r = radeon_fence_driver_init(rdev); 1646 r = radeon_fence_driver_init(rdev);
1641 if (r) 1647 if (r)
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index dec50108160..5ea43234758 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -582,6 +582,8 @@ r600_blit_copy(struct drm_device *dev,
582 u64 vb_addr; 582 u64 vb_addr;
583 u32 *vb; 583 u32 *vb;
584 584
585 vb = r600_nomm_get_vb_ptr(dev);
586
585 if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { 587 if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
586 max_bytes = 8192; 588 max_bytes = 8192;
587 589
@@ -617,8 +619,8 @@ r600_blit_copy(struct drm_device *dev,
617 if (!dev_priv->blit_vb) 619 if (!dev_priv->blit_vb)
618 return; 620 return;
619 set_shaders(dev); 621 set_shaders(dev);
622 vb = r600_nomm_get_vb_ptr(dev);
620 } 623 }
621 vb = r600_nomm_get_vb_ptr(dev);
622 624
623 vb[0] = i2f(dst_x); 625 vb[0] = i2f(dst_x);
624 vb[1] = 0; 626 vb[1] = 0;
@@ -706,8 +708,8 @@ r600_blit_copy(struct drm_device *dev,
706 return; 708 return;
707 709
708 set_shaders(dev); 710 set_shaders(dev);
711 vb = r600_nomm_get_vb_ptr(dev);
709 } 712 }
710 vb = r600_nomm_get_vb_ptr(dev);
711 713
712 vb[0] = i2f(dst_x / 4); 714 vb[0] = i2f(dst_x / 4);
713 vb[1] = 0; 715 vb[1] = 0;
@@ -772,6 +774,7 @@ r600_blit_swap(struct drm_device *dev,
772{ 774{
773 drm_radeon_private_t *dev_priv = dev->dev_private; 775 drm_radeon_private_t *dev_priv = dev->dev_private;
774 int cb_format, tex_format; 776 int cb_format, tex_format;
777 int sx2, sy2, dx2, dy2;
775 u64 vb_addr; 778 u64 vb_addr;
776 u32 *vb; 779 u32 *vb;
777 780
@@ -786,16 +789,10 @@ r600_blit_swap(struct drm_device *dev,
786 } 789 }
787 vb = r600_nomm_get_vb_ptr(dev); 790 vb = r600_nomm_get_vb_ptr(dev);
788 791
789 if (cpp == 4) { 792 sx2 = sx + w;
790 cb_format = COLOR_8_8_8_8; 793 sy2 = sy + h;
791 tex_format = FMT_8_8_8_8; 794 dx2 = dx + w;
792 } else if (cpp == 2) { 795 dy2 = dy + h;
793 cb_format = COLOR_5_6_5;
794 tex_format = FMT_5_6_5;
795 } else {
796 cb_format = COLOR_8;
797 tex_format = FMT_8;
798 }
799 796
800 vb[0] = i2f(dx); 797 vb[0] = i2f(dx);
801 vb[1] = i2f(dy); 798 vb[1] = i2f(dy);
@@ -803,31 +800,46 @@ r600_blit_swap(struct drm_device *dev,
803 vb[3] = i2f(sy); 800 vb[3] = i2f(sy);
804 801
805 vb[4] = i2f(dx); 802 vb[4] = i2f(dx);
806 vb[5] = i2f(dy + h); 803 vb[5] = i2f(dy2);
807 vb[6] = i2f(sx); 804 vb[6] = i2f(sx);
808 vb[7] = i2f(sy + h); 805 vb[7] = i2f(sy2);
806
807 vb[8] = i2f(dx2);
808 vb[9] = i2f(dy2);
809 vb[10] = i2f(sx2);
810 vb[11] = i2f(sy2);
809 811
810 vb[8] = i2f(dx + w); 812 switch(cpp) {
811 vb[9] = i2f(dy + h); 813 case 4:
812 vb[10] = i2f(sx + w); 814 cb_format = COLOR_8_8_8_8;
813 vb[11] = i2f(sy + h); 815 tex_format = FMT_8_8_8_8;
816 break;
817 case 2:
818 cb_format = COLOR_5_6_5;
819 tex_format = FMT_5_6_5;
820 break;
821 default:
822 cb_format = COLOR_8;
823 tex_format = FMT_8;
824 break;
825 }
814 826
815 /* src */ 827 /* src */
816 set_tex_resource(dev_priv, tex_format, 828 set_tex_resource(dev_priv, tex_format,
817 src_pitch / cpp, 829 src_pitch / cpp,
818 sy + h, src_pitch / cpp, 830 sy2, src_pitch / cpp,
819 src_gpu_addr); 831 src_gpu_addr);
820 832
821 cp_set_surface_sync(dev_priv, 833 cp_set_surface_sync(dev_priv,
822 R600_TC_ACTION_ENA, (src_pitch * (sy + h)), src_gpu_addr); 834 R600_TC_ACTION_ENA, src_pitch * sy2, src_gpu_addr);
823 835
824 /* dst */ 836 /* dst */
825 set_render_target(dev_priv, cb_format, 837 set_render_target(dev_priv, cb_format,
826 dst_pitch / cpp, dy + h, 838 dst_pitch / cpp, dy2,
827 dst_gpu_addr); 839 dst_gpu_addr);
828 840
829 /* scissors */ 841 /* scissors */
830 set_scissors(dev_priv, dx, dy, dx + w, dy + h); 842 set_scissors(dev_priv, dx, dy, dx2, dy2);
831 843
832 /* Vertex buffer setup */ 844 /* Vertex buffer setup */
833 vb_addr = dev_priv->gart_buffers_offset + 845 vb_addr = dev_priv->gart_buffers_offset +
@@ -840,7 +852,7 @@ r600_blit_swap(struct drm_device *dev,
840 852
841 cp_set_surface_sync(dev_priv, 853 cp_set_surface_sync(dev_priv,
842 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA, 854 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
843 dst_pitch * (dy + h), dst_gpu_addr); 855 dst_pitch * dy2, dst_gpu_addr);
844 856
845 dev_priv->blit_vb->used += 12 * 4; 857 dev_priv->blit_vb->used += 12 * 4;
846} 858}
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 93108bb31d1..dbf716e1fbf 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -368,7 +368,7 @@ set_default_state(struct radeon_device *rdev)
368 if ((rdev->family == CHIP_RV610) || 368 if ((rdev->family == CHIP_RV610) ||
369 (rdev->family == CHIP_RV620) || 369 (rdev->family == CHIP_RV620) ||
370 (rdev->family == CHIP_RS780) || 370 (rdev->family == CHIP_RS780) ||
371 (rdev->family == CHIP_RS780) || 371 (rdev->family == CHIP_RS880) ||
372 (rdev->family == CHIP_RV710)) 372 (rdev->family == CHIP_RV710))
373 sq_config = 0; 373 sq_config = 0;
374 else 374 else
@@ -610,6 +610,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
610 610
611 DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, 611 DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
612 size_bytes, rdev->r600_blit.vb_used); 612 size_bytes, rdev->r600_blit.vb_used);
613 vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
613 if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { 614 if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
614 max_bytes = 8192; 615 max_bytes = 8192;
615 616
@@ -652,7 +653,6 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
652 vb = r600_nomm_get_vb_ptr(dev); 653 vb = r600_nomm_get_vb_ptr(dev);
653#endif 654#endif
654 } 655 }
655 vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
656 656
657 vb[0] = i2f(dst_x); 657 vb[0] = i2f(dst_x);
658 vb[1] = 0; 658 vb[1] = 0;
@@ -747,7 +747,6 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
747 vb = r600_nomm_get_vb_ptr(dev); 747 vb = r600_nomm_get_vb_ptr(dev);
748 } 748 }
749#endif 749#endif
750 vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
751 750
752 vb[0] = i2f(dst_x / 4); 751 vb[0] = i2f(dst_x / 4);
753 vb[1] = 0; 752 vb[1] = 0;
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 17e42195c63..0d820764f34 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -466,6 +466,23 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
466 for (i = 0; i < pkt->count; i++) { 466 for (i = 0; i < pkt->count; i++) {
467 reg = start_reg + (4 * i); 467 reg = start_reg + (4 * i);
468 switch (reg) { 468 switch (reg) {
469 case SQ_ESGS_RING_BASE:
470 case SQ_GSVS_RING_BASE:
471 case SQ_ESTMP_RING_BASE:
472 case SQ_GSTMP_RING_BASE:
473 case SQ_VSTMP_RING_BASE:
474 case SQ_PSTMP_RING_BASE:
475 case SQ_FBUF_RING_BASE:
476 case SQ_REDUC_RING_BASE:
477 case SX_MEMORY_EXPORT_BASE:
478 r = r600_cs_packet_next_reloc(p, &reloc);
479 if (r) {
480 DRM_ERROR("bad SET_CONFIG_REG "
481 "0x%04X\n", reg);
482 return -EINVAL;
483 }
484 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
485 break;
469 case CP_COHER_BASE: 486 case CP_COHER_BASE:
470 /* use PACKET3_SURFACE_SYNC */ 487 /* use PACKET3_SURFACE_SYNC */
471 return -EINVAL; 488 return -EINVAL;
@@ -487,6 +504,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
487 reg = start_reg + (4 * i); 504 reg = start_reg + (4 * i);
488 switch (reg) { 505 switch (reg) {
489 case DB_DEPTH_BASE: 506 case DB_DEPTH_BASE:
507 case DB_HTILE_DATA_BASE:
490 case CB_COLOR0_BASE: 508 case CB_COLOR0_BASE:
491 case CB_COLOR1_BASE: 509 case CB_COLOR1_BASE:
492 case CB_COLOR2_BASE: 510 case CB_COLOR2_BASE:
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 9b64d47f1f8..27ab428b149 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -119,6 +119,7 @@
119#define DB_DEBUG 0x9830 119#define DB_DEBUG 0x9830
120#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) 120#define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
121#define DB_DEPTH_BASE 0x2800C 121#define DB_DEPTH_BASE 0x2800C
122#define DB_HTILE_DATA_BASE 0x28014
122#define DB_WATERMARKS 0x9838 123#define DB_WATERMARKS 0x9838
123#define DEPTH_FREE(x) ((x) << 0) 124#define DEPTH_FREE(x) ((x) << 0)
124#define DEPTH_FLUSH(x) ((x) << 5) 125#define DEPTH_FLUSH(x) ((x) << 5)
@@ -171,6 +172,14 @@
171#define SQ_STACK_RESOURCE_MGMT_2 0x8c14 172#define SQ_STACK_RESOURCE_MGMT_2 0x8c14
172# define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 173# define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
173# define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 174# define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
175#define SQ_ESGS_RING_BASE 0x8c40
176#define SQ_GSVS_RING_BASE 0x8c48
177#define SQ_ESTMP_RING_BASE 0x8c50
178#define SQ_GSTMP_RING_BASE 0x8c58
179#define SQ_VSTMP_RING_BASE 0x8c60
180#define SQ_PSTMP_RING_BASE 0x8c68
181#define SQ_FBUF_RING_BASE 0x8c70
182#define SQ_REDUC_RING_BASE 0x8c78
174 183
175#define GRBM_CNTL 0x8000 184#define GRBM_CNTL 0x8000
176# define GRBM_READ_TIMEOUT(x) ((x) << 0) 185# define GRBM_READ_TIMEOUT(x) ((x) << 0)
@@ -271,6 +280,10 @@
271#define PCIE_PORT_INDEX 0x0038 280#define PCIE_PORT_INDEX 0x0038
272#define PCIE_PORT_DATA 0x003C 281#define PCIE_PORT_DATA 0x003C
273 282
283#define CHMAP 0x2004
284#define NOOFCHAN_SHIFT 12
285#define NOOFCHAN_MASK 0x00003000
286
274#define RAMCFG 0x2408 287#define RAMCFG 0x2408
275#define NOOFBANK_SHIFT 0 288#define NOOFBANK_SHIFT 0
276#define NOOFBANK_MASK 0x00000001 289#define NOOFBANK_MASK 0x00000001
@@ -352,6 +365,7 @@
352 365
353 366
354#define SX_MISC 0x28350 367#define SX_MISC 0x28350
368#define SX_MEMORY_EXPORT_BASE 0x9010
355#define SX_DEBUG_1 0x9054 369#define SX_DEBUG_1 0x9054
356#define SMX_EVENT_RELEASE (1 << 0) 370#define SMX_EVENT_RELEASE (1 << 0)
357#define ENABLE_NEW_SMX_ADDRESS (1 << 16) 371#define ENABLE_NEW_SMX_ADDRESS (1 << 16)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 5ab35b81c86..224506a2f7b 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -139,6 +139,10 @@ struct radeon_clock {
139 uint32_t default_sclk; 139 uint32_t default_sclk;
140}; 140};
141 141
142/*
143 * Power management
144 */
145int radeon_pm_init(struct radeon_device *rdev);
142 146
143/* 147/*
144 * Fences. 148 * Fences.
@@ -276,6 +280,8 @@ union radeon_gart_table {
276 struct radeon_gart_table_vram vram; 280 struct radeon_gart_table_vram vram;
277}; 281};
278 282
283#define RADEON_GPU_PAGE_SIZE 4096
284
279struct radeon_gart { 285struct radeon_gart {
280 dma_addr_t table_addr; 286 dma_addr_t table_addr;
281 unsigned num_gpu_pages; 287 unsigned num_gpu_pages;
@@ -513,6 +519,7 @@ typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
513 * AGP 519 * AGP
514 */ 520 */
515int radeon_agp_init(struct radeon_device *rdev); 521int radeon_agp_init(struct radeon_device *rdev);
522void radeon_agp_resume(struct radeon_device *rdev);
516void radeon_agp_fini(struct radeon_device *rdev); 523void radeon_agp_fini(struct radeon_device *rdev);
517 524
518 525
@@ -621,7 +628,9 @@ struct radeon_asic {
621 uint64_t dst_offset, 628 uint64_t dst_offset,
622 unsigned num_pages, 629 unsigned num_pages,
623 struct radeon_fence *fence); 630 struct radeon_fence *fence);
631 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
624 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); 632 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
633 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
625 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); 634 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
626 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); 635 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
627 void (*set_clock_gating)(struct radeon_device *rdev, int enable); 636 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
@@ -783,6 +792,7 @@ struct radeon_device {
783 const struct firmware *me_fw; /* all family ME firmware */ 792 const struct firmware *me_fw; /* all family ME firmware */
784 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 793 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
785 struct r600_blit r600_blit; 794 struct r600_blit r600_blit;
795 int msi_enabled; /* msi enabled */
786}; 796};
787 797
788int radeon_device_init(struct radeon_device *rdev, 798int radeon_device_init(struct radeon_device *rdev,
@@ -952,7 +962,9 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
952#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 962#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
953#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 963#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
954#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) 964#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
965#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
955#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 966#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
967#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
956#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 968#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
957#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 969#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
958#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 970#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index 23ea9955ac5..54bf49a6d67 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -237,6 +237,18 @@ int radeon_agp_init(struct radeon_device *rdev)
237#endif 237#endif
238} 238}
239 239
240void radeon_agp_resume(struct radeon_device *rdev)
241{
242#if __OS_HAS_AGP
243 int r;
244 if (rdev->flags & RADEON_IS_AGP) {
245 r = radeon_agp_init(rdev);
246 if (r)
247 dev_warn(rdev->dev, "radeon AGP reinit failed\n");
248 }
249#endif
250}
251
240void radeon_agp_fini(struct radeon_device *rdev) 252void radeon_agp_fini(struct radeon_device *rdev)
241{ 253{
242#if __OS_HAS_AGP 254#if __OS_HAS_AGP
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index c3532c7a6f3..c18fbee387d 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -31,10 +31,13 @@
31/* 31/*
32 * common functions 32 * common functions
33 */ 33 */
34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
34void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
35void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); 36void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
36 37
38uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
37void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock); 39void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
40uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
38void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock); 41void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
39void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); 42void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
40 43
@@ -95,7 +98,9 @@ static struct radeon_asic r100_asic = {
95 .copy_blit = &r100_copy_blit, 98 .copy_blit = &r100_copy_blit,
96 .copy_dma = NULL, 99 .copy_dma = NULL,
97 .copy = &r100_copy_blit, 100 .copy = &r100_copy_blit,
101 .get_engine_clock = &radeon_legacy_get_engine_clock,
98 .set_engine_clock = &radeon_legacy_set_engine_clock, 102 .set_engine_clock = &radeon_legacy_set_engine_clock,
103 .get_memory_clock = NULL,
99 .set_memory_clock = NULL, 104 .set_memory_clock = NULL,
100 .set_pcie_lanes = NULL, 105 .set_pcie_lanes = NULL,
101 .set_clock_gating = &radeon_legacy_set_clock_gating, 106 .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -148,7 +153,9 @@ static struct radeon_asic r300_asic = {
148 .copy_blit = &r100_copy_blit, 153 .copy_blit = &r100_copy_blit,
149 .copy_dma = &r300_copy_dma, 154 .copy_dma = &r300_copy_dma,
150 .copy = &r100_copy_blit, 155 .copy = &r100_copy_blit,
156 .get_engine_clock = &radeon_legacy_get_engine_clock,
151 .set_engine_clock = &radeon_legacy_set_engine_clock, 157 .set_engine_clock = &radeon_legacy_set_engine_clock,
158 .get_memory_clock = NULL,
152 .set_memory_clock = NULL, 159 .set_memory_clock = NULL,
153 .set_pcie_lanes = &rv370_set_pcie_lanes, 160 .set_pcie_lanes = &rv370_set_pcie_lanes,
154 .set_clock_gating = &radeon_legacy_set_clock_gating, 161 .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -185,7 +192,9 @@ static struct radeon_asic r420_asic = {
185 .copy_blit = &r100_copy_blit, 192 .copy_blit = &r100_copy_blit,
186 .copy_dma = &r300_copy_dma, 193 .copy_dma = &r300_copy_dma,
187 .copy = &r100_copy_blit, 194 .copy = &r100_copy_blit,
195 .get_engine_clock = &radeon_atom_get_engine_clock,
188 .set_engine_clock = &radeon_atom_set_engine_clock, 196 .set_engine_clock = &radeon_atom_set_engine_clock,
197 .get_memory_clock = &radeon_atom_get_memory_clock,
189 .set_memory_clock = &radeon_atom_set_memory_clock, 198 .set_memory_clock = &radeon_atom_set_memory_clock,
190 .set_pcie_lanes = &rv370_set_pcie_lanes, 199 .set_pcie_lanes = &rv370_set_pcie_lanes,
191 .set_clock_gating = &radeon_atom_set_clock_gating, 200 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -227,7 +236,9 @@ static struct radeon_asic rs400_asic = {
227 .copy_blit = &r100_copy_blit, 236 .copy_blit = &r100_copy_blit,
228 .copy_dma = &r300_copy_dma, 237 .copy_dma = &r300_copy_dma,
229 .copy = &r100_copy_blit, 238 .copy = &r100_copy_blit,
239 .get_engine_clock = &radeon_legacy_get_engine_clock,
230 .set_engine_clock = &radeon_legacy_set_engine_clock, 240 .set_engine_clock = &radeon_legacy_set_engine_clock,
241 .get_memory_clock = NULL,
231 .set_memory_clock = NULL, 242 .set_memory_clock = NULL,
232 .set_pcie_lanes = NULL, 243 .set_pcie_lanes = NULL,
233 .set_clock_gating = &radeon_legacy_set_clock_gating, 244 .set_clock_gating = &radeon_legacy_set_clock_gating,
@@ -273,7 +284,9 @@ static struct radeon_asic rs600_asic = {
273 .copy_blit = &r100_copy_blit, 284 .copy_blit = &r100_copy_blit,
274 .copy_dma = &r300_copy_dma, 285 .copy_dma = &r300_copy_dma,
275 .copy = &r100_copy_blit, 286 .copy = &r100_copy_blit,
287 .get_engine_clock = &radeon_atom_get_engine_clock,
276 .set_engine_clock = &radeon_atom_set_engine_clock, 288 .set_engine_clock = &radeon_atom_set_engine_clock,
289 .get_memory_clock = &radeon_atom_get_memory_clock,
277 .set_memory_clock = &radeon_atom_set_memory_clock, 290 .set_memory_clock = &radeon_atom_set_memory_clock,
278 .set_pcie_lanes = NULL, 291 .set_pcie_lanes = NULL,
279 .set_clock_gating = &radeon_atom_set_clock_gating, 292 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -312,7 +325,9 @@ static struct radeon_asic rs690_asic = {
312 .copy_blit = &r100_copy_blit, 325 .copy_blit = &r100_copy_blit,
313 .copy_dma = &r300_copy_dma, 326 .copy_dma = &r300_copy_dma,
314 .copy = &r300_copy_dma, 327 .copy = &r300_copy_dma,
328 .get_engine_clock = &radeon_atom_get_engine_clock,
315 .set_engine_clock = &radeon_atom_set_engine_clock, 329 .set_engine_clock = &radeon_atom_set_engine_clock,
330 .get_memory_clock = &radeon_atom_get_memory_clock,
316 .set_memory_clock = &radeon_atom_set_memory_clock, 331 .set_memory_clock = &radeon_atom_set_memory_clock,
317 .set_pcie_lanes = NULL, 332 .set_pcie_lanes = NULL,
318 .set_clock_gating = &radeon_atom_set_clock_gating, 333 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -357,7 +372,9 @@ static struct radeon_asic rv515_asic = {
357 .copy_blit = &r100_copy_blit, 372 .copy_blit = &r100_copy_blit,
358 .copy_dma = &r300_copy_dma, 373 .copy_dma = &r300_copy_dma,
359 .copy = &r100_copy_blit, 374 .copy = &r100_copy_blit,
375 .get_engine_clock = &radeon_atom_get_engine_clock,
360 .set_engine_clock = &radeon_atom_set_engine_clock, 376 .set_engine_clock = &radeon_atom_set_engine_clock,
377 .get_memory_clock = &radeon_atom_get_memory_clock,
361 .set_memory_clock = &radeon_atom_set_memory_clock, 378 .set_memory_clock = &radeon_atom_set_memory_clock,
362 .set_pcie_lanes = &rv370_set_pcie_lanes, 379 .set_pcie_lanes = &rv370_set_pcie_lanes,
363 .set_clock_gating = &radeon_atom_set_clock_gating, 380 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -393,7 +410,9 @@ static struct radeon_asic r520_asic = {
393 .copy_blit = &r100_copy_blit, 410 .copy_blit = &r100_copy_blit,
394 .copy_dma = &r300_copy_dma, 411 .copy_dma = &r300_copy_dma,
395 .copy = &r100_copy_blit, 412 .copy = &r100_copy_blit,
413 .get_engine_clock = &radeon_atom_get_engine_clock,
396 .set_engine_clock = &radeon_atom_set_engine_clock, 414 .set_engine_clock = &radeon_atom_set_engine_clock,
415 .get_memory_clock = &radeon_atom_get_memory_clock,
397 .set_memory_clock = &radeon_atom_set_memory_clock, 416 .set_memory_clock = &radeon_atom_set_memory_clock,
398 .set_pcie_lanes = &rv370_set_pcie_lanes, 417 .set_pcie_lanes = &rv370_set_pcie_lanes,
399 .set_clock_gating = &radeon_atom_set_clock_gating, 418 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -456,7 +475,9 @@ static struct radeon_asic r600_asic = {
456 .copy_blit = &r600_copy_blit, 475 .copy_blit = &r600_copy_blit,
457 .copy_dma = &r600_copy_blit, 476 .copy_dma = &r600_copy_blit,
458 .copy = &r600_copy_blit, 477 .copy = &r600_copy_blit,
478 .get_engine_clock = &radeon_atom_get_engine_clock,
459 .set_engine_clock = &radeon_atom_set_engine_clock, 479 .set_engine_clock = &radeon_atom_set_engine_clock,
480 .get_memory_clock = &radeon_atom_get_memory_clock,
460 .set_memory_clock = &radeon_atom_set_memory_clock, 481 .set_memory_clock = &radeon_atom_set_memory_clock,
461 .set_pcie_lanes = NULL, 482 .set_pcie_lanes = NULL,
462 .set_clock_gating = &radeon_atom_set_clock_gating, 483 .set_clock_gating = &radeon_atom_set_clock_gating,
@@ -493,7 +514,9 @@ static struct radeon_asic rv770_asic = {
493 .copy_blit = &r600_copy_blit, 514 .copy_blit = &r600_copy_blit,
494 .copy_dma = &r600_copy_blit, 515 .copy_dma = &r600_copy_blit,
495 .copy = &r600_copy_blit, 516 .copy = &r600_copy_blit,
517 .get_engine_clock = &radeon_atom_get_engine_clock,
496 .set_engine_clock = &radeon_atom_set_engine_clock, 518 .set_engine_clock = &radeon_atom_set_engine_clock,
519 .get_memory_clock = &radeon_atom_get_memory_clock,
497 .set_memory_clock = &radeon_atom_set_memory_clock, 520 .set_memory_clock = &radeon_atom_set_memory_clock,
498 .set_pcie_lanes = NULL, 521 .set_pcie_lanes = NULL,
499 .set_clock_gating = &radeon_atom_set_clock_gating, 522 .set_clock_gating = &radeon_atom_set_clock_gating,
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 5b6c08cee40..2ed88a82093 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -46,7 +46,8 @@ radeon_add_atom_connector(struct drm_device *dev,
46 uint32_t supported_device, 46 uint32_t supported_device,
47 int connector_type, 47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus, 48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info); 49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id);
50 51
51/* from radeon_legacy_encoder.c */ 52/* from radeon_legacy_encoder.c */
52extern void 53extern void
@@ -193,6 +194,23 @@ const int supported_devices_connector_convert[] = {
193 DRM_MODE_CONNECTOR_DisplayPort 194 DRM_MODE_CONNECTOR_DisplayPort
194}; 195};
195 196
197const uint16_t supported_devices_connector_object_id_convert[] = {
198 CONNECTOR_OBJECT_ID_NONE,
199 CONNECTOR_OBJECT_ID_VGA,
200 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
201 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
202 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
203 CONNECTOR_OBJECT_ID_COMPOSITE,
204 CONNECTOR_OBJECT_ID_SVIDEO,
205 CONNECTOR_OBJECT_ID_LVDS,
206 CONNECTOR_OBJECT_ID_9PIN_DIN,
207 CONNECTOR_OBJECT_ID_9PIN_DIN,
208 CONNECTOR_OBJECT_ID_DISPLAYPORT,
209 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
210 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
211 CONNECTOR_OBJECT_ID_SVIDEO
212};
213
196const int object_connector_convert[] = { 214const int object_connector_convert[] = {
197 DRM_MODE_CONNECTOR_Unknown, 215 DRM_MODE_CONNECTOR_Unknown,
198 DRM_MODE_CONNECTOR_DVII, 216 DRM_MODE_CONNECTOR_DVII,
@@ -229,7 +247,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
229 ATOM_OBJECT_HEADER *obj_header; 247 ATOM_OBJECT_HEADER *obj_header;
230 int i, j, path_size, device_support; 248 int i, j, path_size, device_support;
231 int connector_type; 249 int connector_type;
232 uint16_t igp_lane_info, conn_id; 250 uint16_t igp_lane_info, conn_id, connector_object_id;
233 bool linkb; 251 bool linkb;
234 struct radeon_i2c_bus_rec ddc_bus; 252 struct radeon_i2c_bus_rec ddc_bus;
235 253
@@ -277,7 +295,8 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
277 ATOM_DEVICE_CV_SUPPORT) 295 ATOM_DEVICE_CV_SUPPORT)
278 continue; 296 continue;
279 297
280 if ((rdev->family == CHIP_RS780) && 298 /* IGP chips */
299 if ((rdev->flags & RADEON_IS_IGP) &&
281 (con_obj_id == 300 (con_obj_id ==
282 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) { 301 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
283 uint16_t igp_offset = 0; 302 uint16_t igp_offset = 0;
@@ -311,6 +330,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
311 connector_type = 330 connector_type =
312 object_connector_convert 331 object_connector_convert
313 [ct]; 332 [ct];
333 connector_object_id = ct;
314 igp_lane_info = 334 igp_lane_info =
315 slot_config & 0xffff; 335 slot_config & 0xffff;
316 } else 336 } else
@@ -321,6 +341,7 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
321 igp_lane_info = 0; 341 igp_lane_info = 0;
322 connector_type = 342 connector_type =
323 object_connector_convert[con_obj_id]; 343 object_connector_convert[con_obj_id];
344 connector_object_id = con_obj_id;
324 } 345 }
325 346
326 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 347 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
@@ -425,7 +446,8 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
425 le16_to_cpu(path-> 446 le16_to_cpu(path->
426 usDeviceTag), 447 usDeviceTag),
427 connector_type, &ddc_bus, 448 connector_type, &ddc_bus,
428 linkb, igp_lane_info); 449 linkb, igp_lane_info,
450 connector_object_id);
429 451
430 } 452 }
431 } 453 }
@@ -435,6 +457,45 @@ bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
435 return true; 457 return true;
436} 458}
437 459
460static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
461 int connector_type,
462 uint16_t devices)
463{
464 struct radeon_device *rdev = dev->dev_private;
465
466 if (rdev->flags & RADEON_IS_IGP) {
467 return supported_devices_connector_object_id_convert
468 [connector_type];
469 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
470 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
471 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
472 struct radeon_mode_info *mode_info = &rdev->mode_info;
473 struct atom_context *ctx = mode_info->atom_context;
474 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
475 uint16_t size, data_offset;
476 uint8_t frev, crev;
477 ATOM_XTMDS_INFO *xtmds;
478
479 atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset);
480 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
481
482 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
483 if (connector_type == DRM_MODE_CONNECTOR_DVII)
484 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
485 else
486 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
487 } else {
488 if (connector_type == DRM_MODE_CONNECTOR_DVII)
489 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
490 else
491 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
492 }
493 } else {
494 return supported_devices_connector_object_id_convert
495 [connector_type];
496 }
497}
498
438struct bios_connector { 499struct bios_connector {
439 bool valid; 500 bool valid;
440 uint16_t line_mux; 501 uint16_t line_mux;
@@ -593,14 +654,20 @@ bool radeon_get_atom_connector_info_from_supported_devices_table(struct
593 654
594 /* add the connectors */ 655 /* add the connectors */
595 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) { 656 for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
596 if (bios_connectors[i].valid) 657 if (bios_connectors[i].valid) {
658 uint16_t connector_object_id =
659 atombios_get_connector_object_id(dev,
660 bios_connectors[i].connector_type,
661 bios_connectors[i].devices);
597 radeon_add_atom_connector(dev, 662 radeon_add_atom_connector(dev,
598 bios_connectors[i].line_mux, 663 bios_connectors[i].line_mux,
599 bios_connectors[i].devices, 664 bios_connectors[i].devices,
600 bios_connectors[i]. 665 bios_connectors[i].
601 connector_type, 666 connector_type,
602 &bios_connectors[i].ddc_bus, 667 &bios_connectors[i].ddc_bus,
603 false, 0); 668 false, 0,
669 connector_object_id);
670 }
604 } 671 }
605 672
606 radeon_link_encoder_connector(dev); 673 radeon_link_encoder_connector(dev);
@@ -641,8 +708,12 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
641 le16_to_cpu(firmware_info->info.usReferenceClock); 708 le16_to_cpu(firmware_info->info.usReferenceClock);
642 p1pll->reference_div = 0; 709 p1pll->reference_div = 0;
643 710
644 p1pll->pll_out_min = 711 if (crev < 2)
645 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output); 712 p1pll->pll_out_min =
713 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
714 else
715 p1pll->pll_out_min =
716 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
646 p1pll->pll_out_max = 717 p1pll->pll_out_max =
647 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 718 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
648 719
@@ -651,6 +722,16 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
651 p1pll->pll_out_min = 64800; 722 p1pll->pll_out_min = 64800;
652 else 723 else
653 p1pll->pll_out_min = 20000; 724 p1pll->pll_out_min = 20000;
725 } else if (p1pll->pll_out_min > 64800) {
726 /* Limiting the pll output range is a good thing generally as
727 * it limits the number of possible pll combinations for a given
728 * frequency presumably to the ones that work best on each card.
729 * However, certain duallink DVI monitors seem to like
730 * pll combinations that would be limited by this at least on
731 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
732 * family.
733 */
734 p1pll->pll_out_min = 64800;
654 } 735 }
655 736
656 p1pll->pll_in_min = 737 p1pll->pll_in_min =
@@ -767,6 +848,46 @@ bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
767 return false; 848 return false;
768} 849}
769 850
851static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
852 radeon_encoder
853 *encoder,
854 int id)
855{
856 struct drm_device *dev = encoder->base.dev;
857 struct radeon_device *rdev = dev->dev_private;
858 struct radeon_mode_info *mode_info = &rdev->mode_info;
859 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
860 uint16_t data_offset;
861 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
862 uint8_t frev, crev;
863 struct radeon_atom_ss *ss = NULL;
864
865 if (id > ATOM_MAX_SS_ENTRY)
866 return NULL;
867
868 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
869 &crev, &data_offset);
870
871 ss_info =
872 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
873
874 if (ss_info) {
875 ss =
876 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
877
878 if (!ss)
879 return NULL;
880
881 ss->percentage = le16_to_cpu(ss_info->asSS_Info[id].usSpreadSpectrumPercentage);
882 ss->type = ss_info->asSS_Info[id].ucSpreadSpectrumType;
883 ss->step = ss_info->asSS_Info[id].ucSS_Step;
884 ss->delay = ss_info->asSS_Info[id].ucSS_Delay;
885 ss->range = ss_info->asSS_Info[id].ucSS_Range;
886 ss->refdiv = ss_info->asSS_Info[id].ucRecommendedRef_Div;
887 }
888 return ss;
889}
890
770union lvds_info { 891union lvds_info {
771 struct _ATOM_LVDS_INFO info; 892 struct _ATOM_LVDS_INFO info;
772 struct _ATOM_LVDS_INFO_V12 info_12; 893 struct _ATOM_LVDS_INFO_V12 info_12;
@@ -798,27 +919,31 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
798 if (!lvds) 919 if (!lvds)
799 return NULL; 920 return NULL;
800 921
801 lvds->native_mode.dotclock = 922 lvds->native_mode.clock =
802 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10; 923 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
803 lvds->native_mode.panel_xres = 924 lvds->native_mode.hdisplay =
804 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive); 925 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
805 lvds->native_mode.panel_yres = 926 lvds->native_mode.vdisplay =
806 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive); 927 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
807 lvds->native_mode.hblank = 928 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
808 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time); 929 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
809 lvds->native_mode.hoverplus = 930 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
810 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset); 931 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
811 lvds->native_mode.hsync_width = 932 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
812 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth); 933 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
813 lvds->native_mode.vblank = 934 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
814 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time); 935 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
815 lvds->native_mode.voverplus = 936 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
816 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset); 937 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
817 lvds->native_mode.vsync_width = 938 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
818 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth); 939 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
819 lvds->panel_pwr_delay = 940 lvds->panel_pwr_delay =
820 le16_to_cpu(lvds_info->info.usOffDelayInMs); 941 le16_to_cpu(lvds_info->info.usOffDelayInMs);
821 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc; 942 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
943 /* set crtc values */
944 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
945
946 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
822 947
823 encoder->native_mode = lvds->native_mode; 948 encoder->native_mode = lvds->native_mode;
824 } 949 }
@@ -857,8 +982,7 @@ radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
857} 982}
858 983
859bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, 984bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
860 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, 985 struct drm_display_mode *mode)
861 int32_t *pixel_clock)
862{ 986{
863 struct radeon_mode_info *mode_info = &rdev->mode_info; 987 struct radeon_mode_info *mode_info = &rdev->mode_info;
864 ATOM_ANALOG_TV_INFO *tv_info; 988 ATOM_ANALOG_TV_INFO *tv_info;
@@ -866,7 +990,7 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
866 ATOM_DTD_FORMAT *dtd_timings; 990 ATOM_DTD_FORMAT *dtd_timings;
867 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info); 991 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
868 u8 frev, crev; 992 u8 frev, crev;
869 uint16_t data_offset; 993 u16 data_offset, misc;
870 994
871 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset); 995 atom_parse_data_header(mode_info->atom_context, data_index, NULL, &frev, &crev, &data_offset);
872 996
@@ -876,28 +1000,37 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
876 if (index > MAX_SUPPORTED_TV_TIMING) 1000 if (index > MAX_SUPPORTED_TV_TIMING)
877 return false; 1001 return false;
878 1002
879 crtc_timing->usH_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total); 1003 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
880 crtc_timing->usH_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp); 1004 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
881 crtc_timing->usH_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart); 1005 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
882 crtc_timing->usH_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth); 1006 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
883 1007 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
884 crtc_timing->usV_Total = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total); 1008
885 crtc_timing->usV_Disp = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp); 1009 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
886 crtc_timing->usV_SyncStart = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart); 1010 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
887 crtc_timing->usV_SyncWidth = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth); 1011 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
888 1012 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
889 crtc_timing->susModeMiscInfo = tv_info->aModeTimings[index].susModeMiscInfo; 1013 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
890 1014
891 crtc_timing->ucOverscanRight = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanRight); 1015 mode->flags = 0;
892 crtc_timing->ucOverscanLeft = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanLeft); 1016 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
893 crtc_timing->ucOverscanBottom = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanBottom); 1017 if (misc & ATOM_VSYNC_POLARITY)
894 crtc_timing->ucOverscanTop = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_OverscanTop); 1018 mode->flags |= DRM_MODE_FLAG_NVSYNC;
895 *pixel_clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10; 1019 if (misc & ATOM_HSYNC_POLARITY)
1020 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1021 if (misc & ATOM_COMPOSITESYNC)
1022 mode->flags |= DRM_MODE_FLAG_CSYNC;
1023 if (misc & ATOM_INTERLACE)
1024 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1025 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1026 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1027
1028 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
896 1029
897 if (index == 1) { 1030 if (index == 1) {
898 /* PAL timings appear to have wrong values for totals */ 1031 /* PAL timings appear to have wrong values for totals */
899 crtc_timing->usH_Total -= 1; 1032 mode->crtc_htotal -= 1;
900 crtc_timing->usV_Total -= 1; 1033 mode->crtc_vtotal -= 1;
901 } 1034 }
902 break; 1035 break;
903 case 2: 1036 case 2:
@@ -906,17 +1039,36 @@ bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
906 return false; 1039 return false;
907 1040
908 dtd_timings = &tv_info_v1_2->aModeTimings[index]; 1041 dtd_timings = &tv_info_v1_2->aModeTimings[index];
909 crtc_timing->usH_Total = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHBlanking_Time); 1042 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
910 crtc_timing->usH_Disp = le16_to_cpu(dtd_timings->usHActive); 1043 le16_to_cpu(dtd_timings->usHBlanking_Time);
911 crtc_timing->usH_SyncStart = le16_to_cpu(dtd_timings->usHActive) + le16_to_cpu(dtd_timings->usHSyncOffset); 1044 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
912 crtc_timing->usH_SyncWidth = le16_to_cpu(dtd_timings->usHSyncWidth); 1045 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
913 crtc_timing->usV_Total = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVBlanking_Time); 1046 le16_to_cpu(dtd_timings->usHSyncOffset);
914 crtc_timing->usV_Disp = le16_to_cpu(dtd_timings->usVActive); 1047 mode->crtc_hsync_end = mode->crtc_hsync_start +
915 crtc_timing->usV_SyncStart = le16_to_cpu(dtd_timings->usVActive) + le16_to_cpu(dtd_timings->usVSyncOffset); 1048 le16_to_cpu(dtd_timings->usHSyncWidth);
916 crtc_timing->usV_SyncWidth = le16_to_cpu(dtd_timings->usVSyncWidth); 1049
917 1050 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
918 crtc_timing->susModeMiscInfo.usAccess = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess); 1051 le16_to_cpu(dtd_timings->usVBlanking_Time);
919 *pixel_clock = le16_to_cpu(dtd_timings->usPixClk) * 10; 1052 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1053 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1054 le16_to_cpu(dtd_timings->usVSyncOffset);
1055 mode->crtc_vsync_end = mode->crtc_vsync_start +
1056 le16_to_cpu(dtd_timings->usVSyncWidth);
1057
1058 mode->flags = 0;
1059 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1060 if (misc & ATOM_VSYNC_POLARITY)
1061 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1062 if (misc & ATOM_HSYNC_POLARITY)
1063 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1064 if (misc & ATOM_COMPOSITESYNC)
1065 mode->flags |= DRM_MODE_FLAG_CSYNC;
1066 if (misc & ATOM_INTERLACE)
1067 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1068 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1069 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1070
1071 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
920 break; 1072 break;
921 } 1073 }
922 return true; 1074 return true;
@@ -981,6 +1133,24 @@ void radeon_atom_static_pwrmgt_setup(struct radeon_device *rdev, int enable)
981 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 1133 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
982} 1134}
983 1135
1136uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1137{
1138 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1139 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1140
1141 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1142 return args.ulReturnEngineClock;
1143}
1144
1145uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1146{
1147 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1148 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1149
1150 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1151 return args.ulReturnMemoryClock;
1152}
1153
984void radeon_atom_set_engine_clock(struct radeon_device *rdev, 1154void radeon_atom_set_engine_clock(struct radeon_device *rdev,
985 uint32_t eng_clock) 1155 uint32_t eng_clock)
986{ 1156{
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c
index 2e938f7496f..10bd50a7db8 100644
--- a/drivers/gpu/drm/radeon/radeon_benchmark.c
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -63,7 +63,7 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
63 if (r) { 63 if (r) {
64 goto out_cleanup; 64 goto out_cleanup;
65 } 65 }
66 r = radeon_copy_dma(rdev, saddr, daddr, size / 4096, fence); 66 r = radeon_copy_dma(rdev, saddr, daddr, size / RADEON_GPU_PAGE_SIZE, fence);
67 if (r) { 67 if (r) {
68 goto out_cleanup; 68 goto out_cleanup;
69 } 69 }
@@ -88,7 +88,7 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
88 if (r) { 88 if (r) {
89 goto out_cleanup; 89 goto out_cleanup;
90 } 90 }
91 r = radeon_copy_blit(rdev, saddr, daddr, size / 4096, fence); 91 r = radeon_copy_blit(rdev, saddr, daddr, size / RADEON_GPU_PAGE_SIZE, fence);
92 if (r) { 92 if (r) {
93 goto out_cleanup; 93 goto out_cleanup;
94 } 94 }
diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c
index 34a9b911951..906921740c6 100644
--- a/drivers/gpu/drm/radeon/radeon_bios.c
+++ b/drivers/gpu/drm/radeon/radeon_bios.c
@@ -50,19 +50,16 @@ static bool igp_read_bios_from_vram(struct radeon_device *rdev)
50 vram_base = drm_get_resource_start(rdev->ddev, 0); 50 vram_base = drm_get_resource_start(rdev->ddev, 0);
51 bios = ioremap(vram_base, size); 51 bios = ioremap(vram_base, size);
52 if (!bios) { 52 if (!bios) {
53 DRM_ERROR("Unable to mmap vram\n");
54 return false; 53 return false;
55 } 54 }
56 55
57 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) { 56 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
58 iounmap(bios); 57 iounmap(bios);
59 DRM_ERROR("bad rom signature\n");
60 return false; 58 return false;
61 } 59 }
62 rdev->bios = kmalloc(size, GFP_KERNEL); 60 rdev->bios = kmalloc(size, GFP_KERNEL);
63 if (rdev->bios == NULL) { 61 if (rdev->bios == NULL) {
64 iounmap(bios); 62 iounmap(bios);
65 DRM_ERROR("kmalloc failed\n");
66 return false; 63 return false;
67 } 64 }
68 memcpy(rdev->bios, bios, size); 65 memcpy(rdev->bios, bios, size);
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index f5c32a766b1..a8135416762 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -32,7 +32,7 @@
32#include "atom.h" 32#include "atom.h"
33 33
34/* 10 khz */ 34/* 10 khz */
35static uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev) 35uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
36{ 36{
37 struct radeon_pll *spll = &rdev->clock.spll; 37 struct radeon_pll *spll = &rdev->clock.spll;
38 uint32_t fb_div, ref_div, post_div, sclk; 38 uint32_t fb_div, ref_div, post_div, sclk;
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 748265a105b..5253cbf6db1 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -49,7 +49,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
49 uint32_t connector_id, 49 uint32_t connector_id,
50 uint32_t supported_device, 50 uint32_t supported_device,
51 int connector_type, 51 int connector_type,
52 struct radeon_i2c_bus_rec *i2c_bus); 52 struct radeon_i2c_bus_rec *i2c_bus,
53 uint16_t connector_object_id);
53 54
54/* from radeon_legacy_encoder.c */ 55/* from radeon_legacy_encoder.c */
55extern void 56extern void
@@ -808,25 +809,25 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
808 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 809 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;
809 810
810 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 811 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)
811 lvds->native_mode.panel_yres = 812 lvds->native_mode.vdisplay =
812 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 813 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>
813 RADEON_VERT_PANEL_SHIFT) + 1; 814 RADEON_VERT_PANEL_SHIFT) + 1;
814 else 815 else
815 lvds->native_mode.panel_yres = 816 lvds->native_mode.vdisplay =
816 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 817 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;
817 818
818 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 819 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)
819 lvds->native_mode.panel_xres = 820 lvds->native_mode.hdisplay =
820 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 821 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>
821 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 822 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;
822 else 823 else
823 lvds->native_mode.panel_xres = 824 lvds->native_mode.hdisplay =
824 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 825 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;
825 826
826 if ((lvds->native_mode.panel_xres < 640) || 827 if ((lvds->native_mode.hdisplay < 640) ||
827 (lvds->native_mode.panel_yres < 480)) { 828 (lvds->native_mode.vdisplay < 480)) {
828 lvds->native_mode.panel_xres = 640; 829 lvds->native_mode.hdisplay = 640;
829 lvds->native_mode.panel_yres = 480; 830 lvds->native_mode.vdisplay = 480;
830 } 831 }
831 832
832 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 833 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;
@@ -846,8 +847,8 @@ static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct
846 lvds->panel_vcc_delay = 200; 847 lvds->panel_vcc_delay = 200;
847 848
848 DRM_INFO("Panel info derived from registers\n"); 849 DRM_INFO("Panel info derived from registers\n");
849 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres, 850 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
850 lvds->native_mode.panel_yres); 851 lvds->native_mode.vdisplay);
851 852
852 return lvds; 853 return lvds;
853} 854}
@@ -882,11 +883,11 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
882 883
883 DRM_INFO("Panel ID String: %s\n", stmp); 884 DRM_INFO("Panel ID String: %s\n", stmp);
884 885
885 lvds->native_mode.panel_xres = RBIOS16(lcd_info + 0x19); 886 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);
886 lvds->native_mode.panel_yres = RBIOS16(lcd_info + 0x1b); 887 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);
887 888
888 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.panel_xres, 889 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,
889 lvds->native_mode.panel_yres); 890 lvds->native_mode.vdisplay);
890 891
891 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 892 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
892 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0) 893 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0)
@@ -944,27 +945,25 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
944 if (tmp == 0) 945 if (tmp == 0)
945 break; 946 break;
946 947
947 if ((RBIOS16(tmp) == lvds->native_mode.panel_xres) && 948 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&
948 (RBIOS16(tmp + 2) == 949 (RBIOS16(tmp + 2) ==
949 lvds->native_mode.panel_yres)) { 950 lvds->native_mode.vdisplay)) {
950 lvds->native_mode.hblank = 951 lvds->native_mode.htotal = RBIOS16(tmp + 17) * 8;
951 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 952 lvds->native_mode.hsync_start = RBIOS16(tmp + 21) * 8;
952 lvds->native_mode.hoverplus = 953 lvds->native_mode.hsync_end = (RBIOS8(tmp + 23) +
953 (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 954 RBIOS16(tmp + 21)) * 8;
954 1) * 8; 955
955 lvds->native_mode.hsync_width = 956 lvds->native_mode.vtotal = RBIOS16(tmp + 24);
956 RBIOS8(tmp + 23) * 8; 957 lvds->native_mode.vsync_start = RBIOS16(tmp + 28) & 0x7ff;
957 958 lvds->native_mode.vsync_end =
958 lvds->native_mode.vblank = (RBIOS16(tmp + 24) - 959 ((RBIOS16(tmp + 28) & 0xf800) >> 11) +
959 RBIOS16(tmp + 26)); 960 (RBIOS16(tmp + 28) & 0x7ff);
960 lvds->native_mode.voverplus = 961
961 ((RBIOS16(tmp + 28) & 0x7ff) - 962 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;
962 RBIOS16(tmp + 26));
963 lvds->native_mode.vsync_width =
964 ((RBIOS16(tmp + 28) & 0xf800) >> 11);
965 lvds->native_mode.dotclock =
966 RBIOS16(tmp + 9) * 10;
967 lvds->native_mode.flags = 0; 963 lvds->native_mode.flags = 0;
964 /* set crtc values */
965 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
966
968 } 967 }
969 } 968 }
970 } else { 969 } else {
@@ -1178,7 +1177,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1178 radeon_add_legacy_connector(dev, 0, 1177 radeon_add_legacy_connector(dev, 0,
1179 ATOM_DEVICE_CRT1_SUPPORT, 1178 ATOM_DEVICE_CRT1_SUPPORT,
1180 DRM_MODE_CONNECTOR_VGA, 1179 DRM_MODE_CONNECTOR_VGA,
1181 &ddc_i2c); 1180 &ddc_i2c,
1181 CONNECTOR_OBJECT_ID_VGA);
1182 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1182 } else if (rdev->flags & RADEON_IS_MOBILITY) {
1183 /* LVDS */ 1183 /* LVDS */
1184 ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK); 1184 ddc_i2c = combios_setup_i2c_bus(RADEON_LCD_GPIO_MASK);
@@ -1190,7 +1190,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1190 radeon_add_legacy_connector(dev, 0, 1190 radeon_add_legacy_connector(dev, 0,
1191 ATOM_DEVICE_LCD1_SUPPORT, 1191 ATOM_DEVICE_LCD1_SUPPORT,
1192 DRM_MODE_CONNECTOR_LVDS, 1192 DRM_MODE_CONNECTOR_LVDS,
1193 &ddc_i2c); 1193 &ddc_i2c,
1194 CONNECTOR_OBJECT_ID_LVDS);
1194 1195
1195 /* VGA - primary dac */ 1196 /* VGA - primary dac */
1196 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 1197 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
@@ -1202,7 +1203,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1202 radeon_add_legacy_connector(dev, 1, 1203 radeon_add_legacy_connector(dev, 1,
1203 ATOM_DEVICE_CRT1_SUPPORT, 1204 ATOM_DEVICE_CRT1_SUPPORT,
1204 DRM_MODE_CONNECTOR_VGA, 1205 DRM_MODE_CONNECTOR_VGA,
1205 &ddc_i2c); 1206 &ddc_i2c,
1207 CONNECTOR_OBJECT_ID_VGA);
1206 } else { 1208 } else {
1207 /* DVI-I - tv dac, int tmds */ 1209 /* DVI-I - tv dac, int tmds */
1208 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 1210 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
@@ -1220,7 +1222,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1220 ATOM_DEVICE_DFP1_SUPPORT | 1222 ATOM_DEVICE_DFP1_SUPPORT |
1221 ATOM_DEVICE_CRT2_SUPPORT, 1223 ATOM_DEVICE_CRT2_SUPPORT,
1222 DRM_MODE_CONNECTOR_DVII, 1224 DRM_MODE_CONNECTOR_DVII,
1223 &ddc_i2c); 1225 &ddc_i2c,
1226 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
1224 1227
1225 /* VGA - primary dac */ 1228 /* VGA - primary dac */
1226 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 1229 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
@@ -1232,7 +1235,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1232 radeon_add_legacy_connector(dev, 1, 1235 radeon_add_legacy_connector(dev, 1,
1233 ATOM_DEVICE_CRT1_SUPPORT, 1236 ATOM_DEVICE_CRT1_SUPPORT,
1234 DRM_MODE_CONNECTOR_VGA, 1237 DRM_MODE_CONNECTOR_VGA,
1235 &ddc_i2c); 1238 &ddc_i2c,
1239 CONNECTOR_OBJECT_ID_VGA);
1236 } 1240 }
1237 1241
1238 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1242 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {
@@ -1245,7 +1249,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1245 radeon_add_legacy_connector(dev, 2, 1249 radeon_add_legacy_connector(dev, 2,
1246 ATOM_DEVICE_TV1_SUPPORT, 1250 ATOM_DEVICE_TV1_SUPPORT,
1247 DRM_MODE_CONNECTOR_SVIDEO, 1251 DRM_MODE_CONNECTOR_SVIDEO,
1248 &ddc_i2c); 1252 &ddc_i2c,
1253 CONNECTOR_OBJECT_ID_SVIDEO);
1249 } 1254 }
1250 break; 1255 break;
1251 case CT_IBOOK: 1256 case CT_IBOOK:
@@ -1259,7 +1264,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1259 0), 1264 0),
1260 ATOM_DEVICE_LCD1_SUPPORT); 1265 ATOM_DEVICE_LCD1_SUPPORT);
1261 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1266 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1262 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c); 1267 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1268 CONNECTOR_OBJECT_ID_LVDS);
1263 /* VGA - TV DAC */ 1269 /* VGA - TV DAC */
1264 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 1270 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1265 radeon_add_legacy_encoder(dev, 1271 radeon_add_legacy_encoder(dev,
@@ -1268,7 +1274,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1268 2), 1274 2),
1269 ATOM_DEVICE_CRT2_SUPPORT); 1275 ATOM_DEVICE_CRT2_SUPPORT);
1270 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1276 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1271 DRM_MODE_CONNECTOR_VGA, &ddc_i2c); 1277 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1278 CONNECTOR_OBJECT_ID_VGA);
1272 /* TV - TV DAC */ 1279 /* TV - TV DAC */
1273 radeon_add_legacy_encoder(dev, 1280 radeon_add_legacy_encoder(dev,
1274 radeon_get_encoder_id(dev, 1281 radeon_get_encoder_id(dev,
@@ -1277,7 +1284,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1277 ATOM_DEVICE_TV1_SUPPORT); 1284 ATOM_DEVICE_TV1_SUPPORT);
1278 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1285 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1279 DRM_MODE_CONNECTOR_SVIDEO, 1286 DRM_MODE_CONNECTOR_SVIDEO,
1280 &ddc_i2c); 1287 &ddc_i2c,
1288 CONNECTOR_OBJECT_ID_SVIDEO);
1281 break; 1289 break;
1282 case CT_POWERBOOK_EXTERNAL: 1290 case CT_POWERBOOK_EXTERNAL:
1283 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1291 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",
@@ -1290,7 +1298,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1290 0), 1298 0),
1291 ATOM_DEVICE_LCD1_SUPPORT); 1299 ATOM_DEVICE_LCD1_SUPPORT);
1292 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1300 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1293 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c); 1301 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1302 CONNECTOR_OBJECT_ID_LVDS);
1294 /* DVI-I - primary dac, ext tmds */ 1303 /* DVI-I - primary dac, ext tmds */
1295 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 1304 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1296 radeon_add_legacy_encoder(dev, 1305 radeon_add_legacy_encoder(dev,
@@ -1303,10 +1312,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1303 ATOM_DEVICE_CRT1_SUPPORT, 1312 ATOM_DEVICE_CRT1_SUPPORT,
1304 1), 1313 1),
1305 ATOM_DEVICE_CRT1_SUPPORT); 1314 ATOM_DEVICE_CRT1_SUPPORT);
1315 /* XXX some are SL */
1306 radeon_add_legacy_connector(dev, 1, 1316 radeon_add_legacy_connector(dev, 1,
1307 ATOM_DEVICE_DFP2_SUPPORT | 1317 ATOM_DEVICE_DFP2_SUPPORT |
1308 ATOM_DEVICE_CRT1_SUPPORT, 1318 ATOM_DEVICE_CRT1_SUPPORT,
1309 DRM_MODE_CONNECTOR_DVII, &ddc_i2c); 1319 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1320 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I);
1310 /* TV - TV DAC */ 1321 /* TV - TV DAC */
1311 radeon_add_legacy_encoder(dev, 1322 radeon_add_legacy_encoder(dev,
1312 radeon_get_encoder_id(dev, 1323 radeon_get_encoder_id(dev,
@@ -1315,7 +1326,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1315 ATOM_DEVICE_TV1_SUPPORT); 1326 ATOM_DEVICE_TV1_SUPPORT);
1316 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1327 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1317 DRM_MODE_CONNECTOR_SVIDEO, 1328 DRM_MODE_CONNECTOR_SVIDEO,
1318 &ddc_i2c); 1329 &ddc_i2c,
1330 CONNECTOR_OBJECT_ID_SVIDEO);
1319 break; 1331 break;
1320 case CT_POWERBOOK_INTERNAL: 1332 case CT_POWERBOOK_INTERNAL:
1321 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1333 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",
@@ -1328,7 +1340,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1328 0), 1340 0),
1329 ATOM_DEVICE_LCD1_SUPPORT); 1341 ATOM_DEVICE_LCD1_SUPPORT);
1330 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1342 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1331 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c); 1343 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1344 CONNECTOR_OBJECT_ID_LVDS);
1332 /* DVI-I - primary dac, int tmds */ 1345 /* DVI-I - primary dac, int tmds */
1333 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 1346 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1334 radeon_add_legacy_encoder(dev, 1347 radeon_add_legacy_encoder(dev,
@@ -1344,7 +1357,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1344 radeon_add_legacy_connector(dev, 1, 1357 radeon_add_legacy_connector(dev, 1,
1345 ATOM_DEVICE_DFP1_SUPPORT | 1358 ATOM_DEVICE_DFP1_SUPPORT |
1346 ATOM_DEVICE_CRT1_SUPPORT, 1359 ATOM_DEVICE_CRT1_SUPPORT,
1347 DRM_MODE_CONNECTOR_DVII, &ddc_i2c); 1360 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1361 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
1348 /* TV - TV DAC */ 1362 /* TV - TV DAC */
1349 radeon_add_legacy_encoder(dev, 1363 radeon_add_legacy_encoder(dev,
1350 radeon_get_encoder_id(dev, 1364 radeon_get_encoder_id(dev,
@@ -1353,7 +1367,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1353 ATOM_DEVICE_TV1_SUPPORT); 1367 ATOM_DEVICE_TV1_SUPPORT);
1354 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1368 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1355 DRM_MODE_CONNECTOR_SVIDEO, 1369 DRM_MODE_CONNECTOR_SVIDEO,
1356 &ddc_i2c); 1370 &ddc_i2c,
1371 CONNECTOR_OBJECT_ID_SVIDEO);
1357 break; 1372 break;
1358 case CT_POWERBOOK_VGA: 1373 case CT_POWERBOOK_VGA:
1359 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1374 DRM_INFO("Connector Table: %d (powerbook vga)\n",
@@ -1366,7 +1381,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1366 0), 1381 0),
1367 ATOM_DEVICE_LCD1_SUPPORT); 1382 ATOM_DEVICE_LCD1_SUPPORT);
1368 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1383 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,
1369 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c); 1384 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,
1385 CONNECTOR_OBJECT_ID_LVDS);
1370 /* VGA - primary dac */ 1386 /* VGA - primary dac */
1371 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC); 1387 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1372 radeon_add_legacy_encoder(dev, 1388 radeon_add_legacy_encoder(dev,
@@ -1375,7 +1391,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1375 1), 1391 1),
1376 ATOM_DEVICE_CRT1_SUPPORT); 1392 ATOM_DEVICE_CRT1_SUPPORT);
1377 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1393 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,
1378 DRM_MODE_CONNECTOR_VGA, &ddc_i2c); 1394 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1395 CONNECTOR_OBJECT_ID_VGA);
1379 /* TV - TV DAC */ 1396 /* TV - TV DAC */
1380 radeon_add_legacy_encoder(dev, 1397 radeon_add_legacy_encoder(dev,
1381 radeon_get_encoder_id(dev, 1398 radeon_get_encoder_id(dev,
@@ -1384,7 +1401,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1384 ATOM_DEVICE_TV1_SUPPORT); 1401 ATOM_DEVICE_TV1_SUPPORT);
1385 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1402 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1386 DRM_MODE_CONNECTOR_SVIDEO, 1403 DRM_MODE_CONNECTOR_SVIDEO,
1387 &ddc_i2c); 1404 &ddc_i2c,
1405 CONNECTOR_OBJECT_ID_SVIDEO);
1388 break; 1406 break;
1389 case CT_MINI_EXTERNAL: 1407 case CT_MINI_EXTERNAL:
1390 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1408 DRM_INFO("Connector Table: %d (mini external tmds)\n",
@@ -1401,10 +1419,12 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1401 ATOM_DEVICE_CRT2_SUPPORT, 1419 ATOM_DEVICE_CRT2_SUPPORT,
1402 2), 1420 2),
1403 ATOM_DEVICE_CRT2_SUPPORT); 1421 ATOM_DEVICE_CRT2_SUPPORT);
1422 /* XXX are any DL? */
1404 radeon_add_legacy_connector(dev, 0, 1423 radeon_add_legacy_connector(dev, 0,
1405 ATOM_DEVICE_DFP2_SUPPORT | 1424 ATOM_DEVICE_DFP2_SUPPORT |
1406 ATOM_DEVICE_CRT2_SUPPORT, 1425 ATOM_DEVICE_CRT2_SUPPORT,
1407 DRM_MODE_CONNECTOR_DVII, &ddc_i2c); 1426 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1427 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
1408 /* TV - TV DAC */ 1428 /* TV - TV DAC */
1409 radeon_add_legacy_encoder(dev, 1429 radeon_add_legacy_encoder(dev,
1410 radeon_get_encoder_id(dev, 1430 radeon_get_encoder_id(dev,
@@ -1413,7 +1433,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1413 ATOM_DEVICE_TV1_SUPPORT); 1433 ATOM_DEVICE_TV1_SUPPORT);
1414 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1434 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1415 DRM_MODE_CONNECTOR_SVIDEO, 1435 DRM_MODE_CONNECTOR_SVIDEO,
1416 &ddc_i2c); 1436 &ddc_i2c,
1437 CONNECTOR_OBJECT_ID_SVIDEO);
1417 break; 1438 break;
1418 case CT_MINI_INTERNAL: 1439 case CT_MINI_INTERNAL:
1419 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1440 DRM_INFO("Connector Table: %d (mini internal tmds)\n",
@@ -1433,7 +1454,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1433 radeon_add_legacy_connector(dev, 0, 1454 radeon_add_legacy_connector(dev, 0,
1434 ATOM_DEVICE_DFP1_SUPPORT | 1455 ATOM_DEVICE_DFP1_SUPPORT |
1435 ATOM_DEVICE_CRT2_SUPPORT, 1456 ATOM_DEVICE_CRT2_SUPPORT,
1436 DRM_MODE_CONNECTOR_DVII, &ddc_i2c); 1457 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,
1458 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
1437 /* TV - TV DAC */ 1459 /* TV - TV DAC */
1438 radeon_add_legacy_encoder(dev, 1460 radeon_add_legacy_encoder(dev,
1439 radeon_get_encoder_id(dev, 1461 radeon_get_encoder_id(dev,
@@ -1442,7 +1464,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1442 ATOM_DEVICE_TV1_SUPPORT); 1464 ATOM_DEVICE_TV1_SUPPORT);
1443 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1465 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,
1444 DRM_MODE_CONNECTOR_SVIDEO, 1466 DRM_MODE_CONNECTOR_SVIDEO,
1445 &ddc_i2c); 1467 &ddc_i2c,
1468 CONNECTOR_OBJECT_ID_SVIDEO);
1446 break; 1469 break;
1447 case CT_IMAC_G5_ISIGHT: 1470 case CT_IMAC_G5_ISIGHT:
1448 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1471 DRM_INFO("Connector Table: %d (imac g5 isight)\n",
@@ -1455,7 +1478,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1455 0), 1478 0),
1456 ATOM_DEVICE_DFP1_SUPPORT); 1479 ATOM_DEVICE_DFP1_SUPPORT);
1457 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1480 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,
1458 DRM_MODE_CONNECTOR_DVID, &ddc_i2c); 1481 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,
1482 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D);
1459 /* VGA - tv dac */ 1483 /* VGA - tv dac */
1460 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC); 1484 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
1461 radeon_add_legacy_encoder(dev, 1485 radeon_add_legacy_encoder(dev,
@@ -1464,7 +1488,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1464 2), 1488 2),
1465 ATOM_DEVICE_CRT2_SUPPORT); 1489 ATOM_DEVICE_CRT2_SUPPORT);
1466 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1490 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1467 DRM_MODE_CONNECTOR_VGA, &ddc_i2c); 1491 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1492 CONNECTOR_OBJECT_ID_VGA);
1468 /* TV - TV DAC */ 1493 /* TV - TV DAC */
1469 radeon_add_legacy_encoder(dev, 1494 radeon_add_legacy_encoder(dev,
1470 radeon_get_encoder_id(dev, 1495 radeon_get_encoder_id(dev,
@@ -1473,7 +1498,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1473 ATOM_DEVICE_TV1_SUPPORT); 1498 ATOM_DEVICE_TV1_SUPPORT);
1474 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1499 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1475 DRM_MODE_CONNECTOR_SVIDEO, 1500 DRM_MODE_CONNECTOR_SVIDEO,
1476 &ddc_i2c); 1501 &ddc_i2c,
1502 CONNECTOR_OBJECT_ID_SVIDEO);
1477 break; 1503 break;
1478 case CT_EMAC: 1504 case CT_EMAC:
1479 DRM_INFO("Connector Table: %d (emac)\n", 1505 DRM_INFO("Connector Table: %d (emac)\n",
@@ -1486,7 +1512,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1486 1), 1512 1),
1487 ATOM_DEVICE_CRT1_SUPPORT); 1513 ATOM_DEVICE_CRT1_SUPPORT);
1488 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1514 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,
1489 DRM_MODE_CONNECTOR_VGA, &ddc_i2c); 1515 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1516 CONNECTOR_OBJECT_ID_VGA);
1490 /* VGA - tv dac */ 1517 /* VGA - tv dac */
1491 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC); 1518 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_CRT2_DDC);
1492 radeon_add_legacy_encoder(dev, 1519 radeon_add_legacy_encoder(dev,
@@ -1495,7 +1522,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1495 2), 1522 2),
1496 ATOM_DEVICE_CRT2_SUPPORT); 1523 ATOM_DEVICE_CRT2_SUPPORT);
1497 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1524 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,
1498 DRM_MODE_CONNECTOR_VGA, &ddc_i2c); 1525 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,
1526 CONNECTOR_OBJECT_ID_VGA);
1499 /* TV - TV DAC */ 1527 /* TV - TV DAC */
1500 radeon_add_legacy_encoder(dev, 1528 radeon_add_legacy_encoder(dev,
1501 radeon_get_encoder_id(dev, 1529 radeon_get_encoder_id(dev,
@@ -1504,7 +1532,8 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)
1504 ATOM_DEVICE_TV1_SUPPORT); 1532 ATOM_DEVICE_TV1_SUPPORT);
1505 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1533 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,
1506 DRM_MODE_CONNECTOR_SVIDEO, 1534 DRM_MODE_CONNECTOR_SVIDEO,
1507 &ddc_i2c); 1535 &ddc_i2c,
1536 CONNECTOR_OBJECT_ID_SVIDEO);
1508 break; 1537 break;
1509 default: 1538 default:
1510 DRM_INFO("Connector table: %d (invalid)\n", 1539 DRM_INFO("Connector table: %d (invalid)\n",
@@ -1581,11 +1610,63 @@ static bool radeon_apply_legacy_quirks(struct drm_device *dev,
1581 return true; 1610 return true;
1582} 1611}
1583 1612
1613static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)
1614{
1615 /* Acer 5102 has non-existent TV port */
1616 if (dev->pdev->device == 0x5975 &&
1617 dev->pdev->subsystem_vendor == 0x1025 &&
1618 dev->pdev->subsystem_device == 0x009f)
1619 return false;
1620
1621 /* HP dc5750 has non-existent TV port */
1622 if (dev->pdev->device == 0x5974 &&
1623 dev->pdev->subsystem_vendor == 0x103c &&
1624 dev->pdev->subsystem_device == 0x280a)
1625 return false;
1626
1627 return true;
1628}
1629
1630static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)
1631{
1632 struct radeon_device *rdev = dev->dev_private;
1633 uint32_t ext_tmds_info;
1634
1635 if (rdev->flags & RADEON_IS_IGP) {
1636 if (is_dvi_d)
1637 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1638 else
1639 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1640 }
1641 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);
1642 if (ext_tmds_info) {
1643 uint8_t rev = RBIOS8(ext_tmds_info);
1644 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);
1645 if (rev >= 3) {
1646 if (is_dvi_d)
1647 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1648 else
1649 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1650 } else {
1651 if (flags & 1) {
1652 if (is_dvi_d)
1653 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
1654 else
1655 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
1656 }
1657 }
1658 }
1659 if (is_dvi_d)
1660 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
1661 else
1662 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1663}
1664
1584bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 1665bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1585{ 1666{
1586 struct radeon_device *rdev = dev->dev_private; 1667 struct radeon_device *rdev = dev->dev_private;
1587 uint32_t conn_info, entry, devices; 1668 uint32_t conn_info, entry, devices;
1588 uint16_t tmp; 1669 uint16_t tmp, connector_object_id;
1589 enum radeon_combios_ddc ddc_type; 1670 enum radeon_combios_ddc ddc_type;
1590 enum radeon_combios_connector connector; 1671 enum radeon_combios_connector connector;
1591 int i = 0; 1672 int i = 0;
@@ -1628,8 +1709,9 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1628 break; 1709 break;
1629 } 1710 }
1630 1711
1631 radeon_apply_legacy_quirks(dev, i, &connector, 1712 if (!radeon_apply_legacy_quirks(dev, i, &connector,
1632 &ddc_i2c); 1713 &ddc_i2c))
1714 continue;
1633 1715
1634 switch (connector) { 1716 switch (connector) {
1635 case CONNECTOR_PROPRIETARY_LEGACY: 1717 case CONNECTOR_PROPRIETARY_LEGACY:
@@ -1644,7 +1726,8 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1644 radeon_add_legacy_connector(dev, i, devices, 1726 radeon_add_legacy_connector(dev, i, devices,
1645 legacy_connector_convert 1727 legacy_connector_convert
1646 [connector], 1728 [connector],
1647 &ddc_i2c); 1729 &ddc_i2c,
1730 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D);
1648 break; 1731 break;
1649 case CONNECTOR_CRT_LEGACY: 1732 case CONNECTOR_CRT_LEGACY:
1650 if (tmp & 0x1) { 1733 if (tmp & 0x1) {
@@ -1669,7 +1752,8 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1669 devices, 1752 devices,
1670 legacy_connector_convert 1753 legacy_connector_convert
1671 [connector], 1754 [connector],
1672 &ddc_i2c); 1755 &ddc_i2c,
1756 CONNECTOR_OBJECT_ID_VGA);
1673 break; 1757 break;
1674 case CONNECTOR_DVI_I_LEGACY: 1758 case CONNECTOR_DVI_I_LEGACY:
1675 devices = 0; 1759 devices = 0;
@@ -1698,6 +1782,7 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1698 ATOM_DEVICE_DFP2_SUPPORT, 1782 ATOM_DEVICE_DFP2_SUPPORT,
1699 0), 1783 0),
1700 ATOM_DEVICE_DFP2_SUPPORT); 1784 ATOM_DEVICE_DFP2_SUPPORT);
1785 connector_object_id = combios_check_dl_dvi(dev, 0);
1701 } else { 1786 } else {
1702 devices |= ATOM_DEVICE_DFP1_SUPPORT; 1787 devices |= ATOM_DEVICE_DFP1_SUPPORT;
1703 radeon_add_legacy_encoder(dev, 1788 radeon_add_legacy_encoder(dev,
@@ -1706,19 +1791,24 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1706 ATOM_DEVICE_DFP1_SUPPORT, 1791 ATOM_DEVICE_DFP1_SUPPORT,
1707 0), 1792 0),
1708 ATOM_DEVICE_DFP1_SUPPORT); 1793 ATOM_DEVICE_DFP1_SUPPORT);
1794 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1709 } 1795 }
1710 radeon_add_legacy_connector(dev, 1796 radeon_add_legacy_connector(dev,
1711 i, 1797 i,
1712 devices, 1798 devices,
1713 legacy_connector_convert 1799 legacy_connector_convert
1714 [connector], 1800 [connector],
1715 &ddc_i2c); 1801 &ddc_i2c,
1802 connector_object_id);
1716 break; 1803 break;
1717 case CONNECTOR_DVI_D_LEGACY: 1804 case CONNECTOR_DVI_D_LEGACY:
1718 if ((tmp >> 4) & 0x1) 1805 if ((tmp >> 4) & 0x1) {
1719 devices = ATOM_DEVICE_DFP2_SUPPORT; 1806 devices = ATOM_DEVICE_DFP2_SUPPORT;
1720 else 1807 connector_object_id = combios_check_dl_dvi(dev, 1);
1808 } else {
1721 devices = ATOM_DEVICE_DFP1_SUPPORT; 1809 devices = ATOM_DEVICE_DFP1_SUPPORT;
1810 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
1811 }
1722 radeon_add_legacy_encoder(dev, 1812 radeon_add_legacy_encoder(dev,
1723 radeon_get_encoder_id 1813 radeon_get_encoder_id
1724 (dev, devices, 0), 1814 (dev, devices, 0),
@@ -1726,7 +1816,8 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1726 radeon_add_legacy_connector(dev, i, devices, 1816 radeon_add_legacy_connector(dev, i, devices,
1727 legacy_connector_convert 1817 legacy_connector_convert
1728 [connector], 1818 [connector],
1729 &ddc_i2c); 1819 &ddc_i2c,
1820 connector_object_id);
1730 break; 1821 break;
1731 case CONNECTOR_CTV_LEGACY: 1822 case CONNECTOR_CTV_LEGACY:
1732 case CONNECTOR_STV_LEGACY: 1823 case CONNECTOR_STV_LEGACY:
@@ -1740,7 +1831,8 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1740 ATOM_DEVICE_TV1_SUPPORT, 1831 ATOM_DEVICE_TV1_SUPPORT,
1741 legacy_connector_convert 1832 legacy_connector_convert
1742 [connector], 1833 [connector],
1743 &ddc_i2c); 1834 &ddc_i2c,
1835 CONNECTOR_OBJECT_ID_SVIDEO);
1744 break; 1836 break;
1745 default: 1837 default:
1746 DRM_ERROR("Unknown connector type: %d\n", 1838 DRM_ERROR("Unknown connector type: %d\n",
@@ -1772,10 +1864,29 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1772 ATOM_DEVICE_CRT1_SUPPORT | 1864 ATOM_DEVICE_CRT1_SUPPORT |
1773 ATOM_DEVICE_DFP1_SUPPORT, 1865 ATOM_DEVICE_DFP1_SUPPORT,
1774 DRM_MODE_CONNECTOR_DVII, 1866 DRM_MODE_CONNECTOR_DVII,
1775 &ddc_i2c); 1867 &ddc_i2c,
1868 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I);
1776 } else { 1869 } else {
1777 DRM_DEBUG("No connector info found\n"); 1870 uint16_t crt_info =
1778 return false; 1871 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);
1872 DRM_DEBUG("Found CRT table, assuming VGA connector\n");
1873 if (crt_info) {
1874 radeon_add_legacy_encoder(dev,
1875 radeon_get_encoder_id(dev,
1876 ATOM_DEVICE_CRT1_SUPPORT,
1877 1),
1878 ATOM_DEVICE_CRT1_SUPPORT);
1879 ddc_i2c = combios_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
1880 radeon_add_legacy_connector(dev,
1881 0,
1882 ATOM_DEVICE_CRT1_SUPPORT,
1883 DRM_MODE_CONNECTOR_VGA,
1884 &ddc_i2c,
1885 CONNECTOR_OBJECT_ID_VGA);
1886 } else {
1887 DRM_DEBUG("No connector info found\n");
1888 return false;
1889 }
1779 } 1890 }
1780 } 1891 }
1781 1892
@@ -1870,7 +1981,8 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1870 5, 1981 5,
1871 ATOM_DEVICE_LCD1_SUPPORT, 1982 ATOM_DEVICE_LCD1_SUPPORT,
1872 DRM_MODE_CONNECTOR_LVDS, 1983 DRM_MODE_CONNECTOR_LVDS,
1873 &ddc_i2c); 1984 &ddc_i2c,
1985 CONNECTOR_OBJECT_ID_LVDS);
1874 } 1986 }
1875 } 1987 }
1876 1988
@@ -1880,16 +1992,19 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
1880 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1992 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
1881 if (tv_info) { 1993 if (tv_info) {
1882 if (RBIOS8(tv_info + 6) == 'T') { 1994 if (RBIOS8(tv_info + 6) == 'T') {
1883 radeon_add_legacy_encoder(dev, 1995 if (radeon_apply_legacy_tv_quirks(dev)) {
1884 radeon_get_encoder_id 1996 radeon_add_legacy_encoder(dev,
1885 (dev, 1997 radeon_get_encoder_id
1886 ATOM_DEVICE_TV1_SUPPORT, 1998 (dev,
1887 2), 1999 ATOM_DEVICE_TV1_SUPPORT,
1888 ATOM_DEVICE_TV1_SUPPORT); 2000 2),
1889 radeon_add_legacy_connector(dev, 6, 2001 ATOM_DEVICE_TV1_SUPPORT);
1890 ATOM_DEVICE_TV1_SUPPORT, 2002 radeon_add_legacy_connector(dev, 6,
1891 DRM_MODE_CONNECTOR_SVIDEO, 2003 ATOM_DEVICE_TV1_SUPPORT,
1892 &ddc_i2c); 2004 DRM_MODE_CONNECTOR_SVIDEO,
2005 &ddc_i2c,
2006 CONNECTOR_OBJECT_ID_SVIDEO);
2007 }
1893 } 2008 }
1894 } 2009 }
1895 } 2010 }
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index e376be47a4a..29763ceae3a 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -178,25 +178,12 @@ static struct drm_display_mode *radeon_fp_native_mode(struct drm_encoder *encode
178 struct drm_device *dev = encoder->dev; 178 struct drm_device *dev = encoder->dev;
179 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 179 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
180 struct drm_display_mode *mode = NULL; 180 struct drm_display_mode *mode = NULL;
181 struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; 181 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
182
183 if (native_mode->panel_xres != 0 &&
184 native_mode->panel_yres != 0 &&
185 native_mode->dotclock != 0) {
186 mode = drm_mode_create(dev);
187
188 mode->hdisplay = native_mode->panel_xres;
189 mode->vdisplay = native_mode->panel_yres;
190
191 mode->htotal = mode->hdisplay + native_mode->hblank;
192 mode->hsync_start = mode->hdisplay + native_mode->hoverplus;
193 mode->hsync_end = mode->hsync_start + native_mode->hsync_width;
194 mode->vtotal = mode->vdisplay + native_mode->vblank;
195 mode->vsync_start = mode->vdisplay + native_mode->voverplus;
196 mode->vsync_end = mode->vsync_start + native_mode->vsync_width;
197 mode->clock = native_mode->dotclock;
198 mode->flags = 0;
199 182
183 if (native_mode->hdisplay != 0 &&
184 native_mode->vdisplay != 0 &&
185 native_mode->clock != 0) {
186 mode = drm_mode_duplicate(dev, native_mode);
200 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER; 187 mode->type = DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_DRIVER;
201 drm_mode_set_name(mode); 188 drm_mode_set_name(mode);
202 189
@@ -210,7 +197,7 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn
210 struct drm_device *dev = encoder->dev; 197 struct drm_device *dev = encoder->dev;
211 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 198 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
212 struct drm_display_mode *mode = NULL; 199 struct drm_display_mode *mode = NULL;
213 struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; 200 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
214 int i; 201 int i;
215 struct mode_size { 202 struct mode_size {
216 int w; 203 int w;
@@ -236,11 +223,16 @@ static void radeon_add_common_modes(struct drm_encoder *encoder, struct drm_conn
236 }; 223 };
237 224
238 for (i = 0; i < 17; i++) { 225 for (i = 0; i < 17; i++) {
226 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {
227 if (common_modes[i].w > 1024 ||
228 common_modes[i].h > 768)
229 continue;
230 }
239 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 231 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
240 if (common_modes[i].w > native_mode->panel_xres || 232 if (common_modes[i].w > native_mode->hdisplay ||
241 common_modes[i].h > native_mode->panel_yres || 233 common_modes[i].h > native_mode->vdisplay ||
242 (common_modes[i].w == native_mode->panel_xres && 234 (common_modes[i].w == native_mode->hdisplay &&
243 common_modes[i].h == native_mode->panel_yres)) 235 common_modes[i].h == native_mode->vdisplay))
244 continue; 236 continue;
245 } 237 }
246 if (common_modes[i].w < 320 || common_modes[i].h < 200) 238 if (common_modes[i].w < 320 || common_modes[i].h < 200)
@@ -344,28 +336,23 @@ static void radeon_fixup_lvds_native_mode(struct drm_encoder *encoder,
344 struct drm_connector *connector) 336 struct drm_connector *connector)
345{ 337{
346 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 338 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
347 struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; 339 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
348 340
349 /* Try to get native mode details from EDID if necessary */ 341 /* Try to get native mode details from EDID if necessary */
350 if (!native_mode->dotclock) { 342 if (!native_mode->clock) {
351 struct drm_display_mode *t, *mode; 343 struct drm_display_mode *t, *mode;
352 344
353 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) { 345 list_for_each_entry_safe(mode, t, &connector->probed_modes, head) {
354 if (mode->hdisplay == native_mode->panel_xres && 346 if (mode->hdisplay == native_mode->hdisplay &&
355 mode->vdisplay == native_mode->panel_yres) { 347 mode->vdisplay == native_mode->vdisplay) {
356 native_mode->hblank = mode->htotal - mode->hdisplay; 348 *native_mode = *mode;
357 native_mode->hoverplus = mode->hsync_start - mode->hdisplay; 349 drm_mode_set_crtcinfo(native_mode, CRTC_INTERLACE_HALVE_V);
358 native_mode->hsync_width = mode->hsync_end - mode->hsync_start;
359 native_mode->vblank = mode->vtotal - mode->vdisplay;
360 native_mode->voverplus = mode->vsync_start - mode->vdisplay;
361 native_mode->vsync_width = mode->vsync_end - mode->vsync_start;
362 native_mode->dotclock = mode->clock;
363 DRM_INFO("Determined LVDS native mode details from EDID\n"); 350 DRM_INFO("Determined LVDS native mode details from EDID\n");
364 break; 351 break;
365 } 352 }
366 } 353 }
367 } 354 }
368 if (!native_mode->dotclock) { 355 if (!native_mode->clock) {
369 DRM_INFO("No LVDS native mode details, disabling RMX\n"); 356 DRM_INFO("No LVDS native mode details, disabling RMX\n");
370 radeon_encoder->rmx_type = RMX_OFF; 357 radeon_encoder->rmx_type = RMX_OFF;
371 } 358 }
@@ -410,13 +397,64 @@ static int radeon_lvds_get_modes(struct drm_connector *connector)
410static int radeon_lvds_mode_valid(struct drm_connector *connector, 397static int radeon_lvds_mode_valid(struct drm_connector *connector,
411 struct drm_display_mode *mode) 398 struct drm_display_mode *mode)
412{ 399{
400 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
401
402 if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
403 return MODE_PANEL;
404
405 if (encoder) {
406 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
407 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
408
409 /* AVIVO hardware supports downscaling modes larger than the panel
410 * to the panel size, but I'm not sure this is desirable.
411 */
412 if ((mode->hdisplay > native_mode->hdisplay) ||
413 (mode->vdisplay > native_mode->vdisplay))
414 return MODE_PANEL;
415
416 /* if scaling is disabled, block non-native modes */
417 if (radeon_encoder->rmx_type == RMX_OFF) {
418 if ((mode->hdisplay != native_mode->hdisplay) ||
419 (mode->vdisplay != native_mode->vdisplay))
420 return MODE_PANEL;
421 }
422 }
423
413 return MODE_OK; 424 return MODE_OK;
414} 425}
415 426
416static enum drm_connector_status radeon_lvds_detect(struct drm_connector *connector) 427static enum drm_connector_status radeon_lvds_detect(struct drm_connector *connector)
417{ 428{
418 enum drm_connector_status ret = connector_status_connected; 429 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
430 struct drm_encoder *encoder = radeon_best_single_encoder(connector);
431 enum drm_connector_status ret = connector_status_disconnected;
432
433 if (encoder) {
434 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
435 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
436
437 /* check if panel is valid */
438 if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
439 ret = connector_status_connected;
440
441 }
442
443 /* check for edid as well */
444 if (radeon_connector->edid)
445 ret = connector_status_connected;
446 else {
447 if (radeon_connector->ddc_bus) {
448 radeon_i2c_do_lock(radeon_connector, 1);
449 radeon_connector->edid = drm_get_edid(&radeon_connector->base,
450 &radeon_connector->ddc_bus->adapter);
451 radeon_i2c_do_lock(radeon_connector, 0);
452 if (radeon_connector->edid)
453 ret = connector_status_connected;
454 }
455 }
419 /* check acpi lid status ??? */ 456 /* check acpi lid status ??? */
457
420 radeon_connector_update_scratch_regs(connector, ret); 458 radeon_connector_update_scratch_regs(connector, ret);
421 return ret; 459 return ret;
422} 460}
@@ -427,6 +465,8 @@ static void radeon_connector_destroy(struct drm_connector *connector)
427 465
428 if (radeon_connector->ddc_bus) 466 if (radeon_connector->ddc_bus)
429 radeon_i2c_destroy(radeon_connector->ddc_bus); 467 radeon_i2c_destroy(radeon_connector->ddc_bus);
468 if (radeon_connector->edid)
469 kfree(radeon_connector->edid);
430 kfree(radeon_connector->con_priv); 470 kfree(radeon_connector->con_priv);
431 drm_sysfs_connector_remove(connector); 471 drm_sysfs_connector_remove(connector);
432 drm_connector_cleanup(connector); 472 drm_connector_cleanup(connector);
@@ -496,6 +536,8 @@ static int radeon_vga_get_modes(struct drm_connector *connector)
496static int radeon_vga_mode_valid(struct drm_connector *connector, 536static int radeon_vga_mode_valid(struct drm_connector *connector,
497 struct drm_display_mode *mode) 537 struct drm_display_mode *mode)
498{ 538{
539 /* XXX check mode bandwidth */
540 /* XXX verify against max DAC output frequency */
499 return MODE_OK; 541 return MODE_OK;
500} 542}
501 543
@@ -514,9 +556,33 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
514 radeon_i2c_do_lock(radeon_connector, 1); 556 radeon_i2c_do_lock(radeon_connector, 1);
515 dret = radeon_ddc_probe(radeon_connector); 557 dret = radeon_ddc_probe(radeon_connector);
516 radeon_i2c_do_lock(radeon_connector, 0); 558 radeon_i2c_do_lock(radeon_connector, 0);
517 if (dret) 559 if (dret) {
518 ret = connector_status_connected; 560 if (radeon_connector->edid) {
519 else { 561 kfree(radeon_connector->edid);
562 radeon_connector->edid = NULL;
563 }
564 radeon_i2c_do_lock(radeon_connector, 1);
565 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
566 radeon_i2c_do_lock(radeon_connector, 0);
567
568 if (!radeon_connector->edid) {
569 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
570 drm_get_connector_name(connector));
571 ret = connector_status_connected;
572 } else {
573 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
574
575 /* some oems have boards with separate digital and analog connectors
576 * with a shared ddc line (often vga + hdmi)
577 */
578 if (radeon_connector->use_digital && radeon_connector->shared_ddc) {
579 kfree(radeon_connector->edid);
580 radeon_connector->edid = NULL;
581 ret = connector_status_disconnected;
582 } else
583 ret = connector_status_connected;
584 }
585 } else {
520 if (radeon_connector->dac_load_detect) { 586 if (radeon_connector->dac_load_detect) {
521 encoder_funcs = encoder->helper_private; 587 encoder_funcs = encoder->helper_private;
522 ret = encoder_funcs->detect(encoder, connector); 588 ret = encoder_funcs->detect(encoder, connector);
@@ -570,6 +636,8 @@ static int radeon_tv_get_modes(struct drm_connector *connector)
570static int radeon_tv_mode_valid(struct drm_connector *connector, 636static int radeon_tv_mode_valid(struct drm_connector *connector,
571 struct drm_display_mode *mode) 637 struct drm_display_mode *mode)
572{ 638{
639 if ((mode->hdisplay > 1024) || (mode->vdisplay > 768))
640 return MODE_CLOCK_RANGE;
573 return MODE_OK; 641 return MODE_OK;
574} 642}
575 643
@@ -644,20 +712,29 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
644 dret = radeon_ddc_probe(radeon_connector); 712 dret = radeon_ddc_probe(radeon_connector);
645 radeon_i2c_do_lock(radeon_connector, 0); 713 radeon_i2c_do_lock(radeon_connector, 0);
646 if (dret) { 714 if (dret) {
715 if (radeon_connector->edid) {
716 kfree(radeon_connector->edid);
717 radeon_connector->edid = NULL;
718 }
647 radeon_i2c_do_lock(radeon_connector, 1); 719 radeon_i2c_do_lock(radeon_connector, 1);
648 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); 720 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
649 radeon_i2c_do_lock(radeon_connector, 0); 721 radeon_i2c_do_lock(radeon_connector, 0);
650 722
651 if (!radeon_connector->edid) { 723 if (!radeon_connector->edid) {
652 DRM_ERROR("DDC responded but not EDID found for %s\n", 724 DRM_ERROR("%s: probed a monitor but no|invalid EDID\n",
653 drm_get_connector_name(connector)); 725 drm_get_connector_name(connector));
654 } else { 726 } else {
655 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL); 727 radeon_connector->use_digital = !!(radeon_connector->edid->input & DRM_EDID_INPUT_DIGITAL);
656 728
657 /* if this isn't a digital monitor 729 /* some oems have boards with separate digital and analog connectors
658 then we need to make sure we don't have any 730 * with a shared ddc line (often vga + hdmi)
659 TV conflicts */ 731 */
660 ret = connector_status_connected; 732 if ((!radeon_connector->use_digital) && radeon_connector->shared_ddc) {
733 kfree(radeon_connector->edid);
734 radeon_connector->edid = NULL;
735 ret = connector_status_disconnected;
736 } else
737 ret = connector_status_connected;
661 } 738 }
662 } 739 }
663 740
@@ -753,9 +830,27 @@ static void radeon_dvi_force(struct drm_connector *connector)
753 radeon_connector->use_digital = true; 830 radeon_connector->use_digital = true;
754} 831}
755 832
833static int radeon_dvi_mode_valid(struct drm_connector *connector,
834 struct drm_display_mode *mode)
835{
836 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
837
838 /* XXX check mode bandwidth */
839
840 if (radeon_connector->use_digital && (mode->clock > 165000)) {
841 if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
842 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
843 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B))
844 return MODE_OK;
845 else
846 return MODE_CLOCK_HIGH;
847 }
848 return MODE_OK;
849}
850
756struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = { 851struct drm_connector_helper_funcs radeon_dvi_connector_helper_funcs = {
757 .get_modes = radeon_dvi_get_modes, 852 .get_modes = radeon_dvi_get_modes,
758 .mode_valid = radeon_vga_mode_valid, 853 .mode_valid = radeon_dvi_mode_valid,
759 .best_encoder = radeon_dvi_encoder, 854 .best_encoder = radeon_dvi_encoder,
760}; 855};
761 856
@@ -775,13 +870,15 @@ radeon_add_atom_connector(struct drm_device *dev,
775 int connector_type, 870 int connector_type,
776 struct radeon_i2c_bus_rec *i2c_bus, 871 struct radeon_i2c_bus_rec *i2c_bus,
777 bool linkb, 872 bool linkb,
778 uint32_t igp_lane_info) 873 uint32_t igp_lane_info,
874 uint16_t connector_object_id)
779{ 875{
780 struct radeon_device *rdev = dev->dev_private; 876 struct radeon_device *rdev = dev->dev_private;
781 struct drm_connector *connector; 877 struct drm_connector *connector;
782 struct radeon_connector *radeon_connector; 878 struct radeon_connector *radeon_connector;
783 struct radeon_connector_atom_dig *radeon_dig_connector; 879 struct radeon_connector_atom_dig *radeon_dig_connector;
784 uint32_t subpixel_order = SubPixelNone; 880 uint32_t subpixel_order = SubPixelNone;
881 bool shared_ddc = false;
785 int ret; 882 int ret;
786 883
787 /* fixme - tv/cv/din */ 884 /* fixme - tv/cv/din */
@@ -795,6 +892,13 @@ radeon_add_atom_connector(struct drm_device *dev,
795 radeon_connector->devices |= supported_device; 892 radeon_connector->devices |= supported_device;
796 return; 893 return;
797 } 894 }
895 if (radeon_connector->ddc_bus && i2c_bus->valid) {
896 if (memcmp(&radeon_connector->ddc_bus->rec, i2c_bus,
897 sizeof(struct radeon_i2c_bus_rec)) == 0) {
898 radeon_connector->shared_ddc = true;
899 shared_ddc = true;
900 }
901 }
798 } 902 }
799 903
800 radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL); 904 radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
@@ -805,6 +909,8 @@ radeon_add_atom_connector(struct drm_device *dev,
805 909
806 radeon_connector->connector_id = connector_id; 910 radeon_connector->connector_id = connector_id;
807 radeon_connector->devices = supported_device; 911 radeon_connector->devices = supported_device;
912 radeon_connector->shared_ddc = shared_ddc;
913 radeon_connector->connector_object_id = connector_object_id;
808 switch (connector_type) { 914 switch (connector_type) {
809 case DRM_MODE_CONNECTOR_VGA: 915 case DRM_MODE_CONNECTOR_VGA:
810 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 916 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -956,7 +1062,8 @@ radeon_add_legacy_connector(struct drm_device *dev,
956 uint32_t connector_id, 1062 uint32_t connector_id,
957 uint32_t supported_device, 1063 uint32_t supported_device,
958 int connector_type, 1064 int connector_type,
959 struct radeon_i2c_bus_rec *i2c_bus) 1065 struct radeon_i2c_bus_rec *i2c_bus,
1066 uint16_t connector_object_id)
960{ 1067{
961 struct radeon_device *rdev = dev->dev_private; 1068 struct radeon_device *rdev = dev->dev_private;
962 struct drm_connector *connector; 1069 struct drm_connector *connector;
@@ -985,6 +1092,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
985 1092
986 radeon_connector->connector_id = connector_id; 1093 radeon_connector->connector_id = connector_id;
987 radeon_connector->devices = supported_device; 1094 radeon_connector->devices = supported_device;
1095 radeon_connector->connector_object_id = connector_object_id;
988 switch (connector_type) { 1096 switch (connector_type) {
989 case DRM_MODE_CONNECTOR_VGA: 1097 case DRM_MODE_CONNECTOR_VGA:
990 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type); 1098 drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
@@ -1042,6 +1150,13 @@ radeon_add_legacy_connector(struct drm_device *dev,
1042 if (ret) 1150 if (ret)
1043 goto failed; 1151 goto failed;
1044 radeon_connector->dac_load_detect = true; 1152 radeon_connector->dac_load_detect = true;
1153 /* RS400,RC410,RS480 chipset seems to report a lot
1154 * of false positive on load detect, we haven't yet
1155 * found a way to make load detect reliable on those
1156 * chipset, thus just disable it for TV.
1157 */
1158 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480)
1159 radeon_connector->dac_load_detect = false;
1045 drm_connector_attach_property(&radeon_connector->base, 1160 drm_connector_attach_property(&radeon_connector->base,
1046 rdev->mode_info.load_detect_property, 1161 rdev->mode_info.load_detect_property,
1047 1); 1162 1);
diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
index b13c79e38bc..28772a37009 100644
--- a/drivers/gpu/drm/radeon/radeon_cursor.c
+++ b/drivers/gpu/drm/radeon/radeon_cursor.c
@@ -109,9 +109,15 @@ static void radeon_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
109 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 109 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
110 struct radeon_device *rdev = crtc->dev->dev_private; 110 struct radeon_device *rdev = crtc->dev->dev_private;
111 111
112 if (ASIC_IS_AVIVO(rdev)) 112 if (ASIC_IS_AVIVO(rdev)) {
113 if (rdev->family >= CHIP_RV770) {
114 if (radeon_crtc->crtc_id)
115 WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH, 0);
116 else
117 WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH, 0);
118 }
113 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); 119 WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr);
114 else { 120 } else {
115 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr; 121 radeon_crtc->legacy_cursor_offset = gpu_addr - radeon_crtc->legacy_display_base_addr;
116 /* offset is from DISP(2)_BASE_ADDRESS */ 122 /* offset is from DISP(2)_BASE_ADDRESS */
117 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); 123 WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index df988142e6b..41bb76fbe73 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -444,20 +444,24 @@ static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
444 return r; 444 return r;
445} 445}
446 446
447static struct card_info atom_card_info = {
448 .dev = NULL,
449 .reg_read = cail_reg_read,
450 .reg_write = cail_reg_write,
451 .mc_read = cail_mc_read,
452 .mc_write = cail_mc_write,
453 .pll_read = cail_pll_read,
454 .pll_write = cail_pll_write,
455};
456
457int radeon_atombios_init(struct radeon_device *rdev) 447int radeon_atombios_init(struct radeon_device *rdev)
458{ 448{
459 atom_card_info.dev = rdev->ddev; 449 struct card_info *atom_card_info =
460 rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios); 450 kzalloc(sizeof(struct card_info), GFP_KERNEL);
451
452 if (!atom_card_info)
453 return -ENOMEM;
454
455 rdev->mode_info.atom_card_info = atom_card_info;
456 atom_card_info->dev = rdev->ddev;
457 atom_card_info->reg_read = cail_reg_read;
458 atom_card_info->reg_write = cail_reg_write;
459 atom_card_info->mc_read = cail_mc_read;
460 atom_card_info->mc_write = cail_mc_write;
461 atom_card_info->pll_read = cail_pll_read;
462 atom_card_info->pll_write = cail_pll_write;
463
464 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
461 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 465 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
462 return 0; 466 return 0;
463} 467}
@@ -465,6 +469,7 @@ int radeon_atombios_init(struct radeon_device *rdev)
465void radeon_atombios_fini(struct radeon_device *rdev) 469void radeon_atombios_fini(struct radeon_device *rdev)
466{ 470{
467 kfree(rdev->mode_info.atom_context); 471 kfree(rdev->mode_info.atom_context);
472 kfree(rdev->mode_info.atom_card_info);
468} 473}
469 474
470int radeon_combios_init(struct radeon_device *rdev) 475int radeon_combios_init(struct radeon_device *rdev)
@@ -683,6 +688,8 @@ int radeon_resume_kms(struct drm_device *dev)
683 return -1; 688 return -1;
684 } 689 }
685 pci_set_master(dev->pdev); 690 pci_set_master(dev->pdev);
691 /* resume AGP if in use */
692 radeon_agp_resume(rdev);
686 radeon_resume(rdev); 693 radeon_resume(rdev);
687 radeon_restore_bios_scratch_regs(rdev); 694 radeon_restore_bios_scratch_regs(rdev);
688 fb_set_suspend(rdev->fbdev_info, 0); 695 fb_set_suspend(rdev->fbdev_info, 0);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 3655d91993a..c85df4afcb7 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -137,9 +137,6 @@ static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
137 if (size != 256) { 137 if (size != 256) {
138 return; 138 return;
139 } 139 }
140 if (crtc->fb == NULL) {
141 return;
142 }
143 140
144 /* userspace palettes are always correct as is */ 141 /* userspace palettes are always correct as is */
145 for (i = 0; i < 256; i++) { 142 for (i = 0; i < 256; i++) {
@@ -147,7 +144,6 @@ static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
147 radeon_crtc->lut_g[i] = green[i] >> 6; 144 radeon_crtc->lut_g[i] = green[i] >> 6;
148 radeon_crtc->lut_b[i] = blue[i] >> 6; 145 radeon_crtc->lut_b[i] = blue[i] >> 6;
149 } 146 }
150
151 radeon_crtc_load_lut(crtc); 147 radeon_crtc_load_lut(crtc);
152} 148}
153 149
@@ -338,27 +334,19 @@ static bool radeon_setup_enc_conn(struct drm_device *dev)
338 334
339int radeon_ddc_get_modes(struct radeon_connector *radeon_connector) 335int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
340{ 336{
341 struct edid *edid;
342 int ret = 0; 337 int ret = 0;
343 338
344 if (!radeon_connector->ddc_bus) 339 if (!radeon_connector->ddc_bus)
345 return -1; 340 return -1;
346 if (!radeon_connector->edid) { 341 if (!radeon_connector->edid) {
347 radeon_i2c_do_lock(radeon_connector, 1); 342 radeon_i2c_do_lock(radeon_connector, 1);
348 edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter); 343 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
349 radeon_i2c_do_lock(radeon_connector, 0); 344 radeon_i2c_do_lock(radeon_connector, 0);
350 } else 345 }
351 edid = radeon_connector->edid;
352 346
353 if (edid) { 347 if (radeon_connector->edid) {
354 /* update digital bits here */ 348 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
355 if (edid->input & DRM_EDID_INPUT_DIGITAL) 349 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
356 radeon_connector->use_digital = 1;
357 else
358 radeon_connector->use_digital = 0;
359 drm_mode_connector_update_edid_property(&radeon_connector->base, edid);
360 ret = drm_add_edid_modes(&radeon_connector->base, edid);
361 kfree(edid);
362 return ret; 350 return ret;
363 } 351 }
364 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL); 352 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
@@ -765,7 +753,7 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
765 radeon_crtc->rmx_type = radeon_encoder->rmx_type; 753 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
766 memcpy(&radeon_crtc->native_mode, 754 memcpy(&radeon_crtc->native_mode,
767 &radeon_encoder->native_mode, 755 &radeon_encoder->native_mode,
768 sizeof(struct radeon_native_mode)); 756 sizeof(struct drm_display_mode));
769 first = false; 757 first = false;
770 } else { 758 } else {
771 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { 759 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
@@ -783,10 +771,10 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
783 if (radeon_crtc->rmx_type != RMX_OFF) { 771 if (radeon_crtc->rmx_type != RMX_OFF) {
784 fixed20_12 a, b; 772 fixed20_12 a, b;
785 a.full = rfixed_const(crtc->mode.vdisplay); 773 a.full = rfixed_const(crtc->mode.vdisplay);
786 b.full = rfixed_const(radeon_crtc->native_mode.panel_xres); 774 b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
787 radeon_crtc->vsc.full = rfixed_div(a, b); 775 radeon_crtc->vsc.full = rfixed_div(a, b);
788 a.full = rfixed_const(crtc->mode.hdisplay); 776 a.full = rfixed_const(crtc->mode.hdisplay);
789 b.full = rfixed_const(radeon_crtc->native_mode.panel_yres); 777 b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
790 radeon_crtc->hsc.full = rfixed_div(a, b); 778 radeon_crtc->hsc.full = rfixed_div(a, b);
791 } else { 779 } else {
792 radeon_crtc->vsc.full = rfixed_const(1); 780 radeon_crtc->vsc.full = rfixed_const(1);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index a65ab1a0dad..d42bc512d75 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -31,6 +31,10 @@
31 31
32extern int atom_debug; 32extern int atom_debug;
33 33
34/* evil but including atombios.h is much worse */
35bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
34uint32_t 38uint32_t
35radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac) 39radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
36{ 40{
@@ -167,49 +171,17 @@ void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 171 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
168 struct drm_device *dev = encoder->dev; 172 struct drm_device *dev = encoder->dev;
169 struct radeon_device *rdev = dev->dev_private; 173 struct radeon_device *rdev = dev->dev_private;
170 struct radeon_native_mode *native_mode = &radeon_encoder->native_mode; 174 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
171 175
172 if (mode->hdisplay < native_mode->panel_xres || 176 if (mode->hdisplay < native_mode->hdisplay ||
173 mode->vdisplay < native_mode->panel_yres) { 177 mode->vdisplay < native_mode->vdisplay) {
174 if (ASIC_IS_AVIVO(rdev)) { 178 int mode_id = adjusted_mode->base.id;
175 adjusted_mode->hdisplay = native_mode->panel_xres; 179 *adjusted_mode = *native_mode;
176 adjusted_mode->vdisplay = native_mode->panel_yres; 180 if (!ASIC_IS_AVIVO(rdev)) {
177 adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank; 181 adjusted_mode->hdisplay = mode->hdisplay;
178 adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus; 182 adjusted_mode->vdisplay = mode->vdisplay;
179 adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
180 adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
181 adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
182 adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
183 /* update crtc values */
184 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
185 /* adjust crtc values */
186 adjusted_mode->crtc_hdisplay = native_mode->panel_xres;
187 adjusted_mode->crtc_vdisplay = native_mode->panel_yres;
188 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
189 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
190 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
191 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
192 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
193 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
194 } else {
195 adjusted_mode->htotal = native_mode->panel_xres + native_mode->hblank;
196 adjusted_mode->hsync_start = native_mode->panel_xres + native_mode->hoverplus;
197 adjusted_mode->hsync_end = adjusted_mode->hsync_start + native_mode->hsync_width;
198 adjusted_mode->vtotal = native_mode->panel_yres + native_mode->vblank;
199 adjusted_mode->vsync_start = native_mode->panel_yres + native_mode->voverplus;
200 adjusted_mode->vsync_end = adjusted_mode->vsync_start + native_mode->vsync_width;
201 /* update crtc values */
202 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
203 /* adjust crtc values */
204 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + native_mode->hblank;
205 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + native_mode->hoverplus;
206 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + native_mode->hsync_width;
207 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + native_mode->vblank;
208 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + native_mode->voverplus;
209 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + native_mode->vsync_width;
210 } 183 }
211 adjusted_mode->flags = native_mode->flags; 184 adjusted_mode->base.id = mode_id;
212 adjusted_mode->clock = native_mode->dotclock;
213 } 185 }
214} 186}
215 187
@@ -219,7 +191,11 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
219 struct drm_display_mode *adjusted_mode) 191 struct drm_display_mode *adjusted_mode)
220{ 192{
221 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
194 struct drm_device *dev = encoder->dev;
195 struct radeon_device *rdev = dev->dev_private;
222 196
197 /* set the active encoder to connector routing */
198 radeon_encoder_set_active_device(encoder);
223 drm_mode_set_crtcinfo(adjusted_mode, 0); 199 drm_mode_set_crtcinfo(adjusted_mode, 0);
224 200
225 if (radeon_encoder->rmx_type != RMX_OFF) 201 if (radeon_encoder->rmx_type != RMX_OFF)
@@ -230,6 +206,18 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
230 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2))) 206 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
231 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2; 207 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
232 208
209 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
210 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
211 if (tv_dac) {
212 if (tv_dac->tv_std == TV_STD_NTSC ||
213 tv_dac->tv_std == TV_STD_NTSC_J ||
214 tv_dac->tv_std == TV_STD_PAL_M)
215 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
216 else
217 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
218 }
219 }
220
233 return true; 221 return true;
234} 222}
235 223
@@ -461,7 +449,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
461 case 1: 449 case 1:
462 args.v1.ucMisc = 0; 450 args.v1.ucMisc = 0;
463 args.v1.ucAction = action; 451 args.v1.ucAction = action;
464 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) 452 if (drm_detect_hdmi_monitor(radeon_connector->edid))
465 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 453 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
466 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 454 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
467 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 455 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
@@ -486,7 +474,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
486 if (dig->coherent_mode) 474 if (dig->coherent_mode)
487 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT; 475 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
488 } 476 }
489 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) 477 if (drm_detect_hdmi_monitor(radeon_connector->edid))
490 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE; 478 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
491 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 479 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
492 args.v2.ucTruncate = 0; 480 args.v2.ucTruncate = 0;
@@ -544,7 +532,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
544 switch (connector->connector_type) { 532 switch (connector->connector_type) {
545 case DRM_MODE_CONNECTOR_DVII: 533 case DRM_MODE_CONNECTOR_DVII:
546 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ 534 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
547 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) 535 if (drm_detect_hdmi_monitor(radeon_connector->edid))
548 return ATOM_ENCODER_MODE_HDMI; 536 return ATOM_ENCODER_MODE_HDMI;
549 else if (radeon_connector->use_digital) 537 else if (radeon_connector->use_digital)
550 return ATOM_ENCODER_MODE_DVI; 538 return ATOM_ENCODER_MODE_DVI;
@@ -554,7 +542,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
554 case DRM_MODE_CONNECTOR_DVID: 542 case DRM_MODE_CONNECTOR_DVID:
555 case DRM_MODE_CONNECTOR_HDMIA: 543 case DRM_MODE_CONNECTOR_HDMIA:
556 default: 544 default:
557 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) 545 if (drm_detect_hdmi_monitor(radeon_connector->edid))
558 return ATOM_ENCODER_MODE_HDMI; 546 return ATOM_ENCODER_MODE_HDMI;
559 else 547 else
560 return ATOM_ENCODER_MODE_DVI; 548 return ATOM_ENCODER_MODE_DVI;
@@ -566,7 +554,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
566 /*if (radeon_output->MonType == MT_DP) 554 /*if (radeon_output->MonType == MT_DP)
567 return ATOM_ENCODER_MODE_DP; 555 return ATOM_ENCODER_MODE_DP;
568 else*/ 556 else*/
569 if (drm_detect_hdmi_monitor((struct edid *)connector->edid_blob_ptr)) 557 if (drm_detect_hdmi_monitor(radeon_connector->edid))
570 return ATOM_ENCODER_MODE_HDMI; 558 return ATOM_ENCODER_MODE_HDMI;
571 else 559 else
572 return ATOM_ENCODER_MODE_DVI; 560 return ATOM_ENCODER_MODE_DVI;
@@ -734,14 +722,17 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
734 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 722 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
735 723
736 args.v1.ucAction = action; 724 args.v1.ucAction = action;
737 725 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
726 args.v1.usInitInfo = radeon_connector->connector_object_id;
727 } else {
728 if (radeon_encoder->pixel_clock > 165000)
729 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
730 else
731 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
732 }
738 if (ASIC_IS_DCE32(rdev)) { 733 if (ASIC_IS_DCE32(rdev)) {
739 if (radeon_encoder->pixel_clock > 165000) { 734 if (radeon_encoder->pixel_clock > 165000)
740 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 2) / 100); 735 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
741 args.v2.acConfig.fDualLinkConnector = 1;
742 } else {
743 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock * 10 * 4) / 100);
744 }
745 if (dig->dig_block) 736 if (dig->dig_block)
746 args.v2.acConfig.ucEncoderSel = 1; 737 args.v2.acConfig.ucEncoderSel = 1;
747 738
@@ -766,7 +757,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action)
766 } 757 }
767 } else { 758 } else {
768 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 759 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
769 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock) / 10);
770 760
771 switch (radeon_encoder->encoder_id) { 761 switch (radeon_encoder->encoder_id) {
772 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 762 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
@@ -874,16 +864,9 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
874 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args; 864 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
875 int index = 0; 865 int index = 0;
876 bool is_dig = false; 866 bool is_dig = false;
877 int devices;
878 867
879 memset(&args, 0, sizeof(args)); 868 memset(&args, 0, sizeof(args));
880 869
881 /* on DPMS off we have no idea if active device is meaningful */
882 if (mode != DRM_MODE_DPMS_ON && !radeon_encoder->active_device)
883 devices = radeon_encoder->devices;
884 else
885 devices = radeon_encoder->active_device;
886
887 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n", 870 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
888 radeon_encoder->encoder_id, mode, radeon_encoder->devices, 871 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
889 radeon_encoder->active_device); 872 radeon_encoder->active_device);
@@ -914,18 +897,18 @@ radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
914 break; 897 break;
915 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 898 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
916 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 899 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
917 if (devices & (ATOM_DEVICE_TV_SUPPORT)) 900 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
918 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 901 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
919 else if (devices & (ATOM_DEVICE_CV_SUPPORT)) 902 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
920 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 903 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
921 else 904 else
922 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl); 905 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
923 break; 906 break;
924 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 907 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
925 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 908 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
926 if (devices & (ATOM_DEVICE_TV_SUPPORT)) 909 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
927 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl); 910 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
928 else if (devices & (ATOM_DEVICE_CV_SUPPORT)) 911 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
929 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl); 912 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
930 else 913 else
931 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl); 914 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
@@ -1104,8 +1087,11 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1104 } 1087 }
1105 1088
1106 /* set scaler clears this on some chips */ 1089 /* set scaler clears this on some chips */
1107 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE)) 1090 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1108 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, AVIVO_D1MODE_INTERLEAVE_EN); 1091 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1092 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1093 AVIVO_D1MODE_INTERLEAVE_EN);
1094 }
1109} 1095}
1110 1096
1111static void 1097static void
@@ -1153,6 +1139,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1153 1139
1154 /* setup and enable the encoder and transmitter */ 1140 /* setup and enable the encoder and transmitter */
1155 atombios_dig_encoder_setup(encoder, ATOM_ENABLE); 1141 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1142 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT);
1156 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP); 1143 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP);
1157 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE); 1144 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE);
1158 break; 1145 break;
@@ -1268,8 +1255,6 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1268{ 1255{
1269 radeon_atom_output_lock(encoder, true); 1256 radeon_atom_output_lock(encoder, true);
1270 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1257 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1271
1272 radeon_encoder_set_active_device(encoder);
1273} 1258}
1274 1259
1275static void radeon_atom_encoder_commit(struct drm_encoder *encoder) 1260static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index a931af065dd..a68d7566178 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -140,15 +140,15 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
140 WARN(1, "trying to unbind memory to unitialized GART !\n"); 140 WARN(1, "trying to unbind memory to unitialized GART !\n");
141 return; 141 return;
142 } 142 }
143 t = offset / 4096; 143 t = offset / RADEON_GPU_PAGE_SIZE;
144 p = t / (PAGE_SIZE / 4096); 144 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
145 for (i = 0; i < pages; i++, p++) { 145 for (i = 0; i < pages; i++, p++) {
146 if (rdev->gart.pages[p]) { 146 if (rdev->gart.pages[p]) {
147 pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p], 147 pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
148 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 148 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
149 rdev->gart.pages[p] = NULL; 149 rdev->gart.pages[p] = NULL;
150 rdev->gart.pages_addr[p] = 0; 150 rdev->gart.pages_addr[p] = 0;
151 for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) { 151 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
152 radeon_gart_set_page(rdev, t, 0); 152 radeon_gart_set_page(rdev, t, 0);
153 } 153 }
154 } 154 }
@@ -169,8 +169,8 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
169 DRM_ERROR("trying to bind memory to unitialized GART !\n"); 169 DRM_ERROR("trying to bind memory to unitialized GART !\n");
170 return -EINVAL; 170 return -EINVAL;
171 } 171 }
172 t = offset / 4096; 172 t = offset / RADEON_GPU_PAGE_SIZE;
173 p = t / (PAGE_SIZE / 4096); 173 p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE);
174 174
175 for (i = 0; i < pages; i++, p++) { 175 for (i = 0; i < pages; i++, p++) {
176 /* we need to support large memory configurations */ 176 /* we need to support large memory configurations */
@@ -185,9 +185,9 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
185 } 185 }
186 rdev->gart.pages[p] = pagelist[i]; 186 rdev->gart.pages[p] = pagelist[i];
187 page_base = rdev->gart.pages_addr[p]; 187 page_base = rdev->gart.pages_addr[p];
188 for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) { 188 for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
189 radeon_gart_set_page(rdev, t, page_base); 189 radeon_gart_set_page(rdev, t, page_base);
190 page_base += 4096; 190 page_base += RADEON_GPU_PAGE_SIZE;
191 } 191 }
192 } 192 }
193 mb(); 193 mb();
@@ -200,14 +200,14 @@ int radeon_gart_init(struct radeon_device *rdev)
200 if (rdev->gart.pages) { 200 if (rdev->gart.pages) {
201 return 0; 201 return 0;
202 } 202 }
203 /* We need PAGE_SIZE >= 4096 */ 203 /* We need PAGE_SIZE >= RADEON_GPU_PAGE_SIZE */
204 if (PAGE_SIZE < 4096) { 204 if (PAGE_SIZE < RADEON_GPU_PAGE_SIZE) {
205 DRM_ERROR("Page size is smaller than GPU page size!\n"); 205 DRM_ERROR("Page size is smaller than GPU page size!\n");
206 return -EINVAL; 206 return -EINVAL;
207 } 207 }
208 /* Compute table size */ 208 /* Compute table size */
209 rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; 209 rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
210 rdev->gart.num_gpu_pages = rdev->mc.gtt_size / 4096; 210 rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
211 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", 211 DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
212 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); 212 rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages);
213 /* Allocate pages table */ 213 /* Allocate pages table */
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 8e0a8759e42..a0fe6232dcb 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -92,6 +92,13 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
92 if (r) { 92 if (r) {
93 return r; 93 return r;
94 } 94 }
95 /* enable msi */
96 rdev->msi_enabled = 0;
97 if (rdev->family >= CHIP_RV380) {
98 int ret = pci_enable_msi(rdev->pdev);
99 if (!ret)
100 rdev->msi_enabled = 1;
101 }
95 drm_irq_install(rdev->ddev); 102 drm_irq_install(rdev->ddev);
96 rdev->irq.installed = true; 103 rdev->irq.installed = true;
97 DRM_INFO("radeon: irq initialized.\n"); 104 DRM_INFO("radeon: irq initialized.\n");
@@ -103,5 +110,7 @@ void radeon_irq_kms_fini(struct radeon_device *rdev)
103 if (rdev->irq.installed) { 110 if (rdev->irq.installed) {
104 rdev->irq.installed = false; 111 rdev->irq.installed = false;
105 drm_irq_uninstall(rdev->ddev); 112 drm_irq_uninstall(rdev->ddev);
113 if (rdev->msi_enabled)
114 pci_disable_msi(rdev->pdev);
106 } 115 }
107} 116}
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 36410f85d70..8d0b7aa87fa 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -48,7 +48,7 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
48 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active; 48 u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
49 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp; 49 u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
50 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp; 50 u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
51 struct radeon_native_mode *native_mode = &radeon_crtc->native_mode; 51 struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
52 52
53 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) & 53 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
54 (RADEON_VERT_STRETCH_RESERVED | 54 (RADEON_VERT_STRETCH_RESERVED |
@@ -95,19 +95,19 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
95 95
96 fp_horz_vert_active = 0; 96 fp_horz_vert_active = 0;
97 97
98 if (native_mode->panel_xres == 0 || 98 if (native_mode->hdisplay == 0 ||
99 native_mode->panel_yres == 0) { 99 native_mode->vdisplay == 0) {
100 hscale = false; 100 hscale = false;
101 vscale = false; 101 vscale = false;
102 } else { 102 } else {
103 if (xres > native_mode->panel_xres) 103 if (xres > native_mode->hdisplay)
104 xres = native_mode->panel_xres; 104 xres = native_mode->hdisplay;
105 if (yres > native_mode->panel_yres) 105 if (yres > native_mode->vdisplay)
106 yres = native_mode->panel_yres; 106 yres = native_mode->vdisplay;
107 107
108 if (xres == native_mode->panel_xres) 108 if (xres == native_mode->hdisplay)
109 hscale = false; 109 hscale = false;
110 if (yres == native_mode->panel_yres) 110 if (yres == native_mode->vdisplay)
111 vscale = false; 111 vscale = false;
112 } 112 }
113 113
@@ -119,11 +119,11 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
119 else { 119 else {
120 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0; 120 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
121 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX) 121 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
122 / native_mode->panel_xres + 1; 122 / native_mode->hdisplay + 1;
123 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) | 123 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
124 RADEON_HORZ_STRETCH_BLEND | 124 RADEON_HORZ_STRETCH_BLEND |
125 RADEON_HORZ_STRETCH_ENABLE | 125 RADEON_HORZ_STRETCH_ENABLE |
126 ((native_mode->panel_xres/8-1) << 16)); 126 ((native_mode->hdisplay/8-1) << 16));
127 } 127 }
128 128
129 if (!vscale) 129 if (!vscale)
@@ -131,11 +131,11 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
131 else { 131 else {
132 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0; 132 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
133 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX) 133 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
134 / native_mode->panel_yres + 1; 134 / native_mode->vdisplay + 1;
135 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) | 135 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
136 RADEON_VERT_STRETCH_ENABLE | 136 RADEON_VERT_STRETCH_ENABLE |
137 RADEON_VERT_STRETCH_BLEND | 137 RADEON_VERT_STRETCH_BLEND |
138 ((native_mode->panel_yres-1) << 12)); 138 ((native_mode->vdisplay-1) << 12));
139 } 139 }
140 break; 140 break;
141 case RMX_CENTER: 141 case RMX_CENTER:
@@ -175,8 +175,8 @@ static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
175 ? RADEON_CRTC_V_SYNC_POL 175 ? RADEON_CRTC_V_SYNC_POL
176 : 0))); 176 : 0)));
177 177
178 fp_horz_vert_active = (((native_mode->panel_yres) & 0xfff) | 178 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
179 (((native_mode->panel_xres / 8) & 0x1ff) << 16)); 179 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
180 break; 180 break;
181 case RMX_OFF: 181 case RMX_OFF:
182 default: 182 default:
@@ -532,6 +532,10 @@ int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
532 radeon_fb = to_radeon_framebuffer(old_fb); 532 radeon_fb = to_radeon_framebuffer(old_fb);
533 radeon_gem_object_unpin(radeon_fb->obj); 533 radeon_gem_object_unpin(radeon_fb->obj);
534 } 534 }
535
536 /* Bytes per pixel may have changed */
537 radeon_bandwidth_update(rdev);
538
535 return 0; 539 return 0;
536} 540}
537 541
@@ -664,6 +668,9 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
664 668
665 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl); 669 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
666 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 670 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
671
672 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
673 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
667 } else { 674 } else {
668 uint32_t crtc_gen_cntl; 675 uint32_t crtc_gen_cntl;
669 uint32_t crtc_ext_cntl; 676 uint32_t crtc_ext_cntl;
@@ -1015,14 +1022,11 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc,
1015 int x, int y, struct drm_framebuffer *old_fb) 1022 int x, int y, struct drm_framebuffer *old_fb)
1016{ 1023{
1017 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1024 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1018 struct drm_device *dev = crtc->dev;
1019 struct radeon_device *rdev = dev->dev_private;
1020 1025
1021 /* TODO TV */ 1026 /* TODO TV */
1022 radeon_crtc_set_base(crtc, x, y, old_fb); 1027 radeon_crtc_set_base(crtc, x, y, old_fb);
1023 radeon_set_crtc_timing(crtc, adjusted_mode); 1028 radeon_set_crtc_timing(crtc, adjusted_mode);
1024 radeon_set_pll(crtc, adjusted_mode); 1029 radeon_set_pll(crtc, adjusted_mode);
1025 radeon_bandwidth_update(rdev);
1026 if (radeon_crtc->crtc_id == 0) { 1030 if (radeon_crtc->crtc_id == 0) {
1027 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode); 1031 radeon_legacy_rmx_mode_set(crtc, mode, adjusted_mode);
1028 } else { 1032 } else {
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 6ceb958fd19..00382122869 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -107,8 +107,6 @@ static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
107 else 107 else
108 radeon_combios_output_lock(encoder, true); 108 radeon_combios_output_lock(encoder, true);
109 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); 109 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
110
111 radeon_encoder_set_active_device(encoder);
112} 110}
113 111
114static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) 112static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
@@ -192,6 +190,8 @@ static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
192{ 190{
193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 191 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
194 192
193 /* set the active encoder to connector routing */
194 radeon_encoder_set_active_device(encoder);
195 drm_mode_set_crtcinfo(adjusted_mode, 0); 195 drm_mode_set_crtcinfo(adjusted_mode, 0);
196 196
197 if (radeon_encoder->rmx_type != RMX_OFF) 197 if (radeon_encoder->rmx_type != RMX_OFF)
@@ -218,7 +218,8 @@ static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
218 struct drm_display_mode *mode, 218 struct drm_display_mode *mode,
219 struct drm_display_mode *adjusted_mode) 219 struct drm_display_mode *adjusted_mode)
220{ 220{
221 221 /* set the active encoder to connector routing */
222 radeon_encoder_set_active_device(encoder);
222 drm_mode_set_crtcinfo(adjusted_mode, 0); 223 drm_mode_set_crtcinfo(adjusted_mode, 0);
223 224
224 return true; 225 return true;
@@ -272,7 +273,6 @@ static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
272 else 273 else
273 radeon_combios_output_lock(encoder, true); 274 radeon_combios_output_lock(encoder, true);
274 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 275 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
275 radeon_encoder_set_active_device(encoder);
276} 276}
277 277
278static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) 278static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
@@ -468,7 +468,6 @@ static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
468 else 468 else
469 radeon_combios_output_lock(encoder, true); 469 radeon_combios_output_lock(encoder, true);
470 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); 470 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
471 radeon_encoder_set_active_device(encoder);
472} 471}
473 472
474static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) 473static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
@@ -543,6 +542,14 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
543 542
544 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 543 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
545 544
545 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
546 RADEON_FP_DFP_SYNC_SEL |
547 RADEON_FP_CRT_SYNC_SEL |
548 RADEON_FP_CRTC_LOCK_8DOT |
549 RADEON_FP_USE_SHADOW_EN |
550 RADEON_FP_CRTC_USE_SHADOW_VEND |
551 RADEON_FP_CRT_SYNC_ALT);
552
546 if (1) /* FIXME rgbBits == 8 */ 553 if (1) /* FIXME rgbBits == 8 */
547 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ 554 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */
548 else 555 else
@@ -556,7 +563,7 @@ static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
556 else 563 else
557 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; 564 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
558 } else 565 } else
559 fp_gen_cntl |= RADEON_FP_SEL_CRTC1; 566 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
560 } else { 567 } else {
561 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 568 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
562 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 569 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
@@ -593,7 +600,8 @@ static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
593 struct drm_display_mode *mode, 600 struct drm_display_mode *mode,
594 struct drm_display_mode *adjusted_mode) 601 struct drm_display_mode *adjusted_mode)
595{ 602{
596 603 /* set the active encoder to connector routing */
604 radeon_encoder_set_active_device(encoder);
597 drm_mode_set_crtcinfo(adjusted_mode, 0); 605 drm_mode_set_crtcinfo(adjusted_mode, 0);
598 606
599 return true; 607 return true;
@@ -636,7 +644,6 @@ static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
636 else 644 else
637 radeon_combios_output_lock(encoder, true); 645 radeon_combios_output_lock(encoder, true);
638 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); 646 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
639 radeon_encoder_set_active_device(encoder);
640} 647}
641 648
642static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) 649static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
@@ -735,7 +742,8 @@ static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
735 struct drm_display_mode *mode, 742 struct drm_display_mode *mode,
736 struct drm_display_mode *adjusted_mode) 743 struct drm_display_mode *adjusted_mode)
737{ 744{
738 745 /* set the active encoder to connector routing */
746 radeon_encoder_set_active_device(encoder);
739 drm_mode_set_crtcinfo(adjusted_mode, 0); 747 drm_mode_set_crtcinfo(adjusted_mode, 0);
740 748
741 return true; 749 return true;
@@ -839,7 +847,6 @@ static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
839 else 847 else
840 radeon_combios_output_lock(encoder, true); 848 radeon_combios_output_lock(encoder, true);
841 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 849 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
842 radeon_encoder_set_active_device(encoder);
843} 850}
844 851
845static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) 852static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index e61226817cc..ace726aa0d7 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -172,6 +172,7 @@ enum radeon_connector_table {
172 172
173struct radeon_mode_info { 173struct radeon_mode_info {
174 struct atom_context *atom_context; 174 struct atom_context *atom_context;
175 struct card_info *atom_card_info;
175 enum radeon_connector_table connector_table; 176 enum radeon_connector_table connector_table;
176 bool mode_config_initialized; 177 bool mode_config_initialized;
177 struct radeon_crtc *crtcs[2]; 178 struct radeon_crtc *crtcs[2];
@@ -186,17 +187,6 @@ struct radeon_mode_info {
186 187
187}; 188};
188 189
189struct radeon_native_mode {
190 /* preferred mode */
191 uint32_t panel_xres, panel_yres;
192 uint32_t hoverplus, hsync_width;
193 uint32_t hblank;
194 uint32_t voverplus, vsync_width;
195 uint32_t vblank;
196 uint32_t dotclock;
197 uint32_t flags;
198};
199
200#define MAX_H_CODE_TIMING_LEN 32 190#define MAX_H_CODE_TIMING_LEN 32
201#define MAX_V_CODE_TIMING_LEN 32 191#define MAX_V_CODE_TIMING_LEN 32
202 192
@@ -228,7 +218,7 @@ struct radeon_crtc {
228 enum radeon_rmx_type rmx_type; 218 enum radeon_rmx_type rmx_type;
229 fixed20_12 vsc; 219 fixed20_12 vsc;
230 fixed20_12 hsc; 220 fixed20_12 hsc;
231 struct radeon_native_mode native_mode; 221 struct drm_display_mode native_mode;
232}; 222};
233 223
234struct radeon_encoder_primary_dac { 224struct radeon_encoder_primary_dac {
@@ -248,7 +238,7 @@ struct radeon_encoder_lvds {
248 bool use_bios_dividers; 238 bool use_bios_dividers;
249 uint32_t lvds_gen_cntl; 239 uint32_t lvds_gen_cntl;
250 /* panel mode */ 240 /* panel mode */
251 struct radeon_native_mode native_mode; 241 struct drm_display_mode native_mode;
252}; 242};
253 243
254struct radeon_encoder_tv_dac { 244struct radeon_encoder_tv_dac {
@@ -271,6 +261,16 @@ struct radeon_encoder_int_tmds {
271 struct radeon_tmds_pll tmds_pll[4]; 261 struct radeon_tmds_pll tmds_pll[4];
272}; 262};
273 263
264/* spread spectrum */
265struct radeon_atom_ss {
266 uint16_t percentage;
267 uint8_t type;
268 uint8_t step;
269 uint8_t delay;
270 uint8_t range;
271 uint8_t refdiv;
272};
273
274struct radeon_encoder_atom_dig { 274struct radeon_encoder_atom_dig {
275 /* atom dig */ 275 /* atom dig */
276 bool coherent_mode; 276 bool coherent_mode;
@@ -278,8 +278,9 @@ struct radeon_encoder_atom_dig {
278 /* atom lvds */ 278 /* atom lvds */
279 uint32_t lvds_misc; 279 uint32_t lvds_misc;
280 uint16_t panel_pwr_delay; 280 uint16_t panel_pwr_delay;
281 struct radeon_atom_ss *ss;
281 /* panel mode */ 282 /* panel mode */
282 struct radeon_native_mode native_mode; 283 struct drm_display_mode native_mode;
283}; 284};
284 285
285struct radeon_encoder_atom_dac { 286struct radeon_encoder_atom_dac {
@@ -294,7 +295,7 @@ struct radeon_encoder {
294 uint32_t flags; 295 uint32_t flags;
295 uint32_t pixel_clock; 296 uint32_t pixel_clock;
296 enum radeon_rmx_type rmx_type; 297 enum radeon_rmx_type rmx_type;
297 struct radeon_native_mode native_mode; 298 struct drm_display_mode native_mode;
298 void *enc_priv; 299 void *enc_priv;
299}; 300};
300 301
@@ -308,12 +309,15 @@ struct radeon_connector {
308 uint32_t connector_id; 309 uint32_t connector_id;
309 uint32_t devices; 310 uint32_t devices;
310 struct radeon_i2c_chan *ddc_bus; 311 struct radeon_i2c_chan *ddc_bus;
312 /* some systems have a an hdmi and vga port with a shared ddc line */
313 bool shared_ddc;
311 bool use_digital; 314 bool use_digital;
312 /* we need to mind the EDID between detect 315 /* we need to mind the EDID between detect
313 and get modes due to analog/digital/tvencoder */ 316 and get modes due to analog/digital/tvencoder */
314 struct edid *edid; 317 struct edid *edid;
315 void *con_priv; 318 void *con_priv;
316 bool dac_load_detect; 319 bool dac_load_detect;
320 uint16_t connector_object_id;
317}; 321};
318 322
319struct radeon_framebuffer { 323struct radeon_framebuffer {
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
new file mode 100644
index 00000000000..46146c6a2a0
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -0,0 +1,65 @@
1/*
2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
8 *
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
19 *
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 */
22#include "drmP.h"
23#include "radeon.h"
24
25int radeon_debugfs_pm_init(struct radeon_device *rdev);
26
27int radeon_pm_init(struct radeon_device *rdev)
28{
29 if (radeon_debugfs_pm_init(rdev)) {
30 DRM_ERROR("Failed to register debugfs file for CP !\n");
31 }
32
33 return 0;
34}
35
36/*
37 * Debugfs info
38 */
39#if defined(CONFIG_DEBUG_FS)
40
41static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
42{
43 struct drm_info_node *node = (struct drm_info_node *) m->private;
44 struct drm_device *dev = node->minor->dev;
45 struct radeon_device *rdev = dev->dev_private;
46
47 seq_printf(m, "engine clock: %u0 Hz\n", radeon_get_engine_clock(rdev));
48 seq_printf(m, "memory clock: %u0 Hz\n", radeon_get_memory_clock(rdev));
49
50 return 0;
51}
52
53static struct drm_info_list radeon_pm_info_list[] = {
54 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
55};
56#endif
57
58int radeon_debugfs_pm_init(struct radeon_device *rdev)
59{
60#if defined(CONFIG_DEBUG_FS)
61 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
62#else
63 return 0;
64#endif
65}
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index bfa1ab9c93e..29ab75903ec 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -290,6 +290,8 @@
290#define RADEON_BUS_CNTL 0x0030 290#define RADEON_BUS_CNTL 0x0030
291# define RADEON_BUS_MASTER_DIS (1 << 6) 291# define RADEON_BUS_MASTER_DIS (1 << 6)
292# define RADEON_BUS_BIOS_DIS_ROM (1 << 12) 292# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
293# define RS600_BUS_MASTER_DIS (1 << 14)
294# define RS600_MSI_REARM (1 << 20) /* rs600/rs690/rs740 */
293# define RADEON_BUS_RD_DISCARD_EN (1 << 24) 295# define RADEON_BUS_RD_DISCARD_EN (1 << 24)
294# define RADEON_BUS_RD_ABORT_EN (1 << 25) 296# define RADEON_BUS_RD_ABORT_EN (1 << 25)
295# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28) 297# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
@@ -297,6 +299,9 @@
297# define RADEON_BUS_READ_BURST (1 << 30) 299# define RADEON_BUS_READ_BURST (1 << 30)
298#define RADEON_BUS_CNTL1 0x0034 300#define RADEON_BUS_CNTL1 0x0034
299# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4) 301# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
302/* rv370/rv380, rv410, r423/r430/r480, r5xx */
303#define RADEON_MSI_REARM_EN 0x0160
304# define RV370_MSI_REARM_EN (1 << 0)
300 305
301/* #define RADEON_PCIE_INDEX 0x0030 */ 306/* #define RADEON_PCIE_INDEX 0x0030 */
302/* #define RADEON_PCIE_DATA 0x0034 */ 307/* #define RADEON_PCIE_DATA 0x0034 */
@@ -3311,6 +3316,7 @@
3311#define RADEON_AIC_CNTL 0x01d0 3316#define RADEON_AIC_CNTL 0x01d0
3312# define RADEON_PCIGART_TRANSLATE_EN (1 << 0) 3317# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
3313# define RADEON_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1) 3318# define RADEON_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1)
3319# define RS400_MSI_REARM (1 << 3) /* rs400/rs480 */
3314#define RADEON_AIC_LO_ADDR 0x01dc 3320#define RADEON_AIC_LO_ADDR 0x01dc
3315#define RADEON_AIC_PT_BASE 0x01d8 3321#define RADEON_AIC_PT_BASE 0x01d8
3316#define RADEON_AIC_HI_ADDR 0x01e0 3322#define RADEON_AIC_HI_ADDR 0x01e0
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index 03c33cf4e14..f8a465d9a1c 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -42,7 +42,7 @@ void radeon_test_moves(struct radeon_device *rdev)
42 /* Number of tests = 42 /* Number of tests =
43 * (Total GTT - IB pool - writeback page - ring buffer) / test size 43 * (Total GTT - IB pool - writeback page - ring buffer) / test size
44 */ 44 */
45 n = (rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - 4096 - 45 n = (rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - RADEON_GPU_PAGE_SIZE -
46 rdev->cp.ring_size) / size; 46 rdev->cp.ring_size) / size;
47 47
48 gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL); 48 gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
@@ -102,7 +102,7 @@ void radeon_test_moves(struct radeon_device *rdev)
102 goto out_cleanup; 102 goto out_cleanup;
103 } 103 }
104 104
105 r = radeon_copy(rdev, gtt_addr, vram_addr, size / 4096, fence); 105 r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, fence);
106 if (r) { 106 if (r) {
107 DRM_ERROR("Failed GTT->VRAM copy %d\n", i); 107 DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
108 goto out_cleanup; 108 goto out_cleanup;
@@ -145,7 +145,7 @@ void radeon_test_moves(struct radeon_device *rdev)
145 goto out_cleanup; 145 goto out_cleanup;
146 } 146 }
147 147
148 r = radeon_copy(rdev, vram_addr, gtt_addr, size / 4096, fence); 148 r = radeon_copy(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, fence);
149 if (r) { 149 if (r) {
150 DRM_ERROR("Failed VRAM->GTT copy %d\n", i); 150 DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
151 goto out_cleanup; 151 goto out_cleanup;
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 765bd184b6f..1381e06d6af 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -295,6 +295,12 @@ static int radeon_move_vram_ram(struct ttm_buffer_object *bo,
295 if (unlikely(r)) { 295 if (unlikely(r)) {
296 return r; 296 return r;
297 } 297 }
298
299 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
300 if (unlikely(r)) {
301 goto out_cleanup;
302 }
303
298 r = ttm_tt_bind(bo->ttm, &tmp_mem); 304 r = ttm_tt_bind(bo->ttm, &tmp_mem);
299 if (unlikely(r)) { 305 if (unlikely(r)) {
300 goto out_cleanup; 306 goto out_cleanup;
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index a769c296f6a..ca037160a58 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -418,6 +418,8 @@ int rs400_resume(struct radeon_device *rdev)
418 rs400_gart_disable(rdev); 418 rs400_gart_disable(rdev);
419 /* Resume clock before doing reset */ 419 /* Resume clock before doing reset */
420 r300_clock_startup(rdev); 420 r300_clock_startup(rdev);
421 /* setup MC before calling post tables */
422 rs400_mc_program(rdev);
421 /* Reset gpu before posting otherwise ATOM will enter infinite loop */ 423 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
422 if (radeon_gpu_reset(rdev)) { 424 if (radeon_gpu_reset(rdev)) {
423 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", 425 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 10dfa78762d..5f117cd8736 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -242,7 +242,7 @@ void rs600_irq_disable(struct radeon_device *rdev)
242 242
243int rs600_irq_process(struct radeon_device *rdev) 243int rs600_irq_process(struct radeon_device *rdev)
244{ 244{
245 uint32_t status; 245 uint32_t status, msi_rearm;
246 uint32_t r500_disp_int; 246 uint32_t r500_disp_int;
247 247
248 status = rs600_irq_ack(rdev, &r500_disp_int); 248 status = rs600_irq_ack(rdev, &r500_disp_int);
@@ -260,6 +260,22 @@ int rs600_irq_process(struct radeon_device *rdev)
260 drm_handle_vblank(rdev->ddev, 1); 260 drm_handle_vblank(rdev->ddev, 1);
261 status = rs600_irq_ack(rdev, &r500_disp_int); 261 status = rs600_irq_ack(rdev, &r500_disp_int);
262 } 262 }
263 if (rdev->msi_enabled) {
264 switch (rdev->family) {
265 case CHIP_RS600:
266 case CHIP_RS690:
267 case CHIP_RS740:
268 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
269 WREG32(RADEON_BUS_CNTL, msi_rearm);
270 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
271 break;
272 default:
273 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
274 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
275 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
276 break;
277 }
278 }
263 return IRQ_HANDLED; 279 return IRQ_HANDLED;
264} 280}
265 281
@@ -472,6 +488,8 @@ int rs600_init(struct radeon_device *rdev)
472 } 488 }
473 /* Initialize clocks */ 489 /* Initialize clocks */
474 radeon_get_clock_info(rdev->ddev); 490 radeon_get_clock_info(rdev->ddev);
491 /* Initialize power management */
492 radeon_pm_init(rdev);
475 /* Get vram informations */ 493 /* Get vram informations */
476 rs600_vram_info(rdev); 494 rs600_vram_info(rdev);
477 /* Initialize memory controller (also test AGP) */ 495 /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 025e3225346..27547175cf9 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -706,6 +706,8 @@ int rs690_init(struct radeon_device *rdev)
706 } 706 }
707 /* Initialize clocks */ 707 /* Initialize clocks */
708 radeon_get_clock_info(rdev->ddev); 708 radeon_get_clock_info(rdev->ddev);
709 /* Initialize power management */
710 radeon_pm_init(rdev);
709 /* Get vram informations */ 711 /* Get vram informations */
710 rs690_vram_info(rdev); 712 rs690_vram_info(rdev);
711 /* Initialize memory controller (also test AGP) */ 713 /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 41a34c23e6d..ba68c9fe90a 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -380,7 +380,6 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
380 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL); 380 save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
381 381
382 /* Stop all video */ 382 /* Stop all video */
383 WREG32(R_000330_D1VGA_CONTROL, 0);
384 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 383 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
385 WREG32(R_000300_VGA_RENDER_CONTROL, 0); 384 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
386 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 385 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
@@ -389,6 +388,8 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
389 WREG32(R_006880_D2CRTC_CONTROL, 0); 388 WREG32(R_006880_D2CRTC_CONTROL, 0);
390 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 389 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
391 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 390 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
391 WREG32(R_000330_D1VGA_CONTROL, 0);
392 WREG32(R_000338_D2VGA_CONTROL, 0);
392} 393}
393 394
394void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 395void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -402,14 +403,14 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
402 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control); 403 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
403 mdelay(1); 404 mdelay(1);
404 /* Restore video state */ 405 /* Restore video state */
406 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
407 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
405 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1); 408 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
406 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1); 409 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
407 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control); 410 WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
408 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control); 411 WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
409 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0); 412 WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
410 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0); 413 WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
411 WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
412 WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
413 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control); 414 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
414} 415}
415 416
@@ -585,6 +586,8 @@ int rv515_init(struct radeon_device *rdev)
585 } 586 }
586 /* Initialize clocks */ 587 /* Initialize clocks */
587 radeon_get_clock_info(rdev->ddev); 588 radeon_get_clock_info(rdev->ddev);
589 /* Initialize power management */
590 radeon_pm_init(rdev);
588 /* Get vram informations */ 591 /* Get vram informations */
589 rv515_vram_info(rdev); 592 rv515_vram_info(rdev);
590 /* Initialize memory controller (also test AGP) */ 593 /* Initialize memory controller (also test AGP) */
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 595ac638039..b0efd0ddae7 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -529,11 +529,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
529 if (rdev->family == CHIP_RV770) 529 if (rdev->family == CHIP_RV770)
530 gb_tiling_config |= BANK_TILING(1); 530 gb_tiling_config |= BANK_TILING(1);
531 else 531 else
532 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_SHIFT) >> NOOFBANK_MASK); 532 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
533 533
534 gb_tiling_config |= GROUP_SIZE(0); 534 gb_tiling_config |= GROUP_SIZE(0);
535 535
536 if (((mc_arb_ramcfg & NOOFROWS_MASK) & NOOFROWS_SHIFT) > 3) { 536 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
537 gb_tiling_config |= ROW_TILING(3); 537 gb_tiling_config |= ROW_TILING(3);
538 gb_tiling_config |= SAMPLE_SPLIT(3); 538 gb_tiling_config |= SAMPLE_SPLIT(3);
539 } else { 539 } else {
@@ -579,14 +579,14 @@ static void rv770_gpu_init(struct radeon_device *rdev)
579 579
580 /* set HW defaults for 3D engine */ 580 /* set HW defaults for 3D engine */
581 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | 581 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
582 ROQ_IB2_START(0x2b))); 582 ROQ_IB2_START(0x2b)));
583 583
584 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); 584 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
585 585
586 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | 586 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
587 SYNC_GRADIENT | 587 SYNC_GRADIENT |
588 SYNC_WALKER | 588 SYNC_WALKER |
589 SYNC_ALIGNER)); 589 SYNC_ALIGNER));
590 590
591 sx_debug_1 = RREG32(SX_DEBUG_1); 591 sx_debug_1 = RREG32(SX_DEBUG_1);
592 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; 592 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
@@ -598,9 +598,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
598 WREG32(SMX_DC_CTL0, smx_dc_ctl0); 598 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
599 599
600 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | 600 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
601 GS_FLUSH_CTL(4) | 601 GS_FLUSH_CTL(4) |
602 ACK_FLUSH_CTL(3) | 602 ACK_FLUSH_CTL(3) |
603 SYNC_FLUSH_CTL)); 603 SYNC_FLUSH_CTL));
604 604
605 if (rdev->family == CHIP_RV770) 605 if (rdev->family == CHIP_RV770)
606 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f)); 606 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
@@ -611,12 +611,12 @@ static void rv770_gpu_init(struct radeon_device *rdev)
611 } 611 }
612 612
613 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | 613 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
614 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | 614 POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
615 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); 615 SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
616 616
617 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | 617 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
618 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | 618 SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
619 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); 619 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
620 620
621 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); 621 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
622 622
@@ -774,14 +774,36 @@ int rv770_mc_init(struct radeon_device *rdev)
774{ 774{
775 fixed20_12 a; 775 fixed20_12 a;
776 u32 tmp; 776 u32 tmp;
777 int chansize, numchan;
777 int r; 778 int r;
778 779
779 /* Get VRAM informations */ 780 /* Get VRAM informations */
780 /* FIXME: Don't know how to determine vram width, need to check
781 * vram_width usage
782 */
783 rdev->mc.vram_width = 128;
784 rdev->mc.vram_is_ddr = true; 781 rdev->mc.vram_is_ddr = true;
782 tmp = RREG32(MC_ARB_RAMCFG);
783 if (tmp & CHANSIZE_OVERRIDE) {
784 chansize = 16;
785 } else if (tmp & CHANSIZE_MASK) {
786 chansize = 64;
787 } else {
788 chansize = 32;
789 }
790 tmp = RREG32(MC_SHARED_CHMAP);
791 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
792 case 0:
793 default:
794 numchan = 1;
795 break;
796 case 1:
797 numchan = 2;
798 break;
799 case 2:
800 numchan = 4;
801 break;
802 case 3:
803 numchan = 8;
804 break;
805 }
806 rdev->mc.vram_width = numchan * chansize;
785 /* Could aper size report 0 ? */ 807 /* Could aper size report 0 ? */
786 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); 808 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
787 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); 809 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
@@ -961,10 +983,13 @@ int rv770_init(struct radeon_device *rdev)
961 r600_scratch_init(rdev); 983 r600_scratch_init(rdev);
962 /* Initialize surface registers */ 984 /* Initialize surface registers */
963 radeon_surface_init(rdev); 985 radeon_surface_init(rdev);
986 /* Initialize clocks */
964 radeon_get_clock_info(rdev->ddev); 987 radeon_get_clock_info(rdev->ddev);
965 r = radeon_clocks_init(rdev); 988 r = radeon_clocks_init(rdev);
966 if (r) 989 if (r)
967 return r; 990 return r;
991 /* Initialize power management */
992 radeon_pm_init(rdev);
968 /* Fence driver */ 993 /* Fence driver */
969 r = radeon_fence_driver_init(rdev); 994 r = radeon_fence_driver_init(rdev);
970 if (r) 995 if (r)
diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 4b9c3d6396f..a1367ab6f26 100644
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -129,6 +129,10 @@
129#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 129#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
130#define HDP_TILING_CONFIG 0x2F3C 130#define HDP_TILING_CONFIG 0x2F3C
131 131
132#define MC_SHARED_CHMAP 0x2004
133#define NOOFCHAN_SHIFT 12
134#define NOOFCHAN_MASK 0x00003000
135
132#define MC_ARB_RAMCFG 0x2760 136#define MC_ARB_RAMCFG 0x2760
133#define NOOFBANK_SHIFT 0 137#define NOOFBANK_SHIFT 0
134#define NOOFBANK_MASK 0x00000003 138#define NOOFBANK_MASK 0x00000003
@@ -142,6 +146,7 @@
142#define CHANSIZE_MASK 0x00000100 146#define CHANSIZE_MASK 0x00000100
143#define BURSTLENGTH_SHIFT 9 147#define BURSTLENGTH_SHIFT 9
144#define BURSTLENGTH_MASK 0x00000200 148#define BURSTLENGTH_MASK 0x00000200
149#define CHANSIZE_OVERRIDE (1 << 11)
145#define MC_VM_AGP_TOP 0x2028 150#define MC_VM_AGP_TOP 0x2028
146#define MC_VM_AGP_BOT 0x202C 151#define MC_VM_AGP_BOT 0x202C
147#define MC_VM_AGP_BASE 0x2030 152#define MC_VM_AGP_BASE 0x2030
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index a55ee1a56c1..7bcb89f39ce 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -279,6 +279,7 @@ int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement)
279 279
280 return ttm_tt_set_caching(ttm, state); 280 return ttm_tt_set_caching(ttm, state);
281} 281}
282EXPORT_SYMBOL(ttm_tt_set_placement_caching);
282 283
283static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm) 284static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm)
284{ 285{
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 06:27:06 -0400