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-rw-r--r--drivers/gpu/drm/i915/i915_gem.c29
1 files changed, 3 insertions, 26 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c73da4049c8..302e096c3ca 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2460,39 +2460,16 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2460 */ 2460 */
2461 drm_gem_object_reference(old_obj); 2461 drm_gem_object_reference(old_obj);
2462 2462
2463 /* i915 uses fences for GPU access to tiled buffers */
2464 if (IS_I965G(dev) || !old_obj_priv->active)
2465 break;
2466
2467 /* This brings the object to the head of the LRU if it
2468 * had been written to. The only way this should
2469 * result in us waiting longer than the expected
2470 * optimal amount of time is if there was a
2471 * fence-using buffer later that was read-only.
2472 */
2473 i915_gem_object_flush_gpu_write_domain(old_obj);
2474 ret = i915_gem_object_wait_rendering(old_obj);
2475 if (ret != 0) {
2476 drm_gem_object_unreference(old_obj);
2477 return ret;
2478 }
2479
2480 break; 2463 break;
2481 } 2464 }
2482 2465
2483 /*
2484 * Zap this virtual mapping so we can set up a fence again
2485 * for this object next time we need it.
2486 */
2487 i915_gem_release_mmap(old_obj);
2488
2489 i = old_obj_priv->fence_reg; 2466 i = old_obj_priv->fence_reg;
2490 reg = &dev_priv->fence_regs[i]; 2467 reg = &dev_priv->fence_regs[i];
2491 2468
2492 old_obj_priv->fence_reg = I915_FENCE_REG_NONE; 2469 ret = i915_gem_object_put_fence_reg(old_obj);
2493 list_del_init(&old_obj_priv->fence_list);
2494
2495 drm_gem_object_unreference(old_obj); 2470 drm_gem_object_unreference(old_obj);
2471 if (ret != 0)
2472 return ret;
2496 } 2473 }
2497 2474
2498 obj_priv->fence_reg = i; 2475 obj_priv->fence_reg = i;