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-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c22
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_calc.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_mem.c18
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_reg.h90
-rw-r--r--drivers/gpu/drm/nouveau/nv40_mc.c2
-rw-r--r--drivers/gpu/drm/nouveau/nvreg.h22
6 files changed, 82 insertions, 76 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 31183a41b8d..382977cc2e4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -2129,10 +2129,10 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2129 * This also has probably been done in the scripts, but an mmio trace of 2129 * This also has probably been done in the scripts, but an mmio trace of
2130 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write) 2130 * s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
2131 */ 2131 */
2132 bios_wr32(bios, NV_PFB_REFCTRL, NV_PFB_REFCTRL_VALID_1); 2132 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2133 2133
2134 /* write back the saved configuration value */ 2134 /* write back the saved configuration value */
2135 bios_wr32(bios, NV_PFB_CFG0, bios->state.saved_nv_pfb_cfg0); 2135 bios_wr32(bios, NV04_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
2136 2136
2137 return 1; 2137 return 1;
2138} 2138}
@@ -2209,14 +2209,14 @@ init_configure_mem(struct nvbios *bios, uint16_t offset,
2209 reg = ROM32(bios->data[seqtbloffs += 4])) { 2209 reg = ROM32(bios->data[seqtbloffs += 4])) {
2210 2210
2211 switch (reg) { 2211 switch (reg) {
2212 case NV_PFB_PRE: 2212 case NV04_PFB_PRE:
2213 data = NV_PFB_PRE_CMD_PRECHARGE; 2213 data = NV04_PFB_PRE_CMD_PRECHARGE;
2214 break; 2214 break;
2215 case NV_PFB_PAD: 2215 case NV04_PFB_PAD:
2216 data = NV_PFB_PAD_CKE_NORMAL; 2216 data = NV04_PFB_PAD_CKE_NORMAL;
2217 break; 2217 break;
2218 case NV_PFB_REF: 2218 case NV04_PFB_REF:
2219 data = NV_PFB_REF_CMD_REFRESH; 2219 data = NV04_PFB_REF_CMD_REFRESH;
2220 break; 2220 break;
2221 default: 2221 default:
2222 data = ROM32(bios->data[meminitdata]); 2222 data = ROM32(bios->data[meminitdata]);
@@ -2418,7 +2418,7 @@ init_ram_condition(struct nvbios *bios, uint16_t offset,
2418 * offset + 1 (8 bit): mask 2418 * offset + 1 (8 bit): mask
2419 * offset + 2 (8 bit): cmpval 2419 * offset + 2 (8 bit): cmpval
2420 * 2420 *
2421 * Test if (NV_PFB_BOOT_0 & "mask") equals "cmpval". 2421 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2422 * If condition not met skip subsequent opcodes until condition is 2422 * If condition not met skip subsequent opcodes until condition is
2423 * inverted (INIT_NOT), or we hit INIT_RESUME 2423 * inverted (INIT_NOT), or we hit INIT_RESUME
2424 */ 2424 */
@@ -2430,7 +2430,7 @@ init_ram_condition(struct nvbios *bios, uint16_t offset,
2430 if (!iexec->execute) 2430 if (!iexec->execute)
2431 return 3; 2431 return 3;
2432 2432
2433 data = bios_rd32(bios, NV_PFB_BOOT_0) & mask; 2433 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
2434 2434
2435 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n", 2435 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2436 offset, data, cmpval); 2436 offset, data, cmpval);
@@ -6343,7 +6343,7 @@ nouveau_bios_init(struct drm_device *dev)
6343 6343
6344 /* these will need remembering across a suspend */ 6344 /* these will need remembering across a suspend */
6345 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0); 6345 saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
6346 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV_PFB_CFG0); 6346 bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV04_PFB_CFG0);
6347 6347
6348 /* init script execution disabled */ 6348 /* init script execution disabled */
6349 bios->execute = false; 6349 bios->execute = false;
diff --git a/drivers/gpu/drm/nouveau/nouveau_calc.c b/drivers/gpu/drm/nouveau/nouveau_calc.c
index 88f9bc0941e..ca85da78484 100644
--- a/drivers/gpu/drm/nouveau/nouveau_calc.c
+++ b/drivers/gpu/drm/nouveau/nouveau_calc.c
@@ -200,7 +200,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
200 struct nv_sim_state sim_data; 200 struct nv_sim_state sim_data;
201 int MClk = nouveau_hw_get_clock(dev, MPLL); 201 int MClk = nouveau_hw_get_clock(dev, MPLL);
202 int NVClk = nouveau_hw_get_clock(dev, NVPLL); 202 int NVClk = nouveau_hw_get_clock(dev, NVPLL);
203 uint32_t cfg1 = nvReadFB(dev, NV_PFB_CFG1); 203 uint32_t cfg1 = nvReadFB(dev, NV04_PFB_CFG1);
204 204
205 sim_data.pclk_khz = VClk; 205 sim_data.pclk_khz = VClk;
206 sim_data.mclk_khz = MClk; 206 sim_data.mclk_khz = MClk;
@@ -218,7 +218,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
218 sim_data.mem_latency = 3; 218 sim_data.mem_latency = 3;
219 sim_data.mem_page_miss = 10; 219 sim_data.mem_page_miss = 10;
220 } else { 220 } else {
221 sim_data.memory_type = nvReadFB(dev, NV_PFB_CFG0) & 0x1; 221 sim_data.memory_type = nvReadFB(dev, NV04_PFB_CFG0) & 0x1;
222 sim_data.memory_width = (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; 222 sim_data.memory_width = (nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64;
223 sim_data.mem_latency = cfg1 & 0xf; 223 sim_data.mem_latency = cfg1 & 0xf;
224 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); 224 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 5c48b1e02ca..568bcc21216 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -260,19 +260,19 @@ nouveau_mem_close(struct drm_device *dev)
260static uint32_t 260static uint32_t
261nouveau_mem_detect_nv04(struct drm_device *dev) 261nouveau_mem_detect_nv04(struct drm_device *dev)
262{ 262{
263 uint32_t boot0 = nv_rd32(dev, NV03_BOOT_0); 263 uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
264 264
265 if (boot0 & 0x00000100) 265 if (boot0 & 0x00000100)
266 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024; 266 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
267 267
268 switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) { 268 switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
269 case NV04_BOOT_0_RAM_AMOUNT_32MB: 269 case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
270 return 32 * 1024 * 1024; 270 return 32 * 1024 * 1024;
271 case NV04_BOOT_0_RAM_AMOUNT_16MB: 271 case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
272 return 16 * 1024 * 1024; 272 return 16 * 1024 * 1024;
273 case NV04_BOOT_0_RAM_AMOUNT_8MB: 273 case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
274 return 8 * 1024 * 1024; 274 return 8 * 1024 * 1024;
275 case NV04_BOOT_0_RAM_AMOUNT_4MB: 275 case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
276 return 4 * 1024 * 1024; 276 return 4 * 1024 * 1024;
277 } 277 }
278 278
@@ -318,10 +318,10 @@ nouveau_mem_detect(struct drm_device *dev)
318 dev_priv->vram_size = nouveau_mem_detect_nforce(dev); 318 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
319 } else 319 } else
320 if (dev_priv->card_type < NV_50) { 320 if (dev_priv->card_type < NV_50) {
321 dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA); 321 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
322 dev_priv->vram_size &= NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK; 322 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
323 } else { 323 } else {
324 dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA); 324 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
325 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32; 325 dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
326 dev_priv->vram_size &= 0xffffffff00ll; 326 dev_priv->vram_size &= 0xffffffff00ll;
327 if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) { 327 if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) {
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index b6391a132f0..9c1056cb8a9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -1,19 +1,64 @@
1 1
2#define NV04_PFB_BOOT_0 0x00100000
3# define NV04_PFB_BOOT_0_RAM_AMOUNT 0x00000003
4# define NV04_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000
5# define NV04_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001
6# define NV04_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002
7# define NV04_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003
8# define NV04_PFB_BOOT_0_RAM_WIDTH_128 0x00000004
9# define NV04_PFB_BOOT_0_RAM_TYPE 0x00000028
10# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT 0x00000000
11# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT 0x00000008
12# define NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT_4BANK 0x00000010
13# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT 0x00000018
14# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBIT 0x00000020
15# define NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_64MBITX16 0x00000028
16# define NV04_PFB_BOOT_0_UMA_ENABLE 0x00000100
17# define NV04_PFB_BOOT_0_UMA_SIZE 0x0000f000
18#define NV04_PFB_DEBUG_0 0x00100080
19# define NV04_PFB_DEBUG_0_PAGE_MODE 0x00000001
20# define NV04_PFB_DEBUG_0_REFRESH_OFF 0x00000010
21# define NV04_PFB_DEBUG_0_REFRESH_COUNTX64 0x00003f00
22# define NV04_PFB_DEBUG_0_REFRESH_SLOW_CLK 0x00004000
23# define NV04_PFB_DEBUG_0_SAFE_MODE 0x00008000
24# define NV04_PFB_DEBUG_0_ALOM_ENABLE 0x00010000
25# define NV04_PFB_DEBUG_0_CASOE 0x00100000
26# define NV04_PFB_DEBUG_0_CKE_INVERT 0x10000000
27# define NV04_PFB_DEBUG_0_REFINC 0x20000000
28# define NV04_PFB_DEBUG_0_SAVE_POWER_OFF 0x40000000
29#define NV04_PFB_CFG0 0x00100200
30# define NV04_PFB_CFG0_SCRAMBLE 0x20000000
31#define NV04_PFB_CFG1 0x00100204
32#define NV04_PFB_FIFO_DATA 0x0010020c
33# define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
34# define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
35#define NV10_PFB_REFCTRL 0x00100210
36# define NV10_PFB_REFCTRL_VALID_1 (1 << 31)
37#define NV04_PFB_PAD 0x0010021c
38# define NV04_PFB_PAD_CKE_NORMAL (1 << 0)
39#define NV10_PFB_TILE(i) (0x00100240 + (i*16))
40#define NV10_PFB_TILE__SIZE 8
41#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))
42#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))
43#define NV10_PFB_TSTATUS(i) (0x0010024c + (i*16))
44#define NV04_PFB_REF 0x001002d0
45# define NV04_PFB_REF_CMD_REFRESH (1 << 0)
46#define NV04_PFB_PRE 0x001002d4
47# define NV04_PFB_PRE_CMD_PRECHARGE (1 << 0)
48#define NV10_PFB_CLOSE_PAGE2 0x0010033c
49#define NV04_PFB_SCRAMBLE(i) (0x00100400 + 4 * (i))
50#define NV40_PFB_TILE(i) (0x00100600 + (i*16))
51#define NV40_PFB_TILE__SIZE_0 12
52#define NV40_PFB_TILE__SIZE_1 15
53#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))
54#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))
55#define NV40_PFB_TSTATUS(i) (0x0010060c + (i*16))
56#define NV40_PFB_UNK_800 0x00100800
2 57
3#define NV03_BOOT_0 0x00100000 58#define NV_PEXTDEV_BOOT_0 0x00101000
4# define NV03_BOOT_0_RAM_AMOUNT 0x00000003 59#define NV_PEXTDEV_BOOT_0_RAMCFG 0x0000003c
5# define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000 60# define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (8 << 12)
6# define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001 61#define NV_PEXTDEV_BOOT_3 0x0010100c
7# define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002
8# define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003
9# define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000
10# define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001
11# define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002
12# define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003
13
14#define NV04_FIFO_DATA 0x0010020c
15# define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
16# define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
17 62
18#define NV_RAMIN 0x00700000 63#define NV_RAMIN 0x00700000
19 64
@@ -131,23 +176,6 @@
131#define NV04_PTIMER_TIME_1 0x00009410 176#define NV04_PTIMER_TIME_1 0x00009410
132#define NV04_PTIMER_ALARM_0 0x00009420 177#define NV04_PTIMER_ALARM_0 0x00009420
133 178
134#define NV04_PFB_CFG0 0x00100200
135#define NV04_PFB_CFG1 0x00100204
136#define NV40_PFB_020C 0x0010020C
137#define NV10_PFB_TILE(i) (0x00100240 + (i*16))
138#define NV10_PFB_TILE__SIZE 8
139#define NV10_PFB_TLIMIT(i) (0x00100244 + (i*16))
140#define NV10_PFB_TSIZE(i) (0x00100248 + (i*16))
141#define NV10_PFB_TSTATUS(i) (0x0010024C + (i*16))
142#define NV10_PFB_CLOSE_PAGE2 0x0010033C
143#define NV40_PFB_TILE(i) (0x00100600 + (i*16))
144#define NV40_PFB_TILE__SIZE_0 12
145#define NV40_PFB_TILE__SIZE_1 15
146#define NV40_PFB_TLIMIT(i) (0x00100604 + (i*16))
147#define NV40_PFB_TSIZE(i) (0x00100608 + (i*16))
148#define NV40_PFB_TSTATUS(i) (0x0010060C + (i*16))
149#define NV40_PFB_UNK_800 0x00100800
150
151#define NV04_PGRAPH_DEBUG_0 0x00400080 179#define NV04_PGRAPH_DEBUG_0 0x00400080
152#define NV04_PGRAPH_DEBUG_1 0x00400084 180#define NV04_PGRAPH_DEBUG_1 0x00400084
153#define NV04_PGRAPH_DEBUG_2 0x00400088 181#define NV04_PGRAPH_DEBUG_2 0x00400088
diff --git a/drivers/gpu/drm/nouveau/nv40_mc.c b/drivers/gpu/drm/nouveau/nv40_mc.c
index 2a3495e848e..e4e72c12ab6 100644
--- a/drivers/gpu/drm/nouveau/nv40_mc.c
+++ b/drivers/gpu/drm/nouveau/nv40_mc.c
@@ -19,7 +19,7 @@ nv40_mc_init(struct drm_device *dev)
19 case 0x46: /* G72 */ 19 case 0x46: /* G72 */
20 case 0x4e: 20 case 0x4e:
21 case 0x4c: /* C51_G7X */ 21 case 0x4c: /* C51_G7X */
22 tmp = nv_rd32(dev, NV40_PFB_020C); 22 tmp = nv_rd32(dev, NV04_PFB_FIFO_DATA);
23 nv_wr32(dev, NV40_PMC_1700, tmp); 23 nv_wr32(dev, NV40_PMC_1700, tmp);
24 nv_wr32(dev, NV40_PMC_1704, 0); 24 nv_wr32(dev, NV40_PMC_1704, 0);
25 nv_wr32(dev, NV40_PMC_1708, 0); 25 nv_wr32(dev, NV40_PMC_1708, 0);
diff --git a/drivers/gpu/drm/nouveau/nvreg.h b/drivers/gpu/drm/nouveau/nvreg.h
index 5998c35237b..ad64673ace1 100644
--- a/drivers/gpu/drm/nouveau/nvreg.h
+++ b/drivers/gpu/drm/nouveau/nvreg.h
@@ -147,28 +147,6 @@
147# define NV_VIO_GX_DONT_CARE_INDEX 0x07 147# define NV_VIO_GX_DONT_CARE_INDEX 0x07
148# define NV_VIO_GX_BIT_MASK_INDEX 0x08 148# define NV_VIO_GX_BIT_MASK_INDEX 0x08
149 149
150#define NV_PFB_BOOT_0 0x00100000
151#define NV_PFB_CFG0 0x00100200
152#define NV_PFB_CFG1 0x00100204
153#define NV_PFB_CSTATUS 0x0010020C
154#define NV_PFB_REFCTRL 0x00100210
155# define NV_PFB_REFCTRL_VALID_1 (1 << 31)
156#define NV_PFB_PAD 0x0010021C
157# define NV_PFB_PAD_CKE_NORMAL (1 << 0)
158#define NV_PFB_TILE_NV10 0x00100240
159#define NV_PFB_TILE_SIZE_NV10 0x00100244
160#define NV_PFB_REF 0x001002D0
161# define NV_PFB_REF_CMD_REFRESH (1 << 0)
162#define NV_PFB_PRE 0x001002D4
163# define NV_PFB_PRE_CMD_PRECHARGE (1 << 0)
164#define NV_PFB_CLOSE_PAGE2 0x0010033C
165#define NV_PFB_TILE_NV40 0x00100600
166#define NV_PFB_TILE_SIZE_NV40 0x00100604
167
168#define NV_PEXTDEV_BOOT_0 0x00101000
169# define NV_PEXTDEV_BOOT_0_STRAP_FP_IFACE_12BIT (8 << 12)
170#define NV_PEXTDEV_BOOT_3 0x0010100c
171
172#define NV_PCRTC_INTR_0 0x00600100 150#define NV_PCRTC_INTR_0 0x00600100
173# define NV_PCRTC_INTR_0_VBLANK (1 << 0) 151# define NV_PCRTC_INTR_0_VBLANK (1 << 0)
174#define NV_PCRTC_INTR_EN_0 0x00600140 152#define NV_PCRTC_INTR_EN_0 0x00600140
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 14:00:47 -0400