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path: root/drivers/gpu/drm/radeon
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-rw-r--r--drivers/gpu/drm/radeon/Kconfig12
-rw-r--r--drivers/gpu/drm/radeon/Makefile5
-rw-r--r--drivers/gpu/drm/radeon/ObjectID.h801
-rw-r--r--drivers/gpu/drm/radeon/atom.c102
-rw-r--r--drivers/gpu/drm/radeon/atom.h1
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c259
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c39
-rw-r--r--drivers/gpu/drm/radeon/mkregtable.c4
-rw-r--r--drivers/gpu/drm/radeon/r100.c42
-rw-r--r--drivers/gpu/drm/radeon/r200.c7
-rw-r--r--drivers/gpu/drm/radeon/r300.c33
-rw-r--r--drivers/gpu/drm/radeon/r420.c48
-rw-r--r--drivers/gpu/drm/radeon/r520.c4
-rw-r--r--drivers/gpu/drm/radeon/r600.c207
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c5
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c25
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c83
-rw-r--r--drivers/gpu/drm/radeon/r600d.h25
-rw-r--r--drivers/gpu/drm/radeon/radeon.h29
-rw-r--r--drivers/gpu/drm/radeon/radeon_agp.c17
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h23
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c50
-rw-r--r--drivers/gpu/drm/radeon/radeon_benchmark.c55
-rw-r--r--drivers/gpu/drm/radeon/radeon_clocks.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_combios.c20
-rw-r--r--drivers/gpu/drm/radeon/radeon_connectors.c53
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c63
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c179
-rw-r--r--drivers/gpu/drm/radeon/radeon_fb.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c77
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_encoders.c21
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_tv.c14
-rw-r--r--drivers/gpu/drm/radeon/radeon_mode.h56
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_ttm.c5
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r2002
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r420795
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rs60068
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/rv5156
-rw-r--r--drivers/gpu/drm/radeon/rs400.c30
-rw-r--r--drivers/gpu/drm/radeon/rs600.c12
-rw-r--r--drivers/gpu/drm/radeon/rs690.c4
-rw-r--r--drivers/gpu/drm/radeon/rv515.c5
-rw-r--r--drivers/gpu/drm/radeon/rv770.c79
48 files changed, 2424 insertions, 974 deletions
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 5982321be4d..1c02d23f6fc 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,10 +1,14 @@
1config DRM_RADEON_KMS 1config DRM_RADEON_KMS
2 bool "Enable modesetting on radeon by default" 2 bool "Enable modesetting on radeon by default - NEW DRIVER"
3 depends on DRM_RADEON 3 depends on DRM_RADEON
4 help 4 help
5 Choose this option if you want kernel modesetting enabled by default, 5 Choose this option if you want kernel modesetting enabled by default.
6 and you have a new enough userspace to support this. Running old 6
7 userspaces with this enabled will cause pain. 7 This is a completely new driver. It's only part of the existing drm
8 for compatibility reasons. It requires an entirely different graphics
9 stack above it and works very differently from the old drm stack.
10 i.e. don't enable this unless you know what you are doing it may
11 cause issues or bugs compared to the previous userspace driver stack.
8 12
9 When kernel modesetting is enabled the IOCTL of radeon/drm 13 When kernel modesetting is enabled the IOCTL of radeon/drm
10 driver are considered as invalid and an error message is printed 14 driver are considered as invalid and an error message is printed
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index b5f5fe75e6a..1cc7b937b1e 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -24,6 +24,9 @@ $(obj)/rv515_reg_safe.h: $(src)/reg_srcs/rv515 $(obj)/mkregtable
24$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable 24$(obj)/r300_reg_safe.h: $(src)/reg_srcs/r300 $(obj)/mkregtable
25 $(call if_changed,mkregtable) 25 $(call if_changed,mkregtable)
26 26
27$(obj)/r420_reg_safe.h: $(src)/reg_srcs/r420 $(obj)/mkregtable
28 $(call if_changed,mkregtable)
29
27$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable 30$(obj)/rs600_reg_safe.h: $(src)/reg_srcs/rs600 $(obj)/mkregtable
28 $(call if_changed,mkregtable) 31 $(call if_changed,mkregtable)
29 32
@@ -35,6 +38,8 @@ $(obj)/rv515.o: $(obj)/rv515_reg_safe.h
35 38
36$(obj)/r300.o: $(obj)/r300_reg_safe.h 39$(obj)/r300.o: $(obj)/r300_reg_safe.h
37 40
41$(obj)/r420.o: $(obj)/r420_reg_safe.h
42
38$(obj)/rs600.o: $(obj)/rs600_reg_safe.h 43$(obj)/rs600.o: $(obj)/rs600_reg_safe.h
39 44
40radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ 45radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
diff --git a/drivers/gpu/drm/radeon/ObjectID.h b/drivers/gpu/drm/radeon/ObjectID.h
index 6d0183c61d3..c714179d1bf 100644
--- a/drivers/gpu/drm/radeon/ObjectID.h
+++ b/drivers/gpu/drm/radeon/ObjectID.h
@@ -1,5 +1,5 @@
1/* 1/*
2* Copyright 2006-2007 Advanced Micro Devices, Inc. 2* Copyright 2006-2007 Advanced Micro Devices, Inc.
3* 3*
4* Permission is hereby granted, free of charge, to any person obtaining a 4* Permission is hereby granted, free of charge, to any person obtaining a
5* copy of this software and associated documentation files (the "Software"), 5* copy of this software and associated documentation files (the "Software"),
@@ -41,14 +41,14 @@
41/****************************************************/ 41/****************************************************/
42/* Encoder Object ID Definition */ 42/* Encoder Object ID Definition */
43/****************************************************/ 43/****************************************************/
44#define ENCODER_OBJECT_ID_NONE 0x00 44#define ENCODER_OBJECT_ID_NONE 0x00
45 45
46/* Radeon Class Display Hardware */ 46/* Radeon Class Display Hardware */
47#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01 47#define ENCODER_OBJECT_ID_INTERNAL_LVDS 0x01
48#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02 48#define ENCODER_OBJECT_ID_INTERNAL_TMDS1 0x02
49#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03 49#define ENCODER_OBJECT_ID_INTERNAL_TMDS2 0x03
50#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04 50#define ENCODER_OBJECT_ID_INTERNAL_DAC1 0x04
51#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */ 51#define ENCODER_OBJECT_ID_INTERNAL_DAC2 0x05 /* TV/CV DAC */
52#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06 52#define ENCODER_OBJECT_ID_INTERNAL_SDVOA 0x06
53#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07 53#define ENCODER_OBJECT_ID_INTERNAL_SDVOB 0x07
54 54
@@ -56,11 +56,11 @@
56#define ENCODER_OBJECT_ID_SI170B 0x08 56#define ENCODER_OBJECT_ID_SI170B 0x08
57#define ENCODER_OBJECT_ID_CH7303 0x09 57#define ENCODER_OBJECT_ID_CH7303 0x09
58#define ENCODER_OBJECT_ID_CH7301 0x0A 58#define ENCODER_OBJECT_ID_CH7301 0x0A
59#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */ 59#define ENCODER_OBJECT_ID_INTERNAL_DVO1 0x0B /* This belongs to Radeon Class Display Hardware */
60#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C 60#define ENCODER_OBJECT_ID_EXTERNAL_SDVOA 0x0C
61#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D 61#define ENCODER_OBJECT_ID_EXTERNAL_SDVOB 0x0D
62#define ENCODER_OBJECT_ID_TITFP513 0x0E 62#define ENCODER_OBJECT_ID_TITFP513 0x0E
63#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */ 63#define ENCODER_OBJECT_ID_INTERNAL_LVTM1 0x0F /* not used for Radeon */
64#define ENCODER_OBJECT_ID_VT1623 0x10 64#define ENCODER_OBJECT_ID_VT1623 0x10
65#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11 65#define ENCODER_OBJECT_ID_HDMI_SI1930 0x11
66#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12 66#define ENCODER_OBJECT_ID_HDMI_INTERNAL 0x12
@@ -68,9 +68,9 @@
68#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13 68#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 0x13
69#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14 69#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 0x14
70#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15 70#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 0x15
71#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */ 71#define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 0x16 /* Shared with CV/TV and CRT */
72#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */ 72#define ENCODER_OBJECT_ID_SI178 0X17 /* External TMDS (dual link, no HDCP.) */
73#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */ 73#define ENCODER_OBJECT_ID_MVPU_FPGA 0x18 /* MVPU FPGA chip */
74#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19 74#define ENCODER_OBJECT_ID_INTERNAL_DDI 0x19
75#define ENCODER_OBJECT_ID_VT1625 0x1A 75#define ENCODER_OBJECT_ID_VT1625 0x1A
76#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B 76#define ENCODER_OBJECT_ID_HDMI_SI1932 0x1B
@@ -86,7 +86,7 @@
86/****************************************************/ 86/****************************************************/
87/* Connector Object ID Definition */ 87/* Connector Object ID Definition */
88/****************************************************/ 88/****************************************************/
89#define CONNECTOR_OBJECT_ID_NONE 0x00 89#define CONNECTOR_OBJECT_ID_NONE 0x00
90#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01 90#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I 0x01
91#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02 91#define CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I 0x02
92#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03 92#define CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 0x03
@@ -96,7 +96,7 @@
96#define CONNECTOR_OBJECT_ID_SVIDEO 0x07 96#define CONNECTOR_OBJECT_ID_SVIDEO 0x07
97#define CONNECTOR_OBJECT_ID_YPbPr 0x08 97#define CONNECTOR_OBJECT_ID_YPbPr 0x08
98#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09 98#define CONNECTOR_OBJECT_ID_D_CONNECTOR 0x09
99#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */ 99#define CONNECTOR_OBJECT_ID_9PIN_DIN 0x0A /* Supports both CV & TV */
100#define CONNECTOR_OBJECT_ID_SCART 0x0B 100#define CONNECTOR_OBJECT_ID_SCART 0x0B
101#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C 101#define CONNECTOR_OBJECT_ID_HDMI_TYPE_A 0x0C
102#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D 102#define CONNECTOR_OBJECT_ID_HDMI_TYPE_B 0x0D
@@ -106,6 +106,8 @@
106#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11 106#define CONNECTOR_OBJECT_ID_CROSSFIRE 0x11
107#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12 107#define CONNECTOR_OBJECT_ID_HARDCODE_DVI 0x12
108#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13 108#define CONNECTOR_OBJECT_ID_DISPLAYPORT 0x13
109#define CONNECTOR_OBJECT_ID_eDP 0x14
110#define CONNECTOR_OBJECT_ID_MXM 0x15
109 111
110/* deleted */ 112/* deleted */
111 113
@@ -116,6 +118,14 @@
116#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01 118#define ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL 0x01
117 119
118/****************************************************/ 120/****************************************************/
121/* Generic Object ID Definition */
122/****************************************************/
123#define GENERIC_OBJECT_ID_NONE 0x00
124#define GENERIC_OBJECT_ID_GLSYNC 0x01
125#define GENERIC_OBJECT_ID_PX2_NON_DRIVABLE 0x02
126#define GENERIC_OBJECT_ID_MXM_OPM 0x03
127
128/****************************************************/
119/* Graphics Object ENUM ID Definition */ 129/* Graphics Object ENUM ID Definition */
120/****************************************************/ 130/****************************************************/
121#define GRAPH_OBJECT_ENUM_ID1 0x01 131#define GRAPH_OBJECT_ENUM_ID1 0x01
@@ -124,6 +134,7 @@
124#define GRAPH_OBJECT_ENUM_ID4 0x04 134#define GRAPH_OBJECT_ENUM_ID4 0x04
125#define GRAPH_OBJECT_ENUM_ID5 0x05 135#define GRAPH_OBJECT_ENUM_ID5 0x05
126#define GRAPH_OBJECT_ENUM_ID6 0x06 136#define GRAPH_OBJECT_ENUM_ID6 0x06
137#define GRAPH_OBJECT_ENUM_ID7 0x07
127 138
128/****************************************************/ 139/****************************************************/
129/* Graphics Object ID Bit definition */ 140/* Graphics Object ID Bit definition */
@@ -133,35 +144,35 @@
133#define RESERVED1_ID_MASK 0x0800 144#define RESERVED1_ID_MASK 0x0800
134#define OBJECT_TYPE_MASK 0x7000 145#define OBJECT_TYPE_MASK 0x7000
135#define RESERVED2_ID_MASK 0x8000 146#define RESERVED2_ID_MASK 0x8000
136 147
137#define OBJECT_ID_SHIFT 0x00 148#define OBJECT_ID_SHIFT 0x00
138#define ENUM_ID_SHIFT 0x08 149#define ENUM_ID_SHIFT 0x08
139#define OBJECT_TYPE_SHIFT 0x0C 150#define OBJECT_TYPE_SHIFT 0x0C
140 151
152
141/****************************************************/ 153/****************************************************/
142/* Graphics Object family definition */ 154/* Graphics Object family definition */
143/****************************************************/ 155/****************************************************/
144#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) \ 156#define CONSTRUCTOBJECTFAMILYID(GRAPHICS_OBJECT_TYPE, GRAPHICS_OBJECT_ID) (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \
145 (GRAPHICS_OBJECT_TYPE << OBJECT_TYPE_SHIFT | \ 157 GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT)
146 GRAPHICS_OBJECT_ID << OBJECT_ID_SHIFT)
147/****************************************************/ 158/****************************************************/
148/* GPU Object ID definition - Shared with BIOS */ 159/* GPU Object ID definition - Shared with BIOS */
149/****************************************************/ 160/****************************************************/
150#define GPU_ENUM_ID1 (GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\ 161#define GPU_ENUM_ID1 ( GRAPH_OBJECT_TYPE_GPU << OBJECT_TYPE_SHIFT |\
151 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT) 162 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT)
152 163
153/****************************************************/ 164/****************************************************/
154/* Encoder Object ID definition - Shared with BIOS */ 165/* Encoder Object ID definition - Shared with BIOS */
155/****************************************************/ 166/****************************************************/
156/* 167/*
157#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101 168#define ENCODER_INTERNAL_LVDS_ENUM_ID1 0x2101
158#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102 169#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 0x2102
159#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103 170#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 0x2103
160#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104 171#define ENCODER_INTERNAL_DAC1_ENUM_ID1 0x2104
161#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105 172#define ENCODER_INTERNAL_DAC2_ENUM_ID1 0x2105
162#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106 173#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 0x2106
163#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107 174#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 0x2107
164#define ENCODER_SIL170B_ENUM_ID1 0x2108 175#define ENCODER_SIL170B_ENUM_ID1 0x2108
165#define ENCODER_CH7303_ENUM_ID1 0x2109 176#define ENCODER_CH7303_ENUM_ID1 0x2109
166#define ENCODER_CH7301_ENUM_ID1 0x210A 177#define ENCODER_CH7301_ENUM_ID1 0x210A
167#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B 178#define ENCODER_INTERNAL_DVO1_ENUM_ID1 0x210B
@@ -175,8 +186,8 @@
175#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113 186#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 0x2113
176#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114 187#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 0x2114
177#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115 188#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 0x2115
178#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116 189#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 0x2116
179#define ENCODER_SI178_ENUM_ID1 0x2117 190#define ENCODER_SI178_ENUM_ID1 0x2117
180#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118 191#define ENCODER_MVPU_FPGA_ENUM_ID1 0x2118
181#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119 192#define ENCODER_INTERNAL_DDI_ENUM_ID1 0x2119
182#define ENCODER_VT1625_ENUM_ID1 0x211A 193#define ENCODER_VT1625_ENUM_ID1 0x211A
@@ -185,205 +196,169 @@
185#define ENCODER_DP_DP501_ENUM_ID1 0x211D 196#define ENCODER_DP_DP501_ENUM_ID1 0x211D
186#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E 197#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 0x211E
187*/ 198*/
188#define ENCODER_INTERNAL_LVDS_ENUM_ID1 \ 199#define ENCODER_INTERNAL_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
189 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 200 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
190 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 201 ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT)
191 ENCODER_OBJECT_ID_INTERNAL_LVDS << OBJECT_ID_SHIFT) 202
192 203#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
193#define ENCODER_INTERNAL_TMDS1_ENUM_ID1 \ 204 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
194 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 205 ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT)
195 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 206
196 ENCODER_OBJECT_ID_INTERNAL_TMDS1 << OBJECT_ID_SHIFT) 207#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
197 208 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
198#define ENCODER_INTERNAL_TMDS2_ENUM_ID1 \ 209 ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT)
199 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 210
200 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 211#define ENCODER_INTERNAL_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
201 ENCODER_OBJECT_ID_INTERNAL_TMDS2 << OBJECT_ID_SHIFT) 212 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
202 213 ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT)
203#define ENCODER_INTERNAL_DAC1_ENUM_ID1 \ 214
204 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 215#define ENCODER_INTERNAL_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
205 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 216 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
206 ENCODER_OBJECT_ID_INTERNAL_DAC1 << OBJECT_ID_SHIFT) 217 ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT)
207 218
208#define ENCODER_INTERNAL_DAC2_ENUM_ID1 \ 219#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
209 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 220 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
210 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 221 ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
211 ENCODER_OBJECT_ID_INTERNAL_DAC2 << OBJECT_ID_SHIFT) 222
212 223#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
213#define ENCODER_INTERNAL_SDVOA_ENUM_ID1 \ 224 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
214 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 225 ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT)
215 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 226
216 ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) 227#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
217 228 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
218#define ENCODER_INTERNAL_SDVOA_ENUM_ID2 \ 229 ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT)
219 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 230
220 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 231#define ENCODER_SIL170B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
221 ENCODER_OBJECT_ID_INTERNAL_SDVOA << OBJECT_ID_SHIFT) 232 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
222 233 ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT)
223#define ENCODER_INTERNAL_SDVOB_ENUM_ID1 \ 234
224 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 235#define ENCODER_CH7303_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
225 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 236 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
226 ENCODER_OBJECT_ID_INTERNAL_SDVOB << OBJECT_ID_SHIFT) 237 ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT)
227 238
228#define ENCODER_SIL170B_ENUM_ID1 \ 239#define ENCODER_CH7301_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
229 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 240 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
230 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 241 ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT)
231 ENCODER_OBJECT_ID_SI170B << OBJECT_ID_SHIFT) 242
232 243#define ENCODER_INTERNAL_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
233#define ENCODER_CH7303_ENUM_ID1 \ 244 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
234 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 245 ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT)
235 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 246
236 ENCODER_OBJECT_ID_CH7303 << OBJECT_ID_SHIFT) 247#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
237 248 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
238#define ENCODER_CH7301_ENUM_ID1 \ 249 ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
239 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 250
240 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 251#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
241 ENCODER_OBJECT_ID_CH7301 << OBJECT_ID_SHIFT) 252 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
242 253 ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT)
243#define ENCODER_INTERNAL_DVO1_ENUM_ID1 \ 254
244 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 255
245 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 256#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
246 ENCODER_OBJECT_ID_INTERNAL_DVO1 << OBJECT_ID_SHIFT) 257 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
247 258 ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT)
248#define ENCODER_EXTERNAL_SDVOA_ENUM_ID1 \ 259
249 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 260
250 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 261#define ENCODER_TITFP513_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
251 ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) 262 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
252 263 ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT)
253#define ENCODER_EXTERNAL_SDVOA_ENUM_ID2 \ 264
254 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 265#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
255 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 266 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
256 ENCODER_OBJECT_ID_EXTERNAL_SDVOA << OBJECT_ID_SHIFT) 267 ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT)
257 268
258#define ENCODER_EXTERNAL_SDVOB_ENUM_ID1 \ 269#define ENCODER_VT1623_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
259 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 270 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
260 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 271 ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT)
261 ENCODER_OBJECT_ID_EXTERNAL_SDVOB << OBJECT_ID_SHIFT) 272
262 273#define ENCODER_HDMI_SI1930_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
263#define ENCODER_TITFP513_ENUM_ID1 \ 274 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
264 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 275 ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT)
265 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 276
266 ENCODER_OBJECT_ID_TITFP513 << OBJECT_ID_SHIFT) 277#define ENCODER_HDMI_INTERNAL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
267 278 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
268#define ENCODER_INTERNAL_LVTM1_ENUM_ID1 \ 279 ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT)
269 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 280
270 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 281#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
271 ENCODER_OBJECT_ID_INTERNAL_LVTM1 << OBJECT_ID_SHIFT) 282 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
272 283 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
273#define ENCODER_VT1623_ENUM_ID1 \ 284
274 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 285
275 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 286#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
276 ENCODER_OBJECT_ID_VT1623 << OBJECT_ID_SHIFT) 287 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
277 288 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT)
278#define ENCODER_HDMI_SI1930_ENUM_ID1 \ 289
279 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 290
280 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 291#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
281 ENCODER_OBJECT_ID_HDMI_SI1930 << OBJECT_ID_SHIFT) 292 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
282 293 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT)
283#define ENCODER_HDMI_INTERNAL_ENUM_ID1 \ 294
284 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 295#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
285 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 296 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
286 ENCODER_OBJECT_ID_HDMI_INTERNAL << OBJECT_ID_SHIFT) 297 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT)
287 298
288#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1 \ 299#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
289 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 300 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
290 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 301 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) // Shared with CV/TV and CRT
291 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) 302
292 303#define ENCODER_SI178_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
293#define ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID2 \ 304 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
294 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 305 ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT)
295 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 306
296 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1 << OBJECT_ID_SHIFT) 307#define ENCODER_MVPU_FPGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
297 308 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
298#define ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1 \ 309 ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT)
299 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 310
300 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 311#define ENCODER_INTERNAL_DDI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
301 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1 << OBJECT_ID_SHIFT) 312 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
302 313 ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT)
303#define ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1 \ 314
304 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 315#define ENCODER_VT1625_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
305 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 316 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
306 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1 << OBJECT_ID_SHIFT) 317 ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT)
307 318
308#define ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1 \ 319#define ENCODER_HDMI_SI1932_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
309 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 320 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
310 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 321 ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT)
311 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2 << OBJECT_ID_SHIFT) /* Shared with CV/TV and CRT */ 322
312 323#define ENCODER_DP_DP501_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
313#define ENCODER_SI178_ENUM_ID1 \ 324 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
314 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 325 ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT)
315 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 326
316 ENCODER_OBJECT_ID_SI178 << OBJECT_ID_SHIFT) 327#define ENCODER_DP_AN9801_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
317 328 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
318#define ENCODER_MVPU_FPGA_ENUM_ID1 \ 329 ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT)
319 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 330
320 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 331#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
321 ENCODER_OBJECT_ID_MVPU_FPGA << OBJECT_ID_SHIFT) 332 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
322 333 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
323#define ENCODER_INTERNAL_DDI_ENUM_ID1 \ 334
324 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 335#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
325 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 336 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
326 ENCODER_OBJECT_ID_INTERNAL_DDI << OBJECT_ID_SHIFT) 337 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
327 338
328#define ENCODER_VT1625_ENUM_ID1 \ 339#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
329 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 340 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
330 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 341 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
331 ENCODER_OBJECT_ID_VT1625 << OBJECT_ID_SHIFT) 342
332 343#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
333#define ENCODER_HDMI_SI1932_ENUM_ID1 \ 344 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
334 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 345 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
335 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 346
336 ENCODER_OBJECT_ID_HDMI_SI1932 << OBJECT_ID_SHIFT) 347#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
337 348 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
338#define ENCODER_DP_DP501_ENUM_ID1 \ 349 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
339 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 350
340 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 351#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
341 ENCODER_OBJECT_ID_DP_DP501 << OBJECT_ID_SHIFT) 352 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
342 353 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
343#define ENCODER_DP_AN9801_ENUM_ID1 \ 354
344 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 355#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
345 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 356 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
346 ENCODER_OBJECT_ID_DP_AN9801 << OBJECT_ID_SHIFT) 357 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
347 358
348#define ENCODER_INTERNAL_UNIPHY_ENUM_ID1 \ 359#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
349 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\ 360 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
350 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 361 ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
351 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
352
353#define ENCODER_INTERNAL_UNIPHY_ENUM_ID2 \
354 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
355 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
356 ENCODER_OBJECT_ID_INTERNAL_UNIPHY << OBJECT_ID_SHIFT)
357
358#define ENCODER_INTERNAL_KLDSCP_LVTMA_ENUM_ID1 \
359 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
360 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
361 ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)
362
363#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1 \
364 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
365 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
366 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
367
368#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2 \
369 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
370 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
371 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
372
373#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1 \
374 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
375 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
376 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
377
378#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2 \
379 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
380 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
381 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
382
383#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1 \
384 (GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
385 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
386 ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
387 362
388/****************************************************/ 363/****************************************************/
389/* Connector Object ID definition - Shared with BIOS */ 364/* Connector Object ID definition - Shared with BIOS */
@@ -406,167 +381,253 @@
406#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F 381#define CONNECTOR_7PIN_DIN_ENUM_ID1 0x310F
407#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110 382#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 0x3110
408*/ 383*/
409#define CONNECTOR_LVDS_ENUM_ID1 \ 384#define CONNECTOR_LVDS_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
410 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 385 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
411 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 386 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
412 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT) 387
413 388#define CONNECTOR_LVDS_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
414#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 \ 389 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
415 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 390 CONNECTOR_OBJECT_ID_LVDS << OBJECT_ID_SHIFT)
416 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 391
417 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) 392#define CONNECTOR_eDP_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
418 393 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
419#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 \ 394 CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
420 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 395
421 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 396#define CONNECTOR_eDP_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
422 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT) 397 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
423 398 CONNECTOR_OBJECT_ID_eDP << OBJECT_ID_SHIFT)
424#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 \ 399
425 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 400#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
426 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 401 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
427 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) 402 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
428 403
429#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 \ 404#define CONNECTOR_SINGLE_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
430 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 405 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
431 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 406 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I << OBJECT_ID_SHIFT)
432 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT) 407
433 408#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
434#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 \ 409 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
435 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 410 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
436 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 411
437 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) 412#define CONNECTOR_DUAL_LINK_DVI_I_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
438 413 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
439#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 \ 414 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I << OBJECT_ID_SHIFT)
440 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 415
441 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 416#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
442 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT) 417 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
443 418 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
444#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 \ 419
445 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 420#define CONNECTOR_SINGLE_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
446 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 421 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
447 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT) 422 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D << OBJECT_ID_SHIFT)
448 423
449#define CONNECTOR_VGA_ENUM_ID1 \ 424#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
450 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 425 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
451 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 426 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
452 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) 427
453 428#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
454#define CONNECTOR_VGA_ENUM_ID2 \ 429 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
455 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 430 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
456 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 431
457 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT) 432#define CONNECTOR_DUAL_LINK_DVI_D_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
458 433 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
459#define CONNECTOR_COMPOSITE_ENUM_ID1 \ 434 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D << OBJECT_ID_SHIFT)
460 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 435
461 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 436#define CONNECTOR_VGA_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
462 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT) 437 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
463 438 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
464#define CONNECTOR_SVIDEO_ENUM_ID1 \ 439
465 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 440#define CONNECTOR_VGA_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
466 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 441 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
467 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT) 442 CONNECTOR_OBJECT_ID_VGA << OBJECT_ID_SHIFT)
468 443
469#define CONNECTOR_YPbPr_ENUM_ID1 \ 444#define CONNECTOR_COMPOSITE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
470 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 445 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
471 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 446 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
472 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT) 447
473 448#define CONNECTOR_COMPOSITE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
474#define CONNECTOR_D_CONNECTOR_ENUM_ID1 \ 449 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
475 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 450 CONNECTOR_OBJECT_ID_COMPOSITE << OBJECT_ID_SHIFT)
476 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 451
477 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT) 452#define CONNECTOR_SVIDEO_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
478 453 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
479#define CONNECTOR_9PIN_DIN_ENUM_ID1 \ 454 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
480 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 455
481 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 456#define CONNECTOR_SVIDEO_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
482 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT) 457 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
483 458 CONNECTOR_OBJECT_ID_SVIDEO << OBJECT_ID_SHIFT)
484#define CONNECTOR_SCART_ENUM_ID1 \ 459
485 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 460#define CONNECTOR_YPbPr_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
486 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 461 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
487 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT) 462 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
488 463
489#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 \ 464#define CONNECTOR_YPbPr_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
490 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 465 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
491 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 466 CONNECTOR_OBJECT_ID_YPbPr << OBJECT_ID_SHIFT)
492 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT) 467
493 468#define CONNECTOR_D_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
494#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 \ 469 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
495 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 470 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
496 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 471
497 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT) 472#define CONNECTOR_D_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
498 473 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
499#define CONNECTOR_7PIN_DIN_ENUM_ID1 \ 474 CONNECTOR_OBJECT_ID_D_CONNECTOR << OBJECT_ID_SHIFT)
500 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 475
501 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 476#define CONNECTOR_9PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
502 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT) 477 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
503 478 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
504#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 \ 479
505 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 480#define CONNECTOR_9PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
506 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 481 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
507 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) 482 CONNECTOR_OBJECT_ID_9PIN_DIN << OBJECT_ID_SHIFT)
508 483
509#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 \ 484#define CONNECTOR_SCART_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
510 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 485 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
511 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 486 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
512 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT) 487
513 488#define CONNECTOR_SCART_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
514#define CONNECTOR_CROSSFIRE_ENUM_ID1 \ 489 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
515 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 490 CONNECTOR_OBJECT_ID_SCART << OBJECT_ID_SHIFT)
516 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 491
517 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) 492#define CONNECTOR_HDMI_TYPE_A_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
518 493 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
519#define CONNECTOR_CROSSFIRE_ENUM_ID2 \ 494 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
520 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 495
521 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 496#define CONNECTOR_HDMI_TYPE_A_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
522 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT) 497 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
523 498 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
524#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 \ 499
525 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 500#define CONNECTOR_HDMI_TYPE_A_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
526 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 501 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
527 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) 502 CONNECTOR_OBJECT_ID_HDMI_TYPE_A << OBJECT_ID_SHIFT)
528 503
529#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 \ 504#define CONNECTOR_HDMI_TYPE_B_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
530 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 505 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
531 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 506 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
532 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT) 507
533 508#define CONNECTOR_HDMI_TYPE_B_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
534#define CONNECTOR_DISPLAYPORT_ENUM_ID1 \ 509 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
535 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 510 CONNECTOR_OBJECT_ID_HDMI_TYPE_B << OBJECT_ID_SHIFT)
536 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 511
537 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) 512#define CONNECTOR_7PIN_DIN_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
538 513 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
539#define CONNECTOR_DISPLAYPORT_ENUM_ID2 \ 514 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
540 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 515#define CONNECTOR_7PIN_DIN_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
541 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\ 516 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
542 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) 517 CONNECTOR_OBJECT_ID_7PIN_DIN << OBJECT_ID_SHIFT)
543 518
544#define CONNECTOR_DISPLAYPORT_ENUM_ID3 \ 519#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
545 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 520 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
546 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\ 521 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
547 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) 522
548 523#define CONNECTOR_PCIE_CONNECTOR_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
549#define CONNECTOR_DISPLAYPORT_ENUM_ID4 \ 524 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
550 (GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\ 525 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR << OBJECT_ID_SHIFT)
551 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\ 526
552 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT) 527#define CONNECTOR_CROSSFIRE_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
528 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
529 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
530
531#define CONNECTOR_CROSSFIRE_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
532 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
533 CONNECTOR_OBJECT_ID_CROSSFIRE << OBJECT_ID_SHIFT)
534
535
536#define CONNECTOR_HARDCODE_DVI_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
537 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
538 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
539
540#define CONNECTOR_HARDCODE_DVI_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
541 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
542 CONNECTOR_OBJECT_ID_HARDCODE_DVI << OBJECT_ID_SHIFT)
543
544#define CONNECTOR_DISPLAYPORT_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
545 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
546 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
547
548#define CONNECTOR_DISPLAYPORT_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
549 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
550 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
551
552#define CONNECTOR_DISPLAYPORT_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
553 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
554 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
555
556#define CONNECTOR_DISPLAYPORT_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
557 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
558 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
559
560#define CONNECTOR_DISPLAYPORT_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
561 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
562 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
563
564#define CONNECTOR_DISPLAYPORT_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
565 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
566 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
567
568#define CONNECTOR_MXM_ENUM_ID1 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
569 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
570 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_A
571
572#define CONNECTOR_MXM_ENUM_ID2 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
573 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
574 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_B
575
576#define CONNECTOR_MXM_ENUM_ID3 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
577 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
578 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_C
579
580#define CONNECTOR_MXM_ENUM_ID4 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
581 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
582 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DP_D
583
584#define CONNECTOR_MXM_ENUM_ID5 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
585 GRAPH_OBJECT_ENUM_ID5 << ENUM_ID_SHIFT |\
586 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_TXxx
587
588#define CONNECTOR_MXM_ENUM_ID6 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
589 GRAPH_OBJECT_ENUM_ID6 << ENUM_ID_SHIFT |\
590 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_LVDS_UXxx
591
592#define CONNECTOR_MXM_ENUM_ID7 ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
593 GRAPH_OBJECT_ENUM_ID7 << ENUM_ID_SHIFT |\
594 CONNECTOR_OBJECT_ID_MXM << OBJECT_ID_SHIFT) //Mapping to MXM_DAC
553 595
554/****************************************************/ 596/****************************************************/
555/* Router Object ID definition - Shared with BIOS */ 597/* Router Object ID definition - Shared with BIOS */
556/****************************************************/ 598/****************************************************/
557#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 \ 599#define ROUTER_I2C_EXTENDER_CNTL_ENUM_ID1 ( GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\
558 (GRAPH_OBJECT_TYPE_ROUTER << OBJECT_TYPE_SHIFT |\ 600 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
559 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\ 601 ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
560 ROUTER_OBJECT_ID_I2C_EXTENDER_CNTL << OBJECT_ID_SHIFT)
561 602
562/* deleted */ 603/* deleted */
563 604
564/****************************************************/ 605/****************************************************/
606/* Generic Object ID definition - Shared with BIOS */
607/****************************************************/
608#define GENERICOBJECT_GLSYNC_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
609 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
610 GENERIC_OBJECT_ID_GLSYNC << OBJECT_ID_SHIFT)
611
612#define GENERICOBJECT_PX2_NON_DRIVABLE_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
613 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
614 GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
615
616#define GENERICOBJECT_PX2_NON_DRIVABLE_ID2 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
617 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
618 GENERIC_OBJECT_ID_PX2_NON_DRIVABLE<< OBJECT_ID_SHIFT)
619
620#define GENERICOBJECT_MXM_OPM_ENUM_ID1 (GRAPH_OBJECT_TYPE_GENERIC << OBJECT_TYPE_SHIFT |\
621 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
622 GENERIC_OBJECT_ID_MXM_OPM << OBJECT_ID_SHIFT)
623
624/****************************************************/
565/* Object Cap definition - Shared with BIOS */ 625/* Object Cap definition - Shared with BIOS */
566/****************************************************/ 626/****************************************************/
567#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L 627#define GRAPHICS_OBJECT_CAP_I2C 0x00000001L
568#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L 628#define GRAPHICS_OBJECT_CAP_TABLE_ID 0x00000002L
569 629
630
570#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01 631#define GRAPHICS_OBJECT_I2CCOMMAND_TABLE_ID 0x01
571#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02 632#define GRAPHICS_OBJECT_HOTPLUGDETECTIONINTERUPT_TABLE_ID 0x02
572#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03 633#define GRAPHICS_OBJECT_ENCODER_OUTPUT_PROTECTION_TABLE_ID 0x03
@@ -575,4 +636,8 @@
575#pragma pack() 636#pragma pack()
576#endif 637#endif
577 638
578#endif /*GRAPHICTYPE */ 639#endif /*GRAPHICTYPE */
640
641
642
643
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 388140a7e65..e3b44562d26 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -246,6 +246,9 @@ static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr,
246 case ATOM_WS_ATTRIBUTES: 246 case ATOM_WS_ATTRIBUTES:
247 val = gctx->io_attr; 247 val = gctx->io_attr;
248 break; 248 break;
249 case ATOM_WS_REGPTR:
250 val = gctx->reg_block;
251 break;
249 default: 252 default:
250 val = ctx->ws[idx]; 253 val = ctx->ws[idx];
251 } 254 }
@@ -385,6 +388,32 @@ static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr)
385 return atom_get_src_int(ctx, attr, ptr, NULL, 1); 388 return atom_get_src_int(ctx, attr, ptr, NULL, 1);
386} 389}
387 390
391static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr)
392{
393 uint32_t val = 0xCDCDCDCD;
394
395 switch (align) {
396 case ATOM_SRC_DWORD:
397 val = U32(*ptr);
398 (*ptr) += 4;
399 break;
400 case ATOM_SRC_WORD0:
401 case ATOM_SRC_WORD8:
402 case ATOM_SRC_WORD16:
403 val = U16(*ptr);
404 (*ptr) += 2;
405 break;
406 case ATOM_SRC_BYTE0:
407 case ATOM_SRC_BYTE8:
408 case ATOM_SRC_BYTE16:
409 case ATOM_SRC_BYTE24:
410 val = U8(*ptr);
411 (*ptr)++;
412 break;
413 }
414 return val;
415}
416
388static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, 417static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr,
389 int *ptr, uint32_t *saved, int print) 418 int *ptr, uint32_t *saved, int print)
390{ 419{
@@ -482,6 +511,9 @@ static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr,
482 case ATOM_WS_ATTRIBUTES: 511 case ATOM_WS_ATTRIBUTES:
483 gctx->io_attr = val; 512 gctx->io_attr = val;
484 break; 513 break;
514 case ATOM_WS_REGPTR:
515 gctx->reg_block = val;
516 break;
485 default: 517 default:
486 ctx->ws[idx] = val; 518 ctx->ws[idx] = val;
487 } 519 }
@@ -677,7 +709,7 @@ static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg)
677 SDEBUG(" dst: "); 709 SDEBUG(" dst: ");
678 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 710 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
679 SDEBUG(" src1: "); 711 SDEBUG(" src1: ");
680 src1 = atom_get_src(ctx, attr, ptr); 712 src1 = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr);
681 SDEBUG(" src2: "); 713 SDEBUG(" src2: ");
682 src2 = atom_get_src(ctx, attr, ptr); 714 src2 = atom_get_src(ctx, attr, ptr);
683 dst &= src1; 715 dst &= src1;
@@ -809,6 +841,38 @@ static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg)
809 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); 841 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block);
810} 842}
811 843
844static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg)
845{
846 uint8_t attr = U8((*ptr)++), shift;
847 uint32_t saved, dst;
848 int dptr = *ptr;
849 attr &= 0x38;
850 attr |= atom_def_dst[attr >> 3] << 6;
851 SDEBUG(" dst: ");
852 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
853 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
854 SDEBUG(" shift: %d\n", shift);
855 dst <<= shift;
856 SDEBUG(" dst: ");
857 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
858}
859
860static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg)
861{
862 uint8_t attr = U8((*ptr)++), shift;
863 uint32_t saved, dst;
864 int dptr = *ptr;
865 attr &= 0x38;
866 attr |= atom_def_dst[attr >> 3] << 6;
867 SDEBUG(" dst: ");
868 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
869 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr);
870 SDEBUG(" shift: %d\n", shift);
871 dst >>= shift;
872 SDEBUG(" dst: ");
873 atom_put_dst(ctx, arg, attr, &dptr, dst, saved);
874}
875
812static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) 876static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
813{ 877{
814 uint8_t attr = U8((*ptr)++), shift; 878 uint8_t attr = U8((*ptr)++), shift;
@@ -818,7 +882,7 @@ static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg)
818 attr |= atom_def_dst[attr >> 3] << 6; 882 attr |= atom_def_dst[attr >> 3] << 6;
819 SDEBUG(" dst: "); 883 SDEBUG(" dst: ");
820 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 884 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
821 shift = U8((*ptr)++); 885 shift = atom_get_src(ctx, attr, ptr);
822 SDEBUG(" shift: %d\n", shift); 886 SDEBUG(" shift: %d\n", shift);
823 dst <<= shift; 887 dst <<= shift;
824 SDEBUG(" dst: "); 888 SDEBUG(" dst: ");
@@ -834,7 +898,7 @@ static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg)
834 attr |= atom_def_dst[attr >> 3] << 6; 898 attr |= atom_def_dst[attr >> 3] << 6;
835 SDEBUG(" dst: "); 899 SDEBUG(" dst: ");
836 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 900 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1);
837 shift = U8((*ptr)++); 901 shift = atom_get_src(ctx, attr, ptr);
838 SDEBUG(" shift: %d\n", shift); 902 SDEBUG(" shift: %d\n", shift);
839 dst >>= shift; 903 dst >>= shift;
840 SDEBUG(" dst: "); 904 SDEBUG(" dst: ");
@@ -937,18 +1001,18 @@ static struct {
937 atom_op_or, ATOM_ARG_FB}, { 1001 atom_op_or, ATOM_ARG_FB}, {
938 atom_op_or, ATOM_ARG_PLL}, { 1002 atom_op_or, ATOM_ARG_PLL}, {
939 atom_op_or, ATOM_ARG_MC}, { 1003 atom_op_or, ATOM_ARG_MC}, {
940 atom_op_shl, ATOM_ARG_REG}, { 1004 atom_op_shift_left, ATOM_ARG_REG}, {
941 atom_op_shl, ATOM_ARG_PS}, { 1005 atom_op_shift_left, ATOM_ARG_PS}, {
942 atom_op_shl, ATOM_ARG_WS}, { 1006 atom_op_shift_left, ATOM_ARG_WS}, {
943 atom_op_shl, ATOM_ARG_FB}, { 1007 atom_op_shift_left, ATOM_ARG_FB}, {
944 atom_op_shl, ATOM_ARG_PLL}, { 1008 atom_op_shift_left, ATOM_ARG_PLL}, {
945 atom_op_shl, ATOM_ARG_MC}, { 1009 atom_op_shift_left, ATOM_ARG_MC}, {
946 atom_op_shr, ATOM_ARG_REG}, { 1010 atom_op_shift_right, ATOM_ARG_REG}, {
947 atom_op_shr, ATOM_ARG_PS}, { 1011 atom_op_shift_right, ATOM_ARG_PS}, {
948 atom_op_shr, ATOM_ARG_WS}, { 1012 atom_op_shift_right, ATOM_ARG_WS}, {
949 atom_op_shr, ATOM_ARG_FB}, { 1013 atom_op_shift_right, ATOM_ARG_FB}, {
950 atom_op_shr, ATOM_ARG_PLL}, { 1014 atom_op_shift_right, ATOM_ARG_PLL}, {
951 atom_op_shr, ATOM_ARG_MC}, { 1015 atom_op_shift_right, ATOM_ARG_MC}, {
952 atom_op_mul, ATOM_ARG_REG}, { 1016 atom_op_mul, ATOM_ARG_REG}, {
953 atom_op_mul, ATOM_ARG_PS}, { 1017 atom_op_mul, ATOM_ARG_PS}, {
954 atom_op_mul, ATOM_ARG_WS}, { 1018 atom_op_mul, ATOM_ARG_WS}, {
@@ -1058,8 +1122,6 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
1058 1122
1059 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1123 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps);
1060 1124
1061 /* reset reg block */
1062 ctx->reg_block = 0;
1063 ectx.ctx = ctx; 1125 ectx.ctx = ctx;
1064 ectx.ps_shift = ps / 4; 1126 ectx.ps_shift = ps / 4;
1065 ectx.start = base; 1127 ectx.start = base;
@@ -1096,6 +1158,12 @@ static void atom_execute_table_locked(struct atom_context *ctx, int index, uint3
1096void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1158void atom_execute_table(struct atom_context *ctx, int index, uint32_t * params)
1097{ 1159{
1098 mutex_lock(&ctx->mutex); 1160 mutex_lock(&ctx->mutex);
1161 /* reset reg block */
1162 ctx->reg_block = 0;
1163 /* reset fb window */
1164 ctx->fb_base = 0;
1165 /* reset io mode */
1166 ctx->io_mode = ATOM_IO_MM;
1099 atom_execute_table_locked(ctx, index, params); 1167 atom_execute_table_locked(ctx, index, params);
1100 mutex_unlock(&ctx->mutex); 1168 mutex_unlock(&ctx->mutex);
1101} 1169}
diff --git a/drivers/gpu/drm/radeon/atom.h b/drivers/gpu/drm/radeon/atom.h
index 47fd943f6d1..bc73781423a 100644
--- a/drivers/gpu/drm/radeon/atom.h
+++ b/drivers/gpu/drm/radeon/atom.h
@@ -91,6 +91,7 @@
91#define ATOM_WS_AND_MASK 0x45 91#define ATOM_WS_AND_MASK 0x45
92#define ATOM_WS_FB_WINDOW 0x46 92#define ATOM_WS_FB_WINDOW 0x46
93#define ATOM_WS_ATTRIBUTES 0x47 93#define ATOM_WS_ATTRIBUTES 0x47
94#define ATOM_WS_REGPTR 0x48
94 95
95#define ATOM_IIO_NOP 0 96#define ATOM_IIO_NOP 0
96#define ATOM_IIO_START 1 97#define ATOM_IIO_START 1
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 260fcf59f00..af464e351fb 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -307,7 +307,6 @@ atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id; 308 args.ucCRTC = radeon_crtc->crtc_id;
309 309
310 printk("executing set crtc dtd timing\n");
311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
312} 311}
313 312
@@ -347,7 +346,6 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
347 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 346 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
348 args.ucCRTC = radeon_crtc->crtc_id; 347 args.ucCRTC = radeon_crtc->crtc_id;
349 348
350 printk("executing set crtc timing\n");
351 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 349 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
352} 350}
353 351
@@ -409,59 +407,57 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
409 } 407 }
410} 408}
411 409
412void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 410union adjust_pixel_clock {
411 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
412};
413
414static u32 atombios_adjust_pll(struct drm_crtc *crtc,
415 struct drm_display_mode *mode,
416 struct radeon_pll *pll)
413{ 417{
414 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
415 struct drm_device *dev = crtc->dev; 418 struct drm_device *dev = crtc->dev;
416 struct radeon_device *rdev = dev->dev_private; 419 struct radeon_device *rdev = dev->dev_private;
417 struct drm_encoder *encoder = NULL; 420 struct drm_encoder *encoder = NULL;
418 struct radeon_encoder *radeon_encoder = NULL; 421 struct radeon_encoder *radeon_encoder = NULL;
419 uint8_t frev, crev; 422 u32 adjusted_clock = mode->clock;
420 int index;
421 SET_PIXEL_CLOCK_PS_ALLOCATION args;
422 PIXEL_CLOCK_PARAMETERS *spc1_ptr;
423 PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
424 PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
425 uint32_t pll_clock = mode->clock;
426 uint32_t adjusted_clock;
427 uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
428 struct radeon_pll *pll;
429 int pll_flags = 0;
430 423
431 memset(&args, 0, sizeof(args)); 424 /* reset the pll flags */
425 pll->flags = 0;
432 426
433 if (ASIC_IS_AVIVO(rdev)) { 427 if (ASIC_IS_AVIVO(rdev)) {
434 if ((rdev->family == CHIP_RS600) || 428 if ((rdev->family == CHIP_RS600) ||
435 (rdev->family == CHIP_RS690) || 429 (rdev->family == CHIP_RS690) ||
436 (rdev->family == CHIP_RS740)) 430 (rdev->family == CHIP_RS740))
437 pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV | 431 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
438 RADEON_PLL_PREFER_CLOSEST_LOWER); 432 RADEON_PLL_PREFER_CLOSEST_LOWER);
439 433
440 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 434 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
441 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 435 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
442 else 436 else
443 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 437 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
444 } else { 438 } else {
445 pll_flags |= RADEON_PLL_LEGACY; 439 pll->flags |= RADEON_PLL_LEGACY;
446 440
447 if (mode->clock > 200000) /* range limits??? */ 441 if (mode->clock > 200000) /* range limits??? */
448 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 442 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
449 else 443 else
450 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 444 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
451 445
452 } 446 }
453 447
454 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 448 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
455 if (encoder->crtc == crtc) { 449 if (encoder->crtc == crtc) {
456 if (!ASIC_IS_AVIVO(rdev)) {
457 if (encoder->encoder_type !=
458 DRM_MODE_ENCODER_DAC)
459 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
460 if (encoder->encoder_type ==
461 DRM_MODE_ENCODER_LVDS)
462 pll_flags |= RADEON_PLL_USE_REF_DIV;
463 }
464 radeon_encoder = to_radeon_encoder(encoder); 450 radeon_encoder = to_radeon_encoder(encoder);
451 if (ASIC_IS_AVIVO(rdev)) {
452 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
453 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
454 adjusted_clock = mode->clock * 2;
455 } else {
456 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
457 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
458 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
459 pll->flags |= RADEON_PLL_USE_REF_DIV;
460 }
465 break; 461 break;
466 } 462 }
467 } 463 }
@@ -471,46 +467,101 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
471 * special hw requirements. 467 * special hw requirements.
472 */ 468 */
473 if (ASIC_IS_DCE3(rdev)) { 469 if (ASIC_IS_DCE3(rdev)) {
474 ADJUST_DISPLAY_PLL_PS_ALLOCATION adjust_pll_args; 470 union adjust_pixel_clock args;
471 struct radeon_encoder_atom_dig *dig;
472 u8 frev, crev;
473 int index;
475 474
476 if (!encoder) 475 if (!radeon_encoder->enc_priv)
477 return; 476 return adjusted_clock;
478 477 dig = radeon_encoder->enc_priv;
479 memset(&adjust_pll_args, 0, sizeof(adjust_pll_args));
480 adjust_pll_args.usPixelClock = cpu_to_le16(mode->clock / 10);
481 adjust_pll_args.ucTransmitterID = radeon_encoder->encoder_id;
482 adjust_pll_args.ucEncodeMode = atombios_get_encoder_mode(encoder);
483 478
484 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 479 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
485 atom_execute_table(rdev->mode_info.atom_context, 480 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
486 index, (uint32_t *)&adjust_pll_args); 481 &crev);
487 adjusted_clock = le16_to_cpu(adjust_pll_args.usPixelClock) * 10; 482
488 } else { 483 memset(&args, 0, sizeof(args));
489 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 484
490 if (ASIC_IS_AVIVO(rdev) && 485 switch (frev) {
491 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)) 486 case 1:
492 adjusted_clock = mode->clock * 2; 487 switch (crev) {
493 else 488 case 1:
494 adjusted_clock = mode->clock; 489 case 2:
490 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
491 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
492 args.v1.ucEncodeMode = atombios_get_encoder_mode(encoder);
493
494 atom_execute_table(rdev->mode_info.atom_context,
495 index, (uint32_t *)&args);
496 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
497 break;
498 default:
499 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
500 return adjusted_clock;
501 }
502 break;
503 default:
504 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
505 return adjusted_clock;
506 }
495 } 507 }
508 return adjusted_clock;
509}
510
511union set_pixel_clock {
512 SET_PIXEL_CLOCK_PS_ALLOCATION base;
513 PIXEL_CLOCK_PARAMETERS v1;
514 PIXEL_CLOCK_PARAMETERS_V2 v2;
515 PIXEL_CLOCK_PARAMETERS_V3 v3;
516};
517
518void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
519{
520 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
521 struct drm_device *dev = crtc->dev;
522 struct radeon_device *rdev = dev->dev_private;
523 struct drm_encoder *encoder = NULL;
524 struct radeon_encoder *radeon_encoder = NULL;
525 u8 frev, crev;
526 int index;
527 union set_pixel_clock args;
528 u32 pll_clock = mode->clock;
529 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
530 struct radeon_pll *pll;
531 u32 adjusted_clock;
532
533 memset(&args, 0, sizeof(args));
534
535 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
536 if (encoder->crtc == crtc) {
537 radeon_encoder = to_radeon_encoder(encoder);
538 break;
539 }
540 }
541
542 if (!radeon_encoder)
543 return;
496 544
497 if (radeon_crtc->crtc_id == 0) 545 if (radeon_crtc->crtc_id == 0)
498 pll = &rdev->clock.p1pll; 546 pll = &rdev->clock.p1pll;
499 else 547 else
500 pll = &rdev->clock.p2pll; 548 pll = &rdev->clock.p2pll;
501 549
550 /* adjust pixel clock as needed */
551 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
552
502 if (ASIC_IS_AVIVO(rdev)) { 553 if (ASIC_IS_AVIVO(rdev)) {
503 if (radeon_new_pll) 554 if (radeon_new_pll)
504 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, 555 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock,
505 &fb_div, &frac_fb_div, 556 &fb_div, &frac_fb_div,
506 &ref_div, &post_div, pll_flags); 557 &ref_div, &post_div);
507 else 558 else
508 radeon_compute_pll(pll, adjusted_clock, &pll_clock, 559 radeon_compute_pll(pll, adjusted_clock, &pll_clock,
509 &fb_div, &frac_fb_div, 560 &fb_div, &frac_fb_div,
510 &ref_div, &post_div, pll_flags); 561 &ref_div, &post_div);
511 } else 562 } else
512 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, 563 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
513 &ref_div, &post_div, pll_flags); 564 &ref_div, &post_div);
514 565
515 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 566 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
516 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 567 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
@@ -520,45 +571,38 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
520 case 1: 571 case 1:
521 switch (crev) { 572 switch (crev) {
522 case 1: 573 case 1:
523 spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput; 574 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
524 spc1_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 575 args.v1.usRefDiv = cpu_to_le16(ref_div);
525 spc1_ptr->usRefDiv = cpu_to_le16(ref_div); 576 args.v1.usFbDiv = cpu_to_le16(fb_div);
526 spc1_ptr->usFbDiv = cpu_to_le16(fb_div); 577 args.v1.ucFracFbDiv = frac_fb_div;
527 spc1_ptr->ucFracFbDiv = frac_fb_div; 578 args.v1.ucPostDiv = post_div;
528 spc1_ptr->ucPostDiv = post_div; 579 args.v1.ucPpll =
529 spc1_ptr->ucPpll =
530 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 580 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
531 spc1_ptr->ucCRTC = radeon_crtc->crtc_id; 581 args.v1.ucCRTC = radeon_crtc->crtc_id;
532 spc1_ptr->ucRefDivSrc = 1; 582 args.v1.ucRefDivSrc = 1;
533 break; 583 break;
534 case 2: 584 case 2:
535 spc2_ptr = 585 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
536 (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput; 586 args.v2.usRefDiv = cpu_to_le16(ref_div);
537 spc2_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 587 args.v2.usFbDiv = cpu_to_le16(fb_div);
538 spc2_ptr->usRefDiv = cpu_to_le16(ref_div); 588 args.v2.ucFracFbDiv = frac_fb_div;
539 spc2_ptr->usFbDiv = cpu_to_le16(fb_div); 589 args.v2.ucPostDiv = post_div;
540 spc2_ptr->ucFracFbDiv = frac_fb_div; 590 args.v2.ucPpll =
541 spc2_ptr->ucPostDiv = post_div;
542 spc2_ptr->ucPpll =
543 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 591 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
544 spc2_ptr->ucCRTC = radeon_crtc->crtc_id; 592 args.v2.ucCRTC = radeon_crtc->crtc_id;
545 spc2_ptr->ucRefDivSrc = 1; 593 args.v2.ucRefDivSrc = 1;
546 break; 594 break;
547 case 3: 595 case 3:
548 if (!encoder) 596 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
549 return; 597 args.v3.usRefDiv = cpu_to_le16(ref_div);
550 spc3_ptr = 598 args.v3.usFbDiv = cpu_to_le16(fb_div);
551 (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput; 599 args.v3.ucFracFbDiv = frac_fb_div;
552 spc3_ptr->usPixelClock = cpu_to_le16(mode->clock / 10); 600 args.v3.ucPostDiv = post_div;
553 spc3_ptr->usRefDiv = cpu_to_le16(ref_div); 601 args.v3.ucPpll =
554 spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
555 spc3_ptr->ucFracFbDiv = frac_fb_div;
556 spc3_ptr->ucPostDiv = post_div;
557 spc3_ptr->ucPpll =
558 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; 602 radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
559 spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); 603 args.v3.ucMiscInfo = (radeon_crtc->crtc_id << 2);
560 spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id; 604 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
561 spc3_ptr->ucEncoderMode = 605 args.v3.ucEncoderMode =
562 atombios_get_encoder_mode(encoder); 606 atombios_get_encoder_mode(encoder);
563 break; 607 break;
564 default: 608 default:
@@ -571,12 +615,11 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
571 return; 615 return;
572 } 616 }
573 617
574 printk("executing set pll\n");
575 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 618 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
576} 619}
577 620
578int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 621static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
579 struct drm_framebuffer *old_fb) 622 struct drm_framebuffer *old_fb)
580{ 623{
581 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 624 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
582 struct drm_device *dev = crtc->dev; 625 struct drm_device *dev = crtc->dev;
@@ -706,6 +749,42 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
706 return 0; 749 return 0;
707} 750}
708 751
752int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
753 struct drm_framebuffer *old_fb)
754{
755 struct drm_device *dev = crtc->dev;
756 struct radeon_device *rdev = dev->dev_private;
757
758 if (ASIC_IS_AVIVO(rdev))
759 return avivo_crtc_set_base(crtc, x, y, old_fb);
760 else
761 return radeon_crtc_set_base(crtc, x, y, old_fb);
762}
763
764/* properly set additional regs when using atombios */
765static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
766{
767 struct drm_device *dev = crtc->dev;
768 struct radeon_device *rdev = dev->dev_private;
769 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
770 u32 disp_merge_cntl;
771
772 switch (radeon_crtc->crtc_id) {
773 case 0:
774 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
775 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
776 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
777 break;
778 case 1:
779 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
780 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
781 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
782 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
783 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
784 break;
785 }
786}
787
709int atombios_crtc_mode_set(struct drm_crtc *crtc, 788int atombios_crtc_mode_set(struct drm_crtc *crtc,
710 struct drm_display_mode *mode, 789 struct drm_display_mode *mode,
711 struct drm_display_mode *adjusted_mode, 790 struct drm_display_mode *adjusted_mode,
@@ -727,8 +806,8 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
727 else { 806 else {
728 if (radeon_crtc->crtc_id == 0) 807 if (radeon_crtc->crtc_id == 0)
729 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 808 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
730 radeon_crtc_set_base(crtc, x, y, old_fb); 809 atombios_crtc_set_base(crtc, x, y, old_fb);
731 radeon_legacy_atom_set_surface(crtc); 810 radeon_legacy_atom_fixup(crtc);
732 } 811 }
733 atombios_overscan_setup(crtc, mode, adjusted_mode); 812 atombios_overscan_setup(crtc, mode, adjusted_mode);
734 atombios_scaler_setup(crtc); 813 atombios_scaler_setup(crtc);
@@ -746,8 +825,8 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
746 825
747static void atombios_crtc_prepare(struct drm_crtc *crtc) 826static void atombios_crtc_prepare(struct drm_crtc *crtc)
748{ 827{
749 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
750 atombios_lock_crtc(crtc, 1); 828 atombios_lock_crtc(crtc, 1);
829 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
751} 830}
752 831
753static void atombios_crtc_commit(struct drm_crtc *crtc) 832static void atombios_crtc_commit(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 0d63c4436e7..b32eeea5bb8 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -332,11 +332,13 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
332 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args; 332 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION args;
333 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 333 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
334 unsigned char *base; 334 unsigned char *base;
335 int retry_count = 0;
335 336
336 memset(&args, 0, sizeof(args)); 337 memset(&args, 0, sizeof(args));
337 338
338 base = (unsigned char *)rdev->mode_info.atom_context->scratch; 339 base = (unsigned char *)rdev->mode_info.atom_context->scratch;
339 340
341retry:
340 memcpy(base, req_bytes, num_bytes); 342 memcpy(base, req_bytes, num_bytes);
341 343
342 args.lpAuxRequest = 0; 344 args.lpAuxRequest = 0;
@@ -347,10 +349,12 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
347 349
348 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 350 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
349 351
350 if (args.ucReplyStatus) { 352 if (args.ucReplyStatus && !args.ucDataOutLen) {
351 DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x\n", 353 if (args.ucReplyStatus == 0x20 && retry_count < 10)
354 goto retry;
355 DRM_DEBUG("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n",
352 req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3], 356 req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
353 chan->rec.i2c_id, args.ucReplyStatus); 357 chan->rec.i2c_id, args.ucReplyStatus, retry_count);
354 return false; 358 return false;
355 } 359 }
356 360
@@ -468,7 +472,8 @@ void radeon_dp_set_link_config(struct drm_connector *connector,
468 struct radeon_connector *radeon_connector; 472 struct radeon_connector *radeon_connector;
469 struct radeon_connector_atom_dig *dig_connector; 473 struct radeon_connector_atom_dig *dig_connector;
470 474
471 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 475 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
476 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
472 return; 477 return;
473 478
474 radeon_connector = to_radeon_connector(connector); 479 radeon_connector = to_radeon_connector(connector);
@@ -582,7 +587,8 @@ void dp_link_train(struct drm_encoder *encoder,
582 u8 train_set[4]; 587 u8 train_set[4];
583 int i; 588 int i;
584 589
585 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 590 if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
591 (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
586 return; 592 return;
587 593
588 if (!radeon_encoder->enc_priv) 594 if (!radeon_encoder->enc_priv)
@@ -594,21 +600,14 @@ void dp_link_train(struct drm_encoder *encoder,
594 return; 600 return;
595 dig_connector = radeon_connector->con_priv; 601 dig_connector = radeon_connector->con_priv;
596 602
597 if (ASIC_IS_DCE32(rdev)) { 603 if (dig->dig_encoder)
598 if (dig->dig_block) 604 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
599 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; 605 else
600 else 606 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
601 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; 607 if (dig_connector->linkb)
602 if (dig_connector->linkb) 608 enc_id |= ATOM_DP_CONFIG_LINK_B;
603 enc_id |= ATOM_DP_CONFIG_LINK_B; 609 else
604 else 610 enc_id |= ATOM_DP_CONFIG_LINK_A;
605 enc_id |= ATOM_DP_CONFIG_LINK_A;
606 } else {
607 if (dig_connector->linkb)
608 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER | ATOM_DP_CONFIG_LINK_B;
609 else
610 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER | ATOM_DP_CONFIG_LINK_A;
611 }
612 611
613 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); 612 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
614 if (dig_connector->dp_clock == 270000) 613 if (dig_connector->dp_clock == 270000)
diff --git a/drivers/gpu/drm/radeon/mkregtable.c b/drivers/gpu/drm/radeon/mkregtable.c
index 0d79577c157..607241c6a8a 100644
--- a/drivers/gpu/drm/radeon/mkregtable.c
+++ b/drivers/gpu/drm/radeon/mkregtable.c
@@ -661,8 +661,10 @@ static int parser_auth(struct table *t, const char *filename)
661 fseek(file, 0, SEEK_SET); 661 fseek(file, 0, SEEK_SET);
662 662
663 /* get header */ 663 /* get header */
664 if (fgets(buf, 1024, file) == NULL) 664 if (fgets(buf, 1024, file) == NULL) {
665 fclose(file);
665 return -1; 666 return -1;
667 }
666 668
667 /* first line will contain the last register 669 /* first line will contain the last register
668 * and gpu name */ 670 * and gpu name */
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 71727460968..c0d4650cdb7 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -131,7 +131,8 @@ void r100_hpd_init(struct radeon_device *rdev)
131 break; 131 break;
132 } 132 }
133 } 133 }
134 r100_irq_set(rdev); 134 if (rdev->irq.installed)
135 r100_irq_set(rdev);
135} 136}
136 137
137void r100_hpd_fini(struct radeon_device *rdev) 138void r100_hpd_fini(struct radeon_device *rdev)
@@ -243,6 +244,11 @@ int r100_irq_set(struct radeon_device *rdev)
243{ 244{
244 uint32_t tmp = 0; 245 uint32_t tmp = 0;
245 246
247 if (!rdev->irq.installed) {
248 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
249 WREG32(R_000040_GEN_INT_CNTL, 0);
250 return -EINVAL;
251 }
246 if (rdev->irq.sw_int) { 252 if (rdev->irq.sw_int) {
247 tmp |= RADEON_SW_INT_ENABLE; 253 tmp |= RADEON_SW_INT_ENABLE;
248 } 254 }
@@ -348,14 +354,25 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
348 return RREG32(RADEON_CRTC2_CRNT_FRAME); 354 return RREG32(RADEON_CRTC2_CRNT_FRAME);
349} 355}
350 356
357/* Who ever call radeon_fence_emit should call ring_lock and ask
358 * for enough space (today caller are ib schedule and buffer move) */
351void r100_fence_ring_emit(struct radeon_device *rdev, 359void r100_fence_ring_emit(struct radeon_device *rdev,
352 struct radeon_fence *fence) 360 struct radeon_fence *fence)
353{ 361{
354 /* Who ever call radeon_fence_emit should call ring_lock and ask 362 /* We have to make sure that caches are flushed before
355 * for enough space (today caller are ib schedule and buffer move) */ 363 * CPU might read something from VRAM. */
364 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
365 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
366 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
367 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
356 /* Wait until IDLE & CLEAN */ 368 /* Wait until IDLE & CLEAN */
357 radeon_ring_write(rdev, PACKET0(0x1720, 0)); 369 radeon_ring_write(rdev, PACKET0(0x1720, 0));
358 radeon_ring_write(rdev, (1 << 16) | (1 << 17)); 370 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
371 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
372 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
373 RADEON_HDP_READ_BUFFER_INVALIDATE);
374 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
375 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
359 /* Emit fence sequence & fire IRQ */ 376 /* Emit fence sequence & fire IRQ */
360 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 377 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
361 radeon_ring_write(rdev, fence->seq); 378 radeon_ring_write(rdev, fence->seq);
@@ -1493,6 +1510,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1493 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n"); 1510 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1494 return -EINVAL; 1511 return -EINVAL;
1495 } 1512 }
1513 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1496 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1); 1514 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1497 track->immd_dwords = pkt->count - 1; 1515 track->immd_dwords = pkt->count - 1;
1498 r = r100_cs_track_check(p->rdev, track); 1516 r = r100_cs_track_check(p->rdev, track);
@@ -1713,14 +1731,6 @@ void r100_gpu_init(struct radeon_device *rdev)
1713 r100_hdp_reset(rdev); 1731 r100_hdp_reset(rdev);
1714} 1732}
1715 1733
1716void r100_hdp_flush(struct radeon_device *rdev)
1717{
1718 u32 tmp;
1719 tmp = RREG32(RADEON_HOST_PATH_CNTL);
1720 tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;
1721 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1722}
1723
1724void r100_hdp_reset(struct radeon_device *rdev) 1734void r100_hdp_reset(struct radeon_device *rdev)
1725{ 1735{
1726 uint32_t tmp; 1736 uint32_t tmp;
@@ -3313,6 +3323,7 @@ static int r100_startup(struct radeon_device *rdev)
3313 } 3323 }
3314 /* Enable IRQ */ 3324 /* Enable IRQ */
3315 r100_irq_set(rdev); 3325 r100_irq_set(rdev);
3326 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3316 /* 1M ring buffer */ 3327 /* 1M ring buffer */
3317 r = r100_cp_init(rdev, 1024 * 1024); 3328 r = r100_cp_init(rdev, 1024 * 1024);
3318 if (r) { 3329 if (r) {
@@ -3364,13 +3375,13 @@ int r100_suspend(struct radeon_device *rdev)
3364 3375
3365void r100_fini(struct radeon_device *rdev) 3376void r100_fini(struct radeon_device *rdev)
3366{ 3377{
3367 r100_suspend(rdev);
3368 r100_cp_fini(rdev); 3378 r100_cp_fini(rdev);
3369 r100_wb_fini(rdev); 3379 r100_wb_fini(rdev);
3370 r100_ib_fini(rdev); 3380 r100_ib_fini(rdev);
3371 radeon_gem_fini(rdev); 3381 radeon_gem_fini(rdev);
3372 if (rdev->flags & RADEON_IS_PCI) 3382 if (rdev->flags & RADEON_IS_PCI)
3373 r100_pci_gart_fini(rdev); 3383 r100_pci_gart_fini(rdev);
3384 radeon_agp_fini(rdev);
3374 radeon_irq_kms_fini(rdev); 3385 radeon_irq_kms_fini(rdev);
3375 radeon_fence_driver_fini(rdev); 3386 radeon_fence_driver_fini(rdev);
3376 radeon_bo_fini(rdev); 3387 radeon_bo_fini(rdev);
@@ -3394,9 +3405,7 @@ int r100_mc_init(struct radeon_device *rdev)
3394 if (rdev->flags & RADEON_IS_AGP) { 3405 if (rdev->flags & RADEON_IS_AGP) {
3395 r = radeon_agp_init(rdev); 3406 r = radeon_agp_init(rdev);
3396 if (r) { 3407 if (r) {
3397 printk(KERN_WARNING "[drm] Disabling AGP\n"); 3408 radeon_agp_disable(rdev);
3398 rdev->flags &= ~RADEON_IS_AGP;
3399 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
3400 } else { 3409 } else {
3401 rdev->mc.gtt_location = rdev->mc.agp_base; 3410 rdev->mc.gtt_location = rdev->mc.agp_base;
3402 } 3411 }
@@ -3477,13 +3486,12 @@ int r100_init(struct radeon_device *rdev)
3477 if (r) { 3486 if (r) {
3478 /* Somethings want wront with the accel init stop accel */ 3487 /* Somethings want wront with the accel init stop accel */
3479 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 3488 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3480 r100_suspend(rdev);
3481 r100_cp_fini(rdev); 3489 r100_cp_fini(rdev);
3482 r100_wb_fini(rdev); 3490 r100_wb_fini(rdev);
3483 r100_ib_fini(rdev); 3491 r100_ib_fini(rdev);
3492 radeon_irq_kms_fini(rdev);
3484 if (rdev->flags & RADEON_IS_PCI) 3493 if (rdev->flags & RADEON_IS_PCI)
3485 r100_pci_gart_fini(rdev); 3494 r100_pci_gart_fini(rdev);
3486 radeon_irq_kms_fini(rdev);
3487 rdev->accel_working = false; 3495 rdev->accel_working = false;
3488 } 3496 }
3489 return 0; 3497 return 0;
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 20942127c46..ff1e0cd608b 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -371,13 +371,16 @@ int r200_packet0_check(struct radeon_cs_parser *p,
371 case 5: 371 case 5:
372 case 6: 372 case 6:
373 case 7: 373 case 7:
374 /* 1D/2D */
374 track->textures[i].tex_coord_type = 0; 375 track->textures[i].tex_coord_type = 0;
375 break; 376 break;
376 case 1: 377 case 1:
377 track->textures[i].tex_coord_type = 1; 378 /* CUBE */
379 track->textures[i].tex_coord_type = 2;
378 break; 380 break;
379 case 2: 381 case 2:
380 track->textures[i].tex_coord_type = 2; 382 /* 3D */
383 track->textures[i].tex_coord_type = 1;
381 break; 384 break;
382 } 385 }
383 break; 386 break;
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 3f2cc9e2e8d..43b55a030b4 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -36,7 +36,15 @@
36#include "rv350d.h" 36#include "rv350d.h"
37#include "r300_reg_safe.h" 37#include "r300_reg_safe.h"
38 38
39/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */ 39/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
40 *
41 * GPU Errata:
42 * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
43 * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
44 * However, scheduling such write to the ring seems harmless, i suspect
45 * the CP read collide with the flush somehow, or maybe the MC, hard to
46 * tell. (Jerome Glisse)
47 */
40 48
41/* 49/*
42 * rv370,rv380 PCIE GART 50 * rv370,rv380 PCIE GART
@@ -178,6 +186,11 @@ void r300_fence_ring_emit(struct radeon_device *rdev,
178 /* Wait until IDLE & CLEAN */ 186 /* Wait until IDLE & CLEAN */
179 radeon_ring_write(rdev, PACKET0(0x1720, 0)); 187 radeon_ring_write(rdev, PACKET0(0x1720, 0));
180 radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9)); 188 radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9));
189 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
190 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
191 RADEON_HDP_READ_BUFFER_INVALIDATE);
192 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
193 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
181 /* Emit fence sequence & fire IRQ */ 194 /* Emit fence sequence & fire IRQ */
182 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0)); 195 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
183 radeon_ring_write(rdev, fence->seq); 196 radeon_ring_write(rdev, fence->seq);
@@ -493,11 +506,14 @@ void r300_vram_info(struct radeon_device *rdev)
493 506
494 /* DDR for all card after R300 & IGP */ 507 /* DDR for all card after R300 & IGP */
495 rdev->mc.vram_is_ddr = true; 508 rdev->mc.vram_is_ddr = true;
509
496 tmp = RREG32(RADEON_MEM_CNTL); 510 tmp = RREG32(RADEON_MEM_CNTL);
497 if (tmp & R300_MEM_NUM_CHANNELS_MASK) { 511 tmp &= R300_MEM_NUM_CHANNELS_MASK;
498 rdev->mc.vram_width = 128; 512 switch (tmp) {
499 } else { 513 case 0: rdev->mc.vram_width = 64; break;
500 rdev->mc.vram_width = 64; 514 case 1: rdev->mc.vram_width = 128; break;
515 case 2: rdev->mc.vram_width = 256; break;
516 default: rdev->mc.vram_width = 128; break;
501 } 517 }
502 518
503 r100_vram_init_sizes(rdev); 519 r100_vram_init_sizes(rdev);
@@ -1258,6 +1274,7 @@ static int r300_startup(struct radeon_device *rdev)
1258 } 1274 }
1259 /* Enable IRQ */ 1275 /* Enable IRQ */
1260 r100_irq_set(rdev); 1276 r100_irq_set(rdev);
1277 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1261 /* 1M ring buffer */ 1278 /* 1M ring buffer */
1262 r = r100_cp_init(rdev, 1024 * 1024); 1279 r = r100_cp_init(rdev, 1024 * 1024);
1263 if (r) { 1280 if (r) {
@@ -1313,7 +1330,6 @@ int r300_suspend(struct radeon_device *rdev)
1313 1330
1314void r300_fini(struct radeon_device *rdev) 1331void r300_fini(struct radeon_device *rdev)
1315{ 1332{
1316 r300_suspend(rdev);
1317 r100_cp_fini(rdev); 1333 r100_cp_fini(rdev);
1318 r100_wb_fini(rdev); 1334 r100_wb_fini(rdev);
1319 r100_ib_fini(rdev); 1335 r100_ib_fini(rdev);
@@ -1322,6 +1338,7 @@ void r300_fini(struct radeon_device *rdev)
1322 rv370_pcie_gart_fini(rdev); 1338 rv370_pcie_gart_fini(rdev);
1323 if (rdev->flags & RADEON_IS_PCI) 1339 if (rdev->flags & RADEON_IS_PCI)
1324 r100_pci_gart_fini(rdev); 1340 r100_pci_gart_fini(rdev);
1341 radeon_agp_fini(rdev);
1325 radeon_irq_kms_fini(rdev); 1342 radeon_irq_kms_fini(rdev);
1326 radeon_fence_driver_fini(rdev); 1343 radeon_fence_driver_fini(rdev);
1327 radeon_bo_fini(rdev); 1344 radeon_bo_fini(rdev);
@@ -1403,15 +1420,15 @@ int r300_init(struct radeon_device *rdev)
1403 if (r) { 1420 if (r) {
1404 /* Somethings want wront with the accel init stop accel */ 1421 /* Somethings want wront with the accel init stop accel */
1405 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 1422 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1406 r300_suspend(rdev);
1407 r100_cp_fini(rdev); 1423 r100_cp_fini(rdev);
1408 r100_wb_fini(rdev); 1424 r100_wb_fini(rdev);
1409 r100_ib_fini(rdev); 1425 r100_ib_fini(rdev);
1426 radeon_irq_kms_fini(rdev);
1410 if (rdev->flags & RADEON_IS_PCIE) 1427 if (rdev->flags & RADEON_IS_PCIE)
1411 rv370_pcie_gart_fini(rdev); 1428 rv370_pcie_gart_fini(rdev);
1412 if (rdev->flags & RADEON_IS_PCI) 1429 if (rdev->flags & RADEON_IS_PCI)
1413 r100_pci_gart_fini(rdev); 1430 r100_pci_gart_fini(rdev);
1414 radeon_irq_kms_fini(rdev); 1431 radeon_agp_fini(rdev);
1415 rdev->accel_working = false; 1432 rdev->accel_working = false;
1416 } 1433 }
1417 return 0; 1434 return 0;
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index c05a7270cf0..d9373246c97 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -30,7 +30,15 @@
30#include "radeon_reg.h" 30#include "radeon_reg.h"
31#include "radeon.h" 31#include "radeon.h"
32#include "atom.h" 32#include "atom.h"
33#include "r100d.h"
33#include "r420d.h" 34#include "r420d.h"
35#include "r420_reg_safe.h"
36
37static void r420_set_reg_safe(struct radeon_device *rdev)
38{
39 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm;
40 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm);
41}
34 42
35int r420_mc_init(struct radeon_device *rdev) 43int r420_mc_init(struct radeon_device *rdev)
36{ 44{
@@ -42,9 +50,7 @@ int r420_mc_init(struct radeon_device *rdev)
42 if (rdev->flags & RADEON_IS_AGP) { 50 if (rdev->flags & RADEON_IS_AGP) {
43 r = radeon_agp_init(rdev); 51 r = radeon_agp_init(rdev);
44 if (r) { 52 if (r) {
45 printk(KERN_WARNING "[drm] Disabling AGP\n"); 53 radeon_agp_disable(rdev);
46 rdev->flags &= ~RADEON_IS_AGP;
47 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
48 } else { 54 } else {
49 rdev->mc.gtt_location = rdev->mc.agp_base; 55 rdev->mc.gtt_location = rdev->mc.agp_base;
50 } 56 }
@@ -165,6 +171,34 @@ static void r420_clock_resume(struct radeon_device *rdev)
165 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); 171 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
166} 172}
167 173
174static void r420_cp_errata_init(struct radeon_device *rdev)
175{
176 /* RV410 and R420 can lock up if CP DMA to host memory happens
177 * while the 2D engine is busy.
178 *
179 * The proper workaround is to queue a RESYNC at the beginning
180 * of the CP init, apparently.
181 */
182 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
183 radeon_ring_lock(rdev, 8);
184 radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
185 radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
186 radeon_ring_write(rdev, 0xDEADBEEF);
187 radeon_ring_unlock_commit(rdev);
188}
189
190static void r420_cp_errata_fini(struct radeon_device *rdev)
191{
192 /* Catch the RESYNC we dispatched all the way back,
193 * at the very beginning of the CP init.
194 */
195 radeon_ring_lock(rdev, 8);
196 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
197 radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
198 radeon_ring_unlock_commit(rdev);
199 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
200}
201
168static int r420_startup(struct radeon_device *rdev) 202static int r420_startup(struct radeon_device *rdev)
169{ 203{
170 int r; 204 int r;
@@ -190,12 +224,14 @@ static int r420_startup(struct radeon_device *rdev)
190 r420_pipes_init(rdev); 224 r420_pipes_init(rdev);
191 /* Enable IRQ */ 225 /* Enable IRQ */
192 r100_irq_set(rdev); 226 r100_irq_set(rdev);
227 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
193 /* 1M ring buffer */ 228 /* 1M ring buffer */
194 r = r100_cp_init(rdev, 1024 * 1024); 229 r = r100_cp_init(rdev, 1024 * 1024);
195 if (r) { 230 if (r) {
196 dev_err(rdev->dev, "failled initializing CP (%d).\n", r); 231 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
197 return r; 232 return r;
198 } 233 }
234 r420_cp_errata_init(rdev);
199 r = r100_wb_init(rdev); 235 r = r100_wb_init(rdev);
200 if (r) { 236 if (r) {
201 dev_err(rdev->dev, "failled initializing WB (%d).\n", r); 237 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
@@ -238,6 +274,7 @@ int r420_resume(struct radeon_device *rdev)
238 274
239int r420_suspend(struct radeon_device *rdev) 275int r420_suspend(struct radeon_device *rdev)
240{ 276{
277 r420_cp_errata_fini(rdev);
241 r100_cp_disable(rdev); 278 r100_cp_disable(rdev);
242 r100_wb_disable(rdev); 279 r100_wb_disable(rdev);
243 r100_irq_disable(rdev); 280 r100_irq_disable(rdev);
@@ -346,22 +383,21 @@ int r420_init(struct radeon_device *rdev)
346 if (r) 383 if (r)
347 return r; 384 return r;
348 } 385 }
349 r300_set_reg_safe(rdev); 386 r420_set_reg_safe(rdev);
350 rdev->accel_working = true; 387 rdev->accel_working = true;
351 r = r420_startup(rdev); 388 r = r420_startup(rdev);
352 if (r) { 389 if (r) {
353 /* Somethings want wront with the accel init stop accel */ 390 /* Somethings want wront with the accel init stop accel */
354 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 391 dev_err(rdev->dev, "Disabling GPU acceleration\n");
355 r420_suspend(rdev);
356 r100_cp_fini(rdev); 392 r100_cp_fini(rdev);
357 r100_wb_fini(rdev); 393 r100_wb_fini(rdev);
358 r100_ib_fini(rdev); 394 r100_ib_fini(rdev);
395 radeon_irq_kms_fini(rdev);
359 if (rdev->flags & RADEON_IS_PCIE) 396 if (rdev->flags & RADEON_IS_PCIE)
360 rv370_pcie_gart_fini(rdev); 397 rv370_pcie_gart_fini(rdev);
361 if (rdev->flags & RADEON_IS_PCI) 398 if (rdev->flags & RADEON_IS_PCI)
362 r100_pci_gart_fini(rdev); 399 r100_pci_gart_fini(rdev);
363 radeon_agp_fini(rdev); 400 radeon_agp_fini(rdev);
364 radeon_irq_kms_fini(rdev);
365 rdev->accel_working = false; 401 rdev->accel_working = false;
366 } 402 }
367 return 0; 403 return 0;
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 0f3843b6dac..ddf5731eba0 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -186,6 +186,7 @@ static int r520_startup(struct radeon_device *rdev)
186 } 186 }
187 /* Enable IRQ */ 187 /* Enable IRQ */
188 rs600_irq_set(rdev); 188 rs600_irq_set(rdev);
189 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
189 /* 1M ring buffer */ 190 /* 1M ring buffer */
190 r = r100_cp_init(rdev, 1024 * 1024); 191 r = r100_cp_init(rdev, 1024 * 1024);
191 if (r) { 192 if (r) {
@@ -293,13 +294,12 @@ int r520_init(struct radeon_device *rdev)
293 if (r) { 294 if (r) {
294 /* Somethings want wront with the accel init stop accel */ 295 /* Somethings want wront with the accel init stop accel */
295 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 296 dev_err(rdev->dev, "Disabling GPU acceleration\n");
296 rv515_suspend(rdev);
297 r100_cp_fini(rdev); 297 r100_cp_fini(rdev);
298 r100_wb_fini(rdev); 298 r100_wb_fini(rdev);
299 r100_ib_fini(rdev); 299 r100_ib_fini(rdev);
300 radeon_irq_kms_fini(rdev);
300 rv370_pcie_gart_fini(rdev); 301 rv370_pcie_gart_fini(rdev);
301 radeon_agp_fini(rdev); 302 radeon_agp_fini(rdev);
302 radeon_irq_kms_fini(rdev);
303 rdev->accel_working = false; 303 rdev->accel_working = false;
304 } 304 }
305 return 0; 305 return 0;
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index a0ac3c134b1..2ffcf5a0355 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -285,7 +285,8 @@ void r600_hpd_init(struct radeon_device *rdev)
285 } 285 }
286 } 286 }
287 } 287 }
288 r600_irq_set(rdev); 288 if (rdev->irq.installed)
289 r600_irq_set(rdev);
289} 290}
290 291
291void r600_hpd_fini(struct radeon_device *rdev) 292void r600_hpd_fini(struct radeon_device *rdev)
@@ -623,7 +624,6 @@ int r600_mc_init(struct radeon_device *rdev)
623 fixed20_12 a; 624 fixed20_12 a;
624 u32 tmp; 625 u32 tmp;
625 int chansize, numchan; 626 int chansize, numchan;
626 int r;
627 627
628 /* Get VRAM informations */ 628 /* Get VRAM informations */
629 rdev->mc.vram_is_ddr = true; 629 rdev->mc.vram_is_ddr = true;
@@ -666,9 +666,6 @@ int r600_mc_init(struct radeon_device *rdev)
666 rdev->mc.real_vram_size = rdev->mc.aper_size; 666 rdev->mc.real_vram_size = rdev->mc.aper_size;
667 667
668 if (rdev->flags & RADEON_IS_AGP) { 668 if (rdev->flags & RADEON_IS_AGP) {
669 r = radeon_agp_init(rdev);
670 if (r)
671 return r;
672 /* gtt_size is setup by radeon_agp_init */ 669 /* gtt_size is setup by radeon_agp_init */
673 rdev->mc.gtt_location = rdev->mc.agp_base; 670 rdev->mc.gtt_location = rdev->mc.agp_base;
674 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; 671 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
@@ -726,6 +723,10 @@ int r600_mc_init(struct radeon_device *rdev)
726 a.full = rfixed_const(100); 723 a.full = rfixed_const(100);
727 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); 724 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
728 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); 725 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
726
727 if (rdev->flags & RADEON_IS_IGP)
728 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
729
729 return 0; 730 return 0;
730} 731}
731 732
@@ -1384,11 +1385,6 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1384 (void)RREG32(PCIE_PORT_DATA); 1385 (void)RREG32(PCIE_PORT_DATA);
1385} 1386}
1386 1387
1387void r600_hdp_flush(struct radeon_device *rdev)
1388{
1389 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1390}
1391
1392/* 1388/*
1393 * CP & Ring 1389 * CP & Ring
1394 */ 1390 */
@@ -1658,6 +1654,12 @@ void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1658 rdev->cp.align_mask = 16 - 1; 1654 rdev->cp.align_mask = 16 - 1;
1659} 1655}
1660 1656
1657void r600_cp_fini(struct radeon_device *rdev)
1658{
1659 r600_cp_stop(rdev);
1660 radeon_ring_fini(rdev);
1661}
1662
1661 1663
1662/* 1664/*
1663 * GPU scratch registers helpers function. 1665 * GPU scratch registers helpers function.
@@ -1785,28 +1787,31 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
1785 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 1787 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1786 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 1788 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1787 radeon_ring_write(rdev, fence->seq); 1789 radeon_ring_write(rdev, fence->seq);
1790 radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
1791 radeon_ring_write(rdev, 1);
1788 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 1792 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1789 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); 1793 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1790 radeon_ring_write(rdev, RB_INT_STAT); 1794 radeon_ring_write(rdev, RB_INT_STAT);
1791} 1795}
1792 1796
1793int r600_copy_dma(struct radeon_device *rdev,
1794 uint64_t src_offset,
1795 uint64_t dst_offset,
1796 unsigned num_pages,
1797 struct radeon_fence *fence)
1798{
1799 /* FIXME: implement */
1800 return 0;
1801}
1802
1803int r600_copy_blit(struct radeon_device *rdev, 1797int r600_copy_blit(struct radeon_device *rdev,
1804 uint64_t src_offset, uint64_t dst_offset, 1798 uint64_t src_offset, uint64_t dst_offset,
1805 unsigned num_pages, struct radeon_fence *fence) 1799 unsigned num_pages, struct radeon_fence *fence)
1806{ 1800{
1807 r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); 1801 int r;
1802
1803 mutex_lock(&rdev->r600_blit.mutex);
1804 rdev->r600_blit.vb_ib = NULL;
1805 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1806 if (r) {
1807 if (rdev->r600_blit.vb_ib)
1808 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1809 mutex_unlock(&rdev->r600_blit.mutex);
1810 return r;
1811 }
1808 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); 1812 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1809 r600_blit_done_copy(rdev, fence); 1813 r600_blit_done_copy(rdev, fence);
1814 mutex_unlock(&rdev->r600_blit.mutex);
1810 return 0; 1815 return 0;
1811} 1816}
1812 1817
@@ -1862,26 +1867,25 @@ int r600_startup(struct radeon_device *rdev)
1862 return r; 1867 return r;
1863 } 1868 }
1864 r600_gpu_init(rdev); 1869 r600_gpu_init(rdev);
1865 1870 r = r600_blit_init(rdev);
1866 if (!rdev->r600_blit.shader_obj) { 1871 if (r) {
1867 r = r600_blit_init(rdev); 1872 r600_blit_fini(rdev);
1873 rdev->asic->copy = NULL;
1874 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1875 }
1876 /* pin copy shader into vram */
1877 if (rdev->r600_blit.shader_obj) {
1878 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1879 if (unlikely(r != 0))
1880 return r;
1881 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1882 &rdev->r600_blit.shader_gpu_addr);
1883 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1868 if (r) { 1884 if (r) {
1869 DRM_ERROR("radeon: failed blitter (%d).\n", r); 1885 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1870 return r; 1886 return r;
1871 } 1887 }
1872 } 1888 }
1873
1874 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1875 if (unlikely(r != 0))
1876 return r;
1877 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1878 &rdev->r600_blit.shader_gpu_addr);
1879 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1880 if (r) {
1881 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1882 return r;
1883 }
1884
1885 /* Enable IRQ */ 1889 /* Enable IRQ */
1886 r = r600_irq_init(rdev); 1890 r = r600_irq_init(rdev);
1887 if (r) { 1891 if (r) {
@@ -1946,6 +1950,13 @@ int r600_resume(struct radeon_device *rdev)
1946 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1950 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1947 return r; 1951 return r;
1948 } 1952 }
1953
1954 r = r600_audio_init(rdev);
1955 if (r) {
1956 DRM_ERROR("radeon: audio resume failed\n");
1957 return r;
1958 }
1959
1949 return r; 1960 return r;
1950} 1961}
1951 1962
@@ -1953,17 +1964,21 @@ int r600_suspend(struct radeon_device *rdev)
1953{ 1964{
1954 int r; 1965 int r;
1955 1966
1967 r600_audio_fini(rdev);
1956 /* FIXME: we should wait for ring to be empty */ 1968 /* FIXME: we should wait for ring to be empty */
1957 r600_cp_stop(rdev); 1969 r600_cp_stop(rdev);
1958 rdev->cp.ready = false; 1970 rdev->cp.ready = false;
1971 r600_irq_suspend(rdev);
1959 r600_wb_disable(rdev); 1972 r600_wb_disable(rdev);
1960 r600_pcie_gart_disable(rdev); 1973 r600_pcie_gart_disable(rdev);
1961 /* unpin shaders bo */ 1974 /* unpin shaders bo */
1962 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1975 if (rdev->r600_blit.shader_obj) {
1963 if (unlikely(r != 0)) 1976 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1964 return r; 1977 if (!r) {
1965 radeon_bo_unpin(rdev->r600_blit.shader_obj); 1978 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1966 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 1979 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1980 }
1981 }
1967 return 0; 1982 return 0;
1968} 1983}
1969 1984
@@ -2024,6 +2039,11 @@ int r600_init(struct radeon_device *rdev)
2024 r = radeon_fence_driver_init(rdev); 2039 r = radeon_fence_driver_init(rdev);
2025 if (r) 2040 if (r)
2026 return r; 2041 return r;
2042 if (rdev->flags & RADEON_IS_AGP) {
2043 r = radeon_agp_init(rdev);
2044 if (r)
2045 radeon_agp_disable(rdev);
2046 }
2027 r = r600_mc_init(rdev); 2047 r = r600_mc_init(rdev);
2028 if (r) 2048 if (r)
2029 return r; 2049 return r;
@@ -2049,22 +2069,25 @@ int r600_init(struct radeon_device *rdev)
2049 rdev->accel_working = true; 2069 rdev->accel_working = true;
2050 r = r600_startup(rdev); 2070 r = r600_startup(rdev);
2051 if (r) { 2071 if (r) {
2052 r600_suspend(rdev); 2072 dev_err(rdev->dev, "disabling GPU acceleration\n");
2073 r600_cp_fini(rdev);
2053 r600_wb_fini(rdev); 2074 r600_wb_fini(rdev);
2054 radeon_ring_fini(rdev); 2075 r600_irq_fini(rdev);
2076 radeon_irq_kms_fini(rdev);
2055 r600_pcie_gart_fini(rdev); 2077 r600_pcie_gart_fini(rdev);
2056 rdev->accel_working = false; 2078 rdev->accel_working = false;
2057 } 2079 }
2058 if (rdev->accel_working) { 2080 if (rdev->accel_working) {
2059 r = radeon_ib_pool_init(rdev); 2081 r = radeon_ib_pool_init(rdev);
2060 if (r) { 2082 if (r) {
2061 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 2083 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2062 rdev->accel_working = false;
2063 }
2064 r = r600_ib_test(rdev);
2065 if (r) {
2066 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2067 rdev->accel_working = false; 2084 rdev->accel_working = false;
2085 } else {
2086 r = r600_ib_test(rdev);
2087 if (r) {
2088 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2089 rdev->accel_working = false;
2090 }
2068 } 2091 }
2069 } 2092 }
2070 2093
@@ -2076,21 +2099,17 @@ int r600_init(struct radeon_device *rdev)
2076 2099
2077void r600_fini(struct radeon_device *rdev) 2100void r600_fini(struct radeon_device *rdev)
2078{ 2101{
2079 /* Suspend operations */
2080 r600_suspend(rdev);
2081
2082 r600_audio_fini(rdev); 2102 r600_audio_fini(rdev);
2083 r600_blit_fini(rdev); 2103 r600_blit_fini(rdev);
2104 r600_cp_fini(rdev);
2105 r600_wb_fini(rdev);
2084 r600_irq_fini(rdev); 2106 r600_irq_fini(rdev);
2085 radeon_irq_kms_fini(rdev); 2107 radeon_irq_kms_fini(rdev);
2086 radeon_ring_fini(rdev);
2087 r600_wb_fini(rdev);
2088 r600_pcie_gart_fini(rdev); 2108 r600_pcie_gart_fini(rdev);
2109 radeon_agp_fini(rdev);
2089 radeon_gem_fini(rdev); 2110 radeon_gem_fini(rdev);
2090 radeon_fence_driver_fini(rdev); 2111 radeon_fence_driver_fini(rdev);
2091 radeon_clocks_fini(rdev); 2112 radeon_clocks_fini(rdev);
2092 if (rdev->flags & RADEON_IS_AGP)
2093 radeon_agp_fini(rdev);
2094 radeon_bo_fini(rdev); 2113 radeon_bo_fini(rdev);
2095 radeon_atombios_fini(rdev); 2114 radeon_atombios_fini(rdev);
2096 kfree(rdev->bios); 2115 kfree(rdev->bios);
@@ -2196,14 +2215,14 @@ void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2196 rb_bufsz = drm_order(ring_size / 4); 2215 rb_bufsz = drm_order(ring_size / 4);
2197 ring_size = (1 << rb_bufsz) * 4; 2216 ring_size = (1 << rb_bufsz) * 4;
2198 rdev->ih.ring_size = ring_size; 2217 rdev->ih.ring_size = ring_size;
2199 rdev->ih.align_mask = 4 - 1; 2218 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2219 rdev->ih.rptr = 0;
2200} 2220}
2201 2221
2202static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size) 2222static int r600_ih_ring_alloc(struct radeon_device *rdev)
2203{ 2223{
2204 int r; 2224 int r;
2205 2225
2206 rdev->ih.ring_size = ring_size;
2207 /* Allocate ring buffer */ 2226 /* Allocate ring buffer */
2208 if (rdev->ih.ring_obj == NULL) { 2227 if (rdev->ih.ring_obj == NULL) {
2209 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, 2228 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
@@ -2233,9 +2252,6 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev, unsigned ring_size)
2233 return r; 2252 return r;
2234 } 2253 }
2235 } 2254 }
2236 rdev->ih.ptr_mask = (rdev->cp.ring_size / 4) - 1;
2237 rdev->ih.rptr = 0;
2238
2239 return 0; 2255 return 0;
2240} 2256}
2241 2257
@@ -2385,7 +2401,7 @@ int r600_irq_init(struct radeon_device *rdev)
2385 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 2401 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2386 2402
2387 /* allocate ring */ 2403 /* allocate ring */
2388 ret = r600_ih_ring_alloc(rdev, rdev->ih.ring_size); 2404 ret = r600_ih_ring_alloc(rdev);
2389 if (ret) 2405 if (ret)
2390 return ret; 2406 return ret;
2391 2407
@@ -2448,10 +2464,15 @@ int r600_irq_init(struct radeon_device *rdev)
2448 return ret; 2464 return ret;
2449} 2465}
2450 2466
2451void r600_irq_fini(struct radeon_device *rdev) 2467void r600_irq_suspend(struct radeon_device *rdev)
2452{ 2468{
2453 r600_disable_interrupts(rdev); 2469 r600_disable_interrupts(rdev);
2454 r600_rlc_stop(rdev); 2470 r600_rlc_stop(rdev);
2471}
2472
2473void r600_irq_fini(struct radeon_device *rdev)
2474{
2475 r600_irq_suspend(rdev);
2455 r600_ih_ring_fini(rdev); 2476 r600_ih_ring_fini(rdev);
2456} 2477}
2457 2478
@@ -2461,9 +2482,17 @@ int r600_irq_set(struct radeon_device *rdev)
2461 u32 mode_int = 0; 2482 u32 mode_int = 0;
2462 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; 2483 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2463 2484
2485 if (!rdev->irq.installed) {
2486 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2487 return -EINVAL;
2488 }
2464 /* don't enable anything if the ih is disabled */ 2489 /* don't enable anything if the ih is disabled */
2465 if (!rdev->ih.enabled) 2490 if (!rdev->ih.enabled) {
2491 r600_disable_interrupts(rdev);
2492 /* force the active interrupt state to all disabled */
2493 r600_disable_interrupt_state(rdev);
2466 return 0; 2494 return 0;
2495 }
2467 2496
2468 if (ASIC_IS_DCE3(rdev)) { 2497 if (ASIC_IS_DCE3(rdev)) {
2469 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN; 2498 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
@@ -2633,16 +2662,18 @@ static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2633 wptr = RREG32(IH_RB_WPTR); 2662 wptr = RREG32(IH_RB_WPTR);
2634 2663
2635 if (wptr & RB_OVERFLOW) { 2664 if (wptr & RB_OVERFLOW) {
2636 WARN_ON(1); 2665 /* When a ring buffer overflow happen start parsing interrupt
2637 /* XXX deal with overflow */ 2666 * from the last not overwritten vector (wptr + 16). Hopefully
2638 DRM_ERROR("IH RB overflow\n"); 2667 * this should allow us to catchup.
2668 */
2669 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2670 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2671 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2639 tmp = RREG32(IH_RB_CNTL); 2672 tmp = RREG32(IH_RB_CNTL);
2640 tmp |= IH_WPTR_OVERFLOW_CLEAR; 2673 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2641 WREG32(IH_RB_CNTL, tmp); 2674 WREG32(IH_RB_CNTL, tmp);
2642 } 2675 }
2643 wptr = wptr & WPTR_OFFSET_MASK; 2676 return (wptr & rdev->ih.ptr_mask);
2644
2645 return wptr;
2646} 2677}
2647 2678
2648/* r600 IV Ring 2679/* r600 IV Ring
@@ -2678,12 +2709,13 @@ int r600_irq_process(struct radeon_device *rdev)
2678 u32 wptr = r600_get_ih_wptr(rdev); 2709 u32 wptr = r600_get_ih_wptr(rdev);
2679 u32 rptr = rdev->ih.rptr; 2710 u32 rptr = rdev->ih.rptr;
2680 u32 src_id, src_data; 2711 u32 src_id, src_data;
2681 u32 last_entry = rdev->ih.ring_size - 16;
2682 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2; 2712 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2683 unsigned long flags; 2713 unsigned long flags;
2684 bool queue_hotplug = false; 2714 bool queue_hotplug = false;
2685 2715
2686 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2716 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2717 if (!rdev->ih.enabled)
2718 return IRQ_NONE;
2687 2719
2688 spin_lock_irqsave(&rdev->ih.lock, flags); 2720 spin_lock_irqsave(&rdev->ih.lock, flags);
2689 2721
@@ -2724,7 +2756,7 @@ restart_ih:
2724 } 2756 }
2725 break; 2757 break;
2726 default: 2758 default:
2727 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2759 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2728 break; 2760 break;
2729 } 2761 }
2730 break; 2762 break;
@@ -2744,7 +2776,7 @@ restart_ih:
2744 } 2776 }
2745 break; 2777 break;
2746 default: 2778 default:
2747 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2779 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2748 break; 2780 break;
2749 } 2781 }
2750 break; 2782 break;
@@ -2793,7 +2825,7 @@ restart_ih:
2793 } 2825 }
2794 break; 2826 break;
2795 default: 2827 default:
2796 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2828 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2797 break; 2829 break;
2798 } 2830 }
2799 break; 2831 break;
@@ -2807,15 +2839,13 @@ restart_ih:
2807 DRM_DEBUG("IH: CP EOP\n"); 2839 DRM_DEBUG("IH: CP EOP\n");
2808 break; 2840 break;
2809 default: 2841 default:
2810 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 2842 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2811 break; 2843 break;
2812 } 2844 }
2813 2845
2814 /* wptr/rptr are in bytes! */ 2846 /* wptr/rptr are in bytes! */
2815 if (rptr == last_entry) 2847 rptr += 16;
2816 rptr = 0; 2848 rptr &= rdev->ih.ptr_mask;
2817 else
2818 rptr += 16;
2819 } 2849 }
2820 /* make sure wptr hasn't changed while processing */ 2850 /* make sure wptr hasn't changed while processing */
2821 wptr = r600_get_ih_wptr(rdev); 2851 wptr = r600_get_ih_wptr(rdev);
@@ -2883,3 +2913,18 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2883 return 0; 2913 return 0;
2884#endif 2914#endif
2885} 2915}
2916
2917/**
2918 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2919 * rdev: radeon device structure
2920 * bo: buffer object struct which userspace is waiting for idle
2921 *
2922 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2923 * through ring buffer, this leads to corruption in rendering, see
2924 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2925 * directly perform HDP flush by writing register through MMIO.
2926 */
2927void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2928{
2929 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2930}
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index 99e2c3891a7..0dcb6904c4f 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -35,7 +35,7 @@
35 */ 35 */
36static int r600_audio_chipset_supported(struct radeon_device *rdev) 36static int r600_audio_chipset_supported(struct radeon_device *rdev)
37{ 37{
38 return rdev->family >= CHIP_R600 38 return (rdev->family >= CHIP_R600 && rdev->family < CHIP_RV710)
39 || rdev->family == CHIP_RS600 39 || rdev->family == CHIP_RS600
40 || rdev->family == CHIP_RS690 40 || rdev->family == CHIP_RS690
41 || rdev->family == CHIP_RS740; 41 || rdev->family == CHIP_RS740;
@@ -261,7 +261,6 @@ void r600_audio_fini(struct radeon_device *rdev)
261 if (!r600_audio_chipset_supported(rdev)) 261 if (!r600_audio_chipset_supported(rdev))
262 return; 262 return;
263 263
264 WREG32_P(R600_AUDIO_ENABLE, 0x0, ~0x81000000);
265
266 del_timer(&rdev->audio_timer); 264 del_timer(&rdev->audio_timer);
265 WREG32_P(R600_AUDIO_ENABLE, 0x0, ~0x81000000);
267} 266}
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 9aecafb51b6..af1c3ca8a4c 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -449,6 +449,7 @@ int r600_blit_init(struct radeon_device *rdev)
449 u32 packet2s[16]; 449 u32 packet2s[16];
450 int num_packet2s = 0; 450 int num_packet2s = 0;
451 451
452 mutex_init(&rdev->r600_blit.mutex);
452 rdev->r600_blit.state_offset = 0; 453 rdev->r600_blit.state_offset = 0;
453 454
454 if (rdev->family >= CHIP_RV770) 455 if (rdev->family >= CHIP_RV770)
@@ -512,14 +513,16 @@ void r600_blit_fini(struct radeon_device *rdev)
512{ 513{
513 int r; 514 int r;
514 515
516 if (rdev->r600_blit.shader_obj == NULL)
517 return;
518 /* If we can't reserve the bo, unref should be enough to destroy
519 * it when it becomes idle.
520 */
515 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 521 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
516 if (unlikely(r != 0)) { 522 if (!r) {
517 dev_err(rdev->dev, "(%d) can't finish r600 blit\n", r); 523 radeon_bo_unpin(rdev->r600_blit.shader_obj);
518 goto out_unref; 524 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
519 } 525 }
520 radeon_bo_unpin(rdev->r600_blit.shader_obj);
521 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
522out_unref:
523 radeon_bo_unref(&rdev->r600_blit.shader_obj); 526 radeon_bo_unref(&rdev->r600_blit.shader_obj);
524} 527}
525 528
@@ -555,7 +558,8 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
555 int dwords_per_loop = 76, num_loops; 558 int dwords_per_loop = 76, num_loops;
556 559
557 r = r600_vb_ib_get(rdev); 560 r = r600_vb_ib_get(rdev);
558 WARN_ON(r); 561 if (r)
562 return r;
559 563
560 /* set_render_target emits 2 extra dwords on rv6xx */ 564 /* set_render_target emits 2 extra dwords on rv6xx */
561 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) 565 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770)
@@ -577,11 +581,12 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
577 ring_size = num_loops * dwords_per_loop; 581 ring_size = num_loops * dwords_per_loop;
578 /* set default + shaders */ 582 /* set default + shaders */
579 ring_size += 40; /* shaders + def state */ 583 ring_size += 40; /* shaders + def state */
580 ring_size += 5; /* fence emit for VB IB */ 584 ring_size += 7; /* fence emit for VB IB */
581 ring_size += 5; /* done copy */ 585 ring_size += 5; /* done copy */
582 ring_size += 5; /* fence emit for done copy */ 586 ring_size += 7; /* fence emit for done copy */
583 r = radeon_ring_lock(rdev, ring_size); 587 r = radeon_ring_lock(rdev, ring_size);
584 WARN_ON(r); 588 if (r)
589 return r;
585 590
586 set_default_state(rdev); /* 14 */ 591 set_default_state(rdev); /* 14 */
587 set_shaders(rdev); /* 26 */ 592 set_shaders(rdev); /* 26 */
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 44060b92d9e..e4c45ec1650 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -36,6 +36,10 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
36typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); 36typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
37static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; 37static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
38 38
39struct r600_cs_track {
40 u32 cb_color0_base_last;
41};
42
39/** 43/**
40 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet 44 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet
41 * @parser: parser structure holding parsing context. 45 * @parser: parser structure holding parsing context.
@@ -177,6 +181,28 @@ static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
177} 181}
178 182
179/** 183/**
184 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
185 * @parser: parser structure holding parsing context.
186 *
187 * Check next packet is relocation packet3, do bo validation and compute
188 * GPU offset using the provided start.
189 **/
190static inline int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
191{
192 struct radeon_cs_packet p3reloc;
193 int r;
194
195 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
196 if (r) {
197 return 0;
198 }
199 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
200 return 0;
201 }
202 return 1;
203}
204
205/**
180 * r600_cs_packet_next_vline() - parse userspace VLINE packet 206 * r600_cs_packet_next_vline() - parse userspace VLINE packet
181 * @parser: parser structure holding parsing context. 207 * @parser: parser structure holding parsing context.
182 * 208 *
@@ -337,6 +363,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
337 struct radeon_cs_packet *pkt) 363 struct radeon_cs_packet *pkt)
338{ 364{
339 struct radeon_cs_reloc *reloc; 365 struct radeon_cs_reloc *reloc;
366 struct r600_cs_track *track;
340 volatile u32 *ib; 367 volatile u32 *ib;
341 unsigned idx; 368 unsigned idx;
342 unsigned i; 369 unsigned i;
@@ -344,6 +371,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
344 int r; 371 int r;
345 u32 idx_value; 372 u32 idx_value;
346 373
374 track = (struct r600_cs_track *)p->track;
347 ib = p->ib->ptr; 375 ib = p->ib->ptr;
348 idx = pkt->idx + 1; 376 idx = pkt->idx + 1;
349 idx_value = radeon_get_ib_value(p, idx); 377 idx_value = radeon_get_ib_value(p, idx);
@@ -503,9 +531,60 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
503 for (i = 0; i < pkt->count; i++) { 531 for (i = 0; i < pkt->count; i++) {
504 reg = start_reg + (4 * i); 532 reg = start_reg + (4 * i);
505 switch (reg) { 533 switch (reg) {
534 /* This register were added late, there is userspace
535 * which does provide relocation for those but set
536 * 0 offset. In order to avoid breaking old userspace
537 * we detect this and set address to point to last
538 * CB_COLOR0_BASE, note that if userspace doesn't set
539 * CB_COLOR0_BASE before this register we will report
540 * error. Old userspace always set CB_COLOR0_BASE
541 * before any of this.
542 */
543 case R_0280E0_CB_COLOR0_FRAG:
544 case R_0280E4_CB_COLOR1_FRAG:
545 case R_0280E8_CB_COLOR2_FRAG:
546 case R_0280EC_CB_COLOR3_FRAG:
547 case R_0280F0_CB_COLOR4_FRAG:
548 case R_0280F4_CB_COLOR5_FRAG:
549 case R_0280F8_CB_COLOR6_FRAG:
550 case R_0280FC_CB_COLOR7_FRAG:
551 case R_0280C0_CB_COLOR0_TILE:
552 case R_0280C4_CB_COLOR1_TILE:
553 case R_0280C8_CB_COLOR2_TILE:
554 case R_0280CC_CB_COLOR3_TILE:
555 case R_0280D0_CB_COLOR4_TILE:
556 case R_0280D4_CB_COLOR5_TILE:
557 case R_0280D8_CB_COLOR6_TILE:
558 case R_0280DC_CB_COLOR7_TILE:
559 if (!r600_cs_packet_next_is_pkt3_nop(p)) {
560 if (!track->cb_color0_base_last) {
561 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
562 return -EINVAL;
563 }
564 ib[idx+1+i] = track->cb_color0_base_last;
565 printk_once(KERN_WARNING "radeon: You have old & broken userspace "
566 "please consider updating mesa & xf86-video-ati\n");
567 } else {
568 r = r600_cs_packet_next_reloc(p, &reloc);
569 if (r) {
570 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
571 return -EINVAL;
572 }
573 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
574 }
575 break;
506 case DB_DEPTH_BASE: 576 case DB_DEPTH_BASE:
507 case DB_HTILE_DATA_BASE: 577 case DB_HTILE_DATA_BASE:
508 case CB_COLOR0_BASE: 578 case CB_COLOR0_BASE:
579 r = r600_cs_packet_next_reloc(p, &reloc);
580 if (r) {
581 DRM_ERROR("bad SET_CONTEXT_REG "
582 "0x%04X\n", reg);
583 return -EINVAL;
584 }
585 ib[idx+1+i] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
586 track->cb_color0_base_last = ib[idx+1+i];
587 break;
509 case CB_COLOR1_BASE: 588 case CB_COLOR1_BASE:
510 case CB_COLOR2_BASE: 589 case CB_COLOR2_BASE:
511 case CB_COLOR3_BASE: 590 case CB_COLOR3_BASE:
@@ -678,8 +757,11 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
678int r600_cs_parse(struct radeon_cs_parser *p) 757int r600_cs_parse(struct radeon_cs_parser *p)
679{ 758{
680 struct radeon_cs_packet pkt; 759 struct radeon_cs_packet pkt;
760 struct r600_cs_track *track;
681 int r; 761 int r;
682 762
763 track = kzalloc(sizeof(*track), GFP_KERNEL);
764 p->track = track;
683 do { 765 do {
684 r = r600_cs_packet_parse(p, &pkt, p->idx); 766 r = r600_cs_packet_parse(p, &pkt, p->idx);
685 if (r) { 767 if (r) {
@@ -757,6 +839,7 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
757 /* initialize parser */ 839 /* initialize parser */
758 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 840 memset(&parser, 0, sizeof(struct radeon_cs_parser));
759 parser.filp = filp; 841 parser.filp = filp;
842 parser.dev = &dev->pdev->dev;
760 parser.rdev = NULL; 843 parser.rdev = NULL;
761 parser.family = family; 844 parser.family = family;
762 parser.ib = &fake_ib; 845 parser.ib = &fake_ib;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 05894edadab..30480881aed 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -882,4 +882,29 @@
882#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 882#define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17)
883 883
884#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 884#define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
885
886#define R_0280E0_CB_COLOR0_FRAG 0x0280E0
887#define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
888#define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
889#define C_0280E0_BASE_256B 0x00000000
890#define R_0280E4_CB_COLOR1_FRAG 0x0280E4
891#define R_0280E8_CB_COLOR2_FRAG 0x0280E8
892#define R_0280EC_CB_COLOR3_FRAG 0x0280EC
893#define R_0280F0_CB_COLOR4_FRAG 0x0280F0
894#define R_0280F4_CB_COLOR5_FRAG 0x0280F4
895#define R_0280F8_CB_COLOR6_FRAG 0x0280F8
896#define R_0280FC_CB_COLOR7_FRAG 0x0280FC
897#define R_0280C0_CB_COLOR0_TILE 0x0280C0
898#define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0)
899#define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF)
900#define C_0280C0_BASE_256B 0x00000000
901#define R_0280C4_CB_COLOR1_TILE 0x0280C4
902#define R_0280C8_CB_COLOR2_TILE 0x0280C8
903#define R_0280CC_CB_COLOR3_TILE 0x0280CC
904#define R_0280D0_CB_COLOR4_TILE 0x0280D0
905#define R_0280D4_CB_COLOR5_TILE 0x0280D4
906#define R_0280D8_CB_COLOR6_TILE 0x0280D8
907#define R_0280DC_CB_COLOR7_TILE 0x0280DC
908
909
885#endif 910#endif
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 53b55608102..f57480ba135 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -319,10 +319,12 @@ struct radeon_mc {
319 u64 real_vram_size; 319 u64 real_vram_size;
320 int vram_mtrr; 320 int vram_mtrr;
321 bool vram_is_ddr; 321 bool vram_is_ddr;
322 bool igp_sideport_enabled;
322}; 323};
323 324
324int radeon_mc_setup(struct radeon_device *rdev); 325int radeon_mc_setup(struct radeon_device *rdev);
325 326bool radeon_combios_sideport_present(struct radeon_device *rdev);
327bool radeon_atombios_sideport_present(struct radeon_device *rdev);
326 328
327/* 329/*
328 * GPU scratch registers structures, functions & helpers 330 * GPU scratch registers structures, functions & helpers
@@ -408,13 +410,13 @@ struct r600_ih {
408 unsigned wptr_old; 410 unsigned wptr_old;
409 unsigned ring_size; 411 unsigned ring_size;
410 uint64_t gpu_addr; 412 uint64_t gpu_addr;
411 uint32_t align_mask;
412 uint32_t ptr_mask; 413 uint32_t ptr_mask;
413 spinlock_t lock; 414 spinlock_t lock;
414 bool enabled; 415 bool enabled;
415}; 416};
416 417
417struct r600_blit { 418struct r600_blit {
419 struct mutex mutex;
418 struct radeon_bo *shader_obj; 420 struct radeon_bo *shader_obj;
419 u64 shader_gpu_addr; 421 u64 shader_gpu_addr;
420 u32 vs_offset, ps_offset; 422 u32 vs_offset, ps_offset;
@@ -463,6 +465,7 @@ struct radeon_cs_chunk {
463}; 465};
464 466
465struct radeon_cs_parser { 467struct radeon_cs_parser {
468 struct device *dev;
466 struct radeon_device *rdev; 469 struct radeon_device *rdev;
467 struct drm_file *filp; 470 struct drm_file *filp;
468 /* chunks */ 471 /* chunks */
@@ -654,11 +657,17 @@ struct radeon_asic {
654 uint32_t offset, uint32_t obj_size); 657 uint32_t offset, uint32_t obj_size);
655 int (*clear_surface_reg)(struct radeon_device *rdev, int reg); 658 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
656 void (*bandwidth_update)(struct radeon_device *rdev); 659 void (*bandwidth_update)(struct radeon_device *rdev);
657 void (*hdp_flush)(struct radeon_device *rdev);
658 void (*hpd_init)(struct radeon_device *rdev); 660 void (*hpd_init)(struct radeon_device *rdev);
659 void (*hpd_fini)(struct radeon_device *rdev); 661 void (*hpd_fini)(struct radeon_device *rdev);
660 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 662 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
661 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); 663 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
664 /* ioctl hw specific callback. Some hw might want to perform special
665 * operation on specific ioctl. For instance on wait idle some hw
666 * might want to perform and HDP flush through MMIO as it seems that
667 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
668 * through ring.
669 */
670 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
662}; 671};
663 672
664/* 673/*
@@ -667,11 +676,14 @@ struct radeon_asic {
667struct r100_asic { 676struct r100_asic {
668 const unsigned *reg_safe_bm; 677 const unsigned *reg_safe_bm;
669 unsigned reg_safe_bm_size; 678 unsigned reg_safe_bm_size;
679 u32 hdp_cntl;
670}; 680};
671 681
672struct r300_asic { 682struct r300_asic {
673 const unsigned *reg_safe_bm; 683 const unsigned *reg_safe_bm;
674 unsigned reg_safe_bm_size; 684 unsigned reg_safe_bm_size;
685 u32 resync_scratch;
686 u32 hdp_cntl;
675}; 687};
676 688
677struct r600_asic { 689struct r600_asic {
@@ -843,7 +855,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev,
843 855
844static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 856static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
845{ 857{
846 if (reg < 0x10000) 858 if (reg < rdev->rmmio_size)
847 return readl(((void __iomem *)rdev->rmmio) + reg); 859 return readl(((void __iomem *)rdev->rmmio) + reg);
848 else { 860 else {
849 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 861 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -853,7 +865,7 @@ static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
853 865
854static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) 866static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
855{ 867{
856 if (reg < 0x10000) 868 if (reg < rdev->rmmio_size)
857 writel(v, ((void __iomem *)rdev->rmmio) + reg); 869 writel(v, ((void __iomem *)rdev->rmmio) + reg);
858 else { 870 else {
859 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); 871 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
@@ -1007,13 +1019,14 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1007#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 1019#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1008#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 1020#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1009#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 1021#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1010#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
1011#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) 1022#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1012#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) 1023#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1013#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) 1024#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1014#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) 1025#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1015 1026
1016/* Common functions */ 1027/* Common functions */
1028/* AGP */
1029extern void radeon_agp_disable(struct radeon_device *rdev);
1017extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 1030extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1018extern int radeon_modeset_init(struct radeon_device *rdev); 1031extern int radeon_modeset_init(struct radeon_device *rdev);
1019extern void radeon_modeset_fini(struct radeon_device *rdev); 1032extern void radeon_modeset_fini(struct radeon_device *rdev);
@@ -1137,6 +1150,7 @@ extern bool r600_card_posted(struct radeon_device *rdev);
1137extern void r600_cp_stop(struct radeon_device *rdev); 1150extern void r600_cp_stop(struct radeon_device *rdev);
1138extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 1151extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1139extern int r600_cp_resume(struct radeon_device *rdev); 1152extern int r600_cp_resume(struct radeon_device *rdev);
1153extern void r600_cp_fini(struct radeon_device *rdev);
1140extern int r600_count_pipe_bits(uint32_t val); 1154extern int r600_count_pipe_bits(uint32_t val);
1141extern int r600_gart_clear_page(struct radeon_device *rdev, int i); 1155extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
1142extern int r600_mc_wait_for_idle(struct radeon_device *rdev); 1156extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
@@ -1157,7 +1171,8 @@ extern int r600_irq_init(struct radeon_device *rdev);
1157extern void r600_irq_fini(struct radeon_device *rdev); 1171extern void r600_irq_fini(struct radeon_device *rdev);
1158extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size); 1172extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1159extern int r600_irq_set(struct radeon_device *rdev); 1173extern int r600_irq_set(struct radeon_device *rdev);
1160 1174extern void r600_irq_suspend(struct radeon_device *rdev);
1175/* r600 audio */
1161extern int r600_audio_init(struct radeon_device *rdev); 1176extern int r600_audio_init(struct radeon_device *rdev);
1162extern int r600_audio_tmds_index(struct drm_encoder *encoder); 1177extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1163extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock); 1178extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c
index 54bf49a6d67..c0681a5556d 100644
--- a/drivers/gpu/drm/radeon/radeon_agp.c
+++ b/drivers/gpu/drm/radeon/radeon_agp.c
@@ -144,9 +144,19 @@ int radeon_agp_init(struct radeon_device *rdev)
144 144
145 ret = drm_agp_info(rdev->ddev, &info); 145 ret = drm_agp_info(rdev->ddev, &info);
146 if (ret) { 146 if (ret) {
147 drm_agp_release(rdev->ddev);
147 DRM_ERROR("Unable to get AGP info: %d\n", ret); 148 DRM_ERROR("Unable to get AGP info: %d\n", ret);
148 return ret; 149 return ret;
149 } 150 }
151
152 if (rdev->ddev->agp->agp_info.aper_size < 32) {
153 drm_agp_release(rdev->ddev);
154 dev_warn(rdev->dev, "AGP aperture too small (%zuM) "
155 "need at least 32M, disabling AGP\n",
156 rdev->ddev->agp->agp_info.aper_size);
157 return -EINVAL;
158 }
159
150 mode.mode = info.mode; 160 mode.mode = info.mode;
151 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode; 161 agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
152 is_v3 = !!(agp_status & RADEON_AGPv3_MODE); 162 is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
@@ -221,6 +231,7 @@ int radeon_agp_init(struct radeon_device *rdev)
221 ret = drm_agp_enable(rdev->ddev, mode); 231 ret = drm_agp_enable(rdev->ddev, mode);
222 if (ret) { 232 if (ret) {
223 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode); 233 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
234 drm_agp_release(rdev->ddev);
224 return ret; 235 return ret;
225 } 236 }
226 237
@@ -252,10 +263,8 @@ void radeon_agp_resume(struct radeon_device *rdev)
252void radeon_agp_fini(struct radeon_device *rdev) 263void radeon_agp_fini(struct radeon_device *rdev)
253{ 264{
254#if __OS_HAS_AGP 265#if __OS_HAS_AGP
255 if (rdev->flags & RADEON_IS_AGP) { 266 if (rdev->ddev->agp && rdev->ddev->agp->acquired) {
256 if (rdev->ddev->agp && rdev->ddev->agp->acquired) { 267 drm_agp_release(rdev->ddev);
257 drm_agp_release(rdev->ddev);
258 }
259 } 268 }
260#endif 269#endif
261} 270}
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index eb29217bbf1..05ee1aeac3f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -77,7 +77,6 @@ int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
77void r100_bandwidth_update(struct radeon_device *rdev); 77void r100_bandwidth_update(struct radeon_device *rdev);
78void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 78void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
79int r100_ring_test(struct radeon_device *rdev); 79int r100_ring_test(struct radeon_device *rdev);
80void r100_hdp_flush(struct radeon_device *rdev);
81void r100_hpd_init(struct radeon_device *rdev); 80void r100_hpd_init(struct radeon_device *rdev);
82void r100_hpd_fini(struct radeon_device *rdev); 81void r100_hpd_fini(struct radeon_device *rdev);
83bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 82bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
@@ -114,11 +113,11 @@ static struct radeon_asic r100_asic = {
114 .set_surface_reg = r100_set_surface_reg, 113 .set_surface_reg = r100_set_surface_reg,
115 .clear_surface_reg = r100_clear_surface_reg, 114 .clear_surface_reg = r100_clear_surface_reg,
116 .bandwidth_update = &r100_bandwidth_update, 115 .bandwidth_update = &r100_bandwidth_update,
117 .hdp_flush = &r100_hdp_flush,
118 .hpd_init = &r100_hpd_init, 116 .hpd_init = &r100_hpd_init,
119 .hpd_fini = &r100_hpd_fini, 117 .hpd_fini = &r100_hpd_fini,
120 .hpd_sense = &r100_hpd_sense, 118 .hpd_sense = &r100_hpd_sense,
121 .hpd_set_polarity = &r100_hpd_set_polarity, 119 .hpd_set_polarity = &r100_hpd_set_polarity,
120 .ioctl_wait_idle = NULL,
122}; 121};
123 122
124 123
@@ -174,11 +173,11 @@ static struct radeon_asic r300_asic = {
174 .set_surface_reg = r100_set_surface_reg, 173 .set_surface_reg = r100_set_surface_reg,
175 .clear_surface_reg = r100_clear_surface_reg, 174 .clear_surface_reg = r100_clear_surface_reg,
176 .bandwidth_update = &r100_bandwidth_update, 175 .bandwidth_update = &r100_bandwidth_update,
177 .hdp_flush = &r100_hdp_flush,
178 .hpd_init = &r100_hpd_init, 176 .hpd_init = &r100_hpd_init,
179 .hpd_fini = &r100_hpd_fini, 177 .hpd_fini = &r100_hpd_fini,
180 .hpd_sense = &r100_hpd_sense, 178 .hpd_sense = &r100_hpd_sense,
181 .hpd_set_polarity = &r100_hpd_set_polarity, 179 .hpd_set_polarity = &r100_hpd_set_polarity,
180 .ioctl_wait_idle = NULL,
182}; 181};
183 182
184/* 183/*
@@ -218,11 +217,11 @@ static struct radeon_asic r420_asic = {
218 .set_surface_reg = r100_set_surface_reg, 217 .set_surface_reg = r100_set_surface_reg,
219 .clear_surface_reg = r100_clear_surface_reg, 218 .clear_surface_reg = r100_clear_surface_reg,
220 .bandwidth_update = &r100_bandwidth_update, 219 .bandwidth_update = &r100_bandwidth_update,
221 .hdp_flush = &r100_hdp_flush,
222 .hpd_init = &r100_hpd_init, 220 .hpd_init = &r100_hpd_init,
223 .hpd_fini = &r100_hpd_fini, 221 .hpd_fini = &r100_hpd_fini,
224 .hpd_sense = &r100_hpd_sense, 222 .hpd_sense = &r100_hpd_sense,
225 .hpd_set_polarity = &r100_hpd_set_polarity, 223 .hpd_set_polarity = &r100_hpd_set_polarity,
224 .ioctl_wait_idle = NULL,
226}; 225};
227 226
228 227
@@ -267,11 +266,11 @@ static struct radeon_asic rs400_asic = {
267 .set_surface_reg = r100_set_surface_reg, 266 .set_surface_reg = r100_set_surface_reg,
268 .clear_surface_reg = r100_clear_surface_reg, 267 .clear_surface_reg = r100_clear_surface_reg,
269 .bandwidth_update = &r100_bandwidth_update, 268 .bandwidth_update = &r100_bandwidth_update,
270 .hdp_flush = &r100_hdp_flush,
271 .hpd_init = &r100_hpd_init, 269 .hpd_init = &r100_hpd_init,
272 .hpd_fini = &r100_hpd_fini, 270 .hpd_fini = &r100_hpd_fini,
273 .hpd_sense = &r100_hpd_sense, 271 .hpd_sense = &r100_hpd_sense,
274 .hpd_set_polarity = &r100_hpd_set_polarity, 272 .hpd_set_polarity = &r100_hpd_set_polarity,
273 .ioctl_wait_idle = NULL,
275}; 274};
276 275
277 276
@@ -324,11 +323,11 @@ static struct radeon_asic rs600_asic = {
324 .set_pcie_lanes = NULL, 323 .set_pcie_lanes = NULL,
325 .set_clock_gating = &radeon_atom_set_clock_gating, 324 .set_clock_gating = &radeon_atom_set_clock_gating,
326 .bandwidth_update = &rs600_bandwidth_update, 325 .bandwidth_update = &rs600_bandwidth_update,
327 .hdp_flush = &r100_hdp_flush,
328 .hpd_init = &rs600_hpd_init, 326 .hpd_init = &rs600_hpd_init,
329 .hpd_fini = &rs600_hpd_fini, 327 .hpd_fini = &rs600_hpd_fini,
330 .hpd_sense = &rs600_hpd_sense, 328 .hpd_sense = &rs600_hpd_sense,
331 .hpd_set_polarity = &rs600_hpd_set_polarity, 329 .hpd_set_polarity = &rs600_hpd_set_polarity,
330 .ioctl_wait_idle = NULL,
332}; 331};
333 332
334 333
@@ -372,11 +371,11 @@ static struct radeon_asic rs690_asic = {
372 .set_surface_reg = r100_set_surface_reg, 371 .set_surface_reg = r100_set_surface_reg,
373 .clear_surface_reg = r100_clear_surface_reg, 372 .clear_surface_reg = r100_clear_surface_reg,
374 .bandwidth_update = &rs690_bandwidth_update, 373 .bandwidth_update = &rs690_bandwidth_update,
375 .hdp_flush = &r100_hdp_flush,
376 .hpd_init = &rs600_hpd_init, 374 .hpd_init = &rs600_hpd_init,
377 .hpd_fini = &rs600_hpd_fini, 375 .hpd_fini = &rs600_hpd_fini,
378 .hpd_sense = &rs600_hpd_sense, 376 .hpd_sense = &rs600_hpd_sense,
379 .hpd_set_polarity = &rs600_hpd_set_polarity, 377 .hpd_set_polarity = &rs600_hpd_set_polarity,
378 .ioctl_wait_idle = NULL,
380}; 379};
381 380
382 381
@@ -424,11 +423,11 @@ static struct radeon_asic rv515_asic = {
424 .set_surface_reg = r100_set_surface_reg, 423 .set_surface_reg = r100_set_surface_reg,
425 .clear_surface_reg = r100_clear_surface_reg, 424 .clear_surface_reg = r100_clear_surface_reg,
426 .bandwidth_update = &rv515_bandwidth_update, 425 .bandwidth_update = &rv515_bandwidth_update,
427 .hdp_flush = &r100_hdp_flush,
428 .hpd_init = &rs600_hpd_init, 426 .hpd_init = &rs600_hpd_init,
429 .hpd_fini = &rs600_hpd_fini, 427 .hpd_fini = &rs600_hpd_fini,
430 .hpd_sense = &rs600_hpd_sense, 428 .hpd_sense = &rs600_hpd_sense,
431 .hpd_set_polarity = &rs600_hpd_set_polarity, 429 .hpd_set_polarity = &rs600_hpd_set_polarity,
430 .ioctl_wait_idle = NULL,
432}; 431};
433 432
434 433
@@ -467,11 +466,11 @@ static struct radeon_asic r520_asic = {
467 .set_surface_reg = r100_set_surface_reg, 466 .set_surface_reg = r100_set_surface_reg,
468 .clear_surface_reg = r100_clear_surface_reg, 467 .clear_surface_reg = r100_clear_surface_reg,
469 .bandwidth_update = &rv515_bandwidth_update, 468 .bandwidth_update = &rv515_bandwidth_update,
470 .hdp_flush = &r100_hdp_flush,
471 .hpd_init = &rs600_hpd_init, 469 .hpd_init = &rs600_hpd_init,
472 .hpd_fini = &rs600_hpd_fini, 470 .hpd_fini = &rs600_hpd_fini,
473 .hpd_sense = &rs600_hpd_sense, 471 .hpd_sense = &rs600_hpd_sense,
474 .hpd_set_polarity = &rs600_hpd_set_polarity, 472 .hpd_set_polarity = &rs600_hpd_set_polarity,
473 .ioctl_wait_idle = NULL,
475}; 474};
476 475
477/* 476/*
@@ -508,12 +507,12 @@ int r600_ring_test(struct radeon_device *rdev);
508int r600_copy_blit(struct radeon_device *rdev, 507int r600_copy_blit(struct radeon_device *rdev,
509 uint64_t src_offset, uint64_t dst_offset, 508 uint64_t src_offset, uint64_t dst_offset,
510 unsigned num_pages, struct radeon_fence *fence); 509 unsigned num_pages, struct radeon_fence *fence);
511void r600_hdp_flush(struct radeon_device *rdev);
512void r600_hpd_init(struct radeon_device *rdev); 510void r600_hpd_init(struct radeon_device *rdev);
513void r600_hpd_fini(struct radeon_device *rdev); 511void r600_hpd_fini(struct radeon_device *rdev);
514bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 512bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
515void r600_hpd_set_polarity(struct radeon_device *rdev, 513void r600_hpd_set_polarity(struct radeon_device *rdev,
516 enum radeon_hpd_id hpd); 514 enum radeon_hpd_id hpd);
515extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
517 516
518static struct radeon_asic r600_asic = { 517static struct radeon_asic r600_asic = {
519 .init = &r600_init, 518 .init = &r600_init,
@@ -544,11 +543,11 @@ static struct radeon_asic r600_asic = {
544 .set_surface_reg = r600_set_surface_reg, 543 .set_surface_reg = r600_set_surface_reg,
545 .clear_surface_reg = r600_clear_surface_reg, 544 .clear_surface_reg = r600_clear_surface_reg,
546 .bandwidth_update = &rv515_bandwidth_update, 545 .bandwidth_update = &rv515_bandwidth_update,
547 .hdp_flush = &r600_hdp_flush,
548 .hpd_init = &r600_hpd_init, 546 .hpd_init = &r600_hpd_init,
549 .hpd_fini = &r600_hpd_fini, 547 .hpd_fini = &r600_hpd_fini,
550 .hpd_sense = &r600_hpd_sense, 548 .hpd_sense = &r600_hpd_sense,
551 .hpd_set_polarity = &r600_hpd_set_polarity, 549 .hpd_set_polarity = &r600_hpd_set_polarity,
550 .ioctl_wait_idle = r600_ioctl_wait_idle,
552}; 551};
553 552
554/* 553/*
@@ -589,11 +588,11 @@ static struct radeon_asic rv770_asic = {
589 .set_surface_reg = r600_set_surface_reg, 588 .set_surface_reg = r600_set_surface_reg,
590 .clear_surface_reg = r600_clear_surface_reg, 589 .clear_surface_reg = r600_clear_surface_reg,
591 .bandwidth_update = &rv515_bandwidth_update, 590 .bandwidth_update = &rv515_bandwidth_update,
592 .hdp_flush = &r600_hdp_flush,
593 .hpd_init = &r600_hpd_init, 591 .hpd_init = &r600_hpd_init,
594 .hpd_fini = &r600_hpd_fini, 592 .hpd_fini = &r600_hpd_fini,
595 .hpd_sense = &r600_hpd_sense, 593 .hpd_sense = &r600_hpd_sense,
596 .hpd_set_polarity = &r600_hpd_set_polarity, 594 .hpd_set_polarity = &r600_hpd_set_polarity,
595 .ioctl_wait_idle = r600_ioctl_wait_idle,
597}; 596};
598 597
599#endif 598#endif
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 41dd8ebff21..2dcda611587 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -287,6 +287,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
287 *connector_type = DRM_MODE_CONNECTOR_DVID; 287 *connector_type = DRM_MODE_CONNECTOR_DVID;
288 } 288 }
289 289
290 /* XFX Pine Group device rv730 reports no VGA DDC lines
291 * even though they are wired up to record 0x93
292 */
293 if ((dev->pdev->device == 0x9498) &&
294 (dev->pdev->subsystem_vendor == 0x1682) &&
295 (dev->pdev->subsystem_device == 0x2452)) {
296 struct radeon_device *rdev = dev->dev_private;
297 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
298 }
290 return true; 299 return true;
291} 300}
292 301
@@ -346,7 +355,9 @@ const int object_connector_convert[] = {
346 DRM_MODE_CONNECTOR_Unknown, 355 DRM_MODE_CONNECTOR_Unknown,
347 DRM_MODE_CONNECTOR_Unknown, 356 DRM_MODE_CONNECTOR_Unknown,
348 DRM_MODE_CONNECTOR_Unknown, 357 DRM_MODE_CONNECTOR_Unknown,
349 DRM_MODE_CONNECTOR_DisplayPort 358 DRM_MODE_CONNECTOR_DisplayPort,
359 DRM_MODE_CONNECTOR_eDP,
360 DRM_MODE_CONNECTOR_Unknown
350}; 361};
351 362
352bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev) 363bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
@@ -936,6 +947,43 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
936 return false; 947 return false;
937} 948}
938 949
950union igp_info {
951 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
952 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
953};
954
955bool radeon_atombios_sideport_present(struct radeon_device *rdev)
956{
957 struct radeon_mode_info *mode_info = &rdev->mode_info;
958 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
959 union igp_info *igp_info;
960 u8 frev, crev;
961 u16 data_offset;
962
963 atom_parse_data_header(mode_info->atom_context, index, NULL, &frev,
964 &crev, &data_offset);
965
966 igp_info = (union igp_info *)(mode_info->atom_context->bios +
967 data_offset);
968
969 if (igp_info) {
970 switch (crev) {
971 case 1:
972 if (igp_info->info.ucMemoryType & 0xf0)
973 return true;
974 break;
975 case 2:
976 if (igp_info->info_2.ucMemoryType & 0x0f)
977 return true;
978 break;
979 default:
980 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
981 break;
982 }
983 }
984 return false;
985}
986
939bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder, 987bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
940 struct radeon_encoder_int_tmds *tmds) 988 struct radeon_encoder_int_tmds *tmds)
941{ 989{
diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c
index 4ddfd4b5bc5..7932dc4d6b9 100644
--- a/drivers/gpu/drm/radeon/radeon_benchmark.c
+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c
@@ -65,31 +65,42 @@ void radeon_benchmark_move(struct radeon_device *rdev, unsigned bsize,
65 if (r) { 65 if (r) {
66 goto out_cleanup; 66 goto out_cleanup;
67 } 67 }
68 start_jiffies = jiffies; 68
69 for (i = 0; i < n; i++) { 69 /* r100 doesn't have dma engine so skip the test */
70 r = radeon_fence_create(rdev, &fence); 70 if (rdev->asic->copy_dma) {
71 if (r) { 71
72 goto out_cleanup; 72 start_jiffies = jiffies;
73 for (i = 0; i < n; i++) {
74 r = radeon_fence_create(rdev, &fence);
75 if (r) {
76 goto out_cleanup;
77 }
78
79 r = radeon_copy_dma(rdev, saddr, daddr,
80 size / RADEON_GPU_PAGE_SIZE, fence);
81
82 if (r) {
83 goto out_cleanup;
84 }
85 r = radeon_fence_wait(fence, false);
86 if (r) {
87 goto out_cleanup;
88 }
89 radeon_fence_unref(&fence);
73 } 90 }
74 r = radeon_copy_dma(rdev, saddr, daddr, size / RADEON_GPU_PAGE_SIZE, fence); 91 end_jiffies = jiffies;
75 if (r) { 92 time = end_jiffies - start_jiffies;
76 goto out_cleanup; 93 time = jiffies_to_msecs(time);
94 if (time > 0) {
95 i = ((n * size) >> 10) / time;
96 printk(KERN_INFO "radeon: dma %u bo moves of %ukb from"
97 " %d to %d in %lums (%ukb/ms %ukb/s %uM/s)\n",
98 n, size >> 10,
99 sdomain, ddomain, time,
100 i, i * 1000, (i * 1000) / 1024);
77 } 101 }
78 r = radeon_fence_wait(fence, false);
79 if (r) {
80 goto out_cleanup;
81 }
82 radeon_fence_unref(&fence);
83 }
84 end_jiffies = jiffies;
85 time = end_jiffies - start_jiffies;
86 time = jiffies_to_msecs(time);
87 if (time > 0) {
88 i = ((n * size) >> 10) / time;
89 printk(KERN_INFO "radeon: dma %u bo moves of %ukb from %d to %d"
90 " in %lums (%ukb/ms %ukb/s %uM/s)\n", n, size >> 10,
91 sdomain, ddomain, time, i, i * 1000, (i * 1000) / 1024);
92 } 102 }
103
93 start_jiffies = jiffies; 104 start_jiffies = jiffies;
94 for (i = 0; i < n; i++) { 105 for (i = 0; i < n; i++) {
95 r = radeon_fence_create(rdev, &fence); 106 r = radeon_fence_create(rdev, &fence);
diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c
index 812f24dbc2a..73c4405bf42 100644
--- a/drivers/gpu/drm/radeon/radeon_clocks.c
+++ b/drivers/gpu/drm/radeon/radeon_clocks.c
@@ -56,7 +56,7 @@ uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev)
56 else if (post_div == 3) 56 else if (post_div == 3)
57 sclk >>= 2; 57 sclk >>= 2;
58 else if (post_div == 4) 58 else if (post_div == 4)
59 sclk >>= 4; 59 sclk >>= 3;
60 60
61 return sclk; 61 return sclk;
62} 62}
@@ -86,7 +86,7 @@ uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev)
86 else if (post_div == 3) 86 else if (post_div == 3)
87 mclk >>= 2; 87 mclk >>= 2;
88 else if (post_div == 4) 88 else if (post_div == 4)
89 mclk >>= 4; 89 mclk >>= 3;
90 90
91 return mclk; 91 return mclk;
92} 92}
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 58f342659cc..e7b19440102 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -595,6 +595,20 @@ bool radeon_combios_get_clock_info(struct drm_device *dev)
595 return false; 595 return false;
596} 596}
597 597
598bool radeon_combios_sideport_present(struct radeon_device *rdev)
599{
600 struct drm_device *dev = rdev->ddev;
601 u16 igp_info;
602
603 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);
604
605 if (igp_info) {
606 if (RBIOS16(igp_info + 0x4))
607 return true;
608 }
609 return false;
610}
611
598static const uint32_t default_primarydac_adj[CHIP_LAST] = { 612static const uint32_t default_primarydac_adj[CHIP_LAST] = {
599 0x00000808, /* r100 */ 613 0x00000808, /* r100 */
600 0x00000808, /* rv100 */ 614 0x00000808, /* rv100 */
@@ -673,6 +687,9 @@ radeon_combios_get_tv_info(struct radeon_device *rdev)
673 uint16_t tv_info; 687 uint16_t tv_info;
674 enum radeon_tv_std tv_std = TV_STD_NTSC; 688 enum radeon_tv_std tv_std = TV_STD_NTSC;
675 689
690 if (rdev->bios == NULL)
691 return tv_std;
692
676 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 693 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);
677 if (tv_info) { 694 if (tv_info) {
678 if (RBIOS8(tv_info + 6) == 'T') { 695 if (RBIOS8(tv_info + 6) == 'T') {
@@ -954,8 +971,7 @@ struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder
954 lvds->native_mode.vdisplay); 971 lvds->native_mode.vdisplay);
955 972
956 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 973 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);
957 if (lvds->panel_vcc_delay > 2000 || lvds->panel_vcc_delay < 0) 974 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);
958 lvds->panel_vcc_delay = 2000;
959 975
960 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 976 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);
961 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 977 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index b82ae61d4d1..23818854001 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -49,8 +49,10 @@ void radeon_connector_hotplug(struct drm_connector *connector)
49 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 49 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
50 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); 50 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
51 51
52 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 52 if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
53 if (radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 53 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
54 if ((radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
55 (radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_eDP)) {
54 if (radeon_dp_needs_link_train(radeon_connector)) { 56 if (radeon_dp_needs_link_train(radeon_connector)) {
55 if (connector->encoder) 57 if (connector->encoder)
56 dp_link_train(connector->encoder, connector); 58 dp_link_train(connector->encoder, connector);
@@ -578,16 +580,18 @@ static enum drm_connector_status radeon_vga_detect(struct drm_connector *connect
578 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 580 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
579 struct drm_encoder *encoder; 581 struct drm_encoder *encoder;
580 struct drm_encoder_helper_funcs *encoder_funcs; 582 struct drm_encoder_helper_funcs *encoder_funcs;
581 bool dret; 583 bool dret = false;
582 enum drm_connector_status ret = connector_status_disconnected; 584 enum drm_connector_status ret = connector_status_disconnected;
583 585
584 encoder = radeon_best_single_encoder(connector); 586 encoder = radeon_best_single_encoder(connector);
585 if (!encoder) 587 if (!encoder)
586 ret = connector_status_disconnected; 588 ret = connector_status_disconnected;
587 589
588 radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); 590 if (radeon_connector->ddc_bus) {
589 dret = radeon_ddc_probe(radeon_connector); 591 radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
590 radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); 592 dret = radeon_ddc_probe(radeon_connector);
593 radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
594 }
591 if (dret) { 595 if (dret) {
592 if (radeon_connector->edid) { 596 if (radeon_connector->edid) {
593 kfree(radeon_connector->edid); 597 kfree(radeon_connector->edid);
@@ -738,11 +742,13 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
738 struct drm_mode_object *obj; 742 struct drm_mode_object *obj;
739 int i; 743 int i;
740 enum drm_connector_status ret = connector_status_disconnected; 744 enum drm_connector_status ret = connector_status_disconnected;
741 bool dret; 745 bool dret = false;
742 746
743 radeon_i2c_do_lock(radeon_connector->ddc_bus, 1); 747 if (radeon_connector->ddc_bus) {
744 dret = radeon_ddc_probe(radeon_connector); 748 radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
745 radeon_i2c_do_lock(radeon_connector->ddc_bus, 0); 749 dret = radeon_ddc_probe(radeon_connector);
750 radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
751 }
746 if (dret) { 752 if (dret) {
747 if (radeon_connector->edid) { 753 if (radeon_connector->edid) {
748 kfree(radeon_connector->edid); 754 kfree(radeon_connector->edid);
@@ -898,10 +904,18 @@ static void radeon_dvi_force(struct drm_connector *connector)
898static int radeon_dvi_mode_valid(struct drm_connector *connector, 904static int radeon_dvi_mode_valid(struct drm_connector *connector,
899 struct drm_display_mode *mode) 905 struct drm_display_mode *mode)
900{ 906{
907 struct drm_device *dev = connector->dev;
908 struct radeon_device *rdev = dev->dev_private;
901 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 909 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
902 910
903 /* XXX check mode bandwidth */ 911 /* XXX check mode bandwidth */
904 912
913 /* clocks over 135 MHz have heat issues with DVI on RV100 */
914 if (radeon_connector->use_digital &&
915 (rdev->family == CHIP_RV100) &&
916 (mode->clock > 135000))
917 return MODE_CLOCK_HIGH;
918
905 if (radeon_connector->use_digital && (mode->clock > 165000)) { 919 if (radeon_connector->use_digital && (mode->clock > 165000)) {
906 if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) || 920 if ((radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I) ||
907 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || 921 (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) ||
@@ -967,7 +981,8 @@ static enum drm_connector_status radeon_dp_detect(struct drm_connector *connecto
967 } 981 }
968 982
969 sink_type = radeon_dp_getsinktype(radeon_connector); 983 sink_type = radeon_dp_getsinktype(radeon_connector);
970 if (sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) { 984 if ((sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
985 (sink_type == CONNECTOR_OBJECT_ID_eDP)) {
971 if (radeon_dp_getdpcd(radeon_connector)) { 986 if (radeon_dp_getdpcd(radeon_connector)) {
972 radeon_dig_connector->dp_sink_type = sink_type; 987 radeon_dig_connector->dp_sink_type = sink_type;
973 ret = connector_status_connected; 988 ret = connector_status_connected;
@@ -992,7 +1007,8 @@ static int radeon_dp_mode_valid(struct drm_connector *connector,
992 1007
993 /* XXX check mode bandwidth */ 1008 /* XXX check mode bandwidth */
994 1009
995 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 1010 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
1011 (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
996 return radeon_dp_mode_valid_helper(radeon_connector, mode); 1012 return radeon_dp_mode_valid_helper(radeon_connector, mode);
997 else 1013 else
998 return MODE_OK; 1014 return MODE_OK;
@@ -1145,6 +1161,7 @@ radeon_add_atom_connector(struct drm_device *dev,
1145 subpixel_order = SubPixelHorizontalRGB; 1161 subpixel_order = SubPixelHorizontalRGB;
1146 break; 1162 break;
1147 case DRM_MODE_CONNECTOR_DisplayPort: 1163 case DRM_MODE_CONNECTOR_DisplayPort:
1164 case DRM_MODE_CONNECTOR_eDP:
1148 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL); 1165 radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
1149 if (!radeon_dig_connector) 1166 if (!radeon_dig_connector)
1150 goto failed; 1167 goto failed;
@@ -1157,10 +1174,16 @@ radeon_add_atom_connector(struct drm_device *dev,
1157 goto failed; 1174 goto failed;
1158 if (i2c_bus->valid) { 1175 if (i2c_bus->valid) {
1159 /* add DP i2c bus */ 1176 /* add DP i2c bus */
1160 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch"); 1177 if (connector_type == DRM_MODE_CONNECTOR_eDP)
1178 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch");
1179 else
1180 radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
1161 if (!radeon_dig_connector->dp_i2c_bus) 1181 if (!radeon_dig_connector->dp_i2c_bus)
1162 goto failed; 1182 goto failed;
1163 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP"); 1183 if (connector_type == DRM_MODE_CONNECTOR_eDP)
1184 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "eDP");
1185 else
1186 radeon_connector->ddc_bus = radeon_i2c_create(dev, i2c_bus, "DP");
1164 if (!radeon_connector->ddc_bus) 1187 if (!radeon_connector->ddc_bus)
1165 goto failed; 1188 goto failed;
1166 } 1189 }
@@ -1324,7 +1347,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
1324 radeon_connector->dac_load_detect = false; 1347 radeon_connector->dac_load_detect = false;
1325 drm_connector_attach_property(&radeon_connector->base, 1348 drm_connector_attach_property(&radeon_connector->base,
1326 rdev->mode_info.load_detect_property, 1349 rdev->mode_info.load_detect_property,
1327 1); 1350 radeon_connector->dac_load_detect);
1328 drm_connector_attach_property(&radeon_connector->base, 1351 drm_connector_attach_property(&radeon_connector->base,
1329 rdev->mode_info.tv_std_property, 1352 rdev->mode_info.tv_std_property,
1330 radeon_combios_get_tv_info(rdev)); 1353 radeon_combios_get_tv_info(rdev));
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 65590a0f1d9..1190148cf5e 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -189,7 +189,7 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
189{ 189{
190 unsigned i; 190 unsigned i;
191 191
192 if (error) { 192 if (error && parser->ib) {
193 radeon_bo_list_unvalidate(&parser->validated, 193 radeon_bo_list_unvalidate(&parser->validated,
194 parser->ib->fence); 194 parser->ib->fence);
195 } else { 195 } else {
@@ -231,6 +231,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
231 memset(&parser, 0, sizeof(struct radeon_cs_parser)); 231 memset(&parser, 0, sizeof(struct radeon_cs_parser));
232 parser.filp = filp; 232 parser.filp = filp;
233 parser.rdev = rdev; 233 parser.rdev = rdev;
234 parser.dev = rdev->dev;
234 r = radeon_cs_parser_init(&parser, data); 235 r = radeon_cs_parser_init(&parser, data);
235 if (r) { 236 if (r) {
236 DRM_ERROR("Failed to initialize parser !\n"); 237 DRM_ERROR("Failed to initialize parser !\n");
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 0c51f8e4661..768b1509fa0 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -544,6 +544,7 @@ void radeon_agp_disable(struct radeon_device *rdev)
544 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; 544 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
545 rdev->asic->gart_set_page = &r100_pci_gart_set_page; 545 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
546 } 546 }
547 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
547} 548}
548 549
549void radeon_check_arguments(struct radeon_device *rdev) 550void radeon_check_arguments(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index 1fb2f029d7e..7e17a362b54 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -234,7 +234,7 @@ static const char *encoder_names[34] = {
234 "INTERNAL_UNIPHY2", 234 "INTERNAL_UNIPHY2",
235}; 235};
236 236
237static const char *connector_names[13] = { 237static const char *connector_names[15] = {
238 "Unknown", 238 "Unknown",
239 "VGA", 239 "VGA",
240 "DVI-I", 240 "DVI-I",
@@ -248,6 +248,8 @@ static const char *connector_names[13] = {
248 "DisplayPort", 248 "DisplayPort",
249 "HDMI-A", 249 "HDMI-A",
250 "HDMI-B", 250 "HDMI-B",
251 "TV",
252 "eDP",
251}; 253};
252 254
253static const char *hpd_names[7] = { 255static const char *hpd_names[7] = {
@@ -276,7 +278,7 @@ static void radeon_print_display_setup(struct drm_device *dev)
276 DRM_INFO(" %s\n", connector_names[connector->connector_type]); 278 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
277 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE) 279 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
278 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]); 280 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
279 if (radeon_connector->ddc_bus) 281 if (radeon_connector->ddc_bus) {
280 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 282 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
281 radeon_connector->ddc_bus->rec.mask_clk_reg, 283 radeon_connector->ddc_bus->rec.mask_clk_reg,
282 radeon_connector->ddc_bus->rec.mask_data_reg, 284 radeon_connector->ddc_bus->rec.mask_data_reg,
@@ -286,6 +288,15 @@ static void radeon_print_display_setup(struct drm_device *dev)
286 radeon_connector->ddc_bus->rec.en_data_reg, 288 radeon_connector->ddc_bus->rec.en_data_reg,
287 radeon_connector->ddc_bus->rec.y_clk_reg, 289 radeon_connector->ddc_bus->rec.y_clk_reg,
288 radeon_connector->ddc_bus->rec.y_data_reg); 290 radeon_connector->ddc_bus->rec.y_data_reg);
291 } else {
292 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
293 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
294 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
295 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
296 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
297 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
298 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
299 }
289 DRM_INFO(" Encoders:\n"); 300 DRM_INFO(" Encoders:\n");
290 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 301 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
291 radeon_encoder = to_radeon_encoder(encoder); 302 radeon_encoder = to_radeon_encoder(encoder);
@@ -352,9 +363,11 @@ int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
352{ 363{
353 int ret = 0; 364 int ret = 0;
354 365
355 if (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) { 366 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
367 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
356 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; 368 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
357 if (dig->dp_i2c_bus) 369 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
370 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
358 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter); 371 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
359 } 372 }
360 if (!radeon_connector->ddc_bus) 373 if (!radeon_connector->ddc_bus)
@@ -407,11 +420,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
407 uint32_t *fb_div_p, 420 uint32_t *fb_div_p,
408 uint32_t *frac_fb_div_p, 421 uint32_t *frac_fb_div_p,
409 uint32_t *ref_div_p, 422 uint32_t *ref_div_p,
410 uint32_t *post_div_p, 423 uint32_t *post_div_p)
411 int flags)
412{ 424{
413 uint32_t min_ref_div = pll->min_ref_div; 425 uint32_t min_ref_div = pll->min_ref_div;
414 uint32_t max_ref_div = pll->max_ref_div; 426 uint32_t max_ref_div = pll->max_ref_div;
427 uint32_t min_post_div = pll->min_post_div;
428 uint32_t max_post_div = pll->max_post_div;
415 uint32_t min_fractional_feed_div = 0; 429 uint32_t min_fractional_feed_div = 0;
416 uint32_t max_fractional_feed_div = 0; 430 uint32_t max_fractional_feed_div = 0;
417 uint32_t best_vco = pll->best_vco; 431 uint32_t best_vco = pll->best_vco;
@@ -427,7 +441,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
427 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div); 441 DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
428 freq = freq * 1000; 442 freq = freq * 1000;
429 443
430 if (flags & RADEON_PLL_USE_REF_DIV) 444 if (pll->flags & RADEON_PLL_USE_REF_DIV)
431 min_ref_div = max_ref_div = pll->reference_div; 445 min_ref_div = max_ref_div = pll->reference_div;
432 else { 446 else {
433 while (min_ref_div < max_ref_div-1) { 447 while (min_ref_div < max_ref_div-1) {
@@ -442,19 +456,22 @@ void radeon_compute_pll(struct radeon_pll *pll,
442 } 456 }
443 } 457 }
444 458
445 if (flags & RADEON_PLL_USE_FRAC_FB_DIV) { 459 if (pll->flags & RADEON_PLL_USE_POST_DIV)
460 min_post_div = max_post_div = pll->post_div;
461
462 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
446 min_fractional_feed_div = pll->min_frac_feedback_div; 463 min_fractional_feed_div = pll->min_frac_feedback_div;
447 max_fractional_feed_div = pll->max_frac_feedback_div; 464 max_fractional_feed_div = pll->max_frac_feedback_div;
448 } 465 }
449 466
450 for (post_div = pll->min_post_div; post_div <= pll->max_post_div; ++post_div) { 467 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
451 uint32_t ref_div; 468 uint32_t ref_div;
452 469
453 if ((flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1)) 470 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
454 continue; 471 continue;
455 472
456 /* legacy radeons only have a few post_divs */ 473 /* legacy radeons only have a few post_divs */
457 if (flags & RADEON_PLL_LEGACY) { 474 if (pll->flags & RADEON_PLL_LEGACY) {
458 if ((post_div == 5) || 475 if ((post_div == 5) ||
459 (post_div == 7) || 476 (post_div == 7) ||
460 (post_div == 9) || 477 (post_div == 9) ||
@@ -501,7 +518,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
501 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div; 518 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
502 current_freq = radeon_div(tmp, ref_div * post_div); 519 current_freq = radeon_div(tmp, ref_div * post_div);
503 520
504 if (flags & RADEON_PLL_PREFER_CLOSEST_LOWER) { 521 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
505 error = freq - current_freq; 522 error = freq - current_freq;
506 error = error < 0 ? 0xffffffff : error; 523 error = error < 0 ? 0xffffffff : error;
507 } else 524 } else
@@ -528,12 +545,12 @@ void radeon_compute_pll(struct radeon_pll *pll,
528 best_freq = current_freq; 545 best_freq = current_freq;
529 best_error = error; 546 best_error = error;
530 best_vco_diff = vco_diff; 547 best_vco_diff = vco_diff;
531 } else if (((flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || 548 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
532 ((flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || 549 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
533 ((flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) || 550 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
534 ((flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) || 551 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
535 ((flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) || 552 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
536 ((flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) { 553 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
537 best_post_div = post_div; 554 best_post_div = post_div;
538 best_ref_div = ref_div; 555 best_ref_div = ref_div;
539 best_feedback_div = feedback_div; 556 best_feedback_div = feedback_div;
@@ -569,8 +586,7 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
569 uint32_t *fb_div_p, 586 uint32_t *fb_div_p,
570 uint32_t *frac_fb_div_p, 587 uint32_t *frac_fb_div_p,
571 uint32_t *ref_div_p, 588 uint32_t *ref_div_p,
572 uint32_t *post_div_p, 589 uint32_t *post_div_p)
573 int flags)
574{ 590{
575 fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq; 591 fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
576 fixed20_12 pll_out_max, pll_out_min; 592 fixed20_12 pll_out_max, pll_out_min;
@@ -664,7 +680,6 @@ static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
664 radeonfb_remove(dev, fb); 680 radeonfb_remove(dev, fb);
665 681
666 if (radeon_fb->obj) { 682 if (radeon_fb->obj) {
667 radeon_gem_object_unpin(radeon_fb->obj);
668 mutex_lock(&dev->struct_mutex); 683 mutex_lock(&dev->struct_mutex);
669 drm_gem_object_unreference(radeon_fb->obj); 684 drm_gem_object_unreference(radeon_fb->obj);
670 mutex_unlock(&dev->struct_mutex); 685 mutex_unlock(&dev->struct_mutex);
@@ -712,7 +727,11 @@ radeon_user_framebuffer_create(struct drm_device *dev,
712 struct drm_gem_object *obj; 727 struct drm_gem_object *obj;
713 728
714 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle); 729 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
715 730 if (obj == NULL) {
731 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
732 "can't create framebuffer\n", mode_cmd->handle);
733 return NULL;
734 }
716 return radeon_framebuffer_create(dev, mode_cmd, obj); 735 return radeon_framebuffer_create(dev, mode_cmd, obj);
717} 736}
718 737
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index ccba95f83d1..3c91724457c 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -156,6 +156,26 @@ radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t
156 return ret; 156 return ret;
157} 157}
158 158
159static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160{
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178}
159void 179void
160radeon_link_encoder_connector(struct drm_device *dev) 180radeon_link_encoder_connector(struct drm_device *dev)
161{ 181{
@@ -202,7 +222,7 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder)
202 222
203 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
204 radeon_connector = to_radeon_connector(connector); 224 radeon_connector = to_radeon_connector(connector);
205 if (radeon_encoder->devices & radeon_connector->devices) 225 if (radeon_encoder->active_device & radeon_connector->devices)
206 return connector; 226 return connector;
207 } 227 }
208 return NULL; 228 return NULL;
@@ -596,21 +616,23 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
596 return ATOM_ENCODER_MODE_LVDS; 616 return ATOM_ENCODER_MODE_LVDS;
597 break; 617 break;
598 case DRM_MODE_CONNECTOR_DisplayPort: 618 case DRM_MODE_CONNECTOR_DisplayPort:
619 case DRM_MODE_CONNECTOR_eDP:
599 radeon_dig_connector = radeon_connector->con_priv; 620 radeon_dig_connector = radeon_connector->con_priv;
600 if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) 621 if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
622 (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
601 return ATOM_ENCODER_MODE_DP; 623 return ATOM_ENCODER_MODE_DP;
602 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) 624 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
603 return ATOM_ENCODER_MODE_HDMI; 625 return ATOM_ENCODER_MODE_HDMI;
604 else 626 else
605 return ATOM_ENCODER_MODE_DVI; 627 return ATOM_ENCODER_MODE_DVI;
606 break; 628 break;
607 case CONNECTOR_DVI_A: 629 case DRM_MODE_CONNECTOR_DVIA:
608 case CONNECTOR_VGA: 630 case DRM_MODE_CONNECTOR_VGA:
609 return ATOM_ENCODER_MODE_CRT; 631 return ATOM_ENCODER_MODE_CRT;
610 break; 632 break;
611 case CONNECTOR_STV: 633 case DRM_MODE_CONNECTOR_Composite:
612 case CONNECTOR_CTV: 634 case DRM_MODE_CONNECTOR_SVIDEO:
613 case CONNECTOR_DIN: 635 case DRM_MODE_CONNECTOR_9PinDIN:
614 /* fix me */ 636 /* fix me */
615 return ATOM_ENCODER_MODE_TV; 637 return ATOM_ENCODER_MODE_TV;
616 /*return ATOM_ENCODER_MODE_CV;*/ 638 /*return ATOM_ENCODER_MODE_CV;*/
@@ -674,31 +696,11 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
674 696
675 memset(&args, 0, sizeof(args)); 697 memset(&args, 0, sizeof(args));
676 698
677 if (ASIC_IS_DCE32(rdev)) { 699 if (dig->dig_encoder)
678 if (dig->dig_block) 700 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
679 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl); 701 else
680 else 702 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
681 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl); 703 num = dig->dig_encoder + 1;
682 num = dig->dig_block + 1;
683 } else {
684 switch (radeon_encoder->encoder_id) {
685 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
686 /* XXX doesn't really matter which dig encoder we pick as long as it's
687 * not already in use
688 */
689 if (dig_connector->linkb)
690 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
691 else
692 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
693 num = 1;
694 break;
695 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
696 /* Only dig2 encoder can drive LVTMA */
697 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
698 num = 2;
699 break;
700 }
701 }
702 704
703 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev); 705 atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev);
704 706
@@ -820,7 +822,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
820 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 822 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
821 } 823 }
822 if (ASIC_IS_DCE32(rdev)) { 824 if (ASIC_IS_DCE32(rdev)) {
823 if (dig->dig_block) 825 if (dig->dig_encoder == 1)
824 args.v2.acConfig.ucEncoderSel = 1; 826 args.v2.acConfig.ucEncoderSel = 1;
825 if (dig_connector->linkb) 827 if (dig_connector->linkb)
826 args.v2.acConfig.ucLinkSel = 1; 828 args.v2.acConfig.ucLinkSel = 1;
@@ -847,17 +849,16 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
847 args.v2.acConfig.fCoherentMode = 1; 849 args.v2.acConfig.fCoherentMode = 1;
848 } 850 }
849 } else { 851 } else {
852
850 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 853 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
851 854
855 if (dig->dig_encoder)
856 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
857 else
858 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
859
852 switch (radeon_encoder->encoder_id) { 860 switch (radeon_encoder->encoder_id) {
853 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 861 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
854 /* XXX doesn't really matter which dig encoder we pick as long as it's
855 * not already in use
856 */
857 if (dig_connector->linkb)
858 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
859 else
860 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
861 if (rdev->flags & RADEON_IS_IGP) { 862 if (rdev->flags & RADEON_IS_IGP) {
862 if (radeon_encoder->pixel_clock > 165000) { 863 if (radeon_encoder->pixel_clock > 165000) {
863 if (dig_connector->igp_lane_info & 0x3) 864 if (dig_connector->igp_lane_info & 0x3)
@@ -876,10 +877,6 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
876 } 877 }
877 } 878 }
878 break; 879 break;
879 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
880 /* Only dig2 encoder can drive LVTMA */
881 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
882 break;
883 } 880 }
884 881
885 if (radeon_encoder->pixel_clock > 165000) 882 if (radeon_encoder->pixel_clock > 165000)
@@ -1044,6 +1041,7 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1044 union crtc_sourc_param args; 1041 union crtc_sourc_param args;
1045 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source); 1042 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1046 uint8_t frev, crev; 1043 uint8_t frev, crev;
1044 struct radeon_encoder_atom_dig *dig;
1047 1045
1048 memset(&args, 0, sizeof(args)); 1046 memset(&args, 0, sizeof(args));
1049 1047
@@ -1107,40 +1105,16 @@ atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1107 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1105 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1108 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1106 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1109 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1107 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1110 if (ASIC_IS_DCE32(rdev)) { 1108 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1111 if (radeon_crtc->crtc_id) 1109 dig = radeon_encoder->enc_priv;
1112 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID; 1110 if (dig->dig_encoder)
1113 else 1111 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1114 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID; 1112 else
1115 } else { 1113 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1116 struct drm_connector *connector;
1117 struct radeon_connector *radeon_connector;
1118 struct radeon_connector_atom_dig *dig_connector;
1119
1120 connector = radeon_get_connector_for_encoder(encoder);
1121 if (!connector)
1122 return;
1123 radeon_connector = to_radeon_connector(connector);
1124 if (!radeon_connector->con_priv)
1125 return;
1126 dig_connector = radeon_connector->con_priv;
1127
1128 /* XXX doesn't really matter which dig encoder we pick as long as it's
1129 * not already in use
1130 */
1131 if (dig_connector->linkb)
1132 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1133 else
1134 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1135 }
1136 break; 1114 break;
1137 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 1115 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1138 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID; 1116 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1139 break; 1117 break;
1140 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1141 /* Only dig2 encoder can drive LVTMA */
1142 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1143 break;
1144 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 1118 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1145 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1119 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1146 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID; 1120 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
@@ -1200,6 +1174,47 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1200 } 1174 }
1201} 1175}
1202 1176
1177static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1178{
1179 struct drm_device *dev = encoder->dev;
1180 struct radeon_device *rdev = dev->dev_private;
1181 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1182 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1183 struct drm_encoder *test_encoder;
1184 struct radeon_encoder_atom_dig *dig;
1185 uint32_t dig_enc_in_use = 0;
1186 /* on DCE32 and encoder can driver any block so just crtc id */
1187 if (ASIC_IS_DCE32(rdev)) {
1188 return radeon_crtc->crtc_id;
1189 }
1190
1191 /* on DCE3 - LVTMA can only be driven by DIGB */
1192 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1193 struct radeon_encoder *radeon_test_encoder;
1194
1195 if (encoder == test_encoder)
1196 continue;
1197
1198 if (!radeon_encoder_is_digital(test_encoder))
1199 continue;
1200
1201 radeon_test_encoder = to_radeon_encoder(test_encoder);
1202 dig = radeon_test_encoder->enc_priv;
1203
1204 if (dig->dig_encoder >= 0)
1205 dig_enc_in_use |= (1 << dig->dig_encoder);
1206 }
1207
1208 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1209 if (dig_enc_in_use & 0x2)
1210 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1211 return 1;
1212 }
1213 if (!(dig_enc_in_use & 1))
1214 return 0;
1215 return 1;
1216}
1217
1203static void 1218static void
1204radeon_atom_encoder_mode_set(struct drm_encoder *encoder, 1219radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1205 struct drm_display_mode *mode, 1220 struct drm_display_mode *mode,
@@ -1212,12 +1227,9 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1212 1227
1213 if (radeon_encoder->active_device & 1228 if (radeon_encoder->active_device &
1214 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) { 1229 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1215 if (radeon_encoder->enc_priv) { 1230 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1216 struct radeon_encoder_atom_dig *dig; 1231 if (dig)
1217 1232 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1218 dig = radeon_encoder->enc_priv;
1219 dig->dig_block = radeon_crtc->crtc_id;
1220 }
1221 } 1233 }
1222 radeon_encoder->pixel_clock = adjusted_mode->clock; 1234 radeon_encoder->pixel_clock = adjusted_mode->clock;
1223 1235
@@ -1377,7 +1389,13 @@ static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1377static void radeon_atom_encoder_disable(struct drm_encoder *encoder) 1389static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1378{ 1390{
1379 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1391 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1392 struct radeon_encoder_atom_dig *dig;
1380 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 1393 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1394
1395 if (radeon_encoder_is_digital(encoder)) {
1396 dig = radeon_encoder->enc_priv;
1397 dig->dig_encoder = -1;
1398 }
1381 radeon_encoder->active_device = 0; 1399 radeon_encoder->active_device = 0;
1382} 1400}
1383 1401
@@ -1434,6 +1452,7 @@ radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1434 1452
1435 /* coherent mode by default */ 1453 /* coherent mode by default */
1436 dig->coherent_mode = true; 1454 dig->coherent_mode = true;
1455 dig->dig_encoder = -1;
1437 1456
1438 return dig; 1457 return dig;
1439} 1458}
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 3ba213d1b06..d71e346e9ab 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -248,7 +248,7 @@ int radeonfb_create(struct drm_device *dev,
248 if (ret) 248 if (ret)
249 goto out_unref; 249 goto out_unref;
250 250
251 memset_io(fbptr, 0xff, aligned_size); 251 memset_io(fbptr, 0x0, aligned_size);
252 252
253 strcpy(info->fix.id, "radeondrmfb"); 253 strcpy(info->fix.id, "radeondrmfb");
254 254
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 60df2d7e7e4..db8e9a355a0 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -131,7 +131,6 @@ int radeon_gem_set_domain(struct drm_gem_object *gobj,
131 printk(KERN_ERR "Failed to wait for object !\n"); 131 printk(KERN_ERR "Failed to wait for object !\n");
132 return r; 132 return r;
133 } 133 }
134 radeon_hdp_flush(robj->rdev);
135 } 134 }
136 return 0; 135 return 0;
137} 136}
@@ -309,10 +308,12 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
309 } 308 }
310 robj = gobj->driver_private; 309 robj = gobj->driver_private;
311 r = radeon_bo_wait(robj, NULL, false); 310 r = radeon_bo_wait(robj, NULL, false);
311 /* callback hw specific functions if any */
312 if (robj->rdev->asic->ioctl_wait_idle)
313 robj->rdev->asic->ioctl_wait_idle(robj->rdev, robj);
312 mutex_lock(&dev->struct_mutex); 314 mutex_lock(&dev->struct_mutex);
313 drm_gem_object_unreference(gobj); 315 drm_gem_object_unreference(gobj);
314 mutex_unlock(&dev->struct_mutex); 316 mutex_unlock(&dev->struct_mutex);
315 radeon_hdp_flush(robj->rdev);
316 return r; 317 return r;
317} 318}
318 319
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 9223296fe37..3cfd60fd008 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -97,6 +97,7 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
97 rdev->irq.sw_int = false; 97 rdev->irq.sw_int = false;
98 for (i = 0; i < 2; i++) { 98 for (i = 0; i < 2; i++) {
99 rdev->irq.crtc_vblank_int[i] = false; 99 rdev->irq.crtc_vblank_int[i] = false;
100 rdev->irq.hpd[i] = false;
100 } 101 }
101 radeon_irq_set(rdev); 102 radeon_irq_set(rdev);
102} 103}
@@ -128,17 +129,22 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
128 DRM_INFO("radeon: using MSI.\n"); 129 DRM_INFO("radeon: using MSI.\n");
129 } 130 }
130 } 131 }
131 drm_irq_install(rdev->ddev);
132 rdev->irq.installed = true; 132 rdev->irq.installed = true;
133 r = drm_irq_install(rdev->ddev);
134 if (r) {
135 rdev->irq.installed = false;
136 return r;
137 }
133 DRM_INFO("radeon: irq initialized.\n"); 138 DRM_INFO("radeon: irq initialized.\n");
134 return 0; 139 return 0;
135} 140}
136 141
137void radeon_irq_kms_fini(struct radeon_device *rdev) 142void radeon_irq_kms_fini(struct radeon_device *rdev)
138{ 143{
144 drm_vblank_cleanup(rdev->ddev);
139 if (rdev->irq.installed) { 145 if (rdev->irq.installed) {
140 rdev->irq.installed = false;
141 drm_irq_uninstall(rdev->ddev); 146 drm_irq_uninstall(rdev->ddev);
147 rdev->irq.installed = false;
142 if (rdev->msi_enabled) 148 if (rdev->msi_enabled)
143 pci_disable_msi(rdev->pdev); 149 pci_disable_msi(rdev->pdev);
144 } 150 }
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index cc27485a07a..b6d8081e124 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -339,69 +339,6 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
339 } 339 }
340} 340}
341 341
342/* properly set crtc bpp when using atombios */
343void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
344{
345 struct drm_device *dev = crtc->dev;
346 struct radeon_device *rdev = dev->dev_private;
347 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
348 int format;
349 uint32_t crtc_gen_cntl;
350 uint32_t disp_merge_cntl;
351 uint32_t crtc_pitch;
352
353 switch (crtc->fb->bits_per_pixel) {
354 case 8:
355 format = 2;
356 break;
357 case 15: /* 555 */
358 format = 3;
359 break;
360 case 16: /* 565 */
361 format = 4;
362 break;
363 case 24: /* RGB */
364 format = 5;
365 break;
366 case 32: /* xRGB */
367 format = 6;
368 break;
369 default:
370 return;
371 }
372
373 crtc_pitch = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
374 ((crtc->fb->bits_per_pixel * 8) - 1)) /
375 (crtc->fb->bits_per_pixel * 8));
376 crtc_pitch |= crtc_pitch << 16;
377
378 WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
379
380 switch (radeon_crtc->crtc_id) {
381 case 0:
382 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
383 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
384 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
385
386 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
387 crtc_gen_cntl |= (format << 8);
388 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
389 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
390 break;
391 case 1:
392 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
393 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
394 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
395
396 crtc_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
397 crtc_gen_cntl |= (format << 8);
398 WREG32(RADEON_CRTC2_GEN_CNTL, crtc_gen_cntl);
399 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
400 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
401 break;
402 }
403}
404
405int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 342int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
406 struct drm_framebuffer *old_fb) 343 struct drm_framebuffer *old_fb)
407{ 344{
@@ -755,7 +692,6 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
755 uint32_t post_divider = 0; 692 uint32_t post_divider = 0;
756 uint32_t freq = 0; 693 uint32_t freq = 0;
757 uint8_t pll_gain; 694 uint8_t pll_gain;
758 int pll_flags = RADEON_PLL_LEGACY;
759 bool use_bios_divs = false; 695 bool use_bios_divs = false;
760 /* PLL registers */ 696 /* PLL registers */
761 uint32_t pll_ref_div = 0; 697 uint32_t pll_ref_div = 0;
@@ -789,10 +725,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
789 else 725 else
790 pll = &rdev->clock.p1pll; 726 pll = &rdev->clock.p1pll;
791 727
728 pll->flags = RADEON_PLL_LEGACY;
729
792 if (mode->clock > 200000) /* range limits??? */ 730 if (mode->clock > 200000) /* range limits??? */
793 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 731 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
794 else 732 else
795 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 733 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
796 734
797 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 735 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
798 if (encoder->crtc == crtc) { 736 if (encoder->crtc == crtc) {
@@ -804,7 +742,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
804 } 742 }
805 743
806 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 744 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
807 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 745 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
808 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 746 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
809 if (!rdev->is_atom_bios) { 747 if (!rdev->is_atom_bios) {
810 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 748 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -819,7 +757,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
819 } 757 }
820 } 758 }
821 } 759 }
822 pll_flags |= RADEON_PLL_USE_REF_DIV; 760 pll->flags |= RADEON_PLL_USE_REF_DIV;
823 } 761 }
824 } 762 }
825 } 763 }
@@ -829,8 +767,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
829 if (!use_bios_divs) { 767 if (!use_bios_divs) {
830 radeon_compute_pll(pll, mode->clock, 768 radeon_compute_pll(pll, mode->clock,
831 &freq, &feedback_div, &frac_fb_div, 769 &freq, &feedback_div, &frac_fb_div,
832 &reference_div, &post_divider, 770 &reference_div, &post_divider);
833 pll_flags);
834 771
835 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 772 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
836 if (post_div->divider == post_divider) 773 if (post_div->divider == post_divider)
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index 981508ff703..38e45e231ef 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -46,6 +46,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; 47 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
48 int panel_pwr_delay = 2000; 48 int panel_pwr_delay = 2000;
49 bool is_mac = false;
49 DRM_DEBUG("\n"); 50 DRM_DEBUG("\n");
50 51
51 if (radeon_encoder->enc_priv) { 52 if (radeon_encoder->enc_priv) {
@@ -58,6 +59,15 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
58 } 59 }
59 } 60 }
60 61
62 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely
63 * Taken from radeonfb.
64 */
65 if ((rdev->mode_info.connector_table == CT_IBOOK) ||
66 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
67 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
68 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
69 is_mac = true;
70
61 switch (mode) { 71 switch (mode) {
62 case DRM_MODE_DPMS_ON: 72 case DRM_MODE_DPMS_ON:
63 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); 73 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
@@ -74,6 +84,8 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
74 84
75 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 85 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
76 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON); 86 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
87 if (is_mac)
88 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
77 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS); 89 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
78 udelay(panel_pwr_delay * 1000); 90 udelay(panel_pwr_delay * 1000);
79 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 91 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
@@ -85,7 +97,14 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
85 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 97 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
86 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 98 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
87 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 99 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
88 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); 100 if (is_mac) {
101 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
102 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
103 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
104 } else {
105 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
106 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
107 }
89 udelay(panel_pwr_delay * 1000); 108 udelay(panel_pwr_delay * 1000);
90 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 109 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
91 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 110 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
index 3a12bb0c056..417684daef4 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -77,7 +77,7 @@ struct radeon_tv_mode_constants {
77 unsigned pix_to_tv; 77 unsigned pix_to_tv;
78}; 78};
79 79
80static const uint16_t hor_timing_NTSC[] = { 80static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = {
81 0x0007, 81 0x0007,
82 0x003f, 82 0x003f,
83 0x0263, 83 0x0263,
@@ -98,7 +98,7 @@ static const uint16_t hor_timing_NTSC[] = {
98 0 98 0
99}; 99};
100 100
101static const uint16_t vert_timing_NTSC[] = { 101static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = {
102 0x2001, 102 0x2001,
103 0x200d, 103 0x200d,
104 0x1006, 104 0x1006,
@@ -115,7 +115,7 @@ static const uint16_t vert_timing_NTSC[] = {
115 0 115 0
116}; 116};
117 117
118static const uint16_t hor_timing_PAL[] = { 118static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = {
119 0x0007, 119 0x0007,
120 0x0058, 120 0x0058,
121 0x027c, 121 0x027c,
@@ -136,7 +136,7 @@ static const uint16_t hor_timing_PAL[] = {
136 0 136 0
137}; 137};
138 138
139static const uint16_t vert_timing_PAL[] = { 139static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = {
140 0x2001, 140 0x2001,
141 0x200c, 141 0x200c,
142 0x1005, 142 0x1005,
@@ -623,9 +623,9 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
623 } 623 }
624 flicker_removal = (tmp + 500) / 1000; 624 flicker_removal = (tmp + 500) / 1000;
625 625
626 if (flicker_removal < 3) 626 if (flicker_removal < 2)
627 flicker_removal = 3; 627 flicker_removal = 2;
628 for (i = 0; i < 6; ++i) { 628 for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
629 if (flicker_removal == SLOPE_limit[i]) 629 if (flicker_removal == SLOPE_limit[i])
630 break; 630 break;
631 } 631 }
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 402369db5ba..e81b2aeb6a8 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -46,32 +46,6 @@ struct radeon_device;
46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base) 46#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base) 47#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
48 48
49enum radeon_connector_type {
50 CONNECTOR_NONE,
51 CONNECTOR_VGA,
52 CONNECTOR_DVI_I,
53 CONNECTOR_DVI_D,
54 CONNECTOR_DVI_A,
55 CONNECTOR_STV,
56 CONNECTOR_CTV,
57 CONNECTOR_LVDS,
58 CONNECTOR_DIGITAL,
59 CONNECTOR_SCART,
60 CONNECTOR_HDMI_TYPE_A,
61 CONNECTOR_HDMI_TYPE_B,
62 CONNECTOR_0XC,
63 CONNECTOR_0XD,
64 CONNECTOR_DIN,
65 CONNECTOR_DISPLAY_PORT,
66 CONNECTOR_UNSUPPORTED
67};
68
69enum radeon_dvi_type {
70 DVI_AUTO,
71 DVI_DIGITAL,
72 DVI_ANALOG
73};
74
75enum radeon_rmx_type { 49enum radeon_rmx_type {
76 RMX_OFF, 50 RMX_OFF,
77 RMX_FULL, 51 RMX_FULL,
@@ -151,16 +125,24 @@ struct radeon_tmds_pll {
151#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9) 125#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
152#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10) 126#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
153#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11) 127#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
128#define RADEON_PLL_USE_POST_DIV (1 << 12)
154 129
155struct radeon_pll { 130struct radeon_pll {
156 uint16_t reference_freq; 131 /* reference frequency */
157 uint16_t reference_div; 132 uint32_t reference_freq;
133
134 /* fixed dividers */
135 uint32_t reference_div;
136 uint32_t post_div;
137
138 /* pll in/out limits */
158 uint32_t pll_in_min; 139 uint32_t pll_in_min;
159 uint32_t pll_in_max; 140 uint32_t pll_in_max;
160 uint32_t pll_out_min; 141 uint32_t pll_out_min;
161 uint32_t pll_out_max; 142 uint32_t pll_out_max;
162 uint16_t xclk; 143 uint32_t best_vco;
163 144
145 /* divider limits */
164 uint32_t min_ref_div; 146 uint32_t min_ref_div;
165 uint32_t max_ref_div; 147 uint32_t max_ref_div;
166 uint32_t min_post_div; 148 uint32_t min_post_div;
@@ -169,7 +151,12 @@ struct radeon_pll {
169 uint32_t max_feedback_div; 151 uint32_t max_feedback_div;
170 uint32_t min_frac_feedback_div; 152 uint32_t min_frac_feedback_div;
171 uint32_t max_frac_feedback_div; 153 uint32_t max_frac_feedback_div;
172 uint32_t best_vco; 154
155 /* flags for the current clock */
156 uint32_t flags;
157
158 /* pll id */
159 uint32_t id;
173}; 160};
174 161
175struct radeon_i2c_chan { 162struct radeon_i2c_chan {
@@ -312,7 +299,7 @@ struct radeon_atom_ss {
312struct radeon_encoder_atom_dig { 299struct radeon_encoder_atom_dig {
313 /* atom dig */ 300 /* atom dig */
314 bool coherent_mode; 301 bool coherent_mode;
315 int dig_block; 302 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB */
316 /* atom lvds */ 303 /* atom lvds */
317 uint32_t lvds_misc; 304 uint32_t lvds_misc;
318 uint16_t panel_pwr_delay; 305 uint16_t panel_pwr_delay;
@@ -443,8 +430,7 @@ extern void radeon_compute_pll(struct radeon_pll *pll,
443 uint32_t *fb_div_p, 430 uint32_t *fb_div_p,
444 uint32_t *frac_fb_div_p, 431 uint32_t *frac_fb_div_p,
445 uint32_t *ref_div_p, 432 uint32_t *ref_div_p,
446 uint32_t *post_div_p, 433 uint32_t *post_div_p);
447 int flags);
448 434
449extern void radeon_compute_pll_avivo(struct radeon_pll *pll, 435extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
450 uint64_t freq, 436 uint64_t freq,
@@ -452,8 +438,7 @@ extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
452 uint32_t *fb_div_p, 438 uint32_t *fb_div_p,
453 uint32_t *frac_fb_div_p, 439 uint32_t *frac_fb_div_p,
454 uint32_t *ref_div_p, 440 uint32_t *ref_div_p,
455 uint32_t *post_div_p, 441 uint32_t *post_div_p);
456 int flags);
457 442
458extern void radeon_setup_encoder_clones(struct drm_device *dev); 443extern void radeon_setup_encoder_clones(struct drm_device *dev);
459 444
@@ -479,7 +464,6 @@ extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
479 464
480extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y, 465extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
481 struct drm_framebuffer *old_fb); 466 struct drm_framebuffer *old_fb);
482extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
483 467
484extern int radeon_crtc_cursor_set(struct drm_crtc *crtc, 468extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
485 struct drm_file *file_priv, 469 struct drm_file *file_priv,
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index d9ffe1f56e8..d72a71bff21 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -220,9 +220,11 @@ int radeon_bo_unpin(struct radeon_bo *bo)
220 220
221int radeon_bo_evict_vram(struct radeon_device *rdev) 221int radeon_bo_evict_vram(struct radeon_device *rdev)
222{ 222{
223 if (rdev->flags & RADEON_IS_IGP) { 223 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
224 /* Useless to evict on IGP chips */ 224 if (0 && (rdev->flags & RADEON_IS_IGP)) {
225 return 0; 225 if (rdev->mc.igp_sideport_enabled == false)
226 /* Useless to evict on IGP chips */
227 return 0;
226 } 228 }
227 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM); 229 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
228} 230}
diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c
index 3b0c07b444a..58b5adf974c 100644
--- a/drivers/gpu/drm/radeon/radeon_ttm.c
+++ b/drivers/gpu/drm/radeon/radeon_ttm.c
@@ -215,7 +215,10 @@ static void radeon_evict_flags(struct ttm_buffer_object *bo,
215 rbo = container_of(bo, struct radeon_bo, tbo); 215 rbo = container_of(bo, struct radeon_bo, tbo);
216 switch (bo->mem.mem_type) { 216 switch (bo->mem.mem_type) {
217 case TTM_PL_VRAM: 217 case TTM_PL_VRAM:
218 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 218 if (rbo->rdev->cp.ready == false)
219 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU);
220 else
221 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
219 break; 222 break;
220 case TTM_PL_TT: 223 case TTM_PL_TT:
221 default: 224 default:
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r200 b/drivers/gpu/drm/radeon/reg_srcs/r200
index 6021c8849a1..c29ac434ac9 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r200
+++ b/drivers/gpu/drm/radeon/reg_srcs/r200
@@ -91,6 +91,8 @@ r200 0x3294
910x22b8 SE_TCL_TEX_CYL_WRAP_CTL 910x22b8 SE_TCL_TEX_CYL_WRAP_CTL
920x22c0 SE_TCL_UCP_VERT_BLEND_CNTL 920x22c0 SE_TCL_UCP_VERT_BLEND_CNTL
930x22c4 SE_TCL_POINT_SPRITE_CNTL 930x22c4 SE_TCL_POINT_SPRITE_CNTL
940x22d0 SE_PVS_CNTL
950x22d4 SE_PVS_CONST_CNTL
940x2648 RE_POINTSIZE 960x2648 RE_POINTSIZE
950x26c0 RE_TOP_LEFT 970x26c0 RE_TOP_LEFT
960x26c4 RE_MISC 980x26c4 RE_MISC
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r420 b/drivers/gpu/drm/radeon/reg_srcs/r420
new file mode 100644
index 00000000000..989f7a02083
--- /dev/null
+++ b/drivers/gpu/drm/radeon/reg_srcs/r420
@@ -0,0 +1,795 @@
1r420 0x4f60
20x1434 SRC_Y_X
30x1438 DST_Y_X
40x143C DST_HEIGHT_WIDTH
50x146C DP_GUI_MASTER_CNTL
60x1474 BRUSH_Y_X
70x1478 DP_BRUSH_BKGD_CLR
80x147C DP_BRUSH_FRGD_CLR
90x1480 BRUSH_DATA0
100x1484 BRUSH_DATA1
110x1598 DST_WIDTH_HEIGHT
120x15C0 CLR_CMP_CNTL
130x15C4 CLR_CMP_CLR_SRC
140x15C8 CLR_CMP_CLR_DST
150x15CC CLR_CMP_MSK
160x15D8 DP_SRC_FRGD_CLR
170x15DC DP_SRC_BKGD_CLR
180x1600 DST_LINE_START
190x1604 DST_LINE_END
200x1608 DST_LINE_PATCOUNT
210x16C0 DP_CNTL
220x16CC DP_WRITE_MSK
230x16D0 DP_CNTL_XDIR_YDIR_YMAJOR
240x16E8 DEFAULT_SC_BOTTOM_RIGHT
250x16EC SC_TOP_LEFT
260x16F0 SC_BOTTOM_RIGHT
270x16F4 SRC_SC_BOTTOM_RIGHT
280x1714 DSTCACHE_CTLSTAT
290x1720 WAIT_UNTIL
300x172C RBBM_GUICNTL
310x1D98 VAP_VPORT_XSCALE
320x1D9C VAP_VPORT_XOFFSET
330x1DA0 VAP_VPORT_YSCALE
340x1DA4 VAP_VPORT_YOFFSET
350x1DA8 VAP_VPORT_ZSCALE
360x1DAC VAP_VPORT_ZOFFSET
370x2080 VAP_CNTL
380x2090 VAP_OUT_VTX_FMT_0
390x2094 VAP_OUT_VTX_FMT_1
400x20B0 VAP_VTE_CNTL
410x2138 VAP_VF_MIN_VTX_INDX
420x2140 VAP_CNTL_STATUS
430x2150 VAP_PROG_STREAM_CNTL_0
440x2154 VAP_PROG_STREAM_CNTL_1
450x2158 VAP_PROG_STREAM_CNTL_2
460x215C VAP_PROG_STREAM_CNTL_3
470x2160 VAP_PROG_STREAM_CNTL_4
480x2164 VAP_PROG_STREAM_CNTL_5
490x2168 VAP_PROG_STREAM_CNTL_6
500x216C VAP_PROG_STREAM_CNTL_7
510x2180 VAP_VTX_STATE_CNTL
520x2184 VAP_VSM_VTX_ASSM
530x2188 VAP_VTX_STATE_IND_REG_0
540x218C VAP_VTX_STATE_IND_REG_1
550x2190 VAP_VTX_STATE_IND_REG_2
560x2194 VAP_VTX_STATE_IND_REG_3
570x2198 VAP_VTX_STATE_IND_REG_4
580x219C VAP_VTX_STATE_IND_REG_5
590x21A0 VAP_VTX_STATE_IND_REG_6
600x21A4 VAP_VTX_STATE_IND_REG_7
610x21A8 VAP_VTX_STATE_IND_REG_8
620x21AC VAP_VTX_STATE_IND_REG_9
630x21B0 VAP_VTX_STATE_IND_REG_10
640x21B4 VAP_VTX_STATE_IND_REG_11
650x21B8 VAP_VTX_STATE_IND_REG_12
660x21BC VAP_VTX_STATE_IND_REG_13
670x21C0 VAP_VTX_STATE_IND_REG_14
680x21C4 VAP_VTX_STATE_IND_REG_15
690x21DC VAP_PSC_SGN_NORM_CNTL
700x21E0 VAP_PROG_STREAM_CNTL_EXT_0
710x21E4 VAP_PROG_STREAM_CNTL_EXT_1
720x21E8 VAP_PROG_STREAM_CNTL_EXT_2
730x21EC VAP_PROG_STREAM_CNTL_EXT_3
740x21F0 VAP_PROG_STREAM_CNTL_EXT_4
750x21F4 VAP_PROG_STREAM_CNTL_EXT_5
760x21F8 VAP_PROG_STREAM_CNTL_EXT_6
770x21FC VAP_PROG_STREAM_CNTL_EXT_7
780x2200 VAP_PVS_VECTOR_INDX_REG
790x2204 VAP_PVS_VECTOR_DATA_REG
800x2208 VAP_PVS_VECTOR_DATA_REG_128
810x221C VAP_CLIP_CNTL
820x2220 VAP_GB_VERT_CLIP_ADJ
830x2224 VAP_GB_VERT_DISC_ADJ
840x2228 VAP_GB_HORZ_CLIP_ADJ
850x222C VAP_GB_HORZ_DISC_ADJ
860x2230 VAP_PVS_FLOW_CNTL_ADDRS_0
870x2234 VAP_PVS_FLOW_CNTL_ADDRS_1
880x2238 VAP_PVS_FLOW_CNTL_ADDRS_2
890x223C VAP_PVS_FLOW_CNTL_ADDRS_3
900x2240 VAP_PVS_FLOW_CNTL_ADDRS_4
910x2244 VAP_PVS_FLOW_CNTL_ADDRS_5
920x2248 VAP_PVS_FLOW_CNTL_ADDRS_6
930x224C VAP_PVS_FLOW_CNTL_ADDRS_7
940x2250 VAP_PVS_FLOW_CNTL_ADDRS_8
950x2254 VAP_PVS_FLOW_CNTL_ADDRS_9
960x2258 VAP_PVS_FLOW_CNTL_ADDRS_10
970x225C VAP_PVS_FLOW_CNTL_ADDRS_11
980x2260 VAP_PVS_FLOW_CNTL_ADDRS_12
990x2264 VAP_PVS_FLOW_CNTL_ADDRS_13
1000x2268 VAP_PVS_FLOW_CNTL_ADDRS_14
1010x226C VAP_PVS_FLOW_CNTL_ADDRS_15
1020x2284 VAP_PVS_STATE_FLUSH_REG
1030x2288 VAP_PVS_VTX_TIMEOUT_REG
1040x2290 VAP_PVS_FLOW_CNTL_LOOP_INDEX_0
1050x2294 VAP_PVS_FLOW_CNTL_LOOP_INDEX_1
1060x2298 VAP_PVS_FLOW_CNTL_LOOP_INDEX_2
1070x229C VAP_PVS_FLOW_CNTL_LOOP_INDEX_3
1080x22A0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_4
1090x22A4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_5
1100x22A8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_6
1110x22AC VAP_PVS_FLOW_CNTL_LOOP_INDEX_7
1120x22B0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_8
1130x22B4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_9
1140x22B8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_10
1150x22BC VAP_PVS_FLOW_CNTL_LOOP_INDEX_11
1160x22C0 VAP_PVS_FLOW_CNTL_LOOP_INDEX_12
1170x22C4 VAP_PVS_FLOW_CNTL_LOOP_INDEX_13
1180x22C8 VAP_PVS_FLOW_CNTL_LOOP_INDEX_14
1190x22CC VAP_PVS_FLOW_CNTL_LOOP_INDEX_15
1200x22D0 VAP_PVS_CODE_CNTL_0
1210x22D4 VAP_PVS_CONST_CNTL
1220x22D8 VAP_PVS_CODE_CNTL_1
1230x22DC VAP_PVS_FLOW_CNTL_OPC
1240x342C RB2D_DSTCACHE_CTLSTAT
1250x4000 GB_VAP_RASTER_VTX_FMT_0
1260x4004 GB_VAP_RASTER_VTX_FMT_1
1270x4008 GB_ENABLE
1280x401C GB_SELECT
1290x4020 GB_AA_CONFIG
1300x4024 GB_FIFO_SIZE
1310x4100 TX_INVALTAGS
1320x4200 GA_POINT_S0
1330x4204 GA_POINT_T0
1340x4208 GA_POINT_S1
1350x420C GA_POINT_T1
1360x4214 GA_TRIANGLE_STIPPLE
1370x421C GA_POINT_SIZE
1380x4230 GA_POINT_MINMAX
1390x4234 GA_LINE_CNTL
1400x4238 GA_LINE_STIPPLE_CONFIG
1410x4260 GA_LINE_STIPPLE_VALUE
1420x4264 GA_LINE_S0
1430x4268 GA_LINE_S1
1440x4278 GA_COLOR_CONTROL
1450x427C GA_SOLID_RG
1460x4280 GA_SOLID_BA
1470x4288 GA_POLY_MODE
1480x428C GA_ROUND_MODE
1490x4290 GA_OFFSET
1500x4294 GA_FOG_SCALE
1510x4298 GA_FOG_OFFSET
1520x42A0 SU_TEX_WRAP
1530x42A4 SU_POLY_OFFSET_FRONT_SCALE
1540x42A8 SU_POLY_OFFSET_FRONT_OFFSET
1550x42AC SU_POLY_OFFSET_BACK_SCALE
1560x42B0 SU_POLY_OFFSET_BACK_OFFSET
1570x42B4 SU_POLY_OFFSET_ENABLE
1580x42B8 SU_CULL_MODE
1590x42C0 SU_DEPTH_SCALE
1600x42C4 SU_DEPTH_OFFSET
1610x42C8 SU_REG_DEST
1620x4300 RS_COUNT
1630x4304 RS_INST_COUNT
1640x4310 RS_IP_0
1650x4314 RS_IP_1
1660x4318 RS_IP_2
1670x431C RS_IP_3
1680x4320 RS_IP_4
1690x4324 RS_IP_5
1700x4328 RS_IP_6
1710x432C RS_IP_7
1720x4330 RS_INST_0
1730x4334 RS_INST_1
1740x4338 RS_INST_2
1750x433C RS_INST_3
1760x4340 RS_INST_4
1770x4344 RS_INST_5
1780x4348 RS_INST_6
1790x434C RS_INST_7
1800x4350 RS_INST_8
1810x4354 RS_INST_9
1820x4358 RS_INST_10
1830x435C RS_INST_11
1840x4360 RS_INST_12
1850x4364 RS_INST_13
1860x4368 RS_INST_14
1870x436C RS_INST_15
1880x43A4 SC_HYPERZ_EN
1890x43A8 SC_EDGERULE
1900x43B0 SC_CLIP_0_A
1910x43B4 SC_CLIP_0_B
1920x43B8 SC_CLIP_1_A
1930x43BC SC_CLIP_1_B
1940x43C0 SC_CLIP_2_A
1950x43C4 SC_CLIP_2_B
1960x43C8 SC_CLIP_3_A
1970x43CC SC_CLIP_3_B
1980x43D0 SC_CLIP_RULE
1990x43E0 SC_SCISSOR0
2000x43E8 SC_SCREENDOOR
2010x4440 TX_FILTER1_0
2020x4444 TX_FILTER1_1
2030x4448 TX_FILTER1_2
2040x444C TX_FILTER1_3
2050x4450 TX_FILTER1_4
2060x4454 TX_FILTER1_5
2070x4458 TX_FILTER1_6
2080x445C TX_FILTER1_7
2090x4460 TX_FILTER1_8
2100x4464 TX_FILTER1_9
2110x4468 TX_FILTER1_10
2120x446C TX_FILTER1_11
2130x4470 TX_FILTER1_12
2140x4474 TX_FILTER1_13
2150x4478 TX_FILTER1_14
2160x447C TX_FILTER1_15
2170x4580 TX_CHROMA_KEY_0
2180x4584 TX_CHROMA_KEY_1
2190x4588 TX_CHROMA_KEY_2
2200x458C TX_CHROMA_KEY_3
2210x4590 TX_CHROMA_KEY_4
2220x4594 TX_CHROMA_KEY_5
2230x4598 TX_CHROMA_KEY_6
2240x459C TX_CHROMA_KEY_7
2250x45A0 TX_CHROMA_KEY_8
2260x45A4 TX_CHROMA_KEY_9
2270x45A8 TX_CHROMA_KEY_10
2280x45AC TX_CHROMA_KEY_11
2290x45B0 TX_CHROMA_KEY_12
2300x45B4 TX_CHROMA_KEY_13
2310x45B8 TX_CHROMA_KEY_14
2320x45BC TX_CHROMA_KEY_15
2330x45C0 TX_BORDER_COLOR_0
2340x45C4 TX_BORDER_COLOR_1
2350x45C8 TX_BORDER_COLOR_2
2360x45CC TX_BORDER_COLOR_3
2370x45D0 TX_BORDER_COLOR_4
2380x45D4 TX_BORDER_COLOR_5
2390x45D8 TX_BORDER_COLOR_6
2400x45DC TX_BORDER_COLOR_7
2410x45E0 TX_BORDER_COLOR_8
2420x45E4 TX_BORDER_COLOR_9
2430x45E8 TX_BORDER_COLOR_10
2440x45EC TX_BORDER_COLOR_11
2450x45F0 TX_BORDER_COLOR_12
2460x45F4 TX_BORDER_COLOR_13
2470x45F8 TX_BORDER_COLOR_14
2480x45FC TX_BORDER_COLOR_15
2490x4600 US_CONFIG
2500x4604 US_PIXSIZE
2510x4608 US_CODE_OFFSET
2520x460C US_RESET
2530x4610 US_CODE_ADDR_0
2540x4614 US_CODE_ADDR_1
2550x4618 US_CODE_ADDR_2
2560x461C US_CODE_ADDR_3
2570x4620 US_TEX_INST_0
2580x4624 US_TEX_INST_1
2590x4628 US_TEX_INST_2
2600x462C US_TEX_INST_3
2610x4630 US_TEX_INST_4
2620x4634 US_TEX_INST_5
2630x4638 US_TEX_INST_6
2640x463C US_TEX_INST_7
2650x4640 US_TEX_INST_8
2660x4644 US_TEX_INST_9
2670x4648 US_TEX_INST_10
2680x464C US_TEX_INST_11
2690x4650 US_TEX_INST_12
2700x4654 US_TEX_INST_13
2710x4658 US_TEX_INST_14
2720x465C US_TEX_INST_15
2730x4660 US_TEX_INST_16
2740x4664 US_TEX_INST_17
2750x4668 US_TEX_INST_18
2760x466C US_TEX_INST_19
2770x4670 US_TEX_INST_20
2780x4674 US_TEX_INST_21
2790x4678 US_TEX_INST_22
2800x467C US_TEX_INST_23
2810x4680 US_TEX_INST_24
2820x4684 US_TEX_INST_25
2830x4688 US_TEX_INST_26
2840x468C US_TEX_INST_27
2850x4690 US_TEX_INST_28
2860x4694 US_TEX_INST_29
2870x4698 US_TEX_INST_30
2880x469C US_TEX_INST_31
2890x46A4 US_OUT_FMT_0
2900x46A8 US_OUT_FMT_1
2910x46AC US_OUT_FMT_2
2920x46B0 US_OUT_FMT_3
2930x46B4 US_W_FMT
2940x46B8 US_CODE_BANK
2950x46BC US_CODE_EXT
2960x46C0 US_ALU_RGB_ADDR_0
2970x46C4 US_ALU_RGB_ADDR_1
2980x46C8 US_ALU_RGB_ADDR_2
2990x46CC US_ALU_RGB_ADDR_3
3000x46D0 US_ALU_RGB_ADDR_4
3010x46D4 US_ALU_RGB_ADDR_5
3020x46D8 US_ALU_RGB_ADDR_6
3030x46DC US_ALU_RGB_ADDR_7
3040x46E0 US_ALU_RGB_ADDR_8
3050x46E4 US_ALU_RGB_ADDR_9
3060x46E8 US_ALU_RGB_ADDR_10
3070x46EC US_ALU_RGB_ADDR_11
3080x46F0 US_ALU_RGB_ADDR_12
3090x46F4 US_ALU_RGB_ADDR_13
3100x46F8 US_ALU_RGB_ADDR_14
3110x46FC US_ALU_RGB_ADDR_15
3120x4700 US_ALU_RGB_ADDR_16
3130x4704 US_ALU_RGB_ADDR_17
3140x4708 US_ALU_RGB_ADDR_18
3150x470C US_ALU_RGB_ADDR_19
3160x4710 US_ALU_RGB_ADDR_20
3170x4714 US_ALU_RGB_ADDR_21
3180x4718 US_ALU_RGB_ADDR_22
3190x471C US_ALU_RGB_ADDR_23
3200x4720 US_ALU_RGB_ADDR_24
3210x4724 US_ALU_RGB_ADDR_25
3220x4728 US_ALU_RGB_ADDR_26
3230x472C US_ALU_RGB_ADDR_27
3240x4730 US_ALU_RGB_ADDR_28
3250x4734 US_ALU_RGB_ADDR_29
3260x4738 US_ALU_RGB_ADDR_30
3270x473C US_ALU_RGB_ADDR_31
3280x4740 US_ALU_RGB_ADDR_32
3290x4744 US_ALU_RGB_ADDR_33
3300x4748 US_ALU_RGB_ADDR_34
3310x474C US_ALU_RGB_ADDR_35
3320x4750 US_ALU_RGB_ADDR_36
3330x4754 US_ALU_RGB_ADDR_37
3340x4758 US_ALU_RGB_ADDR_38
3350x475C US_ALU_RGB_ADDR_39
3360x4760 US_ALU_RGB_ADDR_40
3370x4764 US_ALU_RGB_ADDR_41
3380x4768 US_ALU_RGB_ADDR_42
3390x476C US_ALU_RGB_ADDR_43
3400x4770 US_ALU_RGB_ADDR_44
3410x4774 US_ALU_RGB_ADDR_45
3420x4778 US_ALU_RGB_ADDR_46
3430x477C US_ALU_RGB_ADDR_47
3440x4780 US_ALU_RGB_ADDR_48
3450x4784 US_ALU_RGB_ADDR_49
3460x4788 US_ALU_RGB_ADDR_50
3470x478C US_ALU_RGB_ADDR_51
3480x4790 US_ALU_RGB_ADDR_52
3490x4794 US_ALU_RGB_ADDR_53
3500x4798 US_ALU_RGB_ADDR_54
3510x479C US_ALU_RGB_ADDR_55
3520x47A0 US_ALU_RGB_ADDR_56
3530x47A4 US_ALU_RGB_ADDR_57
3540x47A8 US_ALU_RGB_ADDR_58
3550x47AC US_ALU_RGB_ADDR_59
3560x47B0 US_ALU_RGB_ADDR_60
3570x47B4 US_ALU_RGB_ADDR_61
3580x47B8 US_ALU_RGB_ADDR_62
3590x47BC US_ALU_RGB_ADDR_63
3600x47C0 US_ALU_ALPHA_ADDR_0
3610x47C4 US_ALU_ALPHA_ADDR_1
3620x47C8 US_ALU_ALPHA_ADDR_2
3630x47CC US_ALU_ALPHA_ADDR_3
3640x47D0 US_ALU_ALPHA_ADDR_4
3650x47D4 US_ALU_ALPHA_ADDR_5
3660x47D8 US_ALU_ALPHA_ADDR_6
3670x47DC US_ALU_ALPHA_ADDR_7
3680x47E0 US_ALU_ALPHA_ADDR_8
3690x47E4 US_ALU_ALPHA_ADDR_9
3700x47E8 US_ALU_ALPHA_ADDR_10
3710x47EC US_ALU_ALPHA_ADDR_11
3720x47F0 US_ALU_ALPHA_ADDR_12
3730x47F4 US_ALU_ALPHA_ADDR_13
3740x47F8 US_ALU_ALPHA_ADDR_14
3750x47FC US_ALU_ALPHA_ADDR_15
3760x4800 US_ALU_ALPHA_ADDR_16
3770x4804 US_ALU_ALPHA_ADDR_17
3780x4808 US_ALU_ALPHA_ADDR_18
3790x480C US_ALU_ALPHA_ADDR_19
3800x4810 US_ALU_ALPHA_ADDR_20
3810x4814 US_ALU_ALPHA_ADDR_21
3820x4818 US_ALU_ALPHA_ADDR_22
3830x481C US_ALU_ALPHA_ADDR_23
3840x4820 US_ALU_ALPHA_ADDR_24
3850x4824 US_ALU_ALPHA_ADDR_25
3860x4828 US_ALU_ALPHA_ADDR_26
3870x482C US_ALU_ALPHA_ADDR_27
3880x4830 US_ALU_ALPHA_ADDR_28
3890x4834 US_ALU_ALPHA_ADDR_29
3900x4838 US_ALU_ALPHA_ADDR_30
3910x483C US_ALU_ALPHA_ADDR_31
3920x4840 US_ALU_ALPHA_ADDR_32
3930x4844 US_ALU_ALPHA_ADDR_33
3940x4848 US_ALU_ALPHA_ADDR_34
3950x484C US_ALU_ALPHA_ADDR_35
3960x4850 US_ALU_ALPHA_ADDR_36
3970x4854 US_ALU_ALPHA_ADDR_37
3980x4858 US_ALU_ALPHA_ADDR_38
3990x485C US_ALU_ALPHA_ADDR_39
4000x4860 US_ALU_ALPHA_ADDR_40
4010x4864 US_ALU_ALPHA_ADDR_41
4020x4868 US_ALU_ALPHA_ADDR_42
4030x486C US_ALU_ALPHA_ADDR_43
4040x4870 US_ALU_ALPHA_ADDR_44
4050x4874 US_ALU_ALPHA_ADDR_45
4060x4878 US_ALU_ALPHA_ADDR_46
4070x487C US_ALU_ALPHA_ADDR_47
4080x4880 US_ALU_ALPHA_ADDR_48
4090x4884 US_ALU_ALPHA_ADDR_49
4100x4888 US_ALU_ALPHA_ADDR_50
4110x488C US_ALU_ALPHA_ADDR_51
4120x4890 US_ALU_ALPHA_ADDR_52
4130x4894 US_ALU_ALPHA_ADDR_53
4140x4898 US_ALU_ALPHA_ADDR_54
4150x489C US_ALU_ALPHA_ADDR_55
4160x48A0 US_ALU_ALPHA_ADDR_56
4170x48A4 US_ALU_ALPHA_ADDR_57
4180x48A8 US_ALU_ALPHA_ADDR_58
4190x48AC US_ALU_ALPHA_ADDR_59
4200x48B0 US_ALU_ALPHA_ADDR_60
4210x48B4 US_ALU_ALPHA_ADDR_61
4220x48B8 US_ALU_ALPHA_ADDR_62
4230x48BC US_ALU_ALPHA_ADDR_63
4240x48C0 US_ALU_RGB_INST_0
4250x48C4 US_ALU_RGB_INST_1
4260x48C8 US_ALU_RGB_INST_2
4270x48CC US_ALU_RGB_INST_3
4280x48D0 US_ALU_RGB_INST_4
4290x48D4 US_ALU_RGB_INST_5
4300x48D8 US_ALU_RGB_INST_6
4310x48DC US_ALU_RGB_INST_7
4320x48E0 US_ALU_RGB_INST_8
4330x48E4 US_ALU_RGB_INST_9
4340x48E8 US_ALU_RGB_INST_10
4350x48EC US_ALU_RGB_INST_11
4360x48F0 US_ALU_RGB_INST_12
4370x48F4 US_ALU_RGB_INST_13
4380x48F8 US_ALU_RGB_INST_14
4390x48FC US_ALU_RGB_INST_15
4400x4900 US_ALU_RGB_INST_16
4410x4904 US_ALU_RGB_INST_17
4420x4908 US_ALU_RGB_INST_18
4430x490C US_ALU_RGB_INST_19
4440x4910 US_ALU_RGB_INST_20
4450x4914 US_ALU_RGB_INST_21
4460x4918 US_ALU_RGB_INST_22
4470x491C US_ALU_RGB_INST_23
4480x4920 US_ALU_RGB_INST_24
4490x4924 US_ALU_RGB_INST_25
4500x4928 US_ALU_RGB_INST_26
4510x492C US_ALU_RGB_INST_27
4520x4930 US_ALU_RGB_INST_28
4530x4934 US_ALU_RGB_INST_29
4540x4938 US_ALU_RGB_INST_30
4550x493C US_ALU_RGB_INST_31
4560x4940 US_ALU_RGB_INST_32
4570x4944 US_ALU_RGB_INST_33
4580x4948 US_ALU_RGB_INST_34
4590x494C US_ALU_RGB_INST_35
4600x4950 US_ALU_RGB_INST_36
4610x4954 US_ALU_RGB_INST_37
4620x4958 US_ALU_RGB_INST_38
4630x495C US_ALU_RGB_INST_39
4640x4960 US_ALU_RGB_INST_40
4650x4964 US_ALU_RGB_INST_41
4660x4968 US_ALU_RGB_INST_42
4670x496C US_ALU_RGB_INST_43
4680x4970 US_ALU_RGB_INST_44
4690x4974 US_ALU_RGB_INST_45
4700x4978 US_ALU_RGB_INST_46
4710x497C US_ALU_RGB_INST_47
4720x4980 US_ALU_RGB_INST_48
4730x4984 US_ALU_RGB_INST_49
4740x4988 US_ALU_RGB_INST_50
4750x498C US_ALU_RGB_INST_51
4760x4990 US_ALU_RGB_INST_52
4770x4994 US_ALU_RGB_INST_53
4780x4998 US_ALU_RGB_INST_54
4790x499C US_ALU_RGB_INST_55
4800x49A0 US_ALU_RGB_INST_56
4810x49A4 US_ALU_RGB_INST_57
4820x49A8 US_ALU_RGB_INST_58
4830x49AC US_ALU_RGB_INST_59
4840x49B0 US_ALU_RGB_INST_60
4850x49B4 US_ALU_RGB_INST_61
4860x49B8 US_ALU_RGB_INST_62
4870x49BC US_ALU_RGB_INST_63
4880x49C0 US_ALU_ALPHA_INST_0
4890x49C4 US_ALU_ALPHA_INST_1
4900x49C8 US_ALU_ALPHA_INST_2
4910x49CC US_ALU_ALPHA_INST_3
4920x49D0 US_ALU_ALPHA_INST_4
4930x49D4 US_ALU_ALPHA_INST_5
4940x49D8 US_ALU_ALPHA_INST_6
4950x49DC US_ALU_ALPHA_INST_7
4960x49E0 US_ALU_ALPHA_INST_8
4970x49E4 US_ALU_ALPHA_INST_9
4980x49E8 US_ALU_ALPHA_INST_10
4990x49EC US_ALU_ALPHA_INST_11
5000x49F0 US_ALU_ALPHA_INST_12
5010x49F4 US_ALU_ALPHA_INST_13
5020x49F8 US_ALU_ALPHA_INST_14
5030x49FC US_ALU_ALPHA_INST_15
5040x4A00 US_ALU_ALPHA_INST_16
5050x4A04 US_ALU_ALPHA_INST_17
5060x4A08 US_ALU_ALPHA_INST_18
5070x4A0C US_ALU_ALPHA_INST_19
5080x4A10 US_ALU_ALPHA_INST_20
5090x4A14 US_ALU_ALPHA_INST_21
5100x4A18 US_ALU_ALPHA_INST_22
5110x4A1C US_ALU_ALPHA_INST_23
5120x4A20 US_ALU_ALPHA_INST_24
5130x4A24 US_ALU_ALPHA_INST_25
5140x4A28 US_ALU_ALPHA_INST_26
5150x4A2C US_ALU_ALPHA_INST_27
5160x4A30 US_ALU_ALPHA_INST_28
5170x4A34 US_ALU_ALPHA_INST_29
5180x4A38 US_ALU_ALPHA_INST_30
5190x4A3C US_ALU_ALPHA_INST_31
5200x4A40 US_ALU_ALPHA_INST_32
5210x4A44 US_ALU_ALPHA_INST_33
5220x4A48 US_ALU_ALPHA_INST_34
5230x4A4C US_ALU_ALPHA_INST_35
5240x4A50 US_ALU_ALPHA_INST_36
5250x4A54 US_ALU_ALPHA_INST_37
5260x4A58 US_ALU_ALPHA_INST_38
5270x4A5C US_ALU_ALPHA_INST_39
5280x4A60 US_ALU_ALPHA_INST_40
5290x4A64 US_ALU_ALPHA_INST_41
5300x4A68 US_ALU_ALPHA_INST_42
5310x4A6C US_ALU_ALPHA_INST_43
5320x4A70 US_ALU_ALPHA_INST_44
5330x4A74 US_ALU_ALPHA_INST_45
5340x4A78 US_ALU_ALPHA_INST_46
5350x4A7C US_ALU_ALPHA_INST_47
5360x4A80 US_ALU_ALPHA_INST_48
5370x4A84 US_ALU_ALPHA_INST_49
5380x4A88 US_ALU_ALPHA_INST_50
5390x4A8C US_ALU_ALPHA_INST_51
5400x4A90 US_ALU_ALPHA_INST_52
5410x4A94 US_ALU_ALPHA_INST_53
5420x4A98 US_ALU_ALPHA_INST_54
5430x4A9C US_ALU_ALPHA_INST_55
5440x4AA0 US_ALU_ALPHA_INST_56
5450x4AA4 US_ALU_ALPHA_INST_57
5460x4AA8 US_ALU_ALPHA_INST_58
5470x4AAC US_ALU_ALPHA_INST_59
5480x4AB0 US_ALU_ALPHA_INST_60
5490x4AB4 US_ALU_ALPHA_INST_61
5500x4AB8 US_ALU_ALPHA_INST_62
5510x4ABC US_ALU_ALPHA_INST_63
5520x4AC0 US_ALU_EXT_ADDR_0
5530x4AC4 US_ALU_EXT_ADDR_1
5540x4AC8 US_ALU_EXT_ADDR_2
5550x4ACC US_ALU_EXT_ADDR_3
5560x4AD0 US_ALU_EXT_ADDR_4
5570x4AD4 US_ALU_EXT_ADDR_5
5580x4AD8 US_ALU_EXT_ADDR_6
5590x4ADC US_ALU_EXT_ADDR_7
5600x4AE0 US_ALU_EXT_ADDR_8
5610x4AE4 US_ALU_EXT_ADDR_9
5620x4AE8 US_ALU_EXT_ADDR_10
5630x4AEC US_ALU_EXT_ADDR_11
5640x4AF0 US_ALU_EXT_ADDR_12
5650x4AF4 US_ALU_EXT_ADDR_13
5660x4AF8 US_ALU_EXT_ADDR_14
5670x4AFC US_ALU_EXT_ADDR_15
5680x4B00 US_ALU_EXT_ADDR_16
5690x4B04 US_ALU_EXT_ADDR_17
5700x4B08 US_ALU_EXT_ADDR_18
5710x4B0C US_ALU_EXT_ADDR_19
5720x4B10 US_ALU_EXT_ADDR_20
5730x4B14 US_ALU_EXT_ADDR_21
5740x4B18 US_ALU_EXT_ADDR_22
5750x4B1C US_ALU_EXT_ADDR_23
5760x4B20 US_ALU_EXT_ADDR_24
5770x4B24 US_ALU_EXT_ADDR_25
5780x4B28 US_ALU_EXT_ADDR_26
5790x4B2C US_ALU_EXT_ADDR_27
5800x4B30 US_ALU_EXT_ADDR_28
5810x4B34 US_ALU_EXT_ADDR_29
5820x4B38 US_ALU_EXT_ADDR_30
5830x4B3C US_ALU_EXT_ADDR_31
5840x4B40 US_ALU_EXT_ADDR_32
5850x4B44 US_ALU_EXT_ADDR_33
5860x4B48 US_ALU_EXT_ADDR_34
5870x4B4C US_ALU_EXT_ADDR_35
5880x4B50 US_ALU_EXT_ADDR_36
5890x4B54 US_ALU_EXT_ADDR_37
5900x4B58 US_ALU_EXT_ADDR_38
5910x4B5C US_ALU_EXT_ADDR_39
5920x4B60 US_ALU_EXT_ADDR_40
5930x4B64 US_ALU_EXT_ADDR_41
5940x4B68 US_ALU_EXT_ADDR_42
5950x4B6C US_ALU_EXT_ADDR_43
5960x4B70 US_ALU_EXT_ADDR_44
5970x4B74 US_ALU_EXT_ADDR_45
5980x4B78 US_ALU_EXT_ADDR_46
5990x4B7C US_ALU_EXT_ADDR_47
6000x4B80 US_ALU_EXT_ADDR_48
6010x4B84 US_ALU_EXT_ADDR_49
6020x4B88 US_ALU_EXT_ADDR_50
6030x4B8C US_ALU_EXT_ADDR_51
6040x4B90 US_ALU_EXT_ADDR_52
6050x4B94 US_ALU_EXT_ADDR_53
6060x4B98 US_ALU_EXT_ADDR_54
6070x4B9C US_ALU_EXT_ADDR_55
6080x4BA0 US_ALU_EXT_ADDR_56
6090x4BA4 US_ALU_EXT_ADDR_57
6100x4BA8 US_ALU_EXT_ADDR_58
6110x4BAC US_ALU_EXT_ADDR_59
6120x4BB0 US_ALU_EXT_ADDR_60
6130x4BB4 US_ALU_EXT_ADDR_61
6140x4BB8 US_ALU_EXT_ADDR_62
6150x4BBC US_ALU_EXT_ADDR_63
6160x4BC0 FG_FOG_BLEND
6170x4BC4 FG_FOG_FACTOR
6180x4BC8 FG_FOG_COLOR_R
6190x4BCC FG_FOG_COLOR_G
6200x4BD0 FG_FOG_COLOR_B
6210x4BD4 FG_ALPHA_FUNC
6220x4BD8 FG_DEPTH_SRC
6230x4C00 US_ALU_CONST_R_0
6240x4C04 US_ALU_CONST_G_0
6250x4C08 US_ALU_CONST_B_0
6260x4C0C US_ALU_CONST_A_0
6270x4C10 US_ALU_CONST_R_1
6280x4C14 US_ALU_CONST_G_1
6290x4C18 US_ALU_CONST_B_1
6300x4C1C US_ALU_CONST_A_1
6310x4C20 US_ALU_CONST_R_2
6320x4C24 US_ALU_CONST_G_2
6330x4C28 US_ALU_CONST_B_2
6340x4C2C US_ALU_CONST_A_2
6350x4C30 US_ALU_CONST_R_3
6360x4C34 US_ALU_CONST_G_3
6370x4C38 US_ALU_CONST_B_3
6380x4C3C US_ALU_CONST_A_3
6390x4C40 US_ALU_CONST_R_4
6400x4C44 US_ALU_CONST_G_4
6410x4C48 US_ALU_CONST_B_4
6420x4C4C US_ALU_CONST_A_4
6430x4C50 US_ALU_CONST_R_5
6440x4C54 US_ALU_CONST_G_5
6450x4C58 US_ALU_CONST_B_5
6460x4C5C US_ALU_CONST_A_5
6470x4C60 US_ALU_CONST_R_6
6480x4C64 US_ALU_CONST_G_6
6490x4C68 US_ALU_CONST_B_6
6500x4C6C US_ALU_CONST_A_6
6510x4C70 US_ALU_CONST_R_7
6520x4C74 US_ALU_CONST_G_7
6530x4C78 US_ALU_CONST_B_7
6540x4C7C US_ALU_CONST_A_7
6550x4C80 US_ALU_CONST_R_8
6560x4C84 US_ALU_CONST_G_8
6570x4C88 US_ALU_CONST_B_8
6580x4C8C US_ALU_CONST_A_8
6590x4C90 US_ALU_CONST_R_9
6600x4C94 US_ALU_CONST_G_9
6610x4C98 US_ALU_CONST_B_9
6620x4C9C US_ALU_CONST_A_9
6630x4CA0 US_ALU_CONST_R_10
6640x4CA4 US_ALU_CONST_G_10
6650x4CA8 US_ALU_CONST_B_10
6660x4CAC US_ALU_CONST_A_10
6670x4CB0 US_ALU_CONST_R_11
6680x4CB4 US_ALU_CONST_G_11
6690x4CB8 US_ALU_CONST_B_11
6700x4CBC US_ALU_CONST_A_11
6710x4CC0 US_ALU_CONST_R_12
6720x4CC4 US_ALU_CONST_G_12
6730x4CC8 US_ALU_CONST_B_12
6740x4CCC US_ALU_CONST_A_12
6750x4CD0 US_ALU_CONST_R_13
6760x4CD4 US_ALU_CONST_G_13
6770x4CD8 US_ALU_CONST_B_13
6780x4CDC US_ALU_CONST_A_13
6790x4CE0 US_ALU_CONST_R_14
6800x4CE4 US_ALU_CONST_G_14
6810x4CE8 US_ALU_CONST_B_14
6820x4CEC US_ALU_CONST_A_14
6830x4CF0 US_ALU_CONST_R_15
6840x4CF4 US_ALU_CONST_G_15
6850x4CF8 US_ALU_CONST_B_15
6860x4CFC US_ALU_CONST_A_15
6870x4D00 US_ALU_CONST_R_16
6880x4D04 US_ALU_CONST_G_16
6890x4D08 US_ALU_CONST_B_16
6900x4D0C US_ALU_CONST_A_16
6910x4D10 US_ALU_CONST_R_17
6920x4D14 US_ALU_CONST_G_17
6930x4D18 US_ALU_CONST_B_17
6940x4D1C US_ALU_CONST_A_17
6950x4D20 US_ALU_CONST_R_18
6960x4D24 US_ALU_CONST_G_18
6970x4D28 US_ALU_CONST_B_18
6980x4D2C US_ALU_CONST_A_18
6990x4D30 US_ALU_CONST_R_19
7000x4D34 US_ALU_CONST_G_19
7010x4D38 US_ALU_CONST_B_19
7020x4D3C US_ALU_CONST_A_19
7030x4D40 US_ALU_CONST_R_20
7040x4D44 US_ALU_CONST_G_20
7050x4D48 US_ALU_CONST_B_20
7060x4D4C US_ALU_CONST_A_20
7070x4D50 US_ALU_CONST_R_21
7080x4D54 US_ALU_CONST_G_21
7090x4D58 US_ALU_CONST_B_21
7100x4D5C US_ALU_CONST_A_21
7110x4D60 US_ALU_CONST_R_22
7120x4D64 US_ALU_CONST_G_22
7130x4D68 US_ALU_CONST_B_22
7140x4D6C US_ALU_CONST_A_22
7150x4D70 US_ALU_CONST_R_23
7160x4D74 US_ALU_CONST_G_23
7170x4D78 US_ALU_CONST_B_23
7180x4D7C US_ALU_CONST_A_23
7190x4D80 US_ALU_CONST_R_24
7200x4D84 US_ALU_CONST_G_24
7210x4D88 US_ALU_CONST_B_24
7220x4D8C US_ALU_CONST_A_24
7230x4D90 US_ALU_CONST_R_25
7240x4D94 US_ALU_CONST_G_25
7250x4D98 US_ALU_CONST_B_25
7260x4D9C US_ALU_CONST_A_25
7270x4DA0 US_ALU_CONST_R_26
7280x4DA4 US_ALU_CONST_G_26
7290x4DA8 US_ALU_CONST_B_26
7300x4DAC US_ALU_CONST_A_26
7310x4DB0 US_ALU_CONST_R_27
7320x4DB4 US_ALU_CONST_G_27
7330x4DB8 US_ALU_CONST_B_27
7340x4DBC US_ALU_CONST_A_27
7350x4DC0 US_ALU_CONST_R_28
7360x4DC4 US_ALU_CONST_G_28
7370x4DC8 US_ALU_CONST_B_28
7380x4DCC US_ALU_CONST_A_28
7390x4DD0 US_ALU_CONST_R_29
7400x4DD4 US_ALU_CONST_G_29
7410x4DD8 US_ALU_CONST_B_29
7420x4DDC US_ALU_CONST_A_29
7430x4DE0 US_ALU_CONST_R_30
7440x4DE4 US_ALU_CONST_G_30
7450x4DE8 US_ALU_CONST_B_30
7460x4DEC US_ALU_CONST_A_30
7470x4DF0 US_ALU_CONST_R_31
7480x4DF4 US_ALU_CONST_G_31
7490x4DF8 US_ALU_CONST_B_31
7500x4DFC US_ALU_CONST_A_31
7510x4E04 RB3D_BLENDCNTL_R3
7520x4E08 RB3D_ABLENDCNTL_R3
7530x4E0C RB3D_COLOR_CHANNEL_MASK
7540x4E10 RB3D_CONSTANT_COLOR
7550x4E14 RB3D_COLOR_CLEAR_VALUE
7560x4E18 RB3D_ROPCNTL_R3
7570x4E1C RB3D_CLRCMP_FLIPE_R3
7580x4E20 RB3D_CLRCMP_CLR_R3
7590x4E24 RB3D_CLRCMP_MSK_R3
7600x4E48 RB3D_DEBUG_CTL
7610x4E4C RB3D_DSTCACHE_CTLSTAT_R3
7620x4E50 RB3D_DITHER_CTL
7630x4E54 RB3D_CMASK_OFFSET0
7640x4E58 RB3D_CMASK_OFFSET1
7650x4E5C RB3D_CMASK_OFFSET2
7660x4E60 RB3D_CMASK_OFFSET3
7670x4E64 RB3D_CMASK_PITCH0
7680x4E68 RB3D_CMASK_PITCH1
7690x4E6C RB3D_CMASK_PITCH2
7700x4E70 RB3D_CMASK_PITCH3
7710x4E74 RB3D_CMASK_WRINDEX
7720x4E78 RB3D_CMASK_DWORD
7730x4E7C RB3D_CMASK_RDINDEX
7740x4E80 RB3D_AARESOLVE_OFFSET
7750x4E84 RB3D_AARESOLVE_PITCH
7760x4E88 RB3D_AARESOLVE_CTL
7770x4EA0 RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD
7780x4EA4 RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD
7790x4F04 ZB_ZSTENCILCNTL
7800x4F08 ZB_STENCILREFMASK
7810x4F14 ZB_ZTOP
7820x4F18 ZB_ZCACHE_CTLSTAT
7830x4F1C ZB_BW_CNTL
7840x4F28 ZB_DEPTHCLEARVALUE
7850x4F30 ZB_ZMASK_OFFSET
7860x4F34 ZB_ZMASK_PITCH
7870x4F38 ZB_ZMASK_WRINDEX
7880x4F3C ZB_ZMASK_DWORD
7890x4F40 ZB_ZMASK_RDINDEX
7900x4F44 ZB_HIZ_OFFSET
7910x4F48 ZB_HIZ_WRINDEX
7920x4F4C ZB_HIZ_DWORD
7930x4F50 ZB_HIZ_RDINDEX
7940x4F54 ZB_HIZ_PITCH
7950x4F58 ZB_ZPASS_DATA
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rs600 b/drivers/gpu/drm/radeon/reg_srcs/rs600
index 8e3c0b807ad..6801b865d1c 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rs600
+++ b/drivers/gpu/drm/radeon/reg_srcs/rs600
@@ -153,7 +153,7 @@ rs600 0x6d40
1530x42A4 SU_POLY_OFFSET_FRONT_SCALE 1530x42A4 SU_POLY_OFFSET_FRONT_SCALE
1540x42A8 SU_POLY_OFFSET_FRONT_OFFSET 1540x42A8 SU_POLY_OFFSET_FRONT_OFFSET
1550x42AC SU_POLY_OFFSET_BACK_SCALE 1550x42AC SU_POLY_OFFSET_BACK_SCALE
1560x42B0 SU_POLY_OFFSET_BACK_OFFSET 1560x42B0 SU_POLY_OFFSET_BACK_OFFSET
1570x42B4 SU_POLY_OFFSET_ENABLE 1570x42B4 SU_POLY_OFFSET_ENABLE
1580x42B8 SU_CULL_MODE 1580x42B8 SU_CULL_MODE
1590x42C0 SU_DEPTH_SCALE 1590x42C0 SU_DEPTH_SCALE
@@ -291,6 +291,8 @@ rs600 0x6d40
2910x46AC US_OUT_FMT_2 2910x46AC US_OUT_FMT_2
2920x46B0 US_OUT_FMT_3 2920x46B0 US_OUT_FMT_3
2930x46B4 US_W_FMT 2930x46B4 US_W_FMT
2940x46B8 US_CODE_BANK
2950x46BC US_CODE_EXT
2940x46C0 US_ALU_RGB_ADDR_0 2960x46C0 US_ALU_RGB_ADDR_0
2950x46C4 US_ALU_RGB_ADDR_1 2970x46C4 US_ALU_RGB_ADDR_1
2960x46C8 US_ALU_RGB_ADDR_2 2980x46C8 US_ALU_RGB_ADDR_2
@@ -547,6 +549,70 @@ rs600 0x6d40
5470x4AB4 US_ALU_ALPHA_INST_61 5490x4AB4 US_ALU_ALPHA_INST_61
5480x4AB8 US_ALU_ALPHA_INST_62 5500x4AB8 US_ALU_ALPHA_INST_62
5490x4ABC US_ALU_ALPHA_INST_63 5510x4ABC US_ALU_ALPHA_INST_63
5520x4AC0 US_ALU_EXT_ADDR_0
5530x4AC4 US_ALU_EXT_ADDR_1
5540x4AC8 US_ALU_EXT_ADDR_2
5550x4ACC US_ALU_EXT_ADDR_3
5560x4AD0 US_ALU_EXT_ADDR_4
5570x4AD4 US_ALU_EXT_ADDR_5
5580x4AD8 US_ALU_EXT_ADDR_6
5590x4ADC US_ALU_EXT_ADDR_7
5600x4AE0 US_ALU_EXT_ADDR_8
5610x4AE4 US_ALU_EXT_ADDR_9
5620x4AE8 US_ALU_EXT_ADDR_10
5630x4AEC US_ALU_EXT_ADDR_11
5640x4AF0 US_ALU_EXT_ADDR_12
5650x4AF4 US_ALU_EXT_ADDR_13
5660x4AF8 US_ALU_EXT_ADDR_14
5670x4AFC US_ALU_EXT_ADDR_15
5680x4B00 US_ALU_EXT_ADDR_16
5690x4B04 US_ALU_EXT_ADDR_17
5700x4B08 US_ALU_EXT_ADDR_18
5710x4B0C US_ALU_EXT_ADDR_19
5720x4B10 US_ALU_EXT_ADDR_20
5730x4B14 US_ALU_EXT_ADDR_21
5740x4B18 US_ALU_EXT_ADDR_22
5750x4B1C US_ALU_EXT_ADDR_23
5760x4B20 US_ALU_EXT_ADDR_24
5770x4B24 US_ALU_EXT_ADDR_25
5780x4B28 US_ALU_EXT_ADDR_26
5790x4B2C US_ALU_EXT_ADDR_27
5800x4B30 US_ALU_EXT_ADDR_28
5810x4B34 US_ALU_EXT_ADDR_29
5820x4B38 US_ALU_EXT_ADDR_30
5830x4B3C US_ALU_EXT_ADDR_31
5840x4B40 US_ALU_EXT_ADDR_32
5850x4B44 US_ALU_EXT_ADDR_33
5860x4B48 US_ALU_EXT_ADDR_34
5870x4B4C US_ALU_EXT_ADDR_35
5880x4B50 US_ALU_EXT_ADDR_36
5890x4B54 US_ALU_EXT_ADDR_37
5900x4B58 US_ALU_EXT_ADDR_38
5910x4B5C US_ALU_EXT_ADDR_39
5920x4B60 US_ALU_EXT_ADDR_40
5930x4B64 US_ALU_EXT_ADDR_41
5940x4B68 US_ALU_EXT_ADDR_42
5950x4B6C US_ALU_EXT_ADDR_43
5960x4B70 US_ALU_EXT_ADDR_44
5970x4B74 US_ALU_EXT_ADDR_45
5980x4B78 US_ALU_EXT_ADDR_46
5990x4B7C US_ALU_EXT_ADDR_47
6000x4B80 US_ALU_EXT_ADDR_48
6010x4B84 US_ALU_EXT_ADDR_49
6020x4B88 US_ALU_EXT_ADDR_50
6030x4B8C US_ALU_EXT_ADDR_51
6040x4B90 US_ALU_EXT_ADDR_52
6050x4B94 US_ALU_EXT_ADDR_53
6060x4B98 US_ALU_EXT_ADDR_54
6070x4B9C US_ALU_EXT_ADDR_55
6080x4BA0 US_ALU_EXT_ADDR_56
6090x4BA4 US_ALU_EXT_ADDR_57
6100x4BA8 US_ALU_EXT_ADDR_58
6110x4BAC US_ALU_EXT_ADDR_59
6120x4BB0 US_ALU_EXT_ADDR_60
6130x4BB4 US_ALU_EXT_ADDR_61
6140x4BB8 US_ALU_EXT_ADDR_62
6150x4BBC US_ALU_EXT_ADDR_63
5500x4BC0 FG_FOG_BLEND 6160x4BC0 FG_FOG_BLEND
5510x4BC4 FG_FOG_FACTOR 6170x4BC4 FG_FOG_FACTOR
5520x4BC8 FG_FOG_COLOR_R 6180x4BC8 FG_FOG_COLOR_R
diff --git a/drivers/gpu/drm/radeon/reg_srcs/rv515 b/drivers/gpu/drm/radeon/reg_srcs/rv515
index 0102a0d5735..38abf63bf2c 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/rv515
+++ b/drivers/gpu/drm/radeon/reg_srcs/rv515
@@ -161,7 +161,12 @@ rv515 0x6d40
1610x401C GB_SELECT 1610x401C GB_SELECT
1620x4020 GB_AA_CONFIG 1620x4020 GB_AA_CONFIG
1630x4024 GB_FIFO_SIZE 1630x4024 GB_FIFO_SIZE
1640x4028 GB_Z_PEQ_CONFIG
1640x4100 TX_INVALTAGS 1650x4100 TX_INVALTAGS
1660x4114 SU_TEX_WRAP_PS3
1670x4118 PS3_ENABLE
1680x411c PS3_VTX_FMT
1690x4120 PS3_TEX_SOURCE
1650x4200 GA_POINT_S0 1700x4200 GA_POINT_S0
1660x4204 GA_POINT_T0 1710x4204 GA_POINT_T0
1670x4208 GA_POINT_S1 1720x4208 GA_POINT_S1
@@ -171,6 +176,7 @@ rv515 0x6d40
1710x4230 GA_POINT_MINMAX 1760x4230 GA_POINT_MINMAX
1720x4234 GA_LINE_CNTL 1770x4234 GA_LINE_CNTL
1730x4238 GA_LINE_STIPPLE_CONFIG 1780x4238 GA_LINE_STIPPLE_CONFIG
1790x4258 GA_COLOR_CONTROL_PS3
1740x4260 GA_LINE_STIPPLE_VALUE 1800x4260 GA_LINE_STIPPLE_VALUE
1750x4264 GA_LINE_S0 1810x4264 GA_LINE_S0
1760x4268 GA_LINE_S1 1820x4268 GA_LINE_S1
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 368415df5f3..287fcebfb4e 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -223,15 +223,31 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
223 return 0; 223 return 0;
224} 224}
225 225
226int rs400_mc_wait_for_idle(struct radeon_device *rdev)
227{
228 unsigned i;
229 uint32_t tmp;
230
231 for (i = 0; i < rdev->usec_timeout; i++) {
232 /* read MC_STATUS */
233 tmp = RREG32(0x0150);
234 if (tmp & (1 << 2)) {
235 return 0;
236 }
237 DRM_UDELAY(1);
238 }
239 return -1;
240}
241
226void rs400_gpu_init(struct radeon_device *rdev) 242void rs400_gpu_init(struct radeon_device *rdev)
227{ 243{
228 /* FIXME: HDP same place on rs400 ? */ 244 /* FIXME: HDP same place on rs400 ? */
229 r100_hdp_reset(rdev); 245 r100_hdp_reset(rdev);
230 /* FIXME: is this correct ? */ 246 /* FIXME: is this correct ? */
231 r420_pipes_init(rdev); 247 r420_pipes_init(rdev);
232 if (r300_mc_wait_for_idle(rdev)) { 248 if (rs400_mc_wait_for_idle(rdev)) {
233 printk(KERN_WARNING "Failed to wait MC idle while " 249 printk(KERN_WARNING "rs400: Failed to wait MC idle while "
234 "programming pipes. Bad things might happen.\n"); 250 "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
235 } 251 }
236} 252}
237 253
@@ -356,6 +372,7 @@ static int rs400_mc_init(struct radeon_device *rdev)
356 rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16; 372 rdev->mc.vram_location = G_00015C_MC_FB_START(tmp) << 16;
357 rdev->mc.gtt_location = 0xFFFFFFFFUL; 373 rdev->mc.gtt_location = 0xFFFFFFFFUL;
358 r = radeon_mc_setup(rdev); 374 r = radeon_mc_setup(rdev);
375 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);
359 if (r) 376 if (r)
360 return r; 377 return r;
361 return 0; 378 return 0;
@@ -369,8 +386,8 @@ void rs400_mc_program(struct radeon_device *rdev)
369 r100_mc_stop(rdev, &save); 386 r100_mc_stop(rdev, &save);
370 387
371 /* Wait for mc idle */ 388 /* Wait for mc idle */
372 if (r300_mc_wait_for_idle(rdev)) 389 if (rs400_mc_wait_for_idle(rdev))
373 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); 390 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n");
374 WREG32(R_000148_MC_FB_LOCATION, 391 WREG32(R_000148_MC_FB_LOCATION,
375 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | 392 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
376 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); 393 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
@@ -395,6 +412,7 @@ static int rs400_startup(struct radeon_device *rdev)
395 return r; 412 return r;
396 /* Enable IRQ */ 413 /* Enable IRQ */
397 r100_irq_set(rdev); 414 r100_irq_set(rdev);
415 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
398 /* 1M ring buffer */ 416 /* 1M ring buffer */
399 r = r100_cp_init(rdev, 1024 * 1024); 417 r = r100_cp_init(rdev, 1024 * 1024);
400 if (r) { 418 if (r) {
@@ -446,7 +464,6 @@ int rs400_suspend(struct radeon_device *rdev)
446 464
447void rs400_fini(struct radeon_device *rdev) 465void rs400_fini(struct radeon_device *rdev)
448{ 466{
449 rs400_suspend(rdev);
450 r100_cp_fini(rdev); 467 r100_cp_fini(rdev);
451 r100_wb_fini(rdev); 468 r100_wb_fini(rdev);
452 r100_ib_fini(rdev); 469 r100_ib_fini(rdev);
@@ -525,7 +542,6 @@ int rs400_init(struct radeon_device *rdev)
525 if (r) { 542 if (r) {
526 /* Somethings want wront with the accel init stop accel */ 543 /* Somethings want wront with the accel init stop accel */
527 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 544 dev_err(rdev->dev, "Disabling GPU acceleration\n");
528 rs400_suspend(rdev);
529 r100_cp_fini(rdev); 545 r100_cp_fini(rdev);
530 r100_wb_fini(rdev); 546 r100_wb_fini(rdev);
531 r100_ib_fini(rdev); 547 r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 4245218e954..c3818562a13 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -56,6 +56,7 @@ int rs600_mc_init(struct radeon_device *rdev)
56 rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16; 56 rdev->mc.vram_location = G_000004_MC_FB_START(tmp) << 16;
57 rdev->mc.gtt_location = 0xffffffffUL; 57 rdev->mc.gtt_location = 0xffffffffUL;
58 r = radeon_mc_setup(rdev); 58 r = radeon_mc_setup(rdev);
59 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
59 if (r) 60 if (r)
60 return r; 61 return r;
61 return 0; 62 return 0;
@@ -134,7 +135,8 @@ void rs600_hpd_init(struct radeon_device *rdev)
134 break; 135 break;
135 } 136 }
136 } 137 }
137 rs600_irq_set(rdev); 138 if (rdev->irq.installed)
139 rs600_irq_set(rdev);
138} 140}
139 141
140void rs600_hpd_fini(struct radeon_device *rdev) 142void rs600_hpd_fini(struct radeon_device *rdev)
@@ -315,6 +317,11 @@ int rs600_irq_set(struct radeon_device *rdev)
315 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) & 317 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
316 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1); 318 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
317 319
320 if (!rdev->irq.installed) {
321 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
322 WREG32(R_000040_GEN_INT_CNTL, 0);
323 return -EINVAL;
324 }
318 if (rdev->irq.sw_int) { 325 if (rdev->irq.sw_int) {
319 tmp |= S_000040_SW_INT_EN(1); 326 tmp |= S_000040_SW_INT_EN(1);
320 } 327 }
@@ -553,6 +560,7 @@ static int rs600_startup(struct radeon_device *rdev)
553 return r; 560 return r;
554 /* Enable IRQ */ 561 /* Enable IRQ */
555 rs600_irq_set(rdev); 562 rs600_irq_set(rdev);
563 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
556 /* 1M ring buffer */ 564 /* 1M ring buffer */
557 r = r100_cp_init(rdev, 1024 * 1024); 565 r = r100_cp_init(rdev, 1024 * 1024);
558 if (r) { 566 if (r) {
@@ -602,7 +610,6 @@ int rs600_suspend(struct radeon_device *rdev)
602 610
603void rs600_fini(struct radeon_device *rdev) 611void rs600_fini(struct radeon_device *rdev)
604{ 612{
605 rs600_suspend(rdev);
606 r100_cp_fini(rdev); 613 r100_cp_fini(rdev);
607 r100_wb_fini(rdev); 614 r100_wb_fini(rdev);
608 r100_ib_fini(rdev); 615 r100_ib_fini(rdev);
@@ -681,7 +688,6 @@ int rs600_init(struct radeon_device *rdev)
681 if (r) { 688 if (r) {
682 /* Somethings want wront with the accel init stop accel */ 689 /* Somethings want wront with the accel init stop accel */
683 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 690 dev_err(rdev->dev, "Disabling GPU acceleration\n");
684 rs600_suspend(rdev);
685 r100_cp_fini(rdev); 691 r100_cp_fini(rdev);
686 r100_wb_fini(rdev); 692 r100_wb_fini(rdev);
687 r100_ib_fini(rdev); 693 r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index 1e22f52d603..06e2771aee5 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -172,6 +172,7 @@ static int rs690_mc_init(struct radeon_device *rdev)
172 rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16; 172 rdev->mc.vram_location = G_000100_MC_FB_START(tmp) << 16;
173 rdev->mc.gtt_location = 0xFFFFFFFFUL; 173 rdev->mc.gtt_location = 0xFFFFFFFFUL;
174 r = radeon_mc_setup(rdev); 174 r = radeon_mc_setup(rdev);
175 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
175 if (r) 176 if (r)
176 return r; 177 return r;
177 return 0; 178 return 0;
@@ -625,6 +626,7 @@ static int rs690_startup(struct radeon_device *rdev)
625 return r; 626 return r;
626 /* Enable IRQ */ 627 /* Enable IRQ */
627 rs600_irq_set(rdev); 628 rs600_irq_set(rdev);
629 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
628 /* 1M ring buffer */ 630 /* 1M ring buffer */
629 r = r100_cp_init(rdev, 1024 * 1024); 631 r = r100_cp_init(rdev, 1024 * 1024);
630 if (r) { 632 if (r) {
@@ -674,7 +676,6 @@ int rs690_suspend(struct radeon_device *rdev)
674 676
675void rs690_fini(struct radeon_device *rdev) 677void rs690_fini(struct radeon_device *rdev)
676{ 678{
677 rs690_suspend(rdev);
678 r100_cp_fini(rdev); 679 r100_cp_fini(rdev);
679 r100_wb_fini(rdev); 680 r100_wb_fini(rdev);
680 r100_ib_fini(rdev); 681 r100_ib_fini(rdev);
@@ -754,7 +755,6 @@ int rs690_init(struct radeon_device *rdev)
754 if (r) { 755 if (r) {
755 /* Somethings want wront with the accel init stop accel */ 756 /* Somethings want wront with the accel init stop accel */
756 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 757 dev_err(rdev->dev, "Disabling GPU acceleration\n");
757 rs690_suspend(rdev);
758 r100_cp_fini(rdev); 758 r100_cp_fini(rdev);
759 r100_wb_fini(rdev); 759 r100_wb_fini(rdev);
760 r100_ib_fini(rdev); 760 r100_ib_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 59632a506b4..0e1e6b8632b 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -479,6 +479,7 @@ static int rv515_startup(struct radeon_device *rdev)
479 } 479 }
480 /* Enable IRQ */ 480 /* Enable IRQ */
481 rs600_irq_set(rdev); 481 rs600_irq_set(rdev);
482 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
482 /* 1M ring buffer */ 483 /* 1M ring buffer */
483 r = r100_cp_init(rdev, 1024 * 1024); 484 r = r100_cp_init(rdev, 1024 * 1024);
484 if (r) { 485 if (r) {
@@ -536,7 +537,6 @@ void rv515_set_safe_registers(struct radeon_device *rdev)
536 537
537void rv515_fini(struct radeon_device *rdev) 538void rv515_fini(struct radeon_device *rdev)
538{ 539{
539 rv515_suspend(rdev);
540 r100_cp_fini(rdev); 540 r100_cp_fini(rdev);
541 r100_wb_fini(rdev); 541 r100_wb_fini(rdev);
542 r100_ib_fini(rdev); 542 r100_ib_fini(rdev);
@@ -614,13 +614,12 @@ int rv515_init(struct radeon_device *rdev)
614 if (r) { 614 if (r) {
615 /* Somethings want wront with the accel init stop accel */ 615 /* Somethings want wront with the accel init stop accel */
616 dev_err(rdev->dev, "Disabling GPU acceleration\n"); 616 dev_err(rdev->dev, "Disabling GPU acceleration\n");
617 rv515_suspend(rdev);
618 r100_cp_fini(rdev); 617 r100_cp_fini(rdev);
619 r100_wb_fini(rdev); 618 r100_wb_fini(rdev);
620 r100_ib_fini(rdev); 619 r100_ib_fini(rdev);
620 radeon_irq_kms_fini(rdev);
621 rv370_pcie_gart_fini(rdev); 621 rv370_pcie_gart_fini(rdev);
622 radeon_agp_fini(rdev); 622 radeon_agp_fini(rdev);
623 radeon_irq_kms_fini(rdev);
624 rdev->accel_working = false; 623 rdev->accel_working = false;
625 } 624 }
626 return 0; 625 return 0;
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 3bcb66e5278..5943d561fd1 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -779,7 +779,6 @@ int rv770_mc_init(struct radeon_device *rdev)
779 fixed20_12 a; 779 fixed20_12 a;
780 u32 tmp; 780 u32 tmp;
781 int chansize, numchan; 781 int chansize, numchan;
782 int r;
783 782
784 /* Get VRAM informations */ 783 /* Get VRAM informations */
785 rdev->mc.vram_is_ddr = true; 784 rdev->mc.vram_is_ddr = true;
@@ -822,9 +821,6 @@ int rv770_mc_init(struct radeon_device *rdev)
822 rdev->mc.real_vram_size = rdev->mc.aper_size; 821 rdev->mc.real_vram_size = rdev->mc.aper_size;
823 822
824 if (rdev->flags & RADEON_IS_AGP) { 823 if (rdev->flags & RADEON_IS_AGP) {
825 r = radeon_agp_init(rdev);
826 if (r)
827 return r;
828 /* gtt_size is setup by radeon_agp_init */ 824 /* gtt_size is setup by radeon_agp_init */
829 rdev->mc.gtt_location = rdev->mc.agp_base; 825 rdev->mc.gtt_location = rdev->mc.agp_base;
830 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; 826 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
@@ -891,26 +887,25 @@ static int rv770_startup(struct radeon_device *rdev)
891 return r; 887 return r;
892 } 888 }
893 rv770_gpu_init(rdev); 889 rv770_gpu_init(rdev);
894 890 r = r600_blit_init(rdev);
895 if (!rdev->r600_blit.shader_obj) { 891 if (r) {
896 r = r600_blit_init(rdev); 892 r600_blit_fini(rdev);
893 rdev->asic->copy = NULL;
894 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
895 }
896 /* pin copy shader into vram */
897 if (rdev->r600_blit.shader_obj) {
898 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
899 if (unlikely(r != 0))
900 return r;
901 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
902 &rdev->r600_blit.shader_gpu_addr);
903 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
897 if (r) { 904 if (r) {
898 DRM_ERROR("radeon: failed blitter (%d).\n", r); 905 DRM_ERROR("failed to pin blit object %d\n", r);
899 return r; 906 return r;
900 } 907 }
901 } 908 }
902
903 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
904 if (unlikely(r != 0))
905 return r;
906 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
907 &rdev->r600_blit.shader_gpu_addr);
908 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
909 if (r) {
910 DRM_ERROR("failed to pin blit object %d\n", r);
911 return r;
912 }
913
914 /* Enable IRQ */ 909 /* Enable IRQ */
915 r = r600_irq_init(rdev); 910 r = r600_irq_init(rdev);
916 if (r) { 911 if (r) {
@@ -972,13 +967,16 @@ int rv770_suspend(struct radeon_device *rdev)
972 /* FIXME: we should wait for ring to be empty */ 967 /* FIXME: we should wait for ring to be empty */
973 r700_cp_stop(rdev); 968 r700_cp_stop(rdev);
974 rdev->cp.ready = false; 969 rdev->cp.ready = false;
970 r600_irq_suspend(rdev);
975 r600_wb_disable(rdev); 971 r600_wb_disable(rdev);
976 rv770_pcie_gart_disable(rdev); 972 rv770_pcie_gart_disable(rdev);
977 /* unpin shaders bo */ 973 /* unpin shaders bo */
978 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 974 if (rdev->r600_blit.shader_obj) {
979 if (likely(r == 0)) { 975 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
980 radeon_bo_unpin(rdev->r600_blit.shader_obj); 976 if (likely(r == 0)) {
981 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 977 radeon_bo_unpin(rdev->r600_blit.shader_obj);
978 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
979 }
982 } 980 }
983 return 0; 981 return 0;
984} 982}
@@ -1037,6 +1035,11 @@ int rv770_init(struct radeon_device *rdev)
1037 r = radeon_fence_driver_init(rdev); 1035 r = radeon_fence_driver_init(rdev);
1038 if (r) 1036 if (r)
1039 return r; 1037 return r;
1038 if (rdev->flags & RADEON_IS_AGP) {
1039 r = radeon_agp_init(rdev);
1040 if (r)
1041 radeon_agp_disable(rdev);
1042 }
1040 r = rv770_mc_init(rdev); 1043 r = rv770_mc_init(rdev);
1041 if (r) 1044 if (r)
1042 return r; 1045 return r;
@@ -1062,22 +1065,25 @@ int rv770_init(struct radeon_device *rdev)
1062 rdev->accel_working = true; 1065 rdev->accel_working = true;
1063 r = rv770_startup(rdev); 1066 r = rv770_startup(rdev);
1064 if (r) { 1067 if (r) {
1065 rv770_suspend(rdev); 1068 dev_err(rdev->dev, "disabling GPU acceleration\n");
1069 r600_cp_fini(rdev);
1066 r600_wb_fini(rdev); 1070 r600_wb_fini(rdev);
1067 radeon_ring_fini(rdev); 1071 r600_irq_fini(rdev);
1072 radeon_irq_kms_fini(rdev);
1068 rv770_pcie_gart_fini(rdev); 1073 rv770_pcie_gart_fini(rdev);
1069 rdev->accel_working = false; 1074 rdev->accel_working = false;
1070 } 1075 }
1071 if (rdev->accel_working) { 1076 if (rdev->accel_working) {
1072 r = radeon_ib_pool_init(rdev); 1077 r = radeon_ib_pool_init(rdev);
1073 if (r) { 1078 if (r) {
1074 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 1079 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1075 rdev->accel_working = false;
1076 }
1077 r = r600_ib_test(rdev);
1078 if (r) {
1079 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1080 rdev->accel_working = false; 1080 rdev->accel_working = false;
1081 } else {
1082 r = r600_ib_test(rdev);
1083 if (r) {
1084 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1085 rdev->accel_working = false;
1086 }
1081 } 1087 }
1082 } 1088 }
1083 return 0; 1089 return 0;
@@ -1085,19 +1091,16 @@ int rv770_init(struct radeon_device *rdev)
1085 1091
1086void rv770_fini(struct radeon_device *rdev) 1092void rv770_fini(struct radeon_device *rdev)
1087{ 1093{
1088 rv770_suspend(rdev);
1089
1090 r600_blit_fini(rdev); 1094 r600_blit_fini(rdev);
1095 r600_cp_fini(rdev);
1096 r600_wb_fini(rdev);
1091 r600_irq_fini(rdev); 1097 r600_irq_fini(rdev);
1092 radeon_irq_kms_fini(rdev); 1098 radeon_irq_kms_fini(rdev);
1093 radeon_ring_fini(rdev);
1094 r600_wb_fini(rdev);
1095 rv770_pcie_gart_fini(rdev); 1099 rv770_pcie_gart_fini(rdev);
1096 radeon_gem_fini(rdev); 1100 radeon_gem_fini(rdev);
1097 radeon_fence_driver_fini(rdev); 1101 radeon_fence_driver_fini(rdev);
1098 radeon_clocks_fini(rdev); 1102 radeon_clocks_fini(rdev);
1099 if (rdev->flags & RADEON_IS_AGP) 1103 radeon_agp_fini(rdev);
1100 radeon_agp_fini(rdev);
1101 radeon_bo_fini(rdev); 1104 radeon_bo_fini(rdev);
1102 radeon_atombios_fini(rdev); 1105 radeon_atombios_fini(rdev);
1103 kfree(rdev->bios); 1106 kfree(rdev->bios);
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 22:55:48 -0500