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path: root/drivers/gpu/drm/radeon/si.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/si.c')
-rw-r--r--drivers/gpu/drm/radeon/si.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 2a5c337715d..156c9941e6c 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2426,7 +2426,7 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
2426 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, 2426 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
2427 (u32)(rdev->dummy_page.addr >> 12)); 2427 (u32)(rdev->dummy_page.addr >> 12));
2428 WREG32(VM_CONTEXT1_CNTL2, 0); 2428 WREG32(VM_CONTEXT1_CNTL2, 0);
2429 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | 2429 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
2430 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 2430 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
2431 2431
2432 si_pcie_gart_tlb_flush(rdev); 2432 si_pcie_gart_tlb_flush(rdev);
@@ -2804,7 +2804,7 @@ void si_vm_flush(struct radeon_device *rdev, struct radeon_ib *ib)
2804 radeon_ring_write(ring, PACKET0(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 2804 radeon_ring_write(ring, PACKET0(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR
2805 + ((vm->id - 8) << 2), 0)); 2805 + ((vm->id - 8) << 2), 0));
2806 } 2806 }
2807 radeon_ring_write(ring, vm->pt_gpu_addr >> 12); 2807 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2808 2808
2809 /* flush hdp cache */ 2809 /* flush hdp cache */
2810 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); 2810 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));