1 files changed, 32 insertions, 22 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index f79633a036c..b0db712060f 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2407,12 +2407,13 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
         WREG32(0x15DC, 0);
 
         /* empty context1-15 */
-        /* FIXME start with 4G, once using 2 level pt switch to full
-         * vm size space
-         */
         /* set vm size, must be a multiple of 4 */
         WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
         WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
+        /* Assign the pt base to something valid for now; the pts used for
+         * the VMs are determined by the application and setup and assigned
+         * on the fly in the vm part of radeon_gart.c
+         */
         for (i = 1; i < 16; i++) {
                 if (i < 8)
                         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
@@ -2807,26 +2808,31 @@ void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
 {
         struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
         uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
-        int i;
-        uint64_t value;
 
-        radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 2 + count * 2));
-        radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
-                                 WRITE_DATA_DST_SEL(1)));
-        radeon_ring_write(ring, pe);
-        radeon_ring_write(ring, upper_32_bits(pe));
-        for (i = 0; i < count; ++i) {
-                if (flags & RADEON_VM_PAGE_SYSTEM) {
-                        value = radeon_vm_map_gart(rdev, addr);
-                        value &= 0xFFFFFFFFFFFFF000ULL;
-                } else if (flags & RADEON_VM_PAGE_VALID)
-                        value = addr;
-                else
-                        value = 0;
-                addr += incr;
-                value |= r600_flags;
-                radeon_ring_write(ring, value);
-                radeon_ring_write(ring, upper_32_bits(value));
+        while (count) {
+                unsigned ndw = 2 + count * 2;
+                if (ndw > 0x3FFE)
+                        ndw = 0x3FFE;
+
+                radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw));
+                radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+                                         WRITE_DATA_DST_SEL(1)));
+                radeon_ring_write(ring, pe);
+                radeon_ring_write(ring, upper_32_bits(pe));
+                for (; ndw > 2; ndw -= 2, --count, pe += 8) {
+                        uint64_t value;
+                        if (flags & RADEON_VM_PAGE_SYSTEM) {
+                                value = radeon_vm_map_gart(rdev, addr);
+                                value &= 0xFFFFFFFFFFFFF000ULL;
+                        } else if (flags & RADEON_VM_PAGE_VALID)
+                                value = addr;
+                        else
+                                value = 0;
+                        addr += incr;
+                        value |= r600_flags;
+                        radeon_ring_write(ring, value);
+                        radeon_ring_write(ring, upper_32_bits(value));
+                }
         }
 }
 
@@ -2867,6 +2873,10 @@ void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
         radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
         radeon_ring_write(ring, 0);
         radeon_ring_write(ring, 1 << vm->id);
+
+        /* sync PFP to ME, otherwise we might get invalid PFP reads */
+        radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
+        radeon_ring_write(ring, 0x0);
 }
 
 /*