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path: root/drivers/gpu/drm/radeon/radeon_state.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_state.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c51
1 files changed, 31 insertions, 20 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index ef940a079dc..fa728ec6ed3 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -1556,9 +1556,15 @@ static void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *
1556 buf_priv->age = ++master_priv->sarea_priv->last_dispatch; 1556 buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
1557 1557
1558 /* Emit the vertex buffer age */ 1558 /* Emit the vertex buffer age */
1559 BEGIN_RING(2); 1559 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1560 RADEON_DISPATCH_AGE(buf_priv->age); 1560 BEGIN_RING(3);
1561 ADVANCE_RING(); 1561 R600_DISPATCH_AGE(buf_priv->age);
1562 ADVANCE_RING();
1563 } else {
1564 BEGIN_RING(2);
1565 RADEON_DISPATCH_AGE(buf_priv->age);
1566 ADVANCE_RING();
1567 }
1562 1568
1563 buf->pending = 1; 1569 buf->pending = 1;
1564 buf->used = 0; 1570 buf->used = 0;
@@ -1980,7 +1986,7 @@ static int alloc_surface(drm_radeon_surface_alloc_t *new,
1980 1986
1981 /* find a virtual surface */ 1987 /* find a virtual surface */
1982 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) 1988 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
1983 if (dev_priv->virt_surfaces[i].file_priv == 0) 1989 if (dev_priv->virt_surfaces[i].file_priv == NULL)
1984 break; 1990 break;
1985 if (i == 2 * RADEON_MAX_SURFACES) { 1991 if (i == 2 * RADEON_MAX_SURFACES) {
1986 return -1; 1992 return -1;
@@ -2473,24 +2479,25 @@ static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_fil
2473 2479
2474 buf->used = indirect->end; 2480 buf->used = indirect->end;
2475 2481
2476 /* Wait for the 3D stream to idle before the indirect buffer
2477 * containing 2D acceleration commands is processed.
2478 */
2479 BEGIN_RING(2);
2480
2481 RADEON_WAIT_UNTIL_3D_IDLE();
2482
2483 ADVANCE_RING();
2484
2485 /* Dispatch the indirect buffer full of commands from the 2482 /* Dispatch the indirect buffer full of commands from the
2486 * X server. This is insecure and is thus only available to 2483 * X server. This is insecure and is thus only available to
2487 * privileged clients. 2484 * privileged clients.
2488 */ 2485 */
2489 radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end); 2486 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2490 if (indirect->discard) { 2487 r600_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
2491 radeon_cp_discard_buffer(dev, file_priv->master, buf); 2488 else {
2489 /* Wait for the 3D stream to idle before the indirect buffer
2490 * containing 2D acceleration commands is processed.
2491 */
2492 BEGIN_RING(2);
2493 RADEON_WAIT_UNTIL_3D_IDLE();
2494 ADVANCE_RING();
2495 radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
2492 } 2496 }
2493 2497
2498 if (indirect->discard)
2499 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2500
2494 COMMIT_RING(); 2501 COMMIT_RING();
2495 return 0; 2502 return 0;
2496} 2503}
@@ -3010,14 +3017,14 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
3010 break; 3017 break;
3011 case RADEON_PARAM_LAST_FRAME: 3018 case RADEON_PARAM_LAST_FRAME:
3012 dev_priv->stats.last_frame_reads++; 3019 dev_priv->stats.last_frame_reads++;
3013 value = GET_SCRATCH(0); 3020 value = GET_SCRATCH(dev_priv, 0);
3014 break; 3021 break;
3015 case RADEON_PARAM_LAST_DISPATCH: 3022 case RADEON_PARAM_LAST_DISPATCH:
3016 value = GET_SCRATCH(1); 3023 value = GET_SCRATCH(dev_priv, 1);
3017 break; 3024 break;
3018 case RADEON_PARAM_LAST_CLEAR: 3025 case RADEON_PARAM_LAST_CLEAR:
3019 dev_priv->stats.last_clear_reads++; 3026 dev_priv->stats.last_clear_reads++;
3020 value = GET_SCRATCH(2); 3027 value = GET_SCRATCH(dev_priv, 2);
3021 break; 3028 break;
3022 case RADEON_PARAM_IRQ_NR: 3029 case RADEON_PARAM_IRQ_NR:
3023 value = drm_dev_to_irq(dev); 3030 value = drm_dev_to_irq(dev);
@@ -3052,7 +3059,10 @@ static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_fil
3052 case RADEON_PARAM_SCRATCH_OFFSET: 3059 case RADEON_PARAM_SCRATCH_OFFSET:
3053 if (!dev_priv->writeback_works) 3060 if (!dev_priv->writeback_works)
3054 return -EINVAL; 3061 return -EINVAL;
3055 value = RADEON_SCRATCH_REG_OFFSET; 3062 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3063 value = R600_SCRATCH_REG_OFFSET;
3064 else
3065 value = RADEON_SCRATCH_REG_OFFSET;
3056 break; 3066 break;
3057 case RADEON_PARAM_CARD_TYPE: 3067 case RADEON_PARAM_CARD_TYPE:
3058 if (dev_priv->flags & RADEON_IS_PCIE) 3068 if (dev_priv->flags & RADEON_IS_PCIE)
@@ -3155,6 +3165,7 @@ void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
3155 3165
3156void radeon_driver_lastclose(struct drm_device *dev) 3166void radeon_driver_lastclose(struct drm_device *dev)
3157{ 3167{
3168 radeon_surfaces_release(PCIGART_FILE_PRIV, dev->dev_private);
3158 radeon_do_release(dev); 3169 radeon_do_release(dev);
3159} 3170}
3160 3171