1 files changed, 17 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 342deaccc15..91541e63d58 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -224,7 +224,8 @@ void radeon_bo_unref(struct radeon_bo **bo)
                 *bo = NULL;
 }
 
-int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
+int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
+                             u64 *gpu_addr)
 {
         int r, i;
 
@@ -232,6 +233,7 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
                 bo->pin_count++;
                 if (gpu_addr)
                         *gpu_addr = radeon_bo_gpu_offset(bo);
+                WARN_ON_ONCE(max_offset != 0);
                 return 0;
         }
         radeon_ttm_placement_from_domain(bo, domain);
@@ -239,6 +241,15 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
                 /* force to pin into visible video ram */
                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
         }
+        if (max_offset) {
+                u64 lpfn = max_offset >> PAGE_SHIFT;
+
+                if (!bo->placement.lpfn)
+                        bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
+
+                if (lpfn < bo->placement.lpfn)
+                        bo->placement.lpfn = lpfn;
+        }
         for (i = 0; i < bo->placement.num_placement; i++)
                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
@@ -252,6 +263,11 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
         return r;
 }
 
+int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
+{
+        return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
+}
+
 int radeon_bo_unpin(struct radeon_bo *bo)
 {
         int r, i;