diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_cs.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 0be768be530..9ea13d07cc5 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
@@ -2294,6 +2294,35 @@ static int r600_packet3_check(struct radeon_cs_parser *p, | |||
2294 | ib[idx+4] = upper_32_bits(offset) & 0xff; | 2294 | ib[idx+4] = upper_32_bits(offset) & 0xff; |
2295 | } | 2295 | } |
2296 | break; | 2296 | break; |
2297 | case PACKET3_MEM_WRITE: | ||
2298 | { | ||
2299 | u64 offset; | ||
2300 | |||
2301 | if (pkt->count != 3) { | ||
2302 | DRM_ERROR("bad MEM_WRITE (invalid count)\n"); | ||
2303 | return -EINVAL; | ||
2304 | } | ||
2305 | r = r600_cs_packet_next_reloc(p, &reloc); | ||
2306 | if (r) { | ||
2307 | DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); | ||
2308 | return -EINVAL; | ||
2309 | } | ||
2310 | offset = radeon_get_ib_value(p, idx+0); | ||
2311 | offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; | ||
2312 | if (offset & 0x7) { | ||
2313 | DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n"); | ||
2314 | return -EINVAL; | ||
2315 | } | ||
2316 | if ((offset + 8) > radeon_bo_size(reloc->robj)) { | ||
2317 | DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n", | ||
2318 | offset + 8, radeon_bo_size(reloc->robj)); | ||
2319 | return -EINVAL; | ||
2320 | } | ||
2321 | offset += reloc->lobj.gpu_offset; | ||
2322 | ib[idx+0] = offset; | ||
2323 | ib[idx+1] = upper_32_bits(offset) & 0xff; | ||
2324 | break; | ||
2325 | } | ||
2297 | case PACKET3_COPY_DW: | 2326 | case PACKET3_COPY_DW: |
2298 | if (pkt->count != 4) { | 2327 | if (pkt->count != 4) { |
2299 | DRM_ERROR("bad COPY_DW (invalid count)\n"); | 2328 | DRM_ERROR("bad COPY_DW (invalid count)\n"); |