aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/r600_blit_kms.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_blit_kms.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c13
1 files changed, 2 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index af1c3ca8a4c..2d7d16e14f9 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -403,8 +403,6 @@ set_default_state(struct radeon_device *rdev)
403 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); 403 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
404 radeon_ring_write(rdev, dwords); 404 radeon_ring_write(rdev, dwords);
405 405
406 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
407 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
408 /* SQ config */ 406 /* SQ config */
409 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); 407 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
410 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 408 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
@@ -581,9 +579,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
581 ring_size = num_loops * dwords_per_loop; 579 ring_size = num_loops * dwords_per_loop;
582 /* set default + shaders */ 580 /* set default + shaders */
583 ring_size += 40; /* shaders + def state */ 581 ring_size += 40; /* shaders + def state */
584 ring_size += 7; /* fence emit for VB IB */ 582 ring_size += 12; /* fence emit for VB IB */
585 ring_size += 5; /* done copy */ 583 ring_size += 5; /* done copy */
586 ring_size += 7; /* fence emit for done copy */ 584 ring_size += 12; /* fence emit for done copy */
587 r = radeon_ring_lock(rdev, ring_size); 585 r = radeon_ring_lock(rdev, ring_size);
588 if (r) 586 if (r)
589 return r; 587 return r;
@@ -597,13 +595,6 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
597{ 595{
598 int r; 596 int r;
599 597
600 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
601 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
602 /* wait for 3D idle clean */
603 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
604 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
605 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
606
607 if (rdev->r600_blit.vb_ib) 598 if (rdev->r600_blit.vb_ib)
608 r600_vb_ib_put(rdev); 599 r600_vb_ib_put(rdev);
609 600