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path: root/drivers/gpu/drm/radeon/r600_blit_kms.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r600_blit_kms.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c235
1 files changed, 123 insertions, 112 deletions
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index e09d2818f94..d996f438113 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -50,6 +50,7 @@ static void
50set_render_target(struct radeon_device *rdev, int format, 50set_render_target(struct radeon_device *rdev, int format,
51 int w, int h, u64 gpu_addr) 51 int w, int h, u64 gpu_addr)
52{ 52{
53 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
53 u32 cb_color_info; 54 u32 cb_color_info;
54 int pitch, slice; 55 int pitch, slice;
55 56
@@ -63,38 +64,38 @@ set_render_target(struct radeon_device *rdev, int format,
63 pitch = (w / 8) - 1; 64 pitch = (w / 8) - 1;
64 slice = ((w * h) / 64) - 1; 65 slice = ((w * h) / 64) - 1;
65 66
66 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 67 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
67 radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 68 radeon_ring_write(ring, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
68 radeon_ring_write(rdev, gpu_addr >> 8); 69 radeon_ring_write(ring, gpu_addr >> 8);
69 70
70 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { 71 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
71 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); 72 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
72 radeon_ring_write(rdev, 2 << 0); 73 radeon_ring_write(ring, 2 << 0);
73 } 74 }
74 75
75 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 76 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
76 radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 77 radeon_ring_write(ring, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
77 radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); 78 radeon_ring_write(ring, (pitch << 0) | (slice << 10));
78 79
79 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 80 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
80 radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 81 radeon_ring_write(ring, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
81 radeon_ring_write(rdev, 0); 82 radeon_ring_write(ring, 0);
82 83
83 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 84 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
84 radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 85 radeon_ring_write(ring, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
85 radeon_ring_write(rdev, cb_color_info); 86 radeon_ring_write(ring, cb_color_info);
86 87
87 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 88 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
88 radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 89 radeon_ring_write(ring, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
89 radeon_ring_write(rdev, 0); 90 radeon_ring_write(ring, 0);
90 91
91 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 92 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
92 radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 93 radeon_ring_write(ring, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
93 radeon_ring_write(rdev, 0); 94 radeon_ring_write(ring, 0);
94 95
95 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 96 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
96 radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 97 radeon_ring_write(ring, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
97 radeon_ring_write(rdev, 0); 98 radeon_ring_write(ring, 0);
98} 99}
99 100
100/* emits 5dw */ 101/* emits 5dw */
@@ -103,6 +104,7 @@ cp_set_surface_sync(struct radeon_device *rdev,
103 u32 sync_type, u32 size, 104 u32 sync_type, u32 size,
104 u64 mc_addr) 105 u64 mc_addr)
105{ 106{
107 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
106 u32 cp_coher_size; 108 u32 cp_coher_size;
107 109
108 if (size == 0xffffffff) 110 if (size == 0xffffffff)
@@ -110,17 +112,18 @@ cp_set_surface_sync(struct radeon_device *rdev,
110 else 112 else
111 cp_coher_size = ((size + 255) >> 8); 113 cp_coher_size = ((size + 255) >> 8);
112 114
113 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); 115 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
114 radeon_ring_write(rdev, sync_type); 116 radeon_ring_write(ring, sync_type);
115 radeon_ring_write(rdev, cp_coher_size); 117 radeon_ring_write(ring, cp_coher_size);
116 radeon_ring_write(rdev, mc_addr >> 8); 118 radeon_ring_write(ring, mc_addr >> 8);
117 radeon_ring_write(rdev, 10); /* poll interval */ 119 radeon_ring_write(ring, 10); /* poll interval */
118} 120}
119 121
120/* emits 21dw + 1 surface sync = 26dw */ 122/* emits 21dw + 1 surface sync = 26dw */
121static void 123static void
122set_shaders(struct radeon_device *rdev) 124set_shaders(struct radeon_device *rdev)
123{ 125{
126 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
124 u64 gpu_addr; 127 u64 gpu_addr;
125 u32 sq_pgm_resources; 128 u32 sq_pgm_resources;
126 129
@@ -129,35 +132,35 @@ set_shaders(struct radeon_device *rdev)
129 132
130 /* VS */ 133 /* VS */
131 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; 134 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
132 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 135 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
133 radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 136 radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
134 radeon_ring_write(rdev, gpu_addr >> 8); 137 radeon_ring_write(ring, gpu_addr >> 8);
135 138
136 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 139 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
137 radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 140 radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
138 radeon_ring_write(rdev, sq_pgm_resources); 141 radeon_ring_write(ring, sq_pgm_resources);
139 142
140 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 143 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
141 radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 144 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
142 radeon_ring_write(rdev, 0); 145 radeon_ring_write(ring, 0);
143 146
144 /* PS */ 147 /* PS */
145 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; 148 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
146 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 149 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
147 radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 150 radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
148 radeon_ring_write(rdev, gpu_addr >> 8); 151 radeon_ring_write(ring, gpu_addr >> 8);
149 152
150 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 153 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
151 radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 154 radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
152 radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); 155 radeon_ring_write(ring, sq_pgm_resources | (1 << 28));
153 156
154 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 157 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
155 radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 158 radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
156 radeon_ring_write(rdev, 2); 159 radeon_ring_write(ring, 2);
157 160
158 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 161 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
159 radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 162 radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
160 radeon_ring_write(rdev, 0); 163 radeon_ring_write(ring, 0);
161 164
162 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; 165 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
163 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); 166 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
@@ -167,6 +170,7 @@ set_shaders(struct radeon_device *rdev)
167static void 170static void
168set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) 171set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
169{ 172{
173 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
170 u32 sq_vtx_constant_word2; 174 u32 sq_vtx_constant_word2;
171 175
172 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | 176 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
@@ -175,15 +179,15 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
175 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32); 179 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
176#endif 180#endif
177 181
178 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); 182 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
179 radeon_ring_write(rdev, 0x460); 183 radeon_ring_write(ring, 0x460);
180 radeon_ring_write(rdev, gpu_addr & 0xffffffff); 184 radeon_ring_write(ring, gpu_addr & 0xffffffff);
181 radeon_ring_write(rdev, 48 - 1); 185 radeon_ring_write(ring, 48 - 1);
182 radeon_ring_write(rdev, sq_vtx_constant_word2); 186 radeon_ring_write(ring, sq_vtx_constant_word2);
183 radeon_ring_write(rdev, 1 << 0); 187 radeon_ring_write(ring, 1 << 0);
184 radeon_ring_write(rdev, 0); 188 radeon_ring_write(ring, 0);
185 radeon_ring_write(rdev, 0); 189 radeon_ring_write(ring, 0);
186 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); 190 radeon_ring_write(ring, SQ_TEX_VTX_VALID_BUFFER << 30);
187 191
188 if ((rdev->family == CHIP_RV610) || 192 if ((rdev->family == CHIP_RV610) ||
189 (rdev->family == CHIP_RV620) || 193 (rdev->family == CHIP_RV620) ||
@@ -203,6 +207,7 @@ set_tex_resource(struct radeon_device *rdev,
203 int format, int w, int h, int pitch, 207 int format, int w, int h, int pitch,
204 u64 gpu_addr, u32 size) 208 u64 gpu_addr, u32 size)
205{ 209{
210 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
206 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; 211 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
207 212
208 if (h < 1) 213 if (h < 1)
@@ -225,15 +230,15 @@ set_tex_resource(struct radeon_device *rdev,
225 cp_set_surface_sync(rdev, 230 cp_set_surface_sync(rdev,
226 PACKET3_TC_ACTION_ENA, size, gpu_addr); 231 PACKET3_TC_ACTION_ENA, size, gpu_addr);
227 232
228 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); 233 radeon_ring_write(ring, PACKET3(PACKET3_SET_RESOURCE, 7));
229 radeon_ring_write(rdev, 0); 234 radeon_ring_write(ring, 0);
230 radeon_ring_write(rdev, sq_tex_resource_word0); 235 radeon_ring_write(ring, sq_tex_resource_word0);
231 radeon_ring_write(rdev, sq_tex_resource_word1); 236 radeon_ring_write(ring, sq_tex_resource_word1);
232 radeon_ring_write(rdev, gpu_addr >> 8); 237 radeon_ring_write(ring, gpu_addr >> 8);
233 radeon_ring_write(rdev, gpu_addr >> 8); 238 radeon_ring_write(ring, gpu_addr >> 8);
234 radeon_ring_write(rdev, sq_tex_resource_word4); 239 radeon_ring_write(ring, sq_tex_resource_word4);
235 radeon_ring_write(rdev, 0); 240 radeon_ring_write(ring, 0);
236 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30); 241 radeon_ring_write(ring, SQ_TEX_VTX_VALID_TEXTURE << 30);
237} 242}
238 243
239/* emits 12 */ 244/* emits 12 */
@@ -241,43 +246,45 @@ static void
241set_scissors(struct radeon_device *rdev, int x1, int y1, 246set_scissors(struct radeon_device *rdev, int x1, int y1,
242 int x2, int y2) 247 int x2, int y2)
243{ 248{
244 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 249 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
245 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 250 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
246 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); 251 radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
247 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); 252 radeon_ring_write(ring, (x1 << 0) | (y1 << 16));
248 253 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
249 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 254
250 radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 255 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
251 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); 256 radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
252 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); 257 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
253 258 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
254 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 259
255 radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 260 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
256 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); 261 radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
257 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); 262 radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31));
263 radeon_ring_write(ring, (x2 << 0) | (y2 << 16));
258} 264}
259 265
260/* emits 10 */ 266/* emits 10 */
261static void 267static void
262draw_auto(struct radeon_device *rdev) 268draw_auto(struct radeon_device *rdev)
263{ 269{
264 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 270 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
265 radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 271 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
266 radeon_ring_write(rdev, DI_PT_RECTLIST); 272 radeon_ring_write(ring, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
273 radeon_ring_write(ring, DI_PT_RECTLIST);
267 274
268 radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); 275 radeon_ring_write(ring, PACKET3(PACKET3_INDEX_TYPE, 0));
269 radeon_ring_write(rdev, 276 radeon_ring_write(ring,
270#ifdef __BIG_ENDIAN 277#ifdef __BIG_ENDIAN
271 (2 << 2) | 278 (2 << 2) |
272#endif 279#endif
273 DI_INDEX_SIZE_16_BIT); 280 DI_INDEX_SIZE_16_BIT);
274 281
275 radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); 282 radeon_ring_write(ring, PACKET3(PACKET3_NUM_INSTANCES, 0));
276 radeon_ring_write(rdev, 1); 283 radeon_ring_write(ring, 1);
277 284
278 radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); 285 radeon_ring_write(ring, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
279 radeon_ring_write(rdev, 3); 286 radeon_ring_write(ring, 3);
280 radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); 287 radeon_ring_write(ring, DI_SRC_SEL_AUTO_INDEX);
281 288
282} 289}
283 290
@@ -285,6 +292,7 @@ draw_auto(struct radeon_device *rdev)
285static void 292static void
286set_default_state(struct radeon_device *rdev) 293set_default_state(struct radeon_device *rdev)
287{ 294{
295 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
288 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; 296 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
289 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; 297 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
290 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; 298 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
@@ -440,24 +448,24 @@ set_default_state(struct radeon_device *rdev)
440 /* emit an IB pointing at default state */ 448 /* emit an IB pointing at default state */
441 dwords = ALIGN(rdev->r600_blit.state_len, 0x10); 449 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
442 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; 450 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
443 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 451 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
444 radeon_ring_write(rdev, 452 radeon_ring_write(ring,
445#ifdef __BIG_ENDIAN 453#ifdef __BIG_ENDIAN
446 (2 << 0) | 454 (2 << 0) |
447#endif 455#endif
448 (gpu_addr & 0xFFFFFFFC)); 456 (gpu_addr & 0xFFFFFFFC));
449 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); 457 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xFF);
450 radeon_ring_write(rdev, dwords); 458 radeon_ring_write(ring, dwords);
451 459
452 /* SQ config */ 460 /* SQ config */
453 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); 461 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6));
454 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 462 radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
455 radeon_ring_write(rdev, sq_config); 463 radeon_ring_write(ring, sq_config);
456 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); 464 radeon_ring_write(ring, sq_gpr_resource_mgmt_1);
457 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); 465 radeon_ring_write(ring, sq_gpr_resource_mgmt_2);
458 radeon_ring_write(rdev, sq_thread_resource_mgmt); 466 radeon_ring_write(ring, sq_thread_resource_mgmt);
459 radeon_ring_write(rdev, sq_stack_resource_mgmt_1); 467 radeon_ring_write(ring, sq_stack_resource_mgmt_1);
460 radeon_ring_write(rdev, sq_stack_resource_mgmt_2); 468 radeon_ring_write(ring, sq_stack_resource_mgmt_2);
461} 469}
462 470
463static uint32_t i2f(uint32_t input) 471static uint32_t i2f(uint32_t input)
@@ -611,16 +619,17 @@ void r600_blit_fini(struct radeon_device *rdev)
611 radeon_bo_unref(&rdev->r600_blit.shader_obj); 619 radeon_bo_unref(&rdev->r600_blit.shader_obj);
612} 620}
613 621
614static int r600_vb_ib_get(struct radeon_device *rdev) 622static int r600_vb_ib_get(struct radeon_device *rdev, unsigned size)
615{ 623{
616 int r; 624 int r;
617 r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); 625 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX,
626 &rdev->r600_blit.vb_ib, size);
618 if (r) { 627 if (r) {
619 DRM_ERROR("failed to get IB for vertex buffer\n"); 628 DRM_ERROR("failed to get IB for vertex buffer\n");
620 return r; 629 return r;
621 } 630 }
622 631
623 rdev->r600_blit.vb_total = 64*1024; 632 rdev->r600_blit.vb_total = size;
624 rdev->r600_blit.vb_used = 0; 633 rdev->r600_blit.vb_used = 0;
625 return 0; 634 return 0;
626} 635}
@@ -679,15 +688,12 @@ static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
679 688
680int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages) 689int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages)
681{ 690{
691 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
682 int r; 692 int r;
683 int ring_size; 693 int ring_size;
684 int num_loops = 0; 694 int num_loops = 0;
685 int dwords_per_loop = rdev->r600_blit.ring_size_per_loop; 695 int dwords_per_loop = rdev->r600_blit.ring_size_per_loop;
686 696
687 r = r600_vb_ib_get(rdev);
688 if (r)
689 return r;
690
691 /* num loops */ 697 /* num loops */
692 while (num_gpu_pages) { 698 while (num_gpu_pages) {
693 num_gpu_pages -= 699 num_gpu_pages -=
@@ -696,10 +702,15 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages)
696 num_loops++; 702 num_loops++;
697 } 703 }
698 704
705 /* 48 bytes for vertex per loop */
706 r = r600_vb_ib_get(rdev, (num_loops*48)+256);
707 if (r)
708 return r;
709
699 /* calculate number of loops correctly */ 710 /* calculate number of loops correctly */
700 ring_size = num_loops * dwords_per_loop; 711 ring_size = num_loops * dwords_per_loop;
701 ring_size += rdev->r600_blit.ring_size_common; 712 ring_size += rdev->r600_blit.ring_size_common;
702 r = radeon_ring_lock(rdev, ring_size); 713 r = radeon_ring_lock(rdev, ring, ring_size);
703 if (r) 714 if (r)
704 return r; 715 return r;
705 716
@@ -718,7 +729,7 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
718 if (fence) 729 if (fence)
719 r = radeon_fence_emit(rdev, fence); 730 r = radeon_fence_emit(rdev, fence);
720 731
721 radeon_ring_unlock_commit(rdev); 732 radeon_ring_unlock_commit(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
722} 733}
723 734
724void r600_kms_blit_copy(struct radeon_device *rdev, 735void r600_kms_blit_copy(struct radeon_device *rdev,
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-19 07:25:54 -0400