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-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.c100
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bios.h1
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c15
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_channel.c24
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_connector.c6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h10
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_fence.c6
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_gem.c47
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_i2c.c2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_sgdma.c12
-rw-r--r--drivers/gpu/drm/nouveau/nv04_dfp.c31
-rw-r--r--drivers/gpu/drm/nouveau/nv17_tv.c12
-rw-r--r--drivers/gpu/drm/nouveau/nv50_instmem.c4
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_instmem.c13
14 files changed, 176 insertions, 107 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 0b69a9628c9..974b0f8ae04 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -2166,7 +2166,7 @@ peek_fb(struct drm_device *dev, struct io_mapping *fb,
2166 uint32_t val = 0; 2166 uint32_t val = 0;
2167 2167
2168 if (off < pci_resource_len(dev->pdev, 1)) { 2168 if (off < pci_resource_len(dev->pdev, 1)) {
2169 uint32_t __iomem *p = 2169 uint8_t __iomem *p =
2170 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0); 2170 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0);
2171 2171
2172 val = ioread32(p + (off & ~PAGE_MASK)); 2172 val = ioread32(p + (off & ~PAGE_MASK));
@@ -2182,7 +2182,7 @@ poke_fb(struct drm_device *dev, struct io_mapping *fb,
2182 uint32_t off, uint32_t val) 2182 uint32_t off, uint32_t val)
2183{ 2183{
2184 if (off < pci_resource_len(dev->pdev, 1)) { 2184 if (off < pci_resource_len(dev->pdev, 1)) {
2185 uint32_t __iomem *p = 2185 uint8_t __iomem *p =
2186 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0); 2186 io_mapping_map_atomic_wc(fb, off & PAGE_MASK, KM_USER0);
2187 2187
2188 iowrite32(val, p + (off & ~PAGE_MASK)); 2188 iowrite32(val, p + (off & ~PAGE_MASK));
@@ -3869,27 +3869,10 @@ static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entr
3869 } 3869 }
3870#ifdef __powerpc__ 3870#ifdef __powerpc__
3871 /* Powerbook specific quirks */ 3871 /* Powerbook specific quirks */
3872 if ((dev->pci_device & 0xffff) == 0x0179 || 3872 if (script == LVDS_RESET &&
3873 (dev->pci_device & 0xffff) == 0x0189 || 3873 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3874 (dev->pci_device & 0xffff) == 0x0329) { 3874 dev->pci_device == 0x0329))
3875 if (script == LVDS_RESET) { 3875 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3876 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3877
3878 } else if (script == LVDS_PANEL_ON) {
3879 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3880 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3881 | (1 << 31));
3882 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3883 bios_rd32(bios, NV_PCRTC_GPIO_EXT) | 1);
3884
3885 } else if (script == LVDS_PANEL_OFF) {
3886 bios_wr32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL,
3887 bios_rd32(bios, NV_PBUS_DEBUG_DUALHEAD_CTL)
3888 & ~(1 << 31));
3889 bios_wr32(bios, NV_PCRTC_GPIO_EXT,
3890 bios_rd32(bios, NV_PCRTC_GPIO_EXT) & ~3);
3891 }
3892 }
3893#endif 3876#endif
3894 3877
3895 return 0; 3878 return 0;
@@ -4381,11 +4364,8 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b
4381 * 4364 *
4382 * For the moment, a quirk will do :) 4365 * For the moment, a quirk will do :)
4383 */ 4366 */
4384 if ((dev->pdev->device == 0x01d7) && 4367 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
4385 (dev->pdev->subsystem_vendor == 0x1028) &&
4386 (dev->pdev->subsystem_device == 0x01c2)) {
4387 bios->fp.duallink_transition_clk = 80000; 4368 bios->fp.duallink_transition_clk = 80000;
4388 }
4389 4369
4390 /* set dual_link flag for EDID case */ 4370 /* set dual_link flag for EDID case */
4391 if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) 4371 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
@@ -4587,7 +4567,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4587 return 1; 4567 return 1;
4588 } 4568 }
4589 4569
4590 NV_TRACE(dev, "0x%04X: parsing output script 0\n", script); 4570 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
4591 nouveau_bios_run_init_table(dev, script, dcbent); 4571 nouveau_bios_run_init_table(dev, script, dcbent);
4592 } else 4572 } else
4593 if (pxclk == -1) { 4573 if (pxclk == -1) {
@@ -4597,7 +4577,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4597 return 1; 4577 return 1;
4598 } 4578 }
4599 4579
4600 NV_TRACE(dev, "0x%04X: parsing output script 1\n", script); 4580 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
4601 nouveau_bios_run_init_table(dev, script, dcbent); 4581 nouveau_bios_run_init_table(dev, script, dcbent);
4602 } else 4582 } else
4603 if (pxclk == -2) { 4583 if (pxclk == -2) {
@@ -4610,7 +4590,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4610 return 1; 4590 return 1;
4611 } 4591 }
4612 4592
4613 NV_TRACE(dev, "0x%04X: parsing output script 2\n", script); 4593 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
4614 nouveau_bios_run_init_table(dev, script, dcbent); 4594 nouveau_bios_run_init_table(dev, script, dcbent);
4615 } else 4595 } else
4616 if (pxclk > 0) { 4596 if (pxclk > 0) {
@@ -4622,7 +4602,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4622 return 1; 4602 return 1;
4623 } 4603 }
4624 4604
4625 NV_TRACE(dev, "0x%04X: parsing clock script 0\n", script); 4605 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
4626 nouveau_bios_run_init_table(dev, script, dcbent); 4606 nouveau_bios_run_init_table(dev, script, dcbent);
4627 } else 4607 } else
4628 if (pxclk < 0) { 4608 if (pxclk < 0) {
@@ -4634,7 +4614,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4634 return 1; 4614 return 1;
4635 } 4615 }
4636 4616
4637 NV_TRACE(dev, "0x%04X: parsing clock script 1\n", script); 4617 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
4638 nouveau_bios_run_init_table(dev, script, dcbent); 4618 nouveau_bios_run_init_table(dev, script, dcbent);
4639 } 4619 }
4640 4620
@@ -5357,19 +5337,17 @@ static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5357 } 5337 }
5358 5338
5359 tmdstableptr = ROM16(bios->data[bitentry->offset]); 5339 tmdstableptr = ROM16(bios->data[bitentry->offset]);
5360 5340 if (!tmdstableptr) {
5361 if (tmdstableptr == 0x0) {
5362 NV_ERROR(dev, "Pointer to TMDS table invalid\n"); 5341 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5363 return -EINVAL; 5342 return -EINVAL;
5364 } 5343 }
5365 5344
5345 NV_INFO(dev, "TMDS table version %d.%d\n",
5346 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5347
5366 /* nv50+ has v2.0, but we don't parse it atm */ 5348 /* nv50+ has v2.0, but we don't parse it atm */
5367 if (bios->data[tmdstableptr] != 0x11) { 5349 if (bios->data[tmdstableptr] != 0x11)
5368 NV_WARN(dev,
5369 "TMDS table revision %d.%d not currently supported\n",
5370 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5371 return -ENOSYS; 5350 return -ENOSYS;
5372 }
5373 5351
5374 /* 5352 /*
5375 * These two scripts are odd: they don't seem to get run even when 5353 * These two scripts are odd: they don't seem to get run even when
@@ -5809,6 +5787,20 @@ parse_dcb_gpio_table(struct nvbios *bios)
5809 gpio->line = tvdac_gpio[1] >> 4; 5787 gpio->line = tvdac_gpio[1] >> 4;
5810 gpio->invert = tvdac_gpio[0] & 2; 5788 gpio->invert = tvdac_gpio[0] & 2;
5811 } 5789 }
5790 } else {
5791 /*
5792 * No systematic way to store GPIO info on pre-v2.2
5793 * DCBs, try to match the PCI device IDs.
5794 */
5795
5796 /* Apple iMac G4 NV18 */
5797 if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) {
5798 struct dcb_gpio_entry *gpio = new_gpio_entry(bios);
5799
5800 gpio->tag = DCB_GPIO_TVDAC0;
5801 gpio->line = 4;
5802 }
5803
5812 } 5804 }
5813 5805
5814 if (!gpio_table_ptr) 5806 if (!gpio_table_ptr)
@@ -5884,9 +5876,7 @@ apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5884 struct drm_device *dev = bios->dev; 5876 struct drm_device *dev = bios->dev;
5885 5877
5886 /* Gigabyte NX85T */ 5878 /* Gigabyte NX85T */
5887 if ((dev->pdev->device == 0x0421) && 5879 if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) {
5888 (dev->pdev->subsystem_vendor == 0x1458) &&
5889 (dev->pdev->subsystem_device == 0x344c)) {
5890 if (cte->type == DCB_CONNECTOR_HDMI_1) 5880 if (cte->type == DCB_CONNECTOR_HDMI_1)
5891 cte->type = DCB_CONNECTOR_DVI_I; 5881 cte->type = DCB_CONNECTOR_DVI_I;
5892 } 5882 }
@@ -6139,7 +6129,7 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6139 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4; 6129 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
6140 6130
6141 break; 6131 break;
6142 case 0xe: 6132 case OUTPUT_EOL:
6143 /* weird g80 mobile type that "nv" treats as a terminator */ 6133 /* weird g80 mobile type that "nv" treats as a terminator */
6144 dcb->entries--; 6134 dcb->entries--;
6145 return false; 6135 return false;
@@ -6176,22 +6166,14 @@ parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6176 entry->type = OUTPUT_TV; 6166 entry->type = OUTPUT_TV;
6177 break; 6167 break;
6178 case 2: 6168 case 2:
6179 case 3:
6180 entry->type = OUTPUT_LVDS;
6181 break;
6182 case 4: 6169 case 4:
6183 switch ((conn & 0x000000f0) >> 4) { 6170 if (conn & 0x10)
6184 case 0:
6185 entry->type = OUTPUT_TMDS;
6186 break;
6187 case 1:
6188 entry->type = OUTPUT_LVDS; 6171 entry->type = OUTPUT_LVDS;
6189 break; 6172 else
6190 default: 6173 entry->type = OUTPUT_TMDS;
6191 NV_ERROR(dev, "Unknown DCB subtype 4/%d\n", 6174 break;
6192 (conn & 0x000000f0) >> 4); 6175 case 3:
6193 return false; 6176 entry->type = OUTPUT_LVDS;
6194 }
6195 break; 6177 break;
6196 default: 6178 default:
6197 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f); 6179 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
@@ -6307,9 +6289,7 @@ apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6307 * nasty problems until this is sorted (assuming it's not a 6289 * nasty problems until this is sorted (assuming it's not a
6308 * VBIOS bug). 6290 * VBIOS bug).
6309 */ 6291 */
6310 if ((dev->pdev->device == 0x040d) && 6292 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
6311 (dev->pdev->subsystem_vendor == 0x1028) &&
6312 (dev->pdev->subsystem_device == 0x019b)) {
6313 if (*conn == 0x02026312 && *conf == 0x00000020) 6293 if (*conn == 0x02026312 && *conf == 0x00000020)
6314 return false; 6294 return false;
6315 } 6295 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index fd14dfd3d78..c1de2f3fcb0 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -95,6 +95,7 @@ enum dcb_type {
95 OUTPUT_TMDS = 2, 95 OUTPUT_TMDS = 2,
96 OUTPUT_LVDS = 3, 96 OUTPUT_LVDS = 3,
97 OUTPUT_DP = 6, 97 OUTPUT_DP = 6,
98 OUTPUT_EOL = 14, /* DCB 4.0+, appears to be end-of-list */
98 OUTPUT_ANY = -1 99 OUTPUT_ANY = -1
99}; 100};
100 101
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 84f85183d04..f6f44779d82 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -36,6 +36,21 @@
36#include <linux/log2.h> 36#include <linux/log2.h>
37#include <linux/slab.h> 37#include <linux/slab.h>
38 38
39int
40nouveau_bo_sync_gpu(struct nouveau_bo *nvbo, struct nouveau_channel *chan)
41{
42 struct nouveau_fence *prev_fence = nvbo->bo.sync_obj;
43 int ret;
44
45 if (!prev_fence || nouveau_fence_channel(prev_fence) == chan)
46 return 0;
47
48 spin_lock(&nvbo->bo.lock);
49 ret = ttm_bo_wait(&nvbo->bo, false, false, false);
50 spin_unlock(&nvbo->bo.lock);
51 return ret;
52}
53
39static void 54static void
40nouveau_bo_del_ttm(struct ttm_buffer_object *bo) 55nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
41{ 56{
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 90fdcda332b..0480f064f2c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -426,18 +426,18 @@ nouveau_ioctl_fifo_free(struct drm_device *dev, void *data,
426 ***********************************/ 426 ***********************************/
427 427
428struct drm_ioctl_desc nouveau_ioctls[] = { 428struct drm_ioctl_desc nouveau_ioctls[] = {
429 DRM_IOCTL_DEF(DRM_NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH), 429 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_ioctl_getparam, DRM_AUTH),
430 DRM_IOCTL_DEF(DRM_NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), 430 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
431 DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH), 431 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_ioctl_fifo_alloc, DRM_AUTH),
432 DRM_IOCTL_DEF(DRM_NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH), 432 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_ioctl_fifo_free, DRM_AUTH),
433 DRM_IOCTL_DEF(DRM_NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH), 433 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_ioctl_grobj_alloc, DRM_AUTH),
434 DRM_IOCTL_DEF(DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH), 434 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_ioctl_notifier_alloc, DRM_AUTH),
435 DRM_IOCTL_DEF(DRM_NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH), 435 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_ioctl_gpuobj_free, DRM_AUTH),
436 DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH), 436 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH),
437 DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH), 437 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH),
438 DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH), 438 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH),
439 DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH), 439 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH),
440 DRM_IOCTL_DEF(DRM_NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH), 440 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH),
441}; 441};
442 442
443int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls); 443int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index b1b22baf142..a1473fff06a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -104,7 +104,7 @@ nouveau_connector_ddc_detect(struct drm_connector *connector,
104 int i; 104 int i;
105 105
106 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { 106 for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
107 struct nouveau_i2c_chan *i2c; 107 struct nouveau_i2c_chan *i2c = NULL;
108 struct nouveau_encoder *nv_encoder; 108 struct nouveau_encoder *nv_encoder;
109 struct drm_mode_object *obj; 109 struct drm_mode_object *obj;
110 int id; 110 int id;
@@ -117,7 +117,9 @@ nouveau_connector_ddc_detect(struct drm_connector *connector,
117 if (!obj) 117 if (!obj)
118 continue; 118 continue;
119 nv_encoder = nouveau_encoder(obj_to_encoder(obj)); 119 nv_encoder = nouveau_encoder(obj_to_encoder(obj));
120 i2c = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index); 120
121 if (nv_encoder->dcb->i2c_index < 0xf)
122 i2c = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
121 123
122 if (i2c && nouveau_probe_i2c_addr(i2c, 0x50)) { 124 if (i2c && nouveau_probe_i2c_addr(i2c, 0x50)) {
123 *pnv_encoder = nv_encoder; 125 *pnv_encoder = nv_encoder;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index e424bf74d70..b1be617373b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -1165,6 +1165,7 @@ extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1165extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); 1165extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1166extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); 1166extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1167extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); 1167extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
1168extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *);
1168 1169
1169/* nouveau_fence.c */ 1170/* nouveau_fence.c */
1170struct nouveau_fence; 1171struct nouveau_fence;
@@ -1388,6 +1389,15 @@ nv_two_reg_pll(struct drm_device *dev)
1388 return false; 1389 return false;
1389} 1390}
1390 1391
1392static inline bool
1393nv_match_device(struct drm_device *dev, unsigned device,
1394 unsigned sub_vendor, unsigned sub_device)
1395{
1396 return dev->pdev->device == device &&
1397 dev->pdev->subsystem_vendor == sub_vendor &&
1398 dev->pdev->subsystem_device == sub_device;
1399}
1400
1391#define NV_SW 0x0000506e 1401#define NV_SW 0x0000506e
1392#define NV_SW_DMA_SEMAPHORE 0x00000060 1402#define NV_SW_DMA_SEMAPHORE 0x00000060
1393#define NV_SW_SEMAPHORE_OFFSET 0x00000064 1403#define NV_SW_SEMAPHORE_OFFSET 0x00000064
diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c
index 6b208ffafa8..87ac21ec23d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fence.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c
@@ -64,16 +64,17 @@ nouveau_fence_update(struct nouveau_channel *chan)
64 struct nouveau_fence *fence; 64 struct nouveau_fence *fence;
65 uint32_t sequence; 65 uint32_t sequence;
66 66
67 spin_lock(&chan->fence.lock);
68
67 if (USE_REFCNT) 69 if (USE_REFCNT)
68 sequence = nvchan_rd32(chan, 0x48); 70 sequence = nvchan_rd32(chan, 0x48);
69 else 71 else
70 sequence = atomic_read(&chan->fence.last_sequence_irq); 72 sequence = atomic_read(&chan->fence.last_sequence_irq);
71 73
72 if (chan->fence.sequence_ack == sequence) 74 if (chan->fence.sequence_ack == sequence)
73 return; 75 goto out;
74 chan->fence.sequence_ack = sequence; 76 chan->fence.sequence_ack = sequence;
75 77
76 spin_lock(&chan->fence.lock);
77 list_for_each_safe(entry, tmp, &chan->fence.pending) { 78 list_for_each_safe(entry, tmp, &chan->fence.pending) {
78 fence = list_entry(entry, struct nouveau_fence, entry); 79 fence = list_entry(entry, struct nouveau_fence, entry);
79 80
@@ -85,6 +86,7 @@ nouveau_fence_update(struct nouveau_channel *chan)
85 if (sequence == chan->fence.sequence_ack) 86 if (sequence == chan->fence.sequence_ack)
86 break; 87 break;
87 } 88 }
89out:
88 spin_unlock(&chan->fence.lock); 90 spin_unlock(&chan->fence.lock);
89} 91}
90 92
diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c
index 0f417ac1b69..ead7b8fc53f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_gem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c
@@ -245,7 +245,7 @@ validate_fini_list(struct list_head *list, struct nouveau_fence *fence)
245 list_del(&nvbo->entry); 245 list_del(&nvbo->entry);
246 nvbo->reserved_by = NULL; 246 nvbo->reserved_by = NULL;
247 ttm_bo_unreserve(&nvbo->bo); 247 ttm_bo_unreserve(&nvbo->bo);
248 drm_gem_object_unreference(nvbo->gem); 248 drm_gem_object_unreference_unlocked(nvbo->gem);
249 } 249 }
250} 250}
251 251
@@ -300,7 +300,7 @@ retry:
300 validate_fini(op, NULL); 300 validate_fini(op, NULL);
301 if (ret == -EAGAIN) 301 if (ret == -EAGAIN)
302 ret = ttm_bo_wait_unreserved(&nvbo->bo, false); 302 ret = ttm_bo_wait_unreserved(&nvbo->bo, false);
303 drm_gem_object_unreference(gem); 303 drm_gem_object_unreference_unlocked(gem);
304 if (ret) { 304 if (ret) {
305 NV_ERROR(dev, "fail reserve\n"); 305 NV_ERROR(dev, "fail reserve\n");
306 return ret; 306 return ret;
@@ -337,7 +337,9 @@ retry:
337 return -EINVAL; 337 return -EINVAL;
338 } 338 }
339 339
340 mutex_unlock(&drm_global_mutex);
340 ret = ttm_bo_wait_cpu(&nvbo->bo, false); 341 ret = ttm_bo_wait_cpu(&nvbo->bo, false);
342 mutex_lock(&drm_global_mutex);
341 if (ret) { 343 if (ret) {
342 NV_ERROR(dev, "fail wait_cpu\n"); 344 NV_ERROR(dev, "fail wait_cpu\n");
343 return ret; 345 return ret;
@@ -361,16 +363,11 @@ validate_list(struct nouveau_channel *chan, struct list_head *list,
361 363
362 list_for_each_entry(nvbo, list, entry) { 364 list_for_each_entry(nvbo, list, entry) {
363 struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[nvbo->pbbo_index]; 365 struct drm_nouveau_gem_pushbuf_bo *b = &pbbo[nvbo->pbbo_index];
364 struct nouveau_fence *prev_fence = nvbo->bo.sync_obj;
365 366
366 if (prev_fence && nouveau_fence_channel(prev_fence) != chan) { 367 ret = nouveau_bo_sync_gpu(nvbo, chan);
367 spin_lock(&nvbo->bo.lock); 368 if (unlikely(ret)) {
368 ret = ttm_bo_wait(&nvbo->bo, false, false, false); 369 NV_ERROR(dev, "fail pre-validate sync\n");
369 spin_unlock(&nvbo->bo.lock); 370 return ret;
370 if (unlikely(ret)) {
371 NV_ERROR(dev, "fail wait other chan\n");
372 return ret;
373 }
374 } 371 }
375 372
376 ret = nouveau_gem_set_domain(nvbo->gem, b->read_domains, 373 ret = nouveau_gem_set_domain(nvbo->gem, b->read_domains,
@@ -381,7 +378,7 @@ validate_list(struct nouveau_channel *chan, struct list_head *list,
381 return ret; 378 return ret;
382 } 379 }
383 380
384 nvbo->channel = chan; 381 nvbo->channel = (b->read_domains & (1 << 31)) ? NULL : chan;
385 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, 382 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
386 false, false, false); 383 false, false, false);
387 nvbo->channel = NULL; 384 nvbo->channel = NULL;
@@ -390,6 +387,12 @@ validate_list(struct nouveau_channel *chan, struct list_head *list,
390 return ret; 387 return ret;
391 } 388 }
392 389
390 ret = nouveau_bo_sync_gpu(nvbo, chan);
391 if (unlikely(ret)) {
392 NV_ERROR(dev, "fail post-validate sync\n");
393 return ret;
394 }
395
393 if (nvbo->bo.offset == b->presumed.offset && 396 if (nvbo->bo.offset == b->presumed.offset &&
394 ((nvbo->bo.mem.mem_type == TTM_PL_VRAM && 397 ((nvbo->bo.mem.mem_type == TTM_PL_VRAM &&
395 b->presumed.domain & NOUVEAU_GEM_DOMAIN_VRAM) || 398 b->presumed.domain & NOUVEAU_GEM_DOMAIN_VRAM) ||
@@ -613,7 +616,20 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
613 return PTR_ERR(bo); 616 return PTR_ERR(bo);
614 } 617 }
615 618
616 mutex_lock(&dev->struct_mutex); 619 /* Mark push buffers as being used on PFIFO, the validation code
620 * will then make sure that if the pushbuf bo moves, that they
621 * happen on the kernel channel, which will in turn cause a sync
622 * to happen before we try and submit the push buffer.
623 */
624 for (i = 0; i < req->nr_push; i++) {
625 if (push[i].bo_index >= req->nr_buffers) {
626 NV_ERROR(dev, "push %d buffer not in list\n", i);
627 ret = -EINVAL;
628 goto out;
629 }
630
631 bo[push[i].bo_index].read_domains |= (1 << 31);
632 }
617 633
618 /* Validate buffer list */ 634 /* Validate buffer list */
619 ret = nouveau_gem_pushbuf_validate(chan, file_priv, bo, req->buffers, 635 ret = nouveau_gem_pushbuf_validate(chan, file_priv, bo, req->buffers,
@@ -647,7 +663,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
647 push[i].length); 663 push[i].length);
648 } 664 }
649 } else 665 } else
650 if (dev_priv->card_type >= NV_20) { 666 if (dev_priv->chipset >= 0x25) {
651 ret = RING_SPACE(chan, req->nr_push * 2); 667 ret = RING_SPACE(chan, req->nr_push * 2);
652 if (ret) { 668 if (ret) {
653 NV_ERROR(dev, "cal_space: %d\n", ret); 669 NV_ERROR(dev, "cal_space: %d\n", ret);
@@ -713,7 +729,6 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
713out: 729out:
714 validate_fini(&op, fence); 730 validate_fini(&op, fence);
715 nouveau_fence_unref((void**)&fence); 731 nouveau_fence_unref((void**)&fence);
716 mutex_unlock(&dev->struct_mutex);
717 kfree(bo); 732 kfree(bo);
718 kfree(push); 733 kfree(push);
719 734
@@ -722,7 +737,7 @@ out_next:
722 req->suffix0 = 0x00000000; 737 req->suffix0 = 0x00000000;
723 req->suffix1 = 0x00000000; 738 req->suffix1 = 0x00000000;
724 } else 739 } else
725 if (dev_priv->card_type >= NV_20) { 740 if (dev_priv->chipset >= 0x25) {
726 req->suffix0 = 0x00020000; 741 req->suffix0 = 0x00020000;
727 req->suffix1 = 0x00000000; 742 req->suffix1 = 0x00000000;
728 } else { 743 } else {
diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.c b/drivers/gpu/drm/nouveau/nouveau_i2c.c
index 0bd407ca3d4..84614858728 100644
--- a/drivers/gpu/drm/nouveau/nouveau_i2c.c
+++ b/drivers/gpu/drm/nouveau/nouveau_i2c.c
@@ -163,7 +163,7 @@ nouveau_i2c_init(struct drm_device *dev, struct dcb_i2c_entry *entry, int index)
163 if (entry->chan) 163 if (entry->chan)
164 return -EEXIST; 164 return -EEXIST;
165 165
166 if (dev_priv->card_type == NV_C0 && entry->read >= NV50_I2C_PORTS) { 166 if (dev_priv->card_type >= NV_50 && entry->read >= NV50_I2C_PORTS) {
167 NV_ERROR(dev, "unknown i2c port %d\n", entry->read); 167 NV_ERROR(dev, "unknown i2c port %d\n", entry->read);
168 return -EINVAL; 168 return -EINVAL;
169 } 169 }
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index 491767fe4fc..6b9187d7f67 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -214,6 +214,7 @@ int
214nouveau_sgdma_init(struct drm_device *dev) 214nouveau_sgdma_init(struct drm_device *dev)
215{ 215{
216 struct drm_nouveau_private *dev_priv = dev->dev_private; 216 struct drm_nouveau_private *dev_priv = dev->dev_private;
217 struct pci_dev *pdev = dev->pdev;
217 struct nouveau_gpuobj *gpuobj = NULL; 218 struct nouveau_gpuobj *gpuobj = NULL;
218 uint32_t aper_size, obj_size; 219 uint32_t aper_size, obj_size;
219 int i, ret; 220 int i, ret;
@@ -239,10 +240,19 @@ nouveau_sgdma_init(struct drm_device *dev)
239 240
240 dev_priv->gart_info.sg_dummy_page = 241 dev_priv->gart_info.sg_dummy_page =
241 alloc_page(GFP_KERNEL|__GFP_DMA32); 242 alloc_page(GFP_KERNEL|__GFP_DMA32);
243 if (!dev_priv->gart_info.sg_dummy_page) {
244 nouveau_gpuobj_del(dev, &gpuobj);
245 return -ENOMEM;
246 }
247
242 set_bit(PG_locked, &dev_priv->gart_info.sg_dummy_page->flags); 248 set_bit(PG_locked, &dev_priv->gart_info.sg_dummy_page->flags);
243 dev_priv->gart_info.sg_dummy_bus = 249 dev_priv->gart_info.sg_dummy_bus =
244 pci_map_page(dev->pdev, dev_priv->gart_info.sg_dummy_page, 0, 250 pci_map_page(pdev, dev_priv->gart_info.sg_dummy_page, 0,
245 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 251 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
252 if (pci_dma_mapping_error(pdev, dev_priv->gart_info.sg_dummy_bus)) {
253 nouveau_gpuobj_del(dev, &gpuobj);
254 return -EFAULT;
255 }
246 256
247 if (dev_priv->card_type < NV_50) { 257 if (dev_priv->card_type < NV_50) {
248 /* Maybe use NV_DMA_TARGET_AGP for PCIE? NVIDIA do this, and 258 /* Maybe use NV_DMA_TARGET_AGP for PCIE? NVIDIA do this, and
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index a5dcf768580..0d3206a7046 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -444,6 +444,7 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
444 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 444 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
445 struct dcb_entry *dcbe = nv_encoder->dcb; 445 struct dcb_entry *dcbe = nv_encoder->dcb;
446 int head = nouveau_crtc(encoder->crtc)->index; 446 int head = nouveau_crtc(encoder->crtc)->index;
447 struct drm_encoder *slave_encoder;
447 448
448 if (dcbe->type == OUTPUT_TMDS) 449 if (dcbe->type == OUTPUT_TMDS)
449 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock); 450 run_tmds_table(dev, dcbe, head, nv_encoder->mode.clock);
@@ -462,9 +463,10 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
462 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000); 463 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
463 464
464 /* Init external transmitters */ 465 /* Init external transmitters */
465 if (get_tmds_slave(encoder)) 466 slave_encoder = get_tmds_slave(encoder);
466 get_slave_funcs(get_tmds_slave(encoder))->mode_set( 467 if (slave_encoder)
467 encoder, &nv_encoder->mode, &nv_encoder->mode); 468 get_slave_funcs(slave_encoder)->mode_set(
469 slave_encoder, &nv_encoder->mode, &nv_encoder->mode);
468 470
469 helper->dpms(encoder, DRM_MODE_DPMS_ON); 471 helper->dpms(encoder, DRM_MODE_DPMS_ON);
470 472
@@ -473,6 +475,27 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
473 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or)); 475 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
474} 476}
475 477
478static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
479{
480#ifdef __powerpc__
481 struct drm_device *dev = encoder->dev;
482
483 /* BIOS scripts usually take care of the backlight, thanks
484 * Apple for your consistency.
485 */
486 if (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
487 dev->pci_device == 0x0329) {
488 if (mode == DRM_MODE_DPMS_ON) {
489 nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 0, 1 << 31);
490 nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 1);
491 } else {
492 nv_mask(dev, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
493 nv_mask(dev, NV_PCRTC_GPIO_EXT, 3, 0);
494 }
495 }
496#endif
497}
498
476static inline bool is_powersaving_dpms(int mode) 499static inline bool is_powersaving_dpms(int mode)
477{ 500{
478 return (mode != DRM_MODE_DPMS_ON); 501 return (mode != DRM_MODE_DPMS_ON);
@@ -520,6 +543,7 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
520 LVDS_PANEL_OFF, 0); 543 LVDS_PANEL_OFF, 0);
521 } 544 }
522 545
546 nv04_dfp_update_backlight(encoder, mode);
523 nv04_dfp_update_fp_control(encoder, mode); 547 nv04_dfp_update_fp_control(encoder, mode);
524 548
525 if (mode == DRM_MODE_DPMS_ON) 549 if (mode == DRM_MODE_DPMS_ON)
@@ -543,6 +567,7 @@ static void nv04_tmds_dpms(struct drm_encoder *encoder, int mode)
543 NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n", 567 NV_INFO(dev, "Setting dpms mode %d on tmds encoder (output %d)\n",
544 mode, nv_encoder->dcb->index); 568 mode, nv_encoder->dcb->index);
545 569
570 nv04_dfp_update_backlight(encoder, mode);
546 nv04_dfp_update_fp_control(encoder, mode); 571 nv04_dfp_update_fp_control(encoder, mode);
547} 572}
548 573
diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c
index 44fefb0c708..13cdc05b7c2 100644
--- a/drivers/gpu/drm/nouveau/nv17_tv.c
+++ b/drivers/gpu/drm/nouveau/nv17_tv.c
@@ -121,10 +121,14 @@ static bool
121get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask) 121get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
122{ 122{
123 /* Zotac FX5200 */ 123 /* Zotac FX5200 */
124 if (dev->pdev->device == 0x0322 && 124 if (nv_match_device(dev, 0x0322, 0x19da, 0x1035) ||
125 dev->pdev->subsystem_vendor == 0x19da && 125 nv_match_device(dev, 0x0322, 0x19da, 0x2035)) {
126 (dev->pdev->subsystem_device == 0x1035 || 126 *pin_mask = 0xc;
127 dev->pdev->subsystem_device == 0x2035)) { 127 return false;
128 }
129
130 /* MSI nForce2 IGP */
131 if (nv_match_device(dev, 0x01f0, 0x1462, 0x5710)) {
128 *pin_mask = 0xc; 132 *pin_mask = 0xc;
129 return false; 133 return false;
130 } 134 }
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
index 37c7b48ab24..91ef93cf1f3 100644
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
@@ -139,6 +139,8 @@ nv50_instmem_init(struct drm_device *dev)
139 chan->file_priv = (struct drm_file *)-2; 139 chan->file_priv = (struct drm_file *)-2;
140 dev_priv->fifos[0] = dev_priv->fifos[127] = chan; 140 dev_priv->fifos[0] = dev_priv->fifos[127] = chan;
141 141
142 INIT_LIST_HEAD(&chan->ramht_refs);
143
142 /* Channel's PRAMIN object + heap */ 144 /* Channel's PRAMIN object + heap */
143 ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0, 145 ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0,
144 NULL, &chan->ramin); 146 NULL, &chan->ramin);
@@ -278,7 +280,7 @@ nv50_instmem_init(struct drm_device *dev)
278 /*XXX: incorrect, but needed to make hash func "work" */ 280 /*XXX: incorrect, but needed to make hash func "work" */
279 dev_priv->ramht_offset = 0x10000; 281 dev_priv->ramht_offset = 0x10000;
280 dev_priv->ramht_bits = 9; 282 dev_priv->ramht_bits = 9;
281 dev_priv->ramht_size = (1 << dev_priv->ramht_bits); 283 dev_priv->ramht_size = (1 << dev_priv->ramht_bits) * 8;
282 return 0; 284 return 0;
283} 285}
284 286
diff --git a/drivers/gpu/drm/nouveau/nvc0_instmem.c b/drivers/gpu/drm/nouveau/nvc0_instmem.c
index 3ab3cdc4217..6b451f86478 100644
--- a/drivers/gpu/drm/nouveau/nvc0_instmem.c
+++ b/drivers/gpu/drm/nouveau/nvc0_instmem.c
@@ -142,14 +142,16 @@ int
142nvc0_instmem_suspend(struct drm_device *dev) 142nvc0_instmem_suspend(struct drm_device *dev)
143{ 143{
144 struct drm_nouveau_private *dev_priv = dev->dev_private; 144 struct drm_nouveau_private *dev_priv = dev->dev_private;
145 u32 *buf;
145 int i; 146 int i;
146 147
147 dev_priv->susres.ramin_copy = vmalloc(65536); 148 dev_priv->susres.ramin_copy = vmalloc(65536);
148 if (!dev_priv->susres.ramin_copy) 149 if (!dev_priv->susres.ramin_copy)
149 return -ENOMEM; 150 return -ENOMEM;
151 buf = dev_priv->susres.ramin_copy;
150 152
151 for (i = 0x700000; i < 0x710000; i += 4) 153 for (i = 0; i < 65536; i += 4)
152 dev_priv->susres.ramin_copy[i/4] = nv_rd32(dev, i); 154 buf[i/4] = nv_rd32(dev, NV04_PRAMIN + i);
153 return 0; 155 return 0;
154} 156}
155 157
@@ -157,14 +159,15 @@ void
157nvc0_instmem_resume(struct drm_device *dev) 159nvc0_instmem_resume(struct drm_device *dev)
158{ 160{
159 struct drm_nouveau_private *dev_priv = dev->dev_private; 161 struct drm_nouveau_private *dev_priv = dev->dev_private;
162 u32 *buf = dev_priv->susres.ramin_copy;
160 u64 chan; 163 u64 chan;
161 int i; 164 int i;
162 165
163 chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram; 166 chan = dev_priv->vram_size - dev_priv->ramin_rsvd_vram;
164 nv_wr32(dev, 0x001700, chan >> 16); 167 nv_wr32(dev, 0x001700, chan >> 16);
165 168
166 for (i = 0x700000; i < 0x710000; i += 4) 169 for (i = 0; i < 65536; i += 4)
167 nv_wr32(dev, i, dev_priv->susres.ramin_copy[i/4]); 170 nv_wr32(dev, NV04_PRAMIN + i, buf[i/4]);
168 vfree(dev_priv->susres.ramin_copy); 171 vfree(dev_priv->susres.ramin_copy);
169 dev_priv->susres.ramin_copy = NULL; 172 dev_priv->susres.ramin_copy = NULL;
170 173
@@ -221,7 +224,7 @@ nvc0_instmem_init(struct drm_device *dev)
221 /*XXX: incorrect, but needed to make hash func "work" */ 224 /*XXX: incorrect, but needed to make hash func "work" */
222 dev_priv->ramht_offset = 0x10000; 225 dev_priv->ramht_offset = 0x10000;
223 dev_priv->ramht_bits = 9; 226 dev_priv->ramht_bits = 9;
224 dev_priv->ramht_size = (1 << dev_priv->ramht_bits); 227 dev_priv->ramht_size = (1 << dev_priv->ramht_bits) * 8;
225 return 0; 228 return 0;
226} 229}
227 230