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path: root/drivers/gpu/drm/nouveau/nva3_pm.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nva3_pm.c')
-rw-r--r--drivers/gpu/drm/nouveau/nva3_pm.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/nouveau/nva3_pm.c b/drivers/gpu/drm/nouveau/nva3_pm.c
index 618c144b7a3..9e636e6ef6d 100644
--- a/drivers/gpu/drm/nouveau/nva3_pm.c
+++ b/drivers/gpu/drm/nouveau/nva3_pm.c
@@ -287,12 +287,13 @@ nva3_pm_grcp_idle(void *data)
287 return false; 287 return false;
288} 288}
289 289
290void 290int
291nva3_pm_clocks_set(struct drm_device *dev, void *pre_state) 291nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
292{ 292{
293 struct drm_nouveau_private *dev_priv = dev->dev_private; 293 struct drm_nouveau_private *dev_priv = dev->dev_private;
294 struct nva3_pm_state *info = pre_state; 294 struct nva3_pm_state *info = pre_state;
295 unsigned long flags; 295 unsigned long flags;
296 int ret = -EAGAIN;
296 297
297 /* prevent any new grctx switches from starting */ 298 /* prevent any new grctx switches from starting */
298 spin_lock_irqsave(&dev_priv->context_switch_lock, flags); 299 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
@@ -328,6 +329,8 @@ nva3_pm_clocks_set(struct drm_device *dev, void *pre_state)
328 nv_wr32(dev, 0x100210, 0x80000000); 329 nv_wr32(dev, 0x100210, 0x80000000);
329 } 330 }
330 331
332 ret = 0;
333
331cleanup: 334cleanup:
332 /* unfreeze PFIFO */ 335 /* unfreeze PFIFO */
333 nv_mask(dev, 0x002504, 0x00000001, 0x00000000); 336 nv_mask(dev, 0x002504, 0x00000001, 0x00000000);
@@ -339,4 +342,5 @@ cleanup:
339 nv_mask(dev, 0x400824, 0x10000000, 0x10000000); 342 nv_mask(dev, 0x400824, 0x10000000, 0x10000000);
340 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); 343 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
341 kfree(info); 344 kfree(info);
345 return ret;
342} 346}