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path: root/drivers/gpu/drm/nouveau/nv84_crypt.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv84_crypt.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv84_crypt.c205
1 files changed, 0 insertions, 205 deletions
diff --git a/drivers/gpu/drm/nouveau/nv84_crypt.c b/drivers/gpu/drm/nouveau/nv84_crypt.c
deleted file mode 100644
index dc2bc5cc536..00000000000
--- a/drivers/gpu/drm/nouveau/nv84_crypt.c
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * Copyright 2010 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <drm/drmP.h>
26#include "nouveau_drv.h"
27#include "nouveau_util.h"
28#include "nouveau_vm.h"
29#include "nouveau_ramht.h"
30
31struct nv84_crypt_engine {
32 struct nouveau_exec_engine base;
33};
34
35static int
36nv84_crypt_context_new(struct nouveau_channel *chan, int engine)
37{
38 struct drm_device *dev = chan->dev;
39 struct drm_nouveau_private *dev_priv = dev->dev_private;
40 struct nouveau_gpuobj *ramin = chan->ramin;
41 struct nouveau_gpuobj *ctx;
42 int ret;
43
44 NV_DEBUG(dev, "ch%d\n", chan->id);
45
46 ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC |
47 NVOBJ_FLAG_ZERO_FREE, &ctx);
48 if (ret)
49 return ret;
50
51 nv_wo32(ramin, 0xa0, 0x00190000);
52 nv_wo32(ramin, 0xa4, ctx->vinst + ctx->size - 1);
53 nv_wo32(ramin, 0xa8, ctx->vinst);
54 nv_wo32(ramin, 0xac, 0);
55 nv_wo32(ramin, 0xb0, 0);
56 nv_wo32(ramin, 0xb4, 0);
57 dev_priv->engine.instmem.flush(dev);
58
59 atomic_inc(&chan->vm->engref[engine]);
60 chan->engctx[engine] = ctx;
61 return 0;
62}
63
64static void
65nv84_crypt_context_del(struct nouveau_channel *chan, int engine)
66{
67 struct nouveau_gpuobj *ctx = chan->engctx[engine];
68 struct drm_device *dev = chan->dev;
69 u32 inst;
70
71 inst = (chan->ramin->vinst >> 12);
72 inst |= 0x80000000;
73
74 /* mark context as invalid if still on the hardware, not
75 * doing this causes issues the next time PCRYPT is used,
76 * unsurprisingly :)
77 */
78 nv_wr32(dev, 0x10200c, 0x00000000);
79 if (nv_rd32(dev, 0x102188) == inst)
80 nv_mask(dev, 0x102188, 0x80000000, 0x00000000);
81 if (nv_rd32(dev, 0x10218c) == inst)
82 nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
83 nv_wr32(dev, 0x10200c, 0x00000010);
84
85 nouveau_gpuobj_ref(NULL, &ctx);
86
87 atomic_dec(&chan->vm->engref[engine]);
88 chan->engctx[engine] = NULL;
89}
90
91static int
92nv84_crypt_object_new(struct nouveau_channel *chan, int engine,
93 u32 handle, u16 class)
94{
95 struct drm_device *dev = chan->dev;
96 struct drm_nouveau_private *dev_priv = dev->dev_private;
97 struct nouveau_gpuobj *obj = NULL;
98 int ret;
99
100 ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
101 if (ret)
102 return ret;
103 obj->engine = 5;
104 obj->class = class;
105
106 nv_wo32(obj, 0x00, class);
107 dev_priv->engine.instmem.flush(dev);
108
109 ret = nouveau_ramht_insert(chan, handle, obj);
110 nouveau_gpuobj_ref(NULL, &obj);
111 return ret;
112}
113
114static void
115nv84_crypt_tlb_flush(struct drm_device *dev, int engine)
116{
117 nv50_vm_flush_engine(dev, 0x0a);
118}
119
120static struct nouveau_bitfield nv84_crypt_intr[] = {
121 { 0x00000001, "INVALID_STATE" },
122 { 0x00000002, "ILLEGAL_MTHD" },
123 { 0x00000004, "ILLEGAL_CLASS" },
124 { 0x00000080, "QUERY" },
125 { 0x00000100, "FAULT" },
126 {}
127};
128
129static void
130nv84_crypt_isr(struct drm_device *dev)
131{
132 u32 stat = nv_rd32(dev, 0x102130);
133 u32 mthd = nv_rd32(dev, 0x102190);
134 u32 data = nv_rd32(dev, 0x102194);
135 u64 inst = (u64)(nv_rd32(dev, 0x102188) & 0x7fffffff) << 12;
136 int show = nouveau_ratelimit();
137 int chid = nv50_graph_isr_chid(dev, inst);
138
139 if (show) {
140 NV_INFO(dev, "PCRYPT:");
141 nouveau_bitfield_print(nv84_crypt_intr, stat);
142 printk(KERN_CONT " ch %d (0x%010llx) mthd 0x%04x data 0x%08x\n",
143 chid, inst, mthd, data);
144 }
145
146 nv_wr32(dev, 0x102130, stat);
147 nv_wr32(dev, 0x10200c, 0x10);
148
149 nv50_fb_vm_trap(dev, show);
150}
151
152static int
153nv84_crypt_fini(struct drm_device *dev, int engine, bool suspend)
154{
155 nv_wr32(dev, 0x102140, 0x00000000);
156 return 0;
157}
158
159static int
160nv84_crypt_init(struct drm_device *dev, int engine)
161{
162 nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
163 nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
164
165 nv_wr32(dev, 0x102130, 0xffffffff);
166 nv_wr32(dev, 0x102140, 0xffffffbf);
167
168 nv_wr32(dev, 0x10200c, 0x00000010);
169 return 0;
170}
171
172static void
173nv84_crypt_destroy(struct drm_device *dev, int engine)
174{
175 struct nv84_crypt_engine *pcrypt = nv_engine(dev, engine);
176
177 NVOBJ_ENGINE_DEL(dev, CRYPT);
178
179 nouveau_irq_unregister(dev, 14);
180 kfree(pcrypt);
181}
182
183int
184nv84_crypt_create(struct drm_device *dev)
185{
186 struct nv84_crypt_engine *pcrypt;
187
188 pcrypt = kzalloc(sizeof(*pcrypt), GFP_KERNEL);
189 if (!pcrypt)
190 return -ENOMEM;
191
192 pcrypt->base.destroy = nv84_crypt_destroy;
193 pcrypt->base.init = nv84_crypt_init;
194 pcrypt->base.fini = nv84_crypt_fini;
195 pcrypt->base.context_new = nv84_crypt_context_new;
196 pcrypt->base.context_del = nv84_crypt_context_del;
197 pcrypt->base.object_new = nv84_crypt_object_new;
198 pcrypt->base.tlb_flush = nv84_crypt_tlb_flush;
199
200 nouveau_irq_register(dev, 14, nv84_crypt_isr);
201
202 NVOBJ_ENGINE_ADD(dev, CRYPT, &pcrypt->base);
203 NVOBJ_CLASS (dev, 0x74c1, CRYPT);
204 return 0;
205}
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