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path: root/drivers/gpu/drm/nouveau/nv10_fence.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv10_fence.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv10_fence.c63
1 files changed, 31 insertions, 32 deletions
diff --git a/drivers/gpu/drm/nouveau/nv10_fence.c b/drivers/gpu/drm/nouveau/nv10_fence.c
index dd7f17dd990..ce752bf5cc4 100644
--- a/drivers/gpu/drm/nouveau/nv10_fence.c
+++ b/drivers/gpu/drm/nouveau/nv10_fence.c
@@ -22,10 +22,11 @@
22 * Authors: Ben Skeggs <bskeggs@redhat.com> 22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */ 23 */
24 24
25#include "drmP.h" 25#include <core/object.h>
26#include "nouveau_drv.h" 26#include <core/class.h>
27
28#include "nouveau_drm.h"
27#include "nouveau_dma.h" 29#include "nouveau_dma.h"
28#include <core/ramht.h>
29#include "nouveau_fence.h" 30#include "nouveau_fence.h"
30 31
31struct nv10_fence_chan { 32struct nv10_fence_chan {
@@ -64,12 +65,11 @@ int
64nv17_fence_sync(struct nouveau_fence *fence, 65nv17_fence_sync(struct nouveau_fence *fence,
65 struct nouveau_channel *prev, struct nouveau_channel *chan) 66 struct nouveau_channel *prev, struct nouveau_channel *chan)
66{ 67{
67 struct drm_nouveau_private *dev_priv = chan->dev->dev_private; 68 struct nv10_fence_priv *priv = chan->drm->fence;
68 struct nv10_fence_priv *priv = dev_priv->fence.func;
69 u32 value; 69 u32 value;
70 int ret; 70 int ret;
71 71
72 if (!mutex_trylock(&prev->mutex)) 72 if (!mutex_trylock(&prev->cli->mutex))
73 return -EBUSY; 73 return -EBUSY;
74 74
75 spin_lock(&priv->lock); 75 spin_lock(&priv->lock);
@@ -96,14 +96,14 @@ nv17_fence_sync(struct nouveau_fence *fence,
96 FIRE_RING (chan); 96 FIRE_RING (chan);
97 } 97 }
98 98
99 mutex_unlock(&prev->mutex); 99 mutex_unlock(&prev->cli->mutex);
100 return 0; 100 return 0;
101} 101}
102 102
103u32 103u32
104nv10_fence_read(struct nouveau_channel *chan) 104nv10_fence_read(struct nouveau_channel *chan)
105{ 105{
106 return nvchan_rd32(chan, 0x0048); 106 return nv_ro32(chan->object, 0x0048);
107} 107}
108 108
109void 109void
@@ -118,10 +118,8 @@ nv10_fence_context_del(struct nouveau_channel *chan)
118static int 118static int
119nv10_fence_context_new(struct nouveau_channel *chan) 119nv10_fence_context_new(struct nouveau_channel *chan)
120{ 120{
121 struct drm_nouveau_private *dev_priv = chan->dev->dev_private; 121 struct nv10_fence_priv *priv = chan->drm->fence;
122 struct nv10_fence_priv *priv = dev_priv->fence.func;
123 struct nv10_fence_chan *fctx; 122 struct nv10_fence_chan *fctx;
124 struct nouveau_gpuobj *obj;
125 int ret = 0; 123 int ret = 0;
126 124
127 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); 125 fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
@@ -132,15 +130,19 @@ nv10_fence_context_new(struct nouveau_channel *chan)
132 130
133 if (priv->bo) { 131 if (priv->bo) {
134 struct ttm_mem_reg *mem = &priv->bo->bo.mem; 132 struct ttm_mem_reg *mem = &priv->bo->bo.mem;
135 133 struct nouveau_object *object;
136 ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_FROM_MEMORY, 134 u32 start = mem->start * PAGE_SIZE;
137 mem->start * PAGE_SIZE, mem->size, 135 u32 limit = mem->start + mem->size - 1;
138 NV_MEM_ACCESS_RW, 136
139 NV_MEM_TARGET_VRAM, &obj); 137 ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
140 if (!ret) { 138 NvSema, 0x0002,
141 ret = nouveau_ramht_insert(chan, NvSema, obj); 139 &(struct nv_dma_class) {
142 nouveau_gpuobj_ref(NULL, &obj); 140 .flags = NV_DMA_TARGET_VRAM |
143 } 141 NV_DMA_ACCESS_RDWR,
142 .start = start,
143 .limit = limit,
144 }, sizeof(struct nv_dma_class),
145 &object);
144 } 146 }
145 147
146 if (ret) 148 if (ret)
@@ -149,24 +151,22 @@ nv10_fence_context_new(struct nouveau_channel *chan)
149} 151}
150 152
151void 153void
152nv10_fence_destroy(struct drm_device *dev) 154nv10_fence_destroy(struct nouveau_drm *drm)
153{ 155{
154 struct drm_nouveau_private *dev_priv = dev->dev_private; 156 struct nv10_fence_priv *priv = drm->fence;
155 struct nv10_fence_priv *priv = dev_priv->fence.func; 157 nouveau_bo_unmap(priv->bo);
156
157 nouveau_bo_ref(NULL, &priv->bo); 158 nouveau_bo_ref(NULL, &priv->bo);
158 dev_priv->fence.func = NULL; 159 drm->fence = NULL;
159 kfree(priv); 160 kfree(priv);
160} 161}
161 162
162int 163int
163nv10_fence_create(struct drm_device *dev) 164nv10_fence_create(struct nouveau_drm *drm)
164{ 165{
165 struct drm_nouveau_private *dev_priv = dev->dev_private;
166 struct nv10_fence_priv *priv; 166 struct nv10_fence_priv *priv;
167 int ret = 0; 167 int ret = 0;
168 168
169 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 169 priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
170 if (!priv) 170 if (!priv)
171 return -ENOMEM; 171 return -ENOMEM;
172 172
@@ -176,11 +176,10 @@ nv10_fence_create(struct drm_device *dev)
176 priv->base.emit = nv10_fence_emit; 176 priv->base.emit = nv10_fence_emit;
177 priv->base.read = nv10_fence_read; 177 priv->base.read = nv10_fence_read;
178 priv->base.sync = nv10_fence_sync; 178 priv->base.sync = nv10_fence_sync;
179 dev_priv->fence.func = &priv->base;
180 spin_lock_init(&priv->lock); 179 spin_lock_init(&priv->lock);
181 180
182 if (dev_priv->chipset >= 0x17) { 181 if (nv_device(drm->device)->chipset >= 0x17) {
183 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, 182 ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
184 0, 0x0000, NULL, &priv->bo); 183 0, 0x0000, NULL, &priv->bo);
185 if (!ret) { 184 if (!ret) {
186 ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM); 185 ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
@@ -197,6 +196,6 @@ nv10_fence_create(struct drm_device *dev)
197 } 196 }
198 197
199 if (ret) 198 if (ret)
200 nv10_fence_destroy(dev); 199 nv10_fence_destroy(drm);
201 return ret; 200 return ret;
202} 201}