diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv10_fb.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv10_fb.c | 48 |
1 files changed, 33 insertions, 15 deletions
diff --git a/drivers/gpu/drm/nouveau/nv10_fb.c b/drivers/gpu/drm/nouveau/nv10_fb.c index cc5cda44e50..d50acc6a90d 100644 --- a/drivers/gpu/drm/nouveau/nv10_fb.c +++ b/drivers/gpu/drm/nouveau/nv10_fb.c | |||
@@ -4,22 +4,40 @@ | |||
4 | #include "nouveau_drm.h" | 4 | #include "nouveau_drm.h" |
5 | 5 | ||
6 | void | 6 | void |
7 | nv10_fb_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, | 7 | nv10_fb_init_tile_region(struct drm_device *dev, int i, uint32_t addr, |
8 | uint32_t size, uint32_t pitch) | 8 | uint32_t size, uint32_t pitch, uint32_t flags) |
9 | { | 9 | { |
10 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 10 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
11 | uint32_t limit = max(1u, addr + size) - 1; | 11 | struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; |
12 | 12 | ||
13 | if (pitch) { | 13 | tile->addr = addr; |
14 | if (dev_priv->card_type >= NV_20) | 14 | tile->limit = max(1u, addr + size) - 1; |
15 | addr |= 1; | 15 | tile->pitch = pitch; |
16 | else | 16 | |
17 | addr |= 1 << 31; | 17 | if (dev_priv->card_type == NV_20) |
18 | } | 18 | tile->addr |= 1; |
19 | 19 | else | |
20 | nv_wr32(dev, NV10_PFB_TLIMIT(i), limit); | 20 | tile->addr |= 1 << 31; |
21 | nv_wr32(dev, NV10_PFB_TSIZE(i), pitch); | 21 | } |
22 | nv_wr32(dev, NV10_PFB_TILE(i), addr); | 22 | |
23 | void | ||
24 | nv10_fb_free_tile_region(struct drm_device *dev, int i) | ||
25 | { | ||
26 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
27 | struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; | ||
28 | |||
29 | tile->addr = tile->limit = tile->pitch = 0; | ||
30 | } | ||
31 | |||
32 | void | ||
33 | nv10_fb_set_tile_region(struct drm_device *dev, int i) | ||
34 | { | ||
35 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
36 | struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; | ||
37 | |||
38 | nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit); | ||
39 | nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch); | ||
40 | nv_wr32(dev, NV10_PFB_TILE(i), tile->addr); | ||
23 | } | 41 | } |
24 | 42 | ||
25 | int | 43 | int |
@@ -33,7 +51,7 @@ nv10_fb_init(struct drm_device *dev) | |||
33 | 51 | ||
34 | /* Turn all the tiling regions off. */ | 52 | /* Turn all the tiling regions off. */ |
35 | for (i = 0; i < pfb->num_tiles; i++) | 53 | for (i = 0; i < pfb->num_tiles; i++) |
36 | pfb->set_region_tiling(dev, i, 0, 0, 0); | 54 | pfb->set_tile_region(dev, i); |
37 | 55 | ||
38 | return 0; | 56 | return 0; |
39 | } | 57 | } |