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path: root/drivers/gpu/drm/nouveau/nv04_fbcon.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nv04_fbcon.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv04_fbcon.c70
1 files changed, 36 insertions, 34 deletions
diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c
index 06fb68acf81..35480b6776f 100644
--- a/drivers/gpu/drm/nouveau/nv04_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c
@@ -22,19 +22,18 @@
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24 24
25#include "drmP.h" 25#include <core/object.h>
26#include "nouveau_drv.h" 26
27#include "nouveau_drm.h"
27#include "nouveau_dma.h" 28#include "nouveau_dma.h"
28#include <core/ramht.h>
29#include "nouveau_fbcon.h" 29#include "nouveau_fbcon.h"
30 30
31int 31int
32nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region) 32nv04_fbcon_copyarea(struct fb_info *info, const struct fb_copyarea *region)
33{ 33{
34 struct nouveau_fbdev *nfbdev = info->par; 34 struct nouveau_fbdev *nfbdev = info->par;
35 struct drm_device *dev = nfbdev->dev; 35 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev);
36 struct drm_nouveau_private *dev_priv = dev->dev_private; 36 struct nouveau_channel *chan = drm->channel;
37 struct nouveau_channel *chan = dev_priv->channel;
38 int ret; 37 int ret;
39 38
40 ret = RING_SPACE(chan, 4); 39 ret = RING_SPACE(chan, 4);
@@ -53,9 +52,8 @@ int
53nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect) 52nv04_fbcon_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
54{ 53{
55 struct nouveau_fbdev *nfbdev = info->par; 54 struct nouveau_fbdev *nfbdev = info->par;
56 struct drm_device *dev = nfbdev->dev; 55 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev);
57 struct drm_nouveau_private *dev_priv = dev->dev_private; 56 struct nouveau_channel *chan = drm->channel;
58 struct nouveau_channel *chan = dev_priv->channel;
59 int ret; 57 int ret;
60 58
61 ret = RING_SPACE(chan, 7); 59 ret = RING_SPACE(chan, 7);
@@ -81,9 +79,8 @@ int
81nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) 79nv04_fbcon_imageblit(struct fb_info *info, const struct fb_image *image)
82{ 80{
83 struct nouveau_fbdev *nfbdev = info->par; 81 struct nouveau_fbdev *nfbdev = info->par;
84 struct drm_device *dev = nfbdev->dev; 82 struct nouveau_drm *drm = nouveau_newpriv(nfbdev->dev);
85 struct drm_nouveau_private *dev_priv = dev->dev_private; 83 struct nouveau_channel *chan = drm->channel;
86 struct nouveau_channel *chan = dev_priv->channel;
87 uint32_t fg; 84 uint32_t fg;
88 uint32_t bg; 85 uint32_t bg;
89 uint32_t dsize; 86 uint32_t dsize;
@@ -142,9 +139,10 @@ nv04_fbcon_accel_init(struct fb_info *info)
142{ 139{
143 struct nouveau_fbdev *nfbdev = info->par; 140 struct nouveau_fbdev *nfbdev = info->par;
144 struct drm_device *dev = nfbdev->dev; 141 struct drm_device *dev = nfbdev->dev;
145 struct drm_nouveau_private *dev_priv = dev->dev_private; 142 struct nouveau_drm *drm = nouveau_newpriv(dev);
146 struct nouveau_channel *chan = dev_priv->channel; 143 struct nouveau_channel *chan = drm->channel;
147 const int sub = NvSubCtxSurf2D; 144 struct nouveau_device *device = nv_device(drm->device);
145 struct nouveau_object *object;
148 int surface_fmt, pattern_fmt, rect_fmt; 146 int surface_fmt, pattern_fmt, rect_fmt;
149 int ret; 147 int ret;
150 148
@@ -176,31 +174,35 @@ nv04_fbcon_accel_init(struct fb_info *info)
176 return -EINVAL; 174 return -EINVAL;
177 } 175 }
178 176
179 ret = nouveau_gpuobj_gr_new(chan, NvCtxSurf2D, 177 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvCtxSurf2D,
180 dev_priv->card_type >= NV_10 ? 178 device->card_type >= NV_10 ? 0x0062 : 0x0042,
181 0x0062 : 0x0042); 179 NULL, 0, &object);
182 if (ret) 180 if (ret)
183 return ret; 181 return ret;
184 182
185 ret = nouveau_gpuobj_gr_new(chan, NvClipRect, 0x0019); 183 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvClipRect,
184 0x0019, NULL, 0, &object);
186 if (ret) 185 if (ret)
187 return ret; 186 return ret;
188 187
189 ret = nouveau_gpuobj_gr_new(chan, NvRop, 0x0043); 188 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvRop,
189 0x0043, NULL, 0, &object);
190 if (ret) 190 if (ret)
191 return ret; 191 return ret;
192 192
193 ret = nouveau_gpuobj_gr_new(chan, NvImagePatt, 0x0044); 193 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvImagePatt,
194 0x0044, NULL, 0, &object);
194 if (ret) 195 if (ret)
195 return ret; 196 return ret;
196 197
197 ret = nouveau_gpuobj_gr_new(chan, NvGdiRect, 0x004a); 198 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvGdiRect,
199 0x004a, NULL, 0, &object);
198 if (ret) 200 if (ret)
199 return ret; 201 return ret;
200 202
201 ret = nouveau_gpuobj_gr_new(chan, NvImageBlit, 203 ret = nouveau_object_new(nv_object(chan->cli), NVDRM_CHAN, NvImageBlit,
202 dev_priv->chipset >= 0x11 ? 204 device->chipset >= 0x11 ? 0x009f : 0x005f,
203 0x009f : 0x005f); 205 NULL, 0, &object);
204 if (ret) 206 if (ret)
205 return ret; 207 return ret;
206 208
@@ -209,25 +211,25 @@ nv04_fbcon_accel_init(struct fb_info *info)
209 return 0; 211 return 0;
210 } 212 }
211 213
212 BEGIN_NV04(chan, sub, 0x0000, 1); 214 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
213 OUT_RING(chan, NvCtxSurf2D); 215 OUT_RING(chan, NvCtxSurf2D);
214 BEGIN_NV04(chan, sub, 0x0184, 2); 216 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0184, 2);
215 OUT_RING(chan, NvDmaFB); 217 OUT_RING(chan, NvDmaFB);
216 OUT_RING(chan, NvDmaFB); 218 OUT_RING(chan, NvDmaFB);
217 BEGIN_NV04(chan, sub, 0x0300, 4); 219 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 4);
218 OUT_RING(chan, surface_fmt); 220 OUT_RING(chan, surface_fmt);
219 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); 221 OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16));
220 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); 222 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
221 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base); 223 OUT_RING(chan, info->fix.smem_start - dev->mode_config.fb_base);
222 224
223 BEGIN_NV04(chan, sub, 0x0000, 1); 225 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
224 OUT_RING(chan, NvRop); 226 OUT_RING(chan, NvRop);
225 BEGIN_NV04(chan, sub, 0x0300, 1); 227 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 1);
226 OUT_RING(chan, 0x55); 228 OUT_RING(chan, 0x55);
227 229
228 BEGIN_NV04(chan, sub, 0x0000, 1); 230 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
229 OUT_RING(chan, NvImagePatt); 231 OUT_RING(chan, NvImagePatt);
230 BEGIN_NV04(chan, sub, 0x0300, 8); 232 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 8);
231 OUT_RING(chan, pattern_fmt); 233 OUT_RING(chan, pattern_fmt);
232#ifdef __BIG_ENDIAN 234#ifdef __BIG_ENDIAN
233 OUT_RING(chan, 2); 235 OUT_RING(chan, 2);
@@ -241,9 +243,9 @@ nv04_fbcon_accel_init(struct fb_info *info)
241 OUT_RING(chan, ~0); 243 OUT_RING(chan, ~0);
242 OUT_RING(chan, ~0); 244 OUT_RING(chan, ~0);
243 245
244 BEGIN_NV04(chan, sub, 0x0000, 1); 246 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0000, 1);
245 OUT_RING(chan, NvClipRect); 247 OUT_RING(chan, NvClipRect);
246 BEGIN_NV04(chan, sub, 0x0300, 2); 248 BEGIN_NV04(chan, NvSubCtxSurf2D, 0x0300, 2);
247 OUT_RING(chan, 0); 249 OUT_RING(chan, 0);
248 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual); 250 OUT_RING(chan, (info->var.yres_virtual << 16) | info->var.xres_virtual);
249 251