1 files changed, 115 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.h b/drivers/gpu/drm/nouveau/nouveau_vm.h
new file mode 100644
index 00000000000..579ca8cc223
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_vm.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#ifndef __NOUVEAU_VM_H__
+#define __NOUVEAU_VM_H__
+#include "drmP.h"
+#include "nouveau_drv.h"
+#include "nouveau_mm.h"
+struct nouveau_vm_pgt {
+        struct nouveau_gpuobj *obj[2];
+        u32 refcount[2];
+};
+struct nouveau_vm_pgd {
+        struct list_head head;
+        struct nouveau_gpuobj *obj;
+};
+struct nouveau_vma {
+        struct list_head head;
+        int refcount;
+        struct nouveau_vm *vm;
+        struct nouveau_mm_node *node;
+        u64 offset;
+        u32 access;
+};
+struct nouveau_vm {
+        struct drm_device *dev;
+        struct nouveau_mm *mm;
+        int refcount;
+        struct list_head pgd_list;
+        atomic_t engref[16];
+        struct nouveau_vm_pgt *pgt;
+        u32 fpde;
+        u32 lpde;
+        u32 pgt_bits;
+        u8  spg_shift;
+        u8  lpg_shift;
+        void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde,
+                        struct nouveau_gpuobj *pgt[2]);
+        void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *,
+                    struct nouveau_mem *, u32 pte, u32 cnt,
+                    u64 phys, u64 delta);
+        void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *,
+                       struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *);
+        void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt);
+        void (*flush)(struct nouveau_vm *);
+};
+/* nouveau_vm.c */
+int  nouveau_vm_new(struct drm_device *, u64 offset, u64 length, u64 mm_offset,
+                    struct nouveau_vm **);
+int  nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **,
+                    struct nouveau_gpuobj *pgd);
+int  nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift,
+                    u32 access, struct nouveau_vma *);
+void nouveau_vm_put(struct nouveau_vma *);
+void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *);
+void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *);
+void nouveau_vm_unmap(struct nouveau_vma *);
+void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length);
+void nouveau_vm_map_sg(struct nouveau_vma *, u64 offset, u64 length,
+                       struct nouveau_mem *, dma_addr_t *);
+/* nv50_vm.c */
+void nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
+                     struct nouveau_gpuobj *pgt[2]);
+void nv50_vm_map(struct nouveau_vma *, struct nouveau_gpuobj *,
+                 struct nouveau_mem *, u32 pte, u32 cnt, u64 phys, u64 delta);
+void nv50_vm_map_sg(struct nouveau_vma *, struct nouveau_gpuobj *,
+                    struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *);
+void nv50_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
+void nv50_vm_flush(struct nouveau_vm *);
+void nv50_vm_flush_engine(struct drm_device *, int engine);
+/* nvc0_vm.c */
+void nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
+                     struct nouveau_gpuobj *pgt[2]);
+void nvc0_vm_map(struct nouveau_vma *, struct nouveau_gpuobj *,
+                 struct nouveau_mem *, u32 pte, u32 cnt, u64 phys, u64 delta);
+void nvc0_vm_map_sg(struct nouveau_vma *, struct nouveau_gpuobj *,
+                    struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *);
+void nvc0_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
+void nvc0_vm_flush(struct nouveau_vm *);
+#endif

diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.h b/drivers/gpu/drm/nouveau/nouveau_vm.h new file mode 100644 index 00000000000..579ca8cc223 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nouveau_vm.h
@@ -0,0 +1,115 @@
	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#ifndef __NOUVEAU_VM_H__
	26	#define __NOUVEAU_VM_H__
	27
	28	#include "drmP.h"
	29
	30	#include "nouveau_drv.h"
	31	#include "nouveau_mm.h"
	32
	33	struct nouveau_vm_pgt {
	34	struct nouveau_gpuobj *obj[2];
	35	u32 refcount[2];
	36	};
	37
	38	struct nouveau_vm_pgd {
	39	struct list_head head;
	40	struct nouveau_gpuobj *obj;
	41	};
	42
	43	struct nouveau_vma {
	44	struct list_head head;
	45	int refcount;
	46	struct nouveau_vm *vm;
	47	struct nouveau_mm_node *node;
	48	u64 offset;
	49	u32 access;
	50	};
	51
	52	struct nouveau_vm {
	53	struct drm_device *dev;
	54	struct nouveau_mm *mm;
	55	int refcount;
	56
	57	struct list_head pgd_list;
	58	atomic_t engref[16];
	59
	60	struct nouveau_vm_pgt *pgt;
	61	u32 fpde;
	62	u32 lpde;
	63
	64	u32 pgt_bits;
	65	u8 spg_shift;
	66	u8 lpg_shift;
	67
	68	void (map_pgt)(struct nouveau_gpuobj pgd, u32 pde,
	69	struct nouveau_gpuobj *pgt[2]);
	70	void (map)(struct nouveau_vma , struct nouveau_gpuobj *,
	71	struct nouveau_mem *, u32 pte, u32 cnt,
	72	u64 phys, u64 delta);
	73	void (map_sg)(struct nouveau_vma , struct nouveau_gpuobj *,
	74	struct nouveau_mem , u32 pte, u32 cnt, dma_addr_t );
	75	void (unmap)(struct nouveau_gpuobj pgt, u32 pte, u32 cnt);
	76	void (flush)(struct nouveau_vm );
	77	};
	78
	79	/* nouveau_vm.c */
	80	int nouveau_vm_new(struct drm_device *, u64 offset, u64 length, u64 mm_offset,
	81	struct nouveau_vm **);
	82	int nouveau_vm_ref(struct nouveau_vm , struct nouveau_vm *,
	83	struct nouveau_gpuobj *pgd);
	84	int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift,
	85	u32 access, struct nouveau_vma *);
	86	void nouveau_vm_put(struct nouveau_vma *);
	87	void nouveau_vm_map(struct nouveau_vma , struct nouveau_mem );
	88	void nouveau_vm_map_at(struct nouveau_vma , u64 offset, struct nouveau_mem );
	89	void nouveau_vm_unmap(struct nouveau_vma *);
	90	void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length);
	91	void nouveau_vm_map_sg(struct nouveau_vma *, u64 offset, u64 length,
	92	struct nouveau_mem , dma_addr_t );
	93
	94	/* nv50_vm.c */
	95	void nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
	96	struct nouveau_gpuobj *pgt[2]);
	97	void nv50_vm_map(struct nouveau_vma , struct nouveau_gpuobj ,
	98	struct nouveau_mem *, u32 pte, u32 cnt, u64 phys, u64 delta);
	99	void nv50_vm_map_sg(struct nouveau_vma , struct nouveau_gpuobj ,
	100	struct nouveau_mem , u32 pte, u32 cnt, dma_addr_t );
	101	void nv50_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
	102	void nv50_vm_flush(struct nouveau_vm *);
	103	void nv50_vm_flush_engine(struct drm_device *, int engine);
	104
	105	/* nvc0_vm.c */
	106	void nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
	107	struct nouveau_gpuobj *pgt[2]);
	108	void nvc0_vm_map(struct nouveau_vma , struct nouveau_gpuobj ,
	109	struct nouveau_mem *, u32 pte, u32 cnt, u64 phys, u64 delta);
	110	void nvc0_vm_map_sg(struct nouveau_vma , struct nouveau_gpuobj ,
	111	struct nouveau_mem , u32 pte, u32 cnt, dma_addr_t );
	112	void nvc0_vm_unmap(struct nouveau_gpuobj *, u32 pte, u32 cnt);
	113	void nvc0_vm_flush(struct nouveau_vm *);
	114
	115	#endif