diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_drv.h')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_drv.h | 72 |
1 files changed, 57 insertions, 15 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 5f8cbb79c49..026419fe879 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h | |||
@@ -59,11 +59,19 @@ struct nouveau_grctx; | |||
59 | #define MAX_NUM_DCB_ENTRIES 16 | 59 | #define MAX_NUM_DCB_ENTRIES 16 |
60 | 60 | ||
61 | #define NOUVEAU_MAX_CHANNEL_NR 128 | 61 | #define NOUVEAU_MAX_CHANNEL_NR 128 |
62 | #define NOUVEAU_MAX_TILE_NR 15 | ||
62 | 63 | ||
63 | #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) | 64 | #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) |
64 | #define NV50_VM_BLOCK (512*1024*1024ULL) | 65 | #define NV50_VM_BLOCK (512*1024*1024ULL) |
65 | #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) | 66 | #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) |
66 | 67 | ||
68 | struct nouveau_tile_reg { | ||
69 | struct nouveau_fence *fence; | ||
70 | uint32_t addr; | ||
71 | uint32_t size; | ||
72 | bool used; | ||
73 | }; | ||
74 | |||
67 | struct nouveau_bo { | 75 | struct nouveau_bo { |
68 | struct ttm_buffer_object bo; | 76 | struct ttm_buffer_object bo; |
69 | struct ttm_placement placement; | 77 | struct ttm_placement placement; |
@@ -83,6 +91,7 @@ struct nouveau_bo { | |||
83 | 91 | ||
84 | uint32_t tile_mode; | 92 | uint32_t tile_mode; |
85 | uint32_t tile_flags; | 93 | uint32_t tile_flags; |
94 | struct nouveau_tile_reg *tile; | ||
86 | 95 | ||
87 | struct drm_gem_object *gem; | 96 | struct drm_gem_object *gem; |
88 | struct drm_file *cpu_filp; | 97 | struct drm_file *cpu_filp; |
@@ -277,8 +286,13 @@ struct nouveau_timer_engine { | |||
277 | }; | 286 | }; |
278 | 287 | ||
279 | struct nouveau_fb_engine { | 288 | struct nouveau_fb_engine { |
289 | int num_tiles; | ||
290 | |||
280 | int (*init)(struct drm_device *dev); | 291 | int (*init)(struct drm_device *dev); |
281 | void (*takedown)(struct drm_device *dev); | 292 | void (*takedown)(struct drm_device *dev); |
293 | |||
294 | void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, | ||
295 | uint32_t size, uint32_t pitch); | ||
282 | }; | 296 | }; |
283 | 297 | ||
284 | struct nouveau_fifo_engine { | 298 | struct nouveau_fifo_engine { |
@@ -292,6 +306,8 @@ struct nouveau_fifo_engine { | |||
292 | void (*disable)(struct drm_device *); | 306 | void (*disable)(struct drm_device *); |
293 | void (*enable)(struct drm_device *); | 307 | void (*enable)(struct drm_device *); |
294 | bool (*reassign)(struct drm_device *, bool enable); | 308 | bool (*reassign)(struct drm_device *, bool enable); |
309 | bool (*cache_flush)(struct drm_device *dev); | ||
310 | bool (*cache_pull)(struct drm_device *dev, bool enable); | ||
295 | 311 | ||
296 | int (*channel_id)(struct drm_device *); | 312 | int (*channel_id)(struct drm_device *); |
297 | 313 | ||
@@ -330,6 +346,9 @@ struct nouveau_pgraph_engine { | |||
330 | void (*destroy_context)(struct nouveau_channel *); | 346 | void (*destroy_context)(struct nouveau_channel *); |
331 | int (*load_context)(struct nouveau_channel *); | 347 | int (*load_context)(struct nouveau_channel *); |
332 | int (*unload_context)(struct drm_device *); | 348 | int (*unload_context)(struct drm_device *); |
349 | |||
350 | void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, | ||
351 | uint32_t size, uint32_t pitch); | ||
333 | }; | 352 | }; |
334 | 353 | ||
335 | struct nouveau_engine { | 354 | struct nouveau_engine { |
@@ -548,6 +567,12 @@ struct drm_nouveau_private { | |||
548 | unsigned long sg_handle; | 567 | unsigned long sg_handle; |
549 | } gart_info; | 568 | } gart_info; |
550 | 569 | ||
570 | /* nv10-nv40 tiling regions */ | ||
571 | struct { | ||
572 | struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; | ||
573 | spinlock_t lock; | ||
574 | } tile; | ||
575 | |||
551 | /* G8x/G9x virtual address space */ | 576 | /* G8x/G9x virtual address space */ |
552 | uint64_t vm_gart_base; | 577 | uint64_t vm_gart_base; |
553 | uint64_t vm_gart_size; | 578 | uint64_t vm_gart_size; |
@@ -685,6 +710,13 @@ extern void nouveau_mem_release(struct drm_file *, struct mem_block *heap); | |||
685 | extern int nouveau_mem_init(struct drm_device *); | 710 | extern int nouveau_mem_init(struct drm_device *); |
686 | extern int nouveau_mem_init_agp(struct drm_device *); | 711 | extern int nouveau_mem_init_agp(struct drm_device *); |
687 | extern void nouveau_mem_close(struct drm_device *); | 712 | extern void nouveau_mem_close(struct drm_device *); |
713 | extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, | ||
714 | uint32_t addr, | ||
715 | uint32_t size, | ||
716 | uint32_t pitch); | ||
717 | extern void nv10_mem_expire_tiling(struct drm_device *dev, | ||
718 | struct nouveau_tile_reg *tile, | ||
719 | struct nouveau_fence *fence); | ||
688 | extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, | 720 | extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, |
689 | uint32_t size, uint32_t flags, | 721 | uint32_t size, uint32_t flags, |
690 | uint64_t phys); | 722 | uint64_t phys); |
@@ -713,7 +745,6 @@ extern int nouveau_channel_alloc(struct drm_device *dev, | |||
713 | struct drm_file *file_priv, | 745 | struct drm_file *file_priv, |
714 | uint32_t fb_ctxdma, uint32_t tt_ctxdma); | 746 | uint32_t fb_ctxdma, uint32_t tt_ctxdma); |
715 | extern void nouveau_channel_free(struct nouveau_channel *); | 747 | extern void nouveau_channel_free(struct nouveau_channel *); |
716 | extern int nouveau_channel_idle(struct nouveau_channel *chan); | ||
717 | 748 | ||
718 | /* nouveau_object.c */ | 749 | /* nouveau_object.c */ |
719 | extern int nouveau_gpuobj_early_init(struct drm_device *); | 750 | extern int nouveau_gpuobj_early_init(struct drm_device *); |
@@ -756,6 +787,8 @@ extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, | |||
756 | uint32_t *o_ret); | 787 | uint32_t *o_ret); |
757 | extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, | 788 | extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, |
758 | struct nouveau_gpuobj **); | 789 | struct nouveau_gpuobj **); |
790 | extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, | ||
791 | struct nouveau_gpuobj **); | ||
759 | extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, | 792 | extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, |
760 | struct drm_file *); | 793 | struct drm_file *); |
761 | extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, | 794 | extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, |
@@ -804,6 +837,7 @@ nouveau_debugfs_channel_fini(struct nouveau_channel *chan) | |||
804 | #endif | 837 | #endif |
805 | 838 | ||
806 | /* nouveau_dma.c */ | 839 | /* nouveau_dma.c */ |
840 | extern void nouveau_dma_pre_init(struct nouveau_channel *); | ||
807 | extern int nouveau_dma_init(struct nouveau_channel *); | 841 | extern int nouveau_dma_init(struct nouveau_channel *); |
808 | extern int nouveau_dma_wait(struct nouveau_channel *, int size); | 842 | extern int nouveau_dma_wait(struct nouveau_channel *, int size); |
809 | 843 | ||
@@ -879,16 +913,22 @@ extern void nv04_fb_takedown(struct drm_device *); | |||
879 | /* nv10_fb.c */ | 913 | /* nv10_fb.c */ |
880 | extern int nv10_fb_init(struct drm_device *); | 914 | extern int nv10_fb_init(struct drm_device *); |
881 | extern void nv10_fb_takedown(struct drm_device *); | 915 | extern void nv10_fb_takedown(struct drm_device *); |
916 | extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, | ||
917 | uint32_t, uint32_t); | ||
882 | 918 | ||
883 | /* nv40_fb.c */ | 919 | /* nv40_fb.c */ |
884 | extern int nv40_fb_init(struct drm_device *); | 920 | extern int nv40_fb_init(struct drm_device *); |
885 | extern void nv40_fb_takedown(struct drm_device *); | 921 | extern void nv40_fb_takedown(struct drm_device *); |
922 | extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, | ||
923 | uint32_t, uint32_t); | ||
886 | 924 | ||
887 | /* nv04_fifo.c */ | 925 | /* nv04_fifo.c */ |
888 | extern int nv04_fifo_init(struct drm_device *); | 926 | extern int nv04_fifo_init(struct drm_device *); |
889 | extern void nv04_fifo_disable(struct drm_device *); | 927 | extern void nv04_fifo_disable(struct drm_device *); |
890 | extern void nv04_fifo_enable(struct drm_device *); | 928 | extern void nv04_fifo_enable(struct drm_device *); |
891 | extern bool nv04_fifo_reassign(struct drm_device *, bool); | 929 | extern bool nv04_fifo_reassign(struct drm_device *, bool); |
930 | extern bool nv04_fifo_cache_flush(struct drm_device *); | ||
931 | extern bool nv04_fifo_cache_pull(struct drm_device *, bool); | ||
892 | extern int nv04_fifo_channel_id(struct drm_device *); | 932 | extern int nv04_fifo_channel_id(struct drm_device *); |
893 | extern int nv04_fifo_create_context(struct nouveau_channel *); | 933 | extern int nv04_fifo_create_context(struct nouveau_channel *); |
894 | extern void nv04_fifo_destroy_context(struct nouveau_channel *); | 934 | extern void nv04_fifo_destroy_context(struct nouveau_channel *); |
@@ -941,6 +981,8 @@ extern void nv10_graph_destroy_context(struct nouveau_channel *); | |||
941 | extern int nv10_graph_load_context(struct nouveau_channel *); | 981 | extern int nv10_graph_load_context(struct nouveau_channel *); |
942 | extern int nv10_graph_unload_context(struct drm_device *); | 982 | extern int nv10_graph_unload_context(struct drm_device *); |
943 | extern void nv10_graph_context_switch(struct drm_device *); | 983 | extern void nv10_graph_context_switch(struct drm_device *); |
984 | extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, | ||
985 | uint32_t, uint32_t); | ||
944 | 986 | ||
945 | /* nv20_graph.c */ | 987 | /* nv20_graph.c */ |
946 | extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; | 988 | extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; |
@@ -952,6 +994,8 @@ extern int nv20_graph_unload_context(struct drm_device *); | |||
952 | extern int nv20_graph_init(struct drm_device *); | 994 | extern int nv20_graph_init(struct drm_device *); |
953 | extern void nv20_graph_takedown(struct drm_device *); | 995 | extern void nv20_graph_takedown(struct drm_device *); |
954 | extern int nv30_graph_init(struct drm_device *); | 996 | extern int nv30_graph_init(struct drm_device *); |
997 | extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, | ||
998 | uint32_t, uint32_t); | ||
955 | 999 | ||
956 | /* nv40_graph.c */ | 1000 | /* nv40_graph.c */ |
957 | extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; | 1001 | extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; |
@@ -963,6 +1007,8 @@ extern void nv40_graph_destroy_context(struct nouveau_channel *); | |||
963 | extern int nv40_graph_load_context(struct nouveau_channel *); | 1007 | extern int nv40_graph_load_context(struct nouveau_channel *); |
964 | extern int nv40_graph_unload_context(struct drm_device *); | 1008 | extern int nv40_graph_unload_context(struct drm_device *); |
965 | extern void nv40_grctx_init(struct nouveau_grctx *); | 1009 | extern void nv40_grctx_init(struct nouveau_grctx *); |
1010 | extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, | ||
1011 | uint32_t, uint32_t); | ||
966 | 1012 | ||
967 | /* nv50_graph.c */ | 1013 | /* nv50_graph.c */ |
968 | extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; | 1014 | extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; |
@@ -1030,8 +1076,7 @@ extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, | |||
1030 | 1076 | ||
1031 | /* nv04_dac.c */ | 1077 | /* nv04_dac.c */ |
1032 | extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry); | 1078 | extern int nv04_dac_create(struct drm_device *dev, struct dcb_entry *entry); |
1033 | extern enum drm_connector_status nv17_dac_detect(struct drm_encoder *encoder, | 1079 | extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); |
1034 | struct drm_connector *connector); | ||
1035 | extern int nv04_dac_output_offset(struct drm_encoder *encoder); | 1080 | extern int nv04_dac_output_offset(struct drm_encoder *encoder); |
1036 | extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); | 1081 | extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); |
1037 | 1082 | ||
@@ -1049,9 +1094,6 @@ extern int nv04_tv_create(struct drm_device *dev, struct dcb_entry *entry); | |||
1049 | 1094 | ||
1050 | /* nv17_tv.c */ | 1095 | /* nv17_tv.c */ |
1051 | extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry); | 1096 | extern int nv17_tv_create(struct drm_device *dev, struct dcb_entry *entry); |
1052 | extern enum drm_connector_status nv17_tv_detect(struct drm_encoder *encoder, | ||
1053 | struct drm_connector *connector, | ||
1054 | uint32_t pin_mask); | ||
1055 | 1097 | ||
1056 | /* nv04_display.c */ | 1098 | /* nv04_display.c */ |
1057 | extern int nv04_display_create(struct drm_device *); | 1099 | extern int nv04_display_create(struct drm_device *); |
@@ -1290,14 +1332,14 @@ nv_two_reg_pll(struct drm_device *dev) | |||
1290 | return false; | 1332 | return false; |
1291 | } | 1333 | } |
1292 | 1334 | ||
1293 | #define NV50_NVSW 0x0000506e | 1335 | #define NV_SW 0x0000506e |
1294 | #define NV50_NVSW_DMA_SEMAPHORE 0x00000060 | 1336 | #define NV_SW_DMA_SEMAPHORE 0x00000060 |
1295 | #define NV50_NVSW_SEMAPHORE_OFFSET 0x00000064 | 1337 | #define NV_SW_SEMAPHORE_OFFSET 0x00000064 |
1296 | #define NV50_NVSW_SEMAPHORE_ACQUIRE 0x00000068 | 1338 | #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 |
1297 | #define NV50_NVSW_SEMAPHORE_RELEASE 0x0000006c | 1339 | #define NV_SW_SEMAPHORE_RELEASE 0x0000006c |
1298 | #define NV50_NVSW_DMA_VBLSEM 0x0000018c | 1340 | #define NV_SW_DMA_VBLSEM 0x0000018c |
1299 | #define NV50_NVSW_VBLSEM_OFFSET 0x00000400 | 1341 | #define NV_SW_VBLSEM_OFFSET 0x00000400 |
1300 | #define NV50_NVSW_VBLSEM_RELEASE_VALUE 0x00000404 | 1342 | #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 |
1301 | #define NV50_NVSW_VBLSEM_RELEASE 0x00000408 | 1343 | #define NV_SW_VBLSEM_RELEASE 0x00000408 |
1302 | 1344 | ||
1303 | #endif /* __NOUVEAU_DRV_H__ */ | 1345 | #endif /* __NOUVEAU_DRV_H__ */ |