diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_bios.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_bios.c | 366 |
1 files changed, 220 insertions, 146 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 974b0f8ae04..53f4eba65cb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c | |||
@@ -43,9 +43,6 @@ | |||
43 | #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) | 43 | #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg) |
44 | #define LOG_OLD_VALUE(x) | 44 | #define LOG_OLD_VALUE(x) |
45 | 45 | ||
46 | #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x)) | ||
47 | #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x)) | ||
48 | |||
49 | struct init_exec { | 46 | struct init_exec { |
50 | bool execute; | 47 | bool execute; |
51 | bool repeat; | 48 | bool repeat; |
@@ -272,12 +269,6 @@ struct init_tbl_entry { | |||
272 | int (*handler)(struct nvbios *, uint16_t, struct init_exec *); | 269 | int (*handler)(struct nvbios *, uint16_t, struct init_exec *); |
273 | }; | 270 | }; |
274 | 271 | ||
275 | struct bit_entry { | ||
276 | uint8_t id[2]; | ||
277 | uint16_t length; | ||
278 | uint16_t offset; | ||
279 | }; | ||
280 | |||
281 | static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); | 272 | static int parse_init_table(struct nvbios *, unsigned int, struct init_exec *); |
282 | 273 | ||
283 | #define MACRO_INDEX_SIZE 2 | 274 | #define MACRO_INDEX_SIZE 2 |
@@ -1231,7 +1222,7 @@ init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) | |||
1231 | return 3; | 1222 | return 3; |
1232 | } | 1223 | } |
1233 | 1224 | ||
1234 | if (cond & 1) | 1225 | if (!(cond & 1)) |
1235 | iexec->execute = false; | 1226 | iexec->execute = false; |
1236 | } | 1227 | } |
1237 | break; | 1228 | break; |
@@ -4675,6 +4666,92 @@ int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, i | |||
4675 | return 0; | 4666 | return 0; |
4676 | } | 4667 | } |
4677 | 4668 | ||
4669 | struct pll_mapping { | ||
4670 | u8 type; | ||
4671 | u32 reg; | ||
4672 | }; | ||
4673 | |||
4674 | static struct pll_mapping nv04_pll_mapping[] = { | ||
4675 | { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF }, | ||
4676 | { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF }, | ||
4677 | { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF }, | ||
4678 | { PLL_VPLL1 , NV_RAMDAC_VPLL2 }, | ||
4679 | {} | ||
4680 | }; | ||
4681 | |||
4682 | static struct pll_mapping nv40_pll_mapping[] = { | ||
4683 | { PLL_CORE , 0x004000 }, | ||
4684 | { PLL_MEMORY, 0x004020 }, | ||
4685 | { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF }, | ||
4686 | { PLL_VPLL1 , NV_RAMDAC_VPLL2 }, | ||
4687 | {} | ||
4688 | }; | ||
4689 | |||
4690 | static struct pll_mapping nv50_pll_mapping[] = { | ||
4691 | { PLL_CORE , 0x004028 }, | ||
4692 | { PLL_SHADER, 0x004020 }, | ||
4693 | { PLL_UNK03 , 0x004000 }, | ||
4694 | { PLL_MEMORY, 0x004008 }, | ||
4695 | { PLL_UNK40 , 0x00e810 }, | ||
4696 | { PLL_UNK41 , 0x00e818 }, | ||
4697 | { PLL_UNK42 , 0x00e824 }, | ||
4698 | { PLL_VPLL0 , 0x614100 }, | ||
4699 | { PLL_VPLL1 , 0x614900 }, | ||
4700 | {} | ||
4701 | }; | ||
4702 | |||
4703 | static struct pll_mapping nv84_pll_mapping[] = { | ||
4704 | { PLL_CORE , 0x004028 }, | ||
4705 | { PLL_SHADER, 0x004020 }, | ||
4706 | { PLL_MEMORY, 0x004008 }, | ||
4707 | { PLL_UNK05 , 0x004030 }, | ||
4708 | { PLL_UNK41 , 0x00e818 }, | ||
4709 | { PLL_VPLL0 , 0x614100 }, | ||
4710 | { PLL_VPLL1 , 0x614900 }, | ||
4711 | {} | ||
4712 | }; | ||
4713 | |||
4714 | u32 | ||
4715 | get_pll_register(struct drm_device *dev, enum pll_types type) | ||
4716 | { | ||
4717 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
4718 | struct nvbios *bios = &dev_priv->vbios; | ||
4719 | struct pll_mapping *map; | ||
4720 | int i; | ||
4721 | |||
4722 | if (dev_priv->card_type < NV_40) | ||
4723 | map = nv04_pll_mapping; | ||
4724 | else | ||
4725 | if (dev_priv->card_type < NV_50) | ||
4726 | map = nv40_pll_mapping; | ||
4727 | else { | ||
4728 | u8 *plim = &bios->data[bios->pll_limit_tbl_ptr]; | ||
4729 | |||
4730 | if (plim[0] >= 0x30) { | ||
4731 | u8 *entry = plim + plim[1]; | ||
4732 | for (i = 0; i < plim[3]; i++, entry += plim[2]) { | ||
4733 | if (entry[0] == type) | ||
4734 | return ROM32(entry[3]); | ||
4735 | } | ||
4736 | |||
4737 | return 0; | ||
4738 | } | ||
4739 | |||
4740 | if (dev_priv->chipset == 0x50) | ||
4741 | map = nv50_pll_mapping; | ||
4742 | else | ||
4743 | map = nv84_pll_mapping; | ||
4744 | } | ||
4745 | |||
4746 | while (map->reg) { | ||
4747 | if (map->type == type) | ||
4748 | return map->reg; | ||
4749 | map++; | ||
4750 | } | ||
4751 | |||
4752 | return 0; | ||
4753 | } | ||
4754 | |||
4678 | int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) | 4755 | int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim) |
4679 | { | 4756 | { |
4680 | /* | 4757 | /* |
@@ -4750,6 +4827,17 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims | |||
4750 | /* initialize all members to zero */ | 4827 | /* initialize all members to zero */ |
4751 | memset(pll_lim, 0, sizeof(struct pll_lims)); | 4828 | memset(pll_lim, 0, sizeof(struct pll_lims)); |
4752 | 4829 | ||
4830 | /* if we were passed a type rather than a register, figure | ||
4831 | * out the register and store it | ||
4832 | */ | ||
4833 | if (limit_match > PLL_MAX) | ||
4834 | pll_lim->reg = limit_match; | ||
4835 | else { | ||
4836 | pll_lim->reg = get_pll_register(dev, limit_match); | ||
4837 | if (!pll_lim->reg) | ||
4838 | return -ENOENT; | ||
4839 | } | ||
4840 | |||
4753 | if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { | 4841 | if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) { |
4754 | uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; | 4842 | uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex]; |
4755 | 4843 | ||
@@ -4785,7 +4873,6 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims | |||
4785 | pll_lim->max_usable_log2p = 0x6; | 4873 | pll_lim->max_usable_log2p = 0x6; |
4786 | } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { | 4874 | } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) { |
4787 | uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; | 4875 | uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen; |
4788 | uint32_t reg = 0; /* default match */ | ||
4789 | uint8_t *pll_rec; | 4876 | uint8_t *pll_rec; |
4790 | int i; | 4877 | int i; |
4791 | 4878 | ||
@@ -4797,37 +4884,22 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims | |||
4797 | NV_WARN(dev, "Default PLL limit entry has non-zero " | 4884 | NV_WARN(dev, "Default PLL limit entry has non-zero " |
4798 | "register field\n"); | 4885 | "register field\n"); |
4799 | 4886 | ||
4800 | if (limit_match > MAX_PLL_TYPES) | ||
4801 | /* we've been passed a reg as the match */ | ||
4802 | reg = limit_match; | ||
4803 | else /* limit match is a pll type */ | ||
4804 | for (i = 1; i < entries && !reg; i++) { | ||
4805 | uint32_t cmpreg = ROM32(bios->data[plloffs + recordlen * i]); | ||
4806 | |||
4807 | if (limit_match == NVPLL && | ||
4808 | (cmpreg == NV_PRAMDAC_NVPLL_COEFF || cmpreg == 0x4000)) | ||
4809 | reg = cmpreg; | ||
4810 | if (limit_match == MPLL && | ||
4811 | (cmpreg == NV_PRAMDAC_MPLL_COEFF || cmpreg == 0x4020)) | ||
4812 | reg = cmpreg; | ||
4813 | if (limit_match == VPLL1 && | ||
4814 | (cmpreg == NV_PRAMDAC_VPLL_COEFF || cmpreg == 0x4010)) | ||
4815 | reg = cmpreg; | ||
4816 | if (limit_match == VPLL2 && | ||
4817 | (cmpreg == NV_RAMDAC_VPLL2 || cmpreg == 0x4018)) | ||
4818 | reg = cmpreg; | ||
4819 | } | ||
4820 | |||
4821 | for (i = 1; i < entries; i++) | 4887 | for (i = 1; i < entries; i++) |
4822 | if (ROM32(bios->data[plloffs + recordlen * i]) == reg) { | 4888 | if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) { |
4823 | pllindex = i; | 4889 | pllindex = i; |
4824 | break; | 4890 | break; |
4825 | } | 4891 | } |
4826 | 4892 | ||
4893 | if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) { | ||
4894 | NV_ERROR(dev, "Register 0x%08x not found in PLL " | ||
4895 | "limits table", pll_lim->reg); | ||
4896 | return -ENOENT; | ||
4897 | } | ||
4898 | |||
4827 | pll_rec = &bios->data[plloffs + recordlen * pllindex]; | 4899 | pll_rec = &bios->data[plloffs + recordlen * pllindex]; |
4828 | 4900 | ||
4829 | BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", | 4901 | BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n", |
4830 | pllindex ? reg : 0); | 4902 | pllindex ? pll_lim->reg : 0); |
4831 | 4903 | ||
4832 | /* | 4904 | /* |
4833 | * Frequencies are stored in tables in MHz, kHz are more | 4905 | * Frequencies are stored in tables in MHz, kHz are more |
@@ -4877,8 +4949,8 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims | |||
4877 | if (cv == 0x51 && !pll_lim->refclk) { | 4949 | if (cv == 0x51 && !pll_lim->refclk) { |
4878 | uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); | 4950 | uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK); |
4879 | 4951 | ||
4880 | if (((limit_match == NV_PRAMDAC_VPLL_COEFF || limit_match == VPLL1) && sel_clk & 0x20) || | 4952 | if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) || |
4881 | ((limit_match == NV_RAMDAC_VPLL2 || limit_match == VPLL2) && sel_clk & 0x80)) { | 4953 | (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) { |
4882 | if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) | 4954 | if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3) |
4883 | pll_lim->refclk = 200000; | 4955 | pll_lim->refclk = 200000; |
4884 | else | 4956 | else |
@@ -4891,10 +4963,10 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims | |||
4891 | int i; | 4963 | int i; |
4892 | 4964 | ||
4893 | BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", | 4965 | BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", |
4894 | limit_match); | 4966 | pll_lim->reg); |
4895 | 4967 | ||
4896 | for (i = 0; i < entries; i++, entry += recordlen) { | 4968 | for (i = 0; i < entries; i++, entry += recordlen) { |
4897 | if (ROM32(entry[3]) == limit_match) { | 4969 | if (ROM32(entry[3]) == pll_lim->reg) { |
4898 | record = &bios->data[ROM16(entry[1])]; | 4970 | record = &bios->data[ROM16(entry[1])]; |
4899 | break; | 4971 | break; |
4900 | } | 4972 | } |
@@ -4902,7 +4974,7 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims | |||
4902 | 4974 | ||
4903 | if (!record) { | 4975 | if (!record) { |
4904 | NV_ERROR(dev, "Register 0x%08x not found in PLL " | 4976 | NV_ERROR(dev, "Register 0x%08x not found in PLL " |
4905 | "limits table", limit_match); | 4977 | "limits table", pll_lim->reg); |
4906 | return -ENOENT; | 4978 | return -ENOENT; |
4907 | } | 4979 | } |
4908 | 4980 | ||
@@ -4931,10 +5003,10 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims | |||
4931 | int i; | 5003 | int i; |
4932 | 5004 | ||
4933 | BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", | 5005 | BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n", |
4934 | limit_match); | 5006 | pll_lim->reg); |
4935 | 5007 | ||
4936 | for (i = 0; i < entries; i++, entry += recordlen) { | 5008 | for (i = 0; i < entries; i++, entry += recordlen) { |
4937 | if (ROM32(entry[3]) == limit_match) { | 5009 | if (ROM32(entry[3]) == pll_lim->reg) { |
4938 | record = &bios->data[ROM16(entry[1])]; | 5010 | record = &bios->data[ROM16(entry[1])]; |
4939 | break; | 5011 | break; |
4940 | } | 5012 | } |
@@ -4942,7 +5014,7 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims | |||
4942 | 5014 | ||
4943 | if (!record) { | 5015 | if (!record) { |
4944 | NV_ERROR(dev, "Register 0x%08x not found in PLL " | 5016 | NV_ERROR(dev, "Register 0x%08x not found in PLL " |
4945 | "limits table", limit_match); | 5017 | "limits table", pll_lim->reg); |
4946 | return -ENOENT; | 5018 | return -ENOENT; |
4947 | } | 5019 | } |
4948 | 5020 | ||
@@ -5293,7 +5365,7 @@ parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios, | |||
5293 | if (bitentry->length < 0x5) | 5365 | if (bitentry->length < 0x5) |
5294 | return 0; | 5366 | return 0; |
5295 | 5367 | ||
5296 | if (bitentry->id[1] < 2) { | 5368 | if (bitentry->version < 2) { |
5297 | bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; | 5369 | bios->ram_restrict_group_count = bios->data[bitentry->offset + 2]; |
5298 | bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); | 5370 | bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]); |
5299 | } else { | 5371 | } else { |
@@ -5403,27 +5475,40 @@ struct bit_table { | |||
5403 | 5475 | ||
5404 | #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) | 5476 | #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry }) |
5405 | 5477 | ||
5478 | int | ||
5479 | bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit) | ||
5480 | { | ||
5481 | struct drm_nouveau_private *dev_priv = dev->dev_private; | ||
5482 | struct nvbios *bios = &dev_priv->vbios; | ||
5483 | u8 entries, *entry; | ||
5484 | |||
5485 | entries = bios->data[bios->offset + 10]; | ||
5486 | entry = &bios->data[bios->offset + 12]; | ||
5487 | while (entries--) { | ||
5488 | if (entry[0] == id) { | ||
5489 | bit->id = entry[0]; | ||
5490 | bit->version = entry[1]; | ||
5491 | bit->length = ROM16(entry[2]); | ||
5492 | bit->offset = ROM16(entry[4]); | ||
5493 | bit->data = ROMPTR(bios, entry[4]); | ||
5494 | return 0; | ||
5495 | } | ||
5496 | |||
5497 | entry += bios->data[bios->offset + 9]; | ||
5498 | } | ||
5499 | |||
5500 | return -ENOENT; | ||
5501 | } | ||
5502 | |||
5406 | static int | 5503 | static int |
5407 | parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, | 5504 | parse_bit_table(struct nvbios *bios, const uint16_t bitoffset, |
5408 | struct bit_table *table) | 5505 | struct bit_table *table) |
5409 | { | 5506 | { |
5410 | struct drm_device *dev = bios->dev; | 5507 | struct drm_device *dev = bios->dev; |
5411 | uint8_t maxentries = bios->data[bitoffset + 4]; | ||
5412 | int i, offset; | ||
5413 | struct bit_entry bitentry; | 5508 | struct bit_entry bitentry; |
5414 | 5509 | ||
5415 | for (i = 0, offset = bitoffset + 6; i < maxentries; i++, offset += 6) { | 5510 | if (bit_table(dev, table->id, &bitentry) == 0) |
5416 | bitentry.id[0] = bios->data[offset]; | ||
5417 | |||
5418 | if (bitentry.id[0] != table->id) | ||
5419 | continue; | ||
5420 | |||
5421 | bitentry.id[1] = bios->data[offset + 1]; | ||
5422 | bitentry.length = ROM16(bios->data[offset + 2]); | ||
5423 | bitentry.offset = ROM16(bios->data[offset + 4]); | ||
5424 | |||
5425 | return table->parse_fn(dev, bios, &bitentry); | 5511 | return table->parse_fn(dev, bios, &bitentry); |
5426 | } | ||
5427 | 5512 | ||
5428 | NV_INFO(dev, "BIT table '%c' not found\n", table->id); | 5513 | NV_INFO(dev, "BIT table '%c' not found\n", table->id); |
5429 | return -ENOSYS; | 5514 | return -ENOSYS; |
@@ -5683,8 +5768,14 @@ static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) | |||
5683 | static struct dcb_gpio_entry * | 5768 | static struct dcb_gpio_entry * |
5684 | new_gpio_entry(struct nvbios *bios) | 5769 | new_gpio_entry(struct nvbios *bios) |
5685 | { | 5770 | { |
5771 | struct drm_device *dev = bios->dev; | ||
5686 | struct dcb_gpio_table *gpio = &bios->dcb.gpio; | 5772 | struct dcb_gpio_table *gpio = &bios->dcb.gpio; |
5687 | 5773 | ||
5774 | if (gpio->entries >= DCB_MAX_NUM_GPIO_ENTRIES) { | ||
5775 | NV_ERROR(dev, "exceeded maximum number of gpio entries!!\n"); | ||
5776 | return NULL; | ||
5777 | } | ||
5778 | |||
5688 | return &gpio->entry[gpio->entries++]; | 5779 | return &gpio->entry[gpio->entries++]; |
5689 | } | 5780 | } |
5690 | 5781 | ||
@@ -5706,113 +5797,90 @@ nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag) | |||
5706 | } | 5797 | } |
5707 | 5798 | ||
5708 | static void | 5799 | static void |
5709 | parse_dcb30_gpio_entry(struct nvbios *bios, uint16_t offset) | ||
5710 | { | ||
5711 | struct dcb_gpio_entry *gpio; | ||
5712 | uint16_t ent = ROM16(bios->data[offset]); | ||
5713 | uint8_t line = ent & 0x1f, | ||
5714 | tag = ent >> 5 & 0x3f, | ||
5715 | flags = ent >> 11 & 0x1f; | ||
5716 | |||
5717 | if (tag == 0x3f) | ||
5718 | return; | ||
5719 | |||
5720 | gpio = new_gpio_entry(bios); | ||
5721 | |||
5722 | gpio->tag = tag; | ||
5723 | gpio->line = line; | ||
5724 | gpio->invert = flags != 4; | ||
5725 | gpio->entry = ent; | ||
5726 | } | ||
5727 | |||
5728 | static void | ||
5729 | parse_dcb40_gpio_entry(struct nvbios *bios, uint16_t offset) | ||
5730 | { | ||
5731 | uint32_t entry = ROM32(bios->data[offset]); | ||
5732 | struct dcb_gpio_entry *gpio; | ||
5733 | |||
5734 | if ((entry & 0x0000ff00) == 0x0000ff00) | ||
5735 | return; | ||
5736 | |||
5737 | gpio = new_gpio_entry(bios); | ||
5738 | gpio->tag = (entry & 0x0000ff00) >> 8; | ||
5739 | gpio->line = (entry & 0x0000001f) >> 0; | ||
5740 | gpio->state_default = (entry & 0x01000000) >> 24; | ||
5741 | gpio->state[0] = (entry & 0x18000000) >> 27; | ||
5742 | gpio->state[1] = (entry & 0x60000000) >> 29; | ||
5743 | gpio->entry = entry; | ||
5744 | } | ||
5745 | |||
5746 | static void | ||
5747 | parse_dcb_gpio_table(struct nvbios *bios) | 5800 | parse_dcb_gpio_table(struct nvbios *bios) |
5748 | { | 5801 | { |
5749 | struct drm_device *dev = bios->dev; | 5802 | struct drm_device *dev = bios->dev; |
5750 | uint16_t gpio_table_ptr = bios->dcb.gpio_table_ptr; | 5803 | struct dcb_gpio_entry *e; |
5751 | uint8_t *gpio_table = &bios->data[gpio_table_ptr]; | 5804 | u8 headerlen, entries, recordlen; |
5752 | int header_len = gpio_table[1], | 5805 | u8 *dcb, *gpio = NULL, *entry; |
5753 | entries = gpio_table[2], | ||
5754 | entry_len = gpio_table[3]; | ||
5755 | void (*parse_entry)(struct nvbios *, uint16_t) = NULL; | ||
5756 | int i; | 5806 | int i; |
5757 | 5807 | ||
5758 | if (bios->dcb.version >= 0x40) { | 5808 | dcb = ROMPTR(bios, bios->data[0x36]); |
5759 | if (gpio_table_ptr && entry_len != 4) { | 5809 | if (dcb[0] >= 0x30) { |
5760 | NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); | 5810 | gpio = ROMPTR(bios, dcb[10]); |
5761 | return; | 5811 | if (!gpio) |
5762 | } | 5812 | goto no_table; |
5763 | 5813 | ||
5764 | parse_entry = parse_dcb40_gpio_entry; | 5814 | headerlen = gpio[1]; |
5815 | entries = gpio[2]; | ||
5816 | recordlen = gpio[3]; | ||
5817 | } else | ||
5818 | if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) { | ||
5819 | gpio = ROMPTR(bios, dcb[-15]); | ||
5820 | if (!gpio) | ||
5821 | goto no_table; | ||
5822 | |||
5823 | headerlen = 3; | ||
5824 | entries = gpio[2]; | ||
5825 | recordlen = gpio[1]; | ||
5826 | } else | ||
5827 | if (dcb[0] >= 0x22) { | ||
5828 | /* No GPIO table present, parse the TVDAC GPIO data. */ | ||
5829 | uint8_t *tvdac_gpio = &dcb[-5]; | ||
5765 | 5830 | ||
5766 | } else if (bios->dcb.version >= 0x30) { | 5831 | if (tvdac_gpio[0] & 1) { |
5767 | if (gpio_table_ptr && entry_len != 2) { | 5832 | e = new_gpio_entry(bios); |
5768 | NV_WARN(dev, "Invalid DCB GPIO table entry length.\n"); | 5833 | e->tag = DCB_GPIO_TVDAC0; |
5769 | return; | 5834 | e->line = tvdac_gpio[1] >> 4; |
5835 | e->invert = tvdac_gpio[0] & 2; | ||
5770 | } | 5836 | } |
5771 | 5837 | ||
5772 | parse_entry = parse_dcb30_gpio_entry; | 5838 | goto no_table; |
5773 | 5839 | } else { | |
5774 | } else if (bios->dcb.version >= 0x22) { | 5840 | NV_DEBUG(dev, "no/unknown gpio table on DCB 0x%02x\n", dcb[0]); |
5775 | /* | 5841 | goto no_table; |
5776 | * DCBs older than v3.0 don't really have a GPIO | 5842 | } |
5777 | * table, instead they keep some GPIO info at fixed | ||
5778 | * locations. | ||
5779 | */ | ||
5780 | uint16_t dcbptr = ROM16(bios->data[0x36]); | ||
5781 | uint8_t *tvdac_gpio = &bios->data[dcbptr - 5]; | ||
5782 | 5843 | ||
5783 | if (tvdac_gpio[0] & 1) { | 5844 | entry = gpio + headerlen; |
5784 | struct dcb_gpio_entry *gpio = new_gpio_entry(bios); | 5845 | for (i = 0; i < entries; i++, entry += recordlen) { |
5846 | e = new_gpio_entry(bios); | ||
5847 | if (!e) | ||
5848 | break; | ||
5785 | 5849 | ||
5786 | gpio->tag = DCB_GPIO_TVDAC0; | 5850 | if (gpio[0] < 0x40) { |
5787 | gpio->line = tvdac_gpio[1] >> 4; | 5851 | e->entry = ROM16(entry[0]); |
5788 | gpio->invert = tvdac_gpio[0] & 2; | 5852 | e->tag = (e->entry & 0x07e0) >> 5; |
5789 | } | 5853 | if (e->tag == 0x3f) { |
5790 | } else { | 5854 | bios->dcb.gpio.entries--; |
5791 | /* | 5855 | continue; |
5792 | * No systematic way to store GPIO info on pre-v2.2 | 5856 | } |
5793 | * DCBs, try to match the PCI device IDs. | ||
5794 | */ | ||
5795 | 5857 | ||
5796 | /* Apple iMac G4 NV18 */ | 5858 | e->line = (e->entry & 0x001f); |
5797 | if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) { | 5859 | e->invert = ((e->entry & 0xf800) >> 11) != 4; |
5798 | struct dcb_gpio_entry *gpio = new_gpio_entry(bios); | 5860 | } else { |
5861 | e->entry = ROM32(entry[0]); | ||
5862 | e->tag = (e->entry & 0x0000ff00) >> 8; | ||
5863 | if (e->tag == 0xff) { | ||
5864 | bios->dcb.gpio.entries--; | ||
5865 | continue; | ||
5866 | } | ||
5799 | 5867 | ||
5800 | gpio->tag = DCB_GPIO_TVDAC0; | 5868 | e->line = (e->entry & 0x0000001f) >> 0; |
5801 | gpio->line = 4; | 5869 | e->state_default = (e->entry & 0x01000000) >> 24; |
5870 | e->state[0] = (e->entry & 0x18000000) >> 27; | ||
5871 | e->state[1] = (e->entry & 0x60000000) >> 29; | ||
5802 | } | 5872 | } |
5803 | |||
5804 | } | 5873 | } |
5805 | 5874 | ||
5806 | if (!gpio_table_ptr) | 5875 | no_table: |
5807 | return; | 5876 | /* Apple iMac G4 NV18 */ |
5808 | 5877 | if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) { | |
5809 | if (entries > DCB_MAX_NUM_GPIO_ENTRIES) { | 5878 | e = new_gpio_entry(bios); |
5810 | NV_WARN(dev, "Too many entries in the DCB GPIO table.\n"); | 5879 | if (e) { |
5811 | entries = DCB_MAX_NUM_GPIO_ENTRIES; | 5880 | e->tag = DCB_GPIO_TVDAC0; |
5881 | e->line = 4; | ||
5882 | } | ||
5812 | } | 5883 | } |
5813 | |||
5814 | for (i = 0; i < entries; i++) | ||
5815 | parse_entry(bios, gpio_table_ptr + header_len + entry_len * i); | ||
5816 | } | 5884 | } |
5817 | 5885 | ||
5818 | struct dcb_connector_table_entry * | 5886 | struct dcb_connector_table_entry * |
@@ -6680,6 +6748,8 @@ static int nouveau_parse_vbios_struct(struct drm_device *dev) | |||
6680 | bit_signature, sizeof(bit_signature)); | 6748 | bit_signature, sizeof(bit_signature)); |
6681 | if (offset) { | 6749 | if (offset) { |
6682 | NV_TRACE(dev, "BIT BIOS found\n"); | 6750 | NV_TRACE(dev, "BIT BIOS found\n"); |
6751 | bios->type = NVBIOS_BIT; | ||
6752 | bios->offset = offset; | ||
6683 | return parse_bit_structure(bios, offset + 6); | 6753 | return parse_bit_structure(bios, offset + 6); |
6684 | } | 6754 | } |
6685 | 6755 | ||
@@ -6687,6 +6757,8 @@ static int nouveau_parse_vbios_struct(struct drm_device *dev) | |||
6687 | bmp_signature, sizeof(bmp_signature)); | 6757 | bmp_signature, sizeof(bmp_signature)); |
6688 | if (offset) { | 6758 | if (offset) { |
6689 | NV_TRACE(dev, "BMP BIOS found\n"); | 6759 | NV_TRACE(dev, "BMP BIOS found\n"); |
6760 | bios->type = NVBIOS_BMP; | ||
6761 | bios->offset = offset; | ||
6690 | return parse_bmp_structure(dev, bios, offset); | 6762 | return parse_bmp_structure(dev, bios, offset); |
6691 | } | 6763 | } |
6692 | 6764 | ||
@@ -6806,6 +6878,8 @@ nouveau_bios_init(struct drm_device *dev) | |||
6806 | "running VBIOS init tables.\n"); | 6878 | "running VBIOS init tables.\n"); |
6807 | bios->execute = true; | 6879 | bios->execute = true; |
6808 | } | 6880 | } |
6881 | if (nouveau_force_post) | ||
6882 | bios->execute = true; | ||
6809 | 6883 | ||
6810 | ret = nouveau_run_vbios_init(dev); | 6884 | ret = nouveau_run_vbios_init(dev); |
6811 | if (ret) | 6885 | if (ret) |