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path: root/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
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Diffstat (limited to 'drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
index 1ebf2bd372f..fc7944f0626 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
@@ -27,10 +27,23 @@
27 27
28#include <subdev/bios.h> 28#include <subdev/bios.h>
29#include <subdev/bios/dcb.h> 29#include <subdev/bios/dcb.h>
30#include <subdev/timer.h>
30 31
31#include "nv50.h" 32#include "nv50.h"
32 33
33int 34int
35nv50_sor_power(struct nv50_disp_priv *priv, int or, u32 data)
36{
37 const u32 stat = data & NV50_DISP_SOR_PWR_STATE;
38 const u32 soff = (or * 0x800);
39 nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);
40 nv_mask(priv, 0x61c004 + soff, 0x80000001, 0x80000000 | stat);
41 nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000);
42 nv_wait(priv, 0x61c030 + soff, 0x10000000, 0x00000000);
43 return 0;
44}
45
46int
34nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size) 47nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
35{ 48{
36 struct nv50_disp_priv *priv = (void *)object->engine; 49 struct nv50_disp_priv *priv = (void *)object->engine;
@@ -72,6 +85,9 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
72 85
73 data = *(u32 *)args; 86 data = *(u32 *)args;
74 switch (mthd & ~0x3f) { 87 switch (mthd & ~0x3f) {
88 case NV50_DISP_SOR_PWR:
89 ret = priv->sor.power(priv, or, data);
90 break;
75 case NV94_DISP_SOR_DP_TRAIN: 91 case NV94_DISP_SOR_DP_TRAIN:
76 ret = priv->sor.dp_train(priv, or, link, type, mask, data, &outp); 92 ret = priv->sor.dp_train(priv, or, link, type, mask, data, &outp);
77 break; 93 break;