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path: root/drivers/gpu/drm/i915/intel_ringbuffer.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c86
1 files changed, 28 insertions, 58 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7fc55a80be2..21871b0766e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -508,25 +508,18 @@ ring_status_page_get_seqno(struct intel_ring_buffer *ring)
508} 508}
509 509
510static int 510static int
511ring_dispatch_execbuffer(struct intel_ring_buffer *ring, 511ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
512 struct drm_i915_gem_execbuffer2 *exec,
513 struct drm_clip_rect *cliprects,
514 uint64_t exec_offset)
515{ 512{
516 uint32_t exec_start;
517 int ret; 513 int ret;
518 514
519 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
520
521 ret = intel_ring_begin(ring, 2); 515 ret = intel_ring_begin(ring, 2);
522 if (ret) 516 if (ret)
523 return ret; 517 return ret;
524 518
525 intel_ring_emit(ring, 519 intel_ring_emit(ring,
526 MI_BATCH_BUFFER_START | 520 MI_BATCH_BUFFER_START | (2 << 6) |
527 (2 << 6) |
528 MI_BATCH_NON_SECURE_I965); 521 MI_BATCH_NON_SECURE_I965);
529 intel_ring_emit(ring, exec_start); 522 intel_ring_emit(ring, offset);
530 intel_ring_advance(ring); 523 intel_ring_advance(ring);
531 524
532 return 0; 525 return 0;
@@ -534,58 +527,40 @@ ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
534 527
535static int 528static int
536render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, 529render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
537 struct drm_i915_gem_execbuffer2 *exec, 530 u32 offset, u32 len)
538 struct drm_clip_rect *cliprects,
539 uint64_t exec_offset)
540{ 531{
541 struct drm_device *dev = ring->dev; 532 struct drm_device *dev = ring->dev;
542 drm_i915_private_t *dev_priv = dev->dev_private; 533 drm_i915_private_t *dev_priv = dev->dev_private;
543 int nbox = exec->num_cliprects; 534 int ret;
544 uint32_t exec_start, exec_len;
545 int i, count, ret;
546
547 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
548 exec_len = (uint32_t) exec->batch_len;
549 535
550 trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); 536 trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
551 537
552 count = nbox ? nbox : 1; 538 if (IS_I830(dev) || IS_845G(dev)) {
553 for (i = 0; i < count; i++) { 539 ret = intel_ring_begin(ring, 4);
554 if (i < nbox) { 540 if (ret)
555 ret = i915_emit_box(dev, cliprects, i, 541 return ret;
556 exec->DR1, exec->DR4);
557 if (ret)
558 return ret;
559 }
560 542
561 if (IS_I830(dev) || IS_845G(dev)) { 543 intel_ring_emit(ring, MI_BATCH_BUFFER);
562 ret = intel_ring_begin(ring, 4); 544 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
563 if (ret) 545 intel_ring_emit(ring, offset + len - 8);
564 return ret; 546 intel_ring_emit(ring, 0);
547 } else {
548 ret = intel_ring_begin(ring, 2);
549 if (ret)
550 return ret;
565 551
566 intel_ring_emit(ring, MI_BATCH_BUFFER); 552 if (INTEL_INFO(dev)->gen >= 4) {
567 intel_ring_emit(ring, exec_start | MI_BATCH_NON_SECURE); 553 intel_ring_emit(ring,
568 intel_ring_emit(ring, exec_start + exec_len - 4); 554 MI_BATCH_BUFFER_START | (2 << 6) |
569 intel_ring_emit(ring, 0); 555 MI_BATCH_NON_SECURE_I965);
556 intel_ring_emit(ring, offset);
570 } else { 557 } else {
571 ret = intel_ring_begin(ring, 2); 558 intel_ring_emit(ring,
572 if (ret) 559 MI_BATCH_BUFFER_START | (2 << 6));
573 return ret; 560 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
574
575 if (INTEL_INFO(dev)->gen >= 4) {
576 intel_ring_emit(ring,
577 MI_BATCH_BUFFER_START | (2 << 6)
578 | MI_BATCH_NON_SECURE_I965);
579 intel_ring_emit(ring, exec_start);
580 } else {
581 intel_ring_emit(ring, MI_BATCH_BUFFER_START
582 | (2 << 6));
583 intel_ring_emit(ring, exec_start |
584 MI_BATCH_NON_SECURE);
585 }
586 } 561 }
587 intel_ring_advance(ring);
588 } 562 }
563 intel_ring_advance(ring);
589 564
590 return 0; 565 return 0;
591} 566}
@@ -904,22 +879,17 @@ static void gen6_ring_flush(struct intel_ring_buffer *ring,
904 879
905static int 880static int
906gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, 881gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
907 struct drm_i915_gem_execbuffer2 *exec, 882 u32 offset, u32 len)
908 struct drm_clip_rect *cliprects,
909 uint64_t exec_offset)
910{ 883{
911 uint32_t exec_start;
912 int ret; 884 int ret;
913 885
914 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
915
916 ret = intel_ring_begin(ring, 2); 886 ret = intel_ring_begin(ring, 2);
917 if (ret) 887 if (ret)
918 return ret; 888 return ret;
919 889
920 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); 890 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
921 /* bit0-7 is the length on GEN6+ */ 891 /* bit0-7 is the length on GEN6+ */
922 intel_ring_emit(ring, exec_start); 892 intel_ring_emit(ring, offset);
923 intel_ring_advance(ring); 893 intel_ring_advance(ring);
924 894
925 return 0; 895 return 0;