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path: root/drivers/gpu/drm/i915/intel_display.c
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Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c50
1 files changed, 25 insertions, 25 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af3e5813366..09236115395 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1384,6 +1384,28 @@ static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1384 disable_pch_hdmi(dev_priv, pipe, HDMID); 1384 disable_pch_hdmi(dev_priv, pipe, HDMID);
1385} 1385}
1386 1386
1387static void i8xx_disable_fbc(struct drm_device *dev)
1388{
1389 struct drm_i915_private *dev_priv = dev->dev_private;
1390 u32 fbc_ctl;
1391
1392 /* Disable compression */
1393 fbc_ctl = I915_READ(FBC_CONTROL);
1394 if ((fbc_ctl & FBC_CTL_EN) == 0)
1395 return;
1396
1397 fbc_ctl &= ~FBC_CTL_EN;
1398 I915_WRITE(FBC_CONTROL, fbc_ctl);
1399
1400 /* Wait for compressing bit to clear */
1401 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1402 DRM_DEBUG_KMS("FBC idle timed out\n");
1403 return;
1404 }
1405
1406 DRM_DEBUG_KMS("disabled FBC\n");
1407}
1408
1387static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 1409static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1388{ 1410{
1389 struct drm_device *dev = crtc->dev; 1411 struct drm_device *dev = crtc->dev;
@@ -1439,28 +1461,6 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1439 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane); 1461 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1440} 1462}
1441 1463
1442void i8xx_disable_fbc(struct drm_device *dev)
1443{
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 u32 fbc_ctl;
1446
1447 /* Disable compression */
1448 fbc_ctl = I915_READ(FBC_CONTROL);
1449 if ((fbc_ctl & FBC_CTL_EN) == 0)
1450 return;
1451
1452 fbc_ctl &= ~FBC_CTL_EN;
1453 I915_WRITE(FBC_CONTROL, fbc_ctl);
1454
1455 /* Wait for compressing bit to clear */
1456 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1457 DRM_DEBUG_KMS("FBC idle timed out\n");
1458 return;
1459 }
1460
1461 DRM_DEBUG_KMS("disabled FBC\n");
1462}
1463
1464static bool i8xx_fbc_enabled(struct drm_device *dev) 1464static bool i8xx_fbc_enabled(struct drm_device *dev)
1465{ 1465{
1466 struct drm_i915_private *dev_priv = dev->dev_private; 1466 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -1516,7 +1516,7 @@ static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1516 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 1516 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1517} 1517}
1518 1518
1519void g4x_disable_fbc(struct drm_device *dev) 1519static void g4x_disable_fbc(struct drm_device *dev)
1520{ 1520{
1521 struct drm_i915_private *dev_priv = dev->dev_private; 1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 u32 dpfc_ctl; 1522 u32 dpfc_ctl;
@@ -1616,7 +1616,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1616 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 1616 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1617} 1617}
1618 1618
1619void ironlake_disable_fbc(struct drm_device *dev) 1619static void ironlake_disable_fbc(struct drm_device *dev)
1620{ 1620{
1621 struct drm_i915_private *dev_priv = dev->dev_private; 1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 u32 dpfc_ctl; 1622 u32 dpfc_ctl;
@@ -1648,7 +1648,7 @@ bool intel_fbc_enabled(struct drm_device *dev)
1648 return dev_priv->display.fbc_enabled(dev); 1648 return dev_priv->display.fbc_enabled(dev);
1649} 1649}
1650 1650
1651void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 1651static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1652{ 1652{
1653 struct drm_i915_private *dev_priv = crtc->dev->dev_private; 1653 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1654 1654