1 files changed, 8 insertions, 3 deletions

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 7886e4fb60e..2b5eb229ff2 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -28,14 +28,19 @@
 #include "drm.h"
 #include "i915_drm.h"
 #include "intel_drv.h"
+#include "i915_reg.h"
 
 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         u32     dpll_reg;
 
+        /* On IVB, 3rd pipe shares PLL with another one */
+        if (pipe > 1)
+                return false;
+
         if (HAS_PCH_SPLIT(dev))
-                dpll_reg = (pipe == PIPE_A) ? _PCH_DPLL_A : _PCH_DPLL_B;
+                dpll_reg = PCH_DPLL(pipe);
         else
                 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B;
 
@@ -822,7 +827,7 @@ int i915_save_state(struct drm_device *dev)
 
         if (IS_IRONLAKE_M(dev))
                 ironlake_disable_drps(dev);
-        if (IS_GEN6(dev))
+        if (INTEL_INFO(dev)->gen >= 6)
                 gen6_disable_rps(dev);
 
         /* Cache mode state */
@@ -881,7 +886,7 @@ int i915_restore_state(struct drm_device *dev)
                 intel_init_emon(dev);
         }
 
-        if (IS_GEN6(dev)) {
+        if (INTEL_INFO(dev)->gen >= 6) {
                 gen6_enable_rps(dev_priv);
                 gen6_update_ring_freq(dev_priv);
         }