diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 281db6e5403..67e3ec1a6af 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -170,6 +170,7 @@ | |||
| 170 | #define MI_NO_WRITE_FLUSH (1 << 2) | 170 | #define MI_NO_WRITE_FLUSH (1 << 2) |
| 171 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ | 171 | #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */ |
| 172 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ | 172 | #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */ |
| 173 | #define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */ | ||
| 173 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) | 174 | #define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0) |
| 174 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) | 175 | #define MI_REPORT_HEAD MI_INSTR(0x07, 0) |
| 175 | #define MI_OVERLAY_FLIP MI_INSTR(0x11,0) | 176 | #define MI_OVERLAY_FLIP MI_INSTR(0x11,0) |
| @@ -180,6 +181,12 @@ | |||
| 180 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) | 181 | #define MI_DISPLAY_FLIP MI_INSTR(0x14, 2) |
| 181 | #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) | 182 | #define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1) |
| 182 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) | 183 | #define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20) |
| 184 | #define MI_SET_CONTEXT MI_INSTR(0x18, 0) | ||
| 185 | #define MI_MM_SPACE_GTT (1<<8) | ||
| 186 | #define MI_MM_SPACE_PHYSICAL (0<<8) | ||
| 187 | #define MI_SAVE_EXT_STATE_EN (1<<3) | ||
| 188 | #define MI_RESTORE_EXT_STATE_EN (1<<2) | ||
| 189 | #define MI_RESTORE_INHIBIT (1<<0) | ||
| 183 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) | 190 | #define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1) |
| 184 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ | 191 | #define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */ |
| 185 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) | 192 | #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) |
| @@ -1100,6 +1107,11 @@ | |||
| 1100 | #define PEG_BAND_GAP_DATA 0x14d68 | 1107 | #define PEG_BAND_GAP_DATA 0x14d68 |
| 1101 | 1108 | ||
| 1102 | /* | 1109 | /* |
| 1110 | * Logical Context regs | ||
| 1111 | */ | ||
| 1112 | #define CCID 0x2180 | ||
| 1113 | #define CCID_EN (1<<0) | ||
| 1114 | /* | ||
| 1103 | * Overlay regs | 1115 | * Overlay regs |
| 1104 | */ | 1116 | */ |
| 1105 | 1117 | ||
| @@ -2069,6 +2081,7 @@ | |||
| 2069 | #define PIPE_DITHER_TYPE_ST01 (1 << 2) | 2081 | #define PIPE_DITHER_TYPE_ST01 (1 << 2) |
| 2070 | /* Pipe A */ | 2082 | /* Pipe A */ |
| 2071 | #define PIPEADSL 0x70000 | 2083 | #define PIPEADSL 0x70000 |
| 2084 | #define DSL_LINEMASK 0x00000fff | ||
| 2072 | #define PIPEACONF 0x70008 | 2085 | #define PIPEACONF 0x70008 |
| 2073 | #define PIPEACONF_ENABLE (1<<31) | 2086 | #define PIPEACONF_ENABLE (1<<31) |
| 2074 | #define PIPEACONF_DISABLE 0 | 2087 | #define PIPEACONF_DISABLE 0 |
| @@ -2928,6 +2941,7 @@ | |||
| 2928 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 | 2941 | #define TRANS_DP_VSYNC_ACTIVE_LOW 0 |
| 2929 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) | 2942 | #define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3) |
| 2930 | #define TRANS_DP_HSYNC_ACTIVE_LOW 0 | 2943 | #define TRANS_DP_HSYNC_ACTIVE_LOW 0 |
| 2944 | #define TRANS_DP_SYNC_MASK (3<<3) | ||
| 2931 | 2945 | ||
| 2932 | /* SNB eDP training params */ | 2946 | /* SNB eDP training params */ |
| 2933 | /* SNB A-stepping */ | 2947 | /* SNB A-stepping */ |