diff options
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 31 |
1 files changed, 7 insertions, 24 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 15c0ca58ad8..06a37f4fd74 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -139,7 +139,6 @@ struct sdvo_device_mapping { | |||
139 | u8 slave_addr; | 139 | u8 slave_addr; |
140 | u8 dvo_wiring; | 140 | u8 dvo_wiring; |
141 | u8 i2c_pin; | 141 | u8 i2c_pin; |
142 | u8 i2c_speed; | ||
143 | u8 ddc_pin; | 142 | u8 ddc_pin; |
144 | }; | 143 | }; |
145 | 144 | ||
@@ -349,7 +348,6 @@ typedef struct drm_i915_private { | |||
349 | /* LVDS info */ | 348 | /* LVDS info */ |
350 | int backlight_level; /* restore backlight to this value */ | 349 | int backlight_level; /* restore backlight to this value */ |
351 | bool backlight_enabled; | 350 | bool backlight_enabled; |
352 | struct drm_display_mode *panel_fixed_mode; | ||
353 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | 351 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
354 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | 352 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ |
355 | 353 | ||
@@ -359,6 +357,7 @@ typedef struct drm_i915_private { | |||
359 | unsigned int lvds_vbt:1; | 357 | unsigned int lvds_vbt:1; |
360 | unsigned int int_crt_support:1; | 358 | unsigned int int_crt_support:1; |
361 | unsigned int lvds_use_ssc:1; | 359 | unsigned int lvds_use_ssc:1; |
360 | unsigned int display_clock_mode:1; | ||
362 | int lvds_ssc_freq; | 361 | int lvds_ssc_freq; |
363 | struct { | 362 | struct { |
364 | int rate; | 363 | int rate; |
@@ -674,10 +673,9 @@ typedef struct drm_i915_private { | |||
674 | unsigned int lvds_border_bits; | 673 | unsigned int lvds_border_bits; |
675 | /* Panel fitter placement and size for Ironlake+ */ | 674 | /* Panel fitter placement and size for Ironlake+ */ |
676 | u32 pch_pf_pos, pch_pf_size; | 675 | u32 pch_pf_pos, pch_pf_size; |
677 | int panel_t3, panel_t12; | ||
678 | 676 | ||
679 | struct drm_crtc *plane_to_crtc_mapping[2]; | 677 | struct drm_crtc *plane_to_crtc_mapping[3]; |
680 | struct drm_crtc *pipe_to_crtc_mapping[2]; | 678 | struct drm_crtc *pipe_to_crtc_mapping[3]; |
681 | wait_queue_head_t pending_flip_queue; | 679 | wait_queue_head_t pending_flip_queue; |
682 | bool flip_pending_is_done; | 680 | bool flip_pending_is_done; |
683 | 681 | ||
@@ -1303,6 +1301,7 @@ extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); | |||
1303 | extern bool intel_fbc_enabled(struct drm_device *dev); | 1301 | extern bool intel_fbc_enabled(struct drm_device *dev); |
1304 | extern void intel_disable_fbc(struct drm_device *dev); | 1302 | extern void intel_disable_fbc(struct drm_device *dev); |
1305 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); | 1303 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
1304 | extern void ironlake_init_pch_refclk(struct drm_device *dev); | ||
1306 | extern void ironlake_enable_rc6(struct drm_device *dev); | 1305 | extern void ironlake_enable_rc6(struct drm_device *dev); |
1307 | extern void gen6_set_rps(struct drm_device *dev, u8 val); | 1306 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
1308 | extern void intel_detect_pch(struct drm_device *dev); | 1307 | extern void intel_detect_pch(struct drm_device *dev); |
@@ -1356,18 +1355,7 @@ void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); | |||
1356 | ((reg) != FORCEWAKE)) | 1355 | ((reg) != FORCEWAKE)) |
1357 | 1356 | ||
1358 | #define __i915_read(x, y) \ | 1357 | #define __i915_read(x, y) \ |
1359 | static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | 1358 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); |
1360 | u##x val = 0; \ | ||
1361 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | ||
1362 | gen6_gt_force_wake_get(dev_priv); \ | ||
1363 | val = read##y(dev_priv->regs + reg); \ | ||
1364 | gen6_gt_force_wake_put(dev_priv); \ | ||
1365 | } else { \ | ||
1366 | val = read##y(dev_priv->regs + reg); \ | ||
1367 | } \ | ||
1368 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | ||
1369 | return val; \ | ||
1370 | } | ||
1371 | 1359 | ||
1372 | __i915_read(8, b) | 1360 | __i915_read(8, b) |
1373 | __i915_read(16, w) | 1361 | __i915_read(16, w) |
@@ -1376,13 +1364,8 @@ __i915_read(64, q) | |||
1376 | #undef __i915_read | 1364 | #undef __i915_read |
1377 | 1365 | ||
1378 | #define __i915_write(x, y) \ | 1366 | #define __i915_write(x, y) \ |
1379 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | 1367 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val); |
1380 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ | 1368 | |
1381 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | ||
1382 | __gen6_gt_wait_for_fifo(dev_priv); \ | ||
1383 | } \ | ||
1384 | write##y(val, dev_priv->regs + reg); \ | ||
1385 | } | ||
1386 | __i915_write(8, b) | 1369 | __i915_write(8, b) |
1387 | __i915_write(16, w) | 1370 | __i915_write(16, w) |
1388 | __i915_write(32, l) | 1371 | __i915_write(32, l) |