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path: root/drivers/gpu/drm/gma500/psb_irq.c
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Diffstat (limited to 'drivers/gpu/drm/gma500/psb_irq.c')
-rw-r--r--drivers/gpu/drm/gma500/psb_irq.c58
1 files changed, 58 insertions, 0 deletions
diff --git a/drivers/gpu/drm/gma500/psb_irq.c b/drivers/gpu/drm/gma500/psb_irq.c
index 7be802baceb..a86fc3c4bf3 100644
--- a/drivers/gpu/drm/gma500/psb_irq.c
+++ b/drivers/gpu/drm/gma500/psb_irq.c
@@ -27,6 +27,8 @@
27#include "psb_reg.h" 27#include "psb_reg.h"
28#include "psb_intel_reg.h" 28#include "psb_intel_reg.h"
29#include "power.h" 29#include "power.h"
30#include "psb_irq.h"
31#include "mdfld_output.h"
30 32
31/* 33/*
32 * inline functions 34 * inline functions
@@ -453,6 +455,11 @@ int psb_enable_vblank(struct drm_device *dev, int pipe)
453 uint32_t reg_val = 0; 455 uint32_t reg_val = 0;
454 uint32_t pipeconf_reg = mid_pipeconf(pipe); 456 uint32_t pipeconf_reg = mid_pipeconf(pipe);
455 457
458 /* Medfield is different - we should perhaps extract out vblank
459 and blacklight etc ops */
460 if (IS_MFLD(dev))
461 return mdfld_enable_te(dev, pipe);
462
456 if (gma_power_begin(dev, false)) { 463 if (gma_power_begin(dev, false)) {
457 reg_val = REG_READ(pipeconf_reg); 464 reg_val = REG_READ(pipeconf_reg);
458 gma_power_end(dev); 465 gma_power_end(dev);
@@ -485,6 +492,8 @@ void psb_disable_vblank(struct drm_device *dev, int pipe)
485 struct drm_psb_private *dev_priv = dev->dev_private; 492 struct drm_psb_private *dev_priv = dev->dev_private;
486 unsigned long irqflags; 493 unsigned long irqflags;
487 494
495 if (IS_MFLD(dev))
496 mdfld_disable_te(dev, pipe);
488 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags); 497 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
489 498
490 if (pipe == 0) 499 if (pipe == 0)
@@ -499,6 +508,55 @@ void psb_disable_vblank(struct drm_device *dev, int pipe)
499 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); 508 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
500} 509}
501 510
511/*
512 * It is used to enable TE interrupt
513 */
514int mdfld_enable_te(struct drm_device *dev, int pipe)
515{
516 struct drm_psb_private *dev_priv =
517 (struct drm_psb_private *) dev->dev_private;
518 unsigned long irqflags;
519 uint32_t reg_val = 0;
520 uint32_t pipeconf_reg = mid_pipeconf(pipe);
521
522 if (gma_power_begin(dev, false)) {
523 reg_val = REG_READ(pipeconf_reg);
524 gma_power_end(dev);
525 }
526
527 if (!(reg_val & PIPEACONF_ENABLE))
528 return -EINVAL;
529
530 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
531
532 mid_enable_pipe_event(dev_priv, pipe);
533 psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
534
535 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
536
537 return 0;
538}
539
540/*
541 * It is used to disable TE interrupt
542 */
543void mdfld_disable_te(struct drm_device *dev, int pipe)
544{
545 struct drm_psb_private *dev_priv =
546 (struct drm_psb_private *) dev->dev_private;
547 unsigned long irqflags;
548
549 if (!dev_priv->dsr_enable)
550 return;
551
552 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
553
554 mid_disable_pipe_event(dev_priv, pipe);
555 psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
556
557 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
558}
559
502/* Called from drm generic code, passed a 'crtc', which 560/* Called from drm generic code, passed a 'crtc', which
503 * we use as a pipe index 561 * we use as a pipe index
504 */ 562 */