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Diffstat (limited to 'drivers/gpu/drm/gma500/mdfld_dsi_output.h')
-rw-r--r--drivers/gpu/drm/gma500/mdfld_dsi_output.h389
1 files changed, 389 insertions, 0 deletions
diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_output.h b/drivers/gpu/drm/gma500/mdfld_dsi_output.h
new file mode 100644
index 00000000000..2cdf666536d
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+++ b/drivers/gpu/drm/gma500/mdfld_dsi_output.h
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1/*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * jim liu <jim.liu@intel.com>
25 * Jackie Li<yaodong.li@intel.com>
26 */
27
28#ifndef __MDFLD_DSI_OUTPUT_H__
29#define __MDFLD_DSI_OUTPUT_H__
30
31#include <linux/backlight.h>
32#include <linux/version.h>
33#include <drm/drmP.h>
34#include <drm/drm.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
37
38#include "psb_drv.h"
39#include "psb_intel_drv.h"
40#include "psb_intel_reg.h"
41#include "mdfld_output.h"
42
43#include <asm/mrst.h>
44
45#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
46#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
47#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
48#define FLD_MOD(orig, val, start, end) \
49 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
50
51#define REG_FLD_MOD(reg, val, start, end) \
52 REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end))
53
54static inline int REGISTER_FLD_WAIT(struct drm_device *dev, u32 reg,
55 u32 val, int start, int end)
56{
57 int t = 100000;
58
59 while (FLD_GET(REG_READ(reg), start, end) != val) {
60 if (--t == 0)
61 return 1;
62 }
63
64 return 0;
65}
66
67#define REG_FLD_WAIT(reg, val, start, end) \
68 REGISTER_FLD_WAIT(dev, reg, val, start, end)
69
70#define REG_BIT_WAIT(reg, val, bitnum) \
71 REGISTER_FLD_WAIT(dev, reg, val, bitnum, bitnum)
72
73#define MDFLD_DSI_BRIGHTNESS_MAX_LEVEL 100
74
75#ifdef DEBUG
76#define CHECK_PIPE(pipe) ({ \
77 const typeof(pipe) __pipe = (pipe); \
78 BUG_ON(__pipe != 0 && __pipe != 2); \
79 __pipe; })
80#else
81#define CHECK_PIPE(pipe) (pipe)
82#endif
83
84/*
85 * Actual MIPIA->MIPIC reg offset is 0x800, value 0x400 is valid for 0 and 2
86 */
87#define REG_OFFSET(pipe) (CHECK_PIPE(pipe) * 0x400)
88
89/* mdfld DSI controller registers */
90#define MIPI_DEVICE_READY_REG(pipe) (0xb000 + REG_OFFSET(pipe))
91#define MIPI_INTR_STAT_REG(pipe) (0xb004 + REG_OFFSET(pipe))
92#define MIPI_INTR_EN_REG(pipe) (0xb008 + REG_OFFSET(pipe))
93#define MIPI_DSI_FUNC_PRG_REG(pipe) (0xb00c + REG_OFFSET(pipe))
94#define MIPI_HS_TX_TIMEOUT_REG(pipe) (0xb010 + REG_OFFSET(pipe))
95#define MIPI_LP_RX_TIMEOUT_REG(pipe) (0xb014 + REG_OFFSET(pipe))
96#define MIPI_TURN_AROUND_TIMEOUT_REG(pipe) (0xb018 + REG_OFFSET(pipe))
97#define MIPI_DEVICE_RESET_TIMER_REG(pipe) (0xb01c + REG_OFFSET(pipe))
98#define MIPI_DPI_RESOLUTION_REG(pipe) (0xb020 + REG_OFFSET(pipe))
99#define MIPI_DBI_FIFO_THROTTLE_REG(pipe) (0xb024 + REG_OFFSET(pipe))
100#define MIPI_HSYNC_COUNT_REG(pipe) (0xb028 + REG_OFFSET(pipe))
101#define MIPI_HBP_COUNT_REG(pipe) (0xb02c + REG_OFFSET(pipe))
102#define MIPI_HFP_COUNT_REG(pipe) (0xb030 + REG_OFFSET(pipe))
103#define MIPI_HACTIVE_COUNT_REG(pipe) (0xb034 + REG_OFFSET(pipe))
104#define MIPI_VSYNC_COUNT_REG(pipe) (0xb038 + REG_OFFSET(pipe))
105#define MIPI_VBP_COUNT_REG(pipe) (0xb03c + REG_OFFSET(pipe))
106#define MIPI_VFP_COUNT_REG(pipe) (0xb040 + REG_OFFSET(pipe))
107#define MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe) (0xb044 + REG_OFFSET(pipe))
108#define MIPI_DPI_CONTROL_REG(pipe) (0xb048 + REG_OFFSET(pipe))
109#define MIPI_DPI_DATA_REG(pipe) (0xb04c + REG_OFFSET(pipe))
110#define MIPI_INIT_COUNT_REG(pipe) (0xb050 + REG_OFFSET(pipe))
111#define MIPI_MAX_RETURN_PACK_SIZE_REG(pipe) (0xb054 + REG_OFFSET(pipe))
112#define MIPI_VIDEO_MODE_FORMAT_REG(pipe) (0xb058 + REG_OFFSET(pipe))
113#define MIPI_EOT_DISABLE_REG(pipe) (0xb05c + REG_OFFSET(pipe))
114#define MIPI_LP_BYTECLK_REG(pipe) (0xb060 + REG_OFFSET(pipe))
115#define MIPI_LP_GEN_DATA_REG(pipe) (0xb064 + REG_OFFSET(pipe))
116#define MIPI_HS_GEN_DATA_REG(pipe) (0xb068 + REG_OFFSET(pipe))
117#define MIPI_LP_GEN_CTRL_REG(pipe) (0xb06c + REG_OFFSET(pipe))
118#define MIPI_HS_GEN_CTRL_REG(pipe) (0xb070 + REG_OFFSET(pipe))
119#define MIPI_GEN_FIFO_STAT_REG(pipe) (0xb074 + REG_OFFSET(pipe))
120#define MIPI_HS_LS_DBI_ENABLE_REG(pipe) (0xb078 + REG_OFFSET(pipe))
121#define MIPI_DPHY_PARAM_REG(pipe) (0xb080 + REG_OFFSET(pipe))
122#define MIPI_DBI_BW_CTRL_REG(pipe) (0xb084 + REG_OFFSET(pipe))
123#define MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe) (0xb088 + REG_OFFSET(pipe))
124
125#define MIPI_CTRL_REG(pipe) (0xb104 + REG_OFFSET(pipe))
126#define MIPI_DATA_ADD_REG(pipe) (0xb108 + REG_OFFSET(pipe))
127#define MIPI_DATA_LEN_REG(pipe) (0xb10c + REG_OFFSET(pipe))
128#define MIPI_CMD_ADD_REG(pipe) (0xb110 + REG_OFFSET(pipe))
129#define MIPI_CMD_LEN_REG(pipe) (0xb114 + REG_OFFSET(pipe))
130
131/* non-uniform reg offset */
132#define MIPI_PORT_CONTROL(pipe) (CHECK_PIPE(pipe) ? MIPI_C : MIPI)
133
134#define DSI_DEVICE_READY (0x1)
135#define DSI_POWER_STATE_ULPS_ENTER (0x2 << 1)
136#define DSI_POWER_STATE_ULPS_EXIT (0x1 << 1)
137#define DSI_POWER_STATE_ULPS_OFFSET (0x1)
138
139
140#define DSI_ONE_DATA_LANE (0x1)
141#define DSI_TWO_DATA_LANE (0x2)
142#define DSI_THREE_DATA_LANE (0X3)
143#define DSI_FOUR_DATA_LANE (0x4)
144#define DSI_DPI_VIRT_CHANNEL_OFFSET (0x3)
145#define DSI_DBI_VIRT_CHANNEL_OFFSET (0x5)
146#define DSI_DPI_COLOR_FORMAT_RGB565 (0x01 << 7)
147#define DSI_DPI_COLOR_FORMAT_RGB666 (0x02 << 7)
148#define DSI_DPI_COLOR_FORMAT_RGB666_UNPACK (0x03 << 7)
149#define DSI_DPI_COLOR_FORMAT_RGB888 (0x04 << 7)
150#define DSI_DBI_COLOR_FORMAT_OPTION2 (0x05 << 13)
151
152#define DSI_INTR_STATE_RXSOTERROR BIT(0)
153
154#define DSI_INTR_STATE_SPL_PKG_SENT BIT(30)
155#define DSI_INTR_STATE_TE BIT(31)
156
157#define DSI_HS_TX_TIMEOUT_MASK (0xffffff)
158
159#define DSI_LP_RX_TIMEOUT_MASK (0xffffff)
160
161#define DSI_TURN_AROUND_TIMEOUT_MASK (0x3f)
162
163#define DSI_RESET_TIMER_MASK (0xffff)
164
165#define DSI_DBI_FIFO_WM_HALF (0x0)
166#define DSI_DBI_FIFO_WM_QUARTER (0x1)
167#define DSI_DBI_FIFO_WM_LOW (0x2)
168
169#define DSI_DPI_TIMING_MASK (0xffff)
170
171#define DSI_INIT_TIMER_MASK (0xffff)
172
173#define DSI_DBI_RETURN_PACK_SIZE_MASK (0x3ff)
174
175#define DSI_LP_BYTECLK_MASK (0x0ffff)
176
177#define DSI_HS_CTRL_GEN_SHORT_W0 (0x03)
178#define DSI_HS_CTRL_GEN_SHORT_W1 (0x13)
179#define DSI_HS_CTRL_GEN_SHORT_W2 (0x23)
180#define DSI_HS_CTRL_GEN_R0 (0x04)
181#define DSI_HS_CTRL_GEN_R1 (0x14)
182#define DSI_HS_CTRL_GEN_R2 (0x24)
183#define DSI_HS_CTRL_GEN_LONG_W (0x29)
184#define DSI_HS_CTRL_MCS_SHORT_W0 (0x05)
185#define DSI_HS_CTRL_MCS_SHORT_W1 (0x15)
186#define DSI_HS_CTRL_MCS_R0 (0x06)
187#define DSI_HS_CTRL_MCS_LONG_W (0x39)
188#define DSI_HS_CTRL_VC_OFFSET (0x06)
189#define DSI_HS_CTRL_WC_OFFSET (0x08)
190
191#define DSI_FIFO_GEN_HS_DATA_FULL BIT(0)
192#define DSI_FIFO_GEN_HS_DATA_HALF_EMPTY BIT(1)
193#define DSI_FIFO_GEN_HS_DATA_EMPTY BIT(2)
194#define DSI_FIFO_GEN_LP_DATA_FULL BIT(8)
195#define DSI_FIFO_GEN_LP_DATA_HALF_EMPTY BIT(9)
196#define DSI_FIFO_GEN_LP_DATA_EMPTY BIT(10)
197#define DSI_FIFO_GEN_HS_CTRL_FULL BIT(16)
198#define DSI_FIFO_GEN_HS_CTRL_HALF_EMPTY BIT(17)
199#define DSI_FIFO_GEN_HS_CTRL_EMPTY BIT(18)
200#define DSI_FIFO_GEN_LP_CTRL_FULL BIT(24)
201#define DSI_FIFO_GEN_LP_CTRL_HALF_EMPTY BIT(25)
202#define DSI_FIFO_GEN_LP_CTRL_EMPTY BIT(26)
203#define DSI_FIFO_DBI_EMPTY BIT(27)
204#define DSI_FIFO_DPI_EMPTY BIT(28)
205
206#define DSI_DBI_HS_LP_SWITCH_MASK (0x1)
207
208#define DSI_HS_LP_SWITCH_COUNTER_OFFSET (0x0)
209#define DSI_LP_HS_SWITCH_COUNTER_OFFSET (0x16)
210
211#define DSI_DPI_CTRL_HS_SHUTDOWN (0x00000001)
212#define DSI_DPI_CTRL_HS_TURN_ON (0x00000002)
213
214/*dsi power modes*/
215#define DSI_POWER_MODE_DISPLAY_ON BIT(2)
216#define DSI_POWER_MODE_NORMAL_ON BIT(3)
217#define DSI_POWER_MODE_SLEEP_OUT BIT(4)
218#define DSI_POWER_MODE_PARTIAL_ON BIT(5)
219#define DSI_POWER_MODE_IDLE_ON BIT(6)
220
221enum {
222 MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_PULSE = 1,
223 MDFLD_DSI_VIDEO_NON_BURST_MODE_SYNC_EVENTS = 2,
224 MDFLD_DSI_VIDEO_BURST_MODE = 3,
225};
226
227#define DSI_DPI_COMPLETE_LAST_LINE BIT(2)
228#define DSI_DPI_DISABLE_BTA BIT(3)
229
230struct mdfld_dsi_connector_state {
231 u32 mipi_ctrl_reg;
232};
233
234struct mdfld_dsi_encoder_state {
235
236};
237
238struct mdfld_dsi_connector {
239 struct psb_intel_connector base;
240
241 int pipe;
242 void *private;
243 void *pkg_sender;
244
245 /* Connection status */
246 enum drm_connector_status status;
247};
248
249struct mdfld_dsi_encoder {
250 struct psb_intel_encoder base;
251 void *private;
252};
253
254/*
255 * DSI config, consists of one DSI connector, two DSI encoders.
256 * DRM will pick up on DSI encoder basing on differents configs.
257 */
258struct mdfld_dsi_config {
259 struct drm_device *dev;
260 struct drm_display_mode *fixed_mode;
261 struct drm_display_mode *mode;
262
263 struct mdfld_dsi_connector *connector;
264 struct mdfld_dsi_encoder *encoder;
265
266 int changed;
267
268 int bpp;
269 int lane_count;
270 /*Virtual channel number for this encoder*/
271 int channel_num;
272 /*video mode configure*/
273 int video_mode;
274
275 int dvr_ic_inited;
276};
277
278static inline struct mdfld_dsi_connector *mdfld_dsi_connector(
279 struct drm_connector *connector)
280{
281 struct psb_intel_connector *psb_connector;
282
283 psb_connector = to_psb_intel_connector(connector);
284
285 return container_of(psb_connector, struct mdfld_dsi_connector, base);
286}
287
288static inline struct mdfld_dsi_encoder *mdfld_dsi_encoder(
289 struct drm_encoder *encoder)
290{
291 struct psb_intel_encoder *psb_encoder;
292
293 psb_encoder = to_psb_intel_encoder(encoder);
294
295 return container_of(psb_encoder, struct mdfld_dsi_encoder, base);
296}
297
298static inline struct mdfld_dsi_config *
299 mdfld_dsi_get_config(struct mdfld_dsi_connector *connector)
300{
301 if (!connector)
302 return NULL;
303 return (struct mdfld_dsi_config *)connector->private;
304}
305
306static inline void *mdfld_dsi_get_pkg_sender(struct mdfld_dsi_config *config)
307{
308 struct mdfld_dsi_connector *dsi_connector;
309
310 if (!config)
311 return NULL;
312
313 dsi_connector = config->connector;
314
315 if (!dsi_connector)
316 return NULL;
317
318 return dsi_connector->pkg_sender;
319}
320
321static inline struct mdfld_dsi_config *
322 mdfld_dsi_encoder_get_config(struct mdfld_dsi_encoder *encoder)
323{
324 if (!encoder)
325 return NULL;
326 return (struct mdfld_dsi_config *)encoder->private;
327}
328
329static inline struct mdfld_dsi_connector *
330 mdfld_dsi_encoder_get_connector(struct mdfld_dsi_encoder *encoder)
331{
332 struct mdfld_dsi_config *config;
333
334 if (!encoder)
335 return NULL;
336
337 config = mdfld_dsi_encoder_get_config(encoder);
338 if (!config)
339 return NULL;
340
341 return config->connector;
342}
343
344static inline void *mdfld_dsi_encoder_get_pkg_sender(
345 struct mdfld_dsi_encoder *encoder)
346{
347 struct mdfld_dsi_config *dsi_config;
348
349 dsi_config = mdfld_dsi_encoder_get_config(encoder);
350 if (!dsi_config)
351 return NULL;
352
353 return mdfld_dsi_get_pkg_sender(dsi_config);
354}
355
356static inline int mdfld_dsi_encoder_get_pipe(struct mdfld_dsi_encoder *encoder)
357{
358 struct mdfld_dsi_connector *connector;
359
360 if (!encoder)
361 return -1;
362
363 connector = mdfld_dsi_encoder_get_connector(encoder);
364 if (!connector)
365 return -1;
366 return connector->pipe;
367}
368
369/* Export functions */
370extern void mdfld_dsi_gen_fifo_ready(struct drm_device *dev,
371 u32 gen_fifo_stat_reg, u32 fifo_stat);
372extern void mdfld_dsi_brightness_init(struct mdfld_dsi_config *dsi_config,
373 int pipe);
374extern void mdfld_dsi_brightness_control(struct drm_device *dev, int pipe,
375 int level);
376extern void mdfld_dsi_output_init(struct drm_device *dev,
377 int pipe,
378 struct mdfld_dsi_config *config,
379 const struct panel_funcs *p_vid_funcs);
380extern void mdfld_dsi_controller_init(struct mdfld_dsi_config *dsi_config,
381 int pipe);
382
383extern int mdfld_dsi_get_power_mode(struct mdfld_dsi_config *dsi_config,
384 u32 *mode, bool hs);
385extern int mdfld_dsi_get_diagnostic_result(struct mdfld_dsi_config *dsi_config,
386 u32 *result, bool hs);
387extern int mdfld_dsi_panel_reset(int pipe);
388
389#endif /*__MDFLD_DSI_OUTPUT_H__*/
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