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-rw-r--r--drivers/gpio/gpio-u300.c1190
1 files changed, 705 insertions, 485 deletions
diff --git a/drivers/gpio/gpio-u300.c b/drivers/gpio/gpio-u300.c
index 53e8255cb0b..4035778852b 100644
--- a/drivers/gpio/gpio-u300.c
+++ b/drivers/gpio/gpio-u300.c
@@ -1,18 +1,17 @@
1/* 1/*
2 * U300 GPIO module. 2 * U300 GPIO module.
3 * 3 *
4 * Copyright (C) 2007-2009 ST-Ericsson AB 4 * Copyright (C) 2007-2011 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2 5 * License terms: GNU General Public License (GPL) version 2
6 * This can driver either of the two basic GPIO cores 6 * This can driver either of the two basic GPIO cores
7 * available in the U300 platforms: 7 * available in the U300 platforms:
8 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0) 8 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
9 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) 9 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
10 * Notice that you also have inline macros in <asm-arch/gpio.h> 10 * Author: Linus Walleij <linus.walleij@linaro.org>
11 * Author: Linus Walleij <linus.walleij@stericsson.com>
12 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
13 *
14 */ 12 */
15#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/irq.h>
16#include <linux/interrupt.h> 15#include <linux/interrupt.h>
17#include <linux/delay.h> 16#include <linux/delay.h>
18#include <linux/errno.h> 17#include <linux/errno.h>
@@ -21,677 +20,898 @@
21#include <linux/err.h> 20#include <linux/err.h>
22#include <linux/platform_device.h> 21#include <linux/platform_device.h>
23#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/list.h>
24#include <linux/slab.h>
25#include <mach/gpio-u300.h>
24 26
25/* Reference to GPIO block clock */ 27/*
26static struct clk *clk; 28 * Bias modes for U300 GPIOs
29 *
30 * GPIO_U300_CONFIG_BIAS_UNKNOWN: this bias mode is not known to us
31 * GPIO_U300_CONFIG_BIAS_FLOAT: no specific bias, the GPIO will float or state
32 * is not controlled by software
33 * GPIO_U300_CONFIG_BIAS_PULL_UP: the GPIO will be pulled up (usually with high
34 * impedance to VDD)
35 */
36#define GPIO_U300_CONFIG_BIAS_UNKNOWN 0x1000
37#define GPIO_U300_CONFIG_BIAS_FLOAT 0x1001
38#define GPIO_U300_CONFIG_BIAS_PULL_UP 0x1002
27 39
28/* Memory resource */ 40/*
29static struct resource *memres; 41 * Drive modes for U300 GPIOs (output)
30static void __iomem *virtbase; 42 *
31static struct device *gpiodev; 43 * GPIO_U300_CONFIG_DRIVE_PUSH_PULL: the GPIO will be driven actively high and
44 * low, this is the most typical case and is typically achieved with two
45 * active transistors on the output
46 * GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN: the GPIO will be driven with open drain
47 * (open collector) which means it is usually wired with other output
48 * ports which are then pulled up with an external resistor
49 * GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE: the GPIO will be driven with open drain
50 * (open emitter) which is the same as open drain mutatis mutandis but
51 * pulled to ground
52 */
53#define GPIO_U300_CONFIG_DRIVE_PUSH_PULL 0x2000
54#define GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN 0x2001
55#define GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE 0x2002
56
57/*
58 * Register definitions for COH 901 335 variant
59 */
60#define U300_335_PORT_STRIDE (0x1C)
61/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
62#define U300_335_PXPDIR (0x00)
63#define U300_335_PXPDOR (0x00)
64/* Port X Pin Config Register 32bit (R/W) */
65#define U300_335_PXPCR (0x04)
66/* This register layout is the same in both blocks */
67#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
68#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
69#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
70#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
71#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
72#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
73#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
74/* Port X Interrupt Event Register 32bit (R/W) */
75#define U300_335_PXIEV (0x08)
76/* Port X Interrupt Enable Register 32bit (R/W) */
77#define U300_335_PXIEN (0x0C)
78/* Port X Interrupt Force Register 32bit (R/W) */
79#define U300_335_PXIFR (0x10)
80/* Port X Interrupt Config Register 32bit (R/W) */
81#define U300_335_PXICR (0x14)
82/* This register layout is the same in both blocks */
83#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
84#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
85#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
86#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
87/* Port X Pull-up Enable Register 32bit (R/W) */
88#define U300_335_PXPER (0x18)
89/* This register layout is the same in both blocks */
90#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
91#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
92/* Control Register 32bit (R/W) */
93#define U300_335_CR (0x54)
94#define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
95
96/*
97 * Register definitions for COH 901 571 / 3 variant
98 */
99#define U300_571_PORT_STRIDE (0x30)
100/*
101 * Control Register 32bit (R/W)
102 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
103 * gives the number of GPIO pins.
104 * bit 8-2 (mask 0x000001FC) contains the core version ID.
105 */
106#define U300_571_CR (0x00)
107#define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL)
108#define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
109/*
110 * These registers have the same layout and function as the corresponding
111 * COH 901 335 registers, just at different offset.
112 */
113#define U300_571_PXPDIR (0x04)
114#define U300_571_PXPDOR (0x08)
115#define U300_571_PXPCR (0x0C)
116#define U300_571_PXPER (0x10)
117#define U300_571_PXIEV (0x14)
118#define U300_571_PXIEN (0x18)
119#define U300_571_PXIFR (0x1C)
120#define U300_571_PXICR (0x20)
121
122/* 8 bits per port, no version has more than 7 ports */
123#define U300_GPIO_PINS_PER_PORT 8
124#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
125
126struct u300_gpio {
127 struct gpio_chip chip;
128 struct list_head port_list;
129 struct clk *clk;
130 struct resource *memres;
131 void __iomem *base;
132 struct device *dev;
133 int irq_base;
134 u32 stride;
135 /* Register offsets */
136 u32 pcr;
137 u32 dor;
138 u32 dir;
139 u32 per;
140 u32 icr;
141 u32 ien;
142 u32 iev;
143};
32 144
33struct u300_gpio_port { 145struct u300_gpio_port {
34 const char *name; 146 struct list_head node;
147 struct u300_gpio *gpio;
148 char name[8];
35 int irq; 149 int irq;
36 int number; 150 int number;
151 u8 toggle_edge_mode;
37}; 152};
38 153
154/*
155 * Macro to expand to read a specific register found in the "gpio"
156 * struct. It requires the struct u300_gpio *gpio variable to exist in
157 * its context. It calculates the port offset from the given pin
158 * offset, muliplies by the port stride and adds the register offset
159 * so it provides a pointer to the desired register.
160 */
161#define U300_PIN_REG(pin, reg) \
162 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
39 163
40static struct u300_gpio_port gpio_ports[] = { 164/*
41 { 165 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
42 .name = "gpio0", 166 * register.
43 .number = 0, 167 */
44 }, 168#define U300_PIN_BIT(pin) \
45 { 169 (1 << (pin & 0x07))
46 .name = "gpio1",
47 .number = 1,
48 },
49 {
50 .name = "gpio2",
51 .number = 2,
52 },
53#ifdef U300_COH901571_3
54 {
55 .name = "gpio3",
56 .number = 3,
57 },
58 {
59 .name = "gpio4",
60 .number = 4,
61 },
62#ifdef CONFIG_MACH_U300_BS335
63 {
64 .name = "gpio5",
65 .number = 5,
66 },
67 {
68 .name = "gpio6",
69 .number = 6,
70 },
71#endif
72#endif
73 170
171struct u300_gpio_confdata {
172 u16 bias_mode;
173 bool output;
174 int outval;
74}; 175};
75 176
177/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
178#define BS335_GPIO_NUM_PORTS 7
179/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
180#define BS365_GPIO_NUM_PORTS 5
76 181
77#ifdef U300_COH901571_3 182#define U300_FLOATING_INPUT { \
183 .bias_mode = GPIO_U300_CONFIG_BIAS_FLOAT, \
184 .output = false, \
185}
78 186
79/* Default input value */ 187#define U300_PULL_UP_INPUT { \
80#define DEFAULT_OUTPUT_LOW 0 188 .bias_mode = GPIO_U300_CONFIG_BIAS_PULL_UP, \
81#define DEFAULT_OUTPUT_HIGH 1 189 .output = false, \
190}
82 191
83/* GPIO Pull-Up status */ 192#define U300_OUTPUT_LOW { \
84#define DISABLE_PULL_UP 0 193 .output = true, \
85#define ENABLE_PULL_UP 1 194 .outval = 0, \
195}
86 196
87#define GPIO_NOT_USED 0 197#define U300_OUTPUT_HIGH { \
88#define GPIO_IN 1 198 .output = true, \
89#define GPIO_OUT 2 199 .outval = 1, \
200}
90 201
91struct u300_gpio_configuration_data {
92 unsigned char pin_usage;
93 unsigned char default_output_value;
94 unsigned char pull_up;
95};
96 202
97/* Initial configuration */ 203/* Initial configuration */
98const struct u300_gpio_configuration_data 204static const struct __initdata u300_gpio_confdata
99u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 205bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
100#ifdef CONFIG_MACH_U300_BS335
101 /* Port 0, pins 0-7 */ 206 /* Port 0, pins 0-7 */
102 { 207 {
103 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 208 U300_FLOATING_INPUT,
104 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, 209 U300_OUTPUT_HIGH,
105 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 210 U300_FLOATING_INPUT,
106 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 211 U300_OUTPUT_LOW,
107 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 212 U300_OUTPUT_LOW,
108 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 213 U300_OUTPUT_LOW,
109 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 214 U300_OUTPUT_LOW,
110 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 215 U300_OUTPUT_LOW,
111 }, 216 },
112 /* Port 1, pins 0-7 */ 217 /* Port 1, pins 0-7 */
113 { 218 {
114 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 219 U300_OUTPUT_LOW,
115 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 220 U300_OUTPUT_LOW,
116 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 221 U300_OUTPUT_LOW,
117 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 222 U300_PULL_UP_INPUT,
118 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 223 U300_FLOATING_INPUT,
119 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, 224 U300_OUTPUT_HIGH,
120 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 225 U300_OUTPUT_LOW,
121 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 226 U300_OUTPUT_LOW,
122 }, 227 },
123 /* Port 2, pins 0-7 */ 228 /* Port 2, pins 0-7 */
124 { 229 {
125 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 230 U300_FLOATING_INPUT,
126 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 231 U300_FLOATING_INPUT,
127 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 232 U300_FLOATING_INPUT,
128 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 233 U300_FLOATING_INPUT,
129 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 234 U300_OUTPUT_LOW,
130 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 235 U300_PULL_UP_INPUT,
131 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 236 U300_OUTPUT_LOW,
132 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 237 U300_PULL_UP_INPUT,
133 }, 238 },
134 /* Port 3, pins 0-7 */ 239 /* Port 3, pins 0-7 */
135 { 240 {
136 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 241 U300_PULL_UP_INPUT,
137 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 242 U300_OUTPUT_LOW,
138 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 243 U300_FLOATING_INPUT,
139 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 244 U300_FLOATING_INPUT,
140 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 245 U300_FLOATING_INPUT,
141 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 246 U300_FLOATING_INPUT,
142 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 247 U300_FLOATING_INPUT,
143 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 248 U300_FLOATING_INPUT,
144 }, 249 },
145 /* Port 4, pins 0-7 */ 250 /* Port 4, pins 0-7 */
146 { 251 {
147 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 252 U300_FLOATING_INPUT,
148 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 253 U300_FLOATING_INPUT,
149 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 254 U300_FLOATING_INPUT,
150 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 255 U300_FLOATING_INPUT,
151 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 256 U300_FLOATING_INPUT,
152 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 257 U300_FLOATING_INPUT,
153 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 258 U300_FLOATING_INPUT,
154 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 259 U300_FLOATING_INPUT,
155 }, 260 },
156 /* Port 5, pins 0-7 */ 261 /* Port 5, pins 0-7 */
157 { 262 {
158 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 263 U300_FLOATING_INPUT,
159 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 264 U300_FLOATING_INPUT,
160 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 265 U300_FLOATING_INPUT,
161 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 266 U300_FLOATING_INPUT,
162 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 267 U300_FLOATING_INPUT,
163 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 268 U300_FLOATING_INPUT,
164 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 269 U300_FLOATING_INPUT,
165 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 270 U300_FLOATING_INPUT,
166 }, 271 },
167 /* Port 6, pind 0-7 */ 272 /* Port 6, pind 0-7 */
168 { 273 {
169 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 274 U300_FLOATING_INPUT,
170 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 275 U300_FLOATING_INPUT,
171 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 276 U300_FLOATING_INPUT,
172 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 277 U300_FLOATING_INPUT,
173 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 278 U300_FLOATING_INPUT,
174 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 279 U300_FLOATING_INPUT,
175 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 280 U300_FLOATING_INPUT,
176 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 281 U300_FLOATING_INPUT,
177 } 282 }
178#endif 283};
179 284
180#ifdef CONFIG_MACH_U300_BS365 285static const struct __initdata u300_gpio_confdata
286bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
181 /* Port 0, pins 0-7 */ 287 /* Port 0, pins 0-7 */
182 { 288 {
183 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 289 U300_FLOATING_INPUT,
184 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 290 U300_OUTPUT_LOW,
185 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 291 U300_FLOATING_INPUT,
186 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 292 U300_OUTPUT_LOW,
187 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 293 U300_OUTPUT_LOW,
188 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 294 U300_OUTPUT_LOW,
189 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 295 U300_PULL_UP_INPUT,
190 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 296 U300_FLOATING_INPUT,
191 }, 297 },
192 /* Port 1, pins 0-7 */ 298 /* Port 1, pins 0-7 */
193 { 299 {
194 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 300 U300_OUTPUT_LOW,
195 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 301 U300_FLOATING_INPUT,
196 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 302 U300_OUTPUT_LOW,
197 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 303 U300_FLOATING_INPUT,
198 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 304 U300_FLOATING_INPUT,
199 {GPIO_OUT, DEFAULT_OUTPUT_HIGH, DISABLE_PULL_UP}, 305 U300_OUTPUT_HIGH,
200 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 306 U300_OUTPUT_LOW,
201 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP} 307 U300_OUTPUT_LOW,
202 }, 308 },
203 /* Port 2, pins 0-7 */ 309 /* Port 2, pins 0-7 */
204 { 310 {
205 {GPIO_IN, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 311 U300_FLOATING_INPUT,
206 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 312 U300_PULL_UP_INPUT,
207 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 313 U300_OUTPUT_LOW,
208 {GPIO_OUT, DEFAULT_OUTPUT_LOW, DISABLE_PULL_UP}, 314 U300_OUTPUT_LOW,
209 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 315 U300_PULL_UP_INPUT,
210 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 316 U300_PULL_UP_INPUT,
211 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 317 U300_PULL_UP_INPUT,
212 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 318 U300_PULL_UP_INPUT,
213 }, 319 },
214 /* Port 3, pins 0-7 */ 320 /* Port 3, pins 0-7 */
215 { 321 {
216 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 322 U300_PULL_UP_INPUT,
217 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 323 U300_PULL_UP_INPUT,
218 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 324 U300_PULL_UP_INPUT,
219 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 325 U300_PULL_UP_INPUT,
220 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 326 U300_PULL_UP_INPUT,
221 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 327 U300_PULL_UP_INPUT,
222 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 328 U300_PULL_UP_INPUT,
223 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 329 U300_PULL_UP_INPUT,
224 }, 330 },
225 /* Port 4, pins 0-7 */ 331 /* Port 4, pins 0-7 */
226 { 332 {
227 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 333 U300_PULL_UP_INPUT,
228 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 334 U300_PULL_UP_INPUT,
229 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 335 U300_PULL_UP_INPUT,
230 {GPIO_IN, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 336 U300_PULL_UP_INPUT,
231 /* These 4 pins doesn't exist on DB3210 */ 337 /* These 4 pins doesn't exist on DB3210 */
232 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 338 U300_OUTPUT_LOW,
233 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 339 U300_OUTPUT_LOW,
234 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP}, 340 U300_OUTPUT_LOW,
235 {GPIO_OUT, DEFAULT_OUTPUT_LOW, ENABLE_PULL_UP} 341 U300_OUTPUT_LOW,
236 } 342 }
237#endif
238}; 343};
239#endif
240 344
241 345/**
242/* No users == we can power down GPIO */ 346 * to_u300_gpio() - get the pointer to u300_gpio
243static int gpio_users; 347 * @chip: the gpio chip member of the structure u300_gpio
244
245struct gpio_struct {
246 int (*callback)(void *);
247 void *data;
248 int users;
249};
250
251static struct gpio_struct gpio_pin[U300_GPIO_MAX];
252
253/*
254 * Let drivers register callback in order to get notified when there is
255 * an interrupt on the gpio pin
256 */ 348 */
257int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data) 349static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
258{ 350{
259 if (gpio_pin[gpio].callback) 351 return container_of(chip, struct u300_gpio, chip);
260 dev_warn(gpiodev, "%s: WARNING: callback already "
261 "registered for gpio pin#%d\n", __func__, gpio);
262 gpio_pin[gpio].callback = func;
263 gpio_pin[gpio].data = data;
264
265 return 0;
266} 352}
267EXPORT_SYMBOL(gpio_register_callback);
268 353
269int gpio_unregister_callback(unsigned gpio) 354static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
270{ 355{
271 if (!gpio_pin[gpio].callback) 356 struct u300_gpio *gpio = to_u300_gpio(chip);
272 dev_warn(gpiodev, "%s: WARNING: callback already "
273 "unregistered for gpio pin#%d\n", __func__, gpio);
274 gpio_pin[gpio].callback = NULL;
275 gpio_pin[gpio].data = NULL;
276 357
277 return 0; 358 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
278} 359}
279EXPORT_SYMBOL(gpio_unregister_callback);
280 360
281/* Non-zero means valid */ 361static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
282int gpio_is_valid(int number)
283{ 362{
284 if (number >= 0 && 363 struct u300_gpio *gpio = to_u300_gpio(chip);
285 number < (U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT)) 364 unsigned long flags;
286 return 1; 365 u32 val;
287 return 0;
288}
289EXPORT_SYMBOL(gpio_is_valid);
290 366
291int gpio_request(unsigned gpio, const char *label) 367 local_irq_save(flags);
292{
293 if (gpio_pin[gpio].users)
294 return -EINVAL;
295 else
296 gpio_pin[gpio].users++;
297 368
298 gpio_users++; 369 val = readl(U300_PIN_REG(offset, dor));
370 if (value)
371 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
372 else
373 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
299 374
300 return 0; 375 local_irq_restore(flags);
301} 376}
302EXPORT_SYMBOL(gpio_request);
303 377
304void gpio_free(unsigned gpio) 378static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
305{ 379{
306 gpio_users--; 380 struct u300_gpio *gpio = to_u300_gpio(chip);
307 gpio_pin[gpio].users--; 381 unsigned long flags;
308 if (unlikely(gpio_pin[gpio].users < 0)) { 382 u32 val;
309 dev_warn(gpiodev, "warning: gpio#%d release mismatch\n",
310 gpio);
311 gpio_pin[gpio].users = 0;
312 }
313
314 return;
315}
316EXPORT_SYMBOL(gpio_free);
317 383
318/* This returns zero or nonzero */ 384 local_irq_save(flags);
319int gpio_get_value(unsigned gpio) 385 val = readl(U300_PIN_REG(offset, pcr));
320{ 386 /* Mask out this pin, note 2 bits per setting */
321 return readl(virtbase + U300_GPIO_PXPDIR + 387 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
322 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07)); 388 writel(val, U300_PIN_REG(offset, pcr));
389 local_irq_restore(flags);
390 return 0;
323} 391}
324EXPORT_SYMBOL(gpio_get_value);
325 392
326/* 393static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
327 * We hope that the compiler will optimize away the unused branch 394 int value)
328 * in case "value" is a constant
329 */
330void gpio_set_value(unsigned gpio, int value)
331{ 395{
332 u32 val; 396 struct u300_gpio *gpio = to_u300_gpio(chip);
333 unsigned long flags; 397 unsigned long flags;
398 u32 oldmode;
399 u32 val;
334 400
335 local_irq_save(flags); 401 local_irq_save(flags);
336 if (value) { 402 val = readl(U300_PIN_REG(offset, pcr));
337 /* set */ 403 /*
338 val = readl(virtbase + U300_GPIO_PXPDOR + 404 * Drive mode must be set by the special mode set function, set
339 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) 405 * push/pull mode by default if no mode has been selected.
340 & (1 << (gpio & 0x07)); 406 */
341 writel(val | (1 << (gpio & 0x07)), virtbase + 407 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
342 U300_GPIO_PXPDOR + 408 ((offset & 0x07) << 1));
343 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING); 409 /* mode = 0 means input, else some mode is already set */
344 } else { 410 if (oldmode == 0) {
345 /* clear */ 411 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
346 val = readl(virtbase + U300_GPIO_PXPDOR + 412 ((offset & 0x07) << 1));
347 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) 413 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
348 & (1 << (gpio & 0x07)); 414 << ((offset & 0x07) << 1));
349 writel(val & ~(1 << (gpio & 0x07)), virtbase + 415 writel(val, U300_PIN_REG(offset, pcr));
350 U300_GPIO_PXPDOR +
351 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
352 } 416 }
417 u300_gpio_set(chip, offset, value);
353 local_irq_restore(flags); 418 local_irq_restore(flags);
419 return 0;
354} 420}
355EXPORT_SYMBOL(gpio_set_value);
356 421
357int gpio_direction_input(unsigned gpio) 422static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
358{ 423{
424 struct u300_gpio *gpio = to_u300_gpio(chip);
425 int retirq = gpio->irq_base + offset;
426
427 dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d\n", offset,
428 retirq);
429 return retirq;
430}
431
432static int u300_gpio_config(struct gpio_chip *chip, unsigned offset,
433 u16 param, unsigned long *data)
434{
435 struct u300_gpio *gpio = to_u300_gpio(chip);
359 unsigned long flags; 436 unsigned long flags;
360 u32 val; 437 u32 val;
361 438
362 if (gpio > U300_GPIO_MAX)
363 return -EINVAL;
364
365 local_irq_save(flags); 439 local_irq_save(flags);
366 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * 440 switch (param) {
367 U300_GPIO_PORTX_SPACING); 441 case GPIO_U300_CONFIG_BIAS_UNKNOWN:
368 /* Mask out this pin*/ 442 case GPIO_U300_CONFIG_BIAS_FLOAT:
369 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1)); 443 val = readl(U300_PIN_REG(offset, per));
370 /* This is not needed since it sets the bits to zero.*/ 444 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
371 /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */ 445 break;
372 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * 446 case GPIO_U300_CONFIG_BIAS_PULL_UP:
373 U300_GPIO_PORTX_SPACING); 447 val = readl(U300_PIN_REG(offset, per));
448 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
449 break;
450 case GPIO_U300_CONFIG_DRIVE_PUSH_PULL:
451 val = readl(U300_PIN_REG(offset, pcr));
452 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
453 << ((offset & 0x07) << 1));
454 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
455 << ((offset & 0x07) << 1));
456 writel(val, U300_PIN_REG(offset, pcr));
457 break;
458 case GPIO_U300_CONFIG_DRIVE_OPEN_DRAIN:
459 val = readl(U300_PIN_REG(offset, pcr));
460 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
461 << ((offset & 0x07) << 1));
462 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
463 << ((offset & 0x07) << 1));
464 writel(val, U300_PIN_REG(offset, pcr));
465 break;
466 case GPIO_U300_CONFIG_DRIVE_OPEN_SOURCE:
467 val = readl(U300_PIN_REG(offset, pcr));
468 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
469 << ((offset & 0x07) << 1));
470 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
471 << ((offset & 0x07) << 1));
472 writel(val, U300_PIN_REG(offset, pcr));
473 break;
474 default:
475 local_irq_restore(flags);
476 dev_err(gpio->dev, "illegal configuration requested\n");
477 return -EINVAL;
478 }
374 local_irq_restore(flags); 479 local_irq_restore(flags);
375 return 0; 480 return 0;
376} 481}
377EXPORT_SYMBOL(gpio_direction_input);
378 482
379int gpio_direction_output(unsigned gpio, int value) 483static struct gpio_chip u300_gpio_chip = {
484 .label = "u300-gpio-chip",
485 .owner = THIS_MODULE,
486 .get = u300_gpio_get,
487 .set = u300_gpio_set,
488 .direction_input = u300_gpio_direction_input,
489 .direction_output = u300_gpio_direction_output,
490 .to_irq = u300_gpio_to_irq,
491};
492
493static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
380{ 494{
381 unsigned long flags;
382 u32 val; 495 u32 val;
383 496
384 if (gpio > U300_GPIO_MAX) 497 val = readl(U300_PIN_REG(offset, icr));
385 return -EINVAL; 498 /* Set mode depending on state */
386 499 if (u300_gpio_get(&gpio->chip, offset)) {
387 local_irq_save(flags); 500 /* High now, let's trigger on falling edge next then */
388 val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) * 501 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
389 U300_GPIO_PORTX_SPACING); 502 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
390 /* Mask out this pin */ 503 offset);
391 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1)); 504 } else {
392 /* 505 /* Low now, let's trigger on rising edge next then */
393 * FIXME: configure for push/pull, open drain or open source per pin 506 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
394 * in setup. The current driver will only support push/pull. 507 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
395 */ 508 offset);
396 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL 509 }
397 << ((gpio & 0x07) << 1));
398 writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
399 U300_GPIO_PORTX_SPACING);
400 gpio_set_value(gpio, value);
401 local_irq_restore(flags);
402 return 0;
403} 510}
404EXPORT_SYMBOL(gpio_direction_output);
405 511
406/* 512static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
407 * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
408 */
409void enable_irq_on_gpio_pin(unsigned gpio, int edge)
410{ 513{
514 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
515 struct u300_gpio *gpio = port->gpio;
516 int offset = d->irq - gpio->irq_base;
411 u32 val; 517 u32 val;
412 unsigned long flags;
413 local_irq_save(flags);
414 518
415 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * 519 if ((trigger & IRQF_TRIGGER_RISING) &&
416 U300_GPIO_PORTX_SPACING); 520 (trigger & IRQF_TRIGGER_FALLING)) {
417 val |= (1 << (gpio & 0x07)); 521 /*
418 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * 522 * The GPIO block can only trigger on falling OR rising edges,
419 U300_GPIO_PORTX_SPACING); 523 * not both. So we need to toggle the mode whenever the pin
420 val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) * 524 * goes from one state to the other with a special state flag
421 U300_GPIO_PORTX_SPACING); 525 */
422 if (edge) 526 dev_dbg(gpio->dev,
423 val |= (1 << (gpio & 0x07)); 527 "trigger on both rising and falling edge on pin %d\n",
424 else 528 offset);
425 val &= ~(1 << (gpio & 0x07)); 529 port->toggle_edge_mode |= U300_PIN_BIT(offset);
426 writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) * 530 u300_toggle_trigger(gpio, offset);
427 U300_GPIO_PORTX_SPACING); 531 } else if (trigger & IRQF_TRIGGER_RISING) {
428 local_irq_restore(flags); 532 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
533 offset);
534 val = readl(U300_PIN_REG(offset, icr));
535 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
536 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
537 } else if (trigger & IRQF_TRIGGER_FALLING) {
538 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
539 offset);
540 val = readl(U300_PIN_REG(offset, icr));
541 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
542 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
543 }
544
545 return 0;
429} 546}
430EXPORT_SYMBOL(enable_irq_on_gpio_pin);
431 547
432void disable_irq_on_gpio_pin(unsigned gpio) 548static void u300_gpio_irq_enable(struct irq_data *d)
433{ 549{
550 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
551 struct u300_gpio *gpio = port->gpio;
552 int offset = d->irq - gpio->irq_base;
434 u32 val; 553 u32 val;
435 unsigned long flags; 554 unsigned long flags;
436 555
437 local_irq_save(flags); 556 local_irq_save(flags);
438 val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) * 557 val = readl(U300_PIN_REG(offset, ien));
439 U300_GPIO_PORTX_SPACING); 558 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
440 val &= ~(1 << (gpio & 0x07));
441 writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
442 U300_GPIO_PORTX_SPACING);
443 local_irq_restore(flags); 559 local_irq_restore(flags);
444} 560}
445EXPORT_SYMBOL(disable_irq_on_gpio_pin);
446 561
447/* Enable (value == 0) or disable (value == 1) internal pullup */ 562static void u300_gpio_irq_disable(struct irq_data *d)
448void gpio_pullup(unsigned gpio, int value)
449{ 563{
564 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
565 struct u300_gpio *gpio = port->gpio;
566 int offset = d->irq - gpio->irq_base;
450 u32 val; 567 u32 val;
451 unsigned long flags; 568 unsigned long flags;
452 569
453 local_irq_save(flags); 570 local_irq_save(flags);
454 if (value) { 571 val = readl(U300_PIN_REG(offset, ien));
455 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) * 572 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
456 U300_GPIO_PORTX_SPACING);
457 writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
458 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
459 } else {
460 val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
461 U300_GPIO_PORTX_SPACING);
462 writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
463 PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
464 }
465 local_irq_restore(flags); 573 local_irq_restore(flags);
466} 574}
467EXPORT_SYMBOL(gpio_pullup);
468 575
469static irqreturn_t gpio_irq_handler(int irq, void *dev_id) 576static struct irq_chip u300_gpio_irqchip = {
577 .name = "u300-gpio-irqchip",
578 .irq_enable = u300_gpio_irq_enable,
579 .irq_disable = u300_gpio_irq_disable,
580 .irq_set_type = u300_gpio_irq_type,
581
582};
583
584static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
470{ 585{
471 struct u300_gpio_port *port = dev_id; 586 struct u300_gpio_port *port = irq_get_handler_data(irq);
472 u32 val; 587 struct u300_gpio *gpio = port->gpio;
473 int pin; 588 int pinoffset = port->number << 3; /* get the right stride */
589 unsigned long val;
474 590
591 desc->irq_data.chip->irq_ack(&desc->irq_data);
475 /* Read event register */ 592 /* Read event register */
476 val = readl(virtbase + U300_GPIO_PXIEV + port->number * 593 val = readl(U300_PIN_REG(pinoffset, iev));
477 U300_GPIO_PORTX_SPACING);
478 /* Mask with enable register */
479 val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
480 U300_GPIO_PORTX_SPACING);
481 /* Mask relevant bits */ 594 /* Mask relevant bits */
482 val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK; 595 val &= 0xFFU; /* 8 bits per port */
483 /* ACK IRQ (clear event) */ 596 /* ACK IRQ (clear event) */
484 writel(val, virtbase + U300_GPIO_PXIEV + port->number * 597 writel(val, U300_PIN_REG(pinoffset, iev));
485 U300_GPIO_PORTX_SPACING); 598
486 /* Print message */ 599 /* Call IRQ handler */
487 while (val != 0) { 600 if (val != 0) {
488 unsigned gpio; 601 int irqoffset;
489 602
490 pin = __ffs(val); 603 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
491 /* mask off this pin */ 604 int pin_irq = gpio->irq_base + (port->number << 3)
492 val &= ~(1 << pin); 605 + irqoffset;
493 gpio = (port->number << 3) + pin; 606 int offset = pinoffset + irqoffset;
494 607
495 if (gpio_pin[gpio].callback) 608 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
496 (void)gpio_pin[gpio].callback(gpio_pin[gpio].data); 609 pin_irq, offset);
497 else 610 generic_handle_irq(pin_irq);
498 dev_dbg(gpiodev, "stray GPIO IRQ on line %d\n", 611 /*
499 gpio); 612 * Triggering IRQ on both rising and falling edge
613 * needs mockery
614 */
615 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
616 u300_toggle_trigger(gpio, offset);
617 }
500 } 618 }
501 return IRQ_HANDLED; 619
620 desc->irq_data.chip->irq_unmask(&desc->irq_data);
502} 621}
503 622
504static void gpio_set_initial_values(void) 623static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
624 int offset,
625 const struct u300_gpio_confdata *conf)
505{ 626{
506#ifdef U300_COH901571_3 627 /* Set mode: input or output */
507 int i, j; 628 if (conf->output) {
508 unsigned long flags; 629 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
509 u32 val;
510 630
511 /* Write default values to all pins */ 631 /* Deactivate bias mode for output */
512 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { 632 u300_gpio_config(&gpio->chip, offset,
513 val = 0; 633 GPIO_U300_CONFIG_BIAS_FLOAT,
514 for (j = 0; j < 8; j++) 634 NULL);
515 val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j; 635
516 local_irq_save(flags); 636 /* Set drive mode for output */
517 writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING); 637 u300_gpio_config(&gpio->chip, offset,
518 local_irq_restore(flags); 638 GPIO_U300_CONFIG_DRIVE_PUSH_PULL, NULL);
639
640 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
641 offset, conf->outval);
642 } else {
643 u300_gpio_direction_input(&gpio->chip, offset);
644
645 /* Always set output low on input pins */
646 u300_gpio_set(&gpio->chip, offset, 0);
647
648 /* Set bias mode for input */
649 u300_gpio_config(&gpio->chip, offset, conf->bias_mode, NULL);
650
651 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
652 offset, conf->bias_mode);
519 } 653 }
654}
520 655
521 /* 656static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
522 * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED' 657 struct u300_gpio_platform *plat)
523 * to output and 'GPIO_IN' to input for each port. And initialize 658{
524 * default value on outputs. 659 int i, j;
525 */ 660
526 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { 661 /* Write default config and values to all pins */
527 for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) { 662 for (i = 0; i < plat->ports; i++) {
528 local_irq_save(flags); 663 for (j = 0; j < 8; j++) {
529 val = readl(virtbase + U300_GPIO_PXPCR + 664 const struct u300_gpio_confdata *conf;
530 i * U300_GPIO_PORTX_SPACING); 665 int offset = (i*8) + j;
531 /* Mask out this pin */ 666
532 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1)); 667 if (plat->variant == U300_GPIO_COH901571_3_BS335)
533 668 conf = &bs335_gpio_config[i][j];
534 if (u300_gpio_config[i][j].pin_usage != GPIO_IN) 669 else if (plat->variant == U300_GPIO_COH901571_3_BS365)
535 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1)); 670 conf = &bs365_gpio_config[i][j];
536 writel(val, virtbase + U300_GPIO_PXPCR + 671 else
537 i * U300_GPIO_PORTX_SPACING); 672 break;
538 local_irq_restore(flags); 673
674 u300_gpio_init_pin(gpio, offset, conf);
539 } 675 }
540 } 676 }
677}
541 678
542 /* Enable or disable the internal pull-ups in the GPIO ASIC block */ 679static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
543 for (i = 0; i < U300_GPIO_MAX; i++) { 680{
544 val = 0; 681 struct u300_gpio_port *port;
545 for (j = 0; j < 8; j++) 682 struct list_head *p, *n;
546 val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j); 683
547 local_irq_save(flags); 684 list_for_each_safe(p, n, &gpio->port_list) {
548 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING); 685 port = list_entry(p, struct u300_gpio_port, node);
549 local_irq_restore(flags); 686 list_del(&port->node);
687 free_irq(port->irq, port);
688 kfree(port);
550 } 689 }
551#endif
552} 690}
553 691
554static int __init gpio_probe(struct platform_device *pdev) 692static int __init u300_gpio_probe(struct platform_device *pdev)
555{ 693{
556 u32 val; 694 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
695 struct u300_gpio *gpio;
557 int err = 0; 696 int err = 0;
697 int portno;
698 u32 val;
699 u32 ifr;
558 int i; 700 int i;
559 int num_irqs;
560 701
561 gpiodev = &pdev->dev; 702 gpio = kzalloc(sizeof(struct u300_gpio), GFP_KERNEL);
562 memset(gpio_pin, 0, sizeof(gpio_pin)); 703 if (gpio == NULL) {
704 dev_err(&pdev->dev, "failed to allocate memory\n");
705 return -ENOMEM;
706 }
707
708 gpio->chip = u300_gpio_chip;
709 gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
710 gpio->irq_base = plat->gpio_irq_base;
711 gpio->chip.dev = &pdev->dev;
712 gpio->chip.base = plat->gpio_base;
713 gpio->dev = &pdev->dev;
563 714
564 /* Get GPIO clock */ 715 /* Get GPIO clock */
565 clk = clk_get(&pdev->dev, NULL); 716 gpio->clk = clk_get(gpio->dev, NULL);
566 if (IS_ERR(clk)) { 717 if (IS_ERR(gpio->clk)) {
567 err = PTR_ERR(clk); 718 err = PTR_ERR(gpio->clk);
568 dev_err(gpiodev, "could not get GPIO clock\n"); 719 dev_err(gpio->dev, "could not get GPIO clock\n");
569 goto err_no_clk; 720 goto err_no_clk;
570 } 721 }
571 err = clk_enable(clk); 722 err = clk_enable(gpio->clk);
572 if (err) { 723 if (err) {
573 dev_err(gpiodev, "could not enable GPIO clock\n"); 724 dev_err(gpio->dev, "could not enable GPIO clock\n");
574 goto err_no_clk_enable; 725 goto err_no_clk_enable;
575 } 726 }
576 727
577 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 728 gpio->memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
578 if (!memres) 729 if (!gpio->memres) {
730 dev_err(gpio->dev, "could not get GPIO memory resource\n");
731 err = -ENODEV;
579 goto err_no_resource; 732 goto err_no_resource;
733 }
580 734
581 if (!request_mem_region(memres->start, resource_size(memres), 735 if (!request_mem_region(gpio->memres->start,
736 resource_size(gpio->memres),
582 "GPIO Controller")) { 737 "GPIO Controller")) {
583 err = -ENODEV; 738 err = -ENODEV;
584 goto err_no_ioregion; 739 goto err_no_ioregion;
585 } 740 }
586 741
587 virtbase = ioremap(memres->start, resource_size(memres)); 742 gpio->base = ioremap(gpio->memres->start, resource_size(gpio->memres));
588 if (!virtbase) { 743 if (!gpio->base) {
589 err = -ENOMEM; 744 err = -ENOMEM;
590 goto err_no_ioremap; 745 goto err_no_ioremap;
591 } 746 }
592 dev_info(gpiodev, "remapped 0x%08x to %p\n", 747
593 memres->start, virtbase); 748 if (plat->variant == U300_GPIO_COH901335) {
594 749 dev_info(gpio->dev,
595#ifdef U300_COH901335 750 "initializing GPIO Controller COH 901 335\n");
596 dev_info(gpiodev, "initializing GPIO Controller COH 901 335\n"); 751 gpio->stride = U300_335_PORT_STRIDE;
597 /* Turn on the GPIO block */ 752 gpio->pcr = U300_335_PXPCR;
598 writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR); 753 gpio->dor = U300_335_PXPDOR;
599#endif 754 gpio->dir = U300_335_PXPDIR;
600 755 gpio->per = U300_335_PXPER;
601#ifdef U300_COH901571_3 756 gpio->icr = U300_335_PXICR;
602 dev_info(gpiodev, "initializing GPIO Controller COH 901 571/3\n"); 757 gpio->ien = U300_335_PXIEN;
603 val = readl(virtbase + U300_GPIO_CR); 758 gpio->iev = U300_335_PXIEV;
604 dev_info(gpiodev, "COH901571/3 block version: %d, " \ 759 ifr = U300_335_PXIFR;
605 "number of cores: %d\n", 760
606 ((val & 0x0000FE00) >> 9), 761 /* Turn on the GPIO block */
607 ((val & 0x000001FC) >> 2)); 762 writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
608 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR); 763 gpio->base + U300_335_CR);
609#endif 764 } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
610 765 plat->variant == U300_GPIO_COH901571_3_BS365) {
611 gpio_set_initial_values(); 766 dev_info(gpio->dev,
612 767 "initializing GPIO Controller COH 901 571/3\n");
613 for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) { 768 gpio->stride = U300_571_PORT_STRIDE;
614 769 gpio->pcr = U300_571_PXPCR;
615 gpio_ports[num_irqs].irq = 770 gpio->dor = U300_571_PXPDOR;
616 platform_get_irq_byname(pdev, 771 gpio->dir = U300_571_PXPDIR;
617 gpio_ports[num_irqs].name); 772 gpio->per = U300_571_PXPER;
618 773 gpio->icr = U300_571_PXICR;
619 err = request_irq(gpio_ports[num_irqs].irq, 774 gpio->ien = U300_571_PXIEN;
620 gpio_irq_handler, IRQF_DISABLED, 775 gpio->iev = U300_571_PXIEV;
621 gpio_ports[num_irqs].name, 776 ifr = U300_571_PXIFR;
622 &gpio_ports[num_irqs]); 777
623 if (err) { 778 val = readl(gpio->base + U300_571_CR);
624 dev_err(gpiodev, "cannot allocate IRQ for %s!\n", 779 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
625 gpio_ports[num_irqs].name); 780 "number of cores: %d totalling %d pins\n",
626 goto err_no_irq; 781 ((val & 0x000001FC) >> 2),
782 ((val & 0x0000FE00) >> 9),
783 ((val & 0x0000FE00) >> 9) * 8);
784 writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
785 gpio->base + U300_571_CR);
786 u300_gpio_init_coh901571(gpio, plat);
787 } else {
788 dev_err(gpio->dev, "unknown block variant\n");
789 err = -ENODEV;
790 goto err_unknown_variant;
791 }
792
793 /* Add each port with its IRQ separately */
794 INIT_LIST_HEAD(&gpio->port_list);
795 for (portno = 0 ; portno < plat->ports; portno++) {
796 struct u300_gpio_port *port =
797 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
798
799 if (!port) {
800 dev_err(gpio->dev, "out of memory\n");
801 err = -ENOMEM;
802 goto err_no_port;
627 } 803 }
628 /* Turns off PortX_irq_force */ 804
629 writel(0x0, virtbase + U300_GPIO_PXIFR + 805 snprintf(port->name, 8, "gpio%d", portno);
630 num_irqs * U300_GPIO_PORTX_SPACING); 806 port->number = portno;
807 port->gpio = gpio;
808
809 port->irq = platform_get_irq_byname(pdev,
810 port->name);
811
812 dev_dbg(gpio->dev, "register IRQ %d for %s\n", port->irq,
813 port->name);
814
815 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
816 irq_set_handler_data(port->irq, port);
817
818 /* For each GPIO pin set the unique IRQ handler */
819 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
820 int irqno = gpio->irq_base + (portno << 3) + i;
821
822 dev_dbg(gpio->dev, "handler for IRQ %d on %s\n",
823 irqno, port->name);
824 irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
825 handle_simple_irq);
826 set_irq_flags(irqno, IRQF_VALID);
827 irq_set_chip_data(irqno, port);
828 }
829
830 /* Turns off irq force (test register) for this port */
831 writel(0x0, gpio->base + portno * gpio->stride + ifr);
832
833 list_add_tail(&port->node, &gpio->port_list);
631 } 834 }
835 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
836
837 err = gpiochip_add(&gpio->chip);
838 if (err) {
839 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
840 goto err_no_chip;
841 }
842
843 platform_set_drvdata(pdev, gpio);
632 844
633 return 0; 845 return 0;
634 846
635 err_no_irq: 847err_no_chip:
636 for (i = 0; i < num_irqs; i++) 848err_no_port:
637 free_irq(gpio_ports[i].irq, &gpio_ports[i]); 849 u300_gpio_free_ports(gpio);
638 iounmap(virtbase); 850err_unknown_variant:
639 err_no_ioremap: 851 iounmap(gpio->base);
640 release_mem_region(memres->start, resource_size(memres)); 852err_no_ioremap:
641 err_no_ioregion: 853 release_mem_region(gpio->memres->start, resource_size(gpio->memres));
642 err_no_resource: 854err_no_ioregion:
643 clk_disable(clk); 855err_no_resource:
644 err_no_clk_enable: 856 clk_disable(gpio->clk);
645 clk_put(clk); 857err_no_clk_enable:
646 err_no_clk: 858 clk_put(gpio->clk);
647 dev_info(gpiodev, "module ERROR:%d\n", err); 859err_no_clk:
860 kfree(gpio);
861 dev_info(&pdev->dev, "module ERROR:%d\n", err);
648 return err; 862 return err;
649} 863}
650 864
651static int __exit gpio_remove(struct platform_device *pdev) 865static int __exit u300_gpio_remove(struct platform_device *pdev)
652{ 866{
653 int i; 867 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
868 struct u300_gpio *gpio = platform_get_drvdata(pdev);
869 int err;
654 870
655 /* Turn off the GPIO block */ 871 /* Turn off the GPIO block */
656 writel(0x00000000U, virtbase + U300_GPIO_CR); 872 if (plat->variant == U300_GPIO_COH901335)
657 for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++) 873 writel(0x00000000U, gpio->base + U300_335_CR);
658 free_irq(gpio_ports[i].irq, &gpio_ports[i]); 874 if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
659 iounmap(virtbase); 875 plat->variant == U300_GPIO_COH901571_3_BS365)
660 release_mem_region(memres->start, resource_size(memres)); 876 writel(0x00000000U, gpio->base + U300_571_CR);
661 clk_disable(clk); 877
662 clk_put(clk); 878 err = gpiochip_remove(&gpio->chip);
879 if (err < 0) {
880 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
881 return err;
882 }
883 u300_gpio_free_ports(gpio);
884 iounmap(gpio->base);
885 release_mem_region(gpio->memres->start,
886 resource_size(gpio->memres));
887 clk_disable(gpio->clk);
888 clk_put(gpio->clk);
889 platform_set_drvdata(pdev, NULL);
890 kfree(gpio);
663 return 0; 891 return 0;
664} 892}
665 893
666static struct platform_driver gpio_driver = { 894static struct platform_driver u300_gpio_driver = {
667 .driver = { 895 .driver = {
668 .name = "u300-gpio", 896 .name = "u300-gpio",
669 }, 897 },
670 .remove = __exit_p(gpio_remove), 898 .remove = __exit_p(u300_gpio_remove),
671}; 899};
672 900
673 901
674static int __init u300_gpio_init(void) 902static int __init u300_gpio_init(void)
675{ 903{
676 return platform_driver_probe(&gpio_driver, gpio_probe); 904 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
677} 905}
678 906
679static void __exit u300_gpio_exit(void) 907static void __exit u300_gpio_exit(void)
680{ 908{
681 platform_driver_unregister(&gpio_driver); 909 platform_driver_unregister(&u300_gpio_driver);
682} 910}
683 911
684arch_initcall(u300_gpio_init); 912arch_initcall(u300_gpio_init);
685module_exit(u300_gpio_exit); 913module_exit(u300_gpio_exit);
686 914
687MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 915MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
688 916MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
689#ifdef U300_COH901571_3
690MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
691#endif
692
693#ifdef U300_COH901335
694MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
695#endif
696
697MODULE_LICENSE("GPL"); 917MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 02:20:16 -0500