1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h
index e48ab3108ad..5b739411d62 100644
--- a/drivers/edac/edac_core.h
+++ b/drivers/edac/edac_core.h
@@ -107,13 +107,13 @@ extern int edac_debug_level;
 *
 * CPU caches (L1 and L2)
 * DMA engines
- * Core CPU swithces
+ * Core CPU switches
 * Fabric switch units
 * PCIe interface controllers
 * other EDAC/ECC type devices that can be monitored for
 * errors, etc.
 *
- * It allows for a 2 level set of hiearchry. For example:
+ * It allows for a 2 level set of hierarchy. For example:
 *
 * cache could be composed of L1, L2 and L3 levels of cache.
 * Each CPU core would have its own L1 cache, while sharing

diff --git a/drivers/edac/edac_core.h b/drivers/edac/edac_core.h index e48ab3108ad..5b739411d62 100644 --- a/drivers/edac/edac_core.h +++ b/drivers/edac/edac_core.h
@@ -107,13 +107,13 @@ extern int edac_debug_level;
107	*	107	*
108	* CPU caches (L1 and L2)	108	* CPU caches (L1 and L2)
109	* DMA engines	109	* DMA engines
110	* Core CPU swithces	110	* Core CPU switches
111	* Fabric switch units	111	* Fabric switch units
112	* PCIe interface controllers	112	* PCIe interface controllers
113	* other EDAC/ECC type devices that can be monitored for	113	* other EDAC/ECC type devices that can be monitored for
114	* errors, etc.	114	* errors, etc.
115	*	115	*
116	* It allows for a 2 level set of hiearchry. For example:	116	* It allows for a 2 level set of hierarchy. For example:
117	*	117	*
118	* cache could be composed of L1, L2 and L3 levels of cache.	118	* cache could be composed of L1, L2 and L3 levels of cache.
119	* Each CPU core would have its own L1 cache, while sharing	119	* Each CPU core would have its own L1 cache, while sharing