diff options
Diffstat (limited to 'drivers/edac/e7xxx_edac.c')
-rw-r--r-- | drivers/edac/e7xxx_edac.c | 44 |
1 files changed, 25 insertions, 19 deletions
diff --git a/drivers/edac/e7xxx_edac.c b/drivers/edac/e7xxx_edac.c index 68dea87b72e..5ed97f6eb34 100644 --- a/drivers/edac/e7xxx_edac.c +++ b/drivers/edac/e7xxx_edac.c | |||
@@ -347,11 +347,12 @@ static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, | |||
347 | int dev_idx, u32 drc) | 347 | int dev_idx, u32 drc) |
348 | { | 348 | { |
349 | unsigned long last_cumul_size; | 349 | unsigned long last_cumul_size; |
350 | int index; | 350 | int index, j; |
351 | u8 value; | 351 | u8 value; |
352 | u32 dra, cumul_size; | 352 | u32 dra, cumul_size; |
353 | int drc_chan, drc_drbg, drc_ddim, mem_dev; | 353 | int drc_chan, drc_drbg, drc_ddim, mem_dev; |
354 | struct csrow_info *csrow; | 354 | struct csrow_info *csrow; |
355 | struct dimm_info *dimm; | ||
355 | 356 | ||
356 | pci_read_config_dword(pdev, E7XXX_DRA, &dra); | 357 | pci_read_config_dword(pdev, E7XXX_DRA, &dra); |
357 | drc_chan = dual_channel_active(drc, dev_idx); | 358 | drc_chan = dual_channel_active(drc, dev_idx); |
@@ -381,24 +382,29 @@ static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev, | |||
381 | csrow->last_page = cumul_size - 1; | 382 | csrow->last_page = cumul_size - 1; |
382 | csrow->nr_pages = cumul_size - last_cumul_size; | 383 | csrow->nr_pages = cumul_size - last_cumul_size; |
383 | last_cumul_size = cumul_size; | 384 | last_cumul_size = cumul_size; |
384 | csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ | 385 | |
385 | csrow->mtype = MEM_RDDR; /* only one type supported */ | 386 | for (j = 0; j < drc_chan + 1; j++) { |
386 | csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; | 387 | dimm = csrow->channels[j].dimm; |
387 | 388 | ||
388 | /* | 389 | dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */ |
389 | * if single channel or x8 devices then SECDED | 390 | dimm->mtype = MEM_RDDR; /* only one type supported */ |
390 | * if dual channel and x4 then S4ECD4ED | 391 | dimm->dtype = mem_dev ? DEV_X4 : DEV_X8; |
391 | */ | 392 | |
392 | if (drc_ddim) { | 393 | /* |
393 | if (drc_chan && mem_dev) { | 394 | * if single channel or x8 devices then SECDED |
394 | csrow->edac_mode = EDAC_S4ECD4ED; | 395 | * if dual channel and x4 then S4ECD4ED |
395 | mci->edac_cap |= EDAC_FLAG_S4ECD4ED; | 396 | */ |
396 | } else { | 397 | if (drc_ddim) { |
397 | csrow->edac_mode = EDAC_SECDED; | 398 | if (drc_chan && mem_dev) { |
398 | mci->edac_cap |= EDAC_FLAG_SECDED; | 399 | dimm->edac_mode = EDAC_S4ECD4ED; |
399 | } | 400 | mci->edac_cap |= EDAC_FLAG_S4ECD4ED; |
400 | } else | 401 | } else { |
401 | csrow->edac_mode = EDAC_NONE; | 402 | dimm->edac_mode = EDAC_SECDED; |
403 | mci->edac_cap |= EDAC_FLAG_SECDED; | ||
404 | } | ||
405 | } else | ||
406 | dimm->edac_mode = EDAC_NONE; | ||
407 | } | ||
402 | } | 408 | } |
403 | } | 409 | } |
404 | 410 | ||