1 files changed, 94 insertions, 33 deletions

diff --git a/drivers/dma/pch_dma.c b/drivers/dma/pch_dma.c
index ff5b38f9d45..1ac8d4b580b 100644
--- a/drivers/dma/pch_dma.c
+++ b/drivers/dma/pch_dma.c
@@ -45,7 +45,8 @@
 #define DMA_STATUS_MASK_BITS            0x3
 #define DMA_STATUS_SHIFT_BITS           16
 #define DMA_STATUS_IRQ(x)               (0x1 << (x))
-#define DMA_STATUS_ERR(x)               (0x1 << ((x) + 8))
+#define DMA_STATUS0_ERR(x)              (0x1 << ((x) + 8))
+#define DMA_STATUS2_ERR(x)              (0x1 << (x))
 
 #define DMA_DESC_WIDTH_SHIFT_BITS       12
 #define DMA_DESC_WIDTH_1_BYTE           (0x3 << DMA_DESC_WIDTH_SHIFT_BITS)
@@ -61,6 +62,9 @@
 
 #define MAX_CHAN_NR                     8
 
+#define DMA_MASK_CTL0_MODE      0x33333333
+#define DMA_MASK_CTL2_MODE      0x00003333
+
 static unsigned int init_nr_desc_per_channel = 64;
 module_param(init_nr_desc_per_channel, uint, 0644);
 MODULE_PARM_DESC(init_nr_desc_per_channel,
@@ -133,6 +137,7 @@ struct pch_dma {
 #define PCH_DMA_CTL3    0x0C
 #define PCH_DMA_STS0    0x10
 #define PCH_DMA_STS1    0x14
+#define PCH_DMA_STS2    0x18
 
 #define dma_readl(pd, name) \
         readl((pd)->membase + PCH_DMA_##name)
@@ -183,13 +188,19 @@ static void pdc_enable_irq(struct dma_chan *chan, int enable)
 {
         struct pch_dma *pd = to_pd(chan->device);
         u32 val;
+        int pos;
+
+        if (chan->chan_id < 8)
+                pos = chan->chan_id;
+        else
+                pos = chan->chan_id + 8;
 
         val = dma_readl(pd, CTL2);
 
         if (enable)
-                val |= 0x1 << chan->chan_id;
+                val |= 0x1 << pos;
         else
-                val &= ~(0x1 << chan->chan_id);
+                val &= ~(0x1 << pos);
 
         dma_writel(pd, CTL2, val);
 
@@ -202,10 +213,17 @@ static void pdc_set_dir(struct dma_chan *chan)
         struct pch_dma_chan *pd_chan = to_pd_chan(chan);
         struct pch_dma *pd = to_pd(chan->device);
         u32 val;
+        u32 mask_mode;
+        u32 mask_ctl;
 
         if (chan->chan_id < 8) {
                 val = dma_readl(pd, CTL0);
 
+                mask_mode = DMA_CTL0_MODE_MASK_BITS <<
+                                        (DMA_CTL0_BITS_PER_CH * chan->chan_id);
+                mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
+                                       (DMA_CTL0_BITS_PER_CH * chan->chan_id));
+                val &= mask_mode;
                 if (pd_chan->dir == DMA_TO_DEVICE)
                         val |= 0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
                                        DMA_CTL0_DIR_SHIFT_BITS);
@@ -213,18 +231,24 @@ static void pdc_set_dir(struct dma_chan *chan)
                         val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +
                                          DMA_CTL0_DIR_SHIFT_BITS));
 
+                val |= mask_ctl;
                 dma_writel(pd, CTL0, val);
         } else {
                 int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
                 val = dma_readl(pd, CTL3);
 
+                mask_mode = DMA_CTL0_MODE_MASK_BITS <<
+                                                (DMA_CTL0_BITS_PER_CH * ch);
+                mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
+                                                 (DMA_CTL0_BITS_PER_CH * ch));
+                val &= mask_mode;
                 if (pd_chan->dir == DMA_TO_DEVICE)
                         val |= 0x1 << (DMA_CTL0_BITS_PER_CH * ch +
                                        DMA_CTL0_DIR_SHIFT_BITS);
                 else
                         val &= ~(0x1 << (DMA_CTL0_BITS_PER_CH * ch +
                                          DMA_CTL0_DIR_SHIFT_BITS));
-
+                val |= mask_ctl;
                 dma_writel(pd, CTL3, val);
         }
 
@@ -236,33 +260,37 @@ static void pdc_set_mode(struct dma_chan *chan, u32 mode)
 {
         struct pch_dma *pd = to_pd(chan->device);
         u32 val;
+        u32 mask_ctl;
+        u32 mask_dir;
 
         if (chan->chan_id < 8) {
+                mask_ctl = DMA_MASK_CTL0_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
+                           (DMA_CTL0_BITS_PER_CH * chan->chan_id));
+                mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * chan->chan_id +\
+                                 DMA_CTL0_DIR_SHIFT_BITS);
                 val = dma_readl(pd, CTL0);
-
-                val &= ~(DMA_CTL0_MODE_MASK_BITS <<
-                        (DMA_CTL0_BITS_PER_CH * chan->chan_id));
+                val &= mask_dir;
                 val |= mode << (DMA_CTL0_BITS_PER_CH * chan->chan_id);
-
+                val |= mask_ctl;
                 dma_writel(pd, CTL0, val);
         } else {
                 int ch = chan->chan_id - 8; /* ch8-->0 ch9-->1 ... ch11->3 */
-
+                mask_ctl = DMA_MASK_CTL2_MODE & ~(DMA_CTL0_MODE_MASK_BITS <<
+                                                 (DMA_CTL0_BITS_PER_CH * ch));
+                mask_dir = 1 << (DMA_CTL0_BITS_PER_CH * ch +\
+                                 DMA_CTL0_DIR_SHIFT_BITS);
                 val = dma_readl(pd, CTL3);
-
-                val &= ~(DMA_CTL0_MODE_MASK_BITS <<
-                        (DMA_CTL0_BITS_PER_CH * ch));
+                val &= mask_dir;
                 val |= mode << (DMA_CTL0_BITS_PER_CH * ch);
-
+                val |= mask_ctl;
                 dma_writel(pd, CTL3, val);
-
         }
 
         dev_dbg(chan2dev(chan), "pdc_set_mode: chan %d -> %x\n",
                 chan->chan_id, val);
 }
 
-static u32 pdc_get_status(struct pch_dma_chan *pd_chan)
+static u32 pdc_get_status0(struct pch_dma_chan *pd_chan)
 {
         struct pch_dma *pd = to_pd(pd_chan->chan.device);
         u32 val;
@@ -272,9 +300,27 @@ static u32 pdc_get_status(struct pch_dma_chan *pd_chan)
                         DMA_STATUS_BITS_PER_CH * pd_chan->chan.chan_id));
 }
 
+static u32 pdc_get_status2(struct pch_dma_chan *pd_chan)
+{
+        struct pch_dma *pd = to_pd(pd_chan->chan.device);
+        u32 val;
+
+        val = dma_readl(pd, STS2);
+        return DMA_STATUS_MASK_BITS & (val >> (DMA_STATUS_SHIFT_BITS +
+                        DMA_STATUS_BITS_PER_CH * (pd_chan->chan.chan_id - 8)));
+}
+
 static bool pdc_is_idle(struct pch_dma_chan *pd_chan)
 {
-        if (pdc_get_status(pd_chan) == DMA_STATUS_IDLE)
+        u32 sts;
+
+        if (pd_chan->chan.chan_id < 8)
+                sts = pdc_get_status0(pd_chan);
+        else
+                sts = pdc_get_status2(pd_chan);
+
+
+        if (sts == DMA_STATUS_IDLE)
                 return true;
         else
                 return false;
@@ -495,11 +541,11 @@ static int pd_alloc_chan_resources(struct dma_chan *chan)
                 list_add_tail(&desc->desc_node, &tmp_list);
         }
 
-        spin_lock_bh(&pd_chan->lock);
+        spin_lock_irq(&pd_chan->lock);
         list_splice(&tmp_list, &pd_chan->free_list);
         pd_chan->descs_allocated = i;
         pd_chan->completed_cookie = chan->cookie = 1;
-        spin_unlock_bh(&pd_chan->lock);
+        spin_unlock_irq(&pd_chan->lock);
 
         pdc_enable_irq(chan, 1);
 
@@ -517,10 +563,10 @@ static void pd_free_chan_resources(struct dma_chan *chan)
         BUG_ON(!list_empty(&pd_chan->active_list));
         BUG_ON(!list_empty(&pd_chan->queue));
 
-        spin_lock_bh(&pd_chan->lock);
+        spin_lock_irq(&pd_chan->lock);
         list_splice_init(&pd_chan->free_list, &tmp_list);
         pd_chan->descs_allocated = 0;
-        spin_unlock_bh(&pd_chan->lock);
+        spin_unlock_irq(&pd_chan->lock);
 
         list_for_each_entry_safe(desc, _d, &tmp_list, desc_node)
                 pci_pool_free(pd->pool, desc, desc->txd.phys);
@@ -536,10 +582,10 @@ static enum dma_status pd_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
         dma_cookie_t last_completed;
         int ret;
 
-        spin_lock_bh(&pd_chan->lock);
+        spin_lock_irq(&pd_chan->lock);
         last_completed = pd_chan->completed_cookie;
         last_used = chan->cookie;
-        spin_unlock_bh(&pd_chan->lock);
+        spin_unlock_irq(&pd_chan->lock);
 
         ret = dma_async_is_complete(cookie, last_completed, last_used);
 
@@ -654,7 +700,7 @@ static int pd_device_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
         if (cmd != DMA_TERMINATE_ALL)
                 return -ENXIO;
 
-        spin_lock_bh(&pd_chan->lock);
+        spin_lock_irq(&pd_chan->lock);
 
         pdc_set_mode(&pd_chan->chan, DMA_CTL0_DISABLE);
 
@@ -664,7 +710,7 @@ static int pd_device_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
         list_for_each_entry_safe(desc, _d, &list, desc_node)
                 pdc_chain_complete(pd_chan, desc);
 
-        spin_unlock_bh(&pd_chan->lock);
+        spin_unlock_irq(&pd_chan->lock);
 
         return 0;
 }
@@ -693,30 +739,45 @@ static irqreturn_t pd_irq(int irq, void *devid)
         struct pch_dma *pd = (struct pch_dma *)devid;
         struct pch_dma_chan *pd_chan;
         u32 sts0;
+        u32 sts2;
         int i;
-        int ret = IRQ_NONE;
+        int ret0 = IRQ_NONE;
+        int ret2 = IRQ_NONE;
 
         sts0 = dma_readl(pd, STS0);
+        sts2 = dma_readl(pd, STS2);
 
         dev_dbg(pd->dma.dev, "pd_irq sts0: %x\n", sts0);
 
         for (i = 0; i < pd->dma.chancnt; i++) {
                 pd_chan = &pd->channels[i];
 
-                if (sts0 & DMA_STATUS_IRQ(i)) {
-                        if (sts0 & DMA_STATUS_ERR(i))
-                                set_bit(0, &pd_chan->err_status);
+                if (i < 8) {
+                        if (sts0 & DMA_STATUS_IRQ(i)) {
+                                if (sts0 & DMA_STATUS0_ERR(i))
+                                        set_bit(0, &pd_chan->err_status);
 
-                        tasklet_schedule(&pd_chan->tasklet);
-                        ret = IRQ_HANDLED;
-                }
+                                tasklet_schedule(&pd_chan->tasklet);
+                                ret0 = IRQ_HANDLED;
+                        }
+                } else {
+                        if (sts2 & DMA_STATUS_IRQ(i - 8)) {
+                                if (sts2 & DMA_STATUS2_ERR(i))
+                                        set_bit(0, &pd_chan->err_status);
 
+                                tasklet_schedule(&pd_chan->tasklet);
+                                ret2 = IRQ_HANDLED;
+                        }
+                }
         }
 
         /* clear interrupt bits in status register */
-        dma_writel(pd, STS0, sts0);
+        if (ret0)
+                dma_writel(pd, STS0, sts0);
+        if (ret2)
+                dma_writel(pd, STS2, sts2);
 
-        return ret;
+        return ret0 | ret2;
 }
 
 #ifdef  CONFIG_PM