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path: root/drivers/dma/intel_mid_dma.c
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Diffstat (limited to 'drivers/dma/intel_mid_dma.c')
-rw-r--r--drivers/dma/intel_mid_dma.c9
1 files changed, 3 insertions, 6 deletions
diff --git a/drivers/dma/intel_mid_dma.c b/drivers/dma/intel_mid_dma.c
index 8a3fdd87db9..9e96c43a846 100644
--- a/drivers/dma/intel_mid_dma.c
+++ b/drivers/dma/intel_mid_dma.c
@@ -115,16 +115,15 @@ DMAC1 interrupt Functions*/
115 115
116/** 116/**
117 * dmac1_mask_periphral_intr - mask the periphral interrupt 117 * dmac1_mask_periphral_intr - mask the periphral interrupt
118 * @midc: dma channel for which masking is required 118 * @mid: dma device for which masking is required
119 * 119 *
120 * Masks the DMA periphral interrupt 120 * Masks the DMA periphral interrupt
121 * this is valid for DMAC1 family controllers only 121 * this is valid for DMAC1 family controllers only
122 * This controller should have periphral mask registers already mapped 122 * This controller should have periphral mask registers already mapped
123 */ 123 */
124static void dmac1_mask_periphral_intr(struct intel_mid_dma_chan *midc) 124static void dmac1_mask_periphral_intr(struct middma_device *mid)
125{ 125{
126 u32 pimr; 126 u32 pimr;
127 struct middma_device *mid = to_middma_device(midc->chan.device);
128 127
129 if (mid->pimr_mask) { 128 if (mid->pimr_mask) {
130 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK); 129 pimr = readl(mid->mask_reg + LNW_PERIPHRAL_MASK);
@@ -184,7 +183,6 @@ static void enable_dma_interrupt(struct intel_mid_dma_chan *midc)
184static void disable_dma_interrupt(struct intel_mid_dma_chan *midc) 183static void disable_dma_interrupt(struct intel_mid_dma_chan *midc)
185{ 184{
186 /*Check LPE PISR, make sure fwd is disabled*/ 185 /*Check LPE PISR, make sure fwd is disabled*/
187 dmac1_mask_periphral_intr(midc);
188 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_BLOCK); 186 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_BLOCK);
189 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR); 187 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_TFR);
190 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR); 188 iowrite32(MASK_INTR_REG(midc->ch_id), midc->dma_base + MASK_ERR);
@@ -1114,7 +1112,6 @@ static int mid_setup_dma(struct pci_dev *pdev)
1114 1112
1115 midch->chan.device = &dma->common; 1113 midch->chan.device = &dma->common;
1116 midch->chan.cookie = 1; 1114 midch->chan.cookie = 1;
1117 midch->chan.chan_id = i;
1118 midch->ch_id = dma->chan_base + i; 1115 midch->ch_id = dma->chan_base + i;
1119 pr_debug("MDMA:Init CH %d, ID %d\n", i, midch->ch_id); 1116 pr_debug("MDMA:Init CH %d, ID %d\n", i, midch->ch_id);
1120 1117
@@ -1150,7 +1147,6 @@ static int mid_setup_dma(struct pci_dev *pdev)
1150 dma_cap_set(DMA_SLAVE, dma->common.cap_mask); 1147 dma_cap_set(DMA_SLAVE, dma->common.cap_mask);
1151 dma_cap_set(DMA_PRIVATE, dma->common.cap_mask); 1148 dma_cap_set(DMA_PRIVATE, dma->common.cap_mask);
1152 dma->common.dev = &pdev->dev; 1149 dma->common.dev = &pdev->dev;
1153 dma->common.chancnt = dma->max_chan;
1154 1150
1155 dma->common.device_alloc_chan_resources = 1151 dma->common.device_alloc_chan_resources =
1156 intel_mid_dma_alloc_chan_resources; 1152 intel_mid_dma_alloc_chan_resources;
@@ -1350,6 +1346,7 @@ int dma_suspend(struct pci_dev *pci, pm_message_t state)
1350 if (device->ch[i].in_use) 1346 if (device->ch[i].in_use)
1351 return -EAGAIN; 1347 return -EAGAIN;
1352 } 1348 }
1349 dmac1_mask_periphral_intr(device);
1353 device->state = SUSPENDED; 1350 device->state = SUSPENDED;
1354 pci_save_state(pci); 1351 pci_save_state(pci);
1355 pci_disable_device(pci); 1352 pci_disable_device(pci);