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-rw-r--r--drivers/ata/ahci-tegra.c1871
-rw-r--r--drivers/ata/pata_qdi.c366
2 files changed, 2237 insertions, 0 deletions
diff --git a/drivers/ata/ahci-tegra.c b/drivers/ata/ahci-tegra.c
new file mode 100644
index 00000000000..52b5820ac05
--- /dev/null
+++ b/drivers/ata/ahci-tegra.c
@@ -0,0 +1,1871 @@
1/*
2 * ahci-tegra.c - AHCI SATA support for TEGRA AHCI device
3 *
4 * Copyright (c) 2011, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; see the file COPYING. If not, write to
18 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 *
21 * libata documentation is available via 'make {ps|pdf}docs',
22 * as Documentation/DocBook/libata.*
23 *
24 * AHCI hardware documentation:
25 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
26 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
27 *
28 */
29
30#include <linux/platform_device.h>
31#include <linux/irq.h>
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/init.h>
35#include <linux/blkdev.h>
36#include <linux/delay.h>
37#include <linux/interrupt.h>
38#include <linux/dma-mapping.h>
39#include <linux/device.h>
40#include <linux/dmi.h>
41#include <scsi/scsi_host.h>
42#include <scsi/scsi_cmnd.h>
43#include <linux/libata.h>
44#include <linux/regulator/machine.h>
45#include "ahci.h"
46
47#include <linux/clk.h>
48#include <mach/clk.h>
49#include <mach/iomap.h>
50#include <mach/io.h>
51#include <mach/powergate.h>
52
53#define DRV_NAME "tegra-sata"
54#define DRV_VERSION "1.0"
55
56#define ENABLE_AHCI_DBG_PRINT 0
57#if ENABLE_AHCI_DBG_PRINT
58#define AHCI_DBG_PRINT(fmt, arg...) printk(KERN_ERR fmt, ## arg)
59#else
60#define AHCI_DBG_PRINT(fmt, arg...) do {} while (0)
61#endif
62
63/* number of AHCI ports */
64#define TEGRA_AHCI_NUM_PORTS 1
65
66/* idle timeout for PM in msec */
67#define TEGRA_AHCI_MIN_IDLE_TIME 1000
68#define TEGRA_AHCI_DEFAULT_IDLE_TIME 2000
69static u32 tegra_ahci_idle_time = TEGRA_AHCI_DEFAULT_IDLE_TIME;
70
71/* Bit 0 (EN_FPCI) to allow FPCI accesses to SATA */
72#define SATA_CONFIGURATION_0_OFFSET 0x180
73#define EN_FPCI (1 << 0)
74
75#define SATA_INTR_MASK_0_OFFSET 0x188
76#define IP_INT_MASK (1 << 16)
77
78/* Need to write 0x00400200 to 0x70020094 */
79#define SATA_FPCI_BAR5_0_OFFSET 0x094
80#define PRI_ICTLR_CPU_IER_SET_0_OFFSET 0x024
81#define CPU_IER_SATA_CTL (1 << 23)
82
83#define AHCI_BAR5_CONFIG_LOCATION 0x24
84#define TEGRA_SATA_BAR5_INIT_PROGRAM 0xFFFFFFFF
85#define TEGRA_SATA_BAR5_FINAL_PROGRAM 0x40020000
86
87#define FUSE_SATA_CALIB_OFFSET 0x224
88#define FUSE_SATA_CALIB_MASK 0x3
89
90#define T_SATA0_CFG_PHY_REG 0x120
91#define PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK (1 << 11)
92
93#define T_SATA0_CFG_POWER_GATE 0x4ac
94#define POWER_GATE_SSTS_RESTORED_MASK (1 << 23)
95#define POWER_GATE_SSTS_RESTORED_YES (1 << 23)
96#define POWER_GATE_SSTS_RESTORED_NO (0 << 23)
97
98#define T_SATA0_DBG0_OFFSET 0x550
99
100#define T_SATA0_INDEX_OFFSET 0x680
101#define SATA0_NONE_SELECTED 0
102#define SATA0_CH1_SELECTED (1 << 0)
103
104#define T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET 0x690
105#define SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
106#define SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK (0xff << 0)
107#define SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
108#define SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK (0xff << 8)
109
110#define T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET 0x694
111#define SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
112#define SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK (0xff << 0)
113#define SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
114#define SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK (0xff << 12)
115#define SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_SHIFT 24
116#define SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_MASK (0xf << 24)
117
118/* AHCI config space defines */
119#define TEGRA_PRIVATE_AHCI_CC_BKDR 0x4a4
120#define TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE 0x54c
121#define TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN (1 << 12)
122#define TEGRA_PRIVATE_AHCI_CC_BKDR_PGM 0x01060100
123
124/* AHCI HBA_CAP */
125#define TEGRA_PRIVATE_AHCI_CAP_BKDR 0xa0
126#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
127
128#define TEGRA_SATA_IO_SPACE_OFFSET 4
129#define TEGRA_SATA_ENABLE_IO_SPACE (1 << 0)
130#define TEGRA_SATA_ENABLE_MEM_SPACE (1 << 1)
131#define TEGRA_SATA_ENABLE_BUS_MASTER (1 << 2)
132#define TEGRA_SATA_ENABLE_SERR (1 << 8)
133
134#define TEGRA_SATA_CORE_CLOCK_FREQ_HZ (108*1000*1000)
135#define TEGRA_SATA_OOB_CLOCK_FREQ_HZ (216*1000*1000)
136
137#define APB_PMC_SATA_PWRGT_0_REG 0x1ac
138#define CLK_RST_SATA_PLL_CFG0_REG 0x490
139#define CLK_RST_SATA_PLL_CFG1_REG 0x494
140#define SATA_AUX_PAD_PLL_CNTL_1_REG 0x1100
141#define SATA_AUX_MISC_CNTL_1_REG 0x1108
142
143/* for APB_PMC_SATA_PWRGT_0_REG */
144#define PG_INFO_MASK (1 << 6)
145#define PG_INFO_ON (1 << 6)
146#define PG_INFO_OFF (0 << 6)
147#define PLLE_IDDQ_SWCTL_MASK (1 << 4)
148#define PLLE_IDDQ_SWCTL_ON (1 << 4)
149#define PLLE_IDDQ_SWCTL_OFF (0 << 4)
150#define PADPHY_IDDQ_OVERRIDE_VALUE_MASK (1 << 3)
151#define PADPHY_IDDQ_OVERRIDE_VALUE_ON (1 << 3)
152#define PADPHY_IDDQ_OVERRIDE_VALUE_OFF (0 << 3)
153#define PADPHY_IDDQ_SWCTL_MASK (1 << 2)
154#define PADPHY_IDDQ_SWCTL_ON (1 << 2)
155#define PADPHY_IDDQ_SWCTL_OFF (0 << 2)
156#define PADPLL_IDDQ_OVERRIDE_VALUE_MASK (1 << 1)
157#define PADPLL_IDDQ_OVERRIDE_VALUE_ON (1 << 1)
158#define PADPLL_IDDQ_OVERRIDE_VALUE_OFF (0 << 1)
159#define PADPLL_IDDQ_SWCTL_MASK (1 << 0)
160#define PADPLL_IDDQ_SWCTL_ON (1 << 0)
161#define PADPLL_IDDQ_SWCTL_OFF (0 << 0)
162
163/* for CLK_RST_SATA_PLL_CFG0_REG */
164#define PADPLL_RESET_OVERRIDE_VALUE_MASK (1 << 1)
165#define PADPLL_RESET_OVERRIDE_VALUE_ON (1 << 1)
166#define PADPLL_RESET_OVERRIDE_VALUE_OFF (0 << 1)
167#define PADPLL_RESET_SWCTL_MASK (1 << 0)
168#define PADPLL_RESET_SWCTL_ON (1 << 0)
169#define PADPLL_RESET_SWCTL_OFF (0 << 0)
170
171/* for CLK_RST_SATA_PLL_CFG1_REG */
172#define IDDQ2LANE_SLUMBER_DLY_MASK (0xffL << 16)
173#define IDDQ2LANE_SLUMBER_DLY_SHIFT 16
174#define IDDQ2LANE_SLUMBER_DLY_3MS (3 << 16)
175#define IDDQ2LANE_IDDQ_DLY_SHIFT 0
176#define IDDQ2LANE_IDDQ_DLY_MASK (0xffL << 0)
177
178/* for SATA_AUX_PAD_PLL_CNTL_1_REG */
179#define REFCLK_SEL_MASK (3 << 11)
180#define REFCLK_SEL_INT_CML (0 << 11)
181#define LOCKDET_FIELD (1 << 6)
182
183/* for SATA_AUX_MISC_CNTL_1_REG */
184#define NVA2SATA_OOB_ON_POR_MASK (1 << 7)
185#define NVA2SATA_OOB_ON_POR_YES (1 << 7)
186#define NVA2SATA_OOB_ON_POR_NO (0 << 7)
187#define L0_RX_IDLE_T_SAX_SHIFT 5
188#define L0_RX_IDLE_T_SAX_MASK (3 << 5)
189#define L0_RX_IDLE_T_NPG_SHIFT 3
190#define L0_RX_IDLE_T_NPG_MASK (3 << 3)
191#define L0_RX_IDLE_T_MUX_MASK (1 << 2)
192#define L0_RX_IDLE_T_MUX_FROM_APB_MISC (1 << 2)
193#define L0_RX_IDLE_T_MUX_FROM_SATA (0 << 2)
194
195#define SSTAT_IPM_STATE_MASK 0xF00
196#define SSTAT_IPM_SLUMBER_STATE 0x600
197
198enum {
199 AHCI_PCI_BAR = 5,
200};
201
202enum port_idle_status {
203 PORT_IS_NOT_IDLE,
204 PORT_IS_IDLE,
205 PORT_IS_IDLE_NOT_SLUMBER,
206 PORT_IS_SLUMBER,
207};
208
209static int tegra_ahci_init_one(struct platform_device *pdev);
210static int tegra_ahci_remove_one(struct platform_device *pdev);
211
212#ifdef CONFIG_PM
213static bool tegra_ahci_power_un_gate(struct ata_host *host);
214static bool tegra_ahci_power_gate(struct ata_host *host);
215static void tegra_ahci_abort_power_gate(struct ata_host *host);
216static int tegra_ahci_controller_suspend(struct platform_device *pdev);
217static int tegra_ahci_controller_resume(struct platform_device *pdev);
218static int tegra_ahci_suspend(struct platform_device *pdev, pm_message_t mesg);
219static int tegra_ahci_resume(struct platform_device *pdev);
220static void tegra_ahci_idle_timer(unsigned long arg);
221static enum port_idle_status tegra_ahci_is_port_idle(struct ata_port *ap);
222static enum port_idle_status tegra_ahci_is_port_slumber(struct ata_port *ap);
223static bool tegra_ahci_are_all_ports_idle(struct ata_host *host);
224static bool tegra_ahci_are_all_ports_slumber(struct ata_host *host);
225static unsigned int tegra_ahci_qc_issue(struct ata_queued_cmd *qc);
226#else
227#define tegra_ahci_controller_suspend NULL
228#define tegra_ahci_controller_resume NULL
229#define tegra_ahci_suspend NULL
230#define tegra_ahci_resume NULL
231#endif
232
233char *sata_power_rails[] = {
234 "avdd_sata",
235 "vdd_sata",
236 "hvdd_sata",
237 "avdd_sata_pll"
238};
239
240#define NUM_SATA_POWER_RAILS ARRAY_SIZE(sata_power_rails)
241
242/* tegra_ahci_host_priv is the extension of ahci_host_priv
243 * with extra fields: idle_timer, pg_save,
244 * pg_state, etc.
245 */
246struct tegra_ahci_host_priv {
247 struct ahci_host_priv ahci_host_priv;
248 struct regulator *power_rails[NUM_SATA_POWER_RAILS];
249 void __iomem *bars_table[6];
250 struct timer_list idle_timer;
251 void *pg_save;
252 u32 pg_state;
253};
254
255static struct scsi_host_template ahci_sht = {
256 AHCI_SHT("tegra-sata"),
257};
258
259static struct ata_port_operations tegra_ahci_ops = {
260 .inherits = &ahci_ops,
261#ifdef CONFIG_PM
262 .qc_issue = tegra_ahci_qc_issue,
263#endif
264};
265
266static const struct ata_port_info ahci_port_info = {
267 .flags = AHCI_FLAG_COMMON,
268 .pio_mask = 0x1f, /* pio0-4 */
269 .udma_mask = ATA_UDMA6,
270 .port_ops = &tegra_ahci_ops,
271};
272
273static struct platform_driver tegra_platform_ahci_driver = {
274 .probe = tegra_ahci_init_one,
275 .remove = __devexit_p(tegra_ahci_remove_one),
276 .suspend = tegra_ahci_suspend,
277 .resume = tegra_ahci_resume,
278 .driver = {
279 .name = DRV_NAME,
280 }
281};
282
283static inline u32 pmc_readl(u32 offset)
284{
285 u32 val;
286 val = readl(IO_ADDRESS(TEGRA_PMC_BASE + offset));
287 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_PMC_BASE+offset, val);
288 return val;
289}
290
291static inline void pmc_writel(u32 val, u32 offset)
292{
293 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_PMC_BASE+offset, val);
294 writel(val, IO_ADDRESS(TEGRA_PMC_BASE + offset));
295}
296
297static inline u32 clk_readl(u32 offset)
298{
299 u32 val;
300
301 val = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset));
302 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_CLK_RESET_BASE+offset, val);
303 return val;
304}
305
306static inline void clk_writel(u32 val, u32 offset)
307{
308 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_CLK_RESET_BASE+offset, val);
309 writel(val, IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset));
310}
311
312static inline u32 misc_readl(u32 offset)
313{
314 u32 val;
315
316 val = readl(IO_ADDRESS(TEGRA_APB_MISC_BASE + offset));
317 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_APB_MISC_BASE+offset, val);
318 return val;
319}
320
321static inline void misc_writel(u32 val, u32 offset)
322{
323 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_APB_MISC_BASE+offset, val);
324 writel(val, IO_ADDRESS(TEGRA_APB_MISC_BASE + offset));
325}
326
327static inline u32 sata_readl(u32 offset)
328{
329 u32 val;
330
331 val = readl(IO_ADDRESS(TEGRA_SATA_BASE + offset));
332 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_SATA_BASE+offset, val);
333 return val;
334}
335
336static inline void sata_writel(u32 val, u32 offset)
337{
338 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_BASE+offset, val);
339 writel(val, IO_ADDRESS(TEGRA_SATA_BASE + offset));
340}
341
342static inline u32 scfg_readl(u32 offset)
343{
344 u32 val;
345
346 val = readl(IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset));
347 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_SATA_CONFIG_BASE+offset,
348 val);
349 return val;
350}
351
352static inline void scfg_writel(u32 val, u32 offset)
353{
354 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_CONFIG_BASE+offset,
355 val);
356 writel(val, IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset));
357}
358
359static inline u32 pictlr_readl(u32 offset)
360{
361 u32 val;
362
363 val = readl(IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset));
364 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_PRIMARY_ICTLR_BASE+offset,
365 val);
366 return val;
367}
368
369static inline void pictlr_writel(u32 val, u32 offset)
370{
371 AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_PRIMARY_ICTLR_BASE+offset,
372 val);
373 writel(val, IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset));
374}
375
376static inline u32 fuse_readl(u32 offset)
377{
378 u32 val;
379
380 val = readl(IO_ADDRESS(TEGRA_FUSE_BASE + offset));
381 AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_FUSE_BASE+offset, val);
382
383 return val;
384}
385
386/* Sata Pad Cntrl Values */
387struct sata_pad_cntrl {
388 u8 gen1_tx_amp;
389 u8 gen1_tx_peak;
390 u8 gen2_tx_amp;
391 u8 gen2_tx_peak;
392};
393
394static const struct sata_pad_cntrl sata_calib_pad_val[] = {
395 { /* SATA_CALIB[1:0] = 00 */
396 0x0c,
397 0x04,
398 0x0e,
399 0x0a
400 },
401 { /* SATA_CALIB[1:0] = 01 */
402 0x0e,
403 0x04,
404 0x14,
405 0x0a
406 },
407 { /* SATA_CALIB[1:0] = 10 */
408 0x0e,
409 0x07,
410 0x1a,
411 0x0e
412 },
413 { /* SATA_CALIB[1:0] = 11 */
414 0x14,
415 0x0e,
416 0x1a,
417 0x0e
418 }
419};
420
421static void tegra_ahci_set_pad_cntrl_regs(void)
422{
423 int calib_val;
424 int val;
425 int i;
426
427 calib_val = fuse_readl(FUSE_SATA_CALIB_OFFSET) & FUSE_SATA_CALIB_MASK;
428
429 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
430 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
431
432 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
433 val &= ~SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
434 val |= (sata_calib_pad_val[calib_val].gen1_tx_amp <<
435 SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT);
436 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
437
438 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
439 val &= ~SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
440 val |= (sata_calib_pad_val[calib_val].gen1_tx_peak <<
441 SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
442 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
443
444 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
445 val &= ~SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
446 val |= (sata_calib_pad_val[calib_val].gen2_tx_amp <<
447 SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT);
448 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
449
450 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
451 val &= ~SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
452 val |= (sata_calib_pad_val[calib_val].gen2_tx_peak <<
453 SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT);
454 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
455
456 /* set 2 to SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ field */
457 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
458 val &= ~SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_MASK;
459 val |= (2 << SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_SHIFT);
460 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
461 }
462 scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
463}
464
465int tegra_ahci_get_rails(struct regulator *regulators[])
466{
467 struct regulator *reg;
468 int i;
469 int ret = 0;
470
471 for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
472 reg = regulator_get(NULL, sata_power_rails[i]);
473 if (IS_ERR_OR_NULL(reg)) {
474 pr_err("%s: can't get regulator %s\n",
475 __func__, sata_power_rails[i]);
476 WARN_ON(1);
477 ret = PTR_ERR(reg);
478 goto exit;
479 }
480 regulators[i] = reg;
481 }
482exit:
483 return ret;
484}
485
486void tegra_ahci_put_rails(struct regulator *regulators[])
487{
488 int i;
489
490 for (i = 0; i < NUM_SATA_POWER_RAILS; ++i)
491 regulator_put(regulators[i]);
492}
493
494int tegra_ahci_power_on_rails(struct regulator *regulators[])
495{
496 struct regulator *reg;
497 int i;
498 int ret = 0;
499
500 for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
501 reg = regulators[i];
502 ret = regulator_enable(reg);
503 if (ret) {
504 pr_err("%s: can't enable regulator[%d]\n",
505 __func__, i);
506 WARN_ON(1);
507 goto exit;
508 }
509 }
510
511exit:
512 return ret;
513}
514
515int tegra_ahci_power_off_rails(struct regulator *regulators[])
516{
517 struct regulator *reg;
518 int i;
519 int ret = 0;
520
521 for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
522 reg = regulators[i];
523 if (!IS_ERR_OR_NULL(reg)) {
524 ret = regulator_disable(reg);
525 if (ret) {
526 pr_err("%s: can't disable regulator[%d]\n",
527 __func__, i);
528 WARN_ON(1);
529 goto exit;
530 }
531 }
532 }
533
534exit:
535 return ret;
536}
537static int tegra_ahci_controller_init(struct tegra_ahci_host_priv *tegra_hpriv)
538{
539 int err = 0;
540 struct clk *clk_sata = NULL;
541 struct clk *clk_sata_oob = NULL;
542 struct clk *clk_sata_cold = NULL;
543 struct clk *clk_pllp = NULL;
544 u32 val;
545 u32 timeout;
546
547 err = tegra_ahci_get_rails(tegra_hpriv->power_rails);
548 if (err) {
549 pr_err("%s: fails to get rails (%d)\n", __func__, err);
550 goto exit;
551 }
552
553 err = tegra_ahci_power_on_rails(tegra_hpriv->power_rails);
554 if (err) {
555 pr_err("%s: fails to power on rails (%d)\n", __func__, err);
556 goto exit;
557 }
558
559 /* pll_p is the parent of tegra_sata and tegra_sata_oob */
560 clk_pllp = clk_get_sys(NULL, "pll_p");
561 if (IS_ERR_OR_NULL(clk_pllp)) {
562 pr_err("%s: unable to get PLL_P clock\n", __func__);
563 err = -ENODEV;
564 goto exit;
565 }
566
567 clk_sata = clk_get_sys("tegra_sata", NULL);
568 if (IS_ERR_OR_NULL(clk_sata)) {
569 pr_err("%s: unable to get SATA clock\n", __func__);
570 err = -ENODEV;
571 goto exit;
572 }
573
574 clk_sata_oob = clk_get_sys("tegra_sata_oob", NULL);
575 if (IS_ERR_OR_NULL(clk_sata_oob)) {
576 pr_err("%s: unable to get SATA OOB clock\n", __func__);
577 err = -ENODEV;
578 goto exit;
579 }
580
581 clk_sata_cold = clk_get_sys("tegra_sata_cold", NULL);
582 if (IS_ERR_OR_NULL(clk_sata_cold)) {
583 pr_err("%s: unable to get SATA COLD clock\n", __func__);
584 err = -ENODEV;
585 goto exit;
586 }
587
588 tegra_periph_reset_assert(clk_sata);
589 tegra_periph_reset_assert(clk_sata_oob);
590 tegra_periph_reset_assert(clk_sata_cold);
591 udelay(10);
592
593 /* need to establish both clocks divisors before setting clk sources */
594 clk_set_rate(clk_sata, clk_get_rate(clk_sata)/10);
595 clk_set_rate(clk_sata_oob, clk_get_rate(clk_sata_oob)/10);
596
597 /* set SATA clk and SATA_OOB clk source */
598 clk_set_parent(clk_sata, clk_pllp);
599 clk_set_parent(clk_sata_oob, clk_pllp);
600
601 /* Configure SATA clocks */
602 /* Core clock runs at 108MHz */
603 if (clk_set_rate(clk_sata, TEGRA_SATA_CORE_CLOCK_FREQ_HZ)) {
604 err = -ENODEV;
605 goto exit;
606 }
607 /* OOB clock runs at 216MHz */
608 if (clk_set_rate(clk_sata_oob, TEGRA_SATA_OOB_CLOCK_FREQ_HZ)) {
609 err = -ENODEV;
610 goto exit;
611 }
612
613 /**** Init the SATA PAD PLL ****/
614 /* SATA_PADPLL_IDDQ_SWCTL=1 and SATA_PADPLL_IDDQ_OVERRIDE_VALUE=1 */
615 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
616 val &= ~(PADPLL_IDDQ_SWCTL_MASK | PADPLL_IDDQ_OVERRIDE_VALUE_MASK);
617 val |= (PADPLL_IDDQ_SWCTL_ON | PADPLL_IDDQ_OVERRIDE_VALUE_ON);
618 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
619
620 /* SATA_PADPLL_RESET_OVERRIDE_VALUE=1 and SATA_PADPLL_RESET_SWCTL=1 */
621 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
622 val &= ~(PADPLL_RESET_OVERRIDE_VALUE_MASK | PADPLL_RESET_SWCTL_MASK);
623 val |= (PADPLL_RESET_OVERRIDE_VALUE_ON | PADPLL_RESET_SWCTL_ON);
624 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
625
626 /* SATA_PADPHY_IDDQ_OVERRIDE_VALUE and SATA_PADPHY_IDDQ_SWCTL = 1 */
627 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
628 val &= ~(PADPHY_IDDQ_OVERRIDE_VALUE_MASK | PADPHY_IDDQ_SWCTL_MASK);
629 val |= (PADPHY_IDDQ_OVERRIDE_VALUE_ON | PADPHY_IDDQ_SWCTL_ON);
630 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
631
632 /* Get SATA pad PLL out of IDDQ mode */
633 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
634 val &= ~PADPLL_IDDQ_OVERRIDE_VALUE_MASK;
635 val |= PADPLL_IDDQ_OVERRIDE_VALUE_OFF;
636 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
637 udelay(3);
638
639 /* select internal CML ref clk
640 * select PLLE as input to IO phy */
641 val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
642 val &= ~REFCLK_SEL_MASK;
643 val |= REFCLK_SEL_INT_CML;
644 misc_writel(val, SATA_AUX_PAD_PLL_CNTL_1_REG);
645
646 /* wait for SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY = 3 microseconds. */
647 val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
648 val &= ~IDDQ2LANE_SLUMBER_DLY_MASK;
649 val |= IDDQ2LANE_SLUMBER_DLY_3MS;
650 clk_writel(val, CLK_RST_SATA_PLL_CFG1_REG);
651 udelay(3);
652
653 /* de-assert IDDQ mode signal going to PHY */
654 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
655 val &= ~PADPHY_IDDQ_OVERRIDE_VALUE_MASK;
656 val |= PADPHY_IDDQ_OVERRIDE_VALUE_OFF;
657 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
658
659 err = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_SATA);
660 if (err) {
661 pr_err("%s: ** failed to turn-on SATA (0x%x) **\n",
662 __func__, err);
663 goto exit;
664 }
665
666 /* place SATA Pad PLL out of reset by */
667 /* writing SATA_PADPLL_RST_OVERRIDE_VALUE = 0 */
668 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
669 val &= ~PADPLL_RESET_OVERRIDE_VALUE_MASK;
670 val |= PADPLL_RESET_OVERRIDE_VALUE_OFF;
671 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
672
673 /* Wait for SATA_AUX_PAD_PLL_CNTL_1_0_LOCKDET to turn 1 with
674 a timeout of 15 us. */
675 timeout = 15;
676 while (timeout--) {
677 udelay(1);
678 val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
679 if (val & LOCKDET_FIELD)
680 break;
681 }
682 if (timeout == 0) {
683 pr_err("%s: AUX_PAD_PLL_CNTL_1 (0x%x) is not locked in 15us.\n",
684 __func__, val);
685 }
686
687 /* clear SW control of SATA PADPLL, SATA PHY and PLLE */
688 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
689 val &= ~(PADPLL_IDDQ_SWCTL_MASK | PADPHY_IDDQ_SWCTL_MASK |
690 PLLE_IDDQ_SWCTL_MASK);
691 val |= (PADPLL_IDDQ_SWCTL_OFF | PADPHY_IDDQ_SWCTL_OFF |
692 PLLE_IDDQ_SWCTL_OFF);
693 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
694
695 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
696 val &= ~PADPLL_RESET_SWCTL_MASK;
697 val |= PADPLL_RESET_SWCTL_OFF;
698 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
699
700 /* clear NVA2SATA_OOB_ON_POR in SATA_AUX_MISC_CNTL_1_REG */
701 val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
702 val &= ~NVA2SATA_OOB_ON_POR_MASK;
703 misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
704
705 val = sata_readl(SATA_CONFIGURATION_0_OFFSET);
706 val |= EN_FPCI;
707 sata_writel(val, SATA_CONFIGURATION_0_OFFSET);
708
709 /* program sata pad control based on the fuse */
710 tegra_ahci_set_pad_cntrl_regs();
711
712 /* clear bit T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD of
713 * T_SATA0_CFG_PHY_0 */
714 val = scfg_readl(T_SATA0_CFG_PHY_REG);
715 val &= ~PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK;
716 scfg_writel(val, T_SATA0_CFG_PHY_REG);
717
718 /*
719 * WAR: Before enabling SATA PLL shutdown, lockdet needs to be ignored.
720 * To ignore lockdet, T_SATA0_DBG0_OFFSET register bit 10 needs to
721 * be 1, and bit 8 needs to be 0.
722 */
723 val = scfg_readl(T_SATA0_DBG0_OFFSET);
724 val |= (1 << 10);
725 val &= ~(1 << 8);
726 scfg_writel(val, T_SATA0_DBG0_OFFSET);
727
728 /* program class code and programming interface for AHCI */
729 val = scfg_readl(TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
730 val |= TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
731 scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
732 scfg_writel(TEGRA_PRIVATE_AHCI_CC_BKDR_PGM, TEGRA_PRIVATE_AHCI_CC_BKDR);
733 val &= ~TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
734 scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
735
736 /* Program config space registers */
737 /* Enable BUS_MASTER+MEM+IO space, and SERR */
738 val = scfg_readl(TEGRA_SATA_IO_SPACE_OFFSET);
739 val |= TEGRA_SATA_ENABLE_IO_SPACE | TEGRA_SATA_ENABLE_MEM_SPACE |
740 TEGRA_SATA_ENABLE_BUS_MASTER | TEGRA_SATA_ENABLE_SERR;
741 scfg_writel(val, TEGRA_SATA_IO_SPACE_OFFSET);
742
743 /* program bar5 space */
744 /* first write 1's to bar5 register */
745 scfg_writel(TEGRA_SATA_BAR5_INIT_PROGRAM, AHCI_BAR5_CONFIG_LOCATION);
746 /* flush */
747 val = scfg_readl(AHCI_BAR5_CONFIG_LOCATION);
748 /* write the BAR5_FINAL_PROGRAM address */
749 scfg_writel(TEGRA_SATA_BAR5_FINAL_PROGRAM, AHCI_BAR5_CONFIG_LOCATION);
750 /* flush */
751 scfg_readl(AHCI_BAR5_CONFIG_LOCATION);
752
753 sata_writel((TEGRA_SATA_BAR5_FINAL_PROGRAM >> 8),
754 SATA_FPCI_BAR5_0_OFFSET);
755
756 val = scfg_readl(T_SATA0_AHCI_HBA_CAP_BKDR);
757 val |= (HOST_CAP_ALPM | HOST_CAP_SSC | HOST_CAP_PART);
758 scfg_writel(val, T_SATA0_AHCI_HBA_CAP_BKDR);
759
760 /* enable Interrupt channel */
761 val = pictlr_readl(PRI_ICTLR_CPU_IER_SET_0_OFFSET);
762 val |= CPU_IER_SATA_CTL;
763 pictlr_writel(val, PRI_ICTLR_CPU_IER_SET_0_OFFSET);
764
765 /* set IP_INT_MASK */
766 val = sata_readl(SATA_INTR_MASK_0_OFFSET);
767 val |= IP_INT_MASK;
768 sata_writel(val, SATA_INTR_MASK_0_OFFSET);
769
770exit:
771 if (!IS_ERR_OR_NULL(clk_pllp))
772 clk_put(clk_pllp);
773 if (!IS_ERR_OR_NULL(clk_sata))
774 clk_put(clk_sata);
775 if (!IS_ERR_OR_NULL(clk_sata_oob))
776 clk_put(clk_sata_oob);
777 if (!IS_ERR_OR_NULL(clk_sata_cold))
778 clk_put(clk_sata_cold);
779
780 if (err) {
781 /* turn off all SATA power rails; ignore returned status */
782 tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
783 /* return regulators to system */
784 tegra_ahci_put_rails(tegra_hpriv->power_rails);
785 }
786
787 return err;
788}
789
790static void tegra_ahci_save_initial_config(struct platform_device *pdev,
791 struct ahci_host_priv *hpriv)
792{
793 ahci_save_initial_config(&pdev->dev, hpriv, 0, 0);
794}
795
796static void tegra_ahci_controller_remove(struct platform_device *pdev)
797{
798 struct ata_host *host = dev_get_drvdata(&pdev->dev);
799 struct tegra_ahci_host_priv *tegra_hpriv;
800
801#ifdef CONFIG_PM
802 /* call tegra_ahci_controller_suspend() to power-down the SATA */
803 tegra_ahci_controller_suspend(pdev);
804#else
805 /* power off the sata */
806 status = tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
807 if (status)
808 dev_printk(KERN_ERR, host->dev,
809 "remove: error turn-off SATA (0x%x) **\n",
810 status);
811 tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
812#endif
813
814 /* return system resources */
815 tegra_ahci_put_rails(tegra_hpriv->power_rails);
816}
817
818#ifdef CONFIG_PM
819static int tegra_ahci_controller_suspend(struct platform_device *pdev)
820{
821 struct ata_host *host = dev_get_drvdata(&pdev->dev);
822 struct tegra_ahci_host_priv *tegra_hpriv;
823 unsigned long flags;
824
825 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
826
827 /* stop the idle timer */
828 if (timer_pending(&tegra_hpriv->idle_timer))
829 del_timer_sync(&tegra_hpriv->idle_timer);
830
831 spin_lock_irqsave(&host->lock, flags);
832 if (tegra_hpriv->pg_state)
833 dev_printk(KERN_DEBUG, host->dev,
834 "suspend: SATA already power gated\n");
835 else {
836 bool pg_ok;
837
838 dev_printk(KERN_DEBUG, host->dev,
839 "suspend: power gating SATA...\n");
840 pg_ok = tegra_ahci_power_gate(host);
841 if (pg_ok) {
842 tegra_hpriv->pg_state = true;
843 dev_printk(KERN_DEBUG, host->dev,
844 "suspend: SATA is down\n");
845 } else {
846 dev_printk(KERN_ERR, host->dev,
847 "suspend: abort power gating\n");
848 tegra_ahci_abort_power_gate(host);
849 spin_unlock_irqrestore(&host->lock, flags);
850 return -EBUSY;
851 }
852 }
853 spin_unlock_irqrestore(&host->lock, flags);
854
855 return tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
856}
857
858static int tegra_ahci_controller_resume(struct platform_device *pdev)
859{
860 struct ata_host *host = dev_get_drvdata(&pdev->dev);
861 struct tegra_ahci_host_priv *tegra_hpriv;
862 unsigned long flags;
863 int err;
864
865 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
866
867 err = tegra_ahci_power_on_rails(tegra_hpriv->power_rails);
868 if (err) {
869 pr_err("%s: fails to power on rails (%d)\n", __func__, err);
870 return err;
871 }
872
873 spin_lock_irqsave(&host->lock, flags);
874 if (!tegra_hpriv->pg_state)
875 dev_printk(KERN_DEBUG, host->dev,
876 "resume: SATA already powered on\n");
877 else {
878 dev_printk(KERN_DEBUG, host->dev,
879 "resume: powering on SATA...\n");
880 tegra_ahci_power_un_gate(host);
881 tegra_hpriv->pg_state = false;
882 }
883 spin_unlock_irqrestore(&host->lock, flags);
884
885 return 0;
886}
887
888static int tegra_ahci_suspend(struct platform_device *pdev, pm_message_t mesg)
889{
890 struct ata_host *host = dev_get_drvdata(&pdev->dev);
891 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
892 u32 ctl;
893 int rc;
894
895 if (mesg.event & PM_EVENT_SLEEP) {
896 /* AHCI spec rev1.1 section 8.3.3:
897 * Software must disable interrupts prior to requesting a
898 * transition of the HBA to D3 state.
899 */
900 ctl = readl(mmio + HOST_CTL);
901 ctl &= ~HOST_IRQ_EN;
902 writel(ctl, mmio + HOST_CTL);
903 readl(mmio + HOST_CTL); /* flush */
904 }
905
906 rc = ata_host_suspend(host, mesg);
907 if (rc)
908 return rc;
909
910 return tegra_ahci_controller_suspend(pdev);
911}
912
913static int tegra_ahci_resume(struct platform_device *pdev)
914{
915 struct ata_host *host = dev_get_drvdata(&pdev->dev);
916 int rc;
917
918 rc = tegra_ahci_controller_resume(pdev);
919 if (rc)
920 return rc;
921
922 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
923 rc = ahci_reset_controller(host);
924 if (rc)
925 return rc;
926
927 ahci_init_controller(host);
928 }
929
930 ata_host_resume(host);
931 return 0;
932}
933
934static u16 pg_save_bar5_registers[] = {
935 0x018, /* T_AHCI_HBA_CCC_PORTS */
936 0x004, /* T_AHCI_HBA_GHC */
937 0x014, /* T_AHCI_HBA_CCC_CTL - OP (optional) */
938 0x01C, /* T_AHCI_HBA_EM_LOC */
939 0x020 /* T_AHCI_HBA_EM_CTL - OP */
940};
941
942static u16 pg_save_bar5_port_registers[] = {
943 0x100, /* T_AHCI_PORT_PXCLB */
944 0x104, /* T_AHCI_PORT_PXCLBU */
945 0x108, /* T_AHCI_PORT_PXFB */
946 0x10C, /* T_AHCI_PORT_PXFBU */
947 0x114, /* T_AHCI_PORT_PXIE */
948 0x118, /* T_AHCI_PORT_PXCMD */
949 0x12C /* T_AHCI_PORT_PXSCTL */
950};
951
952/*
953 * pg_save_bar5_bkdr_registers:
954 * These registers in BAR5 are read only.
955 * To restore back those register values, write the saved value
956 * to the registers specified in pg_restore_bar5_bkdr_registers[].
957 * These pg_restore_bar5_bkdr_registers[] are in SATA_CONFIG space.
958 */
959static u16 pg_save_bar5_bkdr_registers[] = {
960 /* Save and restore via bkdr writes */
961 0x000, /* T_AHCI_HBA_CAP */
962 0x00C, /* T_AHCI_HBA_PI */
963 0x024 /* T_AHCI_HBA_CAP2 */
964};
965
966static u16 pg_restore_bar5_bkdr_registers[] = {
967 /* Save and restore via bkdr writes */
968 0x300, /* BKDR of T_AHCI_HBA_CAP */
969 0x33c, /* BKDR of T_AHCI_HBA_PI */
970 0x330 /* BKDR of T_AHCI_HBA_CAP2 */
971};
972
973/* These registers are saved for each port */
974/* To save those registers, T_SATA0_INDEX register needs to be set */
975static u16 pg_save_bar5_bkdr_port_registers[] = {
976 0x120, /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXTFD */
977 0x124, /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXSIG */
978 0x128 /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXSSTS */
979};
980
981static u16 pg_restore_bar5_bkdr_port_registers[] = {
982 /* Save and restore via bkdr writes */
983 0x790, /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXTFD */
984 0x794, /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXSIG */
985 0x798 /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXSSTS */
986};
987
988static u16 pg_save_config_registers[] = {
989 0x004, /* T_SATA0_CFG_1 */
990 0x00C, /* T_SATA0_CFG_3 */
991 0x024, /* T_SATA0_CFG_9 */
992 0x028, /* T_SATA0_CFG_10 */
993 0x030, /* T_SATA0_CFG_12 */
994 0x034, /* T_SATA0_CFG_13 */
995 0x038, /* T_SATA0_CFG_14 */
996 0x03C, /* T_SATA0_CFG_15 */
997 0x040, /* T_SATA0_CFG_16 */
998 0x044, /* T_SATA0_CFG_17 */
999 0x048, /* T_SATA0_CFG_18 */
1000 0x0B0, /* T_SATA0_MSI_CTRL */
1001 0x0B4, /* T_SATA0_MSI_ADDR1 */
1002 0x0B8, /* T_SATA0_MSI_ADDR2 */
1003 0x0BC, /* T_SATA0_MSI_DATA */
1004 0x0C0, /* T_SATA0_MSI_QUEUE */
1005 0x0EC, /* T_SATA0_MSI_MAP */
1006 0x124, /* T_SATA0_CFG_PHY_POWER */
1007 0x128, /* T_SATA0_CFG_PHY_POWER_1 */
1008 0x12C, /* T_SATA0_CFG_PHY_1 */
1009 0x174, /* T_SATA0_CFG_LINK_0 */
1010 0x178, /* T_SATA0_CFG_LINK_1 */
1011 0x1D0, /* MCP_SATA0_CFG_TRANS_0 */
1012 0x238, /* T_SATA0_ALPM_CTRL */
1013 0x30C, /* T_SATA0_AHCI_HBA_CYA_0 */
1014 0x320, /* T_SATA0_AHCI_HBA_SPARE_1 */
1015 0x324, /* T_SATA0_AHCI_HBA_SPARE_2 */
1016 0x328, /* T_SATA0_AHCI_HBA_DYN_CLK_CLAMP */
1017 0x32C, /* T_SATA0_AHCI_CFG_ERR_CTRL */
1018 0x338, /* T_SATA0_AHCI_HBA_CYA_1 */
1019 0x340, /* T_SATA0_AHCI_HBA_PRE_STAGING_CONTROL */
1020 0x430, /* T_SATA0_CFG_FPCI_0 */
1021 0x494, /* T_SATA0_CFG_ESATA_CTRL */
1022 0x4A0, /* T_SATA0_CYA1 */
1023 0x4B0, /* T_SATA0_CFG_GLUE */
1024 0x534, /* T_SATA0_PHY_CTRL */
1025 0x540, /* T_SATA0_CTRL */
1026 0x550, /* T_SATA0_DBG0 */
1027 0x554 /* T_SATA0_LOW_POWER_COUNT */
1028};
1029
1030static u16 pg_save_config_port_registers[] = {
1031 /* Save and restore per port */
1032 /* need to have port selected */
1033 0x530, /* T_SATA0_CHXCFG1 */
1034 0x684, /* T_SATA0_CHX_MISC */
1035 0x700, /* T_SATA0_CHXCFG3 */
1036 0x704, /* T_SATA0_CHXCFG4_CHX */
1037 0x690, /* T_SATA0_CHX_PHY_CTRL1_GEN1 */
1038 0x694, /* T_SATA0_CHX_PHY_CTRL1_GEN2 */
1039 0x698, /* T_SATA0_CHX_PHY_CTRL1_GEN3 */
1040 0x69C, /* T_SATA0_CHX_PHY_CTRL_2 */
1041 0x6B0, /* T_SATA0_CHX_PHY_CTRL_3 */
1042 0x6B4, /* T_SATA0_CHX_PHY_CTRL_4 */
1043 0x6B8, /* T_SATA0_CHX_PHY_CTRL_5 */
1044 0x6BC, /* T_SATA0_CHX_PHY_CTRL_6 */
1045 0x714, /* T_SATA0_PRBS_CHX - OP */
1046 0x750, /* T_SATA0_CHX_LINK0 */
1047 0x7F0 /* T_SATA0_CHX_GLUE */
1048};
1049
1050static u16 pg_save_ipfs_registers[] = {
1051 0x094, /* SATA_FPCI_BAR5_0 */
1052 0x0C0, /* SATA_MSI_BAR_SZ_0 */
1053 0x0C4, /* SATA_MSI_AXI_BAR_ST_0 */
1054 0x0C8, /* SATA_MSI_FPCI_BAR_ST_0 */
1055 0x140, /* SATA_MSI_EN_VEC0_0 */
1056 0x144, /* SATA_MSI_EN_VEC1_0 */
1057 0x148, /* SATA_MSI_EN_VEC2_0 */
1058 0x14C, /* SATA_MSI_EN_VEC3_0 */
1059 0x150, /* SATA_MSI_EN_VEC4_0 */
1060 0x154, /* SATA_MSI_EN_VEC5_0 */
1061 0x158, /* SATA_MSI_EN_VEC6_0 */
1062 0x15C, /* SATA_MSI_EN_VEC7_0 */
1063 0x180, /* SATA_CONFIGURATION_0 */
1064 0x184, /* SATA_FPCI_ERROR_MASKS_0 */
1065 0x188, /* SATA_INTR_MASK_0 */
1066 0x1A0, /* SATA_CFG_REVID_0 */
1067 0x198, /* SATA_IPFS_INTR_ENABLE_0 */
1068 0x1BC, /* SATA_CLKGATE_HYSTERSIS_0 */
1069 0x1DC /* SATA_SATA_MCCIF_FIFOCTRL_0 */
1070};
1071
1072static void tegra_ahci_save_regs(u32 **save_addr,
1073 u32 reg_base,
1074 u16 reg_array[],
1075 u32 regs)
1076{
1077 u32 i;
1078 u32 *dest = (u32 *)*save_addr;
1079 u32 base = (u32)IO_ADDRESS(reg_base);
1080
1081 for (i = 0; i < regs; ++i, ++dest) {
1082 *dest = readl(base + (u32)reg_array[i]);
1083 AHCI_DBG_PRINT("save: [0x%x]=0x%08x\n",
1084 (reg_base+(u32)reg_array[i]), *dest);
1085 }
1086 *save_addr = dest;
1087}
1088
1089static void tegra_ahci_restore_regs(void **save_addr,
1090 u32 reg_base,
1091 u16 reg_array[],
1092 u32 regs)
1093{
1094 u32 i;
1095 u32 *src = (u32 *)*save_addr;
1096 u32 base = (u32)IO_ADDRESS(reg_base);
1097
1098 for (i = 0; i < regs; ++i, ++src) {
1099 writel(*src, base + (u32)reg_array[i]);
1100 AHCI_DBG_PRINT("restore: [0x%x]=0x%08x\n",
1101 (reg_base+(u32)reg_array[i]), *src);
1102 }
1103 *save_addr = src;
1104}
1105
1106static void tegra_ahci_pg_save_registers(struct ata_host *host)
1107{
1108 struct tegra_ahci_host_priv *tegra_hpriv;
1109 u32 *pg_save;
1110 u32 regs;
1111 int i;
1112
1113 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1114 pg_save = tegra_hpriv->pg_save;
1115
1116 /*
1117 * Driver should save/restore the registers in the order of
1118 * IPFS, CFG, Ext CFG, BAR5.
1119 */
1120
1121 /* save IPFS registers */
1122 regs = ARRAY_SIZE(pg_save_ipfs_registers);
1123 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BASE,
1124 pg_save_ipfs_registers, regs);
1125 /* after the call, pg_save should point to the next address to save */
1126
1127 /* save CONFIG registers */
1128 regs = ARRAY_SIZE(pg_save_config_registers);
1129 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1130 pg_save_config_registers, regs);
1131
1132 /* save CONFIG per port registers */
1133 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1134 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1135 regs = ARRAY_SIZE(pg_save_config_port_registers);
1136 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1137 pg_save_config_port_registers, regs);
1138 }
1139 scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1140
1141 /* save BAR5 registers */
1142 regs = ARRAY_SIZE(pg_save_bar5_registers);
1143 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
1144 pg_save_bar5_registers, regs);
1145
1146 /* save BAR5 port_registers */
1147 regs = ARRAY_SIZE(pg_save_bar5_port_registers);
1148 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i)
1149 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE + (0x80*i),
1150 pg_save_bar5_port_registers, regs);
1151
1152 /* save bkdr registers */
1153 regs = ARRAY_SIZE(pg_save_bar5_bkdr_registers);
1154 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
1155 pg_save_bar5_bkdr_registers, regs);
1156
1157 /* and save bkdr per_port registers */
1158 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1159 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1160 regs = ARRAY_SIZE(pg_save_bar5_bkdr_port_registers);
1161 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE + (0x80*i),
1162 pg_save_bar5_bkdr_port_registers,
1163 regs);
1164 }
1165 scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1166}
1167
1168static void tegra_ahci_pg_restore_registers(struct ata_host *host)
1169{
1170 struct tegra_ahci_host_priv *tegra_hpriv;
1171 void *pg_save;
1172 u32 regs, val;
1173 int i;
1174
1175 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1176 pg_save = tegra_hpriv->pg_save;
1177
1178 /*
1179 * Driver should restore the registers in the order of
1180 * IPFS, CFG, Ext CFG, BAR5.
1181 */
1182
1183 /* restore IPFS registers */
1184 regs = ARRAY_SIZE(pg_save_ipfs_registers);
1185 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BASE,
1186 pg_save_ipfs_registers, regs);
1187 /* after the call, pg_save should point to the next addr to restore */
1188
1189 /* restore CONFIG registers */
1190 regs = ARRAY_SIZE(pg_save_config_registers);
1191 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1192 pg_save_config_registers, regs);
1193
1194 /* restore CONFIG per port registers */
1195 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1196 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1197 regs = ARRAY_SIZE(pg_save_config_port_registers);
1198 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1199 pg_save_config_port_registers,
1200 regs);
1201 }
1202 scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1203
1204 /* restore BAR5 registers */
1205 regs = ARRAY_SIZE(pg_save_bar5_registers);
1206 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
1207 pg_save_bar5_registers, regs);
1208
1209 /* restore BAR5 port_registers */
1210 regs = ARRAY_SIZE(pg_save_bar5_port_registers);
1211 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i)
1212 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BAR5_BASE+(0x80*i),
1213 pg_save_bar5_port_registers, regs);
1214
1215 /* restore bkdr registers */
1216 regs = ARRAY_SIZE(pg_restore_bar5_bkdr_registers);
1217 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1218 pg_restore_bar5_bkdr_registers, regs);
1219
1220 /* and restore BAR5 bkdr per_port registers */
1221 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1222 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1223 regs = ARRAY_SIZE(pg_restore_bar5_bkdr_port_registers);
1224 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1225 pg_restore_bar5_bkdr_port_registers,
1226 regs);
1227 }
1228 scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1229
1230 /* program class code and programming interface for AHCI */
1231 val = scfg_readl(TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1232 val |= TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
1233 scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1234 scfg_writel(TEGRA_PRIVATE_AHCI_CC_BKDR_PGM, TEGRA_PRIVATE_AHCI_CC_BKDR);
1235 val &= ~TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
1236 scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1237}
1238
1239static u32 tegra_ahci_port_error(struct ata_port *ap)
1240{
1241 void __iomem *port_mmio = ahci_port_base(ap);
1242 u32 err_status;
1243
1244 err_status = readl(port_mmio + PORT_IRQ_STAT);
1245 err_status &= (PORT_IRQ_ERROR & (~PORT_IRQ_PHYRDY));
1246 return err_status;
1247}
1248
1249static bool tegra_ahci_check_errors(struct ata_host *host)
1250{ int i;
1251 struct ata_port *ap;
1252 u32 err;
1253
1254 for (i = 0; i < host->n_ports; i++) {
1255 ap = host->ports[i];
1256 err = tegra_ahci_port_error(ap);
1257 if (err) {
1258 dev_printk(KERN_ERR, host->dev,
1259 "pg-chk-err = 0x%08x on port %d\n", err, i);
1260 return true;
1261 }
1262 }
1263 return false;
1264}
1265
1266static void tegra_ahci_abort_power_gate(struct ata_host *host)
1267{
1268 u32 val;
1269
1270 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1271 val &= ~PG_INFO_MASK;
1272 val |= PG_INFO_OFF;
1273 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1274}
1275
1276static bool tegra_ahci_power_gate(struct ata_host *host)
1277{
1278 u32 val;
1279 u32 dat;
1280 struct tegra_ahci_host_priv *tegra_hpriv;
1281 int status;
1282
1283 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1284
1285 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1286 val &= ~PG_INFO_MASK;
1287 val |= PG_INFO_ON;
1288 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1289
1290 tegra_ahci_pg_save_registers(host);
1291
1292 /* Read SATA_AUX_MISC_CNTL_1_0 register L0_RX_IDLE_T_SAX field and
1293 * write that value into same register L0_RX_IDLE_T_NPG field.
1294 * And write 1 to L0_RX_IDLE_T_MUX field.
1295 */
1296 val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
1297 dat = val;
1298 dat &= L0_RX_IDLE_T_SAX_MASK;
1299 dat >>= L0_RX_IDLE_T_SAX_SHIFT;
1300 dat <<= L0_RX_IDLE_T_NPG_SHIFT;
1301 val &= ~L0_RX_IDLE_T_NPG_MASK;
1302 val |= dat;
1303 val &= ~L0_RX_IDLE_T_MUX_MASK;
1304 val |= L0_RX_IDLE_T_MUX_FROM_APB_MISC;
1305 misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
1306
1307 /* abort PG if there are errors occurred */
1308 if (tegra_ahci_check_errors(host)) {
1309 dev_printk(KERN_ERR, host->dev, "** pg: rrors **\n");
1310 dev_printk(KERN_ERR, host->dev, "** abort power down **\n");
1311 WARN_ON(1);
1312 return false;
1313 }
1314 /* make sure all ports have no outstanding commands and are slumber. */
1315 if (!tegra_ahci_are_all_ports_slumber(host)) {
1316 dev_printk(KERN_ERR, host->dev, "** outstanding cmds **\n");
1317 dev_printk(KERN_ERR, host->dev, "** abort power down **\n");
1318 WARN_ON(1);
1319 return false;
1320 }
1321
1322 /* Hw wake up is not needed:
1323 * Driver/RM shall place the SATA PHY and SATA PADPLL in IDDQ.
1324 *
1325 * SATA_PADPLL_RESET_SWCTL =1
1326 SATA_PADPLL_RESET_OVERRIDE_VALUE=1
1327 SATA_PADPHY_IDDQ_SWCTL=1
1328 SATA_PADPHY_IDDQ_OVERRIDE_VALUE=1
1329 */
1330 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
1331 val &= ~(PADPLL_RESET_SWCTL_MASK | PADPLL_RESET_OVERRIDE_VALUE_MASK);
1332 val |= (PADPLL_RESET_SWCTL_ON | PADPLL_RESET_OVERRIDE_VALUE_ON);
1333 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
1334 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1335 val &= ~(PADPHY_IDDQ_OVERRIDE_VALUE_MASK | PADPHY_IDDQ_SWCTL_MASK);
1336 val |= (PADPHY_IDDQ_SWCTL_ON | PADPHY_IDDQ_OVERRIDE_VALUE_ON);
1337 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1338
1339 /* Wait for time specified in SATA_LANE_IDDQ2_PADPLL_IDDQ */
1340 val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
1341 dat = (val & IDDQ2LANE_IDDQ_DLY_MASK) >> IDDQ2LANE_IDDQ_DLY_SHIFT;
1342 udelay(dat);
1343
1344 /* SATA_PADPLL_IDDQ_SWCTL=1 & SATA_PADPLL_IDDQ_OVERRIDE_VALUE=1 */
1345 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1346 val &= ~(PADPLL_IDDQ_OVERRIDE_VALUE_MASK | PADPLL_IDDQ_SWCTL_MASK);
1347 val |= (PADPLL_IDDQ_SWCTL_ON | PADPLL_IDDQ_OVERRIDE_VALUE_ON);
1348 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1349
1350 /* power off the sata */
1351 status = tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
1352 if (status)
1353 dev_printk(KERN_ERR, host->dev,
1354 "** failed to turn-off SATA (0x%x) **\n",
1355 status);
1356
1357 return true;
1358}
1359
1360static bool tegra_ahci_power_un_gate(struct ata_host *host)
1361{
1362 u32 val;
1363 u32 dat;
1364 u32 timeout;
1365 struct tegra_ahci_host_priv *tegra_hpriv;
1366 int status;
1367
1368 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1369
1370 /* get sata phy and pll out of iddq: */
1371 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1372 val &= ~PADPLL_IDDQ_OVERRIDE_VALUE_MASK;
1373 val |= PADPLL_IDDQ_OVERRIDE_VALUE_OFF;
1374 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1375 /* wait for delay of IDDQ2LAND_SLUMBER_DLY */
1376 val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
1377 dat = (val & IDDQ2LANE_SLUMBER_DLY_MASK) >> IDDQ2LANE_SLUMBER_DLY_SHIFT;
1378 udelay(dat);
1379 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1380 val &= ~PADPHY_IDDQ_OVERRIDE_VALUE_MASK;
1381 val |= PADPHY_IDDQ_OVERRIDE_VALUE_OFF;
1382 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1383
1384 status = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_SATA);
1385 if (status)
1386 dev_printk(KERN_ERR, host->dev,
1387 "** failed to turn-on SATA (0x%x) **\n",
1388 status);
1389
1390 /* deasset PADPLL and wait until it locks. */
1391 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
1392 val &= ~PADPLL_RESET_OVERRIDE_VALUE_MASK;
1393 val |= PADPLL_RESET_OVERRIDE_VALUE_OFF;
1394 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
1395
1396 /* Wait for SATA_AUX_PAD_PLL_CNTL_1_0_LOCKDET to turn 1 with
1397 a timeout of 15 us. */
1398 timeout = 15;
1399 while (timeout--) {
1400 udelay(1);
1401 val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
1402 if (val & LOCKDET_FIELD)
1403 break;
1404 }
1405 if (timeout == 0)
1406 pr_err("%s: SATA_PAD_PLL is not locked in 15us.\n", __func__);
1407
1408 /* restore registers */
1409 tegra_ahci_pg_restore_registers(host);
1410
1411 /* During the restoration of the registers, the driver would now need to
1412 * restore the register T_SATA0_CFG_POWER_GATE_SSTS_RESTORED after the
1413 * ssts_det, ssts_spd are restored. This register is used to tell the
1414 * controller whether a drive existed earlier or not and move the PHY
1415 * state machines into either HR_slumber or not.
1416 */
1417 val = scfg_readl(T_SATA0_CFG_POWER_GATE);
1418 val &= ~POWER_GATE_SSTS_RESTORED_MASK;
1419 val |= POWER_GATE_SSTS_RESTORED_YES;
1420 scfg_writel(val, T_SATA0_CFG_POWER_GATE);
1421
1422 /* Driver needs to switch the rx_idle_t driven source back to from
1423 * Sata controller after SAX is power-ungated.
1424 */
1425 val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
1426 val &= ~L0_RX_IDLE_T_MUX_MASK;
1427 val |= L0_RX_IDLE_T_MUX_FROM_SATA;
1428 misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
1429
1430 /* Driver can start to use main SATA interrupt instead of the
1431 * rx_stat_t interrupt.
1432 */
1433 val = pictlr_readl(PRI_ICTLR_CPU_IER_SET_0_OFFSET);
1434 val |= CPU_IER_SATA_CTL;
1435 pictlr_writel(val, PRI_ICTLR_CPU_IER_SET_0_OFFSET);
1436
1437 /* Set the bits in the CAR to allow HW based low power sequencing. */
1438 val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
1439 val &= ~PADPLL_RESET_SWCTL_MASK;
1440 val |= PADPLL_RESET_SWCTL_OFF;
1441 clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
1442
1443 /* power un-gating process is complete by clearing
1444 * APBDEV_PMC_SATA_PWRGT_0.Pmc2sata_pg_info = 0
1445 */
1446 val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1447 val &= ~PG_INFO_MASK;
1448 val |= PG_INFO_OFF;
1449 pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1450
1451 return true;
1452}
1453
1454static enum port_idle_status tegra_ahci_is_port_idle(struct ata_port *ap)
1455{
1456 void __iomem *port_mmio = ahci_port_base(ap);
1457
1458 if (readl(port_mmio + PORT_CMD_ISSUE) ||
1459 readl(port_mmio + PORT_SCR_ACT))
1460 return PORT_IS_NOT_IDLE;
1461 return PORT_IS_IDLE;
1462}
1463
1464static enum port_idle_status tegra_ahci_is_port_slumber(struct ata_port *ap)
1465{
1466 void __iomem *port_mmio = ahci_port_base(ap);
1467 u32 sstat;
1468
1469 if (tegra_ahci_is_port_idle(ap) == PORT_IS_NOT_IDLE)
1470 return PORT_IS_NOT_IDLE;
1471
1472 /* return 1 if PORT_SCR_STAT is in IPM_SLUMBER_STATE */
1473 sstat = readl(port_mmio + PORT_SCR_STAT);
1474 if ((sstat & SSTAT_IPM_STATE_MASK) == SSTAT_IPM_SLUMBER_STATE)
1475 return PORT_IS_SLUMBER;
1476 return PORT_IS_IDLE_NOT_SLUMBER;
1477}
1478
1479/* check if all supported ports are idle (no outstanding commands) */
1480static bool tegra_ahci_are_all_ports_idle(struct ata_host *host)
1481{ int i;
1482 struct ata_port *ap;
1483
1484 for (i = 0; i < host->n_ports; i++) {
1485 ap = host->ports[i];
1486 if (ap && (tegra_ahci_is_port_idle(ap) == PORT_IS_NOT_IDLE))
1487 return false;
1488 }
1489 return true;
1490}
1491
1492/* check if all supported ports are in slumber */
1493static bool tegra_ahci_are_all_ports_slumber(struct ata_host *host)
1494{ int i;
1495 struct ata_port *ap;
1496
1497 for (i = 0; i < host->n_ports; i++) {
1498 ap = host->ports[i];
1499 if (ap && (tegra_ahci_is_port_slumber(ap) != PORT_IS_SLUMBER))
1500 return false;
1501 }
1502 return true;
1503}
1504
1505static void tegra_ahci_to_add_idle_timer(struct ata_host *host)
1506{
1507 struct tegra_ahci_host_priv *tegra_hpriv;
1508
1509 tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1510
1511 /* note: the routine is called from interrupt context */
1512 spin_lock(&host->lock);
1513 /* start idle-timer if all ports have no outstanding commands */
1514 if (tegra_ahci_are_all_ports_idle(host)) {
1515 /* adjust tegra_ahci_idle_time to minimum if it is too small */
1516 tegra_ahci_idle_time = max((u32)TEGRA_AHCI_MIN_IDLE_TIME,
1517 tegra_ahci_idle_time);
1518 tegra_hpriv->idle_timer.expires =
1519 ata_deadline(jiffies, tegra_ahci_idle_time);
1520 mod_timer(&tegra_hpriv->idle_timer,
1521 tegra_hpriv->idle_timer.expires);
1522 }
1523 spin_unlock(&host->lock);
1524}
1525
1526
1527static void tegra_ahci_idle_timer(unsigned long arg)
1528{
1529 struct ata_host *host = (void *)arg;
1530 struct ahci_host_priv *hpriv = host->private_data;
1531 bool pg_ok;
1532 unsigned long flags;
1533
1534 spin_lock_irqsave(&host->lock, flags);
1535 if (tegra_ahci_are_all_ports_slumber(host)) {
1536 /* if all ports are in slumber, do power-gate */
1537 dev_printk(KERN_DEBUG, host->dev, "** power-down sata **\n");
1538 pg_ok = tegra_ahci_power_gate(host);
1539 dev_printk(KERN_DEBUG, host->dev, "** done **\n");
1540 if (pg_ok)
1541 ((struct tegra_ahci_host_priv *)hpriv)->pg_state = true;
1542 else {
1543 dev_printk(KERN_ERR, host->dev, "** abort pg **\n");
1544 tegra_ahci_abort_power_gate(host);
1545 }
1546 } else
1547 dev_printk(KERN_DEBUG, host->dev, "** keep power **\n");
1548 spin_unlock_irqrestore(&host->lock, flags);
1549}
1550
1551static unsigned int tegra_ahci_qc_issue(struct ata_queued_cmd *qc)
1552{
1553 struct ata_port *ap = qc->ap;
1554 struct ata_host *host = ap->host;
1555 struct tegra_ahci_host_priv *tegra_hpriv = host->private_data;
1556
1557 /* stop the idle timer */
1558 if (timer_pending(&tegra_hpriv->idle_timer))
1559 del_timer_sync(&tegra_hpriv->idle_timer);
1560
1561 /* note: host->lock is locked */
1562 if (tegra_hpriv->pg_state) {
1563 dev_printk(KERN_DEBUG, host->dev, "** power-up sata **\n");
1564 tegra_ahci_power_un_gate(host);
1565 dev_printk(KERN_DEBUG, host->dev, "** done **\n");
1566 tegra_hpriv->pg_state = false;
1567 }
1568
1569 return ahci_ops.qc_issue(qc);
1570}
1571#endif
1572
1573static irqreturn_t tegra_ahci_interrupt(int irq, void *dev_instance)
1574{
1575 irqreturn_t irq_retval;
1576
1577 irq_retval = ahci_interrupt(irq, dev_instance);
1578 if (irq_retval == IRQ_NONE)
1579 return IRQ_NONE;
1580
1581#ifdef CONFIG_PM
1582 tegra_ahci_to_add_idle_timer((struct ata_host *)dev_instance);
1583#endif
1584
1585 return irq_retval;
1586}
1587
1588static int __devexit tegra_ahci_remove_one(struct platform_device *pdev)
1589{
1590 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1591 struct ahci_host_priv *hpriv;
1592
1593 BUG_ON(host == NULL);
1594 BUG_ON(host->iomap[AHCI_PCI_BAR] == NULL);
1595 hpriv = host->private_data;
1596 devm_iounmap(&pdev->dev, host->iomap[AHCI_PCI_BAR]);
1597 devres_free(host);
1598 devm_kfree(&pdev->dev, hpriv);
1599
1600 tegra_ahci_controller_remove(pdev);
1601 return 0;
1602}
1603
1604static int __devinit tegra_ahci_init_one(struct platform_device *pdev)
1605{
1606 static int printed_version;
1607 struct ata_port_info pi = ahci_port_info;
1608 const struct ata_port_info *ppi[] = { &pi, NULL };
1609 struct device *dev = &pdev->dev;
1610 struct ahci_host_priv *hpriv = NULL;
1611 struct tegra_ahci_host_priv *tegra_hpriv;
1612 struct ata_host *host = NULL;
1613 int n_ports, i, rc;
1614 struct resource *res, *irq_res;
1615 void __iomem *mmio;
1616
1617 VPRINTK("ENTER\n");
1618
1619 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1620
1621 if (!printed_version++)
1622 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1623
1624 /* Simple resource validation */
1625 if (pdev->num_resources != 3) {
1626 dev_err(&pdev->dev, "invalid number of resources\n");
1627 dev_printk(KERN_ERR, &pdev->dev, "not enough SATA resources\n");
1628 return -EINVAL;
1629 }
1630
1631 /* acquire bar resources */
1632 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1633 if (res == NULL)
1634 return -EINVAL;
1635
1636 /* acquire IRQ resource */
1637 irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1638 if (irq_res == NULL)
1639 return -EINVAL;
1640 if (irq_res->start <= 0)
1641 return -EINVAL;
1642
1643 /* allocate sizeof tegra_ahci_host_priv, which contains extra fields */
1644 hpriv = devm_kzalloc(dev, sizeof(struct tegra_ahci_host_priv),
1645 GFP_KERNEL);
1646 if (!hpriv) {
1647 rc = -ENOMEM;
1648 goto fail;
1649 }
1650 hpriv->flags |= (unsigned long)pi.private_data;
1651 tegra_hpriv = (struct tegra_ahci_host_priv *)hpriv;
1652
1653 /* Call tegra init routine */
1654 rc = tegra_ahci_controller_init(tegra_hpriv);
1655 if (rc != 0) {
1656 dev_printk(KERN_ERR, &pdev->dev, "TEGRA SATA init failed\n");
1657 goto fail;
1658 }
1659
1660 /*
1661 * We reserve a table of 6 BARs in tegra_hpriv to store BARs.
1662 * Save the mapped AHCI_PCI_BAR address to the table.
1663 */
1664 mmio = devm_ioremap(&pdev->dev, res->start, (res->end-res->start+1));
1665 tegra_hpriv->bars_table[AHCI_PCI_BAR] = mmio;
1666 hpriv->mmio = mmio;
1667
1668 /* save initial config */
1669 tegra_ahci_save_initial_config(pdev, hpriv);
1670 dev_printk(KERN_DEBUG, &pdev->dev, "past save init config\n");
1671
1672 /* prepare host */
1673 if (hpriv->cap & HOST_CAP_NCQ) {
1674 pi.flags |= ATA_FLAG_NCQ;
1675 pi.flags |= ATA_FLAG_FPDMA_AA;
1676 }
1677
1678 /* CAP.NP sometimes indicate the index of the last enabled
1679 * port, at other times, that of the last possible port, so
1680 * determining the maximum port number requires looking at
1681 * both CAP.NP and port_map.
1682 */
1683 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1684 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1685 if (!host) {
1686 rc = -ENOMEM;
1687 goto fail;
1688 }
1689 host->private_data = hpriv;
1690 host->iomap = tegra_hpriv->bars_table;
1691
1692 if (!(hpriv->cap & HOST_CAP_SSS))
1693 host->flags |= ATA_HOST_PARALLEL_SCAN;
1694 else
1695 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1696
1697 for (i = 0; i < host->n_ports; i++) {
1698 struct ata_port *ap = host->ports[i];
1699
1700 /* set initial link pm policy */
1701 ap->target_lpm_policy = ATA_LPM_UNKNOWN;
1702
1703 /* disabled/not-implemented port */
1704 if (!(hpriv->port_map & (1 << i)))
1705 ap->ops = &ata_dummy_port_ops;
1706 else
1707 ap->target_lpm_policy = ATA_LPM_MIN_POWER;
1708 }
1709
1710 rc = ahci_reset_controller(host);
1711 if (rc) {
1712 dev_printk(KERN_ERR, &pdev->dev,
1713 "Reset controller failed! (rc=%d)\n", rc);
1714 goto fail;
1715 }
1716
1717 ahci_init_controller(host);
1718 ahci_print_info(host, "TEGRA-SATA");
1719 dev_printk(KERN_DEBUG, &pdev->dev, "controller init okay\n");
1720
1721#ifdef CONFIG_PM
1722 {
1723 struct tegra_ahci_host_priv *tegra_hpriv;
1724 u32 save_size;
1725
1726 /* setup sata idle timer */
1727 tegra_hpriv = (struct tegra_ahci_host_priv *)hpriv;
1728 init_timer_deferrable(&tegra_hpriv->idle_timer);
1729 tegra_hpriv->idle_timer.function = tegra_ahci_idle_timer;
1730 tegra_hpriv->idle_timer.data = (unsigned long)host;
1731
1732 /* setup PG save/restore area */
1733 /* calculate the size */
1734 save_size = ARRAY_SIZE(pg_save_ipfs_registers) +
1735 ARRAY_SIZE(pg_save_config_registers) +
1736 ARRAY_SIZE(pg_save_bar5_registers) +
1737 ARRAY_SIZE(pg_save_bar5_bkdr_registers);
1738 /* and add save port_registers for all the ports */
1739 save_size += TEGRA_AHCI_NUM_PORTS *
1740 (ARRAY_SIZE(pg_save_config_port_registers) +
1741 ARRAY_SIZE(pg_save_bar5_port_registers) +
1742 ARRAY_SIZE(pg_save_bar5_bkdr_port_registers));
1743 /* save_size is number of registers,
1744 * times number of bytes per register to get total save size */
1745 save_size *= sizeof(u32);
1746 tegra_hpriv->pg_save = devm_kzalloc(dev, save_size, GFP_KERNEL);
1747 if (!tegra_hpriv->pg_save) {
1748 rc = -ENOMEM;
1749 goto fail;
1750 }
1751 }
1752#endif
1753
1754 rc = ata_host_activate(host, irq_res->start, tegra_ahci_interrupt,
1755 IRQF_SHARED, &ahci_sht);
1756 return rc;
1757fail:
1758 if (host) {
1759 if (host->iomap[AHCI_PCI_BAR])
1760 devm_iounmap(&pdev->dev, host->iomap[AHCI_PCI_BAR]);
1761 devres_free(host);
1762 }
1763 if (hpriv)
1764 devm_kfree(&pdev->dev, hpriv);
1765
1766 return rc;
1767}
1768
1769static int __init ahci_init(void)
1770{
1771 return platform_driver_register(&tegra_platform_ahci_driver);
1772}
1773
1774static void __exit ahci_exit(void)
1775{
1776 platform_driver_unregister(&tegra_platform_ahci_driver);
1777}
1778
1779
1780#ifdef CONFIG_DEBUG_FS
1781
1782#include <linux/debugfs.h>
1783#include <linux/seq_file.h>
1784
1785static void dbg_ahci_dump_regs(struct seq_file *s, u32 *ptr, u32 base, u32 regs)
1786{
1787#define REGS_PER_LINE 4
1788
1789 u32 i, j;
1790 u32 lines = regs / REGS_PER_LINE;
1791
1792 for (i = 0; i < lines; i++) {
1793 seq_printf(s, "0x%08x: ", base+(i*16));
1794 for (j = 0; j < REGS_PER_LINE; ++j) {
1795 seq_printf(s, "0x%08x ", readl(ptr));
1796 ++ptr;
1797 }
1798 seq_printf(s, "\n");
1799 }
1800#undef REGS_PER_LINE
1801}
1802
1803static int dbg_ahci_dump_show(struct seq_file *s, void *unused)
1804{
1805 u32 base;
1806 u32 *ptr;
1807 u32 i;
1808
1809 base = TEGRA_SATA_CONFIG_BASE;
1810 ptr = (u32 *)IO_TO_VIRT(base);
1811 seq_printf(s, "SATA CONFIG Registers:\n");
1812 seq_printf(s, "----------------------\n");
1813 dbg_ahci_dump_regs(s, ptr, base, 0x200);
1814
1815 base = TEGRA_SATA_BAR5_BASE;
1816 ptr = (u32 *)IO_TO_VIRT(base);
1817 seq_printf(s, "\nAHCI HBA Registers:\n");
1818 seq_printf(s, "-------------------\n");
1819 dbg_ahci_dump_regs(s, ptr, base, 64);
1820
1821 for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1822 base = TEGRA_SATA_BAR5_BASE + 0x100 + (0x80*i);
1823 ptr = (u32 *)IO_TO_VIRT(base);
1824 seq_printf(s, "\nPort %u Registers:\n", i);
1825 seq_printf(s, "---------------\n");
1826 dbg_ahci_dump_regs(s, ptr, base, 16);
1827 }
1828
1829 /* adjust tegra_ahci_idle_time to minimum if it is too small */
1830 tegra_ahci_idle_time = max((u32)TEGRA_AHCI_MIN_IDLE_TIME,
1831 tegra_ahci_idle_time);
1832 seq_printf(s, "\nIdle Timeout = %u milli-seconds.\n",
1833 tegra_ahci_idle_time);
1834 if (tegra_powergate_is_powered(TEGRA_POWERGATE_SATA))
1835 seq_printf(s, "\n=== SATA controller is powered on ===\n\n");
1836 else
1837 seq_printf(s, "\n=== SATA controller is powered off ===\n\n");
1838
1839 return 0;
1840}
1841
1842static int dbg_ahci_dump_open(struct inode *inode, struct file *file)
1843{
1844 return single_open(file, dbg_ahci_dump_show, &inode->i_private);
1845}
1846
1847static const struct file_operations debug_fops = {
1848 .open = dbg_ahci_dump_open,
1849 .read = seq_read,
1850 .llseek = seq_lseek,
1851 .release = single_release,
1852};
1853
1854static int __init tegra_ahci_dump_debuginit(void)
1855{
1856 (void) debugfs_create_file("tegra_ahci", S_IRUGO,
1857 NULL, NULL, &debug_fops);
1858 (void) debugfs_create_u32("tegra_ahci_idle_ms", S_IRWXUGO,
1859 NULL, &tegra_ahci_idle_time);
1860 return 0;
1861}
1862late_initcall(tegra_ahci_dump_debuginit);
1863#endif
1864
1865MODULE_AUTHOR("NVIDIA");
1866MODULE_DESCRIPTION("Tegra AHCI SATA low-level driver");
1867MODULE_LICENSE("GPL");
1868MODULE_VERSION(DRV_VERSION);
1869
1870module_init(ahci_init);
1871module_exit(ahci_exit);
diff --git a/drivers/ata/pata_qdi.c b/drivers/ata/pata_qdi.c
new file mode 100644
index 00000000000..45879dc6fa4
--- /dev/null
+++ b/drivers/ata/pata_qdi.c
@@ -0,0 +1,366 @@
1/*
2 * pata_qdi.c - QDI VLB ATA controllers
3 * (C) 2006 Red Hat
4 *
5 * This driver mostly exists as a proof of concept for non PCI devices under
6 * libata. While the QDI6580 was 'neat' in 1993 it is no longer terribly
7 * useful.
8 *
9 * Tuning code written from the documentation at
10 * http://www.ryston.cz/petr/vlb/qd6500.html
11 * http://www.ryston.cz/petr/vlb/qd6580.html
12 *
13 * Probe code based on drivers/ide/legacy/qd65xx.c
14 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
15 * Samuel Thibault <samuel.thibault@ens-lyon.org>
16 */
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/pci.h>
21#include <linux/init.h>
22#include <linux/blkdev.h>
23#include <linux/delay.h>
24#include <scsi/scsi_host.h>
25#include <linux/libata.h>
26#include <linux/platform_device.h>
27
28#define DRV_NAME "pata_qdi"
29#define DRV_VERSION "0.3.1"
30
31#define NR_HOST 4 /* Two 6580s */
32
33struct qdi_data {
34 unsigned long timing;
35 u8 clock[2];
36 u8 last;
37 int fast;
38 struct platform_device *platform_dev;
39
40};
41
42static struct ata_host *qdi_host[NR_HOST];
43static struct qdi_data qdi_data[NR_HOST];
44static int nr_qdi_host;
45
46#ifdef MODULE
47static int probe_qdi = 1;
48#else
49static int probe_qdi;
50#endif
51
52static void qdi6500_set_piomode(struct ata_port *ap, struct ata_device *adev)
53{
54 struct ata_timing t;
55 struct qdi_data *qdi = ap->host->private_data;
56 int active, recovery;
57 u8 timing;
58
59 /* Get the timing data in cycles */
60 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
61
62 if (qdi->fast) {
63 active = 8 - clamp_val(t.active, 1, 8);
64 recovery = 18 - clamp_val(t.recover, 3, 18);
65 } else {
66 active = 9 - clamp_val(t.active, 2, 9);
67 recovery = 15 - clamp_val(t.recover, 0, 15);
68 }
69 timing = (recovery << 4) | active | 0x08;
70
71 qdi->clock[adev->devno] = timing;
72
73 outb(timing, qdi->timing);
74}
75
76static void qdi6580_set_piomode(struct ata_port *ap, struct ata_device *adev)
77{
78 struct ata_timing t;
79 struct qdi_data *qdi = ap->host->private_data;
80 int active, recovery;
81 u8 timing;
82
83 /* Get the timing data in cycles */
84 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
85
86 if (qdi->fast) {
87 active = 8 - clamp_val(t.active, 1, 8);
88 recovery = 18 - clamp_val(t.recover, 3, 18);
89 } else {
90 active = 9 - clamp_val(t.active, 2, 9);
91 recovery = 15 - clamp_val(t.recover, 0, 15);
92 }
93 timing = (recovery << 4) | active | 0x08;
94
95 qdi->clock[adev->devno] = timing;
96
97 outb(timing, qdi->timing);
98
99 /* Clear the FIFO */
100 if (adev->class != ATA_DEV_ATA)
101 outb(0x5F, (qdi->timing & 0xFFF0) + 3);
102}
103
104/**
105 * qdi_qc_issue - command issue
106 * @qc: command pending
107 *
108 * Called when the libata layer is about to issue a command. We wrap
109 * this interface so that we can load the correct ATA timings.
110 */
111
112static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
113{
114 struct ata_port *ap = qc->ap;
115 struct ata_device *adev = qc->dev;
116 struct qdi_data *qdi = ap->host->private_data;
117
118 if (qdi->clock[adev->devno] != qdi->last) {
119 if (adev->pio_mode) {
120 qdi->last = qdi->clock[adev->devno];
121 outb(qdi->clock[adev->devno], qdi->timing);
122 }
123 }
124 return ata_sff_qc_issue(qc);
125}
126
127static unsigned int qdi_data_xfer(struct ata_device *dev, unsigned char *buf,
128 unsigned int buflen, int rw)
129{
130 if (ata_id_has_dword_io(dev->id)) {
131 struct ata_port *ap = dev->link->ap;
132 int slop = buflen & 3;
133
134 if (rw == READ)
135 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
136 else
137 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
138
139 if (unlikely(slop)) {
140 __le32 pad;
141 if (rw == READ) {
142 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
143 memcpy(buf + buflen - slop, &pad, slop);
144 } else {
145 memcpy(&pad, buf + buflen - slop, slop);
146 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
147 }
148 buflen += 4 - slop;
149 }
150 } else
151 buflen = ata_sff_data_xfer(dev, buf, buflen, rw);
152
153 return buflen;
154}
155
156static struct scsi_host_template qdi_sht = {
157 ATA_PIO_SHT(DRV_NAME),
158};
159
160static struct ata_port_operations qdi6500_port_ops = {
161 .inherits = &ata_sff_port_ops,
162 .qc_issue = qdi_qc_issue,
163 .sff_data_xfer = qdi_data_xfer,
164 .cable_detect = ata_cable_40wire,
165 .set_piomode = qdi6500_set_piomode,
166};
167
168static struct ata_port_operations qdi6580_port_ops = {
169 .inherits = &qdi6500_port_ops,
170 .set_piomode = qdi6580_set_piomode,
171};
172
173/**
174 * qdi_init_one - attach a qdi interface
175 * @type: Type to display
176 * @io: I/O port start
177 * @irq: interrupt line
178 * @fast: True if on a > 33Mhz VLB
179 *
180 * Register an ISA bus IDE interface. Such interfaces are PIO and we
181 * assume do not support IRQ sharing.
182 */
183
184static __init int qdi_init_one(unsigned long port, int type, unsigned long io, int irq, int fast)
185{
186 unsigned long ctl = io + 0x206;
187 struct platform_device *pdev;
188 struct ata_host *host;
189 struct ata_port *ap;
190 void __iomem *io_addr, *ctl_addr;
191 int ret;
192
193 /*
194 * Fill in a probe structure first of all
195 */
196
197 pdev = platform_device_register_simple(DRV_NAME, nr_qdi_host, NULL, 0);
198 if (IS_ERR(pdev))
199 return PTR_ERR(pdev);
200
201 ret = -ENOMEM;
202 io_addr = devm_ioport_map(&pdev->dev, io, 8);
203 ctl_addr = devm_ioport_map(&pdev->dev, ctl, 1);
204 if (!io_addr || !ctl_addr)
205 goto fail;
206
207 ret = -ENOMEM;
208 host = ata_host_alloc(&pdev->dev, 1);
209 if (!host)
210 goto fail;
211 ap = host->ports[0];
212
213 if (type == 6580) {
214 ap->ops = &qdi6580_port_ops;
215 ap->pio_mask = ATA_PIO4;
216 ap->flags |= ATA_FLAG_SLAVE_POSS;
217 } else {
218 ap->ops = &qdi6500_port_ops;
219 ap->pio_mask = ATA_PIO2; /* Actually PIO3 !IORDY is possible */
220 ap->flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_NO_IORDY;
221 }
222
223 ap->ioaddr.cmd_addr = io_addr;
224 ap->ioaddr.altstatus_addr = ctl_addr;
225 ap->ioaddr.ctl_addr = ctl_addr;
226 ata_sff_std_ports(&ap->ioaddr);
227
228 ata_port_desc(ap, "cmd %lx ctl %lx", io, ctl);
229
230 /*
231 * Hook in a private data structure per channel
232 */
233 ap->private_data = &qdi_data[nr_qdi_host];
234
235 qdi_data[nr_qdi_host].timing = port;
236 qdi_data[nr_qdi_host].fast = fast;
237 qdi_data[nr_qdi_host].platform_dev = pdev;
238
239 printk(KERN_INFO DRV_NAME": qd%d at 0x%lx.\n", type, io);
240
241 /* activate */
242 ret = ata_host_activate(host, irq, ata_sff_interrupt, 0, &qdi_sht);
243 if (ret)
244 goto fail;
245
246 qdi_host[nr_qdi_host++] = dev_get_drvdata(&pdev->dev);
247 return 0;
248
249 fail:
250 platform_device_unregister(pdev);
251 return ret;
252}
253
254/**
255 * qdi_init - attach qdi interfaces
256 *
257 * Attach qdi IDE interfaces by scanning the ports it may occupy.
258 */
259
260static __init int qdi_init(void)
261{
262 unsigned long flags;
263 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
264 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
265 static const int ide_irq[2] = { 14, 15 };
266
267 int ct = 0;
268 int i;
269
270 if (probe_qdi == 0)
271 return -ENODEV;
272
273 /*
274 * Check each possible QD65xx base address
275 */
276
277 for (i = 0; i < 2; i++) {
278 unsigned long port = qd_port[i];
279 u8 r, res;
280
281
282 if (request_region(port, 2, "pata_qdi")) {
283 /* Check for a card */
284 local_irq_save(flags);
285 r = inb_p(port);
286 outb_p(0x19, port);
287 res = inb_p(port);
288 outb_p(r, port);
289 local_irq_restore(flags);
290
291 /* Fail */
292 if (res == 0x19)
293 {
294 release_region(port, 2);
295 continue;
296 }
297
298 /* Passes the presence test */
299 r = inb_p(port + 1); /* Check port agrees with port set */
300 if ((r & 2) >> 1 != i) {
301 release_region(port, 2);
302 continue;
303 }
304
305 /* Check card type */
306 if ((r & 0xF0) == 0xC0) {
307 /* QD6500: single channel */
308 if (r & 8) {
309 /* Disabled ? */
310 release_region(port, 2);
311 continue;
312 }
313 if (qdi_init_one(port, 6500, ide_port[r & 0x01], ide_irq[r & 0x01], r & 0x04) == 0)
314 ct++;
315 }
316 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
317 /* QD6580: dual channel */
318 if (!request_region(port + 2 , 2, "pata_qdi"))
319 {
320 release_region(port, 2);
321 continue;
322 }
323 res = inb(port + 3);
324 if (res & 1) {
325 /* Single channel mode */
326 if (qdi_init_one(port, 6580, ide_port[r & 0x01], ide_irq[r & 0x01], r & 0x04) == 0)
327 ct++;
328 } else {
329 /* Dual channel mode */
330 if (qdi_init_one(port, 6580, 0x1F0, 14, r & 0x04) == 0)
331 ct++;
332 if (qdi_init_one(port + 2, 6580, 0x170, 15, r & 0x04) == 0)
333 ct++;
334 }
335 }
336 }
337 }
338 if (ct != 0)
339 return 0;
340 return -ENODEV;
341}
342
343static __exit void qdi_exit(void)
344{
345 int i;
346
347 for (i = 0; i < nr_qdi_host; i++) {
348 ata_host_detach(qdi_host[i]);
349 /* Free the control resource. The 6580 dual channel has the resources
350 * claimed as a pair of 2 byte resources so we need no special cases...
351 */
352 release_region(qdi_data[i].timing, 2);
353 platform_device_unregister(qdi_data[i].platform_dev);
354 }
355}
356
357MODULE_AUTHOR("Alan Cox");
358MODULE_DESCRIPTION("low-level driver for qdi ATA");
359MODULE_LICENSE("GPL");
360MODULE_VERSION(DRV_VERSION);
361
362module_init(qdi_init);
363module_exit(qdi_exit);
364
365module_param(probe_qdi, int, 0);
366
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-17 07:40:13 -0400