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-rw-r--r--arch/x86/include/asm/perf_event_p4.h4
-rw-r--r--arch/x86/kernel/cpu/perf_event_p4.c2
2 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index 871249cf4d2..2a1a57f7153 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -401,13 +401,13 @@ static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
401#define P4_RETIRED_MISPRED_BRANCH_TYPE P4_EVENT_PACK(0x05, 0x02) 401#define P4_RETIRED_MISPRED_BRANCH_TYPE P4_EVENT_PACK(0x05, 0x02)
402 /* 402 /*
403 * MSR_P4_TBPU_ESCR0: 4, 5 403 * MSR_P4_TBPU_ESCR0: 4, 5
404 * MSR_P4_TBPU_ESCR0: 6, 7 404 * MSR_P4_TBPU_ESCR1: 6, 7
405 */ 405 */
406 406
407#define P4_RETIRED_BRANCH_TYPE P4_EVENT_PACK(0x04, 0x02) 407#define P4_RETIRED_BRANCH_TYPE P4_EVENT_PACK(0x04, 0x02)
408 /* 408 /*
409 * MSR_P4_TBPU_ESCR0: 4, 5 409 * MSR_P4_TBPU_ESCR0: 4, 5
410 * MSR_P4_TBPU_ESCR0: 6, 7 410 * MSR_P4_TBPU_ESCR1: 6, 7
411 */ 411 */
412 412
413#define P4_RESOURCE_STALL P4_EVENT_PACK(0x01, 0x01) 413#define P4_RESOURCE_STALL P4_EVENT_PACK(0x01, 0x01)
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index b7bf9911198..b8a811ab760 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -545,7 +545,7 @@ static void p4_pmu_swap_config_ts(struct hw_perf_event *hwc, int cpu)
545} 545}
546 546
547/* ESCRs are not sequential in memory so we need a map */ 547/* ESCRs are not sequential in memory so we need a map */
548static unsigned int p4_escr_map[ARCH_P4_TOTAL_ESCR] = { 548static const unsigned int p4_escr_map[ARCH_P4_TOTAL_ESCR] = {
549 MSR_P4_ALF_ESCR0, /* 0 */ 549 MSR_P4_ALF_ESCR0, /* 0 */
550 MSR_P4_ALF_ESCR1, /* 1 */ 550 MSR_P4_ALF_ESCR1, /* 1 */
551 MSR_P4_BPU_ESCR0, /* 2 */ 551 MSR_P4_BPU_ESCR0, /* 2 */