2 files changed, 85 insertions, 11 deletions

diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index d053ffca819..5ae58ec025c 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -51,6 +51,7 @@ static struct resource sh7786_pci0_resources[] = {
                 .name   = "PCIe0 MEM 2",
                 .start  = 0xfe100000,
                 .end    = 0xfe100000 + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
         },
 };
 
@@ -74,6 +75,7 @@ static struct resource sh7786_pci1_resources[] = {
                 .name   = "PCIe1 MEM 2",
                 .start  = 0xfe300000,
                 .end    = 0xfe300000 + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
         },
 };
 
@@ -82,6 +84,7 @@ static struct resource sh7786_pci2_resources[] = {
                 .name   = "PCIe2 IO",
                 .start  = 0xfc800000,
                 .end    = 0xfc800000 + SZ_4M - 1,
+                .flags  = IORESOURCE_IO,
         }, {
                 .name   = "PCIe2 MEM 0",
                 .start  = 0x80000000,
@@ -96,6 +99,7 @@ static struct resource sh7786_pci2_resources[] = {
                 .name   = "PCIe2 MEM 2",
                 .start  = 0xfcd00000,
                 .end    = 0xfcd00000 + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
         },
 };
 
@@ -204,16 +208,26 @@ static int phy_init(struct pci_channel *chan)
         return -ETIMEDOUT;
 }
 
+static void pcie_reset(struct sh7786_pcie_port *port)
+{
+        struct pci_channel *chan = port->hose;
+
+        pci_write_reg(chan, 1, SH4A_PCIESRSTR);
+        pci_write_reg(chan, 0, SH4A_PCIETCTLR);
+        pci_write_reg(chan, 0, SH4A_PCIESRSTR);
+        pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
+}
+
 static int pcie_init(struct sh7786_pcie_port *port)
 {
         struct pci_channel *chan = port->hose;
         unsigned int data;
         phys_addr_t memphys;
         size_t memsize;
-        int ret, i;
+        int ret, i, win;
 
         /* Begin initialization */
-        pci_write_reg(chan, 0, SH4A_PCIETCTLR);
+        pcie_reset(port);
 
         /* Initialize as type1. */
         data = pci_read_reg(chan, SH4A_PCIEPCICONF3);
@@ -327,13 +341,19 @@ static int pcie_init(struct sh7786_pcie_port *port)
         printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
                port->index, (data >> 20) & 0x3f);
 
-
-        for (i = 0; i < chan->nr_resources; i++) {
+        for (i = win = 0; i < chan->nr_resources; i++) {
                 struct resource *res = chan->resources + i;
                 resource_size_t size;
                 u32 enable_mask;
 
-                pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
+                /*
+                 * We can't use the 32-bit mode windows in legacy 29-bit
+                 * mode, so just skip them entirely.
+                 */
+                if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
+                        continue;
+
+                pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
 
                 size = resource_size(res);
 
@@ -342,16 +362,18 @@ static int pcie_init(struct sh7786_pcie_port *port)
                  * keeps things pretty simple.
                  */
                 __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
-                             chan->reg_base + SH4A_PCIEPAMR(i));
+                             chan->reg_base + SH4A_PCIEPAMR(win));
 
-                pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
-                pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i));
+                pci_write_reg(chan, res->start, SH4A_PCIEPARL(win));
+                pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(win));
 
                 enable_mask = MASK_PARE;
                 if (res->flags & IORESOURCE_IO)
                         enable_mask |= MASK_SPC;
 
-                pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
+                pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(win));
+
+                win++;
         }
 
         return 0;
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h
index 90a6992576b..1ee054e47ea 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.h
+++ b/arch/sh/drivers/pci/pcie-sh7786.h
@@ -55,8 +55,11 @@
 #define         BITS_ERRRCV     (0)             /* 0 ERRRCV 0 */
 #define         MASK_ERRRCV     (1<<BITS_ERRRCV)
 
+/*      PCIEENBLR        */
+#define SH4A_PCIEENBLR          (0x000008)      /* R/W - 0x0000 0001 32 */
+
 /*      PCIEECR         */
-#define SH4A_PCIEECR            (0x000008)      /* R/W - 0x0000 0000 32 */
+#define SH4A_PCIEECR            (0x00000C)      /* R/W - 0x0000 0000 32 */
 #define         BITS_ENBL       (0)     /* 0 ENBL 0 R/W */
 #define         MASK_ENBL       (1<<BITS_ENBL)
 
@@ -113,6 +116,27 @@
 #define         BITS_MDATA      (0)
 #define         MASK_MDATA      (0xffffffff<<BITS_MDATA)
 
+/*      PCIEUNLOCKCR    */
+#define SH4A_PCIEUNLOCKCR       (0x000048)      /* R/W - 0x0000 0000 32 */
+
+/*      PCIEIDR         */
+#define SH4A_PCIEIDR            (0x000060)      /* R/W - 0x0101 1101 32 */
+
+/*      PCIEDBGCTLR     */
+#define SH4A_PCIEDBGCTLR        (0x000100)      /* R/W - 0x0000 0000 32 */
+
+/*      PCIEINTXR       */
+#define SH4A_PCIEINTXR          (0x004000)      /* R/W - 0x0000 0000 32 */
+
+/*      PCIERMSGR       */
+#define SH4A_PCIERMSGR          (0x004010)      /* R/W - 0x0000 0000 32 */
+
+/*      PCIERSTR        */
+#define SH4A_PCIERSTR(x)        (0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */
+
+/*      PCIESRSTR        */
+#define SH4A_PCIESRSTR          (0x008040)      /* R/W - 0x0000 0000 32 */
+
 /*      PCIEPHYCTLR     */
 #define SH4A_PCIEPHYCTLR        (0x010000)      /* R/W - 0x0000 0000 32 */
 #define         BITS_CKE        (0)
@@ -121,6 +145,9 @@
 /*      PCIERMSGIER     */
 #define SH4A_PCIERMSGIER        (0x004040)      /* R/W - 0x0000 0000 32 */
 
+/*      PCIEPHYCTLR     */
+#define SH4A_PCIEPHYCTLR        (0x010000)      /* R/W - 0x0000 0000 32 */
+
 /*      PCIEPHYADRR     */
 #define SH4A_PCIEPHYADRR        (0x010004)      /* R/W - 0x0000 0000 32 */
 #define         BITS_ACK        (24)                    // Rev1.171
@@ -152,7 +179,7 @@
 #define         MASK_CFINT      (1<<BITS_CFINT)
 
 /*      PCIETSTR        */
-#define SH4A_PCIETSTR           (0x020004)      /* R/W R/W 0x0000 0000 32  */
+#define SH4A_PCIETSTR           (0x020004)      /* R 0x0000 0000 32  */
 
 /*      PCIEINTR        */
 #define SH4A_PCIEINTR           (0x020008)      /* R/W R/W 0x0000 0000 32  */
@@ -236,6 +263,9 @@
 #define         BITS_INTPM                      (8)
 #define         MASK_INTPM                      (1<<BITS_INTPM)
 
+/*      PCIEEH0R        */
+#define SH4A_PCIEEHR(x)         (0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */
+
 /*      PCIEAIR  */
 #define SH4A_PCIEAIR            (SH4A_PCIE_BASE + 0x020010)     /* R/W R/W 0xxxxx xxxx 32 */
 
@@ -244,6 +274,25 @@
 
 /*       PCIEERRFR       */                                                             // Rev1.18
 #define SH4A_PCIEERRFR          (0x020020)              /* R/W R/W 0xxxxx xxxx 32 */    // Rev1.18
+
+/*      PCIEERRFER      */
+#define SH4A_PCIEERRFER         (0x020024)              /* R/W R/W 0x0000 0000 32 */
+
+/*      PCIEERRFR2      */
+#define SH4A_PCIEERRFR2         (0x020028)              /* R/W R/W 0x0000 0000 32 */
+
+/*      PCIEMSIR        */
+#define SH4A_PCIEMSIR           (0x020040)              /* R/W - 0x0000 0000 32 */
+
+/*      PCIEMSIFR       */
+#define SH4A_PCIEMSIFR          (0x020044)              /* R/W R/W 0x0000 0000 32 */
+
+/*      PCIEPWRCTLR     */
+#define SH4A_PCIEPWRCTLR        (0x020100)              /* R/W - 0x0000 0000 32 */
+
+/*      PCIEPCCTLR      */
+#define SH4A_PCIEPCCTLR         (0x020180)              /* R/W - 0x0000 0000 32 */
+
                                                                                         // Rev1.18
 /*      PCIELAR0        */
 #define SH4A_PCIELAR0           (0x020200)      /* R/W R/W 0x0000 0000 32 */
@@ -352,6 +401,7 @@
 #define SH4A_PCIEDMCCR0         (0x021120)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMCC2R0        (0x021124)      /* R/W R/W 0x0000 0000 - */
 #define SH4A_PCIEDMCCCR0        (0x021128)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCHSR0        (0x02112C)      /* R/W - 0x0000 0000 32 */
 #define SH4A_PCIEDMSAR1         (0x021140)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMSAHR1        (0x021144)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMDAR1         (0x021148)      /* R/W R/W 0x0000 0000 32 */
@@ -363,6 +413,7 @@
 #define SH4A_PCIEDMCCR1         (0x021160)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMCC2R1        (0x021164)      /* R/W R/W 0x0000 0000 - */
 #define SH4A_PCIEDMCCCR1        (0x021168)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCHSR1        (0x02116C)      /* R/W - 0x0000 0000 32 */
 #define SH4A_PCIEDMSAR2         (0x021180)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMSAHR2        (0x021184)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMDAR2         (0x021188)      /* R/W R/W 0x0000 0000 32 */
@@ -385,6 +436,7 @@
 #define SH4A_PCIEDMCCR3         (0x0211E0)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMCC2R3        (0x0211E4)      /* R/W R/W 0x0000 0000 -  */
 #define SH4A_PCIEDMCCCR3        (0x0211E8)      /* R/W R/W 0x0000 0000 32 */
+#define SH4A_PCIEDMCHSR3        (0x0211EC)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEPCICONF0       (0x040000)      /* R R - 8/16/32 */
 #define SH4A_PCIEPCICONF1       (0x040004)      /* R/W R/W 0x0008 0000 8/16/32 */
 #define SH4A_PCIEPCICONF2       (0x040008)      /* R/W R/W 0xFF00 0000 8/16/32 */