2043 files changed, 65702 insertions, 32499 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 8c3d957fa8e..72f2fa189cc 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -248,7 +248,14 @@ config HAVE_CMPXCHG_LOCAL
 config HAVE_CMPXCHG_DOUBLE
         bool
 
+config ARCH_WANT_IPC_PARSE_VERSION
+        bool
+
+config ARCH_WANT_COMPAT_IPC_PARSE_VERSION
+        bool
+
 config ARCH_WANT_OLD_COMPAT_IPC
+        select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
         bool
 
 config HAVE_ARCH_SECCOMP_FILTER
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 3de74c9f961..9944dedee5b 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -14,9 +14,12 @@ config ALPHA
         select AUTO_IRQ_AFFINITY if SMP
         select GENERIC_IRQ_SHOW
         select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARCH_WANT_IPC_PARSE_VERSION
         select ARCH_HAVE_NMI_SAFE_CMPXCHG
         select GENERIC_SMP_IDLE_THREAD
         select GENERIC_CMOS_UPDATE
+        select GENERIC_STRNCPY_FROM_USER
+        select GENERIC_STRNLEN_USER
         help
           The Alpha is a 64-bit general-purpose processor designed and
           marketed by the Digital Equipment Corporation of blessed memory,
diff --git a/arch/alpha/include/asm/atomic.h b/arch/alpha/include/asm/atomic.h
index 3bb7ffeae3b..c2cbe4fc391 100644
--- a/arch/alpha/include/asm/atomic.h
+++ b/arch/alpha/include/asm/atomic.h
@@ -14,8 +14,8 @@
  */
 
 
-#define ATOMIC_INIT(i)          ( (atomic_t) { (i) } )
-#define ATOMIC64_INIT(i)        ( (atomic64_t) { (i) } )
+#define ATOMIC_INIT(i)          { (i) }
+#define ATOMIC64_INIT(i)        { (i) }
 
 #define atomic_read(v)          (*(volatile int *)&(v)->counter)
 #define atomic64_read(v)        (*(volatile long *)&(v)->counter)
diff --git a/arch/alpha/include/asm/fpu.h b/arch/alpha/include/asm/fpu.h
index db00f7885fa..e477bcd5b94 100644
--- a/arch/alpha/include/asm/fpu.h
+++ b/arch/alpha/include/asm/fpu.h
@@ -1,7 +1,9 @@
 #ifndef __ASM_ALPHA_FPU_H
 #define __ASM_ALPHA_FPU_H
 
+#ifdef __KERNEL__
 #include <asm/special_insns.h>
+#endif
 
 /*
  * Alpha floating-point control register defines:
diff --git a/arch/alpha/include/asm/ptrace.h b/arch/alpha/include/asm/ptrace.h
index fd698a174f2..b87755a1955 100644
--- a/arch/alpha/include/asm/ptrace.h
+++ b/arch/alpha/include/asm/ptrace.h
@@ -76,7 +76,10 @@ struct switch_stack {
 #define task_pt_regs(task) \
   ((struct pt_regs *) (task_stack_page(task) + 2*PAGE_SIZE) - 1)
 
-#define force_successful_syscall_return() (task_pt_regs(current)->r0 = 0)
+#define current_pt_regs() \
+  ((struct pt_regs *) ((char *)current_thread_info() + 2*PAGE_SIZE) - 1)
+
+#define force_successful_syscall_return() (current_pt_regs()->r0 = 0)
 
 #endif
 
diff --git a/arch/alpha/include/asm/socket.h b/arch/alpha/include/asm/socket.h
index dcb221a4b5b..7d2f75be932 100644
--- a/arch/alpha/include/asm/socket.h
+++ b/arch/alpha/include/asm/socket.h
@@ -76,9 +76,11 @@
 /* Instruct lower device to use last 4-bytes of skb data as FCS */
 #define SO_NOFCS                43
 
+#ifdef __KERNEL__
 /* O_NONBLOCK clashes with the bits used for socket types.  Therefore we
  * have to define SOCK_NONBLOCK to a different value here.
  */
 #define SOCK_NONBLOCK   0x40000000
+#endif /* __KERNEL__ */
 
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/alpha/include/asm/uaccess.h b/arch/alpha/include/asm/uaccess.h
index b49ec2f8d6e..766fdfde2b7 100644
--- a/arch/alpha/include/asm/uaccess.h
+++ b/arch/alpha/include/asm/uaccess.h
@@ -433,36 +433,12 @@ clear_user(void __user *to, long len)
 #undef __module_address
 #undef __module_call
 
-/* Returns: -EFAULT if exception before terminator, N if the entire
-   buffer filled, else strlen.  */
+#define user_addr_max() \
+        (segment_eq(get_fs(), USER_DS) ? TASK_SIZE : ~0UL)
 
-extern long __strncpy_from_user(char *__to, const char __user *__from, long __to_len);
-
-extern inline long
-strncpy_from_user(char *to, const char __user *from, long n)
-{
-        long ret = -EFAULT;
-        if (__access_ok((unsigned long)from, 0, get_fs()))
-                ret = __strncpy_from_user(to, from, n);
-        return ret;
-}
-
-/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
-extern long __strlen_user(const char __user *);
-
-extern inline long strlen_user(const char __user *str)
-{
-        return access_ok(VERIFY_READ,str,0) ? __strlen_user(str) : 0;
-}
-
-/* Returns: 0 if exception before NUL or reaching the supplied limit (N),
- * a value greater than N if the limit would be exceeded, else strlen.  */
-extern long __strnlen_user(const char __user *, long);
-
-extern inline long strnlen_user(const char __user *str, long n)
-{
-        return access_ok(VERIFY_READ,str,0) ? __strnlen_user(str, n) : 0;
-}
+extern long strncpy_from_user(char *dest, const char __user *src, long count);
+extern __must_check long strlen_user(const char __user *str);
+extern __must_check long strnlen_user(const char __user *str, long n);
 
 /*
  * About the exception table:
diff --git a/arch/alpha/include/asm/unistd.h b/arch/alpha/include/asm/unistd.h
index d1f23b722df..a31a78eac9b 100644
--- a/arch/alpha/include/asm/unistd.h
+++ b/arch/alpha/include/asm/unistd.h
@@ -465,12 +465,13 @@
 #define __NR_setns                      501
 #define __NR_accept4                    502
 #define __NR_sendmmsg                   503
+#define __NR_process_vm_readv           504
+#define __NR_process_vm_writev          505
 
 #ifdef __KERNEL__
 
-#define NR_SYSCALLS                     504
+#define NR_SYSCALLS                     506
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_GETHOSTNAME
diff --git a/arch/alpha/include/asm/word-at-a-time.h b/arch/alpha/include/asm/word-at-a-time.h
new file mode 100644
index 00000000000..6b340d0f152
--- /dev/null
+++ b/arch/alpha/include/asm/word-at-a-time.h
@@ -0,0 +1,55 @@
+#ifndef _ASM_WORD_AT_A_TIME_H
+#define _ASM_WORD_AT_A_TIME_H
+
+#include <asm/compiler.h>
+
+/*
+ * word-at-a-time interface for Alpha.
+ */
+
+/*
+ * We do not use the word_at_a_time struct on Alpha, but it needs to be
+ * implemented to humour the generic code.
+ */
+struct word_at_a_time {
+        const unsigned long unused;
+};
+
+#define WORD_AT_A_TIME_CONSTANTS { 0 }
+
+/* Return nonzero if val has a zero */
+static inline unsigned long has_zero(unsigned long val, unsigned long *bits, const struct word_at_a_time *c)
+{
+        unsigned long zero_locations = __kernel_cmpbge(0, val);
+        *bits = zero_locations;
+        return zero_locations;
+}
+
+static inline unsigned long prep_zero_mask(unsigned long val, unsigned long bits, const struct word_at_a_time *c)
+{
+        return bits;
+}
+
+#define create_zero_mask(bits) (bits)
+
+static inline unsigned long find_zero(unsigned long bits)
+{
+#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
+        /* Simple if have CIX instructions */
+        return __kernel_cttz(bits);
+#else
+        unsigned long t1, t2, t3;
+        /* Retain lowest set bit only */
+        bits &= -bits;
+        /* Binary search for lowest set bit */
+        t1 = bits & 0xf0;
+        t2 = bits & 0xcc;
+        t3 = bits & 0xaa;
+        if (t1) t1 = 4;
+        if (t2) t2 = 2;
+        if (t3) t3 = 1;
+        return t1 + t2 + t3;
+#endif
+}
+
+#endif /* _ASM_WORD_AT_A_TIME_H */
diff --git a/arch/alpha/kernel/alpha_ksyms.c b/arch/alpha/kernel/alpha_ksyms.c
index d96e742d4dc..15fa821d09c 100644
--- a/arch/alpha/kernel/alpha_ksyms.c
+++ b/arch/alpha/kernel/alpha_ksyms.c
@@ -52,7 +52,6 @@ EXPORT_SYMBOL(alpha_write_fp_reg_s);
 
 /* entry.S */
 EXPORT_SYMBOL(kernel_thread);
-EXPORT_SYMBOL(kernel_execve);
 
 /* Networking helper routines. */
 EXPORT_SYMBOL(csum_tcpudp_magic);
@@ -74,8 +73,6 @@ EXPORT_SYMBOL(alpha_fp_emul);
  */
 EXPORT_SYMBOL(__copy_user);
 EXPORT_SYMBOL(__do_clear_user);
-EXPORT_SYMBOL(__strncpy_from_user);
-EXPORT_SYMBOL(__strnlen_user);
 
 /* 
  * SMP-specific symbols.
diff --git a/arch/alpha/kernel/entry.S b/arch/alpha/kernel/entry.S
index 6d159cee5f2..ec0da0567ab 100644
--- a/arch/alpha/kernel/entry.S
+++ b/arch/alpha/kernel/entry.S
@@ -663,58 +663,6 @@ kernel_thread:
         br      ret_to_kernel
 .end kernel_thread
 
-/*
- * kernel_execve(path, argv, envp)
- */
-        .align  4
-        .globl  kernel_execve
-        .ent    kernel_execve
-kernel_execve:
-        /* We can be called from a module.  */
-        ldgp    $gp, 0($27)
-        lda     $sp, -(32+SIZEOF_PT_REGS+8)($sp)
-        .frame  $sp, 32+SIZEOF_PT_REGS+8, $26, 0
-        stq     $26, 0($sp)
-        stq     $16, 8($sp)
-        stq     $17, 16($sp)
-        stq     $18, 24($sp)
-        .prologue 1
-
-        lda     $16, 32($sp)
-        lda     $17, 0
-        lda     $18, SIZEOF_PT_REGS
-        bsr     $26, memset             !samegp
-
-        /* Avoid the HAE being gratuitously wrong, which would cause us
-           to do the whole turn off interrupts thing and restore it.  */
-        ldq     $2, alpha_mv+HAE_CACHE
-        stq     $2, 152+32($sp)
-
-        ldq     $16, 8($sp)
-        ldq     $17, 16($sp)
-        ldq     $18, 24($sp)
-        lda     $19, 32($sp)
-        bsr     $26, do_execve          !samegp
-
-        ldq     $26, 0($sp)
-        bne     $0, 1f                  /* error! */
-
-        /* Move the temporary pt_regs struct from its current location
-           to the top of the kernel stack frame.  See copy_thread for
-           details for a normal process.  */
-        lda     $16, 0x4000 - SIZEOF_PT_REGS($8)
-        lda     $17, 32($sp)
-        lda     $18, SIZEOF_PT_REGS
-        bsr     $26, memmove            !samegp
-
-        /* Take that over as our new stack frame and visit userland!  */
-        lda     $sp, 0x4000 - SIZEOF_PT_REGS($8)
-        br      $31, ret_from_sys_call
-
-1:      lda     $sp, 32+SIZEOF_PT_REGS+8($sp)
-        ret
-.end kernel_execve
-
 
 /*
  * Special system calls.  Most of these are special in that they either
@@ -797,115 +745,6 @@ sys_rt_sigreturn:
 .end sys_rt_sigreturn
 
         .align  4
-        .globl  sys_sethae
-        .ent    sys_sethae
-sys_sethae:
-        .prologue 0
-        stq     $16, 152($sp)
-        ret
-.end sys_sethae
-
-        .align  4
-        .globl  osf_getpriority
-        .ent    osf_getpriority
-osf_getpriority:
-        lda     $sp, -16($sp)
-        stq     $26, 0($sp)
-        .prologue 0
-
-        jsr     $26, sys_getpriority
-
-        ldq     $26, 0($sp)
-        blt     $0, 1f
-
-        /* Return value is the unbiased priority, i.e. 20 - prio.
-           This does result in negative return values, so signal
-           no error by writing into the R0 slot.  */
-        lda     $1, 20
-        stq     $31, 16($sp)
-        subl    $1, $0, $0
-        unop
-
-1:      lda     $sp, 16($sp)
-        ret
-.end osf_getpriority
-
-        .align  4
-        .globl  sys_getxuid
-        .ent    sys_getxuid
-sys_getxuid:
-        .prologue 0
-        ldq     $2, TI_TASK($8)
-        ldq     $3, TASK_CRED($2)
-        ldl     $0, CRED_UID($3)
-        ldl     $1, CRED_EUID($3)
-        stq     $1, 80($sp)
-        ret
-.end sys_getxuid
-
-        .align  4
-        .globl  sys_getxgid
-        .ent    sys_getxgid
-sys_getxgid:
-        .prologue 0
-        ldq     $2, TI_TASK($8)
-        ldq     $3, TASK_CRED($2)
-        ldl     $0, CRED_GID($3)
-        ldl     $1, CRED_EGID($3)
-        stq     $1, 80($sp)
-        ret
-.end sys_getxgid
-
-        .align  4
-        .globl  sys_getxpid
-        .ent    sys_getxpid
-sys_getxpid:
-        .prologue 0
-        ldq     $2, TI_TASK($8)
-
-        /* See linux/kernel/timer.c sys_getppid for discussion
-           about this loop.  */
-        ldq     $3, TASK_GROUP_LEADER($2)
-        ldq     $4, TASK_REAL_PARENT($3)
-        ldl     $0, TASK_TGID($2)
-1:      ldl     $1, TASK_TGID($4)
-#ifdef CONFIG_SMP
-        mov     $4, $5
-        mb
-        ldq     $3, TASK_GROUP_LEADER($2)
-        ldq     $4, TASK_REAL_PARENT($3)
-        cmpeq   $4, $5, $5
-        beq     $5, 1b
-#endif
-        stq     $1, 80($sp)
-        ret
-.end sys_getxpid
-
-        .align  4
-        .globl  sys_alpha_pipe
-        .ent    sys_alpha_pipe
-sys_alpha_pipe:
-        lda     $sp, -16($sp)
-        stq     $26, 0($sp)
-        .prologue 0
-
-        mov     $31, $17
-        lda     $16, 8($sp)
-        jsr     $26, do_pipe_flags
-
-        ldq     $26, 0($sp)
-        bne     $0, 1f
-
-        /* The return values are in $0 and $20.  */
-        ldl     $1, 12($sp)
-        ldl     $0, 8($sp)
-
-        stq     $1, 80+16($sp)
-1:      lda     $sp, 16($sp)
-        ret
-.end sys_alpha_pipe
-
-        .align  4
         .globl  sys_execve
         .ent    sys_execve
 sys_execve:
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index 98a103621af..bc1acdda7a5 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -1404,3 +1404,52 @@ SYSCALL_DEFINE3(osf_writev, unsigned long, fd,
 }
 
 #endif
+
+SYSCALL_DEFINE2(osf_getpriority, int, which, int, who)
+{
+        int prio = sys_getpriority(which, who);
+        if (prio >= 0) {
+                /* Return value is the unbiased priority, i.e. 20 - prio.
+                   This does result in negative return values, so signal
+                   no error */
+                force_successful_syscall_return();
+                prio = 20 - prio;
+        }
+        return prio;
+}
+
+SYSCALL_DEFINE0(getxuid)
+{
+        current_pt_regs()->r20 = sys_geteuid();
+        return sys_getuid();
+}
+
+SYSCALL_DEFINE0(getxgid)
+{
+        current_pt_regs()->r20 = sys_getegid();
+        return sys_getgid();
+}
+
+SYSCALL_DEFINE0(getxpid)
+{
+        current_pt_regs()->r20 = sys_getppid();
+        return sys_getpid();
+}
+
+SYSCALL_DEFINE0(alpha_pipe)
+{
+        int fd[2];
+        int res = do_pipe_flags(fd, 0);
+        if (!res) {
+                /* The return values are in $0 and $20.  */
+                current_pt_regs()->r20 = fd[1];
+                res = fd[0];
+        }
+        return res;
+}
+
+SYSCALL_DEFINE1(sethae, unsigned long, val)
+{
+        current_pt_regs()->hae = val;
+        return 0;
+}
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index 1a629636cc1..9816d5a4d17 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -59,15 +59,13 @@ struct pci_controller *pci_isa_hose;
  * Quirks.
  */
 
-static void __init
-quirk_isa_bridge(struct pci_dev *dev)
+static void __devinit quirk_isa_bridge(struct pci_dev *dev)
 {
         dev->class = PCI_CLASS_BRIDGE_ISA << 8;
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
 
-static void __init
-quirk_cypress(struct pci_dev *dev)
+static void __devinit quirk_cypress(struct pci_dev *dev)
 {
         /* The Notorious Cy82C693 chip.  */
 
@@ -106,8 +104,7 @@ quirk_cypress(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
 
 /* Called for each device after PCI setup is done. */
-static void __init
-pcibios_fixup_final(struct pci_dev *dev)
+static void __devinit pcibios_fixup_final(struct pci_dev *dev)
 {
         unsigned int class = dev->class >> 8;
 
@@ -198,12 +195,6 @@ pcibios_init(void)
 
 subsys_initcall(pcibios_init);
 
-char * __devinit
-pcibios_setup(char *str)
-{
-        return str;
-}
-
 #ifdef ALPHA_RESTORE_SRM_SETUP
 static struct pdev_srm_saved_conf *srm_saved_configs;
 
@@ -359,7 +350,7 @@ common_init_pci(void)
                                         hose, &resources);
                 hose->bus = bus;
                 hose->need_domain_info = need_domain_info;
-                next_busno = bus->subordinate + 1;
+                next_busno = bus->busn_res.end + 1;
                 /* Don't allow 8-bit bus number overflow inside the hose -
                    reserve some space for bridges. */ 
                 if (next_busno > 224) {
diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c
index 153d3fce3e8..d6fde98b74b 100644
--- a/arch/alpha/kernel/process.c
+++ b/arch/alpha/kernel/process.c
@@ -455,3 +455,22 @@ get_wchan(struct task_struct *p)
         }
         return pc;
 }
+
+int kernel_execve(const char *path, const char *const argv[], const char *const envp[])
+{
+        /* Avoid the HAE being gratuitously wrong, which would cause us
+           to do the whole turn off interrupts thing and restore it.  */
+        struct pt_regs regs = {.hae = alpha_mv.hae_cache};
+        int err = do_execve(path, argv, envp, &regs);
+        if (!err) {
+                struct pt_regs *p = current_pt_regs();
+                /* copy regs to normal position and off to userland we go... */
+                *p = regs;
+                __asm__ __volatile__ (
+                        "mov    %0, $sp;"
+                        "br     $31, ret_from_sys_call"
+                        : : "r"(p));
+        }
+        return err;
+}
+EXPORT_SYMBOL(kernel_execve);
diff --git a/arch/alpha/kernel/smc37c669.c b/arch/alpha/kernel/smc37c669.c
index 0435921d41c..c803fc76ae4 100644
--- a/arch/alpha/kernel/smc37c669.c
+++ b/arch/alpha/kernel/smc37c669.c
@@ -933,18 +933,6 @@ void SMC37c669_display_device_info(
  *
  *--
  */
-#if 0
-/* $INCLUDE_OPTIONS$ */
-#include    "cp$inc:platform_io.h"
-/* $INCLUDE_OPTIONS_END$ */
-#include    "cp$src:common.h"
-#include    "cp$inc:prototypes.h"
-#include    "cp$src:kernel_def.h"
-#include    "cp$src:msg_def.h"
-#include    "cp$src:smcc669_def.h"
-/* Platform-specific includes */
-#include    "cp$src:platform.h"
-#endif
 
 #ifndef TRUE
 #define TRUE 1
diff --git a/arch/alpha/kernel/systbls.S b/arch/alpha/kernel/systbls.S
index 87835235f11..2ac6b45c3e0 100644
--- a/arch/alpha/kernel/systbls.S
+++ b/arch/alpha/kernel/systbls.S
@@ -111,7 +111,7 @@ sys_call_table:
         .quad sys_socket
         .quad sys_connect
         .quad sys_accept
-        .quad osf_getpriority                   /* 100 */
+        .quad sys_osf_getpriority                       /* 100 */
         .quad sys_send
         .quad sys_recv
         .quad sys_sigreturn
@@ -522,6 +522,8 @@ sys_call_table:
         .quad sys_setns
         .quad sys_accept4
         .quad sys_sendmmsg
+        .quad sys_process_vm_readv
+        .quad sys_process_vm_writev             /* 505 */
 
         .size sys_call_table, . - sys_call_table
         .type sys_call_table, @object
diff --git a/arch/alpha/lib/Makefile b/arch/alpha/lib/Makefile
index c0a83ab62b7..59660743237 100644
--- a/arch/alpha/lib/Makefile
+++ b/arch/alpha/lib/Makefile
@@ -31,8 +31,6 @@ lib-y =	__divqu.o __remqu.o __divlu.o __remlu.o \
         $(ev6-y)memchr.o \
         $(ev6-y)copy_user.o \
         $(ev6-y)clear_user.o \
-        $(ev6-y)strncpy_from_user.o \
-        $(ev67-y)strlen_user.o \
         $(ev6-y)csum_ipv6_magic.o \
         $(ev6-y)clear_page.o \
         $(ev6-y)copy_page.o \
diff --git a/arch/alpha/lib/ev6-strncpy_from_user.S b/arch/alpha/lib/ev6-strncpy_from_user.S
deleted file mode 100644
index d2e28178cac..00000000000
--- a/arch/alpha/lib/ev6-strncpy_from_user.S
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * arch/alpha/lib/ev6-strncpy_from_user.S
- * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
- *
- * Just like strncpy except in the return value:
- *
- * -EFAULT       if an exception occurs before the terminator is copied.
- * N             if the buffer filled.
- *
- * Otherwise the length of the string is returned.
- *
- * Much of the information about 21264 scheduling/coding comes from:
- *      Compiler Writer's Guide for the Alpha 21264
- *      abbreviated as 'CWG' in other comments here
- *      ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
- * Scheduling notation:
- *      E       - either cluster
- *      U       - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
- *      L       - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
- * A bunch of instructions got moved and temp registers were changed
- * to aid in scheduling.  Control flow was also re-arranged to eliminate
- * branches, and to provide longer code sequences to enable better scheduling.
- * A total rewrite (using byte load/stores for start & tail sequences)
- * is desirable, but very difficult to do without a from-scratch rewrite.
- * Save that for the future.
- */
-
-
-#include <asm/errno.h>
-#include <asm/regdef.h>
-
-
-/* Allow an exception for an insn; exit if we get one.  */
-#define EX(x,y...)                      \
-        99: x,##y;                      \
-        .section __ex_table,"a";        \
-        .long 99b - .;                  \
-        lda $31, $exception-99b($0);    \
-        .previous
-
-
-        .set noat
-        .set noreorder
-        .text
-
-        .globl __strncpy_from_user
-        .ent __strncpy_from_user
-        .frame $30, 0, $26
-        .prologue 0
-
-        .align 4
-__strncpy_from_user:
-        and     a0, 7, t3       # E : find dest misalignment
-        beq     a2, $zerolength # U :
-
-        /* Are source and destination co-aligned?  */
-        mov     a0, v0          # E : save the string start
-        xor     a0, a1, t4      # E :
-        EX( ldq_u t1, 0(a1) )   # L : Latency=3 load first quadword
-        ldq_u   t0, 0(a0)       # L : load first (partial) aligned dest quadword
-
-        addq    a2, t3, a2      # E : bias count by dest misalignment
-        subq    a2, 1, a3       # E :
-        addq    zero, 1, t10    # E :
-        and     t4, 7, t4       # E : misalignment between the two
-
-        and     a3, 7, t6       # E : number of tail bytes
-        sll     t10, t6, t10    # E : t10 = bitmask of last count byte
-        bne     t4, $unaligned  # U :
-        lda     t2, -1          # E : build a mask against false zero
-
-        /*
-         * We are co-aligned; take care of a partial first word.
-         * On entry to this basic block:
-         * t0 == the first destination word for masking back in
-         * t1 == the first source word.
-         */
-
-        srl     a3, 3, a2       # E : a2 = loop counter = (count - 1)/8
-        addq    a1, 8, a1       # E :
-        mskqh   t2, a1, t2      # U :   detection in the src word
-        nop
-
-        /* Create the 1st output word and detect 0's in the 1st input word.  */
-        mskqh   t1, a1, t3      # U :
-        mskql   t0, a1, t0      # U : assemble the first output word
-        ornot   t1, t2, t2      # E :
-        nop
-
-        cmpbge  zero, t2, t8    # E : bits set iff null found
-        or      t0, t3, t0      # E :
-        beq     a2, $a_eoc      # U :
-        bne     t8, $a_eos      # U : 2nd branch in a quad.  Bad.
-
-        /* On entry to this basic block:
-         * t0 == a source quad not containing a null.
-         * a0 - current aligned destination address
-         * a1 - current aligned source address
-         * a2 - count of quadwords to move.
-         * NOTE: Loop improvement - unrolling this is going to be
-         *      a huge win, since we're going to stall otherwise.
-         *      Fix this later.  For _really_ large copies, look
-         *      at using wh64 on a look-ahead basis.  See the code
-         *      in clear_user.S and copy_user.S.
-         * Presumably, since (a0) and (a1) do not overlap (by C definition)
-         * Lots of nops here:
-         *      - Separate loads from stores
-         *      - Keep it to 1 branch/quadpack so the branch predictor
-         *        can train.
-         */
-$a_loop:
-        stq_u   t0, 0(a0)       # L :
-        addq    a0, 8, a0       # E :
-        nop
-        subq    a2, 1, a2       # E :
-
-        EX( ldq_u t0, 0(a1) )   # L :
-        addq    a1, 8, a1       # E :
-        cmpbge  zero, t0, t8    # E : Stall 2 cycles on t0
-        beq     a2, $a_eoc      # U :
-
-        beq     t8, $a_loop     # U :
-        nop
-        nop
-        nop
-
-        /* Take care of the final (partial) word store.  At this point
-         * the end-of-count bit is set in t8 iff it applies.
-         *
-         * On entry to this basic block we have:
-         * t0 == the source word containing the null
-         * t8 == the cmpbge mask that found it.
-         */
-$a_eos:
-        negq    t8, t12         # E : find low bit set
-        and     t8, t12, t12    # E : 
-
-        /* We're doing a partial word store and so need to combine
-           our source and original destination words.  */
-        ldq_u   t1, 0(a0)       # L :
-        subq    t12, 1, t6      # E :
-
-        or      t12, t6, t8     # E :
-        zapnot  t0, t8, t0      # U : clear src bytes > null
-        zap     t1, t8, t1      # U : clear dst bytes <= null
-        or      t0, t1, t0      # E :
-
-        stq_u   t0, 0(a0)       # L :
-        br      $finish_up      # L0 :
-        nop
-        nop
-
-        /* Add the end-of-count bit to the eos detection bitmask.  */
-        .align 4
-$a_eoc:
-        or      t10, t8, t8
-        br      $a_eos
-        nop
-        nop
-
-
-/* The source and destination are not co-aligned.  Align the destination
-   and cope.  We have to be very careful about not reading too much and
-   causing a SEGV.  */
-
-        .align 4
-$u_head:
-        /* We know just enough now to be able to assemble the first
-           full source word.  We can still find a zero at the end of it
-           that prevents us from outputting the whole thing.
-
-           On entry to this basic block:
-           t0 == the first dest word, unmasked
-           t1 == the shifted low bits of the first source word
-           t6 == bytemask that is -1 in dest word bytes */
-
-        EX( ldq_u t2, 8(a1) )   # L : load second src word
-        addq    a1, 8, a1       # E :
-        mskql   t0, a0, t0      # U : mask trailing garbage in dst
-        extqh   t2, a1, t4      # U :
-
-        or      t1, t4, t1      # E : first aligned src word complete
-        mskqh   t1, a0, t1      # U : mask leading garbage in src
-        or      t0, t1, t0      # E : first output word complete
-        or      t0, t6, t6      # E : mask original data for zero test
-
-        cmpbge  zero, t6, t8    # E :
-        beq     a2, $u_eocfin   # U :
-        bne     t8, $u_final    # U : bad news - 2nd branch in a quad
-        lda     t6, -1          # E : mask out the bits we have
-
-        mskql   t6, a1, t6      # U :   already seen
-        stq_u   t0, 0(a0)       # L : store first output word
-        or      t6, t2, t2      # E :
-        cmpbge  zero, t2, t8    # E : find nulls in second partial
-
-        addq    a0, 8, a0               # E :
-        subq    a2, 1, a2               # E :
-        bne     t8, $u_late_head_exit   # U :
-        nop
-
-        /* Finally, we've got all the stupid leading edge cases taken care
-           of and we can set up to enter the main loop.  */
-
-        extql   t2, a1, t1      # U : position hi-bits of lo word
-        EX( ldq_u t2, 8(a1) )   # L : read next high-order source word
-        addq    a1, 8, a1       # E :
-        cmpbge  zero, t2, t8    # E :
-
-        beq     a2, $u_eoc      # U :
-        bne     t8, $u_eos      # U :
-        nop
-        nop
-
-        /* Unaligned copy main loop.  In order to avoid reading too much,
-           the loop is structured to detect zeros in aligned source words.
-           This has, unfortunately, effectively pulled half of a loop
-           iteration out into the head and half into the tail, but it does
-           prevent nastiness from accumulating in the very thing we want
-           to run as fast as possible.
-
-           On entry to this basic block:
-           t1 == the shifted high-order bits from the previous source word
-           t2 == the unshifted current source word
-
-           We further know that t2 does not contain a null terminator.  */
-
-        /*
-         * Extra nops here:
-         *      separate load quads from store quads
-         *      only one branch/quad to permit predictor training
-         */
-
-        .align 4
-$u_loop:
-        extqh   t2, a1, t0      # U : extract high bits for current word
-        addq    a1, 8, a1       # E :
-        extql   t2, a1, t3      # U : extract low bits for next time
-        addq    a0, 8, a0       # E :
-
-        or      t0, t1, t0      # E : current dst word now complete
-        EX( ldq_u t2, 0(a1) )   # L : load high word for next time
-        subq    a2, 1, a2       # E :
-        nop
-
-        stq_u   t0, -8(a0)      # L : save the current word
-        mov     t3, t1          # E :
-        cmpbge  zero, t2, t8    # E : test new word for eos
-        beq     a2, $u_eoc      # U :
-
-        beq     t8, $u_loop     # U :
-        nop
-        nop
-        nop
-
-        /* We've found a zero somewhere in the source word we just read.
-           If it resides in the lower half, we have one (probably partial)
-           word to write out, and if it resides in the upper half, we
-           have one full and one partial word left to write out.
-
-           On entry to this basic block:
-           t1 == the shifted high-order bits from the previous source word
-           t2 == the unshifted current source word.  */
-        .align 4
-$u_eos:
-        extqh   t2, a1, t0      # U :
-        or      t0, t1, t0      # E : first (partial) source word complete
-        cmpbge  zero, t0, t8    # E : is the null in this first bit?
-        nop
-
-        bne     t8, $u_final    # U :
-        stq_u   t0, 0(a0)       # L : the null was in the high-order bits
-        addq    a0, 8, a0       # E :
-        subq    a2, 1, a2       # E :
-
-        .align 4
-$u_late_head_exit:
-        extql   t2, a1, t0      # U :
-        cmpbge  zero, t0, t8    # E :
-        or      t8, t10, t6     # E :
-        cmoveq  a2, t6, t8      # E :
-
-        /* Take care of a final (probably partial) result word.
-           On entry to this basic block:
-           t0 == assembled source word
-           t8 == cmpbge mask that found the null.  */
-        .align 4
-$u_final:
-        negq    t8, t6          # E : isolate low bit set
-        and     t6, t8, t12     # E :
-        ldq_u   t1, 0(a0)       # L :
-        subq    t12, 1, t6      # E :
-
-        or      t6, t12, t8     # E :
-        zapnot  t0, t8, t0      # U : kill source bytes > null
-        zap     t1, t8, t1      # U : kill dest bytes <= null
-        or      t0, t1, t0      # E :
-
-        stq_u   t0, 0(a0)       # E :
-        br      $finish_up      # U :
-        nop
-        nop
-
-        .align 4
-$u_eoc:                         # end-of-count
-        extqh   t2, a1, t0      # U :
-        or      t0, t1, t0      # E :
-        cmpbge  zero, t0, t8    # E :
-        nop
-
-        .align 4
-$u_eocfin:                      # end-of-count, final word
-        or      t10, t8, t8     # E :
-        br      $u_final        # U :
-        nop
-        nop
-
-        /* Unaligned copy entry point.  */
-        .align 4
-$unaligned:
-
-        srl     a3, 3, a2       # U : a2 = loop counter = (count - 1)/8
-        and     a0, 7, t4       # E : find dest misalignment
-        and     a1, 7, t5       # E : find src misalignment
-        mov     zero, t0        # E :
-
-        /* Conditionally load the first destination word and a bytemask
-           with 0xff indicating that the destination byte is sacrosanct.  */
-
-        mov     zero, t6        # E :
-        beq     t4, 1f          # U :
-        ldq_u   t0, 0(a0)       # L :
-        lda     t6, -1          # E :
-
-        mskql   t6, a0, t6      # E :
-        nop
-        nop
-        nop
-
-        .align 4
-1:
-        subq    a1, t4, a1      # E : sub dest misalignment from src addr
-        /* If source misalignment is larger than dest misalignment, we need
-           extra startup checks to avoid SEGV.  */
-        cmplt   t4, t5, t12     # E :
-        extql   t1, a1, t1      # U : shift src into place
-        lda     t2, -1          # E : for creating masks later
-
-        beq     t12, $u_head    # U :
-        mskqh   t2, t5, t2      # U : begin src byte validity mask
-        cmpbge  zero, t1, t8    # E : is there a zero?
-        nop
-
-        extql   t2, a1, t2      # U :
-        or      t8, t10, t5     # E : test for end-of-count too
-        cmpbge  zero, t2, t3    # E :
-        cmoveq  a2, t5, t8      # E : Latency=2, extra map slot
-
-        nop                     # E : goes with cmov
-        andnot  t8, t3, t8      # E :
-        beq     t8, $u_head     # U :
-        nop
-
-        /* At this point we've found a zero in the first partial word of
-           the source.  We need to isolate the valid source data and mask
-           it into the original destination data.  (Incidentally, we know
-           that we'll need at least one byte of that original dest word.) */
-
-        ldq_u   t0, 0(a0)       # L :
-        negq    t8, t6          # E : build bitmask of bytes <= zero
-        mskqh   t1, t4, t1      # U :
-        and     t6, t8, t12     # E :
-
-        subq    t12, 1, t6      # E :
-        or      t6, t12, t8     # E :
-        zapnot  t2, t8, t2      # U : prepare source word; mirror changes
-        zapnot  t1, t8, t1      # U : to source validity mask
-
-        andnot  t0, t2, t0      # E : zero place for source to reside
-        or      t0, t1, t0      # E : and put it there
-        stq_u   t0, 0(a0)       # L :
-        nop
-
-        .align 4
-$finish_up:
-        zapnot  t0, t12, t4     # U : was last byte written null?
-        and     t12, 0xf0, t3   # E : binary search for the address of the
-        cmovne  t4, 1, t4       # E : Latency=2, extra map slot
-        nop                     # E : with cmovne
-
-        and     t12, 0xcc, t2   # E : last byte written
-        and     t12, 0xaa, t1   # E :
-        cmovne  t3, 4, t3       # E : Latency=2, extra map slot
-        nop                     # E : with cmovne
-
-        bic     a0, 7, t0
-        cmovne  t2, 2, t2       # E : Latency=2, extra map slot
-        nop                     # E : with cmovne
-        nop
-
-        cmovne  t1, 1, t1       # E : Latency=2, extra map slot
-        nop                     # E : with cmovne
-        addq    t0, t3, t0      # E :
-        addq    t1, t2, t1      # E :
-
-        addq    t0, t1, t0      # E :
-        addq    t0, t4, t0      # add one if we filled the buffer
-        subq    t0, v0, v0      # find string length
-        ret                     # L0 :
-
-        .align 4
-$zerolength:
-        nop
-        nop
-        nop
-        clr     v0
-
-$exception:
-        nop
-        nop
-        nop
-        ret
-
-        .end __strncpy_from_user
diff --git a/arch/alpha/lib/ev67-strlen_user.S b/arch/alpha/lib/ev67-strlen_user.S
deleted file mode 100644
index 57e0d77b81a..00000000000
--- a/arch/alpha/lib/ev67-strlen_user.S
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * arch/alpha/lib/ev67-strlen_user.S
- * 21264 version contributed by Rick Gorton <rick.gorton@api-networks.com>
- *
- * Return the length of the string including the NULL terminator
- * (strlen+1) or zero if an error occurred.
- *
- * In places where it is critical to limit the processing time,
- * and the data is not trusted, strnlen_user() should be used.
- * It will return a value greater than its second argument if
- * that limit would be exceeded. This implementation is allowed
- * to access memory beyond the limit, but will not cross a page
- * boundary when doing so.
- *
- * Much of the information about 21264 scheduling/coding comes from:
- *      Compiler Writer's Guide for the Alpha 21264
- *      abbreviated as 'CWG' in other comments here
- *      ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
- * Scheduling notation:
- *      E       - either cluster
- *      U       - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
- *      L       - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
- * Try not to change the actual algorithm if possible for consistency.
- */
-
-#include <asm/regdef.h>
-
-
-/* Allow an exception for an insn; exit if we get one.  */
-#define EX(x,y...)                      \
-        99: x,##y;                      \
-        .section __ex_table,"a";        \
-        .long 99b - .;                  \
-        lda v0, $exception-99b(zero);   \
-        .previous
-
-
-        .set noreorder
-        .set noat
-        .text
-
-        .globl __strlen_user
-        .ent __strlen_user
-        .frame sp, 0, ra
-
-        .align 4
-__strlen_user:
-        ldah    a1, 32767(zero) # do not use plain strlen_user() for strings
-                                # that might be almost 2 GB long; you should
-                                # be using strnlen_user() instead
-        nop
-        nop
-        nop
-
-        .globl __strnlen_user
-
-        .align 4
-__strnlen_user:
-        .prologue 0
-        EX( ldq_u t0, 0(a0) )   # L : load first quadword (a0 may be misaligned)
-        lda     t1, -1(zero)    # E :
-
-        insqh   t1, a0, t1      # U :
-        andnot  a0, 7, v0       # E :
-        or      t1, t0, t0      # E :
-        subq    a0, 1, a0       # E : get our +1 for the return 
-
-        cmpbge  zero, t0, t1    # E : t1 <- bitmask: bit i == 1 <==> i-th byte == 0
-        subq    a1, 7, t2       # E :
-        subq    a0, v0, t0      # E :
-        bne     t1, $found      # U :
-
-        addq    t2, t0, t2      # E :
-        addq    a1, 1, a1       # E :
-        nop                     # E :
-        nop                     # E :
-
-        .align 4
-$loop:  ble     t2, $limit      # U :
-        EX( ldq t0, 8(v0) )     # L :
-        nop                     # E :
-        nop                     # E :
-
-        cmpbge  zero, t0, t1    # E :
-        subq    t2, 8, t2       # E :
-        addq    v0, 8, v0       # E : addr += 8
-        beq     t1, $loop       # U :
-
-$found: cttz    t1, t2          # U0 :
-        addq    v0, t2, v0      # E :
-        subq    v0, a0, v0      # E :
-        ret                     # L0 :
-
-$exception:
-        nop
-        nop
-        nop
-        ret
-
-        .align 4                # currently redundant
-$limit:
-        nop
-        nop
-        subq    a1, t2, v0
-        ret
-
-        .end __strlen_user
diff --git a/arch/alpha/lib/strlen_user.S b/arch/alpha/lib/strlen_user.S
deleted file mode 100644
index 508a18e9647..00000000000
--- a/arch/alpha/lib/strlen_user.S
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * arch/alpha/lib/strlen_user.S
- *
- * Return the length of the string including the NUL terminator
- * (strlen+1) or zero if an error occurred.
- *
- * In places where it is critical to limit the processing time,
- * and the data is not trusted, strnlen_user() should be used.
- * It will return a value greater than its second argument if
- * that limit would be exceeded. This implementation is allowed
- * to access memory beyond the limit, but will not cross a page
- * boundary when doing so.
- */
-
-#include <asm/regdef.h>
-
-
-/* Allow an exception for an insn; exit if we get one.  */
-#define EX(x,y...)                      \
-        99: x,##y;                      \
-        .section __ex_table,"a";        \
-        .long 99b - .;                  \
-        lda v0, $exception-99b(zero);   \
-        .previous
-
-
-        .set noreorder
-        .set noat
-        .text
-
-        .globl __strlen_user
-        .ent __strlen_user
-        .frame sp, 0, ra
-
-        .align 3
-__strlen_user:
-        ldah    a1, 32767(zero) # do not use plain strlen_user() for strings
-                                # that might be almost 2 GB long; you should
-                                # be using strnlen_user() instead
-
-        .globl __strnlen_user
-
-        .align 3
-__strnlen_user:
-        .prologue 0
-
-        EX( ldq_u t0, 0(a0) )   # load first quadword (a0 may be misaligned)
-        lda     t1, -1(zero)
-        insqh   t1, a0, t1
-        andnot  a0, 7, v0
-        or      t1, t0, t0
-        subq    a0, 1, a0       # get our +1 for the return 
-        cmpbge  zero, t0, t1    # t1 <- bitmask: bit i == 1 <==> i-th byte == 0
-        subq    a1, 7, t2
-        subq    a0, v0, t0
-        bne     t1, $found
-
-        addq    t2, t0, t2
-        addq    a1, 1, a1
-
-        .align 3
-$loop:  ble     t2, $limit
-        EX( ldq t0, 8(v0) )
-        subq    t2, 8, t2
-        addq    v0, 8, v0       # addr += 8
-        cmpbge  zero, t0, t1
-        beq     t1, $loop
-
-$found: negq    t1, t2          # clear all but least set bit
-        and     t1, t2, t1
-
-        and     t1, 0xf0, t2    # binary search for that set bit
-        and     t1, 0xcc, t3
-        and     t1, 0xaa, t4
-        cmovne  t2, 4, t2
-        cmovne  t3, 2, t3
-        cmovne  t4, 1, t4
-        addq    t2, t3, t2
-        addq    v0, t4, v0
-        addq    v0, t2, v0
-        nop                     # dual issue next two on ev4 and ev5
-        subq    v0, a0, v0
-$exception:
-        ret
-
-        .align 3                # currently redundant
-$limit:
-        subq    a1, t2, v0
-        ret
-
-        .end __strlen_user
diff --git a/arch/alpha/lib/strncpy_from_user.S b/arch/alpha/lib/strncpy_from_user.S
deleted file mode 100644
index 73ee21160ff..00000000000
--- a/arch/alpha/lib/strncpy_from_user.S
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * arch/alpha/lib/strncpy_from_user.S
- * Contributed by Richard Henderson (rth@tamu.edu)
- *
- * Just like strncpy except in the return value:
- *
- * -EFAULT       if an exception occurs before the terminator is copied.
- * N             if the buffer filled.
- *
- * Otherwise the length of the string is returned.
- */
-
-
-#include <asm/errno.h>
-#include <asm/regdef.h>
-
-
-/* Allow an exception for an insn; exit if we get one.  */
-#define EX(x,y...)                      \
-        99: x,##y;                      \
-        .section __ex_table,"a";        \
-        .long 99b - .;                  \
-        lda $31, $exception-99b($0);    \
-        .previous
-
-
-        .set noat
-        .set noreorder
-        .text
-
-        .globl __strncpy_from_user
-        .ent __strncpy_from_user
-        .frame $30, 0, $26
-        .prologue 0
-
-        .align 3
-$aligned:
-        /* On entry to this basic block:
-           t0 == the first destination word for masking back in
-           t1 == the first source word.  */
-
-        /* Create the 1st output word and detect 0's in the 1st input word.  */
-        lda     t2, -1          # e1    : build a mask against false zero
-        mskqh   t2, a1, t2      # e0    :   detection in the src word
-        mskqh   t1, a1, t3      # e0    :
-        ornot   t1, t2, t2      # .. e1 :
-        mskql   t0, a1, t0      # e0    : assemble the first output word
-        cmpbge  zero, t2, t8    # .. e1 : bits set iff null found
-        or      t0, t3, t0      # e0    :
-        beq     a2, $a_eoc      # .. e1 :
-        bne     t8, $a_eos      # .. e1 :
-
-        /* On entry to this basic block:
-           t0 == a source word not containing a null.  */
-
-$a_loop:
-        stq_u   t0, 0(a0)       # e0    :
-        addq    a0, 8, a0       # .. e1 :
-        EX( ldq_u t0, 0(a1) )   # e0    :
-        addq    a1, 8, a1       # .. e1 :
-        subq    a2, 1, a2       # e0    :
-        cmpbge  zero, t0, t8    # .. e1 (stall)
-        beq     a2, $a_eoc      # e1    :
-        beq     t8, $a_loop     # e1    :
-
-        /* Take care of the final (partial) word store.  At this point
-           the end-of-count bit is set in t8 iff it applies.
-
-           On entry to this basic block we have:
-           t0 == the source word containing the null
-           t8 == the cmpbge mask that found it.  */
-
-$a_eos:
-        negq    t8, t12         # e0    : find low bit set
-        and     t8, t12, t12    # e1 (stall)
-
-        /* For the sake of the cache, don't read a destination word
-           if we're not going to need it.  */
-        and     t12, 0x80, t6   # e0    :
-        bne     t6, 1f          # .. e1 (zdb)
-
-        /* We're doing a partial word store and so need to combine
-           our source and original destination words.  */
-        ldq_u   t1, 0(a0)       # e0    :
-        subq    t12, 1, t6      # .. e1 :
-        or      t12, t6, t8     # e0    :
-        unop                    #
-        zapnot  t0, t8, t0      # e0    : clear src bytes > null
-        zap     t1, t8, t1      # .. e1 : clear dst bytes <= null
-        or      t0, t1, t0      # e1    :
-
-1:      stq_u   t0, 0(a0)
-        br      $finish_up
-
-        /* Add the end-of-count bit to the eos detection bitmask.  */
-$a_eoc:
-        or      t10, t8, t8
-        br      $a_eos
-
-        /*** The Function Entry Point ***/
-        .align 3
-__strncpy_from_user:
-        mov     a0, v0          # save the string start
-        beq     a2, $zerolength
-
-        /* Are source and destination co-aligned?  */
-        xor     a0, a1, t1      # e0    :
-        and     a0, 7, t0       # .. e1 : find dest misalignment
-        and     t1, 7, t1       # e0    :
-        addq    a2, t0, a2      # .. e1 : bias count by dest misalignment
-        subq    a2, 1, a2       # e0    :
-        and     a2, 7, t2       # e1    :
-        srl     a2, 3, a2       # e0    : a2 = loop counter = (count - 1)/8
-        addq    zero, 1, t10    # .. e1 :
-        sll     t10, t2, t10    # e0    : t10 = bitmask of last count byte
-        bne     t1, $unaligned  # .. e1 :
-
-        /* We are co-aligned; take care of a partial first word.  */
-
-        EX( ldq_u t1, 0(a1) )   # e0    : load first src word
-        addq    a1, 8, a1       # .. e1 :
-
-        beq     t0, $aligned    # avoid loading dest word if not needed
-        ldq_u   t0, 0(a0)       # e0    :
-        br      $aligned        # .. e1 :
-
-
-/* The source and destination are not co-aligned.  Align the destination
-   and cope.  We have to be very careful about not reading too much and
-   causing a SEGV.  */
-
-        .align 3
-$u_head:
-        /* We know just enough now to be able to assemble the first
-           full source word.  We can still find a zero at the end of it
-           that prevents us from outputting the whole thing.
-
-           On entry to this basic block:
-           t0 == the first dest word, unmasked
-           t1 == the shifted low bits of the first source word
-           t6 == bytemask that is -1 in dest word bytes */
-
-        EX( ldq_u t2, 8(a1) )   # e0    : load second src word
-        addq    a1, 8, a1       # .. e1 :
-        mskql   t0, a0, t0      # e0    : mask trailing garbage in dst
-        extqh   t2, a1, t4      # e0    :
-        or      t1, t4, t1      # e1    : first aligned src word complete
-        mskqh   t1, a0, t1      # e0    : mask leading garbage in src
-        or      t0, t1, t0      # e0    : first output word complete
-        or      t0, t6, t6      # e1    : mask original data for zero test
-        cmpbge  zero, t6, t8    # e0    :
-        beq     a2, $u_eocfin   # .. e1 :
-        bne     t8, $u_final    # e1    :
-
-        lda     t6, -1                  # e1    : mask out the bits we have
-        mskql   t6, a1, t6              # e0    :   already seen
-        stq_u   t0, 0(a0)               # e0    : store first output word
-        or      t6, t2, t2              # .. e1 :
-        cmpbge  zero, t2, t8            # e0    : find nulls in second partial
-        addq    a0, 8, a0               # .. e1 :
-        subq    a2, 1, a2               # e0    :
-        bne     t8, $u_late_head_exit   # .. e1 :
-
-        /* Finally, we've got all the stupid leading edge cases taken care
-           of and we can set up to enter the main loop.  */
-
-        extql   t2, a1, t1      # e0    : position hi-bits of lo word
-        EX( ldq_u t2, 8(a1) )   # .. e1 : read next high-order source word
-        addq    a1, 8, a1       # e0    :
-        cmpbge  zero, t2, t8    # e1 (stall)
-        beq     a2, $u_eoc      # e1    :
-        bne     t8, $u_eos      # e1    :
-
-        /* Unaligned copy main loop.  In order to avoid reading too much,
-           the loop is structured to detect zeros in aligned source words.
-           This has, unfortunately, effectively pulled half of a loop
-           iteration out into the head and half into the tail, but it does
-           prevent nastiness from accumulating in the very thing we want
-           to run as fast as possible.
-
-           On entry to this basic block:
-           t1 == the shifted high-order bits from the previous source word
-           t2 == the unshifted current source word
-
-           We further know that t2 does not contain a null terminator.  */
-
-        .align 3
-$u_loop:
-        extqh   t2, a1, t0      # e0    : extract high bits for current word
-        addq    a1, 8, a1       # .. e1 :
-        extql   t2, a1, t3      # e0    : extract low bits for next time
-        addq    a0, 8, a0       # .. e1 :
-        or      t0, t1, t0      # e0    : current dst word now complete
-        EX( ldq_u t2, 0(a1) )   # .. e1 : load high word for next time
-        stq_u   t0, -8(a0)      # e0    : save the current word
-        mov     t3, t1          # .. e1 :
-        subq    a2, 1, a2       # e0    :
-        cmpbge  zero, t2, t8    # .. e1 : test new word for eos
-        beq     a2, $u_eoc      # e1    :
-        beq     t8, $u_loop     # e1    :
-
-        /* We've found a zero somewhere in the source word we just read.
-           If it resides in the lower half, we have one (probably partial)
-           word to write out, and if it resides in the upper half, we
-           have one full and one partial word left to write out.
-
-           On entry to this basic block:
-           t1 == the shifted high-order bits from the previous source word
-           t2 == the unshifted current source word.  */
-$u_eos:
-        extqh   t2, a1, t0      # e0    :
-        or      t0, t1, t0      # e1    : first (partial) source word complete
-
-        cmpbge  zero, t0, t8    # e0    : is the null in this first bit?
-        bne     t8, $u_final    # .. e1 (zdb)
-
-        stq_u   t0, 0(a0)       # e0    : the null was in the high-order bits
-        addq    a0, 8, a0       # .. e1 :
-        subq    a2, 1, a2       # e1    :
-
-$u_late_head_exit:
-        extql   t2, a1, t0      # .. e0 :
-        cmpbge  zero, t0, t8    # e0    :
-        or      t8, t10, t6     # e1    :
-        cmoveq  a2, t6, t8      # e0    :
-        nop                     # .. e1 :
-
-        /* Take care of a final (probably partial) result word.
-           On entry to this basic block:
-           t0 == assembled source word
-           t8 == cmpbge mask that found the null.  */
-$u_final:
-        negq    t8, t6          # e0    : isolate low bit set
-        and     t6, t8, t12     # e1    :
-
-        and     t12, 0x80, t6   # e0    : avoid dest word load if we can
-        bne     t6, 1f          # .. e1 (zdb)
-
-        ldq_u   t1, 0(a0)       # e0    :
-        subq    t12, 1, t6      # .. e1 :
-        or      t6, t12, t8     # e0    :
-        zapnot  t0, t8, t0      # .. e1 : kill source bytes > null
-        zap     t1, t8, t1      # e0    : kill dest bytes <= null
-        or      t0, t1, t0      # e1    :
-
-1:      stq_u   t0, 0(a0)       # e0    :
-        br      $finish_up
-
-$u_eoc:                         # end-of-count
-        extqh   t2, a1, t0
-        or      t0, t1, t0
-        cmpbge  zero, t0, t8
-
-$u_eocfin:                      # end-of-count, final word
-        or      t10, t8, t8
-        br      $u_final
-
-        /* Unaligned copy entry point.  */
-        .align 3
-$unaligned:
-
-        EX( ldq_u t1, 0(a1) )   # e0    : load first source word
-
-        and     a0, 7, t4       # .. e1 : find dest misalignment
-        and     a1, 7, t5       # e0    : find src misalignment
-
-        /* Conditionally load the first destination word and a bytemask
-           with 0xff indicating that the destination byte is sacrosanct.  */
-
-        mov     zero, t0        # .. e1 :
-        mov     zero, t6        # e0    :
-        beq     t4, 1f          # .. e1 :
-        ldq_u   t0, 0(a0)       # e0    :
-        lda     t6, -1          # .. e1 :
-        mskql   t6, a0, t6      # e0    :
-1:
-        subq    a1, t4, a1      # .. e1 : sub dest misalignment from src addr
-
-        /* If source misalignment is larger than dest misalignment, we need
-           extra startup checks to avoid SEGV.  */
-
-        cmplt   t4, t5, t12     # e1    :
-        extql   t1, a1, t1      # .. e0 : shift src into place
-        lda     t2, -1          # e0    : for creating masks later
-        beq     t12, $u_head    # e1    :
-
-        mskqh   t2, t5, t2      # e0    : begin src byte validity mask
-        cmpbge  zero, t1, t8    # .. e1 : is there a zero?
-        extql   t2, a1, t2      # e0    :
-        or      t8, t10, t5     # .. e1 : test for end-of-count too
-        cmpbge  zero, t2, t3    # e0    :
-        cmoveq  a2, t5, t8      # .. e1 :
-        andnot  t8, t3, t8      # e0    :
-        beq     t8, $u_head     # .. e1 (zdb)
-
-        /* At this point we've found a zero in the first partial word of
-           the source.  We need to isolate the valid source data and mask
-           it into the original destination data.  (Incidentally, we know
-           that we'll need at least one byte of that original dest word.) */
-
-        ldq_u   t0, 0(a0)       # e0    :
-        negq    t8, t6          # .. e1 : build bitmask of bytes <= zero
-        mskqh   t1, t4, t1      # e0    :
-        and     t6, t8, t12     # .. e1 :
-        subq    t12, 1, t6      # e0    :
-        or      t6, t12, t8     # e1    :
-
-        zapnot  t2, t8, t2      # e0    : prepare source word; mirror changes
-        zapnot  t1, t8, t1      # .. e1 : to source validity mask
-
-        andnot  t0, t2, t0      # e0    : zero place for source to reside
-        or      t0, t1, t0      # e1    : and put it there
-        stq_u   t0, 0(a0)       # e0    :
-
-$finish_up:
-        zapnot  t0, t12, t4     # was last byte written null?
-        cmovne  t4, 1, t4
-
-        and     t12, 0xf0, t3   # binary search for the address of the
-        and     t12, 0xcc, t2   # last byte written
-        and     t12, 0xaa, t1
-        bic     a0, 7, t0
-        cmovne  t3, 4, t3
-        cmovne  t2, 2, t2
-        cmovne  t1, 1, t1
-        addq    t0, t3, t0
-        addq    t1, t2, t1
-        addq    t0, t1, t0
-        addq    t0, t4, t0      # add one if we filled the buffer
-
-        subq    t0, v0, v0      # find string length
-        ret
-
-$zerolength:
-        clr     v0
-$exception:
-        ret
-
-        .end __strncpy_from_user
diff --git a/arch/alpha/mm/fault.c b/arch/alpha/mm/fault.c
index 5eecab1a84e..0c4132dd350 100644
--- a/arch/alpha/mm/fault.c
+++ b/arch/alpha/mm/fault.c
@@ -89,6 +89,8 @@ do_page_fault(unsigned long address, unsigned long mmcsr,
         const struct exception_table_entry *fixup;
         int fault, si_code = SEGV_MAPERR;
         siginfo_t info;
+        unsigned int flags = (FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
+                              (cause > 0 ? FAULT_FLAG_WRITE : 0));
 
         /* As of EV6, a load into $31/$f31 is a prefetch, and never faults
            (or is suppressed by the PALcode).  Support that for older CPUs
@@ -114,6 +116,7 @@ do_page_fault(unsigned long address, unsigned long mmcsr,
                 goto vmalloc_fault;
 #endif
 
+retry:
         down_read(&mm->mmap_sem);
         vma = find_vma(mm, address);
         if (!vma)
@@ -144,8 +147,11 @@ do_page_fault(unsigned long address, unsigned long mmcsr,
         /* If for any reason at all we couldn't handle the fault,
            make sure we exit gracefully rather than endlessly redo
            the fault.  */
-        fault = handle_mm_fault(mm, vma, address, cause > 0 ? FAULT_FLAG_WRITE : 0);
-        up_read(&mm->mmap_sem);
+        fault = handle_mm_fault(mm, vma, address, flags);
+
+        if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
+                return;
+
         if (unlikely(fault & VM_FAULT_ERROR)) {
                 if (fault & VM_FAULT_OOM)
                         goto out_of_memory;
@@ -153,10 +159,26 @@ do_page_fault(unsigned long address, unsigned long mmcsr,
                         goto do_sigbus;
                 BUG();
         }
-        if (fault & VM_FAULT_MAJOR)
-                current->maj_flt++;
-        else
-                current->min_flt++;
+
+        if (flags & FAULT_FLAG_ALLOW_RETRY) {
+                if (fault & VM_FAULT_MAJOR)
+                        current->maj_flt++;
+                else
+                        current->min_flt++;
+                if (fault & VM_FAULT_RETRY) {
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+
+                         /* No need to up_read(&mm->mmap_sem) as we would
+                         * have already released it in __lock_page_or_retry
+                         * in mm/filemap.c.
+                         */
+
+                        goto retry;
+                }
+        }
+
+        up_read(&mm->mmap_sem);
+
         return;
 
         /* Something tried to access memory that isn't in our memory map.
@@ -186,12 +208,14 @@ do_page_fault(unsigned long address, unsigned long mmcsr,
         /* We ran out of memory, or some other thing happened to us that
            made us unable to handle the page fault gracefully.  */
  out_of_memory:
+        up_read(&mm->mmap_sem);
         if (!user_mode(regs))
                 goto no_context;
         pagefault_out_of_memory();
         return;
 
  do_sigbus:
+        up_read(&mm->mmap_sem);
         /* Send a sigbus, regardless of whether we were in kernel
            or user mode.  */
         info.si_signo = SIGBUS;
diff --git a/arch/alpha/oprofile/common.c b/arch/alpha/oprofile/common.c
index a0a5d27aa21..b8ce18f485d 100644
--- a/arch/alpha/oprofile/common.c
+++ b/arch/alpha/oprofile/common.c
@@ -12,6 +12,7 @@
 #include <linux/smp.h>
 #include <linux/errno.h>
 #include <asm/ptrace.h>
+#include <asm/special_insns.h>
 
 #include "op_impl.h"
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a91009c6187..2f88d8d9770 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -6,11 +6,12 @@ config ARM
         select HAVE_DMA_API_DEBUG
         select HAVE_IDE if PCI || ISA || PCMCIA
         select HAVE_DMA_ATTRS
-        select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
+        select HAVE_DMA_CONTIGUOUS if MMU
         select HAVE_MEMBLOCK
         select RTC_LIB
         select SYS_SUPPORTS_APM_EMULATION
         select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
+        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
         select HAVE_ARCH_KGDB
@@ -37,7 +38,7 @@ config ARM
         select HARDIRQS_SW_RESEND
         select GENERIC_IRQ_PROBE
         select GENERIC_IRQ_SHOW
-        select GENERIC_IRQ_PROBE
+        select ARCH_WANT_IPC_PARSE_VERSION
         select HARDIRQS_SW_RESEND
         select CPU_PM if (SUSPEND || CPU_IDLE)
         select GENERIC_PCI_IOMAP
@@ -45,6 +46,9 @@ config ARM
         select GENERIC_SMP_IDLE_THREAD
         select KTIME_SCALAR
         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+        select GENERIC_STRNCPY_FROM_USER
+        select GENERIC_STRNLEN_USER
+        select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -121,11 +125,6 @@ config TRACE_IRQFLAGS_SUPPORT
         bool
         default y
 
-config GENERIC_LOCKBREAK
-        bool
-        default y
-        depends on SMP && PREEMPT
-
 config RWSEM_GENERIC_SPINLOCK
         bool
         default y
@@ -250,12 +249,31 @@ choice
         prompt "ARM system type"
         default ARCH_VERSATILE
 
+config ARCH_SOCFPGA
+        bool "Altera SOCFPGA family"
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_AMBA
+        select ARM_GIC
+        select CACHE_L2X0
+        select CLKDEV_LOOKUP
+        select COMMON_CLK
+        select CPU_V7
+        select DW_APB_TIMER
+        select DW_APB_TIMER_OF
+        select GENERIC_CLOCKEVENTS
+        select GPIO_PL061 if GPIOLIB
+        select HAVE_ARM_SCU
+        select SPARSE_IRQ
+        select USE_OF
+        help
+          This enables support for Altera SOCFPGA Cyclone V platform
+
 config ARCH_INTEGRATOR
         bool "ARM Ltd. Integrator family"
         select ARM_AMBA
         select ARCH_HAS_CPUFREQ
-        select CLKDEV_LOOKUP
-        select HAVE_MACH_CLKDEV
+        select COMMON_CLK
+        select CLK_VERSATILE
         select HAVE_TCM
         select ICST
         select GENERIC_CLOCKEVENTS
@@ -277,6 +295,7 @@ config ARCH_REALVIEW
         select GENERIC_CLOCKEVENTS
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select PLAT_VERSATILE
+        select PLAT_VERSATILE_CLOCK
         select PLAT_VERSATILE_CLCD
         select ARM_TIMER_SP804
         select GPIO_PL061 if GPIOLIB
@@ -295,6 +314,7 @@ config ARCH_VERSATILE
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select NEED_MACH_IO_H if PCI
         select PLAT_VERSATILE
+        select PLAT_VERSATILE_CLOCK
         select PLAT_VERSATILE_CLCD
         select PLAT_VERSATILE_FPGA_IRQ
         select ARM_TIMER_SP804
@@ -307,7 +327,7 @@ config ARCH_VEXPRESS
         select ARM_AMBA
         select ARM_TIMER_SP804
         select CLKDEV_LOOKUP
-        select HAVE_MACH_CLKDEV
+        select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_PATA_PLATFORM
@@ -315,6 +335,7 @@ config ARCH_VEXPRESS
         select NO_IOPORT
         select PLAT_VERSATILE
         select PLAT_VERSATILE_CLCD
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
           This enables support for the ARM Ltd Versatile Express boards.
 
@@ -349,6 +370,7 @@ config ARCH_HIGHBANK
         select ARM_TIMER_SP804
         select CACHE_L2X0
         select CLKDEV_LOOKUP
+        select COMMON_CLK
         select CPU_V7
         select GENERIC_CLOCKEVENTS
         select HAVE_ARM_SCU
@@ -389,6 +411,7 @@ config ARCH_PRIMA2
         bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
         select CPU_V7
         select NO_IOPORT
+        select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
         select CLKDEV_LOOKUP
         select GENERIC_IRQ_CHIP
@@ -447,6 +470,8 @@ config ARCH_MXC
         select CLKSRC_MMIO
         select GENERIC_IRQ_CHIP
         select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+        select USE_OF
         help
           Support for Freescale MXC/iMX-based family of processors
 
@@ -533,6 +558,18 @@ config ARCH_IXP4XX
         help
           Support for Intel's IXP4XX (XScale) family of processors.
 
+config ARCH_MVEBU
+        bool "Marvell SOCs with Device Tree support"
+        select GENERIC_CLOCKEVENTS
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+        select CLKSRC_MMIO
+        select GENERIC_IRQ_CHIP
+        select IRQ_DOMAIN
+        select COMMON_CLK
+        help
+          Support for the Marvell SoC Family with device tree support
+
 config ARCH_DOVE
         bool "Marvell Dove"
         select CPU_V7
@@ -567,6 +604,7 @@ config ARCH_LPC32XX
         select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         select USE_OF
+        select HAVE_PWM
         help
           Support for the NXP LPC32XX family of processors
 
@@ -647,6 +685,7 @@ config ARCH_TEGRA
         select MIGHT_HAVE_CACHE_L2X0
         select NEED_MACH_IO_H if PCI
         select ARCH_HAS_CPUFREQ
+        select USE_OF
         help
           This enables support for NVIDIA Tegra based systems (Tegra APX,
           Tegra 6xx and Tegra 2 series).
@@ -658,6 +697,7 @@ config ARCH_PICOXCELL
         select ARM_VIC
         select CPU_V6K
         select DW_APB_TIMER
+        select DW_APB_TIMER_OF
         select GENERIC_CLOCKEVENTS
         select GENERIC_GPIO
         select HAVE_TCM
@@ -888,7 +928,7 @@ config ARCH_U300
         select ARM_VIC
         select GENERIC_CLOCKEVENTS
         select CLKDEV_LOOKUP
-        select HAVE_MACH_CLKDEV
+        select COMMON_CLK
         select GENERIC_GPIO
         select ARCH_REQUIRE_GPIOLIB
         help
@@ -913,7 +953,7 @@ config ARCH_NOMADIK
         select ARM_AMBA
         select ARM_VIC
         select CPU_ARM926T
-        select CLKDEV_LOOKUP
+        select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         select PINCTRL
         select MIGHT_HAVE_CACHE_L2X0
@@ -936,6 +976,7 @@ config ARCH_DAVINCI
 
 config ARCH_OMAP
         bool "TI OMAP"
+        depends on MMU
         select HAVE_CLK
         select ARCH_REQUIRE_GPIOLIB
         select ARCH_HAS_CPUFREQ
@@ -964,7 +1005,6 @@ config ARCH_VT8500
         select ARCH_HAS_CPUFREQ
         select GENERIC_CLOCKEVENTS
         select ARCH_REQUIRE_GPIOLIB
-        select HAVE_PWM
         help
           Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
 
@@ -987,6 +1027,8 @@ endchoice
 # Kconfigs may be included either alphabetically (according to the
 # plat- suffix) or along side the corresponding mach-* source.
 #
+source "arch/arm/mach-mvebu/Kconfig"
+
 source "arch/arm/mach-at91/Kconfig"
 
 source "arch/arm/mach-bcmring/Kconfig"
@@ -1021,8 +1063,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
 
 source "arch/arm/mach-ks8695/Kconfig"
 
-source "arch/arm/mach-lpc32xx/Kconfig"
-
 source "arch/arm/mach-msm/Kconfig"
 
 source "arch/arm/mach-mv78xx0/Kconfig"
@@ -1105,6 +1145,7 @@ config PLAT_ORION
         bool
         select CLKSRC_MMIO
         select GENERIC_IRQ_CHIP
+        select IRQ_DOMAIN
         select COMMON_CLK
 
 config PLAT_PXA
@@ -1581,6 +1622,7 @@ config ARCH_NR_GPIO
         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
         default 355 if ARCH_U8500
         default 264 if MACH_H4700
+        default 512 if SOC_OMAP5
         default 0
         help
           Maximum number of GPIOs in the system.
@@ -1961,6 +2003,25 @@ config ARM_ATAG_DTB_COMPAT
           bootloaders, this option allows zImage to extract the information
           from the ATAG list and store it at run time into the appended DTB.
 
+choice
+        prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
+        default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
+
+config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
+        bool "Use bootloader kernel arguments if available"
+        help
+          Uses the command-line options passed by the boot loader instead of
+          the device tree bootargs property. If the boot loader doesn't provide
+          any, the device tree bootargs property will be used.
+
+config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
+        bool "Extend with bootloader kernel arguments"
+        help
+          The command-line arguments provided by the boot loader will be
+          appended to the the device tree bootargs property.
+
+endchoice
+
 config CMDLINE
         string "Default kernel command string"
         default ""
@@ -2083,6 +2144,7 @@ source "drivers/cpufreq/Kconfig"
 config CPU_FREQ_IMX
         tristate "CPUfreq driver for i.MX CPUs"
         depends on ARCH_MXC && CPU_FREQ
+        select CPU_FREQ_TABLE
         help
           This enables the CPUfreq driver for i.MX CPUs.
 
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 01a13414121..f15f82bf3a5 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -310,6 +310,32 @@ choice
                   The uncompressor code port configuration is now handled
                   by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+        config DEBUG_VEXPRESS_UART0_DETECT
+                bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
+                depends on ARCH_VEXPRESS && CPU_CP15_MMU
+                help
+                  This option enables a simple heuristic which tries to determine
+                  the motherboard's memory map variant (original or RS1) and then
+                  choose the relevant UART0 base address.
+
+                  Note that this will only work with standard A-class core tiles,
+                  and may fail with non-standard SMM or custom software models.
+
+        config DEBUG_VEXPRESS_UART0_CA9
+                bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"
+                depends on ARCH_VEXPRESS
+                help
+                  This option selects UART0 at 0x10009000. Except for custom models,
+                  this applies only to the V2P-CA9 tile.
+
+        config DEBUG_VEXPRESS_UART0_RS1
+                bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
+                depends on ARCH_VEXPRESS
+                help
+                  This option selects UART0 at 0x1c090000. This applies to most
+                  of the tiles using the RS1 memory map, including all new A-class
+                  core tiles, FPGA-based SMMs and software models.
+
         config DEBUG_LL_UART_NONE
                 bool "No low-level debugging UART"
                 help
@@ -369,4 +395,13 @@ config ARM_KPROBES_TEST
         help
           Perform tests of kprobes API and instruction set simulation.
 
+config PID_IN_CONTEXTIDR
+        bool "Write the current PID to the CONTEXTIDR register"
+        depends on CPU_COPY_V6
+        help
+          Enabling this option causes the kernel to write the current PID to
+          the PROCID field of the CONTEXTIDR register, at the expense of some
+          additional instructions during context switch. Say Y here only if you
+          are planning to use hardware trace tools with this kernel.
+
 endmenu
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0298b00fe24..30eae87ead6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -10,6 +10,9 @@
 #
 # Copyright (C) 1995-2001 by Russell King
 
+# Ensure linker flags are correct
+LDFLAGS         :=
+
 LDFLAGS_vmlinux :=-p --no-undefined -X
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
@@ -157,6 +160,7 @@ machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
 machine-$(CONFIG_ARCH_IMX_V4_V5)        := imx
 machine-$(CONFIG_ARCH_IMX_V6_V7)        := imx
 machine-$(CONFIG_ARCH_MXS)              := mxs
+machine-$(CONFIG_ARCH_MVEBU)            := mvebu
 machine-$(CONFIG_ARCH_NETX)             := netx
 machine-$(CONFIG_ARCH_NOMADIK)          := nomadik
 machine-$(CONFIG_ARCH_OMAP1)            := omap1
@@ -186,6 +190,7 @@ machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
 machine-$(CONFIG_ARCH_VT8500)           := vt8500
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
+machine-$(CONFIG_ARCH_SOCFPGA)          := socfpga
 machine-$(CONFIG_MACH_SPEAR1310)        := spear13xx
 machine-$(CONFIG_MACH_SPEAR1340)        := spear13xx
 machine-$(CONFIG_MACH_SPEAR300)         := spear3xx
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
index 797f04bedb4..aabc02a6848 100644
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -1,6 +1,12 @@
 #include <asm/setup.h>
 #include <libfdt.h>
 
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
+#define do_extend_cmdline 1
+#else
+#define do_extend_cmdline 0
+#endif
+
 static int node_offset(void *fdt, const char *node_path)
 {
         int offset = fdt_path_offset(fdt, node_path);
@@ -36,6 +42,48 @@ static int setprop_cell(void *fdt, const char *node_path,
         return fdt_setprop_cell(fdt, offset, property, val);
 }
 
+static const void *getprop(const void *fdt, const char *node_path,
+                           const char *property, int *len)
+{
+        int offset = fdt_path_offset(fdt, node_path);
+
+        if (offset == -FDT_ERR_NOTFOUND)
+                return NULL;
+
+        return fdt_getprop(fdt, offset, property, len);
+}
+
+static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
+{
+        char cmdline[COMMAND_LINE_SIZE];
+        const char *fdt_bootargs;
+        char *ptr = cmdline;
+        int len = 0;
+
+        /* copy the fdt command line into the buffer */
+        fdt_bootargs = getprop(fdt, "/chosen", "bootargs", &len);
+        if (fdt_bootargs)
+                if (len < COMMAND_LINE_SIZE) {
+                        memcpy(ptr, fdt_bootargs, len);
+                        /* len is the length of the string
+                         * including the NULL terminator */
+                        ptr += len - 1;
+                }
+
+        /* and append the ATAG_CMDLINE */
+        if (fdt_cmdline) {
+                len = strlen(fdt_cmdline);
+                if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
+                        *ptr++ = ' ';
+                        memcpy(ptr, fdt_cmdline, len);
+                        ptr += len;
+                }
+        }
+        *ptr = '\0';
+
+        setprop_string(fdt, "/chosen", "bootargs", cmdline);
+}
+
 /*
  * Convert and fold provided ATAGs into the provided FDT.
  *
@@ -72,8 +120,18 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
 
         for_each_tag(atag, atag_list) {
                 if (atag->hdr.tag == ATAG_CMDLINE) {
-                        setprop_string(fdt, "/chosen", "bootargs",
-                                        atag->u.cmdline.cmdline);
+                        /* Append the ATAGS command line to the device tree
+                         * command line.
+                         * NB: This means that if the same parameter is set in
+                         * the device tree and in the tags, the one from the
+                         * tags will be chosen.
+                         */
+                        if (do_extend_cmdline)
+                                merge_fdt_bootargs(fdt,
+                                                   atag->u.cmdline.cmdline);
+                        else
+                                setprop_string(fdt, "/chosen", "bootargs",
+                                               atag->u.cmdline.cmdline);
                 } else if (atag->hdr.tag == ATAG_MEM) {
                         if (memcount >= sizeof(mem_reg_property)/4)
                                 continue;
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts
new file mode 100644
index 00000000000..29b9f15e759
--- /dev/null
+++ b/arch/arm/boot/dts/aks-cdu.dts
@@ -0,0 +1,113 @@
+/*
+ * aks-cdu.dts - Device Tree file for AK signal CDU
+ *
+ * Copyright (C) 2012 AK signal Brno a.s.
+ *               2012 Jiri Prchal <jiri.prchal@aksignal.cz>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "ge863-pro3.dtsi"
+
+/ {
+        chosen {
+                bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs";
+        };
+
+        ahb {
+                apb {
+                        usart0: serial@fffb0000 {
+                                status = "okay";
+                        };
+
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                                linux,rs485-enabled-at-boot-time;
+                                rs485-rts-delay = <0 0>;
+                                };
+
+                        usart2: serial@fffb8000 {
+                                status = "okay";
+                                linux,rs485-enabled-at-boot-time;
+                                rs485-rts-delay = <0 0>;
+                        };
+
+                        usart3: serial@fffd0000 {
+                                status = "okay";
+                                linux,rs485-enabled-at-boot-time;
+                                rs485-rts-delay = <0 0>;
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 15 0>;
+                                status = "okay";
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        bootstrap@0 {
+                                label = "bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        uboot@40000 {
+                                label = "uboot";
+                                reg = <0x40000 0x80000>;
+                        };
+                        ubootenv@c0000 {
+                                label = "ubootenv";
+                                reg = <0xc0000 0x40000>;
+                        };
+                        kernel@100000 {
+                                label = "kernel";
+                                reg = <0x100000 0x400000>;
+                        };
+                        rootfs@500000 {
+                                label = "rootfs";
+                                reg = <0x500000 0x7b00000>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                red {
+                        gpios = <&pioC 10 0>;
+                        linux,default-trigger = "none";
+                };
+
+                green {
+                        gpios = <&pioA 5 1>;
+                        linux,default-trigger = "none";
+                        default-state = "on";
+                };
+
+                yellow {
+                        gpios = <&pioB 20 1>;
+                        linux,default-trigger = "none";
+                };
+
+                blue {
+                        gpios = <&pioB 21 1>;
+                        linux,default-trigger = "none";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
new file mode 100644
index 00000000000..a9af4db7234
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "am33xx.dtsi"
+
+/ {
+        model = "TI AM335x BeagleBone";
+        compatible = "ti,am335x-bone", "ti,am33xx";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
new file mode 100644
index 00000000000..d6a97d9eff7
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "am33xx.dtsi"
+
+/ {
+        model = "TI AM335x EVM";
+        compatible = "ti,am335x-evm", "ti,am33xx";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
new file mode 100644
index 00000000000..bd0cff3f808
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -0,0 +1,163 @@
+/*
+ * Device Tree Source for AM33XX SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "ti,am33xx";
+
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                serial5 = &uart6;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+
+        /*
+         * The soc node represents the soc top level view. It is uses for IPs
+         * that are not memory mapped in the MPU view or for the MPU itself.
+         */
+        soc {
+                compatible = "ti,omap-infra";
+                mpu {
+                        compatible = "ti,omap3-mpu";
+                        ti,hwmods = "mpu";
+                };
+        };
+
+        /*
+         * XXX: Use a flat representation of the AM33XX interconnect.
+         * The real AM33XX interconnect network is quite complex.Since
+         * that will not bring real advantage to represent that in DT
+         * for the moment, just use a fake OCP bus entry to represent
+         * the whole bus hierarchy.
+         */
+        ocp {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ti,hwmods = "l3_main";
+
+                intc: interrupt-controller@48200000 {
+                        compatible = "ti,omap2-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        ti,intc-size = <128>;
+                        reg = <0x48200000 0x1000>;
+                };
+
+                gpio1: gpio@44e07000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio1";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio2: gpio@4804C000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio2";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio3: gpio@481AC000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio3";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio4: gpio@481AE000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio4";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                uart1: serial@44E09000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+
+                uart2: serial@48022000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+
+                uart3: serial@48024000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+
+                uart4: serial@481A6000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
+
+                uart5: serial@481A8000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart5";
+                        clock-frequency = <48000000>;
+                };
+
+                uart6: serial@481AA000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart6";
+                        clock-frequency = <48000000>;
+                };
+
+                i2c1: i2c@44E0B000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c1";
+                };
+
+                i2c2: i2c@4802A000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c2";
+                };
+
+                i2c3: i2c@4819C000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c3";
+                };
+
+                wdt2: wdt@44e35000 {
+                        compatible = "ti,omap3-wdt";
+                        ti,hwmods = "wd_timer2";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
new file mode 100644
index 00000000000..474f760ecad
--- /dev/null
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+        model = "TI AM3517 EVM (AM3517/05)";
+        compatible = "ti,am3517-evm", "ti,omap3";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+};
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&i2c3 {
+        clock-frequency = <400000>;
+};
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
new file mode 100644
index 00000000000..fffd5c2a304
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -0,0 +1,42 @@
+/*
+ * Device Tree file for Marvell Armada 370 evaluation board
+ * (DB-88F6710-BP-DDR3)
+ *
+ *  Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "armada-370.dtsi"
+
+/ {
+        model = "Marvell Armada 370 Evaluation Board";
+        compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>; /* 512 MB */
+        };
+
+        soc {
+                serial@d0012000 {
+                        clock-frequency = <200000000>;
+                        status = "okay";
+                };
+                timer@d0020300 {
+                        clock-frequency = <600000000>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
new file mode 100644
index 00000000000..6b6b932a5a7
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common to the Armada
+ * 370 and Armada XP SoC.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        model = "Marvell Armada 370 and XP SoC";
+        compatible = "marvell,armada_370_xp";
+
+        cpus {
+                cpu@0 {
+                        compatible = "marvell,sheeva-v7";
+                };
+        };
+
+        mpic: interrupt-controller@d0020000 {
+              compatible = "marvell,mpic";
+              #interrupt-cells = <1>;
+              #address-cells = <1>;
+              #size-cells = <1>;
+              interrupt-controller;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&mpic>;
+                ranges;
+
+                serial@d0012000 {
+                                compatible = "ns16550";
+                                reg = <0xd0012000 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <41>;
+                                status = "disabled";
+                };
+                serial@d0012100 {
+                                compatible = "ns16550";
+                                reg = <0xd0012100 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <42>;
+                                status = "disabled";
+                };
+
+                timer@d0020300 {
+                               compatible = "marvell,armada-370-xp-timer";
+                               reg = <0xd0020300 0x30>;
+                               interrupts = <37>, <38>, <39>, <40>;
+                };
+        };
+};
+
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
new file mode 100644
index 00000000000..3228ccc8333
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Device Tree Include file for Marvell Armada 370 family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada 370 SoC that are not
+ * common to all Armada SoCs.
+ */
+
+/include/ "armada-370-xp.dtsi"
+
+/ {
+        model = "Marvell Armada 370 family SoC";
+        compatible = "marvell,armada370", "marvell,armada-370-xp";
+
+        mpic: interrupt-controller@d0020000 {
+              reg = <0xd0020a00 0x1d0>,
+                    <0xd0021870 0x58>;
+        };
+
+        soc {
+                system-controller@d0018200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0xd0018200 0x100>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
new file mode 100644
index 00000000000..f97040d4258
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -0,0 +1,50 @@
+/*
+ * Device Tree file for Marvell Armada XP evaluation board
+ * (DB-78460-BP)
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP Evaluation Board";
+        compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        chosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000>; /* 2 GB */
+        };
+
+        soc {
+                serial@d0012000 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012100 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012200 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+                serial@d0012300 {
+                        clock-frequency = <250000000>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
new file mode 100644
index 00000000000..71d6b5d0daf
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -0,0 +1,55 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP SoC that are not
+ * common to all Armada SoCs.
+ */
+
+/include/ "armada-370-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP family SoC";
+        compatible = "marvell,armadaxp", "marvell,armada-370-xp";
+
+        mpic: interrupt-controller@d0020000 {
+              reg = <0xd0020a00 0x1d0>,
+                    <0xd0021870 0x58>;
+        };
+
+        soc {
+                serial@d0012200 {
+                                compatible = "ns16550";
+                                reg = <0xd0012200 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <43>;
+                                status = "disabled";
+                };
+                serial@d0012300 {
+                                compatible = "ns16550";
+                                reg = <0xd0012300 0x100>;
+                                reg-shift = <2>;
+                                interrupts = <44>;
+                                status = "disabled";
+                };
+
+                timer@d0020300 {
+                                marvell,timer-25Mhz;
+                };
+
+                system-controller@d0018200 {
+                                compatible = "marvell,armada-370-xp-system-controller";
+                                reg = <0xd0018200 0x500>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index f449efc9825..66389c1c6f6 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -52,10 +52,11 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <3>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <29 30 31>;
                         };
 
                         ramc0: ramc@ffffea00 {
@@ -81,25 +82,25 @@
                         pit: timer@fffffd30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                         };
 
                         tcb0: timer@fffa0000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffa0000 0x100>;
-                                interrupts = <17 4 18 4 19 4>;
+                                interrupts = <17 4 0 18 4 0 19 4 0>;
                         };
 
                         tcb1: timer@fffdc000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffdc000 0x100>;
-                                interrupts = <26 4 27 4 28 4>;
+                                interrupts = <26 4 0 27 4 0 28 4 0>;
                         };
 
                         pioA: gpio@fffff400 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff400 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -108,7 +109,7 @@
                         pioB: gpio@fffff600 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff600 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -117,7 +118,7 @@
                         pioC: gpio@fffff800 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff800 0x100>;
-                                interrupts = <4 4>;
+                                interrupts = <4 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -126,14 +127,14 @@
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                                 status = "disabled";
                         };
 
                         usart0: serial@fffb0000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb0000 0x200>;
-                                interrupts = <6 4>;
+                                interrupts = <6 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -142,7 +143,7 @@
                         usart1: serial@fffb4000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb4000 0x200>;
-                                interrupts = <7 4>;
+                                interrupts = <7 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -151,7 +152,7 @@
                         usart2: serial@fffb8000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb8000 0x200>;
-                                interrupts = <8 4>;
+                                interrupts = <8 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -160,7 +161,7 @@
                         usart3: serial@fffd0000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd0000 0x200>;
-                                interrupts = <23 4>;
+                                interrupts = <23 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -169,7 +170,7 @@
                         usart4: serial@fffd4000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd4000 0x200>;
-                                interrupts = <24 4>;
+                                interrupts = <24 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -178,7 +179,7 @@
                         usart5: serial@fffd8000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd8000 0x200>;
-                                interrupts = <25 4>;
+                                interrupts = <25 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -187,21 +188,21 @@
                         macb0: ethernet@fffc4000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffc4000 0x100>;
-                                interrupts = <21 4>;
+                                interrupts = <21 4 3>;
                                 status = "disabled";
                         };
 
                         usb1: gadget@fffa4000 {
                                 compatible = "atmel,at91rm9200-udc";
                                 reg = <0xfffa4000 0x4000>;
-                                interrupts = <10 4>;
+                                interrupts = <10 4 2>;
                                 status = "disabled";
                         };
 
                         adc0: adc@fffe0000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xfffe0000 0x100>;
-                                interrupts = <5 4>;
+                                interrupts = <5 4 0>;
                                 atmel,adc-use-external-triggers;
                                 atmel,adc-channels-used = <0xf>;
                                 atmel,adc-vref = <3300>;
@@ -253,7 +254,7 @@
                 usb0: ohci@00500000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00500000 0x100000>;
-                        interrupts = <20 4>;
+                        interrupts = <20 4 2>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 0209913a65a..b460d6ce9eb 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -48,10 +48,11 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <3>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <30 31>;
                         };
 
                         pmc: pmc@fffffc00 {
@@ -68,13 +69,13 @@
                         pit: timer@fffffd30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                         };
 
                         tcb0: timer@fff7c000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfff7c000 0x100>;
-                                interrupts = <19 4>;
+                                interrupts = <19 4 0>;
                         };
 
                         rstc@fffffd00 {
@@ -90,7 +91,7 @@
                         pioA: gpio@fffff200 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff200 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -99,7 +100,7 @@
                         pioB: gpio@fffff400 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff400 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -108,7 +109,7 @@
                         pioC: gpio@fffff600 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff600 0x100>;
-                                interrupts = <4 4>;
+                                interrupts = <4 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -117,7 +118,7 @@
                         pioD: gpio@fffff800 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff800 0x100>;
-                                interrupts = <4 4>;
+                                interrupts = <4 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -126,7 +127,7 @@
                         pioE: gpio@fffffa00 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffffa00 0x100>;
-                                interrupts = <4 4>;
+                                interrupts = <4 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -135,14 +136,14 @@
                         dbgu: serial@ffffee00 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                                 status = "disabled";
                         };
 
                         usart0: serial@fff8c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff8c000 0x200>;
-                                interrupts = <7 4>;
+                                interrupts = <7 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -151,7 +152,7 @@
                         usart1: serial@fff90000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff90000 0x200>;
-                                interrupts = <8 4>;
+                                interrupts = <8 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -160,7 +161,7 @@
                         usart2: serial@fff94000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff94000 0x200>;
-                                interrupts = <9 4>;
+                                interrupts = <9 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -169,14 +170,14 @@
                         macb0: ethernet@fffbc000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffbc000 0x100>;
-                                interrupts = <21 4>;
+                                interrupts = <21 4 3>;
                                 status = "disabled";
                         };
 
                         usb1: gadget@fff78000 {
                                 compatible = "atmel,at91rm9200-udc";
                                 reg = <0xfff78000 0x4000>;
-                                interrupts = <24 4>;
+                                interrupts = <24 4 2>;
                                 status = "disabled";
                         };
                 };
@@ -200,7 +201,7 @@
                 usb0: ohci@00a00000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00a00000 0x100000>;
-                        interrupts = <29 4>;
+                        interrupts = <29 4 2>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 7829a4d0cb2..96514c134e5 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -15,7 +15,7 @@
         compatible = "atmel,at91sam9g25ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
 
         chosen {
-                bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+                bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
         };
 
         ahb {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 7dbccaf199f..bafa8806fc1 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -53,10 +53,11 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <3>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <31>;
                         };
 
                         ramc0: ramc@ffffe400 {
@@ -78,7 +79,7 @@
                         pit: timer@fffffd30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                         };
 
 
@@ -90,25 +91,25 @@
                         tcb0: timer@fff7c000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfff7c000 0x100>;
-                                interrupts = <18 4>;
+                                interrupts = <18 4 0>;
                         };
 
                         tcb1: timer@fffd4000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffd4000 0x100>;
-                                interrupts = <18 4>;
+                                interrupts = <18 4 0>;
                         };
 
                         dma: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <21 4>;
+                                interrupts = <21 4 0>;
                         };
 
                         pioA: gpio@fffff200 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff200 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -117,7 +118,7 @@
                         pioB: gpio@fffff400 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff400 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -126,7 +127,7 @@
                         pioC: gpio@fffff600 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff600 0x100>;
-                                interrupts = <4 4>;
+                                interrupts = <4 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -135,7 +136,7 @@
                         pioD: gpio@fffff800 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff800 0x100>;
-                                interrupts = <5 4>;
+                                interrupts = <5 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -144,7 +145,7 @@
                         pioE: gpio@fffffa00 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffffa00 0x100>;
-                                interrupts = <5 4>;
+                                interrupts = <5 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -153,14 +154,14 @@
                         dbgu: serial@ffffee00 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                                 status = "disabled";
                         };
 
                         usart0: serial@fff8c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff8c000 0x200>;
-                                interrupts = <7 4>;
+                                interrupts = <7 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -169,7 +170,7 @@
                         usart1: serial@fff90000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff90000 0x200>;
-                                interrupts = <8 4>;
+                                interrupts = <8 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -178,7 +179,7 @@
                         usart2: serial@fff94000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff94000 0x200>;
-                                interrupts = <9 4>;
+                                interrupts = <9 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -187,7 +188,7 @@
                         usart3: serial@fff98000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff98000 0x200>;
-                                interrupts = <10 4>;
+                                interrupts = <10 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -196,14 +197,14 @@
                         macb0: ethernet@fffbc000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffbc000 0x100>;
-                                interrupts = <25 4>;
+                                interrupts = <25 4 3>;
                                 status = "disabled";
                         };
 
                         adc0: adc@fffb0000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xfffb0000 0x100>;
-                                interrupts = <20 4>;
+                                interrupts = <20 4 0>;
                                 atmel,adc-use-external-triggers;
                                 atmel,adc-channels-used = <0xff>;
                                 atmel,adc-vref = <3300>;
@@ -257,14 +258,14 @@
                 usb0: ohci@00700000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00700000 0x100000>;
-                        interrupts = <22 4>;
+                        interrupts = <22 4 2>;
                         status = "disabled";
                 };
 
                 usb1: ehci@00800000 {
                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                         reg = <0x00800000 0x100000>;
-                        interrupts = <22 4>;
+                        interrupts = <22 4 2>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index cb84de791b5..bfac0dfc332 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -50,7 +50,7 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <3>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 reg = <0xfffff000 0x200>;
@@ -74,7 +74,7 @@
                         pit: timer@fffffe30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffe30 0xf>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                         };
 
                         shdwc@fffffe10 {
@@ -85,25 +85,25 @@
                         tcb0: timer@f8008000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf8008000 0x100>;
-                                interrupts = <17 4>;
+                                interrupts = <17 4 0>;
                         };
 
                         tcb1: timer@f800c000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf800c000 0x100>;
-                                interrupts = <17 4>;
+                                interrupts = <17 4 0>;
                         };
 
                         dma: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <20 4>;
+                                interrupts = <20 4 0>;
                         };
 
                         pioA: gpio@fffff400 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff400 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -112,7 +112,7 @@
                         pioB: gpio@fffff600 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff600 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -121,7 +121,7 @@
                         pioC: gpio@fffff800 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff800 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -130,7 +130,7 @@
                         pioD: gpio@fffffa00 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffffa00 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -139,14 +139,14 @@
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                                 status = "disabled";
                         };
 
                         usart0: serial@f801c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf801c000 0x4000>;
-                                interrupts = <5 4>;
+                                interrupts = <5 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -155,7 +155,7 @@
                         usart1: serial@f8020000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8020000 0x4000>;
-                                interrupts = <6 4>;
+                                interrupts = <6 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -164,7 +164,7 @@
                         usart2: serial@f8024000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8024000 0x4000>;
-                                interrupts = <7 4>;
+                                interrupts = <7 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -173,7 +173,7 @@
                         usart3: serial@f8028000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8028000 0x4000>;
-                                interrupts = <8 4>;
+                                interrupts = <8 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -201,7 +201,7 @@
                 usb0: ohci@00500000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00500000 0x00100000>;
-                        interrupts = <22 4>;
+                        interrupts = <22 4 2>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 6b3ef4339ae..4a18c393b13 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -51,10 +51,11 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <3>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <31>;
                         };
 
                         ramc0: ramc@ffffe800 {
@@ -80,37 +81,37 @@
                         pit: timer@fffffe30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffe30 0xf>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                         };
 
                         tcb0: timer@f8008000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf8008000 0x100>;
-                                interrupts = <17 4>;
+                                interrupts = <17 4 0>;
                         };
 
                         tcb1: timer@f800c000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf800c000 0x100>;
-                                interrupts = <17 4>;
+                                interrupts = <17 4 0>;
                         };
 
                         dma0: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <20 4>;
+                                interrupts = <20 4 0>;
                         };
 
                         dma1: dma-controller@ffffee00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <21 4>;
+                                interrupts = <21 4 0>;
                         };
 
                         pioA: gpio@fffff400 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff400 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -119,7 +120,7 @@
                         pioB: gpio@fffff600 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff600 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -128,7 +129,7 @@
                         pioC: gpio@fffff800 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff800 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -137,7 +138,7 @@
                         pioD: gpio@fffffa00 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffffa00 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -146,14 +147,14 @@
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                                 status = "disabled";
                         };
 
                         usart0: serial@f801c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf801c000 0x200>;
-                                interrupts = <5 4>;
+                                interrupts = <5 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -162,7 +163,7 @@
                         usart1: serial@f8020000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8020000 0x200>;
-                                interrupts = <6 4>;
+                                interrupts = <6 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -171,7 +172,7 @@
                         usart2: serial@f8024000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8024000 0x200>;
-                                interrupts = <7 4>;
+                                interrupts = <7 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -180,21 +181,21 @@
                         macb0: ethernet@f802c000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xf802c000 0x100>;
-                                interrupts = <24 4>;
+                                interrupts = <24 4 3>;
                                 status = "disabled";
                         };
 
                         macb1: ethernet@f8030000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xf8030000 0x100>;
-                                interrupts = <27 4>;
+                                interrupts = <27 4 3>;
                                 status = "disabled";
                         };
 
                         adc0: adc@f804c000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xf804c000 0x100>;
-                                interrupts = <19 4>;
+                                interrupts = <19 4 0>;
                                 atmel,adc-use-external;
                                 atmel,adc-channels-used = <0xffff>;
                                 atmel,adc-vref = <3300>;
@@ -248,14 +249,14 @@
                 usb0: ohci@00600000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00600000 0x100000>;
-                        interrupts = <22 4>;
+                        interrupts = <22 4 2>;
                         status = "disabled";
                 };
 
                 usb1: ehci@00700000 {
                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                         reg = <0x00700000 0x100000>;
-                        interrupts = <22 4>;
+                        interrupts = <22 4 2>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 4ad5160018c..3180a9c588b 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -48,7 +48,7 @@
                 };
 
                 rtc@80154000 {
-                        compatible = "stericsson,db8500-rtc";
+                        compatible = "arm,rtc-pl031", "arm,primecell";
                         reg = <0x80154000 0x1000>;
                         interrupts = <0 18 0x4>;
                 };
@@ -60,7 +60,7 @@
                         interrupts = <0 119 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <0>;
@@ -73,7 +73,7 @@
                         interrupts = <0 120 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <1>;
@@ -86,7 +86,7 @@
                         interrupts = <0 121 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <2>;
@@ -99,7 +99,7 @@
                         interrupts = <0 122 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <3>;
@@ -112,7 +112,7 @@
                         interrupts = <0 123 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <4>;
@@ -125,7 +125,7 @@
                         interrupts = <0 124 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <5>;
@@ -138,7 +138,7 @@
                         interrupts = <0 125 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <6>;
@@ -151,7 +151,7 @@
                         interrupts = <0 126 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <7>;
@@ -164,7 +164,7 @@
                         interrupts = <0 127 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <8>;
@@ -206,62 +206,74 @@
 
                                 // DB8500_REGULATOR_VAPE
                                 db8500_vape_reg: db8500_vape {
+                                        regulator-compatible = "db8500_vape";
                                         regulator-name = "db8500-vape";
                                         regulator-always-on;
                                 };
 
                                 // DB8500_REGULATOR_VARM
                                 db8500_varm_reg: db8500_varm {
+                                        regulator-compatible = "db8500_varm";
                                         regulator-name = "db8500-varm";
                                 };
 
                                 // DB8500_REGULATOR_VMODEM
                                 db8500_vmodem_reg: db8500_vmodem {
+                                        regulator-compatible = "db8500_vmodem";
                                         regulator-name = "db8500-vmodem";
                                 };
 
                                 // DB8500_REGULATOR_VPLL
                                 db8500_vpll_reg: db8500_vpll {
+                                        regulator-compatible = "db8500_vpll";
                                         regulator-name = "db8500-vpll";
                                 };
 
                                 // DB8500_REGULATOR_VSMPS1
                                 db8500_vsmps1_reg: db8500_vsmps1 {
+                                        regulator-compatible = "db8500_vsmps1";
                                         regulator-name = "db8500-vsmps1";
                                 };
 
                                 // DB8500_REGULATOR_VSMPS2
                                 db8500_vsmps2_reg: db8500_vsmps2 {
+                                        regulator-compatible = "db8500_vsmps2";
                                         regulator-name = "db8500-vsmps2";
                                 };
 
                                 // DB8500_REGULATOR_VSMPS3
                                 db8500_vsmps3_reg: db8500_vsmps3 {
+                                        regulator-compatible = "db8500_vsmps3";
                                         regulator-name = "db8500-vsmps3";
                                 };
 
                                 // DB8500_REGULATOR_VRF1
                                 db8500_vrf1_reg: db8500_vrf1 {
+                                        regulator-compatible = "db8500_vrf1";
                                         regulator-name = "db8500-vrf1";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_SVAMMDSP
                                 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
+                                        regulator-compatible = "db8500_sva_mmdsp";
                                         regulator-name = "db8500-sva-mmdsp";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
                                 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
+                                        regulator-compatible = "db8500_sva_mmdsp_ret";
                                         regulator-name = "db8500-sva-mmdsp-ret";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_SVAPIPE
                                 db8500_sva_pipe_reg: db8500_sva_pipe {
+                                        regulator-compatible = "db8500_sva_pipe";
                                         regulator-name = "db8500_sva_pipe";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_SIAMMDSP
                                 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
+                                        regulator-compatible = "db8500_sia_mmdsp";
                                         regulator-name = "db8500_sia_mmdsp";
                                 };
 
@@ -272,38 +284,45 @@
 
                                 // DB8500_REGULATOR_SWITCH_SIAPIPE
                                 db8500_sia_pipe_reg: db8500_sia_pipe {
+                                        regulator-compatible = "db8500_sia_pipe";
                                         regulator-name = "db8500-sia-pipe";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_SGA
                                 db8500_sga_reg: db8500_sga {
+                                        regulator-compatible = "db8500_sga";
                                         regulator-name = "db8500-sga";
                                         vin-supply = <&db8500_vape_reg>;
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
                                 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
+                                        regulator-compatible = "db8500_b2r2_mcde";
                                         regulator-name = "db8500-b2r2-mcde";
                                         vin-supply = <&db8500_vape_reg>;
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_ESRAM12
                                 db8500_esram12_reg: db8500_esram12 {
+                                        regulator-compatible = "db8500_esram12";
                                         regulator-name = "db8500-esram12";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_ESRAM12RET
                                 db8500_esram12_ret_reg: db8500_esram12_ret {
+                                        regulator-compatible = "db8500_esram12_ret";
                                         regulator-name = "db8500-esram12-ret";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_ESRAM34
                                 db8500_esram34_reg: db8500_esram34 {
+                                        regulator-compatible = "db8500_esram34";
                                         regulator-name = "db8500-esram34";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_ESRAM34RET
                                 db8500_esram34_ret_reg: db8500_esram34_ret {
+                                        regulator-compatible = "db8500_esram34_ret";
                                         regulator-name = "db8500-esram34-ret";
                                 };
                         };
@@ -312,12 +331,70 @@
                                 compatible = "stericsson,ab8500";
                                 reg = <5>; /* mailbox 5 is i2c */
                                 interrupts = <0 40 0x4>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+
+                                ab8500-rtc {
+                                        compatible = "stericsson,ab8500-rtc";
+                                        interrupts = <17 0x4
+                                                      18 0x4>;
+                                        interrupt-names = "60S", "ALARM";
+                                };
+
+                                ab8500-gpadc {
+                                        compatible = "stericsson,ab8500-gpadc";
+                                        interrupts = <32 0x4
+                                                      39 0x4>;
+                                        interrupt-names = "HW_CONV_END", "SW_CONV_END";
+                                        vddadc-supply = <&ab8500_ldo_tvout_reg>;
+                                };
+
+                                ab8500-usb {
+                                        compatible = "stericsson,ab8500-usb";
+                                        interrupts = < 90 0x4
+                                                       96 0x4
+                                                       14 0x4
+                                                       15 0x4
+                                                       79 0x4
+                                                       74 0x4
+                                                       75 0x4>;
+                                        interrupt-names = "ID_WAKEUP_R",
+                                                          "ID_WAKEUP_F",
+                                                          "VBUS_DET_F",
+                                                          "VBUS_DET_R",
+                                                          "USB_LINK_STATUS",
+                                                          "USB_ADP_PROBE_PLUG",
+                                                          "USB_ADP_PROBE_UNPLUG";
+                                        vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
+                                        v-ape-supply = <&db8500_vape_reg>;
+                                        musb_1v8-supply = <&db8500_vsmps2_reg>;
+                                };
+
+                                ab8500-ponkey {
+                                        compatible = "stericsson,ab8500-ponkey";
+                                        interrupts = <6 0x4
+                                                      7 0x4>;
+                                        interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
+                                };
+
+                                ab8500-sysctrl {
+                                        compatible = "stericsson,ab8500-sysctrl";
+                                };
+
+                                ab8500-pwm {
+                                        compatible = "stericsson,ab8500-pwm";
+                                };
+
+                                ab8500-debugfs {
+                                        compatible = "stericsson,ab8500-debug";
+                                };
 
                                 ab8500-regulators {
                                         compatible = "stericsson,ab8500-regulator";
 
                                         // supplies to the display/camera
                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+                                                regulator-compatible = "ab8500_ldo_aux1";
                                                 regulator-name = "V-DISPLAY";
                                                 regulator-min-microvolt = <2500000>;
                                                 regulator-max-microvolt = <2900000>;
@@ -328,6 +405,7 @@
 
                                         // supplies to the on-board eMMC
                                         ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+                                                regulator-compatible = "ab8500_ldo_aux2";
                                                 regulator-name = "V-eMMC1";
                                                 regulator-min-microvolt = <1100000>;
                                                 regulator-max-microvolt = <3300000>;
@@ -335,6 +413,7 @@
 
                                         // supply for VAUX3; SDcard slots
                                         ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+                                                regulator-compatible = "ab8500_ldo_aux3";
                                                 regulator-name = "V-MMC-SD";
                                                 regulator-min-microvolt = <1100000>;
                                                 regulator-max-microvolt = <3300000>;
@@ -342,41 +421,49 @@
 
                                         // supply for v-intcore12; VINTCORE12 LDO
                                         ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                                regulator-compatible = "ab8500_ldo_initcore";
                                                 regulator-name = "V-INTCORE";
                                         };
 
                                         // supply for tvout; gpadc; TVOUT LDO
                                         ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
+                                                regulator-compatible = "ab8500_ldo_tvout";
                                                 regulator-name = "V-TVOUT";
                                         };
 
                                         // supply for ab8500-usb; USB LDO
                                         ab8500_ldo_usb_reg: ab8500_ldo_usb {
+                                                regulator-compatible = "ab8500_ldo_usb";
                                                 regulator-name = "dummy";
                                         };
 
                                         // supply for ab8500-vaudio; VAUDIO LDO
                                         ab8500_ldo_audio_reg: ab8500_ldo_audio {
+                                                regulator-compatible = "ab8500_ldo_audio";
                                                 regulator-name = "V-AUD";
                                         };
 
                                         // supply for v-anamic1 VAMic1-LDO
                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
+                                                regulator-compatible = "ab8500_ldo_anamic1";
                                                 regulator-name = "V-AMIC1";
                                         };
 
                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
                                         ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                                regulator-compatible = "ab8500_ldo_amamic2";
                                                 regulator-name = "V-AMIC2";
                                         };
 
                                         // supply for v-dmic; VDMIC LDO
                                         ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
+                                                regulator-compatible = "ab8500_ldo_dmic";
                                                 regulator-name = "V-DMIC";
                                         };
 
                                         // supply for U8500 CSI/DSI; VANA LDO
                                         ab8500_ldo_ana_reg: ab8500_ldo_ana {
+                                                regulator-compatible = "ab8500_ldo_ana";
                                                 regulator-name = "V-CSI/DSI";
                                         };
                                 };
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts
new file mode 100644
index 00000000000..d79b28d9c96
--- /dev/null
+++ b/arch/arm/boot/dts/ea3250.dts
@@ -0,0 +1,174 @@
+/*
+ * Embedded Artists LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "lpc32xx.dtsi"
+
+/ {
+        model = "Embedded Artists LPC3250 board based on NXP LPC3250";
+        compatible = "ea,ea3250", "nxp,lpc3250";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x4000000>;
+        };
+
+        ahb {
+                mac: ethernet@31060000 {
+                        phy-mode = "rmii";
+                        use-iram;
+                };
+
+                /* Here, choose exactly one from: ohci, usbd */
+                ohci@31020000 {
+                        transceiver = <&isp1301>;
+                        status = "okay";
+                };
+
+/*
+                usbd@31020000 {
+                        transceiver = <&isp1301>;
+                        status = "okay";
+                };
+*/
+
+                /* 128MB Flash via SLC NAND controller */
+                slc: flash@20020000 {
+                        status = "okay";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        nxp,wdr-clks = <14>;
+                        nxp,wwidth = <260000000>;
+                        nxp,whold = <104000000>;
+                        nxp,wsetup = <200000000>;
+                        nxp,rdr-clks = <14>;
+                        nxp,rwidth = <34666666>;
+                        nxp,rhold = <104000000>;
+                        nxp,rsetup = <200000000>;
+                        nand-on-flash-bbt;
+                        gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
+                        mtd0@00000000 {
+                                label = "ea3250-boot";
+                                reg = <0x00000000 0x00080000>;
+                                read-only;
+                        };
+
+                        mtd1@00080000 {
+                                label = "ea3250-uboot";
+                                reg = <0x00080000 0x000c0000>;
+                                read-only;
+                        };
+
+                        mtd2@00140000 {
+                                label = "ea3250-kernel";
+                                reg = <0x00140000 0x00400000>;
+                        };
+
+                        mtd3@00540000 {
+                                label = "ea3250-rootfs";
+                                reg = <0x00540000 0x07ac0000>;
+                        };
+                };
+
+                apb {
+                        uart5: serial@40090000 {
+                                status = "okay";
+                        };
+
+                        uart3: serial@40080000 {
+                                status = "okay";
+                        };
+
+                        uart6: serial@40098000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@400A0000 {
+                                clock-frequency = <100000>;
+
+                                eeprom@50 {
+                                        compatible = "at,24c256";
+                                        reg = <0x50>;
+                                };
+
+                                eeprom@57 {
+                                        compatible = "at,24c64";
+                                        reg = <0x57>;
+                                };
+
+                                uda1380: uda1380@18 {
+                                        compatible = "nxp,uda1380";
+                                        reg = <0x18>;
+                                        power-gpio = <&gpio 0x59 0>;
+                                        reset-gpio = <&gpio 0x51 0>;
+                                        dac-clk = "wspll";
+                                };
+
+                                pca9532: pca9532@60 {
+                                        compatible = "nxp,pca9532";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <0x60>;
+                                };
+                        };
+
+                        i2c2: i2c@400A8000 {
+                                clock-frequency = <100000>;
+                        };
+
+                        i2cusb: i2c@31020300 {
+                                clock-frequency = <100000>;
+
+                                isp1301: usb-transceiver@2d {
+                                        compatible = "nxp,isp1301";
+                                        reg = <0x2d>;
+                                };
+                        };
+
+                        sd@20098000 {
+                                wp-gpios = <&pca9532 5 0>;
+                                cd-gpios = <&pca9532 4 0>;
+                                cd-inverted;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+                };
+
+                fab {
+                        uart1: serial@40014000 {
+                                status = "okay";
+                        };
+
+                        /* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
+                        adc@40048000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                button@21 {
+                        label = "GPIO Key UP";
+                        linux,code = <103>;
+                        gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
new file mode 100644
index 00000000000..b7354e6506d
--- /dev/null
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -0,0 +1,41 @@
+/*
+ * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3
+ *
+ * Copyright (C) 2012 Telit,
+ *               2012 Fabio Porcedda <fabio.porcedda@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "ge863-pro3.dtsi"
+
+/ {
+        model = "Telit EVK-PRO3 for Telit GE863-PRO3";
+        compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 0>;
+                                status = "okay";
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+        };
+
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index b8c476384ee..0c49caa0997 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -134,4 +134,16 @@
         i2c@138D0000 {
                 status = "disabled";
         };
+
+        spi_0: spi@13920000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@13930000 {
+                status = "disabled";
+        };
+
+        spi_2: spi@13940000 {
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 27afc8e535c..1beccc8f14f 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -179,4 +179,42 @@
         i2c@138D0000 {
                 status = "disabled";
         };
+
+        spi_0: spi@13920000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@13930000 {
+                status = "disabled";
+        };
+
+        spi_2: spi@13940000 {
+                gpios = <&gpc1 1 5 3 0>,
+                        <&gpc1 3 5 3 0>,
+                        <&gpc1 4 5 3 0>;
+
+                w25x80@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "w25x80";
+                        reg = <0>;
+                        spi-max-frequency = <1000000>;
+
+                        controller-data {
+                                cs-gpio = <&gpc1 2 1 0 3>;
+                                samsung,spi-feedback-delay = <0>;
+                        };
+
+                        partition@0 {
+                                label = "U-Boot";
+                                reg = <0x0 0x40000>;
+                                read-only;
+                        };
+
+                        partition@40000 {
+                                label = "Kernel";
+                                reg = <0x40000 0xc0000>;
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index a1dd2ee8375..02891fe876e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -25,6 +25,12 @@
         compatible = "samsung,exynos4210";
         interrupt-parent = <&gic>;
 
+        aliases {
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                spi2 = &spi_2;
+        };
+
         gic:interrupt-controller@10490000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -33,6 +39,17 @@
                 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
         };
 
+        combiner:interrupt-controller@10440000 {
+                compatible = "samsung,exynos4210-combiner";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0x10440000 0x1000>;
+                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+        };
+
         watchdog@10060000 {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x10060000 0x100>;
@@ -147,6 +164,36 @@
                 interrupts = <0 65 0>;
         };
 
+        spi_0: spi@13920000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13920000 0x100>;
+                interrupts = <0 66 0>;
+                tx-dma-channel = <&pdma0 7>; /* preliminary */
+                rx-dma-channel = <&pdma0 6>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        spi_1: spi@13930000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13930000 0x100>;
+                interrupts = <0 67 0>;
+                tx-dma-channel = <&pdma1 7>; /* preliminary */
+                rx-dma-channel = <&pdma1 6>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        spi_2: spi@13940000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13940000 0x100>;
+                interrupts = <0 68 0>;
+                tx-dma-channel = <&pdma0 9>; /* preliminary */
+                rx-dma-channel = <&pdma0 8>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49945cc1bc7..8a5e348793c 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -71,4 +71,42 @@
         i2c@12CD0000 {
                 status = "disabled";
         };
+
+        spi_0: spi@12d20000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@12d30000 {
+                gpios = <&gpa2 4 2 3 0>,
+                        <&gpa2 6 2 3 0>,
+                        <&gpa2 7 2 3 0>;
+
+                w25q80bw@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "w25x80";
+                        reg = <0>;
+                        spi-max-frequency = <1000000>;
+
+                        controller-data {
+                                cs-gpio = <&gpa2 5 1 0 3>;
+                                samsung,spi-feedback-delay = <0>;
+                        };
+
+                        partition@0 {
+                                label = "U-Boot";
+                                reg = <0x0 0x40000>;
+                                read-only;
+                        };
+
+                        partition@40000 {
+                                label = "Kernel";
+                                reg = <0x40000 0xc0000>;
+                        };
+                };
+        };
+
+        spi_2: spi@12d40000 {
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 4272b294922..004aaa8d123 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,6 +23,12 @@
         compatible = "samsung,exynos5250";
         interrupt-parent = <&gic>;
 
+        aliases {
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                spi2 = &spi_2;
+        };
+
         gic:interrupt-controller@10481000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -146,6 +152,36 @@
                 #size-cells = <0>;
         };
 
+        spi_0: spi@12d20000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d20000 0x100>;
+                interrupts = <0 66 0>;
+                tx-dma-channel = <&pdma0 5>; /* preliminary */
+                rx-dma-channel = <&pdma0 4>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        spi_1: spi@12d30000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d30000 0x100>;
+                interrupts = <0 67 0>;
+                tx-dma-channel = <&pdma1 5>; /* preliminary */
+                rx-dma-channel = <&pdma1 4>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        spi_2: spi@12d40000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d40000 0x100>;
+                interrupts = <0 68 0>;
+                tx-dma-channel = <&pdma0 7>; /* preliminary */
+                rx-dma-channel = <&pdma0 6>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
new file mode 100644
index 00000000000..17136fc7a51
--- /dev/null
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -0,0 +1,52 @@
+/*
+ * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3
+ *
+ * Copyright (C) 2012 Telit,
+ *               2012 Fabio Porcedda <fabio.porcedda@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "at91sam9260.dtsi"
+
+/ {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <6000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        boot@0 {
+                                label = "boot";
+                                reg = <0x0 0x7c0000>;
+                        };
+
+                        root@07c0000 {
+                                label = "root";
+                                reg = <0x7c0000 0x7840000>;
+                        };
+                };
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs";
+        };
+};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 83e72294aef..9fecf1ae777 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2011 Calxeda, Inc.
+ * Copyright 2011-2012 Calxeda, Inc.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -24,6 +24,7 @@
         compatible = "calxeda,highbank";
         #address-cells = <1>;
         #size-cells = <1>;
+        clock-ranges;
 
         cpus {
                 #address-cells = <1>;
@@ -33,24 +34,32 @@
                         compatible = "arm,cortex-a9";
                         reg = <0>;
                         next-level-cache = <&L2>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
                 };
 
                 cpu@1 {
                         compatible = "arm,cortex-a9";
                         reg = <1>;
                         next-level-cache = <&L2>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
                 };
 
                 cpu@2 {
                         compatible = "arm,cortex-a9";
                         reg = <2>;
                         next-level-cache = <&L2>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
                 };
 
                 cpu@3 {
                         compatible = "arm,cortex-a9";
                         reg = <3>;
                         next-level-cache = <&L2>;
+                        clocks = <&a9pll>;
+                        clock-names = "cpu";
                 };
         };
 
@@ -75,12 +84,14 @@
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = <0xfff10600 0x20>;
                         interrupts = <1 13 0xf01>;
+                        clocks = <&a9periphclk>;
                 };
 
                 watchdog@fff10620 {
                         compatible = "arm,cortex-a9-twd-wdt";
                         reg = <0xfff10620 0x20>;
                         interrupts = <1 14 0xf01>;
+                        clocks = <&a9periphclk>;
                 };
 
                 intc: interrupt-controller@fff11000 {
@@ -116,12 +127,21 @@
                         compatible = "calxeda,hb-sdhci";
                         reg = <0xffe0e000 0x1000>;
                         interrupts = <0 90 4>;
+                        clocks = <&eclk>;
+                };
+
+                memory-controller@fff00000 {
+                        compatible = "calxeda,hb-ddr-ctrl";
+                        reg = <0xfff00000 0x1000>;
+                        interrupts = <0 91 4>;
                 };
 
                 ipc@fff20000 {
                         compatible = "arm,pl320", "arm,primecell";
                         reg = <0xfff20000 0x1000>;
                         interrupts = <0 7 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 gpioe: gpio@fff30000 {
@@ -130,6 +150,8 @@
                         gpio-controller;
                         reg = <0xfff30000 0x1000>;
                         interrupts = <0 14 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 gpiof: gpio@fff31000 {
@@ -138,6 +160,8 @@
                         gpio-controller;
                         reg = <0xfff31000 0x1000>;
                         interrupts = <0 15 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 gpiog: gpio@fff32000 {
@@ -146,6 +170,8 @@
                         gpio-controller;
                         reg = <0xfff32000 0x1000>;
                         interrupts = <0 16 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 gpioh: gpio@fff33000 {
@@ -154,24 +180,32 @@
                         gpio-controller;
                         reg = <0xfff33000 0x1000>;
                         interrupts = <0 17 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 timer {
                         compatible = "arm,sp804", "arm,primecell";
                         reg = <0xfff34000 0x1000>;
                         interrupts = <0 18 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 rtc@fff35000 {
                         compatible = "arm,pl031", "arm,primecell";
                         reg = <0xfff35000 0x1000>;
                         interrupts = <0 19 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 serial@fff36000 {
                         compatible = "arm,pl011", "arm,primecell";
                         reg = <0xfff36000 0x1000>;
                         interrupts = <0 20 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 smic@fff3a000 {
@@ -186,12 +220,79 @@
                 sregs@fff3c000 {
                         compatible = "calxeda,hb-sregs";
                         reg = <0xfff3c000 0x1000>;
+
+                        clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                osc: oscillator {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <33333000>;
+                                };
+
+                                ddrpll: ddrpll {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-pll-clock";
+                                        clocks = <&osc>;
+                                        reg = <0x108>;
+                                };
+
+                                a9pll: a9pll {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-pll-clock";
+                                        clocks = <&osc>;
+                                        reg = <0x100>;
+                                };
+
+                                a9periphclk: a9periphclk {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-a9periph-clock";
+                                        clocks = <&a9pll>;
+                                        reg = <0x104>;
+                                };
+
+                                a9bclk: a9bclk {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-a9bus-clock";
+                                        clocks = <&a9pll>;
+                                        reg = <0x104>;
+                                };
+
+                                emmcpll: emmcpll {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-pll-clock";
+                                        clocks = <&osc>;
+                                        reg = <0x10C>;
+                                };
+
+                                eclk: eclk {
+                                        #clock-cells = <0>;
+                                        compatible = "calxeda,hb-emmc-clock";
+                                        clocks = <&emmcpll>;
+                                        reg = <0x114>;
+                                };
+
+                                pclk: pclk {
+                                        #clock-cells = <0>;
+                                        compatible = "fixed-clock";
+                                        clock-frequency = <150000000>;
+                                };
+                        };
+                };
+
+                sregs@fff3c200 {
+                        compatible = "calxeda,hb-sregs-l2-ecc";
+                        reg = <0xfff3c200 0x100>;
+                        interrupts = <0 71 4  0 72 4>;
                 };
 
                 dma@fff3d000 {
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0xfff3d000 0x1000>;
                         interrupts = <0 92 4>;
+                        clocks = <&pclk>;
+                        clock-names = "apb_pclk";
                 };
 
                 ethernet@fff50000 {
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 70bffa929b6..e3486f486b4 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -22,17 +22,60 @@
 
         apb@80000000 {
                 apbh@80000000 {
+                        gpmi-nand@8000c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;
+                                status = "okay";
+                        };
+
                         ssp0: ssp@80010000 {
                                 compatible = "fsl,imx23-mmc";
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&mmc0_8bit_pins_a &mmc0_pins_fixup>;
-                                bus-width = <8>;
+                                pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+                                bus-width = <4>;
                                 wp-gpios = <&gpio1 30 0>;
+                                vmmc-supply = <&reg_vddio_sd0>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
+                                                0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
+                                                0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_24bit_pins_a>;
+                                panel-enable-gpios = <&gpio1 18 0>;
                                 status = "okay";
                         };
                 };
 
                 apbx@80040000 {
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm2_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+
                         duart: serial@80070000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&duart_pins_a>;
@@ -40,4 +83,23 @@
                         };
                 };
         };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_vddio_sd0: vddio-sd0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "vddio-sd0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio1 29 0>;
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 2 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
new file mode 100644
index 00000000000..20912b1d889
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx23.dtsi"
+
+/ {
+        model = "i.MX23 Olinuxino Low Cost Board";
+        compatible = "olimex,imx23-olinuxino", "fsl,imx23";
+
+        memory {
+                reg = <0x40000000 0x04000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx23-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+                };
+
+                apbx@80040000 {
+                        duart: serial@80070000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
new file mode 100644
index 00000000000..757a327ff3e
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx23.dtsi"
+
+/ {
+        model = "Freescale STMP378x Development Board";
+        compatible = "fsl,stmp378x-devb", "fsl,imx23";
+
+        memory {
+                reg = <0x40000000 0x04000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx23-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+                                bus-width = <4>;
+                                wp-gpios = <&gpio1 30 0>;
+                                vmmc-supply = <&reg_vddio_sd0>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
+                                                0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        auart0: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+
+                        duart: serial@80070000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_vddio_sd0: vddio-sd0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "vddio-sd0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio1 29 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 8c5f9994f3f..e6138310e5c 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -18,6 +18,8 @@
                 gpio0 = &gpio0;
                 gpio1 = &gpio1;
                 gpio2 = &gpio2;
+                serial0 = &auart0;
+                serial1 = &auart1;
         };
 
         cpus {
@@ -49,33 +51,35 @@
 
                         dma-apbh@80004000 {
                                 compatible = "fsl,imx23-dma-apbh";
-                                reg = <0x80004000 2000>;
+                                reg = <0x80004000 0x2000>;
                         };
 
                         ecc@80008000 {
-                                reg = <0x80008000 2000>;
+                                reg = <0x80008000 0x2000>;
                                 status = "disabled";
                         };
 
-                        bch@8000a000 {
-                                reg = <0x8000a000 2000>;
-                                status = "disabled";
-                        };
-
-                        gpmi@8000c000 {
-                                reg = <0x8000c000 2000>;
+                        gpmi-nand@8000c000 {
+                                compatible = "fsl,imx23-gpmi-nand";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
+                                reg-names = "gpmi-nand", "bch";
+                                interrupts = <13>, <56>;
+                                interrupt-names = "gpmi-dma", "bch";
+                                fsl,gpmi-dma-channel = <4>;
                                 status = "disabled";
                         };
 
                         ssp0: ssp@80010000 {
-                                reg = <0x80010000 2000>;
+                                reg = <0x80010000 0x2000>;
                                 interrupts = <15 14>;
                                 fsl,ssp-dma-channel = <1>;
                                 status = "disabled";
                         };
 
                         etm@80014000 {
-                                reg = <0x80014000 2000>;
+                                reg = <0x80014000 0x2000>;
                                 status = "disabled";
                         };
 
@@ -83,7 +87,7 @@
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx23-pinctrl", "simple-bus";
-                                reg = <0x80018000 2000>;
+                                reg = <0x80018000 0x2000>;
 
                                 gpio0: gpio@0 {
                                         compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
@@ -114,24 +118,151 @@
 
                                 duart_pins_a: duart@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x11a2 0x11b2>;
+                                        fsl,pinmux-ids = <
+                                                0x11a2 /* MX23_PAD_PWM0__DUART_RX */
+                                                0x11b2 /* MX23_PAD_PWM1__DUART_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart0_pins_a: auart0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
+                                                0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
+                                                0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
+                                                0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
+                                        >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
 
+                                gpmi_pins_a: gpmi-nand@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
+                                                0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
+                                                0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
+                                                0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
+                                                0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
+                                                0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
+                                                0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
+                                                0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
+                                                0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
+                                                0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
+                                                0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
+                                                0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
+                                                0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
+                                                0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
+                                                0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
+                                                0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
+                                                0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                gpmi_pins_fixup: gpmi-pins-fixup {
+                                        fsl,pinmux-ids = <
+                                                0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
+                                                0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
+                                                0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                };
+
+                                mmc0_4bit_pins_a: mmc0-4bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
+                                                0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
+                                                0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
+                                                0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
+                                                0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
+                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
+                                                0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
                                 mmc0_8bit_pins_a: mmc0-8bit@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x2020 0x2030 0x2040
-                                                0x2050 0x0082 0x0092 0x00a2
-                                                0x00b2 0x2000 0x2010 0x2060>;
+                                        fsl,pinmux-ids = <
+                                                0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
+                                                0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
+                                                0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
+                                                0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
+                                                0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
+                                                0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
+                                                0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
+                                                0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
+                                                0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
+                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
+                                                0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
+                                        >;
                                         fsl,drive-strength = <1>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
                                 };
 
                                 mmc0_pins_fixup: mmc0-pins-fixup {
-                                        fsl,pinmux-ids = <0x2010 0x2060>;
+                                        fsl,pinmux-ids = <
+                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
+                                                0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
+                                        >;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                pwm2_pins_a: pwm2@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x11c0 /* MX23_PAD_PWM2__PWM2 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_24bit_pins_a: lcdif-24bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
+                                                0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
+                                                0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
+                                                0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
+                                                0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
+                                                0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
+                                                0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
+                                                0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
+                                                0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
+                                                0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
+                                                0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
                         };
@@ -142,49 +273,51 @@
                         };
 
                         emi@80020000 {
-                                reg = <0x80020000 2000>;
+                                reg = <0x80020000 0x2000>;
                                 status = "disabled";
                         };
 
                         dma-apbx@80024000 {
                                 compatible = "fsl,imx23-dma-apbx";
-                                reg = <0x80024000 2000>;
+                                reg = <0x80024000 0x2000>;
                         };
 
                         dcp@80028000 {
-                                reg = <0x80028000 2000>;
+                                reg = <0x80028000 0x2000>;
                                 status = "disabled";
                         };
 
                         pxp@8002a000 {
-                                reg = <0x8002a000 2000>;
+                                reg = <0x8002a000 0x2000>;
                                 status = "disabled";
                         };
 
                         ocotp@8002c000 {
-                                reg = <0x8002c000 2000>;
+                                reg = <0x8002c000 0x2000>;
                                 status = "disabled";
                         };
 
                         axi-ahb@8002e000 {
-                                reg = <0x8002e000 2000>;
+                                reg = <0x8002e000 0x2000>;
                                 status = "disabled";
                         };
 
                         lcdif@80030000 {
+                                compatible = "fsl,imx23-lcdif";
                                 reg = <0x80030000 2000>;
+                                interrupts = <46 45>;
                                 status = "disabled";
                         };
 
                         ssp1: ssp@80034000 {
-                                reg = <0x80034000 2000>;
+                                reg = <0x80034000 0x2000>;
                                 interrupts = <2 20>;
                                 fsl,ssp-dma-channel = <2>;
                                 status = "disabled";
                         };
 
                         tvenc@80038000 {
-                                reg = <0x80038000 2000>;
+                                reg = <0x80038000 0x2000>;
                                 status = "disabled";
                         };
                 };
@@ -197,37 +330,37 @@
                         ranges;
 
                         clkctl@80040000 {
-                                reg = <0x80040000 2000>;
+                                reg = <0x80040000 0x2000>;
                                 status = "disabled";
                         };
 
                         saif0: saif@80042000 {
-                                reg = <0x80042000 2000>;
+                                reg = <0x80042000 0x2000>;
                                 status = "disabled";
                         };
 
                         power@80044000 {
-                                reg = <0x80044000 2000>;
+                                reg = <0x80044000 0x2000>;
                                 status = "disabled";
                         };
 
                         saif1: saif@80046000 {
-                                reg = <0x80046000 2000>;
+                                reg = <0x80046000 0x2000>;
                                 status = "disabled";
                         };
 
                         audio-out@80048000 {
-                                reg = <0x80048000 2000>;
+                                reg = <0x80048000 0x2000>;
                                 status = "disabled";
                         };
 
                         audio-in@8004c000 {
-                                reg = <0x8004c000 2000>;
+                                reg = <0x8004c000 0x2000>;
                                 status = "disabled";
                         };
 
                         lradc@80050000 {
-                                reg = <0x80050000 2000>;
+                                reg = <0x80050000 0x2000>;
                                 status = "disabled";
                         };
 
@@ -237,32 +370,40 @@
                         };
 
                         i2c@80058000 {
-                                reg = <0x80058000 2000>;
+                                reg = <0x80058000 0x2000>;
                                 status = "disabled";
                         };
 
                         rtc@8005c000 {
-                                reg = <0x8005c000 2000>;
-                                status = "disabled";
+                                compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
+                                reg = <0x8005c000 0x2000>;
+                                interrupts = <22>;
                         };
 
-                        pwm@80064000 {
-                                reg = <0x80064000 2000>;
+                        pwm: pwm@80064000 {
+                                compatible = "fsl,imx23-pwm";
+                                reg = <0x80064000 0x2000>;
+                                #pwm-cells = <2>;
+                                fsl,pwm-number = <5>;
                                 status = "disabled";
                         };
 
                         timrot@80068000 {
-                                reg = <0x80068000 2000>;
+                                reg = <0x80068000 0x2000>;
                                 status = "disabled";
                         };
 
                         auart0: serial@8006c000 {
+                                compatible = "fsl,imx23-auart";
                                 reg = <0x8006c000 0x2000>;
+                                interrupts = <24 25 23>;
                                 status = "disabled";
                         };
 
                         auart1: serial@8006e000 {
+                                compatible = "fsl,imx23-auart";
                                 reg = <0x8006e000 0x2000>;
+                                interrupts = <59 60 58>;
                                 status = "disabled";
                         };
 
@@ -288,7 +429,7 @@
                 ranges;
 
                 usbctrl@80080000 {
-                        reg = <0x80080000 0x10000>;
+                        reg = <0x80080000 0x40000>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts
new file mode 100644
index 00000000000..0a8978a40ec
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-3ds.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx27.dtsi"
+
+/ {
+        model = "mx27_3ds";
+        compatible = "freescale,imx27-3ds", "fsl,imx27";
+
+        memory {
+                reg = <0x0 0x0>;
+        };
+
+        soc {
+                aipi@10000000 { /* aipi */
+
+                        wdog@10002000 {
+                                status = "okay";
+                        };
+
+                        uart1: serial@1000a000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+
+                        fec@1002b000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 386c769c38d..5303ab680a3 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -19,6 +19,12 @@
                 serial3 = &uart4;
                 serial4 = &uart5;
                 serial5 = &uart6;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+                gpio5 = &gpio6;
         };
 
         avic: avic-interrupt-controller@e0000000 {
@@ -121,7 +127,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio2: gpio@10015100 {
@@ -131,7 +137,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio3: gpio@10015200 {
@@ -141,7 +147,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio4: gpio@10015300 {
@@ -151,7 +157,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio5: gpio@10015400 {
@@ -161,7 +167,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio6: gpio@10015500 {
@@ -171,7 +177,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         cspi3: cspi@10017000 {
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
new file mode 100644
index 00000000000..b383417a558
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -0,0 +1,198 @@
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+        model = "Bluegiga APX4 Development Kit";
+        compatible = "bluegiga,apx4devkit", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x04000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        gpmi-nand@8000c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+                                status = "okay";
+                        };
+
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+
+                        ssp2: ssp@80014000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
+                                                0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */
+                                                0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */
+                                                0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */
+                                                0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
+                                                0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_pins_apx4: lcdif-apx4@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */
+                                                0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */
+                                                0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */
+                                                0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */
+                                                0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */
+                                                0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 {
+                                        fsl,pinmux-ids = <
+                                                0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_24bit_pins_a
+                                             &lcdif_pins_apx4>;
+                                status = "okay";
+                        };
+                };
+
+                apbx@80040000 {
+                        saif0: saif@80042000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&saif0_pins_a>;
+                                status = "okay";
+                        };
+
+                        saif1: saif@80046000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&saif1_pins_a>;
+                                fsl,saif-master = <&saif0>;
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                status = "okay";
+
+                                sgtl5000: codec@0a {
+                                        compatible = "fsl,sgtl5000";
+                                        reg = <0x0a>;
+                                        VDDA-supply = <&reg_3p3v>;
+                                        VDDIO-supply = <&reg_3p3v>;
+
+                                };
+
+                                pcf8563: rtc@51 {
+                                        compatible = "phg,pcf8563";
+                                        reg = <0x51>;
+                                };
+                        };
+
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart1: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart1_2pins_a>;
+                                status = "okay";
+                        };
+
+                        auart2: serial@8006e000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart2_2pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+
+        sound {
+                compatible = "bluegiga,apx4devkit-sgtl5000",
+                             "fsl,mxs-audio-sgtl5000";
+                model = "apx4devkit-sgtl5000";
+                saif-controllers = <&saif0 &saif1>;
+                audio-codec = <&sgtl5000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio3 28 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
new file mode 100644
index 00000000000..c03a577beca
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+        model = "Crystalfontz CFA-10036 Board";
+        compatible = "crystalfontz,cfa10036", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a
+                                        &mmc0_cd_cfg &mmc0_sck_cfg>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+                };
+
+                apbx@80040000 {
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_b>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                power {
+                        gpios = <&gpio3 4 1>;
+                        default-state = "on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index ee520a529cb..773c0e84d1f 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -22,6 +22,13 @@
 
         apb@80000000 {
                 apbh@80000000 {
+                        gpmi-nand@8000c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg
+                                             &gpmi_pins_evk>;
+                                status = "okay";
+                        };
+
                         ssp0: ssp@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
@@ -29,6 +36,7 @@
                                         &mmc0_cd_cfg &mmc0_sck_cfg>;
                                 bus-width = <8>;
                                 wp-gpios = <&gpio2 12 0>;
+                                vmmc-supply = <&reg_vddio_sd0>;
                                 status = "okay";
                         };
 
@@ -36,6 +44,72 @@
                                 compatible = "fsl,imx28-mmc";
                                 bus-width = <8>;
                                 wp-gpios = <&gpio0 28 0>;
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
+                                                0x20f3 /* MX28_PAD_SSP1_DATA3__GPIO_2_15 */
+                                                0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13 */
+                                                0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */
+                                                0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
+                                                0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */
+                                                0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                gpmi_pins_evk: gpmi-nand-evk@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */
+                                                0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_pins_evk: lcdif-evk@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_24bit_pins_a
+                                             &lcdif_pins_evk>;
+                                panel-enable-gpios = <&gpio3 30 0>;
+                                status = "okay";
+                        };
+
+                        can0: can@80032000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can0_pins_a>;
+                                status = "okay";
+                        };
+
+                        can1: can@80034000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can1_pins_a>;
                                 status = "okay";
                         };
                 };
@@ -68,19 +142,58 @@
                                 };
                         };
 
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm2_pins_a>;
+                                status = "okay";
+                        };
+
                         duart: serial@80074000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&duart_pins_a>;
                                 status = "okay";
                         };
+
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart3: serial@80070000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart3_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
                 };
         };
 
         ahb@80080000 {
+                usb0: usb@80080000 {
+                        vbus-supply = <&reg_usb0_vbus>;
+                        status = "okay";
+                };
+
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        status = "okay";
+                };
+
                 mac0: ethernet@800f0000 {
                         phy-mode = "rmii";
                         pinctrl-names = "default";
                         pinctrl-0 = <&mac0_pins_a>;
+                        phy-supply = <&reg_fec_3v3>;
+                        phy-reset-gpios = <&gpio4 13 0>;
+                        phy-reset-duration = <100>;
                         status = "okay";
                 };
 
@@ -102,6 +215,40 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                reg_vddio_sd0: vddio-sd0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "vddio-sd0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio3 28 0>;
+                };
+
+                reg_fec_3v3: fec-3v3 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "fec-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio2 15 0>;
+                };
+
+                reg_usb0_vbus: usb0_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 9 0>;
+                        enable-active-high;
+                };
+
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 8 0>;
+                        enable-active-high;
+                };
         };
 
         sound {
@@ -111,4 +258,21 @@
                 saif-controllers = <&saif0 &saif1>;
                 audio-codec = <&sgtl5000>;
         };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio3 5 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 2 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
new file mode 100644
index 00000000000..183a3fd2d85
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+        model = "DENX M28EVK";
+        compatible = "denx,m28evk", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        gpmi-nand@8000c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+                                status = "okay";
+
+                                partition@0 {
+                                        label = "bootloader";
+                                        reg = <0x00000000 0x00300000>;
+                                        read-only;
+                                };
+
+                                partition@1 {
+                                        label = "environment";
+                                        reg = <0x00300000 0x00080000>;
+                                };
+
+                                partition@2 {
+                                        label = "redundant-environment";
+                                        reg = <0x00380000 0x00080000>;
+                                };
+
+                                partition@3 {
+                                        label = "kernel";
+                                        reg = <0x00400000 0x00400000>;
+                                };
+
+                                partition@4 {
+                                        label = "filesystem";
+                                        reg = <0x00800000 0x0f800000>;
+                                };
+                        };
+
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_8bit_pins_a
+                                             &mmc0_cd_cfg
+                                             &mmc0_sck_cfg>;
+                                bus-width = <8>;
+                                wp-gpios = <&gpio3 10 1>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
+                                                0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_pins_m28: lcdif-m28@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */
+                                                0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_24bit_pins_a
+                                             &lcdif_pins_m28>;
+                                status = "okay";
+                        };
+
+                        can0: can@80032000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can0_pins_a>;
+                                status = "okay";
+                        };
+
+                        can1: can@80034000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can1_pins_a>;
+                                status = "okay";
+                        };
+                };
+
+                apbx@80040000 {
+                        saif0: saif@80042000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&saif0_pins_a>;
+                                status = "okay";
+                        };
+
+                        saif1: saif@80046000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&saif1_pins_a>;
+                                fsl,saif-master = <&saif0>;
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                status = "okay";
+
+                                sgtl5000: codec@0a {
+                                        compatible = "fsl,sgtl5000";
+                                        reg = <0x0a>;
+                                        VDDA-supply = <&reg_3p3v>;
+                                        VDDIO-supply = <&reg_3p3v>;
+
+                                };
+
+                                eeprom: eeprom@51 {
+                                        compatible = "atmel,24c128";
+                                        reg = <0x51>;
+                                        pagesize = <32>;
+                                };
+
+                                rtc: rtc@68 {
+                                        compatible = "stm,mt41t62";
+                                        reg = <0x68>;
+                                };
+                        };
+
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_2pins_a>;
+                                status = "okay";
+                        };
+
+                        auart3: serial@80070000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart3_pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        phy-reset-gpios = <&gpio3 11 0>;
+                        status = "okay";
+                };
+
+                mac1: ethernet@800f4000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac1_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+
+        sound {
+                compatible = "denx,m28evk-sgtl5000",
+                             "fsl,mxs-audio-sgtl5000";
+                model = "m28evk-sgtl5000";
+                saif-controllers = <&saif0 &saif1>;
+                audio-codec = <&sgtl5000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
new file mode 100644
index 00000000000..62bf767409a
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -0,0 +1,97 @@
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+        model = "Ka-Ro electronics TX28 module";
+        compatible = "karo,tx28", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a
+                                             &mmc0_cd_cfg
+                                             &mmc0_sck_cfg>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                status = "okay";
+
+                                ds1339: rtc@68 {
+                                        compatible = "mxim,ds1339";
+                                        reg = <0x68>;
+                                };
+                        };
+
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm0_pins_a>;
+                                status = "okay";
+                        };
+
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_4pins_a>;
+                                status = "okay";
+                        };
+
+                        auart1: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart1_pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio4 10 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 4634cb861a5..3fa6d190fab 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -22,6 +22,11 @@
                 gpio4 = &gpio4;
                 saif0 = &saif0;
                 saif1 = &saif1;
+                serial0 = &auart0;
+                serial1 = &auart1;
+                serial2 = &auart2;
+                serial3 = &auart3;
+                serial4 = &auart4;
         };
 
         cpus {
@@ -52,57 +57,57 @@
                         };
 
                         hsadc@80002000 {
-                                reg = <0x80002000 2000>;
+                                reg = <0x80002000 0x2000>;
                                 interrupts = <13 87>;
                                 status = "disabled";
                         };
 
                         dma-apbh@80004000 {
                                 compatible = "fsl,imx28-dma-apbh";
-                                reg = <0x80004000 2000>;
+                                reg = <0x80004000 0x2000>;
                         };
 
                         perfmon@80006000 {
-                                reg = <0x80006000 800>;
+                                reg = <0x80006000 0x800>;
                                 interrupts = <27>;
                                 status = "disabled";
                         };
 
-                        bch@8000a000 {
-                                reg = <0x8000a000 2000>;
-                                interrupts = <41>;
-                                status = "disabled";
-                        };
-
-                        gpmi@8000c000 {
-                                reg = <0x8000c000 2000>;
-                                interrupts = <42 88>;
+                        gpmi-nand@8000c000 {
+                                compatible = "fsl,imx28-gpmi-nand";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
+                                reg-names = "gpmi-nand", "bch";
+                                interrupts = <88>, <41>;
+                                interrupt-names = "gpmi-dma", "bch";
+                                fsl,gpmi-dma-channel = <4>;
                                 status = "disabled";
                         };
 
                         ssp0: ssp@80010000 {
-                                reg = <0x80010000 2000>;
+                                reg = <0x80010000 0x2000>;
                                 interrupts = <96 82>;
                                 fsl,ssp-dma-channel = <0>;
                                 status = "disabled";
                         };
 
                         ssp1: ssp@80012000 {
-                                reg = <0x80012000 2000>;
+                                reg = <0x80012000 0x2000>;
                                 interrupts = <97 83>;
                                 fsl,ssp-dma-channel = <1>;
                                 status = "disabled";
                         };
 
                         ssp2: ssp@80014000 {
-                                reg = <0x80014000 2000>;
+                                reg = <0x80014000 0x2000>;
                                 interrupts = <98 84>;
                                 fsl,ssp-dma-channel = <2>;
                                 status = "disabled";
                         };
 
                         ssp3: ssp@80016000 {
-                                reg = <0x80016000 2000>;
+                                reg = <0x80016000 0x2000>;
                                 interrupts = <99 85>;
                                 fsl,ssp-dma-channel = <3>;
                                 status = "disabled";
@@ -112,7 +117,7 @@
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx28-pinctrl", "simple-bus";
-                                reg = <0x80018000 2000>;
+                                reg = <0x80018000 0x2000>;
 
                                 gpio0: gpio@0 {
                                         compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
@@ -161,7 +166,150 @@
 
                                 duart_pins_a: duart@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x3102 0x3112>;
+                                        fsl,pinmux-ids = <
+                                                0x3102 /* MX28_PAD_PWM0__DUART_RX */
+                                                0x3112 /* MX28_PAD_PWM1__DUART_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                duart_pins_b: duart@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
+                                                0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                duart_4pins_a: duart-4pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
+                                                0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
+                                                0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
+                                                0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                gpmi_pins_a: gpmi-nand@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
+                                                0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
+                                                0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
+                                                0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
+                                                0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
+                                                0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
+                                                0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
+                                                0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
+                                                0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
+                                                0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
+                                                0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
+                                                0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
+                                                0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
+                                                0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
+                                                0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                gpmi_status_cfg: gpmi-status-cfg {
+                                        fsl,pinmux-ids = <
+                                                0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
+                                                0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
+                                                0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                };
+
+                                auart0_pins_a: auart0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
+                                                0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
+                                                0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
+                                                0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart0_2pins_a: auart0-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
+                                                0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart1_pins_a: auart1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
+                                                0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
+                                                0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
+                                                0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart1_2pins_a: auart1-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
+                                                0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart2_2pins_a: auart2-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
+                                                0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart3_pins_a: auart3@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
+                                                0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
+                                                0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
+                                                0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart3_2pins_a: auart3-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
+                                                0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
+                                        >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
@@ -169,9 +317,17 @@
 
                                 mac0_pins_a: mac0@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x4000 0x4010 0x4020
-                                                0x4030 0x4040 0x4060 0x4070
-                                                0x4080 0x4100>;
+                                        fsl,pinmux-ids = <
+                                                0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
+                                                0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
+                                                0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
+                                                0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
+                                                0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
+                                                0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
+                                                0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
+                                                0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
+                                                0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
+                                        >;
                                         fsl,drive-strength = <1>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
@@ -179,8 +335,14 @@
 
                                 mac1_pins_a: mac1@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x40f1 0x4091 0x40a1
-                                                0x40e1 0x40b1 0x40c1>;
+                                        fsl,pinmux-ids = <
+                                                0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
+                                                0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
+                                                0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
+                                                0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
+                                                0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
+                                                0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
+                                        >;
                                         fsl,drive-strength = <1>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
@@ -188,28 +350,61 @@
 
                                 mmc0_8bit_pins_a: mmc0-8bit@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x2000 0x2010 0x2020
-                                                0x2030 0x2040 0x2050 0x2060
-                                                0x2070 0x2080 0x2090 0x20a0>;
+                                        fsl,pinmux-ids = <
+                                                0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
+                                                0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
+                                                0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
+                                                0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
+                                                0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
+                                                0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
+                                                0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
+                                                0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
+                                                0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
+                                                0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
+                                                0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                mmc0_4bit_pins_a: mmc0-4bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
+                                                0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
+                                                0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
+                                                0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
+                                                0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
+                                                0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
+                                                0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
+                                        >;
                                         fsl,drive-strength = <1>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
                                 };
 
                                 mmc0_cd_cfg: mmc0-cd-cfg {
-                                        fsl,pinmux-ids = <0x2090>;
+                                        fsl,pinmux-ids = <
+                                                0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
+                                        >;
                                         fsl,pull-up = <0>;
                                 };
 
                                 mmc0_sck_cfg: mmc0-sck-cfg {
-                                        fsl,pinmux-ids = <0x20a0>;
+                                        fsl,pinmux-ids = <
+                                                0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
+                                        >;
                                         fsl,drive-strength = <2>;
                                         fsl,pull-up = <0>;
                                 };
 
                                 i2c0_pins_a: i2c0@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x3180 0x3190>;
+                                        fsl,pinmux-ids = <
+                                                0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
+                                                0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
+                                        >;
                                         fsl,drive-strength = <1>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
@@ -217,8 +412,12 @@
 
                                 saif0_pins_a: saif0@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids =
-                                                <0x3140 0x3150 0x3160 0x3170>;
+                                        fsl,pinmux-ids = <
+                                                0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
+                                                0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
+                                                0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
+                                                0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
+                                        >;
                                         fsl,drive-strength = <2>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
@@ -226,101 +425,181 @@
 
                                 saif1_pins_a: saif1@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x31a0>;
+                                        fsl,pinmux-ids = <
+                                                0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
+                                        >;
                                         fsl,drive-strength = <2>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
                                 };
+
+                                pwm0_pins_a: pwm0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3100 /* MX28_PAD_PWM0__PWM_0 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                pwm2_pins_a: pwm2@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3120 /* MX28_PAD_PWM2__PWM_2 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_24bit_pins_a: lcdif-24bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
+                                                0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
+                                                0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
+                                                0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
+                                                0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
+                                                0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
+                                                0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                can0_pins_a: can0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
+                                                0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                can1_pins_a: can1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
+                                                0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                         };
 
                         digctl@8001c000 {
-                                reg = <0x8001c000 2000>;
+                                reg = <0x8001c000 0x2000>;
                                 interrupts = <89>;
                                 status = "disabled";
                         };
 
                         etm@80022000 {
-                                reg = <0x80022000 2000>;
+                                reg = <0x80022000 0x2000>;
                                 status = "disabled";
                         };
 
                         dma-apbx@80024000 {
                                 compatible = "fsl,imx28-dma-apbx";
-                                reg = <0x80024000 2000>;
+                                reg = <0x80024000 0x2000>;
                         };
 
                         dcp@80028000 {
-                                reg = <0x80028000 2000>;
+                                reg = <0x80028000 0x2000>;
                                 interrupts = <52 53 54>;
                                 status = "disabled";
                         };
 
                         pxp@8002a000 {
-                                reg = <0x8002a000 2000>;
+                                reg = <0x8002a000 0x2000>;
                                 interrupts = <39>;
                                 status = "disabled";
                         };
 
                         ocotp@8002c000 {
-                                reg = <0x8002c000 2000>;
+                                reg = <0x8002c000 0x2000>;
                                 status = "disabled";
                         };
 
                         axi-ahb@8002e000 {
-                                reg = <0x8002e000 2000>;
+                                reg = <0x8002e000 0x2000>;
                                 status = "disabled";
                         };
 
                         lcdif@80030000 {
-                                reg = <0x80030000 2000>;
+                                compatible = "fsl,imx28-lcdif";
+                                reg = <0x80030000 0x2000>;
                                 interrupts = <38 86>;
                                 status = "disabled";
                         };
 
                         can0: can@80032000 {
-                                reg = <0x80032000 2000>;
+                                compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x80032000 0x2000>;
                                 interrupts = <8>;
                                 status = "disabled";
                         };
 
                         can1: can@80034000 {
-                                reg = <0x80034000 2000>;
+                                compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
+                                reg = <0x80034000 0x2000>;
                                 interrupts = <9>;
                                 status = "disabled";
                         };
 
                         simdbg@8003c000 {
-                                reg = <0x8003c000 200>;
+                                reg = <0x8003c000 0x200>;
                                 status = "disabled";
                         };
 
                         simgpmisel@8003c200 {
-                                reg = <0x8003c200 100>;
+                                reg = <0x8003c200 0x100>;
                                 status = "disabled";
                         };
 
                         simsspsel@8003c300 {
-                                reg = <0x8003c300 100>;
+                                reg = <0x8003c300 0x100>;
                                 status = "disabled";
                         };
 
                         simmemsel@8003c400 {
-                                reg = <0x8003c400 100>;
+                                reg = <0x8003c400 0x100>;
                                 status = "disabled";
                         };
 
                         gpiomon@8003c500 {
-                                reg = <0x8003c500 100>;
+                                reg = <0x8003c500 0x100>;
                                 status = "disabled";
                         };
 
                         simenet@8003c700 {
-                                reg = <0x8003c700 100>;
+                                reg = <0x8003c700 0x100>;
                                 status = "disabled";
                         };
 
                         armjtag@8003c800 {
-                                reg = <0x8003c800 100>;
+                                reg = <0x8003c800 0x100>;
                                 status = "disabled";
                         };
                 };
@@ -333,54 +612,55 @@
                         ranges;
 
                         clkctl@80040000 {
-                                reg = <0x80040000 2000>;
+                                reg = <0x80040000 0x2000>;
                                 status = "disabled";
                         };
 
                         saif0: saif@80042000 {
                                 compatible = "fsl,imx28-saif";
-                                reg = <0x80042000 2000>;
+                                reg = <0x80042000 0x2000>;
                                 interrupts = <59 80>;
                                 fsl,saif-dma-channel = <4>;
                                 status = "disabled";
                         };
 
                         power@80044000 {
-                                reg = <0x80044000 2000>;
+                                reg = <0x80044000 0x2000>;
                                 status = "disabled";
                         };
 
                         saif1: saif@80046000 {
                                 compatible = "fsl,imx28-saif";
-                                reg = <0x80046000 2000>;
+                                reg = <0x80046000 0x2000>;
                                 interrupts = <58 81>;
                                 fsl,saif-dma-channel = <5>;
                                 status = "disabled";
                         };
 
                         lradc@80050000 {
-                                reg = <0x80050000 2000>;
+                                reg = <0x80050000 0x2000>;
                                 status = "disabled";
                         };
 
                         spdif@80054000 {
-                                reg = <0x80054000 2000>;
+                                reg = <0x80054000 0x2000>;
                                 interrupts = <45 66>;
                                 status = "disabled";
                         };
 
                         rtc@80056000 {
-                                reg = <0x80056000 2000>;
-                                interrupts = <28 29>;
-                                status = "disabled";
+                                compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
+                                reg = <0x80056000 0x2000>;
+                                interrupts = <29>;
                         };
 
                         i2c0: i2c@80058000 {
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx28-i2c";
-                                reg = <0x80058000 2000>;
+                                reg = <0x80058000 0x2000>;
                                 interrupts = <111 68>;
+                                clock-frequency = <100000>;
                                 status = "disabled";
                         };
 
@@ -388,46 +668,55 @@
                                 #address-cells = <1>;
                                 #size-cells = <0>;
                                 compatible = "fsl,imx28-i2c";
-                                reg = <0x8005a000 2000>;
+                                reg = <0x8005a000 0x2000>;
                                 interrupts = <110 69>;
+                                clock-frequency = <100000>;
                                 status = "disabled";
                         };
 
-                        pwm@80064000 {
-                                reg = <0x80064000 2000>;
+                        pwm: pwm@80064000 {
+                                compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
+                                reg = <0x80064000 0x2000>;
+                                #pwm-cells = <2>;
+                                fsl,pwm-number = <8>;
                                 status = "disabled";
                         };
 
                         timrot@80068000 {
-                                reg = <0x80068000 2000>;
+                                reg = <0x80068000 0x2000>;
                                 status = "disabled";
                         };
 
                         auart0: serial@8006a000 {
+                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006a000 0x2000>;
                                 interrupts = <112 70 71>;
                                 status = "disabled";
                         };
 
                         auart1: serial@8006c000 {
+                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006c000 0x2000>;
                                 interrupts = <113 72 73>;
                                 status = "disabled";
                         };
 
                         auart2: serial@8006e000 {
+                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006e000 0x2000>;
                                 interrupts = <114 74 75>;
                                 status = "disabled";
                         };
 
                         auart3: serial@80070000 {
+                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x80070000 0x2000>;
                                 interrupts = <115 76 77>;
                                 status = "disabled";
                         };
 
                         auart4: serial@80072000 {
+                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x80072000 0x2000>;
                                 interrupts = <116 78 79>;
                                 status = "disabled";
@@ -441,11 +730,13 @@
                         };
 
                         usbphy0: usbphy@8007c000 {
+                                compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x8007c000 0x2000>;
                                 status = "disabled";
                         };
 
                         usbphy1: usbphy@8007e000 {
+                                compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x8007e000 0x2000>;
                                 status = "disabled";
                         };
@@ -459,13 +750,19 @@
                 reg = <0x80080000 0x80000>;
                 ranges;
 
-                usbctrl0: usbctrl@80080000 {
+                usb0: usb@80080000 {
+                        compatible = "fsl,imx28-usb", "fsl,imx27-usb";
                         reg = <0x80080000 0x10000>;
+                        interrupts = <93>;
+                        fsl,usbphy = <&usbphy0>;
                         status = "disabled";
                 };
 
-                usbctrl1: usbctrl@80090000 {
+                usb1: usb@80090000 {
+                        compatible = "fsl,imx28-usb", "fsl,imx27-usb";
                         reg = <0x80090000 0x10000>;
+                        interrupts = <92>;
+                        fsl,usbphy = <&usbphy1>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
new file mode 100644
index 00000000000..24731cb78e8
--- /dev/null
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx31.dtsi"
+
+/ {
+        model = "Buglabs i.MX31 Bug 1.x";
+        compatible = "fsl,imx31-bug", "fsl,imx31";
+
+        memory {
+                reg = <0x80000000 0x8000000>; /* 128M */
+        };
+
+        soc {
+                aips@43f00000 { /* AIPS1 */
+                        uart5: serial@43fb4000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
new file mode 100644
index 00000000000..eef7099f3e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+        };
+
+        avic: avic-interrupt-controller@60000000 {
+                compatible = "fsl,imx31-avic", "fsl,avic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x60000000 0x100000>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&avic>;
+                ranges;
+
+                aips@43f00000 { /* AIPS1 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x43f00000 0x100000>;
+                        ranges;
+
+                        uart1: serial@43f90000 {
+                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
+                                reg = <0x43f90000 0x4000>;
+                                interrupts = <45>;
+                                status = "disabled";
+                        };
+
+                        uart2: serial@43f94000 {
+                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
+                                reg = <0x43f94000 0x4000>;
+                                interrupts = <32>;
+                                status = "disabled";
+                        };
+
+                        uart4: serial@43fb0000 {
+                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
+                                reg = <0x43fb0000 0x4000>;
+                                interrupts = <46>;
+                                status = "disabled";
+                        };
+
+                        uart5: serial@43fb4000 {
+                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
+                                reg = <0x43fb4000 0x4000>;
+                                interrupts = <47>;
+                                status = "disabled";
+                        };
+                };
+
+                spba@50000000 {
+                        compatible = "fsl,spba-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x50000000 0x100000>;
+                        ranges;
+
+                        uart3: serial@5000c000 {
+                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
+                                reg = <0x5000c000 0x4000>;
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index de065b5976e..59d9789e550 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -25,8 +25,8 @@
                 aips@70000000 { /* aips-1 */
                         spba@70000000 {
                                 esdhc@70004000 { /* ESDHC1 */
-                                        fsl,cd-internal;
-                                        fsl,wp-internal;
+                                        fsl,cd-controller;
+                                        fsl,wp-controller;
                                         status = "okay";
                                 };
 
@@ -53,7 +53,7 @@
                                                 spi-max-frequency = <6000000>;
                                                 reg = <0>;
                                                 interrupt-parent = <&gpio1>;
-                                                interrupts = <8>;
+                                                interrupts = <8 0x4>;
 
                                                 regulators {
                                                         sw1_reg: sw1 {
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index bfa65abe8ef..aba28dc87fc 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -17,6 +17,10 @@
                 serial0 = &uart1;
                 serial1 = &uart2;
                 serial2 = &uart3;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
         };
 
         tzic: tz-interrupt-controller@e0000000 {
@@ -127,43 +131,43 @@
                         };
 
                         gpio1: gpio@73f84000 {
-                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
                                 reg = <0x73f84000 0x4000>;
                                 interrupts = <50 51>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio2: gpio@73f88000 {
-                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
                                 reg = <0x73f88000 0x4000>;
                                 interrupts = <52 53>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio3: gpio@73f8c000 {
-                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
                                 reg = <0x73f8c000 0x4000>;
                                 interrupts = <54 55>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio4: gpio@73f90000 {
-                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
                                 reg = <0x73f90000 0x4000>;
                                 interrupts = <56 57>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         wdog@73f98000 { /* WDOG1 */
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 5b8eafcdbee..da895e93a99 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -64,12 +64,32 @@
                         reg = <0xf4000000 0x2000000>;
                         phy-mode = "mii";
                         interrupt-parent = <&gpio2>;
-                        interrupts = <31>;
+                        interrupts = <31 0x8>;
                         reg-io-width = <4>;
+                        /*
+                         * VDD33A and VDDVARIO of LAN9220 are supplied by
+                         * SW4_3V3 of LTC3589.  Before the regulator driver
+                         * for this PMIC is available, we use a fixed dummy
+                         * 3V3 regulator to get LAN9220 driver probing work.
+                         */
+                        vdd33a-supply = <&reg_3p3v>;
+                        vddvario-supply = <&reg_3p3v>;
                         smsc,irq-push-pull;
                 };
         };
 
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+
         gpio-keys {
                 compatible = "gpio-keys";
 
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index e3e869470cd..cd37165edce 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -19,6 +19,13 @@
                 serial2 = &uart3;
                 serial3 = &uart4;
                 serial4 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+                gpio5 = &gpio6;
+                gpio6 = &gpio7;
         };
 
         tzic: tz-interrupt-controller@0fffc000 {
@@ -129,43 +136,43 @@
                         };
 
                         gpio1: gpio@53f84000 {
-                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53f84000 0x4000>;
                                 interrupts = <50 51>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio2: gpio@53f88000 {
-                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53f88000 0x4000>;
                                 interrupts = <52 53>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio3: gpio@53f8c000 {
-                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53f8c000 0x4000>;
                                 interrupts = <54 55>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio4: gpio@53f90000 {
-                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53f90000 0x4000>;
                                 interrupts = <56 57>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         wdog@53f98000 { /* WDOG1 */
@@ -197,33 +204,33 @@
                         };
 
                         gpio5: gpio@53fdc000 {
-                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53fdc000 0x4000>;
                                 interrupts = <103 104>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio6: gpio@53fe0000 {
-                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53fe0000 0x4000>;
                                 interrupts = <105 106>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio7: gpio@53fe4000 {
-                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
                                 reg = <0x53fe4000 0x4000>;
                                 interrupts = <107 108>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         i2c@53fec000 { /* I2C3 */
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index db4c6096c56..d792581672c 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -22,6 +22,12 @@
         };
 
         soc {
+                gpmi-nand@00112000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+                        status = "disabled"; /* gpmi nand conflicts with SD */
+                };
+
                 aips-bus@02100000 { /* AIPS2 */
                         ethernet@02188000 {
                                 phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index e0ec92973e7..72f30f3e617 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -27,6 +27,8 @@
                                 ecspi@02008000 { /* eCSPI1 */
                                         fsl,spi-num-chipselects = <1>;
                                         cs-gpios = <&gpio3 19 0>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                         status = "okay";
 
                                         flash: m25p80@0 {
@@ -42,9 +44,32 @@
                                 };
                         };
 
+                        iomuxc@020e0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_gpio_hog>;
+
+                                gpios {
+                                        pinctrl_gpio_hog: gpiohog {
+                                                fsl,pins = <
+                                                           144  0x80000000      /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+                                                           121  0x80000000      /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+                                                           953  0x80000000      /* MX6Q_PAD_GPIO_0__CCM_CLKO */
+                                                           >;
+                                        };
+                                };
+                        };
                 };
 
                 aips-bus@02100000 { /* AIPS2 */
+                        usb@02184000 { /* USB OTG */
+                                vbus-supply = <&reg_usb_otg_vbus>;
+                                status = "okay";
+                        };
+
+                        usb@02184200 { /* USB1 */
+                                status = "okay";
+                        };
+
                         ethernet@02188000 {
                                 phy-mode = "rgmii";
                                 phy-reset-gpios = <&gpio3 23 0>;
@@ -111,6 +136,15 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                reg_usb_otg_vbus: usb_otg_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
         };
 
         sound {
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 8c90cbac945..fd57079f71a 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -19,6 +19,13 @@
                 serial2 = &uart3;
                 serial3 = &uart4;
                 serial4 = &uart5;
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+                gpio5 = &gpio6;
+                gpio6 = &gpio7;
         };
 
         cpus {
@@ -87,6 +94,23 @@
                 interrupt-parent = <&intc>;
                 ranges;
 
+                dma-apbh@00110000 {
+                        compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+                        reg = <0x00110000 0x2000>;
+                };
+
+                gpmi-nand@00112000 {
+                       compatible = "fsl,imx6q-gpmi-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+                       reg-names = "gpmi-nand", "bch";
+                       interrupts = <0 13 0x04>, <0 15 0x04>;
+                       interrupt-names = "gpmi-dma", "bch";
+                       fsl,gpmi-dma-channel = <0>;
+                       status = "disabled";
+                };
+
                 timer@00a00600 {
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = <0x00a00600 0x20>;
@@ -260,73 +284,73 @@
                         };
 
                         gpio1: gpio@0209c000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                 reg = <0x0209c000 0x4000>;
                                 interrupts = <0 66 0x04 0 67 0x04>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio2: gpio@020a0000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                 reg = <0x020a0000 0x4000>;
                                 interrupts = <0 68 0x04 0 69 0x04>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio3: gpio@020a4000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                 reg = <0x020a4000 0x4000>;
                                 interrupts = <0 70 0x04 0 71 0x04>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio4: gpio@020a8000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                 reg = <0x020a8000 0x4000>;
                                 interrupts = <0 72 0x04 0 73 0x04>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio5: gpio@020ac000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                 reg = <0x020ac000 0x4000>;
                                 interrupts = <0 74 0x04 0 75 0x04>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio6: gpio@020b0000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                 reg = <0x020b0000 0x4000>;
                                 interrupts = <0 76 0x04 0 77 0x04>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio7: gpio@020b4000 {
-                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
+                                compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
                                 reg = <0x020b4000 0x4000>;
                                 interrupts = <0 78 0x04 0 79 0x04>;
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         kpp@020b8000 {
@@ -444,12 +468,14 @@
                                 };
                         };
 
-                        usbphy@020c9000 { /* USBPHY1 */
+                        usbphy1: usbphy@020c9000 {
+                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x020c9000 0x1000>;
                                 interrupts = <0 44 0x04>;
                         };
 
-                        usbphy@020ca000 { /* USBPHY2 */
+                        usbphy2: usbphy@020ca000 {
+                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x020ca000 0x1000>;
                                 interrupts = <0 45 0x04>;
                         };
@@ -495,6 +521,30 @@
                                         };
                                 };
 
+                                gpmi-nand {
+                                        pinctrl_gpmi_nand_1: gpmi-nand-1 {
+                                                fsl,pins = <1328 0xb0b1         /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+                                                            1336 0xb0b1         /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
+                                                            1344 0xb0b1         /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
+                                                            1352 0xb000         /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
+                                                            1360 0xb0b1         /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
+                                                            1365 0xb0b1         /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
+                                                            1371 0xb0b1         /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
+                                                            1378 0xb0b1         /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
+                                                            1387 0xb0b1         /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
+                                                            1393 0xb0b1         /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
+                                                            1397 0xb0b1         /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
+                                                            1405 0xb0b1         /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
+                                                            1413 0xb0b1         /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
+                                                            1421 0xb0b1         /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
+                                                            1429 0xb0b1         /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
+                                                            1437 0xb0b1         /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
+                                                            1445 0xb0b1         /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
+                                                            1453 0xb0b1         /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+                                                            1463 0x00b1>;       /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+                                        };
+                                };
+
                                 i2c1 {
                                         pinctrl_i2c1_1: i2c1grp-1 {
                                                 fsl,pins = <137 0x4001b8b1      /* MX6Q_PAD_EIM_D21__I2C1_SCL */
@@ -538,6 +588,14 @@
                                                             1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
                                         };
                                 };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <101 0x100b1         /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+                                                            109 0x100b1         /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+                                                            94  0x100b1>;       /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+                                        };
+                                };
                         };
 
                         dcic@020e4000 { /* DCIC1 */
@@ -573,6 +631,36 @@
                                 reg = <0x0217c000 0x4000>;
                         };
 
+                        usb@02184000 { /* USB OTG */
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184000 0x200>;
+                                interrupts = <0 43 0x04>;
+                                fsl,usbphy = <&usbphy1>;
+                                status = "disabled";
+                        };
+
+                        usb@02184200 { /* USB1 */
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184200 0x200>;
+                                interrupts = <0 40 0x04>;
+                                fsl,usbphy = <&usbphy2>;
+                                status = "disabled";
+                        };
+
+                        usb@02184400 { /* USB2 */
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184400 0x200>;
+                                interrupts = <0 41 0x04>;
+                                status = "disabled";
+                        };
+
+                        usb@02184600 { /* USB3 */
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184600 0x200>;
+                                interrupts = <0 42 0x04>;
+                                status = "disabled";
+                        };
+
                         ethernet@02188000 {
                                 compatible = "fsl,imx6q-fec";
                                 reg = <0x02188000 0x4000>;
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index dc09a735b04..5bb0bf39d3b 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -1,10 +1,10 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
+/include/ "kirkwood-dnskw.dtsi"
 
 / {
         model = "D-Link DNS-320 NAS (Rev A1)";
-        compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+        compatible = "dlink,dns-320-a1", "dlink,dns-320", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
 
         memory {
                 device_type = "memory";
@@ -15,6 +15,31 @@
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
         };
 
+        gpio-leds {
+                compatible = "gpio-leds";
+                blue-power {
+                        label = "dns320:blue:power";
+                        gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
+                        linux,default-trigger = "default-on";
+                };
+                blue-usb {
+                        label = "dns320:blue:usb";
+                        gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */
+                };
+                orange-l_hdd {
+                        label = "dns320:orange:l_hdd";
+                        gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */
+                };
+                orange-r_hdd {
+                        label = "dns320:orange:r_hdd";
+                        gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */
+                };
+                orange-usb {
+                        label = "dns320:orange:usb";
+                        gpios = <&gpio1 3 1>; /* GPIO 35 Active Low */
+                };
+        };
+
         ocp@f1000000 {
                 serial@12000 {
                         clock-frequency = <166666667>;
@@ -25,40 +50,5 @@
                         clock-frequency = <166666667>;
                         status = "okay";
                 };
-
-                nand@3000000 {
-                        status = "okay";
-
-                        partition@0 {
-                                label = "u-boot";
-                                reg = <0x0000000 0x100000>;
-                                read-only;
-                        };
-
-                        partition@100000 {
-                                label = "uImage";
-                                reg = <0x0100000 0x500000>;
-                        };
-
-                        partition@600000 {
-                                label = "ramdisk";
-                                reg = <0x0600000 0x500000>;
-                        };
-
-                        partition@b00000 {
-                                label = "image";
-                                reg = <0x0b00000 0x6600000>;
-                        };
-
-                        partition@7100000 {
-                                label = "mini firmware";
-                                reg = <0x7100000 0xa00000>;
-                        };
-
-                        partition@7b00000 {
-                                label = "config";
-                                reg = <0x7b00000 0x500000>;
-                        };
-                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index c2a5562525d..d430713ea9b 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -1,10 +1,10 @@
 /dts-v1/;
 
-/include/ "kirkwood.dtsi"
+/include/ "kirkwood-dnskw.dtsi"
 
 / {
         model = "D-Link DNS-325 NAS (Rev A1)";
-        compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+        compatible = "dlink,dns-325-a1", "dlink,dns-325", "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
 
         memory {
                 device_type = "memory";
@@ -15,45 +15,43 @@
                 bootargs = "console=ttyS0,115200n8 earlyprintk";
         };
 
-        ocp@f1000000 {
-                serial@12000 {
-                        clock-frequency = <200000000>;
-                        status = "okay";
+        gpio-leds {
+                compatible = "gpio-leds";
+                white-power {
+                        label = "dns325:white:power";
+                        gpios = <&gpio0 26 1>; /* GPIO 26 Active Low */
+                        linux,default-trigger = "default-on";
+                };
+                white-usb {
+                        label = "dns325:white:usb";
+                        gpios = <&gpio1 11 1>; /* GPIO 43 Active Low */
+                };
+                red-l_hdd {
+                        label = "dns325:red:l_hdd";
+                        gpios = <&gpio0 28 1>; /* GPIO 28 Active Low */
                 };
+                red-r_hdd {
+                        label = "dns325:red:r_hdd";
+                        gpios = <&gpio0 27 1>; /* GPIO 27 Active Low */
+                };
+                red-usb {
+                        label = "dns325:red:usb";
+                        gpios = <&gpio0 29 1>; /* GPIO 29 Active Low */
+                };
+        };
 
-                nand@3000000 {
+        ocp@f1000000 {
+                i2c@11000 {
                         status = "okay";
 
-                        partition@0 {
-                                label = "u-boot";
-                                reg = <0x0000000 0x100000>;
-                                read-only;
-                        };
-
-                        partition@100000 {
-                                label = "uImage";
-                                reg = <0x0100000 0x500000>;
-                        };
-
-                        partition@600000 {
-                                label = "ramdisk";
-                                reg = <0x0600000 0x500000>;
-                        };
-
-                        partition@b00000 {
-                                label = "image";
-                                reg = <0x0b00000 0x6600000>;
-                        };
-
-                        partition@7100000 {
-                                label = "mini firmware";
-                                reg = <0x7100000 0xa00000>;
-                        };
-
-                        partition@7b00000 {
-                                label = "config";
-                                reg = <0x7b00000 0x500000>;
+                        lm75: lm75@48 {
+                                compatible = "national,lm75";
+                                reg = <0x48>;
                         };
                 };
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "okay";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
new file mode 100644
index 00000000000..7408655f91b
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -0,0 +1,69 @@
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "D-Link DNS NASes (kirkwood-based)";
+        compatible = "dlink,dns-kirkwood", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "Power button";
+                        linux,code = <116>;
+                        gpios = <&gpio1 2 1>;
+                };
+                button@2 {
+                        label = "USB unmount button";
+                        linux,code = <161>;
+                        gpios = <&gpio1 15 1>;
+                };
+                button@3 {
+                        label = "Reset button";
+                        linux,code = <0x198>;
+                        gpios = <&gpio1 16 1>;
+                };
+        };
+
+        ocp@f1000000 {
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x500000>;
+                        };
+
+                        partition@600000 {
+                                label = "ramdisk";
+                                reg = <0x0600000 0x500000>;
+                        };
+
+                        partition@b00000 {
+                                label = "image";
+                                reg = <0x0b00000 0x6600000>;
+                        };
+
+                        partition@7100000 {
+                                label = "mini firmware";
+                                reg = <0x7100000 0xa00000>;
+                        };
+
+                        partition@7b00000 {
+                                label = "config";
+                                reg = <0x7b00000 0x500000>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index a5376b84227..26e281fbf6b 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -4,7 +4,7 @@
 
 / {
         model = "Globalscale Technologies Dreamplug";
-        compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+        compatible = "globalscale,dreamplug-003-ds2001", "globalscale,dreamplug", "marvell,kirkwood-88f6281", "marvell,kirkwood";
 
         memory {
                 device_type = "memory";
@@ -20,5 +20,55 @@
                         clock-frequency = <200000000>;
                         status = "ok";
                 };
+
+                spi@10600 {
+                        status = "okay";
+
+                        m25p40@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "mx25l1606e";
+                                reg = <0>;
+                                spi-max-frequency = <50000000>;
+                                mode = <0>;
+
+                                partition@0 {
+                                        reg = <0x0 0x80000>;
+                                        label = "u-boot";
+                                };
+
+                                partition@100000 {
+                                        reg = <0x100000 0x10000>;
+                                        label = "u-boot env";
+                                };
+
+                                partition@180000 {
+                                        reg = <0x180000 0x10000>;
+                                        label = "dtb";
+                                };
+                        };
+                };
+
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+        };
+
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                bluetooth {
+                        label = "dreamplug:blue:bluetooth";
+                        gpios = <&gpio1 15 1>;
+                };
+                wifi {
+                        label = "dreamplug:green:wifi";
+                        gpios = <&gpio1 16 1>;
+                };
+                wifi-ap {
+                        label = "dreamplug:green:wifi_ap";
+                        gpios = <&gpio1 17 1>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
new file mode 100644
index 00000000000..7c8238fbb6f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -0,0 +1,99 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Seagate GoFlex Net";
+        compatible = "seagate,goflexnet", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x400000>;
+                        };
+
+                        partition@500000 {
+                                label = "pogoplug";
+                                reg = <0x0500000 0x2000000>;
+                        };
+
+                        partition@2500000 {
+                                label = "root";
+                                reg = <0x02500000 0xd800000>;
+                        };
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                health {
+                        label = "status:green:health";
+                        gpios = <&gpio1 14 1>;
+                        linux,default-trigger = "default-on";
+                };
+                fault {
+                        label = "status:orange:fault";
+                        gpios = <&gpio1 15 1>;
+                };
+                left0 {
+                        label = "status:white:left0";
+                        gpios = <&gpio1 10 0>;
+                };
+                left1 {
+                        label = "status:white:left1";
+                        gpios = <&gpio1 11 0>;
+                };
+                left2 {
+                        label = "status:white:left2";
+                        gpios = <&gpio1 12 0>;
+                };
+                left3 {
+                        label = "status:white:left3";
+                        gpios = <&gpio1 13 0>;
+                };
+                right0 {
+                        label = "status:white:right0";
+                        gpios = <&gpio1 6 0>;
+                };
+                right1 {
+                        label = "status:white:right1";
+                        gpios = <&gpio1 7 0>;
+                };
+                right2 {
+                        label = "status:white:right2";
+                        gpios = <&gpio1 8 0>;
+                };
+                right3 {
+                        label = "status:white:right3";
+                        gpios = <&gpio1 9 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index ada0f0c2308..66794ed75ff 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -4,7 +4,7 @@
 
 / {
         model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
-        compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0",  "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+        compatible = "raidsonic,ib-nas6210-b", "raidsonic,ib-nas6220-b", "raidsonic,ib-nas6210", "raidsonic,ib-nas6220", "raidsonic,ib-nas62x0",  "marvell,kirkwood-88f6281", "marvell,kirkwood";
 
         memory {
                 device_type = "memory";
@@ -21,6 +21,11 @@
                         status = "okay";
                 };
 
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+
                 nand@3000000 {
                         status = "okay";
 
@@ -41,4 +46,37 @@
 
                 };
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "USB Copy";
+                        linux,code = <133>;
+                        gpios = <&gpio0 29 1>;
+                };
+                button@2 {
+                        label = "Reset";
+                        linux,code = <0x198>;
+                        gpios = <&gpio0 28 1>;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                green-os {
+                        label = "ib62x0:green:os";
+                        gpios = <&gpio0 25 0>;
+                        linux,default-trigger = "default-on";
+                };
+                red-os {
+                        label = "ib62x0:red:os";
+                        gpios = <&gpio0 22 0>;
+                };
+                usb-copy {
+                        label = "ib62x0:red:usb_copy";
+                        gpios = <&gpio0 27 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 1ba75d4adec..f8ca6fa8819 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -4,7 +4,7 @@
 
 / {
         model = "Iomega Iconnect";
-        compatible = "iom,iconnect-1.1", "iom,iconnect", "mrvl,kirkwood-88f6281", "mrvl,kirkwood";
+        compatible = "iom,iconnect-1.1", "iom,iconnect", "marvell,kirkwood-88f6281", "marvell,kirkwood";
 
         memory {
                 device_type = "memory";
@@ -18,9 +18,55 @@
         };
 
         ocp@f1000000 {
+                i2c@11000 {
+                        status = "okay";
+
+                        lm63: lm63@4c {
+                                compatible = "national,lm63";
+                                reg = <0x4c>;
+                        };
+                };
                 serial@12000 {
                         clock-frequency = <200000000>;
                         status = "ok";
                 };
         };
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                led-level {
+                        label = "led_level";
+                        gpios = <&gpio1 9 0>;
+                        linux,default-trigger = "default-on";
+                };
+                power-blue {
+                        label = "power:blue";
+                        gpios = <&gpio1 10 0>;
+                        linux,default-trigger = "timer";
+                };
+                power-red {
+                        label = "power:red";
+                        gpios = <&gpio1 11 0>;
+                };
+                usb1 {
+                        label = "usb1:blue";
+                        gpios = <&gpio1 12 0>;
+                };
+                usb2 {
+                        label = "usb2:blue";
+                        gpios = <&gpio1 13 0>;
+                };
+                usb3 {
+                        label = "usb3:blue";
+                        gpios = <&gpio1 14 0>;
+                };
+                usb4 {
+                        label = "usb4:blue";
+                        gpios = <&gpio1 15 0>;
+                };
+                otb {
+                        label = "otb:blue";
+                        gpios = <&gpio1 16 0>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/kirkwood-lschlv2.dts
new file mode 100644
index 00000000000..9510c9ea666
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-lschlv2.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+
+/include/ "kirkwood-lsxl.dtsi"
+
+/ {
+        model = "Buffalo Linkstation LS-CHLv2";
+        compatible = "buffalo,lschlv2", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x4000000>;
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <166666667>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/kirkwood-lsxhl.dts
new file mode 100644
index 00000000000..739019c4cba
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-lsxhl.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+
+/include/ "kirkwood-lsxl.dtsi"
+
+/ {
+        model = "Buffalo Linkstation LS-XHL";
+        compatible = "buffalo,lsxhl", "buffalo,lsxl", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
new file mode 100644
index 00000000000..8ac51c08269
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -0,0 +1,95 @@
+/include/ "kirkwood.dtsi"
+
+/ {
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <1>;
+                };
+
+                spi@10600 {
+                        status = "okay";
+
+                        m25p40@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "m25p40";
+                                reg = <0>;
+                                spi-max-frequency = <25000000>;
+                                mode = <0>;
+
+                                partition@0 {
+                                        reg = <0x0 0x60000>;
+                                        label = "uboot";
+                                        read-only;
+                                };
+
+                                partition@60000 {
+                                        reg = <0x60000 0x10000>;
+                                        label = "dtb";
+                                        read-only;
+                                };
+
+                                partition@70000 {
+                                        reg = <0x70000 0x10000>;
+                                        label = "uboot_env";
+                                };
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "Function Button";
+                        linux,code = <132>;
+                        gpios = <&gpio1 9 1>;
+                };
+                button@2 {
+                        label = "Power-on Switch";
+                        linux,code = <116>;
+                        gpios = <&gpio1 10 1>;
+                };
+                button@3 {
+                        label = "Power-auto Switch";
+                        linux,code = <142>;
+                        gpios = <&gpio1 11 1>;
+                };
+        };
+
+        gpio_leds {
+                compatible = "gpio-leds";
+
+                led@1 {
+                        label = "lschlv2:blue:func";
+                        gpios = <&gpio1 4 1>;
+                };
+
+                led@2 {
+                        label = "lschlv2:red:alarm";
+                        gpios = <&gpio1 5 1>;
+                };
+
+                led@3 {
+                        label = "lschlv2:amber:info";
+                        gpios = <&gpio1 6 1>;
+                };
+
+                led@4 {
+                        label = "lschlv2:blue:power";
+                        gpios = <&gpio1 7 1>;
+                        linux,default-trigger = "default-on";
+                };
+
+                led@5 {
+                        label = "lschlv2:red:func";
+                        gpios = <&gpio1 16 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
new file mode 100644
index 00000000000..ccbf3275780
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+/include/ "kirkwood-ts219.dtsi"
+
+/ {
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "USB Copy";
+                        linux,code = <133>;
+                        gpios = <&gpio0 15 1>;
+                };
+                button@2 {
+                        label = "Reset";
+                        linux,code = <0x198>;
+                        gpios = <&gpio0 16 1>;
+                };
+        };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
new file mode 100644
index 00000000000..fbe9932161a
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+/include/ "kirkwood-ts219.dtsi"
+
+/ {
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "USB Copy";
+                        linux,code = <133>;
+                        gpios = <&gpio1 11 1>;
+                };
+                button@2 {
+                        label = "Reset";
+                        linux,code = <0x198>;
+                        gpios = <&gpio1 5 1>;
+                };
+        };
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
new file mode 100644
index 00000000000..64ea27cb329
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -0,0 +1,78 @@
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "QNAP TS219 family";
+        compatible = "qnap,ts219", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+        };
+
+        ocp@f1000000 {
+                i2c@11000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+
+                        s35390a: s35390a@30 {
+                                compatible = "s35390a";
+                                reg = <0x30>;
+                        };
+                };
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "okay";
+                };
+                serial@12100 {
+                        clock-frequency = <200000000>;
+                        status = "okay";
+                };
+                spi@10600 {
+                        status = "okay";
+
+                        m25p128@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "m25p128";
+                                reg = <0>;
+                                spi-max-frequency = <20000000>;
+                                mode = <0>;
+
+                                partition@0000000 {
+                                        reg = <0x00000000 0x00080000>;
+                                        label = "U-Boot";
+                                };
+
+                                partition@00200000 {
+                                        reg = <0x00200000 0x00200000>;
+                                        label = "Kernel";
+                                };
+
+                                partition@00400000 {
+                                        reg = <0x00400000 0x00900000>;
+                                        label = "RootFS1";
+                                };
+                                partition@00d00000 {
+                                        reg = <0x00d00000 0x00300000>;
+                                        label = "RootFS2";
+                                };
+                                partition@00040000 {
+                                        reg = <0x00080000 0x00040000>;
+                                        label = "U-Boot Config";
+                                };
+                                partition@000c0000 {
+                                        reg = <0x000c0000 0x00140000>;
+                                        label = "NAS Config";
+                                };
+                        };
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 926528b81ba..cef9616f330 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -1,7 +1,16 @@
 /include/ "skeleton.dtsi"
 
 / {
-        compatible = "mrvl,kirkwood";
+        compatible = "marvell,kirkwood";
+        interrupt-parent = <&intc>;
+
+        intc: interrupt-controller {
+                compatible = "marvell,orion-intc", "marvell,intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xf1020204 0x04>,
+                      <0xf1020214 0x04>;
+        };
 
         ocp@f1000000 {
                 compatible = "simple-bus";
@@ -9,6 +18,24 @@
                 #address-cells = <1>;
                 #size-cells = <1>;
 
+                gpio0: gpio@10100 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0x10100 0x40>;
+                        ngpio = <32>;
+                        interrupts = <35>, <36>, <37>, <38>;
+                };
+
+                gpio1: gpio@10140 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0x10140 0x40>;
+                        ngpio = <18>;
+                        interrupts = <39>, <40>, <41>;
+                };
+
                 serial@12000 {
                         compatible = "ns16550a";
                         reg = <0x12000 0x100>;
@@ -28,22 +55,55 @@
                 };
 
                 rtc@10300 {
-                        compatible = "mrvl,kirkwood-rtc", "mrvl,orion-rtc";
+                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
                         reg = <0x10300 0x20>;
                         interrupts = <53>;
                 };
 
+                spi@10600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        interrupts = <23>;
+                        reg = <0x10600 0x28>;
+                        status = "disabled";
+                };
+
+                wdt@20300 {
+                        compatible = "marvell,orion-wdt";
+                        reg = <0x20300 0x28>;
+                        status = "okay";
+                };
+
+                sata@80000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0x80000 0x5000>;
+                        interrupts = <21>;
+                        status = "disabled";
+                };
+
                 nand@3000000 {
                         #address-cells = <1>;
                         #size-cells = <1>;
                         cle = <0>;
                         ale = <1>;
                         bank-width = <1>;
-                        compatible = "mrvl,orion-nand";
+                        compatible = "marvell,orion-nand";
                         reg = <0x3000000 0x400>;
                         chip-delay = <25>;
                         /* set partition map and/or chip-delay in board dts */
                         status = "disabled";
                 };
+
+                i2c@11000 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11000 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <29>;
+                        clock-frequency = <100000>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 3f5dad801a9..e5ffe960dbf 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -35,13 +35,14 @@
                 slc: flash@20020000 {
                         compatible = "nxp,lpc3220-slc";
                         reg = <0x20020000 0x1000>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
-                mlc: flash@200B0000 {
+                mlc: flash@200a8000 {
                         compatible = "nxp,lpc3220-mlc";
-                        reg = <0x200B0000 0x1000>;
-                        status = "disable";
+                        reg = <0x200a8000 0x11000>;
+                        interrupts = <11 0>;
+                        status = "disabled";
                 };
 
                 dma@31000000 {
@@ -57,21 +58,21 @@
                         compatible = "nxp,ohci-nxp", "usb-ohci";
                         reg = <0x31020000 0x300>;
                         interrupts = <0x3b 0>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 usbd@31020000 {
                         compatible = "nxp,lpc3220-udc";
                         reg = <0x31020000 0x300>;
                         interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 clcd@31040000 {
                         compatible = "arm,pl110", "arm,primecell";
                         reg = <0x31040000 0x1000>;
                         interrupts = <0x0e 0>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 mac: ethernet@31060000 {
@@ -114,9 +115,10 @@
                         };
 
                         sd@20098000 {
-                                compatible = "arm,pl180", "arm,primecell";
+                                compatible = "arm,pl18x", "arm,primecell";
                                 reg = <0x20098000 0x1000>;
                                 interrupts = <0x0f 0>, <0x0d 0>;
+                                status = "disabled";
                         };
 
                         i2s1: i2s@2009C000 {
@@ -124,24 +126,42 @@
                                 reg = <0x2009C000 0x1000>;
                         };
 
+                        /* UART5 first since it is the default console, ttyS0 */
+                        uart5: serial@40090000 {
+                                /* actually, ns16550a w/ 64 byte fifos! */
+                                compatible = "nxp,lpc3220-uart";
+                                reg = <0x40090000 0x1000>;
+                                interrupts = <9 0>;
+                                clock-frequency = <13000000>;
+                                reg-shift = <2>;
+                                status = "disabled";
+                        };
+
                         uart3: serial@40080000 {
-                                compatible = "nxp,serial";
+                                compatible = "nxp,lpc3220-uart";
                                 reg = <0x40080000 0x1000>;
+                                interrupts = <7 0>;
+                                clock-frequency = <13000000>;
+                                reg-shift = <2>;
+                                status = "disabled";
                         };
 
                         uart4: serial@40088000 {
-                                compatible = "nxp,serial";
+                                compatible = "nxp,lpc3220-uart";
                                 reg = <0x40088000 0x1000>;
-                        };
-
-                        uart5: serial@40090000 {
-                                compatible = "nxp,serial";
-                                reg = <0x40090000 0x1000>;
+                                interrupts = <8 0>;
+                                clock-frequency = <13000000>;
+                                reg-shift = <2>;
+                                status = "disabled";
                         };
 
                         uart6: serial@40098000 {
-                                compatible = "nxp,serial";
+                                compatible = "nxp,lpc3220-uart";
                                 reg = <0x40098000 0x1000>;
+                                interrupts = <10 0>;
+                                clock-frequency = <13000000>;
+                                reg-shift = <2>;
+                                status = "disabled";
                         };
 
                         i2c1: i2c@400A0000 {
@@ -192,18 +212,24 @@
                         };
 
                         uart1: serial@40014000 {
-                                compatible = "nxp,serial";
+                                compatible = "nxp,lpc3220-hsuart";
                                 reg = <0x40014000 0x1000>;
+                                interrupts = <26 0>;
+                                status = "disabled";
                         };
 
                         uart2: serial@40018000 {
-                                compatible = "nxp,serial";
+                                compatible = "nxp,lpc3220-hsuart";
                                 reg = <0x40018000 0x1000>;
+                                interrupts = <25 0>;
+                                status = "disabled";
                         };
 
-                        uart7: serial@4001C000 {
-                                compatible = "nxp,serial";
-                                reg = <0x4001C000 0x1000>;
+                        uart7: serial@4001c000 {
+                                compatible = "nxp,lpc3220-hsuart";
+                                reg = <0x4001c000 0x1000>;
+                                interrupts = <24 0>;
+                                status = "disabled";
                         };
 
                         rtc@40024000 {
@@ -235,21 +261,28 @@
                                 compatible = "nxp,lpc3220-adc";
                                 reg = <0x40048000 0x1000>;
                                 interrupts = <0x27 0>;
-                                status = "disable";
+                                status = "disabled";
                         };
 
                         tsc@40048000 {
                                 compatible = "nxp,lpc3220-tsc";
                                 reg = <0x40048000 0x1000>;
                                 interrupts = <0x27 0>;
-                                status = "disable";
+                                status = "disabled";
                         };
 
                         key@40050000 {
                                 compatible = "nxp,lpc3220-key";
                                 reg = <0x40050000 0x1000>;
+                                interrupts = <54 0>;
+                                status = "disabled";
                         };
 
+                        pwm: pwm@4005C000 {
+                                compatible = "nxp,lpc3220-pwm";
+                                reg = <0x4005C000 0x8>;
+                                status = "disabled";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
new file mode 100644
index 00000000000..25b50b759de
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap2.dtsi"
+
+/ {
+        model = "TI OMAP2420 H4 board";
+        compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x84000000>; /* 64 MB */
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 5b4506c0a8c..cdcb98c7e07 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -61,9 +61,9 @@
 };
 
 &mmc2 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc3 {
-        status = "disable";
+        status = "disabled";
 };
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 2eee16ec59b..f349ee9182c 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -18,3 +18,31 @@
                 reg = <0x80000000 0x10000000>; /* 256 MB */
         };
 };
+
+&i2c1 {
+        clock-frequency = <2600000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+        };
+};
+
+/include/ "twl4030.dtsi"
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&i2c3 {
+        clock-frequency = <400000>;
+
+        /*
+         * TVP5146 Video decoder-in for analog input support.
+         */
+        tvp5146@5c {
+                compatible = "ti,tvp5146m2";
+                reg = <0x5c>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 99474fa5fac..81094719820 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -215,5 +215,10 @@
                         compatible = "ti,omap3-hsmmc";
                         ti,hwmods = "mmc3";
                 };
+
+                wdt2: wdt@48314000 {
+                        compatible = "ti,omap3-wdt";
+                        ti,hwmods = "wd_timer2";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 1efe0c58798..9880c12877b 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -32,6 +32,30 @@
                         linux,default-trigger = "mmc0";
                 };
         };
+
+        sound: sound {
+                compatible = "ti,abe-twl6040";
+                ti,model = "PandaBoard";
+
+                ti,mclk-freq = <38400000>;
+
+                ti,mcpdm = <&mcpdm>;
+
+                ti,twl6040 = <&twl6040>;
+
+                /* Audio routing */
+                ti,audio-routing =
+                        "Headset Stereophone", "HSOL",
+                        "Headset Stereophone", "HSOR",
+                        "Ext Spk", "HFL",
+                        "Ext Spk", "HFR",
+                        "Line Out", "AUXL",
+                        "Line Out", "AUXR",
+                        "HSMIC", "Headset Mic",
+                        "Headset Mic", "Headset Mic Bias",
+                        "AFML", "Line In",
+                        "AFMR", "Line In";
+        };
 };
 
 &i2c1 {
@@ -43,6 +67,19 @@
                 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
                 interrupt-parent = <&gic>;
         };
+
+        twl6040: twl@4b {
+                compatible = "ti,twl6040";
+                reg = <0x4b>;
+                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
+                interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+                interrupt-parent = <&gic>;
+                ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
+
+                vio-supply = <&v1v8>;
+                v2v1-supply = <&v2v1>;
+                enable-active-high;
+        };
 };
 
 /include/ "twl6030.dtsi"
@@ -74,15 +111,15 @@
 };
 
 &mmc2 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc3 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc4 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc5 {
diff --git a/arch/arm/boot/dts/omap4-pandaES.dts b/arch/arm/boot/dts/omap4-pandaES.dts
new file mode 100644
index 00000000000..d4ba43a48d9
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-pandaES.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/include/ "omap4-panda.dts"
+
+/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
+&sound {
+        ti,model = "PandaBoardES";
+
+        /* Audio routing */
+        ti,audio-routing =
+                "Headset Stereophone", "HSOL",
+                "Headset Stereophone", "HSOR",
+                "Ext Spk", "HFL",
+                "Ext Spk", "HFR",
+                "Line Out", "AUXL",
+                "Line Out", "AUXR",
+                "AFML", "Line In",
+                "AFMR", "Line In";
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index d08c4d13728..72216e932fc 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -28,6 +28,14 @@
                 regulator-boot-on;
         };
 
+        vbat: fixedregulator@2 {
+                compatible = "regulator-fixed";
+                regulator-name = "VBAT";
+                regulator-min-microvolt = <3750000>;
+                regulator-max-microvolt = <3750000>;
+                regulator-boot-on;
+        };
+
         leds {
                 compatible = "gpio-leds";
                 debug0 {
@@ -70,6 +78,41 @@
                         gpios = <&gpio5 11 0>; /* 139 */
                 };
         };
+
+        sound {
+                compatible = "ti,abe-twl6040";
+                ti,model = "SDP4430";
+
+                ti,jack-detection = <1>;
+                ti,mclk-freq = <38400000>;
+
+                ti,mcpdm = <&mcpdm>;
+                ti,dmic = <&dmic>;
+
+                ti,twl6040 = <&twl6040>;
+
+                /* Audio routing */
+                ti,audio-routing =
+                        "Headset Stereophone", "HSOL",
+                        "Headset Stereophone", "HSOR",
+                        "Earphone Spk", "EP",
+                        "Ext Spk", "HFL",
+                        "Ext Spk", "HFR",
+                        "Line Out", "AUXL",
+                        "Line Out", "AUXR",
+                        "Vibrator", "VIBRAL",
+                        "Vibrator", "VIBRAR",
+                        "HSMIC", "Headset Mic",
+                        "Headset Mic", "Headset Mic Bias",
+                        "MAINMIC", "Main Handset Mic",
+                        "Main Handset Mic", "Main Mic Bias",
+                        "SUBMIC", "Sub Handset Mic",
+                        "Sub Handset Mic", "Main Mic Bias",
+                        "AFML", "Line In",
+                        "AFMR", "Line In",
+                        "DMic", "Digital Mic",
+                        "Digital Mic", "Digital Mic1 Bias";
+        };
 };
 
 &i2c1 {
@@ -81,6 +124,31 @@
                 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
                 interrupt-parent = <&gic>;
         };
+
+        twl6040: twl@4b {
+                compatible = "ti,twl6040";
+                reg = <0x4b>;
+                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
+                interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+                interrupt-parent = <&gic>;
+                ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
+
+                vio-supply = <&v1v8>;
+                v2v1-supply = <&v2v1>;
+                enable-active-high;
+
+                /* regulators for vibra motor */
+                vddvibl-supply = <&vbat>;
+                vddvibr-supply = <&vbat>;
+
+                vibra {
+                        /* Vibra driver, motor resistance parameters */
+                        ti,vibldrv-res = <8>;
+                        ti,vibrdrv-res = <3>;
+                        ti,viblmotor-res = <10>;
+                        ti,vibrmotor-res = <10>;
+                };
+        };
 };
 
 /include/ "twl6030.dtsi"
@@ -147,11 +215,11 @@
 };
 
 &mmc3 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc4 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc5 {
diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var_som.dts
new file mode 100644
index 00000000000..6601e6af609
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-var_som.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap4.dtsi"
+
+/ {
+        model = "Variscite OMAP4 SOM";
+        compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>; /* 1 GB */
+        };
+
+        vdd_eth: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "VDD_ETH";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                regulator-boot-on;
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
+                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupt-parent = <&gic>;
+        };
+};
+
+/include/ "twl6030.dtsi"
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&i2c3 {
+        clock-frequency = <400000>;
+
+        /*
+         * Temperature Sensor
+         * http://www.ti.com/lit/ds/symlink/tmp105.pdf
+         */
+        tmp105@49 {
+                compatible = "ti,tmp105";
+                reg = <0x49>;
+        };
+};
+
+&i2c4 {
+        clock-frequency = <400000>;
+};
+
+&mcspi1 {
+        eth@0 {
+                compatible = "ks8851";
+                spi-max-frequency = <24000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <11>; /* gpio line 171 */
+                vdd-supply = <&vdd_eth>;
+        };
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmc>;
+        ti,bus-width = <8>;
+        ti,non-removable;
+};
+
+&mmc2 {
+        status = "disabled";
+};
+
+&mmc3 {
+        status = "disabled";
+};
+
+&mmc4 {
+        status = "disabled";
+};
+
+&mmc5 {
+        ti,bus-width = <4>;
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 359c4979c8a..04cbbcb6ff9 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -272,5 +272,28 @@
                         ti,hwmods = "mmc5";
                         ti,needs-special-reset;
                 };
+
+                wdt2: wdt@4a314000 {
+                        compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+                        ti,hwmods = "wd_timer2";
+                };
+
+                mcpdm: mcpdm@40132000 {
+                        compatible = "ti,omap4-mcpdm";
+                        reg = <0x40132000 0x7f>, /* MPU private access */
+                              <0x49032000 0x7f>; /* L3 Interconnect */
+                        interrupts = <0 112 0x4>;
+                        interrupt-parent = <&gic>;
+                        ti,hwmods = "mcpdm";
+                };
+
+                dmic: dmic@4012e000 {
+                        compatible = "ti,omap4-dmic";
+                        reg = <0x4012e000 0x7f>, /* MPU private access */
+                              <0x4902e000 0x7f>; /* L3 Interconnect */
+                        interrupts = <0 114 0x4>;
+                        interrupt-parent = <&gic>;
+                        ti,hwmods = "dmic";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
new file mode 100644
index 00000000000..200c39ad1c8
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap5.dtsi"
+
+/ {
+        model = "TI OMAP5 EVM board";
+        compatible = "ti,omap5-evm", "ti,omap5";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>; /* 1 GB */
+        };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
new file mode 100644
index 00000000000..57e52708374
--- /dev/null
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/*
+ * Carveout for multimedia usecases
+ * It should be the last 48MB of the first 512MB memory part
+ * In theory, it should not even exist. That zone should be reserved
+ * dynamically during the .reserve callback.
+ */
+/memreserve/ 0x9d000000 0x03000000;
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "ti,omap5";
+        interrupt-parent = <&gic>;
+
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                serial5 = &uart6;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a15";
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a15";
+                };
+        };
+
+        /*
+         * The soc node represents the soc top level view. It is uses for IPs
+         * that are not memory mapped in the MPU view or for the MPU itself.
+         */
+        soc {
+                compatible = "ti,omap-infra";
+                mpu {
+                        compatible = "ti,omap5-mpu";
+                        ti,hwmods = "mpu";
+                };
+        };
+
+        /*
+         * XXX: Use a flat representation of the OMAP3 interconnect.
+         * The real OMAP interconnect network is quite complex.
+         * Since that will not bring real advantage to represent that in DT for
+         * the moment, just use a fake OCP bus entry to represent the whole bus
+         * hierarchy.
+         */
+        ocp {
+                compatible = "ti,omap4-l3-noc", "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
+
+                gic: interrupt-controller@48211000 {
+                        compatible = "arm,cortex-a15-gic";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0x48211000 0x1000>,
+                              <0x48212000 0x1000>;
+                };
+
+                gpio1: gpio@4ae10000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio1";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio2: gpio@48055000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio2";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio3: gpio@48057000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio3";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio4: gpio@48059000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio4";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio5: gpio@4805b000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio5";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio6: gpio@4805d000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio6";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio7: gpio@48051000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio7";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio8: gpio@48053000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio8";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                uart1: serial@4806a000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+
+                uart2: serial@4806c000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+
+                uart3: serial@48020000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+
+                uart4: serial@4806e000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
+
+                uart5: serial@48066000 {
+                        compatible = "ti,omap5-uart";
+                        ti,hwmods = "uart5";
+                        clock-frequency = <48000000>;
+                };
+
+                uart6: serial@48068000 {
+                        compatible = "ti,omap6-uart";
+                        ti,hwmods = "uart6";
+                        clock-frequency = <48000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index c4ff6d1a018..802ec5b2fd0 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -54,6 +54,17 @@
                         #address-cells = <1>;
                         #size-cells = <1>;
 
+                        nxp,wdr-clks = <14>;
+                        nxp,wwidth = <40000000>;
+                        nxp,whold = <100000000>;
+                        nxp,wsetup = <100000000>;
+                        nxp,rdr-clks = <14>;
+                        nxp,rwidth = <40000000>;
+                        nxp,rhold = <66666666>;
+                        nxp,rsetup = <100000000>;
+                        nand-on-flash-bbt;
+                        gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
                         mtd0@00000000 {
                                 label = "phy3250-boot";
                                 reg = <0x00000000 0x00064000>;
@@ -83,6 +94,14 @@
                 };
 
                 apb {
+                        uart5: serial@40090000 {
+                                status = "okay";
+                        };
+
+                        uart3: serial@40080000 {
+                                status = "okay";
+                        };
+
                         i2c1: i2c@400A0000 {
                                 clock-frequency = <100000>;
 
@@ -114,16 +133,58 @@
                         };
 
                         ssp0: ssp@20084000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                pl022,num-chipselects = <1>;
+                                cs-gpios = <&gpio 3 5 0>;
+
                                 eeprom: at25@0 {
+                                        pl022,hierarchy = <0>;
+                                        pl022,interface = <0>;
+                                        pl022,slave-tx-disable = <0>;
+                                        pl022,com-mode = <0>;
+                                        pl022,rx-level-trig = <1>;
+                                        pl022,tx-level-trig = <1>;
+                                        pl022,ctrl-len = <11>;
+                                        pl022,wait-state = <0>;
+                                        pl022,duplex = <0>;
+
+                                        at25,byte-len = <0x8000>;
+                                        at25,addr-mode = <2>;
+                                        at25,page-size = <64>;
+
                                         compatible = "atmel,at25";
+                                        reg = <0>;
+                                        spi-max-frequency = <5000000>;
                                 };
                         };
+
+                        sd@20098000 {
+                                wp-gpios = <&gpio 3 0 0>;
+                                cd-gpios = <&gpio 3 1 0>;
+                                cd-inverted;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
                 };
 
                 fab {
+                        uart2: serial@40018000 {
+                                status = "okay";
+                        };
+
                         tsc@40048000 {
                                 status = "okay";
                         };
+
+                        key@40050000 {
+                                status = "okay";
+                                keypad,num-rows = <1>;
+                                keypad,num-columns = <1>;
+                                nxp,debounce-delay-ms = <3>;
+                                nxp,scan-delay-ms = <34>;
+                                linux,keymap = <0x00000002>;
+                        };
                 };
         };
 
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
new file mode 100644
index 00000000000..798fa35c000
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Device Tree Source for the r8a7740 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "renesas,r8a7740";
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sh7377.dtsi b/arch/arm/boot/dts/sh7377.dtsi
new file mode 100644
index 00000000000..767ee0796da
--- /dev/null
+++ b/arch/arm/boot/dts/sh7377.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Device Tree Source for the sh7377 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "renesas,sh7377";
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index ec3c3397511..7e334d4cae2 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -77,6 +77,8 @@
                 used-led {
                         label = "user_led";
                         gpios = <&gpio4 14 0x4>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
                 };
         };
 
@@ -101,15 +103,30 @@
                         };
                 };
 
+                // External Micro SD slot
                 sdi@80126000 {
-                        status = "enabled";
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <8>;
+                        mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
+
+                        #gpio-cells = <1>;
                         cd-gpios  = <&gpio6 26 0x4>; // 218
+                        cd-inverted;
+
+                        status = "okay";
                 };
 
+                // On-board eMMC
                 sdi@80114000 {
-                        status = "enabled";
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <8>;
+                        mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
+
+                        status = "okay";
                 };
 
                 uart@80120000 {
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
new file mode 100644
index 00000000000..0772f5739f5
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -0,0 +1,147 @@
+/*
+ *  Copyright (C) 2012 Altera <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        aliases {
+                ethernet0 = &gmac0;
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                };
+        };
+
+        intc: intc@fffed000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0xfffed000 0x1000>,
+                      <0xfffec100 0x100>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                device_type = "soc";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        pdma: pdma@ffe01000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0xffe01000 0x1000>;
+                                interrupts = <0 180 4>;
+                        };
+                };
+
+                gmac0: stmmac@ff700000 {
+                        compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
+                        reg = <0xff700000 0x2000>;
+                        interrupts = <0 115 4>;
+                        interrupt-names = "macirq";
+                        mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
+                        phy-mode = "gmii";
+                };
+
+                L2: l2-cache@fffef000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xfffef000 0x1000>;
+                        interrupts = <0 38 0x04>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                /* Local timer */
+                timer@fffec600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0xfffec600 0x100>;
+                        interrupts = <1 13 0xf04>;
+                };
+
+                timer0: timer@ffc08000 {
+                        compatible = "snps,dw-apb-timer-sp";
+                        interrupts = <0 167 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffc08000 0x1000>;
+                };
+
+                timer1: timer@ffc09000 {
+                        compatible = "snps,dw-apb-timer-sp";
+                        interrupts = <0 168 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffc09000 0x1000>;
+                };
+
+                timer2: timer@ffd00000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        interrupts = <0 169 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffd00000 0x1000>;
+                };
+
+                timer3: timer@ffd01000 {
+                        compatible = "snps,dw-apb-timer-osc";
+                        interrupts = <0 170 4>;
+                        clock-frequency = <200000000>;
+                        reg = <0xffd01000 0x1000>;
+                };
+
+                uart0: uart@ffc02000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0xffc02000 0x1000>;
+                        clock-frequency = <7372800>;
+                        interrupts = <0 162 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+
+                uart1: uart@ffc03000 {
+                        compatible = "snps,dw-apb-uart";
+                        reg = <0xffc03000 0x1000>;
+                        clock-frequency = <7372800>;
+                        interrupts = <0 163 4>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dts
new file mode 100644
index 00000000000..ab7e4a94299
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dts
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+        model = "Altera SOCFPGA Cyclone V";
+        compatible = "altr,socfpga-cyclone5";
+
+        chosen {
+                bootargs = "console=ttyS0,57600";
+        };
+
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x0 0x10000000>; /* 256MB */
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 7de701365fc..f146dbf6f7f 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -307,7 +307,6 @@
                 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
-                support-8bit;
                 bus-width = <8>;
         };
 
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index bfeb117d5ae..684a9e1ff7e 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -301,7 +301,6 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                support-8bit;
                 bus-width = <8>;
         };
 
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 89cb7f2acd9..85e621ab296 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -64,11 +64,6 @@
                                 nvidia,pins = "dap4";
                                 nvidia,function = "dap4";
                         };
-                        ddc {
-                                nvidia,pins = "ddc", "owc", "spdi", "spdo",
-                                        "uac";
-                                nvidia,function = "rsvd2";
-                        };
                         dta {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
                                 nvidia,function = "vi";
@@ -129,14 +124,14 @@
                                         "lspi", "lvp1", "lvs";
                                 nvidia,function = "displaya";
                         };
+                        owc {
+                                nvidia,pins = "owc", "spdi", "spdo", "uac";
+                                nvidia,function = "rsvd2";
+                        };
                         pmc {
                                 nvidia,pins = "pmc";
                                 nvidia,function = "pwr_on";
                         };
-                        pta {
-                                nvidia,pins = "pta";
-                                nvidia,function = "i2c2";
-                        };
                         rm {
                                 nvidia,pins = "rm";
                                 nvidia,function = "i2c1";
@@ -176,7 +171,7 @@
                         conf_ata {
                                 nvidia,pins = "ata", "atb", "atc", "atd",
                                         "cdev1", "cdev2", "dap1", "dap2",
-                                        "dap4", "dtf", "gma", "gmc", "gmd",
+                                        "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
                                         "gme", "gpu", "gpu7", "i2cp", "irrx",
                                         "irtx", "pta", "rm", "sdc", "sdd",
                                         "slxd", "slxk", "spdi", "spdo", "uac",
@@ -185,7 +180,7 @@
                                 nvidia,tristate = <0>;
                         };
                         conf_ate {
-                                nvidia,pins = "ate", "csus", "dap3", "ddc",
+                                nvidia,pins = "ate", "csus", "dap3",
                                         "gpv", "owc", "slxc", "spib", "spid",
                                         "spie";
                                 nvidia,pull = <0>;
@@ -255,6 +250,39 @@
                                 nvidia,slew-rate-falling = <3>;
                         };
                 };
+
+                state_i2cmux_ddc: pinmux_i2cmux_ddc {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "rsvd4";
+                        };
+                };
+
+                state_i2cmux_pta: pinmux_i2cmux_pta {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "rsvd4";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "i2c2";
+                        };
+                };
+
+                state_i2cmux_idle: pinmux_i2cmux_idle {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "rsvd4";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "rsvd4";
+                        };
+                };
         };
 
         i2s@70002800 {
@@ -303,12 +331,37 @@
         i2c@7000c400 {
                 status = "okay";
                 clock-frequency = <100000>;
+        };
+
+        i2cmux {
+                compatible = "i2c-mux-pinctrl";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                i2c-parent = <&{/i2c@7000c400}>;
 
-                smart-battery@b {
-                        compatible = "ti,bq20z75", "smart-battery-1.1";
-                        reg = <0xb>;
-                        ti,i2c-retry-count = <2>;
-                        ti,poll-retry-count = <10>;
+                pinctrl-names = "ddc", "pta", "idle";
+                pinctrl-0 = <&state_i2cmux_ddc>;
+                pinctrl-1 = <&state_i2cmux_pta>;
+                pinctrl-2 = <&state_i2cmux_idle>;
+
+                i2c@0 {
+                        reg = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c@1 {
+                        reg = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        smart-battery@b {
+                                compatible = "ti,bq20z75", "smart-battery-1.1";
+                                reg = <0xb>;
+                                ti,i2c-retry-count = <2>;
+                                ti,poll-retry-count = <10>;
+                        };
                 };
         };
 
@@ -334,7 +387,7 @@
                 };
         };
 
-        emc {
+        memory-controller@0x7000f400 {
                 emc-table@190000 {
                         reg = <190000>;
                         compatible = "nvidia,tegra20-emc-table";
@@ -397,7 +450,6 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                support-8bit;
                 bus-width = <8>;
         };
 
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 9de5636023f..27fb8a67ea4 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -276,9 +276,11 @@
 
         usb@c5000000 {
                 status = "okay";
+                nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
         };
 
         usb@c5004000 {
+                status = "okay";
                 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
         };
 
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 445343b0fbd..be90544e6b5 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -314,7 +314,6 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                support-8bit;
                 bus-width = <8>;
         };
 
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
new file mode 100644
index 00000000000..6916310bf58
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -0,0 +1,301 @@
+/dts-v1/;
+
+/include/ "tegra20.dtsi"
+
+/ {
+        model = "NVIDIA Tegra2 Whistler evaluation board";
+        compatible = "nvidia,whistler", "nvidia,tegra20";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        pinmux {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
+                                        "gmc", "gmd", "gpu";
+                                nvidia,function = "gmi";
+                        };
+                        atc {
+                                nvidia,pins = "atc", "atd";
+                                nvidia,function = "sdio4";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "osc";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd";
+                                nvidia,function = "vi";
+                        };
+                        dte {
+                                nvidia,pins = "dte";
+                                nvidia,function = "rsvd1";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gme {
+                                nvidia,pins = "gme";
+                                nvidia,function = "dap5";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uartb";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        kbcb {
+                                nvidia,pins = "kbcb", "kbcd";
+                                nvidia,function = "sdio2";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
+                                        "spia", "spib", "spic";
+                                nvidia,function = "spi3";
+                        };
+                        ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldc", "ldi",
+                                        "lhp0", "lhp1", "lhp2", "lhs", "lm0",
+                                        "lm1", "lpp", "lpw0", "lpw1", "lpw2",
+                                        "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc", "uac";
+                                nvidia,function = "owr";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd", "slxa",
+                                        "slxc", "slxd", "slxk";
+                                nvidia,function = "sdio3";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        spdi {
+                                nvidia,pins = "spdi", "spdo";
+                                nvidia,function = "rsvd2";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        spif {
+                                nvidia,pins = "spif";
+                                nvidia,function = "spi2";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab";
+                                nvidia,function = "uarta";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        uda {
+                                nvidia,pins = "uda";
+                                nvidia,function = "spi1";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
+                                        "gmb", "gmc", "gmd", "irrx", "irtx",
+                                        "kbca", "kbcb", "kbcc", "kbcd", "kbce",
+                                        "kbcf", "sdc", "sdd", "spie", "spig",
+                                        "spih", "uaa", "uab", "uad", "uca",
+                                        "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_atd {
+                                nvidia,pins = "atd", "ate", "cdev1", "csus",
+                                        "dap1", "dap2", "dap3", "dap4", "dte",
+                                        "dtf", "gpu", "gpu7", "gpv", "i2cp",
+                                        "rm", "sdio1", "slxa", "slxc", "slxd",
+                                        "slxk", "spdi", "spdo", "uac", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_cdev2 {
+                                nvidia,pins = "cdev2", "spia", "spib";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "lc", "pmca",
+                                        "pmcb", "pmcc", "pmcd", "xm2c",
+                                        "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd",
+                                        "spid", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_gme {
+                                nvidia,pins = "gme", "owc", "pta", "spic";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                        conf_ls {
+                                nvidia,pins = "ls", "pmce";
+                                nvidia,pull = <2>;
+                        };
+                        drive_dap1 {
+                                nvidia,pins = "drive_dap1";
+                                nvidia,high-speed-mode = <0>;
+                                nvidia,schmitt = <1>;
+                                nvidia,low-power-mode = <0>;
+                                nvidia,pull-down-strength = <0>;
+                                nvidia,pull-up-strength = <0>;
+                                nvidia,slew-rate-rising = <0>;
+                                nvidia,slew-rate-falling = <0>;
+                        };
+                };
+        };
+
+        i2s@70002800 {
+                status = "okay";
+        };
+
+        serial@70006000 {
+                status = "okay";
+                clock-frequency = <216000000>;
+        };
+
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                codec: codec@1a {
+                        compatible = "wlf,wm8753";
+                        reg = <0x1a>;
+                };
+
+                tca6416: gpio@20 {
+                        compatible = "ti,tca6416";
+                        reg = <0x20>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+        };
+
+        usb@c5000000 {
+                status = "okay";
+                nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+        };
+
+        usb@c5008000 {
+                status = "okay";
+                nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+        };
+
+        sdhci@c8000400 {
+                status = "okay";
+                wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+                bus-width = <8>;
+        };
+
+        sdhci@c8000600 {
+                status = "okay";
+                bus-width = <8>;
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm8753-whistler",
+                             "nvidia,tegra-audio-wm8753";
+                nvidia,model = "NVIDIA Tegra Whistler";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "LOUT1",
+                        "Headphone Jack", "ROUT1",
+                        "MIC2", "Mic Jack",
+                        "MIC2N", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&codec>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c417d67e902..405d1673904 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -72,7 +72,7 @@
                 reg = <0x70002800 0x200>;
                 interrupts = <0 13 0x04>;
                 nvidia,dma-request-selector = <&apbdma 2>;
-                status = "disable";
+                status = "disabled";
         };
 
         tegra_i2s2: i2s@70002a00 {
@@ -80,7 +80,7 @@
                 reg = <0x70002a00 0x200>;
                 interrupts = <0 3 0x04>;
                 nvidia,dma-request-selector = <&apbdma 1>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006000 {
@@ -88,7 +88,7 @@
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
                 interrupts = <0 36 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006040 {
@@ -96,7 +96,7 @@
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
                 interrupts = <0 37 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006200 {
@@ -104,7 +104,7 @@
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 46 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006300 {
@@ -112,7 +112,7 @@
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 90 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006400 {
@@ -120,7 +120,13 @@
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 91 0x04>;
-                status = "disable";
+                status = "disabled";
+        };
+
+        pwm {
+                compatible = "nvidia,tegra20-pwm";
+                reg = <0x7000a000 0x100>;
+                #pwm-cells = <2>;
         };
 
         i2c@7000c000 {
@@ -129,7 +135,7 @@
                 interrupts = <0 38 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c400 {
@@ -138,7 +144,7 @@
                 interrupts = <0 84 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c500 {
@@ -147,7 +153,7 @@
                 interrupts = <0 92 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000d000 {
@@ -156,7 +162,7 @@
                 interrupts = <0 53 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         pmc {
@@ -164,7 +170,7 @@
                 reg = <0x7000e400 0x400>;
         };
 
-        mc {
+        memory-controller@0x7000f000 {
                 compatible = "nvidia,tegra20-mc";
                 reg = <0x7000f000 0x024
                        0x7000f03c 0x3c4>;
@@ -177,7 +183,7 @@
                        0x58000000 0x02000000>;  /* GART aperture */
         };
 
-        emc {
+        memory-controller@0x7000f400 {
                 compatible = "nvidia,tegra20-emc";
                 reg = <0x7000f400 0x200>;
                 #address-cells = <1>;
@@ -190,7 +196,7 @@
                 interrupts = <0 20 0x04>;
                 phy_type = "utmi";
                 nvidia,has-legacy-mode;
-                status = "disable";
+                status = "disabled";
         };
 
         usb@c5004000 {
@@ -198,7 +204,7 @@
                 reg = <0xc5004000 0x4000>;
                 interrupts = <0 21 0x04>;
                 phy_type = "ulpi";
-                status = "disable";
+                status = "disabled";
         };
 
         usb@c5008000 {
@@ -206,35 +212,35 @@
                 reg = <0xc5008000 0x4000>;
                 interrupts = <0 97 0x04>;
                 phy_type = "utmi";
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@c8000000 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000000 0x200>;
                 interrupts = <0 14 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@c8000200 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000200 0x200>;
                 interrupts = <0 15 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@c8000400 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000400 0x200>;
                 interrupts = <0 19 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@c8000600 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000600 0x200>;
                 interrupts = <0 31 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         pmu {
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts
index 36321bceec4..c169bced131 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu.dts
@@ -144,7 +144,6 @@
 
         sdhci@78000600 {
                 status = "okay";
-                support-8bit;
                 bus-width = <8>;
         };
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 2dcc09e784b..3e4334d14ef 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -82,7 +82,7 @@
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
                 interrupts = <0 36 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006040 {
@@ -90,7 +90,7 @@
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
                 interrupts = <0 37 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006200 {
@@ -98,7 +98,7 @@
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 46 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006300 {
@@ -106,7 +106,7 @@
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 90 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006400 {
@@ -114,7 +114,13 @@
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 91 0x04>;
-                status = "disable";
+                status = "disabled";
+        };
+
+        pwm {
+                compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
+                reg = <0x7000a000 0x100>;
+                #pwm-cells = <2>;
         };
 
         i2c@7000c000 {
@@ -123,7 +129,7 @@
                 interrupts = <0 38 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c400 {
@@ -132,7 +138,7 @@
                 interrupts = <0 84 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c500 {
@@ -141,7 +147,7 @@
                 interrupts = <0 92 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c700 {
@@ -150,7 +156,7 @@
                 interrupts = <0 120 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000d000 {
@@ -159,7 +165,7 @@
                 interrupts = <0 53 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         pmc {
@@ -167,7 +173,7 @@
                 reg = <0x7000e400 0x400>;
         };
 
-        mc {
+        memory-controller {
                 compatible = "nvidia,tegra30-mc";
                 reg = <0x7000f000 0x010
                        0x7000f03c 0x1b4
@@ -201,35 +207,35 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080300 0x100>;
                         nvidia,ahub-cif-ids = <4 4>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 tegra_i2s1: i2s@70080400 {
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080400 0x100>;
                         nvidia,ahub-cif-ids = <5 5>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 tegra_i2s2: i2s@70080500 {
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080500 0x100>;
                         nvidia,ahub-cif-ids = <6 6>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 tegra_i2s3: i2s@70080600 {
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080600 0x100>;
                         nvidia,ahub-cif-ids = <7 7>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 tegra_i2s4: i2s@70080700 {
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080700 0x100>;
                         nvidia,ahub-cif-ids = <8 8>;
-                        status = "disable";
+                        status = "disabled";
                 };
         };
 
@@ -237,28 +243,28 @@
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000000 0x200>;
                 interrupts = <0 14 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@78000200 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000200 0x200>;
                 interrupts = <0 15 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@78000400 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000400 0x200>;
                 interrupts = <0 19 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@78000600 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000600 0x200>;
                 interrupts = <0 31 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         pmu {
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 3b2f3510d7e..d351b27d721 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -66,6 +66,7 @@
 
         vcxio: regulator@8 {
                 compatible = "ti,twl6030-vcxio";
+                regulator-always-on;
         };
 
         vusb: regulator@9 {
@@ -74,10 +75,12 @@
 
         v1v8: regulator@10 {
                 compatible = "ti,twl6030-v1v8";
+                regulator-always-on;
         };
 
         v2v1: regulator@11 {
                 compatible = "ti,twl6030-v2v1";
+                regulator-always-on;
         };
 
         clk32kg: regulator@12 {
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 16076e2d093..d8a827bd2bf 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -55,6 +55,8 @@
                         reg-io-width = <4>;
                         smsc,irq-active-high;
                         smsc,irq-push-pull;
+                        vdd33a-supply = <&v2m_fixed_3v3>;
+                        vddvario-supply = <&v2m_fixed_3v3>;
                 };
 
                 usb@2,03000000 {
@@ -157,6 +159,7 @@
                         v2m_timer23: timer@120000 {
                                 compatible = "arm,sp804", "arm,primecell";
                                 reg = <0x120000 0x1000>;
+                                interrupts = <3>;
                         };
 
                         /* DVI I2C bus */
@@ -197,5 +200,13 @@
                                 interrupts = <14>;
                         };
                 };
+
+                v2m_fixed_3v3: fixedregulator@0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3V3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index a6c9c7c82d5..dba53fd026b 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -54,6 +54,8 @@
                         reg-io-width = <4>;
                         smsc,irq-active-high;
                         smsc,irq-push-pull;
+                        vdd33a-supply = <&v2m_fixed_3v3>;
+                        vddvario-supply = <&v2m_fixed_3v3>;
                 };
 
                 usb@3,03000000 {
@@ -156,6 +158,7 @@
                         v2m_timer23: timer@12000 {
                                 compatible = "arm,sp804", "arm,primecell";
                                 reg = <0x12000 0x1000>;
+                                interrupts = <3>;
                         };
 
                         /* DVI I2C bus */
@@ -196,5 +199,13 @@
                                 interrupts = <14>;
                         };
                 };
+
+                v2m_fixed_3v3: fixedregulator@0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3V3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 7e1091d91af..d12b34ca056 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -14,8 +14,8 @@
         arm,hbi = <0x237>;
         compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
         interrupt-parent = <&gic>;
-        #address-cells = <1>;
-        #size-cells = <1>;
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         chosen { };
 
@@ -47,23 +47,23 @@
 
         memory@80000000 {
                 device_type = "memory";
-                reg = <0x80000000 0x40000000>;
+                reg = <0 0x80000000 0 0x40000000>;
         };
 
         hdlcd@2b000000 {
                 compatible = "arm,hdlcd";
-                reg = <0x2b000000 0x1000>;
+                reg = <0 0x2b000000 0 0x1000>;
                 interrupts = <0 85 4>;
         };
 
         memory-controller@2b0a0000 {
                 compatible = "arm,pl341", "arm,primecell";
-                reg = <0x2b0a0000 0x1000>;
+                reg = <0 0x2b0a0000 0 0x1000>;
         };
 
         wdt@2b060000 {
                 compatible = "arm,sp805", "arm,primecell";
-                reg = <0x2b060000 0x1000>;
+                reg = <0 0x2b060000 0 0x1000>;
                 interrupts = <98>;
         };
 
@@ -72,23 +72,23 @@
                 #interrupt-cells = <3>;
                 #address-cells = <0>;
                 interrupt-controller;
-                reg = <0x2c001000 0x1000>,
-                      <0x2c002000 0x1000>,
-                      <0x2c004000 0x2000>,
-                      <0x2c006000 0x2000>;
+                reg = <0 0x2c001000 0 0x1000>,
+                      <0 0x2c002000 0 0x1000>,
+                      <0 0x2c004000 0 0x2000>,
+                      <0 0x2c006000 0 0x2000>;
                 interrupts = <1 9 0xf04>;
         };
 
         memory-controller@7ffd0000 {
                 compatible = "arm,pl354", "arm,primecell";
-                reg = <0x7ffd0000 0x1000>;
+                reg = <0 0x7ffd0000 0 0x1000>;
                 interrupts = <0 86 4>,
                              <0 87 4>;
         };
 
         dma@7ffb0000 {
                 compatible = "arm,pl330", "arm,primecell";
-                reg = <0x7ffb0000 0x1000>;
+                reg = <0 0x7ffb0000 0 0x1000>;
                 interrupts = <0 92 4>,
                              <0 88 4>,
                              <0 89 4>,
@@ -111,12 +111,12 @@
         };
 
         motherboard {
-                ranges = <0 0 0x08000000 0x04000000>,
-                         <1 0 0x14000000 0x04000000>,
-                         <2 0 0x18000000 0x04000000>,
-                         <3 0 0x1c000000 0x04000000>,
-                         <4 0 0x0c000000 0x04000000>,
-                         <5 0 0x10000000 0x04000000>;
+                ranges = <0 0 0 0x08000000 0x04000000>,
+                         <1 0 0 0x14000000 0x04000000>,
+                         <2 0 0 0x18000000 0x04000000>,
+                         <3 0 0 0x1c000000 0x04000000>,
+                         <4 0 0 0x0c000000 0x04000000>,
+                         <5 0 0 0x10000000 0x04000000>;
 
                 interrupt-map-mask = <0 0 63>;
                 interrupt-map = <0 0  0 &gic 0  0 4>,
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
new file mode 100644
index 00000000000..4890a81c546
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -0,0 +1,188 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A15x2 A7x3
+ * Cortex-A15_A7 MPCore (V2P-CA15_A7)
+ *
+ * HBI-0249A
+ */
+
+/dts-v1/;
+
+/ {
+        model = "V2P-CA15_CA7";
+        arm,hbi = <0x249>;
+        compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        chosen { };
+
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+                i2c0 = &v2m_i2c_dvi;
+                i2c1 = &v2m_i2c_pcie;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                };
+
+/* A7s disabled till big.LITTLE patches are available...
+                cpu2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x100>;
+                };
+
+                cpu3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x101>;
+                };
+
+                cpu4: cpu@4 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x102>;
+                };
+*/
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0 0x80000000 0 0x40000000>;
+        };
+
+        wdt@2a490000 {
+                compatible = "arm,sp805", "arm,primecell";
+                reg = <0 0x2a490000 0 0x1000>;
+                interrupts = <98>;
+        };
+
+        hdlcd@2b000000 {
+                compatible = "arm,hdlcd";
+                reg = <0 0x2b000000 0 0x1000>;
+                interrupts = <0 85 4>;
+        };
+
+        memory-controller@2b0a0000 {
+                compatible = "arm,pl341", "arm,primecell";
+                reg = <0 0x2b0a0000 0 0x1000>;
+        };
+
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0 0x2c001000 0 0x1000>,
+                      <0 0x2c002000 0 0x1000>,
+                      <0 0x2c004000 0 0x2000>,
+                      <0 0x2c006000 0 0x2000>;
+                interrupts = <1 9 0xf04>;
+        };
+
+        memory-controller@7ffd0000 {
+                compatible = "arm,pl354", "arm,primecell";
+                reg = <0 0x7ffd0000 0 0x1000>;
+                interrupts = <0 86 4>,
+                             <0 87 4>;
+        };
+
+        dma@7ff00000 {
+                compatible = "arm,pl330", "arm,primecell";
+                reg = <0 0x7ff00000 0 0x1000>;
+                interrupts = <0 92 4>,
+                             <0 88 4>,
+                             <0 89 4>,
+                             <0 90 4>,
+                             <0 91 4>;
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+                interrupts = <0 68 4>,
+                             <0 69 4>;
+        };
+
+        motherboard {
+                ranges = <0 0 0 0x08000000 0x04000000>,
+                         <1 0 0 0x14000000 0x04000000>,
+                         <2 0 0 0x18000000 0x04000000>,
+                         <3 0 0 0x1c000000 0x04000000>,
+                         <4 0 0 0x0c000000 0x04000000>,
+                         <5 0 0 0x10000000 0x04000000>;
+
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+        };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index aa07f5938f0..1143c4d5c56 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -452,6 +452,7 @@ static struct dma_map_ops dmabounce_ops = {
         .alloc                  = arm_dma_alloc,
         .free                   = arm_dma_free,
         .mmap                   = arm_dma_mmap,
+        .get_sgtable            = arm_dma_get_sgtable,
         .map_page               = dmabounce_map_page,
         .unmap_page             = dmabounce_unmap_page,
         .sync_single_for_cpu    = dmabounce_sync_for_cpu,
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig
index ddc9fe6a78a..90610c7030f 100644
--- a/arch/arm/configs/armadillo800eva_defconfig
+++ b/arch/arm/configs/armadillo800eva_defconfig
@@ -5,10 +5,7 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
 # CONFIG_UTS_NS is not set
 # CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
@@ -21,7 +18,7 @@ CONFIG_ARCH_SHMOBILE=y
 CONFIG_ARCH_R8A7740=y
 CONFIG_MACH_ARMADILLO800EVA=y
 # CONFIG_SH_TIMER_TMU is not set
-# CONFIG_ARM_THUMB is not set
+CONFIG_ARM_THUMB=y
 CONFIG_CPU_BPREDICT_DISABLE=y
 # CONFIG_CACHE_L2X0 is not set
 CONFIG_ARM_ERRATA_430973=y
@@ -36,9 +33,10 @@ CONFIG_AEABI=y
 CONFIG_FORCE_MAX_ZONEORDER=13
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"
+CONFIG_CMDLINE="console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"
 CONFIG_CMDLINE_FORCE=y
 CONFIG_KEXEC=y
+CONFIG_VFP=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_SUSPEND is not set
 CONFIG_NET=y
@@ -89,26 +87,32 @@ CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_I2C=y
 CONFIG_I2C_SH_MOBILE=y
 # CONFIG_HWMON is not set
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_VIDEO_DEV=y
+# CONFIG_RC_CORE is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+# CONFIG_V4L_USB_DRIVERS is not set
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_MT9T112=y
+CONFIG_VIDEO_SH_MOBILE_CEU=y
+# CONFIG_RADIO_ADAPTERS is not set
 CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_FB_SH_MOBILE_HDMI=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
 # CONFIG_SND_VERBOSE_PROCFS is not set
 # CONFIG_SND_DRIVERS is not set
 # CONFIG_SND_ARM is not set
-CONFIG_SND_SOC=y
 CONFIG_SND_SOC_SH4_FSI=y
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_RENESAS_USBHS=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_RENESAS_USBHS_UDC=y
@@ -116,6 +120,8 @@ CONFIG_USB_ETH=m
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_SH_MMCIF=y
+CONFIG_DMADEVICES=y
+CONFIG_SH_DMAE=y
 CONFIG_UIO=y
 CONFIG_UIO_PDRV_GENIRQ=y
 # CONFIG_DNOTIFY is not set
@@ -124,7 +130,6 @@ CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_NFS_V4_1=y
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
new file mode 100644
index 00000000000..e40b435d204
--- /dev/null
+++ b/arch/arm/configs/exynos_defconfig
@@ -0,0 +1,92 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_S3C_LOWLEVEL_UART_PORT=1
+CONFIG_S3C24XX_PWM=y
+CONFIG_ARCH_EXYNOS5=y
+CONFIG_MACH_EXYNOS4_DT=y
+CONFIG_MACH_EXYNOS5_DT=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_RFKILL_REGULATOR=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_NETDEVICES=y
+CONFIG_SMSC911X=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_SMSC75XX=y
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+# CONFIG_HWMON is not set
+CONFIG_MFD_TPS65090=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_FB=y
+CONFIG_EXYNOS_VIDEO=y
+CONFIG_EXYNOS_MIPI_DSI=y
+CONFIG_EXYNOS_DP=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_FONT_7x14=y
+CONFIG_LOGO=y
+CONFIG_USB=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CRAMFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index e05a2f1665a..78ed575feb1 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -2,7 +2,10 @@ CONFIG_EXPERIMENTAL=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
 CONFIG_EXPERT=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
@@ -36,8 +39,6 @@ CONFIG_MACH_IMX27IPCAM=y
 CONFIG_MACH_IMX27_DT=y
 CONFIG_MXC_IRQ_PRIOR=y
 CONFIG_MXC_PWM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -46,7 +47,6 @@ CONFIG_FPE_NWFPE=y
 CONFIG_FPE_NWFPE_XP=y
 CONFIG_PM_DEBUG=y
 CONFIG_NET=y
-CONFIG_SMSC911X=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
@@ -70,31 +70,31 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
 # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
 # CONFIG_MTD_CFI_I2 is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_MXC=y
 CONFIG_MTD_UBI=y
-CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
+CONFIG_ATA=y
+CONFIG_PATA_IMX=y
 CONFIG_NETDEVICES=y
 CONFIG_CS89x0=y
 CONFIG_CS89x0_PLATFORM=y
 CONFIG_DM9000=y
 CONFIG_SMC91X=y
 CONFIG_SMC911X=y
+CONFIG_SMSC911X=y
 CONFIG_SMSC_PHY=y
 # CONFIG_INPUT_MOUSEDEV is not set
 CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
+CONFIG_KEYBOARD_IMX=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=m
-CONFIG_TOUCHSCREEN_MC13783=m
-# CONFIG_SERIO is not set
+CONFIG_TOUCHSCREEN_MC13783=y
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=m
 CONFIG_SERIAL_IMX=y
@@ -113,31 +113,23 @@ CONFIG_HWMON=m
 CONFIG_SENSORS_MC13783_ADC=m
 CONFIG_WATCHDOG=y
 CONFIG_IMX2_WDT=y
-CONFIG_MFD_MC13XXX=y
+CONFIG_MFD_MC13XXX_SPI=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
-CONFIG_FB=y
-CONFIG_FB_IMX=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_LCD_L4F00242T03=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-CONFIG_VIDEO_MEDIA=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_CONTIG=y
-CONFIG_VIDEOBUF2_CORE=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_SOC_CAMERA=y
 CONFIG_SOC_CAMERA_OV2640=y
-CONFIG_VIDEO_MX2_HOSTSUPPORT=y
 CONFIG_VIDEO_MX2=y
+CONFIG_FB=y
+CONFIG_FB_IMX=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_L4F00242T03=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FONTS=y
@@ -152,13 +144,17 @@ CONFIG_SND_IMX_SOC=y
 CONFIG_SND_SOC_MX27VIS_AIC32X4=y
 CONFIG_SND_SOC_PHYCORE_AC97=y
 CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB_HID=m
 CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
 CONFIG_USB_ULPI=y
 CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
 CONFIG_MMC_MXC=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
@@ -173,22 +169,25 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_IMXDI=y
+CONFIG_RTC_DRV_MC13XXX=y
 CONFIG_RTC_DRV_MXC=y
 CONFIG_DMADEVICES=y
 CONFIG_IMX_SDMA=y
 CONFIG_IMX_DMA=y
+CONFIG_COMMON_CLK_DEBUG=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS=y
 # CONFIG_DNOTIFY is not set
 # CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_UBIFS_FS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=m
 CONFIG_NLS_CODEPAGE_850=m
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=m
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index b1d3675df72..3c9f32f9b6b 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -2,6 +2,8 @@ CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_KERNEL_LZO=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_CGROUPS=y
 CONFIG_RELAY=y
@@ -29,15 +31,12 @@ CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
 CONFIG_MACH_MX51_3DS=y
-CONFIG_MACH_EUKREA_CPUIMX51=y
 CONFIG_MACH_EUKREA_CPUIMX51SD=y
 CONFIG_MACH_MX51_EFIKAMX=y
 CONFIG_MACH_MX51_EFIKASB=y
 CONFIG_MACH_IMX53_DT=y
 CONFIG_SOC_IMX6Q=y
 CONFIG_MXC_PWM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
 CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
@@ -64,17 +63,29 @@ CONFIG_IPV6=y
 # CONFIG_WIRELESS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_SST25L=y
-# CONFIG_STANDALONE is not set
-CONFIG_CONNECTOR=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_GPMI_NAND=y
+CONFIG_MTD_NAND_MXC=y
+CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -105,8 +116,11 @@ CONFIG_SMSC911X=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_EVBUG=m
 CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_IMX=y
 CONFIG_MOUSE_PS2=m
 CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_MC13783=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_MMA8450=y
 CONFIG_SERIO_SERPORT=m
@@ -116,6 +130,7 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_SERIAL_IMX=y
 CONFIG_SERIAL_IMX_CONSOLE=y
 CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MXC_RNGA=y
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
 CONFIG_I2C_CHARDEV=y
@@ -130,42 +145,37 @@ CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_IMX2_WDT=y
-CONFIG_MFD_MC13XXX=y
+CONFIG_MFD_MC13XXX_SPI=y
+CONFIG_MFD_MC13XXX_I2C=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_V4L2=y
 CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF2_CORE=y
-CONFIG_VIDEOBUF2_MEMOPS=y
-CONFIG_VIDEOBUF2_DMA_CONTIG=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_SOC_CAMERA=y
 CONFIG_SOC_CAMERA_OV2640=y
-CONFIG_MX3_VIDEO=y
 CONFIG_VIDEO_MX3=y
 CONFIG_FB=y
-CONFIG_FB_MX3=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_L4F00242T03=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GENERIC=y
-CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 CONFIG_FONTS=y
 CONFIG_FONT_8x8=y
 CONFIG_FONT_8x16=y
 CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_PHYCORE_AC97=y
+CONFIG_SND_SOC_EUKREA_TLV320=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_MC13783=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
@@ -178,9 +188,13 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_MC13XXX=y
 CONFIG_RTC_DRV_MXC=y
 CONFIG_DMADEVICES=y
 CONFIG_IMX_SDMA=y
+CONFIG_MXS_DMA=y
+CONFIG_COMMON_CLK_DEBUG=y
+# CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -204,8 +218,9 @@ CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_CONFIGFS_FS=m
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
@@ -216,14 +231,11 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_ISO8859_15=m
 CONFIG_NLS_UTF8=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
 # CONFIG_FTRACE is not set
 # CONFIG_ARM_UNWIND is not set
 CONFIG_SECURITYFS=y
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 # CONFIG_CRYPTO_HW is not set
 CONFIG_CRC_CCITT=m
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
new file mode 100644
index 00000000000..26146ffea1a
--- /dev/null
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -0,0 +1,89 @@
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_EMEV2=y
+CONFIG_MACH_KZM9D=y
+CONFIG_MEMORY_START=0x40000000
+CONFIG_MEMORY_SIZE=0x10000000
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_SWP_EMULATE is not set
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_LOCAL_TIMERS is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+CONFIG_FORCE_MAX_ZONEORDER=13
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CMDLINE="console=tty0 console=ttyS1,115200n81 earlyprintk=serial8250-em.1,115200n81 mem=128M@0x40000000 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_EM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_EM=y
+# CONFIG_HWMON is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index e3ebc20ed0a..2388c861062 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -100,7 +100,12 @@ CONFIG_SND_SOC_SH4_FSI=y
 CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
 CONFIG_USB_R8A66597_HCD=y
+CONFIG_USB_RENESAS_USBHS=y
 CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_USB_ETH=m
+CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
 # CONFIG_MMC_BLOCK_BOUNCE is not set
 CONFIG_MMC_SDHI=y
@@ -108,12 +113,13 @@ CONFIG_MMC_SH_MMCIF=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_RS5C372=y
 CONFIG_DMADEVICES=y
 CONFIG_SH_DMAE=y
 CONFIG_ASYNC_TX_DMA=y
 CONFIG_STAGING=y
 # CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
+CONFIG_INOTIFY_USER=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 4fa60547494..e42a0e3d4c3 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -1,5 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
@@ -16,8 +18,7 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_LPC32XX=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -52,13 +53,17 @@ CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_MUSEUM_IDS=y
+CONFIG_MTD_NAND_SLC_LPC32XX=y
+CONFIG_MTD_NAND_MLC_LPC32XX=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
@@ -79,16 +84,23 @@ CONFIG_LPC_ENET=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_SMSC_PHY=y
 # CONFIG_WLAN is not set
+CONFIG_INPUT_MATRIXKMAP=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
 CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_LPC32XX=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_LPC32XX=y
+CONFIG_SERIO_LIBPS2=y
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_HS_LPC32XX=y
+CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
@@ -96,7 +108,8 @@ CONFIG_I2C_PNX=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
+CONFIG_SENSORS_DS620=y
+CONFIG_SENSORS_MAX6639=y
 CONFIG_WATCHDOG=y
 CONFIG_PNX4008_WATCHDOG=y
 CONFIG_FB=y
@@ -133,6 +146,8 @@ CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_PCA9532=y
+CONFIG_LEDS_PCA9532_GPIO=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
@@ -146,10 +161,10 @@ CONFIG_RTC_DRV_DS1374=y
 CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_LPC32XX=y
 CONFIG_DMADEVICES=y
-CONFIG_AMBA_PL08X=y
 CONFIG_STAGING=y
-CONFIG_IIO=y
 CONFIG_LPC32XX_ADC=y
+CONFIG_MAX517=y
+CONFIG_IIO=y
 CONFIG_EXT2_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y
@@ -159,7 +174,6 @@ CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_WBUF_VERIFY=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
new file mode 100644
index 00000000000..2e86b31c33c
--- /dev/null
+++ b/arch/arm/configs/mvebu_defconfig
@@ -0,0 +1,46 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_MACH_ARMADA_370_XP=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_USE_OF=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_VFP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_FS_XATTR is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_UTF8=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 5406c23a02e..4edcfb4e4de 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -28,12 +28,12 @@ CONFIG_MACH_MX28EVK=y
 CONFIG_MACH_STMP378X_DEVB=y
 CONFIG_MACH_TX28=y
 CONFIG_MACH_M28EVK=y
+CONFIG_MACH_APX4DEVKIT=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
 CONFIG_AUTO_ZRELADDR=y
 CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
@@ -58,6 +58,9 @@ CONFIG_CAN_FLEXCAN=m
 CONFIG_DEVTMPFS=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_BLK_DEV is not set
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_GPMI_NAND=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_ENC28J60=y
@@ -77,6 +80,7 @@ CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_MXS_AUART=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
@@ -109,8 +113,10 @@ CONFIG_MMC=y
 CONFIG_MMC_MXS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=m
+CONFIG_RTC_DRV_STMP=y
 CONFIG_DMADEVICES=y
 CONFIG_MXS_DMA=y
+CONFIG_COMMON_CLK_DEBUG=y
 CONFIG_EXT3_FS=y
 # CONFIG_DNOTIFY is not set
 CONFIG_FSCACHE=m
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 11828e63253..e58edc36b40 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -193,9 +193,12 @@ CONFIG_MMC_OMAP_HS=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_TWL92330=y
 CONFIG_RTC_DRV_TWL4030=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_OMAP=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_QUOTA=y
 CONFIG_QFMT_V2=y
 CONFIG_MSDOS_FS=y
@@ -235,3 +238,4 @@ CONFIG_CRC_T10DIF=y
 CONFIG_CRC_ITU_T=y
 CONFIG_CRC7=y
 CONFIG_LIBCRC32C=y
+CONFIG_SOC_OMAP5=y
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
new file mode 100644
index 00000000000..0ac1293dba1
--- /dev/null
+++ b/arch/arm/configs/socfpga_defconfig
@@ -0,0 +1,83 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_CGROUPS=y
+CONFIG_CPUSETS=y
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_MACH_SOCFPGA_CYCLONE5=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_NR_CPUS=2
+CONFIG_AEABI=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+CONFIG_STMMAC_ETH=y
+# CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_8250_DW=y
+# CONFIG_RTC_HCTOSYS is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_ENABLE_DEFAULT_TRACERS=y
+CONFIG_DEBUG_USER=y
+CONFIG_XZ_DEC=y
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 1d24f8458be..71277a1591b 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -7,7 +7,7 @@ CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EXPERT=y
 # CONFIG_KALLSYMS is not set
-# CONFIG_BUG is not set
+# CONFIG_BUGVERBOSE is not set
 # CONFIG_ELF_CORE is not set
 # CONFIG_SHMEM is not set
 CONFIG_SLOB=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 1198dd61c7c..db2245353f0 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -1,4 +1,6 @@
 CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_CGROUPS=y
@@ -25,14 +27,9 @@ CONFIG_ARCH_TEGRA=y
 CONFIG_ARCH_TEGRA_2x_SOC=y
 CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_MACH_HARMONY=y
-CONFIG_MACH_KAEN=y
 CONFIG_MACH_PAZ00=y
 CONFIG_MACH_TRIMSLICE=y
-CONFIG_MACH_WARIO=y
-CONFIG_MACH_VENTANA=y
 CONFIG_TEGRA_EMC_SCALING_ENABLE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
@@ -103,19 +100,25 @@ CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PINCTRL=y
 CONFIG_I2C_TEGRA=y
 CONFIG_SPI=y
 CONFIG_SPI_TEGRA=y
+CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_TPS6586X=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_BATTERY_SBS=y
 CONFIG_SENSORS_LM90=y
 CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_TPS62360=y
 CONFIG_REGULATOR_TPS6586X=y
+CONFIG_REGULATOR_TPS65910=y
 CONFIG_SOUND=y
 CONFIG_SND=y
 # CONFIG_SND_SUPPORT_OLD_API is not set
@@ -126,6 +129,7 @@ CONFIG_SND=y
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_TEGRA=y
+CONFIG_SND_SOC_TEGRA_WM8753=y
 CONFIG_SND_SOC_TEGRA_WM8903=y
 CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
 CONFIG_SND_SOC_TEGRA_ALC5632=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 2d4f661d1cf..da6845493ca 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -86,6 +86,7 @@ CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_LM3530=y
 CONFIG_LEDS_LP5521=y
+CONFIG_LEDS_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AB8500=y
 CONFIG_RTC_DRV_PL031=y
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index ed2e95d46e2..62e75475e57 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -1,7 +1,10 @@
 #ifndef __ASMARM_ARCH_TIMER_H
 #define __ASMARM_ARCH_TIMER_H
 
+#include <asm/errno.h>
+
 #ifdef CONFIG_ARM_ARCH_TIMER
+#define ARCH_HAS_READ_CURRENT_TIMER
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
 #else
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 004c1bc95d2..e4448e16046 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -215,7 +215,9 @@ static inline void vivt_flush_cache_mm(struct mm_struct *mm)
 static inline void
 vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 {
-        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
+        struct mm_struct *mm = vma->vm_mm;
+
+        if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm)))
                 __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
                                         vma->vm_flags);
 }
@@ -223,7 +225,9 @@ vivt_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned
 static inline void
 vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
 {
-        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
+        struct mm_struct *mm = vma->vm_mm;
+
+        if (!mm || cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm))) {
                 unsigned long addr = user_addr & PAGE_MASK;
                 __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
         }
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index b2deda18154..dc6145120de 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -6,9 +6,22 @@
 #ifndef __ASM_ARM_DELAY_H
 #define __ASM_ARM_DELAY_H
 
+#include <asm/memory.h>
 #include <asm/param.h>  /* HZ */
 
-extern void __delay(int loops);
+#define MAX_UDELAY_MS   2
+#define UDELAY_MULT     ((UL(2199023) * HZ) >> 11)
+#define UDELAY_SHIFT    30
+
+#ifndef __ASSEMBLY__
+
+extern struct arm_delay_ops {
+        void (*delay)(unsigned long);
+        void (*const_udelay)(unsigned long);
+        void (*udelay)(unsigned long);
+} arm_delay_ops;
+
+#define __delay(n)              arm_delay_ops.delay(n)
 
 /*
  * This function intentionally does not exist; if you see references to
@@ -23,22 +36,27 @@ extern void __bad_udelay(void);
  * division by multiplication: you don't have to worry about
  * loss of precision.
  *
- * Use only for very small delays ( < 1 msec).  Should probably use a
+ * Use only for very small delays ( < 2 msec).  Should probably use a
  * lookup table, really, as the multiplications take much too long with
  * short delays.  This is a "reasonable" implementation, though (and the
  * first constant multiplications gets optimized away if the delay is
  * a constant)
  */
-extern void __udelay(unsigned long usecs);
-extern void __const_udelay(unsigned long);
-
-#define MAX_UDELAY_MS 2
+#define __udelay(n)             arm_delay_ops.udelay(n)
+#define __const_udelay(n)       arm_delay_ops.const_udelay(n)
 
 #define udelay(n)                                                       \
         (__builtin_constant_p(n) ?                                      \
           ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() :              \
-                        __const_udelay((n) * ((2199023U*HZ)>>11))) :    \
+                        __const_udelay((n) * UDELAY_MULT)) :            \
           __udelay(n))
 
+/* Loop-based definitions for assembly code. */
+extern void __loop_delay(unsigned long loops);
+extern void __loop_udelay(unsigned long usecs);
+extern void __loop_const_udelay(unsigned long);
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* defined(_ARM_DELAY_H) */
 
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index bbef15d0489..5c44dcb0987 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -186,17 +186,6 @@ extern int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
                         void *cpu_addr, dma_addr_t dma_addr, size_t size,
                         struct dma_attrs *attrs);
 
-#define dma_mmap_coherent(d, v, c, h, s) dma_mmap_attrs(d, v, c, h, s, NULL)
-
-static inline int dma_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
-                                  void *cpu_addr, dma_addr_t dma_addr,
-                                  size_t size, struct dma_attrs *attrs)
-{
-        struct dma_map_ops *ops = get_dma_ops(dev);
-        BUG_ON(!ops);
-        return ops->mmap(dev, vma, cpu_addr, dma_addr, size, attrs);
-}
-
 static inline void *dma_alloc_writecombine(struct device *dev, size_t size,
                                        dma_addr_t *dma_handle, gfp_t flag)
 {
@@ -213,20 +202,19 @@ static inline void dma_free_writecombine(struct device *dev, size_t size,
         return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
 }
 
-static inline int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
-                      void *cpu_addr, dma_addr_t dma_addr, size_t size)
-{
-        DEFINE_DMA_ATTRS(attrs);
-        dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
-        return dma_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, &attrs);
-}
+/*
+ * This can be called during early boot to increase the size of the atomic
+ * coherent DMA pool above the default value of 256KiB. It must be called
+ * before postcore_initcall.
+ */
+extern void __init init_dma_coherent_pool_size(unsigned long size);
 
 /*
  * This can be called during boot to increase the size of the consistent
  * DMA region above it's default value of 2MB. It must be called before the
  * memory allocator is initialised, i.e. before any core_initcall.
  */
-extern void __init init_consistent_dma_size(unsigned long size);
+static inline void init_consistent_dma_size(unsigned long size) { }
 
 /*
  * For SA-1111, IXP425, and ADI systems  the dma-mapping functions are "magic"
@@ -280,6 +268,9 @@ extern void arm_dma_sync_sg_for_cpu(struct device *, struct scatterlist *, int,
                 enum dma_data_direction);
 extern void arm_dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
                 enum dma_data_direction);
+extern int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
+                void *cpu_addr, dma_addr_t dma_addr, size_t size,
+                struct dma_attrs *attrs);
 
 #endif /* __KERNEL__ */
 #endif
diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h
index e51b1e81df0..83eb2f77291 100644
--- a/arch/arm/include/asm/kmap_types.h
+++ b/arch/arm/include/asm/kmap_types.h
@@ -4,30 +4,6 @@
 /*
  * This is the "bare minimum".  AIO seems to require this.
  */
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_L1_CACHE,
-        KM_L2_CACHE,
-        KM_KDB,
-        KM_TYPE_NR
-};
-
-#ifdef CONFIG_DEBUG_HIGHMEM
-#define KM_NMI          (-1)
-#define KM_NMI_PTE      (-1)
-#define KM_IRQ_PTE      (-1)
-#endif
+#define KM_TYPE_NR 16
 
 #endif
diff --git a/arch/arm/include/asm/locks.h b/arch/arm/include/asm/locks.h
deleted file mode 100644
index ef4c897772d..00000000000
--- a/arch/arm/include/asm/locks.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- *  arch/arm/include/asm/locks.h
- *
- *  Copyright (C) 2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Interrupt safe locking assembler. 
- */
-#ifndef __ASM_PROC_LOCKS_H
-#define __ASM_PROC_LOCKS_H
-
-#if __LINUX_ARM_ARCH__ >= 6
-
-#define __down_op(ptr,fail)                     \
-        ({                                      \
-        __asm__ __volatile__(                   \
-        "@ down_op\n"                           \
-"1:     ldrex   lr, [%0]\n"                     \
-"       sub     lr, lr, %1\n"                   \
-"       strex   ip, lr, [%0]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       teq     lr, #0\n"                       \
-"       movmi   ip, %0\n"                       \
-"       blmi    " #fail                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        })
-
-#define __down_op_ret(ptr,fail)                 \
-        ({                                      \
-                unsigned int ret;               \
-        __asm__ __volatile__(                   \
-        "@ down_op_ret\n"                       \
-"1:     ldrex   lr, [%1]\n"                     \
-"       sub     lr, lr, %2\n"                   \
-"       strex   ip, lr, [%1]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       teq     lr, #0\n"                       \
-"       movmi   ip, %1\n"                       \
-"       movpl   ip, #0\n"                       \
-"       blmi    " #fail "\n"                    \
-"       mov     %0, ip"                         \
-        : "=&r" (ret)                           \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        ret;                                    \
-        })
-
-#define __up_op(ptr,wake)                       \
-        ({                                      \
-        smp_mb();                               \
-        __asm__ __volatile__(                   \
-        "@ up_op\n"                             \
-"1:     ldrex   lr, [%0]\n"                     \
-"       add     lr, lr, %1\n"                   \
-"       strex   ip, lr, [%0]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       cmp     lr, #0\n"                       \
-"       movle   ip, %0\n"                       \
-"       blle    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        })
-
-/*
- * The value 0x01000000 supports up to 128 processors and
- * lots of processes.  BIAS must be chosen such that sub'ing
- * BIAS once per CPU will result in the long remaining
- * negative.
- */
-#define RW_LOCK_BIAS      0x01000000
-#define RW_LOCK_BIAS_STR "0x01000000"
-
-#define __down_op_write(ptr,fail)               \
-        ({                                      \
-        __asm__ __volatile__(                   \
-        "@ down_op_write\n"                     \
-"1:     ldrex   lr, [%0]\n"                     \
-"       sub     lr, lr, %1\n"                   \
-"       strex   ip, lr, [%0]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       teq     lr, #0\n"                       \
-"       movne   ip, %0\n"                       \
-"       blne    " #fail                         \
-        :                                       \
-        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        })
-
-#define __up_op_write(ptr,wake)                 \
-        ({                                      \
-        smp_mb();                               \
-        __asm__ __volatile__(                   \
-        "@ up_op_write\n"                       \
-"1:     ldrex   lr, [%0]\n"                     \
-"       adds    lr, lr, %1\n"                   \
-"       strex   ip, lr, [%0]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       movcs   ip, %0\n"                       \
-"       blcs    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc");                    \
-        })
-
-#define __down_op_read(ptr,fail)                \
-        __down_op(ptr, fail)
-
-#define __up_op_read(ptr,wake)                  \
-        ({                                      \
-        smp_mb();                               \
-        __asm__ __volatile__(                   \
-        "@ up_op_read\n"                        \
-"1:     ldrex   lr, [%0]\n"                     \
-"       add     lr, lr, %1\n"                   \
-"       strex   ip, lr, [%0]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       teq     lr, #0\n"                       \
-"       moveq   ip, %0\n"                       \
-"       bleq    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        })
-
-#else
-
-#define __down_op(ptr,fail)                     \
-        ({                                      \
-        __asm__ __volatile__(                   \
-        "@ down_op\n"                           \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%0]\n"                     \
-"       subs    lr, lr, %1\n"                   \
-"       str     lr, [%0]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       movmi   ip, %0\n"                       \
-"       blmi    " #fail                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        })
-
-#define __down_op_ret(ptr,fail)                 \
-        ({                                      \
-                unsigned int ret;               \
-        __asm__ __volatile__(                   \
-        "@ down_op_ret\n"                       \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%1]\n"                     \
-"       subs    lr, lr, %2\n"                   \
-"       str     lr, [%1]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       movmi   ip, %1\n"                       \
-"       movpl   ip, #0\n"                       \
-"       blmi    " #fail "\n"                    \
-"       mov     %0, ip"                         \
-        : "=&r" (ret)                           \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        ret;                                    \
-        })
-
-#define __up_op(ptr,wake)                       \
-        ({                                      \
-        smp_mb();                               \
-        __asm__ __volatile__(                   \
-        "@ up_op\n"                             \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%0]\n"                     \
-"       adds    lr, lr, %1\n"                   \
-"       str     lr, [%0]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       movle   ip, %0\n"                       \
-"       blle    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        })
-
-/*
- * The value 0x01000000 supports up to 128 processors and
- * lots of processes.  BIAS must be chosen such that sub'ing
- * BIAS once per CPU will result in the long remaining
- * negative.
- */
-#define RW_LOCK_BIAS      0x01000000
-#define RW_LOCK_BIAS_STR "0x01000000"
-
-#define __down_op_write(ptr,fail)               \
-        ({                                      \
-        __asm__ __volatile__(                   \
-        "@ down_op_write\n"                     \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%0]\n"                     \
-"       subs    lr, lr, %1\n"                   \
-"       str     lr, [%0]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       movne   ip, %0\n"                       \
-"       blne    " #fail                         \
-        :                                       \
-        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        })
-
-#define __up_op_write(ptr,wake)                 \
-        ({                                      \
-        __asm__ __volatile__(                   \
-        "@ up_op_write\n"                       \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%0]\n"                     \
-"       adds    lr, lr, %1\n"                   \
-"       str     lr, [%0]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       movcs   ip, %0\n"                       \
-"       blcs    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        })
-
-#define __down_op_read(ptr,fail)                \
-        __down_op(ptr, fail)
-
-#define __up_op_read(ptr,wake)                  \
-        ({                                      \
-        smp_mb();                               \
-        __asm__ __volatile__(                   \
-        "@ up_op_read\n"                        \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%0]\n"                     \
-"       adds    lr, lr, %1\n"                   \
-"       str     lr, [%0]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       moveq   ip, %0\n"                       \
-"       bleq    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        })
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index febe495d0c6..15cb035309f 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -17,7 +17,7 @@ struct seq_file;
 /*
  * This is internal.  Do not use it.
  */
-extern void init_FIQ(void);
+extern void init_FIQ(int);
 extern int show_fiq_list(struct seq_file *, int);
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index fcb575747e5..e965f1b560f 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -16,7 +16,7 @@
 #include <linux/compiler.h>
 #include <linux/const.h>
 #include <linux/types.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #ifdef CONFIG_NEED_MACH_MEMORY_H
 #include <mach/memory.h>
diff --git a/arch/arm/include/asm/mutex.h b/arch/arm/include/asm/mutex.h
index 93226cf23ae..b1479fd04a9 100644
--- a/arch/arm/include/asm/mutex.h
+++ b/arch/arm/include/asm/mutex.h
@@ -7,121 +7,10 @@
  */
 #ifndef _ASM_MUTEX_H
 #define _ASM_MUTEX_H
-
-#if __LINUX_ARM_ARCH__ < 6
-/* On pre-ARMv6 hardware the swp based implementation is the most efficient. */
-# include <asm-generic/mutex-xchg.h>
-#else
-
 /*
- * Attempting to lock a mutex on ARMv6+ can be done with a bastardized
- * atomic decrement (it is not a reliable atomic decrement but it satisfies
- * the defined semantics for our purpose, while being smaller and faster
- * than a real atomic decrement or atomic swap.  The idea is to attempt
- * decrementing the lock value only once.  If once decremented it isn't zero,
- * or if its store-back fails due to a dispute on the exclusive store, we
- * simply bail out immediately through the slow path where the lock will be
- * reattempted until it succeeds.
+ * On pre-ARMv6 hardware this results in a swp-based implementation,
+ * which is the most efficient. For ARMv6+, we emit a pair of exclusive
+ * accesses instead.
  */
-static inline void
-__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
-{
-        int __ex_flag, __res;
-
-        __asm__ (
-
-                "ldrex  %0, [%2]        \n\t"
-                "sub    %0, %0, #1      \n\t"
-                "strex  %1, %0, [%2]    "
-
-                : "=&r" (__res), "=&r" (__ex_flag)
-                : "r" (&(count)->counter)
-                : "cc","memory" );
-
-        __res |= __ex_flag;
-        if (unlikely(__res != 0))
-                fail_fn(count);
-}
-
-static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-        int __ex_flag, __res;
-
-        __asm__ (
-
-                "ldrex  %0, [%2]        \n\t"
-                "sub    %0, %0, #1      \n\t"
-                "strex  %1, %0, [%2]    "
-
-                : "=&r" (__res), "=&r" (__ex_flag)
-                : "r" (&(count)->counter)
-                : "cc","memory" );
-
-        __res |= __ex_flag;
-        if (unlikely(__res != 0))
-                __res = fail_fn(count);
-        return __res;
-}
-
-/*
- * Same trick is used for the unlock fast path. However the original value,
- * rather than the result, is used to test for success in order to have
- * better generated assembly.
- */
-static inline void
-__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
-{
-        int __ex_flag, __res, __orig;
-
-        __asm__ (
-
-                "ldrex  %0, [%3]        \n\t"
-                "add    %1, %0, #1      \n\t"
-                "strex  %2, %1, [%3]    "
-
-                : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag)
-                : "r" (&(count)->counter)
-                : "cc","memory" );
-
-        __orig |= __ex_flag;
-        if (unlikely(__orig != 0))
-                fail_fn(count);
-}
-
-/*
- * If the unlock was done on a contended lock, or if the unlock simply fails
- * then the mutex remains locked.
- */
-#define __mutex_slowpath_needs_to_unlock()      1
-
-/*
- * For __mutex_fastpath_trylock we use another construct which could be
- * described as a "single value cmpxchg".
- *
- * This provides the needed trylock semantics like cmpxchg would, but it is
- * lighter and less generic than a true cmpxchg implementation.
- */
-static inline int
-__mutex_fastpath_trylock(atomic_t *count, int (*fail_fn)(atomic_t *))
-{
-        int __ex_flag, __res, __orig;
-
-        __asm__ (
-
-                "1: ldrex       %0, [%3]        \n\t"
-                "subs           %1, %0, #1      \n\t"
-                "strexeq        %2, %1, [%3]    \n\t"
-                "movlt          %0, #0          \n\t"
-                "cmpeq          %2, #0          \n\t"
-                "bgt            1b              "
-
-                : "=&r" (__orig), "=&r" (__res), "=&r" (__ex_flag)
-                : "r" (&count->counter)
-                : "cc", "memory" );
-
-        return __orig;
-}
-
-#endif
+#include <asm-generic/mutex-xchg.h>
 #endif
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 00cbe10a50e..e074948d814 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,21 +12,6 @@
 #ifndef __ARM_PERF_EVENT_H__
 #define __ARM_PERF_EVENT_H__
 
-/* ARM perf PMU IDs for use by internal perf clients. */
-enum arm_perf_pmu_ids {
-        ARM_PERF_PMU_ID_XSCALE1 = 0,
-        ARM_PERF_PMU_ID_XSCALE2,
-        ARM_PERF_PMU_ID_V6,
-        ARM_PERF_PMU_ID_V6MP,
-        ARM_PERF_PMU_ID_CA8,
-        ARM_PERF_PMU_ID_CA9,
-        ARM_PERF_PMU_ID_CA5,
-        ARM_PERF_PMU_ID_CA15,
-        ARM_PERF_PMU_ID_CA7,
-        ARM_NUM_PMU_IDS,
-};
-
-extern enum arm_perf_pmu_ids
-armpmu_get_pmu_id(void);
+/* Nothing to see here... */
 
 #endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index f66626d71e7..41dc31f834c 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -195,6 +195,18 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 
 #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
 
+#define pte_none(pte)           (!pte_val(pte))
+#define pte_present(pte)        (pte_val(pte) & L_PTE_PRESENT)
+#define pte_write(pte)          (!(pte_val(pte) & L_PTE_RDONLY))
+#define pte_dirty(pte)          (pte_val(pte) & L_PTE_DIRTY)
+#define pte_young(pte)          (pte_val(pte) & L_PTE_YOUNG)
+#define pte_exec(pte)           (!(pte_val(pte) & L_PTE_XN))
+#define pte_special(pte)        (0)
+
+#define pte_present_user(pte) \
+        ((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \
+         (L_PTE_PRESENT | L_PTE_USER))
+
 #if __LINUX_ARM_ARCH__ < 6
 static inline void __sync_icache_dcache(pte_t pteval)
 {
@@ -206,25 +218,15 @@ extern void __sync_icache_dcache(pte_t pteval);
 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
                               pte_t *ptep, pte_t pteval)
 {
-        if (addr >= TASK_SIZE)
-                set_pte_ext(ptep, pteval, 0);
-        else {
+        unsigned long ext = 0;
+
+        if (addr < TASK_SIZE && pte_present_user(pteval)) {
                 __sync_icache_dcache(pteval);
-                set_pte_ext(ptep, pteval, PTE_EXT_NG);
+                ext |= PTE_EXT_NG;
         }
-}
 
-#define pte_none(pte)           (!pte_val(pte))
-#define pte_present(pte)        (pte_val(pte) & L_PTE_PRESENT)
-#define pte_write(pte)          (!(pte_val(pte) & L_PTE_RDONLY))
-#define pte_dirty(pte)          (pte_val(pte) & L_PTE_DIRTY)
-#define pte_young(pte)          (pte_val(pte) & L_PTE_YOUNG)
-#define pte_exec(pte)           (!(pte_val(pte) & L_PTE_XN))
-#define pte_special(pte)        (0)
-
-#define pte_present_user(pte) \
-        ((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \
-         (L_PTE_PRESENT | L_PTE_USER))
+        set_pte_ext(ptep, pteval, ext);
+}
 
 #define PTE_BIT_FUNC(fn,op) \
 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
@@ -251,13 +253,13 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
  *
  *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
  *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- *   <--------------- offset --------------------> <- type --> 0 0 0
+ *   <--------------- offset ----------------------> < type -> 0 0 0
  *
- * This gives us up to 63 swap files and 32GB per swap file.  Note that
+ * This gives us up to 31 swap files and 64GB per swap file.  Note that
  * the offset field is always non-zero.
  */
 #define __SWP_TYPE_SHIFT        3
-#define __SWP_TYPE_BITS         6
+#define __SWP_TYPE_BITS         5
 #define __SWP_TYPE_MASK         ((1 << __SWP_TYPE_BITS) - 1)
 #define __SWP_OFFSET_SHIFT      (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
 
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 90114faa9f3..4432305f4a2 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -103,10 +103,9 @@ struct pmu_hw_events {
 
 struct arm_pmu {
         struct pmu      pmu;
-        enum arm_perf_pmu_ids id;
         enum arm_pmu_type type;
         cpumask_t       active_irqs;
-        const char      *name;
+        char            *name;
         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
         void            (*enable)(struct hw_perf_event *evt, int idx);
         void            (*disable)(struct hw_perf_event *evt, int idx);
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h
index e3f75726343..05b8e82ec9f 100644
--- a/arch/arm/include/asm/sched_clock.h
+++ b/arch/arm/include/asm/sched_clock.h
@@ -10,5 +10,7 @@
 
 extern void sched_clock_postinit(void);
 extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate);
+extern void setup_sched_clock_needs_suspend(u32 (*read)(void), int bits,
+                unsigned long rate);
 
 #endif
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 23ebc0c82a3..24d284a1bfc 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -196,7 +196,7 @@ static const struct tagtable __tagtable_##fn __tag = { tag, fn }
 
 struct membank {
         phys_addr_t start;
-        unsigned long size;
+        phys_addr_t size;
         unsigned int highmem;
 };
 
@@ -217,7 +217,7 @@ extern struct meminfo meminfo;
 #define bank_phys_end(bank)     ((bank)->start + (bank)->size)
 #define bank_phys_size(bank)    (bank)->size
 
-extern int arm_add_memory(phys_addr_t start, unsigned long size);
+extern int arm_add_memory(phys_addr_t start, phys_addr_t size);
 extern void early_print(const char *str, ...);
 extern void dump_machine_table(void);
 
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index 65fa3c88095..b4ca707d0a6 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -59,18 +59,13 @@ static inline void dsb_sev(void)
 }
 
 /*
- * ARMv6 Spin-locking.
+ * ARMv6 ticket-based spin-locking.
  *
- * We exclusively read the old value.  If it is zero, we may have
- * won the lock, so we try exclusively storing it.  A memory barrier
- * is required after we get a lock, and before we release it, because
- * V6 CPUs are assumed to have weakly ordered memory.
- *
- * Unlocked value: 0
- * Locked value: 1
+ * A memory barrier is required after we get a lock, and before we
+ * release it, because V6 CPUs are assumed to have weakly ordered
+ * memory.
  */
 
-#define arch_spin_is_locked(x)          ((x)->lock != 0)
 #define arch_spin_unlock_wait(lock) \
         do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
 
@@ -79,31 +74,39 @@ static inline void dsb_sev(void)
 static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
+        u32 newval;
+        arch_spinlock_t lockval;
 
         __asm__ __volatile__(
-"1:     ldrex   %0, [%1]\n"
-"       teq     %0, #0\n"
-        WFE("ne")
-"       strexeq %0, %2, [%1]\n"
-"       teqeq   %0, #0\n"
+"1:     ldrex   %0, [%3]\n"
+"       add     %1, %0, %4\n"
+"       strex   %2, %1, [%3]\n"
+"       teq     %2, #0\n"
 "       bne     1b"
-        : "=&r" (tmp)
-        : "r" (&lock->lock), "r" (1)
+        : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
+        : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
         : "cc");
 
+        while (lockval.tickets.next != lockval.tickets.owner) {
+                wfe();
+                lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
+        }
+
         smp_mb();
 }
 
 static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
+        u32 slock;
 
         __asm__ __volatile__(
-"       ldrex   %0, [%1]\n"
-"       teq     %0, #0\n"
-"       strexeq %0, %2, [%1]"
-        : "=&r" (tmp)
-        : "r" (&lock->lock), "r" (1)
+"       ldrex   %0, [%2]\n"
+"       subs    %1, %0, %0, ror #16\n"
+"       addeq   %0, %0, %3\n"
+"       strexeq %1, %0, [%2]"
+        : "=&r" (slock), "=&r" (tmp)
+        : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
         : "cc");
 
         if (tmp == 0) {
@@ -116,17 +119,38 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
 
 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
+        unsigned long tmp;
+        u32 slock;
+
         smp_mb();
 
         __asm__ __volatile__(
-"       str     %1, [%0]\n"
-        :
-        : "r" (&lock->lock), "r" (0)
+"       mov     %1, #1\n"
+"1:     ldrex   %0, [%2]\n"
+"       uadd16  %0, %0, %1\n"
+"       strex   %1, %0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (slock), "=&r" (tmp)
+        : "r" (&lock->slock)
         : "cc");
 
         dsb_sev();
 }
 
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
+{
+        struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
+        return tickets.owner != tickets.next;
+}
+
+static inline int arch_spin_is_contended(arch_spinlock_t *lock)
+{
+        struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
+        return (tickets.next - tickets.owner) > 1;
+}
+#define arch_spin_is_contended  arch_spin_is_contended
+
 /*
  * RWLOCKS
  *
@@ -158,7 +182,7 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
         unsigned long tmp;
 
         __asm__ __volatile__(
-"1:     ldrex   %0, [%1]\n"
+"       ldrex   %0, [%1]\n"
 "       teq     %0, #0\n"
 "       strexeq %0, %2, [%1]"
         : "=&r" (tmp)
@@ -244,7 +268,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
         unsigned long tmp, tmp2 = 1;
 
         __asm__ __volatile__(
-"1:     ldrex   %0, [%2]\n"
+"       ldrex   %0, [%2]\n"
 "       adds    %0, %0, #1\n"
 "       strexpl %1, %0, [%2]\n"
         : "=&r" (tmp), "+r" (tmp2)
diff --git a/arch/arm/include/asm/spinlock_types.h b/arch/arm/include/asm/spinlock_types.h
index d14d197ae04..b262d2f8b47 100644
--- a/arch/arm/include/asm/spinlock_types.h
+++ b/arch/arm/include/asm/spinlock_types.h
@@ -5,11 +5,24 @@
 # error "please don't include this file directly"
 #endif
 
+#define TICKET_SHIFT    16
+
 typedef struct {
-        volatile unsigned int lock;
+        union {
+                u32 slock;
+                struct __raw_tickets {
+#ifdef __ARMEB__
+                        u16 next;
+                        u16 owner;
+#else
+                        u16 owner;
+                        u16 next;
+#endif
+                } tickets;
+        };
 } arch_spinlock_t;
 
-#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { { 0 } }
 
 typedef struct {
         volatile unsigned int lock;
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index 3be8de3adab..ce119442277 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -12,13 +12,15 @@
 #ifndef _ASMARM_TIMEX_H
 #define _ASMARM_TIMEX_H
 
+#include <asm/arch_timer.h>
 #include <mach/timex.h>
 
 typedef unsigned long cycles_t;
 
-static inline cycles_t get_cycles (void)
-{
-        return 0;
-}
+#ifdef ARCH_HAS_READ_CURRENT_TIMER
+#define get_cycles()    ({ cycles_t c; read_current_timer(&c) ? 0 : c; })
+#else
+#define get_cycles()    (0)
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 71f6536d17a..479a6352e0b 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -189,6 +189,9 @@ static inline void set_fs(mm_segment_t fs)
 
 #define access_ok(type,addr,size)       (__range_ok(addr,size) == 0)
 
+#define user_addr_max() \
+        (segment_eq(get_fs(), USER_DS) ? TASK_SIZE : ~0UL)
+
 /*
  * The "__xxx" versions of the user access functions do not verify the
  * address space - it must have been done previously with a separate
@@ -398,9 +401,6 @@ extern unsigned long __must_check __clear_user_std(void __user *addr, unsigned l
 #define __clear_user(addr,n)            (memset((void __force *)addr, 0, n), 0)
 #endif
 
-extern unsigned long __must_check __strncpy_from_user(char *to, const char __user *from, unsigned long count);
-extern unsigned long __must_check __strnlen_user(const char __user *s, long n);
-
 static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n)
 {
         if (access_ok(VERIFY_READ, from, n))
@@ -427,24 +427,9 @@ static inline unsigned long __must_check clear_user(void __user *to, unsigned lo
         return n;
 }
 
-static inline long __must_check strncpy_from_user(char *dst, const char __user *src, long count)
-{
-        long res = -EFAULT;
-        if (access_ok(VERIFY_READ, src, 1))
-                res = __strncpy_from_user(dst, src, count);
-        return res;
-}
-
-#define strlen_user(s)  strnlen_user(s, ~0UL >> 1)
+extern long strncpy_from_user(char *dest, const char __user *src, long count);
 
-static inline long __must_check strnlen_user(const char __user *s, long n)
-{
-        unsigned long res = 0;
-
-        if (__addr_ok(s))
-                res = __strnlen_user(s, n);
-
-        return res;
-}
+extern __must_check long strlen_user(const char __user *str);
+extern __must_check long strnlen_user(const char __user *str, long n);
 
 #endif /* _ASMARM_UACCESS_H */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 512cd147345..0cab47d4a83 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -446,7 +446,6 @@
 
 #ifdef __KERNEL__
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_GETHOSTNAME
 #define __ARCH_WANT_SYS_PAUSE
diff --git a/arch/arm/include/asm/word-at-a-time.h b/arch/arm/include/asm/word-at-a-time.h
new file mode 100644
index 00000000000..4d52f92967a
--- /dev/null
+++ b/arch/arm/include/asm/word-at-a-time.h
@@ -0,0 +1,96 @@
+#ifndef __ASM_ARM_WORD_AT_A_TIME_H
+#define __ASM_ARM_WORD_AT_A_TIME_H
+
+#ifndef __ARMEB__
+
+/*
+ * Little-endian word-at-a-time zero byte handling.
+ * Heavily based on the x86 algorithm.
+ */
+#include <linux/kernel.h>
+
+struct word_at_a_time {
+        const unsigned long one_bits, high_bits;
+};
+
+#define WORD_AT_A_TIME_CONSTANTS { REPEAT_BYTE(0x01), REPEAT_BYTE(0x80) }
+
+static inline unsigned long has_zero(unsigned long a, unsigned long *bits,
+                                     const struct word_at_a_time *c)
+{
+        unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits;
+        *bits = mask;
+        return mask;
+}
+
+#define prep_zero_mask(a, bits, c) (bits)
+
+static inline unsigned long create_zero_mask(unsigned long bits)
+{
+        bits = (bits - 1) & ~bits;
+        return bits >> 7;
+}
+
+static inline unsigned long find_zero(unsigned long mask)
+{
+        unsigned long ret;
+
+#if __LINUX_ARM_ARCH__ >= 5
+        /* We have clz available. */
+        ret = fls(mask) >> 3;
+#else
+        /* (000000 0000ff 00ffff ffffff) -> ( 1 1 2 3 ) */
+        ret = (0x0ff0001 + mask) >> 23;
+        /* Fix the 1 for 00 case */
+        ret &= mask;
+#endif
+
+        return ret;
+}
+
+#ifdef CONFIG_DCACHE_WORD_ACCESS
+
+#define zero_bytemask(mask) (mask)
+
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+        unsigned long ret, offset;
+
+        /* Load word from unaligned pointer addr */
+        asm(
+        "1:     ldr     %0, [%2]\n"
+        "2:\n"
+        "       .pushsection .fixup,\"ax\"\n"
+        "       .align 2\n"
+        "3:     and     %1, %2, #0x3\n"
+        "       bic     %2, %2, #0x3\n"
+        "       ldr     %0, [%2]\n"
+        "       lsl     %1, %1, #0x3\n"
+        "       lsr     %0, %0, %1\n"
+        "       b       2b\n"
+        "       .popsection\n"
+        "       .pushsection __ex_table,\"a\"\n"
+        "       .align  3\n"
+        "       .long   1b, 3b\n"
+        "       .popsection"
+        : "=&r" (ret), "=&r" (offset)
+        : "r" (addr), "Qo" (*(unsigned long *)addr));
+
+        return ret;
+}
+
+
+#endif  /* DCACHE_WORD_ACCESS */
+
+#else   /* __ARMEB__ */
+#include <asm-generic/word-at-a-time.h>
+#endif
+
+#endif /* __ASM_ARM_WORD_AT_A_TIME_H */
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index dd58035621f..cf258807160 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -32,6 +32,8 @@ static int arch_timer_ppi2;
 
 static struct clock_event_device __percpu **arch_timer_evt;
 
+extern void init_current_timer_delay(unsigned long freq);
+
 /*
  * Architected system timer support.
  */
@@ -137,7 +139,7 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
         /* Be safe... */
         arch_timer_disable();
 
-        clk->features = CLOCK_EVT_FEAT_ONESHOT;
+        clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
         clk->name = "arch_sys_timer";
         clk->rating = 450;
         clk->set_mode = arch_timer_set_mode;
@@ -223,6 +225,14 @@ static cycle_t arch_counter_read(struct clocksource *cs)
         return arch_counter_get_cntpct();
 }
 
+int read_current_timer(unsigned long *timer_val)
+{
+        if (!arch_timer_rate)
+                return -ENXIO;
+        *timer_val = arch_counter_get_cntpct();
+        return 0;
+}
+
 static struct clocksource clocksource_counter = {
         .name   = "arch_sys_counter",
         .rating = 400,
@@ -296,6 +306,7 @@ static int __init arch_timer_register(void)
         if (err)
                 goto out_free_irq;
 
+        init_current_timer_delay(arch_timer_rate);
         return 0;
 
 out_free_irq:
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index b57c75e0b01..60d3b738d42 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -49,8 +49,7 @@ extern void __aeabi_ulcmp(void);
 extern void fpundefinstr(void);
 
         /* platform dependent support */
-EXPORT_SYMBOL(__udelay);
-EXPORT_SYMBOL(__const_udelay);
+EXPORT_SYMBOL(arm_delay_ops);
 
         /* networking */
 EXPORT_SYMBOL(csum_partial);
@@ -87,10 +86,6 @@ EXPORT_SYMBOL(memmove);
 EXPORT_SYMBOL(memchr);
 EXPORT_SYMBOL(__memzero);
 
-        /* user mem (segment) */
-EXPORT_SYMBOL(__strnlen_user);
-EXPORT_SYMBOL(__strncpy_from_user);
-
 #ifdef CONFIG_MMU
 EXPORT_SYMBOL(copy_page);
 
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 25552508c3f..2b2f25e7fef 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -253,7 +253,7 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
 
-static void __init pci_fixup_it8152(struct pci_dev *dev)
+static void __devinit pci_fixup_it8152(struct pci_dev *dev)
 {
         int i;
         /* fixup for ITE 8152 devices */
@@ -461,7 +461,7 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
                         if (!sys->bus)
                                 panic("PCI: unable to scan bus!");
 
-                        busnr = sys->bus->subordinate + 1;
+                        busnr = sys->bus->busn_res.end + 1;
 
                         list_add(&sys->node, head);
                 } else {
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 0d1851ca6eb..0f82098c9bf 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -244,6 +244,19 @@ svc_preempt:
         b       1b
 #endif
 
+__und_fault:
+        @ Correct the PC such that it is pointing at the instruction
+        @ which caused the fault.  If the faulting instruction was ARM
+        @ the PC will be pointing at the next instruction, and have to
+        @ subtract 4.  Otherwise, it is Thumb, and the PC will be
+        @ pointing at the second half of the Thumb instruction.  We
+        @ have to subtract 2.
+        ldr     r2, [r0, #S_PC]
+        sub     r2, r2, r1
+        str     r2, [r0, #S_PC]
+        b       do_undefinstr
+ENDPROC(__und_fault)
+
         .align  5
 __und_svc:
 #ifdef CONFIG_KPROBES
@@ -261,25 +274,32 @@ __und_svc:
         @
         @  r0 - instruction
         @
-#ifndef CONFIG_THUMB2_KERNEL
+#ifndef CONFIG_THUMB2_KERNEL
         ldr     r0, [r4, #-4]
 #else
+        mov     r1, #2
         ldrh    r0, [r4, #-2]                   @ Thumb instruction at LR - 2
         cmp     r0, #0xe800                     @ 32-bit instruction if xx >= 0
-        ldrhhs  r9, [r4]                        @ bottom 16 bits
-        orrhs   r0, r9, r0, lsl #16
+        blo     __und_svc_fault
+        ldrh    r9, [r4]                        @ bottom 16 bits
+        add     r4, r4, #2
+        str     r4, [sp, #S_PC]
+        orr     r0, r9, r0, lsl #16
 #endif
-        adr     r9, BSYM(1f)
+        adr     r9, BSYM(__und_svc_finish)
         mov     r2, r4
         bl      call_fpe
 
+        mov     r1, #4                          @ PC correction to apply
+__und_svc_fault:
         mov     r0, sp                          @ struct pt_regs *regs
-        bl      do_undefinstr
+        bl      __und_fault
 
         @
         @ IRQs off again before pulling preserved data off the stack
         @
-1:      disable_irq_notrace
+__und_svc_finish:
+        disable_irq_notrace
 
         @
         @ restore SPSR and restart the instruction
@@ -423,25 +443,33 @@ __und_usr:
         mov     r2, r4
         mov     r3, r5
 
+        @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
+        @      faulting instruction depending on Thumb mode.
+        @ r3 = regs->ARM_cpsr
         @
-        @ fall through to the emulation code, which returns using r9 if
-        @ it has emulated the instruction, or the more conventional lr
-        @ if we are to treat this as a real undefined instruction
-        @
-        @  r0 - instruction
+        @ The emulation code returns using r9 if it has emulated the
+        @ instruction, or the more conventional lr if we are to treat
+        @ this as a real undefined instruction
         @
         adr     r9, BSYM(ret_from_exception)
-        adr     lr, BSYM(__und_usr_unknown)
+
         tst     r3, #PSR_T_BIT                  @ Thumb mode?
-        itet    eq                              @ explicit IT needed for the 1f label
-        subeq   r4, r2, #4                      @ ARM instr at LR - 4
-        subne   r4, r2, #2                      @ Thumb instr at LR - 2
-1:      ldreqt  r0, [r4]
+        bne     __und_usr_thumb
+        sub     r4, r2, #4                      @ ARM instr at LR - 4
+1:      ldrt    r0, [r4]
 #ifdef CONFIG_CPU_ENDIAN_BE8
-        reveq   r0, r0                          @ little endian instruction
+        rev     r0, r0                          @ little endian instruction
 #endif
-        beq     call_fpe
+        @ r0 = 32-bit ARM instruction which caused the exception
+        @ r2 = PC value for the following instruction (:= regs->ARM_pc)
+        @ r4 = PC value for the faulting instruction
+        @ lr = 32-bit undefined instruction function
+        adr     lr, BSYM(__und_usr_fault_32)
+        b       call_fpe
+
+__und_usr_thumb:
         @ Thumb instruction
+        sub     r4, r2, #2                      @ First half of thumb instr at LR - 2
 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
 /*
  * Thumb-2 instruction handling.  Note that because pre-v6 and >= v6 platforms
@@ -455,7 +483,7 @@ __und_usr:
         ldr     r5, .LCcpu_architecture
         ldr     r5, [r5]
         cmp     r5, #CPU_ARCH_ARMv7
-        blo     __und_usr_unknown
+        blo     __und_usr_fault_16              @ 16bit undefined instruction
 /*
  * The following code won't get run unless the running CPU really is v7, so
  * coding round the lack of ldrht on older arches is pointless.  Temporarily
@@ -463,15 +491,18 @@ __und_usr:
  */
         .arch   armv6t2
 #endif
-2:
- ARM(   ldrht   r5, [r4], #2    )
- THUMB( ldrht   r5, [r4]        )
- THUMB( add     r4, r4, #2      )
+2:      ldrht   r5, [r4]
         cmp     r5, #0xe800                     @ 32bit instruction if xx != 0
-        blo     __und_usr_unknown
-3:      ldrht   r0, [r4]
+        blo     __und_usr_fault_16              @ 16bit undefined instruction
+3:      ldrht   r0, [r2]
         add     r2, r2, #2                      @ r2 is PC + 2, make it PC + 4
+        str     r2, [sp, #S_PC]                 @ it's a 2x16bit instr, update
         orr     r0, r0, r5, lsl #16
+        adr     lr, BSYM(__und_usr_fault_32)
+        @ r0 = the two 16-bit Thumb instructions which caused the exception
+        @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
+        @ r4 = PC value for the first 16-bit Thumb instruction
+        @ lr = 32bit undefined instruction function
 
 #if __LINUX_ARM_ARCH__ < 7
 /* If the target arch was overridden, change it back: */
@@ -482,17 +513,13 @@ __und_usr:
 #endif
 #endif /* __LINUX_ARM_ARCH__ < 7 */
 #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
-        b       __und_usr_unknown
+        b       __und_usr_fault_16
 #endif
- UNWIND(.fnend          )
+ UNWIND(.fnend)
 ENDPROC(__und_usr)
 
-        @
-        @ fallthrough to call_fpe
-        @
-
 /*
- * The out of line fixup for the ldrt above.
+ * The out of line fixup for the ldrt instructions above.
  */
         .pushsection .fixup, "ax"
         .align  2
@@ -524,11 +551,12 @@ ENDPROC(__und_usr)
  * NEON handler code.
  *
  * Emulators may wish to make use of the following registers:
- *  r0  = instruction opcode.
- *  r2  = PC+4
+ *  r0  = instruction opcode (32-bit ARM or two 16-bit Thumb)
+ *  r2  = PC value to resume execution after successful emulation
  *  r9  = normal "successful" return address
- *  r10 = this threads thread_info structure.
+ *  r10 = this threads thread_info structure
  *  lr  = unrecognised instruction return address
+ * IRQs disabled, FIQs enabled.
  */
         @
         @ Fall-through from Thumb-2 __und_usr
@@ -659,12 +687,17 @@ ENTRY(no_fp)
         mov     pc, lr
 ENDPROC(no_fp)
 
-__und_usr_unknown:
-        enable_irq
+__und_usr_fault_32:
+        mov     r1, #4
+        b       1f
+__und_usr_fault_16:
+        mov     r1, #2
+1:      enable_irq
         mov     r0, sp
         adr     lr, BSYM(ret_from_exception)
-        b       do_undefinstr
-ENDPROC(__und_usr_unknown)
+        b       __und_fault
+ENDPROC(__und_usr_fault_32)
+ENDPROC(__und_usr_fault_16)
 
         .align  5
 __pabt_usr:
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 4afed88d250..978eac57e04 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -51,23 +51,15 @@ ret_fast_syscall:
 fast_work_pending:
         str     r0, [sp, #S_R0+S_OFF]!          @ returned r0
 work_pending:
-        tst     r1, #_TIF_NEED_RESCHED
-        bne     work_resched
-        /*
-         * TIF_SIGPENDING or TIF_NOTIFY_RESUME must've been set if we got here
-         */
-        ldr     r2, [sp, #S_PSR]
         mov     r0, sp                          @ 'regs'
-        tst     r2, #15                         @ are we returning to user mode?
-        bne     no_work_pending                 @ no?  just leave, then...
         mov     r2, why                         @ 'syscall'
-        tst     r1, #_TIF_SIGPENDING            @ delivering a signal?
-        movne   why, #0                         @ prevent further restarts
-        bl      do_notify_resume
-        b       ret_slow_syscall                @ Check work again
+        bl      do_work_pending
+        cmp     r0, #0
+        beq     no_work_pending
+        movlt   scno, #(__NR_restart_syscall - __NR_SYSCALL_BASE)
+        ldmia   sp, {r0 - r6}                   @ have to reload r0 - r6
+        b       local_restart                   @ ... and off we go
 
-work_resched:
-        bl      schedule
 /*
  * "slow" syscall return path.  "why" tells us if this was a real syscall.
  */
@@ -95,13 +87,7 @@ ENDPROC(ret_to_user)
 ENTRY(ret_from_fork)
         bl      schedule_tail
         get_thread_info tsk
-        ldr     r1, [tsk, #TI_FLAGS]            @ check for syscall tracing
         mov     why, #1
-        tst     r1, #_TIF_SYSCALL_WORK          @ are we tracing syscalls?
-        beq     ret_slow_syscall
-        mov     r1, sp
-        mov     r0, #1                          @ trace exit [IP = 1]
-        bl      syscall_trace
         b       ret_slow_syscall
 ENDPROC(ret_from_fork)
 
@@ -415,6 +401,7 @@ ENTRY(vector_swi)
         eor     scno, scno, #__NR_SYSCALL_BASE  @ check OS number
 #endif
 
+local_restart:
         ldr     r10, [tsk, #TI_FLAGS]           @ check for syscall tracing
         stmdb   sp!, {r4, r5}                   @ push fifth and sixth args
 
@@ -448,25 +435,24 @@ ENDPROC(vector_swi)
          * context switches, and waiting for our parent to respond.
          */
 __sys_trace:
-        mov     r2, scno
-        add     r1, sp, #S_OFF
-        mov     r0, #0                          @ trace entry [IP = 0]
-        bl      syscall_trace
+        mov     r1, scno
+        add     r0, sp, #S_OFF
+        bl      syscall_trace_enter
 
         adr     lr, BSYM(__sys_trace_return)    @ return address
         mov     scno, r0                        @ syscall number (possibly new)
         add     r1, sp, #S_R0 + S_OFF           @ pointer to regs
         cmp     scno, #NR_syscalls              @ check upper syscall limit
-        ldmccia r1, {r0 - r3}                   @ have to reload r0 - r3
+        ldmccia r1, {r0 - r6}                   @ have to reload r0 - r6
+        stmccia sp, {r4, r5}                    @ and update the stack args
         ldrcc   pc, [tbl, scno, lsl #2]         @ call sys_* routine
         b       2b
 
 __sys_trace_return:
         str     r0, [sp, #S_R0 + S_OFF]!        @ save returned r0
-        mov     r2, scno
-        mov     r1, sp
-        mov     r0, #1                          @ trace exit [IP = 1]
-        bl      syscall_trace
+        mov     r1, scno
+        mov     r0, sp
+        bl      syscall_trace_exit
         b       ret_slow_syscall
 
         .align  5
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index c32f8456aa0..2adda11f712 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -122,14 +122,16 @@ void release_fiq(struct fiq_handler *f)
         while (current_fiq->fiq_op(current_fiq->dev_id, 0));
 }
 
+static int fiq_start;
+
 void enable_fiq(int fiq)
 {
-        enable_irq(fiq + FIQ_START);
+        enable_irq(fiq + fiq_start);
 }
 
 void disable_fiq(int fiq)
 {
-        disable_irq(fiq + FIQ_START);
+        disable_irq(fiq + fiq_start);
 }
 
 EXPORT_SYMBOL(set_fiq_handler);
@@ -140,7 +142,8 @@ EXPORT_SYMBOL(release_fiq);
 EXPORT_SYMBOL(enable_fiq);
 EXPORT_SYMBOL(disable_fiq);
 
-void __init init_FIQ(void)
+void __init init_FIQ(int start)
 {
         no_fiq_insn = *(unsigned long *)0xffff001c;
+        fiq_start = start;
 }
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
index df0bf0c8cb7..34e56647dce 100644
--- a/arch/arm/kernel/ftrace.c
+++ b/arch/arm/kernel/ftrace.c
@@ -179,19 +179,20 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
         old = *parent;
         *parent = return_hooker;
 
-        err = ftrace_push_return_trace(old, self_addr, &trace.depth,
-                                       frame_pointer);
-        if (err == -EBUSY) {
-                *parent = old;
-                return;
-        }
-
         trace.func = self_addr;
+        trace.depth = current->curr_ret_stack + 1;
 
         /* Only trace if the calling function expects to */
         if (!ftrace_graph_entry(&trace)) {
-                current->curr_ret_stack--;
                 *parent = old;
+                return;
+        }
+
+        err = ftrace_push_return_trace(old, self_addr, &trace.depth,
+                                       frame_pointer);
+        if (err == -EBUSY) {
+                *parent = old;
+                return;
         }
 }
 
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 835898e7d70..3db960e20cb 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -55,14 +55,6 @@
         add     \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
         .endm
 
-#ifdef CONFIG_XIP_KERNEL
-#define KERNEL_START    XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
-#define KERNEL_END      _edata_loc
-#else
-#define KERNEL_START    KERNEL_RAM_VADDR
-#define KERNEL_END      _end
-#endif
-
 /*
  * Kernel startup entry point.
  * ---------------------------
@@ -218,51 +210,46 @@ __create_page_tables:
         blo     1b
 
         /*
-         * Now setup the pagetables for our kernel direct
-         * mapped region.
+         * Map our RAM from the start to the end of the kernel .bss section.
          */
-        mov     r3, pc
-        mov     r3, r3, lsr #SECTION_SHIFT
-        orr     r3, r7, r3, lsl #SECTION_SHIFT
-        add     r0, r4,  #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
-        str     r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
-        ldr     r6, =(KERNEL_END - 1)
-        add     r0, r0, #1 << PMD_ORDER
+        add     r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
+        ldr     r6, =(_end - 1)
+        orr     r3, r8, r7
         add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
-1:      cmp     r0, r6
+1:      str     r3, [r0], #1 << PMD_ORDER
         add     r3, r3, #1 << SECTION_SHIFT
-        strls   r3, [r0], #1 << PMD_ORDER
+        cmp     r0, r6
         bls     1b
 
 #ifdef CONFIG_XIP_KERNEL
         /*
-         * Map some ram to cover our .data and .bss areas.
+         * Map the kernel image separately as it is not located in RAM.
          */
-        add     r3, r8, #TEXT_OFFSET
-        orr     r3, r3, r7
-        add     r0, r4,  #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
-        str     r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]!
-        ldr     r6, =(_end - 1)
-        add     r0, r0, #4
+#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
+        mov     r3, pc
+        mov     r3, r3, lsr #SECTION_SHIFT
+        orr     r3, r7, r3, lsl #SECTION_SHIFT
+        add     r0, r4,  #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
+        str     r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
+        ldr     r6, =(_edata_loc - 1)
+        add     r0, r0, #1 << PMD_ORDER
         add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
 1:      cmp     r0, r6
-        add     r3, r3, #1 << 20
-        strls   r3, [r0], #4
+        add     r3, r3, #1 << SECTION_SHIFT
+        strls   r3, [r0], #1 << PMD_ORDER
         bls     1b
 #endif
 
         /*
-         * Then map boot params address in r2 or the first 1MB (2MB with LPAE)
-         * of ram if boot params address is not specified.
+         * Then map boot params address in r2 if specified.
          */
         mov     r0, r2, lsr #SECTION_SHIFT
         movs    r0, r0, lsl #SECTION_SHIFT
-        moveq   r0, r8
-        sub     r3, r0, r8
-        add     r3, r3, #PAGE_OFFSET
-        add     r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
-        orr     r6, r7, r0
-        str     r6, [r3]
+        subne   r3, r0, r8
+        addne   r3, r3, #PAGE_OFFSET
+        addne   r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
+        orrne   r6, r7, r0
+        strne   r6, [r3]
 
 #ifdef CONFIG_DEBUG_LL
 #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 8349d4e97e2..16cedb42c0c 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -40,13 +40,6 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 
-/*
- * No architecture-specific irq_finish function defined in arm/arch/irqs.h.
- */
-#ifndef irq_finish
-#define irq_finish(irq) do { } while (0)
-#endif
-
 unsigned long irq_err_count;
 
 int arch_show_interrupts(struct seq_file *p, int prec)
@@ -85,9 +78,6 @@ void handle_IRQ(unsigned int irq, struct pt_regs *regs)
                 generic_handle_irq(irq);
         }
 
-        /* AT91 specific workaround */
-        irq_finish(irq);
-
         irq_exit();
         set_irq_regs(old_regs);
 }
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index a02eada3aa5..ab243b87118 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -47,17 +47,14 @@ static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
 /* Set at runtime when we know what CPU type we are. */
 static struct arm_pmu *cpu_pmu;
 
-enum arm_perf_pmu_ids
-armpmu_get_pmu_id(void)
+const char *perf_pmu_name(void)
 {
-        int id = -ENODEV;
-
-        if (cpu_pmu != NULL)
-                id = cpu_pmu->id;
+        if (!cpu_pmu)
+                return NULL;
 
-        return id;
+        return cpu_pmu->pmu.name;
 }
-EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
+EXPORT_SYMBOL_GPL(perf_pmu_name);
 
 int perf_num_counters(void)
 {
@@ -760,7 +757,7 @@ init_hw_perf_events(void)
                         cpu_pmu->name, cpu_pmu->num_events);
                 cpu_pmu_init(cpu_pmu);
                 register_cpu_notifier(&pmu_cpu_notifier);
-                armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
+                armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
         } else {
                 pr_info("no hardware support available\n");
         }
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index ab627a740fa..c90fcb2b696 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -650,7 +650,6 @@ static int armv6_map_event(struct perf_event *event)
 }
 
 static struct arm_pmu armv6pmu = {
-        .id                     = ARM_PERF_PMU_ID_V6,
         .name                   = "v6",
         .handle_irq             = armv6pmu_handle_irq,
         .enable                 = armv6pmu_enable_event,
@@ -685,7 +684,6 @@ static int armv6mpcore_map_event(struct perf_event *event)
 }
 
 static struct arm_pmu armv6mpcore_pmu = {
-        .id                     = ARM_PERF_PMU_ID_V6MP,
         .name                   = "v6mpcore",
         .handle_irq             = armv6pmu_handle_irq,
         .enable                 = armv6pmu_enable_event,
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index d3c53606816..f04070bd218 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1258,7 +1258,6 @@ static u32 __init armv7_read_num_pmnc_events(void)
 
 static struct arm_pmu *__init armv7_a8_pmu_init(void)
 {
-        armv7pmu.id             = ARM_PERF_PMU_ID_CA8;
         armv7pmu.name           = "ARMv7 Cortex-A8";
         armv7pmu.map_event      = armv7_a8_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
@@ -1267,7 +1266,6 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a9_pmu_init(void)
 {
-        armv7pmu.id             = ARM_PERF_PMU_ID_CA9;
         armv7pmu.name           = "ARMv7 Cortex-A9";
         armv7pmu.map_event      = armv7_a9_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
@@ -1276,7 +1274,6 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a5_pmu_init(void)
 {
-        armv7pmu.id             = ARM_PERF_PMU_ID_CA5;
         armv7pmu.name           = "ARMv7 Cortex-A5";
         armv7pmu.map_event      = armv7_a5_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
@@ -1285,7 +1282,6 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a15_pmu_init(void)
 {
-        armv7pmu.id             = ARM_PERF_PMU_ID_CA15;
         armv7pmu.name           = "ARMv7 Cortex-A15";
         armv7pmu.map_event      = armv7_a15_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
@@ -1295,7 +1291,6 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a7_pmu_init(void)
 {
-        armv7pmu.id             = ARM_PERF_PMU_ID_CA7;
         armv7pmu.name           = "ARMv7 Cortex-A7";
         armv7pmu.map_event      = armv7_a7_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index e34e7254e65..f759fe0bab6 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -435,7 +435,6 @@ static int xscale_map_event(struct perf_event *event)
 }
 
 static struct arm_pmu xscale1pmu = {
-        .id             = ARM_PERF_PMU_ID_XSCALE1,
         .name           = "xscale1",
         .handle_irq     = xscale1pmu_handle_irq,
         .enable         = xscale1pmu_enable_event,
@@ -803,7 +802,6 @@ xscale2pmu_write_counter(int counter, u32 val)
 }
 
 static struct arm_pmu xscale2pmu = {
-        .id             = ARM_PERF_PMU_ID_XSCALE2,
         .name           = "xscale2",
         .handle_irq     = xscale2pmu_handle_irq,
         .enable         = xscale2pmu_enable_event,
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 19c95ea65b2..693b744fd57 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -247,6 +247,7 @@ void machine_shutdown(void)
 void machine_halt(void)
 {
         machine_shutdown();
+        local_irq_disable();
         while (1);
 }
 
@@ -268,6 +269,7 @@ void machine_restart(char *cmd)
 
         /* Whoops - the platform was unable to reboot. Tell the user! */
         printk("Reboot failed -- System halted\n");
+        local_irq_disable();
         while (1);
 }
 
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 14e38261cd3..3e0fc5f7ed4 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -25,6 +25,7 @@
 #include <linux/regset.h>
 #include <linux/audit.h>
 #include <linux/tracehook.h>
+#include <linux/unistd.h>
 
 #include <asm/pgtable.h>
 #include <asm/traps.h>
@@ -907,16 +908,16 @@ long arch_ptrace(struct task_struct *child, long request,
         return ret;
 }
 
-asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
+enum ptrace_syscall_dir {
+        PTRACE_SYSCALL_ENTER = 0,
+        PTRACE_SYSCALL_EXIT,
+};
+
+static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
+                                enum ptrace_syscall_dir dir)
 {
         unsigned long ip;
 
-        if (why)
-                audit_syscall_exit(regs);
-        else
-                audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0,
-                                    regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
-
         if (!test_thread_flag(TIF_SYSCALL_TRACE))
                 return scno;
 
@@ -927,14 +928,28 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
          * IP = 0 -> entry, =1 -> exit
          */
         ip = regs->ARM_ip;
-        regs->ARM_ip = why;
+        regs->ARM_ip = dir;
 
-        if (why)
+        if (dir == PTRACE_SYSCALL_EXIT)
                 tracehook_report_syscall_exit(regs, 0);
         else if (tracehook_report_syscall_entry(regs))
                 current_thread_info()->syscall = -1;
 
         regs->ARM_ip = ip;
-
         return current_thread_info()->syscall;
 }
+
+asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
+{
+        int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+        audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
+                            regs->ARM_r2, regs->ARM_r3);
+        return ret;
+}
+
+asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
+{
+        int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+        audit_syscall_exit(regs);
+        return ret;
+}
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index 27d186abbc0..f4515393248 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -21,6 +21,8 @@ struct clock_data {
         u32 epoch_cyc_copy;
         u32 mult;
         u32 shift;
+        bool suspended;
+        bool needs_suspend;
 };
 
 static void sched_clock_poll(unsigned long wrap_ticks);
@@ -49,6 +51,9 @@ static unsigned long long cyc_to_sched_clock(u32 cyc, u32 mask)
         u64 epoch_ns;
         u32 epoch_cyc;
 
+        if (cd.suspended)
+                return cd.epoch_ns;
+
         /*
          * Load the epoch_cyc and epoch_ns atomically.  We do this by
          * ensuring that we always write epoch_cyc, epoch_ns and
@@ -98,6 +103,13 @@ static void sched_clock_poll(unsigned long wrap_ticks)
         update_sched_clock();
 }
 
+void __init setup_sched_clock_needs_suspend(u32 (*read)(void), int bits,
+                unsigned long rate)
+{
+        setup_sched_clock(read, bits, rate);
+        cd.needs_suspend = true;
+}
+
 void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
 {
         unsigned long r, w;
@@ -169,11 +181,23 @@ void __init sched_clock_postinit(void)
 static int sched_clock_suspend(void)
 {
         sched_clock_poll(sched_clock_timer.data);
+        if (cd.needs_suspend)
+                cd.suspended = true;
         return 0;
 }
 
+static void sched_clock_resume(void)
+{
+        if (cd.needs_suspend) {
+                cd.epoch_cyc = read_sched_clock();
+                cd.epoch_cyc_copy = cd.epoch_cyc;
+                cd.suspended = false;
+        }
+}
+
 static struct syscore_ops sched_clock_ops = {
         .suspend = sched_clock_suspend,
+        .resume = sched_clock_resume,
 };
 
 static int __init sched_clock_syscore_init(void)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index e15d83bb4ea..a81dcecc734 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -508,7 +508,7 @@ void __init dump_machine_table(void)
                 /* can't use cpu_relax() here as it may require MMU setup */;
 }
 
-int __init arm_add_memory(phys_addr_t start, unsigned long size)
+int __init arm_add_memory(phys_addr_t start, phys_addr_t size)
 {
         struct membank *bank = &meminfo.bank[meminfo.nr_banks];
 
@@ -538,7 +538,7 @@ int __init arm_add_memory(phys_addr_t start, unsigned long size)
         }
 #endif
 
-        bank->size = size & PAGE_MASK;
+        bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
 
         /*
          * Check whether this memory region has non-zero size or
@@ -558,7 +558,7 @@ int __init arm_add_memory(phys_addr_t start, unsigned long size)
 static int __init early_mem(char *p)
 {
         static int usermem __initdata = 0;
-        unsigned long size;
+        phys_addr_t size;
         phys_addr_t start;
         char *endp;
 
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 536c5d6b340..f27789e4e38 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -27,7 +27,6 @@
  */
 #define SWI_SYS_SIGRETURN       (0xef000000|(__NR_sigreturn)|(__NR_OABI_SYSCALL_BASE))
 #define SWI_SYS_RT_SIGRETURN    (0xef000000|(__NR_rt_sigreturn)|(__NR_OABI_SYSCALL_BASE))
-#define SWI_SYS_RESTART         (0xef000000|__NR_restart_syscall|__NR_OABI_SYSCALL_BASE)
 
 /*
  * With EABI, the syscall number has to be loaded into r7.
@@ -48,18 +47,6 @@ const unsigned long sigreturn_codes[7] = {
 };
 
 /*
- * Either we support OABI only, or we have EABI with the OABI
- * compat layer enabled.  In the later case we don't know if
- * user space is EABI or not, and if not we must not clobber r7.
- * Always using the OABI syscall solves that issue and works for
- * all those cases.
- */
-const unsigned long syscall_restart_code[2] = {
-        SWI_SYS_RESTART,        /* swi  __NR_restart_syscall */
-        0xe49df004,             /* ldr  pc, [sp], #4 */
-};
-
-/*
  * atomically swap in the new signal mask, and wait for a signal.
  */
 asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask)
@@ -582,12 +569,13 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
  * the kernel can handle, and then we build all the user-level signal handling
  * stack-frames in one go after that.
  */
-static void do_signal(struct pt_regs *regs, int syscall)
+static int do_signal(struct pt_regs *regs, int syscall)
 {
         unsigned int retval = 0, continue_addr = 0, restart_addr = 0;
         struct k_sigaction ka;
         siginfo_t info;
         int signr;
+        int restart = 0;
 
         /*
          * If we were from a system call, check for system call restarting...
@@ -602,15 +590,15 @@ static void do_signal(struct pt_regs *regs, int syscall)
                  * debugger will see the already changed PSW.
                  */
                 switch (retval) {
+                case -ERESTART_RESTARTBLOCK:
+                        restart -= 2;
                 case -ERESTARTNOHAND:
                 case -ERESTARTSYS:
                 case -ERESTARTNOINTR:
+                        restart++;
                         regs->ARM_r0 = regs->ARM_ORIG_r0;
                         regs->ARM_pc = restart_addr;
                         break;
-                case -ERESTART_RESTARTBLOCK:
-                        regs->ARM_r0 = -EINTR;
-                        break;
                 }
         }
 
@@ -619,14 +607,17 @@ static void do_signal(struct pt_regs *regs, int syscall)
          * point the debugger may change all our registers ...
          */
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+        /*
+         * Depending on the signal settings we may need to revert the
+         * decision to restart the system call.  But skip this if a
+         * debugger has chosen to restart at a different PC.
+         */
+        if (regs->ARM_pc != restart_addr)
+                restart = 0;
         if (signr > 0) {
-                /*
-                 * Depending on the signal settings we may need to revert the
-                 * decision to restart the system call.  But skip this if a
-                 * debugger has chosen to restart at a different PC.
-                 */
-                if (regs->ARM_pc == restart_addr) {
-                        if (retval == -ERESTARTNOHAND
+                if (unlikely(restart)) {
+                        if (retval == -ERESTARTNOHAND ||
+                            retval == -ERESTART_RESTARTBLOCK
                             || (retval == -ERESTARTSYS
                                 && !(ka.sa.sa_flags & SA_RESTART))) {
                                 regs->ARM_r0 = -EINTR;
@@ -635,52 +626,43 @@ static void do_signal(struct pt_regs *regs, int syscall)
                 }
 
                 handle_signal(signr, &ka, &info, regs);
-                return;
-        }
-
-        if (syscall) {
-                /*
-                 * Handle restarting a different system call.  As above,
-                 * if a debugger has chosen to restart at a different PC,
-                 * ignore the restart.
-                 */
-                if (retval == -ERESTART_RESTARTBLOCK
-                    && regs->ARM_pc == continue_addr) {
-                        if (thumb_mode(regs)) {
-                                regs->ARM_r7 = __NR_restart_syscall - __NR_SYSCALL_BASE;
-                                regs->ARM_pc -= 2;
-                        } else {
-#if defined(CONFIG_AEABI) && !defined(CONFIG_OABI_COMPAT)
-                                regs->ARM_r7 = __NR_restart_syscall;
-                                regs->ARM_pc -= 4;
-#else
-                                u32 __user *usp;
-
-                                regs->ARM_sp -= 4;
-                                usp = (u32 __user *)regs->ARM_sp;
-
-                                if (put_user(regs->ARM_pc, usp) == 0) {
-                                        regs->ARM_pc = KERN_RESTART_CODE;
-                                } else {
-                                        regs->ARM_sp += 4;
-                                        force_sigsegv(0, current);
-                                }
-#endif
-                        }
-                }
+                return 0;
         }
 
         restore_saved_sigmask();
+        if (unlikely(restart))
+                regs->ARM_pc = continue_addr;
+        return restart;
 }
 
-asmlinkage void
-do_notify_resume(struct pt_regs *regs, unsigned int thread_flags, int syscall)
+asmlinkage int
+do_work_pending(struct pt_regs *regs, unsigned int thread_flags, int syscall)
 {
-        if (thread_flags & _TIF_SIGPENDING)
-                do_signal(regs, syscall);
-
-        if (thread_flags & _TIF_NOTIFY_RESUME) {
-                clear_thread_flag(TIF_NOTIFY_RESUME);
-                tracehook_notify_resume(regs);
-        }
+        do {
+                if (likely(thread_flags & _TIF_NEED_RESCHED)) {
+                        schedule();
+                } else {
+                        if (unlikely(!user_mode(regs)))
+                                return 0;
+                        local_irq_enable();
+                        if (thread_flags & _TIF_SIGPENDING) {
+                                int restart = do_signal(regs, syscall);
+                                if (unlikely(restart)) {
+                                        /*
+                                         * Restart without handlers.
+                                         * Deal with it without leaving
+                                         * the kernel space.
+                                         */
+                                        return restart;
+                                }
+                                syscall = 0;
+                        } else {
+                                clear_thread_flag(TIF_NOTIFY_RESUME);
+                                tracehook_notify_resume(regs);
+                        }
+                }
+                local_irq_disable();
+                thread_flags = current_thread_info()->flags;
+        } while (thread_flags & _TIF_WORK_MASK);
+        return 0;
 }
diff --git a/arch/arm/kernel/signal.h b/arch/arm/kernel/signal.h
index 6fcfe8398aa..5ff067b7c75 100644
--- a/arch/arm/kernel/signal.h
+++ b/arch/arm/kernel/signal.h
@@ -8,7 +8,5 @@
  * published by the Free Software Foundation.
  */
 #define KERN_SIGRETURN_CODE     (CONFIG_VECTORS_BASE + 0x00000500)
-#define KERN_RESTART_CODE       (KERN_SIGRETURN_CODE + sizeof(sigreturn_codes))
 
 extern const unsigned long sigreturn_codes[7];
-extern const unsigned long syscall_restart_code[2];
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 2c7217d971d..ebd8ad274d7 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -179,7 +179,7 @@ void __ref cpu_die(void)
         mb();
 
         /* Tell __cpu_die() that this CPU is now safe to dispose of */
-        complete(&cpu_died);
+        RCU_NONIDLE(complete(&cpu_died));
 
         /*
          * actual CPU shutdown procedure is at least platform (if not
@@ -563,7 +563,8 @@ void smp_send_stop(void)
 
         cpumask_copy(&mask, cpu_online_mask);
         cpumask_clear_cpu(smp_processor_id(), &mask);
-        smp_cross_call(&mask, IPI_CPU_STOP);
+        if (!cpumask_empty(&mask))
+                smp_cross_call(&mask, IPI_CPU_STOP);
 
         /* Wait up to one second for other CPUs to stop */
         timeout = USEC_PER_SEC;
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 8200deaa14f..26c12c6440f 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -17,11 +17,190 @@
 #include <linux/percpu.h>
 #include <linux/node.h>
 #include <linux/nodemask.h>
+#include <linux/of.h>
 #include <linux/sched.h>
+#include <linux/slab.h>
 
 #include <asm/cputype.h>
 #include <asm/topology.h>
 
+/*
+ * cpu power scale management
+ */
+
+/*
+ * cpu power table
+ * This per cpu data structure describes the relative capacity of each core.
+ * On a heteregenous system, cores don't have the same computation capacity
+ * and we reflect that difference in the cpu_power field so the scheduler can
+ * take this difference into account during load balance. A per cpu structure
+ * is preferred because each CPU updates its own cpu_power field during the
+ * load balance except for idle cores. One idle core is selected to run the
+ * rebalance_domains for all idle cores and the cpu_power can be updated
+ * during this sequence.
+ */
+static DEFINE_PER_CPU(unsigned long, cpu_scale);
+
+unsigned long arch_scale_freq_power(struct sched_domain *sd, int cpu)
+{
+        return per_cpu(cpu_scale, cpu);
+}
+
+static void set_power_scale(unsigned int cpu, unsigned long power)
+{
+        per_cpu(cpu_scale, cpu) = power;
+}
+
+#ifdef CONFIG_OF
+struct cpu_efficiency {
+        const char *compatible;
+        unsigned long efficiency;
+};
+
+/*
+ * Table of relative efficiency of each processors
+ * The efficiency value must fit in 20bit and the final
+ * cpu_scale value must be in the range
+ *   0 < cpu_scale < 3*SCHED_POWER_SCALE/2
+ * in order to return at most 1 when DIV_ROUND_CLOSEST
+ * is used to compute the capacity of a CPU.
+ * Processors that are not defined in the table,
+ * use the default SCHED_POWER_SCALE value for cpu_scale.
+ */
+struct cpu_efficiency table_efficiency[] = {
+        {"arm,cortex-a15", 3891},
+        {"arm,cortex-a7",  2048},
+        {NULL, },
+};
+
+struct cpu_capacity {
+        unsigned long hwid;
+        unsigned long capacity;
+};
+
+struct cpu_capacity *cpu_capacity;
+
+unsigned long middle_capacity = 1;
+
+/*
+ * Iterate all CPUs' descriptor in DT and compute the efficiency
+ * (as per table_efficiency). Also calculate a middle efficiency
+ * as close as possible to  (max{eff_i} - min{eff_i}) / 2
+ * This is later used to scale the cpu_power field such that an
+ * 'average' CPU is of middle power. Also see the comments near
+ * table_efficiency[] and update_cpu_power().
+ */
+static void __init parse_dt_topology(void)
+{
+        struct cpu_efficiency *cpu_eff;
+        struct device_node *cn = NULL;
+        unsigned long min_capacity = (unsigned long)(-1);
+        unsigned long max_capacity = 0;
+        unsigned long capacity = 0;
+        int alloc_size, cpu = 0;
+
+        alloc_size = nr_cpu_ids * sizeof(struct cpu_capacity);
+        cpu_capacity = (struct cpu_capacity *)kzalloc(alloc_size, GFP_NOWAIT);
+
+        while ((cn = of_find_node_by_type(cn, "cpu"))) {
+                const u32 *rate, *reg;
+                int len;
+
+                if (cpu >= num_possible_cpus())
+                        break;
+
+                for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++)
+                        if (of_device_is_compatible(cn, cpu_eff->compatible))
+                                break;
+
+                if (cpu_eff->compatible == NULL)
+                        continue;
+
+                rate = of_get_property(cn, "clock-frequency", &len);
+                if (!rate || len != 4) {
+                        pr_err("%s missing clock-frequency property\n",
+                                cn->full_name);
+                        continue;
+                }
+
+                reg = of_get_property(cn, "reg", &len);
+                if (!reg || len != 4) {
+                        pr_err("%s missing reg property\n", cn->full_name);
+                        continue;
+                }
+
+                capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency;
+
+                /* Save min capacity of the system */
+                if (capacity < min_capacity)
+                        min_capacity = capacity;
+
+                /* Save max capacity of the system */
+                if (capacity > max_capacity)
+                        max_capacity = capacity;
+
+                cpu_capacity[cpu].capacity = capacity;
+                cpu_capacity[cpu++].hwid = be32_to_cpup(reg);
+        }
+
+        if (cpu < num_possible_cpus())
+                cpu_capacity[cpu].hwid = (unsigned long)(-1);
+
+        /* If min and max capacities are equals, we bypass the update of the
+         * cpu_scale because all CPUs have the same capacity. Otherwise, we
+         * compute a middle_capacity factor that will ensure that the capacity
+         * of an 'average' CPU of the system will be as close as possible to
+         * SCHED_POWER_SCALE, which is the default value, but with the
+         * constraint explained near table_efficiency[].
+         */
+        if (min_capacity == max_capacity)
+                cpu_capacity[0].hwid = (unsigned long)(-1);
+        else if (4*max_capacity < (3*(max_capacity + min_capacity)))
+                middle_capacity = (min_capacity + max_capacity)
+                                >> (SCHED_POWER_SHIFT+1);
+        else
+                middle_capacity = ((max_capacity / 3)
+                                >> (SCHED_POWER_SHIFT-1)) + 1;
+
+}
+
+/*
+ * Look for a customed capacity of a CPU in the cpu_capacity table during the
+ * boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
+ * function returns directly for SMP system.
+ */
+void update_cpu_power(unsigned int cpu, unsigned long hwid)
+{
+        unsigned int idx = 0;
+
+        /* look for the cpu's hwid in the cpu capacity table */
+        for (idx = 0; idx < num_possible_cpus(); idx++) {
+                if (cpu_capacity[idx].hwid == hwid)
+                        break;
+
+                if (cpu_capacity[idx].hwid == -1)
+                        return;
+        }
+
+        if (idx == num_possible_cpus())
+                return;
+
+        set_power_scale(cpu, cpu_capacity[idx].capacity / middle_capacity);
+
+        printk(KERN_INFO "CPU%u: update cpu_power %lu\n",
+                cpu, arch_scale_freq_power(NULL, cpu));
+}
+
+#else
+static inline void parse_dt_topology(void) {}
+static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {}
+#endif
+
+
+/*
+ * cpu topology management
+ */
+
 #define MPIDR_SMP_BITMASK (0x3 << 30)
 #define MPIDR_SMP_VALUE (0x2 << 30)
 
@@ -31,6 +210,7 @@
  * These masks reflect the current use of the affinity levels.
  * The affinity level can be up to 16 bits according to ARM ARM
  */
+#define MPIDR_HWID_BITMASK 0xFFFFFF
 
 #define MPIDR_LEVEL0_MASK 0x3
 #define MPIDR_LEVEL0_SHIFT 0
@@ -41,6 +221,9 @@
 #define MPIDR_LEVEL2_MASK 0xFF
 #define MPIDR_LEVEL2_SHIFT 16
 
+/*
+ * cpu topology table
+ */
 struct cputopo_arm cpu_topology[NR_CPUS];
 
 const struct cpumask *cpu_coregroup_mask(int cpu)
@@ -48,6 +231,32 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
         return &cpu_topology[cpu].core_sibling;
 }
 
+void update_siblings_masks(unsigned int cpuid)
+{
+        struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
+        int cpu;
+
+        /* update core and thread sibling masks */
+        for_each_possible_cpu(cpu) {
+                cpu_topo = &cpu_topology[cpu];
+
+                if (cpuid_topo->socket_id != cpu_topo->socket_id)
+                        continue;
+
+                cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
+                if (cpu != cpuid)
+                        cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
+
+                if (cpuid_topo->core_id != cpu_topo->core_id)
+                        continue;
+
+                cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
+                if (cpu != cpuid)
+                        cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
+        }
+        smp_wmb();
+}
+
 /*
  * store_cpu_topology is called at boot when only one cpu is running
  * and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
@@ -57,7 +266,6 @@ void store_cpu_topology(unsigned int cpuid)
 {
         struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid];
         unsigned int mpidr;
-        unsigned int cpu;
 
         /* If the cpu topology has been already set, just return */
         if (cpuid_topo->core_id != -1)
@@ -99,26 +307,9 @@ void store_cpu_topology(unsigned int cpuid)
                 cpuid_topo->socket_id = -1;
         }
 
-        /* update core and thread sibling masks */
-        for_each_possible_cpu(cpu) {
-                struct cputopo_arm *cpu_topo = &cpu_topology[cpu];
-
-                if (cpuid_topo->socket_id == cpu_topo->socket_id) {
-                        cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
-                        if (cpu != cpuid)
-                                cpumask_set_cpu(cpu,
-                                        &cpuid_topo->core_sibling);
-
-                        if (cpuid_topo->core_id == cpu_topo->core_id) {
-                                cpumask_set_cpu(cpuid,
-                                        &cpu_topo->thread_sibling);
-                                if (cpu != cpuid)
-                                        cpumask_set_cpu(cpu,
-                                                &cpuid_topo->thread_sibling);
-                        }
-                }
-        }
-        smp_wmb();
+        update_siblings_masks(cpuid);
+
+        update_cpu_power(cpuid, mpidr & MPIDR_HWID_BITMASK);
 
         printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",
                 cpuid, cpu_topology[cpuid].thread_id,
@@ -130,11 +321,11 @@ void store_cpu_topology(unsigned int cpuid)
  * init_cpu_topology is called at boot when only one cpu is running
  * which prevent simultaneous write access to cpu_topology array
  */
-void init_cpu_topology(void)
+void __init init_cpu_topology(void)
 {
         unsigned int cpu;
 
-        /* init core mask */
+        /* init core mask and power*/
         for_each_possible_cpu(cpu) {
                 struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);
 
@@ -143,6 +334,10 @@ void init_cpu_topology(void)
                 cpu_topo->socket_id = -1;
                 cpumask_clear(&cpu_topo->core_sibling);
                 cpumask_clear(&cpu_topo->thread_sibling);
+
+                set_power_scale(cpu, SCHED_POWER_SCALE);
         }
         smp_wmb();
+
+        parse_dt_topology();
 }
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 3647170e9a1..f7945218b8c 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -233,9 +233,9 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
 #define S_ISA " ARM"
 #endif
 
-static int __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs)
+static int __die(const char *str, int err, struct pt_regs *regs)
 {
-        struct task_struct *tsk = thread->task;
+        struct task_struct *tsk = current;
         static int die_counter;
         int ret;
 
@@ -245,12 +245,12 @@ static int __die(const char *str, int err, struct thread_info *thread, struct pt
         /* trap and error numbers are mostly meaningless on ARM */
         ret = notify_die(DIE_OOPS, str, regs, err, tsk->thread.trap_no, SIGSEGV);
         if (ret == NOTIFY_STOP)
-                return ret;
+                return 1;
 
         print_modules();
         __show_regs(regs);
         printk(KERN_EMERG "Process %.*s (pid: %d, stack limit = 0x%p)\n",
-                TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), thread + 1);
+                TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), end_of_stack(tsk));
 
         if (!user_mode(regs) || in_interrupt()) {
                 dump_mem(KERN_EMERG, "Stack: ", regs->ARM_sp,
@@ -259,45 +259,77 @@ static int __die(const char *str, int err, struct thread_info *thread, struct pt
                 dump_instr(KERN_EMERG, regs);
         }
 
-        return ret;
+        return 0;
 }
 
-static DEFINE_RAW_SPINLOCK(die_lock);
+static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int die_owner = -1;
+static unsigned int die_nest_count;
 
-/*
- * This function is protected against re-entrancy.
- */
-void die(const char *str, struct pt_regs *regs, int err)
+static unsigned long oops_begin(void)
 {
-        struct thread_info *thread = current_thread_info();
-        int ret;
-        enum bug_trap_type bug_type = BUG_TRAP_TYPE_NONE;
+        int cpu;
+        unsigned long flags;
 
         oops_enter();
 
-        raw_spin_lock_irq(&die_lock);
+        /* racy, but better than risking deadlock. */
+        raw_local_irq_save(flags);
+        cpu = smp_processor_id();
+        if (!arch_spin_trylock(&die_lock)) {
+                if (cpu == die_owner)
+                        /* nested oops. should stop eventually */;
+                else
+                        arch_spin_lock(&die_lock);
+        }
+        die_nest_count++;
+        die_owner = cpu;
         console_verbose();
         bust_spinlocks(1);
-        if (!user_mode(regs))
-                bug_type = report_bug(regs->ARM_pc, regs);
-        if (bug_type != BUG_TRAP_TYPE_NONE)
-                str = "Oops - BUG";
-        ret = __die(str, err, thread, regs);
+        return flags;
+}
 
-        if (regs && kexec_should_crash(thread->task))
+static void oops_end(unsigned long flags, struct pt_regs *regs, int signr)
+{
+        if (regs && kexec_should_crash(current))
                 crash_kexec(regs);
 
         bust_spinlocks(0);
+        die_owner = -1;
         add_taint(TAINT_DIE);
-        raw_spin_unlock_irq(&die_lock);
+        die_nest_count--;
+        if (!die_nest_count)
+                /* Nest count reaches zero, release the lock. */
+                arch_spin_unlock(&die_lock);
+        raw_local_irq_restore(flags);
         oops_exit();
 
         if (in_interrupt())
                 panic("Fatal exception in interrupt");
         if (panic_on_oops)
                 panic("Fatal exception");
-        if (ret != NOTIFY_STOP)
-                do_exit(SIGSEGV);
+        if (signr)
+                do_exit(signr);
+}
+
+/*
+ * This function is protected against re-entrancy.
+ */
+void die(const char *str, struct pt_regs *regs, int err)
+{
+        enum bug_trap_type bug_type = BUG_TRAP_TYPE_NONE;
+        unsigned long flags = oops_begin();
+        int sig = SIGSEGV;
+
+        if (!user_mode(regs))
+                bug_type = report_bug(regs->ARM_pc, regs);
+        if (bug_type != BUG_TRAP_TYPE_NONE)
+                str = "Oops - BUG";
+
+        if (__die(str, err, regs))
+                sig = 0;
+
+        oops_end(flags, regs, sig);
 }
 
 void arm_notify_die(const char *str, struct pt_regs *regs,
@@ -370,18 +402,10 @@ static int call_undef_hook(struct pt_regs *regs, unsigned int instr)
 
 asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
 {
-        unsigned int correction = thumb_mode(regs) ? 2 : 4;
         unsigned int instr;
         siginfo_t info;
         void __user *pc;
 
-        /*
-         * According to the ARM ARM, PC is 2 or 4 bytes ahead,
-         * depending whether we're in Thumb mode or not.
-         * Correct this offset.
-         */
-        regs->ARM_pc -= correction;
-
         pc = (void __user *)instruction_pointer(regs);
 
         if (processor_mode(regs) == SVC_MODE) {
@@ -820,8 +844,6 @@ void __init early_trap_init(void *vectors_base)
          */
         memcpy((void *)(vectors + KERN_SIGRETURN_CODE - CONFIG_VECTORS_BASE),
                sigreturn_codes, sizeof(sigreturn_codes));
-        memcpy((void *)(vectors + KERN_RESTART_CODE - CONFIG_VECTORS_BASE),
-               syscall_restart_code, sizeof(syscall_restart_code));
 
         flush_icache_range(vectors, vectors + PAGE_SIZE);
         modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 992769ae259..af72969820b 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -6,9 +6,8 @@
 
 lib-y           := backtrace.o changebit.o csumipv6.o csumpartial.o   \
                    csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
-                   delay.o findbit.o memchr.o memcpy.o                \
+                   delay.o delay-loop.o findbit.o memchr.o memcpy.o   \
                    memmove.o memset.o memzero.o setbit.o              \
-                   strncpy_from_user.o strnlen_user.o                 \
                    strchr.o strrchr.o                                 \
                    testchangebit.o testclearbit.o testsetbit.o        \
                    ashldi3.o ashrdi3.o lshrdi3.o muldi3.o             \
@@ -17,13 +16,30 @@ lib-y		:= backtrace.o changebit.o csumipv6.o csumpartial.o   \
                    call_with_stack.o
 
 mmu-y   := clear_user.o copy_page.o getuser.o putuser.o
-mmu-y   += copy_from_user.o copy_to_user.o
+
+# the code in uaccess.S is not preemption safe and
+# probably faster on ARMv3 only
+ifeq ($(CONFIG_PREEMPT),y)
+  mmu-y += copy_from_user.o copy_to_user.o
+else
+ifneq ($(CONFIG_CPU_32v3),y)
+  mmu-y += copy_from_user.o copy_to_user.o
+else
+  mmu-y += uaccess.o
+endif
+endif
 
 # using lib_ here won't override already available weak symbols
 obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o
 
-lib-$(CONFIG_MMU)               += $(mmu-y)
-lib-y                           += io-readsw-armv4.o io-writesw-armv4.o
+lib-$(CONFIG_MMU) += $(mmu-y)
+
+ifeq ($(CONFIG_CPU_32v3),y)
+  lib-y += io-readsw-armv3.o io-writesw-armv3.o
+else
+  lib-y += io-readsw-armv4.o io-writesw-armv4.o
+endif
+
 lib-$(CONFIG_ARCH_RPC)          += ecard.o io-acorn.o floppydma.o
 lib-$(CONFIG_ARCH_SHARK)        += io-shark.o
 
diff --git a/arch/arm/lib/delay.S b/arch/arm/lib/delay-loop.S
index 3c9a05c8d20..36b668d8e12 100644
--- a/arch/arm/lib/delay.S
+++ b/arch/arm/lib/delay-loop.S
@@ -9,11 +9,11 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/param.h>
+#include <asm/delay.h>
                 .text
 
 .LC0:           .word   loops_per_jiffy
-.LC1:           .word   (2199023*HZ)>>11
+.LC1:           .word   UDELAY_MULT
 
 /*
  * r0  <= 2000
@@ -21,10 +21,10 @@
  * HZ  <= 1000
  */
 
-ENTRY(__udelay)
+ENTRY(__loop_udelay)
                 ldr     r2, .LC1
                 mul     r0, r2, r0
-ENTRY(__const_udelay)                           @ 0 <= r0 <= 0x7fffff06
+ENTRY(__loop_const_udelay)                      @ 0 <= r0 <= 0x7fffff06
                 mov     r1, #-1
                 ldr     r2, .LC0
                 ldr     r2, [r2]                @ max = 0x01ffffff
@@ -39,12 +39,10 @@ ENTRY(__const_udelay)				@ 0 <= r0 <= 0x7fffff06
 
 /*
  * loops = r0 * HZ * loops_per_jiffy / 1000000
- *
- * Oh, if only we had a cycle counter...
  */
 
 @ Delay routine
-ENTRY(__delay)
+ENTRY(__loop_delay)
                 subs    r0, r0, #1
 #if 0
                 movls   pc, lr
@@ -62,8 +60,8 @@ ENTRY(__delay)
                 movls   pc, lr
                 subs    r0, r0, #1
 #endif
-                bhi     __delay
+                bhi     __loop_delay
                 mov     pc, lr
-ENDPROC(__udelay)
-ENDPROC(__const_udelay)
-ENDPROC(__delay)
+ENDPROC(__loop_udelay)
+ENDPROC(__loop_const_udelay)
+ENDPROC(__loop_delay)
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
new file mode 100644
index 00000000000..d6dacc69254
--- /dev/null
+++ b/arch/arm/lib/delay.c
@@ -0,0 +1,71 @@
+/*
+ * Delay loops based on the OpenRISC implementation.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/timex.h>
+
+/*
+ * Default to the loop-based delay implementation.
+ */
+struct arm_delay_ops arm_delay_ops = {
+        .delay          = __loop_delay,
+        .const_udelay   = __loop_const_udelay,
+        .udelay         = __loop_udelay,
+};
+
+#ifdef ARCH_HAS_READ_CURRENT_TIMER
+static void __timer_delay(unsigned long cycles)
+{
+        cycles_t start = get_cycles();
+
+        while ((get_cycles() - start) < cycles)
+                cpu_relax();
+}
+
+static void __timer_const_udelay(unsigned long xloops)
+{
+        unsigned long long loops = xloops;
+        loops *= loops_per_jiffy;
+        __timer_delay(loops >> UDELAY_SHIFT);
+}
+
+static void __timer_udelay(unsigned long usecs)
+{
+        __timer_const_udelay(usecs * UDELAY_MULT);
+}
+
+void __init init_current_timer_delay(unsigned long freq)
+{
+        pr_info("Switching to timer-based delay loop\n");
+        lpj_fine                        = freq / HZ;
+        arm_delay_ops.delay             = __timer_delay;
+        arm_delay_ops.const_udelay      = __timer_const_udelay;
+        arm_delay_ops.udelay            = __timer_udelay;
+}
+
+unsigned long __cpuinit calibrate_delay_is_known(void)
+{
+        return lpj_fine;
+}
+#endif
diff --git a/arch/arm/lib/io-acorn.S b/arch/arm/lib/io-acorn.S
index 1b197ea7aab..69719bad674 100644
--- a/arch/arm/lib/io-acorn.S
+++ b/arch/arm/lib/io-acorn.S
@@ -11,13 +11,14 @@
  *
  */
 #include <linux/linkage.h>
+#include <linux/kern_levels.h>
 #include <asm/assembler.h>
 
                 .text
                 .align
 
 .Liosl_warning:
-                .ascii  "<4>insl/outsl not implemented, called from %08lX\0"
+                .ascii  KERN_WARNING "insl/outsl not implemented, called from %08lX\0"
                 .align
 
 /*
diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S
new file mode 100644
index 00000000000..88487c8c4f2
--- /dev/null
+++ b/arch/arm/lib/io-readsw-armv3.S
@@ -0,0 +1,106 @@
+/*
+ *  linux/arch/arm/lib/io-readsw-armv3.S
+ *
+ *  Copyright (C) 1995-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+.Linsw_bad_alignment:
+                adr     r0, .Linsw_bad_align_msg
+                mov     r2, lr
+                b       panic
+.Linsw_bad_align_msg:
+                .asciz  "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
+                .align
+
+.Linsw_align:   tst     r1, #1
+                bne     .Linsw_bad_alignment
+
+                ldr     r3, [r0]
+                strb    r3, [r1], #1
+                mov     r3, r3, lsr #8
+                strb    r3, [r1], #1
+
+                subs    r2, r2, #1
+                moveq   pc, lr
+
+ENTRY(__raw_readsw)
+                teq     r2, #0          @ do we have to check for the zero len?
+                moveq   pc, lr
+                tst     r1, #3
+                bne     .Linsw_align
+
+.Linsw_aligned: mov     ip, #0xff
+                orr     ip, ip, ip, lsl #8
+                stmfd   sp!, {r4, r5, r6, lr}
+
+                subs    r2, r2, #8
+                bmi     .Lno_insw_8
+
+.Linsw_8_lp:    ldr     r3, [r0]
+                and     r3, r3, ip
+                ldr     r4, [r0]
+                orr     r3, r3, r4, lsl #16
+
+                ldr     r4, [r0]
+                and     r4, r4, ip
+                ldr     r5, [r0]
+                orr     r4, r4, r5, lsl #16
+
+                ldr     r5, [r0]
+                and     r5, r5, ip
+                ldr     r6, [r0]
+                orr     r5, r5, r6, lsl #16
+
+                ldr     r6, [r0]
+                and     r6, r6, ip
+                ldr     lr, [r0]
+                orr     r6, r6, lr, lsl #16
+
+                stmia   r1!, {r3 - r6}
+
+                subs    r2, r2, #8
+                bpl     .Linsw_8_lp
+
+                tst     r2, #7
+                ldmeqfd sp!, {r4, r5, r6, pc}
+
+.Lno_insw_8:    tst     r2, #4
+                beq     .Lno_insw_4
+
+                ldr     r3, [r0]
+                and     r3, r3, ip
+                ldr     r4, [r0]
+                orr     r3, r3, r4, lsl #16
+
+                ldr     r4, [r0]
+                and     r4, r4, ip
+                ldr     r5, [r0]
+                orr     r4, r4, r5, lsl #16
+
+                stmia   r1!, {r3, r4}
+
+.Lno_insw_4:    tst     r2, #2
+                beq     .Lno_insw_2
+
+                ldr     r3, [r0]
+                and     r3, r3, ip
+                ldr     r4, [r0]
+                orr     r3, r3, r4, lsl #16
+
+                str     r3, [r1], #4
+
+.Lno_insw_2:    tst     r2, #1
+                ldrne   r3, [r0]
+                strneb  r3, [r1], #1
+                movne   r3, r3, lsr #8
+                strneb  r3, [r1]
+
+                ldmfd   sp!, {r4, r5, r6, pc}
+
+
diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S
new file mode 100644
index 00000000000..49b800419e3
--- /dev/null
+++ b/arch/arm/lib/io-writesw-armv3.S
@@ -0,0 +1,126 @@
+/*
+ *  linux/arch/arm/lib/io-writesw-armv3.S
+ *
+ *  Copyright (C) 1995-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+.Loutsw_bad_alignment:
+                adr     r0, .Loutsw_bad_align_msg
+                mov     r2, lr
+                b       panic
+.Loutsw_bad_align_msg:
+                .asciz  "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
+                .align
+
+.Loutsw_align:  tst     r1, #1
+                bne     .Loutsw_bad_alignment
+
+                add     r1, r1, #2
+
+                ldr     r3, [r1, #-4]
+                mov     r3, r3, lsr #16
+                orr     r3, r3, r3, lsl #16
+                str     r3, [r0]
+                subs    r2, r2, #1
+                moveq   pc, lr
+
+ENTRY(__raw_writesw)
+                teq     r2, #0          @ do we have to check for the zero len?
+                moveq   pc, lr
+                tst     r1, #3
+                bne     .Loutsw_align
+
+                stmfd   sp!, {r4, r5, r6, lr}
+
+                subs    r2, r2, #8
+                bmi     .Lno_outsw_8
+
+.Loutsw_8_lp:   ldmia   r1!, {r3, r4, r5, r6}
+
+                mov     ip, r3, lsl #16
+                orr     ip, ip, ip, lsr #16
+                str     ip, [r0]
+
+                mov     ip, r3, lsr #16
+                orr     ip, ip, ip, lsl #16
+                str     ip, [r0]
+
+                mov     ip, r4, lsl #16
+                orr     ip, ip, ip, lsr #16
+                str     ip, [r0]
+
+                mov     ip, r4, lsr #16
+                orr     ip, ip, ip, lsl #16
+                str     ip, [r0]
+
+                mov     ip, r5, lsl #16
+                orr     ip, ip, ip, lsr #16
+                str     ip, [r0]
+
+                mov     ip, r5, lsr #16
+                orr     ip, ip, ip, lsl #16
+                str     ip, [r0]
+
+                mov     ip, r6, lsl #16
+                orr     ip, ip, ip, lsr #16
+                str     ip, [r0]
+
+                mov     ip, r6, lsr #16
+                orr     ip, ip, ip, lsl #16
+                str     ip, [r0]
+
+                subs    r2, r2, #8
+                bpl     .Loutsw_8_lp
+
+                tst     r2, #7
+                ldmeqfd sp!, {r4, r5, r6, pc}
+
+.Lno_outsw_8:   tst     r2, #4
+                beq     .Lno_outsw_4
+
+                ldmia   r1!, {r3, r4}
+
+                mov     ip, r3, lsl #16
+                orr     ip, ip, ip, lsr #16
+                str     ip, [r0]
+
+                mov     ip, r3, lsr #16
+                orr     ip, ip, ip, lsl #16
+                str     ip, [r0]
+
+                mov     ip, r4, lsl #16
+                orr     ip, ip, ip, lsr #16
+                str     ip, [r0]
+
+                mov     ip, r4, lsr #16
+                orr     ip, ip, ip, lsl #16
+                str     ip, [r0]
+
+.Lno_outsw_4:   tst     r2, #2
+                beq     .Lno_outsw_2
+
+                ldr     r3, [r1], #4
+
+                mov     ip, r3, lsl #16
+                orr     ip, ip, ip, lsr #16
+                str     ip, [r0]
+
+                mov     ip, r3, lsr #16
+                orr     ip, ip, ip, lsl #16
+                str     ip, [r0]
+
+.Lno_outsw_2:   tst     r2, #1
+
+                ldrne   r3, [r1]
+
+                movne   ip, r3, lsl #16
+                orrne   ip, ip, ip, lsr #16
+                strne   ip, [r0]
+
+                ldmfd   sp!, {r4, r5, r6, pc}
diff --git a/arch/arm/lib/strncpy_from_user.S b/arch/arm/lib/strncpy_from_user.S
deleted file mode 100644
index f202d7bd164..00000000000
--- a/arch/arm/lib/strncpy_from_user.S
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  linux/arch/arm/lib/strncpy_from_user.S
- *
- *  Copyright (C) 1995-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/errno.h>
-
-        .text
-        .align  5
-
-/*
- * Copy a string from user space to kernel space.
- *  r0 = dst, r1 = src, r2 = byte length
- * returns the number of characters copied (strlen of copied string),
- *  -EFAULT on exception, or "len" if we fill the whole buffer
- */
-ENTRY(__strncpy_from_user)
-        mov     ip, r1
-1:      subs    r2, r2, #1
-        ldrusr  r3, r1, 1, pl
-        bmi     2f
-        strb    r3, [r0], #1
-        teq     r3, #0
-        bne     1b
-        sub     r1, r1, #1      @ take NUL character out of count
-2:      sub     r0, r1, ip
-        mov     pc, lr
-ENDPROC(__strncpy_from_user)
-
-        .pushsection .fixup,"ax"
-        .align  0
-9001:   mov     r3, #0
-        strb    r3, [r0, #0]    @ null terminate
-        mov     r0, #-EFAULT
-        mov     pc, lr
-        .popsection
-
diff --git a/arch/arm/lib/strnlen_user.S b/arch/arm/lib/strnlen_user.S
deleted file mode 100644
index 0ecbb459c4f..00000000000
--- a/arch/arm/lib/strnlen_user.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- *  linux/arch/arm/lib/strnlen_user.S
- *
- *  Copyright (C) 1995-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/errno.h>
-
-        .text
-        .align  5
-
-/* Prototype: unsigned long __strnlen_user(const char *str, long n)
- * Purpose  : get length of a string in user memory
- * Params   : str - address of string in user memory
- * Returns  : length of string *including terminator*
- *            or zero on exception, or n + 1 if too long
- */
-ENTRY(__strnlen_user)
-        mov     r2, r0
-1:
-        ldrusr  r3, r0, 1
-        teq     r3, #0
-        beq     2f
-        subs    r1, r1, #1
-        bne     1b
-        add     r0, r0, #1
-2:      sub     r0, r0, r2
-        mov     pc, lr
-ENDPROC(__strnlen_user)
-
-        .pushsection .fixup,"ax"
-        .align  0
-9001:   mov     r0, #0
-        mov     pc, lr
-        .popsection
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
new file mode 100644
index 00000000000..5c908b1cb8e
--- /dev/null
+++ b/arch/arm/lib/uaccess.S
@@ -0,0 +1,564 @@
+/*
+ *  linux/arch/arm/lib/uaccess.S
+ *
+ *  Copyright (C) 1995, 1996,1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Routines to block copy data to/from user memory
+ *   These are highly optimised both for the 4k page size
+ *   and for various alignments.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/errno.h>
+#include <asm/domain.h>
+
+                .text
+
+#define PAGE_SHIFT 12
+
+/* Prototype: int __copy_to_user(void *to, const char *from, size_t n)
+ * Purpose  : copy a block to user memory from kernel memory
+ * Params   : to   - user memory
+ *          : from - kernel memory
+ *          : n    - number of bytes to copy
+ * Returns  : Number of bytes NOT copied.
+ */
+
+.Lc2u_dest_not_aligned:
+                rsb     ip, ip, #4
+                cmp     ip, #2
+                ldrb    r3, [r1], #1
+USER(   TUSER(  strb)   r3, [r0], #1)                   @ May fault
+                ldrgeb  r3, [r1], #1
+USER(   TUSER(  strgeb) r3, [r0], #1)                   @ May fault
+                ldrgtb  r3, [r1], #1
+USER(   TUSER(  strgtb) r3, [r0], #1)                   @ May fault
+                sub     r2, r2, ip
+                b       .Lc2u_dest_aligned
+
+ENTRY(__copy_to_user)
+                stmfd   sp!, {r2, r4 - r7, lr}
+                cmp     r2, #4
+                blt     .Lc2u_not_enough
+                ands    ip, r0, #3
+                bne     .Lc2u_dest_not_aligned
+.Lc2u_dest_aligned:
+
+                ands    ip, r1, #3
+                bne     .Lc2u_src_not_aligned
+/*
+ * Seeing as there has to be at least 8 bytes to copy, we can
+ * copy one word, and force a user-mode page fault...
+ */
+
+.Lc2u_0fupi:    subs    r2, r2, #4
+                addmi   ip, r2, #4
+                bmi     .Lc2u_0nowords
+                ldr     r3, [r1], #4
+USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
+                mov     ip, r0, lsl #32 - PAGE_SHIFT    @ On each page, use a ld/st??t instruction
+                rsb     ip, ip, #0
+                movs    ip, ip, lsr #32 - PAGE_SHIFT
+                beq     .Lc2u_0fupi
+/*
+ * ip = max no. of bytes to copy before needing another "strt" insn
+ */
+                cmp     r2, ip
+                movlt   ip, r2
+                sub     r2, r2, ip
+                subs    ip, ip, #32
+                blt     .Lc2u_0rem8lp
+
+.Lc2u_0cpy8lp:  ldmia   r1!, {r3 - r6}
+                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
+                ldmia   r1!, {r3 - r6}
+                subs    ip, ip, #32
+                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
+                bpl     .Lc2u_0cpy8lp
+
+.Lc2u_0rem8lp:  cmn     ip, #16
+                ldmgeia r1!, {r3 - r6}
+                stmgeia r0!, {r3 - r6}                  @ Shouldnt fault
+                tst     ip, #8
+                ldmneia r1!, {r3 - r4}
+                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
+                tst     ip, #4
+                ldrne   r3, [r1], #4
+        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
+                ands    ip, ip, #3
+                beq     .Lc2u_0fupi
+.Lc2u_0nowords: teq     ip, #0
+                beq     .Lc2u_finished
+.Lc2u_nowords:  cmp     ip, #2
+                ldrb    r3, [r1], #1
+USER(   TUSER(  strb)   r3, [r0], #1)                   @ May fault
+                ldrgeb  r3, [r1], #1
+USER(   TUSER(  strgeb) r3, [r0], #1)                   @ May fault
+                ldrgtb  r3, [r1], #1
+USER(   TUSER(  strgtb) r3, [r0], #1)                   @ May fault
+                b       .Lc2u_finished
+
+.Lc2u_not_enough:
+                movs    ip, r2
+                bne     .Lc2u_nowords
+.Lc2u_finished: mov     r0, #0
+                ldmfd   sp!, {r2, r4 - r7, pc}
+
+.Lc2u_src_not_aligned:
+                bic     r1, r1, #3
+                ldr     r7, [r1], #4
+                cmp     ip, #2
+                bgt     .Lc2u_3fupi
+                beq     .Lc2u_2fupi
+.Lc2u_1fupi:    subs    r2, r2, #4
+                addmi   ip, r2, #4
+                bmi     .Lc2u_1nowords
+                mov     r3, r7, pull #8
+                ldr     r7, [r1], #4
+                orr     r3, r3, r7, push #24
+USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
+                mov     ip, r0, lsl #32 - PAGE_SHIFT
+                rsb     ip, ip, #0
+                movs    ip, ip, lsr #32 - PAGE_SHIFT
+                beq     .Lc2u_1fupi
+                cmp     r2, ip
+                movlt   ip, r2
+                sub     r2, r2, ip
+                subs    ip, ip, #16
+                blt     .Lc2u_1rem8lp
+
+.Lc2u_1cpy8lp:  mov     r3, r7, pull #8
+                ldmia   r1!, {r4 - r7}
+                subs    ip, ip, #16
+                orr     r3, r3, r4, push #24
+                mov     r4, r4, pull #8
+                orr     r4, r4, r5, push #24
+                mov     r5, r5, pull #8
+                orr     r5, r5, r6, push #24
+                mov     r6, r6, pull #8
+                orr     r6, r6, r7, push #24
+                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
+                bpl     .Lc2u_1cpy8lp
+
+.Lc2u_1rem8lp:  tst     ip, #8
+                movne   r3, r7, pull #8
+                ldmneia r1!, {r4, r7}
+                orrne   r3, r3, r4, push #24
+                movne   r4, r4, pull #8
+                orrne   r4, r4, r7, push #24
+                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
+                tst     ip, #4
+                movne   r3, r7, pull #8
+                ldrne   r7, [r1], #4
+                orrne   r3, r3, r7, push #24
+        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
+                ands    ip, ip, #3
+                beq     .Lc2u_1fupi
+.Lc2u_1nowords: mov     r3, r7, get_byte_1
+                teq     ip, #0
+                beq     .Lc2u_finished
+                cmp     ip, #2
+USER(   TUSER(  strb)   r3, [r0], #1)                   @ May fault
+                movge   r3, r7, get_byte_2
+USER(   TUSER(  strgeb) r3, [r0], #1)                   @ May fault
+                movgt   r3, r7, get_byte_3
+USER(   TUSER(  strgtb) r3, [r0], #1)                   @ May fault
+                b       .Lc2u_finished
+
+.Lc2u_2fupi:    subs    r2, r2, #4
+                addmi   ip, r2, #4
+                bmi     .Lc2u_2nowords
+                mov     r3, r7, pull #16
+                ldr     r7, [r1], #4
+                orr     r3, r3, r7, push #16
+USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
+                mov     ip, r0, lsl #32 - PAGE_SHIFT
+                rsb     ip, ip, #0
+                movs    ip, ip, lsr #32 - PAGE_SHIFT
+                beq     .Lc2u_2fupi
+                cmp     r2, ip
+                movlt   ip, r2
+                sub     r2, r2, ip
+                subs    ip, ip, #16
+                blt     .Lc2u_2rem8lp
+
+.Lc2u_2cpy8lp:  mov     r3, r7, pull #16
+                ldmia   r1!, {r4 - r7}
+                subs    ip, ip, #16
+                orr     r3, r3, r4, push #16
+                mov     r4, r4, pull #16
+                orr     r4, r4, r5, push #16
+                mov     r5, r5, pull #16
+                orr     r5, r5, r6, push #16
+                mov     r6, r6, pull #16
+                orr     r6, r6, r7, push #16
+                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
+                bpl     .Lc2u_2cpy8lp
+
+.Lc2u_2rem8lp:  tst     ip, #8
+                movne   r3, r7, pull #16
+                ldmneia r1!, {r4, r7}
+                orrne   r3, r3, r4, push #16
+                movne   r4, r4, pull #16
+                orrne   r4, r4, r7, push #16
+                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
+                tst     ip, #4
+                movne   r3, r7, pull #16
+                ldrne   r7, [r1], #4
+                orrne   r3, r3, r7, push #16
+        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
+                ands    ip, ip, #3
+                beq     .Lc2u_2fupi
+.Lc2u_2nowords: mov     r3, r7, get_byte_2
+                teq     ip, #0
+                beq     .Lc2u_finished
+                cmp     ip, #2
+USER(   TUSER(  strb)   r3, [r0], #1)                   @ May fault
+                movge   r3, r7, get_byte_3
+USER(   TUSER(  strgeb) r3, [r0], #1)                   @ May fault
+                ldrgtb  r3, [r1], #0
+USER(   TUSER(  strgtb) r3, [r0], #1)                   @ May fault
+                b       .Lc2u_finished
+
+.Lc2u_3fupi:    subs    r2, r2, #4
+                addmi   ip, r2, #4
+                bmi     .Lc2u_3nowords
+                mov     r3, r7, pull #24
+                ldr     r7, [r1], #4
+                orr     r3, r3, r7, push #8
+USER(   TUSER(  str)    r3, [r0], #4)                   @ May fault
+                mov     ip, r0, lsl #32 - PAGE_SHIFT
+                rsb     ip, ip, #0
+                movs    ip, ip, lsr #32 - PAGE_SHIFT
+                beq     .Lc2u_3fupi
+                cmp     r2, ip
+                movlt   ip, r2
+                sub     r2, r2, ip
+                subs    ip, ip, #16
+                blt     .Lc2u_3rem8lp
+
+.Lc2u_3cpy8lp:  mov     r3, r7, pull #24
+                ldmia   r1!, {r4 - r7}
+                subs    ip, ip, #16
+                orr     r3, r3, r4, push #8
+                mov     r4, r4, pull #24
+                orr     r4, r4, r5, push #8
+                mov     r5, r5, pull #24
+                orr     r5, r5, r6, push #8
+                mov     r6, r6, pull #24
+                orr     r6, r6, r7, push #8
+                stmia   r0!, {r3 - r6}                  @ Shouldnt fault
+                bpl     .Lc2u_3cpy8lp
+
+.Lc2u_3rem8lp:  tst     ip, #8
+                movne   r3, r7, pull #24
+                ldmneia r1!, {r4, r7}
+                orrne   r3, r3, r4, push #8
+                movne   r4, r4, pull #24
+                orrne   r4, r4, r7, push #8
+                stmneia r0!, {r3 - r4}                  @ Shouldnt fault
+                tst     ip, #4
+                movne   r3, r7, pull #24
+                ldrne   r7, [r1], #4
+                orrne   r3, r3, r7, push #8
+        TUSER(  strne) r3, [r0], #4                     @ Shouldnt fault
+                ands    ip, ip, #3
+                beq     .Lc2u_3fupi
+.Lc2u_3nowords: mov     r3, r7, get_byte_3
+                teq     ip, #0
+                beq     .Lc2u_finished
+                cmp     ip, #2
+USER(   TUSER(  strb)   r3, [r0], #1)                   @ May fault
+                ldrgeb  r3, [r1], #1
+USER(   TUSER(  strgeb) r3, [r0], #1)                   @ May fault
+                ldrgtb  r3, [r1], #0
+USER(   TUSER(  strgtb) r3, [r0], #1)                   @ May fault
+                b       .Lc2u_finished
+ENDPROC(__copy_to_user)
+
+                .pushsection .fixup,"ax"
+                .align  0
+9001:           ldmfd   sp!, {r0, r4 - r7, pc}
+                .popsection
+
+/* Prototype: unsigned long __copy_from_user(void *to,const void *from,unsigned long n);
+ * Purpose  : copy a block from user memory to kernel memory
+ * Params   : to   - kernel memory
+ *          : from - user memory
+ *          : n    - number of bytes to copy
+ * Returns  : Number of bytes NOT copied.
+ */
+.Lcfu_dest_not_aligned:
+                rsb     ip, ip, #4
+                cmp     ip, #2
+USER(   TUSER(  ldrb)   r3, [r1], #1)                   @ May fault
+                strb    r3, [r0], #1
+USER(   TUSER(  ldrgeb) r3, [r1], #1)                   @ May fault
+                strgeb  r3, [r0], #1
+USER(   TUSER(  ldrgtb) r3, [r1], #1)                   @ May fault
+                strgtb  r3, [r0], #1
+                sub     r2, r2, ip
+                b       .Lcfu_dest_aligned
+
+ENTRY(__copy_from_user)
+                stmfd   sp!, {r0, r2, r4 - r7, lr}
+                cmp     r2, #4
+                blt     .Lcfu_not_enough
+                ands    ip, r0, #3
+                bne     .Lcfu_dest_not_aligned
+.Lcfu_dest_aligned:
+                ands    ip, r1, #3
+                bne     .Lcfu_src_not_aligned
+
+/*
+ * Seeing as there has to be at least 8 bytes to copy, we can
+ * copy one word, and force a user-mode page fault...
+ */
+
+.Lcfu_0fupi:    subs    r2, r2, #4
+                addmi   ip, r2, #4
+                bmi     .Lcfu_0nowords
+USER(   TUSER(  ldr)    r3, [r1], #4)
+                str     r3, [r0], #4
+                mov     ip, r1, lsl #32 - PAGE_SHIFT    @ On each page, use a ld/st??t instruction
+                rsb     ip, ip, #0
+                movs    ip, ip, lsr #32 - PAGE_SHIFT
+                beq     .Lcfu_0fupi
+/*
+ * ip = max no. of bytes to copy before needing another "strt" insn
+ */
+                cmp     r2, ip
+                movlt   ip, r2
+                sub     r2, r2, ip
+                subs    ip, ip, #32
+                blt     .Lcfu_0rem8lp
+
+.Lcfu_0cpy8lp:  ldmia   r1!, {r3 - r6}                  @ Shouldnt fault
+                stmia   r0!, {r3 - r6}
+                ldmia   r1!, {r3 - r6}                  @ Shouldnt fault
+                subs    ip, ip, #32
+                stmia   r0!, {r3 - r6}
+                bpl     .Lcfu_0cpy8lp
+
+.Lcfu_0rem8lp:  cmn     ip, #16
+                ldmgeia r1!, {r3 - r6}                  @ Shouldnt fault
+                stmgeia r0!, {r3 - r6}
+                tst     ip, #8
+                ldmneia r1!, {r3 - r4}                  @ Shouldnt fault
+                stmneia r0!, {r3 - r4}
+                tst     ip, #4
+        TUSER(  ldrne) r3, [r1], #4                     @ Shouldnt fault
+                strne   r3, [r0], #4
+                ands    ip, ip, #3
+                beq     .Lcfu_0fupi
+.Lcfu_0nowords: teq     ip, #0
+                beq     .Lcfu_finished
+.Lcfu_nowords:  cmp     ip, #2
+USER(   TUSER(  ldrb)   r3, [r1], #1)                   @ May fault
+                strb    r3, [r0], #1
+USER(   TUSER(  ldrgeb) r3, [r1], #1)                   @ May fault
+                strgeb  r3, [r0], #1
+USER(   TUSER(  ldrgtb) r3, [r1], #1)                   @ May fault
+                strgtb  r3, [r0], #1
+                b       .Lcfu_finished
+
+.Lcfu_not_enough:
+                movs    ip, r2
+                bne     .Lcfu_nowords
+.Lcfu_finished: mov     r0, #0
+                add     sp, sp, #8
+                ldmfd   sp!, {r4 - r7, pc}
+
+.Lcfu_src_not_aligned:
+                bic     r1, r1, #3
+USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
+                cmp     ip, #2
+                bgt     .Lcfu_3fupi
+                beq     .Lcfu_2fupi
+.Lcfu_1fupi:    subs    r2, r2, #4
+                addmi   ip, r2, #4
+                bmi     .Lcfu_1nowords
+                mov     r3, r7, pull #8
+USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
+                orr     r3, r3, r7, push #24
+                str     r3, [r0], #4
+                mov     ip, r1, lsl #32 - PAGE_SHIFT
+                rsb     ip, ip, #0
+                movs    ip, ip, lsr #32 - PAGE_SHIFT
+                beq     .Lcfu_1fupi
+                cmp     r2, ip
+                movlt   ip, r2
+                sub     r2, r2, ip
+                subs    ip, ip, #16
+                blt     .Lcfu_1rem8lp
+
+.Lcfu_1cpy8lp:  mov     r3, r7, pull #8
+                ldmia   r1!, {r4 - r7}                  @ Shouldnt fault
+                subs    ip, ip, #16
+                orr     r3, r3, r4, push #24
+                mov     r4, r4, pull #8
+                orr     r4, r4, r5, push #24
+                mov     r5, r5, pull #8
+                orr     r5, r5, r6, push #24
+                mov     r6, r6, pull #8
+                orr     r6, r6, r7, push #24
+                stmia   r0!, {r3 - r6}
+                bpl     .Lcfu_1cpy8lp
+
+.Lcfu_1rem8lp:  tst     ip, #8
+                movne   r3, r7, pull #8
+                ldmneia r1!, {r4, r7}                   @ Shouldnt fault
+                orrne   r3, r3, r4, push #24
+                movne   r4, r4, pull #8
+                orrne   r4, r4, r7, push #24
+                stmneia r0!, {r3 - r4}
+                tst     ip, #4
+                movne   r3, r7, pull #8
+USER(   TUSER(  ldrne) r7, [r1], #4)                    @ May fault
+                orrne   r3, r3, r7, push #24
+                strne   r3, [r0], #4
+                ands    ip, ip, #3
+                beq     .Lcfu_1fupi
+.Lcfu_1nowords: mov     r3, r7, get_byte_1
+                teq     ip, #0
+                beq     .Lcfu_finished
+                cmp     ip, #2
+                strb    r3, [r0], #1
+                movge   r3, r7, get_byte_2
+                strgeb  r3, [r0], #1
+                movgt   r3, r7, get_byte_3
+                strgtb  r3, [r0], #1
+                b       .Lcfu_finished
+
+.Lcfu_2fupi:    subs    r2, r2, #4
+                addmi   ip, r2, #4
+                bmi     .Lcfu_2nowords
+                mov     r3, r7, pull #16
+USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
+                orr     r3, r3, r7, push #16
+                str     r3, [r0], #4
+                mov     ip, r1, lsl #32 - PAGE_SHIFT
+                rsb     ip, ip, #0
+                movs    ip, ip, lsr #32 - PAGE_SHIFT
+                beq     .Lcfu_2fupi
+                cmp     r2, ip
+                movlt   ip, r2
+                sub     r2, r2, ip
+                subs    ip, ip, #16
+                blt     .Lcfu_2rem8lp
+
+
+.Lcfu_2cpy8lp:  mov     r3, r7, pull #16
+                ldmia   r1!, {r4 - r7}                  @ Shouldnt fault
+                subs    ip, ip, #16
+                orr     r3, r3, r4, push #16
+                mov     r4, r4, pull #16
+                orr     r4, r4, r5, push #16
+                mov     r5, r5, pull #16
+                orr     r5, r5, r6, push #16
+                mov     r6, r6, pull #16
+                orr     r6, r6, r7, push #16
+                stmia   r0!, {r3 - r6}
+                bpl     .Lcfu_2cpy8lp
+
+.Lcfu_2rem8lp:  tst     ip, #8
+                movne   r3, r7, pull #16
+                ldmneia r1!, {r4, r7}                   @ Shouldnt fault
+                orrne   r3, r3, r4, push #16
+                movne   r4, r4, pull #16
+                orrne   r4, r4, r7, push #16
+                stmneia r0!, {r3 - r4}
+                tst     ip, #4
+                movne   r3, r7, pull #16
+USER(   TUSER(  ldrne) r7, [r1], #4)                    @ May fault
+                orrne   r3, r3, r7, push #16
+                strne   r3, [r0], #4
+                ands    ip, ip, #3
+                beq     .Lcfu_2fupi
+.Lcfu_2nowords: mov     r3, r7, get_byte_2
+                teq     ip, #0
+                beq     .Lcfu_finished
+                cmp     ip, #2
+                strb    r3, [r0], #1
+                movge   r3, r7, get_byte_3
+                strgeb  r3, [r0], #1
+USER(   TUSER(  ldrgtb) r3, [r1], #0)                   @ May fault
+                strgtb  r3, [r0], #1
+                b       .Lcfu_finished
+
+.Lcfu_3fupi:    subs    r2, r2, #4
+                addmi   ip, r2, #4
+                bmi     .Lcfu_3nowords
+                mov     r3, r7, pull #24
+USER(   TUSER(  ldr)    r7, [r1], #4)                   @ May fault
+                orr     r3, r3, r7, push #8
+                str     r3, [r0], #4
+                mov     ip, r1, lsl #32 - PAGE_SHIFT
+                rsb     ip, ip, #0
+                movs    ip, ip, lsr #32 - PAGE_SHIFT
+                beq     .Lcfu_3fupi
+                cmp     r2, ip
+                movlt   ip, r2
+                sub     r2, r2, ip
+                subs    ip, ip, #16
+                blt     .Lcfu_3rem8lp
+
+.Lcfu_3cpy8lp:  mov     r3, r7, pull #24
+                ldmia   r1!, {r4 - r7}                  @ Shouldnt fault
+                orr     r3, r3, r4, push #8
+                mov     r4, r4, pull #24
+                orr     r4, r4, r5, push #8
+                mov     r5, r5, pull #24
+                orr     r5, r5, r6, push #8
+                mov     r6, r6, pull #24
+                orr     r6, r6, r7, push #8
+                stmia   r0!, {r3 - r6}
+                subs    ip, ip, #16
+                bpl     .Lcfu_3cpy8lp
+
+.Lcfu_3rem8lp:  tst     ip, #8
+                movne   r3, r7, pull #24
+                ldmneia r1!, {r4, r7}                   @ Shouldnt fault
+                orrne   r3, r3, r4, push #8
+                movne   r4, r4, pull #24
+                orrne   r4, r4, r7, push #8
+                stmneia r0!, {r3 - r4}
+                tst     ip, #4
+                movne   r3, r7, pull #24
+USER(   TUSER(  ldrne) r7, [r1], #4)                    @ May fault
+                orrne   r3, r3, r7, push #8
+                strne   r3, [r0], #4
+                ands    ip, ip, #3
+                beq     .Lcfu_3fupi
+.Lcfu_3nowords: mov     r3, r7, get_byte_3
+                teq     ip, #0
+                beq     .Lcfu_finished
+                cmp     ip, #2
+                strb    r3, [r0], #1
+USER(   TUSER(  ldrgeb) r3, [r1], #1)                   @ May fault
+                strgeb  r3, [r0], #1
+USER(   TUSER(  ldrgtb) r3, [r1], #1)                   @ May fault
+                strgtb  r3, [r0], #1
+                b       .Lcfu_finished
+ENDPROC(__copy_from_user)
+
+                .pushsection .fixup,"ax"
+                .align  0
+                /*
+                 * We took an exception.  r0 contains a pointer to
+                 * the byte not copied.
+                 */
+9001:           ldr     r2, [sp], #4                    @ void *to
+                sub     r2, r0, r2                      @ bytes copied
+                ldr     r1, [sp], #4                    @ unsigned long count
+                subs    r4, r1, r2                      @ bytes left to copy
+                movne   r1, r4
+                blne    __memzero
+                mov     r0, r4
+                ldmfd   sp!, {r4 - r7, pc}
+                .popsection
+
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 19505c0a3f0..c8050b14e61 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -29,12 +29,16 @@ comment "Atmel AT91 Processor"
 config SOC_AT91SAM9
         bool
         select CPU_ARM926T
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
         select AT91_SAM9_TIME
         select AT91_SAM9_SMC
 
 config SOC_AT91RM9200
         bool "AT91RM9200"
         select CPU_ARM920T
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
         select GENERIC_CLOCKEVENTS
         select HAVE_AT91_DBGU0
 
@@ -140,6 +144,8 @@ config ARCH_AT91SAM9G45
 config ARCH_AT91X40
         bool "AT91x40"
         depends on !MMU
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
         select ARCH_USES_GETTIMEOFFSET
 
 endchoice
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 9e84fe4f2aa..30bb7332e30 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -15,7 +15,9 @@ endif
 
 # Keep dtb files sorted alphabetically for each SoC
 # sam9260
+dtb-$(CONFIG_MACH_AT91SAM_DT) += aks-cdu.dtb
 dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += evk-pro3.dtb
 dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb
 dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb
 # sam9263
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 26917687fc3..6f50c672227 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -17,6 +17,7 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91rm9200.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_st.h>
 #include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index e6b7d0533dd..01fb7325fec 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -41,8 +41,8 @@ static struct resource usbh_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_UHP,
-                .end    = AT91RM9200_ID_UHP,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -94,8 +94,8 @@ static struct resource udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_UDP,
-                .end    = AT91RM9200_ID_UDP,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -145,8 +145,8 @@ static struct resource eth_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_EMAC,
-                .end    = AT91RM9200_ID_EMAC,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -305,8 +305,8 @@ static struct resource mmc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_MCI,
-                .end    = AT91RM9200_ID_MCI,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -488,8 +488,8 @@ static struct resource twi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_TWI,
-                .end    = AT91RM9200_ID_TWI,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -532,8 +532,8 @@ static struct resource spi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_SPI,
-                .end    = AT91RM9200_ID_SPI,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -598,18 +598,18 @@ static struct resource tcb0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_TC0,
-                .end    = AT91RM9200_ID_TC0,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91RM9200_ID_TC1,
-                .end    = AT91RM9200_ID_TC1,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91RM9200_ID_TC2,
-                .end    = AT91RM9200_ID_TC2,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -628,18 +628,18 @@ static struct resource tcb1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_TC3,
-                .end    = AT91RM9200_ID_TC3,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91RM9200_ID_TC4,
-                .end    = AT91RM9200_ID_TC4,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91RM9200_ID_TC5,
-                .end    = AT91RM9200_ID_TC5,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -673,8 +673,8 @@ static struct resource rtc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -729,8 +729,8 @@ static struct resource ssc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_SSC0,
-                .end    = AT91RM9200_ID_SSC0,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -771,8 +771,8 @@ static struct resource ssc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_SSC1,
-                .end    = AT91RM9200_ID_SSC1,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -813,8 +813,8 @@ static struct resource ssc2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_SSC2,
-                .end    = AT91RM9200_ID_SSC2,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -897,8 +897,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -935,8 +935,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_US0,
-                .end    = AT91RM9200_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -984,8 +984,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_US1,
-                .end    = AT91RM9200_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1035,8 +1035,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_US2,
-                .end    = AT91RM9200_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1078,8 +1078,8 @@ static struct resource uart3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_US3,
-                .end    = AT91RM9200_ID_US3,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 104ca40d8d1..aaa443b48c9 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -197,7 +197,7 @@ void __init at91rm9200_timer_init(void)
         at91_st_read(AT91_ST_SR);
 
         /* Make IRQs happen for the system timer */
-        setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
+        setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq);
 
         /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
          * directly for the clocksource and all clockevents, after adjusting
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 2b1e438ed87..30c7f26a466 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -20,6 +20,7 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9260.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 0ded951f785..bce572a530e 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -45,8 +45,8 @@ static struct resource usbh_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_UHP,
-                .end    = AT91SAM9260_ID_UHP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -98,8 +98,8 @@ static struct resource udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_UDP,
-                .end    = AT91SAM9260_ID_UDP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -149,8 +149,8 @@ static struct resource eth_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_EMAC,
-                .end    = AT91SAM9260_ID_EMAC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -223,8 +223,8 @@ static struct resource mmc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_MCI,
-                .end    = AT91SAM9260_ID_MCI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -305,8 +305,8 @@ static struct resource mmc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_MCI,
-                .end    = AT91SAM9260_ID_MCI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -496,8 +496,8 @@ static struct resource twi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_TWI,
-                .end    = AT91SAM9260_ID_TWI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -540,8 +540,8 @@ static struct resource spi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_SPI0,
-                .end    = AT91SAM9260_ID_SPI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -566,8 +566,8 @@ static struct resource spi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_SPI1,
-                .end    = AT91SAM9260_ID_SPI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -652,18 +652,18 @@ static struct resource tcb0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_TC0,
-                .end    = AT91SAM9260_ID_TC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91SAM9260_ID_TC1,
-                .end    = AT91SAM9260_ID_TC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91SAM9260_ID_TC2,
-                .end    = AT91SAM9260_ID_TC2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -682,18 +682,18 @@ static struct resource tcb1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_TC3,
-                .end    = AT91SAM9260_ID_TC3,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91SAM9260_ID_TC4,
-                .end    = AT91SAM9260_ID_TC4,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91SAM9260_ID_TC5,
-                .end    = AT91SAM9260_ID_TC5,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -726,6 +726,8 @@ static struct resource rtt_resources[] = {
                 .flags  = IORESOURCE_MEM,
         }, {
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -744,10 +746,12 @@ static void __init at91_add_device_rtt_rtc(void)
          * The second resource is needed:
          * GPBR will serve as the storage for RTC time offset
          */
-        at91sam9260_rtt_device.num_resources = 2;
+        at91sam9260_rtt_device.num_resources = 3;
         rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
                                  4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
         rtt_resources[1].end = rtt_resources[1].start + 3;
+        rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
+        rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
 }
 #else
 static void __init at91_add_device_rtt_rtc(void)
@@ -807,8 +811,8 @@ static struct resource ssc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_SSC,
-                .end    = AT91SAM9260_ID_SSC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -882,8 +886,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -920,8 +924,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US0,
-                .end    = AT91SAM9260_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -971,8 +975,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US1,
-                .end    = AT91SAM9260_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1014,8 +1018,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US2,
-                .end    = AT91SAM9260_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1057,8 +1061,8 @@ static struct resource uart3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US3,
-                .end    = AT91SAM9260_ID_US3,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1100,8 +1104,8 @@ static struct resource uart4_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US4,
-                .end    = AT91SAM9260_ID_US4,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1138,8 +1142,8 @@ static struct resource uart5_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US5,
-                .end    = AT91SAM9260_ID_US5,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1357,8 +1361,8 @@ static struct resource adc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_ADC,
-                .end    = AT91SAM9260_ID_ADC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index c77d503d09d..f40762c5fed 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -19,6 +19,7 @@
 #include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91sam9261.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 9295e90b08f..bc2590d712d 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -45,8 +45,8 @@ static struct resource usbh_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_UHP,
-                .end    = AT91SAM9261_ID_UHP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -98,8 +98,8 @@ static struct resource udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_UDP,
-                .end    = AT91SAM9261_ID_UDP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -148,8 +148,8 @@ static struct resource mmc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_MCI,
-                .end    = AT91SAM9261_ID_MCI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -310,8 +310,8 @@ static struct resource twi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_TWI,
-                .end    = AT91SAM9261_ID_TWI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -354,8 +354,8 @@ static struct resource spi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_SPI0,
-                .end    = AT91SAM9261_ID_SPI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -380,8 +380,8 @@ static struct resource spi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_SPI1,
-                .end    = AT91SAM9261_ID_SPI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -468,8 +468,8 @@ static struct resource lcdc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_LCDC,
-                .end    = AT91SAM9261_ID_LCDC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
                 .flags  = IORESOURCE_IRQ,
         },
 #if defined(CONFIG_FB_INTSRAM)
@@ -566,18 +566,18 @@ static struct resource tcb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_TC0,
-                .end    = AT91SAM9261_ID_TC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91SAM9261_ID_TC1,
-                .end    = AT91SAM9261_ID_TC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91SAM9261_ID_TC2,
-                .end    = AT91SAM9261_ID_TC2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -609,6 +609,8 @@ static struct resource rtt_resources[] = {
                 .flags  = IORESOURCE_MEM,
         }, {
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_IRQ,
         }
 };
 
@@ -626,10 +628,12 @@ static void __init at91_add_device_rtt_rtc(void)
          * The second resource is needed:
          * GPBR will serve as the storage for RTC time offset
          */
-        at91sam9261_rtt_device.num_resources = 2;
+        at91sam9261_rtt_device.num_resources = 3;
         rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
                                  4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
         rtt_resources[1].end = rtt_resources[1].start + 3;
+        rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
+        rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
 }
 #else
 static void __init at91_add_device_rtt_rtc(void)
@@ -689,8 +693,8 @@ static struct resource ssc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_SSC0,
-                .end    = AT91SAM9261_ID_SSC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -731,8 +735,8 @@ static struct resource ssc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_SSC1,
-                .end    = AT91SAM9261_ID_SSC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -773,8 +777,8 @@ static struct resource ssc2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_SSC2,
-                .end    = AT91SAM9261_ID_SSC2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -857,8 +861,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -895,8 +899,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_US0,
-                .end    = AT91SAM9261_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -938,8 +942,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_US1,
-                .end    = AT91SAM9261_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -981,8 +985,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_US2,
-                .end    = AT91SAM9261_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index ed91c7e9f7c..84b38105231 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -18,6 +18,7 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91sam9263.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 175e0009eaa..9b6ca734f1a 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -44,8 +44,8 @@ static struct resource usbh_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_UHP,
-                .end    = AT91SAM9263_ID_UHP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -104,8 +104,8 @@ static struct resource udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_UDP,
-                .end    = AT91SAM9263_ID_UDP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -155,8 +155,8 @@ static struct resource eth_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_EMAC,
-                .end    = AT91SAM9263_ID_EMAC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -229,8 +229,8 @@ static struct resource mmc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_MCI0,
-                .end    = AT91SAM9263_ID_MCI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -254,8 +254,8 @@ static struct resource mmc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_MCI1,
-                .end    = AT91SAM9263_ID_MCI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -567,8 +567,8 @@ static struct resource twi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_TWI,
-                .end    = AT91SAM9263_ID_TWI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -611,8 +611,8 @@ static struct resource spi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_SPI0,
-                .end    = AT91SAM9263_ID_SPI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -637,8 +637,8 @@ static struct resource spi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_SPI1,
-                .end    = AT91SAM9263_ID_SPI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -725,8 +725,8 @@ static struct resource ac97_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_AC97C,
-                .end    = AT91SAM9263_ID_AC97C,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -776,8 +776,8 @@ static struct resource can_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_CAN,
-                .end    = AT91SAM9263_ID_CAN,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -816,8 +816,8 @@ static struct resource lcdc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_LCDC,
-                .end    = AT91SAM9263_ID_LCDC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -883,8 +883,8 @@ struct resource isi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_ISI,
-                .end    = AT91SAM9263_ID_ISI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -940,8 +940,8 @@ static struct resource tcb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_TCB,
-                .end    = AT91SAM9263_ID_TCB,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -990,6 +990,8 @@ static struct resource rtt0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         }, {
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_IRQ,
         }
 };
 
@@ -1006,6 +1008,8 @@ static struct resource rtt1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         }, {
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_IRQ,
         }
 };
 
@@ -1027,14 +1031,14 @@ static void __init at91_add_device_rtt_rtc(void)
                  * The second resource is needed only for the chosen RTT:
                  * GPBR will serve as the storage for RTC time offset
                  */
-                at91sam9263_rtt0_device.num_resources = 2;
+                at91sam9263_rtt0_device.num_resources = 3;
                 at91sam9263_rtt1_device.num_resources = 1;
                 pdev = &at91sam9263_rtt0_device;
                 r = rtt0_resources;
                 break;
         case 1:
                 at91sam9263_rtt0_device.num_resources = 1;
-                at91sam9263_rtt1_device.num_resources = 2;
+                at91sam9263_rtt1_device.num_resources = 3;
                 pdev = &at91sam9263_rtt1_device;
                 r = rtt1_resources;
                 break;
@@ -1047,6 +1051,8 @@ static void __init at91_add_device_rtt_rtc(void)
         pdev->name = "rtc-at91sam9";
         r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
         r[1].end = r[1].start + 3;
+        r[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
+        r[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
 }
 #else
 static void __init at91_add_device_rtt_rtc(void)
@@ -1108,8 +1114,8 @@ static struct resource pwm_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_PWMC,
-                .end    = AT91SAM9263_ID_PWMC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1161,8 +1167,8 @@ static struct resource ssc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_SSC0,
-                .end    = AT91SAM9263_ID_SSC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1203,8 +1209,8 @@ static struct resource ssc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_SSC1,
-                .end    = AT91SAM9263_ID_SSC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1284,8 +1290,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1322,8 +1328,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_US0,
-                .end    = AT91SAM9263_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1365,8 +1371,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_US1,
-                .end    = AT91SAM9263_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1408,8 +1414,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_US2,
-                .end    = AT91SAM9263_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index a94758b4273..ffc0957d762 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -137,7 +137,7 @@ static struct irqaction at91sam926x_pit_irq = {
         .name           = "at91_tick",
         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = at91sam926x_pit_interrupt,
-        .irq            = AT91_ID_SYS,
+        .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
 };
 
 static void at91sam926x_pit_reset(void)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 4792682d52b..ef6cedd52e3 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -18,6 +18,7 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91sam9g45.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
@@ -182,6 +183,13 @@ static struct clk adc_op_clk = {
         .rate_hz        = 13200000,
 };
 
+/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
+static struct clk aestdessha_clk = {
+        .name           = "aestdessha_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_AESTDESSHA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
 static struct clk *periph_clocks[] __initdata = {
         &pioA_clk,
         &pioB_clk,
@@ -211,6 +219,7 @@ static struct clk *periph_clocks[] __initdata = {
         &udphs_clk,
         &mmc1_clk,
         &adc_op_clk,
+        &aestdessha_clk,
         // irq0
 };
 
@@ -231,6 +240,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
         CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
+        CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
+        CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
+        CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
         /* more usart lookup table for DT entries */
         CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
         CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
@@ -387,7 +399,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
         3,      /* Ethernet */
         0,      /* Image Sensor Interface */
         2,      /* USB Device High speed port */
-        0,
+        0,      /* AESTDESSHA Crypto HW Accelerators */
         0,      /* Multimedia Card Interface 1 */
         0,
         0,      /* Advanced Interrupt Controller (IRQ0) */
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 933fc9afe7d..1b47319ca00 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
 #include <linux/atmel-mci.h>
+#include <linux/platform_data/atmel-aes.h>
 
 #include <linux/platform_data/at91_adc.h>
 
@@ -53,8 +54,8 @@ static struct resource hdmac_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_DMA,
-                .end    = AT91SAM9G45_ID_DMA,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -94,8 +95,8 @@ static struct resource usbh_ohci_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_UHPHS,
-                .end    = AT91SAM9G45_ID_UHPHS,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -156,8 +157,8 @@ static struct resource usbh_ehci_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_UHPHS,
-                .end    = AT91SAM9G45_ID_UHPHS,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -213,8 +214,8 @@ static struct resource usba_udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = AT91SAM9G45_ID_UDPHS,
-                .end    = AT91SAM9G45_ID_UDPHS,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -296,8 +297,8 @@ static struct resource eth_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_EMAC,
-                .end    = AT91SAM9G45_ID_EMAC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -370,8 +371,8 @@ static struct resource mmc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_MCI0,
-                .end    = AT91SAM9G45_ID_MCI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -395,8 +396,8 @@ static struct resource mmc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_MCI1,
-                .end    = AT91SAM9G45_ID_MCI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -645,8 +646,8 @@ static struct resource twi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TWI0,
-                .end    = AT91SAM9G45_ID_TWI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -665,8 +666,8 @@ static struct resource twi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TWI1,
-                .end    = AT91SAM9G45_ID_TWI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -720,8 +721,8 @@ static struct resource spi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_SPI0,
-                .end    = AT91SAM9G45_ID_SPI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -746,8 +747,8 @@ static struct resource spi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_SPI1,
-                .end    = AT91SAM9G45_ID_SPI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -834,8 +835,8 @@ static struct resource ac97_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_AC97C,
-                .end    = AT91SAM9G45_ID_AC97C,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -887,8 +888,8 @@ struct resource isi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_ISI,
-                .end    = AT91SAM9G45_ID_ISI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -979,8 +980,8 @@ static struct resource lcdc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_LCDC,
-                .end    = AT91SAM9G45_ID_LCDC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1054,8 +1055,8 @@ static struct resource tcb0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TCB,
-                .end    = AT91SAM9G45_ID_TCB,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1075,8 +1076,8 @@ static struct resource tcb1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TCB,
-                .end    = AT91SAM9G45_ID_TCB,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1110,8 +1111,8 @@ static struct resource rtc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1147,8 +1148,8 @@ static struct resource tsadcc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TSC,
-                .end    = AT91SAM9G45_ID_TSC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -1197,8 +1198,8 @@ static struct resource adc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TSC,
-                .end    = AT91SAM9G45_ID_TSC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -1292,6 +1293,8 @@ static struct resource rtt_resources[] = {
                 .flags  = IORESOURCE_MEM,
         }, {
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_IRQ,
         }
 };
 
@@ -1309,10 +1312,12 @@ static void __init at91_add_device_rtt_rtc(void)
          * The second resource is needed:
          * GPBR will serve as the storage for RTC time offset
          */
-        at91sam9g45_rtt_device.num_resources = 2;
+        at91sam9g45_rtt_device.num_resources = 3;
         rtt_resources[1].start = AT91SAM9G45_BASE_GPBR +
                                  4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
         rtt_resources[1].end = rtt_resources[1].start + 3;
+        rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
+        rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
 }
 #else
 static void __init at91_add_device_rtt_rtc(void)
@@ -1400,8 +1405,8 @@ static struct resource pwm_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_PWMC,
-                .end    = AT91SAM9G45_ID_PWMC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1453,8 +1458,8 @@ static struct resource ssc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_SSC0,
-                .end    = AT91SAM9G45_ID_SSC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1495,8 +1500,8 @@ static struct resource ssc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_SSC1,
-                .end    = AT91SAM9G45_ID_SSC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1575,8 +1580,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1613,8 +1618,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_US0,
-                .end    = AT91SAM9G45_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1656,8 +1661,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_US1,
-                .end    = AT91SAM9G45_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1699,8 +1704,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_US2,
-                .end    = AT91SAM9G45_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1742,8 +1747,8 @@ static struct resource uart3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_US3,
-                .end    = AT91SAM9G45_ID_US3,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1830,6 +1835,130 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 void __init at91_add_device_serial(void) {}
 #endif
 
+/* --------------------------------------------------------------------
+ *  SHA1/SHA256
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_CRYPTO_DEV_ATMEL_SHA) || defined(CONFIG_CRYPTO_DEV_ATMEL_SHA_MODULE)
+static struct resource sha_resources[] = {
+        {
+                .start  = AT91SAM9G45_BASE_SHA,
+                .end    = AT91SAM9G45_BASE_SHA + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_AESTDESSHA,
+                .end    = AT91SAM9G45_ID_AESTDESSHA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_sha_device = {
+        .name   = "atmel_sha",
+        .id             = -1,
+        .resource       = sha_resources,
+        .num_resources  = ARRAY_SIZE(sha_resources),
+};
+
+static void __init at91_add_device_sha(void)
+{
+        platform_device_register(&at91sam9g45_sha_device);
+}
+#else
+static void __init at91_add_device_sha(void) {}
+#endif
+
+/* --------------------------------------------------------------------
+ *  DES/TDES
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_CRYPTO_DEV_ATMEL_TDES) || defined(CONFIG_CRYPTO_DEV_ATMEL_TDES_MODULE)
+static struct resource tdes_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_TDES,
+                .end    = AT91SAM9G45_BASE_TDES + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_AESTDESSHA,
+                .end    = AT91SAM9G45_ID_AESTDESSHA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_tdes_device = {
+        .name   = "atmel_tdes",
+        .id             = -1,
+        .resource       = tdes_resources,
+        .num_resources  = ARRAY_SIZE(tdes_resources),
+};
+
+static void __init at91_add_device_tdes(void)
+{
+        platform_device_register(&at91sam9g45_tdes_device);
+}
+#else
+static void __init at91_add_device_tdes(void) {}
+#endif
+
+/* --------------------------------------------------------------------
+ *  AES
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_CRYPTO_DEV_ATMEL_AES) || defined(CONFIG_CRYPTO_DEV_ATMEL_AES_MODULE)
+static struct aes_platform_data aes_data;
+static u64 aes_dmamask = DMA_BIT_MASK(32);
+
+static struct resource aes_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_AES,
+                .end    = AT91SAM9G45_BASE_AES + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_AESTDESSHA,
+                .end    = AT91SAM9G45_ID_AESTDESSHA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at91sam9g45_aes_device = {
+        .name   = "atmel_aes",
+        .id             = -1,
+        .dev    = {
+                .dma_mask               = &aes_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &aes_data,
+        },
+        .resource       = aes_resources,
+        .num_resources  = ARRAY_SIZE(aes_resources),
+};
+
+static void __init at91_add_device_aes(void)
+{
+        struct at_dma_slave     *atslave;
+        struct aes_dma_data     *alt_atslave;
+
+        alt_atslave = kzalloc(sizeof(struct aes_dma_data), GFP_KERNEL);
+
+        /* DMA TX slave channel configuration */
+        atslave = &alt_atslave->txdata;
+        atslave->dma_dev = &at_hdmac_device.dev;
+        atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE  | ATC_SRC_H2SEL_HW |
+                                                ATC_SRC_PER(AT_DMA_ID_AES_RX);
+
+        /* DMA RX slave channel configuration */
+        atslave = &alt_atslave->rxdata;
+        atslave->dma_dev = &at_hdmac_device.dev;
+        atslave->cfg = ATC_FIFOCFG_ENOUGHSPACE  | ATC_DST_H2SEL_HW |
+                                                ATC_DST_PER(AT_DMA_ID_AES_TX);
+
+        aes_data.dma_slave = alt_atslave;
+        platform_device_register(&at91sam9g45_aes_device);
+}
+#else
+static void __init at91_add_device_aes(void) {}
+#endif
 
 /* -------------------------------------------------------------------- */
 /*
@@ -1847,6 +1976,9 @@ static int __init at91_add_standard_devices(void)
         at91_add_device_trng();
         at91_add_device_watchdog();
         at91_add_device_tc();
+        at91_add_device_sha();
+        at91_add_device_tdes();
+        at91_add_device_aes();
         return 0;
 }
 
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index e420085a57e..72ce50a50de 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -19,6 +19,7 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9rl.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 9c0b1481a9a..b3d365dadef 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -41,8 +41,8 @@ static struct resource hdmac_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = AT91SAM9RL_ID_DMA,
-                .end    = AT91SAM9RL_ID_DMA,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -84,8 +84,8 @@ static struct resource usba_udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = AT91SAM9RL_ID_UDPHS,
-                .end    = AT91SAM9RL_ID_UDPHS,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -172,8 +172,8 @@ static struct resource mmc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_MCI,
-                .end    = AT91SAM9RL_ID_MCI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -339,8 +339,8 @@ static struct resource twi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_TWI0,
-                .end    = AT91SAM9RL_ID_TWI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -383,8 +383,8 @@ static struct resource spi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_SPI,
-                .end    = AT91SAM9RL_ID_SPI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -452,8 +452,8 @@ static struct resource ac97_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_AC97C,
-                .end    = AT91SAM9RL_ID_AC97C,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -507,8 +507,8 @@ static struct resource lcdc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_LCDC,
-                .end    = AT91SAM9RL_ID_LCDC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -574,18 +574,18 @@ static struct resource tcb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_TC0,
-                .end    = AT91SAM9RL_ID_TC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91SAM9RL_ID_TC1,
-                .end    = AT91SAM9RL_ID_TC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91SAM9RL_ID_TC2,
-                .end    = AT91SAM9RL_ID_TC2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -621,8 +621,8 @@ static struct resource tsadcc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_TSC,
-                .end    = AT91SAM9RL_ID_TSC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -688,6 +688,8 @@ static struct resource rtt_resources[] = {
                 .flags  = IORESOURCE_MEM,
         }, {
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .flags  = IORESOURCE_IRQ,
         }
 };
 
@@ -705,10 +707,12 @@ static void __init at91_add_device_rtt_rtc(void)
          * The second resource is needed:
          * GPBR will serve as the storage for RTC time offset
          */
-        at91sam9rl_rtt_device.num_resources = 2;
+        at91sam9rl_rtt_device.num_resources = 3;
         rtt_resources[1].start = AT91SAM9RL_BASE_GPBR +
                                  4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
         rtt_resources[1].end = rtt_resources[1].start + 3;
+        rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
+        rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
 }
 #else
 static void __init at91_add_device_rtt_rtc(void)
@@ -768,8 +772,8 @@ static struct resource pwm_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_PWMC,
-                .end    = AT91SAM9RL_ID_PWMC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -821,8 +825,8 @@ static struct resource ssc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_SSC0,
-                .end    = AT91SAM9RL_ID_SSC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -863,8 +867,8 @@ static struct resource ssc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_SSC1,
-                .end    = AT91SAM9RL_ID_SSC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -943,8 +947,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -981,8 +985,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_US0,
-                .end    = AT91SAM9RL_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1032,8 +1036,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_US1,
-                .end    = AT91SAM9RL_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1075,8 +1079,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_US2,
-                .end    = AT91SAM9RL_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1118,8 +1122,8 @@ static struct resource uart3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_US3,
-                .end    = AT91SAM9RL_ID_US3,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 1b144b4d3ce..477cf9d0667 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -312,8 +312,6 @@ static void __init at91sam9x5_map_io(void)
 
 void __init at91sam9x5_initialize(void)
 {
-        at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
-
         /* Register GPIO subsystem (using DT) */
         at91_gpio_init(NULL, 0);
 }
@@ -321,47 +319,9 @@ void __init at91sam9x5_initialize(void)
 /* --------------------------------------------------------------------
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller (FIQ) */
-        7,      /* System Peripherals */
-        1,      /* Parallel IO Controller A and B */
-        1,      /* Parallel IO Controller C and D */
-        4,      /* Soft Modem */
-        5,      /* USART 0 */
-        5,      /* USART 1 */
-        5,      /* USART 2 */
-        5,      /* USART 3 */
-        6,      /* Two-Wire Interface 0 */
-        6,      /* Two-Wire Interface 1 */
-        6,      /* Two-Wire Interface 2 */
-        0,      /* Multimedia Card Interface 0 */
-        5,      /* Serial Peripheral Interface 0 */
-        5,      /* Serial Peripheral Interface 1 */
-        5,      /* UART 0 */
-        5,      /* UART 1 */
-        0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-        0,      /* Pulse Width Modulation Controller */
-        0,      /* ADC Controller */
-        0,      /* DMA Controller 0 */
-        0,      /* DMA Controller 1 */
-        2,      /* USB Host High Speed port */
-        2,      /* USB Device High speed port */
-        3,      /* Ethernet MAC 0 */
-        3,      /* LDC Controller or Image Sensor Interface */
-        0,      /* Multimedia Card Interface 1 */
-        3,      /* Ethernet MAC 1 */
-        4,      /* Synchronous Serial Interface */
-        4,      /* CAN Controller 0 */
-        4,      /* CAN Controller 1 */
-        0,      /* Advanced Interrupt Controller (IRQ0) */
-};
 
 struct at91_init_soc __initdata at91sam9x5_soc = {
         .map_io = at91sam9x5_map_io,
-        .default_irq_priority = at91sam9x5_default_irq_priority,
         .register_clocks = at91sam9x5_register_clocks,
         .init = at91sam9x5_initialize,
 };
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index d62fe090d81..46090e642d8 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -13,10 +13,12 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <asm/proc-fns.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <mach/at91x40.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_st.h>
 #include <mach/timex.h>
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 271f994314a..22d8856094f 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -36,6 +36,7 @@
 
 #include <mach/board.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -91,6 +92,7 @@ MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = onearm_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = onearm_board_init,
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index b7d8aa7b81e..de7be193181 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -44,6 +44,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -212,6 +213,7 @@ MACHINE_START(AFEB9260, "Custom afeb9260 board")
         /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = afeb9260_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = afeb9260_board_init,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 29d3ef0a50f..477e708497b 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -39,6 +39,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -188,6 +189,7 @@ MACHINE_START(CAM60, "KwikByte CAM60")
         /* Maintainer: KwikByte */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = cam60_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = cam60_board_init,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 44328a6d460..a5b002f32a6 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -36,6 +36,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -158,6 +159,7 @@ MACHINE_START(CARMEVA, "Carmeva")
         /* Maintainer: Conitec Datasystems */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = carmeva_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = carmeva_board_init,
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 69951ec7dbf..ecbc13b594d 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -41,6 +41,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
 #include <mach/at91_matrix.h>
@@ -376,6 +377,7 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
         /* Maintainer: Eric Benard - EUKREA Electromatique */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = cpu9krea_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = cpu9krea_board_init,
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 895cf2dba61..2e6d043c82f 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -37,6 +37,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
@@ -178,6 +179,7 @@ MACHINE_START(CPUAT91, "Eukrea")
         /* Maintainer: Eric Benard - EUKREA Electromatique */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = cpuat91_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = cpuat91_board_init,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index cd813361cd2..462bc319cbc 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -39,6 +39,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -252,6 +253,7 @@ MACHINE_START(CSB337, "Cogent CSB337")
         /* Maintainer: Bill Gatliff */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = csb337_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = csb337_board_init,
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 7c8b05a57d7..872871ab116 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -36,6 +36,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -133,6 +134,7 @@ MACHINE_START(CSB637, "Cogent CSB637")
         /* Maintainer: Bill Gatliff */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = csb637_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = csb637_board_init,
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index a1fce05aa7a..e8f45c4e0ea 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -16,6 +16,7 @@
 #include <linux/of_platform.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -53,6 +54,7 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = at91_dt_initialize,
         .init_irq       = at91_dt_init_irq,
         .init_machine   = at91_dt_device_init,
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index d2023f27c65..01f66e99ece 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -28,6 +28,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include "generic.h"
 
 static void __init at91eb01_init_irq(void)
@@ -43,6 +44,7 @@ static void __init at91eb01_init_early(void)
 MACHINE_START(AT91EB01, "Atmel AT91 EB01")
         /* Maintainer: Greg Ungerer <gerg@snapgear.com> */
         .timer          = &at91x40_timer,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = at91eb01_init_early,
         .init_irq       = at91eb01_init_irq,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index bd101729798..d1e1f3fc0a4 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -36,6 +36,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -118,6 +119,7 @@ static void __init eb9200_board_init(void)
 MACHINE_START(ATEB9200, "Embest ATEB9200")
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = eb9200_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = eb9200_board_init,
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 89cc3726a9c..9c24cb25707 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -39,6 +39,7 @@
 
 #include <mach/board.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -170,6 +171,7 @@ MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
         /* Maintainer: emQbit.com */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ecb_at91init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ecb_at91board_init,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 558546cf63f..82bdfde3405 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -25,6 +25,7 @@
 #include <asm/mach/map.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
@@ -132,6 +133,7 @@ MACHINE_START(ECO920, "eco920")
         /* Maintainer: Sascha Hauer */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = eco920_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = eco920_board_init,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 47658f78105..6cc83a87d77 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -34,6 +34,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -160,6 +161,7 @@ MACHINE_START(FLEXIBITY, "Flexibity Connect")
         /* Maintainer: Maxim Osipov */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = flexibity_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = flexibity_board_init,
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 33411e6ecb1..69ab1247ef8 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -42,6 +42,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -262,6 +263,7 @@ MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
         /* Maintainer: Sergio Tanzilli */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = foxg20_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = foxg20_board_init,
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index 3e0dfa643a8..a9d5e78118c 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -31,6 +31,7 @@
 #include <asm/mach/arch.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/gsia18s.h>
 #include <mach/stamp9g20.h>
@@ -575,6 +576,7 @@ static void __init gsia18s_board_init(void)
 MACHINE_START(GSIA18S, "GS_IA18_S")
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = gsia18s_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = gsia18s_board_init,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index f260657f32b..64c1dbf88a0 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -35,6 +35,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
@@ -93,6 +94,7 @@ MACHINE_START(KAFA, "Sperry-Sun KAFA")
         /* Maintainer: Sergei Sharonov */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = kafa_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = kafa_board_init,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index ba39db5482b..5d96cb85175 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -37,6 +37,7 @@
 
 #include <mach/board.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
@@ -133,6 +134,7 @@ MACHINE_START(KB9200, "KB920x")
         /* Maintainer: KwikByte, Inc. */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = kb9202_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = kb9202_board_init,
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index d2f4cc16176..18103c5d993 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -45,6 +45,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -378,6 +379,7 @@ MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926")
         /* Maintainer: ADENEO */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = neocore926_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = neocore926_board_init,
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 7fe63834242..9ca3e32c54c 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -30,6 +30,7 @@
 #include <asm/mach/arch.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/stamp9g20.h>
 
@@ -218,6 +219,7 @@ MACHINE_START(PCONTROL_G20, "PControl G20")
         /* Maintainer: pgsellmann@portner-elektronik.at */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = pcontrol_g20_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = pcontrol_g20_board_init,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index b45c0a5d5ca..12706550450 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -38,6 +38,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
@@ -120,6 +121,7 @@ MACHINE_START(PICOTUX2XX, "picotux 200")
         /* Maintainer: Kleinhenz Elektronik GmbH */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = picotux200_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = picotux200_board_init,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 0c61bf0d272..bf351e28542 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -41,6 +41,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 
@@ -258,6 +259,7 @@ MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
         /* Maintainer: calao-systems */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index afd7a471376..cc2bf979607 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -40,6 +40,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
@@ -223,6 +224,7 @@ MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
         /* Maintainer: SAN People/Atmel */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = dk_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = dk_board_init,
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 2b15b8adec4..62e19e64c9d 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -40,6 +40,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
@@ -190,6 +191,7 @@ MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
         /* Maintainer: SAN People/Atmel */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index 24ab9be7510..c3b43aefdb7 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -26,6 +26,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include <linux/gpio.h>
 
@@ -225,6 +226,7 @@ MACHINE_START(RSI_EWS, "RSI EWS")
         /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = rsi_ews_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = rsi_ews_board_init,
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index cdd21f2595d..7bf6da70d7d 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -38,6 +38,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -202,6 +203,7 @@ MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
         /* Maintainer: Olimex */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 7b3c3913551..889c1bf71eb 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -42,6 +42,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
@@ -344,6 +345,7 @@ MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 2736453821b..2269be5fa38 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -46,6 +46,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
@@ -615,6 +616,7 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 983cb98d246..82adf581afc 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -45,6 +45,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
@@ -443,6 +444,7 @@ MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 6860d345110..4ea4ee00364 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -44,6 +44,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
 
@@ -413,6 +414,7 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
@@ -422,6 +424,7 @@ MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 63163dc7df4..3d48ec15468 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -43,6 +43,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
@@ -503,6 +504,7 @@ MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index be3239f13da..e7dc3ead704 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -31,6 +31,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 
@@ -319,6 +320,7 @@ MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 9d446f1bb45..a4e031a039f 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -33,6 +33,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -178,6 +179,7 @@ static void __init snapper9260_board_init(void)
 MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = snapper9260_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = snapper9260_board_init,
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index ee86f9d7ee7..29eae1626bf 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -26,6 +26,7 @@
 #include <asm/mach/arch.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -287,6 +288,7 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20")
         /* Maintainer: taskit GmbH */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = stamp9g20_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = portuxg20_board_init,
@@ -296,6 +298,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
         /* Maintainer: taskit GmbH */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = stamp9g20_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = stamp9g20evb_board_init,
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 95393fcaf19..c1476b9fe7b 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -42,6 +42,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 
@@ -358,6 +359,7 @@ MACHINE_START(USB_A9263, "CALAO USB_A9263")
         /* Maintainer: calao-systems */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
@@ -367,6 +369,7 @@ MACHINE_START(USB_A9260, "CALAO USB_A9260")
         /* Maintainer: calao-systems */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
@@ -376,6 +379,7 @@ MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
         /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index d56665ea4b5..516d340549d 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -44,6 +44,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
@@ -590,6 +591,7 @@ MACHINE_START(YL9200, "uCdragon YL-9200")
         /* Maintainer: S.Birtles */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = yl9200_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = yl9200_board_init,
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index de2ec6b8fea..188c82971eb 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -63,6 +63,12 @@ EXPORT_SYMBOL_GPL(at91_pmc_base);
 
 #define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
 
+#define cpu_has_240M_plla()     (cpu_is_at91sam9261() \
+                                || cpu_is_at91sam9263() \
+                                || cpu_is_at91sam9rl())
+
+#define cpu_has_210M_plla()     (cpu_is_at91sam9260())
+
 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
                                 || cpu_is_at91sam9g45() \
                                 || cpu_is_at91sam9x5() \
@@ -706,6 +712,12 @@ static int __init at91_pmc_init(unsigned long main_clock)
         } else if (cpu_has_800M_plla()) {
                 if (plla.rate_hz > 800000000)
                         pll_overclock = true;
+        } else if (cpu_has_240M_plla()) {
+                if (plla.rate_hz > 240000000)
+                        pll_overclock = true;
+        } else if (cpu_has_210M_plla()) {
+                if (plla.rate_hz > 210000000)
+                        pll_overclock = true;
         } else {
                 if (plla.rate_hz > 209000000)
                         pll_overclock = true;
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 0a60bf83703..f4965067765 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -29,6 +29,8 @@ extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
 extern int  __init at91_aic_of_init(struct device_node *node,
                                     struct device_node *parent);
+extern int  __init at91_aic5_of_init(struct device_node *node,
+                                    struct device_node *parent);
 
 
  /* Timer */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 325837a264c..be42cf0e74b 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -26,6 +26,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_gpio.h>
 
+#include <asm/mach/irq.h>
+
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
 
@@ -585,15 +587,14 @@ static struct irq_chip gpio_irqchip = {
 
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         struct irq_data *idata = irq_desc_get_irq_data(desc);
-        struct irq_chip *chip = irq_data_get_irq_chip(idata);
         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
         void __iomem    *pio = at91_gpio->regbase;
         unsigned long   isr;
         int             n;
 
-        /* temporarily mask (level sensitive) parent IRQ */
-        chip->irq_ack(idata);
+        chained_irq_enter(chip, desc);
         for (;;) {
                 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
                  * When there none are pending, we're finished unless we need
@@ -614,7 +615,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                         n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
                 }
         }
-        chip->irq_unmask(idata);
+        chained_irq_exit(chip, desc);
         /* now it may re-trigger */
 }
 
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
index 3045781c473..eaea66197fa 100644
--- a/arch/arm/mach-at91/include/mach/at91_aic.h
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -23,12 +23,23 @@ extern void __iomem *at91_aic_base;
         __raw_readl(at91_aic_base + field)
 
 #define at91_aic_write(field, value) \
-        __raw_writel(value, at91_aic_base + field);
+        __raw_writel(value, at91_aic_base + field)
 #else
 .extern at91_aic_base
 #endif
 
+/* Number of irq lines managed by AIC */
+#define NR_AIC_IRQS     32
+#define NR_AIC5_IRQS    128
+
+#define AT91_AIC5_SSR           0x0                     /* Source Select Register [AIC5] */
+#define         AT91_AIC5_INTSEL_MSK    (0x7f << 0)             /* Interrupt Line Selection Mask */
+
+#define AT91_AIC_IRQ_MIN_PRIORITY       0
+#define AT91_AIC_IRQ_MAX_PRIORITY       7
+
 #define AT91_AIC_SMR(n)         ((n) * 4)               /* Source Mode Registers 0-31 */
+#define AT91_AIC5_SMR           0x4                     /* Source Mode Register [AIC5] */
 #define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
 #define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
 #define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
@@ -37,29 +48,52 @@ extern void __iomem *at91_aic_base;
 #define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
 
 #define AT91_AIC_SVR(n)         (0x80 + ((n) * 4))      /* Source Vector Registers 0-31 */
+#define AT91_AIC5_SVR           0x8                     /* Source Vector Register [AIC5] */
 #define AT91_AIC_IVR            0x100                   /* Interrupt Vector Register */
+#define AT91_AIC5_IVR           0x10                    /* Interrupt Vector Register [AIC5] */
 #define AT91_AIC_FVR            0x104                   /* Fast Interrupt Vector Register */
+#define AT91_AIC5_FVR           0x14                    /* Fast Interrupt Vector Register [AIC5] */
 #define AT91_AIC_ISR            0x108                   /* Interrupt Status Register */
+#define AT91_AIC5_ISR           0x18                    /* Interrupt Status Register [AIC5] */
 #define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
 
 #define AT91_AIC_IPR            0x10c                   /* Interrupt Pending Register */
+#define AT91_AIC5_IPR0          0x20                    /* Interrupt Pending Register 0 [AIC5] */
+#define AT91_AIC5_IPR1          0x24                    /* Interrupt Pending Register 1 [AIC5] */
+#define AT91_AIC5_IPR2          0x28                    /* Interrupt Pending Register 2 [AIC5] */
+#define AT91_AIC5_IPR3          0x2c                    /* Interrupt Pending Register 3 [AIC5] */
 #define AT91_AIC_IMR            0x110                   /* Interrupt Mask Register */
+#define AT91_AIC5_IMR           0x30                    /* Interrupt Mask Register [AIC5] */
 #define AT91_AIC_CISR           0x114                   /* Core Interrupt Status Register */
+#define AT91_AIC5_CISR          0x34                    /* Core Interrupt Status Register [AIC5] */
 #define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
 #define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
 
 #define AT91_AIC_IECR           0x120                   /* Interrupt Enable Command Register */
+#define AT91_AIC5_IECR          0x40                    /* Interrupt Enable Command Register [AIC5] */
 #define AT91_AIC_IDCR           0x124                   /* Interrupt Disable Command Register */
+#define AT91_AIC5_IDCR          0x44                    /* Interrupt Disable Command Register [AIC5] */
 #define AT91_AIC_ICCR           0x128                   /* Interrupt Clear Command Register */
+#define AT91_AIC5_ICCR          0x48                    /* Interrupt Clear Command Register [AIC5] */
 #define AT91_AIC_ISCR           0x12c                   /* Interrupt Set Command Register */
+#define AT91_AIC5_ISCR          0x4c                    /* Interrupt Set Command Register [AIC5] */
 #define AT91_AIC_EOICR          0x130                   /* End of Interrupt Command Register */
+#define AT91_AIC5_EOICR         0x38                    /* End of Interrupt Command Register [AIC5] */
 #define AT91_AIC_SPU            0x134                   /* Spurious Interrupt Vector Register */
+#define AT91_AIC5_SPU           0x3c                    /* Spurious Interrupt Vector Register [AIC5] */
 #define AT91_AIC_DCR            0x138                   /* Debug Control Register */
+#define AT91_AIC5_DCR           0x6c                    /* Debug Control Register [AIC5] */
 #define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
 #define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
 
 #define AT91_AIC_FFER           0x140                   /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC5_FFER          0x50                    /* Fast Forcing Enable Register [AIC5] */
 #define AT91_AIC_FFDR           0x144                   /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC5_FFDR          0x54                    /* Fast Forcing Disable Register [AIC5] */
 #define AT91_AIC_FFSR           0x148                   /* Fast Forcing Status Register [SAM9 only] */
+#define AT91_AIC5_FFSR          0x58                    /* Fast Forcing Status Register [AIC5] */
+
+void at91_aic_handle_irq(struct pt_regs *regs);
+void at91_aic5_handle_irq(struct pt_regs *regs);
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h
deleted file mode 100644
index 2f6ba0c5636..00000000000
--- a/arch/arm/mach-at91/include/mach/at91_spi.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_spi.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Serial Peripheral Interface (SPI) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_SPI_H
-#define AT91_SPI_H
-
-#define AT91_SPI_CR                     0x00            /* Control Register */
-#define         AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
-#define         AT91_SPI_SPIDIS         (1 <<  1)               /* SPI Disable */
-#define         AT91_SPI_SWRST          (1 <<  7)               /* SPI Software Reset */
-#define         AT91_SPI_LASTXFER       (1 << 24)               /* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_MR                     0x04            /* Mode Register */
-#define         AT91_SPI_MSTR           (1    <<  0)            /* Master/Slave Mode */
-#define         AT91_SPI_PS             (1    <<  1)            /* Peripheral Select */
-#define                 AT91_SPI_PS_FIXED       (0 << 1)
-#define                 AT91_SPI_PS_VARIABLE    (1 << 1)
-#define         AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
-#define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection [AT91RM9200 only] */
-#define         AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
-#define         AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
-#define         AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
-#define         AT91_SPI_DLYBCS         (0xff << 24)            /* Delay Between Chip Selects */
-
-#define AT91_SPI_RDR            0x08                    /* Receive Data Register */
-#define         AT91_SPI_RD             (0xffff <<  0)          /* Receive Data */
-#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
-
-#define AT91_SPI_TDR            0x0c                    /* Transmit Data Register */
-#define         AT91_SPI_TD             (0xffff <<  0)          /* Transmit Data */
-#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
-#define         AT91_SPI_LASTXFER       (1      << 24)          /* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_SR             0x10                    /* Status Register */
-#define         AT91_SPI_RDRF           (1 <<  0)               /* Receive Data Register Full */
-#define         AT91_SPI_TDRE           (1 <<  1)               /* Transmit Data Register Full */
-#define         AT91_SPI_MODF           (1 <<  2)               /* Mode Fault Error */
-#define         AT91_SPI_OVRES          (1 <<  3)               /* Overrun Error Status */
-#define         AT91_SPI_ENDRX          (1 <<  4)               /* End of RX buffer */
-#define         AT91_SPI_ENDTX          (1 <<  5)               /* End of TX buffer */
-#define         AT91_SPI_RXBUFF         (1 <<  6)               /* RX Buffer Full */
-#define         AT91_SPI_TXBUFE         (1 <<  7)               /* TX Buffer Empty */
-#define         AT91_SPI_NSSR           (1 <<  8)               /* NSS Rising [SAM9261 only] */
-#define         AT91_SPI_TXEMPTY        (1 <<  9)               /* Transmission Register Empty [SAM9261 only] */
-#define         AT91_SPI_SPIENS         (1 << 16)               /* SPI Enable Status */
-
-#define AT91_SPI_IER            0x14                    /* Interrupt Enable Register */
-#define AT91_SPI_IDR            0x18                    /* Interrupt Disable Register */
-#define AT91_SPI_IMR            0x1c                    /* Interrupt Mask Register */
-
-#define AT91_SPI_CSR(n)         (0x30 + ((n) * 4))      /* Chip Select Registers 0-3 */
-#define         AT91_SPI_CPOL           (1    <<  0)            /* Clock Polarity */
-#define         AT91_SPI_NCPHA          (1    <<  1)            /* Clock Phase */
-#define         AT91_SPI_CSAAT          (1    <<  3)            /* Chip Select Active After Transfer [SAM9261 only] */
-#define         AT91_SPI_BITS           (0xf  <<  4)            /* Bits Per Transfer */
-#define                 AT91_SPI_BITS_8         (0 << 4)
-#define                 AT91_SPI_BITS_9         (1 << 4)
-#define                 AT91_SPI_BITS_10        (2 << 4)
-#define                 AT91_SPI_BITS_11        (3 << 4)
-#define                 AT91_SPI_BITS_12        (4 << 4)
-#define                 AT91_SPI_BITS_13        (5 << 4)
-#define                 AT91_SPI_BITS_14        (6 << 4)
-#define                 AT91_SPI_BITS_15        (7 << 4)
-#define                 AT91_SPI_BITS_16        (8 << 4)
-#define         AT91_SPI_SCBR           (0xff <<  8)            /* Serial Clock Baud Rate */
-#define         AT91_SPI_DLYBS          (0xff << 16)            /* Delay before SPCK */
-#define         AT91_SPI_DLYBCT         (0xff << 24)            /* Delay between Consecutive Transfers */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ssc.h b/arch/arm/mach-at91/include/mach/at91_ssc.h
deleted file mode 100644
index a81114c11c7..00000000000
--- a/arch/arm/mach-at91/include/mach/at91_ssc.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_ssc.h
- *
- * Copyright (C) SAN People
- *
- * Serial Synchronous Controller (SSC) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_SSC_H
-#define AT91_SSC_H
-
-#define AT91_SSC_CR             0x00    /* Control Register */
-#define         AT91_SSC_RXEN           (1 <<  0)       /* Receive Enable */
-#define         AT91_SSC_RXDIS          (1 <<  1)       /* Receive Disable */
-#define         AT91_SSC_TXEN           (1 <<  8)       /* Transmit Enable */
-#define         AT91_SSC_TXDIS          (1 <<  9)       /* Transmit Disable */
-#define         AT91_SSC_SWRST          (1 << 15)       /* Software Reset */
-
-#define AT91_SSC_CMR            0x04    /* Clock Mode Register */
-#define         AT91_SSC_CMR_DIV        (0xfff << 0)    /* Clock Divider */
-
-#define AT91_SSC_RCMR           0x10    /* Receive Clock Mode Register */
-#define         AT91_SSC_CKS            (3    <<  0)    /* Clock Selection */
-#define                 AT91_SSC_CKS_DIV                (0 << 0)
-#define                 AT91_SSC_CKS_CLOCK              (1 << 0)
-#define                 AT91_SSC_CKS_PIN                (2 << 0)
-#define         AT91_SSC_CKO            (7    <<  2)    /* Clock Output Mode Selection */
-#define                 AT91_SSC_CKO_NONE               (0 << 2)
-#define                 AT91_SSC_CKO_CONTINUOUS         (1 << 2)
-#define         AT91_SSC_CKI            (1    <<  5)    /* Clock Inversion */
-#define                 AT91_SSC_CKI_FALLING            (0 << 5)
-#define                 AT91_SSC_CK_RISING              (1 << 5)
-#define         AT91_SSC_CKG            (1    <<  6)    /* Receive Clock Gating Selection [AT91SAM9261 only] */
-#define                 AT91_SSC_CKG_NONE               (0 << 6)
-#define                 AT91_SSC_CKG_RFLOW              (1 << 6)
-#define                 AT91_SSC_CKG_RFHIGH             (2 << 6)
-#define         AT91_SSC_START          (0xf  <<  8)    /* Start Selection */
-#define                 AT91_SSC_START_CONTINUOUS       (0 << 8)
-#define                 AT91_SSC_START_TX_RX            (1 << 8)
-#define                 AT91_SSC_START_LOW_RF           (2 << 8)
-#define                 AT91_SSC_START_HIGH_RF          (3 << 8)
-#define                 AT91_SSC_START_FALLING_RF       (4 << 8)
-#define                 AT91_SSC_START_RISING_RF        (5 << 8)
-#define                 AT91_SSC_START_LEVEL_RF         (6 << 8)
-#define                 AT91_SSC_START_EDGE_RF          (7 << 8)
-#define         AT91_SSC_STOP           (1    << 12)    /* Receive Stop Selection [AT91SAM9261 only] */
-#define         AT91_SSC_STTDLY         (0xff << 16)    /* Start Delay */
-#define         AT91_SSC_PERIOD         (0xff << 24)    /* Period Divider Selection */
-
-#define AT91_SSC_RFMR           0x14    /* Receive Frame Mode Register */
-#define         AT91_SSC_DATALEN        (0x1f <<  0)    /* Data Length */
-#define         AT91_SSC_LOOP           (1    <<  5)    /* Loop Mode */
-#define         AT91_SSC_MSBF           (1    <<  7)    /* Most Significant Bit First */
-#define         AT91_SSC_DATNB          (0xf  <<  8)    /* Data Number per Frame */
-#define         AT91_SSC_FSLEN          (0xf  << 16)    /* Frame Sync Length */
-#define         AT91_SSC_FSOS           (7    << 20)    /* Frame Sync Output Selection */
-#define                 AT91_SSC_FSOS_NONE              (0 << 20)
-#define                 AT91_SSC_FSOS_NEGATIVE          (1 << 20)
-#define                 AT91_SSC_FSOS_POSITIVE          (2 << 20)
-#define                 AT91_SSC_FSOS_LOW               (3 << 20)
-#define                 AT91_SSC_FSOS_HIGH              (4 << 20)
-#define                 AT91_SSC_FSOS_TOGGLE            (5 << 20)
-#define         AT91_SSC_FSEDGE         (1    << 24)    /* Frame Sync Edge Detection */
-#define                 AT91_SSC_FSEDGE_POSITIVE        (0 << 24)
-#define                 AT91_SSC_FSEDGE_NEGATIVE        (1 << 24)
-
-#define AT91_SSC_TCMR           0x18    /* Transmit Clock Mode Register */
-#define AT91_SSC_TFMR           0x1c    /* Transmit Fram Mode Register */
-#define         AT91_SSC_DATDEF         (1 <<  5)       /* Data Default Value */
-#define         AT91_SSC_FSDEN          (1 << 23)       /* Frame Sync Data Enable */
-
-#define AT91_SSC_RHR            0x20    /* Receive Holding Register */
-#define AT91_SSC_THR            0x24    /* Transmit Holding Register */
-#define AT91_SSC_RSHR           0x30    /* Receive Sync Holding Register */
-#define AT91_SSC_TSHR           0x34    /* Transmit Sync Holding Register */
-
-#define AT91_SSC_RC0R           0x38    /* Receive Compare 0 Register [AT91SAM9261 only] */
-#define AT91_SSC_RC1R           0x3c    /* Receive Compare 1 Register [AT91SAM9261 only] */
-
-#define AT91_SSC_SR             0x40    /* Status Register */
-#define         AT91_SSC_TXRDY          (1 <<  0)       /* Transmit Ready */
-#define         AT91_SSC_TXEMPTY        (1 <<  1)       /* Transmit Empty */
-#define         AT91_SSC_ENDTX          (1 <<  2)       /* End of Transmission */
-#define         AT91_SSC_TXBUFE         (1 <<  3)       /* Transmit Buffer Empty */
-#define         AT91_SSC_RXRDY          (1 <<  4)       /* Receive Ready */
-#define         AT91_SSC_OVRUN          (1 <<  5)       /* Receive Overrun */
-#define         AT91_SSC_ENDRX          (1 <<  6)       /* End of Reception */
-#define         AT91_SSC_RXBUFF         (1 <<  7)       /* Receive Buffer Full */
-#define         AT91_SSC_CP0            (1 <<  8)       /* Compare 0 [AT91SAM9261 only] */
-#define         AT91_SSC_CP1            (1 <<  9)       /* Compare 1 [AT91SAM9261 only] */
-#define         AT91_SSC_TXSYN          (1 << 10)       /* Transmit Sync */
-#define         AT91_SSC_RXSYN          (1 << 11)       /* Receive Sync */
-#define         AT91_SSC_TXENA          (1 << 16)       /* Transmit Enable */
-#define         AT91_SSC_RXENA          (1 << 17)       /* Receive Enable */
-
-#define AT91_SSC_IER            0x44    /* Interrupt Enable Register */
-#define AT91_SSC_IDR            0x48    /* Interrupt Disable Register */
-#define AT91_SSC_IMR            0x4c    /* Interrupt Mask Register */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 3a4da24d591..8eba1021f53 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -136,6 +136,8 @@
 #define AT_DMA_ID_SSC1_RX        8
 #define AT_DMA_ID_AC97_TX        9
 #define AT_DMA_ID_AC97_RX       10
+#define AT_DMA_ID_AES_TX        11
+#define AT_DMA_ID_AES_RX        12
 #define AT_DMA_ID_MCI1          13
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
deleted file mode 100644
index 903bf205a33..00000000000
--- a/arch/arm/mach-at91/include/mach/entry-macro.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/entry-macro.S
- *
- *  Copyright (C) 2003-2005 SAN People
- *
- * Low-level IRQ helper macros for AT91RM9200 platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <mach/hardware.h>
-#include <mach/at91_aic.h>
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =at91_aic_base           @ base virtual address of AIC peripheral
-        ldr     \base, [\base]
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqnr, [\base, #AT91_AIC_IVR]          @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
-        ldr     \irqstat, [\base, #AT91_AIC_ISR]        @ read interrupt source number
-        teq     \irqstat, #0                            @ ISR is 0 when no current interrupt, or spurious interrupt
-        streq   \tmp, [\base, #AT91_AIC_EOICR]          @ not going to be handled further, then ACK it now.
-        .endm
-
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index cfcfcbe3626..1e02c0e49dc 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -23,6 +23,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/mm.h>
+#include <linux/bitmap.h>
 #include <linux/types.h>
 #include <linux/irq.h>
 #include <linux/of.h>
@@ -30,38 +31,218 @@
 #include <linux/of_irq.h>
 #include <linux/irqdomain.h>
 #include <linux/err.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 
+#include <asm/exception.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
+#include <mach/at91_aic.h>
+
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
 static struct device_node *at91_aic_np;
+static unsigned int n_irqs = NR_AIC_IRQS;
+static unsigned long at91_aic_caps = 0;
+
+/* AIC5 introduces a Source Select Register */
+#define AT91_AIC_CAP_AIC5       (1 << 0)
+#define has_aic5()              (at91_aic_caps & AT91_AIC_CAP_AIC5)
+
+#ifdef CONFIG_PM
+
+static unsigned long *wakeups;
+static unsigned long *backups;
+
+#define set_backup(bit) set_bit(bit, backups)
+#define clear_backup(bit) clear_bit(bit, backups)
+
+static int at91_aic_pm_init(void)
+{
+        backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
+        if (!backups)
+                return -ENOMEM;
+
+        wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
+        if (!wakeups) {
+                kfree(backups);
+                return -ENOMEM;
+        }
+
+        return 0;
+}
+
+static int at91_aic_set_wake(struct irq_data *d, unsigned value)
+{
+        if (unlikely(d->hwirq >= n_irqs))
+                return -EINVAL;
+
+        if (value)
+                set_bit(d->hwirq, wakeups);
+        else
+                clear_bit(d->hwirq, wakeups);
+
+        return 0;
+}
+
+void at91_irq_suspend(void)
+{
+        int i = 0, bit;
+
+        if (has_aic5()) {
+                /* disable enabled irqs */
+                while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
+                        at91_aic_write(AT91_AIC5_SSR,
+                                       bit & AT91_AIC5_INTSEL_MSK);
+                        at91_aic_write(AT91_AIC5_IDCR, 1);
+                        i = bit;
+                }
+                /* enable wakeup irqs */
+                i = 0;
+                while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
+                        at91_aic_write(AT91_AIC5_SSR,
+                                       bit & AT91_AIC5_INTSEL_MSK);
+                        at91_aic_write(AT91_AIC5_IECR, 1);
+                        i = bit;
+                }
+        } else {
+                at91_aic_write(AT91_AIC_IDCR, *backups);
+                at91_aic_write(AT91_AIC_IECR, *wakeups);
+        }
+}
+
+void at91_irq_resume(void)
+{
+        int i = 0, bit;
+
+        if (has_aic5()) {
+                /* disable wakeup irqs */
+                while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
+                        at91_aic_write(AT91_AIC5_SSR,
+                                       bit & AT91_AIC5_INTSEL_MSK);
+                        at91_aic_write(AT91_AIC5_IDCR, 1);
+                        i = bit;
+                }
+                /* enable irqs disabled for suspend */
+                i = 0;
+                while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
+                        at91_aic_write(AT91_AIC5_SSR,
+                                       bit & AT91_AIC5_INTSEL_MSK);
+                        at91_aic_write(AT91_AIC5_IECR, 1);
+                        i = bit;
+                }
+        } else {
+                at91_aic_write(AT91_AIC_IDCR, *wakeups);
+                at91_aic_write(AT91_AIC_IECR, *backups);
+        }
+}
+
+#else
+static inline int at91_aic_pm_init(void)
+{
+        return 0;
+}
+
+#define set_backup(bit)
+#define clear_backup(bit)
+#define at91_aic_set_wake       NULL
+
+#endif /* CONFIG_PM */
+
+asmlinkage void __exception_irq_entry
+at91_aic_handle_irq(struct pt_regs *regs)
+{
+        u32 irqnr;
+        u32 irqstat;
+
+        irqnr = at91_aic_read(AT91_AIC_IVR);
+        irqstat = at91_aic_read(AT91_AIC_ISR);
+
+        /*
+         * ISR value is 0 when there is no current interrupt or when there is
+         * a spurious interrupt
+         */
+        if (!irqstat)
+                at91_aic_write(AT91_AIC_EOICR, 0);
+        else
+                handle_IRQ(irqnr, regs);
+}
+
+asmlinkage void __exception_irq_entry
+at91_aic5_handle_irq(struct pt_regs *regs)
+{
+        u32 irqnr;
+        u32 irqstat;
+
+        irqnr = at91_aic_read(AT91_AIC5_IVR);
+        irqstat = at91_aic_read(AT91_AIC5_ISR);
+
+        if (!irqstat)
+                at91_aic_write(AT91_AIC5_EOICR, 0);
+        else
+                handle_IRQ(irqnr, regs);
+}
 
 static void at91_aic_mask_irq(struct irq_data *d)
 {
         /* Disable interrupt on AIC */
         at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
+        /* Update ISR cache */
+        clear_backup(d->hwirq);
+}
+
+static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
+{
+        /* Disable interrupt on AIC5 */
+        at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
+        at91_aic_write(AT91_AIC5_IDCR, 1);
+        /* Update ISR cache */
+        clear_backup(d->hwirq);
 }
 
 static void at91_aic_unmask_irq(struct irq_data *d)
 {
         /* Enable interrupt on AIC */
         at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
+        /* Update ISR cache */
+        set_backup(d->hwirq);
+}
+
+static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
+{
+        /* Enable interrupt on AIC5 */
+        at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
+        at91_aic_write(AT91_AIC5_IECR, 1);
+        /* Update ISR cache */
+        set_backup(d->hwirq);
 }
 
-unsigned int at91_extern_irq;
+static void at91_aic_eoi(struct irq_data *d)
+{
+        /*
+         * Mark end-of-interrupt on AIC, the controller doesn't care about
+         * the value written. Moreover it's a write-only register.
+         */
+        at91_aic_write(AT91_AIC_EOICR, 0);
+}
+
+static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
+{
+        at91_aic_write(AT91_AIC5_EOICR, 0);
+}
 
-#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq)
+unsigned long *at91_extern_irq;
 
-static int at91_aic_set_type(struct irq_data *d, unsigned type)
+#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
+
+static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
 {
-        unsigned int smr, srctype;
+        int srctype;
 
         switch (type) {
         case IRQ_TYPE_LEVEL_HIGH:
@@ -74,65 +255,51 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
                         srctype = AT91_AIC_SRCTYPE_LOW;
                 else
-                        return -EINVAL;
+                        srctype = -EINVAL;
                 break;
         case IRQ_TYPE_EDGE_FALLING:
                 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
                         srctype = AT91_AIC_SRCTYPE_FALLING;
                 else
-                        return -EINVAL;
+                        srctype = -EINVAL;
                 break;
         default:
-                return -EINVAL;
+                srctype = -EINVAL;
         }
 
-        smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
-        at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
-        return 0;
+        return srctype;
 }
 
-#ifdef CONFIG_PM
-
-static u32 wakeups;
-static u32 backups;
-
-static int at91_aic_set_wake(struct irq_data *d, unsigned value)
+static int at91_aic_set_type(struct irq_data *d, unsigned type)
 {
-        if (unlikely(d->hwirq >= NR_AIC_IRQS))
-                return -EINVAL;
-
-        if (value)
-                wakeups |= (1 << d->hwirq);
-        else
-                wakeups &= ~(1 << d->hwirq);
+        unsigned int smr;
+        int srctype;
+
+        srctype = at91_aic_compute_srctype(d, type);
+        if (srctype < 0)
+                return srctype;
+
+        if (has_aic5()) {
+                at91_aic_write(AT91_AIC5_SSR,
+                               d->hwirq & AT91_AIC5_INTSEL_MSK);
+                smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
+                at91_aic_write(AT91_AIC5_SMR, smr | srctype);
+        } else {
+                smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
+                      & ~AT91_AIC_SRCTYPE;
+                at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
+        }
 
         return 0;
 }
 
-void at91_irq_suspend(void)
-{
-        backups = at91_aic_read(AT91_AIC_IMR);
-        at91_aic_write(AT91_AIC_IDCR, backups);
-        at91_aic_write(AT91_AIC_IECR, wakeups);
-}
-
-void at91_irq_resume(void)
-{
-        at91_aic_write(AT91_AIC_IDCR, wakeups);
-        at91_aic_write(AT91_AIC_IECR, backups);
-}
-
-#else
-#define at91_aic_set_wake       NULL
-#endif
-
 static struct irq_chip at91_aic_chip = {
         .name           = "AIC",
-        .irq_ack        = at91_aic_mask_irq,
         .irq_mask       = at91_aic_mask_irq,
         .irq_unmask     = at91_aic_unmask_irq,
         .irq_set_type   = at91_aic_set_type,
         .irq_set_wake   = at91_aic_set_wake,
+        .irq_eoi        = at91_aic_eoi,
 };
 
 static void __init at91_aic_hw_init(unsigned int spu_vector)
@@ -161,41 +328,172 @@ static void __init at91_aic_hw_init(unsigned int spu_vector)
         at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
 }
 
+static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
+{
+        int i;
+
+        /*
+         * Perform 8 End Of Interrupt Command to make sure AIC
+         * will not Lock out nIRQ
+         */
+        for (i = 0; i < 8; i++)
+                at91_aic_write(AT91_AIC5_EOICR, 0);
+
+        /*
+         * Spurious Interrupt ID in Spurious Vector Register.
+         * When there is no current interrupt, the IRQ Vector Register
+         * reads the value stored in AIC_SPU
+         */
+        at91_aic_write(AT91_AIC5_SPU, spu_vector);
+
+        /* No debugging in AIC: Debug (Protect) Control Register */
+        at91_aic_write(AT91_AIC5_DCR, 0);
+
+        /* Disable and clear all interrupts initially */
+        for (i = 0; i < n_irqs; i++) {
+                at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
+                at91_aic_write(AT91_AIC5_IDCR, 1);
+                at91_aic_write(AT91_AIC5_ICCR, 1);
+        }
+}
+
 #if defined(CONFIG_OF)
+static unsigned int *at91_aic_irq_priorities;
+
 static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
                                                         irq_hw_number_t hw)
 {
         /* Put virq number in Source Vector Register */
         at91_aic_write(AT91_AIC_SVR(hw), virq);
 
-        /* Active Low interrupt, without priority */
-        at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW);
+        /* Active Low interrupt, with priority */
+        at91_aic_write(AT91_AIC_SMR(hw),
+                       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
 
-        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq);
+        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
         set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
 
         return 0;
 }
 
+static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
+                irq_hw_number_t hw)
+{
+        at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
+
+        /* Put virq number in Source Vector Register */
+        at91_aic_write(AT91_AIC5_SVR, virq);
+
+        /* Active Low interrupt, with priority */
+        at91_aic_write(AT91_AIC5_SMR,
+                       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
+
+        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+        return 0;
+}
+
+static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
+                                const u32 *intspec, unsigned int intsize,
+                                irq_hw_number_t *out_hwirq, unsigned int *out_type)
+{
+        if (WARN_ON(intsize < 3))
+                return -EINVAL;
+        if (WARN_ON(intspec[0] >= n_irqs))
+                return -EINVAL;
+        if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
+                    || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
+                return -EINVAL;
+
+        *out_hwirq = intspec[0];
+        *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
+        at91_aic_irq_priorities[*out_hwirq] = intspec[2];
+
+        return 0;
+}
+
 static struct irq_domain_ops at91_aic_irq_ops = {
         .map    = at91_aic_irq_map,
-        .xlate  = irq_domain_xlate_twocell,
+        .xlate  = at91_aic_irq_domain_xlate,
 };
 
-int __init at91_aic_of_init(struct device_node *node,
-                                     struct device_node *parent)
+int __init at91_aic_of_common_init(struct device_node *node,
+                                    struct device_node *parent)
 {
+        struct property *prop;
+        const __be32 *p;
+        u32 val;
+
+        at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
+                                  * sizeof(*at91_extern_irq), GFP_KERNEL);
+        if (!at91_extern_irq)
+                return -ENOMEM;
+
+        if (at91_aic_pm_init()) {
+                kfree(at91_extern_irq);
+                return -ENOMEM;
+        }
+
+        at91_aic_irq_priorities = kzalloc(n_irqs
+                                          * sizeof(*at91_aic_irq_priorities),
+                                          GFP_KERNEL);
+        if (!at91_aic_irq_priorities)
+                return -ENOMEM;
+
         at91_aic_base = of_iomap(node, 0);
         at91_aic_np = node;
 
-        at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS,
+        at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
                                                 &at91_aic_irq_ops, NULL);
         if (!at91_aic_domain)
                 panic("Unable to add AIC irq domain (DT)\n");
 
+        of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
+                if (val >= n_irqs)
+                        pr_warn("AIC: external irq %d >= %d skip it\n",
+                                val, n_irqs);
+                else
+                        set_bit(val, at91_extern_irq);
+        }
+
         irq_set_default_host(at91_aic_domain);
 
-        at91_aic_hw_init(NR_AIC_IRQS);
+        return 0;
+}
+
+int __init at91_aic_of_init(struct device_node *node,
+                                     struct device_node *parent)
+{
+        int err;
+
+        err = at91_aic_of_common_init(node, parent);
+        if (err)
+                return err;
+
+        at91_aic_hw_init(n_irqs);
+
+        return 0;
+}
+
+int __init at91_aic5_of_init(struct device_node *node,
+                                     struct device_node *parent)
+{
+        int err;
+
+        at91_aic_caps |= AT91_AIC_CAP_AIC5;
+        n_irqs = NR_AIC5_IRQS;
+        at91_aic_chip.irq_ack           = at91_aic5_mask_irq;
+        at91_aic_chip.irq_mask          = at91_aic5_mask_irq;
+        at91_aic_chip.irq_unmask        = at91_aic5_unmask_irq;
+        at91_aic_chip.irq_eoi           = at91_aic5_eoi;
+        at91_aic_irq_ops.map            = at91_aic5_irq_map;
+
+        err = at91_aic_of_common_init(node, parent);
+        if (err)
+                return err;
+
+        at91_aic5_hw_init(n_irqs);
 
         return 0;
 }
@@ -204,22 +502,25 @@ int __init at91_aic_of_init(struct device_node *node,
 /*
  * Initialize the AIC interrupt controller.
  */
-void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
+void __init at91_aic_init(unsigned int *priority)
 {
         unsigned int i;
         int irq_base;
 
+        if (at91_aic_pm_init())
+                panic("Unable to allocate bit maps\n");
+
         at91_aic_base = ioremap(AT91_AIC, 512);
         if (!at91_aic_base)
                 panic("Unable to ioremap AIC registers\n");
 
         /* Add irq domain for AIC */
-        irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0);
+        irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
         if (irq_base < 0) {
                 WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
                 irq_base = 0;
         }
-        at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS,
+        at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
                                                 irq_base, 0,
                                                 &irq_domain_simple_ops, NULL);
 
@@ -232,15 +533,14 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
          * The IVR is used by macro get_irqnr_and_base to read and verify.
          * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
          */
-        for (i = 0; i < NR_AIC_IRQS; i++) {
+        for (i = 0; i < n_irqs; i++) {
                 /* Put hardware irq number in Source Vector Register: */
-                at91_aic_write(AT91_AIC_SVR(i), i);
+                at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
                 /* Active Low interrupt, with the specified priority */
                 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
-
-                irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
+                irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 
-        at91_aic_hw_init(NR_AIC_IRQS);
+        at91_aic_hw_init(n_irqs);
 }
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 1bfaad62873..2c2d86505a5 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -25,6 +25,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index c965fd8eb31..f15293bd797 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -26,7 +26,6 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/sched.h>
-#include <linux/timex.h>
 
 #include <asm/sizes.h>
 #include <mach/hardware.h>
@@ -188,7 +187,6 @@ static struct irqaction clps711x_timer_irq = {
 
 static void __init clps711x_timer_init(void)
 {
-        struct timespec tv;
         unsigned int syscon;
 
         syscon = clps_readl(SYSCON1);
@@ -198,10 +196,6 @@ static void __init clps711x_timer_init(void)
         clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
 
         setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
-
-        tv.tv_nsec = 0;
-        tv.tv_sec = clps_readl(RTCDR);
-        do_settimeofday(&tv);
 }
 
 struct sys_timer clps711x_timer = {
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
index 3a032a67725..fc0e028d940 100644
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ b/arch/arm/mach-clps711x/include/mach/memory.h
@@ -25,26 +25,6 @@
  */
 #define PLAT_PHYS_OFFSET        UL(0xc0000000)
 
-#if !defined(CONFIG_ARCH_CDB89712) && !defined (CONFIG_ARCH_AUTCPU12)
-
-#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
-#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
-#define __pfn_to_bus(x)         (__pfn_to_phys(x) - PHYS_OFFSET)
-#define __bus_to_pfn(x)         __phys_to_pfn((x) + PHYS_OFFSET)
-
-#endif
-
-
-/*
- * Like the SA1100, the EDB7211 has a large gap between physical RAM
- * banks.  In 2.2, the Psion (CL-PS7110) port added custom support for
- * discontiguous physical memory.  In 2.4, we can use the standard
- * Linux NUMA support.
- *
- * This is not necessary for EP7211 implementations with only one used
- * memory bank.  For those systems, simply undefine CONFIG_DISCONTIGMEM.
- */
-
 /*
  * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
  * uses only one of the two banks (bank #1).  However, even within
@@ -54,23 +34,6 @@
  * them, so we use 24 for the node max shift to get 16MB node sizes.
  */
 
-/*
- * Because of the wide memory address space between physical RAM banks on the 
- * SA1100, it's much more convenient to use Linux's NUMA support to implement
- * our memory map representation.  Assuming all memory nodes have equal access 
- * characteristics, we then have generic discontiguous memory support.
- *
- * Of course, all this isn't mandatory for SA1100 implementations with only
- * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
- *
- * The nodes are matched with the physical memory bank addresses which are 
- * incidentally the same as virtual addresses.
- * 
- *      node 0:  0xc0000000 - 0xc7ffffff
- *      node 1:  0xc8000000 - 0xcfffffff
- *      node 2:  0xd0000000 - 0xd7ffffff
- *      node 3:  0xd8000000 - 0xdfffffff
- */
 #define SECTION_SIZE_BITS       24
 #define MAX_PHYSMEM_BITS        32
 
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index 42ee8f33eaf..f266d90b9ef 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -86,17 +86,7 @@ static void __init p720t_map_io(void)
         iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
 }
 
-MACHINE_START(P720T, "ARM-Prospector720T")
-        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .atag_offset    = 0x100,
-        .fixup          = fixup_p720t,
-        .map_io         = p720t_map_io,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
-
-static int p720t_hw_init(void)
+static void __init p720t_init_early(void)
 {
         /*
          * Power down as much as possible in case we don't
@@ -111,13 +101,19 @@ static int p720t_hw_init(void)
         PLD_CODEC = 0;
         PLD_TCH   = 0;
         PLD_SPI   = 0;
-#ifndef CONFIG_DEBUG_LL
-        PLD_COM2  = 0;
-        PLD_COM1  = 0;
-#endif
-
-        return 0;
+        if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
+                PLD_COM2 = 0;
+                PLD_COM1 = 0;
+        }
 }
 
-__initcall(p720t_hw_init);
-
+MACHINE_START(P720T, "ARM-Prospector720T")
+        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+        .atag_offset    = 0x100,
+        .fixup          = fixup_p720t,
+        .init_early     = p720t_init_early,
+        .map_io         = p720t_map_io,
+        .init_irq       = clps711x_init_irq,
+        .timer          = &clps711x_timer,
+        .restart        = clps711x_restart,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 32d837d8eab..ab99c3c3b75 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,6 +4,7 @@ config AINTC
         bool
 
 config CP_INTC
+        select IRQ_DOMAIN
         bool
 
 config ARCH_DAVINCI_DMx
@@ -61,7 +62,6 @@ config MACH_DAVINCI_EVM
         bool "TI DM644x EVM"
         default ARCH_DAVINCI_DM644x
         depends on ARCH_DAVINCI_DM644x
-        select MISC_DEVICES
         select EEPROM_AT24
         select I2C
         help
@@ -71,7 +71,6 @@ config MACH_DAVINCI_EVM
 config MACH_SFFSDR
         bool "Lyrtech SFFSDR"
         depends on ARCH_DAVINCI_DM644x
-        select MISC_DEVICES
         select EEPROM_AT24
         select I2C
         help
@@ -105,7 +104,6 @@ config MACH_DAVINCI_DM6467_EVM
         default ARCH_DAVINCI_DM646x
         depends on ARCH_DAVINCI_DM646x
         select MACH_DAVINCI_DM6467TEVM
-        select MISC_DEVICES
         select EEPROM_AT24
         select I2C
         help
@@ -119,7 +117,6 @@ config MACH_DAVINCI_DM365_EVM
         bool "TI DM365 EVM"
         default ARCH_DAVINCI_DM365
         depends on ARCH_DAVINCI_DM365
-        select MISC_DEVICES
         select EEPROM_AT24
         select I2C
         help
@@ -131,7 +128,6 @@ config MACH_DAVINCI_DA830_EVM
         default ARCH_DAVINCI_DA830
         depends on ARCH_DAVINCI_DA830
         select GPIO_PCF857X
-        select MISC_DEVICES
         select EEPROM_AT24
         select I2C
         help
@@ -218,7 +214,6 @@ config MACH_TNETV107X
 config MACH_MITYOMAPL138
         bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
         depends on ARCH_DAVINCI_DA850
-        select MISC_DEVICES
         select EEPROM_AT24
         select I2C
         help
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 2db78bd5c83..2227effcb0e 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD)	+= board-omapl138-hawk.o
 obj-$(CONFIG_CPU_FREQ)                  += cpufreq.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_SUSPEND)                   += pm.o sleep.o
+obj-$(CONFIG_HAVE_CLK)                  += pm_domain.o
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 5de69f2fcca..f6b9fc70161 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -162,38 +162,6 @@ static void __init davinci_ntosd2_map_io(void)
         dm644x_init();
 }
 
-/*
- I2C initialization
-*/
-static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
-        .bus_freq       = 20 /* kHz */,
-        .bus_delay      = 100 /* usec */,
-};
-
-static struct i2c_board_info __initdata ntosd2_i2c_info[] =  {
-};
-
-static  int ntosd2_init_i2c(void)
-{
-        int     status;
-
-        davinci_init_i2c(&ntosd2_i2c_pdata);
-        status = gpio_request(NTOSD2_MSP430_IRQ, ntosd2_i2c_info[0].type);
-        if (status == 0) {
-                status = gpio_direction_input(NTOSD2_MSP430_IRQ);
-                if (status == 0) {
-                        status = gpio_to_irq(NTOSD2_MSP430_IRQ);
-                        if (status > 0) {
-                                ntosd2_i2c_info[0].irq = status;
-                                i2c_register_board_info(1,
-                                        ntosd2_i2c_info,
-                                        ARRAY_SIZE(ntosd2_i2c_info));
-                        }
-                }
-        }
-        return status;
-}
-
 static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
         .wires          = 4,
         .version        = MMC_CTLR_VERSION_1
@@ -218,7 +186,6 @@ static __init void davinci_ntosd2_init(void)
 {
         struct clk *aemif_clk;
         struct davinci_soc_info *soc_info = &davinci_soc_info;
-        int     status;
 
         aemif_clk = clk_get(NULL, "aemif");
         clk_enable(aemif_clk);
@@ -242,12 +209,6 @@ static __init void davinci_ntosd2_init(void)
         platform_add_devices(davinci_ntosd2_devices,
                                 ARRAY_SIZE(davinci_ntosd2_devices));
 
-        /* Initialize I2C interface specific for this board */
-        status = ntosd2_init_i2c();
-        if (status < 0)
-                pr_warning("davinci_ntosd2_init: msp430 irq setup failed:"
-                                                "        %d\n", status);
-
         davinci_serial_init(&uart_config);
         dm644x_init_asp(&dm644x_ntosd2_snd_data);
 
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index f83152d643c..006dae8dfe4 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -9,9 +9,14 @@
  * kind, whether express or implied.
  */
 
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <mach/common.h>
 #include <mach/cp_intc.h>
@@ -28,7 +33,7 @@ static inline void cp_intc_write(unsigned long value, unsigned offset)
 
 static void cp_intc_ack_irq(struct irq_data *d)
 {
-        cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR);
+        cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
 }
 
 /* Disable interrupt */
@@ -36,20 +41,20 @@ static void cp_intc_mask_irq(struct irq_data *d)
 {
         /* XXX don't know why we need to disable nIRQ here... */
         cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
-        cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR);
+        cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
         cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
 }
 
 /* Enable interrupt */
 static void cp_intc_unmask_irq(struct irq_data *d)
 {
-        cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET);
+        cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
 }
 
 static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
-        unsigned reg            = BIT_WORD(d->irq);
-        unsigned mask           = BIT_MASK(d->irq);
+        unsigned reg            = BIT_WORD(d->hwirq);
+        unsigned mask           = BIT_MASK(d->hwirq);
         unsigned polarity       = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
         unsigned type           = cp_intc_read(CP_INTC_SYS_TYPE(reg));
 
@@ -99,18 +104,43 @@ static struct irq_chip cp_intc_irq_chip = {
         .irq_set_wake   = cp_intc_set_wake,
 };
 
-void __init cp_intc_init(void)
+static struct irq_domain *cp_intc_domain;
+
+static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
+                          irq_hw_number_t hw)
 {
-        unsigned long num_irq   = davinci_soc_info.intc_irq_num;
+        pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
+
+        irq_set_chip(virq, &cp_intc_irq_chip);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+        irq_set_handler(virq, handle_edge_irq);
+        return 0;
+}
+
+static const struct irq_domain_ops cp_intc_host_ops = {
+        .map = cp_intc_host_map,
+        .xlate = irq_domain_xlate_onetwocell,
+};
+
+int __init cp_intc_of_init(struct device_node *node, struct device_node *parent)
+{
+        u32 num_irq             = davinci_soc_info.intc_irq_num;
         u8 *irq_prio            = davinci_soc_info.intc_irq_prios;
         u32 *host_map           = davinci_soc_info.intc_host_map;
         unsigned num_reg        = BITS_TO_LONGS(num_irq);
-        int i;
+        int i, irq_base;
 
         davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
-        davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
+        if (node) {
+                davinci_intc_base = of_iomap(node, 0);
+                if (of_property_read_u32(node, "ti,intc-size", &num_irq))
+                        pr_warn("unable to get intc-size, default to %d\n",
+                                num_irq);
+        } else {
+                davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
+        }
         if (WARN_ON(!davinci_intc_base))
-                return;
+                return -EINVAL;
 
         cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
 
@@ -165,13 +195,28 @@ void __init cp_intc_init(void)
                 for (i = 0; host_map[i] != -1; i++)
                         cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
 
-        /* Set up genirq dispatching for cp_intc */
-        for (i = 0; i < num_irq; i++) {
-                irq_set_chip(i, &cp_intc_irq_chip);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                irq_set_handler(i, handle_edge_irq);
+        irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
+        if (irq_base < 0) {
+                pr_warn("Couldn't allocate IRQ numbers\n");
+                irq_base = 0;
+        }
+
+        /* create a legacy host */
+        cp_intc_domain = irq_domain_add_legacy(node, num_irq,
+                                        irq_base, 0, &cp_intc_host_ops, NULL);
+
+        if (!cp_intc_domain) {
+                pr_err("cp_intc: failed to allocate irq host!\n");
+                return -EINVAL;
         }
 
         /* Enable global interrupt */
         cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
+
+        return 0;
+}
+
+void __init cp_intc_init(void)
+{
+        cp_intc_of_init(NULL, NULL);
 }
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index d1624a315c9..783eab6845c 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -546,6 +546,7 @@ static struct lcd_ctrl_config lcd_cfg = {
         .sync_edge              = 0,
         .sync_ctrl              = 1,
         .raster_order           = 0,
+        .fifo_th                = 6,
 };
 
 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index 4e8190eed67..d13d8dfa2b0 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -52,5 +52,6 @@
 #define CP_INTC_VECTOR_ADDR(n)          (0x2000 + (n << 2))
 
 void __init cp_intc_init(void);
+int __init cp_intc_of_init(struct device_node *, struct device_node *);
 
 #endif  /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
deleted file mode 100644
index b9bf3d6a442..00000000000
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty, remove once unused */
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
deleted file mode 100644
index b9bf3d6a442..00000000000
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty, remove once unused */
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index 768b3c06021..cf5f573eb5f 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -30,12 +30,10 @@
 #endif
 #if defined(CONFIG_CP_INTC)
 1001:           ldr \irqnr, [\base, #0x80] /* get irq number */
+                mov \tmp, \irqnr, lsr #31
                 and \irqnr, \irqnr, #0xff  /* irq is in bits 0-9 */
-                mov \tmp, \irqnr, lsr #3
-                and \tmp, \tmp, #0xfc
-                add \tmp, \tmp, #0x280 /* get the register offset */
-                ldr \irqstat, [\base, \tmp] /* get the intc status */
-                cmp \irqstat, #0x0
+                and \tmp, \tmp, #0x1
+                cmp \tmp, #0x1
 #endif
 1002:
                 .endm
diff --git a/arch/arm/mach-davinci/pm_domain.c b/arch/arm/mach-davinci/pm_domain.c
new file mode 100644
index 00000000000..00946e23c1e
--- /dev/null
+++ b/arch/arm/mach-davinci/pm_domain.c
@@ -0,0 +1,64 @@
+/*
+ * Runtime PM support code for DaVinci
+ *
+ * Author: Kevin Hilman
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_clock.h>
+#include <linux/platform_device.h>
+
+#ifdef CONFIG_PM_RUNTIME
+static int davinci_pm_runtime_suspend(struct device *dev)
+{
+        int ret;
+
+        dev_dbg(dev, "%s\n", __func__);
+
+        ret = pm_generic_runtime_suspend(dev);
+        if (ret)
+                return ret;
+
+        ret = pm_clk_suspend(dev);
+        if (ret) {
+                pm_generic_runtime_resume(dev);
+                return ret;
+        }
+
+        return 0;
+}
+
+static int davinci_pm_runtime_resume(struct device *dev)
+{
+        dev_dbg(dev, "%s\n", __func__);
+
+        pm_clk_resume(dev);
+        return pm_generic_runtime_resume(dev);
+}
+#endif
+
+static struct dev_pm_domain davinci_pm_domain = {
+        .ops = {
+                SET_RUNTIME_PM_OPS(davinci_pm_runtime_suspend,
+                                   davinci_pm_runtime_resume, NULL)
+                USE_PLATFORM_PM_SLEEP_OPS
+        },
+};
+
+static struct pm_clk_notifier_block platform_bus_notifier = {
+        .pm_domain = &davinci_pm_domain,
+};
+
+static int __init davinci_pm_runtime_init(void)
+{
+        pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier);
+
+        return 0;
+}
+core_initcall(davinci_pm_runtime_init);
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 9493076fc59..6321567d8ea 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -101,8 +101,9 @@ void __init dove_ehci1_init(void)
  ****************************************************************************/
 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge00_init(eth_data,
-                        DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM, 0);
+        orion_ge00_init(eth_data, DOVE_GE00_PHYS_BASE,
+                        IRQ_DOVE_GE00_SUM, IRQ_DOVE_GE00_ERR,
+                        1600);
 }
 
 /*****************************************************************************
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index f07fd16e0c9..9bc97a5baaa 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -20,22 +20,6 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
-static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        int irqoff;
-        BUG_ON(irq < IRQ_DOVE_GPIO_0_7 || irq > IRQ_DOVE_HIGH_GPIO);
-
-        irqoff = irq <= IRQ_DOVE_GPIO_16_23 ? irq - IRQ_DOVE_GPIO_0_7 :
-                3 + irq - IRQ_DOVE_GPIO_24_31;
-
-        orion_gpio_irq_handler(irqoff << 3);
-        if (irq == IRQ_DOVE_HIGH_GPIO) {
-                orion_gpio_irq_handler(40);
-                orion_gpio_irq_handler(48);
-                orion_gpio_irq_handler(56);
-        }
-}
-
 static void pmu_irq_mask(struct irq_data *d)
 {
         int pin = irq_to_pmu(d->irq);
@@ -90,6 +74,27 @@ static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
         }
 }
 
+static int __initdata gpio0_irqs[4] = {
+        IRQ_DOVE_GPIO_0_7,
+        IRQ_DOVE_GPIO_8_15,
+        IRQ_DOVE_GPIO_16_23,
+        IRQ_DOVE_GPIO_24_31,
+};
+
+static int __initdata gpio1_irqs[4] = {
+        IRQ_DOVE_HIGH_GPIO,
+        0,
+        0,
+        0,
+};
+
+static int __initdata gpio2_irqs[4] = {
+        0,
+        0,
+        0,
+        0,
+};
+
 void __init dove_init_irq(void)
 {
         int i;
@@ -100,19 +105,14 @@ void __init dove_init_irq(void)
         /*
          * Initialize gpiolib for GPIOs 0-71.
          */
-        orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
-                        IRQ_DOVE_GPIO_START);
-        irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
-
-        orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
-                        IRQ_DOVE_GPIO_START + 32);
-        irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
-
-        orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
-                        IRQ_DOVE_GPIO_START + 64);
+        orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START, gpio0_irqs);
+
+        orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
+
+        orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
 
         /*
          * Mask and clear PMU interrupts
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 4dd07a0e360..4afe52aaaff 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -797,6 +797,102 @@ static struct platform_device ep93xx_wdt_device = {
         .resource       = ep93xx_wdt_resources,
 };
 
+/*************************************************************************
+ * EP93xx IDE
+ *************************************************************************/
+static struct resource ep93xx_ide_resources[] = {
+        DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
+        DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
+};
+
+static struct platform_device ep93xx_ide_device = {
+        .name           = "ep93xx-ide",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &ep93xx_ide_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(ep93xx_ide_resources),
+        .resource       = ep93xx_ide_resources,
+};
+
+void __init ep93xx_register_ide(void)
+{
+        platform_device_register(&ep93xx_ide_device);
+}
+
+int ep93xx_ide_acquire_gpio(struct platform_device *pdev)
+{
+        int err;
+        int i;
+
+        err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev));
+        if (err)
+                return err;
+        err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev));
+        if (err)
+                goto fail_egpio15;
+        for (i = 2; i < 8; i++) {
+                err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev));
+                if (err)
+                        goto fail_gpio_e;
+        }
+        for (i = 4; i < 8; i++) {
+                err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev));
+                if (err)
+                        goto fail_gpio_g;
+        }
+        for (i = 0; i < 8; i++) {
+                err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev));
+                if (err)
+                        goto fail_gpio_h;
+        }
+
+        /* GPIO ports E[7:2], G[7:4] and H used by IDE */
+        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
+                                 EP93XX_SYSCON_DEVCFG_GONIDE |
+                                 EP93XX_SYSCON_DEVCFG_HONIDE);
+        return 0;
+
+fail_gpio_h:
+        for (--i; i >= 0; --i)
+                gpio_free(EP93XX_GPIO_LINE_H(i));
+        i = 8;
+fail_gpio_g:
+        for (--i; i >= 4; --i)
+                gpio_free(EP93XX_GPIO_LINE_G(i));
+        i = 8;
+fail_gpio_e:
+        for (--i; i >= 2; --i)
+                gpio_free(EP93XX_GPIO_LINE_E(i));
+        gpio_free(EP93XX_GPIO_LINE_EGPIO15);
+fail_egpio15:
+        gpio_free(EP93XX_GPIO_LINE_EGPIO2);
+        return err;
+}
+EXPORT_SYMBOL(ep93xx_ide_acquire_gpio);
+
+void ep93xx_ide_release_gpio(struct platform_device *pdev)
+{
+        int i;
+
+        for (i = 2; i < 8; i++)
+                gpio_free(EP93XX_GPIO_LINE_E(i));
+        for (i = 4; i < 8; i++)
+                gpio_free(EP93XX_GPIO_LINE_G(i));
+        for (i = 0; i < 8; i++)
+                gpio_free(EP93XX_GPIO_LINE_H(i));
+        gpio_free(EP93XX_GPIO_LINE_EGPIO15);
+        gpio_free(EP93XX_GPIO_LINE_EGPIO2);
+
+
+        /* GPIO ports E[7:2], G[7:4] and H used by GPIO */
+        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
+                               EP93XX_SYSCON_DEVCFG_GONIDE |
+                               EP93XX_SYSCON_DEVCFG_HONIDE);
+}
+EXPORT_SYMBOL(ep93xx_ide_release_gpio);
+
 void __init ep93xx_init_devices(void)
 {
         /* Disallow access to MaverickCrunch initially */
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index d74c5cddb98..337ab7cf4c1 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -91,8 +91,8 @@ static void __init edb93xx_register_i2c(void)
                 ep93xx_register_i2c(&edb93xx_i2c_gpio_data,
                                     edb93xxa_i2c_board_info,
                                     ARRAY_SIZE(edb93xxa_i2c_board_info));
-        } else if (machine_is_edb9307() || machine_is_edb9312() ||
-                   machine_is_edb9315()) {
+        } else if (machine_is_edb9302() || machine_is_edb9307()
+                || machine_is_edb9312() || machine_is_edb9315()) {
                 ep93xx_register_i2c(&edb93xx_i2c_gpio_data,
                                     edb93xx_i2c_board_info,
                                     ARRAY_SIZE(edb93xx_i2c_board_info));
@@ -233,6 +233,29 @@ static void __init edb93xx_register_fb(void)
 }
 
 
+/*************************************************************************
+ * EDB93xx IDE
+ *************************************************************************/
+static int __init edb93xx_has_ide(void)
+{
+        /*
+         * Although EDB9312 and EDB9315 do have IDE capability, they have
+         * INTRQ line wired as pull-up, which makes using IDE interface
+         * problematic.
+         */
+        return machine_is_edb9312() || machine_is_edb9315() ||
+               machine_is_edb9315a();
+}
+
+static void __init edb93xx_register_ide(void)
+{
+        if (!edb93xx_has_ide())
+                return;
+
+        ep93xx_register_ide();
+}
+
+
 static void __init edb93xx_init_machine(void)
 {
         ep93xx_init_devices();
@@ -243,6 +266,7 @@ static void __init edb93xx_init_machine(void)
         edb93xx_register_i2s();
         edb93xx_register_pwm();
         edb93xx_register_fb();
+        edb93xx_register_ide();
 }
 
 
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 1ecb040d98b..33a5122c6dc 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -48,6 +48,9 @@ void ep93xx_register_i2s(void);
 int ep93xx_i2s_acquire(void);
 void ep93xx_i2s_release(void);
 void ep93xx_register_ac97(void);
+void ep93xx_register_ide(void);
+int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
+void ep93xx_ide_release_gpio(struct platform_device *pdev);
 
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index 979fba72292..7bf7ff8beae 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -69,6 +69,7 @@
 
 #define EP93XX_BOOT_ROM_BASE            EP93XX_AHB_IOMEM(0x00090000)
 
+#define EP93XX_IDE_PHYS_BASE            EP93XX_AHB_PHYS(0x000a0000)
 #define EP93XX_IDE_BASE                 EP93XX_AHB_IOMEM(0x000a0000)
 
 #define EP93XX_VIC1_BASE                EP93XX_AHB_IOMEM(0x000b0000)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 6f6d13f91e4..b5b4c8c9db1 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -207,6 +207,7 @@ config MACH_SMDKV310
         select S3C_DEV_HSMMC1
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
+        select S3C_DEV_USB_HSOTG
         select SAMSUNG_DEV_BACKLIGHT
         select EXYNOS_DEV_DRM
         select EXYNOS_DEV_SYSMMU
@@ -326,6 +327,7 @@ config MACH_ORIGEN
         select S3C_DEV_WDT
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
+        select S3C_DEV_USB_HSOTG
         select S5P_DEV_FIMC0
         select S5P_DEV_FIMC1
         select S5P_DEV_FIMC2
@@ -360,22 +362,27 @@ config MACH_SMDK4212
         select S3C_DEV_I2C3
         select S3C_DEV_I2C7
         select S3C_DEV_RTC
+        select S3C_DEV_USB_HSOTG
         select S3C_DEV_WDT
         select S5P_DEV_FIMC0
         select S5P_DEV_FIMC1
         select S5P_DEV_FIMC2
         select S5P_DEV_FIMC3
+        select S5P_DEV_FIMD0
         select S5P_DEV_MFC
         select SAMSUNG_DEV_BACKLIGHT
         select SAMSUNG_DEV_KEYPAD
         select SAMSUNG_DEV_PWM
         select EXYNOS_DEV_SYSMMU
         select EXYNOS_DEV_DMA
+        select EXYNOS_DEV_DRM
+        select EXYNOS4_SETUP_FIMD0
         select EXYNOS4_SETUP_I2C1
         select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C7
         select EXYNOS4_SETUP_KEYPAD
         select EXYNOS4_SETUP_SDHCI
+        select EXYNOS4_SETUP_USB_PHY
         help
           Machine support for Samsung SMDK4212
 
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index bcb7db45314..2f51293c187 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = {
                 .ctrlbit        = (1 << 13),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "exynos4210-spi.0",
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 16),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "exynos4210-spi.1",
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 17),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "exynos4210-spi.2",
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 18),
         }, {
@@ -620,10 +620,6 @@ static struct clk exynos4_init_clocks_off[] = {
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 27),
         }, {
-                .name           = "fimg2d",
-                .enable         = exynos4_clk_ip_image_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
                 .name           = "mfc",
                 .devname        = "s5p-mfc",
                 .enable         = exynos4_clk_ip_mfc_ctrl,
@@ -819,47 +815,21 @@ static struct clk *exynos4_clkset_mout_g2d0_list[] = {
         [1] = &exynos4_clk_sclk_apll.clk,
 };
 
-static struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+struct clksrc_sources exynos4_clkset_mout_g2d0 = {
         .sources        = exynos4_clkset_mout_g2d0_list,
         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
 };
 
-static struct clksrc_clk exynos4_clk_mout_g2d0 = {
-        .clk    = {
-                .name           = "mout_g2d0",
-        },
-        .sources = &exynos4_clkset_mout_g2d0,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
-};
-
 static struct clk *exynos4_clkset_mout_g2d1_list[] = {
         [0] = &exynos4_clk_mout_epll.clk,
         [1] = &exynos4_clk_sclk_vpll.clk,
 };
 
-static struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+struct clksrc_sources exynos4_clkset_mout_g2d1 = {
         .sources        = exynos4_clkset_mout_g2d1_list,
         .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
 };
 
-static struct clksrc_clk exynos4_clk_mout_g2d1 = {
-        .clk    = {
-                .name           = "mout_g2d1",
-        },
-        .sources = &exynos4_clkset_mout_g2d1,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
-};
-
-static struct clk *exynos4_clkset_mout_g2d_list[] = {
-        [0] = &exynos4_clk_mout_g2d0.clk,
-        [1] = &exynos4_clk_mout_g2d1.clk,
-};
-
-static struct clksrc_sources exynos4_clkset_mout_g2d = {
-        .sources        = exynos4_clkset_mout_g2d_list,
-        .nr_sources     = ARRAY_SIZE(exynos4_clkset_mout_g2d_list),
-};
-
 static struct clk *exynos4_clkset_mout_mfc0_list[] = {
         [0] = &exynos4_clk_mout_mpll.clk,
         [1] = &exynos4_clk_sclk_apll.clk,
@@ -1126,13 +1096,6 @@ static struct clksrc_clk exynos4_clksrcs[] = {
                 .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
         }, {
                 .clk    = {
-                        .name           = "sclk_fimg2d",
-                },
-                .sources = &exynos4_clkset_mout_g2d,
-                .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
-                .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
                         .name           = "sclk_mfc",
                         .devname        = "s5p-mfc",
                 },
@@ -1242,40 +1205,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
 };
 
+static struct clksrc_clk exynos4_clk_mdout_spi0 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.0",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi1 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.1",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi2 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.2",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
+
 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "exynos4210-spi.0",
+                .parent         = &exynos4_clk_mdout_spi0.clk,
                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
                 .ctrlbit        = (1 << 16),
         },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
 };
 
 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "exynos4210-spi.1",
+                .parent         = &exynos4_clk_mdout_spi1.clk,
                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
                 .ctrlbit        = (1 << 20),
         },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
 };
 
 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "exynos4210-spi.2",
+                .parent         = &exynos4_clk_mdout_spi2.clk,
                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
                 .ctrlbit        = (1 << 24),
         },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
 };
 
 /* Clock initialization code */
@@ -1331,7 +1321,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
         &exynos4_clk_sclk_spi0,
         &exynos4_clk_sclk_spi1,
         &exynos4_clk_sclk_spi2,
-
+        &exynos4_clk_mdout_spi0,
+        &exynos4_clk_mdout_spi1,
+        &exynos4_clk_mdout_spi2,
 };
 
 static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1347,9 +1339,9 @@ static struct clk_lookup exynos4_clk_lookup[] = {
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
 };
 
 static int xtal_rate;
diff --git a/arch/arm/mach-exynos/clock-exynos4.h b/arch/arm/mach-exynos/clock-exynos4.h
index 28a11970118..bd12d5f8b63 100644
--- a/arch/arm/mach-exynos/clock-exynos4.h
+++ b/arch/arm/mach-exynos/clock-exynos4.h
@@ -23,6 +23,9 @@ extern struct clksrc_sources exynos4_clkset_group;
 extern struct clk *exynos4_clkset_aclk_top_list[];
 extern struct clk *exynos4_clkset_group_list[];
 
+extern struct clksrc_sources exynos4_clkset_mout_g2d0;
+extern struct clksrc_sources exynos4_clkset_mout_g2d1;
+
 extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
 extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index b8689ff60ba..fed4c26e9da 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -48,6 +48,32 @@ static struct clksrc_clk *sysclks[] = {
         /* nothing here yet */
 };
 
+static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
+        .clk    = {
+                .name           = "mout_g2d0",
+        },
+        .sources = &exynos4_clkset_mout_g2d0,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
+        .clk    = {
+                .name           = "mout_g2d1",
+        },
+        .sources = &exynos4_clkset_mout_g2d1,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4210_clkset_mout_g2d_list[] = {
+        [0] = &exynos4210_clk_mout_g2d0.clk,
+        [1] = &exynos4210_clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources exynos4210_clkset_mout_g2d = {
+        .sources        = exynos4210_clkset_mout_g2d_list,
+        .nr_sources     = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
+};
+
 static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
@@ -74,6 +100,13 @@ static struct clksrc_clk clksrcs[] = {
                 .sources = &exynos4_clkset_group,
                 .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
                 .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
+        }, {
+                .clk    = {
+                        .name           = "sclk_fimg2d",
+                },
+                .sources = &exynos4210_clkset_mout_g2d,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
         },
 };
 
@@ -105,6 +138,10 @@ static struct clk init_clocks_off[] = {
                 .devname        = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
                 .enable         = exynos4_clk_ip_lcd1_ctrl,
                 .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "fimg2d",
+                .enable         = exynos4_clk_ip_image_ctrl,
+                .ctrlbit        = (1 << 0),
         },
 };
 
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index da397d21bbc..8fba0b5fb8a 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -68,12 +68,45 @@ static struct clksrc_clk clk_mout_mpll_user = {
         .reg_src        = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
 };
 
+static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
+        .clk    = {
+                .name           = "mout_g2d0",
+        },
+        .sources = &exynos4_clkset_mout_g2d0,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
+        .clk    = {
+                .name           = "mout_g2d1",
+        },
+        .sources = &exynos4_clkset_mout_g2d1,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
+};
+
+static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
+        [0] = &exynos4x12_clk_mout_g2d0.clk,
+        [1] = &exynos4x12_clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
+        .sources        = exynos4x12_clkset_mout_g2d_list,
+        .nr_sources     = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
+};
+
 static struct clksrc_clk *sysclks[] = {
         &clk_mout_mpll_user,
 };
 
 static struct clksrc_clk clksrcs[] = {
-        /* nothing here yet */
+        {
+                .clk    = {
+                        .name           = "sclk_fimg2d",
+                },
+                .sources = &exynos4x12_clkset_mout_g2d,
+                .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
+                .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
+        },
 };
 
 static struct clk init_clocks_off[] = {
@@ -102,7 +135,11 @@ static struct clk init_clocks_off[] = {
                 .devname        = "exynos-fimc-lite.1",
                 .enable         = exynos4212_clk_ip_isp0_ctrl,
                 .ctrlbit        = (1 << 3),
-        }
+        }, {
+                .name           = "fimg2d",
+                .enable         = exynos4_clk_ip_dmc_ctrl,
+                .ctrlbit        = (1 << 23),
+        },
 };
 
 #ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index fefa336be2b..774533c6706 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -131,6 +131,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 }
 
+static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
+}
+
 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
@@ -741,6 +746,24 @@ static struct clk exynos5_init_clocks_off[] = {
                 .enable         = exynos5_clk_ip_peric_ctrl,
                 .ctrlbit        = (1 << 14),
         }, {
+                .name           = "spi",
+                .devname        = "exynos4210-spi.0",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "spi",
+                .devname        = "exynos4210-spi.1",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .devname        = "exynos4210-spi.2",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
                 .name           = SYSMMU_CLOCK_NAME,
                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
                 .enable         = &exynos5_clk_ip_mfc_ctrl,
@@ -1034,6 +1057,69 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
 };
 
+static struct clksrc_clk exynos5_clk_mdout_spi0 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.0",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi1 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.1",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi2 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.2",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "exynos4210-spi.0",
+                .parent         = &exynos5_clk_mdout_spi0.clk,
+                .enable         = exynos5_clksrc_mask_peric1_ctrl,
+                .ctrlbit        = (1 << 16),
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "exynos4210-spi.1",
+                .parent         = &exynos5_clk_mdout_spi1.clk,
+                .enable         = exynos5_clksrc_mask_peric1_ctrl,
+                .ctrlbit        = (1 << 20),
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi2 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "exynos4210-spi.2",
+                .parent         = &exynos5_clk_mdout_spi2.clk,
+                .enable         = exynos5_clksrc_mask_peric1_ctrl,
+                .ctrlbit        = (1 << 24),
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
+};
+
 static struct clksrc_clk exynos5_clksrcs[] = {
         {
                 .clk    = {
@@ -1148,6 +1234,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
         &exynos5_clk_dout_mmc4,
         &exynos5_clk_aclk_acp,
         &exynos5_clk_pclk_acp,
+        &exynos5_clk_sclk_spi0,
+        &exynos5_clk_sclk_spi1,
+        &exynos5_clk_sclk_spi2,
+        &exynos5_clk_mdout_spi0,
+        &exynos5_clk_mdout_spi1,
+        &exynos5_clk_mdout_spi2,
 };
 
 static struct clk *exynos5_clk_cdev[] = {
@@ -1176,6 +1268,9 @@ static struct clk_lookup exynos5_clk_lookup[] = {
         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
+        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
+        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 742edd3bbec..4eb39cdf75e 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -540,7 +540,8 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
         .map    = combiner_irq_domain_map,
 };
 
-void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
+static void __init combiner_init(void __iomem *combiner_base,
+                                 struct device_node *np)
 {
         int i, irq, irq_base;
         unsigned int max_nr, nr_irq;
@@ -712,31 +713,6 @@ static int __init exynos4_l2x0_cache_init(void)
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
-static int __init exynos5_l2_cache_init(void)
-{
-        unsigned int val;
-
-        if (!soc_is_exynos5250())
-                return 0;
-
-        asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
-                     "bic %0, %0, #(1 << 2)\n"  /* cache disable */
-                     "mcr p15, 0, %0, c1, c0, 0\n"
-                     "mrc p15, 1, %0, c9, c0, 2\n"
-                     : "=r"(val));
-
-        val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
-
-        asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
-        asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
-                     "orr %0, %0, #(1 << 2)\n"  /* cache enable */
-                     "mcr p15, 0, %0, c1, c0, 0\n"
-                     : : "r"(val));
-
-        return 0;
-}
-early_initcall(exynos5_l2_cache_init);
-
 static int __init exynos_init(void)
 {
         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 7a4b4789eb7..35bced6f909 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -195,6 +195,10 @@
 #define IRQ_IIC6                        EXYNOS4_IRQ_IIC6
 #define IRQ_IIC7                        EXYNOS4_IRQ_IIC7
 
+#define IRQ_SPI0                        EXYNOS4_IRQ_SPI0
+#define IRQ_SPI1                        EXYNOS4_IRQ_SPI1
+#define IRQ_SPI2                        EXYNOS4_IRQ_SPI2
+
 #define IRQ_USB_HOST                    EXYNOS4_IRQ_USB_HOST
 #define IRQ_OTG                         EXYNOS4_IRQ_USB_HSOTG
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index ca4aa89aa46..c72b675b3e4 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -154,6 +154,9 @@
 #define EXYNOS4_PA_SPI0                 0x13920000
 #define EXYNOS4_PA_SPI1                 0x13930000
 #define EXYNOS4_PA_SPI2                 0x13940000
+#define EXYNOS5_PA_SPI0                 0x12D20000
+#define EXYNOS5_PA_SPI1                 0x12D30000
+#define EXYNOS5_PA_SPI2                 0x12D40000
 
 #define EXYNOS4_PA_GPIO1                0x11400000
 #define EXYNOS4_PA_GPIO2                0x11000000
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 43a99e6f56a..d4e392b811a 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -232,6 +232,11 @@
 
 #define EXYNOS5_USB_CFG                                         S5P_PMUREG(0x0230)
 
+#define EXYNOS5_AUTO_WDTRESET_DISABLE                           S5P_PMUREG(0x0408)
+#define EXYNOS5_MASK_WDTRESET_REQUEST                           S5P_PMUREG(0x040C)
+
+#define EXYNOS5_SYS_WDTRESET                                    (1 << 20)
+
 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG                           S5P_PMUREG(0x1000)
 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG             S5P_PMUREG(0x1004)
 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG           S5P_PMUREG(0x1008)
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
index c337cf3a71b..07277735252 100644
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -35,11 +35,21 @@
 #define PHY1_COMMON_ON_N                (1 << 7)
 #define PHY0_COMMON_ON_N                (1 << 4)
 #define PHY0_ID_PULLUP                  (1 << 2)
-#define CLKSEL_MASK                     (0x3 << 0)
-#define CLKSEL_SHIFT                    (0)
-#define CLKSEL_48M                      (0x0 << 0)
-#define CLKSEL_12M                      (0x2 << 0)
-#define CLKSEL_24M                      (0x3 << 0)
+
+#define EXYNOS4_CLKSEL_SHIFT            (0)
+
+#define EXYNOS4210_CLKSEL_MASK          (0x3 << 0)
+#define EXYNOS4210_CLKSEL_48M           (0x0 << 0)
+#define EXYNOS4210_CLKSEL_12M           (0x2 << 0)
+#define EXYNOS4210_CLKSEL_24M           (0x3 << 0)
+
+#define EXYNOS4X12_CLKSEL_MASK          (0x7 << 0)
+#define EXYNOS4X12_CLKSEL_9600K         (0x0 << 0)
+#define EXYNOS4X12_CLKSEL_10M           (0x1 << 0)
+#define EXYNOS4X12_CLKSEL_12M           (0x2 << 0)
+#define EXYNOS4X12_CLKSEL_19200K        (0x3 << 0)
+#define EXYNOS4X12_CLKSEL_20M           (0x4 << 0)
+#define EXYNOS4X12_CLKSEL_24M           (0x5 << 0)
 
 #define EXYNOS4_RSTCON                  EXYNOS4_HSOTG_PHYREG(0x08)
 #define HOST_LINK_PORT_SWRST_MASK       (0xf << 6)
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
deleted file mode 100644
index c71a5fba6a8..00000000000
--- a/arch/arm/mach-exynos/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h
- *
- * Copyright (C) 2011 Samsung Electronics Co. Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_SPI_CLKS_H
-#define __ASM_ARCH_SPI_CLKS_H __FILE__
-
-/* Must source from SCLK_SPI */
-#define EXYNOS_SPI_SRCCLK_SCLK          0
-
-#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index e7e9743543a..b2b5d5faa74 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -55,6 +55,12 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
                                 "exynos4-sdhci.3", NULL),
         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
                                 "s3c2440-i2c.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
+                                "exynos4210-spi.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
+                                "exynos4210-spi.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
+                                "exynos4210-spi.2", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
         {},
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 7b1e11a228c..ef770bc2318 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -47,6 +47,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                 "s3c2440-i2c.0", NULL),
         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
                                 "s3c2440-i2c.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
+                                "exynos4210-spi.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
+                                "exynos4210-spi.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
+                                "exynos4210-spi.2", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 656f8fc9add..ea785fcaf6c 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -50,7 +50,6 @@
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 #include <plat/mfc.h>
-#include <plat/pd.h>
 #include <plat/fimc-core.h>
 #include <plat/camport.h>
 #include <plat/mipi_csis.h>
@@ -1067,12 +1066,8 @@ static struct platform_device nuri_max8903_device = {
 static void __init nuri_power_init(void)
 {
         int gpio;
-        int irq_base = IRQ_GPIO_END + 1;
         int ta_en = 0;
 
-        nuri_max8997_pdata.irq_base = irq_base;
-        irq_base += MAX8997_IRQ_NR;
-
         gpio = EXYNOS4_GPX0(7);
         gpio_request(gpio, "AP_PMIC_IRQ");
         s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
@@ -1342,9 +1337,8 @@ static struct platform_device *nuri_devices[] __initdata = {
 
 static void __init nuri_map_io(void)
 {
-        clk_xusbxti.rate = 24000000;
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
 }
 
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index f5572be9d7b..4e574c24581 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -9,6 +9,7 @@
 */
 
 #include <linux/serial_core.h>
+#include <linux/leds.h>
 #include <linux/gpio.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
@@ -21,6 +22,7 @@
 #include <linux/mfd/max8997.h>
 #include <linux/lcd.h>
 #include <linux/rfkill-gpio.h>
+#include <linux/platform_data/s3c-hsotg.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -38,9 +40,9 @@
 #include <plat/clock.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
-#include <plat/pd.h>
 #include <plat/fb.h>
 #include <plat/mfc.h>
+#include <plat/hdmi.h>
 
 #include <mach/ohci.h>
 #include <mach/map.h>
@@ -425,7 +427,6 @@ static struct max8997_platform_data __initdata origen_max8997_pdata = {
         .buck1_gpiodvs  = false,
         .buck2_gpiodvs  = false,
         .buck5_gpiodvs  = false,
-        .irq_base       = IRQ_GPIO_END + 1,
 
         .ignore_gpiodvs_side_effect = true,
         .buck125_default_idx = 0x0,
@@ -499,6 +500,37 @@ static void __init origen_ohci_init(void)
         exynos4_ohci_set_platdata(pdata);
 }
 
+/* USB OTG */
+static struct s3c_hsotg_plat origen_hsotg_pdata;
+
+static struct gpio_led origen_gpio_leds[] = {
+        {
+                .name                   = "origen::status1",
+                .default_trigger        = "heartbeat",
+                .gpio                   = EXYNOS4_GPX1(3),
+                .active_low             = 1,
+        },
+        {
+                .name                   = "origen::status2",
+                .default_trigger        = "mmc0",
+                .gpio                   = EXYNOS4_GPX1(4),
+                .active_low             = 1,
+        },
+};
+
+static struct gpio_led_platform_data origen_gpio_led_info = {
+        .leds           = origen_gpio_leds,
+        .num_leds       = ARRAY_SIZE(origen_gpio_leds),
+};
+
+static struct platform_device origen_leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &origen_gpio_led_info,
+        },
+};
+
 static struct gpio_keys_button origen_gpio_keys_table[] = {
         {
                 .code                   = KEY_MENU,
@@ -655,6 +687,7 @@ static struct platform_device *origen_devices[] __initdata = {
         &s3c_device_hsmmc0,
         &s3c_device_i2c0,
         &s3c_device_rtc,
+        &s3c_device_usb_hsotg,
         &s3c_device_wdt,
         &s5p_device_ehci,
         &s5p_device_fimc0,
@@ -677,6 +710,7 @@ static struct platform_device *origen_devices[] __initdata = {
         &exynos4_device_ohci,
         &origen_device_gpiokeys,
         &origen_lcd_hv070wsa,
+        &origen_leds_gpio,
         &origen_device_bluetooth,
 };
 
@@ -701,6 +735,11 @@ static void __init origen_bt_setup(void)
         s3c_gpio_setpull(EXYNOS4_GPX2(2), S3C_GPIO_PULL_NONE);
 }
 
+/* I2C module and id for HDMIPHY */
+static struct i2c_board_info hdmiphy_info = {
+        I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
+};
+
 static void s5p_tv_setup(void)
 {
         /* Direct HPD to HDMI chip */
@@ -712,7 +751,7 @@ static void s5p_tv_setup(void)
 static void __init origen_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
 }
 
@@ -744,10 +783,11 @@ static void __init origen_machine_init(void)
 
         origen_ehci_init();
         origen_ohci_init();
-        clk_xusbxti.rate = 24000000;
+        s3c_hsotg_set_platdata(&origen_hsotg_pdata);
 
         s5p_tv_setup();
         s5p_i2c_hdmiphy_set_platdata(NULL);
+        s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
 
 #ifdef CONFIG_DRM_EXYNOS
         s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fb09c70e195..b26beb13ebe 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -13,12 +13,14 @@
 #include <linux/i2c.h>
 #include <linux/input.h>
 #include <linux/io.h>
+#include <linux/lcd.h>
 #include <linux/mfd/max8997.h>
 #include <linux/mmc/host.h>
 #include <linux/platform_device.h>
 #include <linux/pwm_backlight.h>
 #include <linux/regulator/machine.h>
 #include <linux/serial_core.h>
+#include <linux/platform_data/s3c-hsotg.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -28,15 +30,18 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
+#include <plat/fb.h>
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 #include <plat/keypad.h>
 #include <plat/mfc.h>
+#include <plat/regs-fb.h>
 #include <plat/regs-serial.h>
 #include <plat/sdhci.h>
 
 #include <mach/map.h>
 
+#include <drm/exynos_drm.h>
 #include "common.h"
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
@@ -219,8 +224,10 @@ static struct platform_pwm_backlight_data smdk4x12_bl_data = {
 
 static uint32_t smdk4x12_keymap[] __initdata = {
         /* KEY(row, col, keycode) */
-        KEY(1, 0, KEY_D), KEY(1, 1, KEY_A), KEY(1, 2, KEY_B),
-        KEY(1, 3, KEY_E), KEY(1, 4, KEY_C)
+        KEY(1, 3, KEY_1), KEY(1, 4, KEY_2), KEY(1, 5, KEY_3),
+        KEY(1, 6, KEY_4), KEY(1, 7, KEY_5),
+        KEY(2, 5, KEY_D), KEY(2, 6, KEY_A), KEY(2, 7, KEY_B),
+        KEY(0, 7, KEY_E), KEY(0, 5, KEY_C)
 };
 
 static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
@@ -230,10 +237,62 @@ static struct matrix_keymap_data smdk4x12_keymap_data __initdata = {
 
 static struct samsung_keypad_platdata smdk4x12_keypad_data __initdata = {
         .keymap_data    = &smdk4x12_keymap_data,
-        .rows           = 2,
-        .cols           = 5,
+        .rows           = 3,
+        .cols           = 8,
 };
 
+#ifdef CONFIG_DRM_EXYNOS
+static struct exynos_drm_fimd_pdata drm_fimd_pdata = {
+        .panel  = {
+                .timing = {
+                        .left_margin    = 8,
+                        .right_margin   = 8,
+                        .upper_margin   = 6,
+                        .lower_margin   = 6,
+                        .hsync_len      = 6,
+                        .vsync_len      = 4,
+                        .xres           = 480,
+                        .yres           = 800,
+                },
+        },
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .default_win    = 0,
+        .bpp            = 32,
+};
+#else
+static struct s3c_fb_pd_win smdk4x12_fb_win0 = {
+        .xres           = 480,
+        .yres           = 800,
+        .virtual_x      = 480,
+        .virtual_y      = 800 * 2,
+        .max_bpp        = 32,
+        .default_bpp    = 24,
+};
+
+static struct fb_videomode smdk4x12_lcd_timing = {
+        .left_margin    = 8,
+        .right_margin   = 8,
+        .upper_margin   = 6,
+        .lower_margin   = 6,
+        .hsync_len      = 6,
+        .vsync_len      = 4,
+        .xres           = 480,
+        .yres           = 800,
+};
+
+static struct s3c_fb_platdata smdk4x12_lcd_pdata __initdata = {
+        .win[0]         = &smdk4x12_fb_win0,
+        .vtiming        = &smdk4x12_lcd_timing,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
+};
+#endif
+
+/* USB OTG */
+static struct s3c_hsotg_plat smdk4x12_hsotg_pdata;
+
 static struct platform_device *smdk4x12_devices[] __initdata = {
         &s3c_device_hsmmc2,
         &s3c_device_hsmmc3,
@@ -242,22 +301,25 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
         &s3c_device_i2c3,
         &s3c_device_i2c7,
         &s3c_device_rtc,
+        &s3c_device_usb_hsotg,
         &s3c_device_wdt,
         &s5p_device_fimc0,
         &s5p_device_fimc1,
         &s5p_device_fimc2,
         &s5p_device_fimc3,
         &s5p_device_fimc_md,
+        &s5p_device_fimd0,
         &s5p_device_mfc,
         &s5p_device_mfc_l,
         &s5p_device_mfc_r,
+#ifdef CONFIG_DRM_EXYNOS
+        &exynos_device_drm,
+#endif
         &samsung_device_keypad,
 };
 
 static void __init smdk4x12_map_io(void)
 {
-        clk_xusbxti.rate = 24000000;
-
         exynos_init_io(NULL, 0);
         s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
@@ -293,6 +355,15 @@ static void __init smdk4x12_machine_init(void)
         s3c_sdhci2_set_platdata(&smdk4x12_hsmmc2_pdata);
         s3c_sdhci3_set_platdata(&smdk4x12_hsmmc3_pdata);
 
+        s3c_hsotg_set_platdata(&smdk4x12_hsotg_pdata);
+
+#ifdef CONFIG_DRM_EXYNOS
+        s5p_device_fimd0.dev.platform_data = &drm_fimd_pdata;
+        exynos4_fimd0_gpio_setup_24bpp();
+#else
+        s5p_fimd0_set_platdata(&smdk4x12_lcd_pdata);
+#endif
+
         platform_add_devices(smdk4x12_devices, ARRAY_SIZE(smdk4x12_devices));
 }
 
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 262e9e446a9..73f2bce097e 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -19,6 +19,7 @@
 #include <linux/i2c.h>
 #include <linux/input.h>
 #include <linux/pwm_backlight.h>
+#include <linux/platform_data/s3c-hsotg.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -34,12 +35,12 @@
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/iic.h>
-#include <plat/pd.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
 #include <plat/mfc.h>
 #include <plat/ehci.h>
 #include <plat/clock.h>
+#include <plat/hdmi.h>
 
 #include <mach/map.h>
 #include <mach/ohci.h>
@@ -271,6 +272,15 @@ static void __init smdkv310_ohci_init(void)
         exynos4_ohci_set_platdata(pdata);
 }
 
+/* USB OTG */
+static struct s3c_hsotg_plat smdkv310_hsotg_pdata;
+
+/* Audio device */
+static struct platform_device smdkv310_device_audio = {
+        .name = "smdk-audio",
+        .id = -1,
+};
+
 static struct platform_device *smdkv310_devices[] __initdata = {
         &s3c_device_hsmmc0,
         &s3c_device_hsmmc1,
@@ -279,6 +289,7 @@ static struct platform_device *smdkv310_devices[] __initdata = {
         &s3c_device_i2c1,
         &s5p_device_i2c_hdmiphy,
         &s3c_device_rtc,
+        &s3c_device_usb_hsotg,
         &s3c_device_wdt,
         &s5p_device_ehci,
         &s5p_device_fimc0,
@@ -302,6 +313,7 @@ static struct platform_device *smdkv310_devices[] __initdata = {
         &samsung_asoc_dma,
         &samsung_asoc_idma,
         &s5p_device_fimd0,
+        &smdkv310_device_audio,
         &smdkv310_lcd_lte480wv,
         &smdkv310_smsc911x,
         &exynos4_device_ahci,
@@ -343,6 +355,11 @@ static struct platform_pwm_backlight_data smdkv310_bl_data = {
         .pwm_period_ns  = 1000,
 };
 
+/* I2C module and id for HDMIPHY */
+static struct i2c_board_info hdmiphy_info = {
+        I2C_BOARD_INFO("hdmiphy-exynos4210", 0x38),
+};
+
 static void s5p_tv_setup(void)
 {
         /* direct HPD to HDMI chip */
@@ -354,7 +371,7 @@ static void s5p_tv_setup(void)
 static void __init smdkv310_map_io(void)
 {
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
 }
 
@@ -377,6 +394,7 @@ static void __init smdkv310_machine_init(void)
 
         s5p_tv_setup();
         s5p_i2c_hdmiphy_set_platdata(NULL);
+        s5p_hdmi_set_platdata(&hdmiphy_info, NULL, 0);
 
         samsung_keypad_set_platdata(&smdkv310_keypad_data);
 
@@ -390,7 +408,7 @@ static void __init smdkv310_machine_init(void)
 
         smdkv310_ehci_init();
         smdkv310_ohci_init();
-        clk_xusbxti.rate = 24000000;
+        s3c_hsotg_set_platdata(&smdkv310_hsotg_pdata);
 
         platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
 }
@@ -417,5 +435,6 @@ MACHINE_START(SMDKC210, "SMDKC210")
         .init_machine   = smdkv310_machine_init,
         .init_late      = exynos_init_late,
         .timer          = &exynos4_timer,
+        .reserve        = &smdkv310_reserve,
         .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index cd92fa86ba4..4d1f40d44ed 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -39,7 +39,6 @@
 #include <plat/fb.h>
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
-#include <plat/pd.h>
 #include <plat/regs-fb-v4.h>
 #include <plat/fimc-core.h>
 #include <plat/s5p-time.h>
@@ -1100,9 +1099,8 @@ static struct platform_device *universal_devices[] __initdata = {
 
 static void __init universal_map_io(void)
 {
-        clk_xusbxti.rate = 24000000;
         exynos_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
         s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
 }
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 373c3c00d24..c0bc83a7663 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -115,7 +115,7 @@ static __init int exynos_pm_dt_parse_domains(void)
 }
 #endif /* CONFIG_OF */
 
-static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
+static __init __maybe_unused void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
                                                 struct exynos_pm_domain *pd)
 {
         if (pdev->dev.bus) {
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 4aacb66f716..3a48c852be6 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -315,7 +315,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-void __iomem *exynos5_list_both_cnt_feed[] = {
+static void __iomem *exynos5_list_both_cnt_feed[] = {
         EXYNOS5_ARM_CORE0_OPTION,
         EXYNOS5_ARM_CORE1_OPTION,
         EXYNOS5_ARM_COMMON_OPTION,
@@ -329,7 +329,7 @@ void __iomem *exynos5_list_both_cnt_feed[] = {
         EXYNOS5_TOP_PWR_SYSMEM_OPTION,
 };
 
-void __iomem *exynos5_list_diable_wfi_wfe[] = {
+static void __iomem *exynos5_list_diable_wfi_wfe[] = {
         EXYNOS5_ARM_CORE1_OPTION,
         EXYNOS5_FSYS_ARM_OPTION,
         EXYNOS5_ISP_ARM_OPTION,
@@ -390,6 +390,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 
 static int __init exynos_pmu_init(void)
 {
+        unsigned int value;
+
         exynos_pmu_config = exynos4210_pmu_config;
 
         if (soc_is_exynos4210()) {
@@ -399,6 +401,18 @@ static int __init exynos_pmu_init(void)
                 exynos_pmu_config = exynos4x12_pmu_config;
                 pr_info("EXYNOS4x12 PMU Initialize\n");
         } else if (soc_is_exynos5250()) {
+                /*
+                 * When SYS_WDTRESET is set, watchdog timer reset request
+                 * is ignored by power management unit.
+                 */
+                value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+                value &= ~EXYNOS5_SYS_WDTRESET;
+                __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+
+                value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+                value &= ~EXYNOS5_SYS_WDTRESET;
+                __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+
                 exynos_pmu_config = exynos5250_pmu_config;
                 pr_info("EXYNOS5250 PMU Initialize\n");
         } else {
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
index 833ff40ee0e..4999829d1c6 100644
--- a/arch/arm/mach-exynos/setup-spi.c
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -9,21 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .clk_from_cmu   = true,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
@@ -34,15 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .clk_from_cmu   = true,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
@@ -53,15 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .clk_from_cmu   = true,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi2_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
         s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 1af0a7f44e0..b81cc569a8d 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
         struct clk *xusbxti_clk;
         u32 phyclk;
 
-        /* set clock frequency for PLL */
-        phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
-
         xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
         if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
-                switch (clk_get_rate(xusbxti_clk)) {
-                case 12 * MHZ:
-                        phyclk |= CLKSEL_12M;
-                        break;
-                case 24 * MHZ:
-                        phyclk |= CLKSEL_24M;
-                        break;
-                default:
-                case 48 * MHZ:
-                        /* default reference clock */
-                        break;
+                if (soc_is_exynos4210()) {
+                        /* set clock frequency for PLL */
+                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
+
+                        switch (clk_get_rate(xusbxti_clk)) {
+                        case 12 * MHZ:
+                                phyclk |= EXYNOS4210_CLKSEL_12M;
+                                break;
+                        case 48 * MHZ:
+                                phyclk |= EXYNOS4210_CLKSEL_48M;
+                                break;
+                        default:
+                        case 24 * MHZ:
+                                phyclk |= EXYNOS4210_CLKSEL_24M;
+                                break;
+                        }
+                        writel(phyclk, EXYNOS4_PHYCLK);
+                } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                        /* set clock frequency for PLL */
+                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
+
+                        switch (clk_get_rate(xusbxti_clk)) {
+                        case 9600 * KHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_9600K;
+                                break;
+                        case 10 * MHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_10M;
+                                break;
+                        case 12 * MHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_12M;
+                                break;
+                        case 19200 * KHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_19200K;
+                                break;
+                        case 20 * MHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_20M;
+                                break;
+                        default:
+                        case 24 * MHZ:
+                                /* default reference clock */
+                                phyclk |= EXYNOS4X12_CLKSEL_24M;
+                                break;
+                        }
+                        writel(phyclk, EXYNOS4_PHYCLK);
                 }
                 clk_put(xusbxti_clk);
         }
-
-        writel(phyclk, EXYNOS4_PHYCLK);
 }
 
 static int exynos4210_usb_phy0_init(struct platform_device *pdev)
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index ca70e5fcc7a..020852d3bdd 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -17,6 +17,7 @@
 #include <linux/sched.h>
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
+#include <asm/system_misc.h>
 #include <mach/hardware.h>
 
 #define IRQ_SOURCE(base_addr)   (base_addr + 0x00)
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
index ded4652ada8..3ec8bdd25d0 100644
--- a/arch/arm/mach-highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
@@ -1,4 +1,4 @@
-obj-y                                   := clock.o highbank.o system.o smc.o
+obj-y                                   := highbank.o system.o smc.o
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_smc.o                            :=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-highbank/clock.c b/arch/arm/mach-highbank/clock.c
deleted file mode 100644
index c25a2ae4fde..00000000000
--- a/arch/arm/mach-highbank/clock.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2011 Calxeda, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-
-struct clk {
-        unsigned long rate;
-};
-
-int clk_enable(struct clk *clk)
-{
-        return 0;
-}
-
-void clk_disable(struct clk *clk)
-{}
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        return clk->rate;
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        return 0;
-}
-
-static struct clk eclk = { .rate = 200000000 };
-static struct clk pclk = { .rate = 150000000 };
-
-static struct clk_lookup lookups[] = {
-        { .clk = &pclk, .con_id = "apb_pclk", },
-        { .clk = &pclk, .dev_id = "sp804", },
-        { .clk = &eclk, .dev_id = "ffe0e000.sdhci", },
-        { .clk = &pclk, .dev_id = "fff36000.serial", },
-};
-
-void __init highbank_clocks_init(void)
-{
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 8777612b1a4..d75b0a78d88 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -105,6 +105,11 @@ static void __init highbank_init_irq(void)
 #endif
 }
 
+static struct clk_lookup lookup = {
+        .dev_id = "sp804",
+        .con_id = NULL,
+};
+
 static void __init highbank_timer_init(void)
 {
         int irq;
@@ -122,6 +127,8 @@ static void __init highbank_timer_init(void)
         irq = irq_of_parse_and_map(np, 0);
 
         highbank_clocks_init();
+        lookup.clk = of_clk_get(np, 0);
+        clkdev_add(&lookup);
 
         sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
         sp804_clockevents_init(timer_base, irq, "timer0");
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index eff4db5de0d..afd542ad6f9 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -52,6 +52,7 @@ config SOC_IMX25
         select ARCH_MX25
         select COMMON_CLK
         select CPU_ARM926T
+        select HAVE_CAN_FLEXCAN if CAN
         select ARCH_MXC_IOMUX_V3
         select MXC_AVIC
 
@@ -73,12 +74,13 @@ config SOC_IMX31
 
 config SOC_IMX35
         bool
-        select CPU_V6
+        select CPU_V6K
         select ARCH_MXC_IOMUX_V3
         select COMMON_CLK
         select HAVE_EPIT
         select MXC_AVIC
         select SMP_ON_UP if SMP
+        select HAVE_CAN_FLEXCAN if CAN
 
 config SOC_IMX5
         select CPU_V7
@@ -105,6 +107,7 @@ config	SOC_IMX53
         select SOC_IMX5
         select ARCH_MX5
         select ARCH_MX53
+        select HAVE_CAN_FLEXCAN if CAN
 
 if ARCH_IMX_V4_V5
 
@@ -158,7 +161,6 @@ config MACH_MX25_3DS
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMXDI_RTC
         select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
@@ -380,7 +382,6 @@ config MACH_IMX27IPCAM
 config MACH_IMX27_DT
         bool "Support i.MX27 platforms from device tree"
         select SOC_IMX27
-        select USE_OF
         help
           Include support for Freescale i.MX27 based platforms
           using the device tree for discovery
@@ -557,6 +558,14 @@ config MACH_BUG
           Include support for BUGBase 1.3 platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_IMX31_DT
+        bool "Support i.MX31 platforms from device tree"
+        select SOC_IMX31
+        select USE_OF
+        help
+          Include support for Freescale i.MX31 based platforms
+          using the device tree for discovery.
+
 comment "MX35 platforms:"
 
 config MACH_PCM043
@@ -589,6 +598,7 @@ config MACH_MX35_3DS
         select IMX_HAVE_PLATFORM_IPU_CORE
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_MXC_RTC
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         help
           Include support for MX35PDK platform. This includes specific
@@ -663,7 +673,6 @@ comment "i.MX51 machines:"
 config MACH_IMX51_DT
         bool "Support i.MX51 platforms from device tree"
         select SOC_IMX51
-        select USE_OF
         select MACH_MX51_BABBAGE
         help
           Include support for Freescale i.MX51 based platforms
@@ -759,7 +768,6 @@ comment "i.MX53 machines:"
 config MACH_IMX53_DT
         bool "Support i.MX53 platforms from device tree"
         select SOC_IMX53
-        select USE_OF
         select MACH_MX53_ARD
         select MACH_MX53_EVK
         select MACH_MX53_LOCO
@@ -826,13 +834,14 @@ config SOC_IMX6Q
         select COMMON_CLK
         select CPU_V7
         select HAVE_ARM_SCU
+        select HAVE_CAN_FLEXCAN if CAN
         select HAVE_IMX_GPC
         select HAVE_IMX_MMDC
         select HAVE_IMX_SRC
         select HAVE_SMP
+        select MFD_ANATOP
         select PINCTRL
         select PINCTRL_IMX6Q
-        select USE_OF
 
         help
           This enables support for Freescale i.MX6 Quad processor.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ff29421414f..d004d37ad9d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -9,7 +9,8 @@ obj-$(CONFIG_SOC_IMX27) += clk-imx27.o mm-imx27.o ehci-imx27.o
 obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-imx31.o pm-imx3.o
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
+imx5-pm-$(CONFIG_PM) += pm-imx5.o
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
                             clk-pfd.o clk-busy.o
@@ -57,6 +58,7 @@ obj-$(CONFIG_MACH_QONG) += mach-qong.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
 obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
 obj-$(CONFIG_MACH_BUG) += mach-bug.o
+obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o
 
 # i.MX35 based machines
 obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
@@ -69,14 +71,13 @@ obj-$(CONFIG_DEBUG_LL) += lluart.o
 obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
 obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
 obj-$(CONFIG_HAVE_IMX_SRC) += src.o
-obj-$(CONFIG_CPU_V7) += head-v7.o
-AFLAGS_head-v7.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_SMP) += platsmp.o
+AFLAGS_headsmp.o :=-Wa,-march=armv7-a
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
 
 ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
 endif
 
 # i.MX5 based machines
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 295cbd7c08d..f69ca468004 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -223,7 +223,7 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[per3_gate], "per", "imx-fb.0");
         clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
         clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx-fb.0");
-        clk_register_clkdev(clk[csi_ahb_gate], NULL, "mx2-camera.0");
+        clk_register_clkdev(clk[csi_ahb_gate], "ahb", "mx2-camera.0");
         clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
         clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc");
         clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc");
@@ -250,13 +250,15 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx-i2c.1");
         clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
         clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
-        clk_register_clkdev(clk[emma_ahb_gate], "ahb", "imx-emma");
-        clk_register_clkdev(clk[emma_ipg_gate], "ipg", "imx-emma");
+        clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "mx2-camera.0");
+        clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "mx2-camera.0");
+        clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
+        clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
         clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL);
         clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
         clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
         clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
-        clk_register_clkdev(clk[rtc_ipg_gate], "rtc", NULL);
+        clk_register_clkdev(clk[rtc_ipg_gate], NULL, "mxc_rtc");
         clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
         clk_register_clkdev(clk[cpu_div], "cpu", NULL);
         clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
@@ -267,6 +269,8 @@ int __init mx27_clocks_init(unsigned long fref)
 
         clk_prepare_enable(clk[emi_ahb_gate]);
 
+        imx_print_silicon_rev("i.MX27", mx27_revision());
+
         return 0;
 }
 
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index c9a06d800f8..1253af2d997 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -20,6 +20,7 @@
 #include <linux/clkdev.h>
 #include <linux/io.h>
 #include <linux/err.h>
+#include <linux/of.h>
 
 #include <mach/hardware.h>
 #include <mach/mx31.h>
@@ -123,13 +124,13 @@ int __init mx31_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2");
         clk_register_clkdev(clk[pwm_gate], "pwm", NULL);
         clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
+        clk_register_clkdev(clk[rtc_gate], NULL, "mxc_rtc");
         clk_register_clkdev(clk[epit1_gate], "epit", NULL);
         clk_register_clkdev(clk[epit2_gate], "epit", NULL);
         clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0");
         clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
         clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
-        clk_register_clkdev(clk[kpp_gate], "kpp", NULL);
+        clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
         clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0");
         clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0");
         clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
@@ -165,7 +166,7 @@ int __init mx31_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[firi_gate], "firi", NULL);
         clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
         clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
-        clk_register_clkdev(clk[rng_gate], "rng", NULL);
+        clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga");
         clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma");
         clk_register_clkdev(clk[iim_gate], "iim", NULL);
 
@@ -179,3 +180,21 @@ int __init mx31_clocks_init(unsigned long fref)
 
         return 0;
 }
+
+#ifdef CONFIG_OF
+int __init mx31_clocks_init_dt(void)
+{
+        struct device_node *np;
+        u32 fref = 26000000; /* default */
+
+        for_each_compatible_node(np, NULL, "fixed-clock") {
+                if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
+                        continue;
+
+                if (!of_property_read_u32(np, "clock-frequency", &fref))
+                        break;
+        }
+
+        return mx31_clocks_init(fref);
+}
+#endif
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index a2200c77bf7..4bdcaa97bd9 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -58,7 +58,7 @@ enum imx5_clks {
         tve_s, uart1_ipg_gate, uart1_per_gate, uart2_ipg_gate,
         uart2_per_gate, uart3_ipg_gate, uart3_per_gate, i2c1_gate, i2c2_gate,
         gpt_ipg_gate, pwm1_ipg_gate, pwm1_hf_gate, pwm2_ipg_gate, pwm2_hf_gate,
-        gpt_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
+        gpt_hf_gate, fec_gate, usboh3_per_gate, esdhc1_ipg_gate, esdhc2_ipg_gate,
         esdhc3_ipg_gate, esdhc4_ipg_gate, ssi1_ipg_gate, ssi2_ipg_gate,
         ssi3_ipg_gate, ecspi1_ipg_gate, ecspi1_per_gate, ecspi2_ipg_gate,
         ecspi2_per_gate, cspi_ipg_gate, sdma_gate, emi_slow_gate, ipu_s,
@@ -81,6 +81,7 @@ enum imx5_clks {
         ssi1_root_podf, ssi2_root_pred, ssi2_root_podf, ssi_ext1_pred,
         ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
         ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
+        epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
         clk_max
 };
 
@@ -167,12 +168,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk[uart3_per_gate] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
         clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
         clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
-        clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 20);
         clk[pwm1_ipg_gate] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
-        clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "ipg", MXC_CCM_CCGR2, 12);
+        clk[pwm1_hf_gate] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
         clk[pwm2_ipg_gate] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
-        clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "ipg", MXC_CCM_CCGR2, 16);
-        clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per_root", MXC_CCM_CCGR2, 18);
+        clk[pwm2_hf_gate] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
+        clk[gpt_ipg_gate] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
+        clk[gpt_hf_gate] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
         clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
         clk[usboh3_gate] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
         clk[usboh3_per_gate] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
@@ -226,13 +227,17 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk[ssi3_root_gate] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
         clk[ssi_ext1_gate] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
         clk[ssi_ext2_gate] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
+        clk[epit1_ipg_gate] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
+        clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
+        clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
+        clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
 
         for (i = 0; i < ARRAY_SIZE(clk); i++)
                 if (IS_ERR(clk[i]))
                         pr_err("i.MX5 clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
         
-        clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0");
+        clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0");
         clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0");
         clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");
         clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
@@ -248,7 +253,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[ecspi1_ipg_gate], "ipg", "imx51-ecspi.0");
         clk_register_clkdev(clk[ecspi2_per_gate], "per", "imx51-ecspi.1");
         clk_register_clkdev(clk[ecspi2_ipg_gate], "ipg", "imx51-ecspi.1");
-        clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx51-cspi.0");
+        clk_register_clkdev(clk[cspi_ipg_gate], NULL, "imx35-cspi.2");
         clk_register_clkdev(clk[pwm1_ipg_gate], "pwm", "mxc_pwm.0");
         clk_register_clkdev(clk[pwm2_ipg_gate], "pwm", "mxc_pwm.1");
         clk_register_clkdev(clk[i2c1_gate], NULL, "imx-i2c.0");
@@ -279,6 +284,11 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
         clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
         clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
+        clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
+        clk_register_clkdev(clk[epit1_ipg_gate], "ipg", "imx-epit.0");
+        clk_register_clkdev(clk[epit1_hf_gate], "per", "imx-epit.0");
+        clk_register_clkdev(clk[epit2_ipg_gate], "ipg", "imx-epit.1");
+        clk_register_clkdev(clk[epit2_hf_gate], "per", "imx-epit.1");
 
         /* Set SDHC parents to be PLL2 */
         clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
@@ -293,6 +303,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_prepare_enable(clk[aips_tz2]); /* fec */
         clk_prepare_enable(clk[spba]);
         clk_prepare_enable(clk[emi_fast_gate]); /* fec */
+        clk_prepare_enable(clk[emi_slow_gate]); /* eim */
         clk_prepare_enable(clk[tmax1]);
         clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */
         clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */
@@ -336,7 +347,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
         clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
         clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
         clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
         clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
         clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index e1a17ac7b3b..4233d9e3531 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -147,12 +147,12 @@ enum mx6q_clks {
         esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
         hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
         ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
-        mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4,
+        mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
         gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
         ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
         usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
         pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
-        ssi2_ipg, ssi3_ipg, rom,
+        ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
         clk_max
 };
 
@@ -198,6 +198,9 @@ int __init mx6q_clocks_init(void)
         clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x2000,   0x3);
         clk[pll8_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll8_enet",    "osc", base + 0xe0, 0x182000, 0x3);
 
+        clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
+        clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
+
         /*                                name              parent_name        reg       idx */
         clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
         clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
@@ -285,8 +288,10 @@ int __init mx6q_clocks_init(void)
         clk[gpu3d_shader]     = imx_clk_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
         clk[ipu1_podf]        = imx_clk_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
         clk[ipu2_podf]        = imx_clk_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
-        clk[ldb_di0_podf]     = imx_clk_divider("ldb_di0_podf",     "ldb_di0_sel",       base + 0x20, 10, 1);
-        clk[ldb_di1_podf]     = imx_clk_divider("ldb_di1_podf",     "ldb_di1_sel",       base + 0x20, 11, 1);
+        clk[ldb_di0_div_3_5]  = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+        clk[ldb_di0_podf]     = imx_clk_divider("ldb_di0_podf",     "ldb_di0_div_3_5",       base + 0x20, 10, 1);
+        clk[ldb_di1_div_3_5]  = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+        clk[ldb_di1_podf]     = imx_clk_divider("ldb_di1_podf",     "ldb_di1_div_3_5",   base + 0x20, 11, 1);
         clk[ipu1_di0_pre]     = imx_clk_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
         clk[ipu1_di1_pre]     = imx_clk_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
         clk[ipu2_di0_pre]     = imx_clk_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
@@ -318,7 +323,7 @@ int __init mx6q_clocks_init(void)
         clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
 
         /*                                name             parent_name          reg         shift */
-        clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "ahb",               base + 0x68, 4);
+        clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
         clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
         clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
         clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
@@ -357,6 +362,7 @@ int __init mx6q_clocks_init(void)
         clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
         clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
         clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
+        clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
         clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
         clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
         clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
@@ -388,12 +394,21 @@ int __init mx6q_clocks_init(void)
                         pr_err("i.MX6q clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
-        clk_register_clkdev(clk[mmdc_ch0_axi], NULL, "mmdc_ch0_axi");
-        clk_register_clkdev(clk[mmdc_ch1_axi], NULL, "mmdc_ch1_axi");
         clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
         clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
         clk_register_clkdev(clk[twd], NULL, "smp_twd");
-        clk_register_clkdev(clk[usboh3], NULL, "usboh3");
+        clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
+        clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
+        clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
+        clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
+        clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
+        clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
+        clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
+        clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
+        clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
+        clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
+        clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
+        clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
         clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
         clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
         clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 2628e0c474d..93ece55f75d 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -14,7 +14,7 @@ extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
         imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
 
 extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data;
-#define imx21_add_imx2_wdt(pdata)       \
+#define imx21_add_imx2_wdt()    \
         imx_add_imx2_wdt(&imx21_imx2_wdt_data)
 
 extern const struct imx_imx_fb_data imx21_imx_fb_data;
@@ -50,7 +50,7 @@ extern const struct imx_mxc_nand_data imx21_mxc_nand_data;
         imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
 
 extern const struct imx_mxc_w1_data imx21_mxc_w1_data;
-#define imx21_add_mxc_w1(pdata) \
+#define imx21_add_mxc_w1()      \
         imx_add_mxc_w1(&imx21_mxc_w1_data)
 
 extern const struct imx_spi_imx_data imx21_cspi_data[];
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index efa0761c508..f8e03dd1f11 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -24,11 +24,11 @@ extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
         imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
 
 extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
-#define imx25_add_imxdi_rtc(pdata)      \
+#define imx25_add_imxdi_rtc()   \
         imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
 
 extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
-#define imx25_add_imx2_wdt(pdata)       \
+#define imx25_add_imx2_wdt()    \
         imx_add_imx2_wdt(&imx25_imx2_wdt_data)
 
 extern const struct imx_imx_fb_data imx25_imx_fb_data;
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 28537a5d904..436c5720fe6 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -18,7 +18,7 @@ extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
         imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
 
 extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
-#define imx27_add_imx2_wdt(pdata)       \
+#define imx27_add_imx2_wdt()    \
         imx_add_imx2_wdt(&imx27_imx2_wdt_data)
 
 extern const struct imx_imx_fb_data imx27_imx_fb_data;
@@ -50,7 +50,7 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
 extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
 #define imx27_add_mx2_camera(pdata)     \
         imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
-#define imx27_add_mx2_emmaprp(pdata)    \
+#define imx27_add_mx2_emmaprp() \
         imx_add_mx2_emmaprp(&imx27_mx2_camera_data)
 
 extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
@@ -69,7 +69,7 @@ extern const struct imx_mxc_nand_data imx27_mxc_nand_data;
         imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
 
 extern const struct imx_mxc_w1_data imx27_mxc_w1_data;
-#define imx27_add_mxc_w1(pdata) \
+#define imx27_add_mxc_w1()      \
         imx_add_mxc_w1(&imx27_mxc_w1_data)
 
 extern const struct imx_spi_imx_data imx27_cspi_data[];
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
index 488e241a6db..8b2ceb45bb8 100644
--- a/arch/arm/mach-imx/devices-imx31.h
+++ b/arch/arm/mach-imx/devices-imx31.h
@@ -14,7 +14,7 @@ extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
         imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
 
 extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data;
-#define imx31_add_imx2_wdt(pdata)       \
+#define imx31_add_imx2_wdt()       \
         imx_add_imx2_wdt(&imx31_imx2_wdt_data)
 
 extern const struct imx_imx_i2c_data imx31_imx_i2c_data[];
@@ -42,8 +42,8 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
 #define imx31_add_imx_uart4(pdata)      imx31_add_imx_uart(4, pdata)
 
 extern const struct imx_ipu_core_data imx31_ipu_core_data;
-#define imx31_add_ipu_core(pdata)       \
-        imx_add_ipu_core(&imx31_ipu_core_data, pdata)
+#define imx31_add_ipu_core()            \
+        imx_add_ipu_core(&imx31_ipu_core_data)
 #define imx31_alloc_mx3_camera(pdata)   \
         imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
 #define imx31_add_mx3_sdc_fb(pdata)     \
@@ -65,11 +65,11 @@ extern const struct imx_mxc_nand_data imx31_mxc_nand_data;
         imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
 
 extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data;
-#define imx31_add_mxc_rtc(pdata)        \
+#define imx31_add_mxc_rtc()     \
         imx_add_mxc_rtc(&imx31_mxc_rtc_data)
 
 extern const struct imx_mxc_w1_data imx31_mxc_w1_data;
-#define imx31_add_mxc_w1(pdata) \
+#define imx31_add_mxc_w1()      \
         imx_add_mxc_w1(&imx31_mxc_w1_data)
 
 extern const struct imx_spi_imx_data imx31_cspi_data[];
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
index 7b99ef0bb50..c3e9f206ac2 100644
--- a/arch/arm/mach-imx/devices-imx35.h
+++ b/arch/arm/mach-imx/devices-imx35.h
@@ -24,7 +24,7 @@ extern const struct imx_flexcan_data imx35_flexcan_data[];
 #define imx35_add_flexcan1(pdata)       imx35_add_flexcan(1, pdata)
 
 extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
-#define imx35_add_imx2_wdt(pdata)       \
+#define imx35_add_imx2_wdt()       \
         imx_add_imx2_wdt(&imx35_imx2_wdt_data)
 
 extern const struct imx_imx_i2c_data imx35_imx_i2c_data[];
@@ -50,8 +50,8 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
 #define imx35_add_imx_uart2(pdata)      imx35_add_imx_uart(2, pdata)
 
 extern const struct imx_ipu_core_data imx35_ipu_core_data;
-#define imx35_add_ipu_core(pdata)       \
-        imx_add_ipu_core(&imx35_ipu_core_data, pdata)
+#define imx35_add_ipu_core()            \
+        imx_add_ipu_core(&imx35_ipu_core_data)
 #define imx35_alloc_mx3_camera(pdata)   \
         imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
 #define imx35_add_mx3_sdc_fb(pdata)     \
@@ -68,8 +68,12 @@ extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
 #define imx35_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
 
+extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data;
+#define imx35_add_mxc_rtc()     \
+        imx_add_mxc_rtc(&imx35_mxc_rtc_data)
+
 extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
-#define imx35_add_mxc_w1(pdata) \
+#define imx35_add_mxc_w1()      \
         imx_add_mxc_w1(&imx35_mxc_w1_data)
 
 extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[];
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
index af488bc0e22..9f171872519 100644
--- a/arch/arm/mach-imx/devices-imx51.h
+++ b/arch/arm/mach-imx/devices-imx51.h
@@ -55,7 +55,7 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[];
         imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
 
 extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
-#define imx51_add_imx2_wdt(id, pdata)   \
+#define imx51_add_imx2_wdt(id)  \
         imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
 
 extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h
index 6e1e5d1f8c3..77e0db96c44 100644
--- a/arch/arm/mach-imx/devices-imx53.h
+++ b/arch/arm/mach-imx/devices-imx53.h
@@ -30,7 +30,7 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[];
         imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
 
 extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
-#define imx53_add_imx2_wdt(id, pdata)   \
+#define imx53_add_imx2_wdt(id)  \
         imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
 
 extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 865daf0b09e..05bb41d9972 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -24,14 +24,18 @@
 #define MX25_OTG_SIC_SHIFT      29
 #define MX25_OTG_SIC_MASK       (0x3 << MX25_OTG_SIC_SHIFT)
 #define MX25_OTG_PM_BIT         (1 << 24)
+#define MX25_OTG_PP_BIT         (1 << 11)
+#define MX25_OTG_OCPOL_BIT      (1 << 3)
 
 #define MX25_H1_SIC_SHIFT       21
 #define MX25_H1_SIC_MASK        (0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT          (1 << 18)
 #define MX25_H1_PM_BIT          (1 << 8)
 #define MX25_H1_IPPUE_UP_BIT    (1 << 7)
 #define MX25_H1_IPPUE_DOWN_BIT  (1 << 6)
 #define MX25_H1_TLL_BIT         (1 << 5)
 #define MX25_H1_USBTE_BIT       (1 << 4)
+#define MX25_H1_OCPOL_BIT       (1 << 2)
 
 int mx25_initialize_usb_hw(int port, unsigned int flags)
 {
@@ -41,21 +45,35 @@ int mx25_initialize_usb_hw(int port, unsigned int flags)
 
         switch (port) {
         case 0: /* OTG port */
-                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT);
+                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
+                        MX25_OTG_OCPOL_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX25_OTG_PM_BIT;
 
+                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                        v |= MX25_OTG_PP_BIT;
+
+                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+                        v |= MX25_OTG_OCPOL_BIT;
+
                 break;
         case 1: /* H1 port */
-                v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT |
-                        MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
+                v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
+                        MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
+                        MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX25_H1_PM_BIT;
 
+                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                        v |= MX25_H1_PP_BIT;
+
+                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+                        v |= MX25_H1_OCPOL_BIT;
+
                 if (!(flags & MXC_EHCI_TTL_ENABLED))
                         v |= MX25_H1_TLL_BIT;
 
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 001ec3971f5..73574c30cf5 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -24,14 +24,18 @@
 #define MX35_OTG_SIC_SHIFT      29
 #define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
 #define MX35_OTG_PM_BIT         (1 << 24)
+#define MX35_OTG_PP_BIT         (1 << 11)
+#define MX35_OTG_OCPOL_BIT      (1 << 3)
 
 #define MX35_H1_SIC_SHIFT       21
 #define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PP_BIT          (1 << 18)
 #define MX35_H1_PM_BIT          (1 << 8)
 #define MX35_H1_IPPUE_UP_BIT    (1 << 7)
 #define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
 #define MX35_H1_TLL_BIT         (1 << 5)
 #define MX35_H1_USBTE_BIT       (1 << 4)
+#define MX35_H1_OCPOL_BIT       (1 << 2)
 
 int mx35_initialize_usb_hw(int port, unsigned int flags)
 {
@@ -41,21 +45,35 @@ int mx35_initialize_usb_hw(int port, unsigned int flags)
 
         switch (port) {
         case 0: /* OTG port */
-                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
+                        MX35_OTG_OCPOL_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX35_OTG_PM_BIT;
 
+                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                        v |= MX35_OTG_PP_BIT;
+
+                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+                        v |= MX35_OTG_OCPOL_BIT;
+
                 break;
         case 1: /* H1 port */
-                v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
-                        MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+                v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
+                        MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
+                        MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX35_H1_PM_BIT;
 
+                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                        v |= MX35_H1_PP_BIT;
+
+                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+                        v |= MX35_H1_OCPOL_BIT;
+
                 if (!(flags & MXC_EHCI_TTL_ENABLED))
                         v |= MX35_H1_TLL_BIT;
 
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
index c17fa131728..a6a4afb0ad6 100644
--- a/arch/arm/mach-imx/ehci-imx5.c
+++ b/arch/arm/mach-imx/ehci-imx5.c
@@ -28,11 +28,14 @@
 #define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
 #define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
 #define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)               /* HOST1 power mask */
+#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)       /* HOST1 power mask */
 
 /* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_POL_BIT      (1 << 9)        /* OTG Polarity of Overcurrent */
 #define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_POL_BIT               (1 << 6)        /* UH1 Polarity of Overcurrent */
 #define MXC_H1_OC_DIS_BIT               (1 << 5)        /* UH1 Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT     (1 << 3)        /* OTG Power Pin Polarity */
 
 /* USBH2CTRL */
 #define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
@@ -80,13 +83,21 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
                 if (flags & MXC_EHCI_INTERNAL_PHY) {
                         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 
+                        if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+                                v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
+                        else
+                                v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
                         if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
-                                /* OC/USBPWR is not used */
-                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                        } else {
                                 /* OC/USBPWR is used */
                                 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                        } else {
+                                /* OC/USBPWR is not used */
+                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
                         }
+                        if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                                v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
+                        else
+                                v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
                         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 
                         v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
@@ -95,9 +106,9 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
                         else
                                 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
                         if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v |= MXC_OTG_UCTRL_OPM_BIT;
-                        else
                                 v &= ~MXC_OTG_UCTRL_OPM_BIT;
+                        else
+                                v |= MXC_OTG_UCTRL_OPM_BIT;
                         __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
                 }
                 break;
@@ -113,12 +124,16 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
                 }
 
                 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
                 else
                         v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
                 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
                 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+                if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+                        v |= MXC_H1_OC_POL_BIT;
+                else
+                        v &= ~MXC_H1_OC_POL_BIT;
                 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
                         v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
                 else
@@ -142,7 +157,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
                 }
 
                 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
                 else
                         v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
                 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index b46cab0ced5..fd3177f9e79 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -266,7 +266,7 @@ static struct spi_board_info __maybe_unused
                 .bus_num        = 0,
                 .chip_select    = 0,
                 .max_speed_hz   = 1500000,
-                .irq            = IRQ_GPIOD(25),
+                /* irq number is run-time assigned */
                 .platform_data  = &ads7846_config,
                 .mode           = SPI_MODE_2,
         },
@@ -329,6 +329,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
         /* SPI_CS0 init */
         mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
         imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
+        eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(4, 25));
         spi_register_board_info(eukrea_mbimx27_spi_board_info,
                         ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
 
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 557f6c48605..6e9dd12a696 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -95,10 +95,6 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
-        .irq_base = MXC_IPU_IRQ_START,
-};
-
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "CMO-QVGA",
         .mode           = fb_modedb,
@@ -287,7 +283,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
                 printk(KERN_ERR "error setting mbimxsd pads !\n");
 
         imx35_add_imx_uart1(&uart_pdata);
-        imx35_add_ipu_core(&mx3_ipu_data);
+        imx35_add_ipu_core();
         imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 
         imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/headsmp.S
index 7e49deb128a..7e49deb128a 100644
--- a/arch/arm/mach-imx/head-v7.S
+++ b/arch/arm/mach-imx/headsmp.S
diff --git a/arch/arm/mach-imx/hotplug.c b/arch/arm/mach-imx/hotplug.c
index 20ed2d56c1a..f8f7437c83b 100644
--- a/arch/arm/mach-imx/hotplug.c
+++ b/arch/arm/mach-imx/hotplug.c
@@ -42,22 +42,6 @@ static inline void cpu_enter_lowpower(void)
           : "cc");
 }
 
-static inline void cpu_leave_lowpower(void)
-{
-        unsigned int v;
-
-        asm volatile(
-                "mrc    p15, 0, %0, c1, c0, 0\n"
-        "       orr     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       orr     %0, %0, %2\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-          : "=&r" (v)
-          : "Ir" (CR_C), "Ir" (0x40)
-          : "cc");
-}
-
 /*
  * platform-specific code to shutdown a CPU
  *
@@ -67,11 +51,10 @@ void platform_cpu_die(unsigned int cpu)
 {
         cpu_enter_lowpower();
         imx_enable_cpu(cpu, false);
-        cpu_do_idle();
-        cpu_leave_lowpower();
 
-        /* We should never return from idle */
-        panic("cpu %d unexpectedly exit from shutdown\n", cpu);
+        /* spin here until hardware takes it down */
+        while (1)
+                ;
 }
 
 int platform_cpu_disable(unsigned int cpu)
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index eee0cc8d92a..e80d5235dac 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -10,7 +10,6 @@
  */
 
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
@@ -33,35 +32,8 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
         { /* sentinel */ }
 };
 
-static int __init imx27_avic_add_irq_domain(struct device_node *np,
-                                struct device_node *interrupt_parent)
-{
-        irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
-        return 0;
-}
-
-static int __init imx27_gpio_add_irq_domain(struct device_node *np,
-                                struct device_node *interrupt_parent)
-{
-        static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
-        gpio_irq_base -= 32;
-        irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
-                                NULL);
-
-        return 0;
-}
-
-static const struct of_device_id imx27_irq_match[] __initconst = {
-        { .compatible = "fsl,imx27-avic", .data = imx27_avic_add_irq_domain, },
-        { .compatible = "fsl,imx27-gpio", .data = imx27_gpio_add_irq_domain, },
-        { /* sentinel */ }
-};
-
 static void __init imx27_dt_init(void)
 {
-        of_irq_init(imx27_irq_match);
-
         of_platform_populate(NULL, of_default_bus_match_table,
                              imx27_auxdata_lookup, NULL);
 }
@@ -75,7 +47,7 @@ static struct sys_timer imx27_timer = {
         .init = imx27_timer_init,
 };
 
-static const char *imx27_dt_board_compat[] __initdata = {
+static const char * const imx27_dt_board_compat[] __initconst = {
         "fsl,imx27",
         NULL
 };
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
new file mode 100644
index 00000000000..a68ba207b2b
--- /dev/null
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx31.h>
+
+static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
+                        "imx21-uart.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR,
+                        "imx21-uart.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR,
+                        "imx21-uart.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR,
+                        "imx21-uart.3", NULL),
+        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR,
+                        "imx21-uart.4", NULL),
+        { /* sentinel */ }
+};
+
+static void __init imx31_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             imx31_auxdata_lookup, NULL);
+}
+
+static void __init imx31_timer_init(void)
+{
+        mx31_clocks_init_dt();
+}
+
+static struct sys_timer imx31_timer = {
+        .init = imx31_timer_init,
+};
+
+static const char *imx31_dt_board_compat[] __initdata = {
+        "fsl,imx31",
+        NULL
+};
+
+DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
+        .map_io         = mx31_map_io,
+        .init_early     = imx31_init_early,
+        .init_irq       = mx31_init_irq,
+        .handle_irq     = imx31_handle_irq,
+        .timer          = &imx31_timer,
+        .init_machine   = imx31_dt_init,
+        .dt_compat      = imx31_dt_board_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 18e78dba429..d4067fe3635 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -11,7 +11,6 @@
  */
 
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/pinctrl/machine.h>
@@ -45,30 +44,6 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
         { /* sentinel */ }
 };
 
-static int __init imx51_tzic_add_irq_domain(struct device_node *np,
-                                struct device_node *interrupt_parent)
-{
-        irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
-        return 0;
-}
-
-static int __init imx51_gpio_add_irq_domain(struct device_node *np,
-                                struct device_node *interrupt_parent)
-{
-        static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
-        gpio_irq_base -= 32;
-        irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
-
-        return 0;
-}
-
-static const struct of_device_id imx51_irq_match[] __initconst = {
-        { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
-        { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
-        { /* sentinel */ }
-};
-
 static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
         { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
         { /* sentinel */ }
@@ -80,8 +55,6 @@ static void __init imx51_dt_init(void)
         const struct of_device_id *of_id;
         void (*func)(void);
 
-        of_irq_init(imx51_irq_match);
-
         pinctrl_provide_dummies();
 
         node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index eb04b6248e4..1b7a2fc3659 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -15,7 +15,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/pinctrl/machine.h>
@@ -52,30 +51,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
         { /* sentinel */ }
 };
 
-static int __init imx53_tzic_add_irq_domain(struct device_node *np,
-                                struct device_node *interrupt_parent)
-{
-        irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
-        return 0;
-}
-
-static int __init imx53_gpio_add_irq_domain(struct device_node *np,
-                                struct device_node *interrupt_parent)
-{
-        static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
-        gpio_irq_base -= 32;
-        irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
-
-        return 0;
-}
-
-static const struct of_device_id imx53_irq_match[] __initconst = {
-        { .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
-        { .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
-        { /* sentinel */ }
-};
-
 static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
         { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
         { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
@@ -103,8 +78,6 @@ static void __init imx53_dt_init(void)
         const struct of_device_id *of_id;
         void (*func)(void);
 
-        of_irq_init(imx53_irq_match);
-
         pinctrl_provide_dummies();
 
         node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
@@ -147,6 +120,7 @@ DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
         .handle_irq     = imx53_handle_irq,
         .timer          = &imx53_timer,
         .init_machine   = imx53_dt_init,
+        .init_late      = imx53_init_late,
         .dt_compat      = imx53_dt_board_compat,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index f4a63ee9e21..7b99a79722b 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/dm9000.h>
+#include <linux/gpio.h>
 #include <linux/i2c.h>
 
 #include <asm/mach-types.h>
@@ -26,7 +27,6 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <mach/iomux-mx1.h>
 
 #include "devices-imx1.h"
@@ -87,8 +87,7 @@ static struct resource dm9000_resources[] = {
                 .end    = MX1_CS4_PHYS + 0x00C00003,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = IRQ_GPIOB(14),
-                .end    = IRQ_GPIOB(14),
+                /* irq number is run-time assigned */
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
@@ -129,6 +128,8 @@ static void __init apf9328_init(void)
 
         imx1_add_imx_i2c(&apf9328_i2c_data);
 
+        dm9000_resources[2].start = gpio_to_irq(IMX_GPIO_NR(2, 14));
+        dm9000_resources[2].end = gpio_to_irq(IMX_GPIO_NR(2, 14));
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index c650145d164..2c6ab3273f9 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -367,10 +367,6 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
-        .irq_base = MXC_IPU_IRQ_START,
-};
-
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "CRT-VGA",
         .mode           = fb_modedb,
@@ -408,7 +404,8 @@ static int armadillo5x0_sdhc1_init(struct device *dev,
         gpio_direction_input(gpio_wp);
 
         /* When supported the trigger type have to be BOTH */
-        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq,
+        ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)),
+                          detect_irq,
                           IRQF_DISABLED | IRQF_TRIGGER_FALLING,
                           "sdhc-detect", data);
 
@@ -429,7 +426,7 @@ err_gpio_free:
 
 static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data);
+        free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), data);
         gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK));
         gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
 }
@@ -450,8 +447,7 @@ static struct resource armadillo5x0_smc911x_resources[] = {
                 .end    = MX31_CS3_BASE_ADDR + SZ_32M - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
-                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+                /* irq number is run-time assigned */
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
@@ -498,6 +494,10 @@ static void __init armadillo5x0_init(void)
 
         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+        armadillo5x0_smc911x_resources[1].start =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
+        armadillo5x0_smc911x_resources[1].end =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
         platform_add_devices(devices, ARRAY_SIZE(devices));
         imx_add_gpio_keys(&armadillo5x0_button_data);
         imx31_add_imx_i2c1(NULL);
@@ -513,7 +513,7 @@ static void __init armadillo5x0_init(void)
         imx31_add_mxc_mmc(0, &sdhc_pdata);
 
         /* Register FB */
-        imx31_add_ipu_core(&mx3_ipu_data);
+        imx31_add_ipu_core();
         imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 
         /* Register NOR Flash */
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index d085aea0870..2bb9e18d9ee 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -169,28 +169,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
 static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
-                .irq = IRQ_GPIOB(23),
+                /* irq number is run-time assigned */
                 .uartclk = 14745600,
                 .regshift = 1,
                 .iotype = UPIO_MEM,
                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
         }, {
                 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
-                .irq = IRQ_GPIOB(22),
+                /* irq number is run-time assigned */
                 .uartclk = 14745600,
                 .regshift = 1,
                 .iotype = UPIO_MEM,
                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
         }, {
                 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
-                .irq = IRQ_GPIOB(27),
+                /* irq number is run-time assigned */
                 .uartclk = 14745600,
                 .regshift = 1,
                 .iotype = UPIO_MEM,
                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
         }, {
                 .mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
-                .irq = IRQ_GPIOB(30),
+                /* irq number is run-time assigned */
                 .uartclk = 14745600,
                 .regshift = 1,
                 .iotype = UPIO_MEM,
@@ -233,18 +233,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init eukrea_cpuimx27_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", eukrea_cpuimx27_otg_mode);
 
@@ -266,8 +266,8 @@ static void __init eukrea_cpuimx27_init(void)
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_imx2_wdt(NULL);
-        imx27_add_mxc_w1(NULL);
+        imx27_add_imx2_wdt();
+        imx27_add_mxc_w1();
 
 #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
         /* SDHC2 can be used for Wifi */
@@ -279,6 +279,10 @@ static void __init eukrea_cpuimx27_init(void)
 #endif
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+        serial_platform_data[0].irq = IMX_GPIO_NR(2, 23);
+        serial_platform_data[1].irq = IMX_GPIO_NR(2, 22);
+        serial_platform_data[2].irq = IMX_GPIO_NR(2, 27);
+        serial_platform_data[3].irq = IMX_GPIO_NR(2, 30);
         platform_device_register(&serial_device);
 #endif
 
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 6450303f1a7..d49b0ec6bde 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -71,7 +71,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
         }, {
                 I2C_BOARD_INFO("tsc2007", 0x48),
                 .platform_data  = &tsc2007_info,
-                .irq            = IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
+                /* irq number is run-time assigned */
         },
 };
 
@@ -141,18 +141,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init eukrea_cpuimx35_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", eukrea_cpuimx35_otg_mode);
 
@@ -167,11 +167,12 @@ static void __init eukrea_cpuimx35_init(void)
                         ARRAY_SIZE(eukrea_cpuimx35_pads));
 
         imx35_add_fec(NULL);
-        imx35_add_imx2_wdt(NULL);
+        imx35_add_imx2_wdt();
 
         imx35_add_imx_uart0(&uart_pdata);
         imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
 
+        eukrea_cpuimx35_i2c_devices[1].irq = gpio_to_irq(TSC2007_IRQGPIO);
         i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
                         ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
         imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 1e09de50cbc..b87cc49ab1e 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -217,18 +217,18 @@ static const struct mxc_usbh_platform_data usbh1_config __initconst = {
         .portsc = MXC_EHCI_MODE_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init eukrea_cpuimx51sd_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
 
@@ -258,7 +258,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
                 .mode           = SPI_MODE_0,
                 .chip_select     = 0,
                 .platform_data   = &mcp251x_info,
-                .irq             = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
+                /* irq number is run-time assigned */
         },
 };
 
@@ -292,7 +292,7 @@ static void __init eukrea_cpuimx51sd_init(void)
 
         imx51_add_imx_uart(0, &uart_pdata);
         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
-        imx51_add_imx2_wdt(0, NULL);
+        imx51_add_imx2_wdt(0);
 
         gpio_request(ETH_RST, "eth_rst");
         gpio_set_value(ETH_RST, 1);
@@ -309,6 +309,7 @@ static void __init eukrea_cpuimx51sd_init(void)
         msleep(20);
         gpio_set_value(CAN_RST, 1);
         imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
+        cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
         spi_register_board_info(cpuimx51sd_spi_device,
                                 ARRAY_SIZE(cpuimx51sd_spi_device));
 
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index d1e04e676e3..017bbb70ea4 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -109,18 +109,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init eukrea_cpuimx25_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", eukrea_cpuimx25_otg_mode);
 
@@ -134,9 +134,9 @@ static void __init eukrea_cpuimx25_init(void)
 
         imx25_add_imx_uart0(&uart_pdata);
         imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
-        imx25_add_imxdi_rtc(NULL);
+        imx25_add_imxdi_rtc();
         imx25_add_fec(&mx25_fec_pdata);
-        imx25_add_imx2_wdt(NULL);
+        imx25_add_imx2_wdt();
 
         i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index ba09552fe5f..f264ddddd47 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -40,6 +40,7 @@
 #include <asm/mach/time.h>
 #include <asm/system_info.h>
 #include <mach/common.h>
+#include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
 
 #include "devices-imx27.h"
@@ -47,7 +48,7 @@
 #define TVP5150_RSTN (GPIO_PORTC + 18)
 #define TVP5150_PWDN (GPIO_PORTC + 19)
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
-#define SDHC1_IRQ IRQ_GPIOB(25)
+#define SDHC1_IRQ_GPIO IMX_GPIO_NR(2, 25)
 
 #define MOTHERBOARD_BIT2        (GPIO_PORTD + 31)
 #define MOTHERBOARD_BIT1        (GPIO_PORTD + 30)
@@ -307,14 +308,14 @@ static int visstrim_m10_sdhc1_init(struct device *dev,
 {
         int ret;
 
-        ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING,
-                                "mmc-detect", data);
+        ret = request_irq(gpio_to_irq(SDHC1_IRQ_GPIO), detect_irq,
+                          IRQF_TRIGGER_FALLING, "mmc-detect", data);
         return ret;
 }
 
 static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(SDHC1_IRQ, data);
+        free_irq(gpio_to_irq(SDHC1_IRQ_GPIO), data);
 }
 
 static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index c9d350c5dcc..7381387a890 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -57,7 +57,7 @@ static void __init mx27ipcam_init(void)
 
         imx27_add_imx_uart0(NULL);
         imx27_add_fec(NULL);
-        imx27_add_imx2_wdt(NULL);
+        imx27_add_imx2_wdt();
 }
 
 static void __init mx27ipcam_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index b47e98b7d53..045b3f6a387 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -12,11 +12,12 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/cpuidle.h>
 #include <linux/delay.h>
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
@@ -24,6 +25,8 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
+#include <linux/mfd/anatop.h>
+#include <asm/cpuidle.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
@@ -31,8 +34,10 @@
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
 #include <mach/common.h>
+#include <mach/cpuidle.h>
 #include <mach/hardware.h>
 
+
 void imx6q_restart(char mode, const char *cmd)
 {
         struct device_node *np;
@@ -66,7 +71,7 @@ soft:
 /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
 static int ksz9021rn_phy_fixup(struct phy_device *phydev)
 {
-        if (IS_ENABLED(CONFIG_PHYLIB)) {
+        if (IS_BUILTIN(CONFIG_PHYLIB)) {
                 /* min rx data delay */
                 phy_write(phydev, 0x0b, 0x8105);
                 phy_write(phydev, 0x0c, 0x0000);
@@ -107,12 +112,51 @@ put_clk:
 
 static void __init imx6q_sabrelite_init(void)
 {
-        if (IS_ENABLED(CONFIG_PHYLIB))
+        if (IS_BUILTIN(CONFIG_PHYLIB))
                 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
                                 ksz9021rn_phy_fixup);
         imx6q_sabrelite_cko1_setup();
 }
 
+static void __init imx6q_usb_init(void)
+{
+        struct device_node *np;
+        struct platform_device *pdev = NULL;
+        struct anatop *adata = NULL;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
+        if (np)
+                pdev = of_find_device_by_node(np);
+        if (pdev)
+                adata = platform_get_drvdata(pdev);
+        if (!adata) {
+                if (np)
+                        of_node_put(np);
+                return;
+        }
+
+#define HW_ANADIG_USB1_CHRG_DETECT              0x000001b0
+#define HW_ANADIG_USB2_CHRG_DETECT              0x00000210
+
+#define BM_ANADIG_USB_CHRG_DETECT_EN_B          0x00100000
+#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B    0x00080000
+
+        /*
+         * The external charger detector needs to be disabled,
+         * or the signal at DP will be poor
+         */
+        anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
+                        BM_ANADIG_USB_CHRG_DETECT_EN_B
+                        | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
+                        ~0);
+        anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
+                        BM_ANADIG_USB_CHRG_DETECT_EN_B |
+                        BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
+                        ~0);
+
+        of_node_put(np);
+}
+
 static void __init imx6q_init_machine(void)
 {
         /*
@@ -127,6 +171,20 @@ static void __init imx6q_init_machine(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         imx6q_pm_init();
+        imx6q_usb_init();
+}
+
+static struct cpuidle_driver imx6q_cpuidle_driver = {
+        .name                   = "imx6q_cpuidle",
+        .owner                  = THIS_MODULE,
+        .en_core_tk_irqen       = 1,
+        .states[0]              = ARM_CPUIDLE_WFI_STATE,
+        .state_count            = 1,
+};
+
+static void __init imx6q_init_late(void)
+{
+        imx_cpuidle_init(&imx6q_cpuidle_driver);
 }
 
 static void __init imx6q_map_io(void)
@@ -136,21 +194,8 @@ static void __init imx6q_map_io(void)
         imx6q_clock_map_io();
 }
 
-static int __init imx6q_gpio_add_irq_domain(struct device_node *np,
-                                struct device_node *interrupt_parent)
-{
-        static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
-        gpio_irq_base -= 32;
-        irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
-                              NULL);
-
-        return 0;
-}
-
 static const struct of_device_id imx6q_irq_match[] __initconst = {
         { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        { .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, },
         { /* sentinel */ }
 };
 
@@ -186,6 +231,7 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
         .handle_irq     = imx6q_handle_irq,
         .timer          = &imx6q_timer,
         .init_machine   = imx6q_init_machine,
+        .init_late      = imx6q_init_late,
         .dt_compat      = imx6q_dt_compat,
         .restart        = imx6q_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 15a26e90826..5d08533ab2c 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -73,7 +73,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .membase        = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
                 .mapbase        = KZM_ARM11_16550,
-                .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+                /* irq number is run-time assigned */
                 .irqflags       = IRQ_TYPE_EDGE_RISING,
                 .uartclk        = 14745600,
                 .regshift       = 0,
@@ -91,8 +91,7 @@ static struct resource serial8250_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
-                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+                /* irq number is run-time assigned */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -125,6 +124,13 @@ static int __init kzm_init_ext_uart(void)
         tmp |= 0x2;
         __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
 
+        serial_platform_data[0].irq =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+        serial8250_resources[1].start =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+        serial8250_resources[1].end =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+
         return platform_device_register(&serial_device);
 }
 #else
@@ -152,8 +158,7 @@ static struct resource kzm_smsc9118_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
-                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
+                /* irq number is run-time assigned */
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
         },
 };
@@ -184,6 +189,11 @@ static int __init kzm_init_smsc9118(void)
 
         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+        kzm_smsc9118_resources[1].start =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
+        kzm_smsc9118_resources[1].end =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
+
         return platform_device_register(&kzm_smsc9118_device);
 }
 #else
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 7274e792813..667f359a2e8 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -26,7 +26,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx1.h>
-#include <mach/irqs.h>
 
 #include "devices-imx1.h"
 
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 3e7401fca76..ed22e3fe6ec 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -38,7 +38,7 @@
                 (MX21ADS_MMIO_BASE_ADDR + (offset))
 
 #define MX21ADS_CS8900A_MMIO_SIZE   0x200000
-#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
+#define MX21ADS_CS8900A_IRQ_GPIO    IMX_GPIO_NR(5, 11)
 #define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
 #define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
 #define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
@@ -159,9 +159,10 @@ static struct platform_device mx21ads_nor_mtd_device = {
         .resource = &mx21ads_flash_resource,
 };
 
-static const struct resource mx21ads_cs8900_resources[] __initconst = {
+static struct resource mx21ads_cs8900_resources[] __initdata = {
         DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE),
-        DEFINE_RES_IRQ(MX21ADS_CS8900A_IRQ),
+        /* irq number is run-time assigned */
+        DEFINE_RES_IRQ(-1),
 };
 
 static const struct platform_device_info mx21ads_cs8900_devinfo __initconst = {
@@ -241,13 +242,13 @@ static int mx21ads_sdhc_get_ro(struct device *dev)
 static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
         void *data)
 {
-        return request_irq(IRQ_GPIOD(25), detect_irq,
+        return request_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), detect_irq,
                 IRQF_TRIGGER_FALLING, "mmc-detect", data);
 }
 
 static void mx21ads_sdhc_exit(struct device *dev, void *data)
 {
-        free_irq(IRQ_GPIOD(25), data);
+        free_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), data);
 }
 
 static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
@@ -304,6 +305,11 @@ static void __init mx21ads_board_init(void)
         imx21_add_mxc_nand(&mx21ads_nand_board_info);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+
+        mx21ads_cs8900_resources[1].start =
+                        gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
+        mx21ads_cs8900_resources[1].end =
+                        gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
         platform_device_register_full(&mx21ads_cs8900_devinfo);
 }
 
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index f26734298aa..ce247fd1269 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -237,9 +237,9 @@ static void __init mx25pdk_init(void)
         imx25_add_fsl_usb2_udc(&otg_device_pdata);
         imx25_add_mxc_ehci_hs(&usbh2_pdata);
         imx25_add_mxc_nand(&mx25pdk_nand_board_info);
-        imx25_add_imxdi_rtc(NULL);
+        imx25_add_imxdi_rtc();
         imx25_add_imx_fb(&mx25pdk_fb_pdata);
-        imx25_add_imx2_wdt(NULL);
+        imx25_add_imx2_wdt();
 
         mx25pdk_fec_reset();
         imx25_add_fec(&mx25_fec_pdata);
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index c6d385c5225..58c24c1a7ab 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -40,7 +40,6 @@
 #include <mach/common.h>
 #include <mach/iomux-mx27.h>
 #include <mach/ulpi.h>
-#include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
 
 #include "devices-imx27.h"
@@ -48,7 +47,6 @@
 #define SD1_EN_GPIO             IMX_GPIO_NR(2, 25)
 #define OTG_PHY_RESET_GPIO      IMX_GPIO_NR(2, 23)
 #define SPI2_SS0                IMX_GPIO_NR(4, 21)
-#define EXPIO_PARENT_INT        gpio_to_irq(IMX_GPIO_NR(3, 28))
 #define PMIC_INT                IMX_GPIO_NR(3, 14)
 #define SPI1_SS0                IMX_GPIO_NR(4, 28)
 #define SD1_CD                  IMX_GPIO_NR(2, 26)
@@ -241,18 +239,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init mx27_3ds_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", mx27_3ds_otg_mode);
 
@@ -445,7 +443,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
                 .bus_num        = 1,
                 .chip_select    = 0, /* SS0 */
                 .platform_data  = &mc13783_pdata,
-                .irq = IMX_GPIO_TO_IRQ(PMIC_INT),
+                /* irq number is run-time assigned */
                 .mode = SPI_CS_HIGH,
         }, {
                 .modalias       = "l4f00242t03",
@@ -480,7 +478,7 @@ static void __init mx27pdk_init(void)
         imx27_add_fec(NULL);
         imx27_add_imx_keypad(&mx27_3ds_keymap_data);
         imx27_add_mxc_mmc(0, &sdhc1_pdata);
-        imx27_add_imx2_wdt(NULL);
+        imx27_add_imx2_wdt();
         otg_phy_init();
 
         if (otg_mode_host) {
@@ -496,10 +494,11 @@ static void __init mx27pdk_init(void)
 
         imx27_add_spi_imx1(&spi2_pdata);
         imx27_add_spi_imx0(&spi1_pdata);
+        mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
         spi_register_board_info(mx27_3ds_spi_devs,
                                                 ARRAY_SIZE(mx27_3ds_spi_devs));
 
-        if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+        if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
                 pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
         imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 0228d2e07fe..7dc59bac0e5 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -246,25 +246,25 @@ static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
                               void *data)
 {
-        return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
-                           "sdhc1-card-detect", data);
+        return request_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), detect_irq,
+                           IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
 }
 
 static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
                               void *data)
 {
-        return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
-                           "sdhc2-card-detect", data);
+        return request_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), detect_irq,
+                           IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
 }
 
 static void mx27ads_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(IRQ_GPIOE(21), data);
+        free_irq(gpio_to_irq(IMX_GPIO_NR(5, 21)), data);
 }
 
 static void mx27ads_sdhc2_exit(struct device *dev, void *data)
 {
-        free_irq(IRQ_GPIOB(7), data);
+        free_irq(gpio_to_irq(IMX_GPIO_NR(2, 7)), data);
 }
 
 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
@@ -310,7 +310,7 @@ static void __init mx27ads_board_init(void)
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_mxc_w1(NULL);
+        imx27_add_mxc_w1();
 }
 
 static void __init mx27ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 4eafdf275ea..8915f937b7d 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -44,9 +44,6 @@
 
 #include "devices-imx31.h"
 
-/* CPLD IRQ line for external uart, external ethernet etc */
-#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
-
 static int mx31_3ds_pins[] = {
         /* UART1 */
         MX31_PIN_CTS1__CTS1,
@@ -277,10 +274,6 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
-static struct ipu_platform_data mx3_ipu_data = {
-        .irq_base = MXC_IPU_IRQ_START,
-};
-
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "Epson-VGA",
         .mode           = fb_modedb,
@@ -317,7 +310,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
                 return ret;
         }
 
-        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+        ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
                           detect_irq, IRQF_DISABLED |
                           IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
                           "sdhc1-detect", data);
@@ -336,7 +329,7 @@ gpio_free:
 
 static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
+        free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data);
         gpio_free_array(mx31_3ds_sdhc1_gpios,
                          ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
 }
@@ -539,7 +532,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
                 .bus_num        = 1,
                 .chip_select    = 1, /* SS2 */
                 .platform_data  = &mc13783_pdata,
-                .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+                /* irq number is run-time assigned */
                 .mode = SPI_CS_HIGH,
         }, {
                 .modalias       = "l4f00242t03",
@@ -671,18 +664,18 @@ static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init mx31_3ds_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", mx31_3ds_otg_mode);
 
@@ -714,6 +707,7 @@ static void __init mx31_3ds_init(void)
         imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
         imx31_add_spi_imx1(&spi1_pdata);
+        mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
         spi_register_board_info(mx31_3ds_spi_devs,
                                                 ARRAY_SIZE(mx31_3ds_spi_devs));
 
@@ -736,15 +730,15 @@ static void __init mx31_3ds_init(void)
         if (!otg_mode_host)
                 imx31_add_fsl_usb2_udc(&usbotg_pdata);
 
-        if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+        if (mxc_expio_init(MX31_CS5_BASE_ADDR, IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)))
                 printk(KERN_WARNING "Init of the debug board failed, all "
                                     "devices on the debug board are unusable.\n");
-        imx31_add_imx2_wdt(NULL);
+        imx31_add_imx2_wdt();
         imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
         imx31_add_mxc_mmc(0, &sdhc1_pdata);
 
         imx31_add_spi_imx0(&spi0_pdata);
-        imx31_add_ipu_core(&mx3_ipu_data);
+        imx31_add_ipu_core();
         imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 
         /* CSI */
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 4518e544822..d37f4809c55 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -21,6 +21,7 @@
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -62,20 +63,18 @@
 #define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
 #define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
 #define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
-#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
 
-#define MXC_EXP_IO_BASE         MXC_BOARD_IRQ_START
-#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_XUART_INTA    10
+#define EXPIO_INT_XUART_INTB    11
 
 #define MXC_MAX_EXP_IO_LINES    16
 
 /* CS8900 */
-#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_ENET_INT      8
 #define CS4_CS8900_MMIO_START   0x20000
 
+static struct irq_domain *domain;
+
 /*
  * The serial port definition structure.
  */
@@ -83,7 +82,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
         {
                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
-                .irq      = EXPIO_INT_XUART_INTA,
                 .uartclk  = 14745600,
                 .regshift = 0,
                 .iotype   = UPIO_MEM,
@@ -91,7 +89,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
         }, {
                 .membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
                 .mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
-                .irq      = EXPIO_INT_XUART_INTB,
                 .uartclk  = 14745600,
                 .regshift = 0,
                 .iotype   = UPIO_MEM,
@@ -108,9 +105,9 @@ static struct platform_device serial_device = {
         },
 };
 
-static const struct resource mx31ads_cs8900_resources[] __initconst = {
+static struct resource mx31ads_cs8900_resources[] __initdata = {
         DEFINE_RES_MEM(MX31_CS4_BASE_ADDR + CS4_CS8900_MMIO_START, SZ_64K),
-        DEFINE_RES_IRQ(EXPIO_INT_ENET_INT),
+        DEFINE_RES_IRQ(-1),
 };
 
 static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
@@ -122,11 +119,19 @@ static const struct platform_device_info mx31ads_cs8900_devinfo __initconst = {
 
 static int __init mxc_init_extuart(void)
 {
+        serial_platform_data[0].irq = irq_find_mapping(domain,
+                                                       EXPIO_INT_XUART_INTA);
+        serial_platform_data[1].irq = irq_find_mapping(domain,
+                                                       EXPIO_INT_XUART_INTB);
         return platform_device_register(&serial_device);
 }
 
 static void __init mxc_init_ext_ethernet(void)
 {
+        mx31ads_cs8900_resources[1].start =
+                        irq_find_mapping(domain, EXPIO_INT_ENET_INT);
+        mx31ads_cs8900_resources[1].end =
+                        irq_find_mapping(domain, EXPIO_INT_ENET_INT);
         platform_device_register_full(
                 (struct platform_device_info *)&mx31ads_cs8900_devinfo);
 }
@@ -157,12 +162,12 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
         imr_val = __raw_readw(PBC_INTMASK_SET_REG);
         int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
 
-        expio_irq = MXC_EXP_IO_BASE;
+        expio_irq = 0;
         for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
                 if ((int_valid & 1) == 0)
                         continue;
 
-                generic_handle_irq(expio_irq);
+                generic_handle_irq(irq_find_mapping(domain, expio_irq));
         }
 }
 
@@ -172,7 +177,7 @@ static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
  */
 static void expio_mask_irq(struct irq_data *d)
 {
-        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+        u32 expio = d->hwirq;
         /* mask the interrupt */
         __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
         __raw_readw(PBC_INTMASK_CLEAR_REG);
@@ -184,7 +189,7 @@ static void expio_mask_irq(struct irq_data *d)
  */
 static void expio_ack_irq(struct irq_data *d)
 {
-        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+        u32 expio = d->hwirq;
         /* clear the interrupt status */
         __raw_writew(1 << expio, PBC_INTSTATUS_REG);
 }
@@ -195,7 +200,7 @@ static void expio_ack_irq(struct irq_data *d)
  */
 static void expio_unmask_irq(struct irq_data *d)
 {
-        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+        u32 expio = d->hwirq;
         /* unmask the interrupt */
         __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
 }
@@ -209,7 +214,8 @@ static struct irq_chip expio_irq_chip = {
 
 static void __init mx31ads_init_expio(void)
 {
-        int i;
+        int irq_base;
+        int i, irq;
 
         printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
 
@@ -221,13 +227,21 @@ static void __init mx31ads_init_expio(void)
         /* disable the interrupt and clear the status */
         __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
         __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
-        for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
-             i++) {
+
+        irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
+        WARN_ON(irq_base < 0);
+
+        domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
+                                       &irq_domain_simple_ops, NULL);
+        WARN_ON(!domain);
+
+        for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
                 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
-        irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
-        irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
+        irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
+        irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+        irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
 }
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -479,7 +493,6 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
 
 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
         .init = mx31_wm8350_init,
-        .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
 };
 #endif
 
@@ -488,13 +501,17 @@ static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
         {
                 I2C_BOARD_INFO("wm8350", 0x1a),
                 .platform_data = &mx31_wm8350_pdata,
-                .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+                /* irq number is run-time assigned */
         },
 #endif
 };
 
 static void __init mxc_init_i2c(void)
 {
+#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
+        mx31ads_i2c1_devices[0].irq =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
+#endif
         i2c_register_board_info(1, mx31ads_i2c1_devices,
                                 ARRAY_SIZE(mx31ads_i2c1_devices));
 
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 83714b0cc29..34b9bf075da 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -65,8 +65,7 @@ static struct resource smsc91x_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .start  = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
-                .end    = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+                /* irq number is run-time assigned */
                 .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
         }
 };
@@ -233,7 +232,7 @@ static struct spi_board_info mc13783_dev __initdata = {
         .bus_num        = 1,
         .chip_select    = 0,
         .platform_data  = &mc13783_pdata,
-        .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+        /* irq number is run-time assigned */
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -285,10 +284,15 @@ static void __init mx31lilly_board_init(void)
 
         imx31_add_spi_imx0(&spi0_pdata);
         imx31_add_spi_imx1(&spi1_pdata);
+        mc13783_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
         spi_register_board_info(&mc13783_dev, 1);
 
         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
 
+        smsc91x_resources[1].start =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
+        smsc91x_resources[1].end =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         /* USB */
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 686c6058798..c8785b39eae 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -43,7 +43,6 @@
 #include <mach/common.h>
 #include <mach/board-mx31lite.h>
 #include <mach/iomux-mx3.h>
-#include <mach/irqs.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx31.h"
@@ -83,8 +82,7 @@ static struct resource smsc911x_resources[] = {
                 .end            = MX31_CS4_BASE_ADDR + 0x100,
                 .flags          = IORESOURCE_MEM,
         }, {
-                .start          = IOMUX_TO_IRQ(MX31_PIN_SFS6),
-                .end            = IOMUX_TO_IRQ(MX31_PIN_SFS6),
+                /* irq number is run-time assigned */
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -124,7 +122,7 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
         .bus_num        = 1,
         .chip_select    = 0,
         .platform_data  = &mc13783_pdata,
-        .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+        /* irq number is run-time assigned */
 };
 
 /*
@@ -258,6 +256,7 @@ static void __init mx31lite_init(void)
         imx31_add_mxc_nand(&mx31lite_nand_board_info);
 
         imx31_add_spi_imx1(&spi1_pdata);
+        mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
         spi_register_board_info(&mc13783_spi_dev, 1);
 
         /* USB */
@@ -274,6 +273,10 @@ static void __init mx31lite_init(void)
                 pr_warning("could not get LAN irq gpio\n");
         else {
                 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
+                smsc911x_resources[1].start =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
+                smsc911x_resources[1].end =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
                 platform_device_register(&smsc911x_device);
         }
 }
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 016791f038b..d46290b288e 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -303,7 +303,7 @@ static struct imx_ssi_platform_data moboard_ssi_pdata = {
 static struct spi_board_info moboard_spi_board_info[] __initdata = {
         {
                 .modalias = "mc13783",
-                .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+                /* irq number is run-time assigned */
                 .max_speed_hz = 300000,
                 .bus_num = 1,
                 .chip_select = 0,
@@ -473,10 +473,6 @@ static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = {
         .leds           = mx31moboard_leds,
 };
 
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
-        .irq_base = MXC_IPU_IRQ_START,
-};
-
 static struct platform_device *devices[] __initdata = {
         &mx31moboard_flash,
 };
@@ -494,7 +490,7 @@ static int __init mx31moboard_init_cam(void)
         int dma, ret = -ENOMEM;
         struct platform_device *pdev;
 
-        imx31_add_ipu_core(&mx3_ipu_data);
+        imx31_add_ipu_core();
 
         pdev = imx31_alloc_mx3_camera(&camera_pdata);
         if (IS_ERR(pdev))
@@ -544,7 +540,7 @@ static void __init mx31moboard_init(void)
         platform_add_devices(devices, ARRAY_SIZE(devices));
         gpio_led_register_device(-1, &mx31moboard_led_pdata);
 
-        imx31_add_imx2_wdt(NULL);
+        imx31_add_imx2_wdt();
 
         imx31_add_imx_uart0(&uart0_pdata);
         imx31_add_imx_uart4(&uart4_pdata);
@@ -557,6 +553,8 @@ static void __init mx31moboard_init(void)
 
         gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
         gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
+        moboard_spi_board_info[0].irq =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
         spi_register_board_info(moboard_spi_board_info,
                 ARRAY_SIZE(moboard_spi_board_info));
 
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 28aa19476de..504983c68aa 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -46,7 +46,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
-#include <mach/irqs.h>
 #include <mach/3ds_debugboard.h>
 #include <video/platform_lcd.h>
 
@@ -80,10 +79,6 @@ static const struct fb_videomode fb_modedb[] = {
          },
 };
 
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
-        .irq_base = MXC_IPU_IRQ_START,
-};
-
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name = "Ceramate-CLAA070VC01",
         .mode = fb_modedb,
@@ -136,8 +131,6 @@ static struct platform_device mx35_3ds_lcd = {
         .dev.platform_data = &mx35_3ds_lcd_data,
 };
 
-#define EXPIO_PARENT_INT        gpio_to_irq(IMX_GPIO_NR(1, 1))
-
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -297,10 +290,6 @@ err:
         return ret;
 }
 
-static const struct ipu_platform_data mx35_3ds_ipu_data __initconst = {
-        .irq_base = MXC_IPU_IRQ_START,
-};
-
 static struct i2c_board_info mx35_3ds_i2c_camera = {
         I2C_BOARD_INFO("ov2640", 0x30),
 };
@@ -492,7 +481,7 @@ static struct i2c_board_info mx35_3ds_i2c_mc13892 = {
 
         I2C_BOARD_INFO("mc13892", 0x08),
         .platform_data = &mx35_3ds_mc13892_data,
-        .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
+        /* irq number is run-time assigned */
 };
 
 static void __init imx35_3ds_init_mc13892(void)
@@ -504,6 +493,7 @@ static void __init imx35_3ds_init_mc13892(void)
                 return;
         }
 
+        mx35_3ds_i2c_mc13892.irq = gpio_to_irq(GPIO_PMIC_INT);
         i2c_register_board_info(0, &mx35_3ds_i2c_mc13892, 1);
 }
 
@@ -540,18 +530,18 @@ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
         .portsc         = MXC_EHCI_MODE_SERIAL,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init mx35_3ds_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", mx35_3ds_otg_mode);
 
@@ -571,7 +561,8 @@ static void __init mx35_3ds_init(void)
         mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
 
         imx35_add_fec(NULL);
-        imx35_add_imx2_wdt(NULL);
+        imx35_add_imx2_wdt();
+        imx35_add_mxc_rtc();
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx35_add_imx_uart0(&uart_pdata);
@@ -587,7 +578,7 @@ static void __init mx35_3ds_init(void)
         imx35_add_mxc_nand(&mx35pdk_nand_board_info);
         imx35_add_sdhci_esdhc_imx(0, NULL);
 
-        if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+        if (mxc_expio_init(MX35_CS5_BASE_ADDR, IMX_GPIO_NR(1, 1)))
                 pr_warn("Init of the debugboard failed, all "
                                 "devices on the debugboard are unusable.\n");
         imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
@@ -595,7 +586,7 @@ static void __init mx35_3ds_init(void)
         i2c_register_board_info(
                 0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
 
-        imx35_add_ipu_core(&mx35_3ds_ipu_data);
+        imx35_add_ipu_core();
         platform_device_register(&mx35_3ds_ov2640);
         imx35_3ds_init_camera();
 
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
index 3c5b163923f..9ee84a4af63 100644
--- a/arch/arm/mach-imx/mach-mx51_3ds.c
+++ b/arch/arm/mach-imx/mach-mx51_3ds.c
@@ -26,7 +26,6 @@
 
 #include "devices-imx51.h"
 
-#define EXPIO_PARENT_INT        gpio_to_irq(IMX_GPIO_NR(1, 6))
 #define MX51_3DS_ECSPI2_CS      (GPIO_PORTC + 28)
 
 static iomux_v3_cfg_t mx51_3ds_pads[] = {
@@ -148,13 +147,13 @@ static void __init mx51_3ds_init(void)
         spi_register_board_info(mx51_3ds_spi_nor_device,
                                 ARRAY_SIZE(mx51_3ds_spi_nor_device));
 
-        if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+        if (mxc_expio_init(MX51_CS5_BASE_ADDR, IMX_GPIO_NR(1, 6)))
                 printk(KERN_WARNING "Init of the debugboard failed, all "
                                     "devices on the board are unusable.\n");
 
         imx51_add_sdhci_esdhc_imx(0, NULL);
         imx51_add_imx_keypad(&mx51_3ds_map_data);
-        imx51_add_imx2_wdt(0, NULL);
+        imx51_add_imx2_wdt(0);
 }
 
 static void __init mx51_3ds_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index dde397014d4..7b31cbde877 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -307,18 +307,18 @@ static const struct mxc_usbh_platform_data usbh1_config __initconst = {
         .portsc = MXC_EHCI_MODE_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init babbage_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", babbage_otg_mode);
 
@@ -411,7 +411,7 @@ static void __init mx51_babbage_init(void)
         spi_register_board_info(mx51_babbage_spi_board_info,
                 ARRAY_SIZE(mx51_babbage_spi_board_info));
         imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
-        imx51_add_imx2_wdt(0, NULL);
+        imx51_add_imx2_wdt(0);
 }
 
 static void __init mx51_babbage_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
index 05641980dc5..6c28e65f424 100644
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ b/arch/arm/mach-imx/mach-mx53_ard.c
@@ -135,8 +135,7 @@ static struct resource ard_smsc911x_resources[] = {
                 .flags = IORESOURCE_MEM,
         },
         {
-                .start =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
-                .end =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
+                /* irq number is run-time assigned */
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -240,10 +239,12 @@ static void __init mx53_ard_board_init(void)
         imx53_ard_common_init();
         mx53_ard_io_init();
         regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+        ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
+        ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
-        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx2_wdt(0);
         imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
         imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
         imx_add_gpio_keys(&ard_button_data);
@@ -266,5 +267,6 @@ MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
         .handle_irq = imx53_handle_irq,
         .timer = &mx53_ard_timer,
         .init_machine = mx53_ard_board_init,
+        .init_late      = imx53_init_late,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
index 5a72188b9cd..09fe2197b49 100644
--- a/arch/arm/mach-imx/mach-mx53_evk.c
+++ b/arch/arm/mach-imx/mach-mx53_evk.c
@@ -154,7 +154,7 @@ static void __init mx53_evk_board_init(void)
         spi_register_board_info(mx53_evk_spi_board_info,
                 ARRAY_SIZE(mx53_evk_spi_board_info));
         imx53_add_ecspi(0, &mx53_evk_spi_data);
-        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx2_wdt(0);
         gpio_led_register_device(-1, &mx53evk_leds_data);
 }
 
@@ -174,5 +174,6 @@ MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
         .handle_irq = imx53_handle_irq,
         .timer = &mx53_evk_timer,
         .init_machine = mx53_evk_board_init,
+        .init_late      = imx53_init_late,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
index 37f67cac15a..8abe23c1d3c 100644
--- a/arch/arm/mach-imx/mach-mx53_loco.c
+++ b/arch/arm/mach-imx/mach-mx53_loco.c
@@ -283,7 +283,7 @@ static void __init mx53_loco_board_init(void)
         imx53_add_imx_uart(0, NULL);
         mx53_loco_fec_reset();
         imx53_add_fec(&mx53_loco_fec_data);
-        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx2_wdt(0);
 
         ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
         if (ret)
@@ -316,5 +316,6 @@ MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
         .handle_irq = imx53_handle_irq,
         .timer = &mx53_loco_timer,
         .init_machine = mx53_loco_board_init,
+        .init_late      = imx53_init_late,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
index 8e972c5c3e1..b15d6a6d3b6 100644
--- a/arch/arm/mach-imx/mach-mx53_smd.c
+++ b/arch/arm/mach-imx/mach-mx53_smd.c
@@ -138,7 +138,7 @@ static void __init mx53_smd_board_init(void)
         mx53_smd_init_uart();
         mx53_smd_fec_reset();
         imx53_add_fec(&mx53_smd_fec_data);
-        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx2_wdt(0);
         imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
         imx53_add_sdhci_esdhc_imx(0, NULL);
         imx53_add_sdhci_esdhc_imx(1, NULL);
@@ -163,5 +163,6 @@ MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
         .handle_irq = imx53_handle_irq,
         .timer = &mx53_smd_timer,
         .init_machine = mx53_smd_board_init,
+        .init_late      = imx53_init_late,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 8b3d3f07d89..0bf6d30aa32 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -213,13 +213,13 @@ static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
 static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
                                 void *data)
 {
-        return request_irq(IRQ_GPIOF(8), detect_irq, IRQF_TRIGGER_FALLING,
-                                "sdhc1-card-detect", data);
+        return request_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), detect_irq,
+                           IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data);
 }
 
 static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(IRQ_GPIOF(8), data);
+        free_irq(gpio_to_irq(IMX_GPIO_NR(6, 8)), data);
 }
 
 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 541152e450c..de8516b7d69 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,7 +36,6 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
-#include <mach/irqs.h>
 #include <mach/ulpi.h>
 
 #include "devices-imx27.h"
@@ -245,7 +244,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 {
         int ret;
 
-        ret = request_irq(IRQ_GPIOC(29), detect_irq,
+        ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
                           IRQF_DISABLED | IRQF_TRIGGER_FALLING,
                           "imx-mmc-detect", data);
         if (ret)
@@ -257,7 +256,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 
 static void pca100_sdhc2_exit(struct device *dev, void *data)
 {
-        free_irq(IRQ_GPIOC(29), data);
+        free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
 }
 
 static const struct imxmmc_platform_data sdhc_pdata __initconst = {
@@ -298,18 +297,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init pca100_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", pca100_otg_mode);
 
@@ -408,8 +407,8 @@ static void __init pca100_init(void)
         imx27_add_imx_fb(&pca100_fb_data);
 
         imx27_add_fec(NULL);
-        imx27_add_imx2_wdt(NULL);
-        imx27_add_mxc_w1(NULL);
+        imx27_add_imx2_wdt();
+        imx27_add_mxc_w1();
 }
 
 static void __init pca100_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 0a40004154f..e3c45130fb3 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -225,8 +225,7 @@ static struct resource smsc911x_resources[] = {
                 .end            = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
                 .flags          = IORESOURCE_MEM,
         }, {
-                .start          = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
-                .end            = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+                /* irq number is run-time assigned */
                 .flags          = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
@@ -371,7 +370,7 @@ static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
         gpio_direction_input(SDHC1_GPIO_WP);
 #endif
 
-        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
+        ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
                         IRQF_DISABLED | IRQF_TRIGGER_FALLING,
                                 "sdhc-detect", data);
         if (ret)
@@ -391,7 +390,7 @@ err_gpio_free:
 
 static void pcm970_sdhc1_exit(struct device *dev, void *data)
 {
-        free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
+        free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
         gpio_free(SDHC1_GPIO_DET);
         gpio_free(SDHC1_GPIO_WP);
 }
@@ -442,10 +441,6 @@ static struct platform_device *devices[] __initdata = {
         &pcm037_mt9v022,
 };
 
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
-        .irq_base = MXC_IPU_IRQ_START,
-};
-
 static const struct fb_videomode fb_modedb[] = {
         {
                 /* 240x320 @ 60 Hz Sharp */
@@ -511,8 +506,7 @@ static struct resource pcm970_sja1000_resources[] = {
                 .end     = MX31_CS5_BASE_ADDR + 0x100 - 1,
                 .flags   = IORESOURCE_MEM,
         }, {
-                .start   = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
-                .end     = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+                /* irq number is run-time assigned */
                 .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
         },
 };
@@ -557,18 +551,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init pcm037_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", pcm037_otg_mode);
 
@@ -619,13 +613,13 @@ static void __init pcm037_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        imx31_add_imx2_wdt(NULL);
+        imx31_add_imx2_wdt();
         imx31_add_imx_uart0(&uart_pdata);
         /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
         imx31_add_imx_uart1(&uart_pdata);
         imx31_add_imx_uart2(&uart_pdata);
 
-        imx31_add_mxc_w1(NULL);
+        imx31_add_mxc_w1();
 
         /* LAN9217 IRQ pin */
         ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
@@ -633,6 +627,10 @@ static void __init pcm037_init(void)
                 pr_warning("could not get LAN irq gpio\n");
         else {
                 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
+                smsc911x_resources[1].start =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
+                smsc911x_resources[1].end =
+                        gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
                 platform_device_register(&pcm037_eth);
         }
 
@@ -646,7 +644,7 @@ static void __init pcm037_init(void)
 
         imx31_add_mxc_nand(&pcm037_nand_board_info);
         imx31_add_mxc_mmc(0, &sdhc_pdata);
-        imx31_add_ipu_core(&mx3_ipu_data);
+        imx31_add_ipu_core();
         imx31_add_mx3_sdc_fb(&mx3fb_pdata);
 
         /* CSI */
@@ -659,6 +657,10 @@ static void __init pcm037_init(void)
 
         pcm037_init_camera();
 
+        pcm970_sja1000_resources[1].start =
+                        gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
+        pcm970_sja1000_resources[1].end =
+                        gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
         platform_device_register(&pcm970_sja1000);
 
         if (otg_mode_host) {
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 2f3debe2a11..95f49d936fd 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -27,6 +27,7 @@
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
 #include <linux/irq.h>
+#include <linux/gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -274,7 +275,7 @@ static struct mc13xxx_platform_data pcm038_pmic = {
 static struct spi_board_info pcm038_spi_board_info[] __initdata = {
         {
                 .modalias = "mc13783",
-                .irq = IRQ_GPIOB(23),
+                /* irq number is run-time assigned */
                 .max_speed_hz = 300000,
                 .bus_num = 0,
                 .chip_select = 0,
@@ -325,6 +326,7 @@ static void __init pcm038_init(void)
         mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
 
         imx27_add_spi_imx0(&pcm038_spi0_data);
+        pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
         spi_register_board_info(pcm038_spi_board_info,
                                 ARRAY_SIZE(pcm038_spi_board_info));
 
@@ -332,8 +334,8 @@ static void __init pcm038_init(void)
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_imx2_wdt(NULL);
-        imx27_add_mxc_w1(NULL);
+        imx27_add_imx2_wdt();
+        imx27_add_mxc_w1();
 
 #ifdef CONFIG_MACH_PCM970_BASEBOARD
         pcm970_baseboard_init();
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 73585f55cca..e4bd4387e34 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -76,10 +76,6 @@ static const struct fb_videomode fb_modedb[] = {
         },
 };
 
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
-        .irq_base = MXC_IPU_IRQ_START,
-};
-
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "Sharp-LQ035Q7",
         .mode           = fb_modedb,
@@ -330,18 +326,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_UTMI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init pcm043_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", pcm043_otg_mode);
 
@@ -363,7 +359,7 @@ static void __init pcm043_init(void)
 
         imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
-        imx35_add_imx2_wdt(NULL);
+        imx35_add_imx2_wdt();
 
         imx35_add_imx_uart0(&uart_pdata);
         imx35_add_mxc_nand(&pcm037_nand_board_info);
@@ -376,7 +372,7 @@ static void __init pcm043_init(void)
 
         imx35_add_imx_i2c0(&pcm043_i2c0_data);
 
-        imx35_add_ipu_core(&mx3_ipu_data);
+        imx35_add_ipu_core();
         imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 
         if (otg_mode_host) {
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 260621055b6..fb25fbd3122 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -22,7 +22,6 @@
 #include <linux/gpio.h>
 
 #include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -51,8 +50,6 @@
         (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
 #define QONG_DNET_SIZE          0x00001000
 
-#define QONG_FPGA_IRQ           IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
-
 static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
@@ -78,8 +75,7 @@ static struct resource dnet_resources[] = {
                 .end    = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
                 .flags  = IORESOURCE_MEM,
         }, {
-                .start  = QONG_FPGA_IRQ,
-                .end    = QONG_FPGA_IRQ,
+                /* irq number is run-time assigned */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -95,6 +91,10 @@ static int __init qong_init_dnet(void)
 {
         int ret;
 
+        dnet_resources[1].start =
+                gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
+        dnet_resources[1].end =
+                gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
         ret = platform_device_register(&dnet_device);
         return ret;
 }
@@ -252,7 +252,7 @@ static void __init qong_init(void)
         mxc_init_imx_uart();
         qong_init_nor_mtd();
         qong_init_fpga();
-        imx31_add_imx2_wdt(NULL);
+        imx31_add_imx2_wdt();
 }
 
 static void __init qong_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index cb9ceae2f64..67ff38e9a3c 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -14,6 +14,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/interrupt.h>
 #include <linux/dm9000.h>
+#include <linux/gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -21,7 +22,6 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <mach/iomux-mx1.h>
 
 #include "devices-imx1.h"
@@ -78,8 +78,7 @@ static struct resource dm9000x_resources[] = {
                 .end    = MX1_CS5_PHYS + 5,
                 .flags  = IORESOURCE_MEM,       /* data access */
         }, {
-                .start  = IRQ_GPIOC(3),
-                .end    = IRQ_GPIOC(3),
+                /* irq number is run-time assigned */
                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
@@ -123,6 +122,8 @@ static void __init scb9328_init(void)
         imx1_add_imx_uart0(&uart_pdata);
 
         printk(KERN_INFO"Scb9328: Adding devices\n");
+        dm9000x_resources[2].start = gpio_to_irq(IMX_GPIO_NR(3, 3));
+        dm9000x_resources[2].end = gpio_to_irq(IMX_GPIO_NR(3, 3));
         platform_add_devices(devices, ARRAY_SIZE(devices));
 }
 
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index add8c69c6c1..39eb7960e2a 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -31,7 +31,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/iomux-mx35.h>
-#include <mach/irqs.h>
 
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
@@ -87,10 +86,6 @@ static const struct fb_videomode fb_modedb[] = {
         }
 };
 
-static const struct ipu_platform_data mx3_ipu_data __initconst = {
-        .irq_base = MXC_IPU_IRQ_START,
-};
-
 static struct mx3fb_platform_data mx3fb_pdata __initdata = {
         .name           = "PT0708048",
         .mode           = fb_modedb,
@@ -162,7 +157,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
         }, {
                 I2C_BOARD_INFO("mc13892", 0x08),
                 .platform_data = &vpr200_pmic,
-                .irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
+                /* irq number is run-time assigned */
         }
 };
 
@@ -272,7 +267,7 @@ static void __init vpr200_board_init(void)
         mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
 
         imx35_add_fec(NULL);
-        imx35_add_imx2_wdt(NULL);
+        imx35_add_imx2_wdt();
         imx_add_gpio_keys(&vpr200_gpio_keys_data);
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
@@ -290,7 +285,7 @@ static void __init vpr200_board_init(void)
         imx35_add_imx_uart0(NULL);
         imx35_add_imx_uart2(NULL);
 
-        imx35_add_ipu_core(&mx3_ipu_data);
+        imx35_add_ipu_core();
         imx35_add_mx3_sdc_fb(&mx3fb_pdata);
 
         imx35_add_fsl_usb2_udc(&otg_device_pdata);
@@ -299,6 +294,7 @@ static void __init vpr200_board_init(void)
         imx35_add_mxc_nand(&vpr200_nand_board_info);
         imx35_add_sdhci_esdhc_imx(0, NULL);
 
+        vpr200_i2c_devices[1].irq = gpio_to_irq(GPIO_PMIC_INT);
         i2c_register_board_info(0, vpr200_i2c_devices,
                         ARRAY_SIZE(vpr200_i2c_devices));
 
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index fcafd3dafb8..6d60d51868b 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -24,7 +24,6 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/irqs.h>
 #include <mach/iomux-v1.h>
 
 static struct map_desc imx_io_desc[] __initdata = {
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 5f43905e529..d056dad0940 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -26,7 +26,6 @@
 #include <mach/devices-common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-#include <mach/irqs.h>
 #include <mach/iomux-v1.h>
 
 /* MX21 memory map definition */
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 6ff37140a4f..f3f5c6542ab 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -29,7 +29,6 @@
 #include <mach/hardware.h>
 #include <mach/mx25.h>
 #include <mach/iomux-v3.h>
-#include <mach/irqs.h>
 
 /*
  * This table defines static virtual address mappings for I/O regions.
@@ -90,11 +89,11 @@ static const struct resource imx25_audmux_res[] __initconst = {
 
 void __init imx25_soc_init(void)
 {
-        /* i.mx25 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
-        mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
-        mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
-        mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
+        /* i.mx25 has the i.mx35 type gpio */
+        mxc_register_gpio("imx35-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
+        mxc_register_gpio("imx35-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
+        mxc_register_gpio("imx35-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
+        mxc_register_gpio("imx35-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
 
         pinctrl_provide_dummies();
         /* i.mx25 has the i.mx35 type sdma */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 25662558e01..e7e24afc45e 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -26,7 +26,6 @@
 #include <mach/devices-common.h>
 #include <asm/pgtable.h>
 #include <asm/mach/map.h>
-#include <mach/irqs.h>
 #include <mach/iomux-v1.h>
 
 /* MX27 memory map definition */
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index a8983b9778d..9d2c843bde0 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -30,7 +30,6 @@
 #include <mach/devices-common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-v3.h>
-#include <mach/irqs.h>
 
 #include "crmregs-imx3.h"
 
@@ -273,10 +272,9 @@ void __init imx35_soc_init(void)
 
         imx3_init_l2x0();
 
-        /* i.mx35 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
-        mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
-        mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
+        mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
+        mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
+        mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
 
         pinctrl_provide_dummies();
         if (to_version == 1) {
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 1d003053d56..52d8f534be1 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -16,7 +16,6 @@
 #include <linux/clk.h>
 #include <linux/pinctrl/machine.h>
 
-#include <asm/system_misc.h>
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
@@ -24,24 +23,6 @@
 #include <mach/devices-common.h>
 #include <mach/iomux-v3.h>
 
-static struct clk *gpc_dvfs_clk;
-
-static void imx5_idle(void)
-{
-        /* gpc clock is needed for SRPG */
-        if (gpc_dvfs_clk == NULL) {
-                gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
-                if (IS_ERR(gpc_dvfs_clk))
-                        return;
-                clk_prepare(gpc_dvfs_clk);
-        }
-        clk_enable(gpc_dvfs_clk);
-        mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-        if (!tzic_enable_wake())
-                cpu_do_idle();
-        clk_disable(gpc_dvfs_clk);
-}
-
 /*
  * Define the MX50 memory map.
  */
@@ -105,7 +86,6 @@ void __init imx51_init_early(void)
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-        arm_pm_idle = imx5_idle;
 }
 
 void __init imx53_init_early(void)
@@ -181,13 +161,13 @@ static const struct resource imx53_audmux_res[] __initconst = {
 
 void __init imx50_soc_init(void)
 {
-        /* i.mx50 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
-        mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
-        mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
+        /* i.mx50 has the i.mx35 type gpio */
+        mxc_register_gpio("imx35-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
+        mxc_register_gpio("imx35-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
+        mxc_register_gpio("imx35-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
+        mxc_register_gpio("imx35-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
+        mxc_register_gpio("imx35-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
+        mxc_register_gpio("imx35-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
 
         /* i.mx50 has the i.mx31 type audmux */
         platform_device_register_simple("imx31-audmux", 0, imx50_audmux_res,
@@ -196,11 +176,11 @@ void __init imx50_soc_init(void)
 
 void __init imx51_soc_init(void)
 {
-        /* i.mx51 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
+        /* i.mx51 has the i.mx35 type gpio */
+        mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
+        mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
+        mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
+        mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
 
         pinctrl_provide_dummies();
 
@@ -218,14 +198,14 @@ void __init imx51_soc_init(void)
 
 void __init imx53_soc_init(void)
 {
-        /* i.mx53 has the i.mx31 type gpio */
-        mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
-        mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
-        mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
-        mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
-        mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
-        mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
-        mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
+        /* i.mx53 has the i.mx35 type gpio */
+        mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
+        mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
+        mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
+        mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
+        mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
+        mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
+        mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
 
         pinctrl_provide_dummies();
         /* i.mx53 has the i.mx35 type sdma */
@@ -243,4 +223,10 @@ void __init imx53_soc_init(void)
 void __init imx51_init_late(void)
 {
         mx51_neon_fixup();
+        imx51_pm_init();
+}
+
+void __init imx53_init_late(void)
+{
+        imx53_pm_init();
 }
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
index 7d26f766a4e..29e890f9205 100644
--- a/arch/arm/mach-imx/mx31lilly-db.c
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -130,7 +130,8 @@ static int mxc_mmc1_init(struct device *dev,
         gpio_direction_input(gpio_det);
         gpio_direction_input(gpio_wp);
 
-        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq,
+        ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)),
+                          detect_irq,
                           IRQF_DISABLED | IRQF_TRIGGER_FALLING,
                           "MMC detect", data);
         if (ret)
@@ -151,7 +152,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
 {
         gpio_free(gpio_det);
         gpio_free(gpio_wp);
-        free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
+        free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), data);
 }
 
 static const struct imxmmc_platform_data mmc_pdata __initconst = {
@@ -161,10 +162,6 @@ static const struct imxmmc_platform_data mmc_pdata __initconst = {
 };
 
 /* Framebuffer support */
-static const struct ipu_platform_data ipu_data __initconst = {
-        .irq_base = MXC_IPU_IRQ_START,
-};
-
 static const struct fb_videomode fb_modedb = {
         /* 640x480 TFT panel (IPS-056T) */
         .name           = "CRT-VGA",
@@ -198,7 +195,7 @@ static void __init mx31lilly_init_fb(void)
                 return;
         }
 
-        imx31_add_ipu_core(&ipu_data);
+        imx31_add_ipu_core();
         imx31_add_mx3_sdc_fb(&fb_pdata);
         gpio_direction_output(LCD_VCC_EN_GPIO, 1);
 }
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index bf0fb87946b..83d17d9e0bc 100644
--- a/arch/arm/mach-imx/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -116,7 +116,8 @@ static int mxc_mmc1_init(struct device *dev,
         gpio_direction_input(gpio_det);
         gpio_direction_input(gpio_wp);
 
-        ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
+        ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)),
+                          detect_irq,
                           IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
                           "MMC detect", data);
         if (ret)
@@ -137,7 +138,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
 {
         gpio_free(gpio_det);
         gpio_free(gpio_wp);
-        free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
+        free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), data);
 }
 
 static const struct imxmmc_platform_data mmc_pdata __initconst = {
@@ -191,6 +192,6 @@ void __init mx31lite_db_init(void)
         imx31_add_mxc_mmc(0, &mmc_pdata);
         imx31_add_spi_imx0(&spi0_pdata);
         gpio_led_register_device(-1, &litekit_led_platform_data);
-        imx31_add_imx2_wdt(NULL);
-        imx31_add_mxc_rtc(NULL);
+        imx31_add_imx2_wdt();
+        imx31_add_mxc_rtc();
 }
diff --git a/arch/arm/mach-imx/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
index ec6ca91b299..ee870c49bc6 100644
--- a/arch/arm/mach-imx/mx51_efika.c
+++ b/arch/arm/mach-imx/mx51_efika.c
@@ -587,7 +587,7 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 0,
                 .platform_data = &mx51_efika_mc13892_data,
-                .irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
+                /* irq number is run-time assigned */
         },
 };
 
@@ -620,6 +620,7 @@ void __init efika_board_common_init(void)
 
         gpio_request(EFIKAMX_PMIC, "pmic irq");
         gpio_direction_input(EFIKAMX_PMIC);
+        mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
         spi_register_board_info(mx51_efika_spi_board_info,
                 ARRAY_SIZE(mx51_efika_spi_board_info));
         imx51_add_ecspi(0, &mx51_efika_spi_pdata);
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index 99afbc3f43a..9917e2ff51d 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -95,14 +95,14 @@ static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void
 {
         int ret;
 
-        ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING,
-                                "imx-mmc-detect", data);
+        ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
+                          IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
         if (ret)
                 return ret;
 
         ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
         if (ret) {
-                free_irq(IRQ_GPIOC(29), data);
+                free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
                 return ret;
         }
 
@@ -113,7 +113,7 @@ static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void
 
 static void pcm970_sdhc2_exit(struct device *dev, void *data)
 {
-        free_irq(IRQ_GPIOC(29), data);
+        free_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), data);
         gpio_free(GPIO_PORTC + 28);
 }
 
@@ -192,8 +192,7 @@ static struct resource pcm970_sja1000_resources[] = {
                 .end     = MX27_CS4_BASE_ADDR + 0x100 - 1,
                 .flags   = IORESOURCE_MEM,
         }, {
-                .start   = IRQ_GPIOE(19),
-                .end     = IRQ_GPIOE(19),
+                /* irq number is run-time assigned */
                 .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
         },
 };
@@ -227,5 +226,7 @@ void __init pcm970_baseboard_init(void)
         imx27_add_imx_fb(&pcm038_fb_data);
         mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
         imx27_add_mxc_mmc(1, &sdhc_pdata);
+        pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIO_NR(5, 19));
+        pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIO_NR(5, 19));
         platform_device_register(&pcm970_sja1000);
 }
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index e26a9cb05ed..19621ed1ffa 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -12,19 +12,30 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <asm/cacheflush.h>
+#include <asm/system_misc.h>
 #include <asm/tlbflush.h>
 #include <mach/common.h>
+#include <mach/cpuidle.h>
 #include <mach/hardware.h>
 #include "crm-regs-imx5.h"
 
-static struct clk *gpc_dvfs_clk;
+/*
+ * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
+ * This is also the lowest power state possible without affecting
+ * non-cpu parts of the system.  For these reasons, imx5 should default
+ * to always using this state for cpu idling.  The PM_SUSPEND_STANDBY also
+ * uses this state and needs to take no action when registers remain confgiured
+ * for this state.
+ */
+#define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF
 
 /*
  * set cpu low power mode before WFI instruction. This function is called
  * mx5 because it can be used for mx50, mx51, and mx53.
  */
-void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
+static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 {
         u32 plat_lpc, arm_srpgcr, ccm_clpcr;
         u32 empgc0, empgc1;
@@ -87,11 +98,6 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
         }
 }
 
-static int mx5_suspend_prepare(void)
-{
-        return clk_prepare_enable(gpc_dvfs_clk);
-}
-
 static int mx5_suspend_enter(suspend_state_t state)
 {
         switch (state) {
@@ -99,7 +105,7 @@ static int mx5_suspend_enter(suspend_state_t state)
                 mx5_cpu_lp_set(STOP_POWER_OFF);
                 break;
         case PM_SUSPEND_STANDBY:
-                mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+                /* DEFAULT_IDLE_STATE already configured */
                 break;
         default:
                 return -EINVAL;
@@ -114,12 +120,10 @@ static int mx5_suspend_enter(suspend_state_t state)
                 __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
         }
         cpu_do_idle();
-        return 0;
-}
 
-static void mx5_suspend_finish(void)
-{
-        clk_disable_unprepare(gpc_dvfs_clk);
+        /* return registers to default idle state */
+        mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
+        return 0;
 }
 
 static int mx5_pm_valid(suspend_state_t state)
@@ -129,25 +133,80 @@ static int mx5_pm_valid(suspend_state_t state)
 
 static const struct platform_suspend_ops mx5_suspend_ops = {
         .valid = mx5_pm_valid,
-        .prepare = mx5_suspend_prepare,
         .enter = mx5_suspend_enter,
-        .finish = mx5_suspend_finish,
 };
 
-static int __init mx5_pm_init(void)
+static inline int imx5_cpu_do_idle(void)
+{
+        int ret = tzic_enable_wake();
+
+        if (likely(!ret))
+                cpu_do_idle();
+
+        return ret;
+}
+
+static void imx5_pm_idle(void)
+{
+        imx5_cpu_do_idle();
+}
+
+static int imx5_cpuidle_enter(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv, int idx)
+{
+        int ret;
+
+        ret = imx5_cpu_do_idle();
+        if (ret < 0)
+                return ret;
+
+        return idx;
+}
+
+static struct cpuidle_driver imx5_cpuidle_driver = {
+        .name                   = "imx5_cpuidle",
+        .owner                  = THIS_MODULE,
+        .en_core_tk_irqen       = 1,
+        .states[0]      = {
+                .enter                  = imx5_cpuidle_enter,
+                .exit_latency           = 2,
+                .target_residency       = 1,
+                .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                .name                   = "IMX5 SRPG",
+                .desc                   = "CPU state retained,powered off",
+        },
+        .state_count            = 1,
+};
+
+static int __init imx5_pm_common_init(void)
 {
-        if (!cpu_is_mx51() && !cpu_is_mx53())
-                return 0;
+        int ret;
+        struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
 
-        if (gpc_dvfs_clk == NULL)
-                gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
+        if (IS_ERR(gpc_dvfs_clk))
+                return PTR_ERR(gpc_dvfs_clk);
 
-        if (!IS_ERR(gpc_dvfs_clk)) {
-                if (cpu_is_mx51())
-                        suspend_set_ops(&mx5_suspend_ops);
-        } else
-                return -EPERM;
+        ret = clk_prepare_enable(gpc_dvfs_clk);
+        if (ret)
+                return ret;
 
+        arm_pm_idle = imx5_pm_idle;
+
+        /* Set the registers to the default cpu idle state. */
+        mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
+
+        imx_cpuidle_init(&imx5_cpuidle_driver);
         return 0;
 }
-device_initcall(mx5_pm_init);
+
+void __init imx51_pm_init(void)
+{
+        int ret = imx5_pm_common_init();
+        if (!ret)
+                suspend_set_ops(&mx5_suspend_ops);
+}
+
+void __init imx53_pm_init(void)
+{
+        imx5_pm_common_init();
+}
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index eaf6c6366ff..3fa6c51390d 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -11,6 +11,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/device.h>
+#include <linux/export.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
@@ -21,7 +22,6 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
 #include <linux/io.h>
-#include <linux/clkdev.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -41,17 +41,17 @@ static struct amba_pl010_data integrator_uart_data;
 #define KMI0_IRQ                { IRQ_KMIINT0 }
 #define KMI1_IRQ                { IRQ_KMIINT1 }
 
-static AMBA_APB_DEVICE(rtc, "mb:15", 0,
+static AMBA_APB_DEVICE(rtc, "rtc", 0,
         INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
 
-static AMBA_APB_DEVICE(uart0, "mb:16", 0,
+static AMBA_APB_DEVICE(uart0, "uart0", 0,
         INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
 
-static AMBA_APB_DEVICE(uart1, "mb:17", 0,
+static AMBA_APB_DEVICE(uart1, "uart1", 0,
         INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
 
-static AMBA_APB_DEVICE(kmi0, "mb:18", 0, KMI0_BASE, KMI0_IRQ, NULL);
-static AMBA_APB_DEVICE(kmi1, "mb:19", 0, KMI1_BASE, KMI1_IRQ, NULL);
+static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL);
+static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
         &rtc_device,
@@ -61,50 +61,6 @@ static struct amba_device *amba_devs[] __initdata = {
         &kmi1_device,
 };
 
-/*
- * These are fixed clocks.
- */
-static struct clk clk24mhz = {
-        .rate   = 24000000,
-};
-
-static struct clk uartclk = {
-        .rate   = 14745600,
-};
-
-static struct clk dummy_apb_pclk;
-
-static struct clk_lookup lookups[] = {
-        {       /* Bus clock */
-                .con_id         = "apb_pclk",
-                .clk            = &dummy_apb_pclk,
-        }, {
-                /* Integrator/AP timer frequency */
-                .dev_id         = "ap_timer",
-                .clk            = &clk24mhz,
-        }, {    /* UART0 */
-                .dev_id         = "mb:16",
-                .clk            = &uartclk,
-        }, {    /* UART1 */
-                .dev_id         = "mb:17",
-                .clk            = &uartclk,
-        }, {    /* KMI0 */
-                .dev_id         = "mb:18",
-                .clk            = &clk24mhz,
-        }, {    /* KMI1 */
-                .dev_id         = "mb:19",
-                .clk            = &clk24mhz,
-        }, {    /* MMCI - IntegratorCP */
-                .dev_id         = "mb:1c",
-                .clk            = &uartclk,
-        }
-};
-
-void __init integrator_init_early(void)
-{
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
-
 static int __init integrator_init(void)
 {
         int i;
diff --git a/arch/arm/mach-integrator/include/mach/clkdev.h b/arch/arm/mach-integrator/include/mach/clkdev.h
deleted file mode 100644
index bfe07679fae..00000000000
--- a/arch/arm/mach-integrator/include/mach/clkdev.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#include <linux/module.h>
-#include <plat/clock.h>
-
-struct clk {
-        unsigned long           rate;
-        const struct clk_ops    *ops;
-        struct module           *owner;
-        const struct icst_params *params;
-        void __iomem            *vcoreg;
-        void                    *data;
-};
-
-static inline int __clk_get(struct clk *clk)
-{
-        return try_module_get(clk->owner);
-}
-
-static inline void __clk_put(struct clk *clk)
-{
-        module_put(clk->owner);
-}
-
-#endif
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index c857501c578..3b2267529f5 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -33,6 +33,7 @@
 #include <linux/io.h>
 #include <linux/mtd/physmap.h>
 #include <linux/clk.h>
+#include <linux/platform_data/clk-integrator.h>
 #include <video/vga.h>
 
 #include <mach/hardware.h>
@@ -174,6 +175,7 @@ static void __init ap_init_irq(void)
 
         fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
                 -1, INTEGRATOR_SC_VALID_INT, NULL);
+        integrator_clk_init(false);
 }
 
 #ifdef CONFIG_PM
@@ -440,6 +442,10 @@ static void integrator_clockevent_init(unsigned long inrate)
                                         0xffffU);
 }
 
+void __init ap_init_early(void)
+{
+}
+
 /*
  * Set up timer(s).
  */
@@ -450,7 +456,7 @@ static void __init ap_init_timer(void)
 
         clk = clk_get_sys("ap_timer", NULL);
         BUG_ON(IS_ERR(clk));
-        clk_enable(clk);
+        clk_prepare_enable(clk);
         rate = clk_get_rate(clk);
 
         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
@@ -471,7 +477,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
         .reserve        = integrator_reserve,
         .map_io         = ap_map_io,
         .nr_irqs        = NR_IRQS_INTEGRATOR_AP,
-        .init_early     = integrator_init_early,
+        .init_early     = ap_init_early,
         .init_irq       = ap_init_irq,
         .handle_irq     = fpga_handle_irq,
         .timer          = &ap_timer,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index a56c5360893..82d5c837cc7 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -21,8 +21,8 @@
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
 #include <linux/gfp.h>
-#include <linux/clkdev.h>
 #include <linux/mtd/physmap.h>
+#include <linux/platform_data/clk-integrator.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -171,65 +171,10 @@ static void __init intcp_init_irq(void)
 
         fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
                       IRQ_CP_CPPLDINT, sic_mask, NULL);
+        integrator_clk_init(true);
 }
 
 /*
- * Clock handling
- */
-#define CM_LOCK         (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
-#define CM_AUXOSC       (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
-
-static const struct icst_params cp_auxvco_params = {
-        .ref            = 24000000,
-        .vco_max        = ICST525_VCO_MAX_5V,
-        .vco_min        = ICST525_VCO_MIN,
-        .vd_min         = 8,
-        .vd_max         = 263,
-        .rd_min         = 3,
-        .rd_max         = 65,
-        .s2div          = icst525_s2div,
-        .idx2s          = icst525_idx2s,
-};
-
-static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
-{
-        u32 val;
-
-        val = readl(clk->vcoreg) & ~0x7ffff;
-        val |= vco.v | (vco.r << 9) | (vco.s << 16);
-
-        writel(0xa05f, CM_LOCK);
-        writel(val, clk->vcoreg);
-        writel(0, CM_LOCK);
-}
-
-static const struct clk_ops cp_auxclk_ops = {
-        .round  = icst_clk_round,
-        .set    = icst_clk_set,
-        .setvco = cp_auxvco_set,
-};
-
-static struct clk cp_auxclk = {
-        .ops    = &cp_auxclk_ops,
-        .params = &cp_auxvco_params,
-        .vcoreg = CM_AUXOSC,
-};
-
-static struct clk sp804_clk = {
-        .rate   = 1000000,
-};
-
-static struct clk_lookup cp_lookups[] = {
-        {       /* CLCD */
-                .dev_id         = "mb:c0",
-                .clk            = &cp_auxclk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .clk            = &sp804_clk,
-        },
-};
-
-/*
  * Flash handling.
  */
 static int intcp_flash_init(struct platform_device *dev)
@@ -336,10 +281,10 @@ static struct mmci_platform_data mmc_data = {
 #define INTEGRATOR_CP_MMC_IRQS  { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
 #define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
 
-static AMBA_APB_DEVICE(mmc, "mb:1c", 0, INTEGRATOR_CP_MMC_BASE,
+static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
         INTEGRATOR_CP_MMC_IRQS, &mmc_data);
 
-static AMBA_APB_DEVICE(aaci, "mb:1d", 0, INTEGRATOR_CP_AACI_BASE,
+static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
         INTEGRATOR_CP_AACI_IRQS, NULL);
 
 
@@ -393,7 +338,7 @@ static struct clcd_board clcd_data = {
         .remove         = versatile_clcd_remove_dma,
 };
 
-static AMBA_AHB_DEVICE(clcd, "mb:c0", 0, INTCP_PA_CLCD_BASE,
+static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
         { IRQ_CP_CLCDCINT }, &clcd_data);
 
 static struct amba_device *amba_devs[] __initdata = {
@@ -406,10 +351,6 @@ static struct amba_device *amba_devs[] __initdata = {
 
 static void __init intcp_init_early(void)
 {
-        clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
-
-        integrator_init_early();
-
 #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
         versatile_sched_clock_init(REFCOUNTER, 24000000);
 #endif
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 199764fe0fb..ca5c15a4e62 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -80,6 +80,35 @@ config MACH_IB62X0_DT
           RaidSonic IB-NAS6210 & IB-NAS6220 devices, using
           Flattened Device Tree.
 
+config MACH_TS219_DT
+        bool "Device Tree for QNAP TS-11X, TS-21X NAS"
+        select ARCH_KIRKWOOD_DT
+        select ARM_APPENDED_DTB
+        select ARM_ATAG_DTB_COMPAT
+        help
+          Say 'Y' here if you want your kernel to support the QNAP
+          TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
+          TS-219P+ Turbo NAS devices using Fattened Device Tree.
+          There are two different Device Tree descriptions, depending
+          on if the device is based on an if the board uses the MV6281
+          or MV6282. If you have the wrong one, the buttons will not
+          work.
+
+config MACH_GOFLEXNET_DT
+        bool "Seagate GoFlex Net (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Seagate GoFlex Net (Flattened Device Tree).
+
+config MACH_LSXL_DT
+        bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
+          Flattened Device Tree.
+
 config MACH_TS219
         bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
         help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index d2b05907b10..055c85a1cc4 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -25,3 +25,6 @@ obj-$(CONFIG_MACH_DREAMPLUG_DT)		+= board-dreamplug.o
 obj-$(CONFIG_MACH_ICONNECT_DT)          += board-iconnect.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
 obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
+obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
+obj-$(CONFIG_MACH_GOFLEXNET_DT)         += board-goflexnet.o
+obj-$(CONFIG_MACH_LSXL_DT)              += board-lsxl.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
index 02edbdf5b06..a13299d758e 100644
--- a/arch/arm/mach-kirkwood/Makefile.boot
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -7,3 +7,8 @@ dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns320.dtb
 dtb-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += kirkwood-dns325.dtb
 dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb
 dtb-$(CONFIG_MACH_IB62X0_DT) += kirkwood-ib62x0.dtb
+dtb-$(CONFIG_MACH_TS219_DT)     += kirkwood-ts219-6281.dtb
+dtb-$(CONFIG_MACH_TS219_DT)     += kirkwood-ts219-6282.dtb
+dtb-$(CONFIG_MACH_GOFLEXNET_DT) += kirkwood-goflexnet.dtb
+dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lschlv2.dtb
+dtb-$(CONFIG_MACH_LSXL_DT) += kirkwood-lsxhl.dtb
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 58c2d68f944..4ab35065a14 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -14,13 +14,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/i2c.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/of.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
-#include <linux/gpio_keys.h>
 #include <linux/gpio-fan.h>
 #include <linux/leds.h>
 #include <asm/mach-types.h>
@@ -35,10 +33,6 @@ static struct mv643xx_eth_platform_data dnskw_ge00_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
-static struct mv_sata_platform_data dnskw_sata_data = {
-        .n_ports        = 2,
-};
-
 static unsigned int dnskw_mpp_config[] __initdata = {
         MPP13_UART1_TXD,        /* Custom ... */
         MPP14_UART1_RXD,        /* ... Controller (DNS-320 only) */
@@ -73,132 +67,6 @@ static unsigned int dnskw_mpp_config[] __initdata = {
         0
 };
 
-static struct gpio_led dns325_led_pins[] = {
-        {
-                .name   = "dns325:white:power",
-                .gpio   = 26,
-                .active_low = 1,
-                .default_trigger = "default-on",
-        },
-        {
-                .name   = "dns325:white:usb",
-                .gpio   = 43,
-                .active_low = 1,
-        },
-        {
-                .name   = "dns325:red:l_hdd",
-                .gpio   = 28,
-                .active_low = 1,
-        },
-        {
-                .name   = "dns325:red:r_hdd",
-                .gpio   = 27,
-                .active_low = 1,
-        },
-        {
-                .name   = "dns325:red:usb",
-                .gpio   = 29,
-                .active_low = 1,
-        },
-};
-
-static struct gpio_led_platform_data dns325_led_data = {
-        .num_leds       = ARRAY_SIZE(dns325_led_pins),
-        .leds           = dns325_led_pins,
-};
-
-static struct platform_device dns325_led_device = {
-        .name           = "leds-gpio",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &dns325_led_data,
-        },
-};
-
-static struct gpio_led dns320_led_pins[] = {
-        {
-                .name   = "dns320:blue:power",
-                .gpio   = 26,
-                .active_low = 1,
-                .default_trigger = "default-on",
-        },
-        {
-                .name   = "dns320:blue:usb",
-                .gpio   = 43,
-                .active_low = 1,
-        },
-        {
-                .name   = "dns320:orange:l_hdd",
-                .gpio   = 28,
-                .active_low = 1,
-        },
-        {
-                .name   = "dns320:orange:r_hdd",
-                .gpio   = 27,
-                .active_low = 1,
-        },
-        {
-                .name   = "dns320:orange:usb",
-                .gpio   = 35,
-                .active_low = 1,
-        },
-};
-
-static struct gpio_led_platform_data dns320_led_data = {
-        .num_leds       = ARRAY_SIZE(dns320_led_pins),
-        .leds           = dns320_led_pins,
-};
-
-static struct platform_device dns320_led_device = {
-        .name           = "leds-gpio",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &dns320_led_data,
-        },
-};
-
-static struct i2c_board_info dns325_i2c_board_info[] __initdata = {
-        {
-                I2C_BOARD_INFO("lm75", 0x48),
-        },
-        /* Something at 0x0c also */
-};
-
-static struct gpio_keys_button dnskw_button_pins[] = {
-        {
-                .code           = KEY_POWER,
-                .gpio           = 34,
-                .desc           = "Power button",
-                .active_low     = 1,
-        },
-        {
-                .code           = KEY_EJECTCD,
-                .gpio           = 47,
-                .desc           = "USB unmount button",
-                .active_low     = 1,
-        },
-        {
-                .code           = KEY_RESTART,
-                .gpio           = 48,
-                .desc           = "Reset button",
-                .active_low     = 1,
-        },
-};
-
-static struct gpio_keys_platform_data dnskw_button_data = {
-        .buttons        = dnskw_button_pins,
-        .nbuttons       = ARRAY_SIZE(dnskw_button_pins),
-};
-
-static struct platform_device dnskw_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &dnskw_button_data,
-        }
-};
-
 /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
 static struct gpio_fan_speed dnskw_fan_speed[] = {
         {    0,  0 },
@@ -245,20 +113,9 @@ void __init dnskw_init(void)
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&dnskw_ge00_data);
-        kirkwood_sata_init(&dnskw_sata_data);
-        kirkwood_i2c_init();
 
-        platform_device_register(&dnskw_button_device);
         platform_device_register(&dnskw_fan_device);
 
-        if (of_machine_is_compatible("dlink,dns-325")) {
-                i2c_register_board_info(0, dns325_i2c_board_info,
-                                        ARRAY_SIZE(dns325_i2c_board_info));
-                platform_device_register(&dns325_led_device);
-
-        } else if (of_machine_is_compatible("dlink,dns-320"))
-                platform_device_register(&dns320_led_device);
-
         /* Register power-off GPIO. */
         if (gpio_request(36, "dnskw:power:off") == 0
             && gpio_direction_output(36, 0) == 0)
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
index 55e357ab292..aeb234d0d0e 100644
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ b/arch/arm/mach-kirkwood/board-dreamplug.c
@@ -14,7 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/of.h>
@@ -23,7 +22,6 @@
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/gpio.h>
-#include <linux/leds.h>
 #include <linux/mtd/physmap.h>
 #include <linux/spi/flash.h>
 #include <linux/spi/spi.h>
@@ -36,42 +34,6 @@
 #include "common.h"
 #include "mpp.h"
 
-struct mtd_partition dreamplug_partitions[] = {
-        {
-                .name   = "u-boot",
-                .size   = SZ_512K,
-                .offset = 0,
-        },
-        {
-                .name   = "u-boot env",
-                .size   = SZ_64K,
-                .offset = SZ_512K + SZ_512K,
-        },
-        {
-                .name   = "dtb",
-                .size   = SZ_64K,
-                .offset = SZ_512K + SZ_512K + SZ_512K,
-        },
-};
-
-static const struct flash_platform_data dreamplug_spi_slave_data = {
-        .type           = "mx25l1606e",
-        .name           = "spi_flash",
-        .parts          = dreamplug_partitions,
-        .nr_parts       = ARRAY_SIZE(dreamplug_partitions),
-};
-
-static struct spi_board_info __initdata dreamplug_spi_slave_info[] = {
-        {
-                .modalias       = "m25p80",
-                .platform_data  = &dreamplug_spi_slave_data,
-                .irq            = -1,
-                .max_speed_hz   = 50000000,
-                .bus_num        = 0,
-                .chip_select    = 0,
-        },
-};
-
 static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
 };
@@ -80,45 +42,10 @@ static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(1),
 };
 
-static struct mv_sata_platform_data dreamplug_sata_data = {
-        .n_ports        = 1,
-};
-
 static struct mvsdio_platform_data dreamplug_mvsdio_data = {
         /* unfortunately the CD signal has not been connected */
 };
 
-static struct gpio_led dreamplug_led_pins[] = {
-        {
-                .name                   = "dreamplug:blue:bluetooth",
-                .gpio                   = 47,
-                .active_low             = 1,
-        },
-        {
-                .name                   = "dreamplug:green:wifi",
-                .gpio                   = 48,
-                .active_low             = 1,
-        },
-        {
-                .name                   = "dreamplug:green:wifi_ap",
-                .gpio                   = 49,
-                .active_low             = 1,
-        },
-};
-
-static struct gpio_led_platform_data dreamplug_led_data = {
-        .leds           = dreamplug_led_pins,
-        .num_leds       = ARRAY_SIZE(dreamplug_led_pins),
-};
-
-static struct platform_device dreamplug_leds = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &dreamplug_led_data,
-        }
-};
-
 static unsigned int dreamplug_mpp_config[] __initdata = {
         MPP0_SPI_SCn,
         MPP1_SPI_MOSI,
@@ -137,15 +64,8 @@ void __init dreamplug_init(void)
          */
         kirkwood_mpp_conf(dreamplug_mpp_config);
 
-        spi_register_board_info(dreamplug_spi_slave_info,
-                                ARRAY_SIZE(dreamplug_spi_slave_info));
-        kirkwood_spi_init();
-
         kirkwood_ehci_init();
         kirkwood_ge00_init(&dreamplug_ge00_data);
         kirkwood_ge01_init(&dreamplug_ge01_data);
-        kirkwood_sata_init(&dreamplug_sata_data);
         kirkwood_sdio_init(&dreamplug_mvsdio_data);
-
-        platform_device_register(&dreamplug_leds);
 }
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index edc3f8a9d45..e4eb450de30 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -18,6 +18,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/bridge-regs.h>
+#include <plat/irq.h>
 #include "common.h"
 
 static struct of_device_id kirkwood_dt_match_table[] __initdata = {
@@ -25,6 +26,16 @@ static struct of_device_id kirkwood_dt_match_table[] __initdata = {
         { }
 };
 
+struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
+        OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
+                       NULL),
+        OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
+        OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
+        OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL),
+        {},
+};
+
 static void __init kirkwood_dt_init(void)
 {
         pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk);
@@ -47,7 +58,6 @@ static void __init kirkwood_dt_init(void)
         kirkwood_clk_init();
 
         /* internal devices that every board has */
-        kirkwood_wdt_init();
         kirkwood_xor0_init();
         kirkwood_xor1_init();
         kirkwood_crypto_init();
@@ -68,7 +78,17 @@ static void __init kirkwood_dt_init(void)
         if (of_machine_is_compatible("raidsonic,ib-nas62x0"))
                 ib62x0_init();
 
-        of_platform_populate(NULL, kirkwood_dt_match_table, NULL, NULL);
+        if (of_machine_is_compatible("qnap,ts219"))
+                qnap_dt_ts219_init();
+
+        if (of_machine_is_compatible("seagate,goflexnet"))
+                goflexnet_init();
+
+        if (of_machine_is_compatible("buffalo,lsxl"))
+                lsxl_init();
+
+        of_platform_populate(NULL, kirkwood_dt_match_table,
+                             kirkwood_auxdata_lookup, NULL);
 }
 
 static const char *kirkwood_dt_board_compat[] = {
@@ -77,6 +97,9 @@ static const char *kirkwood_dt_board_compat[] = {
         "dlink,dns-325",
         "iom,iconnect",
         "raidsonic,ib-nas62x0",
+        "qnap,ts219",
+        "seagate,goflexnet",
+        "buffalo,lsxl",
         NULL
 };
 
@@ -84,7 +107,7 @@ DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
         /* Maintainer: Jason Cooper <jason@lakedaemon.net> */
         .map_io         = kirkwood_map_io,
         .init_early     = kirkwood_init_early,
-        .init_irq       = kirkwood_init_irq,
+        .init_irq       = orion_dt_init_irq,
         .timer          = &kirkwood_timer,
         .init_machine   = kirkwood_dt_init,
         .restart        = kirkwood_restart,
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
new file mode 100644
index 00000000000..413e2c8ef5f
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-goflexnet.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
+ *
+ * arch/arm/mach-kirkwood/board-goflexnet.c
+ *
+ * Seagate GoFlext Net Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Copied and modified for Seagate GoFlex Net support by
+ * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's
+ * GoFlex kernel patches.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int goflexnet_mpp_config[] __initdata = {
+        MPP29_GPIO,     /* USB Power Enable */
+        MPP47_GPIO,     /* LED Orange */
+        MPP46_GPIO,     /* LED Green */
+        MPP45_GPIO,     /* LED Left Capacity 3 */
+        MPP44_GPIO,     /* LED Left Capacity 2 */
+        MPP43_GPIO,     /* LED Left Capacity 1 */
+        MPP42_GPIO,     /* LED Left Capacity 0 */
+        MPP41_GPIO,     /* LED Right Capacity 3 */
+        MPP40_GPIO,     /* LED Right Capacity 2 */
+        MPP39_GPIO,     /* LED Right Capacity 1 */
+        MPP38_GPIO,     /* LED Right Capacity 0 */
+        0
+};
+
+void __init goflexnet_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(goflexnet_mpp_config);
+
+        if (gpio_request(29, "USB Power Enable") != 0 ||
+            gpio_direction_output(29, 1) != 0)
+                pr_err("can't setup GPIO 29 (USB Power Enable)\n");
+        kirkwood_ehci_init();
+
+        kirkwood_ge00_init(&goflexnet_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
index eddf1df8891..cfc47f80e73 100644
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ b/arch/arm/mach-kirkwood/board-ib62x0.c
@@ -18,9 +18,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
-#include <linux/gpio_keys.h>
 #include <linux/input.h>
-#include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -33,10 +31,6 @@ static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
 };
 
-static struct mv_sata_platform_data ib62x0_sata_data = {
-        .n_ports        = 2,
-};
-
 static unsigned int ib62x0_mpp_config[] __initdata = {
         MPP0_NF_IO2,
         MPP1_NF_IO3,
@@ -55,69 +49,6 @@ static unsigned int ib62x0_mpp_config[] __initdata = {
         0
 };
 
-static struct gpio_led ib62x0_led_pins[] = {
-        {
-                .name                   = "ib62x0:green:os",
-                .default_trigger        = "default-on",
-                .gpio                   = 25,
-                .active_low             = 0,
-        },
-        {
-                .name                   = "ib62x0:red:os",
-                .default_trigger        = "none",
-                .gpio                   = 22,
-                .active_low             = 0,
-        },
-        {
-                .name                   = "ib62x0:red:usb_copy",
-                .default_trigger        = "none",
-                .gpio                   = 27,
-                .active_low             = 0,
-        },
-};
-
-static struct gpio_led_platform_data ib62x0_led_data = {
-        .leds           = ib62x0_led_pins,
-        .num_leds       = ARRAY_SIZE(ib62x0_led_pins),
-};
-
-static struct platform_device ib62x0_led_device = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &ib62x0_led_data,
-        }
-};
-
-static struct gpio_keys_button ib62x0_button_pins[] = {
-        {
-                .code           = KEY_COPY,
-                .gpio           = 29,
-                .desc           = "USB Copy",
-                .active_low     = 1,
-        },
-        {
-                .code           = KEY_RESTART,
-                .gpio           = 28,
-                .desc           = "Reset",
-                .active_low     = 1,
-        },
-};
-
-static struct gpio_keys_platform_data ib62x0_button_data = {
-        .buttons        = ib62x0_button_pins,
-        .nbuttons       = ARRAY_SIZE(ib62x0_button_pins),
-};
-
-static struct platform_device ib62x0_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev            = {
-                .platform_data  = &ib62x0_button_data,
-        }
-};
-
 static void ib62x0_power_off(void)
 {
         gpio_set_value(IB62X0_GPIO_POWER_OFF, 1);
@@ -132,9 +63,6 @@ void __init ib62x0_init(void)
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&ib62x0_ge00_data);
-        kirkwood_sata_init(&ib62x0_sata_data);
-        platform_device_register(&ib62x0_led_device);
-        platform_device_register(&ib62x0_button_device);
         if (gpio_request(IB62X0_GPIO_POWER_OFF, "ib62x0:power:off") == 0 &&
             gpio_direction_output(IB62X0_GPIO_POWER_OFF, 0) == 0)
                 pm_power_off = ib62x0_power_off;
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index b0d3cc49269..d7a9198ed30 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -19,8 +19,6 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/i2c.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
 #include <asm/mach/arch.h>
@@ -32,50 +30,6 @@ static struct mv643xx_eth_platform_data iconnect_ge00_data = {
         .phy_addr       = MV643XX_ETH_PHY_ADDR(11),
 };
 
-static struct gpio_led iconnect_led_pins[] = {
-        {
-                .name           = "led_level",
-                .gpio           = 41,
-                .default_trigger = "default-on",
-        }, {
-                .name           = "power:blue",
-                .gpio           = 42,
-                .default_trigger = "timer",
-        }, {
-                .name           = "power:red",
-                .gpio           = 43,
-        }, {
-                .name           = "usb1:blue",
-                .gpio           = 44,
-        }, {
-                .name           = "usb2:blue",
-                .gpio           = 45,
-        }, {
-                .name           = "usb3:blue",
-                .gpio           = 46,
-        }, {
-                .name           = "usb4:blue",
-                .gpio           = 47,
-        }, {
-                .name           = "otb:blue",
-                .gpio           = 48,
-        },
-};
-
-static struct gpio_led_platform_data iconnect_led_data = {
-        .leds           = iconnect_led_pins,
-        .num_leds       = ARRAY_SIZE(iconnect_led_pins),
-        .gpio_blink_set = orion_gpio_led_blink_set,
-};
-
-static struct platform_device iconnect_leds = {
-        .name   = "leds-gpio",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &iconnect_led_data,
-        }
-};
-
 static unsigned int iconnect_mpp_config[] __initdata = {
         MPP12_GPIO,
         MPP35_GPIO,
@@ -90,12 +44,6 @@ static unsigned int iconnect_mpp_config[] __initdata = {
         0
 };
 
-static struct i2c_board_info __initdata iconnect_board_info[] = {
-        {
-                I2C_BOARD_INFO("lm63", 0x4c),
-        },
-};
-
 static struct mtd_partition iconnect_nand_parts[] = {
         {
                 .name = "flash",
@@ -142,15 +90,11 @@ void __init iconnect_init(void)
 {
         kirkwood_mpp_conf(iconnect_mpp_config);
         kirkwood_nand_init(ARRAY_AND_SIZE(iconnect_nand_parts), 25);
-        kirkwood_i2c_init();
-        i2c_register_board_info(0, iconnect_board_info,
-                ARRAY_SIZE(iconnect_board_info));
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&iconnect_ge00_data);
 
         platform_device_register(&iconnect_button_device);
-        platform_device_register(&iconnect_leds);
 }
 
 static int __init iconnect_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
new file mode 100644
index 00000000000..83d8975592f
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-lsxl.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright 2012 (C), Michael Walle <michael@walle.cc>
+ *
+ * arch/arm/mach-kirkwood/board-lsxl.c
+ *
+ * Buffalo Linkstation LS-XHL and LS-CHLv2 init for drivers not
+ * converted to flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/gpio.h>
+#include <linux/gpio-fan.h>
+#include <linux/input.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data lsxl_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct mv643xx_eth_platform_data lsxl_ge01_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+static unsigned int lsxl_mpp_config[] __initdata = {
+        MPP10_GPO,      /* HDD Power Enable */
+        MPP11_GPIO,     /* USB Vbus Enable */
+        MPP18_GPO,      /* FAN High Enable# */
+        MPP19_GPO,      /* FAN Low Enable# */
+        MPP36_GPIO,     /* Function Blue LED */
+        MPP37_GPIO,     /* Alarm LED */
+        MPP38_GPIO,     /* Info LED */
+        MPP39_GPIO,     /* Power LED */
+        MPP40_GPIO,     /* Fan Lock */
+        MPP41_GPIO,     /* Function Button */
+        MPP42_GPIO,     /* Power Switch */
+        MPP43_GPIO,     /* Power Auto Switch */
+        MPP48_GPIO,     /* Function Red LED */
+        0
+};
+
+#define LSXL_GPIO_FAN_HIGH      18
+#define LSXL_GPIO_FAN_LOW       19
+#define LSXL_GPIO_FAN_LOCK      40
+
+static struct gpio_fan_alarm lsxl_alarm = {
+        .gpio = LSXL_GPIO_FAN_LOCK,
+};
+
+static struct gpio_fan_speed lsxl_speeds[] = {
+        {
+                .rpm = 0,
+                .ctrl_val = 3,
+        }, {
+                .rpm = 1500,
+                .ctrl_val = 1,
+        }, {
+                .rpm = 3250,
+                .ctrl_val = 2,
+        }, {
+                .rpm = 5000,
+                .ctrl_val = 0,
+        }
+};
+
+static int lsxl_gpio_list[] = {
+        LSXL_GPIO_FAN_HIGH, LSXL_GPIO_FAN_LOW,
+};
+
+static struct gpio_fan_platform_data lsxl_fan_data = {
+        .num_ctrl = ARRAY_SIZE(lsxl_gpio_list),
+        .ctrl = lsxl_gpio_list,
+        .alarm = &lsxl_alarm,
+        .num_speed = ARRAY_SIZE(lsxl_speeds),
+        .speed = lsxl_speeds,
+};
+
+static struct platform_device lsxl_fan_device = {
+        .name = "gpio-fan",
+        .id = -1,
+        .num_resources = 0,
+        .dev = {
+                .platform_data = &lsxl_fan_data,
+        },
+};
+
+/*
+ * On the LS-XHL/LS-CHLv2, the shutdown process is following:
+ * - Userland monitors key events until the power switch goes to off position
+ * - The board reboots
+ * - U-boot starts and goes into an idle mode waiting for the user
+ *   to move the switch to ON position
+ *
+ */
+static void lsxl_power_off(void)
+{
+        kirkwood_restart('h', NULL);
+}
+
+#define LSXL_GPIO_HDD_POWER 10
+#define LSXL_GPIO_USB_POWER 11
+
+void __init lsxl_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(lsxl_mpp_config);
+
+        /* usb and sata power on */
+        gpio_set_value(LSXL_GPIO_USB_POWER, 1);
+        gpio_set_value(LSXL_GPIO_HDD_POWER, 1);
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&lsxl_ge00_data);
+        kirkwood_ge01_init(&lsxl_ge01_data);
+        platform_device_register(&lsxl_fan_device);
+
+        /* register power-off method */
+        pm_power_off = lsxl_power_off;
+}
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
new file mode 100644
index 00000000000..1750e68506c
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-ts219.c
@@ -0,0 +1,82 @@
+/*
+ *
+ * QNAP TS-11x/TS-21x Turbo NAS Board Setup via DT
+ *
+ * Copyright (C) 2012 Andrew Lunn <andrew@lunn.ch>
+ *
+ * Based on the board file ts219-setup.c:
+ *
+ * Copyright (C) 2009  Martin Michlmayr <tbm@cyrius.com>
+ * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+#include "tsx1x-common.h"
+
+static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+static unsigned int qnap_ts219_mpp_config[] __initdata = {
+        MPP0_SPI_SCn,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP4_SATA1_ACTn,
+        MPP5_SATA0_ACTn,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP13_UART1_TXD,        /* PIC controller */
+        MPP14_UART1_RXD,        /* PIC controller */
+        MPP15_GPIO,             /* USB Copy button (on devices with 88F6281) */
+        MPP16_GPIO,             /* Reset button (on devices with 88F6281) */
+        MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
+        MPP37_GPIO,             /* Reset button (on devices with 88F6282) */
+        MPP43_GPIO,             /* USB Copy button (on devices with 88F6282) */
+        MPP44_GPIO,             /* Board ID: 0: TS-11x, 1: TS-21x */
+        0
+};
+
+void __init qnap_dt_ts219_init(void)
+{
+        u32 dev, rev;
+
+        kirkwood_mpp_conf(qnap_ts219_mpp_config);
+
+        kirkwood_pcie_id(&dev, &rev);
+        if (dev == MV88F6282_DEV_ID)
+                qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+
+        kirkwood_ge00_init(&qnap_ts219_ge00_data);
+        kirkwood_ehci_init();
+
+        pm_power_off = qnap_tsx1x_power_off;
+}
+
+/* FIXME: Will not work with DT. Maybe use MPP40_GPIO? */
+static int __init ts219_pci_init(void)
+{
+        if (machine_is_ts219())
+                kirkwood_pcie_init(KW_PCIE0);
+
+        return 0;
+}
+subsys_initcall(ts219_pci_init);
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index f261cd24264..1201191d7f1 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -17,6 +17,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
+#include <linux/mv643xx_i2c.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -67,6 +68,14 @@ void __init kirkwood_map_io(void)
  * CLK tree
  ****************************************************************************/
 
+static void enable_sata0(void)
+{
+        /* Enable PLL and IVREF */
+        writel(readl(SATA0_PHY_MODE_2) | 0xf, SATA0_PHY_MODE_2);
+        /* Enable PHY */
+        writel(readl(SATA0_IF_CTRL) & ~0x200, SATA0_IF_CTRL);
+}
+
 static void disable_sata0(void)
 {
         /* Disable PLL and IVREF */
@@ -75,6 +84,14 @@ static void disable_sata0(void)
         writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
 }
 
+static void enable_sata1(void)
+{
+        /* Enable PLL and IVREF */
+        writel(readl(SATA1_PHY_MODE_2) | 0xf, SATA1_PHY_MODE_2);
+        /* Enable PHY */
+        writel(readl(SATA1_IF_CTRL) & ~0x200, SATA1_IF_CTRL);
+}
+
 static void disable_sata1(void)
 {
         /* Disable PLL and IVREF */
@@ -107,23 +124,38 @@ static void disable_pcie1(void)
         }
 }
 
-/* An extended version of the gated clk. This calls fn() before
- * disabling the clock. We use this to turn off PHYs etc. */
+/* An extended version of the gated clk. This calls fn_en()/fn_dis
+ * before enabling/disabling the clock.  We use this to turn on/off
+ * PHYs etc.  */
 struct clk_gate_fn {
         struct clk_gate gate;
-        void (*fn)(void);
+        void (*fn_en)(void);
+        void (*fn_dis)(void);
 };
 
 #define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate)
 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
 
+static int clk_gate_fn_enable(struct clk_hw *hw)
+{
+        struct clk_gate *gate = to_clk_gate(hw);
+        struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
+        int ret;
+
+        ret = clk_gate_ops.enable(hw);
+        if (!ret && gate_fn->fn_en)
+                gate_fn->fn_en();
+
+        return ret;
+}
+
 static void clk_gate_fn_disable(struct clk_hw *hw)
 {
         struct clk_gate *gate = to_clk_gate(hw);
         struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
 
-        if (gate_fn->fn)
-                gate_fn->fn();
+        if (gate_fn->fn_dis)
+                gate_fn->fn_dis();
 
         clk_gate_ops.disable(hw);
 }
@@ -135,7 +167,7 @@ static struct clk __init *clk_register_gate_fn(struct device *dev,
                 const char *parent_name, unsigned long flags,
                 void __iomem *reg, u8 bit_idx,
                 u8 clk_gate_flags, spinlock_t *lock,
-                void (*fn)(void))
+                void (*fn_en)(void), void (*fn_dis)(void))
 {
         struct clk_gate_fn *gate_fn;
         struct clk *clk;
@@ -159,11 +191,14 @@ static struct clk __init *clk_register_gate_fn(struct device *dev,
         gate_fn->gate.flags = clk_gate_flags;
         gate_fn->gate.lock = lock;
         gate_fn->gate.hw.init = &init;
-        gate_fn->fn = fn;
+        gate_fn->fn_en = fn_en;
+        gate_fn->fn_dis = fn_dis;
 
-        /* ops is the gate ops, but with our disable function */
-        if (clk_gate_fn_ops.disable != clk_gate_fn_disable) {
+        /* ops is the gate ops, but with our enable/disable functions */
+        if (clk_gate_fn_ops.enable != clk_gate_fn_enable ||
+            clk_gate_fn_ops.disable != clk_gate_fn_disable) {
                 clk_gate_fn_ops = clk_gate_ops;
+                clk_gate_fn_ops.enable = clk_gate_fn_enable;
                 clk_gate_fn_ops.disable = clk_gate_fn_disable;
         }
 
@@ -187,11 +222,12 @@ static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
 
 static struct clk __init *kirkwood_register_gate_fn(const char *name,
                                                     u8 bit_idx,
-                                                    void (*fn)(void))
+                                                    void (*fn_en)(void),
+                                                    void (*fn_dis)(void))
 {
         return clk_register_gate_fn(NULL, name, "tclk", 0,
                                     (void __iomem *)CLOCK_GATING_CTRL,
-                                    bit_idx, 0, &gating_lock, fn);
+                                    bit_idx, 0, &gating_lock, fn_en, fn_dis);
 }
 
 static struct clk *ge0, *ge1;
@@ -208,18 +244,18 @@ void __init kirkwood_clk_init(void)
         ge0 = kirkwood_register_gate("ge0",    CGC_BIT_GE0);
         ge1 = kirkwood_register_gate("ge1",    CGC_BIT_GE1);
         sata0 = kirkwood_register_gate_fn("sata0",  CGC_BIT_SATA0,
-                                          disable_sata0);
+                                          enable_sata0, disable_sata0);
         sata1 = kirkwood_register_gate_fn("sata1",  CGC_BIT_SATA1,
-                                          disable_sata1);
+                                          enable_sata1, disable_sata1);
         usb0 = kirkwood_register_gate("usb0",   CGC_BIT_USB0);
         sdio = kirkwood_register_gate("sdio",   CGC_BIT_SDIO);
         crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
         xor0 = kirkwood_register_gate("xor0",   CGC_BIT_XOR0);
         xor1 = kirkwood_register_gate("xor1",   CGC_BIT_XOR1);
         pex0 = kirkwood_register_gate_fn("pex0",   CGC_BIT_PEX0,
-                                         disable_pcie0);
+                                         NULL, disable_pcie0);
         pex1 = kirkwood_register_gate_fn("pex1",   CGC_BIT_PEX1,
-                                         disable_pcie1);
+                                         NULL, disable_pcie1);
         audio = kirkwood_register_gate("audio",  CGC_BIT_AUDIO);
         kirkwood_register_gate("tdm",    CGC_BIT_TDM);
         kirkwood_register_gate("tsu",    CGC_BIT_TSU);
@@ -241,6 +277,12 @@ void __init kirkwood_clk_init(void)
         orion_clkdev_add("0", "pcie", pex0);
         orion_clkdev_add("1", "pcie", pex1);
         orion_clkdev_add(NULL, "kirkwood-i2s", audio);
+        orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", runit);
+
+        /* Marvell says runit is used by SPI, UART, NAND, TWSI, ...,
+         * so should never be gated.
+         */
+        clk_prepare_enable(runit);
 }
 
 /*****************************************************************************
@@ -259,7 +301,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
         orion_ge00_init(eth_data,
                         GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
-                        IRQ_KIRKWOOD_GE00_ERR);
+                        IRQ_KIRKWOOD_GE00_ERR, 1600);
         /* The interface forgets the MAC address assigned by u-boot if
         the clock is turned off, so claim the clk now. */
         clk_prepare_enable(ge0);
@@ -273,7 +315,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
         orion_ge01_init(eth_data,
                         GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
-                        IRQ_KIRKWOOD_GE01_ERR);
+                        IRQ_KIRKWOOD_GE01_ERR, 1600);
         clk_prepare_enable(ge1);
 }
 
@@ -475,6 +517,13 @@ void __init kirkwood_wdt_init(void)
 void __init kirkwood_init_early(void)
 {
         orion_time_set_base(TIMER_VIRT_BASE);
+
+        /*
+         * Some Kirkwood devices allocate their coherent buffers from atomic
+         * context. Increase size of atomic coherent pool to make sure such
+         * the allocations won't fail.
+         */
+        init_dma_coherent_pool_size(SZ_1M);
 }
 
 int kirkwood_tclk;
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 9248fa2c165..304dd1abfdc 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -58,6 +58,11 @@ void dreamplug_init(void);
 #else
 static inline void dreamplug_init(void) {};
 #endif
+#ifdef CONFIG_MACH_TS219_DT
+void qnap_dt_ts219_init(void);
+#else
+static inline void qnap_dt_ts219_init(void) {};
+#endif
 
 #ifdef CONFIG_MACH_DLINK_KIRKWOOD_DT
 void dnskw_init(void);
@@ -77,6 +82,18 @@ void ib62x0_init(void);
 static inline void ib62x0_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_GOFLEXNET_DT
+void goflexnet_init(void);
+#else
+static inline void goflexnet_init(void) {};
+#endif
+
+#ifdef CONFIG_MACH_LSXL_DT
+void lsxl_init(void);
+#else
+static inline void lsxl_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index d9335937959..be90b7d0e10 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -10,6 +10,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/sizes.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/partitions.h>
 #include <linux/ata_platform.h>
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index c4c68e5b94f..720063ffa19 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -9,20 +9,23 @@
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/irq.h>
-#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/irq.h>
-#include "common.h"
 
-static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        BUG_ON(irq < IRQ_KIRKWOOD_GPIO_LOW_0_7);
-        BUG_ON(irq > IRQ_KIRKWOOD_GPIO_HIGH_16_23);
+static int __initdata gpio0_irqs[4] = {
+        IRQ_KIRKWOOD_GPIO_LOW_0_7,
+        IRQ_KIRKWOOD_GPIO_LOW_8_15,
+        IRQ_KIRKWOOD_GPIO_LOW_16_23,
+        IRQ_KIRKWOOD_GPIO_LOW_24_31,
+};
 
-        orion_gpio_irq_handler((irq - IRQ_KIRKWOOD_GPIO_LOW_0_7) << 3);
-}
+static int __initdata gpio1_irqs[4] = {
+        IRQ_KIRKWOOD_GPIO_HIGH_0_7,
+        IRQ_KIRKWOOD_GPIO_HIGH_8_15,
+        IRQ_KIRKWOOD_GPIO_HIGH_16_23,
+        0,
+};
 
 void __init kirkwood_init_irq(void)
 {
@@ -32,17 +35,8 @@ void __init kirkwood_init_irq(void)
         /*
          * Initialize gpiolib for GPIOs 0-49.
          */
-        orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
-                        IRQ_KIRKWOOD_GPIO_START);
-        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
-
-        orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
-                        IRQ_KIRKWOOD_GPIO_START + 32);
-        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23,
-                                gpio_irq_handler);
+        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0,
+                        IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
+        orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0,
+                        IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
 }
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
deleted file mode 100644
index e0b3eee8383..00000000000
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-if ARCH_LPC32XX
-
-menu "Individual UART enable selections"
-
-config ARCH_LPC32XX_UART3_SELECT
-        bool "Add support for standard UART3"
-        help
-         Adds support for standard UART 3 when the 8250 serial support
-         is enabled.
-
-config ARCH_LPC32XX_UART4_SELECT
-        bool "Add support for standard UART4"
-        help
-         Adds support for standard UART 4 when the 8250 serial support
-         is enabled.
-
-config ARCH_LPC32XX_UART5_SELECT
-        bool "Add support for standard UART5"
-        default y
-        help
-         Adds support for standard UART 5 when the 8250 serial support
-         is enabled.
-
-config ARCH_LPC32XX_UART6_SELECT
-        bool "Add support for standard UART6"
-        help
-         Adds support for standard UART 6 when the 8250 serial support
-         is enabled.
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
index 2cfe0ee635c..697323b5f92 100644
--- a/arch/arm/mach-lpc32xx/Makefile.boot
+++ b/arch/arm/mach-lpc32xx/Makefile.boot
@@ -2,3 +2,4 @@
 params_phys-y   := 0x80000100
 initrd_phys-y   := 0x82000000
 
+dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index f6a3ffec1f4..f48c2e961b8 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -607,6 +607,19 @@ static struct clk clk_dma = {
         .get_rate       = local_return_parent_rate,
 };
 
+static struct clk clk_pwm = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_PWM_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN |
+                          LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK |
+                          LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) |
+                          LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN |
+                          LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK |
+                          LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1),
+        .get_rate       = local_return_parent_rate,
+};
+
 static struct clk clk_uart3 = {
         .parent         = &clk_pclk,
         .enable         = local_onoff_enable,
@@ -691,10 +704,21 @@ static struct clk clk_nand = {
         .parent         = &clk_hclk,
         .enable         = local_onoff_enable,
         .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
-        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
+        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN |
+                          LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
         .get_rate       = local_return_parent_rate,
 };
 
+static struct clk clk_nand_mlc = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN |
+                          LPC32XX_CLKPWR_NANDCLK_DMA_INT |
+                          LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC,
+        .get_rate       = local_return_parent_rate,
+};
+
 static struct clk clk_i2s0 = {
         .parent         = &clk_hclk,
         .enable         = local_onoff_enable,
@@ -707,7 +731,8 @@ static struct clk clk_i2s1 = {
         .parent         = &clk_hclk,
         .enable         = local_onoff_enable,
         .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
-        .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
+        .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN |
+                          LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA,
         .get_rate       = local_return_parent_rate,
 };
 
@@ -727,14 +752,77 @@ static struct clk clk_rtc = {
         .get_rate       = local_return_parent_rate,
 };
 
+static int local_usb_enable(struct clk *clk, int enable)
+{
+        u32 tmp;
+
+        if (enable) {
+                /* Set up I2C pull levels */
+                tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
+                tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE;
+                __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
+        }
+
+        return local_onoff_enable(clk, enable);
+}
+
 static struct clk clk_usbd = {
         .parent         = &clk_usbpll,
-        .enable         = local_onoff_enable,
+        .enable         = local_usb_enable,
         .enable_reg     = LPC32XX_CLKPWR_USB_CTRL,
         .enable_mask    = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
         .get_rate       = local_return_parent_rate,
 };
 
+#define OTG_ALWAYS_MASK         (LPC32XX_USB_OTG_OTG_CLOCK_ON | \
+                                 LPC32XX_USB_OTG_I2C_CLOCK_ON)
+
+static int local_usb_otg_enable(struct clk *clk, int enable)
+{
+        int to = 1000;
+
+        if (enable) {
+                __raw_writel(clk->enable_mask, clk->enable_reg);
+
+                while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
+                        clk->enable_mask) != clk->enable_mask) && (to > 0))
+                        to--;
+        } else {
+                __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg);
+
+                while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
+                        OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0))
+                        to--;
+        }
+
+        if (to)
+                return 0;
+        else
+                return -1;
+}
+
+static struct clk clk_usb_otg_dev = {
+        .parent         = &clk_usbpll,
+        .enable         = local_usb_otg_enable,
+        .enable_reg     = LPC32XX_USB_OTG_CLK_CTRL,
+        .enable_mask    = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
+                          LPC32XX_USB_OTG_OTG_CLOCK_ON |
+                          LPC32XX_USB_OTG_DEV_CLOCK_ON |
+                          LPC32XX_USB_OTG_I2C_CLOCK_ON,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_usb_otg_host = {
+        .parent         = &clk_usbpll,
+        .enable         = local_usb_otg_enable,
+        .enable_reg     = LPC32XX_USB_OTG_CLK_CTRL,
+        .enable_mask    = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
+                          LPC32XX_USB_OTG_OTG_CLOCK_ON |
+                          LPC32XX_USB_OTG_HOST_CLOCK_ON |
+                          LPC32XX_USB_OTG_I2C_CLOCK_ON,
+        .get_rate       = local_return_parent_rate,
+};
+
 static int tsc_onoff_enable(struct clk *clk, int enable)
 {
         u32 tmp;
@@ -800,11 +888,17 @@ static int mmc_onoff_enable(struct clk *clk, int enable)
         u32 tmp;
 
         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
-                ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
+                ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
+                  LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN |
+                  LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS |
+                  LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS |
+                  LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS |
+                  LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS);
 
         /* If rate is 0, disable clock */
         if (enable != 0)
-                tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
+                tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
+                        LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
 
         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 
@@ -853,7 +947,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
 
 static int mmc_set_rate(struct clk *clk, unsigned long rate)
 {
-        u32 oldclk, tmp;
+        u32 tmp;
         unsigned long prate, div, crate = mmc_round_rate(clk, rate);
 
         prate = clk->parent->get_rate(clk->parent);
@@ -861,16 +955,12 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate)
         div = prate / crate;
 
         /* The MMC clock must be on when accessing an MMC register */
-        oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
-        __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
-                LPC32XX_CLKPWR_MS_CTRL);
         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
                 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
-        tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
+        tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) |
+                LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 
-        __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
-
         return 0;
 }
 
@@ -1111,6 +1201,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
         CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
         CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
+        CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
         CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
         CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
         CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
@@ -1120,8 +1211,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
         CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
         CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
-        CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
-        CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
+        CLKDEV_INIT("40050000.key", NULL, &clk_kscan),
+        CLKDEV_INIT("20020000.flash", NULL, &clk_nand),
+        CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc),
         CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
         CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
         CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
@@ -1130,6 +1222,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
         CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
         CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
+        CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd),
+        CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev),
+        CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host),
         CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
 };
 
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 5c96057b6d7..a48dc2dec48 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -26,6 +26,7 @@
 #include <linux/io.h>
 
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -224,7 +225,7 @@ void lpc23xx_restart(char mode, const char *cmd)
                 ;
 }
 
-static int __init lpc32xx_display_uid(void)
+static int __init lpc32xx_check_uid(void)
 {
         u32 uid[4];
 
@@ -233,6 +234,11 @@ static int __init lpc32xx_display_uid(void)
         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
                 uid[3], uid[2], uid[1], uid[0]);
 
+        if (!system_serial_low && !system_serial_high) {
+                system_serial_low = uid[0];
+                system_serial_high = uid[1];
+        }
+
         return 1;
 }
-arch_initcall(lpc32xx_display_uid);
+arch_initcall(lpc32xx_check_uid);
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
index 2ba6ca412be..0052e7a7617 100644
--- a/arch/arm/mach-lpc32xx/include/mach/gpio.h
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -3,6 +3,4 @@
 
 #include "gpio-lpc32xx.h"
 
-#define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX)
-
 #endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index c584f5bb164..acc4aabf1c7 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -694,4 +694,18 @@
 #define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
 #define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
 
+/*
+ * USB Otg Registers
+ */
+#define _OTGREG(x)                      io_p2v(LPC32XX_USB_OTG_BASE + (x))
+#define LPC32XX_USB_OTG_CLK_CTRL        _OTGREG(0xFF4)
+#define LPC32XX_USB_OTG_CLK_STAT        _OTGREG(0xFF8)
+
+/* USB OTG CLK CTRL bit defines */
+#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON  _BIT(4)
+#define LPC32XX_USB_OTG_OTG_CLOCK_ON    _BIT(3)
+#define LPC32XX_USB_OTG_I2C_CLOCK_ON    _BIT(2)
+#define LPC32XX_USB_OTG_DEV_CLOCK_ON    _BIT(1)
+#define LPC32XX_USB_OTG_HOST_CLOCK_ON   _BIT(0)
+
 #endif
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 540106cdb9e..b07dcc90829 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -30,12 +30,13 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/mmci.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/clk.h>
-#include <linux/amba/pl08x.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -50,9 +51,9 @@
 /*
  * Mapped GPIOLIB GPIOs
  */
-#define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
-#define LCD_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
-#define BKL_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
+#define LCD_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
+#define BKL_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
+#define MMC_PWR_ENABLE_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
 
 /*
  * AMBA LCD controller
@@ -158,24 +159,6 @@ static struct clcd_board lpc32xx_clcd_data = {
 /*
  * AMBA SSP (SPI)
  */
-static void phy3250_spi_cs_set(u32 control)
-{
-        gpio_set_value(SPI0_CS_GPIO, (int) control);
-}
-
-static struct pl022_config_chip spi0_chip_info = {
-        .com_mode               = INTERRUPT_TRANSFER,
-        .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
-        .hierarchy              = SSP_MASTER,
-        .slave_tx_disable       = 0,
-        .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
-        .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
-        .ctrl_len               = SSP_BITS_8,
-        .wait_state             = SSP_MWIRE_WAIT_ZERO,
-        .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
-        .cs_control             = phy3250_spi_cs_set,
-};
-
 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
         .bus_id                 = 0,
         .num_chipselect         = 1,
@@ -188,45 +171,56 @@ static struct pl022_ssp_controller lpc32xx_ssp1_data = {
         .enable_dma             = 0,
 };
 
-/* AT25 driver registration */
-static int __init phy3250_spi_board_register(void)
+static struct pl08x_channel_data pl08x_slave_channels[] = {
+        {
+                .bus_id = "nand-slc",
+                .min_signal = 1, /* SLC NAND Flash */
+                .max_signal = 1,
+                .periph_buses = PL08X_AHB1,
+        },
+        {
+                .bus_id = "nand-mlc",
+                .min_signal = 12, /* MLC NAND Flash */
+                .max_signal = 12,
+                .periph_buses = PL08X_AHB1,
+        },
+};
+
+static int pl08x_get_signal(const struct pl08x_channel_data *cd)
+{
+        return cd->min_signal;
+}
+
+static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
 {
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-        static struct spi_board_info info[] = {
-                {
-                        .modalias = "spidev",
-                        .max_speed_hz = 5000000,
-                        .bus_num = 0,
-                        .chip_select = 0,
-                        .controller_data = &spi0_chip_info,
-                },
-        };
-
-#else
-        static struct spi_eeprom eeprom = {
-                .name = "at25256a",
-                .byte_len = 0x8000,
-                .page_size = 64,
-                .flags = EE_ADDR2,
-        };
-
-        static struct spi_board_info info[] = {
-                {
-                        .modalias = "at25",
-                        .max_speed_hz = 5000000,
-                        .bus_num = 0,
-                        .chip_select = 0,
-                        .mode = SPI_MODE_0,
-                        .platform_data = &eeprom,
-                        .controller_data = &spi0_chip_info,
-                },
-        };
-#endif
-        return spi_register_board_info(info, ARRAY_SIZE(info));
 }
-arch_initcall(phy3250_spi_board_register);
 
 static struct pl08x_platform_data pl08x_pd = {
+        .slave_channels = &pl08x_slave_channels[0],
+        .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
+        .get_signal = pl08x_get_signal,
+        .put_signal = pl08x_put_signal,
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+};
+
+static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
+{
+        /* Only on and off are supported */
+        if (ios->power_mode == MMC_POWER_OFF)
+                gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
+        else
+                gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
+        return 0;
+}
+
+static struct mmci_platform_data lpc32xx_mmci_data = {
+        .ocr_mask       = MMC_VDD_30_31 | MMC_VDD_31_32 |
+                          MMC_VDD_32_33 | MMC_VDD_33_34,
+        .ios_handler    = mmc_handle_ios,
+        .dma_filter     = NULL,
+        /* No DMA for now since AMBA PL080 dmaengine driver only does scatter
+         * gather, and the MMCI driver doesn't do it this way */
 };
 
 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
@@ -234,6 +228,8 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
         OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
         OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
+        OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
+                       &lpc32xx_mmci_data),
         { }
 };
 
@@ -241,10 +237,6 @@ static void __init lpc3250_machine_init(void)
 {
         u32 tmp;
 
-        /* Setup SLC NAND controller muxing */
-        __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
-                LPC32XX_CLKPWR_NAND_CLK_CTRL);
-
         /* Setup LCD muxing to RGB565 */
         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
@@ -252,47 +244,8 @@ static void __init lpc3250_machine_init(void)
         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
 
-        /* Set up USB power */
-        tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
-        tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
-                LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
-        __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
-
-        /* Set up I2C pull levels */
-        tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
-        tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
-                LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
-        __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
-
-        /* Disable IrDA pulsing support on UART6 */
-        tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
-        tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
-        __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
-
-        /* Enable DMA for I2S1 channel */
-        tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
-        tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
-        __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
-
         lpc32xx_serial_init();
 
-        /*
-         * AMBA peripheral clocks need to be enabled prior to AMBA device
-         * detection or a data fault will occur, so enable the clocks
-         * here.
-         */
-        tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
-        __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
-                LPC32XX_CLKPWR_LCDCLK_CTRL);
-
-        tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
-        __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
-                LPC32XX_CLKPWR_SSP_CLK_CTRL);
-
-        tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
-        __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
-                     LPC32XX_CLKPWR_DMA_CLK_CTRL);
-
         /* Test clock needed for UDA1380 initial init */
         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
                 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
@@ -302,12 +255,10 @@ static void __init lpc3250_machine_init(void)
                              lpc32xx_auxdata_lookup, NULL);
 
         /* Register GPIOs used on this board */
-        if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
-                printk(KERN_ERR "Error requesting gpio %u",
-                        SPI0_CS_GPIO);
-        else if (gpio_direction_output(SPI0_CS_GPIO, 1))
-                printk(KERN_ERR "Error setting gpio %u to output",
-                        SPI0_CS_GPIO);
+        if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
+                pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
+        else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
+                pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
 }
 
 static char const *lpc32xx_dt_compat[] __initdata = {
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index f2735281616..05621a29fba 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -31,59 +31,6 @@
 
 #define LPC32XX_SUART_FIFO_SIZE 64
 
-/* Standard 8250/16550 compatible serial ports */
-static struct plat_serial8250_port serial_std_platform_data[] = {
-#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
-        {
-                .membase        = io_p2v(LPC32XX_UART5_BASE),
-                .mapbase        = LPC32XX_UART5_BASE,
-                .irq            = IRQ_LPC32XX_UART_IIR5,
-                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM32,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
-                                        UPF_SKIP_TEST,
-        },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
-        {
-                .membase        = io_p2v(LPC32XX_UART3_BASE),
-                .mapbase        = LPC32XX_UART3_BASE,
-                .irq            = IRQ_LPC32XX_UART_IIR3,
-                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM32,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
-                                        UPF_SKIP_TEST,
-        },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
-        {
-                .membase        = io_p2v(LPC32XX_UART4_BASE),
-                .mapbase        = LPC32XX_UART4_BASE,
-                .irq            = IRQ_LPC32XX_UART_IIR4,
-                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM32,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
-                                        UPF_SKIP_TEST,
-        },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
-        {
-                .membase        = io_p2v(LPC32XX_UART6_BASE),
-                .mapbase        = LPC32XX_UART6_BASE,
-                .irq            = IRQ_LPC32XX_UART_IIR6,
-                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM32,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
-                                        UPF_SKIP_TEST,
-        },
-#endif
-        { },
-};
-
 struct uartinit {
         char *uart_ck_name;
         u32 ck_mode_mask;
@@ -92,7 +39,6 @@ struct uartinit {
 };
 
 static struct uartinit uartinit_data[] __initdata = {
-#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
         {
                 .uart_ck_name = "uart5_ck",
                 .ck_mode_mask =
@@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] __initdata = {
                 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
                 .mapbase = LPC32XX_UART5_BASE,
         },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
         {
                 .uart_ck_name = "uart3_ck",
                 .ck_mode_mask =
@@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] __initdata = {
                 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
                 .mapbase = LPC32XX_UART3_BASE,
         },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
         {
                 .uart_ck_name = "uart4_ck",
                 .ck_mode_mask =
@@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] __initdata = {
                 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
                 .mapbase = LPC32XX_UART4_BASE,
         },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
         {
                 .uart_ck_name = "uart6_ck",
                 .ck_mode_mask =
@@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] __initdata = {
                 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
                 .mapbase = LPC32XX_UART6_BASE,
         },
-#endif
-};
-
-static struct platform_device serial_std_platform_device = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = serial_std_platform_data,
-        },
-};
-
-static struct platform_device *lpc32xx_serial_devs[] __initdata = {
-        &serial_std_platform_device,
 };
 
 void __init lpc32xx_serial_init(void)
@@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void)
                 clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
                 if (!IS_ERR(clk)) {
                         clk_enable(clk);
-                        serial_std_platform_data[i].uartclk =
-                                clk_get_rate(clk);
                 }
 
-                /* Fall back on main osc rate if clock rate return fails */
-                if (serial_std_platform_data[i].uartclk == 0)
-                        serial_std_platform_data[i].uartclk =
-                                LPC32XX_MAIN_OSC_FREQ;
-
                 /* Setup UART clock modes for all UARTs, disable autoclock */
                 clkmodes |= uartinit_data[i].ck_mode_mask;
 
@@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void)
         __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
         for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
                 /* Force a flush of the RX FIFOs to work around a HW bug */
-                puart = serial_std_platform_data[i].mapbase;
+                puart = uartinit_data[i].mapbase;
                 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
                 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
                 j = LPC32XX_SUART_FIFO_SIZE;
@@ -198,11 +118,13 @@ void __init lpc32xx_serial_init(void)
                 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
         }
 
+        /* Disable IrDA pulsing support on UART6 */
+        tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
+        tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
+        __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
+
         /* Disable UART5->USB transparent mode or USB won't work */
         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
-
-        platform_add_devices(lpc32xx_serial_devs,
-                ARRAY_SIZE(lpc32xx_serial_devs));
 }
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index f516e74ce0d..5c3d61ee729 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -14,6 +14,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
+#include <mach/irqs.h>
 #include <mach/pxa168.h>
 #include <mach/mfp-pxa168.h>
 
diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c
index 4304f951937..7e8a5a2e1ec 100644
--- a/arch/arm/mach-mmp/sram.c
+++ b/arch/arm/mach-mmp/sram.c
@@ -68,7 +68,7 @@ static int __devinit sram_probe(struct platform_device *pdev)
         struct resource *res;
         int ret = 0;
 
-        if (!pdata && !pdata->pool_name)
+        if (!pdata || !pdata->pool_name)
                 return -ENODEV;
 
         info = kzalloc(sizeof(*info), GFP_KERNEL);
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index db0117ec55f..e012dc8391c 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -127,7 +127,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * the boot monitor to read the system wide flags register,
          * and branch to the address found there.
          */
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        gic_raise_softirq(cpumask_of(cpu), 0);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 62b53d710ef..a9bc84180d2 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -37,7 +37,7 @@
 #define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
 #define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
 
-static void __init __iomem *win_cfg_base(int win)
+static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
         /*
          * Find the control register base address for this window.
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index b4c53b846c9..3057f7d4329 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -213,7 +213,8 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
         orion_ge00_init(eth_data,
                         GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
-                        IRQ_MV78XX0_GE_ERR);
+                        IRQ_MV78XX0_GE_ERR,
+                        MV643XX_TX_CSUM_DEFAULT_LIMIT);
 }
 
 
@@ -224,7 +225,8 @@ void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
         orion_ge01_init(eth_data,
                         GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
-                        NO_IRQ);
+                        NO_IRQ,
+                        MV643XX_TX_CSUM_DEFAULT_LIMIT);
 }
 
 
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index e421b701663..eff9a750bbe 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -9,19 +9,17 @@
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
 #include <linux/irq.h>
 #include <mach/bridge-regs.h>
 #include <plat/irq.h>
 #include "common.h"
 
-static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        BUG_ON(irq < IRQ_MV78XX0_GPIO_0_7 || irq > IRQ_MV78XX0_GPIO_24_31);
-
-        orion_gpio_irq_handler((irq - IRQ_MV78XX0_GPIO_0_7) << 3);
-}
+static int __initdata gpio0_irqs[4] = {
+        IRQ_MV78XX0_GPIO_0_7,
+        IRQ_MV78XX0_GPIO_8_15,
+        IRQ_MV78XX0_GPIO_16_23,
+        IRQ_MV78XX0_GPIO_24_31,
+};
 
 void __init mv78xx0_init_irq(void)
 {
@@ -34,11 +32,7 @@ void __init mv78xx0_init_irq(void)
          * registers for core #1 are at an offset of 0x18 from those of
          * core #0.)
          */
-        orion_gpio_init(0, 32, GPIO_VIRT_BASE,
+        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE,
                         mv78xx0_core_index() ? 0x18 : 0,
-                        IRQ_MV78XX0_GPIO_START);
-        irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
+                        IRQ_MV78XX0_GPIO_START, gpio0_irqs);
 }
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
new file mode 100644
index 00000000000..caa2c5e734f
--- /dev/null
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -0,0 +1,16 @@
+if ARCH_MVEBU
+
+menu "Marvell SOC with device tree"
+
+config MACH_ARMADA_370_XP
+        bool "Marvell Armada 370 and Aramada XP boards"
+        select ARMADA_370_XP_TIMER
+        select CPU_V7
+        help
+
+          Say 'Y' here if you want your kernel to support boards based on
+          Marvell Armada 370 or Armada XP with device tree.
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
new file mode 100644
index 00000000000..e61d2b8fdf5
--- /dev/null
+++ b/arch/arm/mach-mvebu/Makefile
@@ -0,0 +1,2 @@
+obj-y += system-controller.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
diff --git a/arch/arm/mach-mvebu/Makefile.boot b/arch/arm/mach-mvebu/Makefile.boot
new file mode 100644
index 00000000000..2579a2fc233
--- /dev/null
+++ b/arch/arm/mach-mvebu/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-db.dtb
+dtb-$(CONFIG_MACH_ARMADA_370_XP) += armada-xp-db.dtb
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
new file mode 100644
index 00000000000..4ef923b032e
--- /dev/null
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -0,0 +1,63 @@
+/*
+ * Device Tree support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+#include <linux/time-armada-370-xp.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/armada-370-xp.h>
+#include "common.h"
+
+static struct map_desc armada_370_xp_io_desc[] __initdata = {
+        {
+                .virtual        = ARMADA_370_XP_REGS_VIRT_BASE,
+                .pfn            = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
+                .length         = ARMADA_370_XP_REGS_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+void __init armada_370_xp_map_io(void)
+{
+        iotable_init(armada_370_xp_io_desc, ARRAY_SIZE(armada_370_xp_io_desc));
+}
+
+struct sys_timer armada_370_xp_timer = {
+        .init           = armada_370_xp_timer_init,
+};
+
+static void __init armada_370_xp_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static const char * const armada_370_xp_dt_board_dt_compat[] = {
+        "marvell,a370-db",
+        "marvell,axp-db",
+        NULL,
+};
+
+DT_MACHINE_START(ARMADA_XP_DT, "Marvell Aramada 370/XP (Device Tree)")
+        .init_machine   = armada_370_xp_dt_init,
+        .map_io         = armada_370_xp_map_io,
+        .init_irq       = armada_370_xp_init_irq,
+        .handle_irq     = armada_370_xp_handle_irq,
+        .timer          = &armada_370_xp_timer,
+        .restart        = mvebu_restart,
+        .dt_compat      = armada_370_xp_dt_board_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
new file mode 100644
index 00000000000..02f89eaa25f
--- /dev/null
+++ b/arch/arm/mach-mvebu/common.h
@@ -0,0 +1,23 @@
+/*
+ * Core functions for Marvell System On Chip
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ARCH_MVEBU_COMMON_H
+#define __ARCH_MVEBU_COMMON_H
+
+void mvebu_restart(char mode, const char *cmd);
+
+void armada_370_xp_init_irq(void);
+void armada_370_xp_handle_irq(struct pt_regs *regs);
+
+#endif
diff --git a/arch/arm/mach-mvebu/include/mach/armada-370-xp.h b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
new file mode 100644
index 00000000000..25f0ca8d782
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/armada-370-xp.h
@@ -0,0 +1,22 @@
+/*
+ * Generic definitions for Marvell Armada_370_XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_ARMADA_370_XP_H
+#define __MACH_ARMADA_370_XP_H
+
+#define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
+#define ARMADA_370_XP_REGS_VIRT_BASE    0xfeb00000
+#define ARMADA_370_XP_REGS_SIZE         SZ_1M
+
+#endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/include/mach/debug-macro.S b/arch/arm/mach-mvebu/include/mach/debug-macro.S
new file mode 100644
index 00000000000..22825760c7e
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/debug-macro.S
@@ -0,0 +1,24 @@
+/*
+ * Early serial output macro for Marvell  SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory Clement <gregory.clement@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <mach/armada-370-xp.h>
+
+        .macro  addruart, rp, rv, tmp
+        ldr     \rp, =ARMADA_370_XP_REGS_PHYS_BASE
+        ldr     \rv, =ARMADA_370_XP_REGS_VIRT_BASE
+        orr     \rp, \rp, #0x00012000
+        orr     \rv, \rv, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-mvebu/include/mach/timex.h b/arch/arm/mach-mvebu/include/mach/timex.h
new file mode 100644
index 00000000000..ab324a3748f
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/timex.h
@@ -0,0 +1,13 @@
+/*
+ * Marvell Armada SoC time definitions
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
diff --git a/arch/arm/mach-mvebu/include/mach/uncompress.h b/arch/arm/mach-mvebu/include/mach/uncompress.h
new file mode 100644
index 00000000000..d6a100ccf30
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/uncompress.h
@@ -0,0 +1,43 @@
+/*
+ * Marvell Armada SoC kernel uncompression UART routines
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <mach/armada-370-xp.h>
+
+#define UART_THR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
+                                                                + 0x12000))
+#define UART_LSR ((volatile unsigned char *)(ARMADA_370_XP_REGS_PHYS_BASE\
+                                                                + 0x12014))
+
+#define LSR_THRE        0x20
+
+static void putc(const char c)
+{
+        int i;
+
+        for (i = 0; i < 0x1000; i++) {
+                /* Transmit fifo not full? */
+                if (*UART_LSR & LSR_THRE)
+                        break;
+        }
+
+        *UART_THR = c;
+}
+
+static void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-mvebu/irq-armada-370-xp.c b/arch/arm/mach-mvebu/irq-armada-370-xp.c
new file mode 100644
index 00000000000..5f5f9394b6b
--- /dev/null
+++ b/arch/arm/mach-mvebu/irq-armada-370-xp.c
@@ -0,0 +1,133 @@
+/*
+ * Marvell Armada 370 and Armada XP SoC IRQ handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Ben Dooks <ben.dooks@codethink.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <asm/mach/arch.h>
+#include <asm/exception.h>
+
+/* Interrupt Controller Registers Map */
+#define ARMADA_370_XP_INT_SET_MASK_OFFS         (0x48)
+#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS       (0x4C)
+
+#define ARMADA_370_XP_INT_CONTROL               (0x00)
+#define ARMADA_370_XP_INT_SET_ENABLE_OFFS       (0x30)
+#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS     (0x34)
+
+#define ARMADA_370_XP_CPU_INTACK_OFFS           (0x44)
+
+static void __iomem *per_cpu_int_base;
+static void __iomem *main_int_base;
+static struct irq_domain *armada_370_xp_mpic_domain;
+
+static void armada_370_xp_irq_mask(struct irq_data *d)
+{
+        writel(irqd_to_hwirq(d),
+               per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
+}
+
+static void armada_370_xp_irq_unmask(struct irq_data *d)
+{
+        writel(irqd_to_hwirq(d),
+               per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
+}
+
+static struct irq_chip armada_370_xp_irq_chip = {
+        .name           = "armada_370_xp_irq",
+        .irq_mask       = armada_370_xp_irq_mask,
+        .irq_mask_ack   = armada_370_xp_irq_mask,
+        .irq_unmask     = armada_370_xp_irq_unmask,
+};
+
+static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
+                                      unsigned int virq, irq_hw_number_t hw)
+{
+        armada_370_xp_irq_mask(irq_get_irq_data(virq));
+        writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
+
+        irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
+                                 handle_level_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+        return 0;
+}
+
+static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
+        .map = armada_370_xp_mpic_irq_map,
+        .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init armada_370_xp_mpic_of_init(struct device_node *node,
+                                             struct device_node *parent)
+{
+        u32 control;
+
+        main_int_base = of_iomap(node, 0);
+        per_cpu_int_base = of_iomap(node, 1);
+
+        BUG_ON(!main_int_base);
+        BUG_ON(!per_cpu_int_base);
+
+        control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
+
+        armada_370_xp_mpic_domain =
+            irq_domain_add_linear(node, (control >> 2) & 0x3ff,
+                                  &armada_370_xp_mpic_irq_ops, NULL);
+
+        if (!armada_370_xp_mpic_domain)
+                panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
+
+        irq_set_default_host(armada_370_xp_mpic_domain);
+        return 0;
+}
+
+asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
+                                                               *regs)
+{
+        u32 irqstat, irqnr;
+
+        do {
+                irqstat = readl_relaxed(per_cpu_int_base +
+                                        ARMADA_370_XP_CPU_INTACK_OFFS);
+                irqnr = irqstat & 0x3FF;
+
+                if (irqnr < 1023) {
+                        irqnr =
+                            irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
+                        handle_IRQ(irqnr, regs);
+                        continue;
+                }
+
+                break;
+        } while (1);
+}
+
+static const struct of_device_id mpic_of_match[] __initconst = {
+        {.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
+        {},
+};
+
+void __init armada_370_xp_init_irq(void)
+{
+        of_irq_init(mpic_of_match);
+}
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
new file mode 100644
index 00000000000..b8079df8c98
--- /dev/null
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -0,0 +1,105 @@
+/*
+ * System controller support for Armada 370 and XP platforms.
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * The Armada 370 and Armada XP SoCs both have a range of
+ * miscellaneous registers, that do not belong to a particular device,
+ * but rather provide system-level features. This basic
+ * system-controller driver provides a device tree binding for those
+ * registers, and implements utility functions offering various
+ * features related to those registers.
+ *
+ * For now, the feature set is limited to restarting the platform by a
+ * soft-reset, but it might be extended in the future.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+
+static void __iomem *system_controller_base;
+
+struct mvebu_system_controller {
+        u32 rstoutn_mask_offset;
+        u32 system_soft_reset_offset;
+
+        u32 rstoutn_mask_reset_out_en;
+        u32 system_soft_reset;
+};
+static struct mvebu_system_controller *mvebu_sc;
+
+const struct mvebu_system_controller armada_370_xp_system_controller = {
+        .rstoutn_mask_offset = 0x60,
+        .system_soft_reset_offset = 0x64,
+        .rstoutn_mask_reset_out_en = 0x1,
+        .system_soft_reset = 0x1,
+};
+
+const struct mvebu_system_controller orion_system_controller = {
+        .rstoutn_mask_offset = 0x108,
+        .system_soft_reset_offset = 0x10c,
+        .rstoutn_mask_reset_out_en = 0x4,
+        .system_soft_reset = 0x1,
+};
+
+static struct of_device_id of_system_controller_table[] = {
+        {
+                .compatible = "marvell,orion-system-controller",
+                .data = (void *) &orion_system_controller,
+        }, {
+                .compatible = "marvell,armada-370-xp-system-controller",
+                .data = (void *) &armada_370_xp_system_controller,
+        },
+        { /* end of list */ },
+};
+
+void mvebu_restart(char mode, const char *cmd)
+{
+        if (!system_controller_base) {
+                pr_err("Cannot restart, system-controller not available: check the device tree\n");
+        } else {
+                /*
+                 * Enable soft reset to assert RSTOUTn.
+                 */
+                writel(mvebu_sc->rstoutn_mask_reset_out_en,
+                        system_controller_base +
+                        mvebu_sc->rstoutn_mask_offset);
+                /*
+                 * Assert soft reset.
+                 */
+                writel(mvebu_sc->system_soft_reset,
+                        system_controller_base +
+                        mvebu_sc->system_soft_reset_offset);
+        }
+
+        while (1)
+                ;
+}
+
+static int __init mvebu_system_controller_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, of_system_controller_table);
+        if (np) {
+                const struct of_device_id *match =
+                    of_match_node(of_system_controller_table, np);
+                BUG_ON(!match);
+                system_controller_base = of_iomap(np, 0);
+                mvebu_sc = (struct mvebu_system_controller *)match->data;
+        }
+
+        return 0;
+}
+
+arch_initcall(mvebu_system_controller_init);
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 91cf0625819..9a8bbda195b 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -2,9 +2,6 @@ if ARCH_MXS
 
 source "arch/arm/mach-mxs/devices/Kconfig"
 
-config MXS_OCOTP
-        bool
-
 config SOC_IMX23
         bool
         select ARM_AMBA
@@ -16,6 +13,7 @@ config SOC_IMX28
         bool
         select ARM_AMBA
         select CPU_ARM926T
+        select HAVE_CAN_FLEXCAN if CAN
         select HAVE_PWM
         select PINCTRL_IMX28
 
@@ -65,7 +63,6 @@ config MACH_MX28EVK
         select MXS_HAVE_PLATFORM_MXS_SAIF
         select MXS_HAVE_PLATFORM_MXS_I2C
         select MXS_HAVE_PLATFORM_RTC_STMP3XXX
-        select MXS_OCOTP
         help
           Include support for MX28EVK platform. This includes specific
           configurations for the board and its peripherals.
@@ -93,7 +90,6 @@ config MODULE_M28
         select MXS_HAVE_PLATFORM_MXS_I2C
         select MXS_HAVE_PLATFORM_MXS_MMC
         select MXS_HAVE_PLATFORM_MXSFB
-        select MXS_OCOTP
 
 config MODULE_APX4
         bool
@@ -105,7 +101,6 @@ config MODULE_APX4
         select MXS_HAVE_PLATFORM_MXS_I2C
         select MXS_HAVE_PLATFORM_MXS_MMC
         select MXS_HAVE_PLATFORM_MXS_SAIF
-        select MXS_OCOTP
 
 config MACH_TX28
         bool "Ka-Ro TX28 module"
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index e41590ccb43..fed3695a133 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,7 +1,6 @@
 # Common support
-obj-y := devices.o icoll.o iomux.o system.o timer.o mm.o
+obj-y := devices.o icoll.o iomux.o ocotp.o system.o timer.o mm.o
 
-obj-$(CONFIG_MXS_OCOTP) += ocotp.o
 obj-$(CONFIG_PM) += pm.o
 
 obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
index 07b11fe6453..4582999cf08 100644
--- a/arch/arm/mach-mxs/Makefile.boot
+++ b/arch/arm/mach-mxs/Makefile.boot
@@ -1 +1,10 @@
 zreladdr-y += 0x40008000
+
+dtb-y += imx23-evk.dtb \
+         imx23-olinuxino.dtb \
+         imx23-stmp378x_devb.dtb \
+         imx28-apx4devkit.dtb \
+         imx28-cfa10036.dtb \
+         imx28-evk.dtb \
+         imx28-m28evk.dtb \
+         imx28-tx28.dtb \
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 9acdd638704..9ee5cede3d4 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -10,7 +10,7 @@
  */
 #include <mach/mx23.h>
 #include <mach/devices-common.h>
-#include <mach/mxsfb.h>
+#include <linux/mxsfb.h>
 #include <linux/amba/bus.h>
 
 static inline int mx23_add_duart(void)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 84b2960df11..fcab431060f 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -10,7 +10,7 @@
  */
 #include <mach/mx28.h>
 #include <mach/devices-common.h>
-#include <mach/mxsfb.h>
+#include <linux/mxsfb.h>
 #include <linux/amba/bus.h>
 
 static inline int mx28_add_duart(void)
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
index 5a75b7180f7..76b53f73418 100644
--- a/arch/arm/mach-mxs/devices/platform-mxsfb.c
+++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c
@@ -10,7 +10,7 @@
 #include <mach/mx23.h>
 #include <mach/mx28.h>
 #include <mach/devices-common.h>
-#include <mach/mxsfb.h>
+#include <linux/mxsfb.h>
 
 #ifdef CONFIG_SOC_IMX23
 struct platform_device *__init mx23_add_mxsfb(
diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h
deleted file mode 100644
index e4d79791515..00000000000
--- a/arch/arm/mach-mxs/include/mach/mxsfb.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_FB_H
-#define __MACH_FB_H
-
-#include <linux/fb.h>
-
-#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */
-#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
-#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
-#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
-
-#define FB_SYNC_DATA_ENABLE_HIGH_ACT    (1 << 6)
-#define FB_SYNC_DOTCLK_FAILING_ACT      (1 << 7) /* failing/negtive edge sampling */
-
-struct mxsfb_platform_data {
-        struct fb_videomode *mode_list;
-        unsigned mode_count;
-
-        unsigned default_bpp;
-
-        unsigned dotclk_delay;  /* refer manual HW_LCDIF_VDCTRL4 register */
-        unsigned ld_intf_width; /* refer STMLCDIF_* macros */
-
-        unsigned fb_size;       /* Size of the video memory. If zero a
-                                 * default will be used
-                                 */
-        unsigned long fb_phys;  /* physical address for the video memory. If
-                                 * zero the framebuffer memory will be dynamically
-                                 * allocated. If specified,fb_size must also be specified.
-                                 * fb_phys must be unused by Linux.
-                                 */
-};
-
-#endif /* __MACH_FB_H */
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 8cac94b3302..8dabfe81d07 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -16,12 +16,95 @@
 #include <linux/init.h>
 #include <linux/init.h>
 #include <linux/irqdomain.h>
+#include <linux/micrel_phy.h>
+#include <linux/mxsfb.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/phy.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
 
+static struct fb_videomode mx23evk_video_modes[] = {
+        {
+                .name           = "Samsung-LMS430HF02",
+                .refresh        = 60,
+                .xres           = 480,
+                .yres           = 272,
+                .pixclock       = 108096, /* picosecond (9.2 MHz) */
+                .left_margin    = 15,
+                .right_margin   = 8,
+                .upper_margin   = 12,
+                .lower_margin   = 4,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                  FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
+
+static struct fb_videomode mx28evk_video_modes[] = {
+        {
+                .name           = "Seiko-43WVF1G",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = 29851, /* picosecond (33.5 MHz) */
+                .left_margin    = 89,
+                .right_margin   = 164,
+                .upper_margin   = 23,
+                .lower_margin   = 10,
+                .hsync_len      = 10,
+                .vsync_len      = 10,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                  FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
+
+static struct fb_videomode m28evk_video_modes[] = {
+        {
+                .name           = "Ampire AM-800480R2TMQW-T01H",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = 30066, /* picosecond (33.26 MHz) */
+                .left_margin    = 0,
+                .right_margin   = 256,
+                .upper_margin   = 0,
+                .lower_margin   = 45,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+        },
+};
+
+static struct fb_videomode apx4devkit_video_modes[] = {
+        {
+                .name           = "HannStar PJ70112A",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = 33333, /* picosecond (30.00 MHz) */
+                .left_margin    = 88,
+                .right_margin   = 40,
+                .upper_margin   = 32,
+                .lower_margin   = 13,
+                .hsync_len      = 48,
+                .vsync_len      = 3,
+                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
+                                  FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                  FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
+
+static struct mxsfb_platform_data mxsfb_pdata __initdata;
+
+static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+        OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+        { /* sentinel */ }
+};
+
 static int __init mxs_icoll_add_irq_domain(struct device_node *np,
                                 struct device_node *interrupt_parent)
 {
@@ -71,33 +154,151 @@ static struct sys_timer imx28_timer = {
         .init = imx28_timer_init,
 };
 
-static void __init imx28_evk_init(void)
+enum mac_oui {
+        OUI_FSL,
+        OUI_DENX,
+};
+
+static void __init update_fec_mac_prop(enum mac_oui oui)
+{
+        struct device_node *np, *from = NULL;
+        struct property *newmac;
+        const u32 *ocotp = mxs_get_ocotp();
+        u8 *macaddr;
+        u32 val;
+        int i;
+
+        for (i = 0; i < 2; i++) {
+                np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
+                if (!np)
+                        return;
+                from = np;
+
+                newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
+                if (!newmac)
+                        return;
+                newmac->value = newmac + 1;
+                newmac->length = 6;
+
+                newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
+                if (!newmac->name) {
+                        kfree(newmac);
+                        return;
+                }
+
+                /*
+                 * OCOTP only stores the last 4 octets for each mac address,
+                 * so hard-code OUI here.
+                 */
+                macaddr = newmac->value;
+                switch (oui) {
+                case OUI_FSL:
+                        macaddr[0] = 0x00;
+                        macaddr[1] = 0x04;
+                        macaddr[2] = 0x9f;
+                        break;
+                case OUI_DENX:
+                        macaddr[0] = 0xc0;
+                        macaddr[1] = 0xe5;
+                        macaddr[2] = 0x4e;
+                        break;
+                }
+                val = ocotp[i];
+                macaddr[3] = (val >> 16) & 0xff;
+                macaddr[4] = (val >> 8) & 0xff;
+                macaddr[5] = (val >> 0) & 0xff;
+
+                prom_update_property(np, newmac);
+        }
+}
+
+static void __init imx23_evk_init(void)
+{
+        mxsfb_pdata.mode_list = mx23evk_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes);
+        mxsfb_pdata.default_bpp = 32;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+}
+
+static inline void enable_clk_enet_out(void)
 {
-        struct clk *clk;
+        struct clk *clk = clk_get_sys("enet_out", NULL);
 
-        /* Enable fec phy clock */
-        clk = clk_get_sys("enet_out", NULL);
         if (!IS_ERR(clk))
                 clk_prepare_enable(clk);
 }
 
+static void __init imx28_evk_init(void)
+{
+        enable_clk_enet_out();
+        update_fec_mac_prop(OUI_FSL);
+
+        mxsfb_pdata.mode_list = mx28evk_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
+        mxsfb_pdata.default_bpp = 32;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+}
+
+static void __init m28evk_init(void)
+{
+        enable_clk_enet_out();
+        update_fec_mac_prop(OUI_DENX);
+
+        mxsfb_pdata.mode_list = m28evk_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
+        mxsfb_pdata.default_bpp = 16;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
+}
+
+static int apx4devkit_phy_fixup(struct phy_device *phy)
+{
+        phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
+        return 0;
+}
+
+static void __init apx4devkit_init(void)
+{
+        enable_clk_enet_out();
+
+        if (IS_BUILTIN(CONFIG_PHYLIB))
+                phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
+                                           apx4devkit_phy_fixup);
+
+        mxsfb_pdata.mode_list = apx4devkit_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes);
+        mxsfb_pdata.default_bpp = 32;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+}
+
 static void __init mxs_machine_init(void)
 {
         if (of_machine_is_compatible("fsl,imx28-evk"))
                 imx28_evk_init();
+        else if (of_machine_is_compatible("fsl,imx23-evk"))
+                imx23_evk_init();
+        else if (of_machine_is_compatible("denx,m28evk"))
+                m28evk_init();
+        else if (of_machine_is_compatible("bluegiga,apx4devkit"))
+                apx4devkit_init();
 
         of_platform_populate(NULL, of_default_bus_match_table,
-                                NULL, NULL);
+                             mxs_auxdata_lookup, NULL);
 }
 
 static const char *imx23_dt_compat[] __initdata = {
         "fsl,imx23-evk",
+        "fsl,stmp378x_devb"
+        "olimex,imx23-olinuxino",
         "fsl,imx23",
         NULL,
 };
 
 static const char *imx28_dt_compat[] __initdata = {
+        "bluegiga,apx4devkit",
+        "crystalfontz,cfa10036",
+        "denx,m28evk",
         "fsl,imx28-evk",
+        "karo,tx28",
         "fsl,imx28",
         NULL,
 };
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
index 9a7b08b2a92..0f71f82101c 100644
--- a/arch/arm/mach-mxs/module-tx28.c
+++ b/arch/arm/mach-mxs/module-tx28.c
@@ -11,7 +11,7 @@
 #include <linux/gpio.h>
 
 #include <mach/iomux-mx28.h>
-#include "../devices-mx28.h"
+#include "devices-mx28.h"
 
 #include "module-tx28.h"
 
diff --git a/arch/arm/mach-netx/fb.c b/arch/arm/mach-netx/fb.c
index 2cdf6ef69be..d122ee6ab99 100644
--- a/arch/arm/mach-netx/fb.c
+++ b/arch/arm/mach-netx/fb.c
@@ -69,29 +69,6 @@ void netx_clcd_remove(struct clcd_fb *fb)
                               fb->fb.screen_base, fb->fb.fix.smem_start);
 }
 
-void clk_disable(struct clk *clk)
-{
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        return 0;
-}
-
-int clk_enable(struct clk *clk)
-{
-        return 0;
-}
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        return dev && strcmp(dev_name(dev), "fb") == 0 ? NULL : ERR_PTR(-ENOENT);
-}
-
-void clk_put(struct clk *clk)
-{
-}
-
 static AMBA_AHB_DEVICE(fb, "fb", 0, 0x00104000, { NETX_IRQ_LCD }, NULL);
 
 int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel)
diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile
index a6bbd1a7b4e..a42c9a33d3b 100644
--- a/arch/arm/mach-nomadik/Makefile
+++ b/arch/arm/mach-nomadik/Makefile
@@ -7,8 +7,6 @@
 
 # Object file lists.
 
-obj-y                   += clock.o
-
 # Cpu revision
 obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o
 
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 2e8d3e176bc..f4535a7dadf 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -14,12 +14,14 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/mmci.h>
 #include <linux/interrupt.h>
 #include <linux/gpio.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/i2c.h>
 #include <linux/io.h>
 #include <asm/hardware/vic.h>
 #include <asm/sizes.h>
@@ -185,16 +187,28 @@ static void __init nhk8815_onenand_init(void)
 #endif
 }
 
-static AMBA_APB_DEVICE(uart0, "uart0", 0, NOMADIK_UART0_BASE,
-        { IRQ_UART0 }, NULL);
+static struct mmci_platform_data mmcsd_plat_data = {
+        .ocr_mask = MMC_VDD_29_30,
+        .f_max = 48000000,
+        .gpio_wp = -1,
+        .gpio_cd = 111,
+        .cd_invert = true,
+        .capabilities = MMC_CAP_MMC_HIGHSPEED |
+        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
+};
 
-static AMBA_APB_DEVICE(uart1, "uart1", 0, NOMADIK_UART1_BASE,
-        { IRQ_UART1 }, NULL);
+static int __init nhk8815_mmcsd_init(void)
+{
+        int ret;
 
-static struct amba_device *amba_devs[] __initdata = {
-        &uart0_device,
-        &uart1_device,
-};
+        ret = gpio_request(112, "card detect bias");
+        if (ret)
+                return ret;
+        gpio_direction_output(112, 0);
+        amba_apb_device_add(NULL, "mmci", NOMADIK_SDI_BASE, SZ_4K, IRQ_SDMMC, 0, &mmcsd_plat_data, 0x10180180);
+        return 0;
+}
+module_init(nhk8815_mmcsd_init);
 
 static struct resource nhk8815_eth_resources[] = {
         {
@@ -253,17 +267,46 @@ static struct sys_timer nomadik_timer = {
         .init   = nomadik_timer_init,
 };
 
+static struct i2c_board_info __initdata nhk8815_i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("stw4811", 0x2d),
+        },
+};
+
+static struct i2c_board_info __initdata nhk8815_i2c1_devices[] = {
+        {
+                I2C_BOARD_INFO("camera", 0x10),
+        },
+        {
+                I2C_BOARD_INFO("stw5095", 0x1a),
+        },
+        {
+                I2C_BOARD_INFO("lis3lv02dl", 0x1d),
+        },
+};
+
+static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
+        {
+                I2C_BOARD_INFO("stw4811-usb", 0x2d),
+        },
+};
+
 static void __init nhk8815_platform_init(void)
 {
-        int i;
-
         cpu8815_platform_init();
         nhk8815_onenand_init();
         platform_add_devices(nhk8815_platform_devices,
                              ARRAY_SIZE(nhk8815_platform_devices));
 
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
+        amba_apb_device_add(NULL, "uart0", NOMADIK_UART0_BASE, SZ_4K, IRQ_UART0, 0, NULL, 0);
+        amba_apb_device_add(NULL, "uart1", NOMADIK_UART1_BASE, SZ_4K, IRQ_UART1, 0, NULL, 0);
+
+        i2c_register_board_info(0, nhk8815_i2c0_devices,
+                                ARRAY_SIZE(nhk8815_i2c0_devices));
+        i2c_register_board_info(1, nhk8815_i2c1_devices,
+                                ARRAY_SIZE(nhk8815_i2c1_devices));
+        i2c_register_board_info(2, nhk8815_i2c2_devices,
+                                ARRAY_SIZE(nhk8815_i2c2_devices));
 }
 
 MACHINE_START(NOMADIK, "NHK8815")
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c
deleted file mode 100644
index 48a59f24e10..00000000000
--- a/arch/arm/mach-nomadik/clock.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- *  linux/arch/arm/mach-nomadik/clock.c
- *
- *  Copyright (C) 2009 Alessandro Rubini
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include "clock.h"
-
-/*
- * The nomadik board uses generic clocks, but the serial pl011 file
- * calls clk_enable(), clk_disable(), clk_get_rate(), so we provide them
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/* enable and disable do nothing */
-int clk_enable(struct clk *clk)
-{
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-static struct clk clk_24 = {
-        .rate = 2400000,
-};
-
-static struct clk clk_48 = {
-        .rate = 48 * 1000 * 1000,
-};
-
-/*
- * Catch-all default clock to satisfy drivers using the clk API.  We don't
- * model the actual hardware clocks yet.
- */
-static struct clk clk_default;
-
-#define CLK(_clk, dev)                          \
-        {                                       \
-                .clk            = _clk,         \
-                .dev_id         = dev,          \
-        }
-
-static struct clk_lookup lookups[] = {
-        {
-                .con_id         = "apb_pclk",
-                .clk            = &clk_default,
-        },
-        CLK(&clk_24, "mtu0"),
-        CLK(&clk_24, "mtu1"),
-        CLK(&clk_48, "uart0"),
-        CLK(&clk_48, "uart1"),
-        CLK(&clk_default, "gpio.0"),
-        CLK(&clk_default, "gpio.1"),
-        CLK(&clk_default, "gpio.2"),
-        CLK(&clk_default, "gpio.3"),
-        CLK(&clk_default, "rng"),
-};
-
-int __init clk_init(void)
-{
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-        return 0;
-}
diff --git a/arch/arm/mach-nomadik/clock.h b/arch/arm/mach-nomadik/clock.h
deleted file mode 100644
index 78da2e7c398..00000000000
--- a/arch/arm/mach-nomadik/clock.h
+++ /dev/null
@@ -1,15 +0,0 @@
-
-/*
- *  linux/arch/arm/mach-nomadik/clock.h
- *
- *  Copyright (C) 2009 Alessandro Rubini
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-struct clk {
-        unsigned long           rate;
-};
-
-int __init clk_init(void);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 27f43a46985..6fd8e46567a 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -22,6 +22,10 @@
 #include <linux/amba/bus.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_data/clk-nomadik.h>
 
 #include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
@@ -32,91 +36,63 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 
-#include "clock.h"
 #include "cpu-8815.h"
 
-#define __MEM_4K_RESOURCE(x) \
-        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
-
 /* The 8815 has 4 GPIO blocks, let's register them immediately */
-
-#define GPIO_RESOURCE(block)                                            \
-        {                                                               \
-                .start  = NOMADIK_GPIO##block##_BASE,                   \
-                .end    = NOMADIK_GPIO##block##_BASE + SZ_4K - 1,       \
-                .flags  = IORESOURCE_MEM,                               \
-        },                                                              \
-        {                                                               \
-                .start  = IRQ_GPIO##block,                              \
-                .end    = IRQ_GPIO##block,                              \
-                .flags  = IORESOURCE_IRQ,                               \
-        }
-
-#define GPIO_DEVICE(block)                                              \
-        {                                                               \
-                .name           = "gpio",                               \
-                .id             = block,                                \
-                .num_resources  = 2,                                    \
-                .resource       = &cpu8815_gpio_resources[block * 2],   \
-                .dev = {                                                \
-                        .platform_data = &cpu8815_gpio[block],          \
-                },                                                      \
-        }
-
-static struct nmk_gpio_platform_data cpu8815_gpio[] = {
-        {
-                .name = "GPIO-0-31",
-                .first_gpio = 0,
-                .first_irq = NOMADIK_GPIO_TO_IRQ(0),
-        }, {
-                .name = "GPIO-32-63",
-                .first_gpio = 32,
-                .first_irq = NOMADIK_GPIO_TO_IRQ(32),
-        }, {
-                .name = "GPIO-64-95",
-                .first_gpio = 64,
-                .first_irq = NOMADIK_GPIO_TO_IRQ(64),
-        }, {
-                .name = "GPIO-96-127", /* 124..127 not routed to pin */
-                .first_gpio = 96,
-                .first_irq = NOMADIK_GPIO_TO_IRQ(96),
-        }
+static resource_size_t __initdata cpu8815_gpio_base[] = {
+        NOMADIK_GPIO0_BASE,
+        NOMADIK_GPIO1_BASE,
+        NOMADIK_GPIO2_BASE,
+        NOMADIK_GPIO3_BASE,
 };
 
-static struct resource cpu8815_gpio_resources[] = {
-        GPIO_RESOURCE(0),
-        GPIO_RESOURCE(1),
-        GPIO_RESOURCE(2),
-        GPIO_RESOURCE(3),
-};
-
-static struct platform_device cpu8815_platform_gpio[] = {
-        GPIO_DEVICE(0),
-        GPIO_DEVICE(1),
-        GPIO_DEVICE(2),
-        GPIO_DEVICE(3),
-};
+static struct platform_device *
+cpu8815_add_gpio(int id, resource_size_t addr, int irq,
+                 struct nmk_gpio_platform_data *pdata)
+{
+        struct resource resources[] = {
+                {
+                        .start  = addr,
+                        .end    = addr + 127,
+                        .flags  = IORESOURCE_MEM,
+                },
+                {
+                        .start  = irq,
+                        .end    = irq,
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        return platform_device_register_resndata(NULL, "gpio", id,
+                                resources, ARRAY_SIZE(resources),
+                                pdata, sizeof(*pdata));
+}
 
-static AMBA_APB_DEVICE(cpu8815_amba_rng, "rng", 0, NOMADIK_RNG_BASE, { }, NULL);
+void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
+                       struct nmk_gpio_platform_data *pdata)
+{
+        int first = 0;
+        int i;
 
-static struct platform_device *platform_devs[] __initdata = {
-        cpu8815_platform_gpio + 0,
-        cpu8815_platform_gpio + 1,
-        cpu8815_platform_gpio + 2,
-        cpu8815_platform_gpio + 3,
-};
+        for (i = 0; i < num; i++, first += 32, irq++) {
+                pdata->first_gpio = first;
+                pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
+                pdata->num_gpio = 32;
 
-static struct amba_device *amba_devs[] __initdata = {
-        &cpu8815_amba_rng_device
-};
+                cpu8815_add_gpio(i, base[i], irq, pdata);
+        }
+}
 
 static int __init cpu8815_init(void)
 {
-        int i;
-
-        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
+        struct nmk_gpio_platform_data pdata = {
+                /* No custom data yet */
+        };
+
+        cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
+                          IRQ_GPIO0, &pdata);
+        amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
+        amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
         return 0;
 }
 arch_initcall(cpu8815_init);
@@ -147,7 +123,7 @@ void __init cpu8815_init_irq(void)
          * Init clocks here so that they are available for system timer
          * initialization.
          */
-        clk_init();
+        nomadik_clk_init();
 }
 
 /*
diff --git a/arch/arm/mach-nomadik/i2c-8815nhk.c b/arch/arm/mach-nomadik/i2c-8815nhk.c
index 0fc2f6f1cc9..6d14454d460 100644
--- a/arch/arm/mach-nomadik/i2c-8815nhk.c
+++ b/arch/arm/mach-nomadik/i2c-8815nhk.c
@@ -5,6 +5,7 @@
 #include <linux/i2c-gpio.h>
 #include <linux/platform_device.h>
 #include <plat/gpio-nomadik.h>
+#include <plat/pincfg.h>
 
 /*
  * There are two busses in the 8815NHK.
@@ -12,19 +13,27 @@
  * use bit-bang through GPIO by now, to keep things simple
  */
 
+/* I2C0 connected to the STw4811 power management chip */
 static struct i2c_gpio_platform_data nhk8815_i2c_data0 = {
         /* keep defaults for timeouts; pins are push-pull bidirectional */
         .scl_pin = 62,
         .sda_pin = 63,
 };
 
+/* I2C1 connected to various sensors */
 static struct i2c_gpio_platform_data nhk8815_i2c_data1 = {
         /* keep defaults for timeouts; pins are push-pull bidirectional */
         .scl_pin = 53,
         .sda_pin = 54,
 };
 
-/* first bus: GPIO XX and YY */
+/* I2C2 connected to the USB portions of the STw4811 only */
+static struct i2c_gpio_platform_data nhk8815_i2c_data2 = {
+        /* keep defaults for timeouts; pins are push-pull bidirectional */
+        .scl_pin = 73,
+        .sda_pin = 74,
+};
+
 static struct platform_device nhk8815_i2c_dev0 = {
         .name   = "i2c-gpio",
         .id     = 0,
@@ -32,7 +41,7 @@ static struct platform_device nhk8815_i2c_dev0 = {
                 .platform_data = &nhk8815_i2c_data0,
         },
 };
-/* second bus: GPIO XX and YY */
+
 static struct platform_device nhk8815_i2c_dev1 = {
         .name   = "i2c-gpio",
         .id     = 1,
@@ -41,15 +50,29 @@ static struct platform_device nhk8815_i2c_dev1 = {
         },
 };
 
+static struct platform_device nhk8815_i2c_dev2 = {
+        .name   = "i2c-gpio",
+        .id     = 2,
+        .dev    = {
+                .platform_data = &nhk8815_i2c_data2,
+        },
+};
+
+static pin_cfg_t cpu8815_pins_i2c[] = {
+        PIN_CFG_INPUT(62, GPIO, PULLUP),
+        PIN_CFG_INPUT(63, GPIO, PULLUP),
+        PIN_CFG_INPUT(53, GPIO, PULLUP),
+        PIN_CFG_INPUT(54, GPIO, PULLUP),
+        PIN_CFG_INPUT(73, GPIO, PULLUP),
+        PIN_CFG_INPUT(74, GPIO, PULLUP),
+};
+
 static int __init nhk8815_i2c_init(void)
 {
-        nmk_gpio_set_mode(nhk8815_i2c_data0.scl_pin, NMK_GPIO_ALT_GPIO);
-        nmk_gpio_set_mode(nhk8815_i2c_data0.sda_pin, NMK_GPIO_ALT_GPIO);
+        nmk_config_pins(cpu8815_pins_i2c, ARRAY_SIZE(cpu8815_pins_i2c));
         platform_device_register(&nhk8815_i2c_dev0);
-
-        nmk_gpio_set_mode(nhk8815_i2c_data1.scl_pin, NMK_GPIO_ALT_GPIO);
-        nmk_gpio_set_mode(nhk8815_i2c_data1.sda_pin, NMK_GPIO_ALT_GPIO);
         platform_device_register(&nhk8815_i2c_dev1);
+        platform_device_register(&nhk8815_i2c_dev2);
 
         return 0;
 }
@@ -58,6 +81,7 @@ static void __exit nhk8815_i2c_exit(void)
 {
         platform_device_unregister(&nhk8815_i2c_dev0);
         platform_device_unregister(&nhk8815_i2c_dev1);
+        platform_device_unregister(&nhk8815_i2c_dev2);
         return;
 }
 
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h
index 8faabc56039..a118e615f86 100644
--- a/arch/arm/mach-nomadik/include/mach/irqs.h
+++ b/arch/arm/mach-nomadik/include/mach/irqs.h
@@ -22,56 +22,56 @@
 
 #include <mach/hardware.h>
 
-#define IRQ_VIC_START           0       /* first VIC interrupt is 0 */
+#define IRQ_VIC_START           1       /* first VIC interrupt is 1 */
 
 /*
  * Interrupt numbers generic for all Nomadik Chip cuts
  */
-#define IRQ_WATCHDOG                    0
-#define IRQ_SOFTINT                     1
-#define IRQ_CRYPTO                      2
-#define IRQ_OWM                         3
-#define IRQ_MTU0                        4
-#define IRQ_MTU1                        5
-#define IRQ_GPIO0                       6
-#define IRQ_GPIO1                       7
-#define IRQ_GPIO2                       8
-#define IRQ_GPIO3                       9
-#define IRQ_RTC_RTT                     10
-#define IRQ_SSP                         11
-#define IRQ_UART0                       12
-#define IRQ_DMA1                        13
-#define IRQ_CLCD_MDIF                   14
-#define IRQ_DMA0                        15
-#define IRQ_PWRFAIL                     16
-#define IRQ_UART1                       17
-#define IRQ_FIRDA                       18
-#define IRQ_MSP0                        19
-#define IRQ_I2C0                        20
-#define IRQ_I2C1                        21
-#define IRQ_SDMMC                       22
-#define IRQ_USBOTG                      23
-#define IRQ_SVA_IT0                     24
-#define IRQ_SVA_IT1                     25
-#define IRQ_SAA_IT0                     26
-#define IRQ_SAA_IT1                     27
-#define IRQ_UART2                       28
-#define IRQ_MSP2                        31
-#define IRQ_L2CC                        48
-#define IRQ_HPI                         49
-#define IRQ_SKE                         50
-#define IRQ_KP                          51
-#define IRQ_MEMST                       54
-#define IRQ_SGA_IT                      58
-#define IRQ_USBM                        60
-#define IRQ_MSP1                        62
+#define IRQ_WATCHDOG                    1
+#define IRQ_SOFTINT                     2
+#define IRQ_CRYPTO                      3
+#define IRQ_OWM                         4
+#define IRQ_MTU0                        5
+#define IRQ_MTU1                        6
+#define IRQ_GPIO0                       7
+#define IRQ_GPIO1                       8
+#define IRQ_GPIO2                       9
+#define IRQ_GPIO3                       10
+#define IRQ_RTC_RTT                     11
+#define IRQ_SSP                         12
+#define IRQ_UART0                       13
+#define IRQ_DMA1                        14
+#define IRQ_CLCD_MDIF                   15
+#define IRQ_DMA0                        16
+#define IRQ_PWRFAIL                     17
+#define IRQ_UART1                       18
+#define IRQ_FIRDA                       19
+#define IRQ_MSP0                        20
+#define IRQ_I2C0                        21
+#define IRQ_I2C1                        22
+#define IRQ_SDMMC                       23
+#define IRQ_USBOTG                      24
+#define IRQ_SVA_IT0                     25
+#define IRQ_SVA_IT1                     26
+#define IRQ_SAA_IT0                     27
+#define IRQ_SAA_IT1                     28
+#define IRQ_UART2                       29
+#define IRQ_MSP2                        30
+#define IRQ_L2CC                        49
+#define IRQ_HPI                         50
+#define IRQ_SKE                         51
+#define IRQ_KP                          52
+#define IRQ_MEMST                       55
+#define IRQ_SGA_IT                      59
+#define IRQ_USBM                        61
+#define IRQ_MSP1                        63
 
-#define NOMADIK_SOC_NR_IRQS             64
+#define NOMADIK_GPIO_OFFSET             (IRQ_VIC_START+64)
 
 /* After chip-specific IRQ numbers we have the GPIO ones */
 #define NOMADIK_NR_GPIO                 128 /* last 4 not wired to pins */
-#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + NOMADIK_SOC_NR_IRQS)
-#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - NOMADIK_SOC_NR_IRQS)
+#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + NOMADIK_GPIO_OFFSET)
+#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - NOMADIK_GPIO_OFFSET)
 #define NR_IRQS                         NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
 
 /* Following two are used by entry_macro.S, to access our dual-vic */
@@ -79,4 +79,3 @@
 #define VIC_REG_IRQSR1          0x20
 
 #endif /* __ASM_ARCH_IRQS_H */
-
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index f2f8a584701..c53469802c0 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -37,12 +37,12 @@
 #include <plat/board-ams-delta.h>
 #include <plat/keypad.h>
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/board.h>
 
 #include <mach/hardware.h>
 #include <mach/ams-delta-fiq.h>
 #include <mach/camera.h>
+#include <mach/usb.h>
 
 #include "iomap.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index e75e2d55a2d..6ec385e2b98 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -23,8 +23,10 @@
 #include <asm/mach/map.h>
 
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/board.h>
+
+#include <mach/usb.h>
+
 #include "common.h"
 
 /* assume no Mini-AB port */
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c
index da0e37d4082..e1362ce4849 100644
--- a/arch/arm/mach-omap1/board-h2-mmc.c
+++ b/arch/arm/mach-omap1/board-h2-mmc.c
@@ -54,7 +54,6 @@ static struct omap_mmc_platform_data mmc1_data = {
         .nr_slots                       = 1,
         .init                           = mmc_late_init,
         .cleanup                        = mmc_cleanup,
-        .dma_mask                       = 0xffffffff,
         .slots[0]       = {
                 .set_power              = mmc_set_power,
                 .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index a28e989a63f..44a4ab195fb 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -40,11 +40,11 @@
 #include <plat/dma.h>
 #include <plat/tc.h>
 #include <plat/irda.h>
-#include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/flash.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 #include "board-h2.h"
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c
index f8242aa9b76..c74daace8cd 100644
--- a/arch/arm/mach-omap1/board-h3-mmc.c
+++ b/arch/arm/mach-omap1/board-h3-mmc.c
@@ -36,7 +36,6 @@ static int mmc_set_power(struct device *dev, int slot, int power_on,
  */
 static struct omap_mmc_platform_data mmc1_data = {
         .nr_slots                       = 1,
-        .dma_mask                       = 0xffffffff,
         .slots[0]       = {
                 .set_power              = mmc_set_power,
                 .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 108a8640fc6..86cb5a04a40 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -40,13 +40,13 @@
 
 #include <plat/mux.h>
 #include <plat/tc.h>
-#include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/dma.h>
 #include <plat/flash.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#include <mach/usb.h>
 
 #include "common.h"
 #include "board-h3.h"
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 118a9d4a4c5..b3f6e943e66 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -44,10 +44,10 @@
 #include <plat/omap7xx.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
-#include <plat/usb.h>
 #include <plat/mmc.h>
 
 #include <mach/irqs.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 7970223a559..f21c2966daa 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -35,11 +35,11 @@
 #include <plat/flash.h>
 #include <plat/fpga.h>
 #include <plat/tc.h>
-#include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/mmc.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "iomap.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 7212ae97f44..2c0ca8fc338 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/lcd_mipid.h>
@@ -34,6 +33,7 @@
 #include <plat/clock.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
@@ -185,7 +185,6 @@ static int nokia770_mmc_get_cover_state(struct device *dev, int slot)
 
 static struct omap_mmc_platform_data nokia770_mmc2_data = {
         .nr_slots                       = 1,
-        .dma_mask                       = 0xffffffff,
         .max_freq                       = 12000000,
         .slots[0]       = {
                 .set_power              = nokia770_mmc_set_power,
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index da8d872d3d1..8784705edb6 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -45,11 +45,11 @@
 #include <asm/mach/map.h>
 
 #include <plat/flash.h>
-#include <plat/usb.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 949b62a7369..26bcb9defcd 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -35,7 +35,6 @@
 
 #include <plat/flash.h>
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/tc.h>
 #include <plat/dma.h>
 #include <plat/board.h>
@@ -43,6 +42,7 @@
 #include <plat/keypad.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 7f1e1cf2bf4..4d099446dfa 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -35,7 +35,6 @@
 #include <plat/led.h>
 #include <plat/flash.h>
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
 #include <plat/board.h>
@@ -43,6 +42,7 @@
 #include <plat/keypad.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 3c71c6bace2..355980321c2 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -37,7 +37,6 @@
 
 #include <plat/flash.h>
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
 #include <plat/board.h>
@@ -45,6 +44,7 @@
 #include <plat/keypad.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
@@ -288,8 +288,7 @@ palmz71_gpio_setup(int early)
                 }
                 gpio_direction_input(PALMZ71_USBDETECT_GPIO);
                 if (request_irq(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
-                                palmz71_powercable, IRQF_SAMPLE_RANDOM,
-                                "palmz71-cable", NULL))
+                                palmz71_powercable, 0, "palmz71-cable", NULL))
                         printk(KERN_ERR
                                         "IRQ request for power cable failed!\n");
                 palmz71_powercable(gpio_to_irq(PALMZ71_USBDETECT_GPIO), NULL);
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 3b7b82b1368..8c665bd16ac 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -37,13 +37,13 @@
 #include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/irda.h>
-#include <plat/usb.h>
 #include <plat/tc.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/board-sx1.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index afd67f0ec49..3497769eb35 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -35,9 +35,10 @@
 #include <plat/flash.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
-#include <plat/usb.h>
+#include <plat/board.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index c6ce93f71d0..c007d80dfb6 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -25,10 +25,11 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/clkdev_omap.h>
+#include <plat/board.h>
 #include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
-#include <plat/usb.h>   /* for OTG_BASE */
 
 #include <mach/hardware.h>
+#include <mach/usb.h>   /* for OTG_BASE */
 
 #include "iomap.h"
 #include "clock.h"
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h
new file mode 100644
index 00000000000..753cd5ce694
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/usb.h
@@ -0,0 +1,165 @@
+/*
+ * FIXME correct answer depends on hmc_mode,
+ * as does (on omap1) any nonzero value for config->otg port number
+ */
+#ifdef  CONFIG_USB_GADGET_OMAP
+#define is_usb0_device(config)  1
+#else
+#define is_usb0_device(config)  0
+#endif
+
+struct omap_usb_config {
+        /* Configure drivers according to the connectors on your board:
+         *  - "A" connector (rectagular)
+         *      ... for host/OHCI use, set "register_host".
+         *  - "B" connector (squarish) or "Mini-B"
+         *      ... for device/gadget use, set "register_dev".
+         *  - "Mini-AB" connector (very similar to Mini-B)
+         *      ... for OTG use as device OR host, initialize "otg"
+         */
+        unsigned        register_host:1;
+        unsigned        register_dev:1;
+        u8              otg;    /* port number, 1-based:  usb1 == 2 */
+
+        u8              hmc_mode;
+
+        /* implicitly true if otg:  host supports remote wakeup? */
+        u8              rwc;
+
+        /* signaling pins used to talk to transceiver on usbN:
+         *  0 == usbN unused
+         *  2 == usb0-only, using internal transceiver
+         *  3 == 3 wire bidirectional
+         *  4 == 4 wire bidirectional
+         *  6 == 6 wire unidirectional (or TLL)
+         */
+        u8              pins[3];
+
+        struct platform_device *udc_device;
+        struct platform_device *ohci_device;
+        struct platform_device *otg_device;
+
+        u32 (*usb0_init)(unsigned nwires, unsigned is_device);
+        u32 (*usb1_init)(unsigned nwires);
+        u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
+
+        int (*ocpi_enable)(void);
+};
+
+void omap_otg_init(struct omap_usb_config *config);
+
+#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
+void omap1_usb_init(struct omap_usb_config *pdata);
+#else
+static inline void omap1_usb_init(struct omap_usb_config *pdata)
+{
+}
+#endif
+
+#define OMAP1_OTG_BASE                  0xfffb0400
+#define OMAP1_UDC_BASE                  0xfffb4000
+#define OMAP1_OHCI_BASE                 0xfffba000
+
+#define OMAP2_OHCI_BASE                 0x4805e000
+#define OMAP2_UDC_BASE                  0x4805e200
+#define OMAP2_OTG_BASE                  0x4805e300
+#define OTG_BASE                        OMAP1_OTG_BASE
+#define UDC_BASE                        OMAP1_UDC_BASE
+#define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
+
+/*
+ * OTG and transceiver registers, for OMAPs starting with ARM926
+ */
+#define OTG_REV                         (OTG_BASE + 0x00)
+#define OTG_SYSCON_1                    (OTG_BASE + 0x04)
+#       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
+#       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
+#       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
+#       define   OTG_IDLE_EN            (1 << 15)
+#       define   HST_IDLE_EN            (1 << 14)
+#       define   DEV_IDLE_EN            (1 << 13)
+#       define   OTG_RESET_DONE         (1 << 2)
+#       define   OTG_SOFT_RESET         (1 << 1)
+#define OTG_SYSCON_2                    (OTG_BASE + 0x08)
+#       define   OTG_EN                 (1 << 31)
+#       define   USBX_SYNCHRO           (1 << 30)
+#       define   OTG_MST16              (1 << 29)
+#       define   SRP_GPDATA             (1 << 28)
+#       define   SRP_GPDVBUS            (1 << 27)
+#       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
+#       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
+#       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
+#       define   SRP_DPW                (1 << 14)
+#       define   SRP_DATA               (1 << 13)
+#       define   SRP_VBUS               (1 << 12)
+#       define   OTG_PADEN              (1 << 10)
+#       define   HMC_PADEN              (1 << 9)
+#       define   UHOST_EN               (1 << 8)
+#       define   HMC_TLLSPEED           (1 << 7)
+#       define   HMC_TLLATTACH          (1 << 6)
+#       define   OTG_HMC(w)             (((w)>>0)&0x3f)
+#define OTG_CTRL                        (OTG_BASE + 0x0c)
+#       define   OTG_USB2_EN            (1 << 29)
+#       define   OTG_USB2_DP            (1 << 28)
+#       define   OTG_USB2_DM            (1 << 27)
+#       define   OTG_USB1_EN            (1 << 26)
+#       define   OTG_USB1_DP            (1 << 25)
+#       define   OTG_USB1_DM            (1 << 24)
+#       define   OTG_USB0_EN            (1 << 23)
+#       define   OTG_USB0_DP            (1 << 22)
+#       define   OTG_USB0_DM            (1 << 21)
+#       define   OTG_ASESSVLD           (1 << 20)
+#       define   OTG_BSESSEND           (1 << 19)
+#       define   OTG_BSESSVLD           (1 << 18)
+#       define   OTG_VBUSVLD            (1 << 17)
+#       define   OTG_ID                 (1 << 16)
+#       define   OTG_DRIVER_SEL         (1 << 15)
+#       define   OTG_A_SETB_HNPEN       (1 << 12)
+#       define   OTG_A_BUSREQ           (1 << 11)
+#       define   OTG_B_HNPEN            (1 << 9)
+#       define   OTG_B_BUSREQ           (1 << 8)
+#       define   OTG_BUSDROP            (1 << 7)
+#       define   OTG_PULLDOWN           (1 << 5)
+#       define   OTG_PULLUP             (1 << 4)
+#       define   OTG_DRV_VBUS           (1 << 3)
+#       define   OTG_PD_VBUS            (1 << 2)
+#       define   OTG_PU_VBUS            (1 << 1)
+#       define   OTG_PU_ID              (1 << 0)
+#define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
+#       define   DRIVER_SWITCH          (1 << 15)
+#       define   A_VBUS_ERR             (1 << 13)
+#       define   A_REQ_TMROUT           (1 << 12)
+#       define   A_SRP_DETECT           (1 << 11)
+#       define   B_HNP_FAIL             (1 << 10)
+#       define   B_SRP_TMROUT           (1 << 9)
+#       define   B_SRP_DONE             (1 << 8)
+#       define   B_SRP_STARTED          (1 << 7)
+#       define   OPRT_CHG               (1 << 0)
+#define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
+        // same bits as in IRQ_EN
+#define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
+#       define   OTGVPD                 (1 << 14)
+#       define   OTGVPU                 (1 << 13)
+#       define   OTGPUID                (1 << 12)
+#       define   USB2VDR                (1 << 10)
+#       define   USB2PDEN               (1 << 9)
+#       define   USB2PUEN               (1 << 8)
+#       define   USB1VDR                (1 << 6)
+#       define   USB1PDEN               (1 << 5)
+#       define   USB1PUEN               (1 << 4)
+#       define   USB0VDR                (1 << 2)
+#       define   USB0PDEN               (1 << 1)
+#       define   USB0PUEN               (1 << 0)
+#define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
+#define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
+
+/*-------------------------------------------------------------------------*/
+
+/* OMAP1 */
+#define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
+#       define  CONF_USB2_UNI_R         (1 << 8)
+#       define  CONF_USB1_UNI_R         (1 << 7)
+#       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
+#       define  CONF_USB0_ISOLATE_R     (1 << 3)
+#       define  CONF_USB_PWRDN_DM_R     (1 << 2)
+#       define  CONF_USB_PWRDN_DP_R     (1 << 1)
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 64c65bcb2d6..aa81593db1a 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -140,7 +140,8 @@ static int __init omap1_dm_timer_init(void)
                 }
 
                 pdata->set_timer_src = omap1_dm_timer_set_src;
-                pdata->needs_manual_reset = 1;
+                pdata->timer_capability = OMAP_TIMER_ALWON |
+                                OMAP_TIMER_NEEDS_RESET;
 
                 ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
                 if (ret) {
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index e61afd92276..65f88176fba 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -27,7 +27,8 @@
 #include <asm/irq.h>
 
 #include <plat/mux.h>
-#include <plat/usb.h>
+
+#include <mach/usb.h>
 
 #include "common.h"
 
@@ -55,6 +56,119 @@
 #define INT_USB_IRQ_HGEN        INT_USB_HHC_1
 #define INT_USB_IRQ_OTG         IH2_BASE + 8
 
+#ifdef  CONFIG_ARCH_OMAP_OTG
+
+void __init
+omap_otg_init(struct omap_usb_config *config)
+{
+        u32             syscon;
+        int             alt_pingroup = 0;
+
+        /* NOTE:  no bus or clock setup (yet?) */
+
+        syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
+        if (!(syscon & OTG_RESET_DONE))
+                pr_debug("USB resets not complete?\n");
+
+        //omap_writew(0, OTG_IRQ_EN);
+
+        /* pin muxing and transceiver pinouts */
+        if (config->pins[0] > 2)        /* alt pingroup 2 */
+                alt_pingroup = 1;
+        syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
+        syscon |= config->usb1_init(config->pins[1]);
+        syscon |= config->usb2_init(config->pins[2], alt_pingroup);
+        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+        omap_writel(syscon, OTG_SYSCON_1);
+
+        syscon = config->hmc_mode;
+        syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
+#ifdef  CONFIG_USB_OTG
+        if (config->otg)
+                syscon |= OTG_EN;
+#endif
+        if (cpu_class_is_omap1())
+                pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
+                         omap_readl(USB_TRANSCEIVER_CTRL));
+        pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
+        omap_writel(syscon, OTG_SYSCON_2);
+
+        printk("USB: hmc %d", config->hmc_mode);
+        if (!alt_pingroup)
+                printk(", usb2 alt %d wires", config->pins[2]);
+        else if (config->pins[0])
+                printk(", usb0 %d wires%s", config->pins[0],
+                        is_usb0_device(config) ? " (dev)" : "");
+        if (config->pins[1])
+                printk(", usb1 %d wires", config->pins[1]);
+        if (!alt_pingroup && config->pins[2])
+                printk(", usb2 %d wires", config->pins[2]);
+        if (config->otg)
+                printk(", Mini-AB on usb%d", config->otg - 1);
+        printk("\n");
+
+        if (cpu_class_is_omap1()) {
+                u16 w;
+
+                /* leave USB clocks/controllers off until needed */
+                w = omap_readw(ULPD_SOFT_REQ);
+                w &= ~SOFT_USB_CLK_REQ;
+                omap_writew(w, ULPD_SOFT_REQ);
+
+                w = omap_readw(ULPD_CLOCK_CTRL);
+                w &= ~USB_MCLK_EN;
+                w |= DIS_USB_PVCI_CLK;
+                omap_writew(w, ULPD_CLOCK_CTRL);
+        }
+        syscon = omap_readl(OTG_SYSCON_1);
+        syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
+
+#ifdef  CONFIG_USB_GADGET_OMAP
+        if (config->otg || config->register_dev) {
+                struct platform_device *udc_device = config->udc_device;
+                int status;
+
+                syscon &= ~DEV_IDLE_EN;
+                udc_device->dev.platform_data = config;
+                status = platform_device_register(udc_device);
+                if (status)
+                        pr_debug("can't register UDC device, %d\n", status);
+        }
+#endif
+
+#if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+        if (config->otg || config->register_host) {
+                struct platform_device *ohci_device = config->ohci_device;
+                int status;
+
+                syscon &= ~HST_IDLE_EN;
+                ohci_device->dev.platform_data = config;
+                status = platform_device_register(ohci_device);
+                if (status)
+                        pr_debug("can't register OHCI device, %d\n", status);
+        }
+#endif
+
+#ifdef  CONFIG_USB_OTG
+        if (config->otg) {
+                struct platform_device *otg_device = config->otg_device;
+                int status;
+
+                syscon &= ~OTG_IDLE_EN;
+                otg_device->dev.platform_data = config;
+                status = platform_device_register(otg_device);
+                if (status)
+                        pr_debug("can't register OTG device, %d\n", status);
+        }
+#endif
+        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+        omap_writel(syscon, OTG_SYSCON_1);
+}
+
+#else
+void omap_otg_init(struct omap_usb_config *config) {}
+#endif
+
 #ifdef  CONFIG_USB_GADGET_OMAP
 
 static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4cf5142f22c..fcd4e85c4dd 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -9,7 +9,7 @@ config ARCH_OMAP2PLUS_TYPICAL
         select REGULATOR
         select PM_RUNTIME
         select VFP
-        select NEON if ARCH_OMAP3 || ARCH_OMAP4
+        select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
         select SERIAL_OMAP
         select SERIAL_OMAP_CONSOLE
         select I2C
@@ -21,12 +21,16 @@ config ARCH_OMAP2PLUS_TYPICAL
         help
           Compile a kernel suitable for booting most boards
 
+config SOC_HAS_OMAP2_SDRC
+        bool "OMAP2 SDRAM Controller support"
+
 config ARCH_OMAP2
         bool "TI OMAP2"
         depends on ARCH_OMAP2PLUS
         default y
         select CPU_V6
         select MULTI_IRQ_HANDLER
+        select SOC_HAS_OMAP2_SDRC
 
 config ARCH_OMAP3
         bool "TI OMAP3"
@@ -35,9 +39,11 @@ config ARCH_OMAP3
         select CPU_V7
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARCH_HAS_OPP
+        select PM_RUNTIME if CPU_IDLE
         select PM_OPP if PM
         select ARM_CPU_SUSPEND if PM
         select MULTI_IRQ_HANDLER
+        select SOC_HAS_OMAP2_SDRC
 
 config ARCH_OMAP4
         bool "TI OMAP4"
@@ -52,9 +58,18 @@ config ARCH_OMAP4
         select PL310_ERRATA_727915
         select ARM_ERRATA_720789
         select ARCH_HAS_OPP
+        select PM_RUNTIME if CPU_IDLE
         select PM_OPP if PM
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARM_CPU_SUSPEND if PM
+        select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+
+config SOC_OMAP5
+        bool "TI OMAP5"
+        select CPU_V7
+        select ARM_GIC
+        select HAVE_SMP
+        select ARM_CPU_SUSPEND if PM
 
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
@@ -64,19 +79,19 @@ config SOC_OMAP2420
         depends on ARCH_OMAP2
         default y
         select OMAP_DM_TIMER
-        select ARCH_OMAP_OTG
+        select SOC_HAS_OMAP2_SDRC
 
 config SOC_OMAP2430
         bool "OMAP2430 support"
         depends on ARCH_OMAP2
         default y
-        select ARCH_OMAP_OTG
+        select SOC_HAS_OMAP2_SDRC
 
 config SOC_OMAP3430
         bool "OMAP3430 support"
         depends on ARCH_OMAP3
         default y
-        select ARCH_OMAP_OTG
+        select SOC_HAS_OMAP2_SDRC
 
 config SOC_TI81XX
         bool "TI81XX support"
@@ -85,8 +100,10 @@ config SOC_TI81XX
 
 config SOC_AM33XX
         bool "AM33XX support"
-        depends on ARCH_OMAP3
         default y
+        select CPU_V7
+        select ARM_CPU_SUSPEND if PM
+        select MULTI_IRQ_HANDLER
 
 config OMAP_PACKAGE_ZAF
        bool
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fa742f3c262..f6a24b3f9c4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,7 +6,7 @@
 obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
          common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
 
-omap-2-3-common                         = irq.o sdrc.o
+omap-2-3-common                         = irq.o
 hwmod-common                            = omap_hwmod.o \
                                           omap_hwmod_common_data.o
 clock-common                            = clock.o clock_common_data.o \
@@ -16,19 +16,24 @@ secure-common				= omap-smc.o omap-secure.o
 obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
 obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
 obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
+obj-$(CONFIG_SOC_OMAP5)  += prm44xx.o $(hwmod-common) $(secure-common)
 
 ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
 obj-y += mcbsp.o
 endif
 
 obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
+obj-$(CONFIG_SOC_HAS_OMAP2_SDRC)        += sdrc.o
 
 # SMP support ONLY available for OMAP4
 
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o
-obj-$(CONFIG_ARCH_OMAP4)                += sleep44xx.o
+omap-4-5-common                         =  omap4-common.o omap-wakeupgen.o \
+                                           sleep44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-4-5-common)
+obj-$(CONFIG_SOC_OMAP5)                 += $(omap-4-5-common)
 
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
@@ -66,12 +71,12 @@ ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
-obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
-obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap-mpuss-lowpower.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
-obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
-obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)   += smartreflex-class3.o
+
+obj-$(CONFIG_POWER_AVS_OMAP)            += sr_device.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3)    += smartreflex-class3.o
 
 AFLAGS_sleep24xx.o                      :=-Wa,-march=armv6
 AFLAGS_sleep34xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
@@ -82,14 +87,22 @@ endif
 
 endif
 
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+endif
+
 # PRCM
+omap-prcm-4-5-common                    =  prcm.o cminst44xx.o cm44xx.o \
+                                           prcm_mpu44xx.o prminst44xx.o \
+                                           vc44xx_data.o vp44xx_data.o
 obj-y                                   += prm_common.o
 obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4)                += prcm.o cminst44xx.o cm44xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += prcm_mpu44xx.o prminst44xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += vc44xx_data.o vp44xx_data.o prm44xx.o
+obj-$(CONFIG_SOC_AM33XX)                += prcm.o prm33xx.o cm33xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(omap-prcm-4-5-common) prm44xx.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(omap-prcm-4-5-common)
 
 # OMAP voltage domains
 voltagedomain-common                    := voltage.o vc.o vp.o
@@ -99,6 +112,9 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += voltagedomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += $(voltagedomain-common)
+obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
 
 # OMAP powerdomain framework
 powerdomain-common                      += powerdomain.o powerdomain-common.o
@@ -113,10 +129,14 @@ obj-$(CONFIG_ARCH_OMAP3)		+= powerdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += $(powerdomain-common)
+obj-$(CONFIG_SOC_AM33XX)                += powerdomain33xx.o
+obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(powerdomain-common)
+obj-$(CONFIG_SOC_OMAP5)                 += powerdomain44xx.o
 
 # PRCM clockdomain control
 clockdomain-common                      += clockdomain.o
-clockdomain-common                      += clockdomains_common_data.o
 obj-$(CONFIG_ARCH_OMAP2)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomains2xxx_3xxx_data.o
@@ -129,6 +149,11 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clockdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += $(clockdomain-common)
+obj-$(CONFIG_SOC_AM33XX)                += clockdomain33xx.o
+obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(clockdomain-common)
+obj-$(CONFIG_SOC_OMAP5)                 += clockdomain44xx.o
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
@@ -146,6 +171,10 @@ obj-$(CONFIG_ARCH_OMAP3)		+= dpll3xxx.o clock3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) clock44xx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_AM33XX)                += $(clock-common) dpll3xxx.o
+obj-$(CONFIG_SOC_AM33XX)                += clock33xx_data.o
+obj-$(CONFIG_SOC_OMAP5)                 += $(clock-common)
+obj-$(CONFIG_SOC_OMAP5)                 += dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
 obj-$(CONFIG_SOC_OMAP2420)              += opp2420_data.o
@@ -173,6 +202,7 @@ obj-$(CONFIG_OMAP3_EMU)			+= emu.o
 # L3 interconnect
 obj-$(CONFIG_ARCH_OMAP3)                += omap_l3_smx.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap_l3_noc.o
+obj-$(CONFIG_SOC_OMAP5)                 += omap_l3_noc.o
 
 obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
 mailbox_mach-objs                       := mailbox.o
@@ -189,6 +219,10 @@ endif
 # OMAP2420 MSDI controller integration support ("MMC")
 obj-$(CONFIG_SOC_OMAP2420)              += msdi.o
 
+ifneq ($(CONFIG_DRM_OMAP),)
+obj-y                                   += drm.o
+endif
+
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_GENERIC)         += board-generic.o
 obj-$(CONFIG_MACH_OMAP_H4)              += board-h4.o
@@ -244,9 +278,6 @@ obj-y					+= $(omap-flash-y) $(omap-flash-m)
 omap-hsmmc-$(CONFIG_MMC_OMAP_HS)        := hsmmc.o
 obj-y                                   += $(omap-hsmmc-m) $(omap-hsmmc-y)
 
-
-usbfs-$(CONFIG_ARCH_OMAP_OTG)           := usb-fs.o
-obj-y                                   += $(usbfs-m) $(usbfs-y)
 obj-y                                   += usb-musb.o
 obj-y                                   += omap_phy_internal.o
 
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 447682c4e11..2c90ac68668 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -15,27 +15,13 @@
  * General Public License for more details.
  */
 
-#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/davinci_emac.h>
-#include <linux/platform_device.h>
-#include <plat/irqs.h>
+#include <asm/system.h>
+#include <plat/omap_device.h>
 #include <mach/am35xx.h>
-
 #include "control.h"
-
-static struct mdio_platform_data am35xx_emac_mdio_pdata;
-
-static struct resource am35xx_emac_mdio_resources[] = {
-        DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K),
-};
-
-static struct platform_device am35xx_emac_mdio_device = {
-        .name           = "davinci_mdio",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(am35xx_emac_mdio_resources),
-        .resource       = am35xx_emac_mdio_resources,
-        .dev.platform_data = &am35xx_emac_mdio_pdata,
-};
+#include "am35xx-emac.h"
 
 static void am35xx_enable_emac_int(void)
 {
@@ -69,41 +55,57 @@ static struct emac_platform_data am35xx_emac_pdata = {
         .interrupt_disable      = am35xx_disable_emac_int,
 };
 
-static struct resource am35xx_emac_resources[] = {
-        DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000),
-        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ),
-        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ),
-        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ),
-        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ),
-};
+static struct mdio_platform_data am35xx_mdio_pdata;
 
-static struct platform_device am35xx_emac_device = {
-        .name           = "davinci_emac",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(am35xx_emac_resources),
-        .resource       = am35xx_emac_resources,
-        .dev            = {
-                .platform_data  = &am35xx_emac_pdata,
-        },
-};
+static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
+                void *pdata, int pdata_len)
+{
+        struct platform_device *pdev;
+
+        pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len,
+                                 NULL, 0, false);
+        if (IS_ERR(pdev)) {
+                WARN(1, "Can't build omap_device for %s:%s.\n",
+                     oh->class->name, oh->name);
+                return PTR_ERR(pdev);
+        }
+
+        return 0;
+}
 
 void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
 {
+        struct omap_hwmod *oh;
         u32 v;
-        int err;
+        int ret;
 
-        am35xx_emac_pdata.rmii_en = rmii_en;
-        am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq;
-        err = platform_device_register(&am35xx_emac_device);
-        if (err) {
-                pr_err("AM35x: failed registering EMAC device: %d\n", err);
+        oh = omap_hwmod_lookup("davinci_mdio");
+        if (!oh) {
+                pr_err("Could not find davinci_mdio hwmod\n");
+                return;
+        }
+
+        am35xx_mdio_pdata.bus_freq = mdio_bus_freq;
+
+        ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata,
+                                         sizeof(am35xx_mdio_pdata));
+        if (ret) {
+                pr_err("Could not build davinci_mdio hwmod device\n");
                 return;
         }
 
-        err = platform_device_register(&am35xx_emac_mdio_device);
-        if (err) {
-                pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err);
-                platform_device_unregister(&am35xx_emac_device);
+        oh = omap_hwmod_lookup("davinci_emac");
+        if (!oh) {
+                pr_err("Could not find davinci_emac hwmod\n");
+                return;
+        }
+
+        am35xx_emac_pdata.rmii_en = rmii_en;
+
+        ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata,
+                                         sizeof(am35xx_emac_pdata));
+        if (ret) {
+                pr_err("Could not build davinci_emac hwmod device\n");
                 return;
         }
 
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 99ca6bad5c3..9511584fdc4 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -218,9 +218,6 @@ static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
 };
 
 static struct twl4030_platform_data sdp2430_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
         .gpio           = &sdp2430_gpio_data,
         .vmmc1          = &sdp2430_vmmc1,
@@ -254,16 +251,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {}      /* Terminator */
 };
 
-static struct omap_usb_config sdp2430_usb_config __initdata = {
-        .otg            = 1,
-#ifdef  CONFIG_USB_GADGET_OMAP
-        .hmc_mode       = 0x0,
-#elif   defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-        .hmc_mode       = 0x1,
-#endif
-        .pins[0]        = 3,
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -280,7 +267,6 @@ static void __init omap_2430sdp_init(void)
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
         omap_hsmmc_init(mmc);
-        omap2_usbfs_init(&sdp2430_usb_config);
 
         omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
         usb_musb_init(NULL);
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 8e17284a803..ad8a7d94afc 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -821,6 +821,9 @@ static void __init omap_4430sdp_display_init(void)
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         OMAP4_MUX(USBB2_ULPITLL_CLK, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+        /* NIRQ2 for twl6040 */
+        OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
+                  OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 502c31e123b..e5fa46bfde2 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -35,7 +35,6 @@
 #include <asm/mach/flash.h>
 
 #include <plat/led.h>
-#include <plat/usb.h>
 #include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
@@ -253,13 +252,6 @@ out:
         clk_put(gpmc_fck);
 }
 
-static struct omap_usb_config apollon_usb_config __initdata = {
-        .register_dev   = 1,
-        .hmc_mode       = 0x14, /* 0:dev 1:host1 2:disable */
-
-        .pins[0]        = 6,
-};
-
 static struct panel_generic_dpi_data apollon_panel_data = {
         .name                   = "apollon",
 };
@@ -297,15 +289,6 @@ static void __init apollon_led_init(void)
         gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds));
 }
 
-static void __init apollon_usb_init(void)
-{
-        /* USB device */
-        /* DEVICE_SUSPEND */
-        omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
-        gpio_request_one(12, GPIOF_OUT_INIT_LOW, "USB suspend");
-        omap2_usbfs_init(&apollon_usb_config);
-}
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -321,7 +304,6 @@ static void __init omap_apollon_init(void)
         apollon_init_smc91x();
         apollon_led_init();
         apollon_flash_init();
-        apollon_usb_init();
 
         /* REVISIT: where's the correct place */
         omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP);
@@ -329,7 +311,7 @@ static void __init omap_apollon_init(void)
         /* LCD PWR_EN */
         omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
 
-        /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
+        /* Use Internal loop-back in MMC/SDIO Module Input Clock selection */
         v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
         v |= (1 << 24);
         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index ded100c80a9..97d719047af 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -490,6 +490,71 @@ static struct twl4030_platform_data cm_t35_twldata = {
         .power          = &cm_t35_power_data,
 };
 
+#if defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
+#include <media/omap3isp.h>
+#include "devices.h"
+
+static struct i2c_board_info cm_t35_isp_i2c_boardinfo[] = {
+        {
+                I2C_BOARD_INFO("mt9t001", 0x5d),
+        },
+        {
+                I2C_BOARD_INFO("tvp5150", 0x5c),
+        },
+};
+
+static struct isp_subdev_i2c_board_info cm_t35_isp_primary_subdevs[] = {
+        {
+                .board_info = &cm_t35_isp_i2c_boardinfo[0],
+                .i2c_adapter_id = 3,
+        },
+        { NULL, 0, },
+};
+
+static struct isp_subdev_i2c_board_info cm_t35_isp_secondary_subdevs[] = {
+        {
+                .board_info = &cm_t35_isp_i2c_boardinfo[1],
+                .i2c_adapter_id = 3,
+        },
+        { NULL, 0, },
+};
+
+static struct isp_v4l2_subdevs_group cm_t35_isp_subdevs[] = {
+        {
+                .subdevs = cm_t35_isp_primary_subdevs,
+                .interface = ISP_INTERFACE_PARALLEL,
+                .bus = {
+                        .parallel = {
+                                .clk_pol = 1,
+                        },
+                },
+        },
+        {
+                .subdevs = cm_t35_isp_secondary_subdevs,
+                .interface = ISP_INTERFACE_PARALLEL,
+                .bus = {
+                        .parallel = {
+                                .clk_pol = 0,
+                        },
+                },
+        },
+        { NULL, 0, },
+};
+
+static struct isp_platform_data cm_t35_isp_pdata = {
+        .subdevs = cm_t35_isp_subdevs,
+};
+
+static void __init cm_t35_init_camera(void)
+{
+        if (omap3_init_camera(&cm_t35_isp_pdata) < 0)
+                pr_warn("CM-T3x: Failed registering camera device!\n");
+}
+
+#else
+static inline void cm_t35_init_camera(void) {}
+#endif /* CONFIG_VIDEO_OMAP3 */
+
 static void __init cm_t35_init_i2c(void)
 {
         omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
@@ -497,6 +562,8 @@ static void __init cm_t35_init_i2c(void)
                               TWL_COMMON_PDATA_AUDIO);
 
         omap3_pmic_init("tps65930", &cm_t35_twldata);
+
+        omap_register_i2c_bus(3, 400, NULL, 0);
 }
 
 #ifdef CONFIG_OMAP_MUX
@@ -574,6 +641,27 @@ static struct omap_board_mux board_mux[] __initdata = {
         OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
         OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
 
+        /* Camera */
+        OMAP3_MUX(CAM_HS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_VS, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_XCLKA, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_FLD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_D0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_D1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_D2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_D3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_D4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_D5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_D6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_D7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+        OMAP3_MUX(CAM_D8, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP3_MUX(CAM_D9, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP3_MUX(CAM_STROBE, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
+
+        OMAP3_MUX(CAM_D10, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN),
+        OMAP3_MUX(CAM_D11, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLDOWN),
+
         /* display controls */
         OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
         OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
@@ -646,6 +734,7 @@ static void __init cm_t3x_common_init(void)
 
         usb_musb_init(NULL);
         cm_t35_init_usbh();
+        cm_t35_init_camera();
 }
 
 static void __init cm_t35_init(void)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 20293465786..6f93a20536e 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -25,23 +25,12 @@
 #include "common-board-devices.h"
 
 #if !(defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3))
-#define omap_intc_of_init       NULL
+#define intc_of_init    NULL
 #endif
 #ifndef CONFIG_ARCH_OMAP4
 #define gic_of_init             NULL
 #endif
 
-static struct of_device_id irq_match[] __initdata = {
-        { .compatible = "ti,omap2-intc", .data = omap_intc_of_init, },
-        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-        { }
-};
-
-static void __init omap_init_irq(void)
-{
-        of_irq_init(irq_match);
-}
-
 static struct of_device_id omap_dt_match_table[] __initdata = {
         { .compatible = "simple-bus", },
         { .compatible = "ti,omap-infra", },
@@ -65,7 +54,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap242x_map_io,
         .init_early     = omap2420_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap_intc_of_init,
         .handle_irq     = omap2_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap2_timer,
@@ -84,7 +73,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap243x_map_io,
         .init_early     = omap2430_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap_intc_of_init,
         .handle_irq     = omap2_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap2_timer,
@@ -103,7 +92,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
         .init_early     = omap3430_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap_intc_of_init,
         .handle_irq     = omap3_intc_handle_irq,
         .init_machine   = omap_generic_init,
         .timer          = &omap3_timer,
@@ -112,6 +101,24 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
 MACHINE_END
 #endif
 
+#ifdef CONFIG_SOC_AM33XX
+static const char *am33xx_boards_compat[] __initdata = {
+        "ti,am33xx",
+        NULL,
+};
+
+DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
+        .reserve        = omap_reserve,
+        .map_io         = am33xx_map_io,
+        .init_early     = am33xx_init_early,
+        .init_irq       = omap_intc_of_init,
+        .handle_irq     = omap3_intc_handle_irq,
+        .init_machine   = omap_generic_init,
+        .timer          = &omap3_am33xx_timer,
+        .dt_compat      = am33xx_boards_compat,
+MACHINE_END
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 static const char *omap4_boards_compat[] __initdata = {
         "ti,omap4",
@@ -122,7 +129,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
         .reserve        = omap_reserve,
         .map_io         = omap4_map_io,
         .init_early     = omap4430_init_early,
-        .init_irq       = omap_init_irq,
+        .init_irq       = omap_gic_of_init,
         .handle_irq     = gic_handle_irq,
         .init_machine   = omap_generic_init,
         .init_late      = omap4430_init_late,
@@ -131,3 +138,22 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
         .restart        = omap_prcm_restart,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_SOC_OMAP5
+static const char *omap5_boards_compat[] __initdata = {
+        "ti,omap5",
+        NULL,
+};
+
+DT_MACHINE_START(OMAP5_DT, "Generic OMAP5 (Flattened Device Tree)")
+        .reserve        = omap_reserve,
+        .map_io         = omap5_map_io,
+        .init_early     = omap5_init_early,
+        .init_irq       = omap_gic_of_init,
+        .handle_irq     = gic_handle_irq,
+        .init_machine   = omap_generic_init,
+        .timer          = &omap5_timer,
+        .dt_compat      = omap5_boards_compat,
+        .restart        = omap_prcm_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 876becf8205..ace20482e3e 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -32,7 +32,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/usb.h>
 #include <plat/board.h>
 #include "common.h"
 #include <plat/menelaus.h>
@@ -329,17 +328,6 @@ static void __init h4_init_flash(void)
         h4_flash_resource.end   = base + SZ_64M - 1;
 }
 
-static struct omap_usb_config h4_usb_config __initdata = {
-        /* S1.10 OFF -- usb "download port"
-         * usb0 switched to Mini-B port and isp1105 transceiver;
-         * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging
-         */
-        .register_dev   = 1,
-        .pins[0]        = 3,
-/*      .hmc_mode       = 0x14,*/       /* 0:dev 1:host 2:disable */
-        .hmc_mode       = 0x00,         /* 0:dev|otg 1:disable 2:disable */
-};
-
 static struct at24_platform_data m24c01 = {
         .byte_len       = SZ_1K / 8,
         .page_size      = 16,
@@ -381,7 +369,6 @@ static void __init omap_h4_init(void)
                         ARRAY_SIZE(h4_i2c_board_info));
 
         platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
-        omap2_usbfs_init(&h4_usb_config);
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
         h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 74915295482..28214483aab 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -554,6 +554,8 @@ static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = {
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */
+        OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #endif
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 2c5d0ed7528..677357ff61a 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -468,7 +468,6 @@ static struct omap_mmc_platform_data mmc1_data = {
         .cleanup                        = n8x0_mmc_cleanup,
         .shutdown                       = n8x0_mmc_shutdown,
         .max_freq                       = 24000000,
-        .dma_mask                       = 0xffffffff,
         .slots[0] = {
                 .wires                  = 4,
                 .set_power              = n8x0_mmc_set_power,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 580fd17208d..6202fc76e49 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -433,7 +433,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
 
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
-        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 639bd07ea38..0d362e9f9cb 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -24,6 +24,10 @@
 #include <linux/leds.h>
 #include <linux/interrupt.h>
 
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/i2c/twl.h>
@@ -43,6 +47,7 @@
 
 #include <plat/board.h>
 #include <plat/usb.h>
+#include <plat/nand.h>
 #include "common.h"
 #include <plat/mcspi.h>
 #include <video/omapdss.h>
@@ -355,6 +360,19 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
 
         platform_device_register(&leds_gpio);
 
+        /* Enable VBUS switch by setting TWL4030.GPIO2DIR as output
+         * for starting USB tranceiver
+         */
+#ifdef CONFIG_TWL4030_CORE
+        if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
+                u8 val;
+
+                twl_i2c_read_u8(TWL4030_MODULE_GPIO, &val, REG_GPIODATADIR1);
+                val |= 0x04; /* TWL4030.GPIO2DIR BIT at GPIODATADIR1(0x9B) */
+                twl_i2c_write_u8(TWL4030_MODULE_GPIO, val, REG_GPIODATADIR1);
+        }
+#endif
+
         return 0;
 }
 
@@ -461,6 +479,28 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
 };
 #endif
 
+/* VAUX2 for USB */
+static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = {
+        REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"),    /* OMAP ISP */
+        REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"),    /* OMAP ISP */
+        REGULATOR_SUPPLY("hsusb1", "ehci-omap.0"),
+        REGULATOR_SUPPLY("vaux2", NULL),
+};
+
+static struct regulator_init_data omap3evm_vaux2 = {
+        .constraints = {
+                .min_uV         = 2800000,
+                .max_uV         = 2800000,
+                .apply_uV       = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(omap3evm_vaux2_supplies),
+        .consumer_supplies              = omap3evm_vaux2_supplies,
+};
+
 static struct twl4030_platform_data omap3evm_twldata = {
         /* platform_data for children goes here */
         .keypad         = &omap3evm_kp_data,
@@ -607,6 +647,37 @@ static struct regulator_consumer_supply dummy_supplies[] = {
         REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
 };
 
+static struct mtd_partition omap3evm_nand_partitions[] = {
+        /* All the partition sizes are listed in terms of NAND block size */
+        {
+                .name           = "X-Loader",
+                .offset         = 0,
+                .size           = 4*(SZ_128K),
+                .mask_flags     = MTD_WRITEABLE
+        },
+        {
+                .name           = "U-Boot",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 14*(SZ_128K),
+                .mask_flags     = MTD_WRITEABLE
+        },
+        {
+                .name           = "U-Boot Env",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 2*(SZ_128K)
+        },
+        {
+                .name           = "Kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 40*(SZ_128K)
+        },
+        {
+                .name           = "File system",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = MTDPART_OFS_APPEND,
+        },
+};
+
 static void __init omap3_evm_init(void)
 {
         struct omap_board_mux *obm;
@@ -623,6 +694,9 @@ static void __init omap3_evm_init(void)
         omap_mux_init_gpio(63, OMAP_PIN_INPUT);
         omap_hsmmc_init(mmc);
 
+        if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
+                omap3evm_twldata.vaux2 = &omap3evm_vaux2;
+
         omap3_evm_i2c_init();
 
         omap_display_init(&omap3_evm_dss_data);
@@ -656,6 +730,9 @@ static void __init omap3_evm_init(void)
         }
         usb_musb_init(&musb_board_data);
         usbhs_init(&usbhs_bdata);
+        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3evm_nand_partitions,
+                             ARRAY_SIZE(omap3evm_nand_partitions));
+
         omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
         omap3evm_init_smsc911x();
         omap3_evm_display_init();
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 932e1778aff..fca93d1afd4 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -93,9 +93,6 @@ static struct twl4030_usb_data omap3logic_usb_data = {
 
 
 static struct twl4030_platform_data omap3logic_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
         .gpio           = &omap3logic_gpio_data,
         .vmmc1          = &omap3logic_vmmc1,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 982fb2622ab..70f6d1d2546 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -106,7 +106,7 @@ static struct platform_device leds_gpio = {
 static struct omap_abe_twl6040_data panda_abe_audio_data = {
         /* Audio out */
         .has_hs         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
-        /* HandsFree through expasion connector */
+        /* HandsFree through expansion connector */
         .has_hf         = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
         /* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */
         .has_aux        = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
@@ -379,6 +379,9 @@ static struct omap_board_mux board_mux[] __initdata = {
         OMAP4_MUX(DPM_EMU18, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
         /* dispc2_data0 */
         OMAP4_MUX(DPM_EMU19, OMAP_PIN_OUTPUT | OMAP_MUX_MODE5),
+        /* NIRQ2 for twl6040 */
+        OMAP4_MUX(SYS_NIRQ2, OMAP_MUX_MODE0 |
+                  OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 5c4e6654216..ea3f565ba1a 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -398,24 +398,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
         return omap2_clksel_set_parent(clk, new_parent);
 }
 
-/* OMAP3/4 non-CORE DPLL clkops */
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-
-const struct clkops clkops_omap3_noncore_dpll_ops = {
-        .enable         = omap3_noncore_dpll_enable,
-        .disable        = omap3_noncore_dpll_disable,
-        .allow_idle     = omap3_dpll_allow_idle,
-        .deny_idle      = omap3_dpll_deny_idle,
-};
-
-const struct clkops clkops_omap3_core_dpll_ops = {
-        .allow_idle     = omap3_dpll_allow_idle,
-        .deny_idle      = omap3_dpll_deny_idle,
-};
-
-#endif
-
 /*
  * OMAP2+ clock reset and init functions
  */
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index a1bb23a2335..35ec5f3d9a7 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -155,4 +155,18 @@ extern const struct clkops clkops_omap3_noncore_dpll_ops;
 extern const struct clkops clkops_omap3_core_dpll_ops;
 extern const struct clkops clkops_omap4_dpllmx_ops;
 
+/* clksel_rate blocks shared between OMAP44xx and AM33xx */
+extern const struct clksel_rate div_1_0_rates[];
+extern const struct clksel_rate div_1_1_rates[];
+extern const struct clksel_rate div_1_2_rates[];
+extern const struct clksel_rate div_1_3_rates[];
+extern const struct clksel_rate div_1_4_rates[];
+extern const struct clksel_rate div31_1to31_rates[];
+
+/* clocks shared between various OMAP SoCs */
+extern struct clk virt_19200000_ck;
+extern struct clk virt_26000000_ck;
+
+extern int am33xx_clk_init(void);
+
 #endif
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index bace9308a4d..002745181ad 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1774,8 +1774,6 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
-        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_242X),
-        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_242X),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
         /* internal analog sources */
         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
@@ -1784,8 +1782,6 @@ static struct omap_clk omap2420_clks[] = {
         /* internal prcm root sources */
         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
         CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
-        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_242X),
-        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_242X),
         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
@@ -1901,42 +1897,9 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
         CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
-        CLK("omap_timer.1",     "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.2",     "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.3",     "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.4",     "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.5",     "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.6",     "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.7",     "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.8",     "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.9",     "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.10",    "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.11",    "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.12",    "32k_ck",       &func_32k_ck,   CK_243X),
-        CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.1",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.2",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.3",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.4",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.5",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.6",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.7",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.8",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.9",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.10",    "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.11",    "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.12",    "alt_ck",       &alt_ck,        CK_243X),
+        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_243X),
+        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
+        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 3b4d09a5039..cacabb070e2 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1858,11 +1858,6 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_243X),
-        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_243X),
-        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_243X),
-        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_243X),
-        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_243X),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
         /* internal analog sources */
         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
@@ -1871,11 +1866,6 @@ static struct omap_clk omap2430_clks[] = {
         /* internal prcm root sources */
         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
         CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
-        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_243X),
-        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_243X),
-        CLK("omap-mcbsp.3",     "prcm_fck",     &func_96m_ck,   CK_243X),
-        CLK("omap-mcbsp.4",     "prcm_fck",     &func_96m_ck,   CK_243X),
-        CLK("omap-mcbsp.5",     "prcm_fck",     &func_96m_ck,   CK_243X),
         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
@@ -2000,42 +1990,9 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
         CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
         CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
-        CLK("omap_timer.1",     "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.2",     "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.3",     "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.4",     "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.5",     "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.6",     "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.7",     "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.8",     "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.9",     "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.10",    "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.11",    "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.12",    "32k_ck",  &func_32k_ck,   CK_243X),
-        CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_243X),
-        CLK("omap_timer.1",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.2",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.3",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.4",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.5",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.6",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.7",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.8",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.9",     "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.10",    "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.11",    "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap_timer.12",    "alt_ck",       &alt_ck,        CK_243X),
+        CLK(NULL,       "timer_32k_ck",  &func_32k_ck,   CK_243X),
+        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
+        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
new file mode 100644
index 00000000000..25bbcc7ca4d
--- /dev/null
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -0,0 +1,1105 @@
+/*
+ * AM33XX Clock data
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <plat/clkdev_omap.h>
+#include <plat/am33xx.h>
+
+#include "iomap.h"
+#include "control.h"
+#include "clock.h"
+#include "cm.h"
+#include "cm33xx.h"
+#include "cm-regbits-33xx.h"
+#include "prm.h"
+
+/* Maximum DPLL multiplier, divider values for AM33XX */
+#define AM33XX_MAX_DPLL_MULT            2047
+#define AM33XX_MAX_DPLL_DIV             128
+
+/* Modulemode control */
+#define AM33XX_MODULEMODE_HWCTRL        0
+#define AM33XX_MODULEMODE_SWCTRL        1
+
+/* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
+ *    physically present, in such a case HWMOD enabling of
+ *    clock would be failure with default parent. And timer
+ *    probe thinks clock is already enabled, this leads to
+ *    crash upon accessing timer 3 & 6 registers in probe.
+ *    Fix by setting parent of both these timers to master
+ *    oscillator clock.
+ */
+static inline void am33xx_init_timer_parent(struct clk *clk)
+{
+        omap2_clksel_set_parent(clk, clk->parent);
+}
+
+/* Root clocks */
+
+/* RTC 32k */
+static struct clk clk_32768_ck = {
+        .name           = "clk_32768_ck",
+        .clkdm_name     = "l4_rtc_clkdm",
+        .rate           = 32768,
+        .ops            = &clkops_null,
+};
+
+/* On-Chip 32KHz RC OSC */
+static struct clk clk_rc32k_ck = {
+        .name           = "clk_rc32k_ck",
+        .rate           = 32000,
+        .ops            = &clkops_null,
+};
+
+/* Crystal input clks */
+static struct clk virt_24000000_ck = {
+        .name           = "virt_24000000_ck",
+        .rate           = 24000000,
+        .ops            = &clkops_null,
+};
+
+static struct clk virt_25000000_ck = {
+        .name           = "virt_25000000_ck",
+        .rate           = 25000000,
+        .ops            = &clkops_null,
+};
+
+/* Oscillator clock */
+/* 19.2, 24, 25 or 26 MHz */
+static const struct clksel sys_clkin_sel[] = {
+        { .parent = &virt_19200000_ck, .rates = div_1_0_rates },
+        { .parent = &virt_24000000_ck, .rates = div_1_1_rates },
+        { .parent = &virt_25000000_ck, .rates = div_1_2_rates },
+        { .parent = &virt_26000000_ck, .rates = div_1_3_rates },
+        { .parent = NULL },
+};
+
+/* External clock - 12 MHz */
+static struct clk tclkin_ck = {
+        .name           = "tclkin_ck",
+        .rate           = 12000000,
+        .ops            = &clkops_null,
+};
+
+/*
+ * sys_clk in: input to the dpll and also used as funtional clock for,
+ *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
+ *
+ */
+static struct clk sys_clkin_ck = {
+        .name           = "sys_clkin_ck",
+        .parent         = &virt_24000000_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel_reg     = AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
+        .clksel_mask    = AM33XX_CONTROL_STATUS_SYSBOOT1_MASK,
+        .clksel         = sys_clkin_sel,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
+        .mult_mask      = AM33XX_DPLL_MULT_MASK,
+        .div1_mask      = AM33XX_DPLL_DIV_MASK,
+        .enable_mask    = AM33XX_DPLL_EN_MASK,
+        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
+        .max_multiplier = AM33XX_MAX_DPLL_MULT,
+        .max_divider    = AM33XX_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+/* CLKDCOLDO output */
+static struct clk dpll_core_ck = {
+        .name           = "dpll_core_ck",
+        .parent         = &sys_clkin_ck,
+        .dpll_data      = &dpll_core_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_omap3_core_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+static struct clk dpll_core_x2_ck = {
+        .name           = "dpll_core_x2_ck",
+        .parent         = &dpll_core_ck,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_clkoutx2_recalc,
+};
+
+
+static const struct clksel dpll_core_m4_div[] = {
+        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_core_m4_ck = {
+        .name           = "dpll_core_m4_ck",
+        .parent         = &dpll_core_x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = dpll_core_m4_div,
+        .clksel_reg     = AM33XX_CM_DIV_M4_DPLL_CORE,
+        .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static const struct clksel dpll_core_m5_div[] = {
+        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_core_m5_ck = {
+        .name           = "dpll_core_m5_ck",
+        .parent         = &dpll_core_x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = dpll_core_m5_div,
+        .clksel_reg     = AM33XX_CM_DIV_M5_DPLL_CORE,
+        .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static const struct clksel dpll_core_m6_div[] = {
+        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_core_m6_ck = {
+        .name           = "dpll_core_m6_ck",
+        .parent         = &dpll_core_x2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = dpll_core_m6_div,
+        .clksel_reg     = AM33XX_CM_DIV_M6_DPLL_CORE,
+        .clksel_mask    = AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_MPU,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
+        .mult_mask      = AM33XX_DPLL_MULT_MASK,
+        .div1_mask      = AM33XX_DPLL_DIV_MASK,
+        .enable_mask    = AM33XX_DPLL_EN_MASK,
+        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
+        .max_multiplier = AM33XX_MAX_DPLL_MULT,
+        .max_divider    = AM33XX_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+/* CLKOUT: fdpll/M2 */
+static struct clk dpll_mpu_ck = {
+        .name           = "dpll_mpu_ck",
+        .parent         = &sys_clkin_ck,
+        .dpll_data      = &dpll_mpu_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_omap3_noncore_dpll_ops,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+};
+
+/*
+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ * and ALT_CLK1/2)
+ */
+static const struct clksel dpll_mpu_m2_div[] = {
+        { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_mpu_m2_ck = {
+        .name           = "dpll_mpu_m2_ck",
+        .clkdm_name     = "mpu_clkdm",
+        .parent         = &dpll_mpu_ck,
+        .clksel         = dpll_mpu_m2_div,
+        .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_MPU,
+        .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+/* DPLL_DDR */
+static struct dpll_data dpll_ddr_dd = {
+        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DDR,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
+        .mult_mask      = AM33XX_DPLL_MULT_MASK,
+        .div1_mask      = AM33XX_DPLL_DIV_MASK,
+        .enable_mask    = AM33XX_DPLL_EN_MASK,
+        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
+        .max_multiplier = AM33XX_MAX_DPLL_MULT,
+        .max_divider    = AM33XX_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+/* CLKOUT: fdpll/M2 */
+static struct clk dpll_ddr_ck = {
+        .name           = "dpll_ddr_ck",
+        .parent         = &sys_clkin_ck,
+        .dpll_data      = &dpll_ddr_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_dpll_recalc,
+};
+
+/*
+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ * and ALT_CLK1/2)
+ */
+static const struct clksel dpll_ddr_m2_div[] = {
+        { .parent = &dpll_ddr_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_ddr_m2_ck = {
+        .name           = "dpll_ddr_m2_ck",
+        .parent         = &dpll_ddr_ck,
+        .clksel         = dpll_ddr_m2_div,
+        .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DDR,
+        .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+/* emif_fck functional clock */
+static struct clk dpll_ddr_m2_div2_ck = {
+        .name           = "dpll_ddr_m2_div2_ck",
+        .clkdm_name     = "l3_clkdm",
+        .parent         = &dpll_ddr_m2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
+/* DPLL_DISP */
+static struct dpll_data dpll_disp_dd = {
+        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DISP,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
+        .mult_mask      = AM33XX_DPLL_MULT_MASK,
+        .div1_mask      = AM33XX_DPLL_DIV_MASK,
+        .enable_mask    = AM33XX_DPLL_EN_MASK,
+        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
+        .max_multiplier = AM33XX_MAX_DPLL_MULT,
+        .max_divider    = AM33XX_MAX_DPLL_DIV,
+        .min_divider    = 1,
+};
+
+/* CLKOUT: fdpll/M2 */
+static struct clk dpll_disp_ck = {
+        .name           = "dpll_disp_ck",
+        .parent         = &sys_clkin_ck,
+        .dpll_data      = &dpll_disp_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+};
+
+/*
+ * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
+ * and ALT_CLK1/2)
+ */
+static const struct clksel dpll_disp_m2_div[] = {
+        { .parent = &dpll_disp_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_disp_m2_ck = {
+        .name           = "dpll_disp_m2_ck",
+        .parent         = &dpll_disp_ck,
+        .clksel         = dpll_disp_m2_div,
+        .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_DISP,
+        .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_PERIPH,
+        .clk_bypass     = &sys_clkin_ck,
+        .clk_ref        = &sys_clkin_ck,
+        .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
+        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
+        .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
+        .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
+        .enable_mask    = AM33XX_DPLL_EN_MASK,
+        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
+        .max_multiplier = AM33XX_MAX_DPLL_MULT,
+        .max_divider    = AM33XX_MAX_DPLL_DIV,
+        .min_divider    = 1,
+        .flags          = DPLL_J_TYPE,
+};
+
+/* CLKDCOLDO */
+static struct clk dpll_per_ck = {
+        .name           = "dpll_per_ck",
+        .parent         = &sys_clkin_ck,
+        .dpll_data      = &dpll_per_dd,
+        .init           = &omap2_init_dpll_parent,
+        .ops            = &clkops_null,
+        .recalc         = &omap3_dpll_recalc,
+        .round_rate     = &omap2_dpll_round_rate,
+        .set_rate       = &omap3_noncore_dpll_set_rate,
+};
+
+/* CLKOUT: fdpll/M2 */
+static const struct clksel dpll_per_m2_div[] = {
+        { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
+        { .parent = NULL },
+};
+
+static struct clk dpll_per_m2_ck = {
+        .name           = "dpll_per_m2_ck",
+        .parent         = &dpll_per_ck,
+        .clksel         = dpll_per_m2_div,
+        .clksel_reg     = AM33XX_CM_DIV_M2_DPLL_PER,
+        .clksel_mask    = AM33XX_DPLL_CLKOUT_DIV_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static struct clk dpll_per_m2_div4_wkupdm_ck = {
+        .name           = "dpll_per_m2_div4_wkupdm_ck",
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &dpll_per_m2_ck,
+        .fixed_div      = 4,
+        .ops            = &clkops_null,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
+static struct clk dpll_per_m2_div4_ck = {
+        .name           = "dpll_per_m2_div4_ck",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &dpll_per_m2_ck,
+        .fixed_div      = 4,
+        .ops            = &clkops_null,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
+static struct clk l3_gclk = {
+        .name           = "l3_gclk",
+        .clkdm_name     = "l3_clkdm",
+        .parent         = &dpll_core_m4_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dpll_core_m4_div2_ck = {
+        .name           = "dpll_core_m4_div2_ck",
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &dpll_core_m4_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
+static struct clk l4_rtc_gclk = {
+        .name           = "l4_rtc_gclk",
+        .parent         = &dpll_core_m4_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
+static struct clk clk_24mhz = {
+        .name           = "clk_24mhz",
+        .parent         = &dpll_per_m2_ck,
+        .fixed_div      = 8,
+        .ops            = &clkops_null,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
+/*
+ * Below clock nodes describes clockdomains derived out
+ * of core clock.
+ */
+static struct clk l4hs_gclk = {
+        .name           = "l4hs_gclk",
+        .clkdm_name     = "l4hs_clkdm",
+        .parent         = &dpll_core_m4_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk l3s_gclk = {
+        .name           = "l3s_gclk",
+        .clkdm_name     = "l3s_clkdm",
+        .parent         = &dpll_core_m4_div2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk l4fw_gclk = {
+        .name           = "l4fw_gclk",
+        .clkdm_name     = "l4fw_clkdm",
+        .parent         = &dpll_core_m4_div2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk l4ls_gclk = {
+        .name           = "l4ls_gclk",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &dpll_core_m4_div2_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk sysclk_div_ck = {
+        .name           = "sysclk_div_ck",
+        .parent         = &dpll_core_m4_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * In order to match the clock domain with hwmod clockdomain entry,
+ * separate clock nodes is required for the modules which are
+ * directly getting their funtioncal clock from sys_clkin.
+ */
+static struct clk adc_tsc_fck = {
+        .name           = "adc_tsc_fck",
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dcan0_fck = {
+        .name           = "dcan0_fck",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk dcan1_fck = {
+        .name           = "dcan1_fck",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcasp0_fck = {
+        .name           = "mcasp0_fck",
+        .clkdm_name     = "l3s_clkdm",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mcasp1_fck = {
+        .name           = "mcasp1_fck",
+        .clkdm_name     = "l3s_clkdm",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk smartreflex0_fck = {
+        .name           = "smartreflex0_fck",
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk smartreflex1_fck = {
+        .name           = "smartreflex1_fck",
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &sys_clkin_ck,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * Modules clock nodes
+ *
+ * The following clock leaf nodes are added for the moment because:
+ *
+ *  - hwmod data is not present for these modules, either hwmod
+ *    control is not required or its not populated.
+ *  - Driver code is not yet migrated to use hwmod/runtime pm
+ *  - Modules outside kernel access (to disable them by default)
+ *
+ *     - debugss
+ *     - mmu (gfx domain)
+ *     - cefuse
+ *     - usbotg_fck (its additional clock and not really a modulemode)
+ *     - ieee5000
+ */
+static struct clk debugss_ick = {
+        .name           = "debugss_ick",
+        .clkdm_name     = "l3_aon_clkdm",
+        .parent         = &dpll_core_m4_ck,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
+        .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmu_fck = {
+        .name           = "mmu_fck",
+        .clkdm_name     = "gfx_l3_clkdm",
+        .parent         = &dpll_core_m4_ck,
+        .ops            = &clkops_omap2_dflt,
+        .enable_reg     = AM33XX_CM_GFX_MMUDATA_CLKCTRL,
+        .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk cefuse_fck = {
+        .name           = "cefuse_fck",
+        .clkdm_name     = "l4_cefuse_clkdm",
+        .parent         = &sys_clkin_ck,
+        .enable_reg     = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL,
+        .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * clkdiv32 is generated from fixed division of 732.4219
+ */
+static struct clk clkdiv32k_ick = {
+        .name           = "clkdiv32k_ick",
+        .clkdm_name     = "clk_24mhz_clkdm",
+        .rate           = 32768,
+        .parent         = &clk_24mhz,
+        .enable_reg     = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
+        .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
+        .ops            = &clkops_omap2_dflt,
+};
+
+static struct clk usbotg_fck = {
+        .name           = "usbotg_fck",
+        .clkdm_name     = "l3s_clkdm",
+        .parent         = &dpll_per_ck,
+        .enable_reg     = AM33XX_CM_CLKDCOLDO_DPLL_PER,
+        .enable_bit     = AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk ieee5000_fck = {
+        .name           = "ieee5000_fck",
+        .clkdm_name     = "l3s_clkdm",
+        .parent         = &dpll_core_m4_div2_ck,
+        .enable_reg     = AM33XX_CM_PER_IEEE5000_CLKCTRL,
+        .enable_bit     = AM33XX_MODULEMODE_SWCTRL,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &followparent_recalc,
+};
+
+/* Timers */
+static const struct clksel timer1_clkmux_sel[] = {
+        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
+        { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
+        { .parent = &tclkin_ck, .rates = div_1_2_rates },
+        { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
+        { .parent = &clk_32768_ck, .rates = div_1_4_rates },
+        { .parent = NULL },
+};
+
+static struct clk timer1_fck = {
+        .name           = "timer1_fck",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = timer1_clkmux_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER1MS_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_2_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel timer2_to_7_clk_sel[] = {
+        { .parent = &tclkin_ck, .rates = div_1_0_rates },
+        { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
+        { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+static struct clk timer2_fck = {
+        .name           = "timer2_fck",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER2_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk timer3_fck = {
+        .name           = "timer3_fck",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &sys_clkin_ck,
+        .init           = &am33xx_init_timer_parent,
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER3_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk timer4_fck = {
+        .name           = "timer4_fck",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER4_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk timer5_fck = {
+        .name           = "timer5_fck",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER5_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk timer6_fck = {
+        .name           = "timer6_fck",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &sys_clkin_ck,
+        .init           = &am33xx_init_timer_parent,
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER6_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk timer7_fck = {
+        .name           = "timer7_fck",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &sys_clkin_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = timer2_to_7_clk_sel,
+        .clksel_reg     = AM33XX_CLKSEL_TIMER7_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk cpsw_125mhz_gclk = {
+        .name           = "cpsw_125mhz_gclk",
+        .clkdm_name     = "cpsw_125mhz_clkdm",
+        .parent         = &dpll_core_m5_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
+static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
+        { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk cpsw_cpts_rft_clk = {
+        .name           = "cpsw_cpts_rft_clk",
+        .clkdm_name     = "cpsw_125mhz_clkdm",
+        .parent         = &dpll_core_m5_ck,
+        .clksel         = cpsw_cpts_rft_clkmux_sel,
+        .clksel_reg     = AM33XX_CM_CPTS_RFT_CLKSEL,
+        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+/* gpio */
+static const struct clksel gpio0_dbclk_mux_sel[] = {
+        { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
+        { .parent = &clk_32768_ck, .rates = div_1_1_rates },
+        { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+static struct clk gpio0_dbclk_mux_ck = {
+        .name           = "gpio0_dbclk_mux_ck",
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &clk_rc32k_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = gpio0_dbclk_mux_sel,
+        .clksel_reg     = AM33XX_CLKSEL_GPIO0_DBCLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static struct clk gpio0_dbclk = {
+        .name           = "gpio0_dbclk",
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &gpio0_dbclk_mux_ck,
+        .enable_reg     = AM33XX_CM_WKUP_GPIO0_CLKCTRL,
+        .enable_bit     = AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio1_dbclk = {
+        .name           = "gpio1_dbclk",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &clkdiv32k_ick,
+        .enable_reg     = AM33XX_CM_PER_GPIO1_CLKCTRL,
+        .enable_bit     = AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio2_dbclk = {
+        .name           = "gpio2_dbclk",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &clkdiv32k_ick,
+        .enable_reg     = AM33XX_CM_PER_GPIO2_CLKCTRL,
+        .enable_bit     = AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk gpio3_dbclk = {
+        .name           = "gpio3_dbclk",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &clkdiv32k_ick,
+        .enable_reg     = AM33XX_CM_PER_GPIO3_CLKCTRL,
+        .enable_bit     = AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT,
+        .ops            = &clkops_omap2_dflt,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel pruss_ocp_clk_mux_sel[] = {
+        { .parent = &l3_gclk, .rates = div_1_0_rates },
+        { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk pruss_ocp_gclk = {
+        .name           = "pruss_ocp_gclk",
+        .clkdm_name     = "pruss_ocp_clkdm",
+        .parent         = &l3_gclk,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = pruss_ocp_clk_mux_sel,
+        .clksel_reg     = AM33XX_CLKSEL_PRUSS_OCP_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel lcd_clk_mux_sel[] = {
+        { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
+        { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
+        { .parent = NULL },
+};
+
+static struct clk lcd_gclk = {
+        .name           = "lcd_gclk",
+        .clkdm_name     = "lcdc_clkdm",
+        .parent         = &dpll_disp_m2_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = lcd_clk_mux_sel,
+        .clksel_reg     = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static struct clk mmc_clk = {
+        .name           = "mmc_clk",
+        .clkdm_name     = "l4ls_clkdm",
+        .parent         = &dpll_per_m2_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
+
+static struct clk mmc2_fck = {
+        .name           = "mmc2_fck",
+        .clkdm_name     = "l3s_clkdm",
+        .parent         = &mmc_clk,
+        .ops            = &clkops_null,
+        .recalc         = &followparent_recalc,
+};
+
+static const struct clksel gfx_clksel_sel[] = {
+        { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
+        { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk gfx_fclk_clksel_ck = {
+        .name           = "gfx_fclk_clksel_ck",
+        .parent         = &dpll_core_m4_ck,
+        .clksel         = gfx_clksel_sel,
+        .ops            = &clkops_null,
+        .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
+        .clksel_mask    = AM33XX_CLKSEL_GFX_FCLK_MASK,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+static const struct clksel_rate div_1_0_2_1_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
+        { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
+        { .div = 0 },
+};
+
+static const struct clksel gfx_div_sel[] = {
+        { .parent = &gfx_fclk_clksel_ck, .rates = div_1_0_2_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk gfx_fck_div_ck = {
+        .name           = "gfx_fck_div_ck",
+        .clkdm_name     = "gfx_l3_clkdm",
+        .parent         = &gfx_fclk_clksel_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = gfx_div_sel,
+        .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+        .ops            = &clkops_null,
+};
+
+static const struct clksel sysclkout_pre_sel[] = {
+        { .parent = &clk_32768_ck, .rates = div_1_0_rates },
+        { .parent = &l3_gclk, .rates = div_1_1_rates },
+        { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
+        { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
+        { .parent = &lcd_gclk, .rates = div_1_4_rates },
+        { .parent = NULL },
+};
+
+static struct clk sysclkout_pre_ck = {
+        .name           = "sysclkout_pre_ck",
+        .parent         = &clk_32768_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = sysclkout_pre_sel,
+        .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
+        .clksel_mask    = AM33XX_CLKOUT2SOURCE_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/* Divide by 8 clock rates with default clock is 1/1*/
+static const struct clksel_rate div8_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_AM33XX },
+        { .div = 2, .val = 1, .flags = RATE_IN_AM33XX },
+        { .div = 3, .val = 2, .flags = RATE_IN_AM33XX },
+        { .div = 4, .val = 3, .flags = RATE_IN_AM33XX },
+        { .div = 5, .val = 4, .flags = RATE_IN_AM33XX },
+        { .div = 6, .val = 5, .flags = RATE_IN_AM33XX },
+        { .div = 7, .val = 6, .flags = RATE_IN_AM33XX },
+        { .div = 8, .val = 7, .flags = RATE_IN_AM33XX },
+        { .div = 0 },
+};
+
+static const struct clksel clkout2_div[] = {
+        { .parent = &sysclkout_pre_ck, .rates = div8_rates },
+        { .parent = NULL },
+};
+
+static struct clk clkout2_ck = {
+        .name           = "clkout2_ck",
+        .parent         = &sysclkout_pre_ck,
+        .ops            = &clkops_omap2_dflt,
+        .clksel         = clkout2_div,
+        .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
+        .clksel_mask    = AM33XX_CLKOUT2DIV_MASK,
+        .enable_reg     = AM33XX_CM_CLKOUT_CTRL,
+        .enable_bit     = AM33XX_CLKOUT2EN_SHIFT,
+        .recalc         = &omap2_clksel_recalc,
+        .round_rate     = &omap2_clksel_round_rate,
+        .set_rate       = &omap2_clksel_set_rate,
+};
+
+static const struct clksel wdt_clkmux_sel[] = {
+        { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
+        { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
+        { .parent = NULL },
+};
+
+static struct clk wdt1_fck = {
+        .name           = "wdt1_fck",
+        .clkdm_name     = "l4_wkup_clkdm",
+        .parent         = &clk_rc32k_ck,
+        .init           = &omap2_init_clksel_parent,
+        .clksel         = wdt_clkmux_sel,
+        .clksel_reg     = AM33XX_CLKSEL_WDT1_CLK,
+        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
+        .ops            = &clkops_null,
+        .recalc         = &omap2_clksel_recalc,
+};
+
+/*
+ * clkdev
+ */
+static struct omap_clk am33xx_clks[] = {
+        CLK(NULL,       "clk_32768_ck",         &clk_32768_ck,  CK_AM33XX),
+        CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck,  CK_AM33XX),
+        CLK(NULL,       "virt_19200000_ck",     &virt_19200000_ck,      CK_AM33XX),
+        CLK(NULL,       "virt_24000000_ck",     &virt_24000000_ck,      CK_AM33XX),
+        CLK(NULL,       "virt_25000000_ck",     &virt_25000000_ck,      CK_AM33XX),
+        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_AM33XX),
+        CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck,  CK_AM33XX),
+        CLK(NULL,       "tclkin_ck",            &tclkin_ck,     CK_AM33XX),
+        CLK(NULL,       "dpll_core_ck",         &dpll_core_ck,  CK_AM33XX),
+        CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck,       CK_AM33XX),
+        CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck,       CK_AM33XX),
+        CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
+        CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck,       CK_AM33XX),
+        CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,   CK_AM33XX),
+        CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
+        CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,   CK_AM33XX),
+        CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
+        CLK(NULL,       "dpll_ddr_m2_div2_ck",  &dpll_ddr_m2_div2_ck,   CK_AM33XX),
+        CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck,  CK_AM33XX),
+        CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck,       CK_AM33XX),
+        CLK(NULL,       "dpll_per_ck",          &dpll_per_ck,   CK_AM33XX),
+        CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck,        CK_AM33XX),
+        CLK(NULL,       "dpll_per_m2_div4_wkupdm_ck",   &dpll_per_m2_div4_wkupdm_ck,    CK_AM33XX),
+        CLK(NULL,       "dpll_per_m2_div4_ck",  &dpll_per_m2_div4_ck,   CK_AM33XX),
+        CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck,   CK_AM33XX),
+        CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
+        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick, CK_AM33XX),
+        CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
+        CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
+        CLK(NULL,       "debugss_ick",          &debugss_ick,   CK_AM33XX),
+        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk,        CK_AM33XX),
+        CLK("davinci-mcasp.0",  NULL,           &mcasp0_fck,    CK_AM33XX),
+        CLK("davinci-mcasp.1",  NULL,           &mcasp1_fck,    CK_AM33XX),
+        CLK("NULL",     "mmc2_fck",             &mmc2_fck,      CK_AM33XX),
+        CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
+        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
+        CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
+        CLK(NULL,       "gpt1_fck",             &timer1_fck,    CK_AM33XX),
+        CLK(NULL,       "gpt2_fck",             &timer2_fck,    CK_AM33XX),
+        CLK(NULL,       "gpt3_fck",             &timer3_fck,    CK_AM33XX),
+        CLK(NULL,       "gpt4_fck",             &timer4_fck,    CK_AM33XX),
+        CLK(NULL,       "gpt5_fck",             &timer5_fck,    CK_AM33XX),
+        CLK(NULL,       "gpt6_fck",             &timer6_fck,    CK_AM33XX),
+        CLK(NULL,       "gpt7_fck",             &timer7_fck,    CK_AM33XX),
+        CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
+        CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
+        CLK(NULL,       "wdt1_fck",             &wdt1_fck,      CK_AM33XX),
+        CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk,   CK_AM33XX),
+        CLK(NULL,       "l3_gclk",              &l3_gclk,       CK_AM33XX),
+        CLK(NULL,       "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,  CK_AM33XX),
+        CLK(NULL,       "l4hs_gclk",            &l4hs_gclk,     CK_AM33XX),
+        CLK(NULL,       "l3s_gclk",             &l3s_gclk,      CK_AM33XX),
+        CLK(NULL,       "l4fw_gclk",            &l4fw_gclk,     CK_AM33XX),
+        CLK(NULL,       "l4ls_gclk",            &l4ls_gclk,     CK_AM33XX),
+        CLK(NULL,       "clk_24mhz",            &clk_24mhz,     CK_AM33XX),
+        CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck, CK_AM33XX),
+        CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk,      CK_AM33XX),
+        CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk,     CK_AM33XX),
+        CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck,    CK_AM33XX),
+        CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk,   CK_AM33XX),
+        CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk,   CK_AM33XX),
+        CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk,   CK_AM33XX),
+        CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk,   CK_AM33XX),
+        CLK(NULL,       "lcd_gclk",             &lcd_gclk,      CK_AM33XX),
+        CLK(NULL,       "mmc_clk",              &mmc_clk,       CK_AM33XX),
+        CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck,    CK_AM33XX),
+        CLK(NULL,       "gfx_fck_div_ck",       &gfx_fck_div_ck,        CK_AM33XX),
+        CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck,      CK_AM33XX),
+        CLK(NULL,       "clkout2_ck",           &clkout2_ck,    CK_AM33XX),
+};
+
+int __init am33xx_clk_init(void)
+{
+        struct omap_clk *c;
+        u32 cpu_clkflg;
+
+        if (soc_is_am33xx()) {
+                cpu_mask = RATE_IN_AM33XX;
+                cpu_clkflg = CK_AM33XX;
+        }
+
+        clk_init(&omap2_clk_functions);
+
+        for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++)
+                clk_preinit(c->lk.clk);
+
+        for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
+                if (c->cpu & cpu_clkflg) {
+                        clkdev_add(&c->lk);
+                        clk_register(c->lk.clk);
+                        omap2_init_clk_clkdm(c->lk.clk);
+                }
+        }
+
+        recalculate_root_clocks();
+
+        /*
+         * Only enable those clocks we will need, let the drivers
+         * enable other clocks as necessary
+         */
+        clk_enable_init_clocks();
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 1efdec236ae..83bed9ad301 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -93,18 +93,6 @@ static struct clk virt_16_8m_ck = {
         .rate           = 16800000,
 };
 
-static struct clk virt_19_2m_ck = {
-        .name           = "virt_19_2m_ck",
-        .ops            = &clkops_null,
-        .rate           = 19200000,
-};
-
-static struct clk virt_26m_ck = {
-        .name           = "virt_26m_ck",
-        .ops            = &clkops_null,
-        .rate           = 26000000,
-};
-
 static struct clk virt_38_4m_ck = {
         .name           = "virt_38_4m_ck",
         .ops            = &clkops_null,
@@ -145,8 +133,8 @@ static const struct clksel osc_sys_clksel[] = {
         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
-        { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
-        { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
+        { .parent = &virt_19200000_ck, .rates = osc_sys_19_2m_rates },
+        { .parent = &virt_26000000_ck,   .rates = osc_sys_26m_rates },
         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
         { .parent = NULL },
 };
@@ -2490,13 +2478,13 @@ static struct clk uart4_fck = {
 };
 
 static struct clk uart4_fck_am35xx = {
-        .name           = "uart4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_UART4_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
+        .name           = "uart4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = AM35XX_EN_UART4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt2_fck = {
@@ -3201,8 +3189,12 @@ static struct clk vpfe_fck = {
 };
 
 /*
- * The UART1/2 functional clock acts as the functional
- * clock for UART4. No separate fclk control available.
+ * The UART1/2 functional clock acts as the functional clock for
+ * UART4. No separate fclk control available.  XXX Well now we have a
+ * uart4_fck that is apparently used as the UART4 functional clock,
+ * but it also seems that uart1_fck or uart2_fck are still needed, at
+ * least for UART4 softresets to complete.  This really needs
+ * clarification.
  */
 static struct clk uart4_ick_am35xx = {
         .name           = "uart4_ick",
@@ -3230,17 +3222,12 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
-        CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
-        CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
+        CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
+        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_3XXX),
         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
-        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
-        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
-        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
-        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
-        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
@@ -3307,8 +3294,6 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
-        CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
@@ -3391,15 +3376,15 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
         CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
         CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
+        CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
@@ -3413,9 +3398,6 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
-        CLK("omap-mcbsp.2",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
-        CLK("omap-mcbsp.3",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
-        CLK("omap-mcbsp.4",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
@@ -3474,38 +3456,16 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
-        CLK("davinci_emac",     NULL,   &emac_ick,      CK_AM35XX),
+        CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
         CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
-        CLK("musb-am35x",       "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
-        CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
+        CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
+        CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx,   CK_AM35XX),
         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
-        CLK("omap_timer.1",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.2",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.3",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.4",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.5",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.6",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.7",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.8",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.9",     "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.10",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.11",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.12",    "32k_ck",       &omap_32k_fck,  CK_3XXX),
-        CLK("omap_timer.1",     "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.2",     "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.3",     "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.4",     "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.5",     "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.6",     "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.7",     "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.8",     "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.9",     "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.10",    "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.11",    "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK("omap_timer.12",    "sys_ck",       &sys_ck,        CK_3XXX),
+        CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
+        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
 };
 
 
@@ -3523,7 +3483,7 @@ int __init omap3xxx_clk_init(void)
         } else if (cpu_is_ti816x()) {
                 cpu_mask = RATE_IN_TI816X;
                 cpu_clkflg = CK_TI816X;
-        } else if (cpu_is_am33xx()) {
+        } else if (soc_is_am33xx()) {
                 cpu_mask = RATE_IN_AM33XX;
         } else if (cpu_is_ti814x()) {
                 cpu_mask = RATE_IN_TI814X;
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index ba6f9a0a43e..d7f55e43b76 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -107,18 +107,6 @@ static struct clk virt_16800000_ck = {
         .rate           = 16800000,
 };
 
-static struct clk virt_19200000_ck = {
-        .name           = "virt_19200000_ck",
-        .ops            = &clkops_null,
-        .rate           = 19200000,
-};
-
-static struct clk virt_26000000_ck = {
-        .name           = "virt_26000000_ck",
-        .ops            = &clkops_null,
-        .rate           = 26000000,
-};
-
 static struct clk virt_27000000_ck = {
         .name           = "virt_27000000_ck",
         .ops            = &clkops_null,
@@ -131,31 +119,6 @@ static struct clk virt_38400000_ck = {
         .rate           = 38400000,
 };
 
-static const struct clksel_rate div_1_0_rates[] = {
-        { .div = 1, .val = 0, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
-static const struct clksel_rate div_1_1_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
-static const struct clksel_rate div_1_2_rates[] = {
-        { .div = 1, .val = 2, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
-static const struct clksel_rate div_1_3_rates[] = {
-        { .div = 1, .val = 3, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
-static const struct clksel_rate div_1_4_rates[] = {
-        { .div = 1, .val = 4, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
 static const struct clksel_rate div_1_5_rates[] = {
         { .div = 1, .val = 5, .flags = RATE_IN_4430 },
         { .div = 0 },
@@ -289,41 +252,6 @@ static struct clk dpll_abe_x2_ck = {
         .recalc         = &omap3_clkoutx2_recalc,
 };
 
-static const struct clksel_rate div31_1to31_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_4430 },
-        { .div = 2, .val = 2, .flags = RATE_IN_4430 },
-        { .div = 3, .val = 3, .flags = RATE_IN_4430 },
-        { .div = 4, .val = 4, .flags = RATE_IN_4430 },
-        { .div = 5, .val = 5, .flags = RATE_IN_4430 },
-        { .div = 6, .val = 6, .flags = RATE_IN_4430 },
-        { .div = 7, .val = 7, .flags = RATE_IN_4430 },
-        { .div = 8, .val = 8, .flags = RATE_IN_4430 },
-        { .div = 9, .val = 9, .flags = RATE_IN_4430 },
-        { .div = 10, .val = 10, .flags = RATE_IN_4430 },
-        { .div = 11, .val = 11, .flags = RATE_IN_4430 },
-        { .div = 12, .val = 12, .flags = RATE_IN_4430 },
-        { .div = 13, .val = 13, .flags = RATE_IN_4430 },
-        { .div = 14, .val = 14, .flags = RATE_IN_4430 },
-        { .div = 15, .val = 15, .flags = RATE_IN_4430 },
-        { .div = 16, .val = 16, .flags = RATE_IN_4430 },
-        { .div = 17, .val = 17, .flags = RATE_IN_4430 },
-        { .div = 18, .val = 18, .flags = RATE_IN_4430 },
-        { .div = 19, .val = 19, .flags = RATE_IN_4430 },
-        { .div = 20, .val = 20, .flags = RATE_IN_4430 },
-        { .div = 21, .val = 21, .flags = RATE_IN_4430 },
-        { .div = 22, .val = 22, .flags = RATE_IN_4430 },
-        { .div = 23, .val = 23, .flags = RATE_IN_4430 },
-        { .div = 24, .val = 24, .flags = RATE_IN_4430 },
-        { .div = 25, .val = 25, .flags = RATE_IN_4430 },
-        { .div = 26, .val = 26, .flags = RATE_IN_4430 },
-        { .div = 27, .val = 27, .flags = RATE_IN_4430 },
-        { .div = 28, .val = 28, .flags = RATE_IN_4430 },
-        { .div = 29, .val = 29, .flags = RATE_IN_4430 },
-        { .div = 30, .val = 30, .flags = RATE_IN_4430 },
-        { .div = 31, .val = 31, .flags = RATE_IN_4430 },
-        { .div = 0 },
-};
-
 static const struct clksel dpll_abe_m2x2_div[] = {
         { .parent = &dpll_abe_x2_ck, .rates = div31_1to31_rates },
         { .parent = NULL },
@@ -3299,17 +3227,17 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
-        CLK(NULL,       "gpt1_fck",                     &timer1_fck,    CK_443X),
-        CLK(NULL,       "gpt10_fck",                    &timer10_fck,   CK_443X),
-        CLK(NULL,       "gpt11_fck",                    &timer11_fck,   CK_443X),
-        CLK(NULL,       "gpt2_fck",                     &timer2_fck,    CK_443X),
-        CLK(NULL,       "gpt3_fck",                     &timer3_fck,    CK_443X),
-        CLK(NULL,       "gpt4_fck",                     &timer4_fck,    CK_443X),
-        CLK(NULL,       "gpt5_fck",                     &timer5_fck,    CK_443X),
-        CLK(NULL,       "gpt6_fck",                     &timer6_fck,    CK_443X),
-        CLK(NULL,       "gpt7_fck",                     &timer7_fck,    CK_443X),
-        CLK(NULL,       "gpt8_fck",                     &timer8_fck,    CK_443X),
-        CLK(NULL,       "gpt9_fck",                     &timer9_fck,    CK_443X),
+        CLK(NULL,       "timer1_fck",                   &timer1_fck,    CK_443X),
+        CLK(NULL,       "timer10_fck",                  &timer10_fck,   CK_443X),
+        CLK(NULL,       "timer11_fck",                  &timer11_fck,   CK_443X),
+        CLK(NULL,       "timer2_fck",                   &timer2_fck,    CK_443X),
+        CLK(NULL,       "timer3_fck",                   &timer3_fck,    CK_443X),
+        CLK(NULL,       "timer4_fck",                   &timer4_fck,    CK_443X),
+        CLK(NULL,       "timer5_fck",                   &timer5_fck,    CK_443X),
+        CLK(NULL,       "timer6_fck",                   &timer6_fck,    CK_443X),
+        CLK(NULL,       "timer7_fck",                   &timer7_fck,    CK_443X),
+        CLK(NULL,       "timer8_fck",                   &timer8_fck,    CK_443X),
+        CLK(NULL,       "timer9_fck",                   &timer9_fck,    CK_443X),
         CLK(NULL,       "uart1_fck",                    &uart1_fck,     CK_443X),
         CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
@@ -3385,28 +3313,18 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
         CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
-        CLK("omap_timer.1",     "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.2",     "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.3",     "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.4",     "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.5",     "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.6",     "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.7",     "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.8",     "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.9",     "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.10",    "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.11",    "32k_ck",       &sys_32k_ck,    CK_443X),
-        CLK("omap_timer.1",     "sys_ck",       &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.2",     "sys_ck",       &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.3",     "sys_ck",       &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.4",     "sys_ck",       &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.9",     "sys_ck",       &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.10",    "sys_ck",       &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.11",    "sys_ck",       &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.5",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.6",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.7",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.8",     "sys_ck",       &syc_clk_div_ck,        CK_443X),
+        CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
+        CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
 };
 
 int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index 6424d46be14..b9f3ba68148 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -43,3 +43,80 @@ const struct clksel_rate dsp_ick_rates[] = {
         { .div = 3, .val = 3, .flags = RATE_IN_243X },
         { .div = 0 },
 };
+
+
+/* clksel_rate blocks shared between OMAP44xx and AM33xx */
+
+const struct clksel_rate div_1_0_rates[] = {
+        { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 0 },
+};
+
+const struct clksel_rate div_1_1_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 0 },
+};
+
+const struct clksel_rate div_1_2_rates[] = {
+        { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 0 },
+};
+
+const struct clksel_rate div_1_3_rates[] = {
+        { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 0 },
+};
+
+const struct clksel_rate div_1_4_rates[] = {
+        { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 0 },
+};
+
+const struct clksel_rate div31_1to31_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX },
+        { .div = 0 },
+};
+
+/* Clocks shared between various OMAP SoCs */
+
+struct clk virt_19200000_ck = {
+        .name           = "virt_19200000_ck",
+        .ops            = &clkops_null,
+        .rate           = 19200000,
+};
+
+struct clk virt_26000000_ck = {
+        .name           = "virt_26000000_ck",
+        .ops            = &clkops_null,
+        .rate           = 26000000,
+};
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 6227e9505c2..5601dc13785 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -199,6 +199,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
 extern void __init omap242x_clockdomains_init(void);
 extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
+extern void __init am33xx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
 extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
@@ -206,11 +207,10 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
 extern struct clkdm_ops omap2_clkdm_operations;
 extern struct clkdm_ops omap3_clkdm_operations;
 extern struct clkdm_ops omap4_clkdm_operations;
+extern struct clkdm_ops am33xx_clkdm_operations;
 
 extern struct clkdm_dep gfx_24xx_wkdeps[];
 extern struct clkdm_dep dsp_24xx_wkdeps[];
 extern struct clockdomain wkup_common_clkdm;
-extern struct clockdomain prm_common_clkdm;
-extern struct clockdomain cm_common_clkdm;
 
 #endif
diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c
new file mode 100644
index 00000000000..aca6388fad7
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain33xx.c
@@ -0,0 +1,74 @@
+/*
+ * AM33XX clockdomain control
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+
+#include "clockdomain.h"
+#include "cm33xx.h"
+
+
+static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+
+static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+
+static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                return am33xx_clkdm_wakeup(clkdm);
+
+        return 0;
+}
+
+static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+
+        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+                am33xx_clkdm_sleep(clkdm);
+
+        return 0;
+}
+
+struct clkdm_ops am33xx_clkdm_operations = {
+        .clkdm_sleep            = am33xx_clkdm_sleep,
+        .clkdm_wakeup           = am33xx_clkdm_wakeup,
+        .clkdm_allow_idle       = am33xx_clkdm_allow_idle,
+        .clkdm_deny_idle        = am33xx_clkdm_deny_idle,
+        .clkdm_clk_enable       = am33xx_clkdm_clk_enable,
+        .clkdm_clk_disable      = am33xx_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 4f04dd11d65..762f2cc542c 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -70,7 +70,7 @@ static int omap4_clkdm_clear_all_wkup_sleep_deps(struct clockdomain *clkdm)
 
 static int omap4_clkdm_sleep(struct clockdomain *clkdm)
 {
-        omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,
+        omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,
                                         clkdm->cm_inst, clkdm->clkdm_offs);
         return 0;
 }
@@ -90,8 +90,12 @@ static void omap4_clkdm_allow_idle(struct clockdomain *clkdm)
 
 static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
 {
-        omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
-                                        clkdm->cm_inst, clkdm->clkdm_offs);
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                omap4_clkdm_wakeup(clkdm);
+        else
+                omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,
+                                                 clkdm->cm_inst,
+                                                 clkdm->clkdm_offs);
 }
 
 static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
index 0ab8e46d5b2..5c741852fac 100644
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -131,8 +131,6 @@ static struct clockdomain dss_2420_clkdm = {
 
 static struct clockdomain *clockdomains_omap242x[] __initdata = {
         &wkup_common_clkdm,
-        &cm_common_clkdm,
-        &prm_common_clkdm,
         &mpu_2420_clkdm,
         &iva1_2420_clkdm,
         &dsp_2420_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
index 3645ed04489..f09617555e1 100644
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -157,8 +157,6 @@ static struct clockdomain dss_2430_clkdm = {
 
 static struct clockdomain *clockdomains_omap243x[] __initdata = {
         &wkup_common_clkdm,
-        &cm_common_clkdm,
-        &prm_common_clkdm,
         &mpu_2430_clkdm,
         &mdm_clkdm,
         &dsp_2430_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
new file mode 100644
index 00000000000..32c90fd9eba
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
@@ -0,0 +1,196 @@
+/*
+ * AM33XX Clock Domain data.
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm.h"
+#include "cm33xx.h"
+#include "cm-regbits-33xx.h"
+
+static struct clockdomain l4ls_am33xx_clkdm = {
+        .name           = "l4ls_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3s_am33xx_clkdm = {
+        .name           = "l3s_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4fw_am33xx_clkdm = {
+        .name           = "l4fw_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3_am33xx_clkdm = {
+        .name           = "l3_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4hs_am33xx_clkdm = {
+        .name           = "l4hs_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain ocpwp_l3_am33xx_clkdm = {
+        .name           = "ocpwp_l3_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain pruss_ocp_am33xx_clkdm = {
+        .name           = "pruss_ocp_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
+        .name           = "cpsw_125mhz_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain lcdc_am33xx_clkdm = {
+        .name           = "lcdc_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain clk_24mhz_am33xx_clkdm = {
+        .name           = "clk_24mhz_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_wkup_am33xx_clkdm = {
+        .name           = "l4_wkup_clkdm",
+        .pwrdm          = { .name = "wkup_pwrdm" },
+        .cm_inst        = AM33XX_CM_WKUP_MOD,
+        .clkdm_offs     = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3_aon_am33xx_clkdm = {
+        .name           = "l3_aon_clkdm",
+        .pwrdm          = { .name = "wkup_pwrdm" },
+        .cm_inst        = AM33XX_CM_WKUP_MOD,
+        .clkdm_offs     = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
+        .name           = "l4_wkup_aon_clkdm",
+        .pwrdm          = { .name = "wkup_pwrdm" },
+        .cm_inst        = AM33XX_CM_WKUP_MOD,
+        .clkdm_offs     = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain mpu_am33xx_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .cm_inst        = AM33XX_CM_MPU_MOD,
+        .clkdm_offs     = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_rtc_am33xx_clkdm = {
+        .name           = "l4_rtc_clkdm",
+        .pwrdm          = { .name = "rtc_pwrdm" },
+        .cm_inst        = AM33XX_CM_RTC_MOD,
+        .clkdm_offs     = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain gfx_l3_am33xx_clkdm = {
+        .name           = "gfx_l3_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .cm_inst        = AM33XX_CM_GFX_MOD,
+        .clkdm_offs     = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
+        .name           = "gfx_l4ls_gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .cm_inst        = AM33XX_CM_GFX_MOD,
+        .clkdm_offs     = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_cefuse_am33xx_clkdm = {
+        .name           = "l4_cefuse_clkdm",
+        .pwrdm          = { .name = "cefuse_pwrdm" },
+        .cm_inst        = AM33XX_CM_CEFUSE_MOD,
+        .clkdm_offs     = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain *clockdomains_am33xx[] __initdata = {
+        &l4ls_am33xx_clkdm,
+        &l3s_am33xx_clkdm,
+        &l4fw_am33xx_clkdm,
+        &l3_am33xx_clkdm,
+        &l4hs_am33xx_clkdm,
+        &ocpwp_l3_am33xx_clkdm,
+        &pruss_ocp_am33xx_clkdm,
+        &cpsw_125mhz_am33xx_clkdm,
+        &lcdc_am33xx_clkdm,
+        &clk_24mhz_am33xx_clkdm,
+        &l4_wkup_am33xx_clkdm,
+        &l3_aon_am33xx_clkdm,
+        &l4_wkup_aon_am33xx_clkdm,
+        &mpu_am33xx_clkdm,
+        &l4_rtc_am33xx_clkdm,
+        &gfx_l3_am33xx_clkdm,
+        &gfx_l4ls_gfx_am33xx_clkdm,
+        &l4_cefuse_am33xx_clkdm,
+        NULL,
+};
+
+void __init am33xx_clockdomains_init(void)
+{
+        clkdm_register_platform_funcs(&am33xx_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_am33xx);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 6038adb9771..56089c49142 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -59,6 +59,12 @@ static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep gfx_sgx_am35x_wkdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
 /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
 static struct clkdm_dep per_wkdeps[] = {
         { .clkdm_name = "core_l3_clkdm" },
@@ -69,6 +75,14 @@ static struct clkdm_dep per_wkdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep per_am35x_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
 /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
 static struct clkdm_dep usbhost_wkdeps[] = {
         { .clkdm_name = "core_l3_clkdm" },
@@ -79,6 +93,14 @@ static struct clkdm_dep usbhost_wkdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep usbhost_am35x_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
 /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
 static struct clkdm_dep mpu_3xxx_wkdeps[] = {
         { .clkdm_name = "core_l3_clkdm" },
@@ -89,6 +111,14 @@ static struct clkdm_dep mpu_3xxx_wkdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep mpu_am35x_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "per_clkdm" },
+        { NULL },
+};
+
 /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
 static struct clkdm_dep iva2_wkdeps[] = {
         { .clkdm_name = "core_l3_clkdm" },
@@ -116,6 +146,12 @@ static struct clkdm_dep dss_wkdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep dss_am35x_wkdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
 /* 3430: PM_WKDEP_NEON: MPU */
 static struct clkdm_dep neon_wkdeps[] = {
         { .clkdm_name = "mpu_clkdm" },
@@ -131,6 +167,11 @@ static struct clkdm_dep dss_sleepdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep dss_am35x_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+
 /* 3430: CM_SLEEPDEP_PER: MPU, IVA */
 static struct clkdm_dep per_sleepdeps[] = {
         { .clkdm_name = "mpu_clkdm" },
@@ -138,6 +179,11 @@ static struct clkdm_dep per_sleepdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep per_am35x_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+
 /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
 static struct clkdm_dep usbhost_sleepdeps[] = {
         { .clkdm_name = "mpu_clkdm" },
@@ -145,6 +191,11 @@ static struct clkdm_dep usbhost_sleepdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep usbhost_am35x_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+
 /* 3430: CM_SLEEPDEP_CAM: MPU */
 static struct clkdm_dep cam_sleepdeps[] = {
         { .clkdm_name = "mpu_clkdm" },
@@ -175,6 +226,15 @@ static struct clockdomain mpu_3xxx_clkdm = {
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
 };
 
+static struct clockdomain mpu_am35x_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
+        .dep_bit        = OMAP3430_EN_MPU_SHIFT,
+        .wkdep_srcs     = mpu_am35x_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
+};
+
 static struct clockdomain neon_clkdm = {
         .name           = "neon_clkdm",
         .pwrdm          = { .name = "neon_pwrdm" },
@@ -210,6 +270,15 @@ static struct clockdomain sgx_clkdm = {
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
 };
 
+static struct clockdomain sgx_am35x_clkdm = {
+        .name           = "sgx_clkdm",
+        .pwrdm          = { .name = "sgx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_sgx_am35x_wkdeps,
+        .sleepdep_srcs  = gfx_sgx_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
+};
+
 /*
  * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
  * then that information was removed from the 34xx ES2+ TRM.  It is
@@ -261,6 +330,16 @@ static struct clockdomain dss_3xxx_clkdm = {
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
 };
 
+static struct clockdomain dss_am35x_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "dss_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
+        .wkdep_srcs     = dss_am35x_wkdeps,
+        .sleepdep_srcs  = dss_am35x_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
+};
+
 static struct clockdomain cam_clkdm = {
         .name           = "cam_clkdm",
         .pwrdm          = { .name = "cam_pwrdm" },
@@ -279,6 +358,15 @@ static struct clockdomain usbhost_clkdm = {
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
 };
 
+static struct clockdomain usbhost_am35x_clkdm = {
+        .name           = "usbhost_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = usbhost_am35x_wkdeps,
+        .sleepdep_srcs  = usbhost_am35x_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
+};
+
 static struct clockdomain per_clkdm = {
         .name           = "per_clkdm",
         .pwrdm          = { .name = "per_pwrdm" },
@@ -289,6 +377,16 @@ static struct clockdomain per_clkdm = {
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 };
 
+static struct clockdomain per_am35x_clkdm = {
+        .name           = "per_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_EN_PER_SHIFT,
+        .wkdep_srcs     = per_am35x_wkdeps,
+        .sleepdep_srcs  = per_am35x_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
+};
+
 /*
  * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
  * switched of even if sdti is in use
@@ -341,31 +439,42 @@ static struct clkdm_autodep clkdm_autodeps[] = {
         }
 };
 
+static struct clkdm_autodep clkdm_am35x_autodeps[] = {
+        {
+                .clkdm = { .name = "mpu_clkdm" },
+        },
+        {
+                .clkdm = { .name = NULL },
+        }
+};
+
 /*
  *
  */
 
-static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
+static struct clockdomain *clockdomains_common[] __initdata = {
         &wkup_common_clkdm,
-        &cm_common_clkdm,
-        &prm_common_clkdm,
-        &mpu_3xxx_clkdm,
         &neon_clkdm,
-        &iva2_clkdm,
-        &d2d_clkdm,
         &core_l3_3xxx_clkdm,
         &core_l4_3xxx_clkdm,
-        &dss_3xxx_clkdm,
-        &cam_clkdm,
-        &per_clkdm,
         &emu_clkdm,
         &dpll1_clkdm,
-        &dpll2_clkdm,
         &dpll3_clkdm,
         &dpll4_clkdm,
         NULL
 };
 
+static struct clockdomain *clockdomains_omap3430[] __initdata = {
+        &mpu_3xxx_clkdm,
+        &iva2_clkdm,
+        &d2d_clkdm,
+        &dss_3xxx_clkdm,
+        &cam_clkdm,
+        &per_clkdm,
+        &dpll2_clkdm,
+        NULL
+};
+
 static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
         &gfx_3430es1_clkdm,
         NULL,
@@ -378,21 +487,41 @@ static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
         NULL,
 };
 
+static struct clockdomain *clockdomains_am35x[] __initdata = {
+        &mpu_am35x_clkdm,
+        &sgx_am35x_clkdm,
+        &dss_am35x_clkdm,
+        &per_am35x_clkdm,
+        &usbhost_am35x_clkdm,
+        &dpll5_clkdm,
+        NULL
+};
+
 void __init omap3xxx_clockdomains_init(void)
 {
         struct clockdomain **sc;
+        unsigned int rev;
 
         if (!cpu_is_omap34xx())
                 return;
 
         clkdm_register_platform_funcs(&omap3_clkdm_operations);
-        clkdm_register_clkdms(clockdomains_omap3430_common);
+        clkdm_register_clkdms(clockdomains_common);
 
-        sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
-                clockdomains_omap3430es2plus;
+        rev = omap_rev();
 
-        clkdm_register_clkdms(sc);
+        if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
+                clkdm_register_clkdms(clockdomains_am35x);
+                clkdm_register_autodeps(clkdm_am35x_autodeps);
+        } else {
+                clkdm_register_clkdms(clockdomains_omap3430);
+
+                sc = (rev == OMAP3430_REV_ES1_0) ?
+                        clockdomains_omap3430es1 : clockdomains_omap3430es2plus;
+
+                clkdm_register_clkdms(sc);
+                clkdm_register_autodeps(clkdm_autodeps);
+        }
 
-        clkdm_register_autodeps(clkdm_autodeps);
         clkdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 7f2133abe7d..63d60a773d3 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -430,8 +430,6 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
         &l4_wkup_44xx_clkdm,
         &emu_sys_44xx_clkdm,
         &l3_dma_44xx_clkdm,
-        &prm_common_clkdm,
-        &cm_common_clkdm,
         NULL
 };
 
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c
deleted file mode 100644
index 615b1f04967..00000000000
--- a/arch/arm/mach-omap2/clockdomains_common_data.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * OMAP2+-common clockdomain data
- *
- * Copyright (C) 2008-2012 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Paul Walmsley, Jouni Högander
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-
-#include "clockdomain.h"
-
-/* These are implicit clockdomains - they are never defined as such in TRM */
-struct clockdomain prm_common_clkdm = {
-        .name           = "prm_clkdm",
-        .pwrdm          = { .name = "wkup_pwrdm" },
-};
-
-struct clockdomain cm_common_clkdm = {
-        .name           = "cm_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-};
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
new file mode 100644
index 00000000000..532027ee3d8
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -0,0 +1,687 @@
+/*
+ * AM33XX Power Management register bits
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
+
+/*
+ * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
+ * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
+ */
+#define AM33XX_AUTO_DPLL_MODE_SHIFT                     0
+#define AM33XX_AUTO_DPLL_MODE_MASK                      (0x7 << 0)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT               14
+#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK                (1 << 16)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT                11
+#define AM33XX_CLKACTIVITY_CAN_CLK_MASK                 (1 << 11)
+
+/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK          (1 << 4)
+
+/* Used by CM_PER_CPSW_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK        (1 << 4)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK        (1 << 4)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT        5
+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK         (1 << 5)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT         6
+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK          (1 << 6)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT          6
+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK           (1 << 6)
+
+/* Used by CM_CEFUSE_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT     9
+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK      (1 << 9)
+
+/* Used by CM_L3_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK               (1 << 2)
+
+/* Used by CM_L3_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT             4
+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK              (1 << 4)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK               (1 << 2)
+
+/* Used by CM_GFX_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT               9
+#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK                (1 << 9)
+
+/* Used by CM_GFX_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK             (1 << 8)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT           8
+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK            (1 << 8)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT          19
+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK           (1 << 19)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT          20
+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK           (1 << 20)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT          21
+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK           (1 << 21)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT          22
+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK           (1 << 22)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT          26
+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK           (1 << 26)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT          18
+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK           (1 << 18)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT             11
+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK              (1 << 11)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT               24
+#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK                (1 << 24)
+
+/* Used by CM_PER_PRUSS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT         5
+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK          (1 << 5)
+
+/* Used by CM_PER_PRUSS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK          (1 << 4)
+
+/* Used by CM_PER_PRUSS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT        6
+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK         (1 << 6)
+
+/* Used by CM_PER_L3S_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK                (1 << 3)
+
+/* Used by CM_L3_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT            3
+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK             (1 << 3)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT                4
+#define AM33XX_CLKACTIVITY_L3_GCLK_MASK                 (1 << 4)
+
+/* Used by CM_PER_L4FW_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK               (1 << 8)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK               (1 << 3)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK               (1 << 8)
+
+/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT          8
+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK           (1 << 8)
+
+/* Used by CM_CEFUSE_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT        8
+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK         (1 << 8)
+
+/* Used by CM_RTC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK             (1 << 8)
+
+/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT       2
+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK        (1 << 2)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT           2
+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK            (1 << 2)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT              17
+#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK               (1 << 17)
+
+/* Used by CM_PER_LCDC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK        (1 << 4)
+
+/* Used by CM_PER_LCDC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT       5
+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK        (1 << 5)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT             7
+#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK              (1 << 7)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK                (1 << 3)
+
+/* Used by CM_MPU_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT                2
+#define AM33XX_CLKACTIVITY_MPU_CLK_MASK                 (1 << 2)
+
+/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT          4
+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK           (1 << 4)
+
+/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT          5
+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK           (1 << 5)
+
+/* Used by CM_RTC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT             9
+#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK              (1 << 9)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT               25
+#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK                (1 << 25)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK               (1 << 3)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT            10
+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK             (1 << 10)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK             (1 << 13)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT            14
+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK             (1 << 14)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT            15
+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK             (1 << 15)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT            16
+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK             (1 << 16)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT            27
+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK             (1 << 27)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT            28
+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK             (1 << 28)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK             (1 << 13)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT            12
+#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK             (1 << 12)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT             10
+#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK              (1 << 10)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT              9
+#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK               (1 << 9)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT              4
+#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK               (1 << 4)
+
+/* Used by CLKSEL_GFX_FCLK */
+#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT                0
+#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK                 (1 << 0)
+
+/* Used by CM_CLKOUT_CTRL */
+#define AM33XX_CLKOUT2DIV_SHIFT                         3
+#define AM33XX_CLKOUT2DIV_MASK                          (0x05 << 3)
+
+/* Used by CM_CLKOUT_CTRL */
+#define AM33XX_CLKOUT2EN_SHIFT                          7
+#define AM33XX_CLKOUT2EN_MASK                           (1 << 7)
+
+/* Used by CM_CLKOUT_CTRL */
+#define AM33XX_CLKOUT2SOURCE_SHIFT                      0
+#define AM33XX_CLKOUT2SOURCE_MASK                       (0x02 << 0)
+
+/*
+ * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
+ * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
+ * CLKSEL_TIMER7_CLK
+ */
+#define AM33XX_CLKSEL_SHIFT                             0
+#define AM33XX_CLKSEL_MASK                              (0x01 << 0)
+
+/*
+ * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
+ * CM_CPTS_RFT_CLKSEL
+ */
+#define AM33XX_CLKSEL_0_0_SHIFT                         0
+#define AM33XX_CLKSEL_0_0_MASK                          (1 << 0)
+
+#define AM33XX_CLKSEL_0_1_SHIFT                         0
+#define AM33XX_CLKSEL_0_1_MASK                          (3 << 0)
+
+/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
+#define AM33XX_CLKSEL_0_2_SHIFT                         0
+#define AM33XX_CLKSEL_0_2_MASK                          (7 << 0)
+
+/* Used by CLKSEL_GFX_FCLK */
+#define AM33XX_CLKSEL_GFX_FCLK_SHIFT                    1
+#define AM33XX_CLKSEL_GFX_FCLK_MASK                     (1 << 1)
+
+/*
+ * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
+ * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
+ * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
+ * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
+ * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
+ * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
+ */
+#define AM33XX_CLKTRCTRL_SHIFT                          0
+#define AM33XX_CLKTRCTRL_MASK                           (0x3 << 0)
+
+/*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
+ * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
+ * CM_SSC_DELTAMSTEP_DPLL_PER
+ */
+#define AM33XX_DELTAMSTEP_SHIFT                         0
+#define AM33XX_DELTAMSTEP_MASK                          (0x19 << 0)
+
+/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
+#define AM33XX_DPLL_BYP_CLKSEL_SHIFT                    23
+#define AM33XX_DPLL_BYP_CLKSEL_MASK                     (1 << 23)
+
+/* Used by CM_CLKDCOLDO_DPLL_PER */
+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT           8
+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK            (1 << 8)
+
+/* Used by CM_CLKDCOLDO_DPLL_PER */
+#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT                12
+#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK                 (1 << 12)
+
+/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
+#define AM33XX_DPLL_CLKOUT_DIV_SHIFT                    0
+#define AM33XX_DPLL_CLKOUT_DIV_MASK                     (0x1f << 0)
+
+/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT                0
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x06 << 0)
+
+/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT               5
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK                (1 << 5)
+
+/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT        7
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK         (1 << 7)
+
+/*
+ * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER
+ */
+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT              8
+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK               (1 << 8)
+
+/*
+ * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
+ * CM_CLKSEL_DPLL_MPU
+ */
+#define AM33XX_DPLL_DIV_SHIFT                           0
+#define AM33XX_DPLL_DIV_MASK                            (0x7f << 0)
+
+#define AM33XX_DPLL_PER_DIV_MASK                        (0xff << 0)
+
+/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
+#define AM33XX_DPLL_DIV_0_7_SHIFT                       0
+#define AM33XX_DPLL_DIV_0_7_MASK                        (0x07 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU
+ */
+#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT                 8
+#define AM33XX_DPLL_DRIFTGUARD_EN_MASK                  (1 << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_EN_SHIFT                            0
+#define AM33XX_DPLL_EN_MASK                             (0x7 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU
+ */
+#define AM33XX_DPLL_LPMODE_EN_SHIFT                     10
+#define AM33XX_DPLL_LPMODE_EN_MASK                      (1 << 10)
+
+/*
+ * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
+ * CM_CLKSEL_DPLL_MPU
+ */
+#define AM33XX_DPLL_MULT_SHIFT                          8
+#define AM33XX_DPLL_MULT_MASK                           (0x7ff << 8)
+
+/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
+#define AM33XX_DPLL_MULT_PERIPH_SHIFT                   8
+#define AM33XX_DPLL_MULT_PERIPH_MASK                    (0xfff << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU
+ */
+#define AM33XX_DPLL_REGM4XEN_SHIFT                      11
+#define AM33XX_DPLL_REGM4XEN_MASK                       (1 << 11)
+
+/* Used by CM_CLKSEL_DPLL_PERIPH */
+#define AM33XX_DPLL_SD_DIV_SHIFT                        24
+#define AM33XX_DPLL_SD_DIV_MASK                         (24, 31)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_SSC_ACK_SHIFT                       13
+#define AM33XX_DPLL_SSC_ACK_MASK                        (1 << 13)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT                14
+#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK                 (1 << 14)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_SSC_EN_SHIFT                        12
+#define AM33XX_DPLL_SSC_EN_MASK                         (1 << 12)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK               (0x1f << 0)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK          (1 << 5)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK         (1 << 8)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK              (1 << 12)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK               (0x1f << 0)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK          (1 << 5)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK         (1 << 8)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK              (1 << 12)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x04 << 0)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK          (1 << 5)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK         (1 << 8)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK              (1 << 12)
+
+/*
+ * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
+ * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
+ * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
+ * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
+ * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
+ * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
+ * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
+ * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
+ * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
+ * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
+ * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
+ * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
+ * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
+ * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
+ * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
+ * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
+ * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
+ * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
+ * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
+ * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
+ * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
+ * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
+ * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
+ * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
+ * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
+ */
+#define AM33XX_IDLEST_SHIFT                             16
+#define AM33XX_IDLEST_MASK                              (0x3 << 16)
+#define AM33XX_IDLEST_VAL                               0x3
+
+/* Used by CM_MAC_CLKSEL */
+#define AM33XX_MII_CLK_SEL_SHIFT                        2
+#define AM33XX_MII_CLK_SEL_MASK                         (1 << 2)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
+ * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER
+ */
+#define AM33XX_MODFREQDIV_EXPONENT_SHIFT                8
+#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x10 << 8)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
+ * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER
+ */
+#define AM33XX_MODFREQDIV_MANTISSA_SHIFT                0
+#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x06 << 0)
+
+/*
+ * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
+ * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
+ * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
+ * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
+ * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
+ * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
+ * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
+ * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
+ * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
+ * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
+ * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
+ * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
+ * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
+ * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
+ * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
+ * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
+ * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
+ * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
+ * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
+ * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
+ * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
+ * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
+ * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
+ * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
+ * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
+ * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
+ * CM_CEFUSE_CEFUSE_CLKCTRL
+ */
+#define AM33XX_MODULEMODE_SHIFT                         0
+#define AM33XX_MODULEMODE_MASK                          (0x3 << 0)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT                  30
+#define AM33XX_OPTCLK_DEBUG_CLKA_MASK                   (1 << 30)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT                19
+#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK                 (1 << 19)
+
+/* Used by CM_WKUP_GPIO0_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT             18
+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK              (1 << 18)
+
+/* Used by CM_PER_GPIO1_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK             (1 << 18)
+
+/* Used by CM_PER_GPIO2_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK             (1 << 18)
+
+/* Used by CM_PER_GPIO3_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK             (1 << 18)
+
+/* Used by CM_PER_GPIO4_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK             (1 << 18)
+
+/* Used by CM_PER_GPIO5_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK             (1 << 18)
+
+/* Used by CM_PER_GPIO6_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK             (1 << 18)
+
+/*
+ * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
+ * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
+ * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
+ * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
+ */
+#define AM33XX_STBYST_SHIFT                             18
+#define AM33XX_STBYST_MASK                              (1 << 18)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT                  27
+#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x29 << 27)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_STM_PMD_CLKSEL_SHIFT                     22
+#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x23 << 22)
+
+/*
+ * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
+ */
+#define AM33XX_ST_DPLL_CLK_SHIFT                        0
+#define AM33XX_ST_DPLL_CLK_MASK                         (1 << 0)
+
+/* Used by CM_CLKDCOLDO_DPLL_PER */
+#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT                  8
+#define AM33XX_ST_DPLL_CLKDCOLDO_MASK                   (1 << 8)
+
+/*
+ * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER
+ */
+#define AM33XX_ST_DPLL_CLKOUT_SHIFT                     9
+#define AM33XX_ST_DPLL_CLKOUT_MASK                      (1 << 9)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK                (1 << 9)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK                (1 << 9)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK                (1 << 9)
+
+/*
+ * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
+ */
+#define AM33XX_ST_MN_BYPASS_SHIFT                       8
+#define AM33XX_ST_MN_BYPASS_MASK                        (1 << 8)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT                  24
+#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x26 << 24)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_TRC_PMD_CLKSEL_SHIFT                     20
+#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x21 << 20)
+
+/* Used by CONTROL_SEC_CLK_CTRL */
+#define AM33XX_TIMER0_CLKSEL_MASK                       (0x3 << 4)
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 8083a8cdc55..766338fe4d3 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -169,8 +169,6 @@
 /* AM35XX specific CM_ICLKEN1_CORE bits */
 #define AM35XX_EN_IPSS_MASK                             (1 << 4)
 #define AM35XX_EN_IPSS_SHIFT                            4
-#define AM35XX_EN_UART4_MASK                            (1 << 23)
-#define AM35XX_EN_UART4_SHIFT                           23
 
 /* CM_ICLKEN2_CORE */
 #define OMAP3430_EN_PKA_MASK                            (1 << 4)
@@ -207,6 +205,8 @@
 #define OMAP3430_ST_DES2_MASK                           (1 << 26)
 #define OMAP3430_ST_MSPRO_SHIFT                         23
 #define OMAP3430_ST_MSPRO_MASK                          (1 << 23)
+#define AM35XX_ST_UART4_SHIFT                           23
+#define AM35XX_ST_UART4_MASK                            (1 << 23)
 #define OMAP3430_ST_HDQ_SHIFT                           22
 #define OMAP3430_ST_HDQ_MASK                            (1 << 22)
 #define OMAP3430ES1_ST_FAC_SHIFT                        8
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
new file mode 100644
index 00000000000..13f56eafef0
--- /dev/null
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -0,0 +1,313 @@
+/*
+ * AM33XX CM functions
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Reference taken from from OMAP4 cminst44xx.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "cm.h"
+#include "cm33xx.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-33xx.h"
+#include "prm33xx.h"
+
+/*
+ * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
+ *
+ *   0x0 func:     Module is fully functional, including OCP
+ *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
+ *                 abortion
+ *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
+ *                 using separate functional clock
+ *   0x3 disabled: Module is disabled and cannot be accessed
+ *
+ */
+#define CLKCTRL_IDLEST_FUNCTIONAL               0x0
+#define CLKCTRL_IDLEST_INTRANSITION             0x1
+#define CLKCTRL_IDLEST_INTERFACE_IDLE           0x2
+#define CLKCTRL_IDLEST_DISABLED                 0x3
+
+/* Private functions */
+
+/* Read a register in a CM instance */
+static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
+{
+        return __raw_readl(cm_base + inst + idx);
+}
+
+/* Write into a register in a CM */
+static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
+{
+        __raw_writel(val, cm_base + inst + idx);
+}
+
+/* Read-modify-write a register in CM */
+static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, idx);
+        v &= ~mask;
+        v |= bits;
+        am33xx_cm_write_reg(v, inst, idx);
+
+        return v;
+}
+
+static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
+{
+        return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
+}
+
+static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
+{
+        return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
+}
+
+static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, idx);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+/**
+ * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
+ * bit 0.
+ */
+static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
+        v &= AM33XX_IDLEST_MASK;
+        v >>= AM33XX_IDLEST_SHIFT;
+        return v;
+}
+
+/**
+ * _is_module_ready - can module registers be accessed without causing an abort?
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
+ * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
+ */
+static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        u32 v;
+
+        v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
+
+        return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
+                v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
+}
+
+/**
+ * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
+ * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * @c must be the unshifted value for CLKTRCTRL - i.e., this function
+ * will handle the shift itself.
+ */
+static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, cdoffs);
+        v &= ~AM33XX_CLKTRCTRL_MASK;
+        v |= c << AM33XX_CLKTRCTRL_SHIFT;
+        am33xx_cm_write_reg(v, inst, cdoffs);
+}
+
+/* Public functions */
+
+/**
+ * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Returns true if the clockdomain referred to by (@inst, @cdoffs)
+ * is in hardware-supervised idle mode, or 0 otherwise.
+ */
+bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, cdoffs);
+        v &= AM33XX_CLKTRCTRL_MASK;
+        v >>= AM33XX_CLKTRCTRL_SHIFT;
+
+        return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
+}
+
+/**
+ * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@inst, @cdoffs) into
+ * hardware-supervised idle mode.  No return value.
+ */
+void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
+}
+
+/**
+ * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@inst, @cdoffs) into
+ * software-supervised idle mode, i.e., controlled manually by the
+ * Linux OMAP clockdomain code.  No return value.
+ */
+void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
+}
+
+/**
+ * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@inst, @cdoffs) into idle
+ * No return value.
+ */
+void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
+}
+
+/**
+ * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
+ * waking it up.  No return value.
+ */
+void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
+}
+
+/*
+ *
+ */
+
+/**
+ * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Wait for the module IDLEST to be functional. If the idle state is in any
+ * the non functional state (trans, idle or disabled), module and thus the
+ * sysconfig cannot be accessed and will probably lead to an "imprecise
+ * external abort"
+ */
+int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        int i = 0;
+
+        if (!clkctrl_offs)
+                return 0;
+
+        omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
+                          MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/**
+ * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
+ * state
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Wait for the module IDLEST to be disabled. Some PRCM transition,
+ * like reset assertion or parent clock de-activation must wait the
+ * module to be fully disabled.
+ */
+int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        int i = 0;
+
+        if (!clkctrl_offs)
+                return 0;
+
+        omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
+                                CLKCTRL_IDLEST_DISABLED),
+                                MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/**
+ * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
+ * @mode: Module mode (SW or HW)
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * No return value.
+ */
+void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, clkctrl_offs);
+        v &= ~AM33XX_MODULEMODE_MASK;
+        v |= mode << AM33XX_MODULEMODE_SHIFT;
+        am33xx_cm_write_reg(v, inst, clkctrl_offs);
+}
+
+/**
+ * am33xx_cm_module_disable - Disable the module inside CLKCTRL
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * No return value.
+ */
+void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, clkctrl_offs);
+        v &= ~AM33XX_MODULEMODE_MASK;
+        am33xx_cm_write_reg(v, inst, clkctrl_offs);
+}
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
new file mode 100644
index 00000000000..5fa0b62e1a7
--- /dev/null
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -0,0 +1,420 @@
+/*
+ * AM33XX CM offset macros
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
+
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "common.h"
+
+#include "cm.h"
+#include "cm-regbits-33xx.h"
+#include "cm33xx.h"
+
+/* CM base address */
+#define AM33XX_CM_BASE          0x44e00000
+
+#define AM33XX_CM_REGADDR(inst, reg)                            \
+        AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
+
+/* CM instances */
+#define AM33XX_CM_PER_MOD               0x0000
+#define AM33XX_CM_WKUP_MOD              0x0400
+#define AM33XX_CM_DPLL_MOD              0x0500
+#define AM33XX_CM_MPU_MOD               0x0600
+#define AM33XX_CM_DEVICE_MOD            0x0700
+#define AM33XX_CM_RTC_MOD               0x0800
+#define AM33XX_CM_GFX_MOD               0x0900
+#define AM33XX_CM_CEFUSE_MOD            0x0A00
+
+/* CM */
+
+/* CM.PER_CM register offsets */
+#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET             0x0000
+#define AM33XX_CM_PER_L4LS_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
+#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET              0x0004
+#define AM33XX_CM_PER_L3S_CLKSTCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
+#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET             0x0008
+#define AM33XX_CM_PER_L4FW_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
+#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET               0x000c
+#define AM33XX_CM_PER_L3_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
+#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET            0x0014
+#define AM33XX_CM_PER_CPGMAC0_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
+#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET               0x0018
+#define AM33XX_CM_PER_LCDC_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
+#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET               0x001c
+#define AM33XX_CM_PER_USB0_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
+#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET                0x0020
+#define AM33XX_CM_PER_MLB_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
+#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET              0x0024
+#define AM33XX_CM_PER_TPTC0_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
+#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET               0x0028
+#define AM33XX_CM_PER_EMIF_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
+#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET            0x002c
+#define AM33XX_CM_PER_OCMCRAM_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
+#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET               0x0030
+#define AM33XX_CM_PER_GPMC_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
+#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET             0x0034
+#define AM33XX_CM_PER_MCASP0_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
+#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET              0x0038
+#define AM33XX_CM_PER_UART5_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
+#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET               0x003c
+#define AM33XX_CM_PER_MMC0_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
+#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET                0x0040
+#define AM33XX_CM_PER_ELM_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
+#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET               0x0044
+#define AM33XX_CM_PER_I2C2_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
+#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET               0x0048
+#define AM33XX_CM_PER_I2C1_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
+#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET               0x004c
+#define AM33XX_CM_PER_SPI0_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
+#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET               0x0050
+#define AM33XX_CM_PER_SPI1_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
+#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET               0x0054
+#define AM33XX_CM_PER_SPI2_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
+#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET               0x0058
+#define AM33XX_CM_PER_SPI3_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
+#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET               0x0060
+#define AM33XX_CM_PER_L4LS_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
+#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET               0x0064
+#define AM33XX_CM_PER_L4FW_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
+#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET             0x0068
+#define AM33XX_CM_PER_MCASP1_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
+#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET              0x006c
+#define AM33XX_CM_PER_UART1_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
+#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET              0x0070
+#define AM33XX_CM_PER_UART2_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
+#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET              0x0074
+#define AM33XX_CM_PER_UART3_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
+#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET              0x0078
+#define AM33XX_CM_PER_UART4_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
+#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET             0x007c
+#define AM33XX_CM_PER_TIMER7_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
+#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET             0x0080
+#define AM33XX_CM_PER_TIMER2_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
+#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET             0x0084
+#define AM33XX_CM_PER_TIMER3_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
+#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET             0x0088
+#define AM33XX_CM_PER_TIMER4_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
+#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET             0x008c
+#define AM33XX_CM_PER_MCASP2_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
+#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET                0x0090
+#define AM33XX_CM_PER_RNG_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
+#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET               0x0094
+#define AM33XX_CM_PER_AES0_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
+#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET               0x0098
+#define AM33XX_CM_PER_AES1_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
+#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET                0x009c
+#define AM33XX_CM_PER_DES_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
+#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET               0x00a0
+#define AM33XX_CM_PER_SHA0_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
+#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET                0x00a4
+#define AM33XX_CM_PER_PKA_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
+#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET              0x00a8
+#define AM33XX_CM_PER_GPIO6_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
+#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET              0x00ac
+#define AM33XX_CM_PER_GPIO1_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
+#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET              0x00b0
+#define AM33XX_CM_PER_GPIO2_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
+#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET              0x00b4
+#define AM33XX_CM_PER_GPIO3_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
+#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET              0x00b8
+#define AM33XX_CM_PER_GPIO4_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
+#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET               0x00bc
+#define AM33XX_CM_PER_TPCC_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
+#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET              0x00c0
+#define AM33XX_CM_PER_DCAN0_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
+#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET              0x00c4
+#define AM33XX_CM_PER_DCAN1_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
+#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET            0x00cc
+#define AM33XX_CM_PER_EPWMSS1_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
+#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET            0x00d0
+#define AM33XX_CM_PER_EMIF_FW_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
+#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET            0x00d4
+#define AM33XX_CM_PER_EPWMSS0_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
+#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET            0x00d8
+#define AM33XX_CM_PER_EPWMSS2_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
+#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET           0x00dc
+#define AM33XX_CM_PER_L3_INSTR_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
+#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET                 0x00e0
+#define AM33XX_CM_PER_L3_CLKCTRL                        AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
+#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET           0x00e4
+#define AM33XX_CM_PER_IEEE5000_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
+#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET              0x00e8
+#define AM33XX_CM_PER_PRUSS_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
+#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET             0x00ec
+#define AM33XX_CM_PER_TIMER5_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
+#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET             0x00f0
+#define AM33XX_CM_PER_TIMER6_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
+#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET               0x00f4
+#define AM33XX_CM_PER_MMC1_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
+#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET               0x00f8
+#define AM33XX_CM_PER_MMC2_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
+#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET              0x00fc
+#define AM33XX_CM_PER_TPTC1_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
+#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET              0x0100
+#define AM33XX_CM_PER_TPTC2_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
+#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET              0x0104
+#define AM33XX_CM_PER_GPIO5_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
+#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET           0x010c
+#define AM33XX_CM_PER_SPINLOCK_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
+#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET           0x0110
+#define AM33XX_CM_PER_MAILBOX0_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
+#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET             0x011c
+#define AM33XX_CM_PER_L4HS_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
+#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET               0x0120
+#define AM33XX_CM_PER_L4HS_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
+#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET          0x0124
+#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL                 AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
+#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET           0x0128
+#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
+#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET         0x012c
+#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL                AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
+#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET              0x0130
+#define AM33XX_CM_PER_OCPWP_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
+#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET           0x0134
+#define AM33XX_CM_PER_MAILBOX1_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
+#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET            0x0140
+#define AM33XX_CM_PER_PRUSS_CLKSTCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
+#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET             0x0144
+#define AM33XX_CM_PER_CPSW_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
+#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET             0x0148
+#define AM33XX_CM_PER_LCDC_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
+#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET          0x014c
+#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL                 AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
+#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET        0x0150
+#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL               AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
+
+/* CM.WKUP_CM register offsets */
+#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET                 0x0000
+#define AM33XX_CM_WKUP_CLKSTCTRL                        AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
+#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET           0x0004
+#define AM33XX_CM_WKUP_CONTROL_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
+#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET             0x0008
+#define AM33XX_CM_WKUP_GPIO0_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
+#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET            0x000c
+#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
+#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET            0x0010
+#define AM33XX_CM_WKUP_TIMER0_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
+#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET           0x0014
+#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
+#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET               0x0018
+#define AM33XX_CM_L3_AON_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
+#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET              0x001c
+#define AM33XX_CM_AUTOIDLE_DPLL_MPU                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
+#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET                0x0020
+#define AM33XX_CM_IDLEST_DPLL_MPU                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET        0x0024
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET        0x0028
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
+#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET                0x002c
+#define AM33XX_CM_CLKSEL_DPLL_MPU                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
+#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET              0x0030
+#define AM33XX_CM_AUTOIDLE_DPLL_DDR                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
+#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET                0x0034
+#define AM33XX_CM_IDLEST_DPLL_DDR                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET        0x0038
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET        0x003c
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
+#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET                0x0040
+#define AM33XX_CM_CLKSEL_DPLL_DDR                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
+#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET             0x0044
+#define AM33XX_CM_AUTOIDLE_DPLL_DISP                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
+#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET               0x0048
+#define AM33XX_CM_IDLEST_DPLL_DISP                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET       0x004c
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP              AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET       0x0050
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP              AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
+#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET               0x0054
+#define AM33XX_CM_CLKSEL_DPLL_DISP                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
+#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET             0x0058
+#define AM33XX_CM_AUTOIDLE_DPLL_CORE                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
+#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET               0x005c
+#define AM33XX_CM_IDLEST_DPLL_CORE                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET       0x0060
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE              AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET       0x0064
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE              AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
+#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET               0x0068
+#define AM33XX_CM_CLKSEL_DPLL_CORE                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
+#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET              0x006c
+#define AM33XX_CM_AUTOIDLE_DPLL_PER                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
+#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET                0x0070
+#define AM33XX_CM_IDLEST_DPLL_PER                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET        0x0074
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET        0x0078
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
+#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET             0x007c
+#define AM33XX_CM_CLKDCOLDO_DPLL_PER                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
+#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET               0x0080
+#define AM33XX_CM_DIV_M4_DPLL_CORE                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
+#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET               0x0084
+#define AM33XX_CM_DIV_M5_DPLL_CORE                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
+#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET               0x0088
+#define AM33XX_CM_CLKMODE_DPLL_MPU                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
+#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET               0x008c
+#define AM33XX_CM_CLKMODE_DPLL_PER                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
+#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET              0x0090
+#define AM33XX_CM_CLKMODE_DPLL_CORE                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
+#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET               0x0094
+#define AM33XX_CM_CLKMODE_DPLL_DDR                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
+#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET              0x0098
+#define AM33XX_CM_CLKMODE_DPLL_DISP                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
+#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET             0x009c
+#define AM33XX_CM_CLKSEL_DPLL_PERIPH                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
+#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET                0x00a0
+#define AM33XX_CM_DIV_M2_DPLL_DDR                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
+#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET               0x00a4
+#define AM33XX_CM_DIV_M2_DPLL_DISP                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
+#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET                0x00a8
+#define AM33XX_CM_DIV_M2_DPLL_MPU                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
+#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET                0x00ac
+#define AM33XX_CM_DIV_M2_DPLL_PER                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
+#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET           0x00b0
+#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
+#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET             0x00b4
+#define AM33XX_CM_WKUP_UART0_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
+#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET              0x00b8
+#define AM33XX_CM_WKUP_I2C0_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
+#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET           0x00bc
+#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
+#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET      0x00c0
+#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL             AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
+#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET            0x00c4
+#define AM33XX_CM_WKUP_TIMER1_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
+#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET      0x00c8
+#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL             AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
+#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET          0x00cc
+#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL                 AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
+#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET              0x00d0
+#define AM33XX_CM_WKUP_WDT0_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
+#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET              0x00d4
+#define AM33XX_CM_WKUP_WDT1_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
+#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET               0x00d8
+#define AM33XX_CM_DIV_M6_DPLL_CORE                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
+
+/* CM.DPLL_CM register offsets */
+#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET                 0x0004
+#define AM33XX_CLKSEL_TIMER7_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
+#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET                 0x0008
+#define AM33XX_CLKSEL_TIMER2_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
+#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET                 0x000c
+#define AM33XX_CLKSEL_TIMER3_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
+#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET                 0x0010
+#define AM33XX_CLKSEL_TIMER4_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
+#define AM33XX_CM_MAC_CLKSEL_OFFSET                     0x0014
+#define AM33XX_CM_MAC_CLKSEL                            AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
+#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET                 0x0018
+#define AM33XX_CLKSEL_TIMER5_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
+#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET                 0x001c
+#define AM33XX_CLKSEL_TIMER6_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
+#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET                0x0020
+#define AM33XX_CM_CPTS_RFT_CLKSEL                       AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
+#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET               0x0028
+#define AM33XX_CLKSEL_TIMER1MS_CLK                      AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
+#define AM33XX_CLKSEL_GFX_FCLK_OFFSET                   0x002c
+#define AM33XX_CLKSEL_GFX_FCLK                          AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
+#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET              0x0030
+#define AM33XX_CLKSEL_PRUSS_OCP_CLK                     AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
+#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET             0x0034
+#define AM33XX_CLKSEL_LCDC_PIXEL_CLK                    AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
+#define AM33XX_CLKSEL_WDT1_CLK_OFFSET                   0x0038
+#define AM33XX_CLKSEL_WDT1_CLK                          AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
+#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET                0x003c
+#define AM33XX_CLKSEL_GPIO0_DBCLK                       AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
+
+/* CM.MPU_CM register offsets */
+#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET                  0x0000
+#define AM33XX_CM_MPU_CLKSTCTRL                         AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
+#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET                0x0004
+#define AM33XX_CM_MPU_MPU_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
+
+/* CM.DEVICE_CM register offsets */
+#define AM33XX_CM_CLKOUT_CTRL_OFFSET                    0x0000
+#define AM33XX_CM_CLKOUT_CTRL                           AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
+
+/* CM.RTC_CM register offsets */
+#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET                0x0000
+#define AM33XX_CM_RTC_RTC_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
+#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET                  0x0004
+#define AM33XX_CM_RTC_CLKSTCTRL                         AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
+
+/* CM.GFX_CM register offsets */
+#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET               0x0000
+#define AM33XX_CM_GFX_L3_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
+#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET                0x0004
+#define AM33XX_CM_GFX_GFX_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
+#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET             0x0008
+#define AM33XX_CM_GFX_BITBLT_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
+#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET      0x000c
+#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1             AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
+#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET             0x0010
+#define AM33XX_CM_GFX_MMUCFG_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
+#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET            0x0014
+#define AM33XX_CM_GFX_MMUDATA_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
+
+/* CM.CEFUSE_CM register offsets */
+#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET               0x0000
+#define AM33XX_CM_CEFUSE_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
+#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET          0x0020
+#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL                 AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
+
+
+extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
+
+#ifdef CONFIG_SOC_AM33XX
+extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs);
+extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs);
+extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs);
+extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs);
+#else
+static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs)
+{
+        return 0;
+}
+static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs)
+{
+}
+static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs)
+{
+}
+static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs)
+{
+        return 0;
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index 1a39945d9ff..1894015ff04 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -235,20 +235,6 @@ void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
 }
 
 /**
- * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle
- * @part: PRCM partition ID that the clockdomain registers exist in
- * @inst: CM instance register offset (*_INST macro)
- * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
- *
- * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle
- * No return value.
- */
-void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
-{
-        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
-}
-
-/**
  * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
  * @part: PRCM partition ID that the clockdomain registers exist in
  * @inst: CM instance register offset (*_INST macro)
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index a018a732787..d69fdefef98 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -16,38 +16,13 @@ extern void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs);
 extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
 extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
 extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
-
 extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
-
-# ifdef CONFIG_ARCH_OMAP4
 extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
                                          u16 clkctrl_offs);
-
 extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
                                        u16 clkctrl_offs);
 extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
                                         u16 clkctrl_offs);
-
-# else
-
-static inline int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
-                                        u16 clkctrl_offs)
-{
-        return 0;
-}
-
-static inline void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
-                                s16 cdoffs, u16 clkctrl_offs)
-{
-}
-
-static inline void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
-                                 u16 clkctrl_offs)
-{
-}
-
-# endif
-
 /*
  * In an ideal world, we would not export these low-level functions,
  * but this will probably take some time to fix properly
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 1706ebcec08..c1875862679 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -63,28 +63,30 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
         struct spi_board_info *spi_bi = &ads7846_spi_board_info;
         int err;
 
-        if (board_pdata && board_pdata->get_pendown_state) {
-                err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
-                if (err) {
-                        pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
-                        return;
-                }
-                gpio_export(gpio_pendown, 0);
-
-                if (gpio_debounce)
-                        gpio_set_debounce(gpio_pendown, gpio_debounce);
+        err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
+        if (err) {
+                pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
+                return;
         }
 
+        if (gpio_debounce)
+                gpio_set_debounce(gpio_pendown, gpio_debounce);
+
         spi_bi->bus_num = bus_num;
         spi_bi->irq     = gpio_to_irq(gpio_pendown);
 
         if (board_pdata) {
                 board_pdata->gpio_pendown = gpio_pendown;
                 spi_bi->platform_data = board_pdata;
+                if (board_pdata->get_pendown_state)
+                        gpio_export(gpio_pendown, 0);
         } else {
                 ads7846_config.gpio_pendown = gpio_pendown;
         }
 
+        if (!board_pdata || (board_pdata && !board_pdata->get_pendown_state))
+                gpio_free(gpio_pendown);
+
         spi_register_board_info(&ads7846_spi_board_info, 1);
 }
 #else
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 8a6953a34fe..069f9725b1c 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -29,8 +29,6 @@
 
 /* Global address base setup code */
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-
 static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
 {
         omap2_set_globals_tap(omap2_globals);
@@ -39,8 +37,6 @@ static void __init __omap2_set_globals(struct omap_globals *omap2_globals)
         omap2_set_globals_prcm(omap2_globals);
 }
 
-#endif
-
 #if defined(CONFIG_SOC_OMAP2420)
 
 static struct omap_globals omap242x_globals = {
@@ -134,7 +130,9 @@ void __init ti81xx_map_io(void)
 {
         omapti81xx_map_common_io();
 }
+#endif
 
+#if defined(CONFIG_SOC_AM33XX)
 #define AM33XX_TAP_BASE         (AM33XX_CTRL_BASE + \
                                 TI81XX_CONTROL_DEVICE_ID - 0x204)
 
@@ -171,9 +169,7 @@ static struct omap_globals omap4_globals = {
 
 void __init omap2_set_globals_443x(void)
 {
-        omap2_set_globals_tap(&omap4_globals);
-        omap2_set_globals_control(&omap4_globals);
-        omap2_set_globals_prcm(&omap4_globals);
+        __omap2_set_globals(&omap4_globals);
 }
 
 void __init omap4_map_io(void)
@@ -182,3 +178,27 @@ void __init omap4_map_io(void)
 }
 #endif
 
+#if defined(CONFIG_SOC_OMAP5)
+static struct omap_globals omap5_globals = {
+        .class  = OMAP54XX_CLASS,
+        .tap    = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
+        .ctrl   = OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
+        .ctrl_pad       = OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE),
+        .prm    = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE),
+        .cm     = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
+        .cm2    = OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE),
+        .prcm_mpu = OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE),
+};
+
+void __init omap2_set_globals_5xxx(void)
+{
+        omap2_set_globals_tap(&omap5_globals);
+        omap2_set_globals_control(&omap5_globals);
+        omap2_set_globals_prcm(&omap5_globals);
+}
+
+void __init omap5_map_io(void)
+{
+        omap5_map_common_io();
+}
+#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index be9dfd1abe6..1f65b1871c2 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -115,12 +115,22 @@ static inline int omap_mux_late_init(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAP5
+extern void omap5_map_common_io(void);
+#else
+static inline void omap5_map_common_io(void)
+{
+}
+#endif
+
 extern void omap2_init_common_infrastructure(void);
 
 extern struct sys_timer omap2_timer;
 extern struct sys_timer omap3_timer;
 extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap3_am33xx_timer;
 extern struct sys_timer omap4_timer;
+extern struct sys_timer omap5_timer;
 
 void omap2420_init_early(void);
 void omap2430_init_early(void);
@@ -128,9 +138,12 @@ void omap3430_init_early(void);
 void omap35xx_init_early(void);
 void omap3630_init_early(void);
 void omap3_init_early(void);    /* Do not use this one */
+void am33xx_init_early(void);
 void am35xx_init_early(void);
 void ti81xx_init_early(void);
+void am33xx_init_early(void);
 void omap4430_init_early(void);
+void omap5_init_early(void);
 void omap3_init_late(void);     /* Do not use this one */
 void omap4430_init_late(void);
 void omap2420_init_late(void);
@@ -166,12 +179,18 @@ void omap2_set_globals_242x(void);
 void omap2_set_globals_243x(void);
 void omap2_set_globals_3xxx(void);
 void omap2_set_globals_443x(void);
+void omap2_set_globals_5xxx(void);
 void omap2_set_globals_ti81xx(void);
 void omap2_set_globals_am33xx(void);
 
 /* These get called from omap2_set_globals_xxxx(), do not call these */
 void omap2_set_globals_tap(struct omap_globals *);
+#if defined(CONFIG_SOC_HAS_OMAP2_SDRC)
 void omap2_set_globals_sdrc(struct omap_globals *);
+#else
+static inline void omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
+{ }
+#endif
 void omap2_set_globals_control(struct omap_globals *);
 void omap2_set_globals_prcm(struct omap_globals *);
 
@@ -180,6 +199,7 @@ void omap243x_map_io(void);
 void omap3_map_io(void);
 void am33xx_map_io(void);
 void omap4_map_io(void);
+void omap5_map_io(void);
 void ti81xx_map_io(void);
 void omap_barriers_init(void);
 
@@ -219,6 +239,8 @@ void omap3_intc_prepare_idle(void);
 void omap3_intc_resume_idle(void);
 void omap2_intc_handle_irq(struct pt_regs *regs);
 void omap3_intc_handle_irq(struct pt_regs *regs);
+void omap_intc_of_init(void);
+void omap_gic_of_init(void);
 
 #ifdef CONFIG_CACHE_L2X0
 extern void __iomem *omap4_get_l2cache_base(void);
@@ -226,10 +248,10 @@ extern void __iomem *omap4_get_l2cache_base(void);
 
 struct device_node;
 #ifdef CONFIG_OF
-int __init omap_intc_of_init(struct device_node *node,
+int __init intc_of_init(struct device_node *node,
                              struct device_node *parent);
 #else
-int __init omap_intc_of_init(struct device_node *node,
+int __init intc_of_init(struct device_node *node,
                              struct device_node *parent)
 {
         return 0;
@@ -256,6 +278,7 @@ extern void omap_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
 extern void omap_auxcoreboot_addr(u32 cpu_addr);
 extern u32 omap_read_auxcoreboot0(void);
+extern void omap5_secondary_startup(void);
 #endif
 
 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 08e674bb041..3223b81e753 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -241,6 +241,49 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
 
 #endif
 
+/**
+ * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
+ * @bootaddr: physical address of the boot loader
+ *
+ * Set boot address for the boot loader of a supported processor
+ * when a power ON sequence occurs.
+ */
+void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
+{
+        u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
+                     cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
+                     cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
+                     0;
+
+        if (!offset) {
+                pr_err("%s: unsupported omap type\n", __func__);
+                return;
+        }
+
+        omap_ctrl_writel(bootaddr, offset);
+}
+
+/**
+ * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
+ * @bootmode: 8-bit value to pass to some boot code
+ *
+ * Sets boot mode for the boot loader of a supported processor
+ * when a power ON sequence occurs.
+ */
+void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
+{
+        u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
+                     cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
+                     0;
+
+        if (!offset) {
+                pr_err("%s: unsupported omap type\n", __func__);
+                return;
+        }
+
+        omap_ctrl_writel(bootmode, offset);
+}
+
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 /*
  * Clears the scratchpad contents in case of cold boot-
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a406fd045ce..b8cdc8531b6 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -21,6 +21,8 @@
 #include <mach/ctrl_module_pad_core_44xx.h>
 #include <mach/ctrl_module_pad_wkup_44xx.h>
 
+#include <plat/am33xx.h>
+
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
                 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -28,6 +30,8 @@
                 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                      \
                 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg)                                        \
+                AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #else
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
                 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -35,6 +39,8 @@
                 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                      \
                 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg)                                        \
+                AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -182,6 +188,7 @@
 #define OMAP3630_CONTROL_FUSE_OPP120_VDD1       (OMAP2_CONTROL_GENERAL + 0x0120)
 #define OMAP3630_CONTROL_FUSE_OPP50_VDD2        (OMAP2_CONTROL_GENERAL + 0x0128)
 #define OMAP3630_CONTROL_FUSE_OPP100_VDD2       (OMAP2_CONTROL_GENERAL + 0x012C)
+#define OMAP3630_CONTROL_CAMERA_PHY_CTRL        (OMAP2_CONTROL_GENERAL + 0x02f0)
 
 /* OMAP44xx control efuse offsets */
 #define OMAP44XX_CONTROL_FUSE_IVA_OPP50         0x22C
@@ -246,6 +253,10 @@
 /* TI81XX CONTROL_DEVCONF register offsets */
 #define TI81XX_CONTROL_DEVICE_ID        (TI81XX_CONTROL_DEVCONF + 0x000)
 
+/* OMAP54XX CONTROL STATUS register */
+#define OMAP5XXX_CONTROL_STATUS                0x134
+#define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
+
 /*
  * REVISIT: This list of registers is not comprehensive - there are more
  * that should be added.
@@ -312,15 +323,15 @@
                                                 OMAP343X_SCRATCHPAD + reg)
 
 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
-#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
-#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
-#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
-#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
-#define AM35XX_USBOTG_FCLK_SHIFT        8
-#define AM35XX_CPGMAC_FCLK_SHIFT        9
-#define AM35XX_VPFE_FCLK_SHIFT          10
-
-/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
+#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
+#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
+#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
+#define AM35XX_USBOTG_FCLK_SHIFT        8
+#define AM35XX_CPGMAC_FCLK_SHIFT        9
+#define AM35XX_VPFE_FCLK_SHIFT          10
+
+/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
 #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
 #define AM35XX_CPGMAC_C0_RX_PULSE_CLR   BIT(1)
 #define AM35XX_CPGMAC_C0_RX_THRESH_CLR  BIT(2)
@@ -330,21 +341,22 @@
 #define AM35XX_VPFE_CCDC_VD1_INT_CLR    BIT(6)
 #define AM35XX_VPFE_CCDC_VD2_INT_CLR    BIT(7)
 
-/*AM35XX CONTROL_IP_SW_RESET bits*/
+/* AM35XX CONTROL_IP_SW_RESET bits */
 #define AM35XX_USBOTGSS_SW_RST          BIT(0)
 #define AM35XX_CPGMACSS_SW_RST          BIT(1)
 #define AM35XX_VPFE_VBUSP_SW_RST        BIT(2)
 #define AM35XX_HECC_SW_RST              BIT(3)
 #define AM35XX_VPFE_PCLK_SW_RST         BIT(4)
 
-/*
- * CONTROL AM33XX STATUS register
- */
+/* AM33XX CONTROL_STATUS register */
 #define AM33XX_CONTROL_STATUS           0x040
+#define AM33XX_CONTROL_SEC_CLK_CTRL     0x1bc
 
-/*
- * CONTROL OMAP STATUS register to identify OMAP3 features
- */
+/* AM33XX CONTROL_STATUS bitfields (partial) */
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT            22
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK             (0x3 << 22)
+
+/* CONTROL OMAP STATUS register to identify OMAP3 features */
 #define OMAP3_CONTROL_OMAP_STATUS       0x044c
 
 #define OMAP3_SGX_SHIFT                 13
@@ -397,6 +409,8 @@ extern u32 omap3_arm_context[128];
 extern void omap3_control_save_context(void);
 extern void omap3_control_restore_context(void);
 extern void omap3_ctrl_write_boot_mode(u8 bootmode);
+extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
+extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
 #else
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 207bc1c7759..f2a49a48ef5 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -36,8 +36,6 @@
 #include "control.h"
 #include "common.h"
 
-#ifdef CONFIG_CPU_IDLE
-
 /* Mach specific information to be recorded in the C-state driver_data */
 struct omap3_idle_statedata {
         u32 mpu_state;
@@ -77,20 +75,6 @@ static struct omap3_idle_statedata omap3_idle_data[] = {
 
 static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
 
-static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
-                                struct clockdomain *clkdm)
-{
-        clkdm_allow_idle(clkdm);
-        return 0;
-}
-
-static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
-                                struct clockdomain *clkdm)
-{
-        clkdm_deny_idle(clkdm);
-        return 0;
-}
-
 static int __omap3_enter_idle(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv,
                                 int index)
@@ -108,8 +92,8 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
 
         /* Deny idle for C1 */
         if (index == 0) {
-                pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
-                pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
+                clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
+                clkdm_deny_idle(core_pd->pwrdm_clkdms[0]);
         }
 
         /*
@@ -131,8 +115,8 @@ static int __omap3_enter_idle(struct cpuidle_device *dev,
 
         /* Re-allow idle for C1 */
         if (index == 0) {
-                pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
-                pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
+                clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
+                clkdm_allow_idle(core_pd->pwrdm_clkdms[0]);
         }
 
 return_sleep_time:
@@ -178,7 +162,7 @@ static int next_valid_state(struct cpuidle_device *dev,
         u32 mpu_deepest_state = PWRDM_POWER_RET;
         u32 core_deepest_state = PWRDM_POWER_RET;
         int idx;
-        int next_index = -1;
+        int next_index = 0; /* C1 is the default value */
 
         if (enable_off_mode) {
                 mpu_deepest_state = PWRDM_POWER_OFF;
@@ -209,12 +193,6 @@ static int next_valid_state(struct cpuidle_device *dev,
                 }
         }
 
-        /*
-         * C1 is always valid.
-         * So, no need to check for 'next_index == -1' outside
-         * this loop.
-         */
-
         return next_index;
 }
 
@@ -228,23 +206,22 @@ static int next_valid_state(struct cpuidle_device *dev,
  * the device to the specified or a safer state.
  */
 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
+                               struct cpuidle_driver *drv,
                                int index)
 {
         int new_state_idx;
-        u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
+        u32 core_next_state, per_next_state = 0, per_saved_state = 0;
         struct omap3_idle_statedata *cx;
         int ret;
 
         /*
-         * Prevent idle completely if CAM is active.
+         * Use only C1 if CAM is active.
          * CAM does not have wakeup capability in OMAP3.
          */
-        cam_state = pwrdm_read_pwrst(cam_pd);
-        if (cam_state == PWRDM_POWER_ON) {
+        if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
                 new_state_idx = drv->safe_state_index;
-                goto select_state;
-        }
+        else
+                new_state_idx = next_valid_state(dev, drv, index);
 
         /*
          * FIXME: we currently manage device-specific idle states
@@ -254,24 +231,28 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
          *        its own code.
          */
 
-        /*
-         * Prevent PER off if CORE is not in retention or off as this
-         * would disable PER wakeups completely.
-         */
-        cx = &omap3_idle_data[index];
+        /* Program PER state */
+        cx = &omap3_idle_data[new_state_idx];
         core_next_state = cx->core_state;
         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
-        if ((per_next_state == PWRDM_POWER_OFF) &&
-            (core_next_state > PWRDM_POWER_RET))
-                per_next_state = PWRDM_POWER_RET;
+        if (new_state_idx == 0) {
+                /* In C1 do not allow PER state lower than CORE state */
+                if (per_next_state < core_next_state)
+                        per_next_state = core_next_state;
+        } else {
+                /*
+                 * Prevent PER OFF if CORE is not in RETention or OFF as this
+                 * would disable PER wakeups completely.
+                 */
+                if ((per_next_state == PWRDM_POWER_OFF) &&
+                    (core_next_state > PWRDM_POWER_RET))
+                        per_next_state = PWRDM_POWER_RET;
+        }
 
         /* Are we changing PER target state? */
         if (per_next_state != per_saved_state)
                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 
-        new_state_idx = next_valid_state(dev, drv, index);
-
-select_state:
         ret = omap3_enter_idle(dev, drv, new_state_idx);
 
         /* Restore original PER state if it was modified */
@@ -288,7 +269,7 @@ struct cpuidle_driver omap3_idle_driver = {
         .owner =        THIS_MODULE,
         .states = {
                 {
-                        .enter            = omap3_enter_idle,
+                        .enter            = omap3_enter_idle_bm,
                         .exit_latency     = 2 + 2,
                         .target_residency = 5,
                         .flags            = CPUIDLE_FLAG_TIME_VALID,
@@ -379,9 +360,3 @@ int __init omap3_idle_init(void)
 
         return 0;
 }
-#else
-int __init omap3_idle_init(void)
-{
-        return 0;
-}
-#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index be1617ca84b..288bee6cbb7 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -21,8 +21,7 @@
 #include "common.h"
 #include "pm.h"
 #include "prm.h"
-
-#ifdef CONFIG_CPU_IDLE
+#include "clockdomain.h"
 
 /* Machine specific information */
 struct omap4_idle_statedata {
@@ -49,10 +48,14 @@ static struct omap4_idle_statedata omap4_idle_data[] = {
         },
 };
 
-static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
+static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
+static struct clockdomain *cpu_clkdm[NR_CPUS];
+
+static atomic_t abort_barrier;
+static bool cpu_done[NR_CPUS];
 
 /**
- * omap4_enter_idle - Programs OMAP4 to enter the specified state
+ * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
  * @dev: cpuidle device
  * @drv: cpuidle driver
  * @index: the index of state to be entered
@@ -61,60 +64,84 @@ static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
  * specified low power state selected by the governor.
  * Returns the amount of time spent in the low power state.
  */
-static int omap4_enter_idle(struct cpuidle_device *dev,
+static int omap4_enter_idle_simple(struct cpuidle_device *dev,
+                        struct cpuidle_driver *drv,
+                        int index)
+{
+        local_fiq_disable();
+        omap_do_wfi();
+        local_fiq_enable();
+
+        return index;
+}
+
+static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
                         struct cpuidle_driver *drv,
                         int index)
 {
         struct omap4_idle_statedata *cx = &omap4_idle_data[index];
-        u32 cpu1_state;
         int cpu_id = smp_processor_id();
 
         local_fiq_disable();
 
         /*
-         * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
+         * CPU0 has to wait and stay ON until CPU1 is OFF state.
          * This is necessary to honour hardware recommondation
          * of triggeing all the possible low power modes once CPU1 is
          * out of coherency and in OFF mode.
-         * Update dev->last_state so that governor stats reflects right
-         * data.
          */
-        cpu1_state = pwrdm_read_pwrst(cpu1_pd);
-        if (cpu1_state != PWRDM_POWER_OFF) {
-                index = drv->safe_state_index;
-                cx = &omap4_idle_data[index];
+        if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
+                while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
+                        cpu_relax();
+
+                        /*
+                         * CPU1 could have already entered & exited idle
+                         * without hitting off because of a wakeup
+                         * or a failed attempt to hit off mode.  Check for
+                         * that here, otherwise we could spin forever
+                         * waiting for CPU1 off.
+                         */
+                        if (cpu_done[1])
+                            goto fail;
+
+                }
         }
 
-        if (index > 0)
-                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
 
         /*
          * Call idle CPU PM enter notifier chain so that
          * VFP and per CPU interrupt context is saved.
          */
-        if (cx->cpu_state == PWRDM_POWER_OFF)
-                cpu_pm_enter();
-
-        pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
-        omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
-
-        /*
-         * Call idle CPU cluster PM enter notifier chain
-         * to save GIC and wakeupgen context.
-         */
-        if ((cx->mpu_state == PWRDM_POWER_RET) &&
-                (cx->mpu_logic_state == PWRDM_POWER_OFF))
-                        cpu_cluster_pm_enter();
+        cpu_pm_enter();
+
+        if (dev->cpu == 0) {
+                pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
+                omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
+
+                /*
+                 * Call idle CPU cluster PM enter notifier chain
+                 * to save GIC and wakeupgen context.
+                 */
+                if ((cx->mpu_state == PWRDM_POWER_RET) &&
+                        (cx->mpu_logic_state == PWRDM_POWER_OFF))
+                                cpu_cluster_pm_enter();
+        }
 
         omap4_enter_lowpower(dev->cpu, cx->cpu_state);
+        cpu_done[dev->cpu] = true;
+
+        /* Wakeup CPU1 only if it is not offlined */
+        if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
+                clkdm_wakeup(cpu_clkdm[1]);
+                clkdm_allow_idle(cpu_clkdm[1]);
+        }
 
         /*
          * Call idle CPU PM exit notifier chain to restore
-         * VFP and per CPU IRQ context. Only CPU0 state is
-         * considered since CPU1 is managed by CPU hotplug.
+         * VFP and per CPU IRQ context.
          */
-        if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
-                cpu_pm_exit();
+        cpu_pm_exit();
 
         /*
          * Call idle CPU cluster PM exit notifier chain
@@ -123,8 +150,11 @@ static int omap4_enter_idle(struct cpuidle_device *dev,
         if (omap4_mpuss_read_prev_context_state())
                 cpu_cluster_pm_exit();
 
-        if (index > 0)
-                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
+
+fail:
+        cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
+        cpu_done[dev->cpu] = false;
 
         local_fiq_enable();
 
@@ -143,7 +173,7 @@ struct cpuidle_driver omap4_idle_driver = {
                         .exit_latency = 2 + 2,
                         .target_residency = 5,
                         .flags = CPUIDLE_FLAG_TIME_VALID,
-                        .enter = omap4_enter_idle,
+                        .enter = omap4_enter_idle_simple,
                         .name = "C1",
                         .desc = "MPUSS ON"
                 },
@@ -151,8 +181,8 @@ struct cpuidle_driver omap4_idle_driver = {
                         /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
                         .exit_latency = 328 + 440,
                         .target_residency = 960,
-                        .flags = CPUIDLE_FLAG_TIME_VALID,
-                        .enter = omap4_enter_idle,
+                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
+                        .enter = omap4_enter_idle_coupled,
                         .name = "C2",
                         .desc = "MPUSS CSWR",
                 },
@@ -160,8 +190,8 @@ struct cpuidle_driver omap4_idle_driver = {
                         /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
                         .exit_latency = 460 + 518,
                         .target_residency = 1100,
-                        .flags = CPUIDLE_FLAG_TIME_VALID,
-                        .enter = omap4_enter_idle,
+                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
+                        .enter = omap4_enter_idle_coupled,
                         .name = "C3",
                         .desc = "MPUSS OSWR",
                 },
@@ -170,6 +200,16 @@ struct cpuidle_driver omap4_idle_driver = {
         .safe_state_index = 0,
 };
 
+/*
+ * For each cpu, setup the broadcast timer because local timers
+ * stops for the states above C1.
+ */
+static void omap_setup_broadcast_timer(void *arg)
+{
+        int cpu = smp_processor_id();
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
+}
+
 /**
  * omap4_idle_init - Init routine for OMAP4 idle
  *
@@ -182,26 +222,32 @@ int __init omap4_idle_init(void)
         unsigned int cpu_id = 0;
 
         mpu_pd = pwrdm_lookup("mpu_pwrdm");
-        cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
-        cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
-        if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
+        cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
+        cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
+        if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
                 return -ENODEV;
 
-        dev = &per_cpu(omap4_idle_dev, cpu_id);
-        dev->cpu = cpu_id;
-
-        cpuidle_register_driver(&omap4_idle_driver);
+        cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
+        cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
+        if (!cpu_clkdm[0] || !cpu_clkdm[1])
+                return -ENODEV;
 
-        if (cpuidle_register_device(dev)) {
-                pr_err("%s: CPUidle register device failed\n", __func__);
-                return -EIO;
+        /* Configure the broadcast timer on each cpu */
+        on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
+
+        for_each_cpu(cpu_id, cpu_online_mask) {
+                dev = &per_cpu(omap4_idle_dev, cpu_id);
+                dev->cpu = cpu_id;
+#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
+                dev->coupled_cpus = *cpu_online_mask;
+#endif
+                cpuidle_register_driver(&omap4_idle_driver);
+
+                if (cpuidle_register_device(dev)) {
+                        pr_err("%s: CPUidle register failed\n", __func__);
+                        return -EIO;
+                }
         }
 
         return 0;
 }
-#else
-int __init omap4_idle_init(void)
-{
-        return 0;
-}
-#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7b4b9327e54..c00c68961bb 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -27,7 +27,6 @@
 
 #include "iomap.h"
 #include <plat/board.h>
-#include <plat/mmc.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
@@ -84,7 +83,7 @@ static int __init omap4_l3_init(void)
          * To avoid code running on other OMAPs in
          * multi-omap builds
          */
-        if (!(cpu_is_omap44xx()))
+        if (!cpu_is_omap44xx() && !soc_is_omap54xx())
                 return -ENODEV;
 
         for (i = 0; i < L3_MODULES; i++) {
@@ -603,112 +602,6 @@ static inline void omap_init_aes(void) { }
 
 /*-------------------------------------------------------------------------*/
 
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
-
-static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
-                                                        *mmc_controller)
-{
-        if ((mmc_controller->slots[0].switch_pin > 0) && \
-                (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
-                omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
-                                        OMAP_PIN_INPUT_PULLUP);
-        if ((mmc_controller->slots[0].gpio_wp > 0) && \
-                (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
-                omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
-                                        OMAP_PIN_INPUT_PULLUP);
-
-        omap_mux_init_signal("sdmmc_cmd", 0);
-        omap_mux_init_signal("sdmmc_clki", 0);
-        omap_mux_init_signal("sdmmc_clko", 0);
-        omap_mux_init_signal("sdmmc_dat0", 0);
-        omap_mux_init_signal("sdmmc_dat_dir0", 0);
-        omap_mux_init_signal("sdmmc_cmd_dir", 0);
-        if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
-                omap_mux_init_signal("sdmmc_dat1", 0);
-                omap_mux_init_signal("sdmmc_dat2", 0);
-                omap_mux_init_signal("sdmmc_dat3", 0);
-                omap_mux_init_signal("sdmmc_dat_dir1", 0);
-                omap_mux_init_signal("sdmmc_dat_dir2", 0);
-                omap_mux_init_signal("sdmmc_dat_dir3", 0);
-        }
-
-        /*
-         * Use internal loop-back in MMC/SDIO Module Input Clock
-         * selection
-         */
-        if (mmc_controller->slots[0].internal_clock) {
-                u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-                v |= (1 << 24);
-                omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-        }
-}
-
-void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
-{
-        struct platform_device *pdev;
-        struct omap_hwmod *oh;
-        int id = 0;
-        char *oh_name = "msdi1";
-        char *dev_name = "mmci-omap";
-
-        if (!mmc_data[0]) {
-                pr_err("%s fails: Incomplete platform data\n", __func__);
-                return;
-        }
-
-        omap242x_mmc_mux(mmc_data[0]);
-
-        oh = omap_hwmod_lookup(oh_name);
-        if (!oh) {
-                pr_err("Could not look up %s\n", oh_name);
-                return;
-        }
-        pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
-                                 sizeof(struct omap_mmc_platform_data), NULL, 0, 0);
-        if (IS_ERR(pdev))
-                WARN(1, "Can'd build omap_device for %s:%s.\n",
-                                        dev_name, oh->name);
-}
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
-#define OMAP_HDQ_BASE   0x480B2000
-static struct resource omap_hdq_resources[] = {
-        {
-                .start          = OMAP_HDQ_BASE,
-                .end            = OMAP_HDQ_BASE + 0x1C,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = INT_24XX_HDQ_IRQ,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device omap_hdq_dev = {
-        .name = "omap_hdq",
-        .id = 0,
-        .dev = {
-                .platform_data = NULL,
-        },
-        .num_resources  = ARRAY_SIZE(omap_hdq_resources),
-        .resource       = omap_hdq_resources,
-};
-static inline void omap_hdq_init(void)
-{
-        if (cpu_is_omap2420())
-                return;
-
-        platform_device_register(&omap_hdq_dev);
-}
-#else
-static inline void omap_hdq_init(void) {}
-#endif
-
-/*---------------------------------------------------------------------------*/
-
 #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
         defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
 #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
@@ -753,7 +646,6 @@ static int __init omap2_init_devices(void)
                 omap_init_mcspi();
         }
         omap_init_pmu();
-        omap_hdq_init();
         omap_init_sti();
         omap_init_sham();
         omap_init_aes();
@@ -772,7 +664,7 @@ static int __init omap_init_wdt(void)
         char *oh_name = "wd_timer2";
         char *dev_name = "omap_wdt";
 
-        if (!cpu_class_is_omap2())
+        if (!cpu_class_is_omap2() || of_have_populated_dt())
                 return 0;
 
         oh = omap_hwmod_lookup(oh_name);
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 5fb47a14f4b..af1ed7d24a1 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -37,6 +37,7 @@
 
 #define DISPC_CONTROL           0x0040
 #define DISPC_CONTROL2          0x0238
+#define DISPC_CONTROL3          0x0848
 #define DISPC_IRQSTATUS         0x0018
 
 #define DSS_SYSCONFIG           0x10
@@ -52,6 +53,7 @@
 #define EVSYNC_EVEN_IRQ_SHIFT   2
 #define EVSYNC_ODD_IRQ_SHIFT    3
 #define FRAMEDONE2_IRQ_SHIFT    22
+#define FRAMEDONE3_IRQ_SHIFT    30
 #define FRAMEDONETV_IRQ_SHIFT   24
 
 /*
@@ -376,7 +378,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
 static void dispc_disable_outputs(void)
 {
         u32 v, irq_mask = 0;
-        bool lcd_en, digit_en, lcd2_en = false;
+        bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
         int i;
         struct omap_dss_dispc_dev_attr *da;
         struct omap_hwmod *oh;
@@ -405,7 +407,13 @@ static void dispc_disable_outputs(void)
                 lcd2_en = v & LCD_EN_MASK;
         }
 
-        if (!(lcd_en | digit_en | lcd2_en))
+        /* store value of LCDENABLE for LCD3 */
+        if (da->manager_count > 3) {
+                v = omap_hwmod_read(oh, DISPC_CONTROL3);
+                lcd3_en = v & LCD_EN_MASK;
+        }
+
+        if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
                 return; /* no managers currently enabled */
 
         /*
@@ -426,10 +434,12 @@ static void dispc_disable_outputs(void)
 
         if (lcd2_en)
                 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
+        if (lcd3_en)
+                irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
 
         /*
          * clear any previous FRAMEDONE, FRAMEDONETV,
-         * EVSYNC_EVEN/ODD or FRAMEDONE2 interrupts
+         * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
          */
         omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
 
@@ -445,12 +455,19 @@ static void dispc_disable_outputs(void)
                 omap_hwmod_write(v, oh, DISPC_CONTROL2);
         }
 
+        /* disable LCD3 manager */
+        if (da->manager_count > 3) {
+                v = omap_hwmod_read(oh, DISPC_CONTROL3);
+                v &= ~LCD_EN_MASK;
+                omap_hwmod_write(v, oh, DISPC_CONTROL3);
+        }
+
         i = 0;
         while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
                irq_mask) {
                 i++;
                 if (i > FRAMEDONE_IRQ_TIMEOUT) {
-                        pr_err("didn't get FRAMEDONE1/2 or TV interrupt\n");
+                        pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
                         break;
                 }
                 mdelay(1);
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index f0f10beeffe..b9c8d2f6a81 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -135,11 +135,20 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
  */
 static int _omap3_noncore_dpll_lock(struct clk *clk)
 {
+        const struct dpll_data *dd;
         u8 ai;
-        int r;
+        u8 state = 1;
+        int r = 0;
 
         pr_debug("clock: locking DPLL %s\n", clk->name);
 
+        dd = clk->dpll_data;
+        state <<= __ffs(dd->idlest_mask);
+
+        /* Check if already locked */
+        if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state)
+                goto done;
+
         ai = omap3_dpll_autoidle_read(clk);
 
         if (ai)
@@ -152,6 +161,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
         if (ai)
                 omap3_dpll_allow_idle(clk);
 
+done:
         return r;
 }
 
@@ -628,3 +638,17 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
                 rate = clk->parent->rate * 2;
         return rate;
 }
+
+/* OMAP3/4 non-CORE DPLL clkops */
+
+const struct clkops clkops_omap3_noncore_dpll_ops = {
+        .enable         = omap3_noncore_dpll_enable,
+        .disable        = omap3_noncore_dpll_disable,
+        .allow_idle     = omap3_dpll_allow_idle,
+        .deny_idle      = omap3_dpll_deny_idle,
+};
+
+const struct clkops clkops_omap3_core_dpll_ops = {
+        .allow_idle     = omap3_dpll_allow_idle,
+        .deny_idle      = omap3_dpll_deny_idle,
+};
diff --git a/arch/arm/mach-omap2/drm.c b/arch/arm/mach-omap2/drm.c
new file mode 100644
index 00000000000..72e0f01b715
--- /dev/null
+++ b/arch/arm/mach-omap2/drm.c
@@ -0,0 +1,61 @@
+/*
+ * DRM/KMS device registration for TI OMAP platforms
+ *
+ * Copyright (C) 2012 Texas Instruments
+ * Author: Rob Clark <rob.clark@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <plat/omap_device.h>
+#include <plat/omap_hwmod.h>
+
+#if defined(CONFIG_DRM_OMAP) || (CONFIG_DRM_OMAP_MODULE)
+
+static struct platform_device omap_drm_device = {
+        .dev = {
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .name = "omapdrm",
+        .id = 0,
+};
+
+static int __init omap_init_drm(void)
+{
+        struct omap_hwmod *oh = NULL;
+        struct platform_device *pdev;
+
+        /* lookup and populate the DMM information, if present - OMAP4+ */
+        oh = omap_hwmod_lookup("dmm");
+
+        if (oh) {
+                pdev = omap_device_build(oh->name, -1, oh, NULL, 0, NULL, 0,
+                                        false);
+                WARN(IS_ERR(pdev), "Could not build omap_device for %s\n",
+                        oh->name);
+        }
+
+        return platform_device_register(&omap_drm_device);
+
+}
+
+arch_initcall(omap_init_drm);
+
+#endif
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 88ffa1e645c..a636ebc16b3 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -23,6 +23,7 @@
 
 #include <asm/memblock.h>
 
+#include "control.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
 #ifdef CONFIG_BRIDGE_DVFS
@@ -46,6 +47,9 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
         .dsp_cm_read = omap2_cm_read_mod_reg,
         .dsp_cm_write = omap2_cm_write_mod_reg,
         .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits,
+
+        .set_bootaddr = omap_ctrl_write_dsp_boot_addr,
+        .set_bootmode = omap_ctrl_write_dsp_boot_mode,
 };
 
 static phys_addr_t omap_dsp_phys_mempool_base;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 2286410671e..b2b5759ab0f 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -727,7 +727,8 @@ static int __init gpmc_init(void)
                 ck = "gpmc_fck";
                 l = OMAP34XX_GPMC_BASE;
                 gpmc_irq = INT_34XX_GPMC_IRQ;
-        } else if (cpu_is_omap44xx()) {
+        } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+                /* Base address and irq number are same for OMAP4/5 */
                 ck = "gpmc_ck";
                 l = OMAP44XX_GPMC_BASE;
                 gpmc_irq = OMAP44XX_IRQ_GPMC;
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index 297ebe03f09..cdd6dda0382 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -22,7 +22,13 @@
  * 02110-1301 USA
  */
 
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+
 #include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
 #include <plat/hdq1w.h>
 
 #include "common.h"
@@ -70,3 +76,23 @@ int omap_hdq1w_reset(struct omap_hwmod *oh)
 
         return 0;
 }
+
+static int __init omap_init_hdq(void)
+{
+        int id = -1;
+        struct platform_device *pdev;
+        struct omap_hwmod *oh;
+        char *oh_name = "hdq1w";
+        char *devname = "omap_hdq";
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh)
+                return 0;
+
+        pdev = omap_device_build(devname, id, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for %s:%s.\n",
+             devname, oh->name);
+
+        return 0;
+}
+arch_initcall(omap_init_hdq);
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index be697d4e084..a9675d8d182 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -315,7 +315,6 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
         mmc->slots[0].caps = c->caps;
         mmc->slots[0].pm_caps = c->pm_caps;
         mmc->slots[0].internal_clock = !c->ext_clock;
-        mmc->dma_mask = 0xffffffff;
         mmc->max_freq = c->max_freq;
         if (cpu_is_omap44xx())
                 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 00486a8564f..40373db649a 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -44,12 +44,17 @@ int omap_type(void)
 
         if (cpu_is_omap24xx()) {
                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
-        } else if (cpu_is_am33xx()) {
+        } else if (soc_is_am33xx()) {
                 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
         } else if (cpu_is_omap34xx()) {
                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
         } else if (cpu_is_omap44xx()) {
                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
+        } else if (soc_is_omap54xx()) {
+                val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
+                val &= OMAP5_DEVICETYPE_MASK;
+                val >>= 6;
+                goto out;
         } else {
                 pr_err("Cannot detect omap type!\n");
                 goto out;
@@ -100,7 +105,7 @@ static u16 tap_prod_id;
 
 void omap_get_die_id(struct omap_die_id *odi)
 {
-        if (cpu_is_omap44xx()) {
+        if (cpu_is_omap44xx() || soc_is_omap54xx()) {
                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
@@ -189,7 +194,7 @@ static void __init omap3_cpuinfo(void)
                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
         } else if (cpu_is_ti816x()) {
                 cpu_name = "TI816X";
-        } else if (cpu_is_am335x()) {
+        } else if (soc_is_am335x()) {
                 cpu_name =  "AM335X";
         } else if (cpu_is_ti814x()) {
                 cpu_name = "TI814X";
@@ -513,6 +518,41 @@ void __init omap4xxx_check_revision(void)
                 ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 }
 
+void __init omap5xxx_check_revision(void)
+{
+        u32 idcode;
+        u16 hawkeye;
+        u8 rev;
+
+        idcode = read_tap_reg(OMAP_TAP_IDCODE);
+        hawkeye = (idcode >> 12) & 0xffff;
+        rev = (idcode >> 28) & 0xff;
+        switch (hawkeye) {
+        case 0xb942:
+                switch (rev) {
+                case 0:
+                default:
+                        omap_revision = OMAP5430_REV_ES1_0;
+                }
+                break;
+
+        case 0xb998:
+                switch (rev) {
+                case 0:
+                default:
+                        omap_revision = OMAP5432_REV_ES1_0;
+                }
+                break;
+
+        default:
+                /* Unknown default to latest silicon rev as default*/
+                omap_revision = OMAP5430_REV_ES1_0;
+        }
+
+        pr_info("OMAP%04x ES%d.0\n",
+                        omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
+}
+
 /*
  * Set up things for map_io and processor detection later on. Gets called
  * pretty much first thing from board init. For multi-omap, this gets
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h
index f1e13d1ca5e..95594495fcf 100644
--- a/arch/arm/mach-omap2/include/mach/am35xx.h
+++ b/arch/arm/mach-omap2/include/mach/am35xx.h
@@ -36,6 +36,8 @@
 #define AM35XX_EMAC_CNTRL_MOD_OFFSET    (0x0)
 #define AM35XX_EMAC_CNTRL_RAM_OFFSET    (0x20000)
 #define AM35XX_EMAC_MDIO_OFFSET         (0x30000)
+#define AM35XX_IPSS_MDIO_BASE           (AM35XX_IPSS_EMAC_BASE + \
+                                                AM35XX_EMAC_MDIO_OFFSET)
 #define AM35XX_EMAC_CNTRL_RAM_SIZE      (0x2000)
 #define AM35XX_EMAC_RAM_ADDR            (AM3517_EMAC_BASE + \
                                                 AM3517_EMAC_CNTRL_RAM_OFFSET)
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
index 2f7ac70a20d..01970824e0e 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -42,6 +42,7 @@
 #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1              0x0268
 #define OMAP4_CTRL_MODULE_CORE_STATUS                           0x02c4
 #define OMAP4_CTRL_MODULE_CORE_DEV_CONF                         0x0300
+#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR                     0x0304
 #define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL          0x0314
 #define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL          0x0318
 #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL         0x0320
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index cdfc2a1f0e7..93d10de7129 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -60,18 +60,20 @@ omap_uart_lsr:	.word	0
                 beq     23f                     @ configure OMAP2UART3
                 cmp     \rp, #OMAP3UART3        @ only on 34xx
                 beq     33f                     @ configure OMAP3UART3
-                cmp     \rp, #OMAP4UART3        @ only on 44xx
-                beq     43f                     @ configure OMAP4UART3
+                cmp     \rp, #OMAP4UART3        @ only on 44xx/54xx
+                beq     43f                     @ configure OMAP4/5UART3
                 cmp     \rp, #OMAP3UART4        @ only on 36xx
                 beq     34f                     @ configure OMAP3UART4
-                cmp     \rp, #OMAP4UART4        @ only on 44xx
-                beq     44f                     @ configure OMAP4UART4
+                cmp     \rp, #OMAP4UART4        @ only on 44xx/54xx
+                beq     44f                     @ configure OMAP4/5UART4
                 cmp     \rp, #TI81XXUART1       @ ti81Xx UART offsets different
                 beq     81f                     @ configure UART1
                 cmp     \rp, #TI81XXUART2       @ ti81Xx UART offsets different
                 beq     82f                     @ configure UART2
                 cmp     \rp, #TI81XXUART3       @ ti81Xx UART offsets different
                 beq     83f                     @ configure UART3
+                cmp     \rp, #AM33XXUART1       @ AM33XX UART offsets different
+                beq     84f                     @ configure UART1
                 cmp     \rp, #ZOOM_UART         @ only on zoom2/3
                 beq     95f                     @ configure ZOOM_UART
 
@@ -100,7 +102,9 @@ omap_uart_lsr:	.word	0
                 b       98f
 83:             mov     \rp, #UART_OFFSET(TI81XX_UART3_BASE)
                 b       98f
-
+84:             ldr     \rp, =AM33XX_UART1_BASE
+                and     \rp, \rp, #0x00ffffff
+                b       97f
 95:             ldr     \rp, =ZOOM_UART_BASE
                 str     \rp, [\tmp, #0]         @ omap_uart_phys
                 ldr     \rp, =ZOOM_UART_VIRT
@@ -109,6 +113,17 @@ omap_uart_lsr:	.word	0
                 str     \rp, [\tmp, #8]         @ omap_uart_lsr
                 b       10b
 
+                /* AM33XX: Store both phys and virt address for the uart */
+97:             add     \rp, \rp, #0x44000000   @ phys base
+                str     \rp, [\tmp, #0]         @ omap_uart_phys
+                sub     \rp, \rp, #0x44000000   @ phys base
+                add     \rp, \rp, #0xf9000000   @ virt base
+                str     \rp, [\tmp, #4]         @ omap_uart_virt
+                mov     \rp, #(UART_LSR << OMAP_PORT_SHIFT)
+                str     \rp, [\tmp, #8]         @ omap_uart_lsr
+
+                b       10b
+
                 /* Store both phys and virt address for the uart */
 98:             add     \rp, \rp, #0x48000000   @ phys base
                 str     \rp, [\tmp, #0]         @ omap_uart_phys
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
index 548de90b58c..b0fd16f5c39 100644
--- a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -11,15 +11,20 @@
 #ifndef OMAP_ARCH_WAKEUPGEN_H
 #define OMAP_ARCH_WAKEUPGEN_H
 
+/* OMAP4 and OMAP5 has same base address */
+#define OMAP_WKUPGEN_BASE                       0x48281000
+
 #define OMAP_WKG_CONTROL_0                      0x00
 #define OMAP_WKG_ENB_A_0                        0x10
 #define OMAP_WKG_ENB_B_0                        0x14
 #define OMAP_WKG_ENB_C_0                        0x18
 #define OMAP_WKG_ENB_D_0                        0x1c
+#define OMAP_WKG_ENB_E_0                        0x20
 #define OMAP_WKG_ENB_A_1                        0x410
 #define OMAP_WKG_ENB_B_1                        0x414
 #define OMAP_WKG_ENB_C_1                        0x418
 #define OMAP_WKG_ENB_D_1                        0x41c
+#define OMAP_WKG_ENB_E_1                        0x420
 #define OMAP_AUX_CORE_BOOT_0                    0x800
 #define OMAP_AUX_CORE_BOOT_1                    0x804
 #define OMAP_PTMSYNCREQ_MASK                    0xc00
@@ -28,4 +33,6 @@
 #define OMAP_TIMESTAMPCYCLEHI                   0xc0c
 
 extern int __init omap_wakeupgen_init(void);
+extern void __iomem *omap_get_wakeupgen_base(void);
+extern int omap_secure_apis_support(void);
 #endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 8d014ba04ab..4d2d981ff5c 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -38,6 +38,7 @@
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include "common.h"
+#include "clock.h"
 #include "clock2xxx.h"
 #include "clock3xxx.h"
 #include "clock44xx.h"
@@ -233,6 +234,35 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
 };
 #endif
 
+#ifdef  CONFIG_SOC_OMAP5
+static struct map_desc omap54xx_io_desc[] __initdata = {
+        {
+                .virtual        = L3_54XX_VIRT,
+                .pfn            = __phys_to_pfn(L3_54XX_PHYS),
+                .length         = L3_54XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = L4_54XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_54XX_PHYS),
+                .length         = L4_54XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = L4_WK_54XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_WK_54XX_PHYS),
+                .length         = L4_WK_54XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+        {
+                .virtual        = L4_PER_54XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_PER_54XX_PHYS),
+                .length         = L4_PER_54XX_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+#endif
+
 #ifdef CONFIG_SOC_OMAP2420
 void __init omap242x_map_common_io(void)
 {
@@ -278,6 +308,12 @@ void __init omap44xx_map_common_io(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAP5
+void __init omap5_map_common_io(void)
+{
+        iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
+}
+#endif
 /*
  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
  *
@@ -477,6 +513,20 @@ void __init ti81xx_init_late(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_AM33XX
+void __init am33xx_init_early(void)
+{
+        omap2_set_globals_am33xx();
+        omap3xxx_check_revision();
+        ti81xx_check_features();
+        omap_common_init_early();
+        am33xx_voltagedomains_init();
+        am33xx_powerdomains_init();
+        am33xx_clockdomains_init();
+        am33xx_clk_init();
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap4430_init_early(void)
 {
@@ -500,6 +550,15 @@ void __init omap4430_init_late(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_OMAP5
+void __init omap5_init_early(void)
+{
+        omap2_set_globals_5xxx();
+        omap5xxx_check_revision();
+        omap_common_init_early();
+}
+#endif
+
 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                                       struct omap_sdrc_params *sdrc_cs1)
 {
diff --git a/arch/arm/mach-omap2/iomap.h b/arch/arm/mach-omap2/iomap.h
index 80b88921fab..cce2b65039f 100644
--- a/arch/arm/mach-omap2/iomap.h
+++ b/arch/arm/mach-omap2/iomap.h
@@ -1,6 +1,14 @@
 /*
  * IO mappings for OMAP2+
  *
+ * IO definitions for TI OMAP processors and boards
+ *
+ * Copied from arch/arm/mach-sa1100/include/mach/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
  * Free Software Foundation; either version 2 of the License, or (at your
@@ -166,4 +174,23 @@
                                                 /* 0x49000000 --> 0xfb000000 */
 #define L4_ABE_44XX_VIRT        (L4_ABE_44XX_PHYS + OMAP2_L4_IO_OFFSET)
 #define L4_ABE_44XX_SIZE        SZ_1M
+/*
+ * ----------------------------------------------------------------------------
+ * Omap5 specific IO mapping
+ * ----------------------------------------------------------------------------
+ */
+#define L3_54XX_PHYS            L3_54XX_BASE    /* 0x44000000 --> 0xf8000000 */
+#define L3_54XX_VIRT            (L3_54XX_PHYS + OMAP4_L3_IO_OFFSET)
+#define L3_54XX_SIZE            SZ_1M
+
+#define L4_54XX_PHYS            L4_54XX_BASE    /* 0x4a000000 --> 0xfc000000 */
+#define L4_54XX_VIRT            (L4_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_54XX_SIZE            SZ_4M
+
+#define L4_WK_54XX_PHYS         L4_WK_54XX_BASE /* 0x4ae00000 --> 0xfce00000 */
+#define L4_WK_54XX_VIRT         (L4_WK_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_WK_54XX_SIZE         SZ_2M
 
+#define L4_PER_54XX_PHYS        L4_PER_54XX_BASE /* 0x48000000 --> 0xfa000000 */
+#define L4_PER_54XX_VIRT        (L4_PER_54XX_PHYS + OMAP2_L4_IO_OFFSET)
+#define L4_PER_54XX_SIZE        SZ_4M
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 6038a8c84b7..bcd83db41bb 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -21,6 +21,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <mach/hardware.h>
 
@@ -258,11 +259,11 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
         omap_intc_handle_irq(base_addr, regs);
 }
 
-int __init omap_intc_of_init(struct device_node *node,
+int __init intc_of_init(struct device_node *node,
                              struct device_node *parent)
 {
         struct resource res;
-        u32 nr_irqs = 96;
+        u32 nr_irq = 96;
 
         if (WARN_ON(!node))
                 return -ENODEV;
@@ -272,15 +273,25 @@ int __init omap_intc_of_init(struct device_node *node,
                 return -EINVAL;
         }
 
-        if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
-                pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
+        if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
+                pr_warn("unable to get intc-size, default to %d\n", nr_irq);
 
-        omap_init_irq(res.start, nr_irqs, of_node_get(node));
+        omap_init_irq(res.start, nr_irq, of_node_get(node));
 
         return 0;
 }
 
-#ifdef CONFIG_ARCH_OMAP3
+static struct of_device_id irq_match[] __initdata = {
+        { .compatible = "ti,omap2-intc", .data = intc_of_init, },
+        { }
+};
+
+void __init omap_intc_of_init(void)
+{
+        of_irq_init(irq_match);
+}
+
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 
 void omap_intc_save_context(void)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 19b8b677486..6875be837d9 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -83,8 +83,6 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
         l = mbox_read_reg(MAILBOX_REVISION);
         pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
 
-        omap2_mbox_enable_irq(mbox, IRQ_RX);
-
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index ef2a6924731..fb5bc6cf377 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -22,11 +22,15 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/err.h>
 
 #include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
 #include <plat/mmc.h>
 
 #include "common.h"
+#include "control.h"
+#include "mux.h"
 
 /*
  * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
@@ -86,3 +90,72 @@ int omap_msdi_reset(struct omap_hwmod *oh)
 
         return 0;
 }
+
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
+
+static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
+                                    *mmc_controller)
+{
+        if ((mmc_controller->slots[0].switch_pin > 0) && \
+                (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
+                omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
+                                        OMAP_PIN_INPUT_PULLUP);
+        if ((mmc_controller->slots[0].gpio_wp > 0) && \
+                (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
+                omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
+                                        OMAP_PIN_INPUT_PULLUP);
+
+        omap_mux_init_signal("sdmmc_cmd", 0);
+        omap_mux_init_signal("sdmmc_clki", 0);
+        omap_mux_init_signal("sdmmc_clko", 0);
+        omap_mux_init_signal("sdmmc_dat0", 0);
+        omap_mux_init_signal("sdmmc_dat_dir0", 0);
+        omap_mux_init_signal("sdmmc_cmd_dir", 0);
+        if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
+                omap_mux_init_signal("sdmmc_dat1", 0);
+                omap_mux_init_signal("sdmmc_dat2", 0);
+                omap_mux_init_signal("sdmmc_dat3", 0);
+                omap_mux_init_signal("sdmmc_dat_dir1", 0);
+                omap_mux_init_signal("sdmmc_dat_dir2", 0);
+                omap_mux_init_signal("sdmmc_dat_dir3", 0);
+        }
+
+        /*
+         * Use internal loop-back in MMC/SDIO Module Input Clock
+         * selection
+         */
+        if (mmc_controller->slots[0].internal_clock) {
+                u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+                v |= (1 << 24);
+                omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
+        }
+}
+
+void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
+{
+        struct platform_device *pdev;
+        struct omap_hwmod *oh;
+        int id = 0;
+        char *oh_name = "msdi1";
+        char *dev_name = "mmci-omap";
+
+        if (!mmc_data[0]) {
+                pr_err("%s fails: Incomplete platform data\n", __func__);
+                return;
+        }
+
+        omap242x_mmc_mux(mmc_data[0]);
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return;
+        }
+        pdev = omap_device_build(dev_name, id, oh, mmc_data[0],
+                                 sizeof(struct omap_mmc_platform_data), NULL, 0, 0);
+        if (IS_ERR(pdev))
+                WARN(1, "Can'd build omap_device for %s:%s.\n",
+                                        dev_name, oh->name);
+}
+
+#endif
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 471e62a74a1..76f9b3c2f58 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -127,7 +127,6 @@ struct omap_mux_partition {
  * @gpio:       GPIO number
  * @muxnames:   available signal modes for a ball
  * @balls:      available balls on the package
- * @partition:  mux partition
  */
 struct omap_mux {
         u16     reg_offset;
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 503ac777a2b..502e3135aad 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -19,6 +19,27 @@
 #include <linux/init.h>
 
         __CPUINIT
+
+/* Physical address needed since MMU not enabled yet on secondary core */
+#define AUX_CORE_BOOT0_PA                       0x48281800
+
+/*
+ * OMAP5 specific entry point for secondary CPU to jump from ROM
+ * code.  This routine also provides a holding flag into which
+ * secondary core is held until we're ready for it to initialise.
+ * The primary core will update this flag using a hardware
++ * register AuxCoreBoot0.
+ */
+ENTRY(omap5_secondary_startup)
+wait:   ldr     r2, =AUX_CORE_BOOT0_PA  @ read from AuxCoreBoot0
+        ldr     r0, [r2]
+        mov     r0, r0, lsr #5
+        mrc     p15, 0, r4, c0, c0, 5
+        and     r4, r4, #0x0f
+        cmp     r0, r4
+        bne     wait
+        b       secondary_startup
+END(omap5_secondary_startup)
 /*
  * OMAP4 specific entry point for secondary CPU to jump from ROM
  * code.  This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 56c345b8b93..414083b427d 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -17,8 +17,10 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
+#include <linux/io.h>
 
 #include <asm/cacheflush.h>
+#include <mach/omap-wakeupgen.h>
 
 #include "common.h"
 
@@ -35,7 +37,8 @@ int platform_cpu_kill(unsigned int cpu)
  */
 void __ref platform_cpu_die(unsigned int cpu)
 {
-        unsigned int this_cpu;
+        unsigned int boot_cpu = 0;
+        void __iomem *base = omap_get_wakeupgen_base();
 
         flush_cache_all();
         dsb();
@@ -43,16 +46,27 @@ void __ref platform_cpu_die(unsigned int cpu)
         /*
          * we're ready for shutdown now, so do it
          */
-        if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
-                pr_err("Secure clear status failed\n");
+        if (omap_secure_apis_support()) {
+                if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
+                        pr_err("Secure clear status failed\n");
+        } else {
+                __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
+        }
+
 
         for (;;) {
                 /*
                  * Enter into low power state
                  */
                 omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
-                this_cpu = smp_processor_id();
-                if (omap_read_auxcoreboot0() == this_cpu) {
+
+                if (omap_secure_apis_support())
+                        boot_cpu = omap_read_auxcoreboot0();
+                else
+                        boot_cpu =
+                                __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
+
+                if (boot_cpu == smp_processor_id()) {
                         /*
                          * OK, proper wakeup, we're done
                          */
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index ac49384d028..1be8bcb52e9 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -73,19 +73,17 @@ static struct iommu_device omap4_devices[] = {
                         .da_end = 0xFFFFF000,
                 },
         },
-#if defined(CONFIG_MPU_TESLA_IOMMU)
         {
                 .base = OMAP4_MMU2_BASE,
-                .irq = INT_44XX_DSP_MMU,
+                .irq = OMAP44XX_IRQ_TESLA_MMU,
                 .pdata = {
                         .name = "tesla",
                         .nr_tlb_entries = 32,
-                        .clk_name = "tesla_ick",
+                        .clk_name = "dsp_fck",
                         .da_start = 0x0,
                         .da_end = 0xFFFFF000,
                 },
         },
-#endif
 };
 #define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
 static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES];
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 13670aa84e5..637a1bdf2ac 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -255,7 +255,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
                 return -ENXIO;
         }
 
-        pwrdm_pre_transition();
+        pwrdm_pre_transition(NULL);
 
         /*
          * Check MPUSS next state and save interrupt controller if needed.
@@ -287,7 +287,7 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
         wakeup_cpu = smp_processor_id();
         set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
 
-        pwrdm_post_transition();
+        pwrdm_post_transition(NULL);
 
         return 0;
 }
@@ -313,7 +313,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
         scu_pwrst_prepare(cpu, power_state);
 
         /*
-         * CPU never retuns back if targetted power state is OFF mode.
+         * CPU never retuns back if targeted power state is OFF mode.
          * CPU ONLINE follows normal CPU ONLINE ptah via
          * omap_secondary_startup().
          */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index deffbf1c962..9a35adf9123 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -26,11 +26,19 @@
 
 #include <mach/hardware.h>
 #include <mach/omap-secure.h>
+#include <mach/omap-wakeupgen.h>
+#include <asm/cputype.h>
 
 #include "iomap.h"
 #include "common.h"
 #include "clockdomain.h"
 
+#define CPU_MASK                0xff0ffff0
+#define CPU_CORTEX_A9           0x410FC090
+#define CPU_CORTEX_A15          0x410FC0F0
+
+#define OMAP5_CORE_COUNT        0x2
+
 /* SCU base address */
 static void __iomem *scu_base;
 
@@ -73,6 +81,8 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         static struct clockdomain *cpu1_clkdm;
         static bool booted;
+        void __iomem *base = omap_get_wakeupgen_base();
+
         /*
          * Set synchronisation state between this boot processor
          * and the secondary one
@@ -85,7 +95,11 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * the AuxCoreBoot1 register is updated with cpu state
          * A barrier is added to ensure that write buffer is drained
          */
-        omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+        if (omap_secure_apis_support())
+                omap_modify_auxcoreboot0(0x200, 0xfffffdff);
+        else
+                __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+
         flush_cache_all();
         smp_wmb();
 
@@ -111,7 +125,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
                 booted = true;
         }
 
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        gic_raise_softirq(cpumask_of(cpu), 0);
 
         /*
          * Now the secondary core is starting up let it run its
@@ -124,13 +138,19 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init wakeup_secondary(void)
 {
+        void __iomem *base = omap_get_wakeupgen_base();
         /*
          * Write the address of secondary startup routine into the
          * AuxCoreBoot1 where ROM code will jump and start executing
          * on secondary core once out of WFE
          * A barrier is added to ensure that write buffer is drained
          */
-        omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+        if (omap_secure_apis_support())
+                omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
+        else
+                __raw_writel(virt_to_phys(omap5_secondary_startup),
+                                                base + OMAP_AUX_CORE_BOOT_1);
+
         smp_wmb();
 
         /*
@@ -147,16 +167,21 @@ static void __init wakeup_secondary(void)
  */
 void __init smp_init_cpus(void)
 {
-        unsigned int i, ncores;
-
-        /*
-         * Currently we can't call ioremap here because
-         * SoC detection won't work until after init_early.
-         */
-        scu_base =  OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
-        BUG_ON(!scu_base);
-
-        ncores = scu_get_core_count(scu_base);
+        unsigned int i = 0, ncores = 1, cpu_id;
+
+        /* Use ARM cpuid check here, as SoC detection will not work so early */
+        cpu_id = read_cpuid(CPUID_ID) & CPU_MASK;
+        if (cpu_id == CPU_CORTEX_A9) {
+                /*
+                 * Currently we can't call ioremap here because
+                 * SoC detection won't work until after init_early.
+                 */
+                scu_base =  OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
+                BUG_ON(!scu_base);
+                ncores = scu_get_core_count(scu_base);
+        } else if (cpu_id == CPU_CORTEX_A15) {
+                ncores = OMAP5_CORE_COUNT;
+        }
 
         /* sanity check */
         if (ncores > nr_cpu_ids) {
@@ -178,6 +203,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
          * Initialise the SCU and wake up the secondary core using
          * wakeup_secondary().
          */
-        scu_enable(scu_base);
+        if (scu_base)
+                scu_enable(scu_base);
         wakeup_secondary();
 }
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index d811c779035..05fdebfaa19 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -33,18 +33,23 @@
 #include "omap4-sar-layout.h"
 #include "common.h"
 
-#define NR_REG_BANKS            4
-#define MAX_IRQS                128
+#define MAX_NR_REG_BANKS        5
+#define MAX_IRQS                160
 #define WKG_MASK_ALL            0x00000000
 #define WKG_UNMASK_ALL          0xffffffff
 #define CPU_ENA_OFFSET          0x400
 #define CPU0_ID                 0x0
 #define CPU1_ID                 0x1
+#define OMAP4_NR_BANKS          4
+#define OMAP4_NR_IRQS           128
 
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
 static DEFINE_SPINLOCK(wakeupgen_lock);
 static unsigned int irq_target_cpu[NR_IRQS];
+static unsigned int irq_banks = MAX_NR_REG_BANKS;
+static unsigned int max_irqs = MAX_IRQS;
+static unsigned int omap_secure_apis;
 
 /*
  * Static helper functions.
@@ -146,13 +151,13 @@ static void wakeupgen_unmask(struct irq_data *d)
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
-static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
+static DEFINE_PER_CPU(u32 [MAX_NR_REG_BANKS], irqmasks);
 
 static void _wakeupgen_save_masks(unsigned int cpu)
 {
         u8 i;
 
-        for (i = 0; i < NR_REG_BANKS; i++)
+        for (i = 0; i < irq_banks; i++)
                 per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
 }
 
@@ -160,7 +165,7 @@ static void _wakeupgen_restore_masks(unsigned int cpu)
 {
         u8 i;
 
-        for (i = 0; i < NR_REG_BANKS; i++)
+        for (i = 0; i < irq_banks; i++)
                 wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
 }
 
@@ -168,7 +173,7 @@ static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
 {
         u8 i;
 
-        for (i = 0; i < NR_REG_BANKS; i++)
+        for (i = 0; i < irq_banks; i++)
                 wakeupgen_writel(reg, i, cpu);
 }
 
@@ -196,25 +201,14 @@ static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
 #endif
 
 #ifdef CONFIG_CPU_PM
-/*
- * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
- * ROM code. WakeupGen IP is integrated along with GIC to manage the
- * interrupt wakeups from CPU low power states. It manages
- * masking/unmasking of Shared peripheral interrupts(SPI). So the
- * interrupt enable/disable control should be in sync and consistent
- * at WakeupGen and GIC so that interrupts are not lost.
- */
-static void irq_save_context(void)
+static inline void omap4_irq_save_context(void)
 {
         u32 i, val;
 
         if (omap_rev() == OMAP4430_REV_ES1_0)
                 return;
 
-        if (!sar_base)
-                sar_base = omap4_get_sar_ram_base();
-
-        for (i = 0; i < NR_REG_BANKS; i++) {
+        for (i = 0; i < irq_banks; i++) {
                 /* Save the CPUx interrupt mask for IRQ 0 to 127 */
                 val = wakeupgen_readl(i, 0);
                 sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
@@ -254,6 +248,53 @@ static void irq_save_context(void)
         val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
         val |= SAR_BACKUP_STATUS_WAKEUPGEN;
         __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+
+}
+
+static inline void omap5_irq_save_context(void)
+{
+        u32 i, val;
+
+        for (i = 0; i < irq_banks; i++) {
+                /* Save the CPUx interrupt mask for IRQ 0 to 159 */
+                val = wakeupgen_readl(i, 0);
+                sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU0, i);
+                val = wakeupgen_readl(i, 1);
+                sar_writel(val, OMAP5_WAKEUPGENENB_OFFSET_CPU1, i);
+                sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
+                sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
+        }
+
+        /* Save AuxBoot* registers */
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
+
+        /* Set the Backup Bit Mask status */
+        val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+        val |= SAR_BACKUP_STATUS_WAKEUPGEN;
+        __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+
+}
+
+/*
+ * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
+ * ROM code. WakeupGen IP is integrated along with GIC to manage the
+ * interrupt wakeups from CPU low power states. It manages
+ * masking/unmasking of Shared peripheral interrupts(SPI). So the
+ * interrupt enable/disable control should be in sync and consistent
+ * at WakeupGen and GIC so that interrupts are not lost.
+ */
+static void irq_save_context(void)
+{
+        if (!sar_base)
+                sar_base = omap4_get_sar_ram_base();
+
+        if (soc_is_omap54xx())
+                omap5_irq_save_context();
+        else
+                omap4_irq_save_context();
 }
 
 /*
@@ -262,9 +303,14 @@ static void irq_save_context(void)
 static void irq_sar_clear(void)
 {
         u32 val;
-        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+        u32 offset = SAR_BACKUP_STATUS_OFFSET;
+
+        if (soc_is_omap54xx())
+                offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
+
+        val = __raw_readl(sar_base + offset);
         val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
-        __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+        __raw_writel(val, sar_base + offset);
 }
 
 /*
@@ -336,13 +382,25 @@ static struct notifier_block irq_notifier_block = {
 
 static void __init irq_pm_init(void)
 {
-        cpu_pm_register_notifier(&irq_notifier_block);
+        /* FIXME: Remove this when MPU OSWR support is added */
+        if (!soc_is_omap54xx())
+                cpu_pm_register_notifier(&irq_notifier_block);
 }
 #else
 static void __init irq_pm_init(void)
 {}
 #endif
 
+void __iomem *omap_get_wakeupgen_base(void)
+{
+        return wakeupgen_base;
+}
+
+int omap_secure_apis_support(void)
+{
+        return omap_secure_apis;
+}
+
 /*
  * Initialise the wakeupgen module.
  */
@@ -358,12 +416,18 @@ int __init omap_wakeupgen_init(void)
         }
 
         /* Static mapping, never released */
-        wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
+        wakeupgen_base = ioremap(OMAP_WKUPGEN_BASE, SZ_4K);
         if (WARN_ON(!wakeupgen_base))
                 return -ENOMEM;
 
+        if (cpu_is_omap44xx()) {
+                irq_banks = OMAP4_NR_BANKS;
+                max_irqs = OMAP4_NR_IRQS;
+                omap_secure_apis = 1;
+        }
+
         /* Clear all IRQ bitmasks at wakeupGen level */
-        for (i = 0; i < NR_REG_BANKS; i++) {
+        for (i = 0; i < irq_banks; i++) {
                 wakeupgen_writel(0, i, CPU0_ID);
                 wakeupgen_writel(0, i, CPU1_ID);
         }
@@ -382,7 +446,7 @@ int __init omap_wakeupgen_init(void)
          */
 
         /* Associate all the IRQs to boot CPU like GIC init does. */
-        for (i = 0; i < NR_IRQS; i++)
+        for (i = 0; i < max_irqs; i++)
                 irq_target_cpu[i] = boot_cpu;
 
         irq_hotplug_init();
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index a8161e5f320..c29dee998a7 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -21,6 +21,8 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
 #include <asm/memblock.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 
 #include <plat/irqs.h>
 #include <plat/sram.h>
@@ -210,6 +212,18 @@ static int __init omap4_sar_ram_init(void)
 }
 early_initcall(omap4_sar_ram_init);
 
+static struct of_device_id irq_match[] __initdata = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        { .compatible = "arm,cortex-a15-gic", .data = gic_of_init, },
+        { }
+};
+
+void __init omap_gic_of_init(void)
+{
+        omap_wakeupgen_init();
+        of_irq_init(irq_match);
+}
+
 #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 {
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index fe5b545ad44..e170fe803b0 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -12,7 +12,7 @@
 #define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
 
 /*
- * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
+ * SAR BANK offsets from base address OMAP44XX/54XX_SAR_RAM_BASE
  */
 #define SAR_BANK1_OFFSET                0x0000
 #define SAR_BANK2_OFFSET                0x1000
@@ -47,4 +47,14 @@
 #define PTMSYNCREQ_EN_OFFSET                    (SAR_BANK3_OFFSET + 0x6d0)
 #define SAR_BACKUP_STATUS_WAKEUPGEN             0x10
 
+/* WakeUpGen save restore offset from OMAP54XX_SAR_RAM_BASE */
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU0          (SAR_BANK3_OFFSET + 0x8d4)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0   (SAR_BANK3_OFFSET + 0x8e8)
+#define OMAP5_WAKEUPGENENB_OFFSET_CPU1          (SAR_BANK3_OFFSET + 0x8fc)
+#define OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1   (SAR_BANK3_OFFSET + 0x910)
+#define OMAP5_AUXCOREBOOT0_OFFSET               (SAR_BANK3_OFFSET + 0x924)
+#define OMAP5_AUXCOREBOOT1_OFFSET               (SAR_BANK3_OFFSET + 0x928)
+#define OMAP5_AMBA_IF_MODE_OFFSET               (SAR_BANK3_OFFSET + 0x92c)
+#define OMAP5_SAR_BACKUP_STATUS_OFFSET          (SAR_BANK3_OFFSET + 0x800)
+
 #endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 2d710f50fca..6ca8e519968 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -153,6 +153,7 @@
 #include "prm44xx.h"
 #include "prminst44xx.h"
 #include "mux.h"
+#include "pm.h"
 
 /* Maximum microseconds to wait for OMAP module to softreset */
 #define MAX_MODULE_SOFTRESET_WAIT       10000
@@ -166,12 +167,40 @@
  */
 #define LINKS_PER_OCP_IF                2
 
+/**
+ * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
+ * @enable_module: function to enable a module (via MODULEMODE)
+ * @disable_module: function to disable a module (via MODULEMODE)
+ *
+ * XXX Eventually this functionality will be hidden inside the PRM/CM
+ * device drivers.  Until then, this should avoid huge blocks of cpu_is_*()
+ * conditionals in this code.
+ */
+struct omap_hwmod_soc_ops {
+        void (*enable_module)(struct omap_hwmod *oh);
+        int (*disable_module)(struct omap_hwmod *oh);
+        int (*wait_target_ready)(struct omap_hwmod *oh);
+        int (*assert_hardreset)(struct omap_hwmod *oh,
+                                struct omap_hwmod_rst_info *ohri);
+        int (*deassert_hardreset)(struct omap_hwmod *oh,
+                                  struct omap_hwmod_rst_info *ohri);
+        int (*is_hardreset_asserted)(struct omap_hwmod *oh,
+                                     struct omap_hwmod_rst_info *ohri);
+        int (*init_clkdm)(struct omap_hwmod *oh);
+};
+
+/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
+static struct omap_hwmod_soc_ops soc_ops;
+
 /* omap_hwmod_list contains all registered struct omap_hwmods */
 static LIST_HEAD(omap_hwmod_list);
 
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
 
+/* io_chain_lock: used to serialize reconfigurations of the I/O chain */
+static DEFINE_SPINLOCK(io_chain_lock);
+
 /*
  * linkspace: ptr to a buffer that struct omap_hwmod_link records are
  * allocated from - used to reduce the number of small memory
@@ -186,6 +215,9 @@ static struct omap_hwmod_link *linkspace;
  */
 static unsigned short free_ls, max_ls, ls_supp;
 
+/* inited: set to true once the hwmod code is initialized */
+static bool inited;
+
 /* Private functions */
 
 /**
@@ -388,6 +420,49 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
 }
 
 /**
+ * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v
+ * @oh: struct omap_hwmod *
+ *
+ * The DMADISABLE bit is a semi-automatic bit present in sysconfig register
+ * of some modules. When the DMA must perform read/write accesses, the
+ * DMADISABLE bit is cleared by the hardware. But when the DMA must stop
+ * for power management, software must set the DMADISABLE bit back to 1.
+ *
+ * Set the DMADISABLE bit in @v for hwmod @oh.  Returns -EINVAL upon
+ * error or 0 upon success.
+ */
+static int _set_dmadisable(struct omap_hwmod *oh)
+{
+        u32 v;
+        u32 dmadisable_mask;
+
+        if (!oh->class->sysc ||
+            !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE))
+                return -EINVAL;
+
+        if (!oh->class->sysc->sysc_fields) {
+                WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
+                return -EINVAL;
+        }
+
+        /* clocks must be on for this operation */
+        if (oh->_state != _HWMOD_STATE_ENABLED) {
+                pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name);
+                return -EINVAL;
+        }
+
+        pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name);
+
+        v = oh->_sysc_cache;
+        dmadisable_mask =
+                (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift);
+        v |= dmadisable_mask;
+        _write_sysconfig(v, oh);
+
+        return 0;
+}
+
+/**
  * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
  * @oh: struct omap_hwmod *
  * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
@@ -771,23 +846,19 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
 }
 
 /**
- * _enable_module - enable CLKCTRL modulemode on OMAP4
+ * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4
  * @oh: struct omap_hwmod *
  *
  * Enables the PRCM module mode related to the hwmod @oh.
  * No return value.
  */
-static void _enable_module(struct omap_hwmod *oh)
+static void _omap4_enable_module(struct omap_hwmod *oh)
 {
-        /* The module mode does not exist prior OMAP4 */
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                return;
-
         if (!oh->clkdm || !oh->prcm.omap4.modulemode)
                 return;
 
-        pr_debug("omap_hwmod: %s: _enable_module: %d\n",
-                 oh->name, oh->prcm.omap4.modulemode);
+        pr_debug("omap_hwmod: %s: %s: %d\n",
+                 oh->name, __func__, oh->prcm.omap4.modulemode);
 
         omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
                                    oh->clkdm->prcm_partition,
@@ -807,10 +878,7 @@ static void _enable_module(struct omap_hwmod *oh)
  */
 static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 {
-        if (!cpu_is_omap44xx())
-                return 0;
-
-        if (!oh)
+        if (!oh || !oh->clkdm)
                 return -EINVAL;
 
         if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
@@ -1301,24 +1369,20 @@ static struct omap_hwmod *_lookup(const char *name)
 
         return oh;
 }
+
 /**
  * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
  * @oh: struct omap_hwmod *
  *
  * Convert a clockdomain name stored in a struct omap_hwmod into a
  * clockdomain pointer, and save it into the struct omap_hwmod.
- * return -EINVAL if clkdm_name does not exist or if the lookup failed.
+ * Return -EINVAL if the clkdm_name lookup failed.
  */
 static int _init_clkdm(struct omap_hwmod *oh)
 {
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+        if (!oh->clkdm_name)
                 return 0;
 
-        if (!oh->clkdm_name) {
-                pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
-                return -EINVAL;
-        }
-
         oh->clkdm = clkdm_lookup(oh->clkdm_name);
         if (!oh->clkdm) {
                 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
@@ -1354,7 +1418,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
         ret |= _init_main_clk(oh);
         ret |= _init_interface_clks(oh);
         ret |= _init_opt_clks(oh);
-        ret |= _init_clkdm(oh);
+        if (soc_ops.init_clkdm)
+                ret |= soc_ops.init_clkdm(oh);
 
         if (!ret)
                 oh->_state = _HWMOD_STATE_CLKS_INITED;
@@ -1365,53 +1430,6 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
 }
 
 /**
- * _wait_target_ready - wait for a module to leave slave idle
- * @oh: struct omap_hwmod *
- *
- * Wait for a module @oh to leave slave idle.  Returns 0 if the module
- * does not have an IDLEST bit or if the module successfully leaves
- * slave idle; otherwise, pass along the return value of the
- * appropriate *_cm*_wait_module_ready() function.
- */
-static int _wait_target_ready(struct omap_hwmod *oh)
-{
-        struct omap_hwmod_ocp_if *os;
-        int ret;
-
-        if (!oh)
-                return -EINVAL;
-
-        if (oh->flags & HWMOD_NO_IDLEST)
-                return 0;
-
-        os = _find_mpu_rt_port(oh);
-        if (!os)
-                return 0;
-
-        /* XXX check module SIDLEMODE */
-
-        /* XXX check clock enable states */
-
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
-                                                 oh->prcm.omap2.idlest_reg_id,
-                                                 oh->prcm.omap2.idlest_idle_bit);
-        } else if (cpu_is_omap44xx()) {
-                if (!oh->clkdm)
-                        return -EINVAL;
-
-                ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
-                                                     oh->clkdm->cm_inst,
-                                                     oh->clkdm->clkdm_offs,
-                                                     oh->prcm.omap4.clkctrl_offs);
-        } else {
-                BUG();
-        };
-
-        return ret;
-}
-
-/**
  * _lookup_hardreset - fill register bit info for this hwmod/reset line
  * @oh: struct omap_hwmod *
  * @name: name of the reset line in the context of this hwmod
@@ -1447,32 +1465,31 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
  * @oh: struct omap_hwmod *
  * @name: name of the reset line to lookup and assert
  *
- * Some IP like dsp, ipu or iva contain processor that require
- * an HW reset line to be assert / deassert in order to enable fully
- * the IP.
+ * Some IP like dsp, ipu or iva contain processor that require an HW
+ * reset line to be assert / deassert in order to enable fully the IP.
+ * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
+ * asserting the hardreset line on the currently-booted SoC, or passes
+ * along the return value from _lookup_hardreset() or the SoC's
+ * assert_hardreset code.
  */
 static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
-        u8 ret;
+        u8 ret = -EINVAL;
 
         if (!oh)
                 return -EINVAL;
 
+        if (!soc_ops.assert_hardreset)
+                return -ENOSYS;
+
         ret = _lookup_hardreset(oh, name, &ohri);
         if (IS_ERR_VALUE(ret))
                 return ret;
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
-                                                  ohri.rst_shift);
-        else if (cpu_is_omap44xx())
-                return omap4_prminst_assert_hardreset(ohri.rst_shift,
-                                  oh->clkdm->pwrdm.ptr->prcm_partition,
-                                  oh->clkdm->pwrdm.ptr->prcm_offs,
-                                  oh->prcm.omap4.rstctrl_offs);
-        else
-                return -EINVAL;
+        ret = soc_ops.assert_hardreset(oh, &ohri);
+
+        return ret;
 }
 
 /**
@@ -1481,38 +1498,29 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
  * @oh: struct omap_hwmod *
  * @name: name of the reset line to look up and deassert
  *
- * Some IP like dsp, ipu or iva contain processor that require
- * an HW reset line to be assert / deassert in order to enable fully
- * the IP.
+ * Some IP like dsp, ipu or iva contain processor that require an HW
+ * reset line to be assert / deassert in order to enable fully the IP.
+ * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
+ * deasserting the hardreset line on the currently-booted SoC, or passes
+ * along the return value from _lookup_hardreset() or the SoC's
+ * deassert_hardreset code.
  */
 static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
-        int ret;
+        int ret = -EINVAL;
 
         if (!oh)
                 return -EINVAL;
 
+        if (!soc_ops.deassert_hardreset)
+                return -ENOSYS;
+
         ret = _lookup_hardreset(oh, name, &ohri);
         if (IS_ERR_VALUE(ret))
                 return ret;
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
-                                                   ohri.rst_shift,
-                                                   ohri.st_shift);
-        } else if (cpu_is_omap44xx()) {
-                if (ohri.st_shift)
-                        pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
-                               oh->name, name);
-                ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
-                                  oh->clkdm->pwrdm.ptr->prcm_partition,
-                                  oh->clkdm->pwrdm.ptr->prcm_offs,
-                                  oh->prcm.omap4.rstctrl_offs);
-        } else {
-                return -EINVAL;
-        }
-
+        ret = soc_ops.deassert_hardreset(oh, &ohri);
         if (ret == -EBUSY)
                 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
 
@@ -1525,31 +1533,28 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
  * @oh: struct omap_hwmod *
  * @name: name of the reset line to look up and read
  *
- * Return the state of the reset line.
+ * Return the state of the reset line.  Returns -EINVAL if @oh is
+ * null, -ENOSYS if we have no way of reading the hardreset line
+ * status on the currently-booted SoC, or passes along the return
+ * value from _lookup_hardreset() or the SoC's is_hardreset_asserted
+ * code.
  */
 static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
-        u8 ret;
+        u8 ret = -EINVAL;
 
         if (!oh)
                 return -EINVAL;
 
+        if (!soc_ops.is_hardreset_asserted)
+                return -ENOSYS;
+
         ret = _lookup_hardreset(oh, name, &ohri);
         if (IS_ERR_VALUE(ret))
                 return ret;
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
-                                                       ohri.st_shift);
-        } else if (cpu_is_omap44xx()) {
-                return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
-                                  oh->clkdm->pwrdm.ptr->prcm_partition,
-                                  oh->clkdm->pwrdm.ptr->prcm_offs,
-                                  oh->prcm.omap4.rstctrl_offs);
-        } else {
-                return -EINVAL;
-        }
+        return soc_ops.is_hardreset_asserted(oh, &ohri);
 }
 
 /**
@@ -1587,10 +1592,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
 {
         int v;
 
-        /* The module mode does not exist prior OMAP4 */
-        if (!cpu_is_omap44xx())
-                return -EINVAL;
-
         if (!oh->clkdm || !oh->prcm.omap4.modulemode)
                 return -EINVAL;
 
@@ -1714,11 +1715,17 @@ dis_opt_clks:
  * therefore have no OCP header registers to access.  Others (like the
  * IVA) have idiosyncratic reset sequences.  So for these relatively
  * rare cases, custom reset code can be supplied in the struct
- * omap_hwmod_class .reset function pointer.  Passes along the return
- * value from either _ocp_softreset() or the custom reset function -
- * these must return -EINVAL if the hwmod cannot be reset this way or
- * if the hwmod is in the wrong state, -ETIMEDOUT if the module did
- * not reset in time, or 0 upon success.
+ * omap_hwmod_class .reset function pointer.
+ *
+ * _set_dmadisable() is called to set the DMADISABLE bit so that it
+ * does not prevent idling of the system. This is necessary for cases
+ * where ROMCODE/BOOTLOADER uses dma and transfers control to the
+ * kernel without disabling dma.
+ *
+ * Passes along the return value from either _ocp_softreset() or the
+ * custom reset function - these must return -EINVAL if the hwmod
+ * cannot be reset this way or if the hwmod is in the wrong state,
+ * -ETIMEDOUT if the module did not reset in time, or 0 upon success.
  */
 static int _reset(struct omap_hwmod *oh)
 {
@@ -1740,6 +1747,8 @@ static int _reset(struct omap_hwmod *oh)
                 }
         }
 
+        _set_dmadisable(oh);
+
         /*
          * OCP_SYSCONFIG bits need to be reprogrammed after a
          * softreset.  The _enable() function should be split to avoid
@@ -1754,6 +1763,32 @@ static int _reset(struct omap_hwmod *oh)
 }
 
 /**
+ * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain
+ *
+ * Call the appropriate PRM function to clear any logged I/O chain
+ * wakeups and to reconfigure the chain.  This apparently needs to be
+ * done upon every mux change.  Since hwmods can be concurrently
+ * enabled and idled, hold a spinlock around the I/O chain
+ * reconfiguration sequence.  No return value.
+ *
+ * XXX When the PRM code is moved to drivers, this function can be removed,
+ * as the PRM infrastructure should abstract this.
+ */
+static void _reconfigure_io_chain(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&io_chain_lock, flags);
+
+        if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl())
+                omap3xxx_prm_reconfigure_io_chain();
+        else if (cpu_is_omap44xx())
+                omap44xx_prm_reconfigure_io_chain();
+
+        spin_unlock_irqrestore(&io_chain_lock, flags);
+}
+
+/**
  * _enable - enable an omap_hwmod
  * @oh: struct omap_hwmod *
  *
@@ -1809,8 +1844,10 @@ static int _enable(struct omap_hwmod *oh)
         /* Mux pins for device runtime if populated */
         if (oh->mux && (!oh->mux->enabled ||
                         ((oh->_state == _HWMOD_STATE_IDLE) &&
-                         oh->mux->pads_dynamic)))
+                         oh->mux->pads_dynamic))) {
                 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+                _reconfigure_io_chain();
+        }
 
         _add_initiator_dep(oh, mpu_oh);
 
@@ -1830,9 +1867,11 @@ static int _enable(struct omap_hwmod *oh)
         }
 
         _enable_clocks(oh);
-        _enable_module(oh);
+        if (soc_ops.enable_module)
+                soc_ops.enable_module(oh);
 
-        r = _wait_target_ready(oh);
+        r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
+                -EINVAL;
         if (!r) {
                 /*
                  * Set the clockdomain to HW_AUTO only if the target is ready,
@@ -1886,7 +1925,8 @@ static int _idle(struct omap_hwmod *oh)
                 _idle_sysc(oh);
         _del_initiator_dep(oh, mpu_oh);
 
-        _omap4_disable_module(oh);
+        if (soc_ops.disable_module)
+                soc_ops.disable_module(oh);
 
         /*
          * The module must be in idle mode before disabling any parents
@@ -1899,8 +1939,10 @@ static int _idle(struct omap_hwmod *oh)
                 clkdm_hwmod_disable(oh->clkdm, oh);
 
         /* Mux pins for device idle if populated */
-        if (oh->mux && oh->mux->pads_dynamic)
+        if (oh->mux && oh->mux->pads_dynamic) {
                 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+                _reconfigure_io_chain();
+        }
 
         oh->_state = _HWMOD_STATE_IDLE;
 
@@ -1991,7 +2033,8 @@ static int _shutdown(struct omap_hwmod *oh)
         if (oh->_state == _HWMOD_STATE_ENABLED) {
                 _del_initiator_dep(oh, mpu_oh);
                 /* XXX what about the other system initiators here? dma, dsp */
-                _omap4_disable_module(oh);
+                if (soc_ops.disable_module)
+                        soc_ops.disable_module(oh);
                 _disable_clocks(oh);
                 if (oh->clkdm)
                         clkdm_hwmod_disable(oh->clkdm, oh);
@@ -2447,6 +2490,194 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
         return 0;
 }
 
+/* Static functions intended only for use in soc_ops field function pointers */
+
+/**
+ * _omap2_wait_target_ready - wait for a module to leave slave idle
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_ready() function.
+ */
+static int _omap2_wait_target_ready(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        if (!_find_mpu_rt_port(oh))
+                return 0;
+
+        /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
+
+        return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
+                                          oh->prcm.omap2.idlest_reg_id,
+                                          oh->prcm.omap2.idlest_idle_bit);
+}
+
+/**
+ * _omap4_wait_target_ready - wait for a module to leave slave idle
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_ready() function.
+ */
+static int _omap4_wait_target_ready(struct omap_hwmod *oh)
+{
+        if (!oh || !oh->clkdm)
+                return -EINVAL;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        if (!_find_mpu_rt_port(oh))
+                return 0;
+
+        /* XXX check module SIDLEMODE, hardreset status */
+
+        return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
+                                              oh->clkdm->cm_inst,
+                                              oh->clkdm->clkdm_offs,
+                                              oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
+ * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to assert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap2_prm_assert_hardreset() with parameters extracted from
+ * the hwmod @oh and the hardreset line data @ohri.  Only intended for
+ * use as an soc_ops function pointer.  Passes along the return value
+ * from omap2_prm_assert_hardreset().  XXX This function is scheduled
+ * for removal when the PRM code is moved into drivers/.
+ */
+static int _omap2_assert_hardreset(struct omap_hwmod *oh,
+                                   struct omap_hwmod_rst_info *ohri)
+{
+        return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
+                                          ohri->rst_shift);
+}
+
+/**
+ * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to deassert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap2_prm_deassert_hardreset() with parameters extracted from
+ * the hwmod @oh and the hardreset line data @ohri.  Only intended for
+ * use as an soc_ops function pointer.  Passes along the return value
+ * from omap2_prm_deassert_hardreset().  XXX This function is
+ * scheduled for removal when the PRM code is moved into drivers/.
+ */
+static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
+                                     struct omap_hwmod_rst_info *ohri)
+{
+        return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
+                                            ohri->rst_shift,
+                                            ohri->st_shift);
+}
+
+/**
+ * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to test hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap2_prm_is_hardreset_asserted() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from omap2_prm_is_hardreset_asserted().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh,
+                                        struct omap_hwmod_rst_info *ohri)
+{
+        return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
+                                               ohri->st_shift);
+}
+
+/**
+ * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to assert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap4_prminst_assert_hardreset() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from omap4_prminst_assert_hardreset().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _omap4_assert_hardreset(struct omap_hwmod *oh,
+                                   struct omap_hwmod_rst_info *ohri)
+{
+        if (!oh->clkdm)
+                return -EINVAL;
+
+        return omap4_prminst_assert_hardreset(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_partition,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+
+/**
+ * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to deassert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap4_prminst_deassert_hardreset() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from omap4_prminst_deassert_hardreset().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
+                                     struct omap_hwmod_rst_info *ohri)
+{
+        if (!oh->clkdm)
+                return -EINVAL;
+
+        if (ohri->st_shift)
+                pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
+                       oh->name, ohri->name);
+        return omap4_prminst_deassert_hardreset(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_partition,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+
+/**
+ * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to test hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap4_prminst_is_hardreset_asserted() with parameters
+ * extracted from the hwmod @oh and the hardreset line data @ohri.
+ * Only intended for use as an soc_ops function pointer.  Passes along
+ * the return value from omap4_prminst_is_hardreset_asserted().  XXX
+ * This function is scheduled for removal when the PRM code is moved
+ * into drivers/.
+ */
+static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
+                                        struct omap_hwmod_rst_info *ohri)
+{
+        if (!oh->clkdm)
+                return -EINVAL;
+
+        return omap4_prminst_is_hardreset_asserted(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_partition,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+
 /* Public functions */
 
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
@@ -2579,12 +2810,18 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
  *
  * Intended to be called early in boot before the clock framework is
  * initialized.  If @ois is not null, will register all omap_hwmods
- * listed in @ois that are valid for this chip.  Returns 0.
+ * listed in @ois that are valid for this chip.  Returns -EINVAL if
+ * omap_hwmod_init() hasn't been called before calling this function,
+ * -ENOMEM if the link memory area can't be allocated, or 0 upon
+ * success.
  */
 int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
 {
         int r, i;
 
+        if (!inited)
+                return -EINVAL;
+
         if (!ois)
                 return 0;
 
@@ -3417,3 +3654,47 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
 
         return 0;
 }
+
+/**
+ * omap_hwmod_init - initialize the hwmod code
+ *
+ * Sets up some function pointers needed by the hwmod code to operate on the
+ * currently-booted SoC.  Intended to be called once during kernel init
+ * before any hwmods are registered.  No return value.
+ */
+void __init omap_hwmod_init(void)
+{
+        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                soc_ops.wait_target_ready = _omap2_wait_target_ready;
+                soc_ops.assert_hardreset = _omap2_assert_hardreset;
+                soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
+                soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+        } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+                soc_ops.enable_module = _omap4_enable_module;
+                soc_ops.disable_module = _omap4_disable_module;
+                soc_ops.wait_target_ready = _omap4_wait_target_ready;
+                soc_ops.assert_hardreset = _omap4_assert_hardreset;
+                soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
+                soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
+                soc_ops.init_clkdm = _init_clkdm;
+        } else {
+                WARN(1, "omap_hwmod: unknown SoC type\n");
+        }
+
+        inited = true;
+}
+
+/**
+ * omap_hwmod_get_main_clk - get pointer to main clock name
+ * @oh: struct omap_hwmod *
+ *
+ * Returns the main clock name assocated with @oh upon success,
+ * or NULL if @oh is NULL.
+ */
+const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return NULL;
+
+        return oh->main_clk;
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a7640d1b215..50cfab61b0e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -192,6 +192,11 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
         .name = "mcbsp",
 };
 
+static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
+        { .role = "pad_fck", .clk = "mcbsp_clks" },
+        { .role = "prcm_fck", .clk = "func_96m_ck" },
+};
+
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
         { .name = "tx", .irq = 59 },
@@ -214,6 +219,8 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* mcbsp2 */
@@ -238,6 +245,8 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
@@ -585,5 +594,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 
 int __init omap2420_hwmod_init(void)
 {
+        omap_hwmod_init();
         return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4d726498123..58b5bc196d3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -296,6 +296,11 @@ static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
         .rev  = MCBSP_CONFIG_TYPE2,
 };
 
+static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
+        { .role = "pad_fck", .clk = "mcbsp_clks" },
+        { .role = "prcm_fck", .clk = "func_96m_ck" },
+};
+
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
         { .name = "tx",         .irq = 59 },
@@ -320,6 +325,8 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* mcbsp2 */
@@ -345,6 +352,8 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* mcbsp3 */
@@ -370,6 +379,8 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* mcbsp4 */
@@ -401,6 +412,8 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* mcbsp5 */
@@ -432,6 +445,8 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* MMC/SD/SDIO common */
@@ -938,5 +953,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
 
 int __init omap2430_hwmod_init(void)
 {
+        omap_hwmod_init();
         return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 83eafd96eca..afad69c6ba6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -68,7 +68,6 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
         .name   = "timer",
         .sysc   = &omap2xxx_timer_sysc,
-        .rev    = OMAP_TIMER_IP_VERSION_1,
 };
 
 /*
@@ -257,7 +256,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -276,7 +274,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -295,7 +292,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -314,7 +310,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -333,7 +328,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -352,7 +346,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -371,7 +364,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index b26d3c9bca1..c9e38200216 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -14,6 +14,8 @@
  *
  * XXX these should be marked initdata for multi-OMAP kernels
  */
+#include <linux/power/smartreflex.h>
+
 #include <plat/omap_hwmod.h>
 #include <mach/irqs.h>
 #include <plat/cpu.h>
@@ -29,8 +31,6 @@
 #include <plat/dmtimer.h>
 
 #include "omap_hwmod_common_data.h"
-
-#include "smartreflex.h"
 #include "prm-regbits-34xx.h"
 #include "cm-regbits-34xx.h"
 #include "wd_timer.h"
@@ -129,7 +129,6 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
         .name = "timer",
         .sysc = &omap3xxx_timer_1ms_sysc,
-        .rev = OMAP_TIMER_IP_VERSION_1,
 };
 
 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
@@ -145,12 +144,11 @@ static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
         .name = "timer",
         .sysc = &omap3xxx_timer_sysc,
-        .rev =  OMAP_TIMER_IP_VERSION_1,
 };
 
 /* secure timers dev attribute */
 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
-        .timer_capability       = OMAP_TIMER_SECURE,
+        .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 };
 
 /* always-on timers dev attribute */
@@ -195,7 +193,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap3xxx_timer_1ms_hwmod_class,
 };
 
@@ -213,7 +210,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -231,7 +227,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -249,7 +244,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -267,7 +261,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -285,7 +278,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -527,11 +519,27 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
 
 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
         { .irq = INT_35XX_UART4_IRQ, },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
+        { .dma_req = -1 }
+};
+
+/*
+ * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
+ * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
+ * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
+ * should not be needed.  The functional clock structure of the AM35xx
+ * UART4 is extremely unclear and opaque; it is unclear what the role
+ * of uart1/2_fck is for the UART4.  Any clarification from either
+ * empirical testing or the AM3505/3517 hardware designers would be
+ * most welcome.
+ */
+static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
+        { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 };
 
 static struct omap_hwmod am35xx_uart4_hwmod = {
@@ -543,11 +551,14 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
                 .omap2 = {
                         .module_offs = CORE_MOD,
                         .prcm_reg_id = 1,
-                        .module_bit = OMAP3430_EN_UART4_SHIFT,
+                        .module_bit = AM35XX_EN_UART4_SHIFT,
                         .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
+                        .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
                 },
         },
+        .opt_clks       = am35xx_uart4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .class          = &omap2_uart_class,
 };
 
@@ -1074,6 +1085,17 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
         .rev  = MCBSP_CONFIG_TYPE3,
 };
 
+/* McBSP functional clock mapping */
+static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
+        { .role = "pad_fck", .clk = "mcbsp_clks" },
+        { .role = "prcm_fck", .clk = "core_96m_fck" },
+};
+
+static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
+        { .role = "pad_fck", .clk = "mcbsp_clks" },
+        { .role = "prcm_fck", .clk = "per_96m_fck" },
+};
+
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
         { .name = "common", .irq = 16 },
@@ -1097,6 +1119,8 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp15_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
 };
 
 /* mcbsp2 */
@@ -1126,6 +1150,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp234_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
 };
 
@@ -1156,6 +1182,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp234_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
 };
 
@@ -1188,6 +1216,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp234_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
 };
 
 /* mcbsp5 */
@@ -1219,6 +1249,8 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp15_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
 };
 
 /* 'mcbsp sidetone' class */
@@ -1325,7 +1357,7 @@ static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
 };
 
 static struct omap_hwmod omap34xx_sr1_hwmod = {
-        .name           = "sr1",
+        .name           = "smartreflex_mpu_iva",
         .class          = &omap34xx_smartreflex_hwmod_class,
         .main_clk       = "sr1_fck",
         .prcm           = {
@@ -1343,7 +1375,7 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
 };
 
 static struct omap_hwmod omap36xx_sr1_hwmod = {
-        .name           = "sr1",
+        .name           = "smartreflex_mpu_iva",
         .class          = &omap36xx_smartreflex_hwmod_class,
         .main_clk       = "sr1_fck",
         .prcm           = {
@@ -1370,7 +1402,7 @@ static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
 };
 
 static struct omap_hwmod omap34xx_sr2_hwmod = {
-        .name           = "sr2",
+        .name           = "smartreflex_core",
         .class          = &omap34xx_smartreflex_hwmod_class,
         .main_clk       = "sr2_fck",
         .prcm           = {
@@ -1388,7 +1420,7 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
 };
 
 static struct omap_hwmod omap36xx_sr2_hwmod = {
-        .name           = "sr2",
+        .name           = "smartreflex_core",
         .class          = &omap36xx_smartreflex_hwmod_class,
         .main_clk       = "sr2_fck",
         .prcm           = {
@@ -1638,25 +1670,20 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
 
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
-
         { .name = "mc", .irq = 71 },
         { .irq = -1 }
 };
 
 static struct omap_hwmod_class am35xx_usbotg_class = {
         .name = "am35xx_usbotg",
-        .sysc = NULL,
 };
 
 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
         .name           = "am35x_otg_hs",
         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
-        .main_clk       = NULL,
-        .prcm = {
-                .omap2 = {
-                },
-        },
+        .main_clk       = "hsotgusb_fck",
         .class          = &am35xx_usbotg_class,
+        .flags          = HWMOD_NO_IDLEST,
 };
 
 /* MMC/SD/SDIO common */
@@ -2097,9 +2124,10 @@ static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
         .master         = &am35xx_usbhsotg_hwmod,
         .slave          = &omap3xxx_l3_main_hwmod,
-        .clk            = "core_l3_ick",
+        .clk            = "hsotgusb_ick",
         .user           = OCP_USER_MPU,
 };
+
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .master = &omap3xxx_l4_core_hwmod,
@@ -2243,6 +2271,7 @@ static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
@@ -2393,7 +2422,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &am35xx_usbhsotg_hwmod,
-        .clk            = "l4_ick",
+        .clk            = "hsotgusb_ick",
         .addr           = am35xx_usbhsotg_addrs,
         .user           = OCP_USER_MPU,
 };
@@ -3138,6 +3167,107 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* am35xx has Davinci MDIO & EMAC */
+static struct omap_hwmod_class am35xx_mdio_class = {
+        .name = "davinci_mdio",
+};
+
+static struct omap_hwmod am35xx_mdio_hwmod = {
+        .name           = "davinci_mdio",
+        .class          = &am35xx_mdio_class,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * XXX Should be connected to an IPSS hwmod, not the L3 directly;
+ * but this will probably require some additional hwmod core support,
+ * so is left as a future to-do item.
+ */
+static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
+        .master         = &am35xx_mdio_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "emac_fck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
+        {
+                .pa_start       = AM35XX_IPSS_MDIO_BASE,
+                .pa_end         = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_core -> davinci mdio  */
+/*
+ * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
+ * but this will probably require some additional hwmod core support,
+ * so is left as a future to-do item.
+ */
+static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_mdio_hwmod,
+        .clk            = "emac_fck",
+        .addr           = am35xx_mdio_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
+        { .name = "rxthresh",   .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
+        { .name = "rx_pulse",   .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
+        { .name = "tx_pulse",   .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
+        { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_class am35xx_emac_class = {
+        .name = "davinci_emac",
+};
+
+static struct omap_hwmod am35xx_emac_hwmod = {
+        .name           = "davinci_emac",
+        .mpu_irqs       = am35xx_emac_mpu_irqs,
+        .class          = &am35xx_emac_class,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/* l3_core -> davinci emac interface */
+/*
+ * XXX Should be connected to an IPSS hwmod, not the L3 directly;
+ * but this will probably require some additional hwmod core support,
+ * so is left as a future to-do item.
+ */
+static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
+        .master         = &am35xx_emac_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "emac_ick",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
+        {
+                .pa_start       = AM35XX_IPSS_EMAC_BASE,
+                .pa_end         = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_core -> davinci emac  */
+/*
+ * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
+ * but this will probably require some additional hwmod core support,
+ * so is left as a future to-do item.
+ */
+static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_emac_hwmod,
+        .clk            = "emac_ick",
+        .addr           = am35xx_emac_addrs,
+        .user           = OCP_USER_MPU,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l3_main__l4_core,
         &omap3xxx_l3_main__l4_per,
@@ -3266,6 +3396,10 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l4_core__usb_tll_hs,
         &omap3xxx_l4_core__es3plus_mmc1,
         &omap3xxx_l4_core__es3plus_mmc2,
+        &am35xx_mdio__l3,
+        &am35xx_l4_core__mdio,
+        &am35xx_emac__l3,
+        &am35xx_l4_core__emac,
         NULL
 };
 
@@ -3283,6 +3417,8 @@ int __init omap3xxx_hwmod_init(void)
         struct omap_hwmod_ocp_if **h = NULL;
         unsigned int rev;
 
+        omap_hwmod_init();
+
         /* Register hwmod links common to all OMAP3 */
         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
         if (r < 0)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index b7bcba5221b..242aee498ce 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -19,6 +19,7 @@
  */
 
 #include <linux/io.h>
+#include <linux/power/smartreflex.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
@@ -32,8 +33,6 @@
 #include <plat/common.h>
 
 #include "omap_hwmod_common_data.h"
-
-#include "smartreflex.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
 #include "prm44xx.h"
@@ -2544,14 +2543,12 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
         .name           = "cm_core_aon",
         .class          = &omap44xx_prcm_hwmod_class,
-        .clkdm_name     = "cm_clkdm",
 };
 
 /* cm_core */
 static struct omap_hwmod omap44xx_cm_core_hwmod = {
         .name           = "cm_core",
         .class          = &omap44xx_prcm_hwmod_class,
-        .clkdm_name     = "cm_clkdm",
 };
 
 /* prm */
@@ -2568,7 +2565,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
 static struct omap_hwmod omap44xx_prm_hwmod = {
         .name           = "prm",
         .class          = &omap44xx_prcm_hwmod_class,
-        .clkdm_name     = "prm_clkdm",
         .mpu_irqs       = omap44xx_prm_irqs,
         .rst_lines      = omap44xx_prm_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
@@ -2947,7 +2943,6 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
 };
 
 /* timer3 */
@@ -2969,7 +2964,6 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
 };
 
 /* timer4 */
@@ -2991,7 +2985,6 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
 };
 
 /* timer5 */
@@ -3013,7 +3006,6 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
 };
 
 /* timer6 */
@@ -3036,7 +3028,6 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
 };
 
 /* timer7 */
@@ -3058,7 +3049,6 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .dev_attr       = &capability_alwon_dev_attr,
 };
 
 /* timer8 */
@@ -6148,6 +6138,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 
 int __init omap44xx_hwmod_init(void)
 {
+        omap_hwmod_init();
         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
 }
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index 51e5418899f..9f1ccdc8cc8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -47,6 +47,16 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
         .midle_shift    = SYSC_TYPE2_MIDLEMODE_SHIFT,
         .sidle_shift    = SYSC_TYPE2_SIDLEMODE_SHIFT,
         .srst_shift     = SYSC_TYPE2_SOFTRESET_SHIFT,
+        .dmadisable_shift = SYSC_TYPE2_DMADISABLE_SHIFT,
+};
+
+/**
+ * struct omap_hwmod_sysc_type3 - TYPE3 sysconfig scheme.
+ * Used by some IPs on AM33xx
+ */
+struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3 = {
+        .midle_shift    = SYSC_TYPE3_MIDLEMODE_SHIFT,
+        .sidle_shift    = SYSC_TYPE3_SIDLEMODE_SHIFT,
 };
 
 struct omap_dss_dispc_dev_attr omap2_3_dss_dispc_dev_attr = {
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
index 90b50984cd2..a6ce34dc481 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.h
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -51,7 +51,9 @@ static u32 l3_targ_inst_clk1[] = {
         0x200, /* DMM2 */
         0x300, /* ABE */
         0x400, /* L4CFG */
-        0x600  /* CLK2 PWR DISC */
+        0x600,  /* CLK2 PWR DISC */
+        0x0,    /* Host CLK1 */
+        0x900   /* L4 Wakeup */
 };
 
 static u32 l3_targ_inst_clk2[] = {
@@ -72,11 +74,16 @@ static u32 l3_targ_inst_clk2[] = {
         0xE00, /* missing in TRM corresponds to AES2*/
         0xC00, /* L4 PER3 */
         0xA00, /* L4 PER1*/
-        0xB00 /* L4 PER2*/
+        0xB00, /* L4 PER2*/
+        0x0, /* HOST CLK2 */
+        0x1800, /* CAL */
+        0x1700 /* LLI */
 };
 
 static u32 l3_targ_inst_clk3[] = {
-        0x0100  /* EMUSS */
+        0x0100  /* EMUSS */,
+        0x0300, /* DEBUGSS_CT_TBR */
+        0x0 /* HOST CLK3 */
 };
 
 static struct l3_masters_data {
@@ -110,13 +117,15 @@ static struct l3_masters_data {
         { 0xC8, "USBHOSTFS"}
 };
 
-static char *l3_targ_inst_name[L3_MODULES][18] = {
+static char *l3_targ_inst_name[L3_MODULES][21] = {
         {
                 "DMM1",
                 "DMM2",
                 "ABE",
                 "L4CFG",
                 "CLK2 PWR DISC",
+                "HOST CLK1",
+                "L4 WAKEUP"
         },
         {
                 "CORTEX M3" ,
@@ -137,9 +146,14 @@ static char *l3_targ_inst_name[L3_MODULES][18] = {
                 "L4 PER3",
                 "L4 PER1",
                 "L4 PER2",
+                "HOST CLK2",
+                "CAL",
+                "LLI"
         },
         {
                 "EMUSS",
+                "DEBUG SOURCE",
+                "HOST CLK3"
         },
 };
 
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index de6d4645174..d8f6dbf45d1 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -53,7 +53,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
         omap_table_init = 1;
 
         /* Lets now register with OPP library */
-        for (i = 0; i < opp_def_size; i++) {
+        for (i = 0; i < opp_def_size; i++, opp_def++) {
                 struct omap_hwmod *oh;
                 struct device *dev;
 
@@ -86,7 +86,6 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
                                         __func__, opp_def->freq,
                                         opp_def->hwmod_name, i, r);
                 }
-                opp_def++;
         }
 
         return 0;
diff --git a/arch/arm/mach-omap2/opp4xxx_data.c b/arch/arm/mach-omap2/opp4xxx_data.c
index 2293ba27101..c95415da23c 100644
--- a/arch/arm/mach-omap2/opp4xxx_data.c
+++ b/arch/arm/mach-omap2/opp4xxx_data.c
@@ -94,7 +94,7 @@ int __init omap4_opp_init(void)
 {
         int r = -ENODEV;
 
-        if (!cpu_is_omap44xx())
+        if (!cpu_is_omap443x())
                 return r;
 
         r = omap_init_opp_table(omap44xx_opp_def_list,
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 78564895e91..686137d164d 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -15,12 +15,25 @@
 
 #include "powerdomain.h"
 
+#ifdef CONFIG_CPU_IDLE
+extern int __init omap3_idle_init(void);
+extern int __init omap4_idle_init(void);
+#else
+static inline int omap3_idle_init(void)
+{
+        return 0;
+}
+
+static inline int omap4_idle_init(void)
+{
+        return 0;
+}
+#endif
+
 extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
-extern int omap3_idle_init(void);
-extern int omap4_idle_init(void);
 extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
 extern int (*omap_pm_suspend)(void);
 
@@ -88,7 +101,7 @@ extern void enable_omap3630_toggle_l2_on_restore(void);
 static inline void enable_omap3630_toggle_l2_on_restore(void) { }
 #endif          /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
 
-#ifdef CONFIG_OMAP_SMARTREFLEX
+#ifdef CONFIG_POWER_AVS_OMAP
 extern int omap_devinit_smartreflex(void);
 extern void omap_enable_smartreflex_on_init(void);
 #else
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 3a595e89972..05bd8f02723 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -70,34 +70,6 @@ void (*omap3_do_wfi_sram)(void);
 
 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
 static struct powerdomain *core_pwrdm, *per_pwrdm;
-static struct powerdomain *cam_pwrdm;
-
-static void omap3_enable_io_chain(void)
-{
-        int timeout = 0;
-
-        omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-                                   PM_WKEN);
-        /* Do a readback to assure write has been done */
-        omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
-
-        while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
-                 OMAP3430_ST_IO_CHAIN_MASK)) {
-                timeout++;
-                if (timeout > 1000) {
-                        pr_err("Wake up daisy chain activation failed.\n");
-                        return;
-                }
-                omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
-                                           WKUP_MOD, PM_WKEN);
-        }
-}
-
-static void omap3_disable_io_chain(void)
-{
-        omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
-                                     PM_WKEN);
-}
 
 static void omap3_core_save_context(void)
 {
@@ -299,15 +271,8 @@ void omap_sram_idle(void)
         /* Enable IO-PAD and IO-CHAIN wakeups */
         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
-        if (omap3_has_io_wakeup() &&
-            (per_next_state < PWRDM_POWER_ON ||
-             core_next_state < PWRDM_POWER_ON)) {
-                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
-                if (omap3_has_io_chain_ctrl())
-                        omap3_enable_io_chain();
-        }
 
-        pwrdm_pre_transition();
+        pwrdm_pre_transition(NULL);
 
         /* PER */
         if (per_next_state < PWRDM_POWER_ON) {
@@ -372,23 +337,11 @@ void omap_sram_idle(void)
         }
         omap3_intc_resume_idle();
 
-        pwrdm_post_transition();
+        pwrdm_post_transition(NULL);
 
         /* PER */
         if (per_next_state < PWRDM_POWER_ON)
                 omap2_gpio_resume_after_idle();
-
-        /* Disable IO-PAD and IO-CHAIN wakeup */
-        if (omap3_has_io_wakeup() &&
-            (per_next_state < PWRDM_POWER_ON ||
-             core_next_state < PWRDM_POWER_ON)) {
-                omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
-                                             PM_WKEN);
-                if (omap3_has_io_chain_ctrl())
-                        omap3_disable_io_chain();
-        }
-
-        clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 }
 
 static void omap3_pm_idle(void)
@@ -581,10 +534,13 @@ static void __init prcm_setup_regs(void)
                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 
         /* Don't attach IVA interrupts */
-        omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
-        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
-        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
-        omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
+        if (omap3_has_iva()) {
+                omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+                omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+                omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+                omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
+                                        OMAP3430_PM_IVAGRPSEL);
+        }
 
         /* Clear any pending 'reset' flags */
         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
@@ -598,7 +554,9 @@ static void __init prcm_setup_regs(void)
         /* Clear any pending PRCM interrupts */
         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-        omap3_iva_idle();
+        if (omap3_has_iva())
+                omap3_iva_idle();
+
         omap3_d2d_idle();
 }
 
@@ -749,7 +707,6 @@ int __init omap3_pm_init(void)
         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
         per_pwrdm = pwrdm_lookup("per_pwrdm");
         core_pwrdm = pwrdm_lookup("core_pwrdm");
-        cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 
         neon_clkdm = clkdm_lookup("neon_clkdm");
         mpu_clkdm = clkdm_lookup("mpu_clkdm");
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 96114901b93..69b36e185e9 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -526,7 +526,8 @@ int pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
  *
  * Return the powerdomain @pwrdm's current power state. Returns -EINVAL
  * if the powerdomain pointer is null or returns the current power state
- * upon success.
+ * upon success. Note that if the power domain only supports the ON state
+ * then just return ON as the current state.
  */
 int pwrdm_read_pwrst(struct powerdomain *pwrdm)
 {
@@ -535,6 +536,9 @@ int pwrdm_read_pwrst(struct powerdomain *pwrdm)
         if (!pwrdm)
                 return -EINVAL;
 
+        if (pwrdm->pwrsts == PWRSTS_ON)
+                return PWRDM_POWER_ON;
+
         if (arch_pwrdm && arch_pwrdm->pwrdm_read_pwrst)
                 ret = arch_pwrdm->pwrdm_read_pwrst(pwrdm);
 
@@ -981,15 +985,23 @@ int pwrdm_state_switch(struct powerdomain *pwrdm)
         return ret;
 }
 
-int pwrdm_pre_transition(void)
+int pwrdm_pre_transition(struct powerdomain *pwrdm)
 {
-        pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
+        if (pwrdm)
+                _pwrdm_pre_transition_cb(pwrdm, NULL);
+        else
+                pwrdm_for_each(_pwrdm_pre_transition_cb, NULL);
+
         return 0;
 }
 
-int pwrdm_post_transition(void)
+int pwrdm_post_transition(struct powerdomain *pwrdm)
 {
-        pwrdm_for_each(_pwrdm_post_transition_cb, NULL);
+        if (pwrdm)
+                _pwrdm_post_transition_cb(pwrdm, NULL);
+        else
+                pwrdm_for_each(_pwrdm_post_transition_cb, NULL);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 8f88d65c46e..baee90608d1 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -67,9 +67,9 @@
 
 /*
  * Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain on OMAP4 is the worst case
+ * PER powerdomain on AM33XX is the worst case
  */
-#define PWRDM_MAX_CLKDMS        9
+#define PWRDM_MAX_CLKDMS        11
 
 /* XXX A completely arbitrary number. What is reasonable here? */
 #define PWRDM_TRANSITION_BAILOUT 100000
@@ -92,6 +92,15 @@ struct powerdomain;
  * @pwrdm_clkdms: Clockdomains in this powerdomain
  * @node: list_head linking all powerdomains
  * @voltdm_node: list_head linking all powerdomains in a voltagedomain
+ * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
+ * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
+ * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
+ *      in @pwrstctrl_offs
+ * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
+ * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
+ * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
+ * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
+ *      in @pwrstctrl_offs
  * @state:
  * @state_counter:
  * @timer:
@@ -121,6 +130,14 @@ struct powerdomain {
         unsigned ret_logic_off_counter;
         unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
 
+        const u8 pwrstctrl_offs;
+        const u8 pwrstst_offs;
+        const u32 logicretstate_mask;
+        const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
+        const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
+        const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
+        const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
+
 #ifdef CONFIG_PM_DEBUG
         s64 timer;
         s64 state_timer[PWRDM_MAX_PWRSTS];
@@ -213,8 +230,8 @@ bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
 int pwrdm_wait_transition(struct powerdomain *pwrdm);
 
 int pwrdm_state_switch(struct powerdomain *pwrdm);
-int pwrdm_pre_transition(void);
-int pwrdm_post_transition(void);
+int pwrdm_pre_transition(struct powerdomain *pwrdm);
+int pwrdm_post_transition(struct powerdomain *pwrdm);
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
 int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
 bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
@@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
 extern void omap242x_powerdomains_init(void);
 extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
+extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
 
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
+extern struct pwrdm_ops am33xx_pwrdm_operations;
 extern struct pwrdm_ops omap4_pwrdm_operations;
 
 /* Common Internal functions used across OMAP rev's */
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c
new file mode 100644
index 00000000000..67c5663899b
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain33xx.c
@@ -0,0 +1,229 @@
+/*
+ * AM33XX Powerdomain control
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
+ * <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <plat/prcm.h>
+
+#include "powerdomain.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+
+static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
+                                (pwrst << OMAP_POWERSTATE_SHIFT),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+
+static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs,  pwrdm->pwrstctrl_offs);
+        v &= OMAP_POWERSTATE_MASK;
+        v >>= OMAP_POWERSTATE_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= OMAP_POWERSTATEST_MASK;
+        v >>= OMAP_POWERSTATEST_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
+        v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+        am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
+                                (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+
+static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
+                                AM33XX_LASTPOWERSTATEENTERED_MASK,
+                                pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        return 0;
+}
+
+static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 m;
+
+        m = pwrdm->logicretstate_mask;
+        if (!m)
+                return -EINVAL;
+
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+        return 0;
+}
+
+static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= AM33XX_LOGICSTATEST_MASK;
+        v >>= AM33XX_LOGICSTATEST_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        u32 v, m;
+
+        m = pwrdm->logicretstate_mask;
+        if (!m)
+                return -EINVAL;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                u8 pwrst)
+{
+        u32 m;
+
+        m = pwrdm->mem_on_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+        return 0;
+}
+
+static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                        u8 pwrst)
+{
+        u32 m;
+
+        m = pwrdm->mem_ret_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+        return 0;
+}
+
+static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = pwrdm->mem_pwrst_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = pwrdm->mem_retst_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+
+        /* XXX Is this udelay() value meaningful? */
+        while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
+                        & OMAP_INTRANSITION_MASK) &&
+                        (c++ < PWRDM_TRANSITION_BAILOUT))
+                udelay(1);
+
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
+                       pwrdm->name);
+                return -EAGAIN;
+        }
+
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+        return 0;
+}
+
+struct pwrdm_ops am33xx_pwrdm_operations = {
+        .pwrdm_set_next_pwrst           = am33xx_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst          = am33xx_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst               = am33xx_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst          = am33xx_pwrdm_read_prev_pwrst,
+        .pwrdm_set_logic_retst          = am33xx_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst         = am33xx_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst         = am33xx_pwrdm_read_logic_retst,
+        .pwrdm_clear_all_prev_pwrst     = am33xx_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_set_lowpwrstchange       = am33xx_pwrdm_set_lowpwrstchange,
+        .pwrdm_read_mem_pwrst           = am33xx_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst           = am33xx_pwrdm_read_mem_retst,
+        .pwrdm_set_mem_onst             = am33xx_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst            = am33xx_pwrdm_set_mem_retst,
+        .pwrdm_wait_transition          = am33xx_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
new file mode 100644
index 00000000000..869adb82569
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -0,0 +1,185 @@
+/*
+ * AM33XX Power domain data
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+#include "prcm-common.h"
+#include "prm-regbits-33xx.h"
+#include "prm33xx.h"
+
+static struct powerdomain gfx_33xx_pwrdm = {
+        .name                   = "gfx_pwrdm",
+        .voltdm                 = { .name = "core" },
+        .prcm_offs              = AM33XX_PRM_GFX_MOD,
+        .pwrstctrl_offs         = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
+        .pwrstst_offs           = AM33XX_PM_GFX_PWRSTST_OFFSET,
+        .pwrsts                 = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret       = PWRSTS_OFF_RET,
+        .flags                  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .banks                  = 1,
+        .logicretstate_mask     = AM33XX_LOGICRETSTATE_MASK,
+        .mem_on_mask            = {
+                [0]             = AM33XX_GFX_MEM_ONSTATE_MASK,  /* gfx_mem */
+        },
+        .mem_ret_mask           = {
+                [0]             = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
+        },
+        .mem_pwrst_mask         = {
+                [0]             = AM33XX_GFX_MEM_STATEST_MASK,  /* gfx_mem */
+        },
+        .mem_retst_mask         = {
+                [0]             = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
+        },
+        .pwrsts_mem_ret         = {
+                [0]             = PWRSTS_OFF_RET,       /* gfx_mem */
+        },
+        .pwrsts_mem_on          = {
+                [0]             = PWRSTS_ON,            /* gfx_mem */
+        },
+};
+
+static struct powerdomain rtc_33xx_pwrdm = {
+        .name                   = "rtc_pwrdm",
+        .voltdm                 = { .name = "rtc" },
+        .prcm_offs              = AM33XX_PRM_RTC_MOD,
+        .pwrstctrl_offs         = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
+        .pwrstst_offs           = AM33XX_PM_RTC_PWRSTST_OFFSET,
+        .pwrsts                 = PWRSTS_ON,
+        .logicretstate_mask     = AM33XX_LOGICRETSTATE_MASK,
+};
+
+static struct powerdomain wkup_33xx_pwrdm = {
+        .name                   = "wkup_pwrdm",
+        .voltdm                 = { .name = "core" },
+        .prcm_offs              = AM33XX_PRM_WKUP_MOD,
+        .pwrstctrl_offs         = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
+        .pwrstst_offs           = AM33XX_PM_WKUP_PWRSTST_OFFSET,
+        .pwrsts                 = PWRSTS_ON,
+        .logicretstate_mask     = AM33XX_LOGICRETSTATE_3_3_MASK,
+};
+
+static struct powerdomain per_33xx_pwrdm = {
+        .name                   = "per_pwrdm",
+        .voltdm                 = { .name = "core" },
+        .prcm_offs              = AM33XX_PRM_PER_MOD,
+        .pwrstctrl_offs         = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
+        .pwrstst_offs           = AM33XX_PM_PER_PWRSTST_OFFSET,
+        .pwrsts                 = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret       = PWRSTS_OFF_RET,
+        .flags                  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .banks                  = 3,
+        .logicretstate_mask     = AM33XX_LOGICRETSTATE_3_3_MASK,
+        .mem_on_mask            = {
+                [0]             = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
+                [1]             = AM33XX_PER_MEM_ONSTATE_MASK,  /* per_mem */
+                [2]             = AM33XX_RAM_MEM_ONSTATE_MASK,  /* ram_mem */
+        },
+        .mem_ret_mask           = {
+                [0]             = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
+                [1]             = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
+                [2]             = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
+        },
+        .mem_pwrst_mask         = {
+                [0]             = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
+                [1]             = AM33XX_PER_MEM_STATEST_MASK,  /* per_mem */
+                [2]             = AM33XX_RAM_MEM_STATEST_MASK,  /* ram_mem */
+        },
+        .mem_retst_mask         = {
+                [0]             = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
+                [1]             = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
+                [2]             = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
+        },
+        .pwrsts_mem_ret         = {
+                [0]             = PWRSTS_OFF_RET,       /* pruss_mem */
+                [1]             = PWRSTS_OFF_RET,       /* per_mem */
+                [2]             = PWRSTS_OFF_RET,       /* ram_mem */
+        },
+        .pwrsts_mem_on          = {
+                [0]             = PWRSTS_ON,            /* pruss_mem */
+                [1]             = PWRSTS_ON,            /* per_mem */
+                [2]             = PWRSTS_ON,            /* ram_mem */
+        },
+};
+
+static struct powerdomain mpu_33xx_pwrdm = {
+        .name                   = "mpu_pwrdm",
+        .voltdm                 = { .name = "mpu" },
+        .prcm_offs              = AM33XX_PRM_MPU_MOD,
+        .pwrstctrl_offs         = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
+        .pwrstst_offs           = AM33XX_PM_MPU_PWRSTST_OFFSET,
+        .pwrsts                 = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret       = PWRSTS_OFF_RET,
+        .flags                  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .banks                  = 3,
+        .logicretstate_mask     = AM33XX_LOGICRETSTATE_MASK,
+        .mem_on_mask            = {
+                [0]             = AM33XX_MPU_L1_ONSTATE_MASK,   /* mpu_l1 */
+                [1]             = AM33XX_MPU_L2_ONSTATE_MASK,   /* mpu_l2 */
+                [2]             = AM33XX_MPU_RAM_ONSTATE_MASK,  /* mpu_ram */
+        },
+        .mem_ret_mask           = {
+                [0]             = AM33XX_MPU_L1_RETSTATE_MASK,  /* mpu_l1 */
+                [1]             = AM33XX_MPU_L2_RETSTATE_MASK,  /* mpu_l2 */
+                [2]             = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
+        },
+        .mem_pwrst_mask         = {
+                [0]             = AM33XX_MPU_L1_STATEST_MASK,   /* mpu_l1 */
+                [1]             = AM33XX_MPU_L2_STATEST_MASK,   /* mpu_l2 */
+                [2]             = AM33XX_MPU_RAM_STATEST_MASK,  /* mpu_ram */
+        },
+        .mem_retst_mask         = {
+                [0]             = AM33XX_MPU_L1_RETSTATE_MASK,  /* mpu_l1 */
+                [1]             = AM33XX_MPU_L2_RETSTATE_MASK,  /* mpu_l2 */
+                [2]             = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
+        },
+        .pwrsts_mem_ret         = {
+                [0]             = PWRSTS_OFF_RET,       /* mpu_l1 */
+                [1]             = PWRSTS_OFF_RET,       /* mpu_l2 */
+                [2]             = PWRSTS_OFF_RET,       /* mpu_ram */
+        },
+        .pwrsts_mem_on          = {
+                [0]             = PWRSTS_ON,            /* mpu_l1 */
+                [1]             = PWRSTS_ON,            /* mpu_l2 */
+                [2]             = PWRSTS_ON,            /* mpu_ram */
+        },
+};
+
+static struct powerdomain cefuse_33xx_pwrdm = {
+        .name           = "cefuse_pwrdm",
+        .voltdm         = { .name = "core" },
+        .prcm_offs      = AM33XX_PRM_CEFUSE_MOD,
+        .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
+        .pwrstst_offs   = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
+        .pwrsts         = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain *powerdomains_am33xx[] __initdata = {
+        &gfx_33xx_pwrdm,
+        &rtc_33xx_pwrdm,
+        &wkup_33xx_pwrdm,
+        &per_33xx_pwrdm,
+        &mpu_33xx_pwrdm,
+        &cefuse_33xx_pwrdm,
+        NULL,
+};
+
+void __init am33xx_powerdomains_init(void)
+{
+        pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_am33xx);
+        pwrdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index fb0a0a6869d..bb883e46307 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -71,6 +71,22 @@ static struct powerdomain mpu_3xxx_pwrdm = {
         .voltdm           = { .name = "mpu_iva" },
 };
 
+static struct powerdomain mpu_am35x_pwrdm = {
+        .name             = "mpu_pwrdm",
+        .prcm_offs        = MPU_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .flags            = PWRDM_HAS_MPU_QUIRK,
+        .banks            = 1,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_ON,
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_ON,
+        },
+        .voltdm           = { .name = "mpu_iva" },
+};
+
 /*
  * The USBTLL Save-and-Restore mechanism is broken on
  * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
@@ -120,6 +136,23 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain core_am35x_pwrdm = {
+        .name             = "core_pwrdm",
+        .prcm_offs        = CORE_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .banks            = 2,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_ON,         /* MEM1RETSTATE */
+                [1] = PWRSTS_ON,         /* MEM2RETSTATE */
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_ON, /* MEM1ONSTATE */
+                [1] = PWRSTS_ON, /* MEM2ONSTATE */
+        },
+        .voltdm           = { .name = "core" },
+};
+
 static struct powerdomain dss_pwrdm = {
         .name             = "dss_pwrdm",
         .prcm_offs        = OMAP3430_DSS_MOD,
@@ -135,6 +168,21 @@ static struct powerdomain dss_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain dss_am35x_pwrdm = {
+        .name             = "dss_pwrdm",
+        .prcm_offs        = OMAP3430_DSS_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_ON, /* MEMRETSTATE */
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
+        },
+        .voltdm           = { .name = "core" },
+};
+
 /*
  * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
  * possible SGX powerstate, the SGX device itself does not support
@@ -156,6 +204,21 @@ static struct powerdomain sgx_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain sgx_am35x_pwrdm = {
+        .name             = "sgx_pwrdm",
+        .prcm_offs        = OMAP3430ES2_SGX_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_ON, /* MEMRETSTATE */
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
+        },
+        .voltdm           = { .name = "core" },
+};
+
 static struct powerdomain cam_pwrdm = {
         .name             = "cam_pwrdm",
         .prcm_offs        = OMAP3430_CAM_MOD,
@@ -186,6 +249,21 @@ static struct powerdomain per_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain per_am35x_pwrdm = {
+        .name             = "per_pwrdm",
+        .prcm_offs        = OMAP3430_PER_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_ON, /* MEMRETSTATE */
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
+        },
+        .voltdm           = { .name = "core" },
+};
+
 static struct powerdomain emu_pwrdm = {
         .name           = "emu_pwrdm",
         .prcm_offs      = OMAP3430_EMU_MOD,
@@ -200,6 +278,14 @@ static struct powerdomain neon_pwrdm = {
         .voltdm           = { .name = "mpu_iva" },
 };
 
+static struct powerdomain neon_am35x_pwrdm = {
+        .name             = "neon_pwrdm",
+        .prcm_offs        = OMAP3430_NEON_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+
 static struct powerdomain usbhost_pwrdm = {
         .name             = "usbhost_pwrdm",
         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
@@ -293,6 +379,22 @@ static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
         NULL
 };
 
+static struct powerdomain *powerdomains_am35x[] __initdata = {
+        &wkup_omap2_pwrdm,
+        &mpu_am35x_pwrdm,
+        &neon_am35x_pwrdm,
+        &core_am35x_pwrdm,
+        &sgx_am35x_pwrdm,
+        &dss_am35x_pwrdm,
+        &per_am35x_pwrdm,
+        &emu_pwrdm,
+        &dpll1_pwrdm,
+        &dpll3_pwrdm,
+        &dpll4_pwrdm,
+        &dpll5_pwrdm,
+        NULL
+};
+
 void __init omap3xxx_powerdomains_init(void)
 {
         unsigned int rev;
@@ -301,21 +403,34 @@ void __init omap3xxx_powerdomains_init(void)
                 return;
 
         pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
-        pwrdm_register_pwrdms(powerdomains_omap3430_common);
 
         rev = omap_rev();
 
-        if (rev == OMAP3430_REV_ES1_0)
-                pwrdm_register_pwrdms(powerdomains_omap3430es1);
-        else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
-                 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
-                pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
-        else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
-                 rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1 ||
-                 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
-                pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
-        else
-                WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
+        if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
+                pwrdm_register_pwrdms(powerdomains_am35x);
+        } else {
+                pwrdm_register_pwrdms(powerdomains_omap3430_common);
+
+                switch (rev) {
+                case OMAP3430_REV_ES1_0:
+                        pwrdm_register_pwrdms(powerdomains_omap3430es1);
+                        break;
+                case OMAP3430_REV_ES2_0:
+                case OMAP3430_REV_ES2_1:
+                case OMAP3430_REV_ES3_0:
+                case OMAP3630_REV_ES1_0:
+                        pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
+                        break;
+                case OMAP3430_REV_ES3_1:
+                case OMAP3430_REV_ES3_1_2:
+                case OMAP3630_REV_ES1_1:
+                case OMAP3630_REV_ES1_2:
+                        pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
+                        break;
+                default:
+                        WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
+                }
+        }
 
         pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6da3ba483ad..e5f0503a68b 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -203,8 +203,8 @@
 #define OMAP3430_EN_MMC2_SHIFT                          25
 #define OMAP3430_EN_MMC1_MASK                           (1 << 24)
 #define OMAP3430_EN_MMC1_SHIFT                          24
-#define OMAP3430_EN_UART4_MASK                          (1 << 23)
-#define OMAP3430_EN_UART4_SHIFT                         23
+#define AM35XX_EN_UART4_MASK                            (1 << 23)
+#define AM35XX_EN_UART4_SHIFT                           23
 #define OMAP3430_EN_MCSPI4_MASK                         (1 << 21)
 #define OMAP3430_EN_MCSPI4_SHIFT                        21
 #define OMAP3430_EN_MCSPI3_MASK                         (1 << 20)
@@ -410,13 +410,21 @@
  */
 #define MAX_MODULE_HARDRESET_WAIT               10000
 
+/*
+ * Maximum time(us) it takes to output the signal WUCLKOUT of the last
+ * pad of the I/O ring after asserting WUCLKIN high.  Tero measured
+ * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4
+ * microseconds on OMAP4, so this timeout may be too high.
+ */
+#define MAX_IOPAD_LATCH_TIME                    100
+
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
 extern void __iomem *cm_base;
 extern void __iomem *cm2_base;
 extern void __iomem *prcm_mpu_base;
 
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5)
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
 extern void omap_prm_base_init(void);
 extern void omap_cm_base_init(void);
 #else
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 480f40a5ee4..053e24ed3c4 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -35,6 +35,7 @@
 #include "prm2xxx_3xxx.h"
 #include "prm44xx.h"
 #include "prminst44xx.h"
+#include "cminst44xx.h"
 #include "prm-regbits-24xx.h"
 #include "prm-regbits-44xx.h"
 #include "control.h"
@@ -159,8 +160,30 @@ void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
         if (omap2_globals->prcm_mpu)
                 prcm_mpu_base = omap2_globals->prcm_mpu;
 
-        if (cpu_is_omap44xx()) {
+        if (cpu_is_omap44xx() || soc_is_omap54xx()) {
                 omap_prm_base_init();
                 omap_cm_base_init();
         }
 }
+
+/*
+ * Stubbed functions so that common files continue to build when
+ * custom builds are used
+ * XXX These are temporary and should be removed at the earliest possible
+ * opportunity
+ */
+int __weak omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs)
+{
+        return 0;
+}
+
+void __weak omap4_cminst_module_enable(u8 mode, u8 part, u16 inst,
+                                s16 cdoffs, u16 clkctrl_offs)
+{
+}
+
+void __weak omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+                                 u16 clkctrl_offs)
+{
+}
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
new file mode 100644
index 00000000000..0221b5c20e8
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -0,0 +1,357 @@
+/*
+ * AM33XX PRM_XXX register bits
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+
+#include "prm.h"
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT                  1
+#define AM33XX_ABBOFF_ACT_EXPORT_MASK                   (1 << 1)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT                2
+#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK                 (1 << 2)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_AIPOFF_SHIFT                             8
+#define AM33XX_AIPOFF_MASK                              (1 << 8)
+
+/* Used by PM_WKUP_PWRSTST */
+#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT                17
+#define AM33XX_DEBUGSS_MEM_STATEST_MASK                 (0x3 << 17)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_DISABLE_RTA_EXPORT_SHIFT                 0
+#define AM33XX_DISABLE_RTA_EXPORT_MASK                  (1 << 0)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT                 12
+#define AM33XX_DPLL_CORE_RECAL_EN_MASK                  (1 << 12)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT                 12
+#define AM33XX_DPLL_CORE_RECAL_ST_MASK                  (1 << 12)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT                  14
+#define AM33XX_DPLL_DDR_RECAL_EN_MASK                   (1 << 14)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT                  14
+#define AM33XX_DPLL_DDR_RECAL_ST_MASK                   (1 << 14)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT                 15
+#define AM33XX_DPLL_DISP_RECAL_EN_MASK                  (1 << 15)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT                 13
+#define AM33XX_DPLL_DISP_RECAL_ST_MASK                  (1 << 13)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT                  11
+#define AM33XX_DPLL_MPU_RECAL_EN_MASK                   (1 << 11)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT                  11
+#define AM33XX_DPLL_MPU_RECAL_ST_MASK                   (1 << 11)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_PER_RECAL_EN_SHIFT                  13
+#define AM33XX_DPLL_PER_RECAL_EN_MASK                   (1 << 13)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_PER_RECAL_ST_SHIFT                  15
+#define AM33XX_DPLL_PER_RECAL_ST_MASK                   (1 << 15)
+
+/* Used by RM_WKUP_RSTST */
+#define AM33XX_EMULATION_M3_RST_SHIFT                   6
+#define AM33XX_EMULATION_M3_RST_MASK                    (1 << 6)
+
+/* Used by RM_MPU_RSTST */
+#define AM33XX_EMULATION_MPU_RST_SHIFT                  5
+#define AM33XX_EMULATION_MPU_RST_MASK                   (1 << 5)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC1_EXPORT_SHIFT                     3
+#define AM33XX_ENFUNC1_EXPORT_MASK                      (1 << 3)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC3_EXPORT_SHIFT                     5
+#define AM33XX_ENFUNC3_EXPORT_MASK                      (1 << 5)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC4_SHIFT                            6
+#define AM33XX_ENFUNC4_MASK                             (1 << 6)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC5_SHIFT                            7
+#define AM33XX_ENFUNC5_MASK                             (1 << 7)
+
+/* Used by PRM_RSTST */
+#define AM33XX_EXTERNAL_WARM_RST_SHIFT                  5
+#define AM33XX_EXTERNAL_WARM_RST_MASK                   (1 << 5)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_FORCEWKUP_EN_SHIFT                       10
+#define AM33XX_FORCEWKUP_EN_MASK                        (1 << 10)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_FORCEWKUP_ST_SHIFT                       10
+#define AM33XX_FORCEWKUP_ST_MASK                        (1 << 10)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define AM33XX_GFX_MEM_ONSTATE_SHIFT                    17
+#define AM33XX_GFX_MEM_ONSTATE_MASK                     (0x3 << 17)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define AM33XX_GFX_MEM_RETSTATE_SHIFT                   6
+#define AM33XX_GFX_MEM_RETSTATE_MASK                    (1 << 6)
+
+/* Used by PM_GFX_PWRSTST */
+#define AM33XX_GFX_MEM_STATEST_SHIFT                    4
+#define AM33XX_GFX_MEM_STATEST_MASK                     (0x3 << 4)
+
+/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
+#define AM33XX_GFX_RST_SHIFT                            0
+#define AM33XX_GFX_RST_MASK                             (1 << 0)
+
+/* Used by PRM_RSTST */
+#define AM33XX_GLOBAL_COLD_RST_SHIFT                    0
+#define AM33XX_GLOBAL_COLD_RST_MASK                     (1 << 0)
+
+/* Used by PRM_RSTST */
+#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT                 1
+#define AM33XX_GLOBAL_WARM_SW_RST_MASK                  (1 << 1)
+
+/* Used by RM_WKUP_RSTST */
+#define AM33XX_ICECRUSHER_M3_RST_SHIFT                  7
+#define AM33XX_ICECRUSHER_M3_RST_MASK                   (1 << 7)
+
+/* Used by RM_MPU_RSTST */
+#define AM33XX_ICECRUSHER_MPU_RST_SHIFT                 6
+#define AM33XX_ICECRUSHER_MPU_RST_MASK                  (1 << 6)
+
+/* Used by PRM_RSTST */
+#define AM33XX_ICEPICK_RST_SHIFT                        9
+#define AM33XX_ICEPICK_RST_MASK                         (1 << 9)
+
+/* Used by RM_PER_RSTCTRL */
+#define AM33XX_PRUSS_LRST_SHIFT                         1
+#define AM33XX_PRUSS_LRST_MASK                          (1 << 1)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT                  5
+#define AM33XX_PRUSS_MEM_ONSTATE_MASK                   (0x3 << 5)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT                 7
+#define AM33XX_PRUSS_MEM_RETSTATE_MASK                  (1 << 7)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_PRUSS_MEM_STATEST_SHIFT                  23
+#define AM33XX_PRUSS_MEM_STATEST_MASK                   (0x3 << 23)
+
+/*
+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ */
+#define AM33XX_INTRANSITION_SHIFT                       20
+#define AM33XX_INTRANSITION_MASK                        (1 << 20)
+
+/* Used by PM_CEFUSE_PWRSTST */
+#define AM33XX_LASTPOWERSTATEENTERED_SHIFT              24
+#define AM33XX_LASTPOWERSTATEENTERED_MASK               (0x3 << 24)
+
+/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
+#define AM33XX_LOGICRETSTATE_SHIFT                      2
+#define AM33XX_LOGICRETSTATE_MASK                       (1 << 2)
+
+/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
+#define AM33XX_LOGICRETSTATE_3_3_SHIFT                  3
+#define AM33XX_LOGICRETSTATE_3_3_MASK                   (1 << 3)
+
+/*
+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ */
+#define AM33XX_LOGICSTATEST_SHIFT                       2
+#define AM33XX_LOGICSTATEST_MASK                        (1 << 2)
+
+/*
+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
+ */
+#define AM33XX_LOWPOWERSTATECHANGE_SHIFT                4
+#define AM33XX_LOWPOWERSTATECHANGE_MASK                 (1 << 4)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L1_ONSTATE_SHIFT                     18
+#define AM33XX_MPU_L1_ONSTATE_MASK                      (0x3 << 18)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L1_RETSTATE_SHIFT                    22
+#define AM33XX_MPU_L1_RETSTATE_MASK                     (1 << 22)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_L1_STATEST_SHIFT                     6
+#define AM33XX_MPU_L1_STATEST_MASK                      (0x3 << 6)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L2_ONSTATE_SHIFT                     20
+#define AM33XX_MPU_L2_ONSTATE_MASK                      (0x3 << 20)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L2_RETSTATE_SHIFT                    23
+#define AM33XX_MPU_L2_RETSTATE_MASK                     (1 << 23)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_L2_STATEST_SHIFT                     8
+#define AM33XX_MPU_L2_STATEST_MASK                      (0x3 << 8)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_RAM_ONSTATE_SHIFT                    16
+#define AM33XX_MPU_RAM_ONSTATE_MASK                     (0x3 << 16)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_RAM_RETSTATE_SHIFT                   24
+#define AM33XX_MPU_RAM_RETSTATE_MASK                    (1 << 24)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_RAM_STATEST_SHIFT                    4
+#define AM33XX_MPU_RAM_STATEST_MASK                     (0x3 << 4)
+
+/* Used by PRM_RSTST */
+#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT              2
+#define AM33XX_MPU_SECURITY_VIOL_RST_MASK               (1 << 2)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_PCHARGECNT_VALUE_SHIFT                   0
+#define AM33XX_PCHARGECNT_VALUE_MASK                    (0x3f << 0)
+
+/* Used by RM_PER_RSTCTRL */
+#define AM33XX_PCI_LRST_SHIFT                           0
+#define AM33XX_PCI_LRST_MASK                            (1 << 0)
+
+/* Renamed from PCI_LRST Used by RM_PER_RSTST */
+#define AM33XX_PCI_LRST_5_5_SHIFT                       5
+#define AM33XX_PCI_LRST_5_5_MASK                        (1 << 5)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PER_MEM_ONSTATE_SHIFT                    25
+#define AM33XX_PER_MEM_ONSTATE_MASK                     (0x3 << 25)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PER_MEM_RETSTATE_SHIFT                   29
+#define AM33XX_PER_MEM_RETSTATE_MASK                    (1 << 29)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_PER_MEM_STATEST_SHIFT                    17
+#define AM33XX_PER_MEM_STATEST_MASK                     (0x3 << 17)
+
+/*
+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL
+ */
+#define AM33XX_POWERSTATE_SHIFT                         0
+#define AM33XX_POWERSTATE_MASK                          (0x3 << 0)
+
+/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
+#define AM33XX_POWERSTATEST_SHIFT                       0
+#define AM33XX_POWERSTATEST_MASK                        (0x3 << 0)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_RAM_MEM_ONSTATE_SHIFT                    30
+#define AM33XX_RAM_MEM_ONSTATE_MASK                     (0x3 << 30)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_RAM_MEM_RETSTATE_SHIFT                   27
+#define AM33XX_RAM_MEM_RETSTATE_MASK                    (1 << 27)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_RAM_MEM_STATEST_SHIFT                    21
+#define AM33XX_RAM_MEM_STATEST_MASK                     (0x3 << 21)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_RETMODE_ENABLE_SHIFT                     0
+#define AM33XX_RETMODE_ENABLE_MASK                      (1 << 0)
+
+/* Used by REVISION_PRM */
+#define AM33XX_REV_SHIFT                                0
+#define AM33XX_REV_MASK                                 (0xff << 0)
+
+/* Used by PRM_RSTTIME */
+#define AM33XX_RSTTIME1_SHIFT                           0
+#define AM33XX_RSTTIME1_MASK                            (0xff << 0)
+
+/* Used by PRM_RSTTIME */
+#define AM33XX_RSTTIME2_SHIFT                           8
+#define AM33XX_RSTTIME2_MASK                            (0x1f << 8)
+
+/* Used by PRM_RSTCTRL */
+#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT                 1
+#define AM33XX_RST_GLOBAL_COLD_SW_MASK                  (1 << 1)
+
+/* Used by PRM_RSTCTRL */
+#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT                 0
+#define AM33XX_RST_GLOBAL_WARM_SW_MASK                  (1 << 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_SLPCNT_VALUE_SHIFT                       16
+#define AM33XX_SLPCNT_VALUE_MASK                        (0xff << 16)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_SRAMLDO_STATUS_SHIFT                     8
+#define AM33XX_SRAMLDO_STATUS_MASK                      (1 << 8)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_SRAM_IN_TRANSITION_SHIFT                 9
+#define AM33XX_SRAM_IN_TRANSITION_MASK                  (1 << 9)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_STARTUP_COUNT_SHIFT                      24
+#define AM33XX_STARTUP_COUNT_MASK                       (0xff << 24)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_TRANSITION_EN_SHIFT                      8
+#define AM33XX_TRANSITION_EN_MASK                       (1 << 8)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_TRANSITION_ST_SHIFT                      8
+#define AM33XX_TRANSITION_ST_MASK                       (1 << 8)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_VSETUPCNT_VALUE_SHIFT                    8
+#define AM33XX_VSETUPCNT_VALUE_MASK                     (0xff << 8)
+
+/* Used by PRM_RSTST */
+#define AM33XX_WDT0_RST_SHIFT                           3
+#define AM33XX_WDT0_RST_MASK                            (1 << 3)
+
+/* Used by PRM_RSTST */
+#define AM33XX_WDT1_RST_SHIFT                           4
+#define AM33XX_WDT1_RST_MASK                            (1 << 4)
+
+/* Used by RM_WKUP_RSTCTRL */
+#define AM33XX_WKUP_M3_LRST_SHIFT                       3
+#define AM33XX_WKUP_M3_LRST_MASK                        (1 << 3)
+
+/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
+#define AM33XX_WKUP_M3_LRST_5_5_SHIFT                   5
+#define AM33XX_WKUP_M3_LRST_5_5_MASK                    (1 << 5)
+
+#endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 21cb74003a5..a0309dea679 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -302,11 +302,59 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask)
                                 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 }
 
+/**
+ * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
+ *
+ * Clear any previously-latched I/O wakeup events and ensure that the
+ * I/O wakeup gates are aligned with the current mux settings.  Works
+ * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
+ * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit.  No
+ * return value.
+ */
+void omap3xxx_prm_reconfigure_io_chain(void)
+{
+        int i = 0;
+
+        omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                                   PM_WKEN);
+
+        omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+                          OMAP3430_ST_IO_CHAIN_MASK,
+                          MAX_IOPAD_LATCH_TIME, i);
+        if (i == MAX_IOPAD_LATCH_TIME)
+                pr_warn("PRM: I/O chain clock line assertion timed out\n");
+
+        omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
+                                     PM_WKEN);
+
+        omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
+                                   PM_WKST);
+
+        omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
+}
+
+/**
+ * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+ *
+ * Activates the I/O wakeup event latches and allows events logged by
+ * those latches to signal a wakeup event to the PRCM.  For I/O
+ * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
+ * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
+ * No return value.
+ */
+static void __init omap3xxx_prm_enable_io_wakeup(void)
+{
+        if (omap3_has_io_wakeup())
+                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
+                                           PM_WKEN);
+}
+
 static int __init omap3xxx_prcm_init(void)
 {
         int ret = 0;
 
         if (cpu_is_omap34xx()) {
+                omap3xxx_prm_enable_io_wakeup();
                 ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
                 if (!ret)
                         irq_set_status_flags(omap_prcm_event_to_irq("io"),
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 70ac2a19dc5..c19d249b481 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -228,68 +228,6 @@
 
 
 #ifndef __ASSEMBLER__
-/*
- * Stub omap2xxx/omap3xxx functions so that common files
- * continue to build when custom builds are used
- */
-#if defined(CONFIG_ARCH_OMAP4) && !(defined(CONFIG_ARCH_OMAP2) ||       \
-                                        defined(CONFIG_ARCH_OMAP3))
-static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-                "not suppose to be used on omap4\n");
-        return 0;
-}
-static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-                "not suppose to be used on omap4\n");
-}
-static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
-                s16 module, s16 idx)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-                "not suppose to be used on omap4\n");
-        return 0;
-}
-static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-                "not suppose to be used on omap4\n");
-        return 0;
-}
-static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-                "not suppose to be used on omap4\n");
-        return 0;
-}
-static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-                "not suppose to be used on omap4\n");
-        return 0;
-}
-static inline int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-                "not suppose to be used on omap4\n");
-        return 0;
-}
-static inline int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-                "not suppose to be used on omap4\n");
-        return 0;
-}
-static inline int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
-                                                u8 st_shift)
-{
-        WARN(1, "prm: omap2xxx/omap3xxx specific function and "
-                "not suppose to be used on omap4\n");
-        return 0;
-}
-#else
 /* Power/reset management domain register get/set */
 extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx);
 extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx);
@@ -315,15 +253,15 @@ extern u32 omap3_prm_vcvp_read(u8 offset);
 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 
+extern void omap3xxx_prm_reconfigure_io_chain(void);
+
 /* PRM interrupt-related functions */
 extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
 extern void omap3xxx_prm_ocp_barrier(void);
 extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
 extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 
-#endif  /* CONFIG_ARCH_OMAP4 */
-
-#endif
+#endif /* __ASSEMBLER */
 
 /*
  * Bits common to specific registers
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
new file mode 100644
index 00000000000..e7dbb6cf125
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -0,0 +1,135 @@
+/*
+ * AM33XX PRM functions
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "common.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+/* Read a register in a PRM instance */
+u32 am33xx_prm_read_reg(s16 inst, u16 idx)
+{
+        return __raw_readl(prm_base + inst + idx);
+}
+
+/* Write into a register in a PRM instance */
+void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
+{
+        __raw_writel(val, prm_base + inst + idx);
+}
+
+/* Read-modify-write a register in PRM. Caller must lock */
+u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(inst, idx);
+        v &= ~mask;
+        v |= bits;
+        am33xx_prm_write_reg(v, inst, idx);
+
+        return v;
+}
+
+/**
+ * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @shift: register bit shift corresponding to the reset line to check
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_offs: RM_RSTCTRL register address offset for this module
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL upon parameter error.
+ */
+int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(inst, rstctrl_offs);
+        v &= 1 << shift;
+        v >>= shift;
+
+        return v;
+}
+
+/**
+ * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
+ * @shift: register bit shift corresponding to the reset line to assert
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
+{
+        u32 mask = 1 << shift;
+
+        am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
+
+        return 0;
+}
+
+/**
+ * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
+ * wait
+ * @shift: register bit shift corresponding to the reset line to deassert
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @rstst_reg: RM_RSTST register address for this module
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+                u16 rstctrl_offs, u16 rstst_offs)
+{
+        int c;
+        u32 mask = 1 << shift;
+
+        /* Check the current status to avoid  de-asserting the line twice */
+        if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
+                return -EEXIST;
+
+        /* Clear the reset status by writing 1 to the status bit */
+        am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
+        /* de-assert the reset control line */
+        am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
+        /* wait the status to be set */
+
+        omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
+                                                           rstst_offs),
+                          MAX_MODULE_HARDRESET_WAIT, c);
+
+        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
new file mode 100644
index 00000000000..3f25c563a82
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -0,0 +1,129 @@
+/*
+ * AM33XX PRM instance offset macros
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+
+#define AM33XX_PRM_BASE               0x44E00000
+
+#define AM33XX_PRM_REGADDR(inst, reg)                         \
+        AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define AM33XX_PRM_OCP_SOCKET_MOD       0x0B00
+#define AM33XX_PRM_PER_MOD              0x0C00
+#define AM33XX_PRM_WKUP_MOD             0x0D00
+#define AM33XX_PRM_MPU_MOD              0x0E00
+#define AM33XX_PRM_DEVICE_MOD           0x0F00
+#define AM33XX_PRM_RTC_MOD              0x1000
+#define AM33XX_PRM_GFX_MOD              0x1100
+#define AM33XX_PRM_CEFUSE_MOD           0x1200
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define AM33XX_REVISION_PRM_OFFSET              0x0000
+#define AM33XX_REVISION_PRM                     AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
+#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET         0x0004
+#define AM33XX_PRM_IRQSTATUS_MPU                AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
+#define AM33XX_PRM_IRQENABLE_MPU_OFFSET         0x0008
+#define AM33XX_PRM_IRQENABLE_MPU                AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
+#define AM33XX_PRM_IRQSTATUS_M3_OFFSET          0x000c
+#define AM33XX_PRM_IRQSTATUS_M3                 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
+#define AM33XX_PRM_IRQENABLE_M3_OFFSET          0x0010
+#define AM33XX_PRM_IRQENABLE_M3                 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
+
+/* PRM.PER_PRM register offsets */
+#define AM33XX_RM_PER_RSTCTRL_OFFSET            0x0000
+#define AM33XX_RM_PER_RSTCTRL                   AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
+#define AM33XX_RM_PER_RSTST_OFFSET              0x0004
+#define AM33XX_RM_PER_RSTST                     AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
+#define AM33XX_PM_PER_PWRSTST_OFFSET            0x0008
+#define AM33XX_PM_PER_PWRSTST                   AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
+#define AM33XX_PM_PER_PWRSTCTRL_OFFSET          0x000c
+#define AM33XX_PM_PER_PWRSTCTRL                 AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
+
+/* PRM.WKUP_PRM register offsets */
+#define AM33XX_RM_WKUP_RSTCTRL_OFFSET           0x0000
+#define AM33XX_RM_WKUP_RSTCTRL                  AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
+#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET         0x0004
+#define AM33XX_PM_WKUP_PWRSTCTRL                AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
+#define AM33XX_PM_WKUP_PWRSTST_OFFSET           0x0008
+#define AM33XX_PM_WKUP_PWRSTST                  AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
+#define AM33XX_RM_WKUP_RSTST_OFFSET             0x000c
+#define AM33XX_RM_WKUP_RSTST                    AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
+
+/* PRM.MPU_PRM register offsets */
+#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET          0x0000
+#define AM33XX_PM_MPU_PWRSTCTRL                 AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
+#define AM33XX_PM_MPU_PWRSTST_OFFSET            0x0004
+#define AM33XX_PM_MPU_PWRSTST                   AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
+#define AM33XX_RM_MPU_RSTST_OFFSET              0x0008
+#define AM33XX_RM_MPU_RSTST                     AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
+
+/* PRM.DEVICE_PRM register offsets */
+#define AM33XX_PRM_RSTCTRL_OFFSET               0x0000
+#define AM33XX_PRM_RSTCTRL                      AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
+#define AM33XX_PRM_RSTTIME_OFFSET               0x0004
+#define AM33XX_PRM_RSTTIME                      AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
+#define AM33XX_PRM_RSTST_OFFSET                 0x0008
+#define AM33XX_PRM_RSTST                        AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
+#define AM33XX_PRM_SRAM_COUNT_OFFSET            0x000c
+#define AM33XX_PRM_SRAM_COUNT                   AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET   0x0010
+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP          AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET    0x0014
+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL           AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET    0x0018
+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP           AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET     0x001c
+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL            AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
+
+/* PRM.RTC_PRM register offsets */
+#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET          0x0000
+#define AM33XX_PM_RTC_PWRSTCTRL                 AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
+#define AM33XX_PM_RTC_PWRSTST_OFFSET            0x0004
+#define AM33XX_PM_RTC_PWRSTST                   AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
+
+/* PRM.GFX_PRM register offsets */
+#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET          0x0000
+#define AM33XX_PM_GFX_PWRSTCTRL                 AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
+#define AM33XX_RM_GFX_RSTCTRL_OFFSET            0x0004
+#define AM33XX_RM_GFX_RSTCTRL                   AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
+#define AM33XX_PM_GFX_PWRSTST_OFFSET            0x0010
+#define AM33XX_PM_GFX_PWRSTST                   AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
+#define AM33XX_RM_GFX_RSTST_OFFSET              0x0014
+#define AM33XX_RM_GFX_RSTST                     AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
+
+/* PRM.CEFUSE_PRM register offsets */
+#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET       0x0000
+#define AM33XX_PM_CEFUSE_PWRSTCTRL              AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
+#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET         0x0004
+#define AM33XX_PM_CEFUSE_PWRSTST                AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
+
+extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
+extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
+extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+extern void am33xx_prm_global_warm_sw_reset(void);
+extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
+                u16 rstctrl_offs);
+extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
+extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+                u16 rstctrl_offs, u16 rstst_offs);
+#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index f106d21ff58..bb727c2d933 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -233,10 +233,71 @@ void omap44xx_prm_restore_irqen(u32 *saved_mask)
                                  OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 }
 
+/**
+ * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
+ *
+ * Clear any previously-latched I/O wakeup events and ensure that the
+ * I/O wakeup gates are aligned with the current mux settings.  Works
+ * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
+ * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
+ * No return value. XXX Are the final two steps necessary?
+ */
+void omap44xx_prm_reconfigure_io_chain(void)
+{
+        int i = 0;
+
+        /* Trigger WUCLKIN enable */
+        omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
+                                    OMAP4430_WUCLK_CTRL_MASK,
+                                    OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_PRM_IO_PMCTRL_OFFSET);
+        omap_test_timeout(
+                (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                           OMAP4_PRM_IO_PMCTRL_OFFSET) &
+                   OMAP4430_WUCLK_STATUS_MASK) >>
+                  OMAP4430_WUCLK_STATUS_SHIFT) == 1),
+                MAX_IOPAD_LATCH_TIME, i);
+        if (i == MAX_IOPAD_LATCH_TIME)
+                pr_warn("PRM: I/O chain clock line assertion timed out\n");
+
+        /* Trigger WUCLKIN disable */
+        omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
+                                    OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_PRM_IO_PMCTRL_OFFSET);
+        omap_test_timeout(
+                (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                           OMAP4_PRM_IO_PMCTRL_OFFSET) &
+                   OMAP4430_WUCLK_STATUS_MASK) >>
+                  OMAP4430_WUCLK_STATUS_SHIFT) == 0),
+                MAX_IOPAD_LATCH_TIME, i);
+        if (i == MAX_IOPAD_LATCH_TIME)
+                pr_warn("PRM: I/O chain clock line deassertion timed out\n");
+
+        return;
+}
+
+/**
+ * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
+ *
+ * Activates the I/O wakeup event latches and allows events logged by
+ * those latches to signal a wakeup event to the PRCM.  For I/O wakeups
+ * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
+ * omap44xx_prm_reconfigure_io_chain() must be called.  No return value.
+ */
+static void __init omap44xx_prm_enable_io_wakeup(void)
+{
+        omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
+                                    OMAP4430_GLOBAL_WUEN_MASK,
+                                    OMAP4430_PRM_DEVICE_INST,
+                                    OMAP4_PRM_IO_PMCTRL_OFFSET);
+}
+
 static int __init omap4xxx_prcm_init(void)
 {
-        if (cpu_is_omap44xx())
+        if (cpu_is_omap44xx()) {
+                omap44xx_prm_enable_io_wakeup();
                 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+        }
         return 0;
 }
 subsys_initcall(omap4xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 7978092946d..ee72ae6bd8c 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -763,6 +763,8 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
 
+extern void omap44xx_prm_reconfigure_io_chain(void);
+
 /* PRM interrupt-related functions */
 extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
 extern void omap44xx_prm_ocp_barrier(void);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index dfe00ddb5c6..03b126d9ad9 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -85,7 +85,7 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
         unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
         struct irq_chip *chip = irq_desc_get_chip(desc);
         unsigned int virtirq;
-        int nr_irqs = prcm_irq_setup->nr_regs * 32;
+        int nr_irq = prcm_irq_setup->nr_regs * 32;
 
         /*
          * If we are suspended, mask all interrupts from PRCM level,
@@ -110,7 +110,7 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
                 prcm_irq_setup->read_pending_irqs(pending);
 
                 /* No bit set, then all IRQs are handled */
-                if (find_first_bit(pending, nr_irqs) >= nr_irqs)
+                if (find_first_bit(pending, nr_irq) >= nr_irq)
                         break;
 
                 omap_prcm_events_filter_priority(pending, priority_pending);
@@ -121,11 +121,11 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
                  */
 
                 /* Serve priority events first */
-                for_each_set_bit(virtirq, priority_pending, nr_irqs)
+                for_each_set_bit(virtirq, priority_pending, nr_irq)
                         generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
 
                 /* Serve normal events next */
-                for_each_set_bit(virtirq, pending, nr_irqs)
+                for_each_set_bit(virtirq, pending, nr_irq)
                         generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
         }
         if (chip->irq_ack)
@@ -319,3 +319,65 @@ err:
         omap_prcm_irq_cleanup();
         return -ENOMEM;
 }
+
+/*
+ * Stubbed functions so that common files continue to build when
+ * custom builds are used
+ * XXX These are temporary and should be removed at the earliest possible
+ * opportunity
+ */
+u32 __weak omap2_prm_read_mod_reg(s16 module, u16 idx)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        return 0;
+}
+
+void __weak omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+}
+
+u32 __weak omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits,
+                s16 module, s16 idx)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        return 0;
+}
+
+u32 __weak omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        return 0;
+}
+
+u32 __weak omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        return 0;
+}
+
+u32 __weak omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        return 0;
+}
+
+int __weak omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        return 0;
+}
+
+int __weak omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        return 0;
+}
+
+int __weak omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift,
+                                                u8 st_shift)
+{
+        WARN(1, "prm: omap2xxx/omap3xxx specific function called on non-omap2xxx/3xxx\n");
+        return 0;
+}
+
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
index 9f6b83d1b19..91e71d8f46f 100644
--- a/arch/arm/mach-omap2/sleep44xx.S
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -56,9 +56,13 @@ ppa_por_params:
  * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
  * It returns to the caller for CPU INACTIVE and ON power states or in case
  * CPU failed to transition to targeted OFF/DORMANT state.
+ *
+ * omap4_finish_suspend() calls v7_flush_dcache_all() which doesn't save
+ * stack frame and it expects the caller to take care of it. Hence the entire
+ * stack frame is saved to avoid possible stack corruption.
  */
 ENTRY(omap4_finish_suspend)
-        stmfd   sp!, {lr}
+        stmfd   sp!, {r4-r12, lr}
         cmp     r0, #0x0
         beq     do_WFI                          @ No lowpower state, jump to WFI
 
@@ -226,7 +230,7 @@ scu_gp_clear:
 skip_scu_gp_clear:
         isb
         dsb
-        ldmfd   sp!, {pc}
+        ldmfd   sp!, {r4-r12, pc}
 ENDPROC(omap4_finish_suspend)
 
 /*
diff --git a/arch/arm/mach-omap2/smartreflex-class3.c b/arch/arm/mach-omap2/smartreflex-class3.c
index 955566eefac..1da8f03c479 100644
--- a/arch/arm/mach-omap2/smartreflex-class3.c
+++ b/arch/arm/mach-omap2/smartreflex-class3.c
@@ -11,36 +11,37 @@
  * published by the Free Software Foundation.
  */
 
-#include "smartreflex.h"
+#include <linux/power/smartreflex.h>
+#include "voltage.h"
 
-static int sr_class3_enable(struct voltagedomain *voltdm)
+static int sr_class3_enable(struct omap_sr *sr)
 {
-        unsigned long volt = voltdm_get_voltage(voltdm);
+        unsigned long volt = voltdm_get_voltage(sr->voltdm);
 
         if (!volt) {
-                pr_warning("%s: Curr voltage unknown. Cannot enable sr_%s\n",
-                                __func__, voltdm->name);
+                pr_warning("%s: Curr voltage unknown. Cannot enable %s\n",
+                                __func__, sr->name);
                 return -ENODATA;
         }
 
-        omap_vp_enable(voltdm);
-        return sr_enable(voltdm, volt);
+        omap_vp_enable(sr->voltdm);
+        return sr_enable(sr->voltdm, volt);
 }
 
-static int sr_class3_disable(struct voltagedomain *voltdm, int is_volt_reset)
+static int sr_class3_disable(struct omap_sr *sr, int is_volt_reset)
 {
-        sr_disable_errgen(voltdm);
-        omap_vp_disable(voltdm);
-        sr_disable(voltdm);
+        sr_disable_errgen(sr->voltdm);
+        omap_vp_disable(sr->voltdm);
+        sr_disable(sr->voltdm);
         if (is_volt_reset)
-                voltdm_reset(voltdm);
+                voltdm_reset(sr->voltdm);
 
         return 0;
 }
 
-static int sr_class3_configure(struct voltagedomain *voltdm)
+static int sr_class3_configure(struct omap_sr *sr)
 {
-        return sr_configure_errgen(voltdm);
+        return sr_configure_errgen(sr->voltdm);
 }
 
 /* SR class3 structure */
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
deleted file mode 100644
index 008fbd7b935..00000000000
--- a/arch/arm/mach-omap2/smartreflex.c
+++ /dev/null
@@ -1,1165 +0,0 @@
-/*
- * OMAP SmartReflex Voltage Control
- *
- * Author: Thara Gopinath       <thara@ti.com>
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Thara Gopinath <thara@ti.com>
- *
- * Copyright (C) 2008 Nokia Corporation
- * Kalle Jokiniemi
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Lesly A M <x0080970@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/pm_runtime.h>
-
-#include "common.h"
-
-#include "pm.h"
-#include "smartreflex.h"
-
-#define SMARTREFLEX_NAME_LEN    16
-#define NVALUE_NAME_LEN         40
-#define SR_DISABLE_TIMEOUT      200
-
-struct omap_sr {
-        struct list_head                node;
-        struct platform_device          *pdev;
-        struct omap_sr_nvalue_table     *nvalue_table;
-        struct voltagedomain            *voltdm;
-        struct dentry                   *dbg_dir;
-        unsigned int                    irq;
-        int                             srid;
-        int                             ip_type;
-        int                             nvalue_count;
-        bool                            autocomp_active;
-        u32                             clk_length;
-        u32                             err_weight;
-        u32                             err_minlimit;
-        u32                             err_maxlimit;
-        u32                             accum_data;
-        u32                             senn_avgweight;
-        u32                             senp_avgweight;
-        u32                             senp_mod;
-        u32                             senn_mod;
-        void __iomem                    *base;
-};
-
-/* sr_list contains all the instances of smartreflex module */
-static LIST_HEAD(sr_list);
-
-static struct omap_sr_class_data *sr_class;
-static struct omap_sr_pmic_data *sr_pmic_data;
-static struct dentry            *sr_dbg_dir;
-
-static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
-{
-        __raw_writel(value, (sr->base + offset));
-}
-
-static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
-                                        u32 value)
-{
-        u32 reg_val;
-
-        /*
-         * Smartreflex error config register is special as it contains
-         * certain status bits which if written a 1 into means a clear
-         * of those bits. So in order to make sure no accidental write of
-         * 1 happens to those status bits, do a clear of them in the read
-         * value. This mean this API doesn't rewrite values in these bits
-         * if they are currently set, but does allow the caller to write
-         * those bits.
-         */
-        if (sr->ip_type == SR_TYPE_V1 && offset == ERRCONFIG_V1)
-                mask |= ERRCONFIG_STATUS_V1_MASK;
-        else if (sr->ip_type == SR_TYPE_V2 && offset == ERRCONFIG_V2)
-                mask |= ERRCONFIG_VPBOUNDINTST_V2;
-
-        reg_val = __raw_readl(sr->base + offset);
-        reg_val &= ~mask;
-
-        value &= mask;
-
-        reg_val |= value;
-
-        __raw_writel(reg_val, (sr->base + offset));
-}
-
-static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
-{
-        return __raw_readl(sr->base + offset);
-}
-
-static struct omap_sr *_sr_lookup(struct voltagedomain *voltdm)
-{
-        struct omap_sr *sr_info;
-
-        if (!voltdm) {
-                pr_err("%s: Null voltage domain passed!\n", __func__);
-                return ERR_PTR(-EINVAL);
-        }
-
-        list_for_each_entry(sr_info, &sr_list, node) {
-                if (voltdm == sr_info->voltdm)
-                        return sr_info;
-        }
-
-        return ERR_PTR(-ENODATA);
-}
-
-static irqreturn_t sr_interrupt(int irq, void *data)
-{
-        struct omap_sr *sr_info = data;
-        u32 status = 0;
-
-        switch (sr_info->ip_type) {
-        case SR_TYPE_V1:
-                /* Read the status bits */
-                status = sr_read_reg(sr_info, ERRCONFIG_V1);
-
-                /* Clear them by writing back */
-                sr_write_reg(sr_info, ERRCONFIG_V1, status);
-                break;
-        case SR_TYPE_V2:
-                /* Read the status bits */
-                status = sr_read_reg(sr_info, IRQSTATUS);
-
-                /* Clear them by writing back */
-                sr_write_reg(sr_info, IRQSTATUS, status);
-                break;
-        default:
-                dev_err(&sr_info->pdev->dev, "UNKNOWN IP type %d\n",
-                        sr_info->ip_type);
-                return IRQ_NONE;
-        }
-
-        if (sr_class->notify)
-                sr_class->notify(sr_info->voltdm, status);
-
-        return IRQ_HANDLED;
-}
-
-static void sr_set_clk_length(struct omap_sr *sr)
-{
-        struct clk *sys_ck;
-        u32 sys_clk_speed;
-
-        if (cpu_is_omap34xx())
-                sys_ck = clk_get(NULL, "sys_ck");
-        else
-                sys_ck = clk_get(NULL, "sys_clkin_ck");
-
-        if (IS_ERR(sys_ck)) {
-                dev_err(&sr->pdev->dev, "%s: unable to get sys clk\n",
-                        __func__);
-                return;
-        }
-
-        sys_clk_speed = clk_get_rate(sys_ck);
-        clk_put(sys_ck);
-
-        switch (sys_clk_speed) {
-        case 12000000:
-                sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
-                break;
-        case 13000000:
-                sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
-                break;
-        case 19200000:
-                sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
-                break;
-        case 26000000:
-                sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
-                break;
-        case 38400000:
-                sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
-                break;
-        default:
-                dev_err(&sr->pdev->dev, "%s: Invalid sysclk value: %d\n",
-                        __func__, sys_clk_speed);
-                break;
-        }
-}
-
-static void sr_set_regfields(struct omap_sr *sr)
-{
-        /*
-         * For time being these values are defined in smartreflex.h
-         * and populated during init. May be they can be moved to board
-         * file or pmic specific data structure. In that case these structure
-         * fields will have to be populated using the pdata or pmic structure.
-         */
-        if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                sr->err_weight = OMAP3430_SR_ERRWEIGHT;
-                sr->err_maxlimit = OMAP3430_SR_ERRMAXLIMIT;
-                sr->accum_data = OMAP3430_SR_ACCUMDATA;
-                if (!(strcmp(sr->voltdm->name, "mpu"))) {
-                        sr->senn_avgweight = OMAP3430_SR1_SENNAVGWEIGHT;
-                        sr->senp_avgweight = OMAP3430_SR1_SENPAVGWEIGHT;
-                } else {
-                        sr->senn_avgweight = OMAP3430_SR2_SENNAVGWEIGHT;
-                        sr->senp_avgweight = OMAP3430_SR2_SENPAVGWEIGHT;
-                }
-        }
-}
-
-static void sr_start_vddautocomp(struct omap_sr *sr)
-{
-        if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
-                dev_warn(&sr->pdev->dev,
-                        "%s: smartreflex class driver not registered\n",
-                        __func__);
-                return;
-        }
-
-        if (!sr_class->enable(sr->voltdm))
-                sr->autocomp_active = true;
-}
-
-static void sr_stop_vddautocomp(struct omap_sr *sr)
-{
-        if (!sr_class || !(sr_class->disable)) {
-                dev_warn(&sr->pdev->dev,
-                        "%s: smartreflex class driver not registered\n",
-                        __func__);
-                return;
-        }
-
-        if (sr->autocomp_active) {
-                sr_class->disable(sr->voltdm, 1);
-                sr->autocomp_active = false;
-        }
-}
-
-/*
- * This function handles the intializations which have to be done
- * only when both sr device and class driver regiter has
- * completed. This will be attempted to be called from both sr class
- * driver register and sr device intializtion API's. Only one call
- * will ultimately succeed.
- *
- * Currently this function registers interrupt handler for a particular SR
- * if smartreflex class driver is already registered and has
- * requested for interrupts and the SR interrupt line in present.
- */
-static int sr_late_init(struct omap_sr *sr_info)
-{
-        char *name;
-        struct omap_sr_data *pdata = sr_info->pdev->dev.platform_data;
-        struct resource *mem;
-        int ret = 0;
-
-        if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
-                name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
-                if (name == NULL) {
-                        ret = -ENOMEM;
-                        goto error;
-                }
-                ret = request_irq(sr_info->irq, sr_interrupt,
-                                0, name, sr_info);
-                if (ret)
-                        goto error;
-                disable_irq(sr_info->irq);
-        }
-
-        if (pdata && pdata->enable_on_init)
-                sr_start_vddautocomp(sr_info);
-
-        return ret;
-
-error:
-        iounmap(sr_info->base);
-        mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
-        release_mem_region(mem->start, resource_size(mem));
-        list_del(&sr_info->node);
-        dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
-                "interrupt handler. Smartreflex will"
-                "not function as desired\n", __func__);
-        kfree(name);
-        kfree(sr_info);
-
-        return ret;
-}
-
-static void sr_v1_disable(struct omap_sr *sr)
-{
-        int timeout = 0;
-        int errconf_val = ERRCONFIG_MCUACCUMINTST | ERRCONFIG_MCUVALIDINTST |
-                        ERRCONFIG_MCUBOUNDINTST;
-
-        /* Enable MCUDisableAcknowledge interrupt */
-        sr_modify_reg(sr, ERRCONFIG_V1,
-                        ERRCONFIG_MCUDISACKINTEN, ERRCONFIG_MCUDISACKINTEN);
-
-        /* SRCONFIG - disable SR */
-        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
-
-        /* Disable all other SR interrupts and clear the status as needed */
-        if (sr_read_reg(sr, ERRCONFIG_V1) & ERRCONFIG_VPBOUNDINTST_V1)
-                errconf_val |= ERRCONFIG_VPBOUNDINTST_V1;
-        sr_modify_reg(sr, ERRCONFIG_V1,
-                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
-                        ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_VPBOUNDINTEN_V1),
-                        errconf_val);
-
-        /*
-         * Wait for SR to be disabled.
-         * wait until ERRCONFIG.MCUDISACKINTST = 1. Typical latency is 1us.
-         */
-        omap_test_timeout((sr_read_reg(sr, ERRCONFIG_V1) &
-                        ERRCONFIG_MCUDISACKINTST), SR_DISABLE_TIMEOUT,
-                        timeout);
-
-        if (timeout >= SR_DISABLE_TIMEOUT)
-                dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
-                        __func__);
-
-        /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
-        sr_modify_reg(sr, ERRCONFIG_V1, ERRCONFIG_MCUDISACKINTEN,
-                        ERRCONFIG_MCUDISACKINTST);
-}
-
-static void sr_v2_disable(struct omap_sr *sr)
-{
-        int timeout = 0;
-
-        /* Enable MCUDisableAcknowledge interrupt */
-        sr_write_reg(sr, IRQENABLE_SET, IRQENABLE_MCUDISABLEACKINT);
-
-        /* SRCONFIG - disable SR */
-        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, 0x0);
-
-        /*
-         * Disable all other SR interrupts and clear the status
-         * write to status register ONLY on need basis - only if status
-         * is set.
-         */
-        if (sr_read_reg(sr, ERRCONFIG_V2) & ERRCONFIG_VPBOUNDINTST_V2)
-                sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
-                        ERRCONFIG_VPBOUNDINTST_V2);
-        else
-                sr_modify_reg(sr, ERRCONFIG_V2, ERRCONFIG_VPBOUNDINTEN_V2,
-                                0x0);
-        sr_write_reg(sr, IRQENABLE_CLR, (IRQENABLE_MCUACCUMINT |
-                        IRQENABLE_MCUVALIDINT |
-                        IRQENABLE_MCUBOUNDSINT));
-        sr_write_reg(sr, IRQSTATUS, (IRQSTATUS_MCUACCUMINT |
-                        IRQSTATUS_MCVALIDINT |
-                        IRQSTATUS_MCBOUNDSINT));
-
-        /*
-         * Wait for SR to be disabled.
-         * wait until IRQSTATUS.MCUDISACKINTST = 1. Typical latency is 1us.
-         */
-        omap_test_timeout((sr_read_reg(sr, IRQSTATUS) &
-                        IRQSTATUS_MCUDISABLEACKINT), SR_DISABLE_TIMEOUT,
-                        timeout);
-
-        if (timeout >= SR_DISABLE_TIMEOUT)
-                dev_warn(&sr->pdev->dev, "%s: Smartreflex disable timedout\n",
-                        __func__);
-
-        /* Disable MCUDisableAcknowledge interrupt & clear pending interrupt */
-        sr_write_reg(sr, IRQENABLE_CLR, IRQENABLE_MCUDISABLEACKINT);
-        sr_write_reg(sr, IRQSTATUS, IRQSTATUS_MCUDISABLEACKINT);
-}
-
-static u32 sr_retrieve_nvalue(struct omap_sr *sr, u32 efuse_offs)
-{
-        int i;
-
-        if (!sr->nvalue_table) {
-                dev_warn(&sr->pdev->dev, "%s: Missing ntarget value table\n",
-                        __func__);
-                return 0;
-        }
-
-        for (i = 0; i < sr->nvalue_count; i++) {
-                if (sr->nvalue_table[i].efuse_offs == efuse_offs)
-                        return sr->nvalue_table[i].nvalue;
-        }
-
-        return 0;
-}
-
-/* Public Functions */
-
-/**
- * sr_configure_errgen() - Configures the smrtreflex to perform AVS using the
- *                       error generator module.
- * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * configure the error generator module inside the smartreflex module.
- * SR settings if using the ERROR module inside Smartreflex.
- * SR CLASS 3 by default uses only the ERROR module where as
- * SR CLASS 2 can choose between ERROR module and MINMAXAVG
- * module. Returns 0 on success and error value in case of failure.
- */
-int sr_configure_errgen(struct voltagedomain *voltdm)
-{
-        u32 sr_config, sr_errconfig, errconfig_offs;
-        u32 vpboundint_en, vpboundint_st;
-        u32 senp_en = 0, senn_en = 0;
-        u8 senp_shift, senn_shift;
-        struct omap_sr *sr = _sr_lookup(voltdm);
-
-        if (IS_ERR(sr)) {
-                pr_warning("%s: omap_sr struct for sr_%s not found\n",
-                        __func__, voltdm->name);
-                return PTR_ERR(sr);
-        }
-
-        if (!sr->clk_length)
-                sr_set_clk_length(sr);
-
-        senp_en = sr->senp_mod;
-        senn_en = sr->senn_mod;
-
-        sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-                SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN;
-
-        switch (sr->ip_type) {
-        case SR_TYPE_V1:
-                sr_config |= SRCONFIG_DELAYCTRL;
-                senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
-                senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
-                errconfig_offs = ERRCONFIG_V1;
-                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
-                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
-                break;
-        case SR_TYPE_V2:
-                senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
-                senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
-                errconfig_offs = ERRCONFIG_V2;
-                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
-                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
-                break;
-        default:
-                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-                        "module without specifying the ip\n", __func__);
-                return -EINVAL;
-        }
-
-        sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
-        sr_write_reg(sr, SRCONFIG, sr_config);
-        sr_errconfig = (sr->err_weight << ERRCONFIG_ERRWEIGHT_SHIFT) |
-                (sr->err_maxlimit << ERRCONFIG_ERRMAXLIMIT_SHIFT) |
-                (sr->err_minlimit <<  ERRCONFIG_ERRMINLIMIT_SHIFT);
-        sr_modify_reg(sr, errconfig_offs, (SR_ERRWEIGHT_MASK |
-                SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
-                sr_errconfig);
-
-        /* Enabling the interrupts if the ERROR module is used */
-        sr_modify_reg(sr, errconfig_offs, (vpboundint_en | vpboundint_st),
-                      vpboundint_en);
-
-        return 0;
-}
-
-/**
- * sr_disable_errgen() - Disables SmartReflex AVS module's errgen component
- * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * disable the error generator module inside the smartreflex module.
- *
- * Returns 0 on success and error value in case of failure.
- */
-int sr_disable_errgen(struct voltagedomain *voltdm)
-{
-        u32 errconfig_offs;
-        u32 vpboundint_en, vpboundint_st;
-        struct omap_sr *sr = _sr_lookup(voltdm);
-
-        if (IS_ERR(sr)) {
-                pr_warning("%s: omap_sr struct for sr_%s not found\n",
-                        __func__, voltdm->name);
-                return PTR_ERR(sr);
-        }
-
-        switch (sr->ip_type) {
-        case SR_TYPE_V1:
-                errconfig_offs = ERRCONFIG_V1;
-                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V1;
-                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V1;
-                break;
-        case SR_TYPE_V2:
-                errconfig_offs = ERRCONFIG_V2;
-                vpboundint_en = ERRCONFIG_VPBOUNDINTEN_V2;
-                vpboundint_st = ERRCONFIG_VPBOUNDINTST_V2;
-                break;
-        default:
-                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-                        "module without specifying the ip\n", __func__);
-                return -EINVAL;
-        }
-
-        /* Disable the interrupts of ERROR module */
-        sr_modify_reg(sr, errconfig_offs, vpboundint_en | vpboundint_st, 0);
-
-        /* Disable the Sensor and errorgen */
-        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN, 0);
-
-        return 0;
-}
-
-/**
- * sr_configure_minmax() - Configures the smrtreflex to perform AVS using the
- *                       minmaxavg module.
- * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * configure the minmaxavg module inside the smartreflex module.
- * SR settings if using the ERROR module inside Smartreflex.
- * SR CLASS 3 by default uses only the ERROR module where as
- * SR CLASS 2 can choose between ERROR module and MINMAXAVG
- * module. Returns 0 on success and error value in case of failure.
- */
-int sr_configure_minmax(struct voltagedomain *voltdm)
-{
-        u32 sr_config, sr_avgwt;
-        u32 senp_en = 0, senn_en = 0;
-        u8 senp_shift, senn_shift;
-        struct omap_sr *sr = _sr_lookup(voltdm);
-
-        if (IS_ERR(sr)) {
-                pr_warning("%s: omap_sr struct for sr_%s not found\n",
-                        __func__, voltdm->name);
-                return PTR_ERR(sr);
-        }
-
-        if (!sr->clk_length)
-                sr_set_clk_length(sr);
-
-        senp_en = sr->senp_mod;
-        senn_en = sr->senn_mod;
-
-        sr_config = (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
-                SRCONFIG_SENENABLE |
-                (sr->accum_data << SRCONFIG_ACCUMDATA_SHIFT);
-
-        switch (sr->ip_type) {
-        case SR_TYPE_V1:
-                sr_config |= SRCONFIG_DELAYCTRL;
-                senn_shift = SRCONFIG_SENNENABLE_V1_SHIFT;
-                senp_shift = SRCONFIG_SENPENABLE_V1_SHIFT;
-                break;
-        case SR_TYPE_V2:
-                senn_shift = SRCONFIG_SENNENABLE_V2_SHIFT;
-                senp_shift = SRCONFIG_SENPENABLE_V2_SHIFT;
-                break;
-        default:
-                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-                        "module without specifying the ip\n", __func__);
-                return -EINVAL;
-        }
-
-        sr_config |= ((senn_en << senn_shift) | (senp_en << senp_shift));
-        sr_write_reg(sr, SRCONFIG, sr_config);
-        sr_avgwt = (sr->senp_avgweight << AVGWEIGHT_SENPAVGWEIGHT_SHIFT) |
-                (sr->senn_avgweight << AVGWEIGHT_SENNAVGWEIGHT_SHIFT);
-        sr_write_reg(sr, AVGWEIGHT, sr_avgwt);
-
-        /*
-         * Enabling the interrupts if MINMAXAVG module is used.
-         * TODO: check if all the interrupts are mandatory
-         */
-        switch (sr->ip_type) {
-        case SR_TYPE_V1:
-                sr_modify_reg(sr, ERRCONFIG_V1,
-                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUVALIDINTEN |
-                        ERRCONFIG_MCUBOUNDINTEN),
-                        (ERRCONFIG_MCUACCUMINTEN | ERRCONFIG_MCUACCUMINTST |
-                         ERRCONFIG_MCUVALIDINTEN | ERRCONFIG_MCUVALIDINTST |
-                         ERRCONFIG_MCUBOUNDINTEN | ERRCONFIG_MCUBOUNDINTST));
-                break;
-        case SR_TYPE_V2:
-                sr_write_reg(sr, IRQSTATUS,
-                        IRQSTATUS_MCUACCUMINT | IRQSTATUS_MCVALIDINT |
-                        IRQSTATUS_MCBOUNDSINT | IRQSTATUS_MCUDISABLEACKINT);
-                sr_write_reg(sr, IRQENABLE_SET,
-                        IRQENABLE_MCUACCUMINT | IRQENABLE_MCUVALIDINT |
-                        IRQENABLE_MCUBOUNDSINT | IRQENABLE_MCUDISABLEACKINT);
-                break;
-        default:
-                dev_err(&sr->pdev->dev, "%s: Trying to Configure smartreflex"
-                        "module without specifying the ip\n", __func__);
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-/**
- * sr_enable() - Enables the smartreflex module.
- * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
- * @volt:       The voltage at which the Voltage domain associated with
- *              the smartreflex module is operating at.
- *              This is required only to program the correct Ntarget value.
- *
- * This API is to be called from the smartreflex class driver to
- * enable a smartreflex module. Returns 0 on success. Returns error
- * value if the voltage passed is wrong or if ntarget value is wrong.
- */
-int sr_enable(struct voltagedomain *voltdm, unsigned long volt)
-{
-        struct omap_volt_data *volt_data;
-        struct omap_sr *sr = _sr_lookup(voltdm);
-        u32 nvalue_reciprocal;
-        int ret;
-
-        if (IS_ERR(sr)) {
-                pr_warning("%s: omap_sr struct for sr_%s not found\n",
-                        __func__, voltdm->name);
-                return PTR_ERR(sr);
-        }
-
-        volt_data = omap_voltage_get_voltdata(sr->voltdm, volt);
-
-        if (IS_ERR(volt_data)) {
-                dev_warn(&sr->pdev->dev, "%s: Unable to get voltage table"
-                        "for nominal voltage %ld\n", __func__, volt);
-                return PTR_ERR(volt_data);
-        }
-
-        nvalue_reciprocal = sr_retrieve_nvalue(sr, volt_data->sr_efuse_offs);
-
-        if (!nvalue_reciprocal) {
-                dev_warn(&sr->pdev->dev, "%s: NVALUE = 0 at voltage %ld\n",
-                        __func__, volt);
-                return -ENODATA;
-        }
-
-        /* errminlimit is opp dependent and hence linked to voltage */
-        sr->err_minlimit = volt_data->sr_errminlimit;
-
-        pm_runtime_get_sync(&sr->pdev->dev);
-
-        /* Check if SR is already enabled. If yes do nothing */
-        if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE)
-                return 0;
-
-        /* Configure SR */
-        ret = sr_class->configure(voltdm);
-        if (ret)
-                return ret;
-
-        sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
-
-        /* SRCONFIG - enable SR */
-        sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
-        return 0;
-}
-
-/**
- * sr_disable() - Disables the smartreflex module.
- * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the smartreflex class driver to
- * disable a smartreflex module.
- */
-void sr_disable(struct voltagedomain *voltdm)
-{
-        struct omap_sr *sr = _sr_lookup(voltdm);
-
-        if (IS_ERR(sr)) {
-                pr_warning("%s: omap_sr struct for sr_%s not found\n",
-                        __func__, voltdm->name);
-                return;
-        }
-
-        /* Check if SR clocks are already disabled. If yes do nothing */
-        if (pm_runtime_suspended(&sr->pdev->dev))
-                return;
-
-        /*
-         * Disable SR if only it is indeed enabled. Else just
-         * disable the clocks.
-         */
-        if (sr_read_reg(sr, SRCONFIG) & SRCONFIG_SRENABLE) {
-                switch (sr->ip_type) {
-                case SR_TYPE_V1:
-                        sr_v1_disable(sr);
-                        break;
-                case SR_TYPE_V2:
-                        sr_v2_disable(sr);
-                        break;
-                default:
-                        dev_err(&sr->pdev->dev, "UNKNOWN IP type %d\n",
-                                sr->ip_type);
-                }
-        }
-
-        pm_runtime_put_sync_suspend(&sr->pdev->dev);
-}
-
-/**
- * sr_register_class() - API to register a smartreflex class parameters.
- * @class_data: The structure containing various sr class specific data.
- *
- * This API is to be called by the smartreflex class driver to register itself
- * with the smartreflex driver during init. Returns 0 on success else the
- * error value.
- */
-int sr_register_class(struct omap_sr_class_data *class_data)
-{
-        struct omap_sr *sr_info;
-
-        if (!class_data) {
-                pr_warning("%s:, Smartreflex class data passed is NULL\n",
-                        __func__);
-                return -EINVAL;
-        }
-
-        if (sr_class) {
-                pr_warning("%s: Smartreflex class driver already registered\n",
-                        __func__);
-                return -EBUSY;
-        }
-
-        sr_class = class_data;
-
-        /*
-         * Call into late init to do intializations that require
-         * both sr driver and sr class driver to be initiallized.
-         */
-        list_for_each_entry(sr_info, &sr_list, node)
-                sr_late_init(sr_info);
-
-        return 0;
-}
-
-/**
- * omap_sr_enable() -  API to enable SR clocks and to call into the
- *                      registered smartreflex class enable API.
- * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to enable
- * a particular smartreflex module. This API will do the initial
- * configurations to turn on the smartreflex module and in turn call
- * into the registered smartreflex class enable API.
- */
-void omap_sr_enable(struct voltagedomain *voltdm)
-{
-        struct omap_sr *sr = _sr_lookup(voltdm);
-
-        if (IS_ERR(sr)) {
-                pr_warning("%s: omap_sr struct for sr_%s not found\n",
-                        __func__, voltdm->name);
-                return;
-        }
-
-        if (!sr->autocomp_active)
-                return;
-
-        if (!sr_class || !(sr_class->enable) || !(sr_class->configure)) {
-                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
-                        "registered\n", __func__);
-                return;
-        }
-
-        sr_class->enable(voltdm);
-}
-
-/**
- * omap_sr_disable() - API to disable SR without resetting the voltage
- *                      processor voltage
- * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to disable
- * a particular smartreflex module. This API will in turn call
- * into the registered smartreflex class disable API. This API will tell
- * the smartreflex class disable not to reset the VP voltage after
- * disabling smartreflex.
- */
-void omap_sr_disable(struct voltagedomain *voltdm)
-{
-        struct omap_sr *sr = _sr_lookup(voltdm);
-
-        if (IS_ERR(sr)) {
-                pr_warning("%s: omap_sr struct for sr_%s not found\n",
-                        __func__, voltdm->name);
-                return;
-        }
-
-        if (!sr->autocomp_active)
-                return;
-
-        if (!sr_class || !(sr_class->disable)) {
-                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
-                        "registered\n", __func__);
-                return;
-        }
-
-        sr_class->disable(voltdm, 0);
-}
-
-/**
- * omap_sr_disable_reset_volt() - API to disable SR and reset the
- *                              voltage processor voltage
- * @voltdm:     VDD pointer to which the SR module to be configured belongs to.
- *
- * This API is to be called from the kernel in order to disable
- * a particular smartreflex module. This API will in turn call
- * into the registered smartreflex class disable API. This API will tell
- * the smartreflex class disable to reset the VP voltage after
- * disabling smartreflex.
- */
-void omap_sr_disable_reset_volt(struct voltagedomain *voltdm)
-{
-        struct omap_sr *sr = _sr_lookup(voltdm);
-
-        if (IS_ERR(sr)) {
-                pr_warning("%s: omap_sr struct for sr_%s not found\n",
-                        __func__, voltdm->name);
-                return;
-        }
-
-        if (!sr->autocomp_active)
-                return;
-
-        if (!sr_class || !(sr_class->disable)) {
-                dev_warn(&sr->pdev->dev, "%s: smartreflex class driver not"
-                        "registered\n", __func__);
-                return;
-        }
-
-        sr_class->disable(voltdm, 1);
-}
-
-/**
- * omap_sr_register_pmic() - API to register pmic specific info.
- * @pmic_data:  The structure containing pmic specific data.
- *
- * This API is to be called from the PMIC specific code to register with
- * smartreflex driver pmic specific info. Currently the only info required
- * is the smartreflex init on the PMIC side.
- */
-void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data)
-{
-        if (!pmic_data) {
-                pr_warning("%s: Trying to register NULL PMIC data structure"
-                        "with smartreflex\n", __func__);
-                return;
-        }
-
-        sr_pmic_data = pmic_data;
-}
-
-/* PM Debug FS entries to enable and disable smartreflex. */
-static int omap_sr_autocomp_show(void *data, u64 *val)
-{
-        struct omap_sr *sr_info = data;
-
-        if (!sr_info) {
-                pr_warning("%s: omap_sr struct not found\n", __func__);
-                return -EINVAL;
-        }
-
-        *val = sr_info->autocomp_active;
-
-        return 0;
-}
-
-static int omap_sr_autocomp_store(void *data, u64 val)
-{
-        struct omap_sr *sr_info = data;
-
-        if (!sr_info) {
-                pr_warning("%s: omap_sr struct not found\n", __func__);
-                return -EINVAL;
-        }
-
-        /* Sanity check */
-        if (val > 1) {
-                pr_warning("%s: Invalid argument %lld\n", __func__, val);
-                return -EINVAL;
-        }
-
-        /* control enable/disable only if there is a delta in value */
-        if (sr_info->autocomp_active != val) {
-                if (!val)
-                        sr_stop_vddautocomp(sr_info);
-                else
-                        sr_start_vddautocomp(sr_info);
-        }
-
-        return 0;
-}
-
-DEFINE_SIMPLE_ATTRIBUTE(pm_sr_fops, omap_sr_autocomp_show,
-                        omap_sr_autocomp_store, "%llu\n");
-
-static int __init omap_sr_probe(struct platform_device *pdev)
-{
-        struct omap_sr *sr_info;
-        struct omap_sr_data *pdata = pdev->dev.platform_data;
-        struct resource *mem, *irq;
-        struct dentry *nvalue_dir;
-        struct omap_volt_data *volt_data;
-        int i, ret = 0;
-        char *name;
-
-        sr_info = kzalloc(sizeof(struct omap_sr), GFP_KERNEL);
-        if (!sr_info) {
-                dev_err(&pdev->dev, "%s: unable to allocate sr_info\n",
-                        __func__);
-                return -ENOMEM;
-        }
-
-        platform_set_drvdata(pdev, sr_info);
-
-        if (!pdata) {
-                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
-                ret = -EINVAL;
-                goto err_free_devinfo;
-        }
-
-        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!mem) {
-                dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
-                ret = -ENODEV;
-                goto err_free_devinfo;
-        }
-
-        mem = request_mem_region(mem->start, resource_size(mem),
-                                        dev_name(&pdev->dev));
-        if (!mem) {
-                dev_err(&pdev->dev, "%s: no mem region\n", __func__);
-                ret = -EBUSY;
-                goto err_free_devinfo;
-        }
-
-        irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-
-        pm_runtime_enable(&pdev->dev);
-        pm_runtime_irq_safe(&pdev->dev);
-
-        sr_info->pdev = pdev;
-        sr_info->srid = pdev->id;
-        sr_info->voltdm = pdata->voltdm;
-        sr_info->nvalue_table = pdata->nvalue_table;
-        sr_info->nvalue_count = pdata->nvalue_count;
-        sr_info->senn_mod = pdata->senn_mod;
-        sr_info->senp_mod = pdata->senp_mod;
-        sr_info->autocomp_active = false;
-        sr_info->ip_type = pdata->ip_type;
-        sr_info->base = ioremap(mem->start, resource_size(mem));
-        if (!sr_info->base) {
-                dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
-                ret = -ENOMEM;
-                goto err_release_region;
-        }
-
-        if (irq)
-                sr_info->irq = irq->start;
-
-        sr_set_clk_length(sr_info);
-        sr_set_regfields(sr_info);
-
-        list_add(&sr_info->node, &sr_list);
-
-        /*
-         * Call into late init to do intializations that require
-         * both sr driver and sr class driver to be initiallized.
-         */
-        if (sr_class) {
-                ret = sr_late_init(sr_info);
-                if (ret) {
-                        pr_warning("%s: Error in SR late init\n", __func__);
-                        goto err_iounmap;
-                }
-        }
-
-        dev_info(&pdev->dev, "%s: SmartReflex driver initialized\n", __func__);
-        if (!sr_dbg_dir) {
-                sr_dbg_dir = debugfs_create_dir("smartreflex", NULL);
-                if (IS_ERR_OR_NULL(sr_dbg_dir)) {
-                        ret = PTR_ERR(sr_dbg_dir);
-                        pr_err("%s:sr debugfs dir creation failed(%d)\n",
-                                __func__, ret);
-                        goto err_iounmap;
-                }
-        }
-
-        name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
-        if (!name) {
-                dev_err(&pdev->dev, "%s: Unable to alloc debugfs name\n",
-                        __func__);
-                ret = -ENOMEM;
-                goto err_iounmap;
-        }
-        sr_info->dbg_dir = debugfs_create_dir(name, sr_dbg_dir);
-        kfree(name);
-        if (IS_ERR_OR_NULL(sr_info->dbg_dir)) {
-                dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
-                        __func__);
-                ret = PTR_ERR(sr_info->dbg_dir);
-                goto err_iounmap;
-        }
-
-        (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
-                        sr_info->dbg_dir, (void *)sr_info, &pm_sr_fops);
-        (void) debugfs_create_x32("errweight", S_IRUGO, sr_info->dbg_dir,
-                        &sr_info->err_weight);
-        (void) debugfs_create_x32("errmaxlimit", S_IRUGO, sr_info->dbg_dir,
-                        &sr_info->err_maxlimit);
-        (void) debugfs_create_x32("errminlimit", S_IRUGO, sr_info->dbg_dir,
-                        &sr_info->err_minlimit);
-
-        nvalue_dir = debugfs_create_dir("nvalue", sr_info->dbg_dir);
-        if (IS_ERR_OR_NULL(nvalue_dir)) {
-                dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
-                        "for n-values\n", __func__);
-                ret = PTR_ERR(nvalue_dir);
-                goto err_debugfs;
-        }
-
-        omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
-        if (!volt_data) {
-                dev_warn(&pdev->dev, "%s: No Voltage table for the"
-                        " corresponding vdd vdd_%s. Cannot create debugfs"
-                        "entries for n-values\n",
-                        __func__, sr_info->voltdm->name);
-                ret = -ENODATA;
-                goto err_debugfs;
-        }
-
-        for (i = 0; i < sr_info->nvalue_count; i++) {
-                char name[NVALUE_NAME_LEN + 1];
-
-                snprintf(name, sizeof(name), "volt_%d",
-                         volt_data[i].volt_nominal);
-                (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
-                                &(sr_info->nvalue_table[i].nvalue));
-        }
-
-        return ret;
-
-err_debugfs:
-        debugfs_remove_recursive(sr_info->dbg_dir);
-err_iounmap:
-        list_del(&sr_info->node);
-        iounmap(sr_info->base);
-err_release_region:
-        release_mem_region(mem->start, resource_size(mem));
-err_free_devinfo:
-        kfree(sr_info);
-
-        return ret;
-}
-
-static int __devexit omap_sr_remove(struct platform_device *pdev)
-{
-        struct omap_sr_data *pdata = pdev->dev.platform_data;
-        struct omap_sr *sr_info;
-        struct resource *mem;
-
-        if (!pdata) {
-                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
-                return -EINVAL;
-        }
-
-        sr_info = _sr_lookup(pdata->voltdm);
-        if (IS_ERR(sr_info)) {
-                dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
-                        __func__);
-                return PTR_ERR(sr_info);
-        }
-
-        if (sr_info->autocomp_active)
-                sr_stop_vddautocomp(sr_info);
-        if (sr_info->dbg_dir)
-                debugfs_remove_recursive(sr_info->dbg_dir);
-
-        list_del(&sr_info->node);
-        iounmap(sr_info->base);
-        kfree(sr_info);
-        mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        release_mem_region(mem->start, resource_size(mem));
-
-        return 0;
-}
-
-static void __devexit omap_sr_shutdown(struct platform_device *pdev)
-{
-        struct omap_sr_data *pdata = pdev->dev.platform_data;
-        struct omap_sr *sr_info;
-
-        if (!pdata) {
-                dev_err(&pdev->dev, "%s: platform data missing\n", __func__);
-                return;
-        }
-
-        sr_info = _sr_lookup(pdata->voltdm);
-        if (IS_ERR(sr_info)) {
-                dev_warn(&pdev->dev, "%s: omap_sr struct not found\n",
-                        __func__);
-                return;
-        }
-
-        if (sr_info->autocomp_active)
-                sr_stop_vddautocomp(sr_info);
-
-        return;
-}
-
-static struct platform_driver smartreflex_driver = {
-        .remove         = __devexit_p(omap_sr_remove),
-        .shutdown       = __devexit_p(omap_sr_shutdown),
-        .driver         = {
-                .name   = "smartreflex",
-        },
-};
-
-static int __init sr_init(void)
-{
-        int ret = 0;
-
-        /*
-         * sr_init is a late init. If by then a pmic specific API is not
-         * registered either there is no need for anything to be done on
-         * the PMIC side or somebody has forgotten to register a PMIC
-         * handler. Warn for the second condition.
-         */
-        if (sr_pmic_data && sr_pmic_data->sr_pmic_init)
-                sr_pmic_data->sr_pmic_init();
-        else
-                pr_warning("%s: No PMIC hook to init smartreflex\n", __func__);
-
-        ret = platform_driver_probe(&smartreflex_driver, omap_sr_probe);
-        if (ret) {
-                pr_err("%s: platform driver register failed for SR\n",
-                        __func__);
-                return ret;
-        }
-
-        return 0;
-}
-late_initcall(sr_init);
-
-static void __exit sr_exit(void)
-{
-        platform_driver_unregister(&smartreflex_driver);
-}
-module_exit(sr_exit);
-
-MODULE_DESCRIPTION("OMAP Smartreflex Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:" DRIVER_NAME);
-MODULE_AUTHOR("Texas Instruments Inc");
diff --git a/arch/arm/mach-omap2/smartreflex.h b/arch/arm/mach-omap2/smartreflex.h
deleted file mode 100644
index 5809141171f..00000000000
--- a/arch/arm/mach-omap2/smartreflex.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * OMAP Smartreflex Defines and Routines
- *
- * Author: Thara Gopinath       <thara@ti.com>
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Thara Gopinath <thara@ti.com>
- *
- * Copyright (C) 2008 Nokia Corporation
- * Kalle Jokiniemi
- *
- * Copyright (C) 2007 Texas Instruments, Inc.
- * Lesly A M <x0080970@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARM_OMAP_SMARTREFLEX_H
-#define __ASM_ARM_OMAP_SMARTREFLEX_H
-
-#include <linux/platform_device.h>
-
-#include "voltage.h"
-
-/*
- * Different Smartreflex IPs version. The v1 is the 65nm version used in
- * OMAP3430. The v2 is the update for the 45nm version of the IP
- * used in OMAP3630 and OMAP4430
- */
-#define SR_TYPE_V1      1
-#define SR_TYPE_V2      2
-
-/* SMART REFLEX REG ADDRESS OFFSET */
-#define SRCONFIG                0x00
-#define SRSTATUS                0x04
-#define SENVAL                  0x08
-#define SENMIN                  0x0C
-#define SENMAX                  0x10
-#define SENAVG                  0x14
-#define AVGWEIGHT               0x18
-#define NVALUERECIPROCAL        0x1c
-#define SENERROR_V1             0x20
-#define ERRCONFIG_V1            0x24
-#define IRQ_EOI                 0x20
-#define IRQSTATUS_RAW           0x24
-#define IRQSTATUS               0x28
-#define IRQENABLE_SET           0x2C
-#define IRQENABLE_CLR           0x30
-#define SENERROR_V2             0x34
-#define ERRCONFIG_V2            0x38
-
-/* Bit/Shift Positions */
-
-/* SRCONFIG */
-#define SRCONFIG_ACCUMDATA_SHIFT        22
-#define SRCONFIG_SRCLKLENGTH_SHIFT      12
-#define SRCONFIG_SENNENABLE_V1_SHIFT    5
-#define SRCONFIG_SENPENABLE_V1_SHIFT    3
-#define SRCONFIG_SENNENABLE_V2_SHIFT    1
-#define SRCONFIG_SENPENABLE_V2_SHIFT    0
-#define SRCONFIG_CLKCTRL_SHIFT          0
-
-#define SRCONFIG_ACCUMDATA_MASK         (0x3ff << 22)
-
-#define SRCONFIG_SRENABLE               BIT(11)
-#define SRCONFIG_SENENABLE              BIT(10)
-#define SRCONFIG_ERRGEN_EN              BIT(9)
-#define SRCONFIG_MINMAXAVG_EN           BIT(8)
-#define SRCONFIG_DELAYCTRL              BIT(2)
-
-/* AVGWEIGHT */
-#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT   2
-#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT   0
-
-/* NVALUERECIPROCAL */
-#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
-#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
-#define NVALUERECIPROCAL_RNSENP_SHIFT   8
-#define NVALUERECIPROCAL_RNSENN_SHIFT   0
-
-/* ERRCONFIG */
-#define ERRCONFIG_ERRWEIGHT_SHIFT       16
-#define ERRCONFIG_ERRMAXLIMIT_SHIFT     8
-#define ERRCONFIG_ERRMINLIMIT_SHIFT     0
-
-#define SR_ERRWEIGHT_MASK               (0x07 << 16)
-#define SR_ERRMAXLIMIT_MASK             (0xff << 8)
-#define SR_ERRMINLIMIT_MASK             (0xff << 0)
-
-#define ERRCONFIG_VPBOUNDINTEN_V1       BIT(31)
-#define ERRCONFIG_VPBOUNDINTST_V1       BIT(30)
-#define ERRCONFIG_MCUACCUMINTEN         BIT(29)
-#define ERRCONFIG_MCUACCUMINTST         BIT(28)
-#define ERRCONFIG_MCUVALIDINTEN         BIT(27)
-#define ERRCONFIG_MCUVALIDINTST         BIT(26)
-#define ERRCONFIG_MCUBOUNDINTEN         BIT(25)
-#define ERRCONFIG_MCUBOUNDINTST         BIT(24)
-#define ERRCONFIG_MCUDISACKINTEN        BIT(23)
-#define ERRCONFIG_VPBOUNDINTST_V2       BIT(23)
-#define ERRCONFIG_MCUDISACKINTST        BIT(22)
-#define ERRCONFIG_VPBOUNDINTEN_V2       BIT(22)
-
-#define ERRCONFIG_STATUS_V1_MASK        (ERRCONFIG_VPBOUNDINTST_V1 | \
-                                        ERRCONFIG_MCUACCUMINTST | \
-                                        ERRCONFIG_MCUVALIDINTST | \
-                                        ERRCONFIG_MCUBOUNDINTST | \
-                                        ERRCONFIG_MCUDISACKINTST)
-/* IRQSTATUS */
-#define IRQSTATUS_MCUACCUMINT           BIT(3)
-#define IRQSTATUS_MCVALIDINT            BIT(2)
-#define IRQSTATUS_MCBOUNDSINT           BIT(1)
-#define IRQSTATUS_MCUDISABLEACKINT      BIT(0)
-
-/* IRQENABLE_SET and IRQENABLE_CLEAR */
-#define IRQENABLE_MCUACCUMINT           BIT(3)
-#define IRQENABLE_MCUVALIDINT           BIT(2)
-#define IRQENABLE_MCUBOUNDSINT          BIT(1)
-#define IRQENABLE_MCUDISABLEACKINT      BIT(0)
-
-/* Common Bit values */
-
-#define SRCLKLENGTH_12MHZ_SYSCLK        0x3c
-#define SRCLKLENGTH_13MHZ_SYSCLK        0x41
-#define SRCLKLENGTH_19MHZ_SYSCLK        0x60
-#define SRCLKLENGTH_26MHZ_SYSCLK        0x82
-#define SRCLKLENGTH_38MHZ_SYSCLK        0xC0
-
-/*
- * 3430 specific values. Maybe these should be passed from board file or
- * pmic structures.
- */
-#define OMAP3430_SR_ACCUMDATA           0x1f4
-
-#define OMAP3430_SR1_SENPAVGWEIGHT      0x03
-#define OMAP3430_SR1_SENNAVGWEIGHT      0x03
-
-#define OMAP3430_SR2_SENPAVGWEIGHT      0x01
-#define OMAP3430_SR2_SENNAVGWEIGHT      0x01
-
-#define OMAP3430_SR_ERRWEIGHT           0x04
-#define OMAP3430_SR_ERRMAXLIMIT         0x02
-
-/**
- * struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
- *                              pmic specific info to smartreflex driver
- *
- * @sr_pmic_init:       API to initialize smartreflex on the PMIC side.
- */
-struct omap_sr_pmic_data {
-        void (*sr_pmic_init) (void);
-};
-
-/**
- * struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
- *
- * @sensor_voltdm_name:       Name of voltdomain of SR instance
- */
-struct omap_smartreflex_dev_attr {
-        const char      *sensor_voltdm_name;
-};
-
-#ifdef CONFIG_OMAP_SMARTREFLEX
-/*
- * The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
- * The smartreflex class driver should pass the class type.
- * Should be used to populate the class_type field of the
- * omap_smartreflex_class_data structure.
- */
-#define SR_CLASS1       0x1
-#define SR_CLASS2       0x2
-#define SR_CLASS3       0x3
-
-/**
- * struct omap_sr_class_data - Smartreflex class driver info
- *
- * @enable:             API to enable a particular class smaartreflex.
- * @disable:            API to disable a particular class smartreflex.
- * @configure:          API to configure a particular class smartreflex.
- * @notify:             API to notify the class driver about an event in SR.
- *                      Not needed for class3.
- * @notify_flags:       specify the events to be notified to the class driver
- * @class_type:         specify which smartreflex class.
- *                      Can be used by the SR driver to take any class
- *                      based decisions.
- */
-struct omap_sr_class_data {
-        int (*enable)(struct voltagedomain *voltdm);
-        int (*disable)(struct voltagedomain *voltdm, int is_volt_reset);
-        int (*configure)(struct voltagedomain *voltdm);
-        int (*notify)(struct voltagedomain *voltdm, u32 status);
-        u8 notify_flags;
-        u8 class_type;
-};
-
-/**
- * struct omap_sr_nvalue_table  - Smartreflex n-target value info
- *
- * @efuse_offs: The offset of the efuse where n-target values are stored.
- * @nvalue:     The n-target value.
- */
-struct omap_sr_nvalue_table {
-        u32 efuse_offs;
-        u32 nvalue;
-};
-
-/**
- * struct omap_sr_data - Smartreflex platform data.
- *
- * @ip_type:            Smartreflex IP type.
- * @senp_mod:           SENPENABLE value for the sr
- * @senn_mod:           SENNENABLE value for sr
- * @nvalue_count:       Number of distinct nvalues in the nvalue table
- * @enable_on_init:     whether this sr module needs to enabled at
- *                      boot up or not.
- * @nvalue_table:       table containing the  efuse offsets and nvalues
- *                      corresponding to them.
- * @voltdm:             Pointer to the voltage domain associated with the SR
- */
-struct omap_sr_data {
-        int                             ip_type;
-        u32                             senp_mod;
-        u32                             senn_mod;
-        int                             nvalue_count;
-        bool                            enable_on_init;
-        struct omap_sr_nvalue_table     *nvalue_table;
-        struct voltagedomain            *voltdm;
-};
-
-/* Smartreflex module enable/disable interface */
-void omap_sr_enable(struct voltagedomain *voltdm);
-void omap_sr_disable(struct voltagedomain *voltdm);
-void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
-
-/* API to register the pmic specific data with the smartreflex driver. */
-void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
-
-/* Smartreflex driver hooks to be called from Smartreflex class driver */
-int sr_enable(struct voltagedomain *voltdm, unsigned long volt);
-void sr_disable(struct voltagedomain *voltdm);
-int sr_configure_errgen(struct voltagedomain *voltdm);
-int sr_disable_errgen(struct voltagedomain *voltdm);
-int sr_configure_minmax(struct voltagedomain *voltdm);
-
-/* API to register the smartreflex class driver with the smartreflex driver */
-int sr_register_class(struct omap_sr_class_data *class_data);
-#else
-static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
-static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
-static inline void omap_sr_disable_reset_volt(
-                struct voltagedomain *voltdm) {}
-static inline void omap_sr_register_pmic(
-                struct omap_sr_pmic_data *pmic_data) {}
-#endif
-#endif
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index a503e1e8358..d033a65f4e4 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -17,6 +17,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/power/smartreflex.h>
 
 #include <linux/err.h>
 #include <linux/slab.h>
@@ -24,7 +25,6 @@
 
 #include <plat/omap_device.h>
 
-#include "smartreflex.h"
 #include "voltage.h"
 #include "control.h"
 #include "pm.h"
@@ -36,7 +36,10 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
                                 struct omap_sr_data *sr_data)
 {
         struct omap_sr_nvalue_table *nvalue_table;
-        int i, count = 0;
+        int i, j, count = 0;
+
+        sr_data->nvalue_count = 0;
+        sr_data->nvalue_table = NULL;
 
         while (volt_data[count].volt_nominal)
                 count++;
@@ -44,8 +47,14 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
         nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count,
                         GFP_KERNEL);
 
-        for (i = 0; i < count; i++) {
+        if (!nvalue_table) {
+                pr_err("OMAP: SmartReflex: cannot allocate memory for n-value table\n");
+                return;
+        }
+
+        for (i = 0, j = 0; i < count; i++) {
                 u32 v;
+
                 /*
                  * In OMAP4 the efuse registers are 24 bit aligned.
                  * A __raw_readl will fail for non-32 bit aligned address
@@ -58,15 +67,30 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
                                 omap_ctrl_readb(offset + 1) << 8 |
                                 omap_ctrl_readb(offset + 2) << 16;
                 } else {
-                         v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
+                        v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
                 }
 
-                nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
-                nvalue_table[i].nvalue = v;
+                /*
+                 * Many OMAP SoCs don't have the eFuse values set.
+                 * For example, pretty much all OMAP3xxx before
+                 * ES3.something.
+                 *
+                 * XXX There needs to be some way for board files or
+                 * userspace to add these in.
+                 */
+                if (v == 0)
+                        continue;
+
+                nvalue_table[j].nvalue = v;
+                nvalue_table[j].efuse_offs = volt_data[i].sr_efuse_offs;
+                nvalue_table[j].errminlimit = volt_data[i].sr_errminlimit;
+                nvalue_table[j].volt_nominal = volt_data[i].volt_nominal;
+
+                j++;
         }
 
         sr_data->nvalue_table = nvalue_table;
-        sr_data->nvalue_count = count;
+        sr_data->nvalue_count = j;
 }
 
 static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
@@ -93,6 +117,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
                 goto exit;
         }
 
+        sr_data->name = oh->name;
         sr_data->ip_type = oh->class->rev;
         sr_data->senn_mod = 0x1;
         sr_data->senp_mod = 0x1;
@@ -106,7 +131,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
 
         omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
         if (!volt_data) {
-                pr_warning("%s: No Voltage table registerd fo VDD%d."
+                pr_warning("%s: No Voltage table registered fo VDD%d."
                         "Something really wrong\n\n", __func__, i + 1);
                 goto exit;
         }
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 840929bd9da..2ff6d41ec6c 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -69,11 +69,6 @@
 #define OMAP3_SECURE_TIMER      1
 #endif
 
-/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
-#define MAX_GPTIMER_ID          12
-
-static u32 sys_timer_reserved;
-
 /* Clockevent code */
 
 static struct omap_dm_timer clkev;
@@ -135,6 +130,7 @@ static struct clock_event_device clockevent_gpt = {
         .name           = "gp_timer",
         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
         .shift          = 32,
+        .rating         = 300,
         .set_next_event = omap2_gp_timer_set_next_event,
         .set_mode       = omap2_gp_timer_set_mode,
 };
@@ -173,14 +169,14 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
                 return -ENXIO;
 
         /* After the dmtimer is using hwmod these clocks won't be needed */
-        sprintf(name, "gpt%d_fck", gptimer_id);
-        timer->fclk = clk_get(NULL, name);
+        timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
         if (IS_ERR(timer->fclk))
                 return -ENODEV;
 
         omap_hwmod_enable(oh);
 
-        sys_timer_reserved |= (1 << (gptimer_id - 1));
+        if (omap_dm_timer_reserve_systimer(gptimer_id))
+                return -ENODEV;
 
         if (gptimer_id != 12) {
                 struct clk *src;
@@ -228,7 +224,8 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
                 clockevent_delta2ns(3, &clockevent_gpt);
                 /* Timer internal resynch latency. */
 
-        clockevent_gpt.cpumask = cpumask_of(0);
+        clockevent_gpt.cpumask = cpu_possible_mask;
+        clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
         clockevents_register_device(&clockevent_gpt);
 
         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
@@ -368,6 +365,11 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 OMAP_SYS_TIMER(3_secure)
 #endif
 
+#ifdef CONFIG_SOC_AM33XX
+OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER(3_am33xx)
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
@@ -393,65 +395,10 @@ static void __init omap4_timer_init(void)
 OMAP_SYS_TIMER(4)
 #endif
 
-/**
- * omap2_dm_timer_set_src - change the timer input clock source
- * @pdev:       timer platform device pointer
- * @source:     array index of parent clock source
- */
-static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
-{
-        int ret;
-        struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
-        struct clk *fclk, *parent;
-        char *parent_name = NULL;
-
-        fclk = clk_get(&pdev->dev, "fck");
-        if (IS_ERR_OR_NULL(fclk)) {
-                dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
-                                __func__, __LINE__);
-                return -EINVAL;
-        }
-
-        switch (source) {
-        case OMAP_TIMER_SRC_SYS_CLK:
-                parent_name = "sys_ck";
-                break;
-
-        case OMAP_TIMER_SRC_32_KHZ:
-                parent_name = "32k_ck";
-                break;
-
-        case OMAP_TIMER_SRC_EXT_CLK:
-                if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
-                        parent_name = "alt_ck";
-                        break;
-                }
-                dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
-                        __func__, __LINE__);
-                clk_put(fclk);
-                return -EINVAL;
-        }
-
-        parent = clk_get(&pdev->dev, parent_name);
-        if (IS_ERR_OR_NULL(parent)) {
-                dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
-                        __func__, __LINE__, parent_name);
-                clk_put(fclk);
-                return -EINVAL;
-        }
-
-        ret = clk_set_parent(fclk, parent);
-        if (IS_ERR_VALUE(ret)) {
-                dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
-                        __func__, parent_name);
-                ret = -EINVAL;
-        }
-
-        clk_put(parent);
-        clk_put(fclk);
-
-        return ret;
-}
+#ifdef CONFIG_SOC_OMAP5
+OMAP_SYS_TIMER_INIT(5, 1, OMAP4_CLKEV_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER(5)
+#endif
 
 /**
  * omap_timer_init - build and register timer device with an
@@ -473,7 +420,6 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
         struct dmtimer_platform_data *pdata;
         struct platform_device *pdev;
         struct omap_timer_capability_dev_attr *timer_dev_attr;
-        struct powerdomain *pwrdm;
 
         pr_debug("%s: %s\n", __func__, oh->name);
 
@@ -501,18 +447,9 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
          */
         sscanf(oh->name, "timer%2d", &id);
 
-        pdata->set_timer_src = omap2_dm_timer_set_src;
-        pdata->timer_ip_version = oh->class->rev;
+        if (timer_dev_attr)
+                pdata->timer_capability = timer_dev_attr->timer_capability;
 
-        /* Mark clocksource and clockevent timers as reserved */
-        if ((sys_timer_reserved >> (id - 1)) & 0x1)
-                pdata->reserved = 1;
-
-        pwrdm = omap_hwmod_get_pwrdm(oh);
-        pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
-#ifdef CONFIG_PM
-        pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
-#endif
         pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
                                  NULL, 0, 0);
 
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 43a97907533..db5ff664237 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -49,6 +49,7 @@ static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
         },
 };
 
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 static int twl_set_voltage(void *data, int target_uV)
 {
         struct voltagedomain *voltdm = (struct voltagedomain *)data;
@@ -60,11 +61,13 @@ static int twl_get_voltage(void *data)
         struct voltagedomain *voltdm = (struct voltagedomain *)data;
         return voltdm_get_voltage(voltdm);
 }
+#endif
 
 void __init omap_pmic_init(int bus, u32 clkrate,
                            const char *pmic_type, int pmic_irq,
                            struct twl4030_platform_data *pmic_data)
 {
+        omap_mux_init_signal("sys_nirq", OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_WAKEUPENABLE);
         strncpy(pmic_i2c_board_info.type, pmic_type,
                 sizeof(pmic_i2c_board_info.type));
         pmic_i2c_board_info.irq = pmic_irq;
@@ -94,7 +97,7 @@ void __init omap4_pmic_init(const char *pmic_type,
 
 void __init omap_pmic_late_init(void)
 {
-        /* Init the OMAP TWL parameters (if PMIC has been registerd) */
+        /* Init the OMAP TWL parameters (if PMIC has been registered) */
         if (pmic_i2c_board_info.irq)
                 omap3_twl_init();
         if (omap4_i2c1_board_info[0].irq)
@@ -213,10 +216,6 @@ static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
 void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                                   u32 pdata_flags, u32 regulators_flags)
 {
-        if (!pmic_data->irq_base)
-                pmic_data->irq_base = TWL4030_IRQ_BASE;
-        if (!pmic_data->irq_end)
-                pmic_data->irq_end = TWL4030_IRQ_END;
         if (!pmic_data->vdd1) {
                 omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
                 omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
@@ -481,11 +480,6 @@ static struct regulator_init_data omap4_v2v1_idata = {
 void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
                                   u32 pdata_flags, u32 regulators_flags)
 {
-        if (!pmic_data->irq_base)
-                pmic_data->irq_base = TWL6030_IRQ_BASE;
-        if (!pmic_data->irq_end)
-                pmic_data->irq_end = TWL6030_IRQ_END;
-
         if (!pmic_data->vdd1) {
                 omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
                 omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
deleted file mode 100644
index 1481078763b..00000000000
--- a/arch/arm/mach-omap2/usb-fs.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
- *
- * Copyright (C) 2004 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-
-#include <asm/irq.h>
-
-#include <plat/usb.h>
-#include <plat/board.h>
-
-#include "control.h"
-#include "mux.h"
-
-#define INT_USB_IRQ_GEN         INT_24XX_USB_IRQ_GEN
-#define INT_USB_IRQ_NISO        INT_24XX_USB_IRQ_NISO
-#define INT_USB_IRQ_ISO         INT_24XX_USB_IRQ_ISO
-#define INT_USB_IRQ_HGEN        INT_24XX_USB_IRQ_HGEN
-#define INT_USB_IRQ_OTG         INT_24XX_USB_IRQ_OTG
-
-#if defined(CONFIG_ARCH_OMAP2)
-
-#ifdef  CONFIG_USB_GADGET_OMAP
-
-static struct resource udc_resources[] = {
-        /* order is significant! */
-        {               /* registers */
-                .start          = UDC_BASE,
-                .end            = UDC_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {            /* general IRQ */
-                .start          = INT_USB_IRQ_GEN,
-                .flags          = IORESOURCE_IRQ,
-        }, {            /* PIO IRQ */
-                .start          = INT_USB_IRQ_NISO,
-                .flags          = IORESOURCE_IRQ,
-        }, {            /* SOF IRQ */
-                .start          = INT_USB_IRQ_ISO,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static u64 udc_dmamask = ~(u32)0;
-
-static struct platform_device udc_device = {
-        .name           = "omap_udc",
-        .id             = -1,
-        .dev = {
-                .dma_mask               = &udc_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(udc_resources),
-        .resource       = udc_resources,
-};
-
-static inline void udc_device_init(struct omap_usb_config *pdata)
-{
-        pdata->udc_device = &udc_device;
-}
-
-#else
-
-static inline void udc_device_init(struct omap_usb_config *pdata)
-{
-}
-
-#endif
-
-#if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32)0;
-
-static struct resource ohci_resources[] = {
-        {
-                .start  = OMAP_OHCI_BASE,
-                .end    = OMAP_OHCI_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_USB_IRQ_HGEN,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ohci_device = {
-        .name                   = "ohci",
-        .id                     = -1,
-        .dev = {
-                .dma_mask               = &ohci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(ohci_resources),
-        .resource               = ohci_resources,
-};
-
-static inline void ohci_device_init(struct omap_usb_config *pdata)
-{
-        pdata->ohci_device = &ohci_device;
-}
-
-#else
-
-static inline void ohci_device_init(struct omap_usb_config *pdata)
-{
-}
-
-#endif
-
-#if     defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
-
-static struct resource otg_resources[] = {
-        /* order is significant! */
-        {
-                .start          = OTG_BASE,
-                .end            = OTG_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = INT_USB_IRQ_OTG,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device otg_device = {
-        .name           = "omap_otg",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(otg_resources),
-        .resource       = otg_resources,
-};
-
-static inline void otg_device_init(struct omap_usb_config *pdata)
-{
-        pdata->otg_device = &otg_device;
-}
-
-#else
-
-static inline void otg_device_init(struct omap_usb_config *pdata)
-{
-}
-
-#endif
-
-static void omap2_usb_devconf_clear(u8 port, u32 mask)
-{
-        u32 r;
-
-        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        r &= ~USBTXWRMODEI(port, mask);
-        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb_devconf_set(u8 port, u32 mask)
-{
-        u32 r;
-
-        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        r |= USBTXWRMODEI(port, mask);
-        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb2_disable_5pinbitll(void)
-{
-        u32 r;
-
-        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
-        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb2_enable_5pinunitll(void)
-{
-        u32 r;
-
-        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
-        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
-{
-        u32     syscon1 = 0;
-
-        omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
-
-        if (nwires == 0)
-                return 0;
-
-        if (is_device)
-                omap_mux_init_signal("usb0_puen", 0);
-
-        omap_mux_init_signal("usb0_dat", 0);
-        omap_mux_init_signal("usb0_txen", 0);
-        omap_mux_init_signal("usb0_se0", 0);
-        if (nwires != 3)
-                omap_mux_init_signal("usb0_rcv", 0);
-
-        switch (nwires) {
-        case 3:
-                syscon1 = 2;
-                omap2_usb_devconf_set(0, USB_BIDIR);
-                break;
-        case 4:
-                syscon1 = 1;
-                omap2_usb_devconf_set(0, USB_BIDIR);
-                break;
-        case 6:
-                syscon1 = 3;
-                omap_mux_init_signal("usb0_vp", 0);
-                omap_mux_init_signal("usb0_vm", 0);
-                omap2_usb_devconf_set(0, USB_UNIDIR);
-                break;
-        default:
-                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                        0, nwires);
-        }
-
-        return syscon1 << 16;
-}
-
-static u32 __init omap2_usb1_init(unsigned nwires)
-{
-        u32     syscon1 = 0;
-
-        omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
-
-        if (nwires == 0)
-                return 0;
-
-        /* NOTE:  board-specific code must set up pin muxing for usb1,
-         * since each signal could come out on either of two balls.
-         */
-
-        switch (nwires) {
-        case 2:
-                /* NOTE: board-specific code must override this setting if
-                 * this TLL link is not using DP/DM
-                 */
-                syscon1 = 1;
-                omap2_usb_devconf_set(1, USB_BIDIR_TLL);
-                break;
-        case 3:
-                syscon1 = 2;
-                omap2_usb_devconf_set(1, USB_BIDIR);
-                break;
-        case 4:
-                syscon1 = 1;
-                omap2_usb_devconf_set(1, USB_BIDIR);
-                break;
-        case 6:
-        default:
-                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                        1, nwires);
-        }
-
-        return syscon1 << 20;
-}
-
-static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
-{
-        u32     syscon1 = 0;
-
-        omap2_usb2_disable_5pinbitll();
-        alt_pingroup = 0;
-
-        /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
-        if (alt_pingroup || nwires == 0)
-                return 0;
-
-        omap_mux_init_signal("usb2_dat", 0);
-        omap_mux_init_signal("usb2_se0", 0);
-        if (nwires > 2)
-                omap_mux_init_signal("usb2_txen", 0);
-        if (nwires > 3)
-                omap_mux_init_signal("usb2_rcv", 0);
-
-        switch (nwires) {
-        case 2:
-                /* NOTE: board-specific code must override this setting if
-                 * this TLL link is not using DP/DM
-                 */
-                syscon1 = 1;
-                omap2_usb_devconf_set(2, USB_BIDIR_TLL);
-                break;
-        case 3:
-                syscon1 = 2;
-                omap2_usb_devconf_set(2, USB_BIDIR);
-                break;
-        case 4:
-                syscon1 = 1;
-                omap2_usb_devconf_set(2, USB_BIDIR);
-                break;
-        case 5:
-                /* NOTE: board-specific code must mux this setting depending
-                 * on TLL link using DP/DM.  Something must also
-                 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
-                 * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0
-                 * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0
-                 */
-
-                syscon1 = 3;
-                omap2_usb2_enable_5pinunitll();
-                break;
-        case 6:
-        default:
-                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                        2, nwires);
-        }
-
-        return syscon1 << 24;
-}
-
-void __init omap2_usbfs_init(struct omap_usb_config *pdata)
-{
-        struct clk *ick;
-
-        if (!cpu_is_omap24xx())
-                return;
-
-        ick = clk_get(NULL, "usb_l4_ick");
-        if (IS_ERR(ick))
-                return;
-
-        clk_enable(ick);
-        pdata->usb0_init = omap2_usb0_init;
-        pdata->usb1_init = omap2_usb1_init;
-        pdata->usb2_init = omap2_usb2_init;
-        udc_device_init(pdata);
-        ohci_device_init(pdata);
-        otg_device_init(pdata);
-        omap_otg_init(pdata);
-        clk_disable(ick);
-        clk_put(ick);
-}
-
-#endif
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 16a1b092cf3..0ac2caf1594 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -16,6 +16,8 @@
 
 #include <linux/err.h>
 
+#include <plat/voltage.h>
+
 #include "vc.h"
 #include "vp.h"
 
@@ -91,25 +93,6 @@ struct voltagedomain {
 };
 
 /**
- * struct omap_volt_data - Omap voltage specific data.
- * @voltage_nominal:    The possible voltage value in uV
- * @sr_efuse_offs:      The offset of the efuse register(from system
- *                      control module base address) from where to read
- *                      the n-target value for the smartreflex module.
- * @sr_errminlimit:     Error min limit value for smartreflex. This value
- *                      differs at differnet opp and thus is linked
- *                      with voltage.
- * @vp_errorgain:       Error gain value for the voltage processor. This
- *                      field also differs according to the voltage/opp.
- */
-struct omap_volt_data {
-        u32     volt_nominal;
-        u32     sr_efuse_offs;
-        u8      sr_errminlimit;
-        u8      vp_errgain;
-};
-
-/**
  * struct omap_voltdm_pmic - PMIC specific data required by voltage driver.
  * @slew_rate:  PMIC slew rate (in uv/us)
  * @step_size:  PMIC voltage step size (in uv)
@@ -156,6 +139,7 @@ int omap_voltage_late_init(void);
 
 extern void omap2xxx_voltagedomains_init(void);
 extern void omap3xxx_voltagedomains_init(void);
+extern void am33xx_voltagedomains_init(void);
 extern void omap44xx_voltagedomains_init(void);
 
 struct voltagedomain *voltdm_lookup(const char *name);
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
new file mode 100644
index 00000000000..965458dc0cb
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c
@@ -0,0 +1,43 @@
+/*
+ * AM33XX voltage domain data
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "voltage.h"
+
+static struct voltagedomain am33xx_voltdm_mpu = {
+        .name           = "mpu",
+};
+
+static struct voltagedomain am33xx_voltdm_core = {
+        .name           = "core",
+};
+
+static struct voltagedomain am33xx_voltdm_rtc = {
+        .name           = "rtc",
+};
+
+static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
+        &am33xx_voltdm_mpu,
+        &am33xx_voltdm_core,
+        &am33xx_voltdm_rtc,
+        NULL,
+};
+
+void __init am33xx_voltagedomains_init(void)
+{
+        voltdm_init(voltagedomains_am33xx);
+}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 9148b229d0d..410291c6766 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -109,7 +109,8 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
 {
         orion_ge00_init(eth_data,
                         ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
-                        IRQ_ORION5X_ETH_ERR);
+                        IRQ_ORION5X_ETH_ERR,
+                        MV643XX_TX_CSUM_DEFAULT_LIMIT);
 }
 
 
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index b1b45fff776..17da7091d31 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -11,19 +11,16 @@
  */
 #include <linux/gpio.h>
 #include <linux/kernel.h>
-#include <linux/init.h>
 #include <linux/irq.h>
-#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/irq.h>
-#include "common.h"
 
-static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
-
-        orion_gpio_irq_handler((irq - IRQ_ORION5X_GPIO_0_7) << 3);
-}
+static int __initdata gpio0_irqs[4] = {
+        IRQ_ORION5X_GPIO_0_7,
+        IRQ_ORION5X_GPIO_8_15,
+        IRQ_ORION5X_GPIO_16_23,
+        IRQ_ORION5X_GPIO_24_31,
+};
 
 void __init orion5x_init_irq(void)
 {
@@ -32,9 +29,6 @@ void __init orion5x_init_irq(void)
         /*
          * Initialize gpiolib for GPIOs 0-31.
          */
-        orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
-        irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
-        irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
+        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0,
+                        IRQ_ORION5X_GPIO_START, gpio0_irqs);
 }
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
index e5ec4a8d9bc..8e39f80fce1 100644
--- a/arch/arm/mach-picoxcell/Makefile
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -1,2 +1 @@
 obj-y   := common.o
-obj-y   += time.o
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index a2e8ae8b582..8f9a0b47a7f 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -14,6 +14,7 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/dw_apb_timer.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/vic.h>
@@ -97,7 +98,7 @@ DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
         .nr_irqs        = NR_IRQS_LEGACY,
         .init_irq       = picoxcell_init_irq,
         .handle_irq     = vic_handle_irq,
-        .timer          = &picoxcell_timer,
+        .timer          = &dw_apb_timer,
         .init_machine   = picoxcell_init_machine,
         .dt_compat      = picoxcell_dt_match,
         .restart        = picoxcell_wdt_restart,
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
index 83d55ab956a..a65cb02f84c 100644
--- a/arch/arm/mach-picoxcell/common.h
+++ b/arch/arm/mach-picoxcell/common.h
@@ -12,6 +12,6 @@
 
 #include <asm/mach/time.h>
 
-extern struct sys_timer picoxcell_timer;
+extern struct sys_timer dw_apb_timer;
 
 #endif /* __PICOXCELL_COMMON_H__ */
diff --git a/arch/arm/mach-picoxcell/time.c b/arch/arm/mach-picoxcell/time.c
deleted file mode 100644
index 2ecba6743b8..00000000000
--- a/arch/arm/mach-picoxcell/time.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * All enquiries to support@picochip.com
- */
-#include <linux/dw_apb_timer.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include <asm/mach/time.h>
-#include <asm/sched_clock.h>
-
-#include "common.h"
-
-static void timer_get_base_and_rate(struct device_node *np,
-                                    void __iomem **base, u32 *rate)
-{
-        *base = of_iomap(np, 0);
-
-        if (!*base)
-                panic("Unable to map regs for %s", np->name);
-
-        if (of_property_read_u32(np, "clock-freq", rate))
-                panic("No clock-freq property for %s", np->name);
-}
-
-static void picoxcell_add_clockevent(struct device_node *event_timer)
-{
-        void __iomem *iobase;
-        struct dw_apb_clock_event_device *ced;
-        u32 irq, rate;
-
-        irq = irq_of_parse_and_map(event_timer, 0);
-        if (irq == NO_IRQ)
-                panic("No IRQ for clock event timer");
-
-        timer_get_base_and_rate(event_timer, &iobase, &rate);
-
-        ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq,
-                                     rate);
-        if (!ced)
-                panic("Unable to initialise clockevent device");
-
-        dw_apb_clockevent_register(ced);
-}
-
-static void picoxcell_add_clocksource(struct device_node *source_timer)
-{
-        void __iomem *iobase;
-        struct dw_apb_clocksource *cs;
-        u32 rate;
-
-        timer_get_base_and_rate(source_timer, &iobase, &rate);
-
-        cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
-        if (!cs)
-                panic("Unable to initialise clocksource device");
-
-        dw_apb_clocksource_start(cs);
-        dw_apb_clocksource_register(cs);
-}
-
-static void __iomem *sched_io_base;
-
-static u32 picoxcell_read_sched_clock(void)
-{
-        return __raw_readl(sched_io_base);
-}
-
-static const struct of_device_id picoxcell_rtc_ids[] __initconst = {
-        { .compatible = "picochip,pc3x2-rtc" },
-        { /* Sentinel */ },
-};
-
-static void picoxcell_init_sched_clock(void)
-{
-        struct device_node *sched_timer;
-        u32 rate;
-
-        sched_timer = of_find_matching_node(NULL, picoxcell_rtc_ids);
-        if (!sched_timer)
-                panic("No RTC for sched clock to use");
-
-        timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
-        of_node_put(sched_timer);
-
-        setup_sched_clock(picoxcell_read_sched_clock, 32, rate);
-}
-
-static const struct of_device_id picoxcell_timer_ids[] __initconst = {
-        { .compatible = "picochip,pc3x2-timer" },
-        {},
-};
-
-static void __init picoxcell_timer_init(void)
-{
-        struct device_node *event_timer, *source_timer;
-
-        event_timer = of_find_matching_node(NULL, picoxcell_timer_ids);
-        if (!event_timer)
-                panic("No timer for clockevent");
-        picoxcell_add_clockevent(event_timer);
-
-        source_timer = of_find_matching_node(event_timer, picoxcell_timer_ids);
-        if (!source_timer)
-                panic("No timer for clocksource");
-        picoxcell_add_clocksource(source_timer);
-
-        of_node_put(source_timer);
-
-        picoxcell_init_sched_clock();
-}
-
-struct sys_timer picoxcell_timer = {
-        .init = picoxcell_timer_init,
-};
diff --git a/arch/arm/mach-prima2/include/mach/gpio.h b/arch/arm/mach-prima2/include/mach/gpio.h
new file mode 100644
index 00000000000..1904bb03876
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/gpio.h
@@ -0,0 +1,13 @@
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+/* Pull up/down values */
+enum sirfsoc_gpio_pull {
+        SIRFSOC_GPIO_PULL_NONE,
+        SIRFSOC_GPIO_PULL_UP,
+        SIRFSOC_GPIO_PULL_DOWN,
+};
+
+void sirfsoc_gpio_set_pull(unsigned gpio, unsigned mode);
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h
index bb354f952fd..f6014a07541 100644
--- a/arch/arm/mach-prima2/include/mach/irqs.h
+++ b/arch/arm/mach-prima2/include/mach/irqs.h
@@ -11,7 +11,7 @@
 
 #define SIRFSOC_INTENAL_IRQ_START  0
 #define SIRFSOC_INTENAL_IRQ_END    59
-
+#define SIRFSOC_GPIO_IRQ_START     (SIRFSOC_INTENAL_IRQ_END + 1)
 #define NR_IRQS 220
 
 #endif
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index 0d024b1e916..f224107de7b 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -132,11 +132,11 @@ static void sirfsoc_clocksource_resume(struct clocksource *cs)
 {
         int i;
 
-        for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
+        for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
                 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 
-        writel_relaxed(sirfsoc_timer_reg_val[i - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
-        writel_relaxed(sirfsoc_timer_reg_val[i - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
+        writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
+        writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
 }
 
 static struct clock_event_device sirfsoc_clockevent = {
diff --git a/arch/arm/mach-pxa/eseries.h b/arch/arm/mach-pxa/eseries.h
deleted file mode 100644
index b96949dd5ad..00000000000
--- a/arch/arm/mach-pxa/eseries.h
+++ /dev/null
@@ -1,14 +0,0 @@
-void __init eseries_fixup(struct tag *tags, char **cmdline, struct meminfo *mi);
-
-extern struct pxa2xx_udc_mach_info e7xx_udc_mach_info;
-extern struct pxaficp_platform_data e7xx_ficp_platform_data;
-extern int e7xx_irda_init(void);
-
-extern int eseries_tmio_enable(struct platform_device *dev);
-extern int eseries_tmio_disable(struct platform_device *dev);
-extern int eseries_tmio_suspend(struct platform_device *dev);
-extern int eseries_tmio_resume(struct platform_device *dev);
-extern void eseries_get_tmio_gpios(void);
-extern struct resource eseries_tmio_resources[];
-extern struct platform_device e300_tc6387xb_device;
-
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index d3de84b0dcb..e6311988add 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -296,27 +296,11 @@ static struct asic3_led asic3_leds[ASIC3_NUM_LEDS] = {
 
 static struct resource asic3_resources[] = {
         /* GPIO part */
-        [0] = {
-                .start  = ASIC3_PHYS,
-                .end    = ASIC3_PHYS + ASIC3_MAP_SIZE_16BIT - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ),
-                .end    = PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ),
-                .flags  = IORESOURCE_IRQ,
-        },
+        [0] = DEFINE_RES_MEM(ASIC3_PHYS, ASIC3_MAP_SIZE_16BIT),
+        [1] = DEFINE_RES_IRQ(PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ)),
         /* SD part */
-        [2] = {
-                .start  = ASIC3_SD_PHYS,
-                .end    = ASIC3_SD_PHYS + ASIC3_MAP_SIZE_16BIT - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [3] = {
-                .start  = PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
-                .end    = PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
-                .flags  = IORESOURCE_IRQ,
-        },
+        [2] = DEFINE_RES_MEM(ASIC3_SD_PHYS, ASIC3_MAP_SIZE_16BIT),
+        [3] = DEFINE_RES_IRQ(PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ)),
 };
 
 static struct asic3_platform_data asic3_platform_data = {
@@ -343,11 +327,7 @@ static struct platform_device asic3 = {
  */
 
 static struct resource egpio_resources[] = {
-        [0] = {
-                .start = PXA_CS5_PHYS,
-                .end   = PXA_CS5_PHYS + 0x4 - 1,
-                .flags = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM(PXA_CS5_PHYS, 0x4),
 };
 
 static struct htc_egpio_chip egpio_chips[] = {
@@ -537,11 +517,7 @@ static struct w100fb_mach_info w3220_info = {
 };
 
 static struct resource w3220_resources[] = {
-        [0] = {
-                .start  = ATI_W3220_PHYS,
-                .end    = ATI_W3220_PHYS + 0x00ffffff,
-                .flags  = IORESOURCE_MEM,
-        },
+        [0] = DEFINE_RES_MEM(ATI_W3220_PHYS, SZ_16M),
 };
 
 static struct platform_device w3220 = {
@@ -683,20 +659,12 @@ static struct pda_power_pdata power_supply_info = {
 };
 
 static struct resource power_supply_resources[] = {
-        [0] = {
-                .name  = "ac",
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
-                         IORESOURCE_IRQ_LOWEDGE,
-                .start = PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN),
-                .end   = PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN),
-        },
-        [1] = {
-                .name  = "usb",
-                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
-                         IORESOURCE_IRQ_LOWEDGE,
-                .start = PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT),
-                .end   = PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT),
-        },
+        [0] = DEFINE_RES_NAMED(PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN), 1, "ac",
+                IORESOURCE_IRQ |
+                IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE),
+        [1] = DEFINE_RES_NAMED(PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT), 1, "usb",
+                IORESOURCE_IRQ |
+                IORESOURCE_IRQ_HIGHEDGE | IORESOURCE_IRQ_LOWEDGE),
 };
 
 static struct platform_device power_supply = {
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h
index a3e5f86ef67..628819995c5 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ost.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ost.h
@@ -7,17 +7,17 @@
  * OS Timer & Match Registers
  */
 
-#define OSMR0           __REG(0x40A00000)  /* */
-#define OSMR1           __REG(0x40A00004)  /* */
-#define OSMR2           __REG(0x40A00008)  /* */
-#define OSMR3           __REG(0x40A0000C)  /* */
-#define OSMR4           __REG(0x40A00080)  /* */
-#define OSCR            __REG(0x40A00010)  /* OS Timer Counter Register */
-#define OSCR4           __REG(0x40A00040)  /* OS Timer Counter Register */
-#define OMCR4           __REG(0x40A000C0)  /* */
-#define OSSR            __REG(0x40A00014)  /* OS Timer Status Register */
-#define OWER            __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
-#define OIER            __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
+#define OSMR0           io_p2v(0x40A00000)  /* */
+#define OSMR1           io_p2v(0x40A00004)  /* */
+#define OSMR2           io_p2v(0x40A00008)  /* */
+#define OSMR3           io_p2v(0x40A0000C)  /* */
+#define OSMR4           io_p2v(0x40A00080)  /* */
+#define OSCR            io_p2v(0x40A00010)  /* OS Timer Counter Register */
+#define OSCR4           io_p2v(0x40A00040)  /* OS Timer Counter Register */
+#define OMCR4           io_p2v(0x40A000C0)  /* */
+#define OSSR            io_p2v(0x40A00014)  /* OS Timer Status Register */
+#define OWER            io_p2v(0x40A00018)  /* OS Timer Watchdog Enable Register */
+#define OIER            io_p2v(0x40A0001C)  /* OS Timer Interrupt Enable Register */
 
 #define OSSR_M3         (1 << 3)        /* Match status channel 3 */
 #define OSSR_M2         (1 << 2)        /* Match status channel 2 */
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 6bb3f47b1f1..0ca0db78790 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -456,7 +456,7 @@ static int lubbock_mci_init(struct device *dev,
         init_timer(&mmc_timer);
         mmc_timer.data = (unsigned long) data;
         return request_irq(LUBBOCK_SD_IRQ, lubbock_detect_int,
-                        IRQF_SAMPLE_RANDOM, "lubbock-sd-detect", data);
+                           0, "lubbock-sd-detect", data);
 }
 
 static int lubbock_mci_get_ro(struct device *dev)
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 2db697cd2b4..39561dcf65f 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -633,9 +633,8 @@ static struct platform_device bq24022 = {
 static int magician_mci_init(struct device *dev,
                                 irq_handler_t detect_irq, void *data)
 {
-        return request_irq(IRQ_MAGICIAN_SD, detect_irq,
-                                IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
-                                "mmc card detect", data);
+        return request_irq(IRQ_MAGICIAN_SD, detect_irq, IRQF_DISABLED,
+                           "mmc card detect", data);
 }
 
 static void magician_mci_exit(struct device *dev, void *data)
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 5905ed130e9..d89d87ae144 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -953,12 +953,12 @@ static struct i2c_board_info raumfeld_connector_i2c_board_info __initdata = {
 
 static struct eeti_ts_platform_data eeti_ts_pdata = {
         .irq_active_high = 1,
+        .irq_gpio = GPIO_TOUCH_IRQ,
 };
 
 static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = {
         .type   = "eeti_ts",
         .addr   = 0x0a,
-        .irq    = PXA_GPIO_TO_IRQ(GPIO_TOUCH_IRQ),
         .platform_data = &eeti_ts_pdata,
 };
 
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index b4528899ef0..3fab583755d 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -77,9 +77,10 @@ static void do_gpio_reset(void)
 static void do_hw_reset(void)
 {
         /* Initialize the watchdog and let it fire */
-        OWER = OWER_WME;
-        OSSR = OSSR_M3;
-        OSMR3 = OSCR + 368640;  /* ... in 100 ms */
+        writel_relaxed(OWER_WME, OWER);
+        writel_relaxed(OSSR_M3, OSSR);
+        /* ... in 100 ms */
+        writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
 }
 
 void pxa_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 3d6c9bd90de..4bc47d63698 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -35,7 +35,7 @@
 
 static u32 notrace pxa_read_sched_clock(void)
 {
-        return OSCR;
+        return readl_relaxed(OSCR);
 }
 
 
@@ -47,8 +47,8 @@ pxa_ost0_interrupt(int irq, void *dev_id)
         struct clock_event_device *c = dev_id;
 
         /* Disarm the compare/match, signal the event. */
-        OIER &= ~OIER_E0;
-        OSSR = OSSR_M0;
+        writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
+        writel_relaxed(OSSR_M0, OSSR);
         c->event_handler(c);
 
         return IRQ_HANDLED;
@@ -59,10 +59,10 @@ pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
 {
         unsigned long next, oscr;
 
-        OIER |= OIER_E0;
-        next = OSCR + delta;
-        OSMR0 = next;
-        oscr = OSCR;
+        writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
+        next = readl_relaxed(OSCR) + delta;
+        writel_relaxed(next, OSMR0);
+        oscr = readl_relaxed(OSCR);
 
         return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
 }
@@ -72,15 +72,15 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 {
         switch (mode) {
         case CLOCK_EVT_MODE_ONESHOT:
-                OIER &= ~OIER_E0;
-                OSSR = OSSR_M0;
+                writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
+                writel_relaxed(OSSR_M0, OSSR);
                 break;
 
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
                 /* initializing, released, or preparing for suspend */
-                OIER &= ~OIER_E0;
-                OSSR = OSSR_M0;
+                writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
+                writel_relaxed(OSSR_M0, OSSR);
                 break;
 
         case CLOCK_EVT_MODE_RESUME:
@@ -108,8 +108,8 @@ static void __init pxa_timer_init(void)
 {
         unsigned long clock_tick_rate = get_clock_tick_rate();
 
-        OIER = 0;
-        OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
+        writel_relaxed(0, OIER);
+        writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
 
         setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
 
@@ -122,7 +122,7 @@ static void __init pxa_timer_init(void)
 
         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 
-        clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32,
+        clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
                 clocksource_mmio_readl_up);
         clockevents_register_device(&ckevt_pxa_osmr0);
 }
@@ -132,12 +132,12 @@ static unsigned long osmr[4], oier, oscr;
 
 static void pxa_timer_suspend(void)
 {
-        osmr[0] = OSMR0;
-        osmr[1] = OSMR1;
-        osmr[2] = OSMR2;
-        osmr[3] = OSMR3;
-        oier = OIER;
-        oscr = OSCR;
+        osmr[0] = readl_relaxed(OSMR0);
+        osmr[1] = readl_relaxed(OSMR1);
+        osmr[2] = readl_relaxed(OSMR2);
+        osmr[3] = readl_relaxed(OSMR3);
+        oier = readl_relaxed(OIER);
+        oscr = readl_relaxed(OSCR);
 }
 
 static void pxa_timer_resume(void)
@@ -151,12 +151,12 @@ static void pxa_timer_resume(void)
         if (osmr[0] - oscr < MIN_OSCR_DELTA)
                 osmr[0] += MIN_OSCR_DELTA;
 
-        OSMR0 = osmr[0];
-        OSMR1 = osmr[1];
-        OSMR2 = osmr[2];
-        OSMR3 = osmr[3];
-        OIER = oier;
-        OSCR = oscr;
+        writel_relaxed(osmr[0], OSMR0);
+        writel_relaxed(osmr[1], OSMR1);
+        writel_relaxed(osmr[2], OSMR2);
+        writel_relaxed(osmr[3], OSMR3);
+        writel_relaxed(oier, OIER);
+        writel_relaxed(oscr, OSCR);
 }
 #else
 #define pxa_timer_suspend NULL
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 2b6ac00b2cd..166dd32cc1d 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -332,8 +332,8 @@ static int trizeps4_mci_init(struct device *dev, irq_handler_t mci_detect_int,
         int err;
 
         err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int,
-                IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_SAMPLE_RANDOM,
-                "MMC card detect", data);
+                          IRQF_DISABLED | IRQF_TRIGGER_RISING,
+                          "MMC card detect", data);
         if (err) {
                 printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request"
                                                 "MMC card detect IRQ\n");
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index cf0e669eaf1..3e4fa849c64 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -163,6 +163,6 @@ void __init rpc_init_irq(void)
                 }
         }
 
-        init_FIQ();
+        init_FIQ(FIQ_START);
 }
 
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index e24961109b7..d56b0f7f2b2 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -483,7 +483,7 @@ config MACH_NEO1973_GTA02
         select I2C
         select POWER_SUPPLY
         select MACH_NEO1973
-        select S3C2410_PWM
+        select S3C24XX_PWM
         select S3C_DEV_USB_HOST
         help
            Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone
@@ -493,7 +493,7 @@ config MACH_RX1950
         select S3C24XX_DCLK
         select PM_H1940 if PM
         select I2C
-        select S3C2410_PWM
+        select S3C24XX_PWM
         select S3C_DEV_NAND
         select S3C2410_IOTIMING if S3C2440_CPUFREQ
         select S3C2440_XTAL_16934400
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 8702ecfaab3..14a81c2317a 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -144,7 +144,8 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
+        /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */
+        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
 };
 
 void __init s3c2416_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index a4c5a520d99..7f689ce1be6 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = {
 
 static struct clk_lookup s3c2443_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
+        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),
 };
 
 void __init s3c2443_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index aeeb2be283f..aeb4a24ff3e 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = {
 
 static struct clk hsspi_clk = {
         .name           = "spi",
-        .devname        = "s3c64xx-spi.0",
+        .devname        = "s3c2443-spi.0",
         .parent         = &clk_p,
         .enable         = s3c2443_clkcon_enable_p,
         .ctrlbit        = S3C2443_PCLKCON_HSSPI,
@@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
+        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
 };
 
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 084604be6ad..87e75a250d5 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
@@ -182,19 +182,21 @@ static struct platform_device __initdata *smdk_devs[] = {
         &smdk_led7,
 };
 
+static const struct gpio smdk_led_gpios[] = {
+        { S3C2410_GPF(4), GPIOF_OUT_INIT_HIGH, NULL },
+        { S3C2410_GPF(5), GPIOF_OUT_INIT_HIGH, NULL },
+        { S3C2410_GPF(6), GPIOF_OUT_INIT_HIGH, NULL },
+        { S3C2410_GPF(7), GPIOF_OUT_INIT_HIGH, NULL },
+};
+
 void __init smdk_machine_init(void)
 {
         /* Configure the LEDs (even if we have no LED support)*/
 
-        s3c_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
-        s3c_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
-        s3c_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
-        s3c_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
-
-        s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
-        s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
-        s3c2410_gpio_setpin(S3C2410_GPF(6), 1);
-        s3c2410_gpio_setpin(S3C2410_GPF(7), 1);
+        int ret = gpio_request_array(smdk_led_gpios,
+                                     ARRAY_SIZE(smdk_led_gpios));
+        if (!WARN_ON(ret < 0))
+                gpio_free_array(smdk_led_gpios, ARRAY_SIZE(smdk_led_gpios));
 
         if (machine_is_smdk2443())
                 smdk_nand_info.twrph0 = 50;
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 56cdd34cce4..0c9e9a785ef 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -41,7 +41,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-serial.h>
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h b/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h
deleted file mode 100644
index 4c38b39b741..00000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-pmu.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      Vincent Sanders <vince@simtec.co.uk>
- *
- * Machine BAST - Power Management chip
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_BASTPMU_H
-#define __ASM_ARCH_BASTPMU_H "08_OCT_2004"
-
-#define BASTPMU_REG_IDENT       (0x00)
-#define BASTPMU_REG_VERSION     (0x01)
-#define BASTPMU_REG_DDCCTRL     (0x02)
-#define BASTPMU_REG_POWER       (0x03)
-#define BASTPMU_REG_RESET       (0x04)
-#define BASTPMU_REG_GWO         (0x05)
-#define BASTPMU_REG_WOL         (0x06)
-#define BASTPMU_REG_WOR         (0x07)
-#define BASTPMU_REG_UID         (0x09)
-
-#define BASTPMU_EEPROM          (0xC0)
-
-#define BASTPMU_EEP_UID         (BASTPMU_EEPROM + 0)
-#define BASTPMU_EEP_WOL         (BASTPMU_EEPROM + 8)
-#define BASTPMU_EEP_WOR         (BASTPMU_EEPROM + 9)
-
-#define BASTPMU_IDENT_0         0x53
-#define BASTPMU_IDENT_1         0x42
-#define BASTPMU_IDENT_2         0x50
-#define BASTPMU_IDENT_3         0x4d
-
-#define BASTPMU_RESET_GUARD     (0x55)
-
-#endif /* __ASM_ARCH_BASTPMU_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index 454831b6603..ee99fd56c04 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -24,7 +24,8 @@
 */
 
 enum dma_ch {
-        DMACH_XD0,
+        DMACH_DT_PROP = -1,     /* not yet supported, do not use */
+        DMACH_XD0 = 0,
         DMACH_XD1,
         DMACH_SDI,
         DMACH_SPI0,
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
index 019ea86057f..3890a05948f 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
@@ -93,26 +93,5 @@ enum s3c_gpio_number {
 #define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
 #define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
 
-/* compatibility until drivers can be modified */
-
-#define S3C2410_GPA0    S3C2410_GPA(0)
-#define S3C2410_GPA1    S3C2410_GPA(1)
-#define S3C2410_GPA3    S3C2410_GPA(3)
-#define S3C2410_GPA7    S3C2410_GPA(7)
-
-#define S3C2410_GPE0    S3C2410_GPE(0)
-#define S3C2410_GPE1    S3C2410_GPE(1)
-#define S3C2410_GPE2    S3C2410_GPE(2)
-#define S3C2410_GPE3    S3C2410_GPE(3)
-#define S3C2410_GPE4    S3C2410_GPE(4)
-#define S3C2410_GPE5    S3C2410_GPE(5)
-#define S3C2410_GPE6    S3C2410_GPE(6)
-#define S3C2410_GPE7    S3C2410_GPE(7)
-#define S3C2410_GPE8    S3C2410_GPE(8)
-#define S3C2410_GPE9    S3C2410_GPE(9)
-#define S3C2410_GPE10   S3C2410_GPE(10)
-
-#define S3C2410_GPH10   S3C2410_GPH(10)
-
 #endif /* __MACH_GPIONRS_H */
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/gta02.h b/arch/arm/mach-s3c24xx/include/mach/gta02.h
index 3a56a229cac..21739348215 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gta02.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gta02.h
@@ -3,82 +3,13 @@
 
 #include <mach/regs-gpio.h>
 
-/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
-#define GTA02v1_SYSTEM_REV      0x00000310
-#define GTA02v2_SYSTEM_REV      0x00000320
-#define GTA02v3_SYSTEM_REV      0x00000330
-#define GTA02v4_SYSTEM_REV      0x00000340
-#define GTA02v5_SYSTEM_REV      0x00000350
-/* since A7 is basically same as A6, we use A6 PCB ID */
-#define GTA02v6_SYSTEM_REV      0x00000360
-
-#define GTA02_GPIO_n3DL_GSM     S3C2410_GPA(13) /* v1 + v2 + v3 only */
-
-#define GTA02_GPIO_PWR_LED1     S3C2410_GPB(0)
-#define GTA02_GPIO_PWR_LED2     S3C2410_GPB(1)
 #define GTA02_GPIO_AUX_LED      S3C2410_GPB(2)
-#define GTA02_GPIO_VIBRATOR_ON  S3C2410_GPB(3)
-#define GTA02_GPIO_MODEM_RST    S3C2410_GPB(5)
-#define GTA02_GPIO_BT_EN        S3C2410_GPB(6)
-#define GTA02_GPIO_MODEM_ON     S3C2410_GPB(7)
-#define GTA02_GPIO_EXTINT8      S3C2410_GPB(8)
 #define GTA02_GPIO_USB_PULLUP   S3C2410_GPB(9)
-
-#define GTA02_GPIO_PIO5         S3C2410_GPC(5)  /* v3 + v4 only */
-
-#define GTA02v3_GPIO_nG1_CS     S3C2410_GPD(12) /* v3 + v4 only */
-#define GTA02v3_GPIO_nG2_CS     S3C2410_GPD(13) /* v3 + v4 only */
-#define GTA02v5_GPIO_HDQ        S3C2410_GPD(14)   /* v5 + */
-
-#define GTA02_GPIO_nG1_INT      S3C2410_GPF(0)
-#define GTA02_GPIO_IO1          S3C2410_GPF(1)
-#define GTA02_GPIO_PIO_2        S3C2410_GPF(2)  /* v2 + v3 + v4 only */
-#define GTA02_GPIO_JACK_INSERT  S3C2410_GPF(4)
-#define GTA02_GPIO_WLAN_GPIO1   S3C2410_GPF(5)  /* v2 + v3 + v4 only */
 #define GTA02_GPIO_AUX_KEY      S3C2410_GPF(6)
 #define GTA02_GPIO_HOLD_KEY     S3C2410_GPF(7)
-
-#define GTA02_GPIO_3D_IRQ       S3C2410_GPG(4)
-#define GTA02v2_GPIO_nG2_INT    S3C2410_GPG(8)  /* v2 + v3 + v4 only */
-#define GTA02v3_GPIO_nUSB_OC    S3C2410_GPG(9)  /* v3 + v4 only */
-#define GTA02v3_GPIO_nUSB_FLT   S3C2410_GPG(10) /* v3 + v4 only */
-#define GTA02v3_GPIO_nGSM_OC    S3C2410_GPG(11) /* v3 + v4 only */
-
 #define GTA02_GPIO_AMP_SHUT     S3C2410_GPJ(1)  /* v2 + v3 + v4 only */
-#define GTA02v1_GPIO_WLAN_GPIO10        S3C2410_GPJ(2)
 #define GTA02_GPIO_HP_IN        S3C2410_GPJ(2)  /* v2 + v3 + v4 only */
-#define GTA02_GPIO_INT0         S3C2410_GPJ(3)  /* v2 + v3 + v4 only */
-#define GTA02_GPIO_nGSM_EN      S3C2410_GPJ(4)
-#define GTA02_GPIO_3D_RESET     S3C2410_GPJ(5)
-#define GTA02_GPIO_nDL_GSM      S3C2410_GPJ(6)  /* v4 + v5 only */
-#define GTA02_GPIO_WLAN_GPIO0   S3C2410_GPJ(7)
-#define GTA02v1_GPIO_BAT_ID     S3C2410_GPJ(8)
-#define GTA02_GPIO_KEEPACT      S3C2410_GPJ(8)
-#define GTA02v1_GPIO_HP_IN      S3C2410_GPJ(10)
-#define GTA02_CHIP_PWD          S3C2410_GPJ(11) /* v2 + v3 + v4 only */
-#define GTA02_GPIO_nWLAN_RESET  S3C2410_GPJ(12) /* v2 + v3 + v4 only */
 
-#define GTA02_IRQ_GSENSOR_1     IRQ_EINT0
-#define GTA02_IRQ_MODEM         IRQ_EINT1
-#define GTA02_IRQ_PIO_2         IRQ_EINT2       /* v2 + v3 + v4 only */
-#define GTA02_IRQ_nJACK_INSERT  IRQ_EINT4
-#define GTA02_IRQ_WLAN_GPIO1    IRQ_EINT5
-#define GTA02_IRQ_AUX           IRQ_EINT6
-#define GTA02_IRQ_nHOLD         IRQ_EINT7
 #define GTA02_IRQ_PCF50633      IRQ_EINT9
-#define GTA02_IRQ_3D            IRQ_EINT12
-#define GTA02_IRQ_GSENSOR_2     IRQ_EINT16      /* v2 + v3 + v4 only */
-#define GTA02v3_IRQ_nUSB_OC     IRQ_EINT17      /* v3 + v4 only */
-#define GTA02v3_IRQ_nUSB_FLT    IRQ_EINT18      /* v3 + v4 only */
-#define GTA02v3_IRQ_nGSM_OC     IRQ_EINT19      /* v3 + v4 only */
-
-/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */
-#define GTA02_PCB_ID1_0         S3C2410_GPC(13)
-#define GTA02_PCB_ID1_1         S3C2410_GPC(15)
-#define GTA02_PCB_ID1_2         S3C2410_GPD(0)
-#define GTA02_PCB_ID2_0         S3C2410_GPD(3)
-#define GTA02_PCB_ID2_1         S3C2410_GPD(4)
-
-int gta02_get_pcb_revision(void);
 
 #endif /* _GTA02_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
index cac1ad6b582..a11a638bd59 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
@@ -302,7 +302,7 @@
 /* S3C2410:
  * Port G consists of 8 GPIO/IRQ/Special function
  *
- * GPGCON has 2 bits for each of the input pins on port F
+ * GPGCON has 2 bits for each of the input pins on port G
  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
  *
  * pull up works like all other ports.
@@ -366,7 +366,7 @@
 
 /* Port H consists of11 GPIO/serial/Misc pins
  *
- * GPGCON has 2 bits for each of the input pins on port F
+ * GPHCON has 2 bits for each of the input pins on port H
  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
  *
  * pull up works like all other ports.
@@ -427,6 +427,19 @@
  * for the 2412/2413 from the 2410/2440/2442
 */
 
+/*
+ * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits
+ * for each of the pins on port J.
+ *   00 - input, 01 output, 10 - camera
+ *
+ * Pull up works like all other ports.
+ */
+
+#define S3C2413_GPJCON     S3C2410_GPIOREG(0x80)
+#define S3C2413_GPJDAT     S3C2410_GPIOREG(0x84)
+#define S3C2413_GPJUP      S3C2410_GPIOREG(0x88)
+#define S3C2413_GPJSLPCON  S3C2410_GPIOREG(0x8C)
+
 /* S3C2443 and above */
 #define S3C2440_GPJCON     S3C2410_GPIOREG(0xD0)
 #define S3C2440_GPJDAT     S3C2410_GPIOREG(0xD4)
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h
deleted file mode 100644
index 19575e06111..00000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2440 GPIO J register definitions
-*/
-
-
-#ifndef __ASM_ARCH_REGS_GPIOJ_H
-#define __ASM_ARCH_REGS_GPIOJ_H "gpioj"
-
-/* Port J consists of 13 GPIO/Camera pins
- *
- * GPJCON has 2 bits for each of the input pins on port F
- *   00 = 0 input, 1 output, 2 Camera
- *
- * pull up works like all other ports.
-*/
-
-#define S3C2413_GPJCON          S3C2410_GPIOREG(0x80)
-#define S3C2413_GPJDAT          S3C2410_GPIOREG(0x84)
-#define S3C2413_GPJUP           S3C2410_GPIOREG(0x88)
-#define S3C2413_GPJSLPCON       S3C2410_GPIOREG(0x8C)
-
-#define S3C2440_GPJ0_OUTP       (0x01 << 0)
-#define S3C2440_GPJ0_CAMDATA0   (0x02 << 0)
-
-#define S3C2440_GPJ1_OUTP       (0x01 << 2)
-#define S3C2440_GPJ1_CAMDATA1   (0x02 << 2)
-
-#define S3C2440_GPJ2_OUTP       (0x01 << 4)
-#define S3C2440_GPJ2_CAMDATA2   (0x02 << 4)
-
-#define S3C2440_GPJ3_OUTP       (0x01 << 6)
-#define S3C2440_GPJ3_CAMDATA3   (0x02 << 6)
-
-#define S3C2440_GPJ4_OUTP       (0x01 << 8)
-#define S3C2440_GPJ4_CAMDATA4   (0x02 << 8)
-
-#define S3C2440_GPJ5_OUTP       (0x01 << 10)
-#define S3C2440_GPJ5_CAMDATA5   (0x02 << 10)
-
-#define S3C2440_GPJ6_OUTP       (0x01 << 12)
-#define S3C2440_GPJ6_CAMDATA6   (0x02 << 12)
-
-#define S3C2440_GPJ7_OUTP       (0x01 << 14)
-#define S3C2440_GPJ7_CAMDATA7   (0x02 << 14)
-
-#define S3C2440_GPJ8_OUTP       (0x01 << 16)
-#define S3C2440_GPJ8_CAMPCLK    (0x02 << 16)
-
-#define S3C2440_GPJ9_OUTP       (0x01 << 18)
-#define S3C2440_GPJ9_CAMVSYNC   (0x02 << 18)
-
-#define S3C2440_GPJ10_OUTP      (0x01 << 20)
-#define S3C2440_GPJ10_CAMHREF   (0x02 << 20)
-
-#define S3C2440_GPJ11_OUTP      (0x01 << 22)
-#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
-
-#define S3C2440_GPJ12_OUTP      (0x01 << 24)
-#define S3C2440_GPJ12_CAMRESET  (0x02 << 24)
-
-#endif  /* __ASM_ARCH_REGS_GPIOJ_H */
-
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 0f29f64a3ee..92e1f93a6bc 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -71,7 +71,6 @@
 
 #include <mach/regs-irq.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-gpioj.h>
 #include <mach/fb.h>
 
 #include <plat/usb-control.h>
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index f092b188ab7..bd6d2525deb 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -634,8 +634,8 @@ static void __init mini2440_init(void)
         s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND);
 
         /* Turn the backlight early on */
-        WARN_ON(gpio_request(S3C2410_GPG(4), "backlight"));
-        gpio_direction_output(S3C2410_GPG(4), 1);
+        WARN_ON(gpio_request_one(S3C2410_GPG(4), GPIOF_OUT_INIT_HIGH, NULL));
+        gpio_free(S3C2410_GPG(4));
 
         /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
         s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index b868dddcb83..678bbca2b5e 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -47,7 +47,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <mach/regs-gpio.h>
 #include <mach/leds-gpio.h>
 #include <mach/regs-lcd.h>
 #include <plat/regs-serial.h>
@@ -325,8 +324,9 @@ static void __init qt2410_machine_init(void)
         }
         s3c24xx_fb_set_platdata(&qt2410_fb_info);
 
-        s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
+        /* set initial state of the LED GPIO */
+        WARN_ON(gpio_request_one(S3C2410_GPB(0), GPIOF_OUT_INIT_HIGH, NULL));
+        gpio_free(S3C2410_GPB(0));
 
         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
         s3c_i2c0_set_platdata(NULL);
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index a6762aae472..7ee73f27f20 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -42,7 +42,6 @@
 #include <asm/mach-types.h>
 
 #include <mach/regs-gpio.h>
-#include <mach/regs-gpioj.h>
 #include <mach/regs-lcd.h>
 #include <mach/h1940.h>
 #include <mach/fb.h>
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
index 03f706dd600..949ae05e07c 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
@@ -77,8 +77,10 @@ static void s3c2410_pm_prepare(void)
                 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
         }
 
-        if ( machine_is_aml_m5900() )
-                s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
+        if (machine_is_aml_m5900()) {
+                gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL);
+                gpio_free(S3C2410_GPF(2));
+        }
 
         if (machine_is_rx1950()) {
                 /* According to S3C2442 user's manual, page 7-17,
@@ -103,8 +105,10 @@ static void s3c2410_pm_resume(void)
         tmp &= S3C2410_GSTATUS2_OFFRESET;
         __raw_writel(tmp, S3C2410_GSTATUS2);
 
-        if ( machine_is_aml_m5900() )
-                s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
+        if (machine_is_aml_m5900()) {
+                gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
+                gpio_free(S3C2410_GPF(2));
+        }
 }
 
 struct syscore_ops s3c2410_pm_syscore_ops = {
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index d04588506ec..c60f67a75af 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -26,7 +26,6 @@
 #include <asm/irq.h>
 
 #include <mach/regs-power.h>
-#include <mach/regs-gpioj.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-dsc.h>
 
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index d4bc7f960bb..6c5f4031ff0 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -39,7 +39,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-gpioj.h>
 #include <mach/regs-dsc.h>
 #include <plat/regs-spi.h>
 #include <mach/regs-s3c2412.h>
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 6f74118f60c..b0b60a1154d 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -36,7 +36,6 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-gpioj.h>
 #include <mach/regs-dsc.h>
 
 #include <plat/s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
index 5712c85f39b..3d47e023ce9 100644
--- a/arch/arm/mach-s3c24xx/setup-spi.c
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -13,20 +13,12 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .tx_st_done     = 21,
-        .high_speed     = 1,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         /* enable hsspi bit in misccr */
         s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
diff --git a/arch/arm/mach-s3c24xx/setup-ts.c b/arch/arm/mach-s3c24xx/setup-ts.c
index ed263866367..4e11affce3a 100644
--- a/arch/arm/mach-s3c24xx/setup-ts.c
+++ b/arch/arm/mach-s3c24xx/setup-ts.c
@@ -16,7 +16,6 @@
 struct platform_device; /* don't need the contents */
 
 #include <mach/hardware.h>
-#include <mach/regs-gpio.h>
 
 /**
  * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems
@@ -27,8 +26,5 @@ struct platform_device; /* don't need the contents */
  */
 void s3c24xx_ts_cfg_gpio(struct platform_device *dev)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPG(12), S3C2410_GPG12_XMON);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPG13_nXPON);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPG14_YMON);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPG15_nYPON);
+        s3c_gpio_cfgpin_range(S3C2410_GPG(12), 4, S3C_GPIO_SFN(3));
 }
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 52f079a691c..28041e83dc8 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = S3C_CLKCON_PCLK_KEYPAD,
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s3c6410-spi.0",
                 .parent         = &clk_p,
                 .enable         = s3c64xx_pclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_PCLK_SPI0,
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s3c6410-spi.1",
                 .parent         = &clk_p,
                 .enable         = s3c64xx_pclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
@@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = {
 
 static struct clk clk_48m_spi0 = {
         .name           = "spi_48m",
-        .devname        = "s3c64xx-spi.0",
+        .devname        = "s3c6410-spi.0",
         .parent         = &clk_48m,
         .enable         = s3c64xx_sclk_ctrl,
         .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
@@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = {
 
 static struct clk clk_48m_spi1 = {
         .name           = "spi_48m",
-        .devname        = "s3c64xx-spi.1",
+        .devname        = "s3c6410-spi.1",
         .parent         = &clk_48m,
         .enable         = s3c64xx_sclk_ctrl,
         .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
@@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
 static struct clksrc_clk clk_sclk_spi0 = {
         .clk    = {
                 .name           = "spi-bus",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s3c6410-spi.0",
                 .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
                 .enable         = s3c64xx_sclk_ctrl,
         },
@@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
         .clk    = {
                 .name           = "spi-bus",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s3c6410-spi.1",
                 .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
                 .enable         = s3c64xx_sclk_ctrl,
         },
@@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
+        CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
+        CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
 };
 
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
index 4cb2f951f1e..4c3c9994fc2 100644
--- a/arch/arm/mach-s3c64xx/include/mach/crag6410.h
+++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
@@ -13,9 +13,7 @@
 
 #include <linux/gpio.h>
 
-#define BANFF_PMIC_IRQ_BASE             IRQ_BOARD_START
-#define GLENFARCLAS_PMIC_IRQ_BASE       (IRQ_BOARD_START + 64)
-#define CODEC_IRQ_BASE                  (IRQ_BOARD_START + 128)
+#define GLENFARCLAS_PMIC_IRQ_BASE       IRQ_BOARD_START
 
 #define PCA935X_GPIO_BASE               GPIO_BOARD_START
 #define CODEC_GPIO_BASE                 (GPIO_BOARD_START + 8)
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index fe1a98cf0e4..57b1ff4b2d7 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -21,6 +21,7 @@
  */
 enum dma_ch {
         /* DMA0/SDMA0 */
+        DMACH_DT_PROP = -1, /* not yet supported, do not use */
         DMACH_UART0 = 0,
         DMACH_UART0_SRC2,
         DMACH_UART1,
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index fcf3dcabb69..c0537f40a3d 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -12,6 +12,9 @@
  * published by the Free Software Foundation.
  */
 
+#ifndef __MACH_S3C64XX_PM_CORE_H
+#define __MACH_S3C64XX_PM_CORE_H __FILE__
+
 #include <mach/regs-gpio.h>
 
 static inline void s3c_pm_debug_init_uart(void)
@@ -113,3 +116,4 @@ static inline void samsung_pm_saved_gpios(void)
 
         __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
 }
+#endif /* __MACH_S3C64XX_PM_CORE_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
deleted file mode 100644
index 9d0c43b4b68..00000000000
--- a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
- *
- * Copyright (C) 2009 Samsung Electronics Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __S3C64XX_PLAT_SPI_CLKS_H
-#define __S3C64XX_PLAT_SPI_CLKS_H __FILE__
-
-#define S3C64XX_SPI_SRCCLK_PCLK         0
-#define S3C64XX_SPI_SRCCLK_SPIBUS       1
-#define S3C64XX_SPI_SRCCLK_48M          2
-
-#endif /* __S3C64XX_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index 7a27f5603c7..9e382e7c77c 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -29,7 +29,6 @@
 #include <mach/crag6410.h>
 
 static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
-        .set_level = gpio_set_value,
         .line = S3C64XX_GPC(3),
 };
 
@@ -39,6 +38,7 @@ static struct spi_board_info wm1253_devs[] = {
                 .bus_num        = 0,
                 .chip_select    = 0,
                 .mode           = SPI_MODE_0,
+                .irq            = S3C_EINT(5),
                 .controller_data = &wm0010_spi_csinfo,
         },
 };
@@ -168,7 +168,6 @@ static struct wm8994_pdata wm8994_pdata = {
         .gpio_defaults = {
                 0x3,          /* IRQ out, active high, CMOS */
         },
-        .irq_base = CODEC_IRQ_BASE,
         .ldo = {
                  { .init_data = &wm8994_ldo1, },
                  { .init_data = &wm8994_ldo2, },
@@ -182,6 +181,11 @@ static const struct i2c_board_info wm1277_devs[] = {
         },
 };
 
+static const struct i2c_board_info wm5102_devs[] = {
+        { I2C_BOARD_INFO("wm5102", 0x1a),
+          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2, },
+};
+
 static const struct i2c_board_info wm6230_i2c_devs[] = {
         { I2C_BOARD_INFO("wm9081", 0x6c),
           .platform_data = &wm9081_pdata, },
@@ -209,6 +213,7 @@ static __devinitdata const struct {
           .spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) },
         { .id = 0x32, .name = "XXXX-EV1 Caol Illa" },
         { .id = 0x33, .name = "XXXX-EV1 Oban" },
+        { .id = 0x34, .name = "WM0010-6320-CS42 Balblair" },
         { .id = 0x39, .name = "1254-EV1 Dallas Dhu",
           .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
         { .id = 0x3a, .name = "1259-EV1 Tobermory",
@@ -218,6 +223,8 @@ static __devinitdata const struct {
         { .id = 0x3c, .name = "1273-EV1 Longmorn" },
         { .id = 0x3d, .name = "1277-EV1 Littlemill",
           .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
+        { .id = 0x3e, .name = "WM5102-6271-EV1-CS127",
+          .i2c_devs = wm5102_devs, .num_i2c_devs = ARRAY_SIZE(wm5102_devs) },
 };
 
 static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index d0c352d861f..09cd81207a3 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -171,7 +171,7 @@ static struct fb_videomode crag6410_lcd_timing = {
 };
 
 /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
-static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = {
+static struct s3c_fb_platdata crag6410_lcd_pdata __devinitdata = {
         .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
         .vtiming        = &crag6410_lcd_timing,
         .win[0]         = &crag6410_fb_win0,
@@ -181,7 +181,7 @@ static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = {
 
 /* 2x6 keypad */
 
-static uint32_t crag6410_keymap[] __initdata = {
+static uint32_t crag6410_keymap[] __devinitdata = {
         /* KEY(row, col, keycode) */
         KEY(0, 0, KEY_VOLUMEUP),
         KEY(0, 1, KEY_HOME),
@@ -197,12 +197,12 @@ static uint32_t crag6410_keymap[] __initdata = {
         KEY(1, 5, KEY_CAMERA),
 };
 
-static struct matrix_keymap_data crag6410_keymap_data __initdata = {
+static struct matrix_keymap_data crag6410_keymap_data __devinitdata = {
         .keymap         = crag6410_keymap,
         .keymap_size    = ARRAY_SIZE(crag6410_keymap),
 };
 
-static struct samsung_keypad_platdata crag6410_keypad_data __initdata = {
+static struct samsung_keypad_platdata crag6410_keypad_data __devinitdata = {
         .keymap_data    = &crag6410_keymap_data,
         .rows           = 2,
         .cols           = 6,
@@ -373,11 +373,11 @@ static struct wm831x_buckv_pdata vddarm_pdata = {
         .dvs_gpio = S3C64XX_GPK(0),
 };
 
-static struct regulator_consumer_supply vddarm_consumers[] __initdata = {
+static struct regulator_consumer_supply vddarm_consumers[] __devinitdata = {
         REGULATOR_SUPPLY("vddarm", NULL),
 };
 
-static struct regulator_init_data vddarm __initdata = {
+static struct regulator_init_data vddarm __devinitdata = {
         .constraints = {
                 .name = "VDDARM",
                 .min_uV = 1000000,
@@ -391,11 +391,11 @@ static struct regulator_init_data vddarm __initdata = {
         .driver_data = &vddarm_pdata,
 };
 
-static struct regulator_consumer_supply vddint_consumers[] __initdata = {
+static struct regulator_consumer_supply vddint_consumers[] __devinitdata = {
         REGULATOR_SUPPLY("vddint", NULL),
 };
 
-static struct regulator_init_data vddint __initdata = {
+static struct regulator_init_data vddint __devinitdata = {
         .constraints = {
                 .name = "VDDINT",
                 .min_uV = 1000000,
@@ -408,27 +408,27 @@ static struct regulator_init_data vddint __initdata = {
         .supply_regulator = "WALLVDD",
 };
 
-static struct regulator_init_data vddmem __initdata = {
+static struct regulator_init_data vddmem __devinitdata = {
         .constraints = {
                 .name = "VDDMEM",
                 .always_on = 1,
         },
 };
 
-static struct regulator_init_data vddsys __initdata = {
+static struct regulator_init_data vddsys __devinitdata = {
         .constraints = {
                 .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS",
                 .always_on = 1,
         },
 };
 
-static struct regulator_consumer_supply vddmmc_consumers[] __initdata = {
+static struct regulator_consumer_supply vddmmc_consumers[] __devinitdata = {
         REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
         REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"),
         REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
 };
 
-static struct regulator_init_data vddmmc __initdata = {
+static struct regulator_init_data vddmmc __devinitdata = {
         .constraints = {
                 .name = "VDDMMC,UH",
                 .always_on = 1,
@@ -438,7 +438,7 @@ static struct regulator_init_data vddmmc __initdata = {
         .supply_regulator = "WALLVDD",
 };
 
-static struct regulator_init_data vddotgi __initdata = {
+static struct regulator_init_data vddotgi __devinitdata = {
         .constraints = {
                 .name = "VDDOTGi",
                 .always_on = 1,
@@ -446,7 +446,7 @@ static struct regulator_init_data vddotgi __initdata = {
         .supply_regulator = "WALLVDD",
 };
 
-static struct regulator_init_data vddotg __initdata = {
+static struct regulator_init_data vddotg __devinitdata = {
         .constraints = {
                 .name = "VDDOTG",
                 .always_on = 1,
@@ -454,7 +454,7 @@ static struct regulator_init_data vddotg __initdata = {
         .supply_regulator = "WALLVDD",
 };
 
-static struct regulator_init_data vddhi __initdata = {
+static struct regulator_init_data vddhi __devinitdata = {
         .constraints = {
                 .name = "VDDHI",
                 .always_on = 1,
@@ -462,7 +462,7 @@ static struct regulator_init_data vddhi __initdata = {
         .supply_regulator = "WALLVDD",
 };
 
-static struct regulator_init_data vddadc __initdata = {
+static struct regulator_init_data vddadc __devinitdata = {
         .constraints = {
                 .name = "VDDADC,VDDDAC",
                 .always_on = 1,
@@ -470,7 +470,7 @@ static struct regulator_init_data vddadc __initdata = {
         .supply_regulator = "WALLVDD",
 };
 
-static struct regulator_init_data vddmem0 __initdata = {
+static struct regulator_init_data vddmem0 __devinitdata = {
         .constraints = {
                 .name = "VDDMEM0",
                 .always_on = 1,
@@ -478,7 +478,7 @@ static struct regulator_init_data vddmem0 __initdata = {
         .supply_regulator = "WALLVDD",
 };
 
-static struct regulator_init_data vddpll __initdata = {
+static struct regulator_init_data vddpll __devinitdata = {
         .constraints = {
                 .name = "VDDPLL",
                 .always_on = 1,
@@ -486,7 +486,7 @@ static struct regulator_init_data vddpll __initdata = {
         .supply_regulator = "WALLVDD",
 };
 
-static struct regulator_init_data vddlcd __initdata = {
+static struct regulator_init_data vddlcd __devinitdata = {
         .constraints = {
                 .name = "VDDLCD",
                 .always_on = 1,
@@ -494,7 +494,7 @@ static struct regulator_init_data vddlcd __initdata = {
         .supply_regulator = "WALLVDD",
 };
 
-static struct regulator_init_data vddalive __initdata = {
+static struct regulator_init_data vddalive __devinitdata = {
         .constraints = {
                 .name = "VDDALIVE",
                 .always_on = 1,
@@ -502,30 +502,29 @@ static struct regulator_init_data vddalive __initdata = {
         .supply_regulator = "WALLVDD",
 };
 
-static struct wm831x_backup_pdata banff_backup_pdata __initdata = {
+static struct wm831x_backup_pdata banff_backup_pdata __devinitdata = {
         .charger_enable = 1,
         .vlim = 2500,  /* mV */
         .ilim = 200,   /* uA */
 };
 
-static struct wm831x_status_pdata banff_red_led __initdata = {
+static struct wm831x_status_pdata banff_red_led __devinitdata = {
         .name = "banff:red:",
         .default_src = WM831X_STATUS_MANUAL,
 };
 
-static struct wm831x_status_pdata banff_green_led __initdata = {
+static struct wm831x_status_pdata banff_green_led __devinitdata = {
         .name = "banff:green:",
         .default_src = WM831X_STATUS_MANUAL,
 };
 
-static struct wm831x_touch_pdata touch_pdata __initdata = {
+static struct wm831x_touch_pdata touch_pdata __devinitdata = {
         .data_irq = S3C_EINT(26),
         .pd_irq = S3C_EINT(27),
 };
 
-static struct wm831x_pdata crag_pmic_pdata __initdata = {
+static struct wm831x_pdata crag_pmic_pdata __devinitdata = {
         .wm831x_num = 1,
-        .irq_base = BANFF_PMIC_IRQ_BASE,
         .gpio_base = BANFF_PMIC_GPIO_BASE,
         .soft_shutdown = true,
 
@@ -568,7 +567,7 @@ static struct wm831x_pdata crag_pmic_pdata __initdata = {
         .touch = &touch_pdata,
 };
 
-static struct i2c_board_info i2c_devs0[] __initdata = {
+static struct i2c_board_info i2c_devs0[] __devinitdata = {
         { I2C_BOARD_INFO("24c08", 0x50), },
         { I2C_BOARD_INFO("tca6408", 0x20),
           .platform_data = &crag6410_pca_data,
@@ -583,12 +582,12 @@ static struct s3c2410_platform_i2c i2c0_pdata = {
         .frequency = 400000,
 };
 
-static struct regulator_consumer_supply pvdd_1v2_consumers[] __initdata = {
+static struct regulator_consumer_supply pvdd_1v2_consumers[] __devinitdata = {
         REGULATOR_SUPPLY("DCVDD", "spi0.0"),
         REGULATOR_SUPPLY("AVDD", "spi0.0"),
 };
 
-static struct regulator_init_data pvdd_1v2 __initdata = {
+static struct regulator_init_data pvdd_1v2 __devinitdata = {
         .constraints = {
                 .name = "PVDD_1V2",
                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
@@ -598,7 +597,7 @@ static struct regulator_init_data pvdd_1v2 __initdata = {
         .num_consumer_supplies = ARRAY_SIZE(pvdd_1v2_consumers),
 };
 
-static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
+static struct regulator_consumer_supply pvdd_1v8_consumers[] __devinitdata = {
         REGULATOR_SUPPLY("LDOVDD", "1-001a"),
         REGULATOR_SUPPLY("PLLVDD", "1-001a"),
         REGULATOR_SUPPLY("DBVDD", "1-001a"),
@@ -612,7 +611,7 @@ static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
         REGULATOR_SUPPLY("DBVDD", "spi0.0"),
 };
 
-static struct regulator_init_data pvdd_1v8 __initdata = {
+static struct regulator_init_data pvdd_1v8 __devinitdata = {
         .constraints = {
                 .name = "PVDD_1V8",
                 .always_on = 1,
@@ -622,12 +621,12 @@ static struct regulator_init_data pvdd_1v8 __initdata = {
         .num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers),
 };
 
-static struct regulator_consumer_supply pvdd_3v3_consumers[] __initdata = {
+static struct regulator_consumer_supply pvdd_3v3_consumers[] __devinitdata = {
         REGULATOR_SUPPLY("MICVDD", "1-001a"),
         REGULATOR_SUPPLY("AVDD1", "1-001a"),
 };
 
-static struct regulator_init_data pvdd_3v3 __initdata = {
+static struct regulator_init_data pvdd_3v3 __devinitdata = {
         .constraints = {
                 .name = "PVDD_3V3",
                 .always_on = 1,
@@ -637,7 +636,7 @@ static struct regulator_init_data pvdd_3v3 __initdata = {
         .num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers),
 };
 
-static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
+static struct wm831x_pdata glenfarclas_pmic_pdata __devinitdata = {
         .wm831x_num = 2,
         .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
         .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
@@ -669,7 +668,7 @@ static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
         },
 };
 
-static struct i2c_board_info i2c_devs1[] __initdata = {
+static struct i2c_board_info i2c_devs1[] __devinitdata = {
         { I2C_BOARD_INFO("wm8311", 0x34),
           .irq = S3C_EINT(0),
           .platform_data = &glenfarclas_pmic_pdata },
@@ -799,7 +798,7 @@ static void __init crag6410_machine_init(void)
         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 
         samsung_keypad_set_platdata(&crag6410_keypad_data);
-        s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1);
+        s3c64xx_spi0_set_platdata(NULL, 0, 1);
 
         platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
 
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index df3103d450e..0fe4f1503f4 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -566,7 +566,6 @@ static struct wm831x_status_pdata wm1192_led8_pdata = {
 
 static struct wm831x_pdata smdk6410_wm1192_pdata = {
         .pre_init = wm1192_pre_init,
-        .irq_base = IRQ_BOARD_START,
 
         .backlight = &wm1192_backlight_pdata,
         .dcdc = {
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
index d9592ad7a82..4dc53450d71 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -9,19 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .tx_st_done     = 21,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
                                 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -30,13 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .tx_st_done     = 21,
-};
-
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
         s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
                                 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index ee1e8e7f563..000445596ec 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = (1 << 17),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5p64x0-spi.0",
                 .parent         = &clk_pclk_low.clk,
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 21),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5p64x0-spi.1",
                 .parent         = &clk_pclk_low.clk,
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 22),
@@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = {
 static struct clksrc_clk clk_sclk_spi0 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5p64x0-spi.0",
                 .ctrlbit        = (1 << 20),
                 .enable         = s5p64x0_sclk_ctrl,
         },
@@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5p64x0-spi.1",
                 .ctrlbit        = (1 << 21),
                 .enable         = s5p64x0_sclk_ctrl,
         },
@@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index dae6a13f43b..f3e0ef3d27c 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -236,13 +236,13 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = (1 << 17),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5p64x0-spi.0",
                 .parent         = &clk_pclk_low.clk,
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 21),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5p64x0-spi.1",
                 .parent         = &clk_pclk_low.clk,
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 22),
@@ -528,7 +528,7 @@ static struct clksrc_clk clk_sclk_uclk = {
 static struct clksrc_clk clk_sclk_spi0 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5p64x0-spi.0",
                 .ctrlbit        = (1 << 20),
                 .enable         = s5p64x0_sclk_ctrl,
         },
@@ -540,7 +540,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5p64x0-spi.1",
                 .ctrlbit        = (1 << 21),
                 .enable         = s5p64x0_sclk_ctrl,
         },
@@ -562,8 +562,8 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 2ee5dc069b3..9c4ce085f58 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -36,8 +36,6 @@
 #include <plat/devs.h>
 #include <plat/irqs.h>
 
-static u64 dma_dmamask = DMA_BIT_MASK(32);
-
 static u8 s5p6440_pdma_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
diff --git a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
deleted file mode 100644
index 170a20a9643..00000000000
--- a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SPI_CLKS_H
-#define __ASM_ARCH_SPI_CLKS_H __FILE__
-
-#define S5P64X0_SPI_SRCCLK_PCLK         0
-#define S5P64X0_SPI_SRCCLK_SCLK         1
-
-#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
index e9b84124035..7664356720c 100644
--- a/arch/arm/mach-s5p64x0/setup-spi.c
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -9,21 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/cpu.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         if (soc_is_s5p6450())
                 s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
@@ -36,13 +25,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
         if (soc_is_s5p6450())
                 s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 16eca4ea201..926219791f0 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = (1 << 5),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5pc100-spi.0",
                 .parent         = &clk_div_d1_bus.clk,
                 .enable         = s5pc100_d1_4_ctrl,
                 .ctrlbit        = (1 << 6),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5pc100-spi.1",
                 .parent         = &clk_div_d1_bus.clk,
                 .enable         = s5pc100_d1_4_ctrl,
                 .ctrlbit        = (1 << 7),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "s5pc100-spi.2",
                 .parent         = &clk_div_d1_bus.clk,
                 .enable         = s5pc100_d1_4_ctrl,
                 .ctrlbit        = (1 << 8),
@@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = {
 
 static struct clk clk_48m_spi0 = {
         .name           = "spi_48m",
-        .devname        = "s3c64xx-spi.0",
+        .devname        = "s5pc100-spi.0",
         .parent         = &clk_mout_48m.clk,
         .enable         = s5pc100_sclk0_ctrl,
         .ctrlbit        = (1 << 7),
@@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = {
 
 static struct clk clk_48m_spi1 = {
         .name           = "spi_48m",
-        .devname        = "s3c64xx-spi.1",
+        .devname        = "s5pc100-spi.1",
         .parent         = &clk_mout_48m.clk,
         .enable         = s5pc100_sclk0_ctrl,
         .ctrlbit        = (1 << 8),
@@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = {
 
 static struct clk clk_48m_spi2 = {
         .name           = "spi_48m",
-        .devname        = "s3c64xx-spi.2",
+        .devname        = "s5pc100-spi.2",
         .parent         = &clk_mout_48m.clk,
         .enable         = s5pc100_sclk0_ctrl,
         .ctrlbit        = (1 << 9),
@@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
 static struct clksrc_clk clk_sclk_spi0 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5pc100-spi.0",
                 .ctrlbit        = (1 << 4),
                 .enable         = s5pc100_sclk0_ctrl,
         },
@@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5pc100-spi.1",
                 .ctrlbit        = (1 << 5),
                 .enable         = s5pc100_sclk0_ctrl,
         },
@@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = {
 static struct clksrc_clk clk_sclk_spi2 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "s5pc100-spi.2",
                 .ctrlbit        = (1 << 6),
                 .enable         = s5pc100_sclk0_ctrl,
         },
@@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
-        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
+        CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
+        CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
+        CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
+        CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
 };
 
 void __init s5pc100_register_clocks(void)
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index afd8db2d599..b1418409709 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -33,8 +33,6 @@
 #include <mach/irqs.h>
 #include <mach/dma.h>
 
-static u64 dma_dmamask = DMA_BIT_MASK(32);
-
 static u8 pdma0_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
diff --git a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
deleted file mode 100644
index 65e426370bb..00000000000
--- a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __S5PC100_PLAT_SPI_CLKS_H
-#define __S5PC100_PLAT_SPI_CLKS_H __FILE__
-
-#define S5PC100_SPI_SRCCLK_PCLK         0
-#define S5PC100_SPI_SRCCLK_48M          1
-#define S5PC100_SPI_SRCCLK_SPIBUS       2
-
-#endif /* __S5PC100_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
index 431a6f747ca..183567961de 100644
--- a/arch/arm/mach-s5pc100/setup-spi.c
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -9,20 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .high_speed     = 1,
-        .tx_st_done     = 21,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
                                 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -31,14 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .high_speed     = 1,
-        .tx_st_done     = 21,
-};
-
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
         s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
                                 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -47,14 +30,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .high_speed     = 1,
-        .tx_st_done     = 21,
-};
-
-int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi2_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
         s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 88e983b0c82..77185c38188 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -152,6 +152,7 @@ config MACH_SMDKV210
         select S3C_DEV_I2C1
         select S3C_DEV_I2C2
         select S3C_DEV_RTC
+        select S3C_DEV_USB_HSOTG
         select S3C_DEV_WDT
         select S5P_DEV_FIMC0
         select S5P_DEV_FIMC1
@@ -170,6 +171,7 @@ config MACH_SMDKV210
         select S5PV210_SETUP_IDE
         select S5PV210_SETUP_KEYPAD
         select S5PV210_SETUP_SDHCI
+        select S5PV210_SETUP_USB_PHY
         help
           Machine support for Samsung SMDKV210
 
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 09609d50961..fcdf52dbcc4 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = (1 << 11),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5pv210-spi.0",
                 .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<12),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5pv210-spi.1",
                 .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<13),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "s5pv210-spi.2",
                 .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<14),
@@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = {
 static struct clksrc_clk clk_sclk_spi0 = {
         .clk            = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5pv210-spi.0",
                 .enable         = s5pv210_clk_mask0_ctrl,
                 .ctrlbit        = (1 << 16),
         },
@@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
         .clk            = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5pv210-spi.1",
                 .enable         = s5pv210_clk_mask0_ctrl,
                 .ctrlbit        = (1 << 17),
         },
@@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
         CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
 };
 
 void __init s5pv210_register_clocks(void)
diff --git a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h
deleted file mode 100644
index 02acded5f73..00000000000
--- a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/spi-clocks.h
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __S5PV210_PLAT_SPI_CLKS_H
-#define __S5PV210_PLAT_SPI_CLKS_H __FILE__
-
-#define S5PV210_SPI_SRCCLK_PCLK         0
-#define S5PV210_SPI_SRCCLK_SCLK         1
-
-#endif /* __S5PV210_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index af528f9e97f..78028df86c5 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -600,10 +600,17 @@ static void aquila_setup_sdhci(void)
         s3c_sdhci2_set_platdata(&aquila_hsmmc2_data);
 };
 
+/* Audio device */
+static struct platform_device aquila_device_audio = {
+        .name = "smdk-audio",
+        .id = -1,
+};
+
 static struct platform_device *aquila_devices[] __initdata = {
         &aquila_i2c_gpio_pmic,
         &aquila_i2c_gpio5,
         &aquila_device_gpiokeys,
+        &aquila_device_audio,
         &s3c_device_fb,
         &s5p_device_onenand,
         &s3c_device_hsmmc0,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index bf5087c2b7f..822a5595068 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -859,12 +859,19 @@ static struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
         .num_clients    = ARRAY_SIZE(goni_camera_sensors),
 };
 
+/* Audio device */
+static struct platform_device goni_device_audio = {
+        .name = "smdk-audio",
+        .id = -1,
+};
+
 static struct platform_device *goni_devices[] __initdata = {
         &s3c_device_fb,
         &s5p_device_onenand,
         &goni_spi_gpio,
         &goni_i2c_gpio_pmic,
         &goni_i2c_gpio5,
+        &goni_device_audio,
         &mmc2_fixed_voltage,
         &goni_device_gpiokeys,
         &s5p_device_mfc,
@@ -901,7 +908,7 @@ static void __init goni_sound_init(void)
 static void __init goni_map_io(void)
 {
         s5pv210_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
         s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
 }
@@ -959,8 +966,6 @@ static void __init goni_machine_init(void)
         /* KEYPAD */
         samsung_keypad_set_platdata(&keypad_data);
 
-        clk_xusbxti.rate = 24000000;
-
         platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices));
 }
 
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 0d7ddec88eb..918b23d71fd 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -19,6 +19,7 @@
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/pwm_backlight.h>
+#include <linux/platform_data/s3c-hsotg.h>
 
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
@@ -47,6 +48,7 @@
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
 #include <plat/mfc.h>
+#include <plat/clock.h>
 
 #include "common.h"
 
@@ -203,6 +205,9 @@ static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
         .setup_gpio     = s5pv210_fb_gpio_setup_24bpp,
 };
 
+/* USB OTG */
+static struct s3c_hsotg_plat smdkv210_hsotg_pdata;
+
 static struct platform_device *smdkv210_devices[] __initdata = {
         &s3c_device_adc,
         &s3c_device_cfcon,
@@ -216,6 +221,7 @@ static struct platform_device *smdkv210_devices[] __initdata = {
         &s3c_device_i2c2,
         &s3c_device_rtc,
         &s3c_device_ts,
+        &s3c_device_usb_hsotg,
         &s3c_device_wdt,
         &s5p_device_fimc0,
         &s5p_device_fimc1,
@@ -279,7 +285,7 @@ static struct platform_pwm_backlight_data smdkv210_bl_data = {
 static void __init smdkv210_map_io(void)
 {
         s5pv210_init_io(NULL, 0);
-        s3c24xx_init_clocks(24000000);
+        s3c24xx_init_clocks(clk_xusbxti.rate);
         s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
         s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
 }
@@ -314,6 +320,8 @@ static void __init smdkv210_machine_init(void)
 
         samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
 
+        s3c_hsotg_set_platdata(&smdkv210_hsotg_pdata);
+
         platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
 }
 
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
index f43c5048a37..81aecc162f8 100644
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -9,20 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
@@ -33,14 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index d1dc7f1a239..d673211f121 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -362,7 +362,7 @@ static void __init assabet_init(void)
 static void __init map_sa1100_gpio_regs( void )
 {
         unsigned long phys = __PREG(GPLR) & PMD_MASK;
-        unsigned long virt = io_p2v(phys);
+        unsigned long virt = (unsigned long)io_p2v(phys);
         int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
         pmd_t *pmd;
 
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index 19b2053f5af..e8f4d1e1923 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -87,6 +87,7 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/cpufreq.h>
+#include <linux/io.h>
 
 #include <asm/cputype.h>
 
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 675bf8ef97e..48c45b0c92b 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -19,6 +19,7 @@
 #include <linux/cpufreq.h>
 #include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/moduleparam.h>
 #include <linux/types.h>
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 3f2d1b60188..0ac6cc08a19 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -830,14 +830,14 @@
  *                      (read/write).
  */
 
-#define OSMR0           __REG(0x90000000)  /* OS timer Match Reg. 0 */
-#define OSMR1           __REG(0x90000004)  /* OS timer Match Reg. 1 */
-#define OSMR2           __REG(0x90000008)  /* OS timer Match Reg. 2 */
-#define OSMR3           __REG(0x9000000c)  /* OS timer Match Reg. 3 */
-#define OSCR    __REG(0x90000010)  /* OS timer Counter Reg. */
-#define OSSR    __REG(0x90000014        )  /* OS timer Status Reg. */
-#define OWER    __REG(0x90000018        )  /* OS timer Watch-dog Enable Reg. */
-#define OIER    __REG(0x9000001C        )  /* OS timer Interrupt Enable Reg. */
+#define OSMR0           io_p2v(0x90000000)  /* OS timer Match Reg. 0 */
+#define OSMR1           io_p2v(0x90000004)  /* OS timer Match Reg. 1 */
+#define OSMR2           io_p2v(0x90000008)  /* OS timer Match Reg. 2 */
+#define OSMR3           io_p2v(0x9000000c)  /* OS timer Match Reg. 3 */
+#define OSCR            io_p2v(0x90000010)  /* OS timer Counter Reg. */
+#define OSSR            io_p2v(0x90000014)  /* OS timer Status Reg. */
+#define OWER            io_p2v(0x90000018)  /* OS timer Watch-dog Enable Reg. */
+#define OIER            io_p2v(0x9000001C)  /* OS timer Interrupt Enable Reg. */
 
 #define OSSR_M(Nb)                      /* Match detected [0..3]           */ \
                         (0x00000001 << (Nb))
diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h
index a38fc4f5424..6a9eecf3137 100644
--- a/arch/arm/mach-sa1100/include/mach/gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/gpio.h
@@ -24,6 +24,7 @@
 #ifndef __ASM_ARCH_SA1100_GPIO_H
 #define __ASM_ARCH_SA1100_GPIO_H
 
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 99f5856d8de..cbedd75a9d6 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -32,7 +32,7 @@
 #define PIO_START       0x80000000      /* physical start of IO space */
 
 #define io_p2v( x )             \
-   ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
+   IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
 #define io_v2p( x )             \
    ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
 
@@ -47,6 +47,8 @@
 #define CPU_SA1110_ID   (0x6901b110)
 #define CPU_SA1110_MASK (0xfffffff0)
 
+#define __MREG(x)       IOMEM(io_p2v(x))
+
 #ifndef __ASSEMBLY__
 
 #include <asm/cputype.h>
@@ -56,7 +58,7 @@
 #define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
 #define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
 
-# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
+# define __REG(x)       (*((volatile unsigned long __iomem *)io_p2v(x)))
 # define __PREG(x)      (io_v2p((unsigned long)&(x)))
 
 static inline unsigned long get_clock_tick_rate(void)
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
index 6cb39ddde65..5cf71da60e4 100644
--- a/arch/arm/mach-sa1100/include/mach/uncompress.h
+++ b/arch/arm/mach-sa1100/include/mach/uncompress.h
@@ -8,6 +8,8 @@
 
 #include "hardware.h"
 
+#define IOMEM(x)        (x)
+
 /*
  * The following code assumes the serial port has already been
  * initialized by the bootloader.  We search for the first enabled
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 516ccc25d7f..2124f1fc2fb 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/ioport.h>
 #include <linux/syscore_ops.h>
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index b412fc09c80..7f07f08d896 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -18,6 +18,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <mach/jornada720.h>
diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c
index 040540fb7d8..30fc3b2bf55 100644
--- a/arch/arm/mach-sa1100/leds-cerf.c
+++ b/arch/arm/mach-sa1100/leds-cerf.c
@@ -4,6 +4,7 @@
  * Author: ???
  */
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-sa1100/leds-hackkit.c b/arch/arm/mach-sa1100/leds-hackkit.c
index 6a2352436e6..f8e47235bab 100644
--- a/arch/arm/mach-sa1100/leds-hackkit.c
+++ b/arch/arm/mach-sa1100/leds-hackkit.c
@@ -10,6 +10,7 @@
  * as cpu led, the green one is used as timer led.
  */
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c
index a51830c60e5..50a5b143b46 100644
--- a/arch/arm/mach-sa1100/leds-lart.c
+++ b/arch/arm/mach-sa1100/leds-lart.c
@@ -10,6 +10,7 @@
  *  pace of the LED.
  */
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 690cf0ce5c0..6645d1e31f1 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -23,6 +23,7 @@
  *                              Storage is local on the stack now.
  */
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/time.h>
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 30cc6721665..85863741ef8 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -38,9 +38,9 @@ ENTRY(sa1100_finish_suspend)
         orr     r4, r4, #MDREFR_K1DB2
         ldr     r5, =PPCR
 
-        @ Pre-load __udelay into the I-cache
+        @ Pre-load __loop_udelay into the I-cache
         mov     r0, #1
-        bl      __udelay
+        bl      __loop_udelay
         mov     r0, r0
 
         @ The following must all exist in a single cache line to
@@ -53,11 +53,11 @@ ENTRY(sa1100_finish_suspend)
         @ delay 90us and set CPU PLL to lowest speed
         @ fixes resume problem on high speed SA1110
         mov     r0, #90
-        bl      __udelay
+        bl      __loop_udelay
         mov     r1, #0
         str     r1, [r5]
         mov     r0, #90
-        bl      __udelay
+        bl      __loop_udelay
 
         /*
          * SA1110 SDRAM controller workaround.  register values:
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 6af26e8d55e..80702c9ecc7 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -22,7 +22,7 @@
 
 static u32 notrace sa1100_read_sched_clock(void)
 {
-        return OSCR;
+        return readl_relaxed(OSCR);
 }
 
 #define MIN_OSCR_DELTA 2
@@ -32,8 +32,8 @@ static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
         struct clock_event_device *c = dev_id;
 
         /* Disarm the compare/match, signal the event. */
-        OIER &= ~OIER_E0;
-        OSSR = OSSR_M0;
+        writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
+        writel_relaxed(OSSR_M0, OSSR);
         c->event_handler(c);
 
         return IRQ_HANDLED;
@@ -44,10 +44,10 @@ sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
 {
         unsigned long next, oscr;
 
-        OIER |= OIER_E0;
-        next = OSCR + delta;
-        OSMR0 = next;
-        oscr = OSCR;
+        writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
+        next = readl_relaxed(OSCR) + delta;
+        writel_relaxed(next, OSMR0);
+        oscr = readl_relaxed(OSCR);
 
         return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
 }
@@ -59,8 +59,8 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
         case CLOCK_EVT_MODE_ONESHOT:
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
-                OIER &= ~OIER_E0;
-                OSSR = OSSR_M0;
+                writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
+                writel_relaxed(OSSR_M0, OSSR);
                 break;
 
         case CLOCK_EVT_MODE_RESUME:
@@ -86,8 +86,8 @@ static struct irqaction sa1100_timer_irq = {
 
 static void __init sa1100_timer_init(void)
 {
-        OIER = 0;
-        OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
+        writel_relaxed(0, OIER);
+        writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
 
         setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
 
@@ -100,7 +100,7 @@ static void __init sa1100_timer_init(void)
 
         setup_irq(IRQ_OST0, &sa1100_timer_irq);
 
-        clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
+        clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
                 clocksource_mmio_readl_up);
         clockevents_register_device(&ckevt_sa1100_osmr0);
 }
@@ -110,26 +110,26 @@ unsigned long osmr[4], oier;
 
 static void sa1100_timer_suspend(void)
 {
-        osmr[0] = OSMR0;
-        osmr[1] = OSMR1;
-        osmr[2] = OSMR2;
-        osmr[3] = OSMR3;
-        oier = OIER;
+        osmr[0] = readl_relaxed(OSMR0);
+        osmr[1] = readl_relaxed(OSMR1);
+        osmr[2] = readl_relaxed(OSMR2);
+        osmr[3] = readl_relaxed(OSMR3);
+        oier = readl_relaxed(OIER);
 }
 
 static void sa1100_timer_resume(void)
 {
-        OSSR = 0x0f;
-        OSMR0 = osmr[0];
-        OSMR1 = osmr[1];
-        OSMR2 = osmr[2];
-        OSMR3 = osmr[3];
-        OIER = oier;
+        writel_relaxed(0x0f, OSSR);
+        writel_relaxed(osmr[0], OSMR0);
+        writel_relaxed(osmr[1], OSMR1);
+        writel_relaxed(osmr[2], OSMR2);
+        writel_relaxed(osmr[3], OSMR3);
+        writel_relaxed(oier, OIER);
 
         /*
          * OSMR0 is the system timer: make sure OSCR is sufficiently behind
          */
-        OSCR = OSMR0 - LATCH;
+        writel_relaxed(OSMR0 - LATCH, OSCR);
 }
 #else
 #define sa1100_timer_suspend NULL
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index df33909205e..4cacc2d22fb 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -19,6 +19,7 @@ config ARCH_SH7372
         select CPU_V7
         select SH_CLK_CPG
         select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARM_CPU_SUSPEND if PM || CPU_IDLE
 
 config ARCH_SH73A0
         bool "SH-Mobile AG5 (R8A73A00)"
@@ -58,6 +59,7 @@ config MACH_G4EVM
         bool "G4EVM board"
         depends on ARCH_SH7377
         select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
 config MACH_AP4EVB
         bool "AP4EVB board"
@@ -65,6 +67,7 @@ config MACH_AP4EVB
         select ARCH_REQUIRE_GPIOLIB
         select SH_LCD_MIPI_DSI
         select SND_SOC_AK4642 if SND_SIMPLE_CARD
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
 choice
         prompt "AP4EVB LCD panel selection"
@@ -83,6 +86,7 @@ config MACH_AG5EVM
         bool "AG5EVM board"
         select ARCH_REQUIRE_GPIOLIB
         select SH_LCD_MIPI_DSI
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         depends on ARCH_SH73A0
 
 config MACH_MACKEREL
@@ -90,15 +94,18 @@ config MACH_MACKEREL
         depends on ARCH_SH7372
         select ARCH_REQUIRE_GPIOLIB
         select SND_SOC_AK4642 if SND_SIMPLE_CARD
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
 config MACH_KOTA2
         bool "KOTA2 board"
         select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         depends on ARCH_SH73A0
 
 config MACH_BONITO
         bool "bonito board"
         select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         depends on ARCH_R8A7740
 
 config MACH_ARMADILLO800EVA
@@ -106,22 +113,28 @@ config MACH_ARMADILLO800EVA
         depends on ARCH_R8A7740
         select ARCH_REQUIRE_GPIOLIB
         select USE_OF
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
+        select SND_SOC_WM8978 if SND_SIMPLE_CARD
 
 config MACH_MARZEN
         bool "MARZEN board"
         depends on ARCH_R8A7779
         select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
 config MACH_KZM9D
         bool "KZM9D board"
         depends on ARCH_EMEV2
         select USE_OF
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
 config MACH_KZM9G
         bool "KZM-A9-GT board"
         depends on ARCH_SH73A0
         select ARCH_REQUIRE_GPIOLIB
         select USE_OF
+        select SND_SOC_AK4642 if SND_SIMPLE_CARD
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
 comment "SH-Mobile System Configuration"
 
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 8aa1962c22a..0df5ae6740c 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -39,7 +39,9 @@ obj-$(CONFIG_ARCH_R8A7740)	+= entry-intc.o
 # PM objects
 obj-$(CONFIG_SUSPEND)           += suspend.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
+obj-$(CONFIG_ARCH_SHMOBILE)     += pm-rmobile.o
 obj-$(CONFIG_ARCH_SH7372)       += pm-sh7372.o sleep-sh7372.o
+obj-$(CONFIG_ARCH_R8A7740)      += pm-r8a7740.o
 obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o
 
 # Board objects
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 5a6f22f05e9..d82c010fdfc 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -27,6 +27,8 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/dma-mapping.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/serial_sci.h>
 #include <linux/smsc911x.h>
 #include <linux/gpio.h>
@@ -52,6 +54,12 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/traps.h>
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static struct resource smsc9220_resources[] = {
         [0] = {
                 .start          = 0x14000000,
@@ -142,6 +150,13 @@ static struct platform_device fsi_device = {
         .resource       = fsi_resources,
 };
 
+/* Fixed 1.8V regulator to be used by MMCIF */
+static struct regulator_consumer_supply fixed1v8_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
+};
+
 static struct resource sh_mmcif_resources[] = {
         [0] = {
                 .name   = "MMCIF",
@@ -364,6 +379,13 @@ static struct platform_device mipidsi0_device = {
         },
 };
 
+/* Fixed 2.8V regulators to be used by SDHI0 */
+static struct regulator_consumer_supply fixed2v8_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
 /* SDHI0 */
 static struct sh_mobile_sdhi_info sdhi0_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
@@ -408,8 +430,57 @@ static struct platform_device sdhi0_device = {
         },
 };
 
-void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
+/* Fixed 3.3V regulator to be used by SDHI1 */
+static struct regulator_consumer_supply cn4_power_consumers[] =
 {
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
+};
+
+static struct regulator_init_data cn4_power_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(cn4_power_consumers),
+        .consumer_supplies      = cn4_power_consumers,
+};
+
+static struct fixed_voltage_config cn4_power_info = {
+        .supply_name = "CN4 SD/MMC Vdd",
+        .microvolts = 3300000,
+        .gpio = GPIO_PORT114,
+        .enable_high = 1,
+        .init_data = &cn4_power_init_data,
+};
+
+static struct platform_device cn4_power = {
+        .name = "reg-fixed-voltage",
+        .id   = 2,
+        .dev  = {
+                .platform_data = &cn4_power_info,
+        },
+};
+
+static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
+{
+        static int power_gpio = -EINVAL;
+
+        if (power_gpio < 0) {
+                int ret = gpio_request(GPIO_PORT114, "sdhi1_power");
+                if (!ret) {
+                        power_gpio = GPIO_PORT114;
+                        gpio_direction_output(power_gpio, 0);
+                }
+        }
+
+        /*
+         * If requesting the GPIO above failed, it means, that the regulator got
+         * probed and grabbed the GPIO, but we don't know, whether the sdhi
+         * driver already uses the regulator. If it doesn't, we have to toggle
+         * the GPIO ourselves, even though it is now owned by the fixed
+         * regulator driver. We have to live with the race in case the driver
+         * gets unloaded and the GPIO freed between these two steps.
+         */
         gpio_set_value(GPIO_PORT114, state);
 }
 
@@ -455,6 +526,7 @@ static struct platform_device sdhi1_device = {
 };
 
 static struct platform_device *ag5evm_devices[] __initdata = {
+        &cn4_power,
         &eth_device,
         &keysc_device,
         &fsi_device,
@@ -468,6 +540,12 @@ static struct platform_device *ag5evm_devices[] __initdata = {
 
 static void __init ag5evm_init(void)
 {
+        regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
+                                     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
+        regulator_register_always_on(1, "fixed-2.8V", fixed2v8_power_consumers,
+                                     ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
+        regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         sh73a0_pinmux_init();
 
         /* enable SCIFA2 */
@@ -562,8 +640,6 @@ static void __init ag5evm_init(void)
         gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
         gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
         gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
-        gpio_request(GPIO_PORT114, "sdhi1_power");
-        gpio_direction_output(GPIO_PORT114, 0);
 
 #ifdef CONFIG_CACHE_L2X0
         /* Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index ace60246a5d..f172ca85905 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -34,6 +34,8 @@
 #include <linux/i2c.h>
 #include <linux/i2c/tsc2007.h>
 #include <linux/io.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_clk.h>
@@ -159,6 +161,27 @@
  * CN12: 3.3v
  */
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply fixed1v8_power_consumers[] =
+{
+        /* J22 default position: 1.8V */
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
+};
+
+static struct regulator_consumer_supply fixed3v3_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 /* MTD */
 static struct mtd_partition nor_flash_partitions[] = {
         {
@@ -1138,21 +1161,6 @@ static void __init fsi_init_pm_clock(void)
         clk_put(fsia_ick);
 }
 
-/*
- * FIXME !!
- *
- * gpio_no_direction
- * are quick_hack.
- *
- * current gpio frame work doesn't have
- * the method to control only pull up/down/free.
- * this function should be replaced by correct gpio function
- */
-static void __init gpio_no_direction(u32 addr)
-{
-        __raw_writeb(0x00, addr);
-}
-
 /* TouchScreen */
 #ifdef CONFIG_AP4EVB_QHD
 # define GPIO_TSC_IRQ   GPIO_FN_IRQ28_123
@@ -1224,6 +1232,12 @@ static void __init ap4evb_init(void)
         u32 srcr4;
         struct clk *clk;
 
+        regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
+                                     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
+        regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+        regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         /* External clock source */
         clk_set_rate(&sh7372_dv_clki_clk, 27000000);
 
@@ -1302,8 +1316,8 @@ static void __init ap4evb_init(void)
 
         gpio_request(GPIO_PORT9, NULL);
         gpio_request(GPIO_PORT10, NULL);
-        gpio_no_direction(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
-        gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
+        gpio_direction_none(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
+        gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
 
         /* card detect pin for MMC slot (CN7) */
         gpio_request(GPIO_PORT41, NULL);
@@ -1447,14 +1461,14 @@ static void __init ap4evb_init(void)
 
         platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
 
-        sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc1_device);
-        sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
-        sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc1_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
 
-        sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
-        sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
 
         hdmi_init_pm_clock();
         fsi_init_pm_clock();
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 9bd135531d7..453a6e50db8 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -28,6 +28,8 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/sh_eth.h>
 #include <linux/videodev2.h>
 #include <linux/usb/renesas_usbhs.h>
@@ -37,14 +39,20 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
+#include <mach/r8a7740.h>
+#include <media/mt9t112.h>
+#include <media/sh_mobile_ceu.h>
+#include <media/soc_camera.h>
 #include <asm/page.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/cache-l2x0.h>
-#include <mach/r8a7740.h>
 #include <video/sh_mobile_lcdc.h>
+#include <video/sh_mobile_hdmi.h>
+#include <sound/sh_fsi.h>
+#include <sound/simple_card.h>
 
 /*
  * CON1         Camera Module
@@ -108,6 +116,14 @@
  */
 
 /*
+ * FSI-WM8978
+ *
+ * this command is required when playback.
+ *
+ * # amixer set "Headphone" 50
+ */
+
+/*
  * USB function
  *
  * When you use USB Function,
@@ -117,14 +133,8 @@
  * These are a little bit complex.
  * see
  *      usbhsf_power_ctrl()
- *
- * CAUTION
- *
- * It uses autonomy mode for USB hotplug at this point
- * (= usbhs_private.platform_callback.get_vbus is NULL),
- * since we don't know what's happen on PM control
- * on this workaround.
  */
+#define IRQ7            evt2irq(0x02e0)
 #define USBCR1          0xe605810a
 #define USBH            0xC6700000
 #define USBH_USBCTR     0x10834
@@ -204,6 +214,20 @@ static void usbhsf_power_ctrl(struct platform_device *pdev,
         }
 }
 
+static int usbhsf_get_vbus(struct platform_device *pdev)
+{
+        return gpio_get_value(GPIO_PORT209);
+}
+
+static irqreturn_t usbhsf_interrupt(int irq, void *data)
+{
+        struct platform_device *pdev = data;
+
+        renesas_usbhs_call_notify_hotplug(pdev);
+
+        return IRQ_HANDLED;
+}
+
 static void usbhsf_hardware_exit(struct platform_device *pdev)
 {
         struct usbhsf_private *priv = usbhsf_get_priv(pdev);
@@ -227,11 +251,14 @@ static void usbhsf_hardware_exit(struct platform_device *pdev)
         priv->host      = NULL;
         priv->func      = NULL;
         priv->usbh_base = NULL;
+
+        free_irq(IRQ7, pdev);
 }
 
 static int usbhsf_hardware_init(struct platform_device *pdev)
 {
         struct usbhsf_private *priv = usbhsf_get_priv(pdev);
+        int ret;
 
         priv->phy       = clk_get(&pdev->dev, "phy");
         priv->usb24     = clk_get(&pdev->dev, "usb24");
@@ -251,6 +278,14 @@ static int usbhsf_hardware_init(struct platform_device *pdev)
                 return -EIO;
         }
 
+        ret = request_irq(IRQ7, usbhsf_interrupt, IRQF_TRIGGER_NONE,
+                          dev_name(&pdev->dev), pdev);
+        if (ret) {
+                dev_err(&pdev->dev, "request_irq err\n");
+                return ret;
+        }
+        irq_set_irq_type(IRQ7, IRQ_TYPE_EDGE_BOTH);
+
         /* usb24 use 1/1 of parent clock (= usb24s = 24MHz) */
         clk_set_rate(priv->usb24,
                      clk_get_rate(clk_get_parent(priv->usb24)));
@@ -262,6 +297,7 @@ static struct usbhsf_private usbhsf_private = {
         .info = {
                 .platform_callback = {
                         .get_id         = usbhsf_get_id,
+                        .get_vbus       = usbhsf_get_vbus,
                         .hardware_init  = usbhsf_hardware_init,
                         .hardware_exit  = usbhsf_hardware_exit,
                         .power_ctrl     = usbhsf_power_ctrl,
@@ -269,6 +305,8 @@ static struct usbhsf_private usbhsf_private = {
                 .driver_param = {
                         .buswait_bwait          = 5,
                         .detection_delay        = 5,
+                        .d0_rx_id       = SHDMA_SLAVE_USBHS_RX,
+                        .d1_tx_id       = SHDMA_SLAVE_USBHS_TX,
                 },
         }
 };
@@ -384,14 +422,112 @@ static struct platform_device lcdc0_device = {
         },
 };
 
+/*
+ * LCDC1/HDMI
+ */
+static struct sh_mobile_hdmi_info hdmi_info = {
+        .flags          = HDMI_OUTPUT_PUSH_PULL |
+                          HDMI_OUTPUT_POLARITY_HI |
+                          HDMI_32BIT_REG |
+                          HDMI_HAS_HTOP1 |
+                          HDMI_SND_SRC_SPDIF,
+};
+
+static struct resource hdmi_resources[] = {
+        [0] = {
+                .name   = "HDMI",
+                .start  = 0xe6be0000,
+                .end    = 0xe6be03ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x1700),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .name   = "HDMI emma3pf",
+                .start  = 0xe6be4000,
+                .end    = 0xe6be43ff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device hdmi_device = {
+        .name           = "sh-mobile-hdmi",
+        .num_resources  = ARRAY_SIZE(hdmi_resources),
+        .resource       = hdmi_resources,
+        .id             = -1,
+        .dev    = {
+                .platform_data  = &hdmi_info,
+        },
+};
+
+static const struct fb_videomode lcdc1_mode = {
+        .name           = "HDMI 720p",
+        .xres           = 1280,
+        .yres           = 720,
+        .pixclock       = 13468,
+        .left_margin    = 220,
+        .right_margin   = 110,
+        .hsync_len      = 40,
+        .upper_margin   = 20,
+        .lower_margin   = 5,
+        .vsync_len      = 5,
+        .refresh        = 60,
+        .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
+};
+
+static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
+        .clock_source   = LCDC_CLK_PERIPHERAL, /* HDMI clock */
+        .ch[0] = {
+                .chan                   = LCDC_CHAN_MAINLCD,
+                .fourcc                 = V4L2_PIX_FMT_RGB565,
+                .interface_type         = RGB24,
+                .clock_divider          = 1,
+                .flags                  = LCDC_FLAGS_DWPOL,
+                .lcd_modes              = &lcdc1_mode,
+                .num_modes              = 1,
+                .tx_dev                 = &hdmi_device,
+                .panel_cfg = {
+                        .width  = 1280,
+                        .height = 720,
+                },
+        },
+};
+
+static struct resource hdmi_lcdc_resources[] = {
+        [0] = {
+                .name   = "LCDC1",
+                .start  = 0xfe944000,
+                .end    = 0xfe948000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x1780),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device hdmi_lcdc_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .num_resources  = ARRAY_SIZE(hdmi_lcdc_resources),
+        .resource       = hdmi_lcdc_resources,
+        .id             = 1,
+        .dev    = {
+                .platform_data  = &hdmi_lcdc_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+
 /* GPIO KEY */
-#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
+#define GPIO_KEY(c, g, d, ...) \
+        { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
 
 static struct gpio_keys_button gpio_buttons[] = {
-        GPIO_KEY(KEY_POWER,     GPIO_PORT99,    "SW1"),
-        GPIO_KEY(KEY_BACK,      GPIO_PORT100,   "SW2"),
-        GPIO_KEY(KEY_MENU,      GPIO_PORT97,    "SW3"),
-        GPIO_KEY(KEY_HOME,      GPIO_PORT98,    "SW4"),
+        GPIO_KEY(KEY_POWER,     GPIO_PORT99,    "SW3", .wakeup = 1),
+        GPIO_KEY(KEY_BACK,      GPIO_PORT100,   "SW4"),
+        GPIO_KEY(KEY_MENU,      GPIO_PORT97,    "SW5"),
+        GPIO_KEY(KEY_HOME,      GPIO_PORT98,    "SW6"),
 };
 
 static struct gpio_keys_platform_data gpio_key_info = {
@@ -407,6 +543,17 @@ static struct platform_device gpio_keys_device = {
         },
 };
 
+/* Fixed 3.3V regulator to be used by SDHI0, SDHI1, MMCIF */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
+};
+
 /* SDHI0 */
 /*
  * FIXME
@@ -418,6 +565,8 @@ static struct platform_device gpio_keys_device = {
  */
 #define IRQ31   evt2irq(0x33E0)
 static struct sh_mobile_sdhi_info sdhi0_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\
                           MMC_CAP_NEEDS_POLL,
         .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -458,6 +607,8 @@ static struct platform_device sdhi0_device = {
 
 /* SDHI1 */
 static struct sh_mobile_sdhi_info sdhi1_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
         .tmio_ocr_mask  = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
@@ -532,12 +683,209 @@ static struct platform_device sh_mmcif_device = {
         .resource       = sh_mmcif_resources,
 };
 
+/* Camera */
+static int mt9t111_power(struct device *dev, int mode)
+{
+        struct clk *mclk = clk_get(NULL, "video1");
+
+        if (IS_ERR(mclk)) {
+                dev_err(dev, "can't get video1 clock\n");
+                return -EINVAL;
+        }
+
+        if (mode) {
+                /* video1 (= CON1 camera) expect 24MHz */
+                clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
+                clk_enable(mclk);
+                gpio_direction_output(GPIO_PORT158, 1);
+        } else {
+                gpio_direction_output(GPIO_PORT158, 0);
+                clk_disable(mclk);
+        }
+
+        clk_put(mclk);
+
+        return 0;
+}
+
+static struct i2c_board_info i2c_camera_mt9t111 = {
+        I2C_BOARD_INFO("mt9t112", 0x3d),
+};
+
+static struct mt9t112_camera_info mt9t111_info = {
+        .divider = { 16, 0, 0, 7, 0, 10, 14, 7, 7 },
+};
+
+static struct soc_camera_link mt9t111_link = {
+        .i2c_adapter_id = 0,
+        .bus_id         = 0,
+        .board_info     = &i2c_camera_mt9t111,
+        .power          = mt9t111_power,
+        .priv           = &mt9t111_info,
+};
+
+static struct platform_device camera_device = {
+        .name   = "soc-camera-pdrv",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &mt9t111_link,
+        },
+};
+
+/* CEU0 */
+static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
+        .flags = SH_CEU_FLAG_LOWER_8BIT,
+};
+
+static struct resource ceu0_resources[] = {
+        [0] = {
+                .name   = "CEU",
+                .start  = 0xfe910000,
+                .end    = 0xfe91009f,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x0500),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                /* place holder for contiguous memory */
+        },
+};
+
+static struct platform_device ceu0_device = {
+        .name           = "sh_mobile_ceu",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(ceu0_resources),
+        .resource       = ceu0_resources,
+        .dev    = {
+                .platform_data          = &sh_mobile_ceu0_info,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+};
+
+/* FSI */
+static int fsi_hdmi_set_rate(struct device *dev, int rate, int enable)
+{
+        struct clk *fsib;
+        int ret;
+
+        /* it support 48KHz only */
+        if (48000 != rate)
+                return -EINVAL;
+
+        fsib = clk_get(dev, "ickb");
+        if (IS_ERR(fsib))
+                return -EINVAL;
+
+        if (enable) {
+                ret = SH_FSI_ACKMD_256 | SH_FSI_BPFMD_64;
+                clk_enable(fsib);
+        } else {
+                ret = 0;
+                clk_disable(fsib);
+        }
+
+        clk_put(fsib);
+
+        return ret;
+}
+
+static struct sh_fsi_platform_info fsi_info = {
+        /* FSI-WM8978 */
+        .port_a = {
+                .tx_id = SHDMA_SLAVE_FSIA_TX,
+        },
+        /* FSI-HDMI */
+        .port_b = {
+                .flags          = SH_FSI_FMT_SPDIF |
+                                  SH_FSI_ENABLE_STREAM_MODE,
+                .set_rate       = fsi_hdmi_set_rate,
+                .tx_id          = SHDMA_SLAVE_FSIB_TX,
+        }
+};
+
+static struct resource fsi_resources[] = {
+        [0] = {
+                .name   = "FSI",
+                .start  = 0xfe1f0000,
+                .end    = 0xfe1f8400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x1840),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device fsi_device = {
+        .name           = "sh_fsi2",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(fsi_resources),
+        .resource       = fsi_resources,
+        .dev    = {
+                .platform_data  = &fsi_info,
+        },
+};
+
+/* FSI-WM8978 */
+static struct asoc_simple_dai_init_info fsi_wm8978_init_info = {
+        .fmt            = SND_SOC_DAIFMT_I2S,
+        .codec_daifmt   = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_NB_NF,
+        .cpu_daifmt     = SND_SOC_DAIFMT_CBS_CFS,
+        .sysclk         = 12288000,
+};
+
+static struct asoc_simple_card_info fsi_wm8978_info = {
+        .name           = "wm8978",
+        .card           = "FSI2A-WM8978",
+        .cpu_dai        = "fsia-dai",
+        .codec          = "wm8978.0-001a",
+        .platform       = "sh_fsi2",
+        .codec_dai      = "wm8978-hifi",
+        .init           = &fsi_wm8978_init_info,
+};
+
+static struct platform_device fsi_wm8978_device = {
+        .name   = "asoc-simple-card",
+        .id     = 0,
+        .dev    = {
+                .platform_data  = &fsi_wm8978_info,
+        },
+};
+
+/* FSI-HDMI */
+static struct asoc_simple_dai_init_info fsi2_hdmi_init_info = {
+        .cpu_daifmt     = SND_SOC_DAIFMT_CBM_CFM,
+};
+
+static struct asoc_simple_card_info fsi2_hdmi_info = {
+        .name           = "HDMI",
+        .card           = "FSI2B-HDMI",
+        .cpu_dai        = "fsib-dai",
+        .codec          = "sh-mobile-hdmi",
+        .platform       = "sh_fsi2",
+        .codec_dai      = "sh_mobile_hdmi-hifi",
+        .init           = &fsi2_hdmi_init_info,
+};
+
+static struct platform_device fsi_hdmi_device = {
+        .name   = "asoc-simple-card",
+        .id     = 1,
+        .dev    = {
+                .platform_data  = &fsi2_hdmi_info,
+        },
+};
+
 /* I2C */
 static struct i2c_board_info i2c0_devices[] = {
         {
                 I2C_BOARD_INFO("st1232-ts", 0x55),
                 .irq = evt2irq(0x0340),
         },
+        {
+                I2C_BOARD_INFO("wm8978", 0x1a),
+        },
 };
 
 /*
@@ -549,6 +897,13 @@ static struct platform_device *eva_devices[] __initdata = {
         &sh_eth_device,
         &sdhi0_device,
         &sh_mmcif_device,
+        &hdmi_device,
+        &hdmi_lcdc_device,
+        &camera_device,
+        &ceu0_device,
+        &fsi_device,
+        &fsi_wm8978_device,
+        &fsi_hdmi_device,
 };
 
 static void __init eva_clock_init(void)
@@ -556,10 +911,14 @@ static void __init eva_clock_init(void)
         struct clk *system      = clk_get(NULL, "system_clk");
         struct clk *xtal1       = clk_get(NULL, "extal1");
         struct clk *usb24s      = clk_get(NULL, "usb24s");
+        struct clk *fsibck      = clk_get(NULL, "fsibck");
+        struct clk *fsib        = clk_get(&fsi_device.dev, "ickb");
 
         if (IS_ERR(system)      ||
             IS_ERR(xtal1)       ||
-            IS_ERR(usb24s)) {
+            IS_ERR(usb24s)      ||
+            IS_ERR(fsibck)      ||
+            IS_ERR(fsib)) {
                 pr_err("armadillo800eva board clock init failed\n");
                 goto clock_error;
         }
@@ -570,6 +929,11 @@ static void __init eva_clock_init(void)
         /* usb24s use extal1 (= system) clock (= 24MHz) */
         clk_set_parent(usb24s, system);
 
+        /* FSIBCK is 12.288MHz, and it is parent of FSI-B */
+        clk_set_parent(fsib, fsibck);
+        clk_set_rate(fsibck, 12288000);
+        clk_set_rate(fsib,   12288000);
+
 clock_error:
         if (!IS_ERR(system))
                 clk_put(system);
@@ -577,16 +941,26 @@ clock_error:
                 clk_put(xtal1);
         if (!IS_ERR(usb24s))
                 clk_put(usb24s);
+        if (!IS_ERR(fsibck))
+                clk_put(fsibck);
+        if (!IS_ERR(fsib))
+                clk_put(fsib);
 }
 
 /*
  * board init
  */
+#define GPIO_PORT7CR    0xe6050007
+#define GPIO_PORT8CR    0xe6050008
 static void __init eva_init(void)
 {
-        eva_clock_init();
+        struct platform_device *usb = NULL;
+
+        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
 
         r8a7740_pinmux_init();
+        r8a7740_meram_workaround();
 
         /* SCIFA1 */
         gpio_request(GPIO_FN_SCIFA1_RXD, NULL);
@@ -667,8 +1041,19 @@ static void __init eva_init(void)
                 /* USB Host */
         } else {
                 /* USB Func */
-                gpio_request(GPIO_FN_VBUS, NULL);
+                /*
+                 * A1 chip has 2 IRQ7 pin and it was controled by MSEL register.
+                 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
+                 * USB connection/disconnection (usbhsf_get_vbus()).
+                 * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
+                 * and select GPIO_PORT209 here
+                 */
+                gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
+                gpio_request(GPIO_PORT209, NULL);
+                gpio_direction_input(GPIO_PORT209);
+
                 platform_device_register(&usbhsf_device);
+                usb = &usbhsf_device;
         }
 
         /* SDHI0 */
@@ -706,6 +1091,48 @@ static void __init eva_init(void)
         gpio_request(GPIO_FN_MMC1_D6_PORT143,   NULL);
         gpio_request(GPIO_FN_MMC1_D7_PORT142,   NULL);
 
+        /* CEU0 */
+        gpio_request(GPIO_FN_VIO0_D7,           NULL);
+        gpio_request(GPIO_FN_VIO0_D6,           NULL);
+        gpio_request(GPIO_FN_VIO0_D5,           NULL);
+        gpio_request(GPIO_FN_VIO0_D4,           NULL);
+        gpio_request(GPIO_FN_VIO0_D3,           NULL);
+        gpio_request(GPIO_FN_VIO0_D2,           NULL);
+        gpio_request(GPIO_FN_VIO0_D1,           NULL);
+        gpio_request(GPIO_FN_VIO0_D0,           NULL);
+        gpio_request(GPIO_FN_VIO0_CLK,          NULL);
+        gpio_request(GPIO_FN_VIO0_HD,           NULL);
+        gpio_request(GPIO_FN_VIO0_VD,           NULL);
+        gpio_request(GPIO_FN_VIO0_FIELD,        NULL);
+        gpio_request(GPIO_FN_VIO_CKO,           NULL);
+
+        /* CON1/CON15 Camera */
+        gpio_request(GPIO_PORT173, NULL); /* STANDBY */
+        gpio_request(GPIO_PORT172, NULL); /* RST */
+        gpio_request(GPIO_PORT158, NULL); /* CAM_PON */
+        gpio_direction_output(GPIO_PORT173, 0);
+        gpio_direction_output(GPIO_PORT172, 1);
+        gpio_direction_output(GPIO_PORT158, 0); /* see mt9t111_power() */
+
+        /* FSI-WM8978 */
+        gpio_request(GPIO_FN_FSIAIBT,           NULL);
+        gpio_request(GPIO_FN_FSIAILR,           NULL);
+        gpio_request(GPIO_FN_FSIAOMC,           NULL);
+        gpio_request(GPIO_FN_FSIAOSLD,          NULL);
+        gpio_request(GPIO_FN_FSIAISLD_PORT5,    NULL);
+
+        gpio_request(GPIO_PORT7, NULL);
+        gpio_request(GPIO_PORT8, NULL);
+        gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
+        gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
+
+        /* FSI-HDMI */
+        gpio_request(GPIO_FN_FSIBCK,            NULL);
+
+        /* HDMI */
+        gpio_request(GPIO_FN_HDMI_HPD,          NULL);
+        gpio_request(GPIO_FN_HDMI_CEC,          NULL);
+
         /*
          * CAUTION
          *
@@ -752,6 +1179,13 @@ static void __init eva_init(void)
 
         platform_add_devices(eva_devices,
                              ARRAY_SIZE(eva_devices));
+
+        eva_clock_init();
+
+        rmobile_add_device_to_domain(&r8a7740_pd_a4lc, &lcdc0_device);
+        rmobile_add_device_to_domain(&r8a7740_pd_a4lc, &hdmi_lcdc_device);
+        if (usb)
+                rmobile_add_device_to_domain(&r8a7740_pd_a3sp, usb);
 }
 
 static void __init eva_earlytimer_init(void)
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index e9b32cfbf74..4129008eae2 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -26,6 +26,8 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/videodev2.h>
 #include <mach/common.h>
@@ -75,6 +77,12 @@
  * S38.2 = OFF
  */
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 /*
  * FPGA
  */
@@ -360,6 +368,8 @@ static void __init bonito_init(void)
 {
         u16 val;
 
+        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         r8a7740_pinmux_init();
         bonito_fpga_init();
 
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index f1257321999..fa5dfc5c8ed 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -26,6 +26,8 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/usb/r8a66597.h>
 #include <linux/io.h>
 #include <linux/input.h>
@@ -196,6 +198,15 @@ static struct platform_device keysc_device = {
         },
 };
 
+/* Fixed 3.3V regulator to be used by SDHI0 and SDHI1 */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
+};
+
 /* SDHI */
 static struct sh_mobile_sdhi_info sdhi0_info = {
         .tmio_caps      = MMC_CAP_SDIO_IRQ,
@@ -271,26 +282,11 @@ static struct platform_device *g4evm_devices[] __initdata = {
 #define GPIO_SDHID1_D3  0xe6052106
 #define GPIO_SDHICMD1   0xe6052107
 
-/*
- * FIXME !!
- *
- * gpio_pull_up is quick_hack.
- *
- * current gpio frame work doesn't have
- * the method to control only pull up/down/free.
- * this function should be replaced by correct gpio function
- */
-static void __init gpio_pull_up(u32 addr)
-{
-        u8 data = __raw_readb(addr);
-
-        data &= 0x0F;
-        data |= 0xC0;
-        __raw_writeb(data, addr);
-}
-
 static void __init g4evm_init(void)
 {
+        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+
         sh7377_pinmux_init();
 
         /* Lit DS14 LED */
@@ -351,11 +347,11 @@ static void __init g4evm_init(void)
         gpio_request(GPIO_FN_SDHID0_3, NULL);
         gpio_request(GPIO_FN_SDHICMD0, NULL);
         gpio_request(GPIO_FN_SDHIWP0, NULL);
-        gpio_pull_up(GPIO_SDHID0_D0);
-        gpio_pull_up(GPIO_SDHID0_D1);
-        gpio_pull_up(GPIO_SDHID0_D2);
-        gpio_pull_up(GPIO_SDHID0_D3);
-        gpio_pull_up(GPIO_SDHICMD0);
+        gpio_request_pullup(GPIO_SDHID0_D0);
+        gpio_request_pullup(GPIO_SDHID0_D1);
+        gpio_request_pullup(GPIO_SDHID0_D2);
+        gpio_request_pullup(GPIO_SDHID0_D3);
+        gpio_request_pullup(GPIO_SDHICMD0);
 
         /* SDHI1 */
         gpio_request(GPIO_FN_SDHICLK1, NULL);
@@ -364,11 +360,11 @@ static void __init g4evm_init(void)
         gpio_request(GPIO_FN_SDHID1_2, NULL);
         gpio_request(GPIO_FN_SDHID1_3, NULL);
         gpio_request(GPIO_FN_SDHICMD1, NULL);
-        gpio_pull_up(GPIO_SDHID1_D0);
-        gpio_pull_up(GPIO_SDHID1_D1);
-        gpio_pull_up(GPIO_SDHID1_D2);
-        gpio_pull_up(GPIO_SDHID1_D3);
-        gpio_pull_up(GPIO_SDHICMD1);
+        gpio_request_pullup(GPIO_SDHID1_D0);
+        gpio_request_pullup(GPIO_SDHID1_D1);
+        gpio_request_pullup(GPIO_SDHID1_D2);
+        gpio_request_pullup(GPIO_SDHID1_D3);
+        gpio_request_pullup(GPIO_SDHICMD1);
 
         sh7377_add_standard_devices();
 
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index f60f1b281cc..21dbe54304d 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -27,6 +27,8 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/io.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
@@ -49,6 +51,12 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/traps.h>
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 /* SMSC 9220 */
 static struct resource smsc9220_resources[] = {
         [0] = {
@@ -288,6 +296,13 @@ static struct platform_device leds_tpu30_device = {
         .resource       = tpu30_resources,
 };
 
+/* Fixed 1.8V regulator to be used by MMCIF */
+static struct regulator_consumer_supply fixed1v8_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
+};
+
 /* MMCIF */
 static struct resource mmcif_resources[] = {
         [0] = {
@@ -321,6 +336,15 @@ static struct platform_device mmcif_device = {
         .resource       = mmcif_resources,
 };
 
+/* Fixed 3.3V regulator to be used by SDHI0 and SDHI1 */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
+};
+
 /* SDHI0 */
 static struct sh_mobile_sdhi_info sdhi0_info = {
         .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
@@ -411,6 +435,12 @@ static struct platform_device *kota2_devices[] __initdata = {
 
 static void __init kota2_init(void)
 {
+        regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
+                                     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
+        regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+        regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         sh73a0_pinmux_init();
 
         /* SCIFA2 (UART2) */
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index 6a33cf39342..2c986eaae7b 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -21,6 +21,8 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <mach/common.h>
 #include <mach/emev2.h>
@@ -28,6 +30,12 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 /* Ether */
 static struct resource smsc911x_resources[] = {
         [0] = {
@@ -63,6 +71,8 @@ static struct platform_device *kzm9d_devices[] __initdata = {
 
 void __init kzm9d_add_standard_devices(void)
 {
+        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         emev2_add_standard_devices();
 
         platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices));
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index c0ae815e7be..53b7ea92c32 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -30,9 +30,14 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/usb/r8a66597.h>
+#include <linux/usb/renesas_usbhs.h>
 #include <linux/videodev2.h>
+#include <sound/sh_fsi.h>
+#include <sound/simple_card.h>
 #include <mach/irqs.h>
 #include <mach/sh73a0.h>
 #include <mach/common.h>
@@ -54,6 +59,20 @@
 #define GPIO_PCF8575_PORT15     (GPIO_NR + 13)
 #define GPIO_PCF8575_PORT16     (GPIO_NR + 14)
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
+/*
+ * FSI-AK4648
+ *
+ * this command is required when playback.
+ *
+ * # amixer set "LINEOUT Mixer DACL" on
+ */
+
 /* SMSC 9221 */
 static struct resource smsc9221_resources[] = {
         [0] = {
@@ -112,6 +131,151 @@ static struct platform_device usb_host_device = {
         .resource       = usb_resources,
 };
 
+/* USB Func CN17 */
+struct usbhs_private {
+        unsigned int phy;
+        unsigned int cr2;
+        struct renesas_usbhs_platform_info info;
+};
+
+#define IRQ15                   intcs_evt2irq(0x03e0)
+#define USB_PHY_MODE            (1 << 4)
+#define USB_PHY_INT_EN          ((1 << 3) | (1 << 2))
+#define USB_PHY_ON              (1 << 1)
+#define USB_PHY_OFF             (1 << 0)
+#define USB_PHY_INT_CLR         (USB_PHY_ON | USB_PHY_OFF)
+
+#define usbhs_get_priv(pdev) \
+        container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info)
+
+static int usbhs_get_vbus(struct platform_device *pdev)
+{
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+        return !((1 << 7) & __raw_readw(priv->cr2));
+}
+
+static void usbhs_phy_reset(struct platform_device *pdev)
+{
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+        /* init phy */
+        __raw_writew(0x8a0a, priv->cr2);
+}
+
+static int usbhs_get_id(struct platform_device *pdev)
+{
+        return USBHS_GADGET;
+}
+
+static irqreturn_t usbhs_interrupt(int irq, void *data)
+{
+        struct platform_device *pdev = data;
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+        renesas_usbhs_call_notify_hotplug(pdev);
+
+        /* clear status */
+        __raw_writew(__raw_readw(priv->phy) | USB_PHY_INT_CLR, priv->phy);
+
+        return IRQ_HANDLED;
+}
+
+static int usbhs_hardware_init(struct platform_device *pdev)
+{
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+        int ret;
+
+        /* clear interrupt status */
+        __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy);
+
+        ret = request_irq(IRQ15, usbhs_interrupt, IRQF_TRIGGER_HIGH,
+                          dev_name(&pdev->dev), pdev);
+        if (ret) {
+                dev_err(&pdev->dev, "request_irq err\n");
+                return ret;
+        }
+
+        /* enable USB phy interrupt */
+        __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->phy);
+
+        return 0;
+}
+
+static void usbhs_hardware_exit(struct platform_device *pdev)
+{
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+        /* clear interrupt status */
+        __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->phy);
+
+        free_irq(IRQ15, pdev);
+}
+
+static u32 usbhs_pipe_cfg[] = {
+        USB_ENDPOINT_XFER_CONTROL,
+        USB_ENDPOINT_XFER_ISOC,
+        USB_ENDPOINT_XFER_ISOC,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_INT,
+        USB_ENDPOINT_XFER_INT,
+        USB_ENDPOINT_XFER_INT,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+};
+
+static struct usbhs_private usbhs_private = {
+        .phy    = 0xe60781e0,           /* USBPHYINT */
+        .cr2    = 0xe605810c,           /* USBCR2 */
+        .info = {
+                .platform_callback = {
+                        .hardware_init  = usbhs_hardware_init,
+                        .hardware_exit  = usbhs_hardware_exit,
+                        .get_id         = usbhs_get_id,
+                        .phy_reset      = usbhs_phy_reset,
+                        .get_vbus       = usbhs_get_vbus,
+                },
+                .driver_param = {
+                        .buswait_bwait  = 4,
+                        .has_otg        = 1,
+                        .pipe_type      = usbhs_pipe_cfg,
+                        .pipe_size      = ARRAY_SIZE(usbhs_pipe_cfg),
+                },
+        },
+};
+
+static struct resource usbhs_resources[] = {
+        [0] = {
+                .start  = 0xE6890000,
+                .end    = 0xE68900e6 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(62),
+                .end    = gic_spi(62),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usbhs_device = {
+        .name   = "renesas_usbhs",
+        .id     = -1,
+        .dev = {
+                .dma_mask               = NULL,
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &usbhs_private.info,
+        },
+        .num_resources  = ARRAY_SIZE(usbhs_resources),
+        .resource       = usbhs_resources,
+};
+
 /* LCDC */
 static struct fb_videomode kzm_lcdc_mode = {
         .name           = "WVGA Panel",
@@ -166,6 +330,13 @@ static struct platform_device lcdc_device = {
         },
 };
 
+/* Fixed 1.8V regulator to be used by MMCIF */
+static struct regulator_consumer_supply fixed1v8_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
+};
+
 /* MMCIF */
 static struct resource sh_mmcif_resources[] = {
         [0] = {
@@ -187,6 +358,8 @@ static struct resource sh_mmcif_resources[] = {
 static struct sh_mmcif_plat_data sh_mmcif_platdata = {
         .ocr            = MMC_VDD_165_195,
         .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+        .slave_id_tx    = SHDMA_SLAVE_MMCIF_TX,
+        .slave_id_rx    = SHDMA_SLAVE_MMCIF_RX,
 };
 
 static struct platform_device mmc_device = {
@@ -200,6 +373,15 @@ static struct platform_device mmc_device = {
         .resource       = sh_mmcif_resources,
 };
 
+/* Fixed 2.8V regulators to be used by SDHI0 and SDHI2 */
+static struct regulator_consumer_supply fixed2v8_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"),
+};
+
 /* SDHI */
 static struct sh_mobile_sdhi_info sdhi0_info = {
         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT,
@@ -240,6 +422,50 @@ static struct platform_device sdhi0_device = {
         },
 };
 
+/* Micro SD */
+static struct sh_mobile_sdhi_info sdhi2_info = {
+        .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT |
+                          TMIO_MMC_USE_GPIO_CD |
+                          TMIO_MMC_WRPROTECT_DISABLE,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+        .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
+        .cd_gpio        = GPIO_PORT13,
+};
+
+static struct resource sdhi2_resources[] = {
+        [0] = {
+                .name   = "SDHI2",
+                .start  = 0xee140000,
+                .end    = 0xee1400ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
+                .start  = gic_spi(103),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .name   = SH_MOBILE_SDHI_IRQ_SDCARD,
+                .start  = gic_spi(104),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .name   = SH_MOBILE_SDHI_IRQ_SDIO,
+                .start  = gic_spi(105),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi2_device = {
+        .name           = "sh_mobile_sdhi",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(sdhi2_resources),
+        .resource       = sdhi2_resources,
+        .dev    = {
+                .platform_data  = &sdhi2_info,
+        },
+};
+
 /* KEY */
 #define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
 
@@ -267,11 +493,74 @@ static struct platform_device gpio_keys_device = {
         },
 };
 
+/* FSI-AK4648 */
+static struct sh_fsi_platform_info fsi_info = {
+        .port_a = {
+                .tx_id = SHDMA_SLAVE_FSI2A_TX,
+        },
+};
+
+static struct resource fsi_resources[] = {
+        [0] = {
+                .name   = "FSI",
+                .start  = 0xEC230000,
+                .end    = 0xEC230400 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(146),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device fsi_device = {
+        .name           = "sh_fsi2",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(fsi_resources),
+        .resource       = fsi_resources,
+        .dev    = {
+                .platform_data  = &fsi_info,
+        },
+};
+
+static struct asoc_simple_dai_init_info fsi2_ak4648_init_info = {
+        .fmt            = SND_SOC_DAIFMT_LEFT_J,
+        .codec_daifmt   = SND_SOC_DAIFMT_CBM_CFM,
+        .cpu_daifmt     = SND_SOC_DAIFMT_CBS_CFS,
+        .sysclk         = 11289600,
+};
+
+static struct asoc_simple_card_info fsi2_ak4648_info = {
+        .name           = "AK4648",
+        .card           = "FSI2A-AK4648",
+        .cpu_dai        = "fsia-dai",
+        .codec          = "ak4642-codec.0-0012",
+        .platform       = "sh_fsi2",
+        .codec_dai      = "ak4642-hifi",
+        .init           = &fsi2_ak4648_init_info,
+};
+
+static struct platform_device fsi_ak4648_device = {
+        .name   = "asoc-simple-card",
+        .dev    = {
+                .platform_data  = &fsi2_ak4648_info,
+        },
+};
+
 /* I2C */
 static struct pcf857x_platform_data pcf8575_pdata = {
         .gpio_base      = GPIO_PCF8575_BASE,
 };
 
+static struct i2c_board_info i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("ak4648", 0x12),
+        },
+        {
+                I2C_BOARD_INFO("r2025sd", 0x32),
+        }
+};
+
 static struct i2c_board_info i2c1_devices[] = {
         {
                 I2C_BOARD_INFO("st1232-ts", 0x55),
@@ -289,10 +578,14 @@ static struct i2c_board_info i2c3_devices[] = {
 static struct platform_device *kzm_devices[] __initdata = {
         &smsc_device,
         &usb_host_device,
+        &usbhs_device,
         &lcdc_device,
         &mmc_device,
         &sdhi0_device,
+        &sdhi2_device,
         &gpio_keys_device,
+        &fsi_device,
+        &fsi_ak4648_device,
 };
 
 /*
@@ -350,6 +643,12 @@ device_initcall(as3711_enable_lcdc_backlight);
 
 static void __init kzm_init(void)
 {
+        regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
+                                     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
+        regulator_register_always_on(1, "fixed-2.8V", fixed2v8_power_consumers,
+                                     ARRAY_SIZE(fixed2v8_power_consumers), 2800000);
+        regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         sh73a0_pinmux_init();
 
         /* enable SCIFA4 */
@@ -427,15 +726,36 @@ static void __init kzm_init(void)
         gpio_request(GPIO_PORT15, NULL);
         gpio_direction_output(GPIO_PORT15, 1); /* power */
 
+        /* enable Micro SD */
+        gpio_request(GPIO_FN_SDHID2_0,          NULL);
+        gpio_request(GPIO_FN_SDHID2_1,          NULL);
+        gpio_request(GPIO_FN_SDHID2_2,          NULL);
+        gpio_request(GPIO_FN_SDHID2_3,          NULL);
+        gpio_request(GPIO_FN_SDHICMD2,          NULL);
+        gpio_request(GPIO_FN_SDHICLK2,          NULL);
+        gpio_request(GPIO_PORT14, NULL);
+        gpio_direction_output(GPIO_PORT14, 1); /* power */
+
         /* I2C 3 */
         gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
         gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
 
+        /* enable FSI2 port A (ak4648) */
+        gpio_request(GPIO_FN_FSIACK,    NULL);
+        gpio_request(GPIO_FN_FSIAILR,   NULL);
+        gpio_request(GPIO_FN_FSIAIBT,   NULL);
+        gpio_request(GPIO_FN_FSIAISLD,  NULL);
+        gpio_request(GPIO_FN_FSIAOSLD,  NULL);
+
+        /* enable USB */
+        gpio_request(GPIO_FN_VBUS_0,    NULL);
+
 #ifdef CONFIG_CACHE_L2X0
         /* Early BRESP enable, Shared attribute override enable, 64K*8way */
         l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
 #endif
 
+        i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
         i2c_register_board_info(1, i2c1_devices, ARRAY_SIZE(i2c1_devices));
         i2c_register_board_info(3, i2c3_devices, ARRAY_SIZE(i2c3_devices));
 
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 150122a4463..c129542f6ae 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -41,6 +41,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/sh_flctl.h>
 #include <linux/pm_clock.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/sh_intc.h>
 #include <linux/tca6416_keypad.h>
@@ -203,31 +205,32 @@
  * amixer set "HPOUTR Mixer DACH" on
  */
 
-/*
- * FIXME !!
- *
- * gpio_no_direction
- * gpio_pull_down
- * are quick_hack.
- *
- * current gpio frame work doesn't have
- * the method to control only pull up/down/free.
- * this function should be replaced by correct gpio function
- */
-static void __init gpio_no_direction(u32 addr)
+/* Fixed 3.3V and 1.8V regulators to be used by multiple devices */
+static struct regulator_consumer_supply fixed1v8_power_consumers[] =
 {
-        __raw_writeb(0x00, addr);
-}
+        /*
+         * J22 on mackerel switches mmcif.0 and sdhi.1 between 1.8V and 3.3V
+         * Since we cannot support both voltages, we support the default 1.8V
+         */
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
+};
 
-static void __init gpio_pull_down(u32 addr)
+static struct regulator_consumer_supply fixed3v3_power_consumers[] =
 {
-        u8 data = __raw_readb(addr);
-
-        data &= 0x0F;
-        data |= 0xA0;
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"),
+};
 
-        __raw_writeb(data, addr);
-}
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
 
 /* MTD */
 static struct mtd_partition nor_flash_partitions[] = {
@@ -692,6 +695,7 @@ static struct platform_device usbhs0_device = {
  *  - J30 "open"
  *  - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET
  *  - add .get_vbus = usbhs_get_vbus in usbhs1_private
+ *  - check usbhs0_device(pio)/usbhs1_device(irq) order in mackerel_devices.
  */
 #define IRQ8 evt2irq(0x0300)
 #define USB_PHY_MODE            (1 << 4)
@@ -1322,8 +1326,8 @@ static struct platform_device *mackerel_devices[] __initdata = {
         &nor_flash_device,
         &smc911x_device,
         &lcdc_device,
-        &usbhs1_device,
         &usbhs0_device,
+        &usbhs1_device,
         &leds_device,
         &fsi_device,
         &fsi_ak4643_device,
@@ -1409,6 +1413,12 @@ static void __init mackerel_init(void)
         u32 srcr4;
         struct clk *clk;
 
+        regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
+                                     ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
+        regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+        regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         /* External clock source */
         clk_set_rate(&sh7372_dv_clki_clk, 27000000);
 
@@ -1458,11 +1468,11 @@ static void __init mackerel_init(void)
 
         /* USBHS0 */
         gpio_request(GPIO_FN_VBUS0_0, NULL);
-        gpio_pull_down(GPIO_PORT168CR); /* VBUS0_0 pull down */
+        gpio_request_pulldown(GPIO_PORT168CR); /* VBUS0_0 pull down */
 
         /* USBHS1 */
         gpio_request(GPIO_FN_VBUS0_1, NULL);
-        gpio_pull_down(GPIO_PORT167CR); /* VBUS0_1 pull down */
+        gpio_request_pulldown(GPIO_PORT167CR); /* VBUS0_1 pull down */
         gpio_request(GPIO_FN_IDIN_1_113, NULL);
 
         /* enable FSI2 port A (ak4643) */
@@ -1475,8 +1485,8 @@ static void __init mackerel_init(void)
 
         gpio_request(GPIO_PORT9,  NULL);
         gpio_request(GPIO_PORT10, NULL);
-        gpio_no_direction(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
-        gpio_no_direction(GPIO_PORT10CR); /* FSIAOLR needs no direction */
+        gpio_direction_none(GPIO_PORT9CR);  /* FSIAOBT needs no direction */
+        gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
 
         intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
 
@@ -1614,20 +1624,20 @@ static void __init mackerel_init(void)
 
         platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
 
-        sh7372_add_device_to_domain(&sh7372_a4lc, &lcdc_device);
-        sh7372_add_device_to_domain(&sh7372_a4lc, &hdmi_lcdc_device);
-        sh7372_add_device_to_domain(&sh7372_a4lc, &meram_device);
-        sh7372_add_device_to_domain(&sh7372_a4mp, &fsi_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs0_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &usbhs1_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &nand_flash_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &sh_mmcif_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi0_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &lcdc_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &hdmi_lcdc_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4lc, &meram_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &fsi_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs0_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usbhs1_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &nand_flash_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sh_mmcif_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi0_device);
 #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
-        sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi1_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi1_device);
 #endif
-        sh7372_add_device_to_domain(&sh7372_a3sp, &sdhi2_device);
-        sh7372_add_device_to_domain(&sh7372_a4r, &ceu_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &sdhi2_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4r, &ceu_device);
 
         hdmi_init_pm_clock();
         sh7372_pm_init();
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 14de3787caf..fcf5a47f477 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -27,6 +27,8 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/dma-mapping.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <mach/hardware.h>
 #include <mach/r8a7779.h>
@@ -37,6 +39,12 @@
 #include <asm/hardware/gic.h>
 #include <asm/traps.h>
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 /* SMSC LAN89218 */
 static struct resource smsc911x_resources[] = {
         [0] = {
@@ -59,7 +67,7 @@ static struct smsc911x_platform_config smsc911x_platdata = {
 
 static struct platform_device eth_device = {
         .name           = "smsc911x",
-        .id             = 0,
+        .id             = -1,
         .dev  = {
                 .platform_data = &smsc911x_platdata,
         },
@@ -73,6 +81,8 @@ static struct platform_device *marzen_devices[] __initdata = {
 
 static void __init marzen_init(void)
 {
+        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         r8a7779_pinmux_init();
 
         /* SCIF2 (CN18: DEBUG0) */
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 26eea5f2105..ad5fccc7b5e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -43,7 +43,10 @@
 /* CPG registers */
 #define FRQCRA          0xe6150000
 #define FRQCRB          0xe6150004
+#define VCLKCR1         0xE6150008
+#define VCLKCR2         0xE615000c
 #define FRQCRC          0xe61500e0
+#define FSIACKCR        0xe6150018
 #define PLLC01CR        0xe6150028
 
 #define SUBCKCR         0xe6150080
@@ -54,6 +57,8 @@
 #define MSTPSR2         0xe6150040
 #define MSTPSR3         0xe6150048
 #define MSTPSR4         0xe615004c
+#define FSIBCKCR        0xe6150090
+#define HDMICKCR        0xe6150094
 #define SMSTPCR0        0xe6150130
 #define SMSTPCR1        0xe6150134
 #define SMSTPCR2        0xe6150138
@@ -271,6 +276,13 @@ static struct clk usb24_clk = {
         .parent         = &usb24s_clk,
 };
 
+/* External FSIACK/FSIBCK clock */
+static struct clk fsiack_clk = {
+};
+
+static struct clk fsibck_clk = {
+};
+
 struct clk *main_clks[] = {
         &extalr_clk,
         &extal1_clk,
@@ -288,6 +300,8 @@ struct clk *main_clks[] = {
         &pllc1_div2_clk,
         &usb24s_clk,
         &usb24_clk,
+        &fsiack_clk,
+        &fsibck_clk,
 };
 
 static void div4_kick(struct clk *clk)
@@ -313,6 +327,107 @@ static struct clk_div4_table div4_table = {
         .kick = div4_kick,
 };
 
+/* DIV6 reparent */
+enum {
+        DIV6_HDMI,
+        DIV6_VCLK1, DIV6_VCLK2,
+        DIV6_FSIA, DIV6_FSIB,
+        DIV6_REPARENT_NR,
+};
+
+static struct clk *hdmi_parent[] = {
+        [0] = &pllc1_div2_clk,
+        [1] = &system_clk,
+        [2] = &dv_clk
+};
+
+static struct clk *vclk_parents[8] = {
+        [0] = &pllc1_div2_clk,
+        [2] = &dv_clk,
+        [3] = &usb24s_clk,
+        [4] = &extal1_div2_clk,
+        [5] = &extalr_clk,
+};
+
+static struct clk *fsia_parents[] = {
+        [0] = &pllc1_div2_clk,
+        [1] = &fsiack_clk, /* external clock */
+};
+
+static struct clk *fsib_parents[] = {
+        [0] = &pllc1_div2_clk,
+        [1] = &fsibck_clk, /* external clock */
+};
+
+static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
+        [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
+                                      hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
+        [DIV6_VCLK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
+                                       vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
+        [DIV6_VCLK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
+                                       vclk_parents, ARRAY_SIZE(vclk_parents), 12, 3),
+        [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
+                                      fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
+        [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
+                                      fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
+};
+
+/* HDMI1/2 clock */
+static unsigned long hdmi12_recalc(struct clk *clk)
+{
+        u32 val = __raw_readl(HDMICKCR);
+        int shift = (int)clk->priv;
+
+        val >>= shift;
+        val &= 0x3;
+
+        return clk->parent->rate / (1 << val);
+};
+
+static int hdmi12_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 val, mask;
+        int i, shift;
+
+        for (i = 0; i < 3; i++)
+                if (rate == clk->parent->rate / (1 << i))
+                        goto find;
+        return -ENODEV;
+
+find:
+        shift = (int)clk->priv;
+
+        val = __raw_readl(HDMICKCR);
+        mask = ~(0x3 << shift);
+        val = (val & mask) | i << shift;
+        __raw_writel(val, HDMICKCR);
+
+        return 0;
+};
+
+static struct sh_clk_ops hdmi12_clk_ops = {
+        .recalc         = hdmi12_recalc,
+        .set_rate       = hdmi12_set_rate,
+};
+
+static struct clk hdmi1_clk = {
+        .ops            = &hdmi12_clk_ops,
+        .priv           = (void *)9,
+        .parent         = &div6_reparent_clks[DIV6_HDMI],  /* late install */
+};
+
+static struct clk hdmi2_clk = {
+        .ops            = &hdmi12_clk_ops,
+        .priv           = (void *)11,
+        .parent         = &div6_reparent_clks[DIV6_HDMI], /* late install */
+};
+
+static struct clk *late_main_clks[] = {
+        &hdmi1_clk,
+        &hdmi2_clk,
+};
+
+/* MSTP */
 enum {
         DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
         DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
@@ -343,11 +458,12 @@ static struct clk div6_clks[DIV6_NR] = {
 };
 
 enum {
-        MSTP125,
+        MSTP128, MSTP127, MSTP125,
         MSTP116, MSTP111, MSTP100, MSTP117,
 
         MSTP230,
         MSTP222,
+        MSTP218, MSTP217, MSTP216, MSTP214,
         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
 
         MSTP329, MSTP328, MSTP323, MSTP320,
@@ -360,6 +476,8 @@ enum {
 };
 
 static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP128] = SH_CLK_MSTP32(&div4_clks[DIV4_S],   SMSTPCR1, 28, 0), /* CEU21 */
+        [MSTP127] = SH_CLK_MSTP32(&div4_clks[DIV4_S],   SMSTPCR1, 27, 0), /* CEU20 */
         [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
         [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   SMSTPCR1, 17, 0), /* LCDC1 */
         [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
@@ -368,6 +486,10 @@ static struct clk mstp_clks[MSTP_NR] = {
 
         [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
         [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
+        [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 18, 0), /* DMAC1 */
+        [MSTP217] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 17, 0), /* DMAC2 */
+        [MSTP216] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 16, 0), /* DMAC3 */
+        [MSTP214] = SH_CLK_MSTP32(&div4_clks[DIV4_HP],  SMSTPCR2, 14, 0), /* USBDMAC */
         [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  7, 0), /* SCIFA5 */
         [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  6, 0), /* SCIFB */
         [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  4, 0), /* SCIFA0 */
@@ -408,6 +530,12 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("pllc1_clk",              &pllc1_clk),
         CLKDEV_CON_ID("pllc1_div2_clk",         &pllc1_div2_clk),
         CLKDEV_CON_ID("usb24s",                 &usb24s_clk),
+        CLKDEV_CON_ID("hdmi1",                  &hdmi1_clk),
+        CLKDEV_CON_ID("hdmi2",                  &hdmi2_clk),
+        CLKDEV_CON_ID("video1",                 &div6_reparent_clks[DIV6_VCLK1]),
+        CLKDEV_CON_ID("video2",                 &div6_reparent_clks[DIV6_VCLK2]),
+        CLKDEV_CON_ID("fsiack",                 &fsiack_clk),
+        CLKDEV_CON_ID("fsibck",                 &fsibck_clk),
 
         /* DIV4 clocks */
         CLKDEV_CON_ID("i_clk",                  &div4_clks[DIV4_I]),
@@ -430,6 +558,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("i2c-sh_mobile.0",        &mstp_clks[MSTP116]),
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",    &mstp_clks[MSTP117]),
         CLKDEV_DEV_ID("sh_tmu.0",               &mstp_clks[MSTP125]),
+        CLKDEV_DEV_ID("sh_mobile_ceu.0",        &mstp_clks[MSTP127]),
+        CLKDEV_DEV_ID("sh_mobile_ceu.1",        &mstp_clks[MSTP128]),
 
         CLKDEV_DEV_ID("sh-sci.4",               &mstp_clks[MSTP200]),
         CLKDEV_DEV_ID("sh-sci.3",               &mstp_clks[MSTP201]),
@@ -438,7 +568,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.0",               &mstp_clks[MSTP204]),
         CLKDEV_DEV_ID("sh-sci.8",               &mstp_clks[MSTP206]),
         CLKDEV_DEV_ID("sh-sci.5",               &mstp_clks[MSTP207]),
-
+        CLKDEV_DEV_ID("sh-dma-engine.3",        &mstp_clks[MSTP214]),
+        CLKDEV_DEV_ID("sh-dma-engine.2",        &mstp_clks[MSTP216]),
+        CLKDEV_DEV_ID("sh-dma-engine.1",        &mstp_clks[MSTP217]),
+        CLKDEV_DEV_ID("sh-dma-engine.0",        &mstp_clks[MSTP218]),
         CLKDEV_DEV_ID("sh-sci.7",               &mstp_clks[MSTP222]),
         CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
 
@@ -459,6 +592,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_ICK_ID("phy",    "renesas_usbhs",        &mstp_clks[MSTP406]),
         CLKDEV_ICK_ID("pci",    "renesas_usbhs",        &div4_clks[DIV4_USBP]),
         CLKDEV_ICK_ID("usb24",  "renesas_usbhs",        &usb24_clk),
+        CLKDEV_ICK_ID("ick",    "sh-mobile-hdmi",       &div6_reparent_clks[DIV6_HDMI]),
+
+        CLKDEV_ICK_ID("icka", "sh_fsi2",        &div6_reparent_clks[DIV6_FSIA]),
+        CLKDEV_ICK_ID("ickb", "sh_fsi2",        &div6_reparent_clks[DIV6_FSIB]),
 };
 
 void __init r8a7740_clock_init(u8 md_ck)
@@ -495,7 +632,14 @@ void __init r8a7740_clock_init(u8 md_ck)
                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+                ret = sh_clk_div6_reparent_register(div6_reparent_clks,
+                                                    DIV6_REPARENT_NR);
+
+        if (!ret)
+                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
+                ret = clk_register(late_main_clks[k]);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 7d6e9fe47b5..339c62c824d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -162,7 +162,7 @@ void __init r8a7779_clock_init(void)
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
                 ret = clk_register(late_main_clks[k]);
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index 006e7b5d304..162b791b898 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -344,7 +344,7 @@ void __init sh7367_clock_init(void)
                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 94d1f88246d..5a2894b1c96 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -704,7 +704,7 @@ void __init sh7372_clock_init(void)
                 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
                 ret = clk_register(late_main_clks[k]);
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index 0798a15936c..85f2a3ec2c4 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -355,7 +355,7 @@ void __init sh7377_clock_init(void)
                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 3946c4ba2aa..7f8da18a858 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -475,9 +475,9 @@ static struct clk *late_main_clks[] = {
 
 enum { MSTP001,
         MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
-        MSTP219, MSTP218,
+        MSTP219, MSTP218, MSTP217,
         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
-        MSTP331, MSTP329, MSTP325, MSTP323,
+        MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
         MSTP314, MSTP313, MSTP312, MSTP311,
         MSTP303, MSTP302, MSTP301, MSTP300,
         MSTP411, MSTP410, MSTP403,
@@ -498,6 +498,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
         [MSTP219] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 19, 0), /* SCIFA7 */
         [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* SY-DMAC */
+        [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* MP-DMAC */
         [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
         [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
         [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
@@ -507,8 +508,10 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
         [MSTP331] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 31, 0), /* SCIFA6 */
         [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP328] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 28, 0), /*FSI*/
         [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
         [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP322] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 22, 0), /* USB */
         [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
         [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
@@ -553,6 +556,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* SY-DMAC */
+        CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* MP-DMAC */
         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
@@ -562,8 +566,10 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
         CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
+        CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
         CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
+        CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
@@ -612,7 +618,7 @@ void __init sh73a0_clock_init(void)
                 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
 
         if (!ret)
-                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 
         for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
                 ret = clk_register(late_main_clks[k]);
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 01e2bc014f1..45e61dada03 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -77,6 +77,7 @@ extern void r8a7779_add_standard_devices(void);
 extern void r8a7779_clock_init(void);
 extern void r8a7779_pinmux_init(void);
 extern void r8a7779_pm_init(void);
+extern void r8a7740_meram_workaround(void);
 
 extern unsigned int r8a7779_get_core_count(void);
 extern int r8a7779_platform_cpu_kill(unsigned int cpu);
diff --git a/arch/arm/mach-shmobile/include/mach/dma-register.h b/arch/arm/mach-shmobile/include/mach/dma-register.h
new file mode 100644
index 00000000000..97c40bd9b94
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/dma-register.h
@@ -0,0 +1,84 @@
+/*
+ * SH-ARM CPU-specific DMA definitions, used by both DMA drivers
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp
+ *
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * Based on arch/sh/include/cpu-sh4/cpu/dma-register.h
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef DMA_REGISTER_H
+#define DMA_REGISTER_H
+
+/*
+ *              Direct Memory Access Controller
+ */
+
+/* Transmit sizes and respective CHCR register values */
+enum {
+        XMIT_SZ_8BIT            = 0,
+        XMIT_SZ_16BIT           = 1,
+        XMIT_SZ_32BIT           = 2,
+        XMIT_SZ_64BIT           = 7,
+        XMIT_SZ_128BIT          = 3,
+        XMIT_SZ_256BIT          = 4,
+        XMIT_SZ_512BIT          = 5,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+static const unsigned int dma_ts_shift[] = {
+        [XMIT_SZ_8BIT]          = 0,
+        [XMIT_SZ_16BIT]         = 1,
+        [XMIT_SZ_32BIT]         = 2,
+        [XMIT_SZ_64BIT]         = 3,
+        [XMIT_SZ_128BIT]        = 4,
+        [XMIT_SZ_256BIT]        = 5,
+        [XMIT_SZ_512BIT]        = 6,
+};
+
+#define TS_LOW_BIT      0x3 /* --xx */
+#define TS_HI_BIT       0xc /* xx-- */
+
+#define TS_LOW_SHIFT    (3)
+#define TS_HI_SHIFT     (20 - 2)        /* 2 bits for shifted low TS */
+
+#define TS_INDEX2VAL(i) \
+        ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
+         (((i) & TS_HI_BIT)  << TS_HI_SHIFT))
+
+#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
+#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
+
+
+/*
+ *              USB High-Speed DMAC
+ */
+/* Transmit sizes and respective CHCR register values */
+enum {
+        USBTS_XMIT_SZ_8BYTE             = 0,
+        USBTS_XMIT_SZ_16BYTE            = 1,
+        USBTS_XMIT_SZ_32BYTE            = 2,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+static const unsigned int dma_usbts_shift[] = {
+        [USBTS_XMIT_SZ_8BYTE]   = 3,
+        [USBTS_XMIT_SZ_16BYTE]  = 4,
+        [USBTS_XMIT_SZ_32BYTE]  = 5,
+};
+
+#define USBTS_LOW_BIT   0x3 /* --xx */
+#define USBTS_HI_BIT    0x0 /* ---- */
+
+#define USBTS_LOW_SHIFT 6
+#define USBTS_HI_SHIFT  0
+
+#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
+
+#endif /* DMA_REGISTER_H */
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h
index de795b42232..844507d937c 100644
--- a/arch/arm/mach-shmobile/include/mach/gpio.h
+++ b/arch/arm/mach-shmobile/include/mach/gpio.h
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/sh_pfc.h>
+#include <linux/io.h>
 
 #ifdef CONFIG_GPIOLIB
 
@@ -27,4 +28,35 @@ static inline int irq_to_gpio(unsigned int irq)
 
 #endif /* CONFIG_GPIOLIB */
 
+/*
+ * FIXME !!
+ *
+ * current gpio frame work doesn't have
+ * the method to control only pull up/down/free.
+ * this function should be replaced by correct gpio function
+ */
+static inline void __init gpio_direction_none(u32 addr)
+{
+        __raw_writeb(0x00, addr);
+}
+
+static inline void __init gpio_request_pullup(u32 addr)
+{
+        u8 data = __raw_readb(addr);
+
+        data &= 0x0F;
+        data |= 0xC0;
+        __raw_writeb(data, addr);
+}
+
+static inline void __init gpio_request_pulldown(u32 addr)
+{
+        u8 data = __raw_readb(addr);
+
+        data &= 0x0F;
+        data |= 0xA0;
+
+        __raw_writeb(data, addr);
+}
+
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h b/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
new file mode 100644
index 00000000000..5a402840fe2
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/pm-rmobile.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef PM_RMOBILE_H
+#define PM_RMOBILE_H
+
+#include <linux/pm_domain.h>
+
+struct platform_device;
+
+struct rmobile_pm_domain {
+        struct generic_pm_domain genpd;
+        struct dev_power_governor *gov;
+        int (*suspend)(void);
+        void (*resume)(void);
+        unsigned int bit_shift;
+        bool no_debug;
+};
+
+static inline
+struct rmobile_pm_domain *to_rmobile_pd(struct generic_pm_domain *d)
+{
+        return container_of(d, struct rmobile_pm_domain, genpd);
+}
+
+#ifdef CONFIG_PM
+extern void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd);
+extern void rmobile_add_device_to_domain(struct rmobile_pm_domain *rmobile_pd,
+                                        struct platform_device *pdev);
+extern void rmobile_pm_add_subdomain(struct rmobile_pm_domain *rmobile_pd,
+                                    struct rmobile_pm_domain *rmobile_sd);
+#else
+#define rmobile_init_pm_domain(pd) do { } while (0)
+#define rmobile_add_device_to_domain(pd, pdev) do { } while (0)
+#define rmobile_pm_add_subdomain(pd, sd) do { } while (0)
+#endif /* CONFIG_PM */
+
+#endif /* PM_RMOBILE_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 9d447abb969..7143147780d 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -19,6 +19,8 @@
 #ifndef __ASM_R8A7740_H__
 #define __ASM_R8A7740_H__
 
+#include <mach/pm-rmobile.h>
+
 /*
  * MD_CKx pin
  */
@@ -139,7 +141,7 @@ enum {
         GPIO_FN_DBGMD10,        GPIO_FN_DBGMD11,        GPIO_FN_DBGMD20,
         GPIO_FN_DBGMD21,
 
-        /* FSI */
+        /* FSI-A */
         GPIO_FN_FSIAISLD_PORT0,         /* FSIAISLD Port 0/5 */
         GPIO_FN_FSIAISLD_PORT5,
         GPIO_FN_FSIASPDIF_PORT9,        /* FSIASPDIF Port 9/18 */
@@ -150,6 +152,9 @@ enum {
         GPIO_FN_FSIACK,         GPIO_FN_FSIAILR,
         GPIO_FN_FSIAIBT,
 
+        /* FSI-B */
+        GPIO_FN_FSIBCK,
+
         /* FMSI */
         GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
         GPIO_FN_FMSISLD_PORT6,
@@ -565,6 +570,10 @@ enum {
         GPIO_FN_RESETP_PULLUP,
         GPIO_FN_RESETP_PLAIN,
 
+        /* HDMI */
+        GPIO_FN_HDMI_HPD,
+        GPIO_FN_HDMI_CEC,
+
         /* SDENC */
         GPIO_FN_SDENC_CPG,
         GPIO_FN_SDENC_DV_CLKI,
@@ -581,4 +590,26 @@ enum {
         GPIO_FN_TRACEAUD_FROM_MEMC,
 };
 
+/* DMA slave IDs */
+enum {
+        SHDMA_SLAVE_INVALID,
+        SHDMA_SLAVE_SDHI0_RX,
+        SHDMA_SLAVE_SDHI0_TX,
+        SHDMA_SLAVE_SDHI1_RX,
+        SHDMA_SLAVE_SDHI1_TX,
+        SHDMA_SLAVE_SDHI2_RX,
+        SHDMA_SLAVE_SDHI2_TX,
+        SHDMA_SLAVE_FSIA_RX,
+        SHDMA_SLAVE_FSIA_TX,
+        SHDMA_SLAVE_FSIB_TX,
+        SHDMA_SLAVE_USBHS_TX,
+        SHDMA_SLAVE_USBHS_RX,
+};
+
+#ifdef CONFIG_PM
+extern struct rmobile_pm_domain r8a7740_pd_a4s;
+extern struct rmobile_pm_domain r8a7740_pd_a3sp;
+extern struct rmobile_pm_domain r8a7740_pd_a4lc;
+#endif /* CONFIG_PM */
+
 #endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 915d0093da0..b59048e6d8f 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -13,6 +13,7 @@
 
 #include <linux/sh_clk.h>
 #include <linux/pm_domain.h>
+#include <mach/pm-rmobile.h>
 
 /*
  * Pin Function Controller:
@@ -477,42 +478,16 @@ extern struct clk sh7372_fsibck_clk;
 extern struct clk sh7372_fsidiva_clk;
 extern struct clk sh7372_fsidivb_clk;
 
-struct platform_device;
-
-struct sh7372_pm_domain {
-        struct generic_pm_domain genpd;
-        struct dev_power_governor *gov;
-        int (*suspend)(void);
-        void (*resume)(void);
-        unsigned int bit_shift;
-        bool no_debug;
-};
-
-static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d)
-{
-        return container_of(d, struct sh7372_pm_domain, genpd);
-}
-
 #ifdef CONFIG_PM
-extern struct sh7372_pm_domain sh7372_a4lc;
-extern struct sh7372_pm_domain sh7372_a4mp;
-extern struct sh7372_pm_domain sh7372_d4;
-extern struct sh7372_pm_domain sh7372_a4r;
-extern struct sh7372_pm_domain sh7372_a3rv;
-extern struct sh7372_pm_domain sh7372_a3ri;
-extern struct sh7372_pm_domain sh7372_a4s;
-extern struct sh7372_pm_domain sh7372_a3sp;
-extern struct sh7372_pm_domain sh7372_a3sg;
-
-extern void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd);
-extern void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
-                                        struct platform_device *pdev);
-extern void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
-                                    struct sh7372_pm_domain *sh7372_sd);
-#else
-#define sh7372_init_pm_domain(pd) do { } while(0)
-#define sh7372_add_device_to_domain(pd, pdev) do { } while(0)
-#define sh7372_pm_add_subdomain(pd, sd) do { } while(0)
+extern struct rmobile_pm_domain sh7372_pd_a4lc;
+extern struct rmobile_pm_domain sh7372_pd_a4mp;
+extern struct rmobile_pm_domain sh7372_pd_d4;
+extern struct rmobile_pm_domain sh7372_pd_a4r;
+extern struct rmobile_pm_domain sh7372_pd_a3rv;
+extern struct rmobile_pm_domain sh7372_pd_a3ri;
+extern struct rmobile_pm_domain sh7372_pd_a4s;
+extern struct rmobile_pm_domain sh7372_pd_a3sp;
+extern struct rmobile_pm_domain sh7372_pd_a3sg;
 #endif /* CONFIG_PM */
 
 extern void sh7372_intcs_suspend(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 398e2c10913..fe950f25d79 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -516,6 +516,13 @@ enum {
         SHDMA_SLAVE_SDHI2_RX,
         SHDMA_SLAVE_MMCIF_TX,
         SHDMA_SLAVE_MMCIF_RX,
+        SHDMA_SLAVE_FSI2A_TX,
+        SHDMA_SLAVE_FSI2A_RX,
+        SHDMA_SLAVE_FSI2B_TX,
+        SHDMA_SLAVE_FSI2B_RX,
+        SHDMA_SLAVE_FSI2C_TX,
+        SHDMA_SLAVE_FSI2C_RX,
+        SHDMA_SLAVE_FSI2D_RX,
 };
 
 /*
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
index 09c42afcb22..9a69a31918b 100644
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -71,10 +71,12 @@ enum {
         DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
         DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
         SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
+        HDMI,
         USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
         RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
         SPU2_0, SPU2_1,
         FSI, FMSI,
+        HDMI_SSS, HDMI_KEY,
         IPMMU,
         AP_ARM_CTIIRQ, AP_ARM_PMURQ,
         MFIS2,
@@ -182,6 +184,7 @@ static struct intc_vect intca_vectors[] __initdata = {
         INTC_VECT(USBH_EHCI,            0x1580),
         INTC_VECT(USBH_PME,             0x15A0),
         INTC_VECT(USBH_BIND,            0x15C0),
+        INTC_VECT(HDMI,                 0x1700),
         INTC_VECT(RSPI_OVRF,            0x1780),
         INTC_VECT(RSPI_SPTEF,           0x17A0),
         INTC_VECT(RSPI_SPRF,            0x17C0),
@@ -189,6 +192,8 @@ static struct intc_vect intca_vectors[] __initdata = {
         INTC_VECT(SPU2_1,               0x1820),
         INTC_VECT(FSI,                  0x1840),
         INTC_VECT(FMSI,                 0x1860),
+        INTC_VECT(HDMI_SSS,             0x18A0),
+        INTC_VECT(HDMI_KEY,             0x18C0),
         INTC_VECT(IPMMU,                0x1920),
         INTC_VECT(AP_ARM_CTIIRQ,        0x1980),
         INTC_VECT(AP_ARM_PMURQ,         0x19A0),
@@ -304,11 +309,11 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
             USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
           /* IMR3A3 / IMCR3A3 */
         { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
-          { 0, 0, 0, 0,
+          { HDMI, 0, 0, 0,
             RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
         { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
           { SPU2_0, SPU2_1, FSI, FMSI,
-            0, 0, 0, 0 } },
+            0, HDMI_SSS, HDMI_KEY, 0 } },
         { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
           { 0, IPMMU, 0, 0,
             AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
@@ -353,10 +358,10 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
         { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
                                 /* IPRGA3 */
                                 /* IPRHA3 */
-                                /* IPRIA3 */
+        { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } },
         { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
         { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
-                                /* IPRLA3 */
+        { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } },
         { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
         { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
         { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index ee447404c85..588555a67d9 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -259,9 +259,9 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
         return 0; /* always allow wakeup */
 }
 
-#define RELOC_BASE 0x1000
+#define RELOC_BASE 0x1200
 
-/* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */
+/* INTCA IRQ pins at INTCS + RELOC_BASE to make space for GIC+INTC handling */
 #define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
 
 INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
index 670fe1869db..ce9e7fa5cc8 100644
--- a/arch/arm/mach-shmobile/pfc-r8a7740.c
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -169,7 +169,7 @@ enum {
         DBGMD10_MARK,   DBGMD11_MARK,   DBGMD20_MARK,
         DBGMD21_MARK,
 
-        /* FSI */
+        /* FSI-A */
         FSIAISLD_PORT0_MARK,    /* FSIAISLD Port 0/5 */
         FSIAISLD_PORT5_MARK,
         FSIASPDIF_PORT9_MARK,   /* FSIASPDIF Port 9/18 */
@@ -178,6 +178,9 @@ enum {
         FSIAOBT_MARK,   FSIAOSLD_MARK,  FSIAOMC_MARK,
         FSIACK_MARK,    FSIAILR_MARK,   FSIAIBT_MARK,
 
+        /* FSI-B */
+        FSIBCK_MARK,
+
         /* FMSI */
         FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
         FMSISLD_PORT6_MARK,
@@ -560,6 +563,9 @@ enum {
         /* SDENC */
         SDENC_CPG_MARK,         SDENC_DV_CLKI_MARK,
 
+        /* HDMI */
+        HDMI_HPD_MARK, HDMI_CEC_MARK,
+
         /* DEBUG */
         EDEBGREQ_PULLUP_MARK,   /* for JTAG */
         EDEBGREQ_PULLDOWN_MARK,
@@ -771,6 +777,7 @@ static pinmux_enum_t pinmux_data[] = {
 
         /* Port11 */
         PINMUX_DATA(FSIACK_MARK,                PORT11_FN1),
+        PINMUX_DATA(FSIBCK_MARK,                PORT11_FN2),
         PINMUX_DATA(IRQ2_PORT11_MARK,           PORT11_FN0,     MSEL1CR_2_0),
 
         /* Port12 */
@@ -1254,7 +1261,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(A21_MARK,                   PORT120_FN1),
         PINMUX_DATA(MSIOF0_RSYNC_MARK,          PORT120_FN2),
         PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK,  PORT120_FN3,    MSEL4CR_10_0),
-        PINMUX_DATA(IRQ7_PORT120_MARK,          PORT120_FN0,    MSEL1CR_7_0),
+        PINMUX_DATA(IRQ7_PORT120_MARK,          PORT120_FN0,    MSEL1CR_7_1),
 
         /* Port121 */
         PINMUX_DATA(A20_MARK,                   PORT121_FN1),
@@ -1616,13 +1623,15 @@ static pinmux_enum_t pinmux_data[] = {
 
         /* Port209 */
         PINMUX_DATA(VBUS_MARK,                  PORT209_FN1),
-        PINMUX_DATA(IRQ7_PORT209_MARK,          PORT209_FN0,    MSEL1CR_7_1),
+        PINMUX_DATA(IRQ7_PORT209_MARK,          PORT209_FN0,    MSEL1CR_7_0),
 
         /* Port210 */
         PINMUX_DATA(IRQ9_PORT210_MARK,          PORT210_FN0,    MSEL1CR_9_1),
+        PINMUX_DATA(HDMI_HPD_MARK,              PORT210_FN1),
 
         /* Port211 */
         PINMUX_DATA(IRQ16_PORT211_MARK,         PORT211_FN0,    MSEL1CR_16_1),
+        PINMUX_DATA(HDMI_CEC_MARK,              PORT211_FN1),
 
         /* LCDC select */
         PINMUX_DATA(LCDC0_SELECT_MARK,                          MSEL3CR_6_0),
@@ -1691,7 +1700,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(DBGMD10),       GPIO_FN(DBGMD11),       GPIO_FN(DBGMD20),
         GPIO_FN(DBGMD21),
 
-        /* FSI */
+        /* FSI-A */
         GPIO_FN(FSIAISLD_PORT0),        /* FSIAISLD Port 0/5 */
         GPIO_FN(FSIAISLD_PORT5),
         GPIO_FN(FSIASPDIF_PORT9),       /* FSIASPDIF Port 9/18 */
@@ -1700,6 +1709,9 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),      GPIO_FN(FSIAOMC),
         GPIO_FN(FSIACK),        GPIO_FN(FSIAILR),       GPIO_FN(FSIAIBT),
 
+        /* FSI-B */
+        GPIO_FN(FSIBCK),
+
         /* FMSI */
         GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
         GPIO_FN(FMSISLD_PORT6),
@@ -2097,6 +2109,10 @@ static struct pinmux_gpio pinmux_gpios[] = {
         GPIO_FN(SDENC_CPG),
         GPIO_FN(SDENC_DV_CLKI),
 
+        /* HDMI */
+        GPIO_FN(HDMI_HPD),
+        GPIO_FN(HDMI_CEC),
+
         /* SYSC */
         GPIO_FN(RESETP_PULLUP),
         GPIO_FN(RESETP_PLAIN),
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c
new file mode 100644
index 00000000000..893504d012a
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-r8a7740.c
@@ -0,0 +1,54 @@
+/*
+ * r8a7740 power management support
+ *
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/console.h>
+#include <mach/pm-rmobile.h>
+
+#ifdef CONFIG_PM
+static int r8a7740_pd_a4s_suspend(void)
+{
+        /*
+         * The A4S domain contains the CPU core and therefore it should
+         * only be turned off if the CPU is in use.
+         */
+        return -EBUSY;
+}
+
+struct rmobile_pm_domain r8a7740_pd_a4s = {
+        .genpd.name     = "A4S",
+        .bit_shift      = 10,
+        .gov            = &pm_domain_always_on_gov,
+        .no_debug       = true,
+        .suspend        = r8a7740_pd_a4s_suspend,
+};
+
+static int r8a7740_pd_a3sp_suspend(void)
+{
+        /*
+         * Serial consoles make use of SCIF hardware located in A3SP,
+         * keep such power domain on if "no_console_suspend" is set.
+         */
+        return console_suspend_enabled ? 0 : -EBUSY;
+}
+
+struct rmobile_pm_domain r8a7740_pd_a3sp = {
+        .genpd.name     = "A3SP",
+        .bit_shift      = 11,
+        .gov            = &pm_domain_always_on_gov,
+        .no_debug       = true,
+        .suspend        = r8a7740_pd_a3sp_suspend,
+};
+
+struct rmobile_pm_domain r8a7740_pd_a4lc = {
+        .genpd.name     = "A4LC",
+        .bit_shift      = 1,
+};
+
+#endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
new file mode 100644
index 00000000000..a8562540f1d
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -0,0 +1,167 @@
+/*
+ * rmobile power management support
+ *
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * based on pm-sh7372.c
+ *  Copyright (C) 2011 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/console.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/pm_clock.h>
+#include <asm/io.h>
+#include <mach/pm-rmobile.h>
+
+/* SYSC */
+#define SPDCR           0xe6180008
+#define SWUCR           0xe6180014
+#define PSTR            0xe6180080
+
+#define PSTR_RETRIES    100
+#define PSTR_DELAY_US   10
+
+#ifdef CONFIG_PM
+static int rmobile_pd_power_down(struct generic_pm_domain *genpd)
+{
+        struct rmobile_pm_domain *rmobile_pd = to_rmobile_pd(genpd);
+        unsigned int mask = 1 << rmobile_pd->bit_shift;
+
+        if (rmobile_pd->suspend) {
+                int ret = rmobile_pd->suspend();
+
+                if (ret)
+                        return ret;
+        }
+
+        if (__raw_readl(PSTR) & mask) {
+                unsigned int retry_count;
+                __raw_writel(mask, SPDCR);
+
+                for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
+                        if (!(__raw_readl(SPDCR) & mask))
+                                break;
+                        cpu_relax();
+                }
+        }
+
+        if (!rmobile_pd->no_debug)
+                pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
+                         genpd->name, mask, __raw_readl(PSTR));
+
+        return 0;
+}
+
+static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd,
+                                 bool do_resume)
+{
+        unsigned int mask = 1 << rmobile_pd->bit_shift;
+        unsigned int retry_count;
+        int ret = 0;
+
+        if (__raw_readl(PSTR) & mask)
+                goto out;
+
+        __raw_writel(mask, SWUCR);
+
+        for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
+                if (!(__raw_readl(SWUCR) & mask))
+                        break;
+                if (retry_count > PSTR_RETRIES)
+                        udelay(PSTR_DELAY_US);
+                else
+                        cpu_relax();
+        }
+        if (!retry_count)
+                ret = -EIO;
+
+        if (!rmobile_pd->no_debug)
+                pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
+                         rmobile_pd->genpd.name, mask, __raw_readl(PSTR));
+
+out:
+        if (ret == 0 && rmobile_pd->resume && do_resume)
+                rmobile_pd->resume();
+
+        return ret;
+}
+
+static int rmobile_pd_power_up(struct generic_pm_domain *genpd)
+{
+        return __rmobile_pd_power_up(to_rmobile_pd(genpd), true);
+}
+
+static bool rmobile_pd_active_wakeup(struct device *dev)
+{
+        bool (*active_wakeup)(struct device *dev);
+
+        active_wakeup = dev_gpd_data(dev)->ops.active_wakeup;
+        return active_wakeup ? active_wakeup(dev) : true;
+}
+
+static int rmobile_pd_stop_dev(struct device *dev)
+{
+        int (*stop)(struct device *dev);
+
+        stop = dev_gpd_data(dev)->ops.stop;
+        if (stop) {
+                int ret = stop(dev);
+                if (ret)
+                        return ret;
+        }
+        return pm_clk_suspend(dev);
+}
+
+static int rmobile_pd_start_dev(struct device *dev)
+{
+        int (*start)(struct device *dev);
+        int ret;
+
+        ret = pm_clk_resume(dev);
+        if (ret)
+                return ret;
+
+        start = dev_gpd_data(dev)->ops.start;
+        if (start)
+                ret = start(dev);
+
+        return ret;
+}
+
+void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
+{
+        struct generic_pm_domain *genpd = &rmobile_pd->genpd;
+        struct dev_power_governor *gov = rmobile_pd->gov;
+
+        pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
+        genpd->dev_ops.stop             = rmobile_pd_stop_dev;
+        genpd->dev_ops.start            = rmobile_pd_start_dev;
+        genpd->dev_ops.active_wakeup    = rmobile_pd_active_wakeup;
+        genpd->dev_irq_safe             = true;
+        genpd->power_off                = rmobile_pd_power_down;
+        genpd->power_on                 = rmobile_pd_power_up;
+        __rmobile_pd_power_up(rmobile_pd, false);
+}
+
+void rmobile_add_device_to_domain(struct rmobile_pm_domain *rmobile_pd,
+                                 struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+
+        pm_genpd_add_device(&rmobile_pd->genpd, dev);
+        if (pm_clk_no_clocks(dev))
+                pm_clk_add(dev, NULL);
+}
+
+void rmobile_pm_add_subdomain(struct rmobile_pm_domain *rmobile_pd,
+                             struct rmobile_pm_domain *rmobile_sd)
+{
+        pm_genpd_add_subdomain(&rmobile_pd->genpd, &rmobile_sd->genpd);
+}
+#endif /* CONFIG_PM */
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index a3bdb12acde..79203706922 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -26,6 +26,7 @@
 #include <asm/suspend.h>
 #include <mach/common.h>
 #include <mach/sh7372.h>
+#include <mach/pm-rmobile.h>
 
 /* DBG */
 #define DBGREG1 0xe6100020
@@ -41,13 +42,10 @@
 #define PLLC01STPCR 0xe61500c8
 
 /* SYSC */
-#define SPDCR 0xe6180008
-#define SWUCR 0xe6180014
 #define SBAR 0xe6180020
 #define WUPRMSK 0xe6180028
 #define WUPSMSK 0xe618002c
 #define WUPSMSK2 0xe6180048
-#define PSTR 0xe6180080
 #define WUPSFAC 0xe6180098
 #define IRQCR 0xe618022c
 #define IRQCR2 0xe6180238
@@ -71,188 +69,48 @@
 /* AP-System Core */
 #define APARMBAREA 0xe6f10020
 
-#define PSTR_RETRIES 100
-#define PSTR_DELAY_US 10
-
 #ifdef CONFIG_PM
 
-static int pd_power_down(struct generic_pm_domain *genpd)
-{
-        struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
-        unsigned int mask = 1 << sh7372_pd->bit_shift;
-
-        if (sh7372_pd->suspend) {
-                int ret = sh7372_pd->suspend();
-
-                if (ret)
-                        return ret;
-        }
-
-        if (__raw_readl(PSTR) & mask) {
-                unsigned int retry_count;
-
-                __raw_writel(mask, SPDCR);
-
-                for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
-                        if (!(__raw_readl(SPDCR) & mask))
-                                break;
-                        cpu_relax();
-                }
-        }
-
-        if (!sh7372_pd->no_debug)
-                pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n",
-                         genpd->name, mask, __raw_readl(PSTR));
-
-        return 0;
-}
-
-static int __pd_power_up(struct sh7372_pm_domain *sh7372_pd, bool do_resume)
-{
-        unsigned int mask = 1 << sh7372_pd->bit_shift;
-        unsigned int retry_count;
-        int ret = 0;
-
-        if (__raw_readl(PSTR) & mask)
-                goto out;
-
-        __raw_writel(mask, SWUCR);
-
-        for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
-                if (!(__raw_readl(SWUCR) & mask))
-                        break;
-                if (retry_count > PSTR_RETRIES)
-                        udelay(PSTR_DELAY_US);
-                else
-                        cpu_relax();
-        }
-        if (!retry_count)
-                ret = -EIO;
-
-        if (!sh7372_pd->no_debug)
-                pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n",
-                         sh7372_pd->genpd.name, mask, __raw_readl(PSTR));
-
- out:
-        if (ret == 0 && sh7372_pd->resume && do_resume)
-                sh7372_pd->resume();
-
-        return ret;
-}
-
-static int pd_power_up(struct generic_pm_domain *genpd)
-{
-         return __pd_power_up(to_sh7372_pd(genpd), true);
-}
-
-static int sh7372_a4r_suspend(void)
-{
-        sh7372_intcs_suspend();
-        __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
-        return 0;
-}
-
-static bool pd_active_wakeup(struct device *dev)
-{
-        bool (*active_wakeup)(struct device *dev);
-
-        active_wakeup = dev_gpd_data(dev)->ops.active_wakeup;
-        return active_wakeup ? active_wakeup(dev) : true;
-}
-
-static int sh7372_stop_dev(struct device *dev)
-{
-        int (*stop)(struct device *dev);
-
-        stop = dev_gpd_data(dev)->ops.stop;
-        if (stop) {
-                int ret = stop(dev);
-                if (ret)
-                        return ret;
-        }
-        return pm_clk_suspend(dev);
-}
-
-static int sh7372_start_dev(struct device *dev)
-{
-        int (*start)(struct device *dev);
-        int ret;
-
-        ret = pm_clk_resume(dev);
-        if (ret)
-                return ret;
-
-        start = dev_gpd_data(dev)->ops.start;
-        if (start)
-                ret = start(dev);
-
-        return ret;
-}
-
-void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
-{
-        struct generic_pm_domain *genpd = &sh7372_pd->genpd;
-        struct dev_power_governor *gov = sh7372_pd->gov;
-
-        pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
-        genpd->dev_ops.stop = sh7372_stop_dev;
-        genpd->dev_ops.start = sh7372_start_dev;
-        genpd->dev_ops.active_wakeup = pd_active_wakeup;
-        genpd->dev_irq_safe = true;
-        genpd->power_off = pd_power_down;
-        genpd->power_on = pd_power_up;
-        __pd_power_up(sh7372_pd, false);
-}
-
-void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
-                                 struct platform_device *pdev)
-{
-        struct device *dev = &pdev->dev;
-
-        pm_genpd_add_device(&sh7372_pd->genpd, dev);
-        if (pm_clk_no_clocks(dev))
-                pm_clk_add(dev, NULL);
-}
-
-void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
-                             struct sh7372_pm_domain *sh7372_sd)
-{
-        pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
-}
-
-struct sh7372_pm_domain sh7372_a4lc = {
+struct rmobile_pm_domain sh7372_pd_a4lc = {
         .genpd.name = "A4LC",
         .bit_shift = 1,
 };
 
-struct sh7372_pm_domain sh7372_a4mp = {
+struct rmobile_pm_domain sh7372_pd_a4mp = {
         .genpd.name = "A4MP",
         .bit_shift = 2,
 };
 
-struct sh7372_pm_domain sh7372_d4 = {
+struct rmobile_pm_domain sh7372_pd_d4 = {
         .genpd.name = "D4",
         .bit_shift = 3,
 };
 
-struct sh7372_pm_domain sh7372_a4r = {
+static int sh7372_a4r_pd_suspend(void)
+{
+        sh7372_intcs_suspend();
+        __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
+        return 0;
+}
+
+struct rmobile_pm_domain sh7372_pd_a4r = {
         .genpd.name = "A4R",
         .bit_shift = 5,
-        .suspend = sh7372_a4r_suspend,
+        .suspend = sh7372_a4r_pd_suspend,
         .resume = sh7372_intcs_resume,
 };
 
-struct sh7372_pm_domain sh7372_a3rv = {
+struct rmobile_pm_domain sh7372_pd_a3rv = {
         .genpd.name = "A3RV",
         .bit_shift = 6,
 };
 
-struct sh7372_pm_domain sh7372_a3ri = {
+struct rmobile_pm_domain sh7372_pd_a3ri = {
         .genpd.name = "A3RI",
         .bit_shift = 8,
 };
 
-static int sh7372_a4s_suspend(void)
+static int sh7372_pd_a4s_suspend(void)
 {
         /*
          * The A4S domain contains the CPU core and therefore it should
@@ -261,15 +119,15 @@ static int sh7372_a4s_suspend(void)
         return -EBUSY;
 }
 
-struct sh7372_pm_domain sh7372_a4s = {
+struct rmobile_pm_domain sh7372_pd_a4s = {
         .genpd.name = "A4S",
         .bit_shift = 10,
         .gov = &pm_domain_always_on_gov,
         .no_debug = true,
-        .suspend = sh7372_a4s_suspend,
+        .suspend = sh7372_pd_a4s_suspend,
 };
 
-static int sh7372_a3sp_suspend(void)
+static int sh7372_a3sp_pd_suspend(void)
 {
         /*
          * Serial consoles make use of SCIF hardware located in A3SP,
@@ -278,32 +136,22 @@ static int sh7372_a3sp_suspend(void)
         return console_suspend_enabled ? 0 : -EBUSY;
 }
 
-struct sh7372_pm_domain sh7372_a3sp = {
+struct rmobile_pm_domain sh7372_pd_a3sp = {
         .genpd.name = "A3SP",
         .bit_shift = 11,
         .gov = &pm_domain_always_on_gov,
         .no_debug = true,
-        .suspend = sh7372_a3sp_suspend,
+        .suspend = sh7372_a3sp_pd_suspend,
 };
 
-struct sh7372_pm_domain sh7372_a3sg = {
+struct rmobile_pm_domain sh7372_pd_a3sg = {
         .genpd.name = "A3SG",
         .bit_shift = 13,
 };
 
-#else /* !CONFIG_PM */
-
-static inline void sh7372_a3sp_init(void) {}
-
-#endif /* !CONFIG_PM */
+#endif /* CONFIG_PM */
 
 #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
-static int sh7372_do_idle_core_standby(unsigned long unused)
-{
-        cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
-        return 0;
-}
-
 static void sh7372_set_reset_vector(unsigned long address)
 {
         /* set reset vector, translate 4k */
@@ -311,21 +159,6 @@ static void sh7372_set_reset_vector(unsigned long address)
         __raw_writel(0, APARMBAREA);
 }
 
-static void sh7372_enter_core_standby(void)
-{
-        sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
-
-        /* enter sleep mode with SYSTBCR to 0x10 */
-        __raw_writel(0x10, SYSTBCR);
-        cpu_suspend(0, sh7372_do_idle_core_standby);
-        __raw_writel(0, SYSTBCR);
-
-         /* disable reset vector translation */
-        __raw_writel(0, SBAR);
-}
-#endif
-
-#ifdef CONFIG_SUSPEND
 static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
 {
         if (pllc0_on)
@@ -465,22 +298,42 @@ static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
 
 static void sh7372_enter_a3sm_common(int pllc0_on)
 {
+        /* use INTCA together with SYSC for wakeup */
+        sh7372_setup_sysc(1 << 0, 0);
         sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
         sh7372_enter_sysc(pllc0_on, 1 << 12);
 }
+#endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
 
-static void sh7372_enter_a4s_common(int pllc0_on)
+#ifdef CONFIG_CPU_IDLE
+static int sh7372_do_idle_core_standby(unsigned long unused)
 {
-        sh7372_intca_suspend();
-        memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
-        sh7372_set_reset_vector(SMFRAM);
-        sh7372_enter_sysc(pllc0_on, 1 << 10);
-        sh7372_intca_resume();
+        cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
+        return 0;
 }
 
-#endif
+static void sh7372_enter_core_standby(void)
+{
+        sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
 
-#ifdef CONFIG_CPU_IDLE
+        /* enter sleep mode with SYSTBCR to 0x10 */
+        __raw_writel(0x10, SYSTBCR);
+        cpu_suspend(0, sh7372_do_idle_core_standby);
+        __raw_writel(0, SYSTBCR);
+
+         /* disable reset vector translation */
+        __raw_writel(0, SBAR);
+}
+
+static void sh7372_enter_a3sm_pll_on(void)
+{
+        sh7372_enter_a3sm_common(1);
+}
+
+static void sh7372_enter_a3sm_pll_off(void)
+{
+        sh7372_enter_a3sm_common(0);
+}
 
 static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
 {
@@ -492,7 +345,24 @@ static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
         state->target_residency = 20 + 10;
         state->flags = CPUIDLE_FLAG_TIME_VALID;
         shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
+        drv->state_count++;
+
+        state = &drv->states[drv->state_count];
+        snprintf(state->name, CPUIDLE_NAME_LEN, "C3");
+        strncpy(state->desc, "A3SM PLL ON", CPUIDLE_DESC_LEN);
+        state->exit_latency = 20;
+        state->target_residency = 30 + 20;
+        state->flags = CPUIDLE_FLAG_TIME_VALID;
+        shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_on;
+        drv->state_count++;
 
+        state = &drv->states[drv->state_count];
+        snprintf(state->name, CPUIDLE_NAME_LEN, "C4");
+        strncpy(state->desc, "A3SM PLL OFF", CPUIDLE_DESC_LEN);
+        state->exit_latency = 120;
+        state->target_residency = 30 + 120;
+        state->flags = CPUIDLE_FLAG_TIME_VALID;
+        shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_a3sm_pll_off;
         drv->state_count++;
 }
 
@@ -505,6 +375,14 @@ static void sh7372_cpuidle_init(void) {}
 #endif
 
 #ifdef CONFIG_SUSPEND
+static void sh7372_enter_a4s_common(int pllc0_on)
+{
+        sh7372_intca_suspend();
+        memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
+        sh7372_set_reset_vector(SMFRAM);
+        sh7372_enter_sysc(pllc0_on, 1 << 10);
+        sh7372_intca_resume();
+}
 
 static int sh7372_enter_suspend(suspend_state_t suspend_state)
 {
@@ -512,24 +390,21 @@ static int sh7372_enter_suspend(suspend_state_t suspend_state)
 
         /* check active clocks to determine potential wakeup sources */
         if (sh7372_sysc_valid(&msk, &msk2)) {
-                /* convert INTC mask and sense to SYSC mask and sense */
-                sh7372_setup_sysc(msk, msk2);
-
                 if (!console_suspend_enabled &&
-                    sh7372_a4s.genpd.status == GPD_STATE_POWER_OFF) {
+                    sh7372_pd_a4s.genpd.status == GPD_STATE_POWER_OFF) {
+                        /* convert INTC mask/sense to SYSC mask/sense */
+                        sh7372_setup_sysc(msk, msk2);
+
                         /* enter A4S sleep with PLLC0 off */
                         pr_debug("entering A4S\n");
                         sh7372_enter_a4s_common(0);
-                } else {
-                        /* enter A3SM sleep with PLLC0 off */
-                        pr_debug("entering A3SM\n");
-                        sh7372_enter_a3sm_common(0);
+                        return 0;
                 }
-        } else {
-                /* default to Core Standby that supports all wakeup sources */
-                pr_debug("entering Core Standby\n");
-                sh7372_enter_core_standby();
         }
+
+        /* default to enter A3SM sleep with PLLC0 off */
+        pr_debug("entering A3SM\n");
+        sh7372_enter_a3sm_common(0);
         return 0;
 }
 
@@ -550,7 +425,7 @@ static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
                  * executed during system suspend and resume, respectively, so
                  * that those functions don't crash while accessing the INTCS.
                  */
-                pm_genpd_poweron(&sh7372_a4r.genpd);
+                pm_genpd_poweron(&sh7372_pd_a4r.genpd);
                 break;
         case PM_POST_SUSPEND:
                 pm_genpd_poweroff_unused();
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index ec4eb49c169..78948a9dba0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -23,9 +23,14 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/of_platform.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
+#include <linux/dma-mapping.h>
+#include <mach/dma-register.h>
 #include <mach/r8a7740.h>
+#include <mach/pm-rmobile.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <asm/mach-types.h>
@@ -276,6 +281,272 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
         &cmt10_device,
 };
 
+/* DMA */
+static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_SDHI0_TX,
+                .addr           = 0xe6850030,
+                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI0_RX,
+                .addr           = 0xe6850030,
+                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc2,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI1_TX,
+                .addr           = 0xe6860030,
+                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc9,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI1_RX,
+                .addr           = 0xe6860030,
+                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xca,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI2_TX,
+                .addr           = 0xe6870030,
+                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xcd,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI2_RX,
+                .addr           = 0xe6870030,
+                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xce,
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSIA_TX,
+                .addr           = 0xfe1f0024,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xb1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSIA_RX,
+                .addr           = 0xfe1f0020,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xb2,
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSIB_TX,
+                .addr           = 0xfe1f0064,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xb5,
+        },
+};
+
+#define DMA_CHANNEL(a, b, c)                    \
+{                                               \
+        .offset         = a,                    \
+        .dmars          = b,                    \
+        .dmars_bit      = c,                    \
+        .chclr_offset   = (0x220 - 0x20) + a    \
+}
+
+static const struct sh_dmae_channel r8a7740_dmae_channels[] = {
+        DMA_CHANNEL(0x00, 0, 0),
+        DMA_CHANNEL(0x10, 0, 8),
+        DMA_CHANNEL(0x20, 4, 0),
+        DMA_CHANNEL(0x30, 4, 8),
+        DMA_CHANNEL(0x50, 8, 0),
+        DMA_CHANNEL(0x60, 8, 8),
+};
+
+static struct sh_dmae_pdata dma_platform_data = {
+        .slave          = r8a7740_dmae_slaves,
+        .slave_num      = ARRAY_SIZE(r8a7740_dmae_slaves),
+        .channel        = r8a7740_dmae_channels,
+        .channel_num    = ARRAY_SIZE(r8a7740_dmae_channels),
+        .ts_low_shift   = TS_LOW_SHIFT,
+        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
+        .ts_high_shift  = TS_HI_SHIFT,
+        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
+        .ts_shift       = dma_ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
+        .dmaor_init     = DMAOR_DME,
+        .chclr_present  = 1,
+};
+
+/* Resource order important! */
+static struct resource r8a7740_dmae0_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xfe008020,
+                .end    = 0xfe00828f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMARSx */
+                .start  = 0xfe009000,
+                .end    = 0xfe00900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "error_irq",
+                .start  = evt2irq(0x20c0),
+                .end    = evt2irq(0x20c0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-5 */
+                .start  = evt2irq(0x2000),
+                .end    = evt2irq(0x20a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* Resource order important! */
+static struct resource r8a7740_dmae1_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xfe018020,
+                .end    = 0xfe01828f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMARSx */
+                .start  = 0xfe019000,
+                .end    = 0xfe01900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "error_irq",
+                .start  = evt2irq(0x21c0),
+                .end    = evt2irq(0x21c0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-5 */
+                .start  = evt2irq(0x2100),
+                .end    = evt2irq(0x21a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+/* Resource order important! */
+static struct resource r8a7740_dmae2_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xfe028020,
+                .end    = 0xfe02828f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMARSx */
+                .start  = 0xfe029000,
+                .end    = 0xfe02900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "error_irq",
+                .start  = evt2irq(0x22c0),
+                .end    = evt2irq(0x22c0),
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-5 */
+                .start  = evt2irq(0x2200),
+                .end    = evt2irq(0x22a0),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 0,
+        .resource       = r8a7740_dmae0_resources,
+        .num_resources  = ARRAY_SIZE(r8a7740_dmae0_resources),
+        .dev            = {
+                .platform_data  = &dma_platform_data,
+        },
+};
+
+static struct platform_device dma1_device = {
+        .name           = "sh-dma-engine",
+        .id             = 1,
+        .resource       = r8a7740_dmae1_resources,
+        .num_resources  = ARRAY_SIZE(r8a7740_dmae1_resources),
+        .dev            = {
+                .platform_data  = &dma_platform_data,
+        },
+};
+
+static struct platform_device dma2_device = {
+        .name           = "sh-dma-engine",
+        .id             = 2,
+        .resource       = r8a7740_dmae2_resources,
+        .num_resources  = ARRAY_SIZE(r8a7740_dmae2_resources),
+        .dev            = {
+                .platform_data  = &dma_platform_data,
+        },
+};
+
+/* USB-DMAC */
+static const struct sh_dmae_channel r8a7740_usb_dma_channels[] = {
+        {
+                .offset = 0,
+        }, {
+                .offset = 0x20,
+        },
+};
+
+static const struct sh_dmae_slave_config r8a7740_usb_dma_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_USBHS_TX,
+                .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
+        }, {
+                .slave_id       = SHDMA_SLAVE_USBHS_RX,
+                .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
+        },
+};
+
+static struct sh_dmae_pdata usb_dma_platform_data = {
+        .slave          = r8a7740_usb_dma_slaves,
+        .slave_num      = ARRAY_SIZE(r8a7740_usb_dma_slaves),
+        .channel        = r8a7740_usb_dma_channels,
+        .channel_num    = ARRAY_SIZE(r8a7740_usb_dma_channels),
+        .ts_low_shift   = USBTS_LOW_SHIFT,
+        .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
+        .ts_high_shift  = USBTS_HI_SHIFT,
+        .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
+        .ts_shift       = dma_usbts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
+        .dmaor_init     = DMAOR_DME,
+        .chcr_offset    = 0x14,
+        .chcr_ie_bit    = 1 << 5,
+        .dmaor_is_32bit = 1,
+        .needs_tend_set = 1,
+        .no_dmars       = 1,
+        .slave_only     = 1,
+};
+
+static struct resource r8a7740_usb_dma_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xe68a0020,
+                .end    = 0xe68a0064 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* VCR/SWR/DMICR */
+                .start  = 0xe68a0000,
+                .end    = 0xe68a0014 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* IRQ for channels */
+                .start  = evt2irq(0x0a00),
+                .end    = evt2irq(0x0a00),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usb_dma_device = {
+        .name           = "sh-dma-engine",
+        .id             = 3,
+        .resource       = r8a7740_usb_dma_resources,
+        .num_resources  = ARRAY_SIZE(r8a7740_usb_dma_resources),
+        .dev            = {
+                .platform_data  = &usb_dma_platform_data,
+        },
+};
+
 /* I2C */
 static struct resource i2c0_resources[] = {
         [0] = {
@@ -322,8 +593,30 @@ static struct platform_device i2c1_device = {
 static struct platform_device *r8a7740_late_devices[] __initdata = {
         &i2c0_device,
         &i2c1_device,
+        &dma0_device,
+        &dma1_device,
+        &dma2_device,
+        &usb_dma_device,
 };
 
+/*
+ * r8a7740 chip has lasting errata on MERAM buffer.
+ * this is work-around for it.
+ * see
+ *      "Media RAM (MERAM)" on r8a7740 documentation
+ */
+#define MEBUFCNTR       0xFE950098
+void r8a7740_meram_workaround(void)
+{
+        void __iomem *reg;
+
+        reg = ioremap_nocache(MEBUFCNTR, 4);
+        if (reg) {
+                iowrite32(0x01600164, reg);
+                iounmap(reg);
+        }
+}
+
 #define ICCR    0x0004
 #define ICSTART 0x0070
 
@@ -380,10 +673,31 @@ void __init r8a7740_add_standard_devices(void)
         r8a7740_i2c_workaround(&i2c0_device);
         r8a7740_i2c_workaround(&i2c1_device);
 
+        /* PM domain */
+        rmobile_init_pm_domain(&r8a7740_pd_a4s);
+        rmobile_init_pm_domain(&r8a7740_pd_a3sp);
+        rmobile_init_pm_domain(&r8a7740_pd_a4lc);
+
+        rmobile_pm_add_subdomain(&r8a7740_pd_a4s, &r8a7740_pd_a3sp);
+
+        /* add devices */
         platform_add_devices(r8a7740_early_devices,
                             ARRAY_SIZE(r8a7740_early_devices));
         platform_add_devices(r8a7740_late_devices,
                              ARRAY_SIZE(r8a7740_late_devices));
+
+        /* add devices to PM domain  */
+
+        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif0_device);
+        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif1_device);
+        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif2_device);
+        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif3_device);
+        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif4_device);
+        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif5_device);
+        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif6_device);
+        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scif7_device);
+        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &scifb_device);
+        rmobile_add_device_to_domain(&r8a7740_pd_a3sp,  &i2c1_device);
 }
 
 static void __init r8a7740_earlytimer_init(void)
@@ -403,3 +717,49 @@ void __init r8a7740_add_early_devices(void)
         /* override timer setup with soc-specific code */
         shmobile_timer.init = r8a7740_earlytimer_init;
 }
+
+#ifdef CONFIG_USE_OF
+
+void __init r8a7740_add_early_devices_dt(void)
+{
+        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
+
+        early_platform_add_devices(r8a7740_early_devices,
+                                   ARRAY_SIZE(r8a7740_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+}
+
+static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = {
+        { }
+};
+
+void __init r8a7740_add_standard_devices_dt(void)
+{
+        /* clocks are setup late during boot in the case of DT */
+        r8a7740_clock_init(0);
+
+        platform_add_devices(r8a7740_early_devices,
+                            ARRAY_SIZE(r8a7740_early_devices));
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             r8a7740_auxdata_lookup, NULL);
+}
+
+static const char *r8a7740_boards_compat_dt[] __initdata = {
+        "renesas,r8a7740",
+        NULL,
+};
+
+DT_MACHINE_START(SH7372_DT, "Generic R8A7740 (Flattened Device Tree)")
+        .map_io         = r8a7740_map_io,
+        .init_early     = r8a7740_add_early_devices_dt,
+        .init_irq       = r8a7740_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = r8a7740_add_standard_devices_dt,
+        .timer          = &shmobile_timer,
+        .dt_compat      = r8a7740_boards_compat_dt,
+MACHINE_END
+
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index fafce9ce821..838a87be1d5 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -33,6 +33,7 @@
 #include <linux/sh_timer.h>
 #include <linux/pm_domain.h>
 #include <linux/dma-mapping.h>
+#include <mach/dma-register.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
@@ -335,151 +336,126 @@ static struct platform_device iic1_device = {
 };
 
 /* DMA */
-/* Transmit sizes and respective CHCR register values */
-enum {
-        XMIT_SZ_8BIT            = 0,
-        XMIT_SZ_16BIT           = 1,
-        XMIT_SZ_32BIT           = 2,
-        XMIT_SZ_64BIT           = 7,
-        XMIT_SZ_128BIT          = 3,
-        XMIT_SZ_256BIT          = 4,
-        XMIT_SZ_512BIT          = 5,
-};
-
-/* log2(size / 8) - used to calculate number of transfers */
-#define TS_SHIFT {                      \
-        [XMIT_SZ_8BIT]          = 0,    \
-        [XMIT_SZ_16BIT]         = 1,    \
-        [XMIT_SZ_32BIT]         = 2,    \
-        [XMIT_SZ_64BIT]         = 3,    \
-        [XMIT_SZ_128BIT]        = 4,    \
-        [XMIT_SZ_256BIT]        = 5,    \
-        [XMIT_SZ_512BIT]        = 6,    \
-}
-
-#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
-                         (((i) & 0xc) << (20 - 2)))
-
 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
         {
                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
                 .addr           = 0xe6c40020,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x21,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
                 .addr           = 0xe6c40024,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x22,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
                 .addr           = 0xe6c50020,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x25,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
                 .addr           = 0xe6c50024,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x26,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
                 .addr           = 0xe6c60020,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x29,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
                 .addr           = 0xe6c60024,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x2a,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
                 .addr           = 0xe6c70020,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x2d,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
                 .addr           = 0xe6c70024,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x2e,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
                 .addr           = 0xe6c80020,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x39,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
                 .addr           = 0xe6c80024,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x3a,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
                 .addr           = 0xe6cb0020,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x35,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
                 .addr           = 0xe6cb0024,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x36,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
                 .addr           = 0xe6c30040,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x3d,
         }, {
                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
                 .addr           = 0xe6c30060,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
                 .mid_rid        = 0x3e,
         }, {
                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
                 .addr           = 0xe6850030,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
                 .mid_rid        = 0xc1,
         }, {
                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
                 .addr           = 0xe6850030,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
                 .mid_rid        = 0xc2,
         }, {
                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
                 .addr           = 0xe6860030,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
                 .mid_rid        = 0xc9,
         }, {
                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
                 .addr           = 0xe6860030,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
                 .mid_rid        = 0xca,
         }, {
                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
                 .addr           = 0xe6870030,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
                 .mid_rid        = 0xcd,
         }, {
                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
                 .addr           = 0xe6870030,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
                 .mid_rid        = 0xce,
         }, {
                 .slave_id       = SHDMA_SLAVE_FSIA_TX,
                 .addr           = 0xfe1f0024,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
                 .mid_rid        = 0xb1,
         }, {
                 .slave_id       = SHDMA_SLAVE_FSIA_RX,
                 .addr           = 0xfe1f0020,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
                 .mid_rid        = 0xb2,
         }, {
                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
                 .addr           = 0xe6bd0034,
-                .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
                 .mid_rid        = 0xd1,
         }, {
                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
                 .addr           = 0xe6bd0034,
-                .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
                 .mid_rid        = 0xd2,
         },
 };
@@ -520,19 +496,17 @@ static const struct sh_dmae_channel sh7372_dmae_channels[] = {
         }
 };
 
-static const unsigned int ts_shift[] = TS_SHIFT;
-
 static struct sh_dmae_pdata dma_platform_data = {
         .slave          = sh7372_dmae_slaves,
         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
         .channel        = sh7372_dmae_channels,
         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
-        .ts_low_shift   = 3,
-        .ts_low_mask    = 0x18,
-        .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
-        .ts_high_mask   = 0x00300000,
-        .ts_shift       = ts_shift,
-        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .ts_low_shift   = TS_LOW_SHIFT,
+        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
+        .ts_high_shift  = TS_HI_SHIFT,
+        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
+        .ts_shift       = dma_ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
         .dmaor_init     = DMAOR_DME,
         .chclr_present  = 1,
 };
@@ -654,17 +628,6 @@ static struct platform_device dma2_device = {
 /*
  * USB-DMAC
  */
-
-unsigned int usbts_shift[] = {3, 4, 5};
-
-enum {
-        XMIT_SZ_8BYTE           = 0,
-        XMIT_SZ_16BYTE          = 1,
-        XMIT_SZ_32BYTE          = 2,
-};
-
-#define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
-
 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
         {
                 .offset = 0,
@@ -677,10 +640,10 @@ static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
         {
                 .slave_id       = SHDMA_SLAVE_USB0_TX,
-                .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
+                .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
         }, {
                 .slave_id       = SHDMA_SLAVE_USB0_RX,
-                .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
+                .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
         },
 };
 
@@ -689,12 +652,12 @@ static struct sh_dmae_pdata usb_dma0_platform_data = {
         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
         .channel        = sh7372_usb_dmae_channels,
         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
-        .ts_low_shift   = 6,
-        .ts_low_mask    = 0xc0,
-        .ts_high_shift  = 0,
-        .ts_high_mask   = 0,
-        .ts_shift       = usbts_shift,
-        .ts_shift_num   = ARRAY_SIZE(usbts_shift),
+        .ts_low_shift   = USBTS_LOW_SHIFT,
+        .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
+        .ts_high_shift  = USBTS_HI_SHIFT,
+        .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
+        .ts_shift       = dma_usbts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
         .dmaor_init     = DMAOR_DME,
         .chcr_offset    = 0x14,
         .chcr_ie_bit    = 1 << 5,
@@ -739,10 +702,10 @@ static struct platform_device usb_dma0_device = {
 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
         {
                 .slave_id       = SHDMA_SLAVE_USB1_TX,
-                .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
+                .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
         }, {
                 .slave_id       = SHDMA_SLAVE_USB1_RX,
-                .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
+                .chcr           = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
         },
 };
 
@@ -751,12 +714,12 @@ static struct sh_dmae_pdata usb_dma1_platform_data = {
         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
         .channel        = sh7372_usb_dmae_channels,
         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
-        .ts_low_shift   = 6,
-        .ts_low_mask    = 0xc0,
-        .ts_high_shift  = 0,
-        .ts_high_mask   = 0,
-        .ts_shift       = usbts_shift,
-        .ts_shift_num   = ARRAY_SIZE(usbts_shift),
+        .ts_low_shift   = USBTS_LOW_SHIFT,
+        .ts_low_mask    = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
+        .ts_high_shift  = USBTS_HI_SHIFT,
+        .ts_high_mask   = USBTS_HI_BIT << USBTS_HI_SHIFT,
+        .ts_shift       = dma_usbts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_usbts_shift),
         .dmaor_init     = DMAOR_DME,
         .chcr_offset    = 0x14,
         .chcr_ie_bit    = 1 << 5,
@@ -1038,21 +1001,21 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
 
 void __init sh7372_add_standard_devices(void)
 {
-        sh7372_init_pm_domain(&sh7372_a4lc);
-        sh7372_init_pm_domain(&sh7372_a4mp);
-        sh7372_init_pm_domain(&sh7372_d4);
-        sh7372_init_pm_domain(&sh7372_a4r);
-        sh7372_init_pm_domain(&sh7372_a3rv);
-        sh7372_init_pm_domain(&sh7372_a3ri);
-        sh7372_init_pm_domain(&sh7372_a4s);
-        sh7372_init_pm_domain(&sh7372_a3sp);
-        sh7372_init_pm_domain(&sh7372_a3sg);
-
-        sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
-        sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
-
-        sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
-        sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
+        rmobile_init_pm_domain(&sh7372_pd_a4lc);
+        rmobile_init_pm_domain(&sh7372_pd_a4mp);
+        rmobile_init_pm_domain(&sh7372_pd_d4);
+        rmobile_init_pm_domain(&sh7372_pd_a4r);
+        rmobile_init_pm_domain(&sh7372_pd_a3rv);
+        rmobile_init_pm_domain(&sh7372_pd_a3ri);
+        rmobile_init_pm_domain(&sh7372_pd_a4s);
+        rmobile_init_pm_domain(&sh7372_pd_a3sp);
+        rmobile_init_pm_domain(&sh7372_pd_a3sg);
+
+        rmobile_pm_add_subdomain(&sh7372_pd_a4lc, &sh7372_pd_a3rv);
+        rmobile_pm_add_subdomain(&sh7372_pd_a4r, &sh7372_pd_a4lc);
+
+        rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sg);
+        rmobile_pm_add_subdomain(&sh7372_pd_a4s, &sh7372_pd_a3sp);
 
         platform_add_devices(sh7372_early_devices,
                             ARRAY_SIZE(sh7372_early_devices));
@@ -1060,30 +1023,30 @@ void __init sh7372_add_standard_devices(void)
         platform_add_devices(sh7372_late_devices,
                             ARRAY_SIZE(sh7372_late_devices));
 
-        sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
-        sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
-        sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
-        sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
-        sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
-        sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
-        sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
-        sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
-        sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
-        sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
-        sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device);
-        sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3rv, &vpu_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu0_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4mp, &spu1_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif0_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif1_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif2_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif3_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif4_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif5_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &scif6_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &iic1_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma0_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma1_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &dma2_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma0_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a3sp, &usb_dma1_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4r, &iic0_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu0_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu1_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu2_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4r, &veu3_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4r, &jpu_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu00_device);
+        rmobile_add_device_to_domain(&sh7372_pd_a4r, &tmu01_device);
 }
 
 static void __init sh7372_earlytimer_init(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index d576a6abbad..855b1506caf 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/of_platform.h>
 #include <linux/uio_driver.h>
 #include <linux/delay.h>
 #include <linux/input.h>
@@ -500,3 +501,49 @@ void __init sh7377_add_early_devices(void)
         /* override timer setup with soc-specific code */
         shmobile_timer.init = sh7377_earlytimer_init;
 }
+
+#ifdef CONFIG_USE_OF
+
+void __init sh7377_add_early_devices_dt(void)
+{
+        shmobile_setup_delay(600, 1, 3); /* Cortex-A8 @ 600MHz */
+
+        early_platform_add_devices(sh7377_early_devices,
+                                   ARRAY_SIZE(sh7377_early_devices));
+
+        /* setup early console here as well */
+        shmobile_setup_console();
+}
+
+static const struct of_dev_auxdata sh7377_auxdata_lookup[] __initconst = {
+        { }
+};
+
+void __init sh7377_add_standard_devices_dt(void)
+{
+        /* clocks are setup late during boot in the case of DT */
+        sh7377_clock_init();
+
+        platform_add_devices(sh7377_early_devices,
+                            ARRAY_SIZE(sh7377_early_devices));
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             sh7377_auxdata_lookup, NULL);
+}
+
+static const char *sh7377_boards_compat_dt[] __initdata = {
+        "renesas,sh7377",
+        NULL,
+};
+
+DT_MACHINE_START(SH7377_DT, "Generic SH7377 (Flattened Device Tree)")
+        .map_io         = sh7377_map_io,
+        .init_early     = sh7377_add_early_devices_dt,
+        .init_irq       = sh7377_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = sh7377_add_standard_devices_dt,
+        .timer          = &shmobile_timer,
+        .dt_compat      = sh7377_boards_compat_dt,
+MACHINE_END
+
+#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 04a0dfe7549..d230af656fc 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -30,6 +30,7 @@
 #include <linux/sh_dma.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
+#include <mach/dma-register.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/sh73a0.h>
@@ -415,32 +416,6 @@ static struct platform_device i2c4_device = {
         .num_resources  = ARRAY_SIZE(i2c4_resources),
 };
 
-/* Transmit sizes and respective CHCR register values */
-enum {
-        XMIT_SZ_8BIT            = 0,
-        XMIT_SZ_16BIT           = 1,
-        XMIT_SZ_32BIT           = 2,
-        XMIT_SZ_64BIT           = 7,
-        XMIT_SZ_128BIT          = 3,
-        XMIT_SZ_256BIT          = 4,
-        XMIT_SZ_512BIT          = 5,
-};
-
-/* log2(size / 8) - used to calculate number of transfers */
-#define TS_SHIFT {                      \
-        [XMIT_SZ_8BIT]          = 0,    \
-        [XMIT_SZ_16BIT]         = 1,    \
-        [XMIT_SZ_32BIT]         = 2,    \
-        [XMIT_SZ_64BIT]         = 3,    \
-        [XMIT_SZ_128BIT]        = 4,    \
-        [XMIT_SZ_256BIT]        = 5,    \
-        [XMIT_SZ_512BIT]        = 6,    \
-}
-
-#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
-#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
-#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
-
 static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
         {
                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
@@ -604,19 +579,17 @@ static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
         DMAE_CHANNEL(0x8980),
 };
 
-static const unsigned int ts_shift[] = TS_SHIFT;
-
 static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
         .slave          = sh73a0_dmae_slaves,
         .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
         .channel        = sh73a0_dmae_channels,
         .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
-        .ts_low_shift   = 3,
-        .ts_low_mask    = 0x18,
-        .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
-        .ts_high_mask   = 0x00300000,
-        .ts_shift       = ts_shift,
-        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .ts_low_shift   = TS_LOW_SHIFT,
+        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
+        .ts_high_shift  = TS_HI_SHIFT,
+        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
+        .ts_shift       = dma_ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
         .dmaor_init     = DMAOR_DME,
 };
 
@@ -651,6 +624,116 @@ static struct platform_device dma0_device = {
         },
 };
 
+/* MPDMAC */
+static const struct sh_dmae_slave_config sh73a0_mpdma_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_FSI2A_RX,
+                .addr           = 0xec230020,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd6, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2A_TX,
+                .addr           = 0xec230024,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd5, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2C_RX,
+                .addr           = 0xec230060,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xda, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2C_TX,
+                .addr           = 0xec230064,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd9, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2B_RX,
+                .addr           = 0xec240020,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x8e, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2B_TX,
+                .addr           = 0xec240024,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x8d, /* CHECK ME */
+        }, {
+                .slave_id       = SHDMA_SLAVE_FSI2D_RX,
+                .addr           =  0xec240060,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0x9a, /* CHECK ME */
+        },
+};
+
+#define MPDMA_CHANNEL(a, b, c)                  \
+{                                               \
+        .offset         = a,                    \
+        .dmars          = b,                    \
+        .dmars_bit      = c,                    \
+        .chclr_offset   = (0x220 - 0x20) + a    \
+}
+
+static const struct sh_dmae_channel sh73a0_mpdma_channels[] = {
+        MPDMA_CHANNEL(0x00, 0, 0),
+        MPDMA_CHANNEL(0x10, 0, 8),
+        MPDMA_CHANNEL(0x20, 4, 0),
+        MPDMA_CHANNEL(0x30, 4, 8),
+        MPDMA_CHANNEL(0x50, 8, 0),
+        MPDMA_CHANNEL(0x70, 8, 8),
+};
+
+static struct sh_dmae_pdata sh73a0_mpdma_platform_data = {
+        .slave          = sh73a0_mpdma_slaves,
+        .slave_num      = ARRAY_SIZE(sh73a0_mpdma_slaves),
+        .channel        = sh73a0_mpdma_channels,
+        .channel_num    = ARRAY_SIZE(sh73a0_mpdma_channels),
+        .ts_low_shift   = TS_LOW_SHIFT,
+        .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
+        .ts_high_shift  = TS_HI_SHIFT,
+        .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
+        .ts_shift       = dma_ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
+        .dmaor_init     = DMAOR_DME,
+        .chclr_present  = 1,
+};
+
+/* Resource order important! */
+static struct resource sh73a0_mpdma_resources[] = {
+        {
+                /* Channel registers and DMAOR */
+                .start  = 0xec618020,
+                .end    = 0xec61828f,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMARSx */
+                .start  = 0xec619000,
+                .end    = 0xec61900b,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "error_irq",
+                .start  = gic_spi(181),
+                .end    = gic_spi(181),
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-5 */
+                .start  = gic_spi(175),
+                .end    = gic_spi(180),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mpdma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 1,
+        .resource       = sh73a0_mpdma_resources,
+        .num_resources  = ARRAY_SIZE(sh73a0_mpdma_resources),
+        .dev            = {
+                .platform_data  = &sh73a0_mpdma_platform_data,
+        },
+};
+
 static struct platform_device *sh73a0_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -673,6 +756,7 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
         &i2c3_device,
         &i2c4_device,
         &dma0_device,
+        &mpdma0_device,
 };
 
 #define SRCR2          0xe61580b0
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
new file mode 100644
index 00000000000..4fb93240971
--- /dev/null
+++ b/arch/arm/mach-socfpga/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y                                   := socfpga.o
diff --git a/arch/arm/mach-socfpga/Makefile.boot b/arch/arm/mach-socfpga/Makefile.boot
new file mode 100644
index 00000000000..dae9661a768
--- /dev/null
+++ b/arch/arm/mach-socfpga/Makefile.boot
@@ -0,0 +1 @@
+zreladdr-y      := 0x00008000
diff --git a/arch/arm/mach-socfpga/include/mach/debug-macro.S b/arch/arm/mach-socfpga/include/mach/debug-macro.S
new file mode 100644
index 00000000000..d6f26d23374
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/debug-macro.S
@@ -0,0 +1,16 @@
+/*
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+                .macro  addruart, rp, rv, tmp
+                mov     \rp, #DEBUG_LL_UART_OFFSET
+                orr     \rp, \rp, #0x00c00000
+                orr     \rv, \rp, #0xfe000000   @ virtual base
+                orr     \rp, \rp, #0xff000000   @ physical base
+                .endm
+
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-socfpga/include/mach/timex.h
index ac8b7dfc85e..43df4354e46 100644
--- a/arch/arm/mach-at91/include/mach/irqs.h
+++ b/arch/arm/mach-socfpga/include/mach/timex.h
@@ -1,7 +1,5 @@
 /*
- * arch/arm/mach-at91/include/mach/irqs.h
- *
- *  Copyright (C) 2004 SAN People
+ *  Copyright (C) 2003 ARM Limited
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,31 +16,4 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#include <linux/io.h>
-#include <mach/at91_aic.h>
-
-#define NR_AIC_IRQS 32
-
-
-/*
- * Acknowledge interrupt with AIC after interrupt has been handled.
- *   (by kernel/irq.c)
- */
-#define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0)
-
-
-/*
- * IRQ interrupt symbols are the AT91xxx_ID_* symbols
- * for IRQs handled directly through the AIC, or else the AT91_PIN_*
- * symbols in gpio.h for ones handled indirectly as GPIOs.
- * We make provision for 5 banks of GPIO.
- */
-#define NR_IRQS         (NR_AIC_IRQS + (5 * 32))
-
-/* FIQ is AIC source 0. */
-#define FIQ_START AT91_ID_FIQ
-
-#endif
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/arch/arm/mach-socfpga/include/mach/uncompress.h b/arch/arm/mach-socfpga/include/mach/uncompress.h
new file mode 100644
index 00000000000..bbe20e69632
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/uncompress.h
@@ -0,0 +1,9 @@
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#define putc(c)
+#define flush()
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
new file mode 100644
index 00000000000..f01e1ebf539
--- /dev/null
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -0,0 +1,62 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/dw_apb_timer.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/arch.h>
+
+extern void socfpga_init_clocks(void);
+
+const static struct of_device_id irq_match[] = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {}
+};
+
+static void __init gic_init_irq(void)
+{
+        of_irq_init(irq_match);
+}
+
+static void socfpga_cyclone5_restart(char mode, const char *cmd)
+{
+        /* TODO: */
+}
+
+static void __init socfpga_cyclone5_init(void)
+{
+        l2x0_of_init(0, ~0UL);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        socfpga_init_clocks();
+}
+
+static const char *altera_dt_match[] = {
+        "altr,socfpga",
+        "altr,socfpga-cyclone5",
+        NULL
+};
+
+DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
+        .init_irq       = gic_init_irq,
+        .handle_irq     = gic_handle_irq,
+        .timer          = &dw_apb_timer,
+        .init_machine   = socfpga_cyclone5_init,
+        .restart        = socfpga_cyclone5_restart,
+        .dt_compat      = altera_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 0f882ecb7d8..6ec30054996 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -120,182 +120,156 @@ struct pl08x_channel_data spear300_dma_info[] = {
                 .min_signal = 2,
                 .max_signal = 2,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart0_tx",
                 .min_signal = 3,
                 .max_signal = 3,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ssp0_rx",
                 .min_signal = 8,
                 .max_signal = 8,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ssp0_tx",
                 .min_signal = 9,
                 .max_signal = 9,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "i2c_rx",
                 .min_signal = 10,
                 .max_signal = 10,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "i2c_tx",
                 .min_signal = 11,
                 .max_signal = 11,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "irda",
                 .min_signal = 12,
                 .max_signal = 12,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "adc",
                 .min_signal = 13,
                 .max_signal = 13,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "to_jpeg",
                 .min_signal = 14,
                 .max_signal = 14,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "from_jpeg",
                 .min_signal = 15,
                 .max_signal = 15,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras0_rx",
                 .min_signal = 0,
                 .max_signal = 0,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras0_tx",
                 .min_signal = 1,
                 .max_signal = 1,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras1_rx",
                 .min_signal = 2,
                 .max_signal = 2,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras1_tx",
                 .min_signal = 3,
                 .max_signal = 3,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras2_rx",
                 .min_signal = 4,
                 .max_signal = 4,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras2_tx",
                 .min_signal = 5,
                 .max_signal = 5,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras3_rx",
                 .min_signal = 6,
                 .max_signal = 6,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras3_tx",
                 .min_signal = 7,
                 .max_signal = 7,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras4_rx",
                 .min_signal = 8,
                 .max_signal = 8,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras4_tx",
                 .min_signal = 9,
                 .max_signal = 9,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras5_rx",
                 .min_signal = 10,
                 .max_signal = 10,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras5_tx",
                 .min_signal = 11,
                 .max_signal = 11,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras6_rx",
                 .min_signal = 12,
                 .max_signal = 12,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras6_tx",
                 .min_signal = 13,
                 .max_signal = 13,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras7_rx",
                 .min_signal = 14,
                 .max_signal = 14,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras7_tx",
                 .min_signal = 15,
                 .max_signal = 15,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         },
 };
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index bbcf4571d36..1d0e435b904 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -205,182 +205,156 @@ struct pl08x_channel_data spear310_dma_info[] = {
                 .min_signal = 2,
                 .max_signal = 2,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart0_tx",
                 .min_signal = 3,
                 .max_signal = 3,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ssp0_rx",
                 .min_signal = 8,
                 .max_signal = 8,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ssp0_tx",
                 .min_signal = 9,
                 .max_signal = 9,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "i2c_rx",
                 .min_signal = 10,
                 .max_signal = 10,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "i2c_tx",
                 .min_signal = 11,
                 .max_signal = 11,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "irda",
                 .min_signal = 12,
                 .max_signal = 12,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "adc",
                 .min_signal = 13,
                 .max_signal = 13,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "to_jpeg",
                 .min_signal = 14,
                 .max_signal = 14,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "from_jpeg",
                 .min_signal = 15,
                 .max_signal = 15,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart1_rx",
                 .min_signal = 0,
                 .max_signal = 0,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart1_tx",
                 .min_signal = 1,
                 .max_signal = 1,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart2_rx",
                 .min_signal = 2,
                 .max_signal = 2,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart2_tx",
                 .min_signal = 3,
                 .max_signal = 3,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart3_rx",
                 .min_signal = 4,
                 .max_signal = 4,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart3_tx",
                 .min_signal = 5,
                 .max_signal = 5,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart4_rx",
                 .min_signal = 6,
                 .max_signal = 6,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart4_tx",
                 .min_signal = 7,
                 .max_signal = 7,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart5_rx",
                 .min_signal = 8,
                 .max_signal = 8,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart5_tx",
                 .min_signal = 9,
                 .max_signal = 9,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras5_rx",
                 .min_signal = 10,
                 .max_signal = 10,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras5_tx",
                 .min_signal = 11,
                 .max_signal = 11,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras6_rx",
                 .min_signal = 12,
                 .max_signal = 12,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras6_tx",
                 .min_signal = 13,
                 .max_signal = 13,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras7_rx",
                 .min_signal = 14,
                 .max_signal = 14,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras7_tx",
                 .min_signal = 15,
                 .max_signal = 15,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         },
 };
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 88d483bcd66..fd823c62457 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -213,182 +213,156 @@ struct pl08x_channel_data spear320_dma_info[] = {
                 .min_signal = 2,
                 .max_signal = 2,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart0_tx",
                 .min_signal = 3,
                 .max_signal = 3,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ssp0_rx",
                 .min_signal = 8,
                 .max_signal = 8,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ssp0_tx",
                 .min_signal = 9,
                 .max_signal = 9,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "i2c0_rx",
                 .min_signal = 10,
                 .max_signal = 10,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "i2c0_tx",
                 .min_signal = 11,
                 .max_signal = 11,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "irda",
                 .min_signal = 12,
                 .max_signal = 12,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "adc",
                 .min_signal = 13,
                 .max_signal = 13,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "to_jpeg",
                 .min_signal = 14,
                 .max_signal = 14,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "from_jpeg",
                 .min_signal = 15,
                 .max_signal = 15,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ssp1_rx",
                 .min_signal = 0,
                 .max_signal = 0,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ssp1_tx",
                 .min_signal = 1,
                 .max_signal = 1,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ssp2_rx",
                 .min_signal = 2,
                 .max_signal = 2,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ssp2_tx",
                 .min_signal = 3,
                 .max_signal = 3,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "uart1_rx",
                 .min_signal = 4,
                 .max_signal = 4,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "uart1_tx",
                 .min_signal = 5,
                 .max_signal = 5,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "uart2_rx",
                 .min_signal = 6,
                 .max_signal = 6,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "uart2_tx",
                 .min_signal = 7,
                 .max_signal = 7,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "i2c1_rx",
                 .min_signal = 8,
                 .max_signal = 8,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "i2c1_tx",
                 .min_signal = 9,
                 .max_signal = 9,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "i2c2_rx",
                 .min_signal = 10,
                 .max_signal = 10,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "i2c2_tx",
                 .min_signal = 11,
                 .max_signal = 11,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "i2s_rx",
                 .min_signal = 12,
                 .max_signal = 12,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "i2s_tx",
                 .min_signal = 13,
                 .max_signal = 13,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "rs485_rx",
                 .min_signal = 14,
                 .max_signal = 14,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "rs485_tx",
                 .min_signal = 15,
                 .max_signal = 15,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         },
 };
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 66db5f13af8..98144baf888 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -46,7 +46,8 @@ struct pl022_ssp_controller pl022_plat_data = {
 struct pl08x_platform_data pl080_plat_data = {
         .memcpy_channel = {
                 .bus_id = "memcpy",
-                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                .cctl_memcpy =
+                        (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
                         PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
                         PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
                         PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 9af67d003c6..5a5a52db252 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -36,336 +36,288 @@ static struct pl08x_channel_data spear600_dma_info[] = {
                 .min_signal = 0,
                 .max_signal = 0,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ssp1_tx",
                 .min_signal = 1,
                 .max_signal = 1,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart0_rx",
                 .min_signal = 2,
                 .max_signal = 2,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart0_tx",
                 .min_signal = 3,
                 .max_signal = 3,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart1_rx",
                 .min_signal = 4,
                 .max_signal = 4,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "uart1_tx",
                 .min_signal = 5,
                 .max_signal = 5,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ssp2_rx",
                 .min_signal = 6,
                 .max_signal = 6,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ssp2_tx",
                 .min_signal = 7,
                 .max_signal = 7,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ssp0_rx",
                 .min_signal = 8,
                 .max_signal = 8,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ssp0_tx",
                 .min_signal = 9,
                 .max_signal = 9,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "i2c_rx",
                 .min_signal = 10,
                 .max_signal = 10,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "i2c_tx",
                 .min_signal = 11,
                 .max_signal = 11,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "irda",
                 .min_signal = 12,
                 .max_signal = 12,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "adc",
                 .min_signal = 13,
                 .max_signal = 13,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "to_jpeg",
                 .min_signal = 14,
                 .max_signal = 14,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "from_jpeg",
                 .min_signal = 15,
                 .max_signal = 15,
                 .muxval = 0,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras0_rx",
                 .min_signal = 0,
                 .max_signal = 0,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras0_tx",
                 .min_signal = 1,
                 .max_signal = 1,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras1_rx",
                 .min_signal = 2,
                 .max_signal = 2,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras1_tx",
                 .min_signal = 3,
                 .max_signal = 3,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras2_rx",
                 .min_signal = 4,
                 .max_signal = 4,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras2_tx",
                 .min_signal = 5,
                 .max_signal = 5,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras3_rx",
                 .min_signal = 6,
                 .max_signal = 6,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras3_tx",
                 .min_signal = 7,
                 .max_signal = 7,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras4_rx",
                 .min_signal = 8,
                 .max_signal = 8,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras4_tx",
                 .min_signal = 9,
                 .max_signal = 9,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras5_rx",
                 .min_signal = 10,
                 .max_signal = 10,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras5_tx",
                 .min_signal = 11,
                 .max_signal = 11,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras6_rx",
                 .min_signal = 12,
                 .max_signal = 12,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras6_tx",
                 .min_signal = 13,
                 .max_signal = 13,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras7_rx",
                 .min_signal = 14,
                 .max_signal = 14,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ras7_tx",
                 .min_signal = 15,
                 .max_signal = 15,
                 .muxval = 1,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB1,
         }, {
                 .bus_id = "ext0_rx",
                 .min_signal = 0,
                 .max_signal = 0,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext0_tx",
                 .min_signal = 1,
                 .max_signal = 1,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext1_rx",
                 .min_signal = 2,
                 .max_signal = 2,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext1_tx",
                 .min_signal = 3,
                 .max_signal = 3,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext2_rx",
                 .min_signal = 4,
                 .max_signal = 4,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext2_tx",
                 .min_signal = 5,
                 .max_signal = 5,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext3_rx",
                 .min_signal = 6,
                 .max_signal = 6,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext3_tx",
                 .min_signal = 7,
                 .max_signal = 7,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext4_rx",
                 .min_signal = 8,
                 .max_signal = 8,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext4_tx",
                 .min_signal = 9,
                 .max_signal = 9,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext5_rx",
                 .min_signal = 10,
                 .max_signal = 10,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext5_tx",
                 .min_signal = 11,
                 .max_signal = 11,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext6_rx",
                 .min_signal = 12,
                 .max_signal = 12,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext6_tx",
                 .min_signal = 13,
                 .max_signal = 13,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext7_rx",
                 .min_signal = 14,
                 .max_signal = 14,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         }, {
                 .bus_id = "ext7_tx",
                 .min_signal = 15,
                 .max_signal = 15,
                 .muxval = 2,
-                .cctl = 0,
                 .periph_buses = PL08X_AHB2,
         },
 };
@@ -373,7 +325,8 @@ static struct pl08x_channel_data spear600_dma_info[] = {
 struct pl08x_platform_data pl080_plat_data = {
         .memcpy_channel = {
                 .bus_id = "memcpy",
-                .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+                .cctl_memcpy =
+                        (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
                         PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
                         PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
                         PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 6a113a9bb87..9077aaa398d 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -63,40 +63,15 @@ comment "Tegra board type"
 config MACH_HARMONY
        bool "Harmony board"
        depends on ARCH_TEGRA_2x_SOC
-       select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
          Support for nVidia Harmony development platform
 
-config MACH_KAEN
-       bool "Kaen board"
-       depends on ARCH_TEGRA_2x_SOC
-       select MACH_SEABOARD
-       select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
-       help
-         Support for the Kaen version of Seaboard
-
 config MACH_PAZ00
        bool "Paz00 board"
        depends on ARCH_TEGRA_2x_SOC
        help
          Support for the Toshiba AC100/Dynabook AZ netbook
 
-config MACH_SEABOARD
-       bool "Seaboard board"
-       depends on ARCH_TEGRA_2x_SOC
-       select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
-       help
-         Support for nVidia Seaboard development platform. It will
-         also be included for some of the derivative boards that
-         have large similarities with the seaboard design.
-
-config MACH_TEGRA_DT
-        bool "Generic Tegra20 board (FDT support)"
-        depends on ARCH_TEGRA_2x_SOC
-        select USE_OF
-        help
-          Support for generic NVIDIA Tegra20 boards using Flattened Device Tree
-
 config MACH_TRIMSLICE
        bool "TrimSlice board"
        depends on ARCH_TEGRA_2x_SOC
@@ -104,20 +79,6 @@ config MACH_TRIMSLICE
        help
          Support for CompuLab TrimSlice platform
 
-config MACH_WARIO
-       bool "Wario board"
-       depends on ARCH_TEGRA_2x_SOC
-       select MACH_SEABOARD
-       help
-         Support for the Wario version of Seaboard
-
-config MACH_VENTANA
-       bool "Ventana board"
-       depends on ARCH_TEGRA_2x_SOC
-       select MACH_TEGRA_DT
-       help
-         Support for the nVidia Ventana development platform
-
 choice
         prompt "Default low-level debug console UART"
         default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 2eb4445ddb1..c3d7303b9ac 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -8,21 +8,24 @@ obj-y                                   += timer.o
 obj-y                                   += fuse.o
 obj-y                                   += pmc.o
 obj-y                                   += flowctrl.o
+obj-y                                   += powergate.o
+obj-y                                   += apbio.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_CPU_IDLE)                  += sleep.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += powergate.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += tegra30_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o apbio.o
+obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
 
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-dt-tegra20.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
+
 obj-$(CONFIG_MACH_HARMONY)              += board-harmony.o
 obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pinmux.o
 obj-$(CONFIG_MACH_HARMONY)              += board-harmony-pcie.o
@@ -31,14 +34,5 @@ obj-$(CONFIG_MACH_HARMONY)              += board-harmony-power.o
 obj-$(CONFIG_MACH_PAZ00)                += board-paz00.o
 obj-$(CONFIG_MACH_PAZ00)                += board-paz00-pinmux.o
 
-obj-$(CONFIG_MACH_SEABOARD)             += board-seaboard.o
-obj-$(CONFIG_MACH_SEABOARD)             += board-seaboard-pinmux.o
-
-obj-$(CONFIG_MACH_TEGRA_DT)             += board-dt-tegra20.o
-obj-$(CONFIG_MACH_TEGRA_DT)             += board-harmony-pinmux.o
-obj-$(CONFIG_MACH_TEGRA_DT)             += board-seaboard-pinmux.o
-obj-$(CONFIG_MACH_TEGRA_DT)             += board-paz00-pinmux.o
-obj-$(CONFIG_MACH_TEGRA_DT)             += board-trimslice-pinmux.o
-
 obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice.o
 obj-$(CONFIG_MACH_TRIMSLICE)            += board-trimslice-pinmux.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 9a82094092d..7a1bb62ddcf 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -2,9 +2,10 @@ zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC)	+= 0x00008000
 params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
 
-dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
-dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb
-dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
-dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb
-dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
-dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-harmony.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-paz00.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-seaboard.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-trimslice.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-ventana.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb
+dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index e75451e517b..dc0fe389be5 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -15,6 +15,9 @@
 
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <mach/iomap.h>
+#include <linux/of.h>
+#include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
 #include <linux/spinlock.h>
 #include <linux/completion.h>
@@ -22,17 +25,21 @@
 #include <linux/mutex.h>
 
 #include <mach/dma.h>
-#include <mach/iomap.h>
 
 #include "apbio.h"
 
+#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA)
 static DEFINE_MUTEX(tegra_apb_dma_lock);
-
-static struct tegra_dma_channel *tegra_apb_dma;
 static u32 *tegra_apb_bb;
 static dma_addr_t tegra_apb_bb_phys;
 static DECLARE_COMPLETION(tegra_apb_wait);
 
+static u32 tegra_apb_readl_direct(unsigned long offset);
+static void tegra_apb_writel_direct(u32 value, unsigned long offset);
+
+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
+static struct tegra_dma_channel *tegra_apb_dma;
+
 bool tegra_apb_init(void)
 {
         struct tegra_dma_channel *ch;
@@ -72,13 +79,13 @@ static void apb_dma_complete(struct tegra_dma_req *req)
         complete(&tegra_apb_wait);
 }
 
-u32 tegra_apb_readl(unsigned long offset)
+static u32 tegra_apb_readl_using_dma(unsigned long offset)
 {
         struct tegra_dma_req req;
         int ret;
 
         if (!tegra_apb_dma && !tegra_apb_init())
-                return readl(IO_TO_VIRT(offset));
+                return tegra_apb_readl_direct(offset);
 
         mutex_lock(&tegra_apb_dma_lock);
         req.complete = apb_dma_complete;
@@ -108,13 +115,13 @@ u32 tegra_apb_readl(unsigned long offset)
         return *((u32 *)tegra_apb_bb);
 }
 
-void tegra_apb_writel(u32 value, unsigned long offset)
+static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
 {
         struct tegra_dma_req req;
         int ret;
 
         if (!tegra_apb_dma && !tegra_apb_init()) {
-                writel(value, IO_TO_VIRT(offset));
+                tegra_apb_writel_direct(value, offset);
                 return;
         }
 
@@ -143,3 +150,176 @@ void tegra_apb_writel(u32 value, unsigned long offset)
 
         mutex_unlock(&tegra_apb_dma_lock);
 }
+
+#else
+static struct dma_chan *tegra_apb_dma_chan;
+static struct dma_slave_config dma_sconfig;
+
+bool tegra_apb_dma_init(void)
+{
+        dma_cap_mask_t mask;
+
+        mutex_lock(&tegra_apb_dma_lock);
+
+        /* Check to see if we raced to setup */
+        if (tegra_apb_dma_chan)
+                goto skip_init;
+
+        dma_cap_zero(mask);
+        dma_cap_set(DMA_SLAVE, mask);
+        tegra_apb_dma_chan = dma_request_channel(mask, NULL, NULL);
+        if (!tegra_apb_dma_chan) {
+                /*
+                 * This is common until the device is probed, so don't
+                 * shout about it.
+                 */
+                pr_debug("%s: can not allocate dma channel\n", __func__);
+                goto err_dma_alloc;
+        }
+
+        tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
+                &tegra_apb_bb_phys, GFP_KERNEL);
+        if (!tegra_apb_bb) {
+                pr_err("%s: can not allocate bounce buffer\n", __func__);
+                goto err_buff_alloc;
+        }
+
+        dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+        dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+        dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR;
+        dma_sconfig.src_maxburst = 1;
+        dma_sconfig.dst_maxburst = 1;
+
+skip_init:
+        mutex_unlock(&tegra_apb_dma_lock);
+        return true;
+
+err_buff_alloc:
+        dma_release_channel(tegra_apb_dma_chan);
+        tegra_apb_dma_chan = NULL;
+
+err_dma_alloc:
+        mutex_unlock(&tegra_apb_dma_lock);
+        return false;
+}
+
+static void apb_dma_complete(void *args)
+{
+        complete(&tegra_apb_wait);
+}
+
+static int do_dma_transfer(unsigned long apb_add,
+                enum dma_transfer_direction dir)
+{
+        struct dma_async_tx_descriptor *dma_desc;
+        int ret;
+
+        if (dir == DMA_DEV_TO_MEM)
+                dma_sconfig.src_addr = apb_add;
+        else
+                dma_sconfig.dst_addr = apb_add;
+
+        ret = dmaengine_slave_config(tegra_apb_dma_chan, &dma_sconfig);
+        if (ret)
+                return ret;
+
+        dma_desc = dmaengine_prep_slave_single(tegra_apb_dma_chan,
+                        tegra_apb_bb_phys, sizeof(u32), dir,
+                        DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
+        if (!dma_desc)
+                return -EINVAL;
+
+        dma_desc->callback = apb_dma_complete;
+        dma_desc->callback_param = NULL;
+
+        INIT_COMPLETION(tegra_apb_wait);
+
+        dmaengine_submit(dma_desc);
+        dma_async_issue_pending(tegra_apb_dma_chan);
+        ret = wait_for_completion_timeout(&tegra_apb_wait,
+                msecs_to_jiffies(50));
+
+        if (WARN(ret == 0, "apb read dma timed out")) {
+                dmaengine_terminate_all(tegra_apb_dma_chan);
+                return -EFAULT;
+        }
+        return 0;
+}
+
+static u32 tegra_apb_readl_using_dma(unsigned long offset)
+{
+        int ret;
+
+        if (!tegra_apb_dma_chan && !tegra_apb_dma_init())
+                return tegra_apb_readl_direct(offset);
+
+        mutex_lock(&tegra_apb_dma_lock);
+        ret = do_dma_transfer(offset, DMA_DEV_TO_MEM);
+        if (ret < 0) {
+                pr_err("error in reading offset 0x%08lx using dma\n", offset);
+                *(u32 *)tegra_apb_bb = 0;
+        }
+        mutex_unlock(&tegra_apb_dma_lock);
+        return *((u32 *)tegra_apb_bb);
+}
+
+static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
+{
+        int ret;
+
+        if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) {
+                tegra_apb_writel_direct(value, offset);
+                return;
+        }
+
+        mutex_lock(&tegra_apb_dma_lock);
+        *((u32 *)tegra_apb_bb) = value;
+        ret = do_dma_transfer(offset, DMA_MEM_TO_DEV);
+        if (ret < 0)
+                pr_err("error in writing offset 0x%08lx using dma\n", offset);
+        mutex_unlock(&tegra_apb_dma_lock);
+}
+#endif
+#else
+#define tegra_apb_readl_using_dma tegra_apb_readl_direct
+#define tegra_apb_writel_using_dma tegra_apb_writel_direct
+#endif
+
+typedef u32 (*apbio_read_fptr)(unsigned long offset);
+typedef void (*apbio_write_fptr)(u32 value, unsigned long offset);
+
+static apbio_read_fptr apbio_read;
+static apbio_write_fptr apbio_write;
+
+static u32 tegra_apb_readl_direct(unsigned long offset)
+{
+        return readl(IO_TO_VIRT(offset));
+}
+
+static void tegra_apb_writel_direct(u32 value, unsigned long offset)
+{
+        writel(value, IO_TO_VIRT(offset));
+}
+
+void tegra_apb_io_init(void)
+{
+        /* Need to use dma only when it is Tegra20 based platform */
+        if (of_machine_is_compatible("nvidia,tegra20") ||
+                        !of_have_populated_dt()) {
+                apbio_read = tegra_apb_readl_using_dma;
+                apbio_write = tegra_apb_writel_using_dma;
+        } else {
+                apbio_read = tegra_apb_readl_direct;
+                apbio_write = tegra_apb_writel_direct;
+        }
+}
+
+u32 tegra_apb_readl(unsigned long offset)
+{
+        return apbio_read(offset);
+}
+
+void tegra_apb_writel(u32 value, unsigned long offset)
+{
+        apbio_write(value, offset);
+}
diff --git a/arch/arm/mach-tegra/apbio.h b/arch/arm/mach-tegra/apbio.h
index 8b49e8c89a6..f05d71c303c 100644
--- a/arch/arm/mach-tegra/apbio.h
+++ b/arch/arm/mach-tegra/apbio.h
@@ -16,24 +16,7 @@
 #ifndef __MACH_TEGRA_APBIO_H
 #define __MACH_TEGRA_APBIO_H
 
-#ifdef CONFIG_TEGRA_SYSTEM_DMA
-
+void tegra_apb_io_init(void);
 u32 tegra_apb_readl(unsigned long offset);
 void tegra_apb_writel(u32 value, unsigned long offset);
-
-#else
-#include <asm/io.h>
-#include <mach/io.h>
-
-static inline u32 tegra_apb_readl(unsigned long offset)
-{
-        return readl(IO_TO_VIRT(offset));
-}
-
-static inline void tegra_apb_writel(u32 value, unsigned long offset)
-{
-        writel(value, IO_TO_VIRT(offset));
-}
-#endif
-
 #endif
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index eb7249db50a..c0999633a9a 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -64,6 +64,8 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
                        &tegra_ehci2_pdata),
         OF_DEV_AUXDATA("nvidia,tegra20-ehci", TEGRA_USB3_BASE, "tegra-ehci.2",
                        &tegra_ehci3_pdata),
+        OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
         {}
 };
 
@@ -81,11 +83,6 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
         { NULL,         NULL,           0,              0},
 };
 
-static struct of_device_id tegra_dt_match_table[] __initdata = {
-        { .compatible = "simple-bus", },
-        {}
-};
-
 static void __init tegra_dt_init(void)
 {
         tegra_clk_init_from_table(tegra_dt_clk_init_table);
@@ -94,10 +91,74 @@ static void __init tegra_dt_init(void)
          * Finished with the static registrations now; fill in the missing
          * devices
          */
-        of_platform_populate(NULL, tegra_dt_match_table,
+        of_platform_populate(NULL, of_default_bus_match_table,
                                 tegra20_auxdata_lookup, NULL);
 }
 
+#ifdef CONFIG_MACH_TRIMSLICE
+static void __init trimslice_init(void)
+{
+        int ret;
+
+        ret = tegra_pcie_init(true, true);
+        if (ret)
+                pr_err("tegra_pci_init() failed: %d\n", ret);
+}
+#endif
+
+#ifdef CONFIG_MACH_HARMONY
+static void __init harmony_init(void)
+{
+        int ret;
+
+        ret = harmony_regulator_init();
+        if (ret) {
+                pr_err("harmony_regulator_init() failed: %d\n", ret);
+                return;
+        }
+
+        ret = harmony_pcie_init();
+        if (ret)
+                pr_err("harmony_pcie_init() failed: %d\n", ret);
+}
+#endif
+
+#ifdef CONFIG_MACH_PAZ00
+static void __init paz00_init(void)
+{
+        tegra_paz00_wifikill_init();
+}
+#endif
+
+static struct {
+        char *machine;
+        void (*init)(void);
+} board_init_funcs[] = {
+#ifdef CONFIG_MACH_TRIMSLICE
+        { "compulab,trimslice", trimslice_init },
+#endif
+#ifdef CONFIG_MACH_HARMONY
+        { "nvidia,harmony", harmony_init },
+#endif
+#ifdef CONFIG_MACH_PAZ00
+        { "compal,paz00", paz00_init },
+#endif
+};
+
+static void __init tegra_dt_init_late(void)
+{
+        int i;
+
+        tegra_init_late();
+
+        for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) {
+                if (of_machine_is_compatible(board_init_funcs[i].machine)) {
+                        board_init_funcs[i].init();
+                        break;
+                }
+        }
+}
+
 static const char *tegra20_dt_board_compat[] = {
         "nvidia,tegra20",
         NULL
@@ -110,7 +171,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
         .handle_irq     = gic_handle_irq,
         .timer          = &tegra_timer,
         .init_machine   = tegra_dt_init,
-        .init_late      = tegra_init_late,
+        .init_late      = tegra_dt_init_late,
         .restart        = tegra_assert_system_reset,
         .dt_compat      = tegra20_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
index 4f76fa7a5da..53bf60f1158 100644
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ b/arch/arm/mach-tegra/board-dt-tegra30.c
@@ -33,14 +33,11 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
 
+#include <mach/iomap.h>
+
 #include "board.h"
 #include "clock.h"
 
-static struct of_device_id tegra_dt_match_table[] __initdata = {
-        { .compatible = "simple-bus", },
-        {}
-};
-
 struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
@@ -52,6 +49,8 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
         OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
         OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
+        OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
         {}
 };
 
@@ -74,7 +73,7 @@ static void __init tegra30_dt_init(void)
 {
         tegra_clk_init_from_table(tegra_dt_clk_init_table);
 
-        of_platform_populate(NULL, tegra_dt_match_table,
+        of_platform_populate(NULL, of_default_bus_match_table,
                                 tegra30_auxdata_lookup, NULL);
 }
 
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index 33c4fedab84..e8c3fda9bec 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -27,14 +27,11 @@
 
 #ifdef CONFIG_TEGRA_PCI
 
-static int __init harmony_pcie_init(void)
+int __init harmony_pcie_init(void)
 {
         struct regulator *regulator = NULL;
         int err;
 
-        if (!machine_is_harmony())
-                return 0;
-
         err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
         if (err)
                 return err;
@@ -62,7 +59,15 @@ err_reg:
         return err;
 }
 
+static int __init harmony_pcie_initcall(void)
+{
+        if (!machine_is_harmony())
+                return 0;
+
+        return harmony_pcie_init();
+}
+
 /* PCI should be initialized after I2C, mfd and regulators */
-subsys_initcall_sync(harmony_pcie_init);
+subsys_initcall_sync(harmony_pcie_initcall);
 
 #endif
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
index 82f32300796..b7344beec10 100644
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ b/arch/arm/mach-tegra/board-harmony-power.c
@@ -19,7 +19,12 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
 #include <linux/mfd/tps6586x.h>
+#include <linux/of.h>
+#include <linux/of_i2c.h>
+
+#include <asm/mach-types.h>
 
 #include <mach/irqs.h>
 
@@ -30,7 +35,9 @@ static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
 };
 
 static struct regulator_init_data ldo0_data = {
+        .supply_regulator = "vdd_sm2",
         .constraints = {
+                .name = "vdd_ldo0",
                 .min_uV = 3300 * 1000,
                 .max_uV = 3300 * 1000,
                 .valid_modes_mask = (REGULATOR_MODE_NORMAL |
@@ -44,9 +51,11 @@ static struct regulator_init_data ldo0_data = {
         .consumer_supplies = tps658621_ldo0_supply,
 };
 
-#define HARMONY_REGULATOR_INIT(_id, _minmv, _maxmv)                     \
+#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv, _on)\
         static struct regulator_init_data _id##_data = {                \
+                .supply_regulator = _supply,                            \
                 .constraints = {                                        \
+                        .name = _name,                                  \
                         .min_uV = (_minmv)*1000,                        \
                         .max_uV = (_maxmv)*1000,                        \
                         .valid_modes_mask = (REGULATOR_MODE_NORMAL |    \
@@ -54,21 +63,22 @@ static struct regulator_init_data ldo0_data = {
                         .valid_ops_mask = (REGULATOR_CHANGE_MODE |      \
                                            REGULATOR_CHANGE_STATUS |    \
                                            REGULATOR_CHANGE_VOLTAGE),   \
+                        .always_on = _on,                               \
                 },                                                      \
         }
 
-HARMONY_REGULATOR_INIT(sm0, 725, 1500);
-HARMONY_REGULATOR_INIT(sm1, 725, 1500);
-HARMONY_REGULATOR_INIT(sm2, 3000, 4550);
-HARMONY_REGULATOR_INIT(ldo1, 725, 1500);
-HARMONY_REGULATOR_INIT(ldo2, 725, 1500);
-HARMONY_REGULATOR_INIT(ldo3, 1250, 3300);
-HARMONY_REGULATOR_INIT(ldo4, 1700, 2475);
-HARMONY_REGULATOR_INIT(ldo5, 1250, 3300);
-HARMONY_REGULATOR_INIT(ldo6, 1250, 3300);
-HARMONY_REGULATOR_INIT(ldo7, 1250, 3300);
-HARMONY_REGULATOR_INIT(ldo8, 1250, 3300);
-HARMONY_REGULATOR_INIT(ldo9, 1250, 3300);
+HARMONY_REGULATOR_INIT(sm0,  "vdd_sm0",  "vdd_sys", 725, 1500, 1);
+HARMONY_REGULATOR_INIT(sm1,  "vdd_sm1",  "vdd_sys", 725, 1500, 1);
+HARMONY_REGULATOR_INIT(sm2,  "vdd_sm2",  "vdd_sys", 3000, 4550, 1);
+HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500, 1);
+HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500, 0);
+HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300, 1);
+HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475, 1);
+HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", NULL,      1250, 3300, 1);
+HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300, 0);
+HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300, 0);
+HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300, 0);
+HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300, 1);
 
 #define TPS_REG(_id, _data)                     \
         {                                       \
@@ -110,7 +120,29 @@ static struct i2c_board_info __initdata harmony_regulators[] = {
 
 int __init harmony_regulator_init(void)
 {
-        i2c_register_board_info(3, harmony_regulators, 1);
+        regulator_register_always_on(0, "vdd_sys",
+                NULL, 0, 5000000);
+
+        if (machine_is_harmony()) {
+                i2c_register_board_info(3, harmony_regulators, 1);
+        } else { /* Harmony, booted using device tree */
+                struct device_node *np;
+                struct i2c_adapter *adapter;
+
+                np = of_find_node_by_path("/i2c@7000d000");
+                if (np == NULL) {
+                        pr_err("Could not find device_node for DVC I2C\n");
+                        return -ENODEV;
+                }
+
+                adapter = of_find_i2c_adapter_by_node(np);
+                if (!adapter) {
+                        pr_err("Could not find i2c_adapter for DVC I2C\n");
+                        return -ENODEV;
+                }
+
+                i2c_new_device(adapter, harmony_regulators);
+        }
 
         return 0;
 }
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index bbc1907e98a..4b64af5cab2 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -148,7 +148,6 @@ static struct platform_device *paz00_devices[] __initdata = {
         &debug_uart,
         &tegra_sdhci_device4,
         &tegra_sdhci_device1,
-        &wifi_rfkill_device,
         &leds_gpio,
         &gpio_keys_device,
 };
@@ -201,6 +200,11 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = {
         .is_8bit        = 1,
 };
 
+void __init tegra_paz00_wifikill_init(void)
+{
+        platform_device_register(&wifi_rfkill_device);
+}
+
 static void __init tegra_paz00_init(void)
 {
         tegra_clk_init_from_table(paz00_clk_init_table);
@@ -211,6 +215,7 @@ static void __init tegra_paz00_init(void)
         tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
 
         platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
+        tegra_paz00_wifikill_init();
 
         paz00_i2c_init();
         paz00_usb_init();
diff --git a/arch/arm/mach-tegra/board-seaboard-pinmux.c b/arch/arm/mach-tegra/board-seaboard-pinmux.c
deleted file mode 100644
index 11fc8a568c6..00000000000
--- a/arch/arm/mach-tegra/board-seaboard-pinmux.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright (C) 2010-2012 NVIDIA Corporation
- * Copyright (C) 2011 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-
-#include "board-seaboard.h"
-#include "board-pinmux.h"
-
-static unsigned long seaboard_pincfg_drive_sdio1[] = {
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE, 0),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SCHMITT, 0),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_LOW_POWER_MODE, 3),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH, 31),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH, 31),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING, 3),
-        TEGRA_PINCONF_PACK(TEGRA_PINCONF_PARAM_SLEW_RATE_RISING, 3),
-};
-
-static struct pinctrl_map common_map[] = {
-        TEGRA_MAP_MUXCONF("ata",   "ide",           none, driven),
-        TEGRA_MAP_MUXCONF("atb",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("atc",   "nand",          none, driven),
-        TEGRA_MAP_MUXCONF("atd",   "gmi",           none, driven),
-        TEGRA_MAP_MUXCONF("ate",   "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("cdev1", "plla_out",      none, driven),
-        TEGRA_MAP_MUXCONF("cdev2", "pllp_out4",     none, driven),
-        TEGRA_MAP_MUXCONF("crtp",  "crt",           up,   tristate),
-        TEGRA_MAP_MUXCONF("csus",  "vi_sensor_clk", none, tristate),
-        TEGRA_MAP_MUXCONF("dap1",  "dap1",          none, driven),
-        TEGRA_MAP_MUXCONF("dap2",  "dap2",          none, driven),
-        TEGRA_MAP_MUXCONF("dap3",  "dap3",          none, tristate),
-        TEGRA_MAP_MUXCONF("dap4",  "dap4",          none, driven),
-        TEGRA_MAP_MUXCONF("dta",   "vi",            down, driven),
-        TEGRA_MAP_MUXCONF("dtb",   "vi",            down, driven),
-        TEGRA_MAP_MUXCONF("dtc",   "vi",            down, driven),
-        TEGRA_MAP_MUXCONF("dtd",   "vi",            down, driven),
-        TEGRA_MAP_MUXCONF("dte",   "vi",            down, tristate),
-        TEGRA_MAP_MUXCONF("dtf",   "i2c3",          none, driven),
-        TEGRA_MAP_MUXCONF("gma",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gmb",   "gmi",           up,   tristate),
-        TEGRA_MAP_MUXCONF("gmc",   "uartd",         none, driven),
-        TEGRA_MAP_MUXCONF("gme",   "sdio4",         none, driven),
-        TEGRA_MAP_MUXCONF("gpu",   "pwm",           none, driven),
-        TEGRA_MAP_MUXCONF("gpu7",  "rtck",          none, driven),
-        TEGRA_MAP_MUXCONF("gpv",   "pcie",          none, tristate),
-        TEGRA_MAP_MUXCONF("hdint", "hdmi",          na,   tristate),
-        TEGRA_MAP_MUXCONF("i2cp",  "i2cp",          none, driven),
-        TEGRA_MAP_MUXCONF("irrx",  "uartb",         none, driven),
-        TEGRA_MAP_MUXCONF("irtx",  "uartb",         none, driven),
-        TEGRA_MAP_MUXCONF("kbca",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcb",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcc",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcd",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbce",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("kbcf",  "kbc",           up,   driven),
-        TEGRA_MAP_MUXCONF("lcsn",  "rsvd4",         na,   tristate),
-        TEGRA_MAP_MUXCONF("ld0",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld1",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld10",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld11",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld12",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld13",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld14",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld15",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld16",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld17",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld2",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld3",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld4",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld5",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld6",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld7",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld8",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ld9",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("ldc",   "rsvd4",         na,   tristate),
-        TEGRA_MAP_MUXCONF("ldi",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhp2",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lhs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lm0",   "rsvd4",         na,   driven),
-        TEGRA_MAP_MUXCONF("lm1",   "crt",           na,   tristate),
-        TEGRA_MAP_MUXCONF("lpp",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lpw1",  "rsvd4",         na,   tristate),
-        TEGRA_MAP_MUXCONF("lsc0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsdi",  "rsvd4",         na,   tristate),
-        TEGRA_MAP_MUXCONF("lspi",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvp0",  "rsvd4",         na,   tristate),
-        TEGRA_MAP_MUXCONF("lvp1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lvs",   "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("owc",   "rsvd2",         none, tristate),
-        TEGRA_MAP_MUXCONF("pmc",   "pwr_on",        na,   driven),
-        TEGRA_MAP_MUXCONF("pta",   "hdmi",          none, driven),
-        TEGRA_MAP_MUXCONF("rm",    "i2c1",          none, driven),
-        TEGRA_MAP_MUXCONF("sdb",   "sdio3",         na,   driven),
-        TEGRA_MAP_MUXCONF("sdc",   "sdio3",         none, driven),
-        TEGRA_MAP_MUXCONF("sdd",   "sdio3",         none, driven),
-        TEGRA_MAP_MUXCONF("sdio1", "sdio1",         up,   driven),
-        TEGRA_MAP_MUXCONF("slxa",  "pcie",          up,   tristate),
-        TEGRA_MAP_MUXCONF("slxd",  "spdif",         none, driven),
-        TEGRA_MAP_MUXCONF("slxk",  "pcie",          none, driven),
-        TEGRA_MAP_MUXCONF("spdi",  "rsvd2",         none, driven),
-        TEGRA_MAP_MUXCONF("spdo",  "rsvd2",         none, driven),
-        TEGRA_MAP_MUXCONF("spib",  "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("spid",  "spi1",          none, tristate),
-        TEGRA_MAP_MUXCONF("spie",  "spi1",          none, tristate),
-        TEGRA_MAP_MUXCONF("spif",  "spi1",          down, tristate),
-        TEGRA_MAP_MUXCONF("spih",  "spi2_alt",      up,   tristate),
-        TEGRA_MAP_MUXCONF("uaa",   "ulpi",          up,   driven),
-        TEGRA_MAP_MUXCONF("uab",   "ulpi",          up,   driven),
-        TEGRA_MAP_MUXCONF("uac",   "rsvd2",         none, driven),
-        TEGRA_MAP_MUXCONF("uad",   "irda",          none, driven),
-        TEGRA_MAP_MUXCONF("uca",   "uartc",         none, driven),
-        TEGRA_MAP_MUXCONF("ucb",   "uartc",         none, driven),
-        TEGRA_MAP_MUXCONF("uda",   "ulpi",          none, driven),
-        TEGRA_MAP_CONF("ck32",    none, na),
-        TEGRA_MAP_CONF("ddrc",    none, na),
-        TEGRA_MAP_CONF("pmca",    none, na),
-        TEGRA_MAP_CONF("pmcb",    none, na),
-        TEGRA_MAP_CONF("pmcc",    none, na),
-        TEGRA_MAP_CONF("pmcd",    none, na),
-        TEGRA_MAP_CONF("pmce",    none, na),
-        TEGRA_MAP_CONF("xm2c",    none, na),
-        TEGRA_MAP_CONF("xm2d",    none, na),
-        TEGRA_MAP_CONF("ls",      up,   na),
-        TEGRA_MAP_CONF("lc",      up,   na),
-        TEGRA_MAP_CONF("ld17_0",  down, na),
-        TEGRA_MAP_CONF("ld19_18", down, na),
-        TEGRA_MAP_CONF("ld21_20", down, na),
-        TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct pinctrl_map seaboard_map[] = {
-        TEGRA_MAP_MUXCONF("ddc",   "rsvd2",         none, tristate),
-        TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, driven),
-        TEGRA_MAP_MUXCONF("lpw0",  "hdmi",          na,   driven),
-        TEGRA_MAP_MUXCONF("lpw2",  "hdmi",          na,   driven),
-        TEGRA_MAP_MUXCONF("lsc1",  "hdmi",          na,   tristate),
-        TEGRA_MAP_MUXCONF("lsck",  "hdmi",          na,   tristate),
-        TEGRA_MAP_MUXCONF("lsda",  "hdmi",          na,   tristate),
-        TEGRA_MAP_MUXCONF("slxc",  "spdif",         none, tristate),
-        TEGRA_MAP_MUXCONF("spia",  "gmi",           up,   tristate),
-        TEGRA_MAP_MUXCONF("spic",  "gmi",           up,   driven),
-        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      up,   tristate),
-        PIN_MAP_CONFIGS_GROUP_HOG_DEFAULT(PINMUX_DEV, "drive_sdio1", seaboard_pincfg_drive_sdio1),
-};
-
-static struct pinctrl_map ventana_map[] = {
-        TEGRA_MAP_MUXCONF("ddc",   "rsvd2",         none, driven),
-        TEGRA_MAP_MUXCONF("gmd",   "sflash",        none, tristate),
-        TEGRA_MAP_MUXCONF("lpw0",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lpw2",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsc1",  "displaya",      na,   driven),
-        TEGRA_MAP_MUXCONF("lsck",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("lsda",  "displaya",      na,   tristate),
-        TEGRA_MAP_MUXCONF("slxc",  "sdio3",         none, driven),
-        TEGRA_MAP_MUXCONF("spia",  "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("spic",  "gmi",           none, tristate),
-        TEGRA_MAP_MUXCONF("spig",  "spi2_alt",      none, tristate),
-};
-
-static struct tegra_board_pinmux_conf common_conf = {
-        .maps = common_map,
-        .map_count = ARRAY_SIZE(common_map),
-};
-
-static struct tegra_board_pinmux_conf seaboard_conf = {
-        .maps = seaboard_map,
-        .map_count = ARRAY_SIZE(seaboard_map),
-};
-
-static struct tegra_board_pinmux_conf ventana_conf = {
-        .maps = ventana_map,
-        .map_count = ARRAY_SIZE(ventana_map),
-};
-
-void seaboard_pinmux_init(void)
-{
-        tegra_board_pinmux_init(&common_conf, &seaboard_conf);
-}
-
-void ventana_pinmux_init(void)
-{
-        tegra_board_pinmux_init(&common_conf, &ventana_conf);
-}
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
deleted file mode 100644
index 71e9f3fc7fb..00000000000
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (c) 2010, 2011 NVIDIA Corporation.
- * Copyright (C) 2010, 2011 Google, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/i2c.h>
-#include <linux/delay.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/platform_data/tegra_usb.h>
-
-#include <sound/wm8903.h>
-
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
-#include <mach/tegra_wm8903_pdata.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/hardware/gic.h>
-
-#include "board.h"
-#include "board-seaboard.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
-        {
-                /* Memory and IRQ filled in before registration */
-                .flags          = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
-                .type           = PORT_TEGRA,
-                .handle_break   = tegra_serial_handle_break,
-                .iotype         = UPIO_MEM,
-                .regshift       = 2,
-                .uartclk        = 216000000,
-        }, {
-                .flags          = 0,
-        }
-};
-
-static struct platform_device debug_uart = {
-        .name = "serial8250",
-        .id = PLAT8250_DEV_PLATFORM,
-        .dev = {
-                .platform_data = debug_uart_platform_data,
-        },
-};
-
-static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = {
-        /* name         parent          rate            enabled */
-        { "uartb",      "pll_p",        216000000,      true},
-        { "uartd",      "pll_p",        216000000,      true},
-        { "pll_a",      "pll_p_out1",   56448000,       true },
-        { "pll_a_out0", "pll_a",        11289600,       true },
-        { "cdev1",      NULL,           0,              true },
-        { "i2s1",       "pll_a_out0",   11289600,       false},
-        { "usbd",       "clk_m",        12000000,       true},
-        { "usb3",       "clk_m",        12000000,       true},
-        { NULL,         NULL,           0,              0},
-};
-
-static struct gpio_keys_button seaboard_gpio_keys_buttons[] = {
-        {
-                .code           = SW_LID,
-                .gpio           = TEGRA_GPIO_LIDSWITCH,
-                .active_low     = 0,
-                .desc           = "Lid",
-                .type           = EV_SW,
-                .wakeup         = 1,
-                .debounce_interval = 1,
-        },
-        {
-                .code           = KEY_POWER,
-                .gpio           = TEGRA_GPIO_POWERKEY,
-                .active_low     = 1,
-                .desc           = "Power",
-                .type           = EV_KEY,
-                .wakeup         = 1,
-        },
-};
-
-static struct gpio_keys_platform_data seaboard_gpio_keys = {
-        .buttons        = seaboard_gpio_keys_buttons,
-        .nbuttons       = ARRAY_SIZE(seaboard_gpio_keys_buttons),
-};
-
-static struct platform_device seaboard_gpio_keys_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &seaboard_gpio_keys,
-        }
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
-        .cd_gpio        = -1,
-        .wp_gpio        = -1,
-        .power_gpio     = -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata3 = {
-        .cd_gpio        = TEGRA_GPIO_SD2_CD,
-        .wp_gpio        = TEGRA_GPIO_SD2_WP,
-        .power_gpio     = TEGRA_GPIO_SD2_POWER,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
-        .cd_gpio        = -1,
-        .wp_gpio        = -1,
-        .power_gpio     = -1,
-        .is_8bit        = 1,
-};
-
-static struct tegra_wm8903_platform_data seaboard_audio_pdata = {
-        .gpio_spkr_en           = TEGRA_GPIO_SPKR_EN,
-        .gpio_hp_det            = TEGRA_GPIO_HP_DET,
-        .gpio_hp_mute           = -1,
-        .gpio_int_mic_en        = -1,
-        .gpio_ext_mic_en        = -1,
-};
-
-static struct platform_device seaboard_audio_device = {
-        .name   = "tegra-snd-wm8903",
-        .id     = 0,
-        .dev    = {
-                .platform_data  = &seaboard_audio_pdata,
-        },
-};
-
-static struct platform_device *seaboard_devices[] __initdata = {
-        &debug_uart,
-        &tegra_pmu_device,
-        &tegra_sdhci_device4,
-        &tegra_sdhci_device3,
-        &tegra_sdhci_device1,
-        &seaboard_gpio_keys_device,
-        &tegra_i2s_device1,
-        &tegra_das_device,
-        &seaboard_audio_device,
-};
-
-static struct i2c_board_info __initdata isl29018_device = {
-        I2C_BOARD_INFO("isl29018", 0x44),
-};
-
-static struct i2c_board_info __initdata adt7461_device = {
-        I2C_BOARD_INFO("adt7461", 0x4c),
-};
-
-static struct wm8903_platform_data wm8903_pdata = {
-        .irq_active_low = 0,
-        .micdet_cfg = 0,
-        .micdet_delay = 100,
-        .gpio_base = SEABOARD_GPIO_WM8903(0),
-        .gpio_cfg = {
-                0,
-                0,
-                WM8903_GPIO_CONFIG_ZERO,
-                0,
-                0,
-        },
-};
-
-static struct i2c_board_info __initdata wm8903_device = {
-        I2C_BOARD_INFO("wm8903", 0x1a),
-        .platform_data = &wm8903_pdata,
-};
-
-static int seaboard_ehci_init(void)
-{
-        struct tegra_ehci_platform_data *pdata;
-
-        pdata = tegra_ehci1_device.dev.platform_data;
-        pdata->vbus_gpio = TEGRA_GPIO_USB1;
-
-        platform_device_register(&tegra_ehci1_device);
-        platform_device_register(&tegra_ehci3_device);
-
-        return 0;
-}
-
-static void __init seaboard_i2c_init(void)
-{
-        isl29018_device.irq = gpio_to_irq(TEGRA_GPIO_ISL29018_IRQ);
-        i2c_register_board_info(0, &isl29018_device, 1);
-
-        wm8903_device.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
-        i2c_register_board_info(0, &wm8903_device, 1);
-
-        i2c_register_board_info(3, &adt7461_device, 1);
-
-        platform_device_register(&tegra_i2c_device1);
-        platform_device_register(&tegra_i2c_device2);
-        platform_device_register(&tegra_i2c_device3);
-        platform_device_register(&tegra_i2c_device4);
-}
-
-static void __init seaboard_common_init(void)
-{
-        seaboard_pinmux_init();
-
-        tegra_clk_init_from_table(seaboard_clk_init_table);
-
-        tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
-        tegra_sdhci_device3.dev.platform_data = &sdhci_pdata3;
-        tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
-        platform_add_devices(seaboard_devices, ARRAY_SIZE(seaboard_devices));
-
-        seaboard_ehci_init();
-}
-
-static void __init tegra_seaboard_init(void)
-{
-        /* Seaboard uses UARTD for the debug port. */
-        debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTD_BASE);
-        debug_uart_platform_data[0].mapbase = TEGRA_UARTD_BASE;
-        debug_uart_platform_data[0].irq = INT_UARTD;
-
-        seaboard_common_init();
-
-        seaboard_i2c_init();
-}
-
-static void __init tegra_kaen_init(void)
-{
-        /* Kaen uses UARTB for the debug port. */
-        debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTB_BASE);
-        debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE;
-        debug_uart_platform_data[0].irq = INT_UARTB;
-
-        seaboard_audio_pdata.gpio_hp_mute = TEGRA_GPIO_KAEN_HP_MUTE;
-
-        seaboard_common_init();
-
-        seaboard_i2c_init();
-}
-
-static void __init tegra_wario_init(void)
-{
-        /* Wario uses UARTB for the debug port. */
-        debug_uart_platform_data[0].membase = IO_ADDRESS(TEGRA_UARTB_BASE);
-        debug_uart_platform_data[0].mapbase = TEGRA_UARTB_BASE;
-        debug_uart_platform_data[0].irq = INT_UARTB;
-
-        seaboard_common_init();
-
-        seaboard_i2c_init();
-}
-
-
-MACHINE_START(SEABOARD, "seaboard")
-        .atag_offset    = 0x100,
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra20_init_early,
-        .init_irq       = tegra_init_irq,
-        .handle_irq     = gic_handle_irq,
-        .timer          = &tegra_timer,
-        .init_machine   = tegra_seaboard_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-MACHINE_END
-
-MACHINE_START(KAEN, "kaen")
-        .atag_offset    = 0x100,
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra20_init_early,
-        .init_irq       = tegra_init_irq,
-        .handle_irq     = gic_handle_irq,
-        .timer          = &tegra_timer,
-        .init_machine   = tegra_kaen_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-MACHINE_END
-
-MACHINE_START(WARIO, "wario")
-        .atag_offset    = 0x100,
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra20_init_early,
-        .init_irq       = tegra_init_irq,
-        .handle_irq     = gic_handle_irq,
-        .timer          = &tegra_timer,
-        .init_machine   = tegra_wario_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-seaboard.h b/arch/arm/mach-tegra/board-seaboard.h
deleted file mode 100644
index 4c45d4ca3c4..00000000000
--- a/arch/arm/mach-tegra/board-seaboard.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-seaboard.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_BOARD_SEABOARD_H
-#define _MACH_TEGRA_BOARD_SEABOARD_H
-
-#include <mach/gpio-tegra.h>
-
-#define SEABOARD_GPIO_TPS6586X(_x_)     (TEGRA_NR_GPIOS + (_x_))
-#define SEABOARD_GPIO_WM8903(_x_)       (SEABOARD_GPIO_TPS6586X(4) + (_x_))
-
-#define TEGRA_GPIO_SD2_CD               TEGRA_GPIO_PI5
-#define TEGRA_GPIO_SD2_WP               TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD2_POWER            TEGRA_GPIO_PI6
-#define TEGRA_GPIO_LIDSWITCH            TEGRA_GPIO_PC7
-#define TEGRA_GPIO_USB1                 TEGRA_GPIO_PD0
-#define TEGRA_GPIO_POWERKEY             TEGRA_GPIO_PV2
-#define TEGRA_GPIO_BACKLIGHT            TEGRA_GPIO_PD4
-#define TEGRA_GPIO_LVDS_SHUTDOWN        TEGRA_GPIO_PB2
-#define TEGRA_GPIO_BACKLIGHT_PWM        TEGRA_GPIO_PU5
-#define TEGRA_GPIO_BACKLIGHT_VDD        TEGRA_GPIO_PW0
-#define TEGRA_GPIO_EN_VDD_PNL           TEGRA_GPIO_PC6
-#define TEGRA_GPIO_MAGNETOMETER         TEGRA_GPIO_PN5
-#define TEGRA_GPIO_ISL29018_IRQ         TEGRA_GPIO_PZ2
-#define TEGRA_GPIO_AC_ONLINE            TEGRA_GPIO_PV3
-#define TEGRA_GPIO_WWAN_PWR             SEABOARD_GPIO_TPS6586X(2)
-#define TEGRA_GPIO_CDC_IRQ              TEGRA_GPIO_PX3
-#define TEGRA_GPIO_SPKR_EN              SEABOARD_GPIO_WM8903(2)
-#define TEGRA_GPIO_HP_DET               TEGRA_GPIO_PX1
-#define TEGRA_GPIO_KAEN_HP_MUTE         TEGRA_GPIO_PA5
-
-void seaboard_pinmux_init(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 65014968fc6..f88e5143c76 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -46,5 +46,14 @@ int __init tegra_powergate_debugfs_init(void);
 static inline int tegra_powergate_debugfs_init(void) { return 0; }
 #endif
 
+int __init harmony_regulator_init(void);
+#ifdef CONFIG_TEGRA_PCI
+int __init harmony_pcie_init(void);
+#else
+static inline int harmony_pcie_init(void) { return 0; }
+#endif
+
+void __init tegra_paz00_wifikill_init(void);
+
 extern struct sys_timer tegra_timer;
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 204a5c8b0b5..96fef6bcc65 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -33,6 +33,7 @@
 #include "clock.h"
 #include "fuse.h"
 #include "pmc.h"
+#include "apbio.h"
 
 /*
  * Storage for debug-macro.S's state.
@@ -127,6 +128,7 @@ static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 void __init tegra20_init_early(void)
 {
+        tegra_apb_io_init();
         tegra_init_fuse();
         tegra2_init_clocks();
         tegra_clk_init_from_table(tegra20_clk_init_table);
@@ -138,6 +140,7 @@ void __init tegra20_init_early(void)
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 void __init tegra30_init_early(void)
 {
+        tegra_apb_io_init();
         tegra_init_fuse();
         tegra30_init_clocks();
         tegra_clk_init_from_table(tegra30_clk_init_table);
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 7a065f0cf63..ceb52db1e2f 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -189,8 +189,8 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
                 return PTR_ERR(emc_clk);
         }
 
-        clk_enable(emc_clk);
-        clk_enable(cpu_clk);
+        clk_prepare_enable(emc_clk);
+        clk_prepare_enable(cpu_clk);
 
         cpufreq_frequency_table_cpuinfo(policy, freq_table);
         cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
@@ -212,7 +212,7 @@ static int tegra_cpu_init(struct cpufreq_policy *policy)
 static int tegra_cpu_exit(struct cpufreq_policy *policy)
 {
         cpufreq_frequency_table_cpuinfo(policy, freq_table);
-        clk_disable(emc_clk);
+        clk_disable_unprepare(emc_clk);
         clk_put(emc_clk);
         clk_put(cpu_clk);
         return 0;
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index d83a8c0296f..566e2f88899 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -27,9 +27,9 @@
 #include <linux/cpuidle.h>
 #include <linux/hrtimer.h>
 
-#include <mach/iomap.h>
+#include <asm/proc-fns.h>
 
-extern void tegra_cpu_wfi(void);
+#include <mach/iomap.h>
 
 static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv, int index);
@@ -64,7 +64,7 @@ static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
 
         enter = ktime_get();
 
-        tegra_cpu_wfi();
+        cpu_do_idle();
 
         exit = ktime_sub(ktime_get(), enter);
         us = ktime_to_us(exit);
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index abea4f6e2dd..29c5114d607 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -714,13 +714,13 @@ int __init tegra_dma_init(void)
 
         bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS);
 
-        c = clk_get_sys("tegra-dma", NULL);
+        c = clk_get_sys("tegra-apbdma", NULL);
         if (IS_ERR(c)) {
                 pr_err("Unable to get clock for APB DMA\n");
                 ret = PTR_ERR(c);
                 goto fail;
         }
-        ret = clk_enable(c);
+        ret = clk_prepare_enable(c);
         if (ret != 0) {
                 pr_err("Unable to enable clock for APB DMA\n");
                 goto fail;
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 0e09137506e..d3ad5150d66 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -723,9 +723,9 @@ static int tegra_pcie_power_regate(void)
 
         tegra_pcie_xclk_clamp(false);
 
-        clk_enable(tegra_pcie.afi_clk);
-        clk_enable(tegra_pcie.pex_clk);
-        return clk_enable(tegra_pcie.pll_e);
+        clk_prepare_enable(tegra_pcie.afi_clk);
+        clk_prepare_enable(tegra_pcie.pex_clk);
+        return clk_prepare_enable(tegra_pcie.pll_e);
 }
 
 static int tegra_pcie_clocks_get(void)
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c
index f5b12fb4ff1..15d506501cc 100644
--- a/arch/arm/mach-tegra/powergate.c
+++ b/arch/arm/mach-tegra/powergate.c
@@ -146,7 +146,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
         if (ret)
                 goto err_power;
 
-        ret = clk_enable(clk);
+        ret = clk_prepare_enable(clk);
         if (ret)
                 goto err_clk;
 
@@ -162,7 +162,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
         return 0;
 
 err_clamp:
-        clk_disable(clk);
+        clk_disable_unprepare(clk);
 err_clk:
         tegra_powergate_power_off(id);
 err_power:
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 5b20197bae7..d29b156a801 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -62,32 +62,3 @@
         movw    \reg, #:lower16:\val
         movt    \reg, #:upper16:\val
 .endm
-
-/*
- * tegra_cpu_wfi
- *
- * puts current CPU in clock-gated wfi using the flow controller
- *
- * corrupts r0-r3
- * must be called with MMU on
- */
-
-ENTRY(tegra_cpu_wfi)
-        cpu_id  r0
-        cpu_to_halt_reg r1, r0
-        cpu_to_csr_reg r2, r0
-        mov32   r0, TEGRA_FLOW_CTRL_VIRT
-        mov     r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-        str     r3, [r0, r2]    @ clear event & interrupt status
-        mov     r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT | FLOW_CTRL_JTAG_RESUME
-        str     r3, [r0, r1]    @ put flow controller in wait irq mode
-        dsb
-        wfi
-        mov     r3, #0
-        str     r3, [r0, r1]    @ clear flow controller halt status
-        mov     r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-        str     r3, [r0, r2]    @ clear event & interrupt status
-        dsb
-        mov     pc, lr
-ENDPROC(tegra_cpu_wfi)
-
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index b59315ce369..a703844b206 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -69,6 +69,8 @@
 
 #define PERIPH_CLK_SOURCE_MASK          (3<<30)
 #define PERIPH_CLK_SOURCE_SHIFT         30
+#define PERIPH_CLK_SOURCE_PWM_MASK      (7<<28)
+#define PERIPH_CLK_SOURCE_PWM_SHIFT     28
 #define PERIPH_CLK_SOURCE_ENABLE        (1<<28)
 #define PERIPH_CLK_SOURCE_DIVU71_MASK   0xFF
 #define PERIPH_CLK_SOURCE_DIVU16_MASK   0xFFFF
@@ -908,9 +910,20 @@ static void tegra2_periph_clk_init(struct clk *c)
         u32 val = clk_readl(c->reg);
         const struct clk_mux_sel *mux = NULL;
         const struct clk_mux_sel *sel;
+        u32 shift;
+        u32 mask;
+
+        if (c->flags & MUX_PWM) {
+                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+                mask = PERIPH_CLK_SOURCE_PWM_MASK;
+        } else {
+                shift = PERIPH_CLK_SOURCE_SHIFT;
+                mask = PERIPH_CLK_SOURCE_MASK;
+        }
+
         if (c->flags & MUX) {
                 for (sel = c->inputs; sel->input != NULL; sel++) {
-                        if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
+                        if ((val & mask) >> shift == sel->value)
                                 mux = sel;
                 }
                 BUG_ON(!mux);
@@ -1023,12 +1036,23 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
 {
         u32 val;
         const struct clk_mux_sel *sel;
+        u32 mask, shift;
+
         pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+
+        if (c->flags & MUX_PWM) {
+                shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+                mask = PERIPH_CLK_SOURCE_PWM_MASK;
+        } else {
+                shift = PERIPH_CLK_SOURCE_SHIFT;
+                mask = PERIPH_CLK_SOURCE_MASK;
+        }
+
         for (sel = c->inputs; sel->input != NULL; sel++) {
                 if (sel->input == p) {
                         val = clk_readl(c->reg);
-                        val &= ~PERIPH_CLK_SOURCE_MASK;
-                        val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
+                        val &= ~mask;
+                        val |= (sel->value) << shift;
 
                         if (c->refcnt)
                                 clk_enable(p);
@@ -2149,14 +2173,14 @@ static struct clk tegra_clk_emc = {
         }
 
 static struct clk tegra_list_clks[] = {
-        PERIPH_CLK("apbdma",    "tegra-dma",            NULL,   34,     0,      108000000, mux_pclk,                    0),
+        PERIPH_CLK("apbdma",    "tegra-apbdma",         NULL,   34,     0,      108000000, mux_pclk,                    0),
         PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET),
         PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
         PERIPH_CLK("i2s1",      "tegra20-i2s.0",        NULL,   11,     0x100,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
         PERIPH_CLK("i2s2",      "tegra20-i2s.1",        NULL,   18,     0x104,  26000000,  mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
         PERIPH_CLK("spdif_out", "spdif_out",            NULL,   10,     0x108,  100000000, mux_pllaout0_audio2x_pllp_clkm,      MUX | DIV_U71),
         PERIPH_CLK("spdif_in",  "spdif_in",             NULL,   10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71),
-        PERIPH_CLK("pwm",       "pwm",                  NULL,   17,     0x110,  432000000, mux_pllp_pllc_audio_clkm_clk32,      MUX | DIV_U71),
+        PERIPH_CLK("pwm",       "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_audio_clkm_clk32,      MUX | DIV_U71 | MUX_PWM),
         PERIPH_CLK("spi",       "spi",                  NULL,   43,     0x114,  40000000,  mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
         PERIPH_CLK("xio",       "xio",                  NULL,   45,     0x120,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
         PERIPH_CLK("twc",       "twc",                  NULL,   16,     0x12c,  150000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71),
@@ -2189,11 +2213,11 @@ static struct clk tegra_list_clks[] = {
         PERIPH_CLK("i2c2_i2c",  "tegra-i2c.1",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
         PERIPH_CLK("i2c3_i2c",  "tegra-i2c.2",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
         PERIPH_CLK("dvc_i2c",   "tegra-i2c.3",          "i2c",  0,      0,      72000000,  mux_pllp_out3,                       0),
-        PERIPH_CLK("uarta",     "uart.0",               NULL,   6,      0x178,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartb",     "uart.1",               NULL,   7,      0x17c,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartc",     "uart.2",               NULL,   55,     0x1a0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uartd",     "uart.3",               NULL,   65,     0x1c0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
-        PERIPH_CLK("uarte",     "uart.4",               NULL,   66,     0x1c4,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
+        PERIPH_CLK("uarta",     "tegra-uart.0",         NULL,   6,      0x178,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
+        PERIPH_CLK("uartb",     "tegra-uart.1",         NULL,   7,      0x17c,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
+        PERIPH_CLK("uartc",     "tegra-uart.2",         NULL,   55,     0x1a0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
+        PERIPH_CLK("uartd",     "tegra-uart.3",         NULL,   65,     0x1c0,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
+        PERIPH_CLK("uarte",     "tegra-uart.4",         NULL,   66,     0x1c4,  600000000, mux_pllp_pllc_pllm_clkm,     MUX),
         PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
         PERIPH_CLK("2d",        "2d",                   NULL,   21,     0x15c,  300000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
         PERIPH_CLK("vi",        "tegra_camera",         "vi",   20,     0x148,  150000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71), /* scales with voltage and process_id */
@@ -2245,20 +2269,16 @@ static struct clk tegra_list_clks[] = {
  * table under two names.
  */
 static struct clk_duplicate tegra_clk_duplicates[] = {
-        CLK_DUPLICATE("uarta",  "tegra_uart.0", NULL),
-        CLK_DUPLICATE("uartb",  "tegra_uart.1", NULL),
-        CLK_DUPLICATE("uartc",  "tegra_uart.2", NULL),
-        CLK_DUPLICATE("uartd",  "tegra_uart.3", NULL),
-        CLK_DUPLICATE("uarte",  "tegra_uart.4", NULL),
+        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
+        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
+        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
+        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
+        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
         CLK_DUPLICATE("usbd", "utmip-pad", NULL),
         CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
         CLK_DUPLICATE("usbd", "tegra-otg", NULL),
         CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
         CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
-        CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
-        CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
-        CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
-        CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
         CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
         CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
         CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index e33fe4b14a2..6674f100e16 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -2871,7 +2871,7 @@ static struct clk tegra30_clk_twd = {
                 },                                      \
         }
 struct clk tegra_list_clks[] = {
-        PERIPH_CLK("apbdma",    "tegra-dma",            NULL,   34,     0,      26000000,  mux_clk_m,                   0),
+        PERIPH_CLK("apbdma",    "tegra-apbdma",         NULL,   34,     0,      26000000,  mux_clk_m,                   0),
         PERIPH_CLK("rtc",       "rtc-tegra",            NULL,   4,      0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
         PERIPH_CLK("kbc",       "tegra-kbc",            NULL,   36,     0,      32768,     mux_clk_32k,                 PERIPH_NO_RESET | PERIPH_ON_APB),
         PERIPH_CLK("timer",     "timer",                NULL,   5,      0,      26000000,  mux_clk_m,                   0),
@@ -2886,7 +2886,7 @@ struct clk tegra_list_clks[] = {
         PERIPH_CLK("i2s4",      "tegra30-i2s.4",        NULL,   102,    0x3c0,  26000000,  mux_pllaout0_audio4_2x_pllp_clkm,    MUX | DIV_U71 | PERIPH_ON_APB),
         PERIPH_CLK("spdif_out", "tegra30-spdif",        "spdif_out",    10,     0x108,  100000000, mux_pllaout0_audio_2x_pllp_clkm,     MUX | DIV_U71 | PERIPH_ON_APB),
         PERIPH_CLK("spdif_in",  "tegra30-spdif",        "spdif_in",     10,     0x10c,  100000000, mux_pllp_pllc_pllm,          MUX | DIV_U71 | PERIPH_ON_APB),
-        PERIPH_CLK("pwm",       "pwm",                  NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
+        PERIPH_CLK("pwm",       "tegra-pwm",            NULL,   17,     0x110,  432000000, mux_pllp_pllc_clk32_clkm,    MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
         PERIPH_CLK("d_audio",   "tegra30-ahub",         "d_audio", 106, 0x3d0,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
         PERIPH_CLK("dam0",      "tegra30-dam.0",        NULL,   108,    0x3d8,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
         PERIPH_CLK("dam1",      "tegra30-dam.1",        NULL,   109,    0x3dc,  48000000,  mux_plla_pllc_pllp_clkm,     MUX | DIV_U71),
@@ -2924,16 +2924,11 @@ struct clk tegra_list_clks[] = {
         PERIPH_CLK("i2c3",      "tegra-i2c.2",          NULL,   67,     0x1b8,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
         PERIPH_CLK("i2c4",      "tegra-i2c.3",          NULL,   103,    0x3c4,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
         PERIPH_CLK("i2c5",      "tegra-i2c.4",          NULL,   47,     0x128,  26000000,  mux_pllp_clkm,               MUX | DIV_U16 | PERIPH_ON_APB),
-        PERIPH_CLK("uarta",     "tegra_uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartb",     "tegra_uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartc",     "tegra_uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartd",     "tegra_uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uarte",     "tegra_uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uarta_dbg", "serial8250.0",         "uarta", 6,     0x178,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartb_dbg", "serial8250.0",         "uartb", 7,     0x17c,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartc_dbg", "serial8250.0",         "uartc", 55,    0x1a0,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uartd_dbg", "serial8250.0",         "uartd", 65,    0x1c0,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
-        PERIPH_CLK("uarte_dbg", "serial8250.0",         "uarte", 66,    0x1c4,  800000000, mux_pllp_clkm,               MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uarta",     "tegra-uart.0",         NULL,   6,      0x178,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartb",     "tegra-uart.1",         NULL,   7,      0x17c,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartc",     "tegra-uart.2",         NULL,   55,     0x1a0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uartd",     "tegra-uart.3",         NULL,   65,     0x1c0,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
+        PERIPH_CLK("uarte",     "tegra-uart.4",         NULL,   66,     0x1c4,  800000000, mux_pllp_pllc_pllm_clkm,     MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
         PERIPH_CLK_EX("vi",     "tegra_camera",         "vi",   20,     0x148,  425000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT,    &tegra_vi_clk_ops),
         PERIPH_CLK("3d",        "3d",                   NULL,   24,     0x158,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
         PERIPH_CLK("3d2",       "3d2",                  NULL,   98,     0x3b0,  520000000, mux_pllm_pllc_pllp_plla,     MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
@@ -2983,6 +2978,11 @@ struct clk tegra_list_clks[] = {
  * table under two names.
  */
 struct clk_duplicate tegra_clk_duplicates[] = {
+        CLK_DUPLICATE("uarta",  "serial8250.0", NULL),
+        CLK_DUPLICATE("uartb",  "serial8250.1", NULL),
+        CLK_DUPLICATE("uartc",  "serial8250.2", NULL),
+        CLK_DUPLICATE("uartd",  "serial8250.3", NULL),
+        CLK_DUPLICATE("uarte",  "serial8250.4", NULL),
         CLK_DUPLICATE("usbd", "utmip-pad", NULL),
         CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
         CLK_DUPLICATE("usbd", "tegra-otg", NULL),
@@ -2990,10 +2990,6 @@ struct clk_duplicate tegra_clk_duplicates[] = {
         CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
         CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
         CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
-        CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
-        CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
-        CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
-        CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
         CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
         CLK_DUPLICATE("bsev", "nvavp", "bsev"),
         CLK_DUPLICATE("vde", "tegra-aes", "vde"),
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 315672c7bd4..57b5bdc13b9 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -189,7 +189,7 @@ static void __init tegra_init_timer(void)
                         " Assuming 12Mhz input clock.\n");
                 rate = 12000000;
         } else {
-                clk_enable(clk);
+                clk_prepare_enable(clk);
                 rate = clk_get_rate(clk);
         }
 
@@ -201,7 +201,7 @@ static void __init tegra_init_timer(void)
         if (IS_ERR(clk))
                 pr_warn("Unable to get rtc-tegra clock\n");
         else
-                clk_enable(clk);
+                clk_prepare_enable(clk);
 
         switch (rate) {
         case 12000000:
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index 54e353c8e30..022b33a05c3 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -247,7 +247,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
         unsigned long val, flags;
         void __iomem *base = phy->pad_regs;
 
-        clk_enable(phy->pad_clk);
+        clk_prepare_enable(phy->pad_clk);
 
         spin_lock_irqsave(&utmip_pad_lock, flags);
 
@@ -259,7 +259,7 @@ static void utmip_pad_power_on(struct tegra_usb_phy *phy)
 
         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 
-        clk_disable(phy->pad_clk);
+        clk_disable_unprepare(phy->pad_clk);
 }
 
 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
@@ -272,7 +272,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
                 return -EINVAL;
         }
 
-        clk_enable(phy->pad_clk);
+        clk_prepare_enable(phy->pad_clk);
 
         spin_lock_irqsave(&utmip_pad_lock, flags);
 
@@ -284,7 +284,7 @@ static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 
         spin_unlock_irqrestore(&utmip_pad_lock, flags);
 
-        clk_disable(phy->pad_clk);
+        clk_disable_unprepare(phy->pad_clk);
 
         return 0;
 }
@@ -580,7 +580,7 @@ static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
         msleep(5);
         gpio_direction_output(config->reset_gpio, 1);
 
-        clk_enable(phy->clk);
+        clk_prepare_enable(phy->clk);
         msleep(1);
 
         val = readl(base + USB_SUSP_CTRL);
@@ -689,7 +689,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
                 err = PTR_ERR(phy->pll_u);
                 goto err0;
         }
-        clk_enable(phy->pll_u);
+        clk_prepare_enable(phy->pll_u);
 
         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
@@ -735,7 +735,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct device *dev, int instance,
         return phy;
 
 err1:
-        clk_disable(phy->pll_u);
+        clk_disable_unprepare(phy->pll_u);
         clk_put(phy->pll_u);
 err0:
         kfree(phy);
@@ -810,7 +810,7 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy)
                 clk_put(phy->clk);
         else
                 utmip_pad_close(phy);
-        clk_disable(phy->pll_u);
+        clk_disable_unprepare(phy->pll_u);
         clk_put(phy->pll_u);
         kfree(phy);
 }
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index fd3a5c382f4..7e47d37aeb0 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel, U300 machine.
 #
 
-obj-y           := core.o clock.o timer.o
+obj-y           := core.o timer.o
 obj-m           :=
 obj-n           :=
 obj-            :=
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
deleted file mode 100644
index 5535dd0a78c..00000000000
--- a/arch/arm/mach-u300/clock.c
+++ /dev/null
@@ -1,1504 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/clock.c
- *
- *
- * Copyright (C) 2007-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Define clocks in the app platform.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- *
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/spinlock.h>
-#include <linux/debugfs.h>
-#include <linux/device.h>
-#include <linux/init.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-#include <linux/seq_file.h>
-#include <linux/clkdev.h>
-
-#include <mach/hardware.h>
-#include <mach/syscon.h>
-
-#include "clock.h"
-
-/*
- * TODO:
- * - move all handling of the CCR register into this file and create
- *   a spinlock for the CCR register
- * - switch to the clkdevice lookup mechanism that maps clocks to
- *   device ID:s instead when it becomes available in kernel 2.6.29.
- * - implement rate get/set for all clocks that need it.
- */
-
-/*
- * Syscon clock I/O registers lock so clock requests don't collide
- * NOTE: this is a local lock only used to lock access to clock and
- * reset registers in syscon.
- */
-static DEFINE_SPINLOCK(syscon_clkreg_lock);
-static DEFINE_SPINLOCK(syscon_resetreg_lock);
-
-/*
- * The clocking hierarchy currently looks like this.
- * NOTE: the idea is NOT to show how the clocks are routed on the chip!
- * The ideas is to show dependencies, so a clock higher up in the
- * hierarchy has to be on in order for another clock to be on. Now,
- * both CPU and DMA can actually be on top of the hierarchy, and that
- * is not modeled currently. Instead we have the backbone AMBA bus on
- * top. This bus cannot be programmed in any way but conceptually it
- * needs to be active for the bridges and devices to transport data.
- *
- * Please be aware that a few clocks are hw controlled, which mean that
- * the hw itself can turn on/off or change the rate of the clock when
- * needed!
- *
- *  AMBA bus
- *  |
- *  +- CPU
- *  +- FSMC NANDIF NAND Flash interface
- *  +- SEMI Shared Memory interface
- *  +- ISP Image Signal Processor (U335 only)
- *  +- CDS (U335 only)
- *  +- DMA Direct Memory Access Controller
- *  +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
- *  +- APEX
- *  +- VIDEO_ENC AVE2/3 Video Encoder
- *  +- XGAM Graphics Accelerator Controller
- *  +- AHB
- *  |
- *  +- ahb:0 AHB Bridge
- *  |  |
- *  |  +- ahb:1 INTCON Interrupt controller
- *  |  +- ahb:3 MSPRO  Memory Stick Pro controller
- *  |  +- ahb:4 EMIF   External Memory interface
- *  |
- *  +- fast:0 FAST bridge
- *  |  |
- *  |  +- fast:1 MMCSD MMC/SD card reader controller
- *  |  +- fast:2 I2S0  PCM I2S channel 0 controller
- *  |  +- fast:3 I2S1  PCM I2S channel 1 controller
- *  |  +- fast:4 I2C0  I2C channel 0 controller
- *  |  +- fast:5 I2C1  I2C channel 1 controller
- *  |  +- fast:6 SPI   SPI controller
- *  |  +- fast:7 UART1 Secondary UART (U335 only)
- *  |
- *  +- slow:0 SLOW bridge
- *     |
- *     +- slow:1 SYSCON (not possible to control)
- *     +- slow:2 WDOG Watchdog
- *     +- slow:3 UART0 primary UART
- *     +- slow:4 TIMER_APP Application timer - used in Linux
- *     +- slow:5 KEYPAD controller
- *     +- slow:6 GPIO controller
- *     +- slow:7 RTC controller
- *     +- slow:8 BT Bus Tracer (not used currently)
- *     +- slow:9 EH Event Handler (not used currently)
- *     +- slow:a TIMER_ACC Access style timer (not used currently)
- *     +- slow:b PPM (U335 only, what is that?)
- */
-
-/*
- * Reset control functions. We remember if a block has been
- * taken out of reset and don't remove the reset assertion again
- * and vice versa. Currently we only remove resets so the
- * enablement function is defined out.
- */
-static void syscon_block_reset_enable(struct clk *clk)
-{
-        u16 val;
-        unsigned long iflags;
-
-        /* Not all blocks support resetting */
-        if (!clk->res_reg || !clk->res_mask)
-                return;
-        spin_lock_irqsave(&syscon_resetreg_lock, iflags);
-        val = readw(clk->res_reg);
-        val |= clk->res_mask;
-        writew(val, clk->res_reg);
-        spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
-        clk->reset = true;
-}
-
-static void syscon_block_reset_disable(struct clk *clk)
-{
-        u16 val;
-        unsigned long iflags;
-
-        /* Not all blocks support resetting */
-        if (!clk->res_reg || !clk->res_mask)
-                return;
-        spin_lock_irqsave(&syscon_resetreg_lock, iflags);
-        val = readw(clk->res_reg);
-        val &= ~clk->res_mask;
-        writew(val, clk->res_reg);
-        spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
-        clk->reset = false;
-}
-
-int __clk_get(struct clk *clk)
-{
-        u16 val;
-
-        /* The MMC and MSPRO clocks need some special set-up */
-        if (!strcmp(clk->name, "MCLK")) {
-                /* Set default MMC clock divisor to 18.9 MHz */
-                writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
-                val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
-                /* Disable the MMC feedback clock */
-                val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
-                /* Disable MSPRO frequency */
-                val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
-                writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
-        }
-        if (!strcmp(clk->name, "MSPRO")) {
-                val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
-                /* Disable the MMC feedback clock */
-                val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
-                /* Enable MSPRO frequency */
-                val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
-                writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
-        }
-        return 1;
-}
-EXPORT_SYMBOL(__clk_get);
-
-void __clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(__clk_put);
-
-static void syscon_clk_disable(struct clk *clk)
-{
-        unsigned long iflags;
-
-        /* Don't touch the hardware controlled clocks */
-        if (clk->hw_ctrld)
-                return;
-
-        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-        writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR);
-        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-
-static void syscon_clk_enable(struct clk *clk)
-{
-        unsigned long iflags;
-
-        /* Don't touch the hardware controlled clocks */
-        if (clk->hw_ctrld)
-                return;
-
-        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-        writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER);
-        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-
-static u16 syscon_clk_get_rate(void)
-{
-        u16 val;
-        unsigned long iflags;
-
-        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
-        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-        return val;
-}
-
-#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
-static void enable_i2s0_vcxo(void)
-{
-        u16 val;
-        unsigned long iflags;
-
-        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-        /* Set I2S0 to use the VCXO 26 MHz clock */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val |= U300_SYSCON_CCR_TURN_VCXO_ON;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-        val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-
-static void enable_i2s1_vcxo(void)
-{
-        u16 val;
-        unsigned long iflags;
-
-        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-        /* Set I2S1 to use the VCXO 26 MHz clock */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val |= U300_SYSCON_CCR_TURN_VCXO_ON;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-        val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-
-static void disable_i2s0_vcxo(void)
-{
-        u16 val;
-        unsigned long iflags;
-
-        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-        /* Disable I2S0 use of the VCXO 26 MHz clock */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        /* Deactivate VCXO if no one else is using VCXO */
-        if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
-                val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-        val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-
-static void disable_i2s1_vcxo(void)
-{
-        u16 val;
-        unsigned long iflags;
-
-        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-        /* Disable I2S1 use of the VCXO 26 MHz clock */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        /* Deactivate VCXO if no one else is using VCXO */
-        if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
-                val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-        val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-#endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
-
-
-static void syscon_clk_rate_set_mclk(unsigned long rate)
-{
-        u16 val;
-        u32 reg;
-        unsigned long iflags;
-
-        switch (rate) {
-        case 18900000:
-                val = 0x0054;
-                break;
-        case 20800000:
-                val = 0x0044;
-                break;
-        case 23100000:
-                val = 0x0043;
-                break;
-        case 26000000:
-                val = 0x0033;
-                break;
-        case 29700000:
-                val = 0x0032;
-                break;
-        case 34700000:
-                val = 0x0022;
-                break;
-        case 41600000:
-                val = 0x0021;
-                break;
-        case 52000000:
-                val = 0x0011;
-                break;
-        case 104000000:
-                val = 0x0000;
-                break;
-        default:
-                printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n",
-                       rate);
-                return;
-        }
-
-        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-        reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
-                ~U300_SYSCON_MMF0R_MASK;
-        writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
-        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-
-void syscon_clk_rate_set_cpuclk(unsigned long rate)
-{
-        u16 val;
-        unsigned long iflags;
-
-        switch (rate) {
-        case 13000000:
-                val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
-                break;
-        case 52000000:
-                val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
-                break;
-        case 104000000:
-                val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
-                break;
-        case 208000000:
-                val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
-                break;
-        default:
-                return;
-        }
-        spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-        val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) &
-                ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk);
-
-void clk_disable(struct clk *clk)
-{
-        unsigned long iflags;
-
-        spin_lock_irqsave(&clk->lock, iflags);
-        if (clk->usecount > 0 && !(--clk->usecount)) {
-                /* some blocks lack clocking registers and cannot be disabled */
-                if (clk->disable)
-                        clk->disable(clk);
-                if (likely((u32)clk->parent))
-                        clk_disable(clk->parent);
-        }
-#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
-        if (unlikely(!strcmp(clk->name, "I2S0")))
-                disable_i2s0_vcxo();
-        if (unlikely(!strcmp(clk->name, "I2S1")))
-                disable_i2s1_vcxo();
-#endif
-        spin_unlock_irqrestore(&clk->lock, iflags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-int clk_enable(struct clk *clk)
-{
-        int ret = 0;
-        unsigned long iflags;
-
-        spin_lock_irqsave(&clk->lock, iflags);
-        if (clk->usecount++ == 0) {
-                if (likely((u32)clk->parent))
-                        ret = clk_enable(clk->parent);
-
-                if (unlikely(ret != 0))
-                        clk->usecount--;
-                else {
-                        /* remove reset line (we never enable reset again) */
-                        syscon_block_reset_disable(clk);
-                        /* clocks without enable function are always on */
-                        if (clk->enable)
-                                clk->enable(clk);
-#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
-                        if (unlikely(!strcmp(clk->name, "I2S0")))
-                                enable_i2s0_vcxo();
-                        if (unlikely(!strcmp(clk->name, "I2S1")))
-                                enable_i2s1_vcxo();
-#endif
-                }
-        }
-        spin_unlock_irqrestore(&clk->lock, iflags);
-        return ret;
-
-}
-EXPORT_SYMBOL(clk_enable);
-
-/* Returns the clock rate in Hz */
-static unsigned long clk_get_rate_cpuclk(struct clk *clk)
-{
-        u16 val;
-
-        val = syscon_clk_get_rate();
-
-        switch (val) {
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
-                return 13000000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
-                return 52000000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
-                return 104000000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
-                return 208000000;
-        default:
-                break;
-        }
-        return clk->rate;
-}
-
-static unsigned long clk_get_rate_ahb_clk(struct clk *clk)
-{
-        u16 val;
-
-        val = syscon_clk_get_rate();
-
-        switch (val) {
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
-                return 6500000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
-                return 26000000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
-                return 52000000;
-        default:
-                break;
-        }
-        return clk->rate;
-
-}
-
-static unsigned long clk_get_rate_emif_clk(struct clk *clk)
-{
-        u16 val;
-
-        val = syscon_clk_get_rate();
-
-        switch (val) {
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
-                return 13000000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
-                return 52000000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
-                return 104000000;
-        default:
-                break;
-        }
-        return clk->rate;
-
-}
-
-static unsigned long clk_get_rate_xgamclk(struct clk *clk)
-{
-        u16 val;
-
-        val = syscon_clk_get_rate();
-
-        switch (val) {
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
-                return 6500000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
-                return 26000000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
-                return 52000000;
-        default:
-                break;
-        }
-
-        return clk->rate;
-}
-
-static unsigned long clk_get_rate_mclk(struct clk *clk)
-{
-        u16 val;
-
-        val = syscon_clk_get_rate();
-
-        switch (val) {
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
-                /*
-                 * Here, the 208 MHz PLL gets shut down and the always
-                 * on 13 MHz PLL used for RTC etc kicks into use
-                 * instead.
-                 */
-                return 13000000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
-        {
-                /*
-                 * This clock is under program control. The register is
-                 * divided in two nybbles, bit 7-4 gives cycles-1 to count
-                 * high, bit 3-0 gives cycles-1 to count low. Distribute
-                 * these with no more than 1 cycle difference between
-                 * low and high and add low and high to get the actual
-                 * divisor. The base PLL is 208 MHz. Writing 0x00 will
-                 * divide by 1 and 1 so the highest frequency possible
-                 * is 104 MHz.
-                 *
-                 * e.g. 0x54 =>
-                 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
-                 */
-                u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
-                        U300_SYSCON_MMF0R_MASK;
-                switch (val) {
-                case 0x0054:
-                        return 18900000;
-                case 0x0044:
-                        return 20800000;
-                case 0x0043:
-                        return 23100000;
-                case 0x0033:
-                        return 26000000;
-                case 0x0032:
-                        return 29700000;
-                case 0x0022:
-                        return 34700000;
-                case 0x0021:
-                        return 41600000;
-                case 0x0011:
-                        return 52000000;
-                case 0x0000:
-                        return 104000000;
-                default:
-                        break;
-                }
-        }
-        default:
-                break;
-        }
-
-        return clk->rate;
-}
-
-static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk)
-{
-        u16 val;
-
-        val = syscon_clk_get_rate();
-
-        switch (val) {
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
-                return 13000000;
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
-        case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
-                return 26000000;
-        default:
-                break;
-        }
-
-        return clk->rate;
-}
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-        if (clk->get_rate)
-                return clk->get_rate(clk);
-        else
-                return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
-{
-        if (rate <= 18900000)
-                return 18900000;
-        if (rate <= 20800000)
-                return 20800000;
-        if (rate <= 23100000)
-                return 23100000;
-        if (rate <= 26000000)
-                return 26000000;
-        if (rate <= 29700000)
-                return 29700000;
-        if (rate <= 34700000)
-                return 34700000;
-        if (rate <= 41600000)
-                return 41600000;
-        if (rate <= 52000000)
-                return 52000000;
-        return -EINVAL;
-}
-
-static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
-{
-        if (rate <= 13000000)
-                return 13000000;
-        if (rate <= 52000000)
-                return 52000000;
-        if (rate <= 104000000)
-                return 104000000;
-        if (rate <= 208000000)
-                return 208000000;
-        return -EINVAL;
-}
-
-/*
- * This adjusts a requested rate to the closest exact rate
- * a certain clock can provide. For a fixed clock it's
- * mostly clk->rate.
- */
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-        /* TODO: get appropriate switches for EMIFCLK, AHBCLK and MCLK */
-        /* Else default to fixed value */
-
-        if (clk->round_rate) {
-                return (long) clk->round_rate(clk, rate);
-        } else {
-                printk(KERN_ERR "clock: Failed to round rate of %s\n",
-                       clk->name);
-        }
-        return (long) clk->rate;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-static int clk_set_rate_mclk(struct clk *clk, unsigned long rate)
-{
-        syscon_clk_rate_set_mclk(clk_round_rate(clk, rate));
-        return 0;
-}
-
-static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate)
-{
-        syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate));
-        return 0;
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-        /* TODO: set for EMIFCLK and AHBCLK */
-        /* Else assume the clock is fixed and fail */
-        if (clk->set_rate) {
-                return clk->set_rate(clk, rate);
-        } else {
-                printk(KERN_ERR "clock: Failed to set %s to %ld hz\n",
-                       clk->name, rate);
-                return -EINVAL;
-        }
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-/*
- * Clock definitions. The clock parents are set to respective
- * bridge and the clock framework makes sure that the clocks have
- * parents activated and are brought out of reset when in use.
- *
- * Clocks that have hw_ctrld = true are hw controlled, and the hw
- * can by itself turn these clocks on and off.
- * So in other words, we don't really have to care about them.
- */
-
-static struct clk amba_clk = {
-        .name       = "AMBA",
-        .rate       = 52000000, /* this varies! */
-        .hw_ctrld   = true,
-        .reset      = false,
-        .lock       = __SPIN_LOCK_UNLOCKED(amba_clk.lock),
-};
-
-/*
- * These blocks are connected directly to the AMBA bus
- * with no bridge.
- */
-
-static struct clk cpu_clk = {
-        .name       = "CPU",
-        .parent     = &amba_clk,
-        .rate       = 208000000, /* this varies! */
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_CPU_RESET_EN,
-        .set_rate   = clk_set_rate_cpuclk,
-        .get_rate   = clk_get_rate_cpuclk,
-        .round_rate = clk_round_rate_cpuclk,
-        .lock       = __SPIN_LOCK_UNLOCKED(cpu_clk.lock),
-};
-
-static struct clk nandif_clk = {
-        .name       = "FSMC",
-        .parent     = &amba_clk,
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_NANDIF_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_NANDIF_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(nandif_clk.lock),
-};
-
-static struct clk semi_clk = {
-        .name       = "SEMI",
-        .parent     = &amba_clk,
-        .rate       = 0, /* FIXME */
-        /* It is not possible to reset SEMI */
-        .hw_ctrld   = false,
-        .reset      = false,
-        .clk_val    = U300_SYSCON_SBCER_SEMI_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(semi_clk.lock),
-};
-
-#ifdef CONFIG_MACH_U300_BS335
-static struct clk isp_clk = {
-        .name       = "ISP",
-        .parent     = &amba_clk,
-        .rate       = 0, /* FIXME */
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_ISP_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_ISP_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(isp_clk.lock),
-};
-
-static struct clk cds_clk = {
-        .name       = "CDS",
-        .parent     = &amba_clk,
-        .rate       = 0, /* FIXME */
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_CDS_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_CDS_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(cds_clk.lock),
-};
-#endif
-
-static struct clk dma_clk = {
-        .name       = "DMA",
-        .parent     = &amba_clk,
-        .rate       = 52000000, /* this varies! */
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_DMAC_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_DMAC_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(dma_clk.lock),
-};
-
-static struct clk aaif_clk = {
-        .name       = "AAIF",
-        .parent     = &amba_clk,
-        .rate       = 52000000, /* this varies! */
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_AAIF_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_AAIF_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(aaif_clk.lock),
-};
-
-static struct clk apex_clk = {
-        .name       = "APEX",
-        .parent     = &amba_clk,
-        .rate       = 0, /* FIXME */
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_APEX_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_APEX_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(apex_clk.lock),
-};
-
-static struct clk video_enc_clk = {
-        .name       = "VIDEO_ENC",
-        .parent     = &amba_clk,
-        .rate       = 208000000, /* this varies! */
-        .hw_ctrld   = false,
-        .reset      = false,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        /* This has XGAM in the name but refers to the video encoder */
-        .res_mask   = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(video_enc_clk.lock),
-};
-
-static struct clk xgam_clk = {
-        .name       = "XGAMCLK",
-        .parent     = &amba_clk,
-        .rate       = 52000000, /* this varies! */
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_XGAM_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_XGAM_CLK_EN,
-        .get_rate   = clk_get_rate_xgamclk,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(xgam_clk.lock),
-};
-
-/* This clock is used to activate the video encoder */
-static struct clk ahb_clk = {
-        .name       = "AHB",
-        .parent     = &amba_clk,
-        .rate       = 52000000, /* this varies! */
-        .hw_ctrld   = false, /* This one is set to false due to HW bug */
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_AHB_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_AHB_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .get_rate   = clk_get_rate_ahb_clk,
-        .lock       = __SPIN_LOCK_UNLOCKED(ahb_clk.lock),
-};
-
-
-/*
- * Clocks on the AHB bridge
- */
-
-static struct clk ahb_subsys_clk = {
-        .name       = "AHB_SUBSYS",
-        .parent     = &amba_clk,
-        .rate       = 52000000, /* this varies! */
-        .hw_ctrld   = true,
-        .reset      = false,
-        .clk_val    = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .get_rate   = clk_get_rate_ahb_clk,
-        .lock       = __SPIN_LOCK_UNLOCKED(ahb_subsys_clk.lock),
-};
-
-static struct clk intcon_clk = {
-        .name       = "INTCON",
-        .parent     = &ahb_subsys_clk,
-        .rate       = 52000000, /* this varies! */
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_INTCON_RESET_EN,
-        /* INTCON can be reset but not clock-gated */
-        .lock       = __SPIN_LOCK_UNLOCKED(intcon_clk.lock),
-
-};
-
-static struct clk mspro_clk = {
-        .name       = "MSPRO",
-        .parent     = &ahb_subsys_clk,
-        .rate       = 0, /* FIXME */
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_MSPRO_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_MSPRO_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(mspro_clk.lock),
-};
-
-static struct clk emif_clk = {
-        .name       = "EMIF",
-        .parent     = &ahb_subsys_clk,
-        .rate       = 104000000, /* this varies! */
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RRR,
-        .res_mask   = U300_SYSCON_RRR_EMIF_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_EMIF_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .get_rate   = clk_get_rate_emif_clk,
-        .lock       = __SPIN_LOCK_UNLOCKED(emif_clk.lock),
-};
-
-
-/*
- * Clocks on the FAST bridge
- */
-static struct clk fast_clk = {
-        .name       = "FAST_BRIDGE",
-        .parent     = &amba_clk,
-        .rate       = 13000000, /* this varies! */
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
-        .res_mask   = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE,
-        .clk_val    = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(fast_clk.lock),
-};
-
-/*
- * The MMCI apb_pclk is hardwired to the same terminal as the
- * external MCI clock. Thus this will be referenced twice.
- */
-static struct clk mmcsd_clk = {
-        .name       = "MCLK",
-        .parent     = &fast_clk,
-        .rate       = 18900000, /* this varies! */
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
-        .res_mask   = U300_SYSCON_RFR_MMC_RESET_ENABLE,
-        .clk_val    = U300_SYSCON_SBCER_MMC_CLK_EN,
-        .get_rate   = clk_get_rate_mclk,
-        .set_rate   = clk_set_rate_mclk,
-        .round_rate = clk_round_rate_mclk,
-        .disable    = syscon_clk_disable,
-        .enable     = syscon_clk_enable,
-        .lock       = __SPIN_LOCK_UNLOCKED(mmcsd_clk.lock),
-};
-
-static struct clk i2s0_clk = {
-        .name       = "i2s0",
-        .parent     = &fast_clk,
-        .rate       = 26000000, /* this varies! */
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
-        .res_mask   = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE,
-        .clk_val    = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .get_rate   = clk_get_rate_i2s_i2c_spi,
-        .lock       = __SPIN_LOCK_UNLOCKED(i2s0_clk.lock),
-};
-
-static struct clk i2s1_clk = {
-        .name       = "i2s1",
-        .parent     = &fast_clk,
-        .rate       = 26000000, /* this varies! */
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
-        .res_mask   = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE,
-        .clk_val    = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .get_rate   = clk_get_rate_i2s_i2c_spi,
-        .lock       = __SPIN_LOCK_UNLOCKED(i2s1_clk.lock),
-};
-
-static struct clk i2c0_clk = {
-        .name       = "I2C0",
-        .parent     = &fast_clk,
-        .rate       = 26000000, /* this varies! */
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
-        .res_mask   = U300_SYSCON_RFR_I2C0_RESET_ENABLE,
-        .clk_val    = U300_SYSCON_SBCER_I2C0_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .get_rate   = clk_get_rate_i2s_i2c_spi,
-        .lock       = __SPIN_LOCK_UNLOCKED(i2c0_clk.lock),
-};
-
-static struct clk i2c1_clk = {
-        .name       = "I2C1",
-        .parent     = &fast_clk,
-        .rate       = 26000000, /* this varies! */
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
-        .res_mask   = U300_SYSCON_RFR_I2C1_RESET_ENABLE,
-        .clk_val    = U300_SYSCON_SBCER_I2C1_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .get_rate   = clk_get_rate_i2s_i2c_spi,
-        .lock       = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock),
-};
-
-/*
- * The SPI apb_pclk is hardwired to the same terminal as the
- * external SPI clock. Thus this will be referenced twice.
- */
-static struct clk spi_clk = {
-        .name       = "SPI",
-        .parent     = &fast_clk,
-        .rate       = 26000000, /* this varies! */
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
-        .res_mask   = U300_SYSCON_RFR_SPI_RESET_ENABLE,
-        .clk_val    = U300_SYSCON_SBCER_SPI_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .get_rate   = clk_get_rate_i2s_i2c_spi,
-        .lock       = __SPIN_LOCK_UNLOCKED(spi_clk.lock),
-};
-
-#ifdef CONFIG_MACH_U300_BS335
-static struct clk uart1_pclk = {
-        .name       = "UART1_PCLK",
-        .parent     = &fast_clk,
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RFR,
-        .res_mask   = U300_SYSCON_RFR_UART1_RESET_ENABLE,
-        .clk_val    = U300_SYSCON_SBCER_UART1_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(uart1_pclk.lock),
-};
-
-/* This one is hardwired to PLL13 */
-static struct clk uart1_clk = {
-        .name       = "UART1_CLK",
-        .rate       = 13000000,
-        .hw_ctrld   = true,
-        .lock       = __SPIN_LOCK_UNLOCKED(uart1_clk.lock),
-};
-#endif
-
-
-/*
- * Clocks on the SLOW bridge
- */
-static struct clk slow_clk = {
-        .name       = "SLOW_BRIDGE",
-        .parent     = &amba_clk,
-        .rate       = 13000000,
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
-        .res_mask   = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(slow_clk.lock),
-};
-
-/* TODO: implement SYSCON clock? */
-
-static struct clk wdog_clk = {
-        .name       = "WDOG",
-        .parent     = &slow_clk,
-        .hw_ctrld   = false,
-        .rate       = 32768,
-        .reset      = false,
-        /* This is always on, cannot be enabled/disabled or reset */
-        .lock       = __SPIN_LOCK_UNLOCKED(wdog_clk.lock),
-};
-
-static struct clk uart0_pclk = {
-        .name       = "UART0_PCLK",
-        .parent     = &slow_clk,
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
-        .res_mask   = U300_SYSCON_RSR_UART_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_UART_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(uart0_pclk.lock),
-};
-
-/* This one is hardwired to PLL13 */
-static struct clk uart0_clk = {
-        .name       = "UART0_CLK",
-        .parent     = &slow_clk,
-        .rate       = 13000000,
-        .hw_ctrld   = true,
-        .lock       = __SPIN_LOCK_UNLOCKED(uart0_clk.lock),
-};
-
-static struct clk keypad_clk = {
-        .name       = "KEYPAD",
-        .parent     = &slow_clk,
-        .rate       = 32768,
-        .hw_ctrld   = false,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
-        .res_mask   = U300_SYSCON_RSR_KEYPAD_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_KEYPAD_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(keypad_clk.lock),
-};
-
-static struct clk gpio_clk = {
-        .name       = "GPIO",
-        .parent     = &slow_clk,
-        .rate       = 13000000,
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
-        .res_mask   = U300_SYSCON_RSR_GPIO_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_GPIO_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(gpio_clk.lock),
-};
-
-static struct clk rtc_clk = {
-        .name       = "RTC",
-        .parent     = &slow_clk,
-        .rate       = 32768,
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
-        .res_mask   = U300_SYSCON_RSR_RTC_RESET_EN,
-        /* This clock is always on, cannot be enabled/disabled */
-        .lock       = __SPIN_LOCK_UNLOCKED(rtc_clk.lock),
-};
-
-static struct clk bustr_clk = {
-        .name       = "BUSTR",
-        .parent     = &slow_clk,
-        .rate       = 13000000,
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
-        .res_mask   = U300_SYSCON_RSR_BTR_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_BTR_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(bustr_clk.lock),
-};
-
-static struct clk evhist_clk = {
-        .name       = "EVHIST",
-        .parent     = &slow_clk,
-        .rate       = 13000000,
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
-        .res_mask   = U300_SYSCON_RSR_EH_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_EH_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(evhist_clk.lock),
-};
-
-static struct clk timer_clk = {
-        .name       = "TIMER",
-        .parent     = &slow_clk,
-        .rate       = 13000000,
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
-        .res_mask   = U300_SYSCON_RSR_ACC_TMR_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(timer_clk.lock),
-};
-
-/*
- * There is a binary divider in the hardware that divides
- * the 13MHz PLL by 13 down to 1 MHz.
- */
-static struct clk app_timer_clk = {
-        .name       = "TIMER_APP",
-        .parent     = &slow_clk,
-        .rate       = 1000000,
-        .hw_ctrld   = true,
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
-        .res_mask   = U300_SYSCON_RSR_APP_TMR_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(app_timer_clk.lock),
-};
-
-#ifdef CONFIG_MACH_U300_BS335
-static struct clk ppm_clk = {
-        .name       = "PPM",
-        .parent     = &slow_clk,
-        .rate       = 0, /* FIXME */
-        .hw_ctrld   = true, /* TODO: Look up if it is hw ctrld or not */
-        .reset      = true,
-        .res_reg    = U300_SYSCON_VBASE + U300_SYSCON_RSR,
-        .res_mask   = U300_SYSCON_RSR_PPM_RESET_EN,
-        .clk_val    = U300_SYSCON_SBCER_PPM_CLK_EN,
-        .enable     = syscon_clk_enable,
-        .disable    = syscon_clk_disable,
-        .lock       = __SPIN_LOCK_UNLOCKED(ppm_clk.lock),
-};
-#endif
-
-#define DEF_LOOKUP(devid, clkref)               \
-        {                                       \
-        .dev_id = devid,                        \
-        .clk = clkref,                          \
-        }
-
-#define DEF_LOOKUP_CON(devid, conid, clkref)    \
-        {                                       \
-        .dev_id = devid,                        \
-        .con_id = conid,                        \
-        .clk = clkref,                          \
-        }
-
-/*
- * Here we only define clocks that are meaningful to
- * look up through clockdevice.
- */
-static struct clk_lookup lookups[] = {
-        /* Connected directly to the AMBA bus */
-        DEF_LOOKUP("amba",      &amba_clk),
-        DEF_LOOKUP("cpu",       &cpu_clk),
-        DEF_LOOKUP("fsmc-nand", &nandif_clk),
-        DEF_LOOKUP("semi",      &semi_clk),
-#ifdef CONFIG_MACH_U300_BS335
-        DEF_LOOKUP("isp",       &isp_clk),
-        DEF_LOOKUP("cds",       &cds_clk),
-#endif
-        DEF_LOOKUP("dma",       &dma_clk),
-        DEF_LOOKUP("msl",       &aaif_clk),
-        DEF_LOOKUP("apex",      &apex_clk),
-        DEF_LOOKUP("video_enc", &video_enc_clk),
-        DEF_LOOKUP("xgam",      &xgam_clk),
-        DEF_LOOKUP("ahb",       &ahb_clk),
-        /* AHB bridge clocks */
-        DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk),
-        DEF_LOOKUP("intcon",    &intcon_clk),
-        DEF_LOOKUP_CON("intcon", "apb_pclk", &intcon_clk),
-        DEF_LOOKUP("mspro",     &mspro_clk),
-        DEF_LOOKUP("pl172",     &emif_clk),
-        DEF_LOOKUP_CON("pl172", "apb_pclk", &emif_clk),
-        /* FAST bridge clocks */
-        DEF_LOOKUP("fast",      &fast_clk),
-        DEF_LOOKUP("mmci",      &mmcsd_clk),
-        DEF_LOOKUP_CON("mmci", "apb_pclk", &mmcsd_clk),
-        /*
-         * The .0 and .1 identifiers on these comes from the platform device
-         * .id field and are assigned when the platform devices are registered.
-         */
-        DEF_LOOKUP("i2s.0",     &i2s0_clk),
-        DEF_LOOKUP("i2s.1",     &i2s1_clk),
-        DEF_LOOKUP("stu300.0",  &i2c0_clk),
-        DEF_LOOKUP("stu300.1",  &i2c1_clk),
-        DEF_LOOKUP("pl022",     &spi_clk),
-        DEF_LOOKUP_CON("pl022", "apb_pclk", &spi_clk),
-#ifdef CONFIG_MACH_U300_BS335
-        DEF_LOOKUP("uart1",     &uart1_clk),
-        DEF_LOOKUP_CON("uart1", "apb_pclk", &uart1_pclk),
-#endif
-        /* SLOW bridge clocks */
-        DEF_LOOKUP("slow",      &slow_clk),
-        DEF_LOOKUP("coh901327_wdog",      &wdog_clk),
-        DEF_LOOKUP("uart0",     &uart0_clk),
-        DEF_LOOKUP_CON("uart0", "apb_pclk", &uart0_pclk),
-        DEF_LOOKUP("apptimer",  &app_timer_clk),
-        DEF_LOOKUP("coh901461-keypad",    &keypad_clk),
-        DEF_LOOKUP("u300-gpio", &gpio_clk),
-        DEF_LOOKUP("rtc-coh901331",      &rtc_clk),
-        DEF_LOOKUP("bustr",     &bustr_clk),
-        DEF_LOOKUP("evhist",    &evhist_clk),
-        DEF_LOOKUP("timer",     &timer_clk),
-#ifdef CONFIG_MACH_U300_BS335
-        DEF_LOOKUP("ppm",       &ppm_clk),
-#endif
-};
-
-static void __init clk_register(void)
-{
-        /* Register the lookups */
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
-
-#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
-/*
- * The following makes it possible to view the status (especially
- * reference count and reset status) for the clocks in the platform
- * by looking into the special file <debugfs>/u300_clocks
- */
-
-/* A list of all clocks in the platform */
-static struct clk *clks[] = {
-        /* Top node clock for the AMBA bus */
-        &amba_clk,
-        /* Connected directly to the AMBA bus */
-        &cpu_clk,
-        &nandif_clk,
-        &semi_clk,
-#ifdef CONFIG_MACH_U300_BS335
-        &isp_clk,
-        &cds_clk,
-#endif
-        &dma_clk,
-        &aaif_clk,
-        &apex_clk,
-        &video_enc_clk,
-        &xgam_clk,
-        &ahb_clk,
-
-        /* AHB bridge clocks */
-        &ahb_subsys_clk,
-        &intcon_clk,
-        &mspro_clk,
-        &emif_clk,
-        /* FAST bridge clocks */
-        &fast_clk,
-        &mmcsd_clk,
-        &i2s0_clk,
-        &i2s1_clk,
-        &i2c0_clk,
-        &i2c1_clk,
-        &spi_clk,
-#ifdef CONFIG_MACH_U300_BS335
-        &uart1_clk,
-        &uart1_pclk,
-#endif
-        /* SLOW bridge clocks */
-        &slow_clk,
-        &wdog_clk,
-        &uart0_clk,
-        &uart0_pclk,
-        &app_timer_clk,
-        &keypad_clk,
-        &gpio_clk,
-        &rtc_clk,
-        &bustr_clk,
-        &evhist_clk,
-        &timer_clk,
-#ifdef CONFIG_MACH_U300_BS335
-        &ppm_clk,
-#endif
-};
-
-static int u300_clocks_show(struct seq_file *s, void *data)
-{
-        struct clk *clk;
-        int i;
-
-        seq_printf(s, "CLOCK           DEVICE          RESET STATE\t" \
-                   "ACTIVE\tUSERS\tHW CTRL FREQ\n");
-        seq_printf(s, "---------------------------------------------" \
-                   "-----------------------------------------\n");
-        for (i = 0; i < ARRAY_SIZE(clks); i++) {
-                clk = clks[i];
-                if (clk != ERR_PTR(-ENOENT)) {
-                        /* Format clock and device name nicely */
-                        char cdp[33];
-                        int chars;
-
-                        chars = snprintf(&cdp[0], 17, "%s", clk->name);
-                        while (chars < 16) {
-                                cdp[chars] = ' ';
-                                chars++;
-                        }
-                        chars = snprintf(&cdp[16], 17, "%s", clk->dev ?
-                                         dev_name(clk->dev) : "N/A");
-                        while (chars < 16) {
-                                cdp[chars+16] = ' ';
-                                chars++;
-                        }
-                        cdp[32] = '\0';
-                        if (clk->get_rate || clk->rate != 0)
-                                seq_printf(s,
-                                           "%s%s\t%s\t%d\t%s\t%lu Hz\n",
-                                           &cdp[0],
-                                           clk->reset ?
-                                           "ASSERTED" : "RELEASED",
-                                           clk->usecount ? "ON" : "OFF",
-                                           clk->usecount,
-                                           clk->hw_ctrld  ? "YES" : "NO ",
-                                           clk_get_rate(clk));
-                        else
-                                seq_printf(s,
-                                           "%s%s\t%s\t%d\t%s\t" \
-                                           "(unknown rate)\n",
-                                           &cdp[0],
-                                           clk->reset ?
-                                           "ASSERTED" : "RELEASED",
-                                           clk->usecount ? "ON" : "OFF",
-                                           clk->usecount,
-                                           clk->hw_ctrld  ? "YES" : "NO ");
-                }
-        }
-        return 0;
-}
-
-static int u300_clocks_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, u300_clocks_show, NULL);
-}
-
-static const struct file_operations u300_clocks_operations = {
-        .open           = u300_clocks_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-};
-
-static int __init init_clk_read_debugfs(void)
-{
-        /* Expose a simple debugfs interface to view all clocks */
-        (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO,
-                                   NULL, NULL,
-                                   &u300_clocks_operations);
-        return 0;
-}
-/*
- * This needs to come in after the core_initcall() for the
- * overall clocks, because debugfs is not available until
- * the subsystems come up.
- */
-module_init(init_clk_read_debugfs);
-#endif
-
-int __init u300_clock_init(void)
-{
-        u16 val;
-
-        /*
-         * FIXME: shall all this powermanagement stuff really live here???
-         */
-
-        /* Set system to run at PLL208, max performance, a known state. */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        /* Wait for the PLL208 to lock if not locked in yet */
-        while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
-                 U300_SYSCON_CSR_PLL208_LOCK_IND));
-
-        /* Power management enable */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
-        val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
-
-        clk_register();
-
-        /*
-         * Some of these may be on when we boot the system so make sure they
-         * are turned OFF.
-         */
-        syscon_block_reset_enable(&timer_clk);
-        timer_clk.disable(&timer_clk);
-
-        /*
-         * These shall be turned on by default when we boot the system
-         * so make sure they are ON. (Adding CPU here is a bit too much.)
-         * These clocks will be claimed by drivers later.
-         */
-        syscon_block_reset_disable(&semi_clk);
-        syscon_block_reset_disable(&emif_clk);
-        clk_enable(&semi_clk);
-        clk_enable(&emif_clk);
-
-        return 0;
-}
diff --git a/arch/arm/mach-u300/clock.h b/arch/arm/mach-u300/clock.h
deleted file mode 100644
index 4f50ca8f901..00000000000
--- a/arch/arm/mach-u300/clock.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * arch/arm/mach-u300/include/mach/clock.h
- *
- * Copyright (C) 2004 - 2005 Nokia corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
- * Copyright (C) 2007-2009 ST-Ericsson AB
- * Adopted to ST-Ericsson U300 platforms by
- * Jonas Aaberg <jonas.aberg@stericsson.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#ifndef __MACH_CLOCK_H
-#define __MACH_CLOCK_H
-
-#include <linux/clk.h>
-
-struct clk {
-        struct list_head node;
-        struct module *owner;
-        struct device *dev;
-        const char *name;
-        struct clk *parent;
-
-        spinlock_t lock;
-        unsigned long rate;
-        bool reset;
-        __u16 clk_val;
-        __s8 usecount;
-        void __iomem * res_reg;
-        __u16 res_mask;
-
-        bool hw_ctrld;
-
-        void (*recalc) (struct clk *);
-        int (*set_rate) (struct clk *, unsigned long);
-        unsigned long (*get_rate) (struct clk *);
-        unsigned long (*round_rate) (struct clk *, unsigned long);
-        void (*init) (struct clk *);
-        void (*enable) (struct clk *);
-        void (*disable) (struct clk *);
-};
-
-int u300_clock_init(void);
-
-#endif
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 33339745d43..03acf1883ec 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -30,6 +30,7 @@
 #include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinconf-generic.h>
 #include <linux/dma-mapping.h>
+#include <linux/platform_data/clk-u300.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -44,7 +45,6 @@
 #include <mach/dma_channels.h>
 #include <mach/gpio-u300.h>
 
-#include "clock.h"
 #include "spi.h"
 #include "i2c.h"
 #include "u300-gpio.h"
@@ -1658,12 +1658,20 @@ void __init u300_init_irq(void)
         int i;
 
         /* initialize clocking early, we want to clock the INTCON */
-        u300_clock_init();
+        u300_clk_init(U300_SYSCON_VBASE);
+
+        /* Bootstrap EMIF and SEMI clocks */
+        clk = clk_get_sys("pl172", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+        clk = clk_get_sys("semi", NULL);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
 
         /* Clock the interrupt controller */
         clk = clk_get_sys("intcon", NULL);
         BUG_ON(IS_ERR(clk));
-        clk_enable(clk);
+        clk_prepare_enable(clk);
 
         for (i = 0; i < U300_VIC_IRQS_END; i++)
                 set_bit(i, (unsigned long *) &mask[0]);
@@ -1811,13 +1819,6 @@ void __init u300_init_devices(void)
         /* Check what platform we run and print some status information */
         u300_init_check_chip();
 
-        /* Set system to run at PLL208, max performance, a known state. */
-        val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
-        writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-        /* Wait for the PLL208 to lock if not locked in yet */
-        while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
-                 U300_SYSCON_CSR_PLL208_LOCK_IND));
         /* Initialize SPI device with some board specifics */
         u300_spi_init(&pl022_device);
 
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index bc1c7897e82..56ac06d38ec 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -354,7 +354,7 @@ static void __init u300_timer_init(void)
         /* Clock the interrupt controller */
         clk = clk_get_sys("apptimer", NULL);
         BUG_ON(IS_ERR(clk));
-        clk_enable(clk);
+        clk_prepare_enable(clk);
         rate = clk_get_rate(clk);
 
         setup_sched_clock(u300_read_sched_clock, 32, rate);
diff --git a/arch/arm/mach-ux500/board-mop500-msp.c b/arch/arm/mach-ux500/board-mop500-msp.c
index 99604803874..df15646036a 100644
--- a/arch/arm/mach-ux500/board-mop500-msp.c
+++ b/arch/arm/mach-ux500/board-mop500-msp.c
@@ -191,9 +191,9 @@ static struct platform_device *db8500_add_msp_i2s(struct device *parent,
         return pdev;
 }
 
-/* Platform device for ASoC U8500 machine */
-static struct platform_device snd_soc_u8500 = {
-                .name = "snd-soc-u8500",
+/* Platform device for ASoC MOP500 machine */
+static struct platform_device snd_soc_mop500 = {
+                .name = "snd-soc-mop500",
                 .id = 0,
                 .dev = {
                         .platform_data = NULL,
@@ -227,8 +227,8 @@ int mop500_msp_init(struct device *parent)
 {
         struct platform_device *msp1;
 
-        pr_info("%s: Register platform-device 'snd-soc-u8500'.\n", __func__);
-        platform_device_register(&snd_soc_u8500);
+        pr_info("%s: Register platform-device 'snd-soc-mop500'.\n", __func__);
+        platform_device_register(&snd_soc_mop500);
 
         pr_info("Initialize MSP I2S-devices.\n");
         db8500_add_msp_i2s(parent, 0, U8500_MSP0_BASE, IRQ_DB8500_MSP0,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 920251cf834..18ff781cfbe 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -80,7 +80,7 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 };
 #endif
 
-static struct mmci_platform_data mop500_sdi0_data = {
+struct mmci_platform_data mop500_sdi0_data = {
         .ios_handler    = mop500_sdi0_ios_handler,
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 50000000,
@@ -227,7 +227,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 };
 #endif
 
-static struct mmci_platform_data mop500_sdi4_data = {
+struct mmci_platform_data mop500_sdi4_data = {
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 4fd93f5c49e..a534d8880de 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/platform_data/i2c-nomadik.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
@@ -25,6 +26,7 @@
 #include <linux/mfd/tc3589x.h>
 #include <linux/mfd/tps6105x.h>
 #include <linux/mfd/abx500/ab8500-gpio.h>
+#include <linux/mfd/abx500/ab8500-codec.h>
 #include <linux/leds-lp5521.h>
 #include <linux/input.h>
 #include <linux/smsc911x.h>
@@ -39,7 +41,6 @@
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
 
-#include <plat/i2c.h>
 #include <plat/ste_dma40.h>
 #include <plat/gpio-nomadik.h>
 
@@ -58,7 +59,7 @@
 static struct gpio_led snowball_led_array[] = {
         {
                 .name = "user_led",
-                .default_trigger = "none",
+                .default_trigger = "heartbeat",
                 .gpio = 142,
         },
 };
@@ -97,6 +98,18 @@ static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
                                         0x7A, 0x00, 0x00},
 };
 
+/* ab8500-codec */
+static struct ab8500_codec_platform_data ab8500_codec_pdata = {
+        .amics =  {
+                .mic1_type = AMIC_TYPE_DIFFERENTIAL,
+                .mic2_type = AMIC_TYPE_DIFFERENTIAL,
+                .mic1a_micbias = AMIC_MICBIAS_VAMIC1,
+                .mic1b_micbias = AMIC_MICBIAS_VAMIC1,
+                .mic2_micbias = AMIC_MICBIAS_VAMIC2
+        },
+        .ear_cmv = EAR_CMV_0_95V
+};
+
 static struct gpio_keys_button snowball_key_array[] = {
         {
                 .gpio           = 32,
@@ -195,24 +208,7 @@ static struct ab8500_platform_data ab8500_platdata = {
         .regulator      = ab8500_regulators,
         .num_regulator  = ARRAY_SIZE(ab8500_regulators),
         .gpio           = &ab8500_gpio_pdata,
-};
-
-static struct resource ab8500_resources[] = {
-        [0] = {
-                .start  = IRQ_DB8500_AB8500,
-                .end    = IRQ_DB8500_AB8500,
-                .flags  = IORESOURCE_IRQ
-        }
-};
-
-struct platform_device ab8500_device = {
-        .name = "ab8500-core",
-        .id = 0,
-        .dev = {
-                .platform_data = &ab8500_platdata,
-        },
-        .num_resources = 1,
-        .resource = ab8500_resources,
+        .codec          = &ab8500_codec_pdata,
 };
 
 /*
@@ -331,43 +327,12 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
         },
 };
 
-#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm)    \
-static struct nmk_i2c_controller u8500_i2c##id##_data = { \
-        /*                              \
-         * slave data setup time, which is      \
-         * 250 ns,100ns,10ns which is 14,6,2    \
-         * respectively for a 48 Mhz    \
-         * i2c clock                    \
-         */                             \
-        .slsu           = _slsu,        \
-        /* Tx FIFO threshold */         \
-        .tft            = _tft,         \
-        /* Rx FIFO threshold */         \
-        .rft            = _rft,         \
-        /* std. mode operation */       \
-        .clk_freq       = clk,          \
-        /* Slave response timeout(ms) */\
-        .timeout        = t_out,        \
-        .sm             = _sm,          \
-}
-
-/*
- * The board uses 4 i2c controllers, initialize all of
- * them with slave data setup time of 250 ns,
- * Tx & Rx FIFO threshold values as 8 and standard
- * mode of operation
- */
-U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
-U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
-U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
-U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
-
 static void __init mop500_i2c_init(struct device *parent)
 {
-        db8500_add_i2c0(parent, &u8500_i2c0_data);
-        db8500_add_i2c1(parent, &u8500_i2c1_data);
-        db8500_add_i2c2(parent, &u8500_i2c2_data);
-        db8500_add_i2c3(parent, &u8500_i2c3_data);
+        db8500_add_i2c0(parent, NULL);
+        db8500_add_i2c1(parent, NULL);
+        db8500_add_i2c2(parent, NULL);
+        db8500_add_i2c3(parent, NULL);
 }
 
 static struct gpio_keys_button mop500_gpio_keys[] = {
@@ -460,7 +425,6 @@ static struct hash_platform_data u8500_hash1_platform_data = {
 /* add any platform devices here - TODO */
 static struct platform_device *mop500_platform_devs[] __initdata = {
         &mop500_gpio_keys_device,
-        &ab8500_device,
 };
 
 #ifdef CONFIG_STE_DMA40
@@ -622,7 +586,6 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
         &snowball_led_dev,
         &snowball_key_dev,
         &snowball_sbnet_dev,
-        &ab8500_device,
 };
 
 static void __init mop500_init_machine(void)
@@ -634,9 +597,8 @@ static void __init mop500_init_machine(void)
         mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
 
         mop500_pinmaps_init();
-        parent = u8500_init_devices();
+        parent = u8500_init_devices(&ab8500_platdata);
 
-        /* FIXME: parent of ab8500 should be prcmu */
         for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
                 mop500_platform_devs[i]->dev.parent = parent;
 
@@ -669,7 +631,7 @@ static void __init snowball_init_machine(void)
         int i;
 
         snowball_pinmaps_init();
-        parent = u8500_init_devices();
+        parent = u8500_init_devices(&ab8500_platdata);
 
         for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
                 snowball_platform_devs[i]->dev.parent = parent;
@@ -701,7 +663,7 @@ static void __init hrefv60_init_machine(void)
         mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
 
         hrefv60_pinmaps_init();
-        parent = u8500_init_devices();
+        parent = u8500_init_devices(&ab8500_platdata);
 
         for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
                 mop500_platform_devs[i]->dev.parent = parent;
@@ -776,6 +738,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
         /* Requires DMA bindings. */
         OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
         /* Requires clock name bindings. */
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
@@ -786,6 +750,11 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
         OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
         /* Requires device name bindings. */
         OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
         {},
@@ -795,9 +764,6 @@ static const struct of_device_id u8500_local_bus_nodes[] = {
         /* only create devices below soc node */
         { .compatible = "stericsson,db8500", },
         { .compatible = "stericsson,db8500-prcmu", },
-        { .compatible = "stericsson,db8500-prcmu-regulator", },
-        { .compatible = "stericsson,ab8500", },
-        { .compatible = "stericsson,ab8500-regulator", },
         { .compatible = "simple-bus"},
         { },
 };
@@ -820,8 +786,6 @@ static void __init u8500_init_machine(void)
 
         for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
                 mop500_platform_devs[i]->dev.parent = parent;
-        for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
-                snowball_platform_devs[i]->dev.parent = parent;
 
         /* automatically probe child nodes of db8500 device */
         of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
@@ -833,6 +797,7 @@ static void __init u8500_init_machine(void)
                                 ARRAY_SIZE(mop500_platform_devs));
 
                 mop500_sdi_init(parent);
+                mop500_msp_init(parent);
                 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
                 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
                 i2c_register_board_info(2, mop500_i2c2_devices,
@@ -841,17 +806,7 @@ static void __init u8500_init_machine(void)
                 mop500_uib_init();
 
         } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-                /*
-                 * Devices to be DT:ed:
-                 *   snowball_led_dev   = todo
-                 *   snowball_key_dev   = todo
-                 *   snowball_sbnet_dev = done
-                 *   ab8500_device      = done
-                 */
-                platform_add_devices(snowball_of_platform_devs,
-                                ARRAY_SIZE(snowball_of_platform_devs));
-
-                snowball_sdi_init(parent);
+                mop500_msp_init(parent);
         } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
                 /*
                  * The HREFv60 board removed a GPIO expander and routed
@@ -863,6 +818,7 @@ static void __init u8500_init_machine(void)
                                 ARRAY_SIZE(mop500_platform_devs));
 
                 hrefv60_sdi_init(parent);
+                mop500_msp_init(parent);
 
                 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
                 i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
@@ -873,7 +829,6 @@ static void __init u8500_init_machine(void)
 
                 mop500_uib_init();
         }
-        mop500_i2c_init(parent);
 
         /* This board has full regulator constraints */
         regulator_has_full_constraints();
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 2f87b25a908..b5bfc1a78b1 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -9,6 +9,7 @@
 
 /* For NOMADIK_NR_GPIO */
 #include <mach/irqs.h>
+#include <linux/amba/mmci.h>
 
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
 #define SNOWBALL_ACCEL_INT1_GPIO        163
@@ -78,6 +79,8 @@
 
 struct device;
 struct i2c_board_info;
+extern struct mmci_platform_data mop500_sdi0_data;
+extern struct mmci_platform_data mop500_sdi4_data;
 
 extern void mop500_sdi_init(struct device *parent);
 extern void snowball_sdi_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 33275eb4c68..db3c52d56ca 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -16,6 +16,7 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/mfd/abx500/ab8500.h>
 
 #include <asm/mach/map.h>
 #include <asm/pmu.h>
@@ -115,7 +116,7 @@ static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
         return ret;
 }
 
-static struct arm_pmu_platdata db8500_pmu_platdata = {
+struct arm_pmu_platdata db8500_pmu_platdata = {
         .handle_irq             = db8500_pmu_handler,
 };
 
@@ -139,7 +140,6 @@ static struct platform_device *platform_devs[] __initdata = {
 
 static struct platform_device *of_platform_devs[] __initdata = {
         &u8500_dma40_device,
-        &db8500_pmu_device,
 };
 
 static resource_size_t __initdata db8500_gpio_base[] = {
@@ -207,7 +207,7 @@ static struct device * __init db8500_soc_device_init(void)
 /*
  * This function is called from the board init
  */
-struct device * __init u8500_init_devices(void)
+struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
 {
         struct device *parent;
         int i;
@@ -224,6 +224,8 @@ struct device * __init u8500_init_devices(void)
         for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
                 platform_devs[i]->dev.parent = parent;
 
+        db8500_prcmu_device.dev.platform_data = ab8500;
+
         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
         return parent;
@@ -237,7 +239,6 @@ struct device * __init u8500_of_init_devices(void)
 
         parent = db8500_soc_device_init();
 
-        db8500_add_rtc(parent);
         db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
 
         platform_device_register_data(parent,
@@ -249,7 +250,7 @@ struct device * __init u8500_of_init_devices(void)
         /*
          * Devices to be DT:ed:
          *   u8500_dma40_device  = todo
-         *   db8500_pmu_device   = todo
+         *   db8500_pmu_device   = done
          *   db8500_prcmu_device = done
          */
         platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs));
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index 6e470656026..ecdd8386cff 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -12,7 +12,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/sys_soc.h>
 #include <linux/amba/bus.h>
-#include <plat/i2c.h>
+#include <linux/platform_data/i2c-nomadik.h>
 #include <mach/crypto-ux500.h>
 
 struct spi_master_cntlr;
@@ -56,27 +56,15 @@ dbx500_add_uart(struct device *parent, const char *name, resource_size_t base,
 
 struct nmk_i2c_controller;
 
-static inline struct platform_device *
+static inline struct amba_device *
 dbx500_add_i2c(struct device *parent, int id, resource_size_t base, int irq,
                struct nmk_i2c_controller *data)
 {
-        struct resource res[] = {
-                DEFINE_RES_MEM(base, SZ_4K),
-                DEFINE_RES_IRQ(irq),
-        };
+        /* Conjure a name similar to what the platform device used to have */
+        char name[16];
 
-        struct platform_device_info pdevinfo = {
-                .parent = parent,
-                .name = "nmk-i2c",
-                .id = id,
-                .res = res,
-                .num_res = ARRAY_SIZE(res),
-                .data = data,
-                .size_data = sizeof(*data),
-                .dma_mask = DMA_BIT_MASK(32),
-        };
-
-        return platform_device_register_full(&pdevinfo);
+        snprintf(name, sizeof(name), "nmk-i2c.%d", id);
+        return amba_apb_device_add(parent, name, base, SZ_4K, irq, 0, data, 0);
 }
 
 static inline struct amba_device *
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 8b7ed82a286..7914e5eaa9c 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -13,11 +13,12 @@
 
 #include <asm/mach/time.h>
 #include <linux/init.h>
+#include <linux/mfd/abx500/ab8500.h>
 
 void __init ux500_map_io(void);
 extern void __init u8500_map_io(void);
 
-extern struct device * __init u8500_init_devices(void);
+extern struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500);
 
 extern void __init ux500_init_irq(void);
 extern void __init ux500_init_late(void);
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index cf8730d35e7..fc3730f0165 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -2,7 +2,8 @@ menu "Versatile Express platform type"
         depends on ARCH_VEXPRESS
 
 config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
-        bool
+        bool "Enable A5 and A9 only errata work-arounds"
+        default y
         select ARM_ERRATA_720789
         select ARM_ERRATA_751472
         select PL310_ERRATA_753970 if CACHE_PL310
@@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 
 config ARCH_VEXPRESS_CA9X4
         bool "Versatile Express Cortex-A9x4 tile"
-        select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
         select ARM_GIC
         select CPU_V7
         select HAVE_SMP
@@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4
 
 config ARCH_VEXPRESS_DT
         bool "Device Tree support for Versatile Express platforms"
-        select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
         select ARM_GIC
         select ARM_PATCH_PHYS_VIRT
         select AUTO_ZRELADDR
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 909f85ebf5f..318d308dfb9 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -6,4 +6,5 @@ initrd_phys-y	:= 0x60800000
 
 dtb-$(CONFIG_ARCH_VEXPRESS_DT)  += vexpress-v2p-ca5s.dtb \
                                    vexpress-v2p-ca9.dtb \
-                                   vexpress-v2p-ca15-tc1.dtb
+                                   vexpress-v2p-ca15-tc1.dtb \
+                                   vexpress-v2p-ca15_a7.dtb
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index c65cc3b462a..61c492403b0 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -66,8 +66,15 @@ static void __init ct_ca9x4_init_irq(void)
 
 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 {
-        v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
-        v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
+        u32 site = v2m_get_master_site();
+
+        /*
+         * Old firmware was using the "site" component of the command
+         * to control the DVI muxer (while it should be always 0 ie. MB).
+         * Newer firmware uses the data register. Keep both for compatibility.
+         */
+        v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
+        v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
 }
 
 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
@@ -105,43 +112,11 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 };
 
 
-static long ct_round(struct clk *clk, unsigned long rate)
-{
-        return rate;
-}
-
-static int ct_set(struct clk *clk, unsigned long rate)
-{
-        return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
-}
-
-static const struct clk_ops osc1_clk_ops = {
-        .round  = ct_round,
-        .set    = ct_set,
-};
-
-static struct clk osc1_clk = {
-        .ops    = &osc1_clk_ops,
-        .rate   = 24000000,
-};
-
-static struct clk ct_sp804_clk = {
-        .rate   = 1000000,
-};
-
-static struct clk_lookup lookups[] = {
-        {       /* CLCD */
-                .dev_id         = "ct:clcd",
-                .clk            = &osc1_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "ct-timer0",
-                .clk            = &ct_sp804_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "ct-timer1",
-                .clk            = &ct_sp804_clk,
-        },
+static struct v2m_osc ct_osc1 = {
+        .osc = 1,
+        .rate_min = 10000000,
+        .rate_max = 80000000,
+        .rate_default = 23750000,
 };
 
 static struct resource pmu_resources[] = {
@@ -174,14 +149,10 @@ static struct platform_device pmu_device = {
         .resource       = pmu_resources,
 };
 
-static void __init ct_ca9x4_init_early(void)
-{
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
-
 static void __init ct_ca9x4_init(void)
 {
         int i;
+        struct clk *clk;
 
 #ifdef CONFIG_CACHE_L2X0
         void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
@@ -193,6 +164,10 @@ static void __init ct_ca9x4_init(void)
         l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 #endif
 
+        ct_osc1.site = v2m_get_master_site();
+        clk = v2m_osc_register("ct:osc1", &ct_osc1);
+        clk_register_clkdev(clk, NULL, "ct:clcd");
+
         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 
@@ -234,7 +209,6 @@ struct ct_desc ct_ca9x4_desc __initdata = {
         .id             = V2M_CT_ID_CA9,
         .name           = "CA9x4",
         .map_io         = ct_ca9x4_map_io,
-        .init_early     = ct_ca9x4_init_early,
         .init_irq       = ct_ca9x4_init_irq,
         .init_tile      = ct_ca9x4_init,
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-vexpress/include/mach/clkdev.h b/arch/arm/mach-vexpress/include/mach/clkdev.h
deleted file mode 100644
index 3f8307d73ca..00000000000
--- a/arch/arm/mach-vexpress/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#include <plat/clock.h>
-
-struct clk {
-        const struct clk_ops    *ops;
-        unsigned long           rate;
-        const struct icst_params *params;
-};
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fa8224794e0..9f509f55d07 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -18,6 +18,8 @@
 
 #define DEBUG_LL_VIRT_BASE              0xf8000000
 
+#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
+
                 .macro  addruart,rp,rv,tmp
 
                 @ Make an educated guess regarding the memory map:
@@ -41,3 +43,42 @@
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
+
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
+
+                .macro  addruart,rp,rv,tmp
+                mov     \rp, #DEBUG_LL_UART_OFFSET
+                orr     \rv, \rp, #DEBUG_LL_VIRT_BASE
+                orr     \rp, \rp, #DEBUG_LL_PHYS_BASE
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
+
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
+
+                .macro  addruart,rp,rv,tmp
+                mov     \rp, #DEBUG_LL_UART_OFFSET_RS1
+                orr     \rv, \rp, #DEBUG_LL_VIRT_BASE
+                orr     \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
+
+#else /* CONFIG_DEBUG_LL_UART_NONE */
+
+                .macro  addruart, rp, rv, tmp
+                /* Safe dummy values */
+                mov     \rp, #0
+                mov     \rv, #DEBUG_LL_VIRT_BASE
+                .endm
+
+                .macro  senduart,rd,rx
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+                .endm
+
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 31a92890893..1e388c7bf4d 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -1,6 +1,8 @@
 #ifndef __MACH_MOTHERBOARD_H
 #define __MACH_MOTHERBOARD_H
 
+#include <linux/clk-provider.h>
+
 /*
  * Physical addresses, offset from V2M_PA_CS0-3
  */
@@ -104,9 +106,10 @@
 #define SYS_CFG_REBOOT          (9 << 20)
 #define SYS_CFG_DVIMODE         (11 << 20)
 #define SYS_CFG_POWER           (12 << 20)
-#define SYS_CFG_SITE_MB         (0 << 16)
-#define SYS_CFG_SITE_DB1        (1 << 16)
-#define SYS_CFG_SITE_DB2        (2 << 16)
+#define SYS_CFG_SITE(n)         ((n) << 16)
+#define SYS_CFG_SITE_MB         0
+#define SYS_CFG_SITE_DB1        1
+#define SYS_CFG_SITE_DB2        2
 #define SYS_CFG_STACK(n)        ((n) << 12)
 
 #define SYS_CFG_ERR             (1 << 1)
@@ -122,6 +125,8 @@ void v2m_flags_set(u32 data);
 #define SYS_MISC_MASTERSITE     (1 << 14)
 #define SYS_PROCIDx_HBI_MASK    0xfff
 
+int v2m_get_master_site(void);
+
 /*
  * Core tile IDs
  */
@@ -144,4 +149,21 @@ struct ct_desc {
 
 extern struct ct_desc *ct_desc;
 
+/*
+ * OSC clock provider
+ */
+struct v2m_osc {
+        struct clk_hw hw;
+        u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
+        u8 stack; /* board stack position */
+        u16 osc;
+        unsigned long rate_min;
+        unsigned long rate_max;
+        unsigned long rate_default;
+};
+
+#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
+
+struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);
+
 #endif
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7dab5596b86..1e472eb0bbd 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -27,6 +27,7 @@
 
 static unsigned long get_uart_base(void)
 {
+#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
         unsigned long mpcore_periph;
 
         /*
@@ -42,6 +43,13 @@ static unsigned long get_uart_base(void)
                 return UART_BASE;
         else
                 return UART_BASE_RS1;
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
+        return UART_BASE;
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
+        return UART_BASE_RS1;
+#else
+        return 0;
+#endif
 }
 
 /*
@@ -51,6 +59,9 @@ static inline void putc(int c)
 {
         unsigned long base = get_uart_base();
 
+        if (!base)
+                return;
+
         while (AMBA_UART_FR(base) & (1 << 5))
                 barrier();
 
@@ -61,6 +72,9 @@ static inline void flush(void)
 {
         unsigned long base = get_uart_base();
 
+        if (!base)
+                return;
+
         while (AMBA_UART_FR(base) & (1 << 3))
                 barrier();
 }
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index fde26adaef3..37608f22ee3 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -16,7 +16,10 @@
 #include <linux/spinlock.h>
 #include <linux/usb/isp1760.h>
 #include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 #include <linux/mtd/physmap.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/arch_timer.h>
 #include <asm/mach-types.h>
@@ -81,16 +84,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
         sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
 }
 
-static void __init v2m_timer_init(void)
-{
-        v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
-        v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
-}
-
-static struct sys_timer v2m_timer = {
-        .init   = v2m_timer_init,
-};
-
 
 static DEFINE_SPINLOCK(v2m_cfg_lock);
 
@@ -147,6 +140,13 @@ void __init v2m_flags_set(u32 data)
         writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
 }
 
+int v2m_get_master_site(void)
+{
+        u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
+
+        return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1;
+}
+
 
 static struct resource v2m_pcie_i2c_resource = {
         .start  = V2M_SERIAL_BUS_PCI,
@@ -201,6 +201,11 @@ static struct platform_device v2m_eth_device = {
         .dev.platform_data = &v2m_eth_config,
 };
 
+static struct regulator_consumer_supply v2m_eth_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static struct resource v2m_usb_resources[] = {
         {
                 .start  = V2M_ISP1761,
@@ -319,98 +324,145 @@ static struct amba_device *v2m_amba_devs[] __initdata = {
 };
 
 
-static long v2m_osc_round(struct clk *clk, unsigned long rate)
+static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct v2m_osc *osc = to_v2m_osc(hw);
+
+        return !parent_rate ? osc->rate_default : parent_rate;
+}
+
+static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long *parent_rate)
 {
+        struct v2m_osc *osc = to_v2m_osc(hw);
+
+        if (WARN_ON(rate < osc->rate_min))
+                rate = osc->rate_min;
+
+        if (WARN_ON(rate > osc->rate_max))
+                rate = osc->rate_max;
+
         return rate;
 }
 
-static int v2m_osc1_set(struct clk *clk, unsigned long rate)
+static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
-        return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate);
+        struct v2m_osc *osc = to_v2m_osc(hw);
+
+        v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
+                        SYS_CFG_STACK(osc->stack) | osc->osc, rate);
+
+        return 0;
 }
 
-static const struct clk_ops osc1_clk_ops = {
-        .round  = v2m_osc_round,
-        .set    = v2m_osc1_set,
-};
-
-static struct clk osc1_clk = {
-        .ops    = &osc1_clk_ops,
-        .rate   = 24000000,
-};
-
-static struct clk osc2_clk = {
-        .rate   = 24000000,
-};
-
-static struct clk v2m_sp804_clk = {
-        .rate   = 1000000,
-};
-
-static struct clk v2m_ref_clk = {
-        .rate   = 32768,
-};
-
-static struct clk dummy_apb_pclk;
-
-static struct clk_lookup v2m_lookups[] = {
-        {       /* AMBA bus clock */
-                .con_id         = "apb_pclk",
-                .clk            = &dummy_apb_pclk,
-        }, {    /* UART0 */
-                .dev_id         = "mb:uart0",
-                .clk            = &osc2_clk,
-        }, {    /* UART1 */
-                .dev_id         = "mb:uart1",
-                .clk            = &osc2_clk,
-        }, {    /* UART2 */
-                .dev_id         = "mb:uart2",
-                .clk            = &osc2_clk,
-        }, {    /* UART3 */
-                .dev_id         = "mb:uart3",
-                .clk            = &osc2_clk,
-        }, {    /* KMI0 */
-                .dev_id         = "mb:kmi0",
-                .clk            = &osc2_clk,
-        }, {    /* KMI1 */
-                .dev_id         = "mb:kmi1",
-                .clk            = &osc2_clk,
-        }, {    /* MMC0 */
-                .dev_id         = "mb:mmci",
-                .clk            = &osc2_clk,
-        }, {    /* CLCD */
-                .dev_id         = "mb:clcd",
-                .clk            = &osc1_clk,
-        }, {    /* SP805 WDT */
-                .dev_id         = "mb:wdt",
-                .clk            = &v2m_ref_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "v2m-timer0",
-                .clk            = &v2m_sp804_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "v2m-timer1",
-                .clk            = &v2m_sp804_clk,
-        },
+static struct clk_ops v2m_osc_ops = {
+        .recalc_rate = v2m_osc_recalc_rate,
+        .round_rate = v2m_osc_round_rate,
+        .set_rate = v2m_osc_set_rate,
+};
+
+struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
+{
+        struct clk_init_data init;
+
+        WARN_ON(osc->site > 2);
+        WARN_ON(osc->stack > 15);
+        WARN_ON(osc->osc > 4095);
+
+        init.name = name;
+        init.ops = &v2m_osc_ops;
+        init.flags = CLK_IS_ROOT;
+        init.num_parents = 0;
+
+        osc->hw.init = &init;
+
+        return clk_register(NULL, &osc->hw);
+}
+
+static struct v2m_osc v2m_mb_osc1 = {
+        .site = SYS_CFG_SITE_MB,
+        .osc = 1,
+        .rate_min = 23750000,
+        .rate_max = 63500000,
+        .rate_default = 23750000,
+};
+
+static const char *v2m_ref_clk_periphs[] __initconst = {
+        "mb:wdt",   "1000f000.wdt",  "1c0f0000.wdt",    /* SP805 WDT */
+};
+
+static const char *v2m_osc1_periphs[] __initconst = {
+        "mb:clcd",  "1001f000.clcd", "1c1f0000.clcd",   /* PL111 CLCD */
+};
+
+static const char *v2m_osc2_periphs[] __initconst = {
+        "mb:mmci",  "10005000.mmci", "1c050000.mmci",   /* PL180 MMCI */
+        "mb:kmi0",  "10006000.kmi",  "1c060000.kmi",    /* PL050 KMI0 */
+        "mb:kmi1",  "10007000.kmi",  "1c070000.kmi",    /* PL050 KMI1 */
+        "mb:uart0", "10009000.uart", "1c090000.uart",   /* PL011 UART0 */
+        "mb:uart1", "1000a000.uart", "1c0a0000.uart",   /* PL011 UART1 */
+        "mb:uart2", "1000b000.uart", "1c0b0000.uart",   /* PL011 UART2 */
+        "mb:uart3", "1000c000.uart", "1c0c0000.uart",   /* PL011 UART3 */
+};
+
+static void __init v2m_clk_init(void)
+{
+        struct clk *clk;
+        int i;
+
+        clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
+                        CLK_IS_ROOT, 0);
+        WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
+
+        clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
+                        CLK_IS_ROOT, 32768);
+        for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
+                WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
+
+        clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
+                        CLK_IS_ROOT, 1000000);
+        WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
+        WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
+
+        clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
+        for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
+                WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
+
+        clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
+                        CLK_IS_ROOT, 24000000);
+        for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
+                WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
+}
+
+static void __init v2m_timer_init(void)
+{
+        v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
+        v2m_clk_init();
+        v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
+}
+
+static struct sys_timer v2m_timer = {
+        .init   = v2m_timer_init,
 };
 
 static void __init v2m_init_early(void)
 {
-        ct_desc->init_early();
-        clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
+        if (ct_desc->init_early)
+                ct_desc->init_early();
         versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
 }
 
 static void v2m_power_off(void)
 {
-        if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0))
+        if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
                 printk(KERN_EMERG "Unable to shutdown\n");
 }
 
 static void v2m_restart(char str, const char *cmd)
 {
-        if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
+        if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
                 printk(KERN_EMERG "Unable to reboot\n");
 }
 
@@ -458,6 +510,9 @@ static void __init v2m_init(void)
 {
         int i;
 
+        regulator_register_fixed(0, v2m_eth_supplies,
+                        ARRAY_SIZE(v2m_eth_supplies));
+
         platform_device_register(&v2m_pcie_i2c_device);
         platform_device_register(&v2m_ddc_i2c_device);
         platform_device_register(&v2m_flash_device);
@@ -522,77 +577,6 @@ void __init v2m_dt_map_io(void)
 #endif
 }
 
-static struct clk_lookup v2m_dt_lookups[] = {
-        {       /* AMBA bus clock */
-                .con_id         = "apb_pclk",
-                .clk            = &dummy_apb_pclk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "v2m-timer0",
-                .clk            = &v2m_sp804_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "v2m-timer1",
-                .clk            = &v2m_sp804_clk,
-        }, {    /* PL180 MMCI */
-                .dev_id         = "mb:mmci", /* 10005000.mmci */
-                .clk            = &osc2_clk,
-        }, {    /* PL050 KMI0 */
-                .dev_id         = "10006000.kmi",
-                .clk            = &osc2_clk,
-        }, {    /* PL050 KMI1 */
-                .dev_id         = "10007000.kmi",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART0 */
-                .dev_id         = "10009000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART1 */
-                .dev_id         = "1000a000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART2 */
-                .dev_id         = "1000b000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART3 */
-                .dev_id         = "1000c000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* SP805 WDT */
-                .dev_id         = "1000f000.wdt",
-                .clk            = &v2m_ref_clk,
-        }, {    /* PL111 CLCD */
-                .dev_id         = "1001f000.clcd",
-                .clk            = &osc1_clk,
-        },
-        /* RS1 memory map */
-        {       /* PL180 MMCI */
-                .dev_id         = "mb:mmci", /* 1c050000.mmci */
-                .clk            = &osc2_clk,
-        }, {    /* PL050 KMI0 */
-                .dev_id         = "1c060000.kmi",
-                .clk            = &osc2_clk,
-        }, {    /* PL050 KMI1 */
-                .dev_id         = "1c070000.kmi",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART0 */
-                .dev_id         = "1c090000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART1 */
-                .dev_id         = "1c0a0000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART2 */
-                .dev_id         = "1c0b0000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART3 */
-                .dev_id         = "1c0c0000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* SP805 WDT */
-                .dev_id         = "1c0f0000.wdt",
-                .clk            = &v2m_ref_clk,
-        }, {    /* PL111 CLCD */
-                .dev_id         = "1c1f0000.clcd",
-                .clk            = &osc1_clk,
-        },
-};
-
 void __init v2m_dt_init_early(void)
 {
         struct device_node *node;
@@ -605,8 +589,8 @@ void __init v2m_dt_init_early(void)
 
         /* Confirm board type against DT property, if available */
         if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
-                u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
-                u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
+                int site = v2m_get_master_site();
+                u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ?
                                 V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
                 u32 hbi = id & SYS_PROCIDx_HBI_MASK;
 
@@ -614,8 +598,6 @@ void __init v2m_dt_init_early(void)
                         pr_warning("vexpress: DT HBI (%x) is not matching "
                                         "hardware (%x)!\n", dt_hbi, hbi);
         }
-
-        clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
 }
 
 static  struct of_device_id vexpress_irq_match[] __initdata = {
@@ -637,6 +619,8 @@ static void __init v2m_dt_timer_init(void)
         node = of_find_compatible_node(NULL, NULL, "arm,sp810");
         v2m_sysctl_init(of_iomap(node, 0));
 
+        v2m_clk_init();
+
         err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
         if (WARN_ON(err))
                 return;
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 81aedb7c893..7ce51767c99 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1,9 +1,7 @@
-obj-y += devices.o gpio.o irq.o timer.o
+obj-y += devices.o gpio.o irq.o timer.o restart.o
 
 obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o
 obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
 
 obj-$(CONFIG_MACH_BV07) += bv07.o
 obj-$(CONFIG_MACH_WM8505_7IN_NETBOOK) += wm8505_7in.o
-
-obj-$(CONFIG_HAVE_PWM) += pwm.o
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
index a464c758441..f9fbeb2d10e 100644
--- a/arch/arm/mach-vt8500/bv07.c
+++ b/arch/arm/mach-vt8500/bv07.c
@@ -23,6 +23,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <mach/restart.h>
 
 #include "devices.h"
 
@@ -62,6 +63,7 @@ void __init bv07_init(void)
         else
                 printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
 
+        wmt_setup_restart();
         vt8500_set_resources();
         platform_add_devices(devices, ARRAY_SIZE(devices));
         vt8500_gpio_init();
@@ -69,6 +71,7 @@ void __init bv07_init(void)
 
 MACHINE_START(BV07, "Benign BV07 Mini Netbook")
         .atag_offset    = 0x100,
+        .restart        = wmt_restart,
         .reserve        = vt8500_reserve_mem,
         .map_io         = vt8500_map_io,
         .init_irq       = vt8500_init_irq,
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
new file mode 100644
index 00000000000..89f9b787d2a
--- /dev/null
+++ b/arch/arm/mach-vt8500/include/mach/restart.h
@@ -0,0 +1,17 @@
+/* linux/arch/arm/mach-vt8500/restart.h
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+void wmt_setup_restart(void);
+void wmt_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/include/mach/system.h b/arch/arm/mach-vt8500/include/mach/system.h
deleted file mode 100644
index 58fa8010ee6..00000000000
--- a/arch/arm/mach-vt8500/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-vt8500/include/mach/system.h
- *
- */
-#include <asm/io.h>
-
-/* PM Software Reset request register */
-#define VT8500_PMSR_VIRT        0xf8130060
-
-static inline void arch_reset(char mode, const char *cmd)
-{
-        writel(1, VT8500_PMSR_VIRT);
-}
diff --git a/arch/arm/mach-vt8500/pwm.c b/arch/arm/mach-vt8500/pwm.c
deleted file mode 100644
index 8ad825e9359..00000000000
--- a/arch/arm/mach-vt8500/pwm.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * arch/arm/mach-vt8500/pwm.c
- *
- *  Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/pwm.h>
-#include <linux/delay.h>
-
-#include <asm/div64.h>
-
-#define VT8500_NR_PWMS 4
-
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device {
-        struct list_head        node;
-        struct platform_device  *pdev;
-
-        const char      *label;
-
-        void __iomem    *regbase;
-
-        unsigned int    use_count;
-        unsigned int    pwm_id;
-};
-
-#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
-static inline void pwm_busy_wait(void __iomem *reg, u8 bitmask)
-{
-        int loops = msecs_to_loops(10);
-        while ((readb(reg) & bitmask) && --loops)
-                cpu_relax();
-
-        if (unlikely(!loops))
-                pr_warning("Waiting for status bits 0x%x to clear timed out\n",
-                           bitmask);
-}
-
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
-{
-        unsigned long long c;
-        unsigned long period_cycles, prescale, pv, dc;
-
-        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
-                return -EINVAL;
-
-        c = 25000000/2; /* wild guess --- need to implement clocks */
-        c = c * period_ns;
-        do_div(c, 1000000000);
-        period_cycles = c;
-
-        if (period_cycles < 1)
-                period_cycles = 1;
-        prescale = (period_cycles - 1) / 4096;
-        pv = period_cycles / (prescale + 1) - 1;
-        if (pv > 4095)
-                pv = 4095;
-
-        if (prescale > 1023)
-                return -EINVAL;
-
-        c = (unsigned long long)pv * duty_ns;
-        do_div(c, period_ns);
-        dc = c;
-
-        pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 1));
-        writel(prescale, pwm->regbase + 0x4 + (pwm->pwm_id << 4));
-
-        pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 2));
-        writel(pv, pwm->regbase + 0x8 + (pwm->pwm_id << 4));
-
-        pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 3));
-        writel(dc, pwm->regbase + 0xc + (pwm->pwm_id << 4));
-
-        return 0;
-}
-EXPORT_SYMBOL(pwm_config);
-
-int pwm_enable(struct pwm_device *pwm)
-{
-        pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 0));
-        writel(5, pwm->regbase + (pwm->pwm_id << 4));
-        return 0;
-}
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-        pwm_busy_wait(pwm->regbase + 0x40 + pwm->pwm_id, (1 << 0));
-        writel(0, pwm->regbase + (pwm->pwm_id << 4));
-}
-EXPORT_SYMBOL(pwm_disable);
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-        struct pwm_device *pwm;
-        int found = 0;
-
-        mutex_lock(&pwm_lock);
-
-        list_for_each_entry(pwm, &pwm_list, node) {
-                if (pwm->pwm_id == pwm_id) {
-                        found = 1;
-                        break;
-                }
-        }
-
-        if (found) {
-                if (pwm->use_count == 0) {
-                        pwm->use_count++;
-                        pwm->label = label;
-                } else {
-                        pwm = ERR_PTR(-EBUSY);
-                }
-        } else {
-                pwm = ERR_PTR(-ENOENT);
-        }
-
-        mutex_unlock(&pwm_lock);
-        return pwm;
-}
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-        mutex_lock(&pwm_lock);
-
-        if (pwm->use_count) {
-                pwm->use_count--;
-                pwm->label = NULL;
-        } else {
-                pr_warning("PWM device already freed\n");
-        }
-
-        mutex_unlock(&pwm_lock);
-}
-EXPORT_SYMBOL(pwm_free);
-
-static inline void __add_pwm(struct pwm_device *pwm)
-{
-        mutex_lock(&pwm_lock);
-        list_add_tail(&pwm->node, &pwm_list);
-        mutex_unlock(&pwm_lock);
-}
-
-static int __devinit pwm_probe(struct platform_device *pdev)
-{
-        struct pwm_device *pwms;
-        struct resource *r;
-        int ret = 0;
-        int i;
-
-        pwms = kzalloc(sizeof(struct pwm_device) * VT8500_NR_PWMS, GFP_KERNEL);
-        if (pwms == NULL) {
-                dev_err(&pdev->dev, "failed to allocate memory\n");
-                return -ENOMEM;
-        }
-
-        for (i = 0; i < VT8500_NR_PWMS; i++) {
-                pwms[i].use_count = 0;
-                pwms[i].pwm_id = i;
-                pwms[i].pdev = pdev;
-        }
-
-        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (r == NULL) {
-                dev_err(&pdev->dev, "no memory resource defined\n");
-                ret = -ENODEV;
-                goto err_free;
-        }
-
-        r = request_mem_region(r->start, resource_size(r), pdev->name);
-        if (r == NULL) {
-                dev_err(&pdev->dev, "failed to request memory resource\n");
-                ret = -EBUSY;
-                goto err_free;
-        }
-
-        pwms[0].regbase = ioremap(r->start, resource_size(r));
-        if (pwms[0].regbase == NULL) {
-                dev_err(&pdev->dev, "failed to ioremap() registers\n");
-                ret = -ENODEV;
-                goto err_free_mem;
-        }
-
-        for (i = 1; i < VT8500_NR_PWMS; i++)
-                pwms[i].regbase = pwms[0].regbase;
-
-        for (i = 0; i < VT8500_NR_PWMS; i++)
-                __add_pwm(&pwms[i]);
-
-        platform_set_drvdata(pdev, pwms);
-        return 0;
-
-err_free_mem:
-        release_mem_region(r->start, resource_size(r));
-err_free:
-        kfree(pwms);
-        return ret;
-}
-
-static int __devexit pwm_remove(struct platform_device *pdev)
-{
-        struct pwm_device *pwms;
-        struct resource *r;
-        int i;
-
-        pwms = platform_get_drvdata(pdev);
-        if (pwms == NULL)
-                return -ENODEV;
-
-        mutex_lock(&pwm_lock);
-
-        for (i = 0; i < VT8500_NR_PWMS; i++)
-                list_del(&pwms[i].node);
-        mutex_unlock(&pwm_lock);
-
-        iounmap(pwms[0].regbase);
-
-        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        release_mem_region(r->start, resource_size(r));
-
-        kfree(pwms);
-        return 0;
-}
-
-static struct platform_driver pwm_driver = {
-        .driver         = {
-                .name   = "vt8500-pwm",
-                .owner  = THIS_MODULE,
-        },
-        .probe          = pwm_probe,
-        .remove         = __devexit_p(pwm_remove),
-};
-
-static int __init pwm_init(void)
-{
-        return platform_driver_register(&pwm_driver);
-}
-arch_initcall(pwm_init);
-
-static void __exit pwm_exit(void)
-{
-        platform_driver_unregister(&pwm_driver);
-}
-module_exit(pwm_exit);
-
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c
new file mode 100644
index 00000000000..497e89a5e13
--- /dev/null
+++ b/arch/arm/mach-vt8500/restart.c
@@ -0,0 +1,54 @@
+/* linux/arch/arm/mach-vt8500/restart.c
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <asm/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define LEGACY_PMC_BASE         0xD8130000
+#define WMT_PRIZM_PMSR_REG      0x60
+
+static void __iomem *pmc_base;
+
+void wmt_setup_restart(void)
+{
+        struct device_node *np;
+
+        /*
+         * Check if Power Mgmt Controller node is present in device tree. If no
+         * device tree node, use the legacy PMSR value (valid for all current
+         * SoCs).
+         */
+        np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc");
+        if (np) {
+                pmc_base = of_iomap(np, 0);
+
+                if (!pmc_base)
+                        pr_err("%s:of_iomap(pmc) failed\n", __func__);
+
+                of_node_put(np);
+        } else {
+                pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
+                if (!pmc_base) {
+                        pr_err("%s:ioremap(rstc) failed\n", __func__);
+                        return;
+                }
+        }
+}
+
+void wmt_restart(char mode, const char *cmd)
+{
+        if (pmc_base)
+                writel(1, pmc_base + WMT_PRIZM_PMSR_REG);
+}
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
index cf910a95608..db19886caf7 100644
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ b/arch/arm/mach-vt8500/wm8505_7in.c
@@ -23,6 +23,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <mach/restart.h>
 
 #include "devices.h"
 
@@ -61,7 +62,7 @@ void __init wm8505_7in_init(void)
                 pm_power_off = &vt8500_power_off;
         else
                 printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-
+        wmt_setup_restart();
         wm8505_set_resources();
         platform_add_devices(devices, ARRAY_SIZE(devices));
         vt8500_gpio_init();
@@ -69,6 +70,7 @@ void __init wm8505_7in_init(void)
 
 MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
         .atag_offset    = 0x100,
+        .restart        = wmt_restart,
         .reserve        = wm8505_reserve_mem,
         .map_io         = wm8505_map_io,
         .init_irq       = wm8505_init_irq,
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 806cc4f6351..119bc52ab93 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -14,6 +14,7 @@
 #include <linux/percpu.h>
 
 #include <asm/mmu_context.h>
+#include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
 
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
@@ -48,6 +49,40 @@ void cpu_set_reserved_ttbr0(void)
 }
 #endif
 
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd,
+                               void *t)
+{
+        u32 contextidr;
+        pid_t pid;
+        struct thread_info *thread = t;
+
+        if (cmd != THREAD_NOTIFY_SWITCH)
+                return NOTIFY_DONE;
+
+        pid = task_pid_nr(thread->task) << ASID_BITS;
+        asm volatile(
+        "       mrc     p15, 0, %0, c13, c0, 1\n"
+        "       bfi     %1, %0, #0, %2\n"
+        "       mcr     p15, 0, %1, c13, c0, 1\n"
+        : "=r" (contextidr), "+r" (pid)
+        : "I" (ASID_BITS));
+        isb();
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block contextidr_notifier_block = {
+        .notifier_call = contextidr_notifier,
+};
+
+static int __init contextidr_notifier_init(void)
+{
+        return thread_register_notifier(&contextidr_notifier_block);
+}
+arch_initcall(contextidr_notifier_init);
+#endif
+
 /*
  * We fork()ed a process, and we need a new context for the child
  * to run in.
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 655878bcc96..051204fc461 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -22,13 +22,14 @@
 #include <linux/memblock.h>
 #include <linux/slab.h>
 #include <linux/iommu.h>
+#include <linux/io.h>
 #include <linux/vmalloc.h>
+#include <linux/sizes.h>
 
 #include <asm/memory.h>
 #include <asm/highmem.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
-#include <asm/sizes.h>
 #include <asm/mach/arch.h>
 #include <asm/dma-iommu.h>
 #include <asm/mach/map.h>
@@ -72,7 +73,7 @@ static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
              unsigned long offset, size_t size, enum dma_data_direction dir,
              struct dma_attrs *attrs)
 {
-        if (!arch_is_coherent())
+        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                 __dma_page_cpu_to_dev(page, offset, size, dir);
         return pfn_to_dma(dev, page_to_pfn(page)) + offset;
 }
@@ -95,7 +96,7 @@ static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
                 size_t size, enum dma_data_direction dir,
                 struct dma_attrs *attrs)
 {
-        if (!arch_is_coherent())
+        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
                                       handle & ~PAGE_MASK, size, dir);
 }
@@ -124,6 +125,7 @@ struct dma_map_ops arm_dma_ops = {
         .alloc                  = arm_dma_alloc,
         .free                   = arm_dma_free,
         .mmap                   = arm_dma_mmap,
+        .get_sgtable            = arm_dma_get_sgtable,
         .map_page               = arm_dma_map_page,
         .unmap_page             = arm_dma_unmap_page,
         .map_sg                 = arm_dma_map_sg,
@@ -217,148 +219,144 @@ static void __dma_free_buffer(struct page *page, size_t size)
 }
 
 #ifdef CONFIG_MMU
+#ifdef CONFIG_HUGETLB_PAGE
+#error ARM Coherent DMA allocator does not (yet) support huge TLB
+#endif
 
-#define CONSISTENT_OFFSET(x)    (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT)
-#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT)
-
-/*
- * These are the page tables (2MB each) covering uncached, DMA consistent allocations
- */
-static pte_t **consistent_pte;
-
-#define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M
+static void *__alloc_from_contiguous(struct device *dev, size_t size,
+                                     pgprot_t prot, struct page **ret_page);
 
-static unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE;
+static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
+                                 pgprot_t prot, struct page **ret_page,
+                                 const void *caller);
 
-void __init init_consistent_dma_size(unsigned long size)
+static void *
+__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
+        const void *caller)
 {
-        unsigned long base = CONSISTENT_END - ALIGN(size, SZ_2M);
+        struct vm_struct *area;
+        unsigned long addr;
 
-        BUG_ON(consistent_pte); /* Check we're called before DMA region init */
-        BUG_ON(base < VMALLOC_END);
+        /*
+         * DMA allocation can be mapped to user space, so lets
+         * set VM_USERMAP flags too.
+         */
+        area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
+                                  caller);
+        if (!area)
+                return NULL;
+        addr = (unsigned long)area->addr;
+        area->phys_addr = __pfn_to_phys(page_to_pfn(page));
 
-        /* Grow region to accommodate specified size  */
-        if (base < consistent_base)
-                consistent_base = base;
+        if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
+                vunmap((void *)addr);
+                return NULL;
+        }
+        return (void *)addr;
 }
 
-#include "vmregion.h"
-
-static struct arm_vmregion_head consistent_head = {
-        .vm_lock        = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock),
-        .vm_list        = LIST_HEAD_INIT(consistent_head.vm_list),
-        .vm_end         = CONSISTENT_END,
-};
-
-#ifdef CONFIG_HUGETLB_PAGE
-#error ARM Coherent DMA allocator does not (yet) support huge TLB
-#endif
-
-/*
- * Initialise the consistent memory allocation.
- */
-static int __init consistent_init(void)
+static void __dma_free_remap(void *cpu_addr, size_t size)
 {
-        int ret = 0;
-        pgd_t *pgd;
-        pud_t *pud;
-        pmd_t *pmd;
-        pte_t *pte;
-        int i = 0;
-        unsigned long base = consistent_base;
-        unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT;
-
-        if (IS_ENABLED(CONFIG_CMA) && !IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU))
-                return 0;
-
-        consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL);
-        if (!consistent_pte) {
-                pr_err("%s: no memory\n", __func__);
-                return -ENOMEM;
+        unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
+        struct vm_struct *area = find_vm_area(cpu_addr);
+        if (!area || (area->flags & flags) != flags) {
+                WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
+                return;
         }
-
-        pr_debug("DMA memory: 0x%08lx - 0x%08lx:\n", base, CONSISTENT_END);
-        consistent_head.vm_start = base;
-
-        do {
-                pgd = pgd_offset(&init_mm, base);
-
-                pud = pud_alloc(&init_mm, pgd, base);
-                if (!pud) {
-                        pr_err("%s: no pud tables\n", __func__);
-                        ret = -ENOMEM;
-                        break;
-                }
-
-                pmd = pmd_alloc(&init_mm, pud, base);
-                if (!pmd) {
-                        pr_err("%s: no pmd tables\n", __func__);
-                        ret = -ENOMEM;
-                        break;
-                }
-                WARN_ON(!pmd_none(*pmd));
-
-                pte = pte_alloc_kernel(pmd, base);
-                if (!pte) {
-                        pr_err("%s: no pte tables\n", __func__);
-                        ret = -ENOMEM;
-                        break;
-                }
-
-                consistent_pte[i++] = pte;
-                base += PMD_SIZE;
-        } while (base < CONSISTENT_END);
-
-        return ret;
+        unmap_kernel_range((unsigned long)cpu_addr, size);
+        vunmap(cpu_addr);
 }
-core_initcall(consistent_init);
 
-static void *__alloc_from_contiguous(struct device *dev, size_t size,
-                                     pgprot_t prot, struct page **ret_page);
+#define DEFAULT_DMA_COHERENT_POOL_SIZE  SZ_256K
 
-static struct arm_vmregion_head coherent_head = {
-        .vm_lock        = __SPIN_LOCK_UNLOCKED(&coherent_head.vm_lock),
-        .vm_list        = LIST_HEAD_INIT(coherent_head.vm_list),
+struct dma_pool {
+        size_t size;
+        spinlock_t lock;
+        unsigned long *bitmap;
+        unsigned long nr_pages;
+        void *vaddr;
+        struct page **pages;
 };
 
-static size_t coherent_pool_size = DEFAULT_CONSISTENT_DMA_SIZE / 8;
+static struct dma_pool atomic_pool = {
+        .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
+};
 
 static int __init early_coherent_pool(char *p)
 {
-        coherent_pool_size = memparse(p, &p);
+        atomic_pool.size = memparse(p, &p);
         return 0;
 }
 early_param("coherent_pool", early_coherent_pool);
 
+void __init init_dma_coherent_pool_size(unsigned long size)
+{
+        /*
+         * Catch any attempt to set the pool size too late.
+         */
+        BUG_ON(atomic_pool.vaddr);
+
+        /*
+         * Set architecture specific coherent pool size only if
+         * it has not been changed by kernel command line parameter.
+         */
+        if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
+                atomic_pool.size = size;
+}
+
 /*
  * Initialise the coherent pool for atomic allocations.
  */
-static int __init coherent_init(void)
+static int __init atomic_pool_init(void)
 {
+        struct dma_pool *pool = &atomic_pool;
         pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
-        size_t size = coherent_pool_size;
+        unsigned long nr_pages = pool->size >> PAGE_SHIFT;
+        unsigned long *bitmap;
         struct page *page;
+        struct page **pages;
         void *ptr;
+        int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
 
-        if (!IS_ENABLED(CONFIG_CMA))
-                return 0;
+        bitmap = kzalloc(bitmap_size, GFP_KERNEL);
+        if (!bitmap)
+                goto no_bitmap;
+
+        pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
+        if (!pages)
+                goto no_pages;
 
-        ptr = __alloc_from_contiguous(NULL, size, prot, &page);
+        if (IS_ENABLED(CONFIG_CMA))
+                ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page);
+        else
+                ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot,
+                                           &page, NULL);
         if (ptr) {
-                coherent_head.vm_start = (unsigned long) ptr;
-                coherent_head.vm_end = (unsigned long) ptr + size;
-                printk(KERN_INFO "DMA: preallocated %u KiB pool for atomic coherent allocations\n",
-                       (unsigned)size / 1024);
+                int i;
+
+                for (i = 0; i < nr_pages; i++)
+                        pages[i] = page + i;
+
+                spin_lock_init(&pool->lock);
+                pool->vaddr = ptr;
+                pool->pages = pages;
+                pool->bitmap = bitmap;
+                pool->nr_pages = nr_pages;
+                pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
+                       (unsigned)pool->size / 1024);
                 return 0;
         }
-        printk(KERN_ERR "DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
-               (unsigned)size / 1024);
+no_pages:
+        kfree(bitmap);
+no_bitmap:
+        pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
+               (unsigned)pool->size / 1024);
         return -ENOMEM;
 }
 /*
  * CMA is activated by core_initcall, so we must be called after it.
  */
-postcore_initcall(coherent_init);
+postcore_initcall(atomic_pool_init);
 
 struct dma_contig_early_reserve {
         phys_addr_t base;
@@ -388,7 +386,7 @@ void __init dma_contiguous_remap(void)
                 if (end > arm_lowmem_limit)
                         end = arm_lowmem_limit;
                 if (start >= end)
-                        return;
+                        continue;
 
                 map.pfn = __phys_to_pfn(start);
                 map.virtual = __phys_to_virt(start);
@@ -406,112 +404,6 @@ void __init dma_contiguous_remap(void)
         }
 }
 
-static void *
-__dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
-        const void *caller)
-{
-        struct arm_vmregion *c;
-        size_t align;
-        int bit;
-
-        if (!consistent_pte) {
-                pr_err("%s: not initialised\n", __func__);
-                dump_stack();
-                return NULL;
-        }
-
-        /*
-         * Align the virtual region allocation - maximum alignment is
-         * a section size, minimum is a page size.  This helps reduce
-         * fragmentation of the DMA space, and also prevents allocations
-         * smaller than a section from crossing a section boundary.
-         */
-        bit = fls(size - 1);
-        if (bit > SECTION_SHIFT)
-                bit = SECTION_SHIFT;
-        align = 1 << bit;
-
-        /*
-         * Allocate a virtual address in the consistent mapping region.
-         */
-        c = arm_vmregion_alloc(&consistent_head, align, size,
-                            gfp & ~(__GFP_DMA | __GFP_HIGHMEM), caller);
-        if (c) {
-                pte_t *pte;
-                int idx = CONSISTENT_PTE_INDEX(c->vm_start);
-                u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
-
-                pte = consistent_pte[idx] + off;
-                c->priv = page;
-
-                do {
-                        BUG_ON(!pte_none(*pte));
-
-                        set_pte_ext(pte, mk_pte(page, prot), 0);
-                        page++;
-                        pte++;
-                        off++;
-                        if (off >= PTRS_PER_PTE) {
-                                off = 0;
-                                pte = consistent_pte[++idx];
-                        }
-                } while (size -= PAGE_SIZE);
-
-                dsb();
-
-                return (void *)c->vm_start;
-        }
-        return NULL;
-}
-
-static void __dma_free_remap(void *cpu_addr, size_t size)
-{
-        struct arm_vmregion *c;
-        unsigned long addr;
-        pte_t *ptep;
-        int idx;
-        u32 off;
-
-        c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr);
-        if (!c) {
-                pr_err("%s: trying to free invalid coherent area: %p\n",
-                       __func__, cpu_addr);
-                dump_stack();
-                return;
-        }
-
-        if ((c->vm_end - c->vm_start) != size) {
-                pr_err("%s: freeing wrong coherent size (%ld != %d)\n",
-                       __func__, c->vm_end - c->vm_start, size);
-                dump_stack();
-                size = c->vm_end - c->vm_start;
-        }
-
-        idx = CONSISTENT_PTE_INDEX(c->vm_start);
-        off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
-        ptep = consistent_pte[idx] + off;
-        addr = c->vm_start;
-        do {
-                pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep);
-
-                ptep++;
-                addr += PAGE_SIZE;
-                off++;
-                if (off >= PTRS_PER_PTE) {
-                        off = 0;
-                        ptep = consistent_pte[++idx];
-                }
-
-                if (pte_none(pte) || !pte_present(pte))
-                        pr_crit("%s: bad page in kernel page table\n",
-                                __func__);
-        } while (size -= PAGE_SIZE);
-
-        flush_tlb_kernel_range(c->vm_start, c->vm_end);
-
-        arm_vmregion_free(&consistent_head, c);
-}
-
 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
                             void *data)
 {
@@ -552,16 +444,17 @@ static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
         return ptr;
 }
 
-static void *__alloc_from_pool(struct device *dev, size_t size,
-                               struct page **ret_page, const void *caller)
+static void *__alloc_from_pool(size_t size, struct page **ret_page)
 {
-        struct arm_vmregion *c;
-        size_t align;
+        struct dma_pool *pool = &atomic_pool;
+        unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
+        unsigned int pageno;
+        unsigned long flags;
+        void *ptr = NULL;
+        unsigned long align_mask;
 
-        if (!coherent_head.vm_start) {
-                printk(KERN_ERR "%s: coherent pool not initialised!\n",
-                       __func__);
-                dump_stack();
+        if (!pool->vaddr) {
+                WARN(1, "coherent pool not initialised!\n");
                 return NULL;
         }
 
@@ -570,36 +463,60 @@ static void *__alloc_from_pool(struct device *dev, size_t size,
          * small, so align them to their order in pages, minimum is a page
          * size. This helps reduce fragmentation of the DMA space.
          */
-        align = PAGE_SIZE << get_order(size);
-        c = arm_vmregion_alloc(&coherent_head, align, size, 0, caller);
-        if (c) {
-                void *ptr = (void *)c->vm_start;
-                struct page *page = virt_to_page(ptr);
-                *ret_page = page;
-                return ptr;
+        align_mask = (1 << get_order(size)) - 1;
+
+        spin_lock_irqsave(&pool->lock, flags);
+        pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
+                                            0, count, align_mask);
+        if (pageno < pool->nr_pages) {
+                bitmap_set(pool->bitmap, pageno, count);
+                ptr = pool->vaddr + PAGE_SIZE * pageno;
+                *ret_page = pool->pages[pageno];
+        } else {
+                pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
+                            "Please increase it with coherent_pool= kernel parameter!\n",
+                            (unsigned)pool->size / 1024);
         }
-        return NULL;
+        spin_unlock_irqrestore(&pool->lock, flags);
+
+        return ptr;
+}
+
+static bool __in_atomic_pool(void *start, size_t size)
+{
+        struct dma_pool *pool = &atomic_pool;
+        void *end = start + size;
+        void *pool_start = pool->vaddr;
+        void *pool_end = pool->vaddr + pool->size;
+
+        if (start < pool_start || start > pool_end)
+                return false;
+
+        if (end <= pool_end)
+                return true;
+
+        WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
+             start, end - 1, pool_start, pool_end - 1);
+
+        return false;
 }
 
-static int __free_from_pool(void *cpu_addr, size_t size)
+static int __free_from_pool(void *start, size_t size)
 {
-        unsigned long start = (unsigned long)cpu_addr;
-        unsigned long end = start + size;
-        struct arm_vmregion *c;
+        struct dma_pool *pool = &atomic_pool;
+        unsigned long pageno, count;
+        unsigned long flags;
 
-        if (start < coherent_head.vm_start || end > coherent_head.vm_end)
+        if (!__in_atomic_pool(start, size))
                 return 0;
 
-        c = arm_vmregion_find_remove(&coherent_head, (unsigned long)start);
+        pageno = (start - pool->vaddr) >> PAGE_SHIFT;
+        count = size >> PAGE_SHIFT;
 
-        if ((c->vm_end - c->vm_start) != size) {
-                printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n",
-                       __func__, c->vm_end - c->vm_start, size);
-                dump_stack();
-                size = c->vm_end - c->vm_start;
-        }
+        spin_lock_irqsave(&pool->lock, flags);
+        bitmap_clear(pool->bitmap, pageno, count);
+        spin_unlock_irqrestore(&pool->lock, flags);
 
-        arm_vmregion_free(&coherent_head, c);
         return 1;
 }
 
@@ -644,7 +561,7 @@ static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
 
 #define __get_dma_pgprot(attrs, prot)   __pgprot(0)
 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c)      NULL
-#define __alloc_from_pool(dev, size, ret_page, c)               NULL
+#define __alloc_from_pool(size, ret_page)                       NULL
 #define __alloc_from_contiguous(dev, size, prot, ret)           NULL
 #define __free_from_pool(cpu_addr, size)                        0
 #define __free_from_contiguous(dev, page, size)                 do { } while (0)
@@ -702,10 +619,10 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
 
         if (arch_is_coherent() || nommu())
                 addr = __alloc_simple_buffer(dev, size, gfp, &page);
+        else if (gfp & GFP_ATOMIC)
+                addr = __alloc_from_pool(size, &page);
         else if (!IS_ENABLED(CONFIG_CMA))
                 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
-        else if (gfp & GFP_ATOMIC)
-                addr = __alloc_from_pool(dev, size, &page, caller);
         else
                 addr = __alloc_from_contiguous(dev, size, prot, &page);
 
@@ -741,16 +658,22 @@ int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
 {
         int ret = -ENXIO;
 #ifdef CONFIG_MMU
+        unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
+        unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
         unsigned long pfn = dma_to_pfn(dev, dma_addr);
+        unsigned long off = vma->vm_pgoff;
+
         vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
 
         if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
                 return ret;
 
-        ret = remap_pfn_range(vma, vma->vm_start,
-                              pfn + vma->vm_pgoff,
-                              vma->vm_end - vma->vm_start,
-                              vma->vm_page_prot);
+        if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
+                ret = remap_pfn_range(vma, vma->vm_start,
+                                      pfn + off,
+                                      vma->vm_end - vma->vm_start,
+                                      vma->vm_page_prot);
+        }
 #endif  /* CONFIG_MMU */
 
         return ret;
@@ -771,12 +694,12 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
 
         if (arch_is_coherent() || nommu()) {
                 __dma_free_buffer(page, size);
+        } else if (__free_from_pool(cpu_addr, size)) {
+                return;
         } else if (!IS_ENABLED(CONFIG_CMA)) {
                 __dma_free_remap(cpu_addr, size);
                 __dma_free_buffer(page, size);
         } else {
-                if (__free_from_pool(cpu_addr, size))
-                        return;
                 /*
                  * Non-atomic allocations cannot be freed with IRQs disabled
                  */
@@ -785,6 +708,21 @@ void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
         }
 }
 
+int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
+                 void *cpu_addr, dma_addr_t handle, size_t size,
+                 struct dma_attrs *attrs)
+{
+        struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
+        int ret;
+
+        ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
+        if (unlikely(ret))
+                return ret;
+
+        sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
+        return 0;
+}
+
 static void dma_cache_maint_page(struct page *page, unsigned long offset,
         size_t size, enum dma_data_direction dir,
         void (*op)(const void *, size_t, int))
@@ -998,9 +936,6 @@ static int arm_dma_set_mask(struct device *dev, u64 dma_mask)
 
 static int __init dma_debug_do_init(void)
 {
-#ifdef CONFIG_MMU
-        arm_vmregion_create_proc("dma-mappings", &consistent_head);
-#endif
         dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
         return 0;
 }
@@ -1088,7 +1023,7 @@ static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t
 
         return pages;
 error:
-        while (--i)
+        while (i--)
                 if (pages[i])
                         __free_pages(pages[i], 0);
         if (array_size <= PAGE_SIZE)
@@ -1117,61 +1052,32 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s
  * Create a CPU mapping for a specified pages
  */
 static void *
-__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot)
+__iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
+                    const void *caller)
 {
-        struct arm_vmregion *c;
-        size_t align;
-        size_t count = size >> PAGE_SHIFT;
-        int bit;
+        unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
+        struct vm_struct *area;
+        unsigned long p;
 
-        if (!consistent_pte[0]) {
-                pr_err("%s: not initialised\n", __func__);
-                dump_stack();
+        area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
+                                  caller);
+        if (!area)
                 return NULL;
-        }
 
-        /*
-         * Align the virtual region allocation - maximum alignment is
-         * a section size, minimum is a page size.  This helps reduce
-         * fragmentation of the DMA space, and also prevents allocations
-         * smaller than a section from crossing a section boundary.
-         */
-        bit = fls(size - 1);
-        if (bit > SECTION_SHIFT)
-                bit = SECTION_SHIFT;
-        align = 1 << bit;
+        area->pages = pages;
+        area->nr_pages = nr_pages;
+        p = (unsigned long)area->addr;
 
-        /*
-         * Allocate a virtual address in the consistent mapping region.
-         */
-        c = arm_vmregion_alloc(&consistent_head, align, size,
-                            gfp & ~(__GFP_DMA | __GFP_HIGHMEM), NULL);
-        if (c) {
-                pte_t *pte;
-                int idx = CONSISTENT_PTE_INDEX(c->vm_start);
-                int i = 0;
-                u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
-
-                pte = consistent_pte[idx] + off;
-                c->priv = pages;
-
-                do {
-                        BUG_ON(!pte_none(*pte));
-
-                        set_pte_ext(pte, mk_pte(pages[i], prot), 0);
-                        pte++;
-                        off++;
-                        i++;
-                        if (off >= PTRS_PER_PTE) {
-                                off = 0;
-                                pte = consistent_pte[++idx];
-                        }
-                } while (i < count);
-
-                dsb();
-
-                return (void *)c->vm_start;
+        for (i = 0; i < nr_pages; i++) {
+                phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
+                if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
+                        goto err;
+                p += PAGE_SIZE;
         }
+        return area->addr;
+err:
+        unmap_kernel_range((unsigned long)area->addr, size);
+        vunmap(area->addr);
         return NULL;
 }
 
@@ -1230,6 +1136,59 @@ static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t si
         return 0;
 }
 
+static struct page **__atomic_get_pages(void *addr)
+{
+        struct dma_pool *pool = &atomic_pool;
+        struct page **pages = pool->pages;
+        int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
+
+        return pages + offs;
+}
+
+static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
+{
+        struct vm_struct *area;
+
+        if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
+                return __atomic_get_pages(cpu_addr);
+
+        if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
+                return cpu_addr;
+
+        area = find_vm_area(cpu_addr);
+        if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
+                return area->pages;
+        return NULL;
+}
+
+static void *__iommu_alloc_atomic(struct device *dev, size_t size,
+                                  dma_addr_t *handle)
+{
+        struct page *page;
+        void *addr;
+
+        addr = __alloc_from_pool(size, &page);
+        if (!addr)
+                return NULL;
+
+        *handle = __iommu_create_mapping(dev, &page, size);
+        if (*handle == DMA_ERROR_CODE)
+                goto err_mapping;
+
+        return addr;
+
+err_mapping:
+        __free_from_pool(addr, size);
+        return NULL;
+}
+
+static void __iommu_free_atomic(struct device *dev, struct page **pages,
+                                dma_addr_t handle, size_t size)
+{
+        __iommu_remove_mapping(dev, handle, size);
+        __free_from_pool(page_address(pages[0]), size);
+}
+
 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
             dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
 {
@@ -1240,6 +1199,9 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
         *handle = DMA_ERROR_CODE;
         size = PAGE_ALIGN(size);
 
+        if (gfp & GFP_ATOMIC)
+                return __iommu_alloc_atomic(dev, size, handle);
+
         pages = __iommu_alloc_buffer(dev, size, gfp);
         if (!pages)
                 return NULL;
@@ -1248,7 +1210,11 @@ static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
         if (*handle == DMA_ERROR_CODE)
                 goto err_buffer;
 
-        addr = __iommu_alloc_remap(pages, size, gfp, prot);
+        if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
+                return pages;
+
+        addr = __iommu_alloc_remap(pages, size, gfp, prot,
+                                   __builtin_return_address(0));
         if (!addr)
                 goto err_mapping;
 
@@ -1265,31 +1231,25 @@ static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
                     void *cpu_addr, dma_addr_t dma_addr, size_t size,
                     struct dma_attrs *attrs)
 {
-        struct arm_vmregion *c;
+        unsigned long uaddr = vma->vm_start;
+        unsigned long usize = vma->vm_end - vma->vm_start;
+        struct page **pages = __iommu_get_pages(cpu_addr, attrs);
 
         vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
-        c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
-
-        if (c) {
-                struct page **pages = c->priv;
-
-                unsigned long uaddr = vma->vm_start;
-                unsigned long usize = vma->vm_end - vma->vm_start;
-                int i = 0;
 
-                do {
-                        int ret;
+        if (!pages)
+                return -ENXIO;
 
-                        ret = vm_insert_page(vma, uaddr, pages[i++]);
-                        if (ret) {
-                                pr_err("Remapping memory, error: %d\n", ret);
-                                return ret;
-                        }
+        do {
+                int ret = vm_insert_page(vma, uaddr, *pages++);
+                if (ret) {
+                        pr_err("Remapping memory failed: %d\n", ret);
+                        return ret;
+                }
+                uaddr += PAGE_SIZE;
+                usize -= PAGE_SIZE;
+        } while (usize > 0);
 
-                        uaddr += PAGE_SIZE;
-                        usize -= PAGE_SIZE;
-                } while (usize > 0);
-        }
         return 0;
 }
 
@@ -1300,16 +1260,40 @@ static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
                           dma_addr_t handle, struct dma_attrs *attrs)
 {
-        struct arm_vmregion *c;
+        struct page **pages = __iommu_get_pages(cpu_addr, attrs);
         size = PAGE_ALIGN(size);
 
-        c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
-        if (c) {
-                struct page **pages = c->priv;
-                __dma_free_remap(cpu_addr, size);
-                __iommu_remove_mapping(dev, handle, size);
-                __iommu_free_buffer(dev, pages, size);
+        if (!pages) {
+                WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
+                return;
         }
+
+        if (__in_atomic_pool(cpu_addr, size)) {
+                __iommu_free_atomic(dev, pages, handle, size);
+                return;
+        }
+
+        if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
+                unmap_kernel_range((unsigned long)cpu_addr, size);
+                vunmap(cpu_addr);
+        }
+
+        __iommu_remove_mapping(dev, handle, size);
+        __iommu_free_buffer(dev, pages, size);
+}
+
+static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
+                                 void *cpu_addr, dma_addr_t dma_addr,
+                                 size_t size, struct dma_attrs *attrs)
+{
+        unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
+        struct page **pages = __iommu_get_pages(cpu_addr, attrs);
+
+        if (!pages)
+                return -ENXIO;
+
+        return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
+                                         GFP_KERNEL);
 }
 
 /*
@@ -1317,7 +1301,7 @@ void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
  */
 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
                           size_t size, dma_addr_t *handle,
-                          enum dma_data_direction dir)
+                          enum dma_data_direction dir, struct dma_attrs *attrs)
 {
         struct dma_iommu_mapping *mapping = dev->archdata.mapping;
         dma_addr_t iova, iova_base;
@@ -1336,7 +1320,8 @@ static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
                 phys_addr_t phys = page_to_phys(sg_page(s));
                 unsigned int len = PAGE_ALIGN(s->offset + s->length);
 
-                if (!arch_is_coherent())
+                if (!arch_is_coherent() &&
+                    !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                         __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
 
                 ret = iommu_map(mapping->domain, iova, phys, len, 0);
@@ -1383,7 +1368,7 @@ int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 
                 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
                         if (__map_sg_chunk(dev, start, size, &dma->dma_address,
-                            dir) < 0)
+                            dir, attrs) < 0)
                                 goto bad_mapping;
 
                         dma->dma_address += offset;
@@ -1396,7 +1381,7 @@ int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
                 }
                 size += s->length;
         }
-        if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir) < 0)
+        if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs) < 0)
                 goto bad_mapping;
 
         dma->dma_address += offset;
@@ -1430,7 +1415,8 @@ void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
                 if (sg_dma_len(s))
                         __iommu_remove_mapping(dev, sg_dma_address(s),
                                                sg_dma_len(s));
-                if (!arch_is_coherent())
+                if (!arch_is_coherent() &&
+                    !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                         __dma_page_dev_to_cpu(sg_page(s), s->offset,
                                               s->length, dir);
         }
@@ -1492,7 +1478,7 @@ static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
         dma_addr_t dma_addr;
         int ret, len = PAGE_ALIGN(size + offset);
 
-        if (!arch_is_coherent())
+        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                 __dma_page_cpu_to_dev(page, offset, size, dir);
 
         dma_addr = __alloc_iova(mapping, len);
@@ -1531,7 +1517,7 @@ static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
         if (!iova)
                 return;
 
-        if (!arch_is_coherent())
+        if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
                 __dma_page_dev_to_cpu(page, offset, size, dir);
 
         iommu_unmap(mapping->domain, iova, len);
@@ -1571,6 +1557,7 @@ struct dma_map_ops iommu_ops = {
         .alloc          = arm_iommu_alloc_attrs,
         .free           = arm_iommu_free_attrs,
         .mmap           = arm_iommu_mmap_attrs,
+        .get_sgtable    = arm_iommu_get_sgtable,
 
         .map_page               = arm_iommu_map_page,
         .unmap_page             = arm_iommu_unmap_page,
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 77458548e03..40ca11ed6e5 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -231,8 +231,6 @@ void __sync_icache_dcache(pte_t pteval)
         struct page *page;
         struct address_space *mapping;
 
-        if (!pte_present_user(pteval))
-                return;
         if (cache_is_vipt_nonaliasing() && !pte_exec(pteval))
                 /* only flush non-aliasing VIPT caches for exec mappings */
                 return;
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index f54d5921976..9aec41fa80a 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -21,13 +21,13 @@
 #include <linux/gfp.h>
 #include <linux/memblock.h>
 #include <linux/dma-contiguous.h>
+#include <linux/sizes.h>
 
 #include <asm/mach-types.h>
 #include <asm/memblock.h>
 #include <asm/prom.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
-#include <asm/sizes.h>
 #include <asm/tlb.h>
 #include <asm/fixmap.h>
 
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 4f55f5062ab..566750fa57d 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -25,6 +25,7 @@
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
 #include <linux/io.h>
+#include <linux/sizes.h>
 
 #include <asm/cp15.h>
 #include <asm/cputype.h>
@@ -32,7 +33,6 @@
 #include <asm/mmu_context.h>
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
-#include <asm/sizes.h>
 #include <asm/system_info.h>
 
 #include <asm/mach/map.h>
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 2e8a1efdf7b..6776160618e 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -59,6 +59,9 @@ extern void __flush_dcache_page(struct address_space *mapping, struct page *page
 #define VM_ARM_MTYPE(mt)                ((mt) << 20)
 #define VM_ARM_MTYPE_MASK       (0x1f << 20)
 
+/* consistent regions used by dma_alloc_attrs() */
+#define VM_ARM_DMA_CONSISTENT   0x20000000
+
 #endif
 
 #ifdef CONFIG_ZONE_DMA
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cf4528d5177..4c2d0451e84 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -16,13 +16,13 @@
 #include <linux/memblock.h>
 #include <linux/fs.h>
 #include <linux/vmalloc.h>
+#include <linux/sizes.h>
 
 #include <asm/cp15.h>
 #include <asm/cputype.h>
 #include <asm/sections.h>
 #include <asm/cachetype.h>
 #include <asm/setup.h>
-#include <asm/sizes.h>
 #include <asm/smp_plat.h>
 #include <asm/tlb.h>
 #include <asm/highmem.h>
@@ -422,12 +422,6 @@ static void __init build_mem_type_table(void)
         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 
         /*
-         * Only use write-through for non-SMP systems
-         */
-        if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
-                vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
-
-        /*
          * Enable CPU-specific coherency if supported.
          * (Only available on XSC3 at the moment.)
          */
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 5900cd520e8..86b8b480634 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -107,6 +107,12 @@ ENTRY(cpu_v6_switch_mm)
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
         mcr     p15, 0, r2, c7, c10, 4          @ drain write buffer
         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+        mrc     p15, 0, r2, c13, c0, 1          @ read current context ID
+        bic     r2, r2, #0xff                   @ extract the PID
+        and     r1, r1, #0xff
+        orr     r1, r1, r2                      @ insert into new context ID
+#endif
         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
 #endif
         mov     pc, lr
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 42ac069c801..fd045e70639 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -46,6 +46,11 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_ARM_ERRATA_430973
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 #endif
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+        mrc     p15, 0, r2, c13, c0, 1          @ read current context ID
+        lsr     r2, r2, #8                      @ extract the PID
+        bfi     r1, r2, #8, #24                 @ insert into new context ID
+#endif
 #ifdef CONFIG_ARM_ERRATA_754322
         dsb
 #endif
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index 845f461f8ec..ea94765acf9 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -39,10 +39,18 @@ ENTRY(v7wbi_flush_user_tlb_range)
         mov     r0, r0, lsr #PAGE_SHIFT         @ align address
         mov     r1, r1, lsr #PAGE_SHIFT
         asid    r3, r3                          @ mask ASID
+#ifdef CONFIG_ARM_ERRATA_720789
+        ALT_SMP(W(mov)  r3, #0  )
+        ALT_UP(W(nop)           )
+#endif
         orr     r0, r3, r0, lsl #PAGE_SHIFT     @ Create initial MVA
         mov     r1, r1, lsl #PAGE_SHIFT
 1:
+#ifdef CONFIG_ARM_ERRATA_720789
+        ALT_SMP(mcr     p15, 0, r0, c8, c3, 3)  @ TLB invalidate U MVA all ASID (shareable)
+#else
         ALT_SMP(mcr     p15, 0, r0, c8, c3, 1)  @ TLB invalidate U MVA (shareable)
+#endif
         ALT_UP(mcr      p15, 0, r0, c8, c7, 1)  @ TLB invalidate U MVA
 
         add     r0, r0, #PAGE_SZ
@@ -67,7 +75,11 @@ ENTRY(v7wbi_flush_kern_tlb_range)
         mov     r0, r0, lsl #PAGE_SHIFT
         mov     r1, r1, lsl #PAGE_SHIFT
 1:
+#ifdef CONFIG_ARM_ERRATA_720789
+        ALT_SMP(mcr     p15, 0, r0, c8, c3, 3)  @ TLB invalidate U MVA all ASID (shareable)
+#else
         ALT_SMP(mcr     p15, 0, r0, c8, c3, 1)  @ TLB invalidate U MVA (shareable)
+#endif
         ALT_UP(mcr      p15, 0, r0, c8, c7, 1)  @ TLB invalidate U MVA
         add     r0, r0, #PAGE_SZ
         cmp     r0, r1
diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
index 4e0a371630b..99c63d4b6af 100644
--- a/arch/arm/oprofile/common.c
+++ b/arch/arm/oprofile/common.c
@@ -23,26 +23,37 @@
 #include <asm/ptrace.h>
 
 #ifdef CONFIG_HW_PERF_EVENTS
+
+/*
+ * OProfile has a curious naming scheme for the ARM PMUs, but they are
+ * part of the user ABI so we need to map from the perf PMU name for
+ * supported PMUs.
+ */
+static struct op_perf_name {
+        char *perf_name;
+        char *op_name;
+} op_perf_name_map[] = {
+        { "xscale1",            "arm/xscale1"   },
+        { "xscale1",            "arm/xscale2"   },
+        { "v6",                 "arm/armv6"     },
+        { "v6mpcore",           "arm/mpcore"    },
+        { "ARMv7 Cortex-A8",    "arm/armv7"     },
+        { "ARMv7 Cortex-A9",    "arm/armv7-ca9" },
+};
+
 char *op_name_from_perf_id(void)
 {
-        enum arm_perf_pmu_ids id = armpmu_get_pmu_id();
-
-        switch (id) {
-        case ARM_PERF_PMU_ID_XSCALE1:
-                return "arm/xscale1";
-        case ARM_PERF_PMU_ID_XSCALE2:
-                return "arm/xscale2";
-        case ARM_PERF_PMU_ID_V6:
-                return "arm/armv6";
-        case ARM_PERF_PMU_ID_V6MP:
-                return "arm/mpcore";
-        case ARM_PERF_PMU_ID_CA8:
-                return "arm/armv7";
-        case ARM_PERF_PMU_ID_CA9:
-                return "arm/armv7-ca9";
-        default:
-                return NULL;
+        int i;
+        struct op_perf_name names;
+        const char *perf_name = perf_pmu_name();
+
+        for (i = 0; i < ARRAY_SIZE(op_perf_name_map); ++i) {
+                names = op_perf_name_map[i];
+                if (!strcmp(names.perf_name, perf_name))
+                        return names.op_name;
         }
+
+        return NULL;
 }
 #endif
 
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index 5cac2c540f4..5c10ad05df7 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -12,9 +12,11 @@
 
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/module.h>
 #include <linux/smsc911x.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
@@ -48,27 +50,22 @@
 /* CPU ID and Personality ID */
 #define MCU_BOARD_ID_REG        0x68
 
-#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_GPIO(irq)    ((irq) - MXC_INTERNAL_IRQS)
-
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
 #define MXC_MAX_EXP_IO_LINES    16
 
 /* interrupts like external uart , external ethernet etc*/
-#define EXPIO_INT_ENET          (MXC_BOARD_IRQ_START + 0)
-#define EXPIO_INT_XUART_A       (MXC_BOARD_IRQ_START + 1)
-#define EXPIO_INT_XUART_B       (MXC_BOARD_IRQ_START + 2)
-#define EXPIO_INT_BUTTON_A      (MXC_BOARD_IRQ_START + 3)
-#define EXPIO_INT_BUTTON_B      (MXC_BOARD_IRQ_START + 4)
+#define EXPIO_INT_ENET          0
+#define EXPIO_INT_XUART_A       1
+#define EXPIO_INT_XUART_B       2
+#define EXPIO_INT_BUTTON_A      3
+#define EXPIO_INT_BUTTON_B      4
 
 static void __iomem *brd_io;
+static struct irq_domain *domain;
 
 static struct resource smsc911x_resources[] = {
         {
                 .flags = IORESOURCE_MEM,
         } , {
-                .start = EXPIO_INT_ENET,
-                .end = EXPIO_INT_ENET,
                 .flags = IORESOURCE_IRQ,
         },
 };
@@ -100,11 +97,11 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
         imr_val = __raw_readw(brd_io + INTR_MASK_REG);
         int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
 
-        expio_irq = MXC_BOARD_IRQ_START;
+        expio_irq = 0;
         for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
                 if ((int_valid & 1) == 0)
                         continue;
-                generic_handle_irq(expio_irq);
+                generic_handle_irq(irq_find_mapping(domain, expio_irq));
         }
 
         desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -118,7 +115,7 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
 static void expio_mask_irq(struct irq_data *d)
 {
         u16 reg;
-        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+        u32 expio = d->hwirq;
 
         reg = __raw_readw(brd_io + INTR_MASK_REG);
         reg |= (1 << expio);
@@ -127,7 +124,7 @@ static void expio_mask_irq(struct irq_data *d)
 
 static void expio_ack_irq(struct irq_data *d)
 {
-        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+        u32 expio = d->hwirq;
 
         __raw_writew(1 << expio, brd_io + INTR_RESET_REG);
         __raw_writew(0, brd_io + INTR_RESET_REG);
@@ -137,7 +134,7 @@ static void expio_ack_irq(struct irq_data *d)
 static void expio_unmask_irq(struct irq_data *d)
 {
         u16 reg;
-        u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+        u32 expio = d->hwirq;
 
         reg = __raw_readw(brd_io + INTR_MASK_REG);
         reg &= ~(1 << expio);
@@ -155,8 +152,10 @@ static struct regulator_consumer_supply dummy_supplies[] = {
         REGULATOR_SUPPLY("vddvario", "smsc911x"),
 };
 
-int __init mxc_expio_init(u32 base, u32 p_irq)
+int __init mxc_expio_init(u32 base, u32 intr_gpio)
 {
+        u32 p_irq = gpio_to_irq(intr_gpio);
+        int irq_base;
         int i;
 
         brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
@@ -178,16 +177,23 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
         /*
          * Configure INT line as GPIO input
          */
-        gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
-        gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
+        gpio_request(intr_gpio, "expio_pirq");
+        gpio_direction_input(intr_gpio);
 
         /* disable the interrupt and clear the status */
         __raw_writew(0, brd_io + INTR_MASK_REG);
         __raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
         __raw_writew(0, brd_io + INTR_RESET_REG);
         __raw_writew(0x1F, brd_io + INTR_MASK_REG);
-        for (i = MXC_EXP_IO_BASE;
-             i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+
+        irq_base = irq_alloc_descs(-1, 0, MXC_MAX_EXP_IO_LINES, numa_node_id());
+        WARN_ON(irq_base < 0);
+
+        domain = irq_domain_add_legacy(NULL, MXC_MAX_EXP_IO_LINES, irq_base, 0,
+                                       &irq_domain_simple_ops, NULL);
+        WARN_ON(!domain);
+
+        for (i = irq_base; i < irq_base + MXC_MAX_EXP_IO_LINES; i++) {
                 irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
@@ -199,6 +205,8 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
 
         smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
         smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
+        smsc911x_resources[1].start = irq_find_mapping(domain, EXPIO_INT_ENET);
+        smsc911x_resources[1].end = irq_find_mapping(domain, EXPIO_INT_ENET);
         platform_device_register(&smsc_lan9217_device);
 
         return 0;
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index c722f9ce691..baf9064c084 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -47,12 +47,6 @@ config MXC_TZIC
 config MXC_AVIC
         bool
 
-config MXC_PWM
-        tristate "Enable PWM driver"
-        select HAVE_PWM
-        help
-          Enable support for the i.MX PWM controller(s).
-
 config MXC_DEBUG_BOARD
         bool "Enable MXC debug board(for 3-stack)"
         help
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index e81290c27c6..6ac72003115 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -11,11 +11,11 @@ obj-$(CONFIG_MXC_AVIC) += avic.o
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
-obj-$(CONFIG_MXC_PWM)  += pwm.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
+obj-$(CONFIG_CPU_IDLE) += cpuidle.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 689f81f9593..cbd55c36def 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -19,11 +19,14 @@
 
 #include <linux/module.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <linux/of.h>
 #include <mach/common.h>
 #include <asm/mach/irq.h>
 #include <asm/exception.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 
 #include "irq-common.h"
 
@@ -50,15 +53,19 @@
 #define AVIC_NUM_IRQS 64
 
 void __iomem *avic_base;
+static struct irq_domain *domain;
 
 static u32 avic_saved_mask_reg[2];
 
 #ifdef CONFIG_MXC_IRQ_PRIOR
 static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
 {
+        struct irq_data *d = irq_get_irq_data(irq);
         unsigned int temp;
         unsigned int mask = 0x0F << irq % 8 * 4;
 
+        irq = d->hwirq;
+
         if (irq >= AVIC_NUM_IRQS)
                 return -EINVAL;
 
@@ -75,8 +82,11 @@ static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
 #ifdef CONFIG_FIQ
 static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
 {
+        struct irq_data *d = irq_get_irq_data(irq);
         unsigned int irqt;
 
+        irq = d->hwirq;
+
         if (irq >= AVIC_NUM_IRQS)
                 return -EINVAL;
 
@@ -108,7 +118,7 @@ static void avic_irq_suspend(struct irq_data *d)
 {
         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
         struct irq_chip_type *ct = gc->chip_types;
-        int idx = gc->irq_base >> 5;
+        int idx = d->hwirq >> 5;
 
         avic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);
         __raw_writel(gc->wake_active, avic_base + ct->regs.mask);
@@ -118,7 +128,7 @@ static void avic_irq_resume(struct irq_data *d)
 {
         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
         struct irq_chip_type *ct = gc->chip_types;
-        int idx = gc->irq_base >> 5;
+        int idx = d->hwirq >> 5;
 
         __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);
 }
@@ -128,11 +138,10 @@ static void avic_irq_resume(struct irq_data *d)
 #define avic_irq_resume NULL
 #endif
 
-static __init void avic_init_gc(unsigned int irq_start)
+static __init void avic_init_gc(int idx, unsigned int irq_start)
 {
         struct irq_chip_generic *gc;
         struct irq_chip_type *ct;
-        int idx = irq_start >> 5;
 
         gc = irq_alloc_generic_chip("mxc-avic", 1, irq_start, avic_base,
                                     handle_level_irq);
@@ -161,7 +170,7 @@ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
                 if (nivector == 0xffff)
                         break;
 
-                handle_IRQ(nivector, regs);
+                handle_IRQ(irq_find_mapping(domain, nivector), regs);
         } while (1);
 }
 
@@ -172,6 +181,8 @@ asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
  */
 void __init mxc_init_irq(void __iomem *irqbase)
 {
+        struct device_node *np;
+        int irq_base;
         int i;
 
         avic_base = irqbase;
@@ -190,8 +201,16 @@ void __init mxc_init_irq(void __iomem *irqbase)
         __raw_writel(0, avic_base + AVIC_INTTYPEH);
         __raw_writel(0, avic_base + AVIC_INTTYPEL);
 
-        for (i = 0; i < AVIC_NUM_IRQS; i += 32)
-                avic_init_gc(i);
+        irq_base = irq_alloc_descs(-1, 0, AVIC_NUM_IRQS, numa_node_id());
+        WARN_ON(irq_base < 0);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,avic");
+        domain = irq_domain_add_legacy(np, AVIC_NUM_IRQS, irq_base, 0,
+                                       &irq_domain_simple_ops, NULL);
+        WARN_ON(!domain);
+
+        for (i = 0; i < AVIC_NUM_IRQS / 32; i++, irq_base += 32)
+                avic_init_gc(i, irq_base);
 
         /* Set default priority value (0) for all IRQ's */
         for (i = 0; i < 8; i++)
@@ -199,7 +218,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
 
 #ifdef CONFIG_FIQ
         /* Initialize FIQ */
-        init_FIQ();
+        init_FIQ(FIQ_START);
 #endif
 
         printk(KERN_INFO "MXC IRQ initialized\n");
diff --git a/arch/arm/plat-mxc/cpuidle.c b/arch/arm/plat-mxc/cpuidle.c
new file mode 100644
index 00000000000..d4cb511a44a
--- /dev/null
+++ b/arch/arm/plat-mxc/cpuidle.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/cpuidle.h>
+#include <linux/err.h>
+#include <linux/hrtimer.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+static struct cpuidle_device __percpu * imx_cpuidle_devices;
+
+static void __init imx_cpuidle_devices_uninit(void)
+{
+        int cpu_id;
+        struct cpuidle_device *dev;
+
+        for_each_possible_cpu(cpu_id) {
+                dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
+                cpuidle_unregister_device(dev);
+        }
+
+        free_percpu(imx_cpuidle_devices);
+}
+
+int __init imx_cpuidle_init(struct cpuidle_driver *drv)
+{
+        struct cpuidle_device *dev;
+        int cpu_id, ret;
+
+        if (drv->state_count > CPUIDLE_STATE_MAX) {
+                pr_err("%s: state_count exceeds maximum\n", __func__);
+                return -EINVAL;
+        }
+
+        ret = cpuidle_register_driver(drv);
+        if (ret) {
+                pr_err("%s: Failed to register cpuidle driver with error: %d\n",
+                         __func__, ret);
+                return ret;
+        }
+
+        imx_cpuidle_devices = alloc_percpu(struct cpuidle_device);
+        if (imx_cpuidle_devices == NULL) {
+                ret = -ENOMEM;
+                goto unregister_drv;
+        }
+
+        /* initialize state data for each cpuidle_device */
+        for_each_possible_cpu(cpu_id) {
+                dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
+                dev->cpu = cpu_id;
+                dev->state_count = drv->state_count;
+
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("%s: Failed to register cpu %u, error: %d\n",
+                                __func__, cpu_id, ret);
+                        goto uninit;
+                }
+        }
+
+        return 0;
+
+uninit:
+        imx_cpuidle_devices_uninit();
+
+unregister_drv:
+        cpuidle_unregister_driver(drv);
+        return ret;
+}
diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c
index 79d340ae0af..d1e33cc6f12 100644
--- a/arch/arm/plat-mxc/devices/platform-ipu-core.c
+++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c
@@ -30,8 +30,7 @@ const struct imx_ipu_core_data imx35_ipu_core_data __initconst =
 static struct platform_device *imx_ipu_coredev __initdata;
 
 struct platform_device *__init imx_add_ipu_core(
-                const struct imx_ipu_core_data *data,
-                const struct ipu_platform_data *pdata)
+                const struct imx_ipu_core_data *data)
 {
         /* The resource order is important! */
         struct resource res[] = {
@@ -55,7 +54,7 @@ struct platform_device *__init imx_add_ipu_core(
         };
 
         return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1,
-                        res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+                        res, ARRAY_SIZE(res), NULL, 0);
 }
 
 struct platform_device *__init imx_alloc_mx3_camera(
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
index 16d0ec4df5f..a5c9ad5721c 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
@@ -20,6 +20,11 @@ const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst =
         imx_mxc_rtc_data_entry_single(MX31);
 #endif /* ifdef CONFIG_SOC_IMX31 */
 
+#ifdef CONFIG_SOC_IMX35
+const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst =
+        imx_mxc_rtc_data_entry_single(MX35);
+#endif /* ifdef CONFIG_SOC_IMX35 */
+
 struct platform_device *__init imx_add_mxc_rtc(
                 const struct imx_mxc_rtc_data *data)
 {
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 9bfae8bd5b8..9c50c14c8f9 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -95,7 +95,7 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
 #ifdef CONFIG_SOC_IMX53
 /* i.mx53 has the i.mx35 type cspi */
 const struct imx_spi_imx_data imx53_cspi_data __initconst =
-        imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 0, , SZ_4K);
+        imx_spi_imx_data_entry_single(MX53, CSPI, "imx35-cspi", 2, , SZ_4K);
 
 /* i.mx53 has the i.mx51 type ecspi */
 const struct imx_spi_imx_data imx53_ecspi_data[] __initconst = {
diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
index a384fdd49c6..9fd6cb3f8fa 100644
--- a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
+++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
@@ -13,6 +13,6 @@
 #ifndef __ASM_ARCH_MXC_3DS_DB_H__
 #define __ASM_ARCH_MXC_3DS_DB_H__
 
-extern int __init mxc_expio_init(u32 base, u32 p_irq);
+extern int __init mxc_expio_init(u32 base, u32 intr_gpio);
 
 #endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index e429ca1b814..7128e971041 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -54,6 +54,7 @@ extern void imx50_soc_init(void);
 extern void imx51_soc_init(void);
 extern void imx53_soc_init(void);
 extern void imx51_init_late(void);
+extern void imx53_init_late(void);
 extern void epit_timer_init(void __iomem *base, int irq);
 extern void mxc_timer_init(void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
@@ -67,6 +68,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
 extern int mx27_clocks_init_dt(void);
+extern int mx31_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
 extern int mx6q_clocks_init(void);
@@ -95,7 +97,6 @@ enum mx3_cpu_pwr_mode {
 };
 
 extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
-extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
 extern void imx_print_silicon_rev(const char *cpu, int srev);
 
 void avic_handle_irq(struct pt_regs *);
@@ -146,8 +147,12 @@ extern void imx6q_clock_map_io(void);
 
 #ifdef CONFIG_PM
 extern void imx6q_pm_init(void);
+extern void imx51_pm_init(void);
+extern void imx53_pm_init(void);
 #else
 static inline void imx6q_pm_init(void) {}
+static inline void imx51_pm_init(void) {}
+static inline void imx53_pm_init(void) {}
 #endif
 
 #ifdef CONFIG_NEON
diff --git a/arch/arm/plat-mxc/include/mach/cpuidle.h b/arch/arm/plat-mxc/include/mach/cpuidle.h
new file mode 100644
index 00000000000..bc932d1af37
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/cpuidle.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/cpuidle.h>
+
+#ifdef CONFIG_CPU_IDLE
+extern int imx_cpuidle_init(struct cpuidle_driver *drv);
+#else
+static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
+{
+        return -ENODEV;
+}
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 1b2258daa05..a7f5bb1084d 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -183,7 +183,6 @@ struct platform_device *__init imx_add_imx_udc(
                 const struct imx_imx_udc_data *data,
                 const struct imxusb_platform_data *pdata);
 
-#include <mach/ipu.h>
 #include <mach/mx3fb.h>
 #include <mach/mx3_camera.h>
 struct imx_ipu_core_data {
@@ -192,8 +191,7 @@ struct imx_ipu_core_data {
         resource_size_t errirq;
 };
 struct platform_device *__init imx_add_ipu_core(
-                const struct imx_ipu_core_data *data,
-                const struct ipu_platform_data *pdata);
+                const struct imx_ipu_core_data *data);
 struct platform_device *__init imx_alloc_mx3_camera(
                 const struct imx_ipu_core_data *data,
                 const struct mx3_camera_pdata *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 0630513554d..ebf10654bb4 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -50,7 +50,7 @@
  *      IO      0x00200000+0x100000     ->      0xf4000000+0x100000
  * mx21:
  *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
- *      SAHB1   0x80000000+0x100000     ->      0xf4000000+0x100000
+ *      SAHB1   0x80000000+0x100000     ->      0xf5000000+0x100000
  *      X_MEMC  0xdf000000+0x004000     ->      0xf5f00000+0x004000
  * mx25:
  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
@@ -58,47 +58,50 @@
  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
  * mx27:
  *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
- *      SAHB1   0x80000000+0x100000     ->      0xf4000000+0x100000
+ *      SAHB1   0x80000000+0x100000     ->      0xf5000000+0x100000
  *      X_MEMC  0xd8000000+0x100000     ->      0xf5c00000+0x100000
  * mx31:
  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
  *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
- *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  * mx35:
  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
  *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
- *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  * mx50:
  *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
- *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
  * mx51:
- *      TZIC    0xe0000000+0x004000     ->      0xf5000000+0x004000
+ *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
  *      IRAM    0x1ffe0000+0x020000     ->      0xf4fe0000+0x020000
+ *      DEBUG   0x60000000+0x100000     ->      0xf5000000+0x100000
  *      SPBA0   0x70000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x73f00000+0x100000     ->      0xf5700000+0x100000
- *      AIPS2   0x83f00000+0x100000     ->      0xf4300000+0x100000
+ *      AIPS2   0x83f00000+0x100000     ->      0xf5300000+0x100000
  * mx53:
  *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
+ *      DEBUG   0x40000000+0x100000     ->      0xf5000000+0x100000
  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
  * mx6q:
- *      SCU     0x00a00000+0x001000     ->      0xf4000000+0x001000
+ *      SCU     0x00a00000+0x004000     ->      0xf4000000+0x004000
  *      CCM     0x020c4000+0x004000     ->      0xf42c4000+0x004000
- *      ANATOP  0x020c8000+0x001000     ->      0xf42c8000+0x001000
+ *      ANATOP  0x020c8000+0x004000     ->      0xf42c8000+0x004000
  *      UART4   0x021f0000+0x004000     ->      0xf42f0000+0x004000
  */
 #define IMX_IO_P2V(x)   (                                               \
-                        0xf4000000 +                                    \
+                        (((x) & 0x80000000) >> 7) |                     \
+                        (0xf4000000 +                                   \
                         (((x) & 0x50000000) >> 6) +                     \
                         (((x) & 0x0b000000) >> 4) +                     \
-                        (((x) & 0x000fffff)))
+                        (((x) & 0x000fffff))))
 
 #define IMX_IO_ADDRESS(x)       IOMEM(IMX_IO_P2V(x))
 
@@ -128,6 +131,4 @@
 /* range e.g. GPIO_1_5 is gpio 5 under linux */
 #define IMX_GPIO_NR(bank, nr)           (((bank) - 1) * 32 + (nr))
 
-#define IMX_GPIO_TO_IRQ(gpio)   (MXC_GPIO_IRQ_START + (gpio))
-
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/i2c.h b/arch/arm/plat-mxc/include/mach/i2c.h
index 375cdd0cf87..8289d915e61 100644
--- a/arch/arm/plat-mxc/include/mach/i2c.h
+++ b/arch/arm/plat-mxc/include/mach/i2c.h
@@ -15,7 +15,7 @@
  *
  **/
 struct imxi2c_platform_data {
-        int bitrate;
+        u32 bitrate;
 };
 
 #endif /* __ASM_ARCH_I2C_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 63f22a009a6..d8b65b51f2a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -160,9 +160,6 @@ int mxc_iomux_mode(unsigned int pin_mode);
 
 #define IOMUX_TO_GPIO(iomux_pin) \
         ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
-#define IOMUX_TO_IRQ(iomux_pin) \
-        (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
-        MXC_GPIO_IRQ_START)
 
 /*
  * This enumeration is constructed based on the Section
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 36c8989d9de..2623e7a2e19 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -107,11 +107,13 @@
 #define MX51_PAD_EIM_D25__UART2_CTS             IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
 #define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
 #define MX51_PAD_EIM_D25__USBOTG_DATA1          IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__GPT_CMPOUT1           IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D26__EIM_D26               IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D26__KEY_COL7              IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART2_RTS             IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
 #define MX51_PAD_EIM_D26__USBOTG_DATA2          IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__GPT_CMPOUT2           IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D27__AUD6_RXC              IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D27__EIM_D27               IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D27__GPIO2_9               IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
@@ -228,6 +230,7 @@
 #define MX51_PAD_EIM_CRE__EIM_CRE               IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_CRE__GPIO3_2               IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__CCM_CLKO             IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_WE_B__GPIO3_3            IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_WE_B__NANDF_WE_B         IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_WE_B__PATA_DIOW          IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
@@ -256,12 +259,14 @@
 #define MX51_PAD_NANDF_RB1__GPIO3_9             IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__NANDF_RB1           IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__PATA_IORDY          IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2         IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__SD4_CMD             IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__DISP2_WAIT          IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
 #define MX51_PAD_NANDF_RB2__GPIO3_10            IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__NANDF_RB2           IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3         IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__USBH3_H3_DP         IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__USBH3_NXT           IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB3__DISP1_WAIT          IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
@@ -637,7 +642,9 @@
 #define MX51_PAD_DISP1_DAT23__DISP2_DAT17       IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS      IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK     IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN15__DI1_PIN15           IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DI_GP2__DISP1_SER_CLK          IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DI_GP2__DISP2_WAIT             IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
 #define MX51_PAD_DI_GP3__CSI1_DATA_EN           IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
@@ -780,6 +787,8 @@
 #define MX51_PAD_GPIO1_2__PWM1_PWMO             IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__GPIO1_3               IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__I2C2_SDA              IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__CCM_CLKO2             IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__GPT_CLKIN             IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__PLL2_BYP              IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__PWM2_PWMO             IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
@@ -788,13 +797,16 @@
 #define MX51_PAD_GPIO1_4__EIM_RDY               IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_4__GPIO1_4               IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__GPT_CAPIN1            IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__CSI2_MCLK             IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__DISP2_PIN16           IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__GPIO1_5               IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__CCM_CLKO              IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_6__DISP2_PIN17           IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_6__GPIO1_6               IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_6__REF_EN_B              IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPT_CAPIN2            IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__CCM_OUT_0             IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__GPIO1_7               IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__SD2_WP                IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
@@ -803,11 +815,13 @@
 #define MX51_PAD_GPIO1_8__GPIO1_8               IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_8__SD2_CD                IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 #define MX51_PAD_GPIO1_8__USBH3_PWR             IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__CCM_CLKO2             IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__CCM_OUT_1             IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__DISP2_D1_CS           IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__DISP2_SER_CS          IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__GPIO1_9               IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__SD2_LCTL              IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__USBH3_OC              IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__CCM_CLKO              IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index f7d18046c04..02651a40fe2 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -85,13 +85,6 @@
 #define GPIO_BOUT_0     (2 << GPIO_BOUT_SHIFT)
 #define GPIO_BOUT_1     (3 << GPIO_BOUT_SHIFT)
 
-#define IRQ_GPIOA(x)  (MXC_GPIO_IRQ_START + x)
-#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
-#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
-#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
-#define IRQ_GPIOE(x)  (IRQ_GPIOD(32) + x)
-#define IRQ_GPIOF(x)  (IRQ_GPIOE(32) + x)
-
 extern int mxc_gpio_mode(int gpio_mode);
 extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
                 const char *label);
diff --git a/arch/arm/plat-mxc/include/mach/ipu.h b/arch/arm/plat-mxc/include/mach/ipu.h
index a9221f1cc1a..539e559d18b 100644
--- a/arch/arm/plat-mxc/include/mach/ipu.h
+++ b/arch/arm/plat-mxc/include/mach/ipu.h
@@ -110,10 +110,6 @@ enum ipu_rotate_mode {
         IPU_ROTATE_90_LEFT = 7,
 };
 
-struct ipu_platform_data {
-        unsigned int    irq_base;
-};
-
 /*
  * Enumeration of DI ports for ADC.
  */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index fd9efb04465..d73f5e8ea9c 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -11,50 +11,6 @@
 #ifndef __ASM_ARCH_MXC_IRQS_H__
 #define __ASM_ARCH_MXC_IRQS_H__
 
-#include <asm-generic/gpio.h>
-
-/*
- * SoCs with GIC interrupt controller have 160 IRQs, those with TZIC
- * have 128 IRQs, and those with AVIC have 64.
- *
- * To support single image, the biggest number should be defined on
- * top of the list.
- */
-#if defined CONFIG_ARM_GIC
-#define MXC_INTERNAL_IRQS       160
-#elif defined CONFIG_MXC_TZIC
-#define MXC_INTERNAL_IRQS       128
-#else
-#define MXC_INTERNAL_IRQS       64
-#endif
-
-#define MXC_GPIO_IRQ_START      MXC_INTERNAL_IRQS
-
-/*
- * The next 16 interrupts are for board specific purposes.  Since
- * the kernel can only run on one machine at a time, we can re-use
- * these.  If you need more, increase MXC_BOARD_IRQS, but keep it
- * within sensible limits.
- */
-#define MXC_BOARD_IRQ_START     (MXC_INTERNAL_IRQS + ARCH_NR_GPIOS)
-
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
-#define MXC_BOARD_IRQS  80
-#else
-#define MXC_BOARD_IRQS  16
-#endif
-
-#define MXC_IPU_IRQ_START       (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
-
-#ifdef CONFIG_MX3_IPU_IRQS
-#define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
-#else
-#define MX3_IPU_IRQS 0
-#endif
-/* REVISIT: Add IPU irqs on IMX51 */
-
-#define NR_IRQS                 (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
-
 extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
 
 /* all normal IRQs can be FIQs */
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 2b7c08d13e8..45bd31cc34d 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -78,61 +78,62 @@
 #define MX1_IO_ADDRESS(x)               IOMEM(MX1_IO_P2V(x))
 
 /* fixed interrput numbers */
-#define MX1_INT_SOFTINT         0
-#define MX1_INT_CSI             6
-#define MX1_DSPA_MAC_INT        7
-#define MX1_DSPA_INT            8
-#define MX1_COMP_INT            9
-#define MX1_MSHC_XINT           10
-#define MX1_GPIO_INT_PORTA      11
-#define MX1_GPIO_INT_PORTB      12
-#define MX1_GPIO_INT_PORTC      13
-#define MX1_INT_LCDC            14
-#define MX1_SIM_INT             15
-#define MX1_SIM_DATA_INT        16
-#define MX1_RTC_INT             17
-#define MX1_RTC_SAMINT          18
-#define MX1_INT_UART2PFERR      19
-#define MX1_INT_UART2RTS        20
-#define MX1_INT_UART2DTR        21
-#define MX1_INT_UART2UARTC      22
-#define MX1_INT_UART2TX         23
-#define MX1_INT_UART2RX         24
-#define MX1_INT_UART1PFERR      25
-#define MX1_INT_UART1RTS        26
-#define MX1_INT_UART1DTR        27
-#define MX1_INT_UART1UARTC      28
-#define MX1_INT_UART1TX         29
-#define MX1_INT_UART1RX         30
-#define MX1_VOICE_DAC_INT       31
-#define MX1_VOICE_ADC_INT       32
-#define MX1_PEN_DATA_INT        33
-#define MX1_PWM_INT             34
-#define MX1_SDHC_INT            35
-#define MX1_INT_I2C             39
-#define MX1_INT_CSPI2           40
-#define MX1_INT_CSPI1           41
-#define MX1_SSI_TX_INT          42
-#define MX1_SSI_TX_ERR_INT      43
-#define MX1_SSI_RX_INT          44
-#define MX1_SSI_RX_ERR_INT      45
-#define MX1_TOUCH_INT           46
-#define MX1_INT_USBD0           47
-#define MX1_INT_USBD1           48
-#define MX1_INT_USBD2           49
-#define MX1_INT_USBD3           50
-#define MX1_INT_USBD4           51
-#define MX1_INT_USBD5           52
-#define MX1_INT_USBD6           53
-#define MX1_BTSYS_INT           55
-#define MX1_BTTIM_INT           56
-#define MX1_BTWUI_INT           57
-#define MX1_TIM2_INT            58
-#define MX1_TIM1_INT            59
-#define MX1_DMA_ERR             60
-#define MX1_DMA_INT             61
-#define MX1_GPIO_INT_PORTD      62
-#define MX1_WDT_INT             63
+#include <asm/irq.h>
+#define MX1_INT_SOFTINT         (NR_IRQS_LEGACY + 0)
+#define MX1_INT_CSI             (NR_IRQS_LEGACY + 6)
+#define MX1_DSPA_MAC_INT        (NR_IRQS_LEGACY + 7)
+#define MX1_DSPA_INT            (NR_IRQS_LEGACY + 8)
+#define MX1_COMP_INT            (NR_IRQS_LEGACY + 9)
+#define MX1_MSHC_XINT           (NR_IRQS_LEGACY + 10)
+#define MX1_GPIO_INT_PORTA      (NR_IRQS_LEGACY + 11)
+#define MX1_GPIO_INT_PORTB      (NR_IRQS_LEGACY + 12)
+#define MX1_GPIO_INT_PORTC      (NR_IRQS_LEGACY + 13)
+#define MX1_INT_LCDC            (NR_IRQS_LEGACY + 14)
+#define MX1_SIM_INT             (NR_IRQS_LEGACY + 15)
+#define MX1_SIM_DATA_INT        (NR_IRQS_LEGACY + 16)
+#define MX1_RTC_INT             (NR_IRQS_LEGACY + 17)
+#define MX1_RTC_SAMINT          (NR_IRQS_LEGACY + 18)
+#define MX1_INT_UART2PFERR      (NR_IRQS_LEGACY + 19)
+#define MX1_INT_UART2RTS        (NR_IRQS_LEGACY + 20)
+#define MX1_INT_UART2DTR        (NR_IRQS_LEGACY + 21)
+#define MX1_INT_UART2UARTC      (NR_IRQS_LEGACY + 22)
+#define MX1_INT_UART2TX         (NR_IRQS_LEGACY + 23)
+#define MX1_INT_UART2RX         (NR_IRQS_LEGACY + 24)
+#define MX1_INT_UART1PFERR      (NR_IRQS_LEGACY + 25)
+#define MX1_INT_UART1RTS        (NR_IRQS_LEGACY + 26)
+#define MX1_INT_UART1DTR        (NR_IRQS_LEGACY + 27)
+#define MX1_INT_UART1UARTC      (NR_IRQS_LEGACY + 28)
+#define MX1_INT_UART1TX         (NR_IRQS_LEGACY + 29)
+#define MX1_INT_UART1RX         (NR_IRQS_LEGACY + 30)
+#define MX1_VOICE_DAC_INT       (NR_IRQS_LEGACY + 31)
+#define MX1_VOICE_ADC_INT       (NR_IRQS_LEGACY + 32)
+#define MX1_PEN_DATA_INT        (NR_IRQS_LEGACY + 33)
+#define MX1_PWM_INT             (NR_IRQS_LEGACY + 34)
+#define MX1_SDHC_INT            (NR_IRQS_LEGACY + 35)
+#define MX1_INT_I2C             (NR_IRQS_LEGACY + 39)
+#define MX1_INT_CSPI2           (NR_IRQS_LEGACY + 40)
+#define MX1_INT_CSPI1           (NR_IRQS_LEGACY + 41)
+#define MX1_SSI_TX_INT          (NR_IRQS_LEGACY + 42)
+#define MX1_SSI_TX_ERR_INT      (NR_IRQS_LEGACY + 43)
+#define MX1_SSI_RX_INT          (NR_IRQS_LEGACY + 44)
+#define MX1_SSI_RX_ERR_INT      (NR_IRQS_LEGACY + 45)
+#define MX1_TOUCH_INT           (NR_IRQS_LEGACY + 46)
+#define MX1_INT_USBD0           (NR_IRQS_LEGACY + 47)
+#define MX1_INT_USBD1           (NR_IRQS_LEGACY + 48)
+#define MX1_INT_USBD2           (NR_IRQS_LEGACY + 49)
+#define MX1_INT_USBD3           (NR_IRQS_LEGACY + 50)
+#define MX1_INT_USBD4           (NR_IRQS_LEGACY + 51)
+#define MX1_INT_USBD5           (NR_IRQS_LEGACY + 52)
+#define MX1_INT_USBD6           (NR_IRQS_LEGACY + 53)
+#define MX1_BTSYS_INT           (NR_IRQS_LEGACY + 55)
+#define MX1_BTTIM_INT           (NR_IRQS_LEGACY + 56)
+#define MX1_BTWUI_INT           (NR_IRQS_LEGACY + 57)
+#define MX1_TIM2_INT            (NR_IRQS_LEGACY + 58)
+#define MX1_TIM1_INT            (NR_IRQS_LEGACY + 59)
+#define MX1_DMA_ERR             (NR_IRQS_LEGACY + 60)
+#define MX1_DMA_INT             (NR_IRQS_LEGACY + 61)
+#define MX1_GPIO_INT_PORTD      (NR_IRQS_LEGACY + 62)
+#define MX1_WDT_INT             (NR_IRQS_LEGACY + 63)
 
 /* DMA */
 #define MX1_DMA_REQ_UART3_T             2
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 6cd049ebbd8..468738aa997 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -99,59 +99,60 @@
 #define MX21_IO_ADDRESS(x)              IOMEM(MX21_IO_P2V(x))
 
 /* fixed interrupt numbers */
-#define MX21_INT_CSPI3          6
-#define MX21_INT_GPIO           8
-#define MX21_INT_FIRI           9
-#define MX21_INT_SDHC2          10
-#define MX21_INT_SDHC1          11
-#define MX21_INT_I2C            12
-#define MX21_INT_SSI2           13
-#define MX21_INT_SSI1           14
-#define MX21_INT_CSPI2          15
-#define MX21_INT_CSPI1          16
-#define MX21_INT_UART4          17
-#define MX21_INT_UART3          18
-#define MX21_INT_UART2          19
-#define MX21_INT_UART1          20
-#define MX21_INT_KPP            21
-#define MX21_INT_RTC            22
-#define MX21_INT_PWM            23
-#define MX21_INT_GPT3           24
-#define MX21_INT_GPT2           25
-#define MX21_INT_GPT1           26
-#define MX21_INT_WDOG           27
-#define MX21_INT_PCMCIA         28
-#define MX21_INT_NFC            29
-#define MX21_INT_BMI            30
-#define MX21_INT_CSI            31
-#define MX21_INT_DMACH0         32
-#define MX21_INT_DMACH1         33
-#define MX21_INT_DMACH2         34
-#define MX21_INT_DMACH3         35
-#define MX21_INT_DMACH4         36
-#define MX21_INT_DMACH5         37
-#define MX21_INT_DMACH6         38
-#define MX21_INT_DMACH7         39
-#define MX21_INT_DMACH8         40
-#define MX21_INT_DMACH9         41
-#define MX21_INT_DMACH10        42
-#define MX21_INT_DMACH11        43
-#define MX21_INT_DMACH12        44
-#define MX21_INT_DMACH13        45
-#define MX21_INT_DMACH14        46
-#define MX21_INT_DMACH15        47
-#define MX21_INT_EMMAENC        49
-#define MX21_INT_EMMADEC        50
-#define MX21_INT_EMMAPRP        51
-#define MX21_INT_EMMAPP         52
-#define MX21_INT_USBWKUP        53
-#define MX21_INT_USBDMA         54
-#define MX21_INT_USBHOST        55
-#define MX21_INT_USBFUNC        56
-#define MX21_INT_USBMNP         57
-#define MX21_INT_USBCTRL        58
-#define MX21_INT_SLCDC          60
-#define MX21_INT_LCDC           61
+#include <asm/irq.h>
+#define MX21_INT_CSPI3          (NR_IRQS_LEGACY + 6)
+#define MX21_INT_GPIO           (NR_IRQS_LEGACY + 8)
+#define MX21_INT_FIRI           (NR_IRQS_LEGACY + 9)
+#define MX21_INT_SDHC2          (NR_IRQS_LEGACY + 10)
+#define MX21_INT_SDHC1          (NR_IRQS_LEGACY + 11)
+#define MX21_INT_I2C            (NR_IRQS_LEGACY + 12)
+#define MX21_INT_SSI2           (NR_IRQS_LEGACY + 13)
+#define MX21_INT_SSI1           (NR_IRQS_LEGACY + 14)
+#define MX21_INT_CSPI2          (NR_IRQS_LEGACY + 15)
+#define MX21_INT_CSPI1          (NR_IRQS_LEGACY + 16)
+#define MX21_INT_UART4          (NR_IRQS_LEGACY + 17)
+#define MX21_INT_UART3          (NR_IRQS_LEGACY + 18)
+#define MX21_INT_UART2          (NR_IRQS_LEGACY + 19)
+#define MX21_INT_UART1          (NR_IRQS_LEGACY + 20)
+#define MX21_INT_KPP            (NR_IRQS_LEGACY + 21)
+#define MX21_INT_RTC            (NR_IRQS_LEGACY + 22)
+#define MX21_INT_PWM            (NR_IRQS_LEGACY + 23)
+#define MX21_INT_GPT3           (NR_IRQS_LEGACY + 24)
+#define MX21_INT_GPT2           (NR_IRQS_LEGACY + 25)
+#define MX21_INT_GPT1           (NR_IRQS_LEGACY + 26)
+#define MX21_INT_WDOG           (NR_IRQS_LEGACY + 27)
+#define MX21_INT_PCMCIA         (NR_IRQS_LEGACY + 28)
+#define MX21_INT_NFC            (NR_IRQS_LEGACY + 29)
+#define MX21_INT_BMI            (NR_IRQS_LEGACY + 30)
+#define MX21_INT_CSI            (NR_IRQS_LEGACY + 31)
+#define MX21_INT_DMACH0         (NR_IRQS_LEGACY + 32)
+#define MX21_INT_DMACH1         (NR_IRQS_LEGACY + 33)
+#define MX21_INT_DMACH2         (NR_IRQS_LEGACY + 34)
+#define MX21_INT_DMACH3         (NR_IRQS_LEGACY + 35)
+#define MX21_INT_DMACH4         (NR_IRQS_LEGACY + 36)
+#define MX21_INT_DMACH5         (NR_IRQS_LEGACY + 37)
+#define MX21_INT_DMACH6         (NR_IRQS_LEGACY + 38)
+#define MX21_INT_DMACH7         (NR_IRQS_LEGACY + 39)
+#define MX21_INT_DMACH8         (NR_IRQS_LEGACY + 40)
+#define MX21_INT_DMACH9         (NR_IRQS_LEGACY + 41)
+#define MX21_INT_DMACH10        (NR_IRQS_LEGACY + 42)
+#define MX21_INT_DMACH11        (NR_IRQS_LEGACY + 43)
+#define MX21_INT_DMACH12        (NR_IRQS_LEGACY + 44)
+#define MX21_INT_DMACH13        (NR_IRQS_LEGACY + 45)
+#define MX21_INT_DMACH14        (NR_IRQS_LEGACY + 46)
+#define MX21_INT_DMACH15        (NR_IRQS_LEGACY + 47)
+#define MX21_INT_EMMAENC        (NR_IRQS_LEGACY + 49)
+#define MX21_INT_EMMADEC        (NR_IRQS_LEGACY + 50)
+#define MX21_INT_EMMAPRP        (NR_IRQS_LEGACY + 51)
+#define MX21_INT_EMMAPP         (NR_IRQS_LEGACY + 52)
+#define MX21_INT_USBWKUP        (NR_IRQS_LEGACY + 53)
+#define MX21_INT_USBDMA         (NR_IRQS_LEGACY + 54)
+#define MX21_INT_USBHOST        (NR_IRQS_LEGACY + 55)
+#define MX21_INT_USBFUNC        (NR_IRQS_LEGACY + 56)
+#define MX21_INT_USBMNP         (NR_IRQS_LEGACY + 57)
+#define MX21_INT_USBCTRL        (NR_IRQS_LEGACY + 58)
+#define MX21_INT_SLCDC          (NR_IRQS_LEGACY + 60)
+#define MX21_INT_LCDC           (NR_IRQS_LEGACY + 61)
 
 /* fixed DMA request numbers */
 #define MX21_DMA_REQ_CSPI3_RX   1
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index ccebf5ba12f..627d94f1b01 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -61,40 +61,44 @@
 #define MX25_IO_P2V(x)                  IMX_IO_P2V(x)
 #define MX25_IO_ADDRESS(x)              IOMEM(MX25_IO_P2V(x))
 
-#define MX25_INT_CSPI3          0
-#define MX25_INT_I2C1           3
-#define MX25_INT_I2C2           4
-#define MX25_INT_UART4          5
-#define MX25_INT_ESDHC2         8
-#define MX25_INT_ESDHC1         9
-#define MX25_INT_I2C3           10
-#define MX25_INT_SSI2           11
-#define MX25_INT_SSI1           12
-#define MX25_INT_CSPI2          13
-#define MX25_INT_CSPI1          14
-#define MX25_INT_GPIO3          16
-#define MX25_INT_CSI            17
-#define MX25_INT_UART3          18
-#define MX25_INT_GPIO4          23
-#define MX25_INT_KPP            24
-#define MX25_INT_DRYICE         25
-#define MX25_INT_PWM1           26
-#define MX25_INT_UART2          32
-#define MX25_INT_NFC            33
-#define MX25_INT_SDMA           34
-#define MX25_INT_USB_HS         35
-#define MX25_INT_PWM2           36
-#define MX25_INT_USB_OTG        37
-#define MX25_INT_LCDC           39
-#define MX25_INT_UART5          40
-#define MX25_INT_PWM3           41
-#define MX25_INT_PWM4           42
-#define MX25_INT_CAN1           43
-#define MX25_INT_CAN2           44
-#define MX25_INT_UART1          45
-#define MX25_INT_GPIO2          51
-#define MX25_INT_GPIO1          52
-#define MX25_INT_FEC            57
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX25_INT_CSPI3          (NR_IRQS_LEGACY + 0)
+#define MX25_INT_I2C1           (NR_IRQS_LEGACY + 3)
+#define MX25_INT_I2C2           (NR_IRQS_LEGACY + 4)
+#define MX25_INT_UART4          (NR_IRQS_LEGACY + 5)
+#define MX25_INT_ESDHC2         (NR_IRQS_LEGACY + 8)
+#define MX25_INT_ESDHC1         (NR_IRQS_LEGACY + 9)
+#define MX25_INT_I2C3           (NR_IRQS_LEGACY + 10)
+#define MX25_INT_SSI2           (NR_IRQS_LEGACY + 11)
+#define MX25_INT_SSI1           (NR_IRQS_LEGACY + 12)
+#define MX25_INT_CSPI2          (NR_IRQS_LEGACY + 13)
+#define MX25_INT_CSPI1          (NR_IRQS_LEGACY + 14)
+#define MX25_INT_GPIO3          (NR_IRQS_LEGACY + 16)
+#define MX25_INT_CSI            (NR_IRQS_LEGACY + 17)
+#define MX25_INT_UART3          (NR_IRQS_LEGACY + 18)
+#define MX25_INT_GPIO4          (NR_IRQS_LEGACY + 23)
+#define MX25_INT_KPP            (NR_IRQS_LEGACY + 24)
+#define MX25_INT_DRYICE         (NR_IRQS_LEGACY + 25)
+#define MX25_INT_PWM1           (NR_IRQS_LEGACY + 26)
+#define MX25_INT_UART2          (NR_IRQS_LEGACY + 32)
+#define MX25_INT_NFC            (NR_IRQS_LEGACY + 33)
+#define MX25_INT_SDMA           (NR_IRQS_LEGACY + 34)
+#define MX25_INT_USB_HS         (NR_IRQS_LEGACY + 35)
+#define MX25_INT_PWM2           (NR_IRQS_LEGACY + 36)
+#define MX25_INT_USB_OTG        (NR_IRQS_LEGACY + 37)
+#define MX25_INT_LCDC           (NR_IRQS_LEGACY + 39)
+#define MX25_INT_UART5          (NR_IRQS_LEGACY + 40)
+#define MX25_INT_PWM3           (NR_IRQS_LEGACY + 41)
+#define MX25_INT_PWM4           (NR_IRQS_LEGACY + 42)
+#define MX25_INT_CAN1           (NR_IRQS_LEGACY + 43)
+#define MX25_INT_CAN2           (NR_IRQS_LEGACY + 44)
+#define MX25_INT_UART1          (NR_IRQS_LEGACY + 45)
+#define MX25_INT_GPIO2          (NR_IRQS_LEGACY + 51)
+#define MX25_INT_GPIO1          (NR_IRQS_LEGACY + 52)
+#define MX25_INT_FEC            (NR_IRQS_LEGACY + 57)
 
 #define MX25_DMA_REQ_SSI2_RX1   22
 #define MX25_DMA_REQ_SSI2_TX1   23
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 6265357284d..e074616d54c 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -128,69 +128,70 @@
 #define MX27_IO_ADDRESS(x)              IOMEM(MX27_IO_P2V(x))
 
 /* fixed interrupt numbers */
-#define MX27_INT_I2C2           1
-#define MX27_INT_GPT6           2
-#define MX27_INT_GPT5           3
-#define MX27_INT_GPT4           4
-#define MX27_INT_RTIC           5
-#define MX27_INT_CSPI3          6
-#define MX27_INT_SDHC           7
-#define MX27_INT_GPIO           8
-#define MX27_INT_SDHC3          9
-#define MX27_INT_SDHC2          10
-#define MX27_INT_SDHC1          11
-#define MX27_INT_I2C1           12
-#define MX27_INT_SSI2           13
-#define MX27_INT_SSI1           14
-#define MX27_INT_CSPI2          15
-#define MX27_INT_CSPI1          16
-#define MX27_INT_UART4          17
-#define MX27_INT_UART3          18
-#define MX27_INT_UART2          19
-#define MX27_INT_UART1          20
-#define MX27_INT_KPP            21
-#define MX27_INT_RTC            22
-#define MX27_INT_PWM            23
-#define MX27_INT_GPT3           24
-#define MX27_INT_GPT2           25
-#define MX27_INT_GPT1           26
-#define MX27_INT_WDOG           27
-#define MX27_INT_PCMCIA         28
-#define MX27_INT_NFC            29
-#define MX27_INT_ATA            30
-#define MX27_INT_CSI            31
-#define MX27_INT_DMACH0         32
-#define MX27_INT_DMACH1         33
-#define MX27_INT_DMACH2         34
-#define MX27_INT_DMACH3         35
-#define MX27_INT_DMACH4         36
-#define MX27_INT_DMACH5         37
-#define MX27_INT_DMACH6         38
-#define MX27_INT_DMACH7         39
-#define MX27_INT_DMACH8         40
-#define MX27_INT_DMACH9         41
-#define MX27_INT_DMACH10        42
-#define MX27_INT_DMACH11        43
-#define MX27_INT_DMACH12        44
-#define MX27_INT_DMACH13        45
-#define MX27_INT_DMACH14        46
-#define MX27_INT_DMACH15        47
-#define MX27_INT_UART6          48
-#define MX27_INT_UART5          49
-#define MX27_INT_FEC            50
-#define MX27_INT_EMMAPRP        51
-#define MX27_INT_EMMAPP         52
-#define MX27_INT_VPU            53
-#define MX27_INT_USB_HS1        54
-#define MX27_INT_USB_HS2        55
-#define MX27_INT_USB_OTG        56
-#define MX27_INT_SCC_SMN        57
-#define MX27_INT_SCC_SCM        58
-#define MX27_INT_SAHARA         59
-#define MX27_INT_SLCDC          60
-#define MX27_INT_LCDC           61
-#define MX27_INT_IIM            62
-#define MX27_INT_CCM            63
+#include <asm/irq.h>
+#define MX27_INT_I2C2           (NR_IRQS_LEGACY + 1)
+#define MX27_INT_GPT6           (NR_IRQS_LEGACY + 2)
+#define MX27_INT_GPT5           (NR_IRQS_LEGACY + 3)
+#define MX27_INT_GPT4           (NR_IRQS_LEGACY + 4)
+#define MX27_INT_RTIC           (NR_IRQS_LEGACY + 5)
+#define MX27_INT_CSPI3          (NR_IRQS_LEGACY + 6)
+#define MX27_INT_SDHC           (NR_IRQS_LEGACY + 7)
+#define MX27_INT_GPIO           (NR_IRQS_LEGACY + 8)
+#define MX27_INT_SDHC3          (NR_IRQS_LEGACY + 9)
+#define MX27_INT_SDHC2          (NR_IRQS_LEGACY + 10)
+#define MX27_INT_SDHC1          (NR_IRQS_LEGACY + 11)
+#define MX27_INT_I2C1           (NR_IRQS_LEGACY + 12)
+#define MX27_INT_SSI2           (NR_IRQS_LEGACY + 13)
+#define MX27_INT_SSI1           (NR_IRQS_LEGACY + 14)
+#define MX27_INT_CSPI2          (NR_IRQS_LEGACY + 15)
+#define MX27_INT_CSPI1          (NR_IRQS_LEGACY + 16)
+#define MX27_INT_UART4          (NR_IRQS_LEGACY + 17)
+#define MX27_INT_UART3          (NR_IRQS_LEGACY + 18)
+#define MX27_INT_UART2          (NR_IRQS_LEGACY + 19)
+#define MX27_INT_UART1          (NR_IRQS_LEGACY + 20)
+#define MX27_INT_KPP            (NR_IRQS_LEGACY + 21)
+#define MX27_INT_RTC            (NR_IRQS_LEGACY + 22)
+#define MX27_INT_PWM            (NR_IRQS_LEGACY + 23)
+#define MX27_INT_GPT3           (NR_IRQS_LEGACY + 24)
+#define MX27_INT_GPT2           (NR_IRQS_LEGACY + 25)
+#define MX27_INT_GPT1           (NR_IRQS_LEGACY + 26)
+#define MX27_INT_WDOG           (NR_IRQS_LEGACY + 27)
+#define MX27_INT_PCMCIA         (NR_IRQS_LEGACY + 28)
+#define MX27_INT_NFC            (NR_IRQS_LEGACY + 29)
+#define MX27_INT_ATA            (NR_IRQS_LEGACY + 30)
+#define MX27_INT_CSI            (NR_IRQS_LEGACY + 31)
+#define MX27_INT_DMACH0         (NR_IRQS_LEGACY + 32)
+#define MX27_INT_DMACH1         (NR_IRQS_LEGACY + 33)
+#define MX27_INT_DMACH2         (NR_IRQS_LEGACY + 34)
+#define MX27_INT_DMACH3         (NR_IRQS_LEGACY + 35)
+#define MX27_INT_DMACH4         (NR_IRQS_LEGACY + 36)
+#define MX27_INT_DMACH5         (NR_IRQS_LEGACY + 37)
+#define MX27_INT_DMACH6         (NR_IRQS_LEGACY + 38)
+#define MX27_INT_DMACH7         (NR_IRQS_LEGACY + 39)
+#define MX27_INT_DMACH8         (NR_IRQS_LEGACY + 40)
+#define MX27_INT_DMACH9         (NR_IRQS_LEGACY + 41)
+#define MX27_INT_DMACH10        (NR_IRQS_LEGACY + 42)
+#define MX27_INT_DMACH11        (NR_IRQS_LEGACY + 43)
+#define MX27_INT_DMACH12        (NR_IRQS_LEGACY + 44)
+#define MX27_INT_DMACH13        (NR_IRQS_LEGACY + 45)
+#define MX27_INT_DMACH14        (NR_IRQS_LEGACY + 46)
+#define MX27_INT_DMACH15        (NR_IRQS_LEGACY + 47)
+#define MX27_INT_UART6          (NR_IRQS_LEGACY + 48)
+#define MX27_INT_UART5          (NR_IRQS_LEGACY + 49)
+#define MX27_INT_FEC            (NR_IRQS_LEGACY + 50)
+#define MX27_INT_EMMAPRP        (NR_IRQS_LEGACY + 51)
+#define MX27_INT_EMMAPP         (NR_IRQS_LEGACY + 52)
+#define MX27_INT_VPU            (NR_IRQS_LEGACY + 53)
+#define MX27_INT_USB_HS1        (NR_IRQS_LEGACY + 54)
+#define MX27_INT_USB_HS2        (NR_IRQS_LEGACY + 55)
+#define MX27_INT_USB_OTG        (NR_IRQS_LEGACY + 56)
+#define MX27_INT_SCC_SMN        (NR_IRQS_LEGACY + 57)
+#define MX27_INT_SCC_SCM        (NR_IRQS_LEGACY + 58)
+#define MX27_INT_SAHARA         (NR_IRQS_LEGACY + 59)
+#define MX27_INT_SLCDC          (NR_IRQS_LEGACY + 60)
+#define MX27_INT_LCDC           (NR_IRQS_LEGACY + 61)
+#define MX27_INT_IIM            (NR_IRQS_LEGACY + 62)
+#define MX27_INT_CCM            (NR_IRQS_LEGACY + 63)
 
 /* fixed DMA request numbers */
 #define MX27_DMA_REQ_CSPI3_RX   1
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index 6d07839fdec..11642f5b224 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -68,49 +68,50 @@
 #define MX2x_CSI_BASE_ADDR                      (MX2x_SAHB1_BASE_ADDR + 0x0000)
 
 /* fixed interrupt numbers */
-#define MX2x_INT_CSPI3          6
-#define MX2x_INT_GPIO           8
-#define MX2x_INT_SDHC2          10
-#define MX2x_INT_SDHC1          11
-#define MX2x_INT_I2C            12
-#define MX2x_INT_SSI2           13
-#define MX2x_INT_SSI1           14
-#define MX2x_INT_CSPI2          15
-#define MX2x_INT_CSPI1          16
-#define MX2x_INT_UART4          17
-#define MX2x_INT_UART3          18
-#define MX2x_INT_UART2          19
-#define MX2x_INT_UART1          20
-#define MX2x_INT_KPP            21
-#define MX2x_INT_RTC            22
-#define MX2x_INT_PWM            23
-#define MX2x_INT_GPT3           24
-#define MX2x_INT_GPT2           25
-#define MX2x_INT_GPT1           26
-#define MX2x_INT_WDOG           27
-#define MX2x_INT_PCMCIA         28
-#define MX2x_INT_NANDFC         29
-#define MX2x_INT_CSI            31
-#define MX2x_INT_DMACH0         32
-#define MX2x_INT_DMACH1         33
-#define MX2x_INT_DMACH2         34
-#define MX2x_INT_DMACH3         35
-#define MX2x_INT_DMACH4         36
-#define MX2x_INT_DMACH5         37
-#define MX2x_INT_DMACH6         38
-#define MX2x_INT_DMACH7         39
-#define MX2x_INT_DMACH8         40
-#define MX2x_INT_DMACH9         41
-#define MX2x_INT_DMACH10        42
-#define MX2x_INT_DMACH11        43
-#define MX2x_INT_DMACH12        44
-#define MX2x_INT_DMACH13        45
-#define MX2x_INT_DMACH14        46
-#define MX2x_INT_DMACH15        47
-#define MX2x_INT_EMMAPRP        51
-#define MX2x_INT_EMMAPP         52
-#define MX2x_INT_SLCDC          60
-#define MX2x_INT_LCDC           61
+#include <asm/irq.h>
+#define MX2x_INT_CSPI3          (NR_IRQS_LEGACY + 6)
+#define MX2x_INT_GPIO           (NR_IRQS_LEGACY + 8)
+#define MX2x_INT_SDHC2          (NR_IRQS_LEGACY + 10)
+#define MX2x_INT_SDHC1          (NR_IRQS_LEGACY + 11)
+#define MX2x_INT_I2C            (NR_IRQS_LEGACY + 12)
+#define MX2x_INT_SSI2           (NR_IRQS_LEGACY + 13)
+#define MX2x_INT_SSI1           (NR_IRQS_LEGACY + 14)
+#define MX2x_INT_CSPI2          (NR_IRQS_LEGACY + 15)
+#define MX2x_INT_CSPI1          (NR_IRQS_LEGACY + 16)
+#define MX2x_INT_UART4          (NR_IRQS_LEGACY + 17)
+#define MX2x_INT_UART3          (NR_IRQS_LEGACY + 18)
+#define MX2x_INT_UART2          (NR_IRQS_LEGACY + 19)
+#define MX2x_INT_UART1          (NR_IRQS_LEGACY + 20)
+#define MX2x_INT_KPP            (NR_IRQS_LEGACY + 21)
+#define MX2x_INT_RTC            (NR_IRQS_LEGACY + 22)
+#define MX2x_INT_PWM            (NR_IRQS_LEGACY + 23)
+#define MX2x_INT_GPT3           (NR_IRQS_LEGACY + 24)
+#define MX2x_INT_GPT2           (NR_IRQS_LEGACY + 25)
+#define MX2x_INT_GPT1           (NR_IRQS_LEGACY + 26)
+#define MX2x_INT_WDOG           (NR_IRQS_LEGACY + 27)
+#define MX2x_INT_PCMCIA         (NR_IRQS_LEGACY + 28)
+#define MX2x_INT_NANDFC         (NR_IRQS_LEGACY + 29)
+#define MX2x_INT_CSI            (NR_IRQS_LEGACY + 31)
+#define MX2x_INT_DMACH0         (NR_IRQS_LEGACY + 32)
+#define MX2x_INT_DMACH1         (NR_IRQS_LEGACY + 33)
+#define MX2x_INT_DMACH2         (NR_IRQS_LEGACY + 34)
+#define MX2x_INT_DMACH3         (NR_IRQS_LEGACY + 35)
+#define MX2x_INT_DMACH4         (NR_IRQS_LEGACY + 36)
+#define MX2x_INT_DMACH5         (NR_IRQS_LEGACY + 37)
+#define MX2x_INT_DMACH6         (NR_IRQS_LEGACY + 38)
+#define MX2x_INT_DMACH7         (NR_IRQS_LEGACY + 39)
+#define MX2x_INT_DMACH8         (NR_IRQS_LEGACY + 40)
+#define MX2x_INT_DMACH9         (NR_IRQS_LEGACY + 41)
+#define MX2x_INT_DMACH10        (NR_IRQS_LEGACY + 42)
+#define MX2x_INT_DMACH11        (NR_IRQS_LEGACY + 43)
+#define MX2x_INT_DMACH12        (NR_IRQS_LEGACY + 44)
+#define MX2x_INT_DMACH13        (NR_IRQS_LEGACY + 45)
+#define MX2x_INT_DMACH14        (NR_IRQS_LEGACY + 46)
+#define MX2x_INT_DMACH15        (NR_IRQS_LEGACY + 47)
+#define MX2x_INT_EMMAPRP        (NR_IRQS_LEGACY + 51)
+#define MX2x_INT_EMMAPP         (NR_IRQS_LEGACY + 52)
+#define MX2x_INT_SLCDC          (NR_IRQS_LEGACY + 60)
+#define MX2x_INT_LCDC           (NR_IRQS_LEGACY + 61)
 
 /* fixed DMA request numbers */
 #define MX2x_DMA_REQ_CSPI3_RX   1
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index e27619e442c..dbced61d9fd 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -118,63 +118,67 @@
 #define MX31_IO_P2V(x)                  IMX_IO_P2V(x)
 #define MX31_IO_ADDRESS(x)              IOMEM(MX31_IO_P2V(x))
 
-#define MX31_INT_I2C3           3
-#define MX31_INT_I2C2           4
-#define MX31_INT_MPEG4_ENCODER  5
-#define MX31_INT_RTIC           6
-#define MX31_INT_FIRI           7
-#define MX31_INT_SDHC2          8
-#define MX31_INT_SDHC1          9
-#define MX31_INT_I2C1           10
-#define MX31_INT_SSI2           11
-#define MX31_INT_SSI1           12
-#define MX31_INT_CSPI2          13
-#define MX31_INT_CSPI1          14
-#define MX31_INT_ATA            15
-#define MX31_INT_MBX            16
-#define MX31_INT_CSPI3          17
-#define MX31_INT_UART3          18
-#define MX31_INT_IIM            19
-#define MX31_INT_SIM2           20
-#define MX31_INT_SIM1           21
-#define MX31_INT_RNGA           22
-#define MX31_INT_EVTMON         23
-#define MX31_INT_KPP            24
-#define MX31_INT_RTC            25
-#define MX31_INT_PWM            26
-#define MX31_INT_EPIT2          27
-#define MX31_INT_EPIT1          28
-#define MX31_INT_GPT            29
-#define MX31_INT_POWER_FAIL     30
-#define MX31_INT_CCM_DVFS       31
-#define MX31_INT_UART2          32
-#define MX31_INT_NFC            33
-#define MX31_INT_SDMA           34
-#define MX31_INT_USB_HS1        35
-#define MX31_INT_USB_HS2        36
-#define MX31_INT_USB_OTG        37
-#define MX31_INT_MSHC1          39
-#define MX31_INT_MSHC2          40
-#define MX31_INT_IPU_ERR        41
-#define MX31_INT_IPU_SYN        42
-#define MX31_INT_UART1          45
-#define MX31_INT_UART4          46
-#define MX31_INT_UART5          47
-#define MX31_INT_ECT            48
-#define MX31_INT_SCC_SCM        49
-#define MX31_INT_SCC_SMN        50
-#define MX31_INT_GPIO2          51
-#define MX31_INT_GPIO1          52
-#define MX31_INT_CCM            53
-#define MX31_INT_PCMCIA         54
-#define MX31_INT_WDOG           55
-#define MX31_INT_GPIO3          56
-#define MX31_INT_EXT_POWER      58
-#define MX31_INT_EXT_TEMPER     59
-#define MX31_INT_EXT_SENSOR60   60
-#define MX31_INT_EXT_SENSOR61   61
-#define MX31_INT_EXT_WDOG       62
-#define MX31_INT_EXT_TV         63
+/*
+ * Interrupt numbers
+ */
+#include <asm/irq.h>
+#define MX31_INT_I2C3           (NR_IRQS_LEGACY + 3)
+#define MX31_INT_I2C2           (NR_IRQS_LEGACY + 4)
+#define MX31_INT_MPEG4_ENCODER  (NR_IRQS_LEGACY + 5)
+#define MX31_INT_RTIC           (NR_IRQS_LEGACY + 6)
+#define MX31_INT_FIRI           (NR_IRQS_LEGACY + 7)
+#define MX31_INT_SDHC2          (NR_IRQS_LEGACY + 8)
+#define MX31_INT_SDHC1          (NR_IRQS_LEGACY + 9)
+#define MX31_INT_I2C1           (NR_IRQS_LEGACY + 10)
+#define MX31_INT_SSI2           (NR_IRQS_LEGACY + 11)
+#define MX31_INT_SSI1           (NR_IRQS_LEGACY + 12)
+#define MX31_INT_CSPI2          (NR_IRQS_LEGACY + 13)
+#define MX31_INT_CSPI1          (NR_IRQS_LEGACY + 14)
+#define MX31_INT_ATA            (NR_IRQS_LEGACY + 15)
+#define MX31_INT_MBX            (NR_IRQS_LEGACY + 16)
+#define MX31_INT_CSPI3          (NR_IRQS_LEGACY + 17)
+#define MX31_INT_UART3          (NR_IRQS_LEGACY + 18)
+#define MX31_INT_IIM            (NR_IRQS_LEGACY + 19)
+#define MX31_INT_SIM2           (NR_IRQS_LEGACY + 20)
+#define MX31_INT_SIM1           (NR_IRQS_LEGACY + 21)
+#define MX31_INT_RNGA           (NR_IRQS_LEGACY + 22)
+#define MX31_INT_EVTMON         (NR_IRQS_LEGACY + 23)
+#define MX31_INT_KPP            (NR_IRQS_LEGACY + 24)
+#define MX31_INT_RTC            (NR_IRQS_LEGACY + 25)
+#define MX31_INT_PWM            (NR_IRQS_LEGACY + 26)
+#define MX31_INT_EPIT2          (NR_IRQS_LEGACY + 27)
+#define MX31_INT_EPIT1          (NR_IRQS_LEGACY + 28)
+#define MX31_INT_GPT            (NR_IRQS_LEGACY + 29)
+#define MX31_INT_POWER_FAIL     (NR_IRQS_LEGACY + 30)
+#define MX31_INT_CCM_DVFS       (NR_IRQS_LEGACY + 31)
+#define MX31_INT_UART2          (NR_IRQS_LEGACY + 32)
+#define MX31_INT_NFC            (NR_IRQS_LEGACY + 33)
+#define MX31_INT_SDMA           (NR_IRQS_LEGACY + 34)
+#define MX31_INT_USB_HS1        (NR_IRQS_LEGACY + 35)
+#define MX31_INT_USB_HS2        (NR_IRQS_LEGACY + 36)
+#define MX31_INT_USB_OTG        (NR_IRQS_LEGACY + 37)
+#define MX31_INT_MSHC1          (NR_IRQS_LEGACY + 39)
+#define MX31_INT_MSHC2          (NR_IRQS_LEGACY + 40)
+#define MX31_INT_IPU_ERR        (NR_IRQS_LEGACY + 41)
+#define MX31_INT_IPU_SYN        (NR_IRQS_LEGACY + 42)
+#define MX31_INT_UART1          (NR_IRQS_LEGACY + 45)
+#define MX31_INT_UART4          (NR_IRQS_LEGACY + 46)
+#define MX31_INT_UART5          (NR_IRQS_LEGACY + 47)
+#define MX31_INT_ECT            (NR_IRQS_LEGACY + 48)
+#define MX31_INT_SCC_SCM        (NR_IRQS_LEGACY + 49)
+#define MX31_INT_SCC_SMN        (NR_IRQS_LEGACY + 50)
+#define MX31_INT_GPIO2          (NR_IRQS_LEGACY + 51)
+#define MX31_INT_GPIO1          (NR_IRQS_LEGACY + 52)
+#define MX31_INT_CCM            (NR_IRQS_LEGACY + 53)
+#define MX31_INT_PCMCIA         (NR_IRQS_LEGACY + 54)
+#define MX31_INT_WDOG           (NR_IRQS_LEGACY + 55)
+#define MX31_INT_GPIO3          (NR_IRQS_LEGACY + 56)
+#define MX31_INT_EXT_POWER      (NR_IRQS_LEGACY + 58)
+#define MX31_INT_EXT_TEMPER     (NR_IRQS_LEGACY + 59)
+#define MX31_INT_EXT_SENSOR60   (NR_IRQS_LEGACY + 60)
+#define MX31_INT_EXT_SENSOR61   (NR_IRQS_LEGACY + 61)
+#define MX31_INT_EXT_WDOG       (NR_IRQS_LEGACY + 62)
+#define MX31_INT_EXT_TV         (NR_IRQS_LEGACY + 63)
 
 #define MX31_DMA_REQ_SDHC1      20
 #define MX31_DMA_REQ_SDHC2      21
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 80965a99aa5..2af5d3a699c 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -120,60 +120,61 @@
 /*
  * Interrupt numbers
  */
-#define MX35_INT_OWIRE          2
-#define MX35_INT_I2C3           3
-#define MX35_INT_I2C2           4
-#define MX35_INT_RTIC           6
-#define MX35_INT_ESDHC1         7
-#define MX35_INT_ESDHC2         8
-#define MX35_INT_ESDHC3         9
-#define MX35_INT_I2C1           10
-#define MX35_INT_SSI1           11
-#define MX35_INT_SSI2           12
-#define MX35_INT_CSPI2          13
-#define MX35_INT_CSPI1          14
-#define MX35_INT_ATA            15
-#define MX35_INT_GPU2D          16
-#define MX35_INT_ASRC           17
-#define MX35_INT_UART3          18
-#define MX35_INT_IIM            19
-#define MX35_INT_RNGA           22
-#define MX35_INT_EVTMON         23
-#define MX35_INT_KPP            24
-#define MX35_INT_RTC            25
-#define MX35_INT_PWM            26
-#define MX35_INT_EPIT2          27
-#define MX35_INT_EPIT1          28
-#define MX35_INT_GPT            29
-#define MX35_INT_POWER_FAIL     30
-#define MX35_INT_UART2          32
-#define MX35_INT_NFC            33
-#define MX35_INT_SDMA           34
-#define MX35_INT_USB_HS         35
-#define MX35_INT_USB_OTG        37
-#define MX35_INT_MSHC1          39
-#define MX35_INT_ESAI           40
-#define MX35_INT_IPU_ERR        41
-#define MX35_INT_IPU_SYN        42
-#define MX35_INT_CAN1           43
-#define MX35_INT_CAN2           44
-#define MX35_INT_UART1          45
-#define MX35_INT_MLB            46
-#define MX35_INT_SPDIF          47
-#define MX35_INT_ECT            48
-#define MX35_INT_SCC_SCM        49
-#define MX35_INT_SCC_SMN        50
-#define MX35_INT_GPIO2          51
-#define MX35_INT_GPIO1          52
-#define MX35_INT_WDOG           55
-#define MX35_INT_GPIO3          56
-#define MX35_INT_FEC            57
-#define MX35_INT_EXT_POWER      58
-#define MX35_INT_EXT_TEMPER     59
-#define MX35_INT_EXT_SENSOR60   60
-#define MX35_INT_EXT_SENSOR61   61
-#define MX35_INT_EXT_WDOG       62
-#define MX35_INT_EXT_TV         63
+#include <asm/irq.h>
+#define MX35_INT_OWIRE          (NR_IRQS_LEGACY + 2)
+#define MX35_INT_I2C3           (NR_IRQS_LEGACY + 3)
+#define MX35_INT_I2C2           (NR_IRQS_LEGACY + 4)
+#define MX35_INT_RTIC           (NR_IRQS_LEGACY + 6)
+#define MX35_INT_ESDHC1         (NR_IRQS_LEGACY + 7)
+#define MX35_INT_ESDHC2         (NR_IRQS_LEGACY + 8)
+#define MX35_INT_ESDHC3         (NR_IRQS_LEGACY + 9)
+#define MX35_INT_I2C1           (NR_IRQS_LEGACY + 10)
+#define MX35_INT_SSI1           (NR_IRQS_LEGACY + 11)
+#define MX35_INT_SSI2           (NR_IRQS_LEGACY + 12)
+#define MX35_INT_CSPI2          (NR_IRQS_LEGACY + 13)
+#define MX35_INT_CSPI1          (NR_IRQS_LEGACY + 14)
+#define MX35_INT_ATA            (NR_IRQS_LEGACY + 15)
+#define MX35_INT_GPU2D          (NR_IRQS_LEGACY + 16)
+#define MX35_INT_ASRC           (NR_IRQS_LEGACY + 17)
+#define MX35_INT_UART3          (NR_IRQS_LEGACY + 18)
+#define MX35_INT_IIM            (NR_IRQS_LEGACY + 19)
+#define MX35_INT_RNGA           (NR_IRQS_LEGACY + 22)
+#define MX35_INT_EVTMON         (NR_IRQS_LEGACY + 23)
+#define MX35_INT_KPP            (NR_IRQS_LEGACY + 24)
+#define MX35_INT_RTC            (NR_IRQS_LEGACY + 25)
+#define MX35_INT_PWM            (NR_IRQS_LEGACY + 26)
+#define MX35_INT_EPIT2          (NR_IRQS_LEGACY + 27)
+#define MX35_INT_EPIT1          (NR_IRQS_LEGACY + 28)
+#define MX35_INT_GPT            (NR_IRQS_LEGACY + 29)
+#define MX35_INT_POWER_FAIL     (NR_IRQS_LEGACY + 30)
+#define MX35_INT_UART2          (NR_IRQS_LEGACY + 32)
+#define MX35_INT_NFC            (NR_IRQS_LEGACY + 33)
+#define MX35_INT_SDMA           (NR_IRQS_LEGACY + 34)
+#define MX35_INT_USB_HS         (NR_IRQS_LEGACY + 35)
+#define MX35_INT_USB_OTG        (NR_IRQS_LEGACY + 37)
+#define MX35_INT_MSHC1          (NR_IRQS_LEGACY + 39)
+#define MX35_INT_ESAI           (NR_IRQS_LEGACY + 40)
+#define MX35_INT_IPU_ERR        (NR_IRQS_LEGACY + 41)
+#define MX35_INT_IPU_SYN        (NR_IRQS_LEGACY + 42)
+#define MX35_INT_CAN1           (NR_IRQS_LEGACY + 43)
+#define MX35_INT_CAN2           (NR_IRQS_LEGACY + 44)
+#define MX35_INT_UART1          (NR_IRQS_LEGACY + 45)
+#define MX35_INT_MLB            (NR_IRQS_LEGACY + 46)
+#define MX35_INT_SPDIF          (NR_IRQS_LEGACY + 47)
+#define MX35_INT_ECT            (NR_IRQS_LEGACY + 48)
+#define MX35_INT_SCC_SCM        (NR_IRQS_LEGACY + 49)
+#define MX35_INT_SCC_SMN        (NR_IRQS_LEGACY + 50)
+#define MX35_INT_GPIO2          (NR_IRQS_LEGACY + 51)
+#define MX35_INT_GPIO1          (NR_IRQS_LEGACY + 52)
+#define MX35_INT_WDOG           (NR_IRQS_LEGACY + 55)
+#define MX35_INT_GPIO3          (NR_IRQS_LEGACY + 56)
+#define MX35_INT_FEC            (NR_IRQS_LEGACY + 57)
+#define MX35_INT_EXT_POWER      (NR_IRQS_LEGACY + 58)
+#define MX35_INT_EXT_TEMPER     (NR_IRQS_LEGACY + 59)
+#define MX35_INT_EXT_SENSOR60   (NR_IRQS_LEGACY + 60)
+#define MX35_INT_EXT_SENSOR61   (NR_IRQS_LEGACY + 61)
+#define MX35_INT_EXT_WDOG       (NR_IRQS_LEGACY + 62)
+#define MX35_INT_EXT_TV         (NR_IRQS_LEGACY + 63)
 
 #define MX35_DMA_REQ_SSI2_RX1   22
 #define MX35_DMA_REQ_SSI2_TX1   23
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 30dbf424583..96fb4fbc8ad 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -143,44 +143,45 @@
 /*
  * Interrupt numbers
  */
-#define MX3x_INT_I2C3           3
-#define MX3x_INT_I2C2           4
-#define MX3x_INT_RTIC           6
-#define MX3x_INT_I2C            10
-#define MX3x_INT_CSPI2          13
-#define MX3x_INT_CSPI1          14
-#define MX3x_INT_ATA            15
-#define MX3x_INT_UART3          18
-#define MX3x_INT_IIM            19
-#define MX3x_INT_RNGA           22
-#define MX3x_INT_EVTMON         23
-#define MX3x_INT_KPP            24
-#define MX3x_INT_RTC            25
-#define MX3x_INT_PWM            26
-#define MX3x_INT_EPIT2          27
-#define MX3x_INT_EPIT1          28
-#define MX3x_INT_GPT            29
-#define MX3x_INT_POWER_FAIL     30
-#define MX3x_INT_UART2          32
-#define MX3x_INT_NANDFC         33
-#define MX3x_INT_SDMA           34
-#define MX3x_INT_MSHC1          39
-#define MX3x_INT_IPU_ERR        41
-#define MX3x_INT_IPU_SYN        42
-#define MX3x_INT_UART1          45
-#define MX3x_INT_ECT            48
-#define MX3x_INT_SCC_SCM        49
-#define MX3x_INT_SCC_SMN        50
-#define MX3x_INT_GPIO2          51
-#define MX3x_INT_GPIO1          52
-#define MX3x_INT_WDOG           55
-#define MX3x_INT_GPIO3          56
-#define MX3x_INT_EXT_POWER      58
-#define MX3x_INT_EXT_TEMPER     59
-#define MX3x_INT_EXT_SENSOR60   60
-#define MX3x_INT_EXT_SENSOR61   61
-#define MX3x_INT_EXT_WDOG       62
-#define MX3x_INT_EXT_TV         63
+#include <asm/irq.h>
+#define MX3x_INT_I2C3           (NR_IRQS_LEGACY + 3)
+#define MX3x_INT_I2C2           (NR_IRQS_LEGACY + 4)
+#define MX3x_INT_RTIC           (NR_IRQS_LEGACY + 6)
+#define MX3x_INT_I2C            (NR_IRQS_LEGACY + 10)
+#define MX3x_INT_CSPI2          (NR_IRQS_LEGACY + 13)
+#define MX3x_INT_CSPI1          (NR_IRQS_LEGACY + 14)
+#define MX3x_INT_ATA            (NR_IRQS_LEGACY + 15)
+#define MX3x_INT_UART3          (NR_IRQS_LEGACY + 18)
+#define MX3x_INT_IIM            (NR_IRQS_LEGACY + 19)
+#define MX3x_INT_RNGA           (NR_IRQS_LEGACY + 22)
+#define MX3x_INT_EVTMON         (NR_IRQS_LEGACY + 23)
+#define MX3x_INT_KPP            (NR_IRQS_LEGACY + 24)
+#define MX3x_INT_RTC            (NR_IRQS_LEGACY + 25)
+#define MX3x_INT_PWM            (NR_IRQS_LEGACY + 26)
+#define MX3x_INT_EPIT2          (NR_IRQS_LEGACY + 27)
+#define MX3x_INT_EPIT1          (NR_IRQS_LEGACY + 28)
+#define MX3x_INT_GPT            (NR_IRQS_LEGACY + 29)
+#define MX3x_INT_POWER_FAIL     (NR_IRQS_LEGACY + 30)
+#define MX3x_INT_UART2          (NR_IRQS_LEGACY + 32)
+#define MX3x_INT_NANDFC         (NR_IRQS_LEGACY + 33)
+#define MX3x_INT_SDMA           (NR_IRQS_LEGACY + 34)
+#define MX3x_INT_MSHC1          (NR_IRQS_LEGACY + 39)
+#define MX3x_INT_IPU_ERR        (NR_IRQS_LEGACY + 41)
+#define MX3x_INT_IPU_SYN        (NR_IRQS_LEGACY + 42)
+#define MX3x_INT_UART1          (NR_IRQS_LEGACY + 45)
+#define MX3x_INT_ECT            (NR_IRQS_LEGACY + 48)
+#define MX3x_INT_SCC_SCM        (NR_IRQS_LEGACY + 49)
+#define MX3x_INT_SCC_SMN        (NR_IRQS_LEGACY + 50)
+#define MX3x_INT_GPIO2          (NR_IRQS_LEGACY + 51)
+#define MX3x_INT_GPIO1          (NR_IRQS_LEGACY + 52)
+#define MX3x_INT_WDOG           (NR_IRQS_LEGACY + 55)
+#define MX3x_INT_GPIO3          (NR_IRQS_LEGACY + 56)
+#define MX3x_INT_EXT_POWER      (NR_IRQS_LEGACY + 58)
+#define MX3x_INT_EXT_TEMPER     (NR_IRQS_LEGACY + 59)
+#define MX3x_INT_EXT_SENSOR60   (NR_IRQS_LEGACY + 60)
+#define MX3x_INT_EXT_SENSOR61   (NR_IRQS_LEGACY + 61)
+#define MX3x_INT_EXT_WDOG       (NR_IRQS_LEGACY + 62)
+#define MX3x_INT_EXT_TV         (NR_IRQS_LEGACY + 63)
 
 #define MX3x_PROD_SIGNATURE             0x1     /* For MX31 */
 
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
index 5f2da75a47f..09ac19c1570 100644
--- a/arch/arm/plat-mxc/include/mach/mx50.h
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -188,99 +188,100 @@
 /*
  * Interrupt numbers
  */
-#define MX50_INT_MMC_SDHC1      1
-#define MX50_INT_MMC_SDHC2      2
-#define MX50_INT_MMC_SDHC3      3
-#define MX50_INT_MMC_SDHC4      4
-#define MX50_INT_DAP            5
-#define MX50_INT_SDMA           6
-#define MX50_INT_IOMUX          7
-#define MX50_INT_UART4          13
-#define MX50_INT_USB_H1         14
-#define MX50_INT_USB_OTG        18
-#define MX50_INT_DATABAHN       19
-#define MX50_INT_ELCDIF         20
-#define MX50_INT_EPXP           21
-#define MX50_INT_SRTC_NTZ       24
-#define MX50_INT_SRTC_TZ        25
-#define MX50_INT_EPDC           27
-#define MX50_INT_NIC            28
-#define MX50_INT_SSI1           29
-#define MX50_INT_SSI2           30
-#define MX50_INT_UART1          31
-#define MX50_INT_UART2          32
-#define MX50_INT_UART3          33
-#define MX50_INT_RESV34         34
-#define MX50_INT_RESV35         35
-#define MX50_INT_CSPI1          36
-#define MX50_INT_CSPI2          37
-#define MX50_INT_CSPI           38
-#define MX50_INT_GPT            39
-#define MX50_INT_EPIT1          40
-#define MX50_INT_GPIO1_INT7     42
-#define MX50_INT_GPIO1_INT6     43
-#define MX50_INT_GPIO1_INT5     44
-#define MX50_INT_GPIO1_INT4     45
-#define MX50_INT_GPIO1_INT3     46
-#define MX50_INT_GPIO1_INT2     47
-#define MX50_INT_GPIO1_INT1     48
-#define MX50_INT_GPIO1_INT0     49
-#define MX50_INT_GPIO1_LOW      50
-#define MX50_INT_GPIO1_HIGH     51
-#define MX50_INT_GPIO2_LOW      52
-#define MX50_INT_GPIO2_HIGH     53
-#define MX50_INT_GPIO3_LOW      54
-#define MX50_INT_GPIO3_HIGH     55
-#define MX50_INT_GPIO4_LOW      56
-#define MX50_INT_GPIO4_HIGH     57
-#define MX50_INT_WDOG1          58
-#define MX50_INT_KPP            60
-#define MX50_INT_PWM1           61
-#define MX50_INT_I2C1           62
-#define MX50_INT_I2C2           63
-#define MX50_INT_I2C3           64
-#define MX50_INT_RESV65         65
-#define MX50_INT_DCDC           66
-#define MX50_INT_THERMAL_ALARM  67
-#define MX50_INT_ANA3           68
-#define MX50_INT_ANA4           69
-#define MX50_INT_CCM1           71
-#define MX50_INT_CCM2           72
-#define MX50_INT_GPC1           73
-#define MX50_INT_GPC2           74
-#define MX50_INT_SRC            75
-#define MX50_INT_NM             76
-#define MX50_INT_PMU            77
-#define MX50_INT_CTI_IRQ        78
-#define MX50_INT_CTI1_TG0       79
-#define MX50_INT_CTI1_TG1       80
-#define MX50_INT_GPU2_IRQ       84
-#define MX50_INT_GPU2_BUSY      85
-#define MX50_INT_UART5          86
-#define MX50_INT_FEC            87
-#define MX50_INT_OWIRE          88
-#define MX50_INT_CTI1_TG2       89
-#define MX50_INT_SJC            90
-#define MX50_INT_DCP_CHAN1_3    91
-#define MX50_INT_DCP_CHAN0      92
-#define MX50_INT_PWM2           94
-#define MX50_INT_RNGB           97
-#define MX50_INT_CTI1_TG3       98
-#define MX50_INT_RAWNAND_BCH    100
-#define MX50_INT_RAWNAND_GPMI   102
-#define MX50_INT_GPIO5_LOW      103
-#define MX50_INT_GPIO5_HIGH     104
-#define MX50_INT_GPIO6_LOW      105
-#define MX50_INT_GPIO6_HIGH     106
-#define MX50_INT_MSHC           109
-#define MX50_INT_APBHDMA_CHAN0  110
-#define MX50_INT_APBHDMA_CHAN1  111
-#define MX50_INT_APBHDMA_CHAN2  112
-#define MX50_INT_APBHDMA_CHAN3  113
-#define MX50_INT_APBHDMA_CHAN4  114
-#define MX50_INT_APBHDMA_CHAN5  115
-#define MX50_INT_APBHDMA_CHAN6  116
-#define MX50_INT_APBHDMA_CHAN7  117
+#include <asm/irq.h>
+#define MX50_INT_MMC_SDHC1      (NR_IRQS_LEGACY + 1)
+#define MX50_INT_MMC_SDHC2      (NR_IRQS_LEGACY + 2)
+#define MX50_INT_MMC_SDHC3      (NR_IRQS_LEGACY + 3)
+#define MX50_INT_MMC_SDHC4      (NR_IRQS_LEGACY + 4)
+#define MX50_INT_DAP            (NR_IRQS_LEGACY + 5)
+#define MX50_INT_SDMA           (NR_IRQS_LEGACY + 6)
+#define MX50_INT_IOMUX          (NR_IRQS_LEGACY + 7)
+#define MX50_INT_UART4          (NR_IRQS_LEGACY + 13)
+#define MX50_INT_USB_H1         (NR_IRQS_LEGACY + 14)
+#define MX50_INT_USB_OTG        (NR_IRQS_LEGACY + 18)
+#define MX50_INT_DATABAHN       (NR_IRQS_LEGACY + 19)
+#define MX50_INT_ELCDIF         (NR_IRQS_LEGACY + 20)
+#define MX50_INT_EPXP           (NR_IRQS_LEGACY + 21)
+#define MX50_INT_SRTC_NTZ       (NR_IRQS_LEGACY + 24)
+#define MX50_INT_SRTC_TZ        (NR_IRQS_LEGACY + 25)
+#define MX50_INT_EPDC           (NR_IRQS_LEGACY + 27)
+#define MX50_INT_NIC            (NR_IRQS_LEGACY + 28)
+#define MX50_INT_SSI1           (NR_IRQS_LEGACY + 29)
+#define MX50_INT_SSI2           (NR_IRQS_LEGACY + 30)
+#define MX50_INT_UART1          (NR_IRQS_LEGACY + 31)
+#define MX50_INT_UART2          (NR_IRQS_LEGACY + 32)
+#define MX50_INT_UART3          (NR_IRQS_LEGACY + 33)
+#define MX50_INT_RESV34         (NR_IRQS_LEGACY + 34)
+#define MX50_INT_RESV35         (NR_IRQS_LEGACY + 35)
+#define MX50_INT_CSPI1          (NR_IRQS_LEGACY + 36)
+#define MX50_INT_CSPI2          (NR_IRQS_LEGACY + 37)
+#define MX50_INT_CSPI           (NR_IRQS_LEGACY + 38)
+#define MX50_INT_GPT            (NR_IRQS_LEGACY + 39)
+#define MX50_INT_EPIT1          (NR_IRQS_LEGACY + 40)
+#define MX50_INT_GPIO1_INT7     (NR_IRQS_LEGACY + 42)
+#define MX50_INT_GPIO1_INT6     (NR_IRQS_LEGACY + 43)
+#define MX50_INT_GPIO1_INT5     (NR_IRQS_LEGACY + 44)
+#define MX50_INT_GPIO1_INT4     (NR_IRQS_LEGACY + 45)
+#define MX50_INT_GPIO1_INT3     (NR_IRQS_LEGACY + 46)
+#define MX50_INT_GPIO1_INT2     (NR_IRQS_LEGACY + 47)
+#define MX50_INT_GPIO1_INT1     (NR_IRQS_LEGACY + 48)
+#define MX50_INT_GPIO1_INT0     (NR_IRQS_LEGACY + 49)
+#define MX50_INT_GPIO1_LOW      (NR_IRQS_LEGACY + 50)
+#define MX50_INT_GPIO1_HIGH     (NR_IRQS_LEGACY + 51)
+#define MX50_INT_GPIO2_LOW      (NR_IRQS_LEGACY + 52)
+#define MX50_INT_GPIO2_HIGH     (NR_IRQS_LEGACY + 53)
+#define MX50_INT_GPIO3_LOW      (NR_IRQS_LEGACY + 54)
+#define MX50_INT_GPIO3_HIGH     (NR_IRQS_LEGACY + 55)
+#define MX50_INT_GPIO4_LOW      (NR_IRQS_LEGACY + 56)
+#define MX50_INT_GPIO4_HIGH     (NR_IRQS_LEGACY + 57)
+#define MX50_INT_WDOG1          (NR_IRQS_LEGACY + 58)
+#define MX50_INT_KPP            (NR_IRQS_LEGACY + 60)
+#define MX50_INT_PWM1           (NR_IRQS_LEGACY + 61)
+#define MX50_INT_I2C1           (NR_IRQS_LEGACY + 62)
+#define MX50_INT_I2C2           (NR_IRQS_LEGACY + 63)
+#define MX50_INT_I2C3           (NR_IRQS_LEGACY + 64)
+#define MX50_INT_RESV65         (NR_IRQS_LEGACY + 65)
+#define MX50_INT_DCDC           (NR_IRQS_LEGACY + 66)
+#define MX50_INT_THERMAL_ALARM  (NR_IRQS_LEGACY + 67)
+#define MX50_INT_ANA3           (NR_IRQS_LEGACY + 68)
+#define MX50_INT_ANA4           (NR_IRQS_LEGACY + 69)
+#define MX50_INT_CCM1           (NR_IRQS_LEGACY + 71)
+#define MX50_INT_CCM2           (NR_IRQS_LEGACY + 72)
+#define MX50_INT_GPC1           (NR_IRQS_LEGACY + 73)
+#define MX50_INT_GPC2           (NR_IRQS_LEGACY + 74)
+#define MX50_INT_SRC            (NR_IRQS_LEGACY + 75)
+#define MX50_INT_NM             (NR_IRQS_LEGACY + 76)
+#define MX50_INT_PMU            (NR_IRQS_LEGACY + 77)
+#define MX50_INT_CTI_IRQ        (NR_IRQS_LEGACY + 78)
+#define MX50_INT_CTI1_TG0       (NR_IRQS_LEGACY + 79)
+#define MX50_INT_CTI1_TG1       (NR_IRQS_LEGACY + 80)
+#define MX50_INT_GPU2_IRQ       (NR_IRQS_LEGACY + 84)
+#define MX50_INT_GPU2_BUSY      (NR_IRQS_LEGACY + 85)
+#define MX50_INT_UART5          (NR_IRQS_LEGACY + 86)
+#define MX50_INT_FEC            (NR_IRQS_LEGACY + 87)
+#define MX50_INT_OWIRE          (NR_IRQS_LEGACY + 88)
+#define MX50_INT_CTI1_TG2       (NR_IRQS_LEGACY + 89)
+#define MX50_INT_SJC            (NR_IRQS_LEGACY + 90)
+#define MX50_INT_DCP_CHAN1_3    (NR_IRQS_LEGACY + 91)
+#define MX50_INT_DCP_CHAN0      (NR_IRQS_LEGACY + 92)
+#define MX50_INT_PWM2           (NR_IRQS_LEGACY + 94)
+#define MX50_INT_RNGB           (NR_IRQS_LEGACY + 97)
+#define MX50_INT_CTI1_TG3       (NR_IRQS_LEGACY + 98)
+#define MX50_INT_RAWNAND_BCH    (NR_IRQS_LEGACY + 100)
+#define MX50_INT_RAWNAND_GPMI   (NR_IRQS_LEGACY + 102)
+#define MX50_INT_GPIO5_LOW      (NR_IRQS_LEGACY + 103)
+#define MX50_INT_GPIO5_HIGH     (NR_IRQS_LEGACY + 104)
+#define MX50_INT_GPIO6_LOW      (NR_IRQS_LEGACY + 105)
+#define MX50_INT_GPIO6_HIGH     (NR_IRQS_LEGACY + 106)
+#define MX50_INT_MSHC           (NR_IRQS_LEGACY + 109)
+#define MX50_INT_APBHDMA_CHAN0  (NR_IRQS_LEGACY + 110)
+#define MX50_INT_APBHDMA_CHAN1  (NR_IRQS_LEGACY + 111)
+#define MX50_INT_APBHDMA_CHAN2  (NR_IRQS_LEGACY + 112)
+#define MX50_INT_APBHDMA_CHAN3  (NR_IRQS_LEGACY + 113)
+#define MX50_INT_APBHDMA_CHAN4  (NR_IRQS_LEGACY + 114)
+#define MX50_INT_APBHDMA_CHAN5  (NR_IRQS_LEGACY + 115)
+#define MX50_INT_APBHDMA_CHAN6  (NR_IRQS_LEGACY + 116)
+#define MX50_INT_APBHDMA_CHAN7  (NR_IRQS_LEGACY + 117)
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 extern int mx50_revision(void);
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index cdf07c65ec1..af844f76261 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -232,110 +232,111 @@
 /*
  * Interrupt numbers
  */
-#define MX51_INT_BASE                   0
-#define MX51_INT_RESV0                  0
-#define MX51_INT_ESDHC1                 1
-#define MX51_INT_ESDHC2                 2
-#define MX51_INT_ESDHC3                 3
-#define MX51_INT_ESDHC4                 4
-#define MX51_INT_RESV5                  5
-#define MX51_INT_SDMA                   6
-#define MX51_INT_IOMUX                  7
-#define MX51_INT_NFC                    8
-#define MX51_INT_VPU                    9
-#define MX51_INT_IPU_ERR                10
-#define MX51_INT_IPU_SYN                11
-#define MX51_INT_GPU                    12
-#define MX51_INT_RESV13                 13
-#define MX51_INT_USB_HS1                14
-#define MX51_INT_EMI                    15
-#define MX51_INT_USB_HS2                16
-#define MX51_INT_USB_HS3                17
-#define MX51_INT_USB_OTG                18
-#define MX51_INT_SAHARA_H0              19
-#define MX51_INT_SAHARA_H1              20
-#define MX51_INT_SCC_SMN                21
-#define MX51_INT_SCC_STZ                22
-#define MX51_INT_SCC_SCM                23
-#define MX51_INT_SRTC_NTZ               24
-#define MX51_INT_SRTC_TZ                25
-#define MX51_INT_RTIC                   26
-#define MX51_INT_CSU                    27
-#define MX51_INT_SLIM_B                 28
-#define MX51_INT_SSI1                   29
-#define MX51_INT_SSI2                   30
-#define MX51_INT_UART1                  31
-#define MX51_INT_UART2                  32
-#define MX51_INT_UART3                  33
-#define MX51_INT_RESV34                 34
-#define MX51_INT_RESV35                 35
-#define MX51_INT_ECSPI1                 36
-#define MX51_INT_ECSPI2                 37
-#define MX51_INT_CSPI                   38
-#define MX51_INT_GPT                    39
-#define MX51_INT_EPIT1                  40
-#define MX51_INT_EPIT2                  41
-#define MX51_INT_GPIO1_INT7             42
-#define MX51_INT_GPIO1_INT6             43
-#define MX51_INT_GPIO1_INT5             44
-#define MX51_INT_GPIO1_INT4             45
-#define MX51_INT_GPIO1_INT3             46
-#define MX51_INT_GPIO1_INT2             47
-#define MX51_INT_GPIO1_INT1             48
-#define MX51_INT_GPIO1_INT0             49
-#define MX51_INT_GPIO1_LOW              50
-#define MX51_INT_GPIO1_HIGH             51
-#define MX51_INT_GPIO2_LOW              52
-#define MX51_INT_GPIO2_HIGH             53
-#define MX51_INT_GPIO3_LOW              54
-#define MX51_INT_GPIO3_HIGH             55
-#define MX51_INT_GPIO4_LOW              56
-#define MX51_INT_GPIO4_HIGH             57
-#define MX51_INT_WDOG1                  58
-#define MX51_INT_WDOG2                  59
-#define MX51_INT_KPP                    60
-#define MX51_INT_PWM1                   61
-#define MX51_INT_I2C1                   62
-#define MX51_INT_I2C2                   63
-#define MX51_INT_HS_I2C                 64
-#define MX51_INT_RESV65                 65
-#define MX51_INT_RESV66                 66
-#define MX51_INT_SIM_IPB                67
-#define MX51_INT_SIM_DAT                68
-#define MX51_INT_IIM                    69
-#define MX51_INT_ATA                    70
-#define MX51_INT_CCM1                   71
-#define MX51_INT_CCM2                   72
-#define MX51_INT_GPC1                           73
-#define MX51_INT_GPC2                   74
-#define MX51_INT_SRC                    75
-#define MX51_INT_NM                     76
-#define MX51_INT_PMU                    77
-#define MX51_INT_CTI_IRQ                78
-#define MX51_INT_CTI1_TG0               79
-#define MX51_INT_CTI1_TG1               80
-#define MX51_INT_MCG_ERR                81
-#define MX51_INT_MCG_TMR                82
-#define MX51_INT_MCG_FUNC               83
-#define MX51_INT_GPU2_IRQ               84
-#define MX51_INT_GPU2_BUSY              85
-#define MX51_INT_RESV86                 86
-#define MX51_INT_FEC                    87
-#define MX51_INT_OWIRE                  88
-#define MX51_INT_CTI1_TG2               89
-#define MX51_INT_SJC                    90
-#define MX51_INT_SPDIF                  91
-#define MX51_INT_TVE                    92
-#define MX51_INT_FIRI                   93
-#define MX51_INT_PWM2                   94
-#define MX51_INT_SLIM_EXP               95
-#define MX51_INT_SSI3                   96
-#define MX51_INT_EMI_BOOT               97
-#define MX51_INT_CTI1_TG3               98
-#define MX51_INT_SMC_RX                 99
-#define MX51_INT_VPU_IDLE               100
-#define MX51_INT_EMI_NFC                101
-#define MX51_INT_GPU_IDLE               102
+#include <asm/irq.h>
+#define MX51_INT_BASE                   (NR_IRQS_LEGACY + 0)
+#define MX51_INT_RESV0                  (NR_IRQS_LEGACY + 0)
+#define MX51_INT_ESDHC1                 (NR_IRQS_LEGACY + 1)
+#define MX51_INT_ESDHC2                 (NR_IRQS_LEGACY + 2)
+#define MX51_INT_ESDHC3                 (NR_IRQS_LEGACY + 3)
+#define MX51_INT_ESDHC4                 (NR_IRQS_LEGACY + 4)
+#define MX51_INT_RESV5                  (NR_IRQS_LEGACY + 5)
+#define MX51_INT_SDMA                   (NR_IRQS_LEGACY + 6)
+#define MX51_INT_IOMUX                  (NR_IRQS_LEGACY + 7)
+#define MX51_INT_NFC                    (NR_IRQS_LEGACY + 8)
+#define MX51_INT_VPU                    (NR_IRQS_LEGACY + 9)
+#define MX51_INT_IPU_ERR                (NR_IRQS_LEGACY + 10)
+#define MX51_INT_IPU_SYN                (NR_IRQS_LEGACY + 11)
+#define MX51_INT_GPU                    (NR_IRQS_LEGACY + 12)
+#define MX51_INT_RESV13                 (NR_IRQS_LEGACY + 13)
+#define MX51_INT_USB_HS1                (NR_IRQS_LEGACY + 14)
+#define MX51_INT_EMI                    (NR_IRQS_LEGACY + 15)
+#define MX51_INT_USB_HS2                (NR_IRQS_LEGACY + 16)
+#define MX51_INT_USB_HS3                (NR_IRQS_LEGACY + 17)
+#define MX51_INT_USB_OTG                (NR_IRQS_LEGACY + 18)
+#define MX51_INT_SAHARA_H0              (NR_IRQS_LEGACY + 19)
+#define MX51_INT_SAHARA_H1              (NR_IRQS_LEGACY + 20)
+#define MX51_INT_SCC_SMN                (NR_IRQS_LEGACY + 21)
+#define MX51_INT_SCC_STZ                (NR_IRQS_LEGACY + 22)
+#define MX51_INT_SCC_SCM                (NR_IRQS_LEGACY + 23)
+#define MX51_INT_SRTC_NTZ               (NR_IRQS_LEGACY + 24)
+#define MX51_INT_SRTC_TZ                (NR_IRQS_LEGACY + 25)
+#define MX51_INT_RTIC                   (NR_IRQS_LEGACY + 26)
+#define MX51_INT_CSU                    (NR_IRQS_LEGACY + 27)
+#define MX51_INT_SLIM_B                 (NR_IRQS_LEGACY + 28)
+#define MX51_INT_SSI1                   (NR_IRQS_LEGACY + 29)
+#define MX51_INT_SSI2                   (NR_IRQS_LEGACY + 30)
+#define MX51_INT_UART1                  (NR_IRQS_LEGACY + 31)
+#define MX51_INT_UART2                  (NR_IRQS_LEGACY + 32)
+#define MX51_INT_UART3                  (NR_IRQS_LEGACY + 33)
+#define MX51_INT_RESV34                 (NR_IRQS_LEGACY + 34)
+#define MX51_INT_RESV35                 (NR_IRQS_LEGACY + 35)
+#define MX51_INT_ECSPI1                 (NR_IRQS_LEGACY + 36)
+#define MX51_INT_ECSPI2                 (NR_IRQS_LEGACY + 37)
+#define MX51_INT_CSPI                   (NR_IRQS_LEGACY + 38)
+#define MX51_INT_GPT                    (NR_IRQS_LEGACY + 39)
+#define MX51_INT_EPIT1                  (NR_IRQS_LEGACY + 40)
+#define MX51_INT_EPIT2                  (NR_IRQS_LEGACY + 41)
+#define MX51_INT_GPIO1_INT7             (NR_IRQS_LEGACY + 42)
+#define MX51_INT_GPIO1_INT6             (NR_IRQS_LEGACY + 43)
+#define MX51_INT_GPIO1_INT5             (NR_IRQS_LEGACY + 44)
+#define MX51_INT_GPIO1_INT4             (NR_IRQS_LEGACY + 45)
+#define MX51_INT_GPIO1_INT3             (NR_IRQS_LEGACY + 46)
+#define MX51_INT_GPIO1_INT2             (NR_IRQS_LEGACY + 47)
+#define MX51_INT_GPIO1_INT1             (NR_IRQS_LEGACY + 48)
+#define MX51_INT_GPIO1_INT0             (NR_IRQS_LEGACY + 49)
+#define MX51_INT_GPIO1_LOW              (NR_IRQS_LEGACY + 50)
+#define MX51_INT_GPIO1_HIGH             (NR_IRQS_LEGACY + 51)
+#define MX51_INT_GPIO2_LOW              (NR_IRQS_LEGACY + 52)
+#define MX51_INT_GPIO2_HIGH             (NR_IRQS_LEGACY + 53)
+#define MX51_INT_GPIO3_LOW              (NR_IRQS_LEGACY + 54)
+#define MX51_INT_GPIO3_HIGH             (NR_IRQS_LEGACY + 55)
+#define MX51_INT_GPIO4_LOW              (NR_IRQS_LEGACY + 56)
+#define MX51_INT_GPIO4_HIGH             (NR_IRQS_LEGACY + 57)
+#define MX51_INT_WDOG1                  (NR_IRQS_LEGACY + 58)
+#define MX51_INT_WDOG2                  (NR_IRQS_LEGACY + 59)
+#define MX51_INT_KPP                    (NR_IRQS_LEGACY + 60)
+#define MX51_INT_PWM1                   (NR_IRQS_LEGACY + 61)
+#define MX51_INT_I2C1                   (NR_IRQS_LEGACY + 62)
+#define MX51_INT_I2C2                   (NR_IRQS_LEGACY + 63)
+#define MX51_INT_HS_I2C                 (NR_IRQS_LEGACY + 64)
+#define MX51_INT_RESV65                 (NR_IRQS_LEGACY + 65)
+#define MX51_INT_RESV66                 (NR_IRQS_LEGACY + 66)
+#define MX51_INT_SIM_IPB                (NR_IRQS_LEGACY + 67)
+#define MX51_INT_SIM_DAT                (NR_IRQS_LEGACY + 68)
+#define MX51_INT_IIM                    (NR_IRQS_LEGACY + 69)
+#define MX51_INT_ATA                    (NR_IRQS_LEGACY + 70)
+#define MX51_INT_CCM1                   (NR_IRQS_LEGACY + 71)
+#define MX51_INT_CCM2                   (NR_IRQS_LEGACY + 72)
+#define MX51_INT_GPC1                   (NR_IRQS_LEGACY + 73)
+#define MX51_INT_GPC2                   (NR_IRQS_LEGACY + 74)
+#define MX51_INT_SRC                    (NR_IRQS_LEGACY + 75)
+#define MX51_INT_NM                     (NR_IRQS_LEGACY + 76)
+#define MX51_INT_PMU                    (NR_IRQS_LEGACY + 77)
+#define MX51_INT_CTI_IRQ                (NR_IRQS_LEGACY + 78)
+#define MX51_INT_CTI1_TG0               (NR_IRQS_LEGACY + 79)
+#define MX51_INT_CTI1_TG1               (NR_IRQS_LEGACY + 80)
+#define MX51_INT_MCG_ERR                (NR_IRQS_LEGACY + 81)
+#define MX51_INT_MCG_TMR                (NR_IRQS_LEGACY + 82)
+#define MX51_INT_MCG_FUNC               (NR_IRQS_LEGACY + 83)
+#define MX51_INT_GPU2_IRQ               (NR_IRQS_LEGACY + 84)
+#define MX51_INT_GPU2_BUSY              (NR_IRQS_LEGACY + 85)
+#define MX51_INT_RESV86                 (NR_IRQS_LEGACY + 86)
+#define MX51_INT_FEC                    (NR_IRQS_LEGACY + 87)
+#define MX51_INT_OWIRE                  (NR_IRQS_LEGACY + 88)
+#define MX51_INT_CTI1_TG2               (NR_IRQS_LEGACY + 89)
+#define MX51_INT_SJC                    (NR_IRQS_LEGACY + 90)
+#define MX51_INT_SPDIF                  (NR_IRQS_LEGACY + 91)
+#define MX51_INT_TVE                    (NR_IRQS_LEGACY + 92)
+#define MX51_INT_FIRI                   (NR_IRQS_LEGACY + 93)
+#define MX51_INT_PWM2                   (NR_IRQS_LEGACY + 94)
+#define MX51_INT_SLIM_EXP               (NR_IRQS_LEGACY + 95)
+#define MX51_INT_SSI3                   (NR_IRQS_LEGACY + 96)
+#define MX51_INT_EMI_BOOT               (NR_IRQS_LEGACY + 97)
+#define MX51_INT_CTI1_TG3               (NR_IRQS_LEGACY + 98)
+#define MX51_INT_SMC_RX                 (NR_IRQS_LEGACY + 99)
+#define MX51_INT_VPU_IDLE               (NR_IRQS_LEGACY + 100)
+#define MX51_INT_EMI_NFC                (NR_IRQS_LEGACY + 101)
+#define MX51_INT_GPU_IDLE               (NR_IRQS_LEGACY + 102)
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 extern int mx51_revision(void);
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index a37e8c35399..f829d1c2250 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -229,113 +229,114 @@
 /*
  * Interrupt numbers
  */
-#define MX53_INT_RESV0          0
-#define MX53_INT_ESDHC1 1
-#define MX53_INT_ESDHC2 2
-#define MX53_INT_ESDHC3 3
-#define MX53_INT_ESDHC4 4
-#define MX53_INT_DAP    5
-#define MX53_INT_SDMA   6
-#define MX53_INT_IOMUX  7
-#define MX53_INT_NFC    8
-#define MX53_INT_VPU    9
-#define MX53_INT_IPU_ERR        10
-#define MX53_INT_IPU_SYN        11
-#define MX53_INT_GPU    12
-#define MX53_INT_UART4  13
-#define MX53_INT_USB_H1 14
-#define MX53_INT_EMI    15
-#define MX53_INT_USB_H2 16
-#define MX53_INT_USB_H3 17
-#define MX53_INT_USB_OTG        18
-#define MX53_INT_SAHARA_H0      19
-#define MX53_INT_SAHARA_H1      20
-#define MX53_INT_SCC_SMN        21
-#define MX53_INT_SCC_STZ        22
-#define MX53_INT_SCC_SCM        23
-#define MX53_INT_SRTC_NTZ       24
-#define MX53_INT_SRTC_TZ        25
-#define MX53_INT_RTIC   26
-#define MX53_INT_CSU    27
-#define MX53_INT_SATA   28
-#define MX53_INT_SSI1   29
-#define MX53_INT_SSI2   30
-#define MX53_INT_UART1  31
-#define MX53_INT_UART2  32
-#define MX53_INT_UART3  33
-#define MX53_INT_RTC    34
-#define MX53_INT_PTP    35
-#define MX53_INT_ECSPI1 36
-#define MX53_INT_ECSPI2 37
-#define MX53_INT_CSPI   38
-#define MX53_INT_GPT    39
-#define MX53_INT_EPIT1  40
-#define MX53_INT_EPIT2  41
-#define MX53_INT_GPIO1_INT7     42
-#define MX53_INT_GPIO1_INT6     43
-#define MX53_INT_GPIO1_INT5     44
-#define MX53_INT_GPIO1_INT4     45
-#define MX53_INT_GPIO1_INT3     46
-#define MX53_INT_GPIO1_INT2     47
-#define MX53_INT_GPIO1_INT1     48
-#define MX53_INT_GPIO1_INT0     49
-#define MX53_INT_GPIO1_LOW      50
-#define MX53_INT_GPIO1_HIGH     51
-#define MX53_INT_GPIO2_LOW      52
-#define MX53_INT_GPIO2_HIGH     53
-#define MX53_INT_GPIO3_LOW      54
-#define MX53_INT_GPIO3_HIGH     55
-#define MX53_INT_GPIO4_LOW      56
-#define MX53_INT_GPIO4_HIGH     57
-#define MX53_INT_WDOG1  58
-#define MX53_INT_WDOG2  59
-#define MX53_INT_KPP    60
-#define MX53_INT_PWM1   61
-#define MX53_INT_I2C1   62
-#define MX53_INT_I2C2   63
-#define MX53_INT_I2C3   64
-#define MX53_INT_MLB    65
-#define MX53_INT_ASRC   66
-#define MX53_INT_SPDIF  67
-#define MX53_INT_SIM_DAT        68
-#define MX53_INT_IIM    69
-#define MX53_INT_ATA    70
-#define MX53_INT_CCM1   71
-#define MX53_INT_CCM2   72
-#define MX53_INT_GPC1   73
-#define MX53_INT_GPC2   74
-#define MX53_INT_SRC    75
-#define MX53_INT_NM             76
-#define MX53_INT_PMU    77
-#define MX53_INT_CTI_IRQ        78
-#define MX53_INT_CTI1_TG0       79
-#define MX53_INT_CTI1_TG1       80
-#define MX53_INT_ESAI   81
-#define MX53_INT_CAN1   82
-#define MX53_INT_CAN2   83
-#define MX53_INT_GPU2_IRQ       84
-#define MX53_INT_GPU2_BUSY      85
-#define MX53_INT_UART5  86
-#define MX53_INT_FEC    87
-#define MX53_INT_OWIRE  88
-#define MX53_INT_CTI1_TG2       89
-#define MX53_INT_SJC    90
-#define MX53_INT_TVE    92
-#define MX53_INT_FIRI   93
-#define MX53_INT_PWM2   94
-#define MX53_INT_SLIM_EXP       95
-#define MX53_INT_SSI3   96
-#define MX53_INT_EMI_BOOT       97
-#define MX53_INT_CTI1_TG3       98
-#define MX53_INT_SMC_RX 99
-#define MX53_INT_VPU_IDLE       100
-#define MX53_INT_EMI_NFC        101
-#define MX53_INT_GPU_IDLE       102
-#define MX53_INT_GPIO5_LOW      103
-#define MX53_INT_GPIO5_HIGH     104
-#define MX53_INT_GPIO6_LOW      105
-#define MX53_INT_GPIO6_HIGH     106
-#define MX53_INT_GPIO7_LOW      107
-#define MX53_INT_GPIO7_HIGH     108
+#include <asm/irq.h>
+#define MX53_INT_RESV0          (NR_IRQS_LEGACY + 0)
+#define MX53_INT_ESDHC1         (NR_IRQS_LEGACY + 1)
+#define MX53_INT_ESDHC2         (NR_IRQS_LEGACY + 2)
+#define MX53_INT_ESDHC3         (NR_IRQS_LEGACY + 3)
+#define MX53_INT_ESDHC4         (NR_IRQS_LEGACY + 4)
+#define MX53_INT_DAP            (NR_IRQS_LEGACY + 5)
+#define MX53_INT_SDMA           (NR_IRQS_LEGACY + 6)
+#define MX53_INT_IOMUX          (NR_IRQS_LEGACY + 7)
+#define MX53_INT_NFC            (NR_IRQS_LEGACY + 8)
+#define MX53_INT_VPU            (NR_IRQS_LEGACY + 9)
+#define MX53_INT_IPU_ERR        (NR_IRQS_LEGACY + 10)
+#define MX53_INT_IPU_SYN        (NR_IRQS_LEGACY + 11)
+#define MX53_INT_GPU            (NR_IRQS_LEGACY + 12)
+#define MX53_INT_UART4          (NR_IRQS_LEGACY + 13)
+#define MX53_INT_USB_H1         (NR_IRQS_LEGACY + 14)
+#define MX53_INT_EMI            (NR_IRQS_LEGACY + 15)
+#define MX53_INT_USB_H2         (NR_IRQS_LEGACY + 16)
+#define MX53_INT_USB_H3         (NR_IRQS_LEGACY + 17)
+#define MX53_INT_USB_OTG        (NR_IRQS_LEGACY + 18)
+#define MX53_INT_SAHARA_H0      (NR_IRQS_LEGACY + 19)
+#define MX53_INT_SAHARA_H1      (NR_IRQS_LEGACY + 20)
+#define MX53_INT_SCC_SMN        (NR_IRQS_LEGACY + 21)
+#define MX53_INT_SCC_STZ        (NR_IRQS_LEGACY + 22)
+#define MX53_INT_SCC_SCM        (NR_IRQS_LEGACY + 23)
+#define MX53_INT_SRTC_NTZ       (NR_IRQS_LEGACY + 24)
+#define MX53_INT_SRTC_TZ        (NR_IRQS_LEGACY + 25)
+#define MX53_INT_RTIC           (NR_IRQS_LEGACY + 26)
+#define MX53_INT_CSU            (NR_IRQS_LEGACY + 27)
+#define MX53_INT_SATA           (NR_IRQS_LEGACY + 28)
+#define MX53_INT_SSI1           (NR_IRQS_LEGACY + 29)
+#define MX53_INT_SSI2           (NR_IRQS_LEGACY + 30)
+#define MX53_INT_UART1          (NR_IRQS_LEGACY + 31)
+#define MX53_INT_UART2          (NR_IRQS_LEGACY + 32)
+#define MX53_INT_UART3          (NR_IRQS_LEGACY + 33)
+#define MX53_INT_RTC            (NR_IRQS_LEGACY + 34)
+#define MX53_INT_PTP            (NR_IRQS_LEGACY + 35)
+#define MX53_INT_ECSPI1         (NR_IRQS_LEGACY + 36)
+#define MX53_INT_ECSPI2         (NR_IRQS_LEGACY + 37)
+#define MX53_INT_CSPI           (NR_IRQS_LEGACY + 38)
+#define MX53_INT_GPT            (NR_IRQS_LEGACY + 39)
+#define MX53_INT_EPIT1          (NR_IRQS_LEGACY + 40)
+#define MX53_INT_EPIT2          (NR_IRQS_LEGACY + 41)
+#define MX53_INT_GPIO1_INT7     (NR_IRQS_LEGACY + 42)
+#define MX53_INT_GPIO1_INT6     (NR_IRQS_LEGACY + 43)
+#define MX53_INT_GPIO1_INT5     (NR_IRQS_LEGACY + 44)
+#define MX53_INT_GPIO1_INT4     (NR_IRQS_LEGACY + 45)
+#define MX53_INT_GPIO1_INT3     (NR_IRQS_LEGACY + 46)
+#define MX53_INT_GPIO1_INT2     (NR_IRQS_LEGACY + 47)
+#define MX53_INT_GPIO1_INT1     (NR_IRQS_LEGACY + 48)
+#define MX53_INT_GPIO1_INT0     (NR_IRQS_LEGACY + 49)
+#define MX53_INT_GPIO1_LOW      (NR_IRQS_LEGACY + 50)
+#define MX53_INT_GPIO1_HIGH     (NR_IRQS_LEGACY + 51)
+#define MX53_INT_GPIO2_LOW      (NR_IRQS_LEGACY + 52)
+#define MX53_INT_GPIO2_HIGH     (NR_IRQS_LEGACY + 53)
+#define MX53_INT_GPIO3_LOW      (NR_IRQS_LEGACY + 54)
+#define MX53_INT_GPIO3_HIGH     (NR_IRQS_LEGACY + 55)
+#define MX53_INT_GPIO4_LOW      (NR_IRQS_LEGACY + 56)
+#define MX53_INT_GPIO4_HIGH     (NR_IRQS_LEGACY + 57)
+#define MX53_INT_WDOG1          (NR_IRQS_LEGACY + 58)
+#define MX53_INT_WDOG2          (NR_IRQS_LEGACY + 59)
+#define MX53_INT_KPP            (NR_IRQS_LEGACY + 60)
+#define MX53_INT_PWM1           (NR_IRQS_LEGACY + 61)
+#define MX53_INT_I2C1           (NR_IRQS_LEGACY + 62)
+#define MX53_INT_I2C2           (NR_IRQS_LEGACY + 63)
+#define MX53_INT_I2C3           (NR_IRQS_LEGACY + 64)
+#define MX53_INT_MLB            (NR_IRQS_LEGACY + 65)
+#define MX53_INT_ASRC           (NR_IRQS_LEGACY + 66)
+#define MX53_INT_SPDIF          (NR_IRQS_LEGACY + 67)
+#define MX53_INT_SIM_DAT        (NR_IRQS_LEGACY + 68)
+#define MX53_INT_IIM            (NR_IRQS_LEGACY + 69)
+#define MX53_INT_ATA            (NR_IRQS_LEGACY + 70)
+#define MX53_INT_CCM1           (NR_IRQS_LEGACY + 71)
+#define MX53_INT_CCM2           (NR_IRQS_LEGACY + 72)
+#define MX53_INT_GPC1           (NR_IRQS_LEGACY + 73)
+#define MX53_INT_GPC2           (NR_IRQS_LEGACY + 74)
+#define MX53_INT_SRC            (NR_IRQS_LEGACY + 75)
+#define MX53_INT_NM             (NR_IRQS_LEGACY + 76)
+#define MX53_INT_PMU            (NR_IRQS_LEGACY + 77)
+#define MX53_INT_CTI_IRQ        (NR_IRQS_LEGACY + 78)
+#define MX53_INT_CTI1_TG0       (NR_IRQS_LEGACY + 79)
+#define MX53_INT_CTI1_TG1       (NR_IRQS_LEGACY + 80)
+#define MX53_INT_ESAI           (NR_IRQS_LEGACY + 81)
+#define MX53_INT_CAN1           (NR_IRQS_LEGACY + 82)
+#define MX53_INT_CAN2           (NR_IRQS_LEGACY + 83)
+#define MX53_INT_GPU2_IRQ       (NR_IRQS_LEGACY + 84)
+#define MX53_INT_GPU2_BUSY      (NR_IRQS_LEGACY + 85)
+#define MX53_INT_UART5          (NR_IRQS_LEGACY + 86)
+#define MX53_INT_FEC            (NR_IRQS_LEGACY + 87)
+#define MX53_INT_OWIRE          (NR_IRQS_LEGACY + 88)
+#define MX53_INT_CTI1_TG2       (NR_IRQS_LEGACY + 89)
+#define MX53_INT_SJC            (NR_IRQS_LEGACY + 90)
+#define MX53_INT_TVE            (NR_IRQS_LEGACY + 92)
+#define MX53_INT_FIRI           (NR_IRQS_LEGACY + 93)
+#define MX53_INT_PWM2           (NR_IRQS_LEGACY + 94)
+#define MX53_INT_SLIM_EXP       (NR_IRQS_LEGACY + 95)
+#define MX53_INT_SSI3           (NR_IRQS_LEGACY + 96)
+#define MX53_INT_EMI_BOOT       (NR_IRQS_LEGACY + 97)
+#define MX53_INT_CTI1_TG3       (NR_IRQS_LEGACY + 98)
+#define MX53_INT_SMC_RX         (NR_IRQS_LEGACY + 99)
+#define MX53_INT_VPU_IDLE       (NR_IRQS_LEGACY + 100)
+#define MX53_INT_EMI_NFC        (NR_IRQS_LEGACY + 101)
+#define MX53_INT_GPU_IDLE       (NR_IRQS_LEGACY + 102)
+#define MX53_INT_GPIO5_LOW      (NR_IRQS_LEGACY + 103)
+#define MX53_INT_GPIO5_HIGH     (NR_IRQS_LEGACY + 104)
+#define MX53_INT_GPIO6_LOW      (NR_IRQS_LEGACY + 105)
+#define MX53_INT_GPIO6_HIGH     (NR_IRQS_LEGACY + 106)
+#define MX53_INT_GPIO7_LOW      (NR_IRQS_LEGACY + 107)
+#define MX53_INT_GPIO7_HIGH     (NR_IRQS_LEGACY + 108)
 
 #endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 9ffd1bbe615..7eb9d132967 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -20,13 +20,15 @@
 #define MXC_EHCI_INTERFACE_MASK         (0xf)
 
 #define MXC_EHCI_POWER_PINS_ENABLED     (1 << 5)
-#define MXC_EHCI_TTL_ENABLED            (1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY           (1 << 7)
-#define MXC_EHCI_IPPUE_DOWN             (1 << 8)
-#define MXC_EHCI_IPPUE_UP               (1 << 9)
-#define MXC_EHCI_WAKEUP_ENABLED (1 << 10)
-#define MXC_EHCI_ITC_NO_THRESHOLD       (1 << 11)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH    (1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW      (1 << 7)
+#define MXC_EHCI_TTL_ENABLED            (1 << 8)
+
+#define MXC_EHCI_INTERNAL_PHY           (1 << 9)
+#define MXC_EHCI_IPPUE_DOWN             (1 << 10)
+#define MXC_EHCI_IPPUE_UP               (1 << 11)
+#define MXC_EHCI_WAKEUP_ENABLED         (1 << 12)
+#define MXC_EHCI_ITC_NO_THRESHOLD       (1 << 13)
 
 #define MXC_USBCTRL_OFFSET              0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET     0x8
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
deleted file mode 100644
index c0cab2270dd..00000000000
--- a/arch/arm/plat-mxc/pwm.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * simple driver for PWM (Pulse Width Modulator) controller
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/pwm.h>
-#include <mach/hardware.h>
-
-
-/* i.MX1 and i.MX21 share the same PWM function block: */
-
-#define MX1_PWMC    0x00   /* PWM Control Register */
-#define MX1_PWMS    0x04   /* PWM Sample Register */
-#define MX1_PWMP    0x08   /* PWM Period Register */
-
-
-/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
-
-#define MX3_PWMCR                 0x00    /* PWM Control Register */
-#define MX3_PWMSAR                0x0C    /* PWM Sample Register */
-#define MX3_PWMPR                 0x10    /* PWM Period Register */
-#define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)
-#define MX3_PWMCR_DOZEEN                (1 << 24)
-#define MX3_PWMCR_WAITEN                (1 << 23)
-#define MX3_PWMCR_DBGEN                 (1 << 22)
-#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
-#define MX3_PWMCR_CLKSRC_IPG      (1 << 16)
-#define MX3_PWMCR_EN              (1 << 0)
-
-
-
-struct pwm_device {
-        struct list_head        node;
-        struct platform_device *pdev;
-
-        const char      *label;
-        struct clk      *clk;
-
-        int             clk_enabled;
-        void __iomem    *mmio_base;
-
-        unsigned int    use_count;
-        unsigned int    pwm_id;
-};
-
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
-{
-        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
-                return -EINVAL;
-
-        if (!(cpu_is_mx1() || cpu_is_mx21())) {
-                unsigned long long c;
-                unsigned long period_cycles, duty_cycles, prescale;
-                u32 cr;
-
-                c = clk_get_rate(pwm->clk);
-                c = c * period_ns;
-                do_div(c, 1000000000);
-                period_cycles = c;
-
-                prescale = period_cycles / 0x10000 + 1;
-
-                period_cycles /= prescale;
-                c = (unsigned long long)period_cycles * duty_ns;
-                do_div(c, period_ns);
-                duty_cycles = c;
-
-                /*
-                 * according to imx pwm RM, the real period value should be
-                 * PERIOD value in PWMPR plus 2.
-                 */
-                if (period_cycles > 2)
-                        period_cycles -= 2;
-                else
-                        period_cycles = 0;
-
-                writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
-                writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
-
-                cr = MX3_PWMCR_PRESCALER(prescale) |
-                        MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
-                        MX3_PWMCR_DBGEN | MX3_PWMCR_EN;
-
-                if (cpu_is_mx25())
-                        cr |= MX3_PWMCR_CLKSRC_IPG;
-                else
-                        cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
-
-                writel(cr, pwm->mmio_base + MX3_PWMCR);
-        } else if (cpu_is_mx1() || cpu_is_mx21()) {
-                /* The PWM subsystem allows for exact frequencies. However,
-                 * I cannot connect a scope on my device to the PWM line and
-                 * thus cannot provide the program the PWM controller
-                 * exactly. Instead, I'm relying on the fact that the
-                 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
-                 * function group already. So I'll just modify the PWM sample
-                 * register to follow the ratio of duty_ns vs. period_ns
-                 * accordingly.
-                 *
-                 * This is good enough for programming the brightness of
-                 * the LCD backlight.
-                 *
-                 * The real implementation would divide PERCLK[0] first by
-                 * both the prescaler (/1 .. /128) and then by CLKSEL
-                 * (/2 .. /16).
-                 */
-                u32 max = readl(pwm->mmio_base + MX1_PWMP);
-                u32 p = max * duty_ns / period_ns;
-                writel(max - p, pwm->mmio_base + MX1_PWMS);
-        } else {
-                BUG();
-        }
-
-        return 0;
-}
-EXPORT_SYMBOL(pwm_config);
-
-int pwm_enable(struct pwm_device *pwm)
-{
-        int rc = 0;
-
-        if (!pwm->clk_enabled) {
-                rc = clk_prepare_enable(pwm->clk);
-                if (!rc)
-                        pwm->clk_enabled = 1;
-        }
-        return rc;
-}
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-        writel(0, pwm->mmio_base + MX3_PWMCR);
-
-        if (pwm->clk_enabled) {
-                clk_disable_unprepare(pwm->clk);
-                pwm->clk_enabled = 0;
-        }
-}
-EXPORT_SYMBOL(pwm_disable);
-
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-        struct pwm_device *pwm;
-        int found = 0;
-
-        mutex_lock(&pwm_lock);
-
-        list_for_each_entry(pwm, &pwm_list, node) {
-                if (pwm->pwm_id == pwm_id) {
-                        found = 1;
-                        break;
-                }
-        }
-
-        if (found) {
-                if (pwm->use_count == 0) {
-                        pwm->use_count++;
-                        pwm->label = label;
-                } else
-                        pwm = ERR_PTR(-EBUSY);
-        } else
-                pwm = ERR_PTR(-ENOENT);
-
-        mutex_unlock(&pwm_lock);
-        return pwm;
-}
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-        mutex_lock(&pwm_lock);
-
-        if (pwm->use_count) {
-                pwm->use_count--;
-                pwm->label = NULL;
-        } else
-                pr_warning("PWM device already freed\n");
-
-        mutex_unlock(&pwm_lock);
-}
-EXPORT_SYMBOL(pwm_free);
-
-static int __devinit mxc_pwm_probe(struct platform_device *pdev)
-{
-        struct pwm_device *pwm;
-        struct resource *r;
-        int ret = 0;
-
-        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-        if (pwm == NULL) {
-                dev_err(&pdev->dev, "failed to allocate memory\n");
-                return -ENOMEM;
-        }
-
-        pwm->clk = clk_get(&pdev->dev, "pwm");
-
-        if (IS_ERR(pwm->clk)) {
-                ret = PTR_ERR(pwm->clk);
-                goto err_free;
-        }
-
-        pwm->clk_enabled = 0;
-
-        pwm->use_count = 0;
-        pwm->pwm_id = pdev->id;
-        pwm->pdev = pdev;
-
-        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (r == NULL) {
-                dev_err(&pdev->dev, "no memory resource defined\n");
-                ret = -ENODEV;
-                goto err_free_clk;
-        }
-
-        r = request_mem_region(r->start, resource_size(r), pdev->name);
-        if (r == NULL) {
-                dev_err(&pdev->dev, "failed to request memory resource\n");
-                ret = -EBUSY;
-                goto err_free_clk;
-        }
-
-        pwm->mmio_base = ioremap(r->start, resource_size(r));
-        if (pwm->mmio_base == NULL) {
-                dev_err(&pdev->dev, "failed to ioremap() registers\n");
-                ret = -ENODEV;
-                goto err_free_mem;
-        }
-
-        mutex_lock(&pwm_lock);
-        list_add_tail(&pwm->node, &pwm_list);
-        mutex_unlock(&pwm_lock);
-
-        platform_set_drvdata(pdev, pwm);
-        return 0;
-
-err_free_mem:
-        release_mem_region(r->start, resource_size(r));
-err_free_clk:
-        clk_put(pwm->clk);
-err_free:
-        kfree(pwm);
-        return ret;
-}
-
-static int __devexit mxc_pwm_remove(struct platform_device *pdev)
-{
-        struct pwm_device *pwm;
-        struct resource *r;
-
-        pwm = platform_get_drvdata(pdev);
-        if (pwm == NULL)
-                return -ENODEV;
-
-        mutex_lock(&pwm_lock);
-        list_del(&pwm->node);
-        mutex_unlock(&pwm_lock);
-
-        iounmap(pwm->mmio_base);
-
-        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        release_mem_region(r->start, resource_size(r));
-
-        clk_put(pwm->clk);
-
-        kfree(pwm);
-        return 0;
-}
-
-static struct platform_driver mxc_pwm_driver = {
-        .driver         = {
-                .name   = "mxc_pwm",
-        },
-        .probe          = mxc_pwm_probe,
-        .remove         = __devexit_p(mxc_pwm_remove),
-};
-
-static int __init mxc_pwm_init(void)
-{
-        return platform_driver_register(&mxc_pwm_driver);
-}
-arch_initcall(mxc_pwm_init);
-
-static void __exit mxc_pwm_exit(void)
-{
-        platform_driver_unregister(&mxc_pwm_driver);
-}
-module_exit(mxc_pwm_exit);
-
-MODULE_LICENSE("GPL v2");
-MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 00e8e659e66..a17abcf9832 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -160,7 +160,8 @@ static const char *clock_event_mode_label[] = {
         [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
         [CLOCK_EVT_MODE_ONESHOT]  = "CLOCK_EVT_MODE_ONESHOT",
         [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
-        [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED"
+        [CLOCK_EVT_MODE_UNUSED]   = "CLOCK_EVT_MODE_UNUSED",
+        [CLOCK_EVT_MODE_RESUME]   = "CLOCK_EVT_MODE_RESUME",
 };
 #endif /* DEBUG */
 
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 98308ec1f32..3ed1adbc09f 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -15,12 +15,15 @@
 #include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
 
 #include <asm/mach/irq.h>
 #include <asm/exception.h>
 
 #include <mach/hardware.h>
 #include <mach/common.h>
+#include <mach/irqs.h>
 
 #include "irq-common.h"
 
@@ -49,6 +52,7 @@
 #define TZIC_ID0        0x0FD0  /* Indentification Register 0 */
 
 void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
+static struct irq_domain *domain;
 
 #define TZIC_NUM_IRQS 128
 
@@ -77,15 +81,14 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
 static void tzic_irq_suspend(struct irq_data *d)
 {
         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        int idx = gc->irq_base >> 5;
+        int idx = d->hwirq >> 5;
 
         __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
 }
 
 static void tzic_irq_resume(struct irq_data *d)
 {
-        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-        int idx = gc->irq_base >> 5;
+        int idx = d->hwirq >> 5;
 
         __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
                      tzic_base + TZIC_WAKEUP0(idx));
@@ -102,11 +105,10 @@ static struct mxc_extra_irq tzic_extra_irq = {
 #endif
 };
 
-static __init void tzic_init_gc(unsigned int irq_start)
+static __init void tzic_init_gc(int idx, unsigned int irq_start)
 {
         struct irq_chip_generic *gc;
         struct irq_chip_type *ct;
-        int idx = irq_start >> 5;
 
         gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
                                     handle_level_irq);
@@ -140,7 +142,8 @@ asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
                         while (stat) {
                                 handled = 1;
                                 irqofs = fls(stat) - 1;
-                                handle_IRQ(irqofs + i * 32, regs);
+                                handle_IRQ(irq_find_mapping(domain,
+                                                irqofs + i * 32), regs);
                                 stat &= ~(1 << irqofs);
                         }
                 }
@@ -154,6 +157,8 @@ asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
  */
 void __init tzic_init_irq(void __iomem *irqbase)
 {
+        struct device_node *np;
+        int irq_base;
         int i;
 
         tzic_base = irqbase;
@@ -175,12 +180,20 @@ void __init tzic_init_irq(void __iomem *irqbase)
 
         /* all IRQ no FIQ Warning :: No selection */
 
-        for (i = 0; i < TZIC_NUM_IRQS; i += 32)
-                tzic_init_gc(i);
+        irq_base = irq_alloc_descs(-1, 0, TZIC_NUM_IRQS, numa_node_id());
+        WARN_ON(irq_base < 0);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,tzic");
+        domain = irq_domain_add_legacy(np, TZIC_NUM_IRQS, irq_base, 0,
+                                       &irq_domain_simple_ops, NULL);
+        WARN_ON(!domain);
+
+        for (i = 0; i < 4; i++, irq_base += 32)
+                tzic_init_gc(i, irq_base);
 
 #ifdef CONFIG_FIQ
         /* Initialize FIQ */
-        init_FIQ();
+        init_FIQ(FIQ_START);
 #endif
 
         pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
@@ -190,6 +203,10 @@ void __init tzic_init_irq(void __iomem *irqbase)
  * tzic_enable_wake() - enable wakeup interrupt
  *
  * @return                      0 if successful; non-zero otherwise
+ *
+ * This function provides an interrupt synchronization point that is required
+ * by tzic enabled platforms before entering imx specific low power modes (ie,
+ * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
  */
 int tzic_enable_wake(void)
 {
diff --git a/arch/arm/plat-nomadik/include/plat/i2c.h b/arch/arm/plat-nomadik/include/plat/i2c.h
deleted file mode 100644
index 8ba70ffc31e..00000000000
--- a/arch/arm/plat-nomadik/include/plat/i2c.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2009 ST-Ericsson
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2, as
- * published by the Free Software Foundation.
- */
-#ifndef __PLAT_I2C_H
-#define __PLAT_I2C_H
-
-enum i2c_freq_mode {
-        I2C_FREQ_MODE_STANDARD,         /* up to 100 Kb/s */
-        I2C_FREQ_MODE_FAST,             /* up to 400 Kb/s */
-        I2C_FREQ_MODE_HIGH_SPEED,       /* up to 3.4 Mb/s */
-        I2C_FREQ_MODE_FAST_PLUS,        /* up to 1 Mb/s */
-};
-
-/**
- * struct nmk_i2c_controller - client specific controller configuration
- * @clk_freq:   clock frequency for the operation mode
- * @slsu:       Slave data setup time in ns.
- *              The needed setup time for three modes of operation
- *              are 250ns, 100ns and 10ns respectively thus leading
- *              to the values of 14, 6, 2 for a 48 MHz i2c clk
- * @tft:        Tx FIFO Threshold in bytes
- * @rft:        Rx FIFO Threshold in bytes
- * @timeout     Slave response timeout(ms)
- * @sm:         speed mode
- */
-struct nmk_i2c_controller {
-        unsigned long   clk_freq;
-        unsigned short  slsu;
-        unsigned char   tft;
-        unsigned char   rft;
-        int timeout;
-        enum i2c_freq_mode      sm;
-};
-
-#endif  /* __PLAT_I2C_H */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index ad95c7a5d00..dd36eba9506 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -29,7 +29,7 @@ config ARCH_OMAP2PLUS
         select USE_OF
         select PROC_DEVICETREE if PROC_FS
         help
-          "Systems based on OMAP2, OMAP3 or OMAP4"
+          "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
 
 endchoice
 
@@ -45,31 +45,30 @@ config OMAP_DEBUG_LEDS
         depends on OMAP_DEBUG_DEVICES
         default y if LEDS_CLASS
 
-config OMAP_SMARTREFLEX
-        bool "SmartReflex support"
-        depends on (ARCH_OMAP3 || ARCH_OMAP4) && PM
+config POWER_AVS_OMAP
+        bool "AVS(Adaptive Voltage Scaling) support for OMAP IP versions 1&2"
+        depends on POWER_AVS && (ARCH_OMAP3 || ARCH_OMAP4) && PM
         help
-          Say Y if you want to enable SmartReflex.
-
-          SmartReflex can perform continuous dynamic voltage
-          scaling around the nominal operating point voltage
-          according to silicon characteristics and operating
-          conditions. Enabling SmartReflex reduces power
-          consumption.
+          Say Y to enable AVS(Adaptive Voltage Scaling)
+          support on OMAP containing the version 1 or
+          version 2 of the SmartReflex IP.
+          V1 is the 65nm version used in OMAP3430.
+          V2 is the update for the 45nm version of the IP used in OMAP3630
+          and OMAP4430
 
           Please note, that by default SmartReflex is only
-          initialized. To enable the automatic voltage
-          compensation for vdd mpu  and vdd core from user space,
+          initialized and not enabled. To enable the automatic voltage
+          compensation for vdd mpu and vdd core from user space,
           user must write 1 to
-                /debug/voltage/vdd_<X>/smartreflex/autocomp,
-          where X is mpu or core for OMAP3.
+                /debug/smartreflex/sr_<X>/autocomp,
+          where X is mpu_iva or core for OMAP3.
           Optionally autocompensation can be enabled in the kernel
           by default during system init via the enable_on_init flag
           which an be passed as platform data to the smartreflex driver.
 
-config OMAP_SMARTREFLEX_CLASS3
+config POWER_AVS_OMAP_CLASS3
         bool "Class 3 mode of Smartreflex Implementation"
-        depends on OMAP_SMARTREFLEX && TWL4030_CORE
+        depends on POWER_AVS_OMAP && TWL4030_CORE
         help
           Say Y to enable Class 3 implementation of Smartreflex
 
@@ -150,7 +149,7 @@ config OMAP_32K_TIMER
           This timer saves power compared to the OMAP_MPU_TIMER, and has
           support for no tick during idle. The 32KHz timer provides less
           intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
-          currently only available for OMAP16XX, 24XX, 34XX and OMAP4.
+          currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
 
 config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
         bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index ed8605f0115..961bf859bc0 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,15 +4,13 @@
 
 # Common support
 obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
-         usb.o fb.o counter_32k.o
+         fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
 
 # omap_device support (OMAP2+ only at the moment)
-obj-$(CONFIG_ARCH_OMAP2) += omap_device.o
-obj-$(CONFIG_ARCH_OMAP3) += omap_device.o
-obj-$(CONFIG_ARCH_OMAP4) += omap_device.o
+obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_device.o
 
 obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
 obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 0a9b9a97011..89a3723b353 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -77,3 +77,12 @@ void __init omap_init_consistent_dma_size(void)
         init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
 #endif
 }
+
+/*
+ * Stub function for OMAP2 so that common files
+ * continue to build when custom builds are used
+ */
+int __weak omap_secure_ram_reserve_memblock(void)
+{
+        return 0;
+}
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 2132c4f389e..dbf1e03029a 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -29,7 +29,10 @@
 #include <plat/clock.h>
 
 /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
-#define OMAP2_32KSYNCNT_CR_OFF          0x10
+#define OMAP2_32KSYNCNT_REV_OFF         0x0
+#define OMAP2_32KSYNCNT_REV_SCHEME      (0x3 << 30)
+#define OMAP2_32KSYNCNT_CR_OFF_LOW      0x10
+#define OMAP2_32KSYNCNT_CR_OFF_HIGH     0x30
 
 /*
  * 32KHz clocksource ... always available, on pretty most chips except
@@ -84,9 +87,16 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
         int ret;
 
         /*
-         * 32k sync Counter register offset is at 0x10
+         * 32k sync Counter IP register offsets vary between the
+         * highlander version and the legacy ones.
+         * The 'SCHEME' bits(30-31) of the revision register is used
+         * to identify the version.
          */
-        sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF;
+        if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
+                                                OMAP2_32KSYNCNT_REV_SCHEME)
+                sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
+        else
+                sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW;
 
         /*
          * 120000 rough estimate from the calculations in
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index cb16ade437c..7fe626761e5 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -573,22 +573,25 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 
 static inline void omap_enable_channel_irq(int lch)
 {
-        u32 status;
-
         /* Clear CSR */
         if (cpu_class_is_omap1())
-                status = p->dma_read(CSR, lch);
-        else if (cpu_class_is_omap2())
+                p->dma_read(CSR, lch);
+        else
                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 
         /* Enable some nice interrupts. */
         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 }
 
-static void omap_disable_channel_irq(int lch)
+static inline void omap_disable_channel_irq(int lch)
 {
-        if (cpu_class_is_omap2())
-                p->dma_write(0, CICR, lch);
+        /* disable channel interrupts */
+        p->dma_write(0, CICR, lch);
+        /* Clear CSR */
+        if (cpu_class_is_omap1())
+                p->dma_read(CSR, lch);
+        else
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 }
 
 void omap_enable_dma_irq(int lch, u16 bits)
@@ -632,14 +635,14 @@ static inline void disable_lnk(int lch)
         l = p->dma_read(CLNK_CTRL, lch);
 
         /* Disable interrupts */
+        omap_disable_channel_irq(lch);
+
         if (cpu_class_is_omap1()) {
-                p->dma_write(0, CICR, lch);
                 /* Set the STOP_LNK bit */
                 l |= 1 << 14;
         }
 
         if (cpu_class_is_omap2()) {
-                omap_disable_channel_irq(lch);
                 /* Clear the ENABLE_LNK bit */
                 l &= ~(1 << 15);
         }
@@ -657,6 +660,9 @@ static inline void omap2_enable_irq_lch(int lch)
                 return;
 
         spin_lock_irqsave(&dma_chan_lock, flags);
+        /* clear IRQ STATUS */
+        p->dma_write(1 << lch, IRQSTATUS_L0, lch);
+        /* Enable interrupt */
         val = p->dma_read(IRQENABLE_L0, lch);
         val |= 1 << lch;
         p->dma_write(val, IRQENABLE_L0, lch);
@@ -672,9 +678,12 @@ static inline void omap2_disable_irq_lch(int lch)
                 return;
 
         spin_lock_irqsave(&dma_chan_lock, flags);
+        /* Disable interrupt */
         val = p->dma_read(IRQENABLE_L0, lch);
         val &= ~(1 << lch);
         p->dma_write(val, IRQENABLE_L0, lch);
+        /* clear IRQ STATUS */
+        p->dma_write(1 << lch, IRQSTATUS_L0, lch);
         spin_unlock_irqrestore(&dma_chan_lock, flags);
 }
 
@@ -745,11 +754,8 @@ int omap_request_dma(int dev_id, const char *dev_name,
         }
 
         if (cpu_class_is_omap2()) {
-                omap2_enable_irq_lch(free_ch);
                 omap_enable_channel_irq(free_ch);
-                /* Clear the CSR register and IRQ status register */
-                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
-                p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
+                omap2_enable_irq_lch(free_ch);
         }
 
         *dma_ch_out = free_ch;
@@ -768,27 +774,19 @@ void omap_free_dma(int lch)
                 return;
         }
 
-        if (cpu_class_is_omap1()) {
-                /* Disable all DMA interrupts for the channel. */
-                p->dma_write(0, CICR, lch);
-                /* Make sure the DMA transfer is stopped. */
-                p->dma_write(0, CCR, lch);
-        }
-
-        if (cpu_class_is_omap2()) {
+        /* Disable interrupt for logical channel */
+        if (cpu_class_is_omap2())
                 omap2_disable_irq_lch(lch);
 
-                /* Clear the CSR register and IRQ status register */
-                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
-                p->dma_write(1 << lch, IRQSTATUS_L0, lch);
+        /* Disable all DMA interrupts for the channel. */
+        omap_disable_channel_irq(lch);
 
-                /* Disable all DMA interrupts for the channel. */
-                p->dma_write(0, CICR, lch);
+        /* Make sure the DMA transfer is stopped. */
+        p->dma_write(0, CCR, lch);
 
-                /* Make sure the DMA transfer is stopped. */
-                p->dma_write(0, CCR, lch);
+        /* Clear registers */
+        if (cpu_class_is_omap2())
                 omap_clear_dma(lch);
-        }
 
         spin_lock_irqsave(&dma_chan_lock, flags);
         dma_chan[lch].dev_id = -1;
@@ -943,8 +941,7 @@ void omap_stop_dma(int lch)
         u32 l;
 
         /* Disable all interrupts on the channel */
-        if (cpu_class_is_omap1())
-                p->dma_write(0, CICR, lch);
+        omap_disable_channel_irq(lch);
 
         l = p->dma_read(CCR, lch);
         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 3b0cfeb33d0..938b50a3343 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -37,14 +37,16 @@
 
 #include <linux/module.h>
 #include <linux/io.h>
-#include <linux/slab.h>
+#include <linux/device.h>
 #include <linux/err.h>
 #include <linux/pm_runtime.h>
 
 #include <plat/dmtimer.h>
+#include <plat/omap-pm.h>
 
 #include <mach/hardware.h>
 
+static u32 omap_reserved_systimers;
 static LIST_HEAD(omap_timer_list);
 static DEFINE_SPINLOCK(dm_timer_lock);
 
@@ -133,17 +135,22 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
 
 int omap_dm_timer_prepare(struct omap_dm_timer *timer)
 {
-        struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
         int ret;
 
-        timer->fclk = clk_get(&timer->pdev->dev, "fck");
-        if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
-                timer->fclk = NULL;
-                dev_err(&timer->pdev->dev, ": No fclk handle.\n");
-                return -EINVAL;
+        /*
+         * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
+         * do not call clk_get() for these devices.
+         */
+        if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
+                timer->fclk = clk_get(&timer->pdev->dev, "fck");
+                if (WARN_ON_ONCE(IS_ERR_OR_NULL(timer->fclk))) {
+                        timer->fclk = NULL;
+                        dev_err(&timer->pdev->dev, ": No fclk handle.\n");
+                        return -EINVAL;
+                }
         }
 
-        if (pdata->needs_manual_reset)
+        if (timer->capability & OMAP_TIMER_NEEDS_RESET)
                 omap_dm_timer_reset(timer);
 
         ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
@@ -152,6 +159,21 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer)
         return ret;
 }
 
+static inline u32 omap_dm_timer_reserved_systimer(int id)
+{
+        return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
+}
+
+int omap_dm_timer_reserve_systimer(int id)
+{
+        if (omap_dm_timer_reserved_systimer(id))
+                return -ENODEV;
+
+        omap_reserved_systimers |= (1 << (id - 1));
+
+        return 0;
+}
+
 struct omap_dm_timer *omap_dm_timer_request(void)
 {
         struct omap_dm_timer *timer = NULL, *t;
@@ -167,6 +189,7 @@ struct omap_dm_timer *omap_dm_timer_request(void)
                 timer->reserved = 1;
                 break;
         }
+        spin_unlock_irqrestore(&dm_timer_lock, flags);
 
         if (timer) {
                 ret = omap_dm_timer_prepare(timer);
@@ -175,7 +198,6 @@ struct omap_dm_timer *omap_dm_timer_request(void)
                         timer = NULL;
                 }
         }
-        spin_unlock_irqrestore(&dm_timer_lock, flags);
 
         if (!timer)
                 pr_debug("%s: timer request failed!\n", __func__);
@@ -198,6 +220,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
                         break;
                 }
         }
+        spin_unlock_irqrestore(&dm_timer_lock, flags);
 
         if (timer) {
                 ret = omap_dm_timer_prepare(timer);
@@ -206,7 +229,6 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
                         timer = NULL;
                 }
         }
-        spin_unlock_irqrestore(&dm_timer_lock, flags);
 
         if (!timer)
                 pr_debug("%s: timer%d request failed!\n", __func__, id);
@@ -236,7 +258,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
 
 void omap_dm_timer_disable(struct omap_dm_timer *timer)
 {
-        pm_runtime_put(&timer->pdev->dev);
+        pm_runtime_put_sync(&timer->pdev->dev);
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
 
@@ -325,10 +347,9 @@ int omap_dm_timer_start(struct omap_dm_timer *timer)
 
         omap_dm_timer_enable(timer);
 
-        if (timer->loses_context) {
-                u32 ctx_loss_cnt_after =
-                        timer->get_context_loss_count(&timer->pdev->dev);
-                if (ctx_loss_cnt_after != timer->ctx_loss_count)
+        if (!(timer->capability & OMAP_TIMER_ALWON)) {
+                if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
+                                timer->ctx_loss_count)
                         omap_timer_restore_context(timer);
         }
 
@@ -347,20 +368,18 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start);
 int omap_dm_timer_stop(struct omap_dm_timer *timer)
 {
         unsigned long rate = 0;
-        struct dmtimer_platform_data *pdata;
 
         if (unlikely(!timer))
                 return -EINVAL;
 
-        pdata = timer->pdev->dev.platform_data;
-        if (!pdata->needs_manual_reset)
+        if (!(timer->capability & OMAP_TIMER_NEEDS_RESET))
                 rate = clk_get_rate(timer->fclk);
 
         __omap_dm_timer_stop(timer, timer->posted, rate);
 
-        if (timer->loses_context && timer->get_context_loss_count)
+        if (!(timer->capability & OMAP_TIMER_ALWON))
                 timer->ctx_loss_count =
-                        timer->get_context_loss_count(&timer->pdev->dev);
+                        omap_pm_get_dev_context_loss_count(&timer->pdev->dev);
 
         /*
          * Since the register values are computed and written within
@@ -378,6 +397,8 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
 {
         int ret;
+        char *parent_name = NULL;
+        struct clk *fclk, *parent;
         struct dmtimer_platform_data *pdata;
 
         if (unlikely(!timer))
@@ -388,7 +409,49 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
         if (source < 0 || source >= 3)
                 return -EINVAL;
 
-        ret = pdata->set_timer_src(timer->pdev, source);
+        /*
+         * FIXME: Used for OMAP1 devices only because they do not currently
+         * use the clock framework to set the parent clock. To be removed
+         * once OMAP1 migrated to using clock framework for dmtimers
+         */
+        if (pdata->set_timer_src)
+                return pdata->set_timer_src(timer->pdev, source);
+
+        fclk = clk_get(&timer->pdev->dev, "fck");
+        if (IS_ERR_OR_NULL(fclk)) {
+                pr_err("%s: fck not found\n", __func__);
+                return -EINVAL;
+        }
+
+        switch (source) {
+        case OMAP_TIMER_SRC_SYS_CLK:
+                parent_name = "timer_sys_ck";
+                break;
+
+        case OMAP_TIMER_SRC_32_KHZ:
+                parent_name = "timer_32k_ck";
+                break;
+
+        case OMAP_TIMER_SRC_EXT_CLK:
+                parent_name = "timer_ext_ck";
+                break;
+        }
+
+        parent = clk_get(&timer->pdev->dev, parent_name);
+        if (IS_ERR_OR_NULL(parent)) {
+                pr_err("%s: %s not found\n", __func__, parent_name);
+                ret = -EINVAL;
+                goto out;
+        }
+
+        ret = clk_set_parent(fclk, parent);
+        if (IS_ERR_VALUE(ret))
+                pr_err("%s: failed to set %s as parent\n", __func__,
+                        parent_name);
+
+        clk_put(parent);
+out:
+        clk_put(fclk);
 
         return ret;
 }
@@ -431,10 +494,9 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
 
         omap_dm_timer_enable(timer);
 
-        if (timer->loses_context) {
-                u32 ctx_loss_cnt_after =
-                        timer->get_context_loss_count(&timer->pdev->dev);
-                if (ctx_loss_cnt_after != timer->ctx_loss_count)
+        if (!(timer->capability & OMAP_TIMER_ALWON)) {
+                if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) !=
+                                timer->ctx_loss_count)
                         omap_timer_restore_context(timer);
         }
 
@@ -627,68 +689,57 @@ EXPORT_SYMBOL_GPL(omap_dm_timers_active);
  */
 static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
 {
-        int ret;
         unsigned long flags;
         struct omap_dm_timer *timer;
-        struct resource *mem, *irq, *ioarea;
+        struct resource *mem, *irq;
+        struct device *dev = &pdev->dev;
         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
 
         if (!pdata) {
-                dev_err(&pdev->dev, "%s: no platform data.\n", __func__);
+                dev_err(dev, "%s: no platform data.\n", __func__);
                 return -ENODEV;
         }
 
         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
         if (unlikely(!irq)) {
-                dev_err(&pdev->dev, "%s: no IRQ resource.\n", __func__);
+                dev_err(dev, "%s: no IRQ resource.\n", __func__);
                 return -ENODEV;
         }
 
         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (unlikely(!mem)) {
-                dev_err(&pdev->dev, "%s: no memory resource.\n", __func__);
+                dev_err(dev, "%s: no memory resource.\n", __func__);
                 return -ENODEV;
         }
 
-        ioarea = request_mem_region(mem->start, resource_size(mem),
-                        pdev->name);
-        if (!ioarea) {
-                dev_err(&pdev->dev, "%s: region already claimed.\n", __func__);
-                return -EBUSY;
-        }
-
-        timer = kzalloc(sizeof(struct omap_dm_timer), GFP_KERNEL);
+        timer = devm_kzalloc(dev, sizeof(struct omap_dm_timer), GFP_KERNEL);
         if (!timer) {
-                dev_err(&pdev->dev, "%s: no memory for omap_dm_timer.\n",
-                        __func__);
-                ret = -ENOMEM;
-                goto err_free_ioregion;
+                dev_err(dev, "%s: memory alloc failed!\n", __func__);
+                return  -ENOMEM;
         }
 
-        timer->io_base = ioremap(mem->start, resource_size(mem));
+        timer->io_base = devm_request_and_ioremap(dev, mem);
         if (!timer->io_base) {
-                dev_err(&pdev->dev, "%s: ioremap failed.\n", __func__);
-                ret = -ENOMEM;
-                goto err_free_mem;
+                dev_err(dev, "%s: region already claimed.\n", __func__);
+                return -ENOMEM;
         }
 
         timer->id = pdev->id;
         timer->irq = irq->start;
-        timer->reserved = pdata->reserved;
+        timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
         timer->pdev = pdev;
-        timer->loses_context = pdata->loses_context;
-        timer->get_context_loss_count = pdata->get_context_loss_count;
+        timer->capability = pdata->timer_capability;
 
         /* Skip pm_runtime_enable for OMAP1 */
-        if (!pdata->needs_manual_reset) {
-                pm_runtime_enable(&pdev->dev);
-                pm_runtime_irq_safe(&pdev->dev);
+        if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
+                pm_runtime_enable(dev);
+                pm_runtime_irq_safe(dev);
         }
 
         if (!timer->reserved) {
-                pm_runtime_get_sync(&pdev->dev);
+                pm_runtime_get_sync(dev);
                 __omap_dm_timer_init_regs(timer);
-                pm_runtime_put(&pdev->dev);
+                pm_runtime_put(dev);
         }
 
         /* add the timer element to the list */
@@ -696,17 +747,9 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
         list_add_tail(&timer->node, &omap_timer_list);
         spin_unlock_irqrestore(&dm_timer_lock, flags);
 
-        dev_dbg(&pdev->dev, "Device Probed.\n");
+        dev_dbg(dev, "Device Probed.\n");
 
         return 0;
-
-err_free_mem:
-        kfree(timer);
-
-err_free_ioregion:
-        release_mem_region(mem->start, resource_size(mem));
-
-        return ret;
 }
 
 /**
@@ -727,7 +770,6 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
         list_for_each_entry(timer, &omap_timer_list, node)
                 if (timer->pdev->id == pdev->id) {
                         list_del(&timer->node);
-                        kfree(timer);
                         ret = 0;
                         break;
                 }
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 4814c5b6530..e62f20a5c0a 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -57,44 +57,6 @@ struct omap_camera_sensor_config {
         int (*power_off)(void * data);
 };
 
-struct omap_usb_config {
-        /* Configure drivers according to the connectors on your board:
-         *  - "A" connector (rectagular)
-         *      ... for host/OHCI use, set "register_host".
-         *  - "B" connector (squarish) or "Mini-B"
-         *      ... for device/gadget use, set "register_dev".
-         *  - "Mini-AB" connector (very similar to Mini-B)
-         *      ... for OTG use as device OR host, initialize "otg"
-         */
-        unsigned        register_host:1;
-        unsigned        register_dev:1;
-        u8              otg;    /* port number, 1-based:  usb1 == 2 */
-
-        u8              hmc_mode;
-
-        /* implicitly true if otg:  host supports remote wakeup? */
-        u8              rwc;
-
-        /* signaling pins used to talk to transceiver on usbN:
-         *  0 == usbN unused
-         *  2 == usb0-only, using internal transceiver
-         *  3 == 3 wire bidirectional
-         *  4 == 4 wire bidirectional
-         *  6 == 6 wire unidirectional (or TLL)
-         */
-        u8              pins[3];
-
-        struct platform_device *udc_device;
-        struct platform_device *ohci_device;
-        struct platform_device *otg_device;
-
-        u32 (*usb0_init)(unsigned nwires, unsigned is_device);
-        u32 (*usb1_init)(unsigned nwires);
-        u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
-
-        int (*ocpi_enable)(void);
-};
-
 struct omap_lcd_config {
         char panel_name[16];
         char ctrl_name[16];
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index d0ed8c443a6..025d85a3ee8 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -39,6 +39,7 @@ struct omap_clk {
 #define CK_443X         (1 << 11)
 #define CK_TI816X       (1 << 12)
 #define CK_446X         (1 << 13)
+#define CK_AM33XX       (1 << 14)       /* AM33xx specific clocks */
 #define CK_1710         (1 << 15)       /* 1710 extra for rate selection */
 
 
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index d0ef57c1d71..656b9862279 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -156,7 +156,6 @@ struct dpll_data {
         u8                      min_divider;
         u16                     max_divider;
         u8                      modes;
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
         void __iomem            *autoidle_reg;
         void __iomem            *idlest_reg;
         u32                     autoidle_mask;
@@ -167,7 +166,6 @@ struct dpll_data {
         u8                      auto_recal_bit;
         u8                      recal_en_bit;
         u8                      recal_st_bit;
-#  endif
         u8                      flags;
 };
 
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index de6c0a08f46..bb5d08a70db 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -9,7 +9,7 @@
  *
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
- * Added OMAP4 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -70,6 +70,7 @@ unsigned int omap_rev(void);
  * cpu_is_omap443x():   True for OMAP4430
  * cpu_is_omap446x():   True for OMAP4460
  * cpu_is_omap447x():   True for OMAP4470
+ * soc_is_omap543x():   True for OMAP5430, OMAP5432
  */
 #define GET_OMAP_CLASS  (omap_rev() & 0xff)
 
@@ -122,6 +123,7 @@ IS_OMAP_CLASS(24xx, 0x24)
 IS_OMAP_CLASS(34xx, 0x34)
 IS_OMAP_CLASS(44xx, 0x44)
 IS_AM_CLASS(35xx, 0x35)
+IS_OMAP_CLASS(54xx, 0x54)
 IS_AM_CLASS(33xx, 0x33)
 
 IS_TI_CLASS(81xx, 0x81)
@@ -133,6 +135,7 @@ IS_OMAP_SUBCLASS(363x, 0x363)
 IS_OMAP_SUBCLASS(443x, 0x443)
 IS_OMAP_SUBCLASS(446x, 0x446)
 IS_OMAP_SUBCLASS(447x, 0x447)
+IS_OMAP_SUBCLASS(543x, 0x543)
 
 IS_TI_SUBCLASS(816x, 0x816)
 IS_TI_SUBCLASS(814x, 0x814)
@@ -150,12 +153,14 @@ IS_AM_SUBCLASS(335x, 0x335)
 #define cpu_is_ti816x()                 0
 #define cpu_is_ti814x()                 0
 #define soc_is_am35xx()                 0
-#define cpu_is_am33xx()                 0
-#define cpu_is_am335x()                 0
+#define soc_is_am33xx()                 0
+#define soc_is_am335x()                 0
 #define cpu_is_omap44xx()               0
 #define cpu_is_omap443x()               0
 #define cpu_is_omap446x()               0
 #define cpu_is_omap447x()               0
+#define soc_is_omap54xx()               0
+#define soc_is_omap543x()               0
 
 #if defined(MULTI_OMAP1)
 # if defined(CONFIG_ARCH_OMAP730)
@@ -238,9 +243,7 @@ IS_AM_SUBCLASS(335x, 0x335)
 /*
  * Macros to detect individual cpu types.
  * These are only rarely needed.
- * cpu_is_omap330():    True for OMAP330
- * cpu_is_omap730():    True for OMAP730
- * cpu_is_omap850():    True for OMAP850
+ * cpu_is_omap310():    True for OMAP310
  * cpu_is_omap1510():   True for OMAP1510
  * cpu_is_omap1610():   True for OMAP1610
  * cpu_is_omap1611():   True for OMAP1611
@@ -262,8 +265,6 @@ static inline int is_omap ##type (void)			\
 }
 
 IS_OMAP_TYPE(310, 0x0310)
-IS_OMAP_TYPE(730, 0x0730)
-IS_OMAP_TYPE(850, 0x0850)
 IS_OMAP_TYPE(1510, 0x1510)
 IS_OMAP_TYPE(1610, 0x1610)
 IS_OMAP_TYPE(1611, 0x1611)
@@ -277,8 +278,6 @@ IS_OMAP_TYPE(2430, 0x2430)
 IS_OMAP_TYPE(3430, 0x3430)
 
 #define cpu_is_omap310()                0
-#define cpu_is_omap730()                0
-#define cpu_is_omap850()                0
 #define cpu_is_omap1510()               0
 #define cpu_is_omap1610()               0
 #define cpu_is_omap5912()               0
@@ -291,22 +290,13 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define cpu_is_omap2430()               0
 #define cpu_is_omap3430()               0
 #define cpu_is_omap3630()               0
+#define soc_is_omap5430()               0
 
 /*
  * Whether we have MULTI_OMAP1 or not, we still need to distinguish
- * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
+ * between 310 vs. 1510 and 1611B/5912 vs. 1710.
  */
 
-#if defined(CONFIG_ARCH_OMAP730)
-# undef  cpu_is_omap730
-# define cpu_is_omap730()               is_omap730()
-#endif
-
-#if defined(CONFIG_ARCH_OMAP850)
-# undef  cpu_is_omap850
-# define cpu_is_omap850()               is_omap850()
-#endif
-
 #if defined(CONFIG_ARCH_OMAP15XX)
 # undef  cpu_is_omap310
 # undef  cpu_is_omap1510
@@ -344,8 +334,6 @@ IS_OMAP_TYPE(3430, 0x3430)
 # undef cpu_is_ti816x
 # undef cpu_is_ti814x
 # undef soc_is_am35xx
-# undef cpu_is_am33xx
-# undef cpu_is_am335x
 # define cpu_is_omap3430()              is_omap3430()
 # undef cpu_is_omap3630
 # define cpu_is_omap3630()              is_omap363x()
@@ -353,8 +341,13 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define cpu_is_ti816x()                is_ti816x()
 # define cpu_is_ti814x()                is_ti814x()
 # define soc_is_am35xx()                is_am35xx()
-# define cpu_is_am33xx()                is_am33xx()
-# define cpu_is_am335x()                is_am335x()
+#endif
+
+# if defined(CONFIG_SOC_AM33XX)
+# undef soc_is_am33xx
+# undef soc_is_am335x
+# define soc_is_am33xx()                is_am33xx()
+# define soc_is_am335x()                is_am335x()
 #endif
 
 # if defined(CONFIG_ARCH_OMAP4)
@@ -368,11 +361,19 @@ IS_OMAP_TYPE(3430, 0x3430)
 # define cpu_is_omap447x()              is_omap447x()
 # endif
 
+# if defined(CONFIG_SOC_OMAP5)
+# undef soc_is_omap54xx
+# undef soc_is_omap543x
+# define soc_is_omap54xx()              is_omap54xx()
+# define soc_is_omap543x()              is_omap543x()
+#endif
+
 /* Macros to detect if we have OMAP1 or OMAP2 */
 #define cpu_class_is_omap1()    (cpu_is_omap7xx() || cpu_is_omap15xx() || \
                                 cpu_is_omap16xx())
 #define cpu_class_is_omap2()    (cpu_is_omap24xx() || cpu_is_omap34xx() || \
-                                cpu_is_omap44xx())
+                                cpu_is_omap44xx() || soc_is_omap54xx() || \
+                                soc_is_am33xx())
 
 /* Various silicon revisions for omap2 */
 #define OMAP242X_CLASS          0x24200024
@@ -408,7 +409,7 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define AM35XX_REV_ES1_0        AM35XX_CLASS
 #define AM35XX_REV_ES1_1        (AM35XX_CLASS | (0x1 << 8))
 
-#define AM335X_CLASS            0x33500034
+#define AM335X_CLASS            0x33500033
 #define AM335X_REV_ES1_0        AM335X_CLASS
 
 #define OMAP443X_CLASS          0x44300044
@@ -425,9 +426,14 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP447X_CLASS          0x44700044
 #define OMAP4470_REV_ES1_0      (OMAP447X_CLASS | (0x10 << 8))
 
+#define OMAP54XX_CLASS          0x54000054
+#define OMAP5430_REV_ES1_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x10 << 8))
+#define OMAP5432_REV_ES1_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
+
 void omap2xxx_check_revision(void);
 void omap3xxx_check_revision(void);
 void omap4xxx_check_revision(void);
+void omap5xxx_check_revision(void);
 void omap3xxx_check_features(void);
 void ti81xx_check_features(void);
 void omap4xxx_check_features(void);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 5da73562e48..19e7fa577bd 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -55,23 +55,17 @@
 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
 
-/*
- * IP revision identifier so that Highlander IP
- * in OMAP4 can be distinguished.
- */
-#define OMAP_TIMER_IP_VERSION_1                        0x1
-
 /* timer capabilities used in hwmod database */
 #define OMAP_TIMER_SECURE                               0x80000000
 #define OMAP_TIMER_ALWON                                0x40000000
 #define OMAP_TIMER_HAS_PWM                              0x20000000
+#define OMAP_TIMER_NEEDS_RESET                          0x10000000
 
 struct omap_timer_capability_dev_attr {
         u32 timer_capability;
 };
 
 struct omap_dm_timer;
-struct clk;
 
 struct timer_regs {
         u32 tidr;
@@ -96,16 +90,12 @@ struct timer_regs {
 };
 
 struct dmtimer_platform_data {
+        /* set_timer_src - Only used for OMAP1 devices */
         int (*set_timer_src)(struct platform_device *pdev, int source);
-        int timer_ip_version;
-        u32 needs_manual_reset:1;
-        bool reserved;
-
-        bool loses_context;
-
-        int (*get_context_loss_count)(struct device *dev);
+        u32 timer_capability;
 };
 
+int omap_dm_timer_reserve_systimer(int id);
 struct omap_dm_timer *omap_dm_timer_request(void);
 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
 int omap_dm_timer_free(struct omap_dm_timer *timer);
@@ -272,13 +262,11 @@ struct omap_dm_timer {
         unsigned reserved:1;
         unsigned posted:1;
         struct timer_regs context;
-        bool loses_context;
         int ctx_loss_count;
         int revision;
+        u32 capability;
         struct platform_device *pdev;
         struct list_head node;
-
-        int (*get_context_loss_count)(struct device *dev);
 };
 
 int omap_dm_timer_prepare(struct omap_dm_timer *timer);
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h
index 9c604b390f9..5927709b190 100644
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ b/arch/arm/plat-omap/include/plat/dsp.h
@@ -18,6 +18,9 @@ struct omap_dsp_platform_data {
         u32 (*dsp_cm_read)(s16 , u16);
         u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
 
+        void (*set_bootaddr)(u32);
+        void (*set_bootmode)(u8);
+
         phys_addr_t phys_mempool_base;
         phys_addr_t phys_mempool_size;
 };
diff --git a/arch/arm/plat-omap/include/plat/hardware.h b/arch/arm/plat-omap/include/plat/hardware.h
index e897978371c..ddbde38e1e3 100644
--- a/arch/arm/plat-omap/include/plat/hardware.h
+++ b/arch/arm/plat-omap/include/plat/hardware.h
@@ -288,5 +288,6 @@
 #include <plat/omap44xx.h>
 #include <plat/ti81xx.h>
 #include <plat/am33xx.h>
+#include <plat/omap54xx.h>
 
 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index 5493bd95da5..eb3e4d55534 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -81,8 +81,6 @@ struct omap_mmc_platform_data {
         /* Return context loss count due to PM states changing */
         int (*get_context_loss_count)(struct device *dev);
 
-        u64 dma_mask;
-
         /* Integrating attributes from the omap_hwmod layer */
         u8 controller_flags;
 
diff --git a/arch/arm/plat-omap/include/plat/multi.h b/arch/arm/plat-omap/include/plat/multi.h
index 999ffba2690..324d31b1485 100644
--- a/arch/arm/plat-omap/include/plat/multi.h
+++ b/arch/arm/plat-omap/include/plat/multi.h
@@ -99,4 +99,22 @@
 # endif
 #endif
 
+#ifdef CONFIG_SOC_OMAP5
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME omap5
+# endif
+#endif
+
+#ifdef CONFIG_SOC_AM33XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP2
+#  define MULTI_OMAP2
+# else
+#  define OMAP_NAME am33xx
+# endif
+#endif
+
 #endif  /* __PLAT_OMAP_MULTI_H */
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index aeba71796ad..32394895920 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -99,7 +99,7 @@
 
 /*
  * OMAP730/850 has a slightly different config for the pin mux.
- * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
+ * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and
  *   not the FUNC_MUX_CTRL_x regs from hardware.h
  * - for pull-up/down, only has one enable bit which is is in the same register
  *   as mux config
diff --git a/arch/arm/plat-omap/include/plat/omap-secure.h b/arch/arm/plat-omap/include/plat/omap-secure.h
index 8c7994ce986..0e4acd2d2de 100644
--- a/arch/arm/plat-omap/include/plat/omap-secure.h
+++ b/arch/arm/plat-omap/include/plat/omap-secure.h
@@ -3,12 +3,7 @@
 
 #include <linux/types.h>
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 extern int omap_secure_ram_reserve_memblock(void);
-#else
-static inline void omap_secure_ram_reserve_memblock(void)
-{ }
-#endif
 
 #ifdef CONFIG_OMAP4_ERRATA_I688
 extern int omap_barrier_reserve_memblock(void);
diff --git a/arch/arm/plat-omap/include/plat/omap54xx.h b/arch/arm/plat-omap/include/plat/omap54xx.h
new file mode 100644
index 00000000000..a2582bb3cab
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/omap54xx.h
@@ -0,0 +1,32 @@
+/*:
+ * Address mappings and base address for OMAP5 interconnects
+ * and peripherals.
+ *
+ * Copyright (C) 2012 Texas Instruments
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *      Sricharan <r.sricharan@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_SOC_OMAP54XX_H
+#define __ASM_SOC_OMAP54XX_H
+
+/*
+ * Please place only base defines here and put the rest in device
+ * specific headers.
+ */
+#define L4_54XX_BASE                    0x4a000000
+#define L4_WK_54XX_BASE                 0x4ae00000
+#define L4_PER_54XX_BASE                0x48000000
+#define L3_54XX_BASE                    0x44000000
+#define OMAP54XX_32KSYNCT_BASE          0x4ae04000
+#define OMAP54XX_CM_CORE_AON_BASE       0x4a004000
+#define OMAP54XX_CM_CORE_BASE           0x4a008000
+#define OMAP54XX_PRM_BASE               0x4ae06000
+#define OMAP54XX_PRCM_MPU_BASE          0x48243000
+#define OMAP54XX_SCM_BASE               0x4a002000
+#define OMAP54XX_CTRL_BASE              0x4a002800
+
+#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/plat-omap/include/plat/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h
deleted file mode 100644
index 14272bc1a6f..00000000000
--- a/arch/arm/plat-omap/include/plat/omap730.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* arch/arm/plat-omap/include/mach/omap730.h
- *
- * Hardware definitions for TI OMAP730 processor.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP730_H
-#define __ASM_ARCH_OMAP730_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP730_DSP_BASE        0xE0000000
-#define OMAP730_DSP_SIZE        0x50000
-#define OMAP730_DSP_START       0xE0000000
-
-#define OMAP730_DSPREG_BASE     0xE1000000
-#define OMAP730_DSPREG_SIZE     SZ_128K
-#define OMAP730_DSPREG_START    0xE1000000
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 specific configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_CONFIG_BASE     0xfffe1000
-#define OMAP730_IO_CONF_0       0xfffe1070
-#define OMAP730_IO_CONF_1       0xfffe1074
-#define OMAP730_IO_CONF_2       0xfffe1078
-#define OMAP730_IO_CONF_3       0xfffe107c
-#define OMAP730_IO_CONF_4       0xfffe1080
-#define OMAP730_IO_CONF_5       0xfffe1084
-#define OMAP730_IO_CONF_6       0xfffe1088
-#define OMAP730_IO_CONF_7       0xfffe108c
-#define OMAP730_IO_CONF_8       0xfffe1090
-#define OMAP730_IO_CONF_9       0xfffe1094
-#define OMAP730_IO_CONF_10      0xfffe1098
-#define OMAP730_IO_CONF_11      0xfffe109c
-#define OMAP730_IO_CONF_12      0xfffe10a0
-#define OMAP730_IO_CONF_13      0xfffe10a4
-
-#define OMAP730_MODE_1          0xfffe1010
-#define OMAP730_MODE_2          0xfffe1014
-
-/* CSMI specials: in terms of base + offset */
-#define OMAP730_MODE2_OFFSET    0x14
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 traffic controller configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_FLASH_CFG_0     0xfffecc10
-#define OMAP730_FLASH_ACFG_0    0xfffecc50
-#define OMAP730_FLASH_CFG_1     0xfffecc14
-#define OMAP730_FLASH_ACFG_1    0xfffecc54
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 DSP control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_ICR_BASE        0xfffbb800
-#define OMAP730_DSP_M_CTL       0xfffbb804
-#define OMAP730_DSP_MMU_BASE    0xfffed200
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 PCC_UPLD configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_PCC_UPLD_CTRL_BASE      (0xfffe0900)
-#define OMAP730_PCC_UPLD_CTRL           (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
-
-#endif /*  __ASM_ARCH_OMAP730_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h
deleted file mode 100644
index c33f6798171..00000000000
--- a/arch/arm/plat-omap/include/plat/omap850.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* arch/arm/plat-omap/include/mach/omap850.h
- *
- * Hardware definitions for TI OMAP850 processor.
- *
- * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP850_H
-#define __ASM_ARCH_OMAP850_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP850_DSP_BASE        0xE0000000
-#define OMAP850_DSP_SIZE        0x50000
-#define OMAP850_DSP_START       0xE0000000
-
-#define OMAP850_DSPREG_BASE     0xE1000000
-#define OMAP850_DSPREG_SIZE     SZ_128K
-#define OMAP850_DSPREG_START    0xE1000000
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 specific configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_CONFIG_BASE     0xfffe1000
-#define OMAP850_IO_CONF_0       0xfffe1070
-#define OMAP850_IO_CONF_1       0xfffe1074
-#define OMAP850_IO_CONF_2       0xfffe1078
-#define OMAP850_IO_CONF_3       0xfffe107c
-#define OMAP850_IO_CONF_4       0xfffe1080
-#define OMAP850_IO_CONF_5       0xfffe1084
-#define OMAP850_IO_CONF_6       0xfffe1088
-#define OMAP850_IO_CONF_7       0xfffe108c
-#define OMAP850_IO_CONF_8       0xfffe1090
-#define OMAP850_IO_CONF_9       0xfffe1094
-#define OMAP850_IO_CONF_10      0xfffe1098
-#define OMAP850_IO_CONF_11      0xfffe109c
-#define OMAP850_IO_CONF_12      0xfffe10a0
-#define OMAP850_IO_CONF_13      0xfffe10a4
-
-#define OMAP850_MODE_1          0xfffe1010
-#define OMAP850_MODE_2          0xfffe1014
-
-/* CSMI specials: in terms of base + offset */
-#define OMAP850_MODE2_OFFSET    0x14
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 traffic controller configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_FLASH_CFG_0     0xfffecc10
-#define OMAP850_FLASH_ACFG_0    0xfffecc50
-#define OMAP850_FLASH_CFG_1     0xfffecc14
-#define OMAP850_FLASH_ACFG_1    0xfffecc54
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 DSP control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_ICR_BASE        0xfffbb800
-#define OMAP850_DSP_M_CTL       0xfffbb804
-#define OMAP850_DSP_MMU_BASE    0xfffed200
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 PCC_UPLD configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_PCC_UPLD_CTRL_BASE      (0xfffe0900)
-#define OMAP850_PCC_UPLD_CTRL           (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
-
-#endif /*  __ASM_ARCH_OMAP850_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index c835b7194ff..6132972aff3 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -41,6 +41,7 @@ struct omap_device;
 
 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type1;
 extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
+extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type3;
 
 /*
  * OCP SYSCONFIG bit shifts/masks TYPE1. These are for IPs compliant
@@ -69,6 +70,17 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
 #define SYSC_TYPE2_SIDLEMODE_MASK       (0x3 << SYSC_TYPE2_SIDLEMODE_SHIFT)
 #define SYSC_TYPE2_MIDLEMODE_SHIFT      4
 #define SYSC_TYPE2_MIDLEMODE_MASK       (0x3 << SYSC_TYPE2_MIDLEMODE_SHIFT)
+#define SYSC_TYPE2_DMADISABLE_SHIFT     16
+#define SYSC_TYPE2_DMADISABLE_MASK      (0x1 << SYSC_TYPE2_DMADISABLE_SHIFT)
+
+/*
+ * OCP SYSCONFIG bit shifts/masks TYPE3.
+ * This is applicable for some IPs present in AM33XX
+ */
+#define SYSC_TYPE3_SIDLEMODE_SHIFT      0
+#define SYSC_TYPE3_SIDLEMODE_MASK       (0x3 << SYSC_TYPE3_SIDLEMODE_SHIFT)
+#define SYSC_TYPE3_MIDLEMODE_SHIFT      2
+#define SYSC_TYPE3_MIDLEMODE_MASK       (0x3 << SYSC_TYPE3_MIDLEMODE_SHIFT)
 
 /* OCP SYSSTATUS bit shifts/masks */
 #define SYSS_RESETDONE_SHIFT            0
@@ -283,6 +295,7 @@ struct omap_hwmod_ocp_if {
 #define SYSS_HAS_RESET_STATUS   (1 << 7)
 #define SYSC_NO_CACHE           (1 << 8)  /* XXX SW flag, belongs elsewhere */
 #define SYSC_HAS_RESET_STATUS   (1 << 9)
+#define SYSC_HAS_DMADISABLE     (1 << 10)
 
 /* omap_hwmod_sysconfig.clockact flags */
 #define CLOCKACT_TEST_BOTH      0x0
@@ -298,6 +311,7 @@ struct omap_hwmod_ocp_if {
  * @enwkup_shift: Offset of the enawakeup bit
  * @srst_shift: Offset of the softreset bit
  * @autoidle_shift: Offset of the autoidle bit
+ * @dmadisable_shift: Offset of the dmadisable bit
  */
 struct omap_hwmod_sysc_fields {
         u8 midle_shift;
@@ -306,6 +320,7 @@ struct omap_hwmod_sysc_fields {
         u8 enwkup_shift;
         u8 srst_shift;
         u8 autoidle_shift;
+        u8 dmadisable_shift;
 };
 
 /**
@@ -374,11 +389,13 @@ struct omap_hwmod_omap2_prcm {
  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
  * @clkctrl_reg: PRCM address of the clock control register
  * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
+ * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
  * @submodule_wkdep_bit: bit shift of the WKDEP range
  */
 struct omap_hwmod_omap4_prcm {
         u16             clkctrl_offs;
         u16             rstctrl_offs;
+        u16             rstst_offs;
         u16             context_offs;
         u8              submodule_wkdep_bit;
         u8              modulemode;
@@ -629,6 +646,10 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
 
 int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
 
+extern void __init omap_hwmod_init(void);
+
+const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
+
 /*
  * Chip variant-specific hwmod init routines - XXX should be converted
  * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index 9bb978ecd88..36d6a766621 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -123,7 +123,7 @@ struct omap_sdrc_params {
         u32 mr;
 };
 
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#ifdef CONFIG_SOC_HAS_OMAP2_SDRC
 void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                             struct omap_sdrc_params *sdrc_cs1);
 #else
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index b073e5f2b19..65fce44dce3 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -60,6 +60,17 @@
 /* AM3505/3517 UART4 */
 #define AM35XX_UART4_BASE       0x4809E000      /* Only on AM3505/3517 */
 
+/* AM33XX serial port */
+#define AM33XX_UART1_BASE       0x44E09000
+
+/* OMAP5 serial ports */
+#define OMAP5_UART1_BASE        OMAP2_UART1_BASE
+#define OMAP5_UART2_BASE        OMAP2_UART2_BASE
+#define OMAP5_UART3_BASE        OMAP4_UART3_BASE
+#define OMAP5_UART4_BASE        OMAP4_UART4_BASE
+#define OMAP5_UART5_BASE        0x48066000
+#define OMAP5_UART6_BASE        0x48068000
+
 /* External port on Zoom2/3 */
 #define ZOOM_UART_BASE          0x10000000
 #define ZOOM_UART_VIRT          0xfa400000
@@ -93,6 +104,9 @@
 #define TI81XXUART1             81
 #define TI81XXUART2             82
 #define TI81XXUART3             83
+#define AM33XXUART1             84
+#define OMAP5UART3              OMAP4UART3
+#define OMAP5UART4              OMAP4UART4
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 
 /* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index cc3f11ba7a9..7f7b112accc 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -95,6 +95,9 @@ static inline void flush(void)
         _DEBUG_LL_ENTRY(mach, OMAP4_UART##p##_BASE, OMAP_PORT_SHIFT,    \
                 OMAP4UART##p)
 
+#define DEBUG_LL_OMAP5(p, mach)                                         \
+        _DEBUG_LL_ENTRY(mach, OMAP5_UART##p##_BASE, OMAP_PORT_SHIFT,    \
+                OMAP5UART##p)
 /* Zoom2/3 shift is different for UART1 and external port */
 #define DEBUG_LL_ZOOM(mach)                                             \
         _DEBUG_LL_ENTRY(mach, ZOOM_UART_BASE, ZOOM_PORT_SHIFT, ZOOM_UART)
@@ -103,7 +106,11 @@ static inline void flush(void)
         _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
                 TI81XXUART##p)
 
-static inline void __arch_decomp_setup(unsigned long arch_id)
+#define DEBUG_LL_AM33XX(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                AM33XXUART##p)
+
+static inline void arch_decomp_setup(void)
 {
         int port = 0;
 
@@ -173,6 +180,9 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_OMAP4(3, omap_4430sdp);
                 DEBUG_LL_OMAP4(3, omap4_panda);
 
+                /* omap5 based boards using UART3 */
+                DEBUG_LL_OMAP5(3, omap5_sevm);
+
                 /* zoom2/3 external uart */
                 DEBUG_LL_ZOOM(omap_zoom2);
                 DEBUG_LL_ZOOM(omap_zoom3);
@@ -183,11 +193,11 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 /* TI8148 base boards using UART1 */
                 DEBUG_LL_TI81XX(1, ti8148evm);
 
+                /* AM33XX base boards using UART1 */
+                DEBUG_LL_AM33XX(1, am335xevm);
         } while (0);
 }
 
-#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
-
 /*
  * nothing to do
  */
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 762eeb0626c..548a4c8d63d 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -44,6 +44,8 @@ struct usbhs_omap_board_data {
         struct regulator                *regulator[OMAP3_HS_USB_PORTS];
 };
 
+#ifdef CONFIG_ARCH_OMAP2PLUS
+
 struct ehci_hcd_omap_platform_data {
         enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
         int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
@@ -64,26 +66,6 @@ struct usbhs_omap_platform_data {
 };
 /*-------------------------------------------------------------------------*/
 
-#define OMAP1_OTG_BASE                  0xfffb0400
-#define OMAP1_UDC_BASE                  0xfffb4000
-#define OMAP1_OHCI_BASE                 0xfffba000
-
-#define OMAP2_OHCI_BASE                 0x4805e000
-#define OMAP2_UDC_BASE                  0x4805e200
-#define OMAP2_OTG_BASE                  0x4805e300
-
-#ifdef CONFIG_ARCH_OMAP1
-
-#define OTG_BASE                        OMAP1_OTG_BASE
-#define UDC_BASE                        OMAP1_UDC_BASE
-#define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
-
-#else
-
-#define OTG_BASE                        OMAP2_OTG_BASE
-#define UDC_BASE                        OMAP2_UDC_BASE
-#define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
-
 struct omap_musb_board_data {
         u8      interface_type;
         u8      mode;
@@ -107,44 +89,6 @@ extern int omap4430_phy_init(struct device *dev);
 extern int omap4430_phy_exit(struct device *dev);
 extern int omap4430_phy_suspend(struct device *dev, int suspend);
 
-/*
- * NOTE: Please update omap USB drivers to use ioremap + read/write
- */
-
-#define OMAP2_L4_IO_OFFSET      0xb2000000
-#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
-
-static inline u8 omap_readb(u32 pa)
-{
-        return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline u16 omap_readw(u32 pa)
-{
-        return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline u32 omap_readl(u32 pa)
-{
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline void omap_writeb(u8 v, u32 pa)
-{
-        __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-
-
-static inline void omap_writew(u16 v, u32 pa)
-{
-        __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline void omap_writel(u32 v, u32 pa)
-{
-        __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-
 #endif
 
 extern void am35x_musb_reset(void);
@@ -153,142 +97,6 @@ extern void am35x_musb_clear_irq(void);
 extern void am35x_set_mode(u8 musb_mode);
 extern void ti81xx_musb_phy_power(u8 on);
 
-/*
- * FIXME correct answer depends on hmc_mode,
- * as does (on omap1) any nonzero value for config->otg port number
- */
-#ifdef  CONFIG_USB_GADGET_OMAP
-#define is_usb0_device(config)  1
-#else
-#define is_usb0_device(config)  0
-#endif
-
-void omap_otg_init(struct omap_usb_config *config);
-
-#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
-void omap1_usb_init(struct omap_usb_config *pdata);
-#else
-static inline void omap1_usb_init(struct omap_usb_config *pdata)
-{
-}
-#endif
-
-#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
-void omap2_usbfs_init(struct omap_usb_config *pdata);
-#else
-static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
-{
-}
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * OTG and transceiver registers, for OMAPs starting with ARM926
- */
-#define OTG_REV                         (OTG_BASE + 0x00)
-#define OTG_SYSCON_1                    (OTG_BASE + 0x04)
-#       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
-#       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
-#       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
-#       define   OTG_IDLE_EN            (1 << 15)
-#       define   HST_IDLE_EN            (1 << 14)
-#       define   DEV_IDLE_EN            (1 << 13)
-#       define   OTG_RESET_DONE         (1 << 2)
-#       define   OTG_SOFT_RESET         (1 << 1)
-#define OTG_SYSCON_2                    (OTG_BASE + 0x08)
-#       define   OTG_EN                 (1 << 31)
-#       define   USBX_SYNCHRO           (1 << 30)
-#       define   OTG_MST16              (1 << 29)
-#       define   SRP_GPDATA             (1 << 28)
-#       define   SRP_GPDVBUS            (1 << 27)
-#       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
-#       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
-#       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
-#       define   SRP_DPW                (1 << 14)
-#       define   SRP_DATA               (1 << 13)
-#       define   SRP_VBUS               (1 << 12)
-#       define   OTG_PADEN              (1 << 10)
-#       define   HMC_PADEN              (1 << 9)
-#       define   UHOST_EN               (1 << 8)
-#       define   HMC_TLLSPEED           (1 << 7)
-#       define   HMC_TLLATTACH          (1 << 6)
-#       define   OTG_HMC(w)             (((w)>>0)&0x3f)
-#define OTG_CTRL                        (OTG_BASE + 0x0c)
-#       define   OTG_USB2_EN            (1 << 29)
-#       define   OTG_USB2_DP            (1 << 28)
-#       define   OTG_USB2_DM            (1 << 27)
-#       define   OTG_USB1_EN            (1 << 26)
-#       define   OTG_USB1_DP            (1 << 25)
-#       define   OTG_USB1_DM            (1 << 24)
-#       define   OTG_USB0_EN            (1 << 23)
-#       define   OTG_USB0_DP            (1 << 22)
-#       define   OTG_USB0_DM            (1 << 21)
-#       define   OTG_ASESSVLD           (1 << 20)
-#       define   OTG_BSESSEND           (1 << 19)
-#       define   OTG_BSESSVLD           (1 << 18)
-#       define   OTG_VBUSVLD            (1 << 17)
-#       define   OTG_ID                 (1 << 16)
-#       define   OTG_DRIVER_SEL         (1 << 15)
-#       define   OTG_A_SETB_HNPEN       (1 << 12)
-#       define   OTG_A_BUSREQ           (1 << 11)
-#       define   OTG_B_HNPEN            (1 << 9)
-#       define   OTG_B_BUSREQ           (1 << 8)
-#       define   OTG_BUSDROP            (1 << 7)
-#       define   OTG_PULLDOWN           (1 << 5)
-#       define   OTG_PULLUP             (1 << 4)
-#       define   OTG_DRV_VBUS           (1 << 3)
-#       define   OTG_PD_VBUS            (1 << 2)
-#       define   OTG_PU_VBUS            (1 << 1)
-#       define   OTG_PU_ID              (1 << 0)
-#define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
-#       define   DRIVER_SWITCH          (1 << 15)
-#       define   A_VBUS_ERR             (1 << 13)
-#       define   A_REQ_TMROUT           (1 << 12)
-#       define   A_SRP_DETECT           (1 << 11)
-#       define   B_HNP_FAIL             (1 << 10)
-#       define   B_SRP_TMROUT           (1 << 9)
-#       define   B_SRP_DONE             (1 << 8)
-#       define   B_SRP_STARTED          (1 << 7)
-#       define   OPRT_CHG               (1 << 0)
-#define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
-        // same bits as in IRQ_EN
-#define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
-#       define   OTGVPD                 (1 << 14)
-#       define   OTGVPU                 (1 << 13)
-#       define   OTGPUID                (1 << 12)
-#       define   USB2VDR                (1 << 10)
-#       define   USB2PDEN               (1 << 9)
-#       define   USB2PUEN               (1 << 8)
-#       define   USB1VDR                (1 << 6)
-#       define   USB1PDEN               (1 << 5)
-#       define   USB1PUEN               (1 << 4)
-#       define   USB0VDR                (1 << 2)
-#       define   USB0PDEN               (1 << 1)
-#       define   USB0PUEN               (1 << 0)
-#define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
-#define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
-
-/*-------------------------------------------------------------------------*/
-
-/* OMAP1 */
-#define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
-#       define  CONF_USB2_UNI_R         (1 << 8)
-#       define  CONF_USB1_UNI_R         (1 << 7)
-#       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
-#       define  CONF_USB0_ISOLATE_R     (1 << 3)
-#       define  CONF_USB_PWRDN_DM_R     (1 << 2)
-#       define  CONF_USB_PWRDN_DP_R     (1 << 1)
-
-/* OMAP2 */
-#       define  USB_UNIDIR                      0x0
-#       define  USB_UNIDIR_TLL                  0x1
-#       define  USB_BIDIR                       0x2
-#       define  USB_BIDIR_TLL                   0x3
-#       define  USBTXWRMODEI(port, x)   ((x) << (22 - (port * 2)))
-#       define  USBT2TLL5PI             (1 << 17)
-#       define  USB0PUENACTLOI          (1 << 16)
-#       define  USBSTANDBYCTRL          (1 << 15)
 /* AM35x */
 /* USB 2.0 PHY Control */
 #define CONF2_PHY_GPIOMODE      (1 << 23)
diff --git a/arch/arm/plat-omap/include/plat/voltage.h b/arch/arm/plat-omap/include/plat/voltage.h
index 0a6a482ec01..5be4d5def42 100644
--- a/arch/arm/plat-omap/include/plat/voltage.h
+++ b/arch/arm/plat-omap/include/plat/voltage.h
@@ -11,10 +11,29 @@
 #ifndef __ARCH_ARM_OMAP_VOLTAGE_H
 #define __ARCH_ARM_OMAP_VOLTAGE_H
 
+/**
+ * struct omap_volt_data - Omap voltage specific data.
+ * @voltage_nominal:    The possible voltage value in uV
+ * @sr_efuse_offs:      The offset of the efuse register(from system
+ *                      control module base address) from where to read
+ *                      the n-target value for the smartreflex module.
+ * @sr_errminlimit:     Error min limit value for smartreflex. This value
+ *                      differs at differnet opp and thus is linked
+ *                      with voltage.
+ * @vp_errorgain:       Error gain value for the voltage processor. This
+ *                      field also differs according to the voltage/opp.
+ */
+struct omap_volt_data {
+        u32     volt_nominal;
+        u32     sr_efuse_offs;
+        u8      sr_errminlimit;
+        u8      vp_errgain;
+};
 struct voltagedomain;
 
 struct voltagedomain *voltdm_lookup(const char *name);
 int voltdm_scale(struct voltagedomain *voltdm, unsigned long target_volt);
 unsigned long voltdm_get_voltage(struct voltagedomain *voltdm);
-
+struct omap_volt_data *omap_voltage_get_voltdata(struct voltagedomain *voltdm,
+                unsigned long volt);
 #endif
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index ad32621aa52..5e13c3884aa 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -282,6 +282,8 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
                 }
                 mbox->rxq = mq;
                 mq->mbox = mbox;
+
+                omap_mbox_enable_irq(mbox, IRQ_RX);
         }
         mutex_unlock(&mbox_configured_lock);
         return 0;
@@ -305,6 +307,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
         mutex_lock(&mbox_configured_lock);
 
         if (!--mbox->use_count) {
+                omap_mbox_disable_irq(mbox, IRQ_RX);
                 free_irq(mbox->irq, mbox);
                 tasklet_kill(&mbox->txq->tasklet);
                 flush_work_sync(&mbox->rxq->work);
@@ -338,13 +341,15 @@ struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
         if (!mbox)
                 return ERR_PTR(-ENOENT);
 
-        ret = omap_mbox_startup(mbox);
-        if (ret)
-                return ERR_PTR(-ENODEV);
-
         if (nb)
                 blocking_notifier_chain_register(&mbox->notifier, nb);
 
+        ret = omap_mbox_startup(mbox);
+        if (ret) {
+                blocking_notifier_chain_unregister(&mbox->notifier, nb);
+                return ERR_PTR(-ENODEV);
+        }
+
         return mbox;
 }
 EXPORT_SYMBOL(omap_mbox_get);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 477363c163e..766181cb5c9 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -6,8 +6,8 @@
  * Copyright (C) 2005 Nokia Corporation
  * Written by Tony Lindgren <tony@atomide.com>
  *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Copyright (C) 2009-2012 Texas Instruments
+ * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -44,6 +44,7 @@
 #else
 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
 #endif
+#define OMAP5_SRAM_PA           0x40300000
 
 #if defined(CONFIG_ARCH_OMAP2PLUS)
 #define SRAM_BOOTLOADER_SZ      0x00
@@ -85,7 +86,7 @@ static int is_sram_locked(void)
                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
                 }
-                if (cpu_is_omap34xx() && !cpu_is_am33xx()) {
+                if (cpu_is_omap34xx()) {
                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
@@ -118,12 +119,15 @@ static void __init omap_detect_sram(void)
                         } else if (cpu_is_omap44xx()) {
                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
                                 omap_sram_size = 0xa000; /* 40K */
+                        } else if (soc_is_omap54xx()) {
+                                omap_sram_start = OMAP5_SRAM_PA;
+                                omap_sram_size = SZ_128K; /* 128KB */
                         } else {
                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
                                 omap_sram_size = 0x800; /* 2K */
                         }
                 } else {
-                        if (cpu_is_am33xx()) {
+                        if (soc_is_am33xx()) {
                                 omap_sram_start = AM33XX_SRAM_PA;
                                 omap_sram_size = 0x10000; /* 64K */
                         } else if (cpu_is_omap34xx()) {
@@ -132,6 +136,9 @@ static void __init omap_detect_sram(void)
                         } else if (cpu_is_omap44xx()) {
                                 omap_sram_start = OMAP4_SRAM_PA;
                                 omap_sram_size = 0xe000; /* 56K */
+                        } else if (soc_is_omap54xx()) {
+                                omap_sram_start = OMAP5_SRAM_PA;
+                                omap_sram_size = SZ_128K; /* 128KB */
                         } else {
                                 omap_sram_start = OMAP2_SRAM_PA;
                                 if (cpu_is_omap242x())
@@ -386,7 +393,7 @@ int __init omap_sram_init(void)
                 omap242x_sram_init();
         else if (cpu_is_omap2430())
                 omap243x_sram_init();
-        else if (cpu_is_am33xx())
+        else if (soc_is_am33xx())
                 am33xx_sram_init();
         else if (cpu_is_omap34xx())
                 omap34xx_sram_init();
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
deleted file mode 100644
index daa0327381b..00000000000
--- a/arch/arm/plat-omap/usb.c
+++ /dev/null
@@ -1,145 +0,0 @@
- /*
- * arch/arm/plat-omap/usb.c -- platform level USB initialization
- *
- * Copyright (C) 2004 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#undef  DEBUG
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <plat/usb.h>
-#include <plat/board.h>
-
-#include <mach/hardware.h>
-
-#ifdef  CONFIG_ARCH_OMAP_OTG
-
-void __init
-omap_otg_init(struct omap_usb_config *config)
-{
-        u32             syscon;
-        int             alt_pingroup = 0;
-
-        /* NOTE:  no bus or clock setup (yet?) */
-
-        syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
-        if (!(syscon & OTG_RESET_DONE))
-                pr_debug("USB resets not complete?\n");
-
-        //omap_writew(0, OTG_IRQ_EN);
-
-        /* pin muxing and transceiver pinouts */
-        if (config->pins[0] > 2)        /* alt pingroup 2 */
-                alt_pingroup = 1;
-        syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
-        syscon |= config->usb1_init(config->pins[1]);
-        syscon |= config->usb2_init(config->pins[2], alt_pingroup);
-        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
-        omap_writel(syscon, OTG_SYSCON_1);
-
-        syscon = config->hmc_mode;
-        syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
-#ifdef  CONFIG_USB_OTG
-        if (config->otg)
-                syscon |= OTG_EN;
-#endif
-        if (cpu_class_is_omap1())
-                pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
-                         omap_readl(USB_TRANSCEIVER_CTRL));
-        pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
-        omap_writel(syscon, OTG_SYSCON_2);
-
-        printk("USB: hmc %d", config->hmc_mode);
-        if (!alt_pingroup)
-                printk(", usb2 alt %d wires", config->pins[2]);
-        else if (config->pins[0])
-                printk(", usb0 %d wires%s", config->pins[0],
-                        is_usb0_device(config) ? " (dev)" : "");
-        if (config->pins[1])
-                printk(", usb1 %d wires", config->pins[1]);
-        if (!alt_pingroup && config->pins[2])
-                printk(", usb2 %d wires", config->pins[2]);
-        if (config->otg)
-                printk(", Mini-AB on usb%d", config->otg - 1);
-        printk("\n");
-
-        if (cpu_class_is_omap1()) {
-                u16 w;
-
-                /* leave USB clocks/controllers off until needed */
-                w = omap_readw(ULPD_SOFT_REQ);
-                w &= ~SOFT_USB_CLK_REQ;
-                omap_writew(w, ULPD_SOFT_REQ);
-
-                w = omap_readw(ULPD_CLOCK_CTRL);
-                w &= ~USB_MCLK_EN;
-                w |= DIS_USB_PVCI_CLK;
-                omap_writew(w, ULPD_CLOCK_CTRL);
-        }
-        syscon = omap_readl(OTG_SYSCON_1);
-        syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
-
-#ifdef  CONFIG_USB_GADGET_OMAP
-        if (config->otg || config->register_dev) {
-                struct platform_device *udc_device = config->udc_device;
-                int status;
-
-                syscon &= ~DEV_IDLE_EN;
-                udc_device->dev.platform_data = config;
-                status = platform_device_register(udc_device);
-                if (status)
-                        pr_debug("can't register UDC device, %d\n", status);
-        }
-#endif
-
-#if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-        if (config->otg || config->register_host) {
-                struct platform_device *ohci_device = config->ohci_device;
-                int status;
-
-                syscon &= ~HST_IDLE_EN;
-                ohci_device->dev.platform_data = config;
-                status = platform_device_register(ohci_device);
-                if (status)
-                        pr_debug("can't register OHCI device, %d\n", status);
-        }
-#endif
-
-#ifdef  CONFIG_USB_OTG
-        if (config->otg) {
-                struct platform_device *otg_device = config->otg_device;
-                int status;
-
-                syscon &= ~OTG_IDLE_EN;
-                otg_device->dev.platform_data = config;
-                status = platform_device_register(otg_device);
-                if (status)
-                        pr_debug("can't register OTG device, %d\n", status);
-        }
-#endif
-        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
-        omap_writel(syscon, OTG_SYSCON_1);
-}
-
-#else
-void omap_otg_init(struct omap_usb_config *config) {}
-#endif
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index c1793786aea..b8b747a9d36 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -47,6 +47,7 @@ void __init orion_clkdev_init(struct clk *tclk)
         orion_clkdev_add(NULL, MV643XX_ETH_NAME ".2", tclk);
         orion_clkdev_add(NULL, MV643XX_ETH_NAME ".3", tclk);
         orion_clkdev_add(NULL, "orion_wdt", tclk);
+        orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", tclk);
 }
 
 /* Fill in the resources structure and link it into the platform
@@ -290,10 +291,12 @@ static struct platform_device orion_ge00 = {
 void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
                             unsigned long mapbase,
                             unsigned long irq,
-                            unsigned long irq_err)
+                            unsigned long irq_err,
+                            unsigned int tx_csum_limit)
 {
         fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
                        mapbase + 0x2000, SZ_16K - 1, irq_err);
+        orion_ge00_shared_data.tx_csum_limit = tx_csum_limit;
         ge_complete(&orion_ge00_shared_data,
                     orion_ge00_resources, irq, &orion_ge00_shared,
                     eth_data, &orion_ge00);
@@ -342,10 +345,12 @@ static struct platform_device orion_ge01 = {
 void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
                             unsigned long mapbase,
                             unsigned long irq,
-                            unsigned long irq_err)
+                            unsigned long irq_err,
+                            unsigned int tx_csum_limit)
 {
         fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
                        mapbase + 0x2000, SZ_16K - 1, irq_err);
+        orion_ge01_shared_data.tx_csum_limit = tx_csum_limit;
         ge_complete(&orion_ge01_shared_data,
                     orion_ge01_resources, irq, &orion_ge01_shared,
                     eth_data, &orion_ge01);
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index af95af25730..dfda74fae6f 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -8,15 +8,22 @@
  * warranty of any kind, whether express or implied.
  */
 
+#define DEBUG
+
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/module.h>
 #include <linux/spinlock.h>
 #include <linux/bitops.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <plat/gpio.h>
 
 /*
  * GPIO unit register offsets.
@@ -38,6 +45,7 @@ struct orion_gpio_chip {
         unsigned long           valid_output;
         int                     mask_offset;
         int                     secondary_irq_base;
+        struct irq_domain       *domain;
 };
 
 static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
@@ -222,10 +230,10 @@ static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
         struct orion_gpio_chip *ochip =
                 container_of(chip, struct orion_gpio_chip, chip);
 
-        return ochip->secondary_irq_base + pin;
+        return irq_create_mapping(ochip->domain,
+                                  ochip->secondary_irq_base + pin);
 }
 
-
 /*
  * Orion-specific GPIO API extensions.
  */
@@ -353,12 +361,10 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
         int pin;
         u32 u;
 
-        pin = d->irq - gc->irq_base;
+        pin = d->hwirq - ochip->secondary_irq_base;
 
         u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
         if (!u) {
-                printk(KERN_ERR "orion gpio_irq_set_type failed "
-                                "(irq %d, pin %d).\n", d->irq, pin);
                 return -EINVAL;
         }
 
@@ -397,17 +403,53 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
                         u &= ~(1 << pin);       /* rising */
                 writel(u, GPIO_IN_POL(ochip));
         }
-
         return 0;
 }
 
-void __init orion_gpio_init(int gpio_base, int ngpio,
-                            u32 base, int mask_offset, int secondary_irq_base)
+static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+        struct orion_gpio_chip *ochip = irq_get_handler_data(irq);
+        u32 cause, type;
+        int i;
+
+        if (ochip == NULL)
+                return;
+
+        cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
+        cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
+
+        for (i = 0; i < ochip->chip.ngpio; i++) {
+                int irq;
+
+                irq = ochip->secondary_irq_base + i;
+
+                if (!(cause & (1 << i)))
+                        continue;
+
+                type = irqd_get_trigger_type(irq_get_irq_data(irq));
+                if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+                        /* Swap polarity (race with GPIO line) */
+                        u32 polarity;
+
+                        polarity = readl(GPIO_IN_POL(ochip));
+                        polarity ^= 1 << i;
+                        writel(polarity, GPIO_IN_POL(ochip));
+                }
+                generic_handle_irq(irq);
+        }
+}
+
+void __init orion_gpio_init(struct device_node *np,
+                            int gpio_base, int ngpio,
+                            void __iomem *base, int mask_offset,
+                            int secondary_irq_base,
+                            int irqs[4])
 {
         struct orion_gpio_chip *ochip;
         struct irq_chip_generic *gc;
         struct irq_chip_type *ct;
         char gc_label[16];
+        int i;
 
         if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
                 return;
@@ -426,6 +468,10 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
         ochip->chip.base = gpio_base;
         ochip->chip.ngpio = ngpio;
         ochip->chip.can_sleep = 0;
+#ifdef CONFIG_OF
+        ochip->chip.of_node = np;
+#endif
+
         spin_lock_init(&ochip->lock);
         ochip->base = (void __iomem *)base;
         ochip->valid_input = 0;
@@ -435,8 +481,6 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
 
         gpiochip_add(&ochip->chip);
 
-        orion_gpio_chip_count++;
-
         /*
          * Mask and clear GPIO interrupts.
          */
@@ -444,16 +488,28 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
         writel(0, GPIO_EDGE_MASK(ochip));
         writel(0, GPIO_LEVEL_MASK(ochip));
 
-        gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
+        /* Setup the interrupt handlers. Each chip can have up to 4
+         * interrupt handlers, with each handler dealing with 8 GPIO
+         * pins. */
+
+        for (i = 0; i < 4; i++) {
+                if (irqs[i]) {
+                        irq_set_handler_data(irqs[i], ochip);
+                        irq_set_chained_handler(irqs[i], gpio_irq_handler);
+                }
+        }
+
+        gc = irq_alloc_generic_chip("orion_gpio_irq", 2,
+                                    secondary_irq_base,
                                     ochip->base, handle_level_irq);
         gc->private = ochip;
-
         ct = gc->chip_types;
         ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
         ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
         ct->chip.irq_mask = irq_gc_mask_clr_bit;
         ct->chip.irq_unmask = irq_gc_mask_set_bit;
         ct->chip.irq_set_type = gpio_irq_set_type;
+        ct->chip.name = ochip->chip.label;
 
         ct++;
         ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
@@ -464,41 +520,69 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
         ct->chip.irq_unmask = irq_gc_mask_set_bit;
         ct->chip.irq_set_type = gpio_irq_set_type;
         ct->handler = handle_edge_irq;
+        ct->chip.name = ochip->chip.label;
 
         irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
                                IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
-}
 
-void orion_gpio_irq_handler(int pinoff)
-{
-        struct orion_gpio_chip *ochip;
-        u32 cause, type;
-        int i;
-
-        ochip = orion_gpio_chip_find(pinoff);
-        if (ochip == NULL)
-                return;
-
-        cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
-        cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
-
-        for (i = 0; i < ochip->chip.ngpio; i++) {
-                int irq;
+        /* Setup irq domain on top of the generic chip. */
+        ochip->domain = irq_domain_add_legacy(np,
+                                              ochip->chip.ngpio,
+                                              ochip->secondary_irq_base,
+                                              ochip->secondary_irq_base,
+                                              &irq_domain_simple_ops,
+                                              ochip);
+        if (!ochip->domain)
+                panic("%s: couldn't allocate irq domain (DT).\n",
+                      ochip->chip.label);
 
-                irq = ochip->secondary_irq_base + i;
+        orion_gpio_chip_count++;
+}
 
-                if (!(cause & (1 << i)))
-                        continue;
+#ifdef CONFIG_OF
+static void __init orion_gpio_of_init_one(struct device_node *np,
+                                          int irq_gpio_base)
+{
+        int ngpio, gpio_base, mask_offset;
+        void __iomem *base;
+        int ret, i;
+        int irqs[4];
+        int secondary_irq_base;
+
+        ret = of_property_read_u32(np, "ngpio", &ngpio);
+        if (ret)
+                goto out;
+        ret = of_property_read_u32(np, "mask-offset", &mask_offset);
+        if (ret == -EINVAL)
+                mask_offset = 0;
+        else
+                goto out;
+        base = of_iomap(np, 0);
+        if (!base)
+                goto out;
+
+        secondary_irq_base = irq_gpio_base + (32 * orion_gpio_chip_count);
+        gpio_base = 32 * orion_gpio_chip_count;
+
+        /* Get the interrupt numbers. Each chip can have up to 4
+         * interrupt handlers, with each handler dealing with 8 GPIO
+         * pins. */
+
+        for (i = 0; i < 4; i++)
+                irqs[i] = irq_of_parse_and_map(np, i);
+
+        orion_gpio_init(np, gpio_base, ngpio, base, mask_offset,
+                        secondary_irq_base, irqs);
+        return;
+out:
+        pr_err("%s: %s: missing mandatory property\n", __func__, np->name);
+}
 
-                type = irqd_get_trigger_type(irq_get_irq_data(irq));
-                if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
-                        /* Swap polarity (race with GPIO line) */
-                        u32 polarity;
+void __init orion_gpio_of_init(int irq_gpio_base)
+{
+        struct device_node *np;
 
-                        polarity = readl(GPIO_IN_POL(ochip));
-                        polarity ^= 1 << i;
-                        writel(polarity, GPIO_IN_POL(ochip));
-                }
-                generic_handle_irq(irq);
-        }
+        for_each_compatible_node(np, NULL, "marvell,orion-gpio")
+                orion_gpio_of_init_one(np, irq_gpio_base);
 }
+#endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index e00fdb21360..ae2377ef63e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -39,12 +39,14 @@ void __init orion_rtc_init(unsigned long mapbase,
 void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
                             unsigned long mapbase,
                             unsigned long irq,
-                            unsigned long irq_err);
+                            unsigned long irq_err,
+                            unsigned int tx_csum_limit);
 
 void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
                             unsigned long mapbase,
                             unsigned long irq,
-                            unsigned long irq_err);
+                            unsigned long irq_err,
+                            unsigned int tx_csum_limit);
 
 void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
                             unsigned long mapbase,
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index bec0c98ce41..81c6fc8a7b2 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -13,7 +13,7 @@
 
 #include <linux/init.h>
 #include <linux/types.h>
-
+#include <linux/irqdomain.h>
 /*
  * Orion-specific GPIO API extensions.
  */
@@ -27,13 +27,11 @@ int orion_gpio_led_blink_set(unsigned gpio, int state,
 void orion_gpio_set_valid(unsigned pin, int mode);
 
 /* Initialize gpiolib. */
-void __init orion_gpio_init(int gpio_base, int ngpio,
-                            u32 base, int mask_offset, int secondary_irq_base);
-
-/*
- * GPIO interrupt handling.
- */
-void orion_gpio_irq_handler(int irqoff);
-
+void __init orion_gpio_init(struct device_node *np,
+                            int gpio_base, int ngpio,
+                            void __iomem *base, int mask_offset,
+                            int secondary_irq_base,
+                            int irq[4]);
 
+void __init orion_gpio_of_init(int irq_gpio_base);
 #endif
diff --git a/arch/arm/plat-orion/include/plat/irq.h b/arch/arm/plat-orion/include/plat/irq.h
index f05eeab9496..50547e41793 100644
--- a/arch/arm/plat-orion/include/plat/irq.h
+++ b/arch/arm/plat-orion/include/plat/irq.h
@@ -12,6 +12,5 @@
 #define __PLAT_IRQ_H
 
 void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
-
-
+void __init orion_dt_init_irq(void);
 #endif
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 2d5b9c1ef38..d751964def4 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -11,8 +11,12 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <plat/irq.h>
+#include <plat/gpio.h>
 
 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 {
@@ -32,3 +36,39 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
         irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
                                IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
 }
+
+#ifdef CONFIG_OF
+static int __init orion_add_irq_domain(struct device_node *np,
+                                       struct device_node *interrupt_parent)
+{
+        int i = 0, irq_gpio;
+        void __iomem *base;
+
+        do {
+                base = of_iomap(np, i);
+                if (base) {
+                        orion_irq_init(i * 32, base);
+                        i++;
+                }
+        } while (base);
+
+        irq_domain_add_legacy(np, i * 32, 0, 0,
+                              &irq_domain_simple_ops, NULL);
+
+        irq_gpio = i * 32;
+        orion_gpio_of_init(irq_gpio);
+
+        return 0;
+}
+
+static const struct of_device_id orion_irq_match[] = {
+        { .compatible = "marvell,orion-intc",
+          .data = orion_add_irq_domain, },
+        {},
+};
+
+void __init orion_dt_init_irq(void)
+{
+        of_irq_init(orion_irq_match);
+}
+#endif
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index f302d048392..af8e484001e 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -8,5 +8,4 @@ obj-$(CONFIG_PXA3xx)		+= mfp.o
 obj-$(CONFIG_PXA95x)            += mfp.o
 obj-$(CONFIG_ARCH_MMP)          += mfp.o
 
-obj-$(CONFIG_HAVE_PWM)          += pwm.o
 obj-$(CONFIG_PXA_SSP)           += ssp.o
diff --git a/arch/arm/plat-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c
deleted file mode 100644
index ef32686feef..00000000000
--- a/arch/arm/plat-pxa/pwm.c
+++ /dev/null
@@ -1,304 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/pwm.c
- *
- * simple driver for PWM (Pulse Width Modulator) controller
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * 2008-02-13   initial version
- *              eric miao <eric.miao@marvell.com>
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/pwm.h>
-
-#include <asm/div64.h>
-
-#define HAS_SECONDARY_PWM       0x10
-#define PWM_ID_BASE(d)          ((d) & 0xf)
-
-static const struct platform_device_id pwm_id_table[] = {
-        /*   PWM    has_secondary_pwm? */
-        { "pxa25x-pwm", 0 },
-        { "pxa27x-pwm", 0 | HAS_SECONDARY_PWM },
-        { "pxa168-pwm", 1 },
-        { "pxa910-pwm", 1 },
-        { },
-};
-MODULE_DEVICE_TABLE(platform, pwm_id_table);
-
-/* PWM registers and bits definitions */
-#define PWMCR           (0x00)
-#define PWMDCR          (0x04)
-#define PWMPCR          (0x08)
-
-#define PWMCR_SD        (1 << 6)
-#define PWMDCR_FD       (1 << 10)
-
-struct pwm_device {
-        struct list_head        node;
-        struct pwm_device       *secondary;
-        struct platform_device  *pdev;
-
-        const char      *label;
-        struct clk      *clk;
-        int             clk_enabled;
-        void __iomem    *mmio_base;
-
-        unsigned int    use_count;
-        unsigned int    pwm_id;
-};
-
-/*
- * period_ns = 10^9 * (PRESCALE + 1) * (PV + 1) / PWM_CLK_RATE
- * duty_ns   = 10^9 * (PRESCALE + 1) * DC / PWM_CLK_RATE
- */
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
-{
-        unsigned long long c;
-        unsigned long period_cycles, prescale, pv, dc;
-
-        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
-                return -EINVAL;
-
-        c = clk_get_rate(pwm->clk);
-        c = c * period_ns;
-        do_div(c, 1000000000);
-        period_cycles = c;
-
-        if (period_cycles < 1)
-                period_cycles = 1;
-        prescale = (period_cycles - 1) / 1024;
-        pv = period_cycles / (prescale + 1) - 1;
-
-        if (prescale > 63)
-                return -EINVAL;
-
-        if (duty_ns == period_ns)
-                dc = PWMDCR_FD;
-        else
-                dc = (pv + 1) * duty_ns / period_ns;
-
-        /* NOTE: the clock to PWM has to be enabled first
-         * before writing to the registers
-         */
-        clk_enable(pwm->clk);
-        __raw_writel(prescale, pwm->mmio_base + PWMCR);
-        __raw_writel(dc, pwm->mmio_base + PWMDCR);
-        __raw_writel(pv, pwm->mmio_base + PWMPCR);
-        clk_disable(pwm->clk);
-
-        return 0;
-}
-EXPORT_SYMBOL(pwm_config);
-
-int pwm_enable(struct pwm_device *pwm)
-{
-        int rc = 0;
-
-        if (!pwm->clk_enabled) {
-                rc = clk_enable(pwm->clk);
-                if (!rc)
-                        pwm->clk_enabled = 1;
-        }
-        return rc;
-}
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-        if (pwm->clk_enabled) {
-                clk_disable(pwm->clk);
-                pwm->clk_enabled = 0;
-        }
-}
-EXPORT_SYMBOL(pwm_disable);
-
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-        struct pwm_device *pwm;
-        int found = 0;
-
-        mutex_lock(&pwm_lock);
-
-        list_for_each_entry(pwm, &pwm_list, node) {
-                if (pwm->pwm_id == pwm_id) {
-                        found = 1;
-                        break;
-                }
-        }
-
-        if (found) {
-                if (pwm->use_count == 0) {
-                        pwm->use_count++;
-                        pwm->label = label;
-                } else
-                        pwm = ERR_PTR(-EBUSY);
-        } else
-                pwm = ERR_PTR(-ENOENT);
-
-        mutex_unlock(&pwm_lock);
-        return pwm;
-}
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-        mutex_lock(&pwm_lock);
-
-        if (pwm->use_count) {
-                pwm->use_count--;
-                pwm->label = NULL;
-        } else
-                pr_warning("PWM device already freed\n");
-
-        mutex_unlock(&pwm_lock);
-}
-EXPORT_SYMBOL(pwm_free);
-
-static inline void __add_pwm(struct pwm_device *pwm)
-{
-        mutex_lock(&pwm_lock);
-        list_add_tail(&pwm->node, &pwm_list);
-        mutex_unlock(&pwm_lock);
-}
-
-static int __devinit pwm_probe(struct platform_device *pdev)
-{
-        const struct platform_device_id *id = platform_get_device_id(pdev);
-        struct pwm_device *pwm, *secondary = NULL;
-        struct resource *r;
-        int ret = 0;
-
-        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-        if (pwm == NULL) {
-                dev_err(&pdev->dev, "failed to allocate memory\n");
-                return -ENOMEM;
-        }
-
-        pwm->clk = clk_get(&pdev->dev, NULL);
-        if (IS_ERR(pwm->clk)) {
-                ret = PTR_ERR(pwm->clk);
-                goto err_free;
-        }
-        pwm->clk_enabled = 0;
-
-        pwm->use_count = 0;
-        pwm->pwm_id = PWM_ID_BASE(id->driver_data) + pdev->id;
-        pwm->pdev = pdev;
-
-        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (r == NULL) {
-                dev_err(&pdev->dev, "no memory resource defined\n");
-                ret = -ENODEV;
-                goto err_free_clk;
-        }
-
-        r = request_mem_region(r->start, resource_size(r), pdev->name);
-        if (r == NULL) {
-                dev_err(&pdev->dev, "failed to request memory resource\n");
-                ret = -EBUSY;
-                goto err_free_clk;
-        }
-
-        pwm->mmio_base = ioremap(r->start, resource_size(r));
-        if (pwm->mmio_base == NULL) {
-                dev_err(&pdev->dev, "failed to ioremap() registers\n");
-                ret = -ENODEV;
-                goto err_free_mem;
-        }
-
-        if (id->driver_data & HAS_SECONDARY_PWM) {
-                secondary = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-                if (secondary == NULL) {
-                        ret = -ENOMEM;
-                        goto err_free_mem;
-                }
-
-                *secondary = *pwm;
-                pwm->secondary = secondary;
-
-                /* registers for the second PWM has offset of 0x10 */
-                secondary->mmio_base = pwm->mmio_base + 0x10;
-                secondary->pwm_id = pdev->id + 2;
-        }
-
-        __add_pwm(pwm);
-        if (secondary)
-                __add_pwm(secondary);
-
-        platform_set_drvdata(pdev, pwm);
-        return 0;
-
-err_free_mem:
-        release_mem_region(r->start, resource_size(r));
-err_free_clk:
-        clk_put(pwm->clk);
-err_free:
-        kfree(pwm);
-        return ret;
-}
-
-static int __devexit pwm_remove(struct platform_device *pdev)
-{
-        struct pwm_device *pwm;
-        struct resource *r;
-
-        pwm = platform_get_drvdata(pdev);
-        if (pwm == NULL)
-                return -ENODEV;
-
-        mutex_lock(&pwm_lock);
-
-        if (pwm->secondary) {
-                list_del(&pwm->secondary->node);
-                kfree(pwm->secondary);
-        }
-
-        list_del(&pwm->node);
-        mutex_unlock(&pwm_lock);
-
-        iounmap(pwm->mmio_base);
-
-        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        release_mem_region(r->start, resource_size(r));
-
-        clk_put(pwm->clk);
-        kfree(pwm);
-        return 0;
-}
-
-static struct platform_driver pwm_driver = {
-        .driver         = {
-                .name   = "pxa25x-pwm",
-                .owner  = THIS_MODULE,
-        },
-        .probe          = pwm_probe,
-        .remove         = __devexit_p(pwm_remove),
-        .id_table       = pwm_id_table,
-};
-
-static int __init pwm_init(void)
-{
-        return platform_driver_register(&pwm_driver);
-}
-arch_initcall(pwm_init);
-
-static void __exit pwm_exit(void)
-{
-        platform_driver_unregister(&pwm_driver);
-}
-module_exit(pwm_exit);
-
-MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 28f898f7538..db98e7021f0 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -430,7 +430,7 @@ s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
  * when necessary.
 */
 
-int s3c2410_dma_enqueue(unsigned int channel, void *id,
+int s3c2410_dma_enqueue(enum dma_ch channel, void *id,
                         dma_addr_t data, int size)
 {
         struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index bc42c04091f..fe57bbbf166 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -533,7 +533,7 @@ void __init s3c24xx_init_irq(void)
         int i;
 
 #ifdef CONFIG_FIQ
-        init_FIQ();
+        init_FIQ(FIQ_START);
 #endif
 
         irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index a2fae4ea093..9c3b90c3538 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -78,6 +78,10 @@ config S5P_HRT
 
 # clock options
 
+config SAMSUNG_CLOCK
+        bool
+        default y if !COMMON_CLK
+
 config SAMSUNG_CLKSRC
         bool
         help
@@ -399,7 +403,8 @@ config S5P_DEV_USB_EHCI
 
 config S3C24XX_PWM
         bool "PWM device support"
-        select HAVE_PWM
+        select PWM
+        select PWM_SAMSUNG
         help
           Support for exporting the PWM timer blocks via the pwm device
           system
@@ -491,14 +496,6 @@ config S5P_SLEEP
           Internal config node to apply common S5P sleep management code.
           Can be selected by S5P and newer SoCs with similar sleep procedure.
 
-comment "Power Domain"
-
-config SAMSUNG_PD
-        bool "Samsung Power Domain"
-        depends on PM_RUNTIME
-        help
-          Say Y here if you want to control Power Domain by Runtime PM.
-
 config DEBUG_S3C_UART
         depends on PLAT_SAMSUNG
         int
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 860b2db4db1..9e40e8d0074 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -15,8 +15,8 @@ obj-y				+= init.o cpu.o
 obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o
 obj-$(CONFIG_S5P_HRT)           += s5p-time.o
 
-obj-y                           += clock.o
-obj-y                           += pwm-clock.o
+obj-$(CONFIG_SAMSUNG_CLOCK)     += clock.o
+obj-$(CONFIG_SAMSUNG_CLOCK)     += pwm-clock.o
 
 obj-$(CONFIG_SAMSUNG_CLKSRC)    += clock-clksrc.o
 obj-$(CONFIG_S5P_CLOCK)         += s5p-clock.o
@@ -59,11 +59,3 @@ obj-$(CONFIG_SAMSUNG_WAKEMASK)	+= wakeup-mask.o
 
 obj-$(CONFIG_S5P_PM)            += s5p-pm.o s5p-irq-pm.o
 obj-$(CONFIG_S5P_SLEEP)         += s5p-sleep.o
-
-# PD support
-
-obj-$(CONFIG_SAMSUNG_PD)        += pd.o
-
-# PWM support
-
-obj-$(CONFIG_HAVE_PWM)          += pwm.o
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 6303974c2ee..fc49f3dabd7 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -32,6 +32,8 @@
 #include <linux/platform_data/s3c-hsudc.h>
 #include <linux/platform_data/s3c-hsotg.h>
 
+#include <media/s5p_hdmi.h>
+
 #include <asm/irq.h>
 #include <asm/pmu.h>
 #include <asm/mach/arch.h>
@@ -748,7 +750,8 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
         if (!pd) {
                 pd = &default_i2c_data;
 
-                if (soc_is_exynos4210())
+                if (soc_is_exynos4210() ||
+                    soc_is_exynos4212() || soc_is_exynos4412())
                         pd->bus_num = 8;
                 else if (soc_is_s5pv210())
                         pd->bus_num = 3;
@@ -759,6 +762,30 @@ void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
         npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
                                &s5p_device_i2c_hdmiphy);
 }
+
+struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
+
+void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
+                                  struct i2c_board_info *mhl_info, int mhl_bus)
+{
+        struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
+
+        if (soc_is_exynos4210() ||
+            soc_is_exynos4212() || soc_is_exynos4412())
+                pd->hdmiphy_bus = 8;
+        else if (soc_is_s5pv210())
+                pd->hdmiphy_bus = 3;
+        else
+                pd->hdmiphy_bus = 0;
+
+        pd->hdmiphy_info = hdmiphy_info;
+        pd->mhl_info = mhl_info;
+        pd->mhl_bus = mhl_bus;
+
+        s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
+                         &s5p_device_hdmi);
+}
+
 #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
 
 /* I2S */
@@ -1513,7 +1540,7 @@ static struct resource s3c64xx_spi0_resource[] = {
 };
 
 struct platform_device s3c64xx_device_spi0 = {
-        .name           = "s3c64xx-spi",
+        .name           = "s3c6410-spi",
         .id             = 0,
         .num_resources  = ARRAY_SIZE(s3c64xx_spi0_resource),
         .resource       = s3c64xx_spi0_resource,
@@ -1523,13 +1550,10 @@ struct platform_device s3c64xx_device_spi0 = {
         },
 };
 
-void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs)
+void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs)
 {
-        if (!pd) {
-                pr_err("%s:Need to pass platform data\n", __func__);
-                return;
-        }
+        struct s3c64xx_spi_info pd;
 
         /* Reject invalid configuration */
         if (!num_cs || src_clk_nr < 0) {
@@ -1537,12 +1561,11 @@ void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
                 return;
         }
 
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        if (!pd->cfg_gpio)
-                pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
+        pd.num_cs = num_cs;
+        pd.src_clk_nr = src_clk_nr;
+        pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
 
-        s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
+        s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
 }
 #endif /* CONFIG_S3C64XX_DEV_SPI0 */
 
@@ -1555,7 +1578,7 @@ static struct resource s3c64xx_spi1_resource[] = {
 };
 
 struct platform_device s3c64xx_device_spi1 = {
-        .name           = "s3c64xx-spi",
+        .name           = "s3c6410-spi",
         .id             = 1,
         .num_resources  = ARRAY_SIZE(s3c64xx_spi1_resource),
         .resource       = s3c64xx_spi1_resource,
@@ -1565,26 +1588,20 @@ struct platform_device s3c64xx_device_spi1 = {
         },
 };
 
-void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs)
+void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs)
 {
-        if (!pd) {
-                pr_err("%s:Need to pass platform data\n", __func__);
-                return;
-        }
-
         /* Reject invalid configuration */
         if (!num_cs || src_clk_nr < 0) {
                 pr_err("%s: Invalid SPI configuration\n", __func__);
                 return;
         }
 
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        if (!pd->cfg_gpio)
-                pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
+        pd.num_cs = num_cs;
+        pd.src_clk_nr = src_clk_nr;
+        pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
 
-        s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
+        s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
 }
 #endif /* CONFIG_S3C64XX_DEV_SPI1 */
 
@@ -1597,7 +1614,7 @@ static struct resource s3c64xx_spi2_resource[] = {
 };
 
 struct platform_device s3c64xx_device_spi2 = {
-        .name           = "s3c64xx-spi",
+        .name           = "s3c6410-spi",
         .id             = 2,
         .num_resources  = ARRAY_SIZE(s3c64xx_spi2_resource),
         .resource       = s3c64xx_spi2_resource,
@@ -1607,13 +1624,10 @@ struct platform_device s3c64xx_device_spi2 = {
         },
 };
 
-void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs)
+void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs)
 {
-        if (!pd) {
-                pr_err("%s:Need to pass platform data\n", __func__);
-                return;
-        }
+        struct s3c64xx_spi_info pd;
 
         /* Reject invalid configuration */
         if (!num_cs || src_clk_nr < 0) {
@@ -1621,11 +1635,10 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
                 return;
         }
 
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        if (!pd->cfg_gpio)
-                pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
+        pd.num_cs = num_cs;
+        pd.src_clk_nr = src_clk_nr;
+        pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
 
-        s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
+        s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
 }
 #endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index eb9f4f53400..c38d7548924 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -19,72 +19,79 @@
 #include <mach/dma.h>
 
 static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
-                                struct samsung_dma_info *info)
+                                struct samsung_dma_req *param)
 {
-        struct dma_chan *chan;
         dma_cap_mask_t mask;
-        struct dma_slave_config slave_config;
         void *filter_param;
 
         dma_cap_zero(mask);
-        dma_cap_set(info->cap, mask);
+        dma_cap_set(param->cap, mask);
 
         /*
          * If a dma channel property of a device node from device tree is
          * specified, use that as the fliter parameter.
          */
-        filter_param = (dma_ch == DMACH_DT_PROP) ? (void *)info->dt_dmach_prop :
-                                (void *)dma_ch;
-        chan = dma_request_channel(mask, pl330_filter, filter_param);
+        filter_param = (dma_ch == DMACH_DT_PROP) ?
+                (void *)param->dt_dmach_prop : (void *)dma_ch;
+        return (unsigned)dma_request_channel(mask, pl330_filter, filter_param);
+}
+
+static int samsung_dmadev_release(unsigned ch, void *param)
+{
+        dma_release_channel((struct dma_chan *)ch);
 
-        if (info->direction == DMA_DEV_TO_MEM) {
+        return 0;
+}
+
+static int samsung_dmadev_config(unsigned ch,
+                                struct samsung_dma_config *param)
+{
+        struct dma_chan *chan = (struct dma_chan *)ch;
+        struct dma_slave_config slave_config;
+
+        if (param->direction == DMA_DEV_TO_MEM) {
                 memset(&slave_config, 0, sizeof(struct dma_slave_config));
-                slave_config.direction = info->direction;
-                slave_config.src_addr = info->fifo;
-                slave_config.src_addr_width = info->width;
+                slave_config.direction = param->direction;
+                slave_config.src_addr = param->fifo;
+                slave_config.src_addr_width = param->width;
                 slave_config.src_maxburst = 1;
                 dmaengine_slave_config(chan, &slave_config);
-        } else if (info->direction == DMA_MEM_TO_DEV) {
+        } else if (param->direction == DMA_MEM_TO_DEV) {
                 memset(&slave_config, 0, sizeof(struct dma_slave_config));
-                slave_config.direction = info->direction;
-                slave_config.dst_addr = info->fifo;
-                slave_config.dst_addr_width = info->width;
+                slave_config.direction = param->direction;
+                slave_config.dst_addr = param->fifo;
+                slave_config.dst_addr_width = param->width;
                 slave_config.dst_maxburst = 1;
                 dmaengine_slave_config(chan, &slave_config);
+        } else {
+                pr_warn("unsupported direction\n");
+                return -EINVAL;
         }
 
-        return (unsigned)chan;
-}
-
-static int samsung_dmadev_release(unsigned ch,
-                        struct s3c2410_dma_client *client)
-{
-        dma_release_channel((struct dma_chan *)ch);
-
         return 0;
 }
 
 static int samsung_dmadev_prepare(unsigned ch,
-                        struct samsung_dma_prep_info *info)
+                        struct samsung_dma_prep *param)
 {
         struct scatterlist sg;
         struct dma_chan *chan = (struct dma_chan *)ch;
         struct dma_async_tx_descriptor *desc;
 
-        switch (info->cap) {
+        switch (param->cap) {
         case DMA_SLAVE:
                 sg_init_table(&sg, 1);
-                sg_dma_len(&sg) = info->len;
-                sg_set_page(&sg, pfn_to_page(PFN_DOWN(info->buf)),
-                            info->len, offset_in_page(info->buf));
-                sg_dma_address(&sg) = info->buf;
+                sg_dma_len(&sg) = param->len;
+                sg_set_page(&sg, pfn_to_page(PFN_DOWN(param->buf)),
+                            param->len, offset_in_page(param->buf));
+                sg_dma_address(&sg) = param->buf;
 
                 desc = dmaengine_prep_slave_sg(chan,
-                        &sg, 1, info->direction, DMA_PREP_INTERRUPT);
+                        &sg, 1, param->direction, DMA_PREP_INTERRUPT);
                 break;
         case DMA_CYCLIC:
-                desc = dmaengine_prep_dma_cyclic(chan,
-                        info->buf, info->len, info->period, info->direction);
+                desc = dmaengine_prep_dma_cyclic(chan, param->buf,
+                        param->len, param->period, param->direction);
                 break;
         default:
                 dev_err(&chan->dev->device, "unsupported format\n");
@@ -96,8 +103,8 @@ static int samsung_dmadev_prepare(unsigned ch,
                 return -EFAULT;
         }
 
-        desc->callback = info->fp;
-        desc->callback_param = info->fp_param;
+        desc->callback = param->fp;
+        desc->callback_param = param->fp_param;
 
         dmaengine_submit((struct dma_async_tx_descriptor *)desc);
 
@@ -119,6 +126,7 @@ static inline int samsung_dmadev_flush(unsigned ch)
 static struct samsung_dma_ops dmadev_ops = {
         .request        = samsung_dmadev_request,
         .release        = samsung_dmadev_release,
+        .config         = samsung_dmadev_config,
         .prepare        = samsung_dmadev_prepare,
         .trigger        = samsung_dmadev_trigger,
         .started        = NULL,
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 0721293fad6..ace4451b765 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
 
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
+#ifndef KHZ
+#define KHZ (1000)
+#endif
+
 #ifndef MHZ
 #define MHZ (1000*1000)
 #endif
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 61ca2f356c5..5da4b4f38f4 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -131,7 +131,6 @@ extern struct platform_device exynos4_device_ohci;
 extern struct platform_device exynos4_device_pcm0;
 extern struct platform_device exynos4_device_pcm1;
 extern struct platform_device exynos4_device_pcm2;
-extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_spdif;
 
 extern struct platform_device exynos_device_drm;
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
index 71a6827c770..f5144cdd300 100644
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -16,7 +16,13 @@
 #include <linux/dmaengine.h>
 #include <mach/dma.h>
 
-struct samsung_dma_prep_info {
+struct samsung_dma_req {
+        enum dma_transaction_type cap;
+        struct property *dt_dmach_prop;
+        struct s3c2410_dma_client *client;
+};
+
+struct samsung_dma_prep {
         enum dma_transaction_type cap;
         enum dma_transfer_direction direction;
         dma_addr_t buf;
@@ -26,19 +32,17 @@ struct samsung_dma_prep_info {
         void *fp_param;
 };
 
-struct samsung_dma_info {
-        enum dma_transaction_type cap;
+struct samsung_dma_config {
         enum dma_transfer_direction direction;
         enum dma_slave_buswidth width;
         dma_addr_t fifo;
-        struct s3c2410_dma_client *client;
-        struct property *dt_dmach_prop;
 };
 
 struct samsung_dma_ops {
-        unsigned (*request)(enum dma_ch ch, struct samsung_dma_info *info);
-        int (*release)(unsigned ch, struct s3c2410_dma_client *client);
-        int (*prepare)(unsigned ch, struct samsung_dma_prep_info *info);
+        unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param);
+        int (*release)(unsigned ch, void *param);
+        int (*config)(unsigned ch, struct samsung_dma_config *param);
+        int (*prepare)(unsigned ch, struct samsung_dma_prep *param);
         int (*trigger)(unsigned ch);
         int (*started)(unsigned ch);
         int (*flush)(unsigned ch);
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 536002ff2ab..b885322717a 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -43,7 +43,6 @@ struct s3c_fb_pd_win {
  * @setup_gpio: Setup the external GPIO pins to the right state to transfer
  *              the data from the display system to the connected display
  *              device.
- * @default_win: default window layer number to be used for UI layer.
  * @vidcon0: The base vidcon0 values to control the panel data format.
  * @vidcon1: The base vidcon1 values to control the panel data output.
  * @vtiming: Video timing when connected to a RGB type panel.
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index df8155b9d4d..08740eed050 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -24,7 +24,7 @@
 #ifndef __PLAT_GPIO_CFG_H
 #define __PLAT_GPIO_CFG_H __FILE__
 
-#include<linux/types.h>
+#include <linux/types.h>
 
 typedef unsigned int __bitwise__ samsung_gpio_pull_t;
 typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
diff --git a/arch/arm/plat-samsung/include/plat/hdmi.h b/arch/arm/plat-samsung/include/plat/hdmi.h
new file mode 100644
index 00000000000..331d046ac2c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/hdmi.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2012 Samsung Electronics Co.Ltd
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_SAMSUNG_HDMI_H
+#define __PLAT_SAMSUNG_HDMI_H __FILE__
+
+extern void s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
+                                  struct i2c_board_info *mhl_info, int mhl_bus);
+
+#endif /* __PLAT_SAMSUNG_HDMI_H */
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h
deleted file mode 100644
index abb4bc32716..00000000000
--- a/arch/arm/plat-samsung/include/plat/pd.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/pd.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_SAMSUNG_PD_H
-#define __ASM_PLAT_SAMSUNG_PD_H __FILE__
-
-struct samsung_pd_info {
-        int (*enable)(struct device *dev);
-        int (*disable)(struct device *dev);
-        void __iomem *base;
-};
-
-enum exynos4_pd_block {
-        PD_MFC,
-        PD_G3D,
-        PD_LCD0,
-        PD_LCD1,
-        PD_TV,
-        PD_CAM,
-        PD_GPS
-};
-
-#endif /* __ASM_PLAT_SAMSUNG_PD_H */
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index fa95e9a0097..ceba18d23a5 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -18,7 +18,6 @@ struct platform_device;
  * @fb_delay: Slave specific feedback delay.
  *            Refer to FB_CLK_SEL register definition in SPI chapter.
  * @line: Custom 'identity' of the CS line.
- * @set_level: CS line control.
  *
  * This is per SPI-Slave Chipselect information.
  * Allocate and initialize one in machine init code and make the
@@ -27,57 +26,41 @@ struct platform_device;
 struct s3c64xx_spi_csinfo {
         u8 fb_delay;
         unsigned line;
-        void (*set_level)(unsigned line_id, int lvl);
 };
 
 /**
  * struct s3c64xx_spi_info - SPI Controller defining structure
  * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
- * @clk_from_cmu: If the SPI clock/prescalar control block is present
- *     by the platform's clock-management-unit and not in SPI controller.
  * @num_cs: Number of CS this controller emulates.
  * @cfg_gpio: Configure pins for this SPI controller.
- * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
- * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
- * @high_speed: If the controller supports HIGH_SPEED_EN bit
- * @tx_st_done: Depends on tx fifo_lvl field
  */
 struct s3c64xx_spi_info {
         int src_clk_nr;
-        bool clk_from_cmu;
-
         int num_cs;
-
-        int (*cfg_gpio)(struct platform_device *pdev);
-
-        /* Following two fields are for future compatibility */
-        int fifo_lvl_mask;
-        int rx_lvl_offset;
-        int high_speed;
-        int tx_st_done;
+        int (*cfg_gpio)(void);
 };
 
 /**
  * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
  *                              initialization code.
- * @pd: SPI platform data to set.
+ * @cfg_gpio: Pointer to gpio setup function.
  * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
  * @num_cs: Number of elements in the 'cs' array.
  *
  * Call this from machine init code for each SPI Controller that
  * has some chips attached to it.
  */
-extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs);
-extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs);
-extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs);
+extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs);
+extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs);
+extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs);
 
 /* defined by architecture to configure gpio */
-extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
-extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
-extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
+extern int s3c64xx_spi0_cfg_gpio(void);
+extern int s3c64xx_spi1_cfg_gpio(void);
+extern int s3c64xx_spi2_cfg_gpio(void);
 
 extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
 extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
diff --git a/arch/arm/plat-samsung/pd.c b/arch/arm/plat-samsung/pd.c
deleted file mode 100644
index 312b510d86b..00000000000
--- a/arch/arm/plat-samsung/pd.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* linux/arch/arm/plat-samsung/pd.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Samsung Power domain support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <linux/pm_runtime.h>
-
-#include <plat/pd.h>
-
-static int samsung_pd_probe(struct platform_device *pdev)
-{
-        struct samsung_pd_info *pdata = pdev->dev.platform_data;
-        struct device *dev = &pdev->dev;
-
-        if (!pdata) {
-                dev_err(dev, "no device data specified\n");
-                return -ENOENT;
-        }
-
-        pm_runtime_set_active(dev);
-        pm_runtime_enable(dev);
-
-        dev_info(dev, "power domain registered\n");
-        return 0;
-}
-
-static int __devexit samsung_pd_remove(struct platform_device *pdev)
-{
-        struct device *dev = &pdev->dev;
-
-        pm_runtime_disable(dev);
-        return 0;
-}
-
-static int samsung_pd_runtime_suspend(struct device *dev)
-{
-        struct samsung_pd_info *pdata = dev->platform_data;
-        int ret = 0;
-
-        if (pdata->disable)
-                ret = pdata->disable(dev);
-
-        dev_dbg(dev, "suspended\n");
-        return ret;
-}
-
-static int samsung_pd_runtime_resume(struct device *dev)
-{
-        struct samsung_pd_info *pdata = dev->platform_data;
-        int ret = 0;
-
-        if (pdata->enable)
-                ret = pdata->enable(dev);
-
-        dev_dbg(dev, "resumed\n");
-        return ret;
-}
-
-static const struct dev_pm_ops samsung_pd_pm_ops = {
-        .runtime_suspend        = samsung_pd_runtime_suspend,
-        .runtime_resume         = samsung_pd_runtime_resume,
-};
-
-static struct platform_driver samsung_pd_driver = {
-        .driver         = {
-                .name           = "samsung-pd",
-                .owner          = THIS_MODULE,
-                .pm             = &samsung_pd_pm_ops,
-        },
-        .probe          = samsung_pd_probe,
-        .remove         = __devexit_p(samsung_pd_remove),
-};
-
-static int __init samsung_pd_init(void)
-{
-        int ret;
-
-        ret = platform_driver_register(&samsung_pd_driver);
-        if (ret)
-                printk(KERN_ERR "%s: failed to add PD driver\n", __func__);
-
-        return ret;
-}
-arch_initcall(samsung_pd_init);
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 64ab65f0fdb..15070284343 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -74,7 +74,7 @@ unsigned char pm_uart_udivslot;
 
 #ifdef CONFIG_SAMSUNG_PM_DEBUG
 
-struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
+static struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS];
 
 static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save)
 {
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c
deleted file mode 100644
index c559d8438c7..00000000000
--- a/arch/arm/plat-samsung/pwm.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/* arch/arm/plat-s3c/pwm.c
- *
- * Copyright (c) 2007 Ben Dooks
- * Copyright (c) 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
- *
- * S3C series PWM device core
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
-*/
-
-#include <linux/export.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/pwm.h>
-
-#include <mach/map.h>
-
-#include <plat/regs-timer.h>
-
-struct pwm_device {
-        struct list_head         list;
-        struct platform_device  *pdev;
-
-        struct clk              *clk_div;
-        struct clk              *clk;
-        const char              *label;
-
-        unsigned int             period_ns;
-        unsigned int             duty_ns;
-
-        unsigned char            tcon_base;
-        unsigned char            running;
-        unsigned char            use_count;
-        unsigned char            pwm_id;
-};
-
-#define pwm_dbg(_pwm, msg...) dev_dbg(&(_pwm)->pdev->dev, msg)
-
-static struct clk *clk_scaler[2];
-
-static inline int pwm_is_tdiv(struct pwm_device *pwm)
-{
-        return clk_get_parent(pwm->clk) == pwm->clk_div;
-}
-
-static DEFINE_MUTEX(pwm_lock);
-static LIST_HEAD(pwm_list);
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-        struct pwm_device *pwm;
-        int found = 0;
-
-        mutex_lock(&pwm_lock);
-
-        list_for_each_entry(pwm, &pwm_list, list) {
-                if (pwm->pwm_id == pwm_id) {
-                        found = 1;
-                        break;
-                }
-        }
-
-        if (found) {
-                if (pwm->use_count == 0) {
-                        pwm->use_count = 1;
-                        pwm->label = label;
-                } else
-                        pwm = ERR_PTR(-EBUSY);
-        } else
-                pwm = ERR_PTR(-ENOENT);
-
-        mutex_unlock(&pwm_lock);
-        return pwm;
-}
-
-EXPORT_SYMBOL(pwm_request);
-
-
-void pwm_free(struct pwm_device *pwm)
-{
-        mutex_lock(&pwm_lock);
-
-        if (pwm->use_count) {
-                pwm->use_count--;
-                pwm->label = NULL;
-        } else
-                printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id);
-
-        mutex_unlock(&pwm_lock);
-}
-
-EXPORT_SYMBOL(pwm_free);
-
-#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0))
-#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2))
-#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3))
-#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1))
-
-int pwm_enable(struct pwm_device *pwm)
-{
-        unsigned long flags;
-        unsigned long tcon;
-
-        local_irq_save(flags);
-
-        tcon = __raw_readl(S3C2410_TCON);
-        tcon |= pwm_tcon_start(pwm);
-        __raw_writel(tcon, S3C2410_TCON);
-
-        local_irq_restore(flags);
-
-        pwm->running = 1;
-        return 0;
-}
-
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-        unsigned long flags;
-        unsigned long tcon;
-
-        local_irq_save(flags);
-
-        tcon = __raw_readl(S3C2410_TCON);
-        tcon &= ~pwm_tcon_start(pwm);
-        __raw_writel(tcon, S3C2410_TCON);
-
-        local_irq_restore(flags);
-
-        pwm->running = 0;
-}
-
-EXPORT_SYMBOL(pwm_disable);
-
-static unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
-{
-        unsigned long tin_parent_rate;
-        unsigned int div;
-
-        tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div));
-        pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate);
-
-        for (div = 2; div <= 16; div *= 2) {
-                if ((tin_parent_rate / (div << 16)) < freq)
-                        return tin_parent_rate / div;
-        }
-
-        return tin_parent_rate / 16;
-}
-
-#define NS_IN_HZ (1000000000UL)
-
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
-{
-        unsigned long tin_rate;
-        unsigned long tin_ns;
-        unsigned long period;
-        unsigned long flags;
-        unsigned long tcon;
-        unsigned long tcnt;
-        long tcmp;
-
-        /* We currently avoid using 64bit arithmetic by using the
-         * fact that anything faster than 1Hz is easily representable
-         * by 32bits. */
-
-        if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
-                return -ERANGE;
-
-        if (duty_ns > period_ns)
-                return -EINVAL;
-
-        if (period_ns == pwm->period_ns &&
-            duty_ns == pwm->duty_ns)
-                return 0;
-
-        /* The TCMP and TCNT can be read without a lock, they're not
-         * shared between the timers. */
-
-        tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id));
-        tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id));
-
-        period = NS_IN_HZ / period_ns;
-
-        pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n",
-                duty_ns, period_ns, period);
-
-        /* Check to see if we are changing the clock rate of the PWM */
-
-        if (pwm->period_ns != period_ns) {
-                if (pwm_is_tdiv(pwm)) {
-                        tin_rate = pwm_calc_tin(pwm, period);
-                        clk_set_rate(pwm->clk_div, tin_rate);
-                } else
-                        tin_rate = clk_get_rate(pwm->clk);
-
-                pwm->period_ns = period_ns;
-
-                pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate);
-
-                tin_ns = NS_IN_HZ / tin_rate;
-                tcnt = period_ns / tin_ns;
-        } else
-                tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk);
-
-        /* Note, counters count down */
-
-        tcmp = duty_ns / tin_ns;
-        tcmp = tcnt - tcmp;
-        /* the pwm hw only checks the compare register after a decrement,
-           so the pin never toggles if tcmp = tcnt */
-        if (tcmp == tcnt)
-                tcmp--;
-
-        pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
-
-        if (tcmp < 0)
-                tcmp = 0;
-
-        /* Update the PWM register block. */
-
-        local_irq_save(flags);
-
-        __raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id));
-        __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id));
-
-        tcon = __raw_readl(S3C2410_TCON);
-        tcon |= pwm_tcon_manulupdate(pwm);
-        tcon |= pwm_tcon_autoreload(pwm);
-        __raw_writel(tcon, S3C2410_TCON);
-
-        tcon &= ~pwm_tcon_manulupdate(pwm);
-        __raw_writel(tcon, S3C2410_TCON);
-
-        local_irq_restore(flags);
-
-        return 0;
-}
-
-EXPORT_SYMBOL(pwm_config);
-
-static int pwm_register(struct pwm_device *pwm)
-{
-        pwm->duty_ns = -1;
-        pwm->period_ns = -1;
-
-        mutex_lock(&pwm_lock);
-        list_add_tail(&pwm->list, &pwm_list);
-        mutex_unlock(&pwm_lock);
-
-        return 0;
-}
-
-static int s3c_pwm_probe(struct platform_device *pdev)
-{
-        struct device *dev = &pdev->dev;
-        struct pwm_device *pwm;
-        unsigned long flags;
-        unsigned long tcon;
-        unsigned int id = pdev->id;
-        int ret;
-
-        if (id == 4) {
-                dev_err(dev, "TIMER4 is currently not supported\n");
-                return -ENXIO;
-        }
-
-        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
-        if (pwm == NULL) {
-                dev_err(dev, "failed to allocate pwm_device\n");
-                return -ENOMEM;
-        }
-
-        pwm->pdev = pdev;
-        pwm->pwm_id = id;
-
-        /* calculate base of control bits in TCON */
-        pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4;
-
-        pwm->clk = clk_get(dev, "pwm-tin");
-        if (IS_ERR(pwm->clk)) {
-                dev_err(dev, "failed to get pwm tin clk\n");
-                ret = PTR_ERR(pwm->clk);
-                goto err_alloc;
-        }
-
-        pwm->clk_div = clk_get(dev, "pwm-tdiv");
-        if (IS_ERR(pwm->clk_div)) {
-                dev_err(dev, "failed to get pwm tdiv clk\n");
-                ret = PTR_ERR(pwm->clk_div);
-                goto err_clk_tin;
-        }
-
-        clk_enable(pwm->clk);
-        clk_enable(pwm->clk_div);
-
-        local_irq_save(flags);
-
-        tcon = __raw_readl(S3C2410_TCON);
-        tcon |= pwm_tcon_invert(pwm);
-        __raw_writel(tcon, S3C2410_TCON);
-
-        local_irq_restore(flags);
-
-
-        ret = pwm_register(pwm);
-        if (ret) {
-                dev_err(dev, "failed to register pwm\n");
-                goto err_clk_tdiv;
-        }
-
-        pwm_dbg(pwm, "config bits %02x\n",
-                (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f);
-
-        dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
-                 clk_get_rate(pwm->clk),
-                 clk_get_rate(pwm->clk_div),
-                 pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base);
-
-        platform_set_drvdata(pdev, pwm);
-        return 0;
-
- err_clk_tdiv:
-        clk_disable(pwm->clk_div);
-        clk_disable(pwm->clk);
-        clk_put(pwm->clk_div);
-
- err_clk_tin:
-        clk_put(pwm->clk);
-
- err_alloc:
-        kfree(pwm);
-        return ret;
-}
-
-static int __devexit s3c_pwm_remove(struct platform_device *pdev)
-{
-        struct pwm_device *pwm = platform_get_drvdata(pdev);
-
-        clk_disable(pwm->clk_div);
-        clk_disable(pwm->clk);
-        clk_put(pwm->clk_div);
-        clk_put(pwm->clk);
-        kfree(pwm);
-
-        return 0;
-}
-
-#ifdef CONFIG_PM
-static int s3c_pwm_suspend(struct platform_device *pdev, pm_message_t state)
-{
-        struct pwm_device *pwm = platform_get_drvdata(pdev);
-
-        /* No one preserve these values during suspend so reset them
-         * Otherwise driver leaves PWM unconfigured if same values
-         * passed to pwm_config
-         */
-        pwm->period_ns = 0;
-        pwm->duty_ns = 0;
-
-        return 0;
-}
-
-static int s3c_pwm_resume(struct platform_device *pdev)
-{
-        struct pwm_device *pwm = platform_get_drvdata(pdev);
-        unsigned long tcon;
-
-        /* Restore invertion */
-        tcon = __raw_readl(S3C2410_TCON);
-        tcon |= pwm_tcon_invert(pwm);
-        __raw_writel(tcon, S3C2410_TCON);
-
-        return 0;
-}
-
-#else
-#define s3c_pwm_suspend NULL
-#define s3c_pwm_resume NULL
-#endif
-
-static struct platform_driver s3c_pwm_driver = {
-        .driver         = {
-                .name   = "s3c24xx-pwm",
-                .owner  = THIS_MODULE,
-        },
-        .probe          = s3c_pwm_probe,
-        .remove         = __devexit_p(s3c_pwm_remove),
-        .suspend        = s3c_pwm_suspend,
-        .resume         = s3c_pwm_resume,
-};
-
-static int __init pwm_init(void)
-{
-        int ret;
-
-        clk_scaler[0] = clk_get(NULL, "pwm-scaler0");
-        clk_scaler[1] = clk_get(NULL, "pwm-scaler1");
-
-        if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) {
-                printk(KERN_ERR "%s: failed to get scaler clocks\n", __func__);
-                return -EINVAL;
-        }
-
-        ret = platform_driver_register(&s3c_pwm_driver);
-        if (ret)
-                printk(KERN_ERR "%s: failed to add pwm driver\n", __func__);
-
-        return ret;
-}
-
-arch_initcall(pwm_init);
diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c
index 78149491282..f99448c48d3 100644
--- a/arch/arm/plat-samsung/s3c-dma-ops.c
+++ b/arch/arm/plat-samsung/s3c-dma-ops.c
@@ -36,30 +36,26 @@ static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param,
 }
 
 static unsigned s3c_dma_request(enum dma_ch dma_ch,
-                                 struct samsung_dma_info *info)
+                                        struct samsung_dma_req *param)
 {
         struct cb_data *data;
 
-        if (s3c2410_dma_request(dma_ch, info->client, NULL) < 0) {
-                s3c2410_dma_free(dma_ch, info->client);
+        if (s3c2410_dma_request(dma_ch, param->client, NULL) < 0) {
+                s3c2410_dma_free(dma_ch, param->client);
                 return 0;
         }
 
+        if (param->cap == DMA_CYCLIC)
+                s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR);
+
         data = kzalloc(sizeof(struct cb_data), GFP_KERNEL);
         data->ch = dma_ch;
         list_add_tail(&data->node, &dma_list);
 
-        s3c2410_dma_devconfig(dma_ch, info->direction, info->fifo);
-
-        if (info->cap == DMA_CYCLIC)
-                s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR);
-
-        s3c2410_dma_config(dma_ch, info->width);
-
         return (unsigned)dma_ch;
 }
 
-static int s3c_dma_release(unsigned ch, struct s3c2410_dma_client *client)
+static int s3c_dma_release(unsigned ch, void *param)
 {
         struct cb_data *data;
 
@@ -68,16 +64,24 @@ static int s3c_dma_release(unsigned ch, struct s3c2410_dma_client *client)
                         break;
         list_del(&data->node);
 
-        s3c2410_dma_free(ch, client);
+        s3c2410_dma_free(ch, param);
         kfree(data);
 
         return 0;
 }
 
-static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep_info *info)
+static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param)
+{
+        s3c2410_dma_devconfig(ch, param->direction, param->fifo);
+        s3c2410_dma_config(ch, param->width);
+
+        return 0;
+}
+
+static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param)
 {
         struct cb_data *data;
-        int len = (info->cap == DMA_CYCLIC) ? info->period : info->len;
+        int len = (param->cap == DMA_CYCLIC) ? param->period : param->len;
 
         list_for_each_entry(data, &dma_list, node)
                 if (data->ch == ch)
@@ -85,11 +89,11 @@ static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep_info *info)
 
         if (!data->fp) {
                 s3c2410_dma_set_buffdone_fn(ch, s3c_dma_cb);
-                data->fp = info->fp;
-                data->fp_param = info->fp_param;
+                data->fp = param->fp;
+                data->fp_param = param->fp_param;
         }
 
-        s3c2410_dma_enqueue(ch, (void *)data, info->buf, len);
+        s3c2410_dma_enqueue(ch, (void *)data, param->buf, len);
 
         return 0;
 }
@@ -117,6 +121,7 @@ static inline int s3c_dma_stop(unsigned ch)
 static struct samsung_dma_ops s3c_dma_ops = {
         .request        = s3c_dma_request,
         .release        = s3c_dma_release,
+        .config         = s3c_dma_config,
         .prepare        = s3c_dma_prepare,
         .trigger        = s3c_dma_trigger,
         .started        = s3c_dma_started,
diff --git a/arch/arm/plat-spear/include/plat/keyboard.h b/arch/arm/plat-spear/include/plat/keyboard.h
index 0562f134621..9248e3a7e33 100644
--- a/arch/arm/plat-spear/include/plat/keyboard.h
+++ b/arch/arm/plat-spear/include/plat/keyboard.h
@@ -149,6 +149,7 @@ int _name[] = { \
  * keymap: pointer to keymap data (table and size)
  * rep: enables key autorepeat
  * mode: choose keyboard support(9x9, 6x6, 2x2)
+ * suspended_rate: rate at which keyboard would operate in suspended mode
  *
  * This structure is supposed to be used by platform code to supply
  * keymaps to drivers that implement keyboards.
@@ -157,6 +158,7 @@ struct kbd_platform_data {
         const struct matrix_keymap_data *keymap;
         bool rep;
         unsigned int mode;
+        unsigned int suspended_rate;
 };
 
 #endif /* __PLAT_KEYBOARD_H */
diff --git a/arch/arm/plat-spear/include/plat/pl080.h b/arch/arm/plat-spear/include/plat/pl080.h
index 2bc6b54460a..eb6590ded40 100644
--- a/arch/arm/plat-spear/include/plat/pl080.h
+++ b/arch/arm/plat-spear/include/plat/pl080.h
@@ -14,8 +14,8 @@
 #ifndef __PLAT_PL080_H
 #define __PLAT_PL080_H
 
-struct pl08x_dma_chan;
-int pl080_get_signal(struct pl08x_dma_chan *ch);
-void pl080_put_signal(struct pl08x_dma_chan *ch);
+struct pl08x_channel_data;
+int pl080_get_signal(const struct pl08x_channel_data *cd);
+void pl080_put_signal(const struct pl08x_channel_data *cd, int signal);
 
 #endif /* __PLAT_PL080_H */
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
index 12cf27f935f..cfa1199d0f4 100644
--- a/arch/arm/plat-spear/pl080.c
+++ b/arch/arm/plat-spear/pl080.c
@@ -27,9 +27,8 @@ struct {
         unsigned char val;
 } signals[16] = {{0, 0}, };
 
-int pl080_get_signal(struct pl08x_dma_chan *ch)
+int pl080_get_signal(const struct pl08x_channel_data *cd)
 {
-        const struct pl08x_channel_data *cd = ch->cd;
         unsigned int signal = cd->min_signal, val;
         unsigned long flags;
 
@@ -63,18 +62,17 @@ int pl080_get_signal(struct pl08x_dma_chan *ch)
         return signal;
 }
 
-void pl080_put_signal(struct pl08x_dma_chan *ch)
+void pl080_put_signal(const struct pl08x_channel_data *cd, int signal)
 {
-        const struct pl08x_channel_data *cd = ch->cd;
         unsigned long flags;
 
         spin_lock_irqsave(&lock, flags);
 
         /* if signal is not used */
-        if (!signals[cd->min_signal].busy)
+        if (!signals[signal].busy)
                 BUG();
 
-        signals[cd->min_signal].busy--;
+        signals[signal].busy--;
 
         spin_unlock_irqrestore(&lock, flags);
 }
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 81ee7cc3445..8d5c10a5084 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -1,5 +1,8 @@
 if PLAT_VERSATILE
 
+config PLAT_VERSATILE_CLOCK
+        bool
+
 config PLAT_VERSATILE_CLCD
         bool
 
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index a5cb1945bdc..272769a8a7d 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,4 +1,4 @@
-obj-y   := clock.o
+obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
 obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index 49c7db48c7f..d7c5c171f5a 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -85,7 +85,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * the boot monitor to read the system wide flags register,
          * and branch to the address found there.
          */
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        gic_raise_softirq(cpumask_of(cpu), 0);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index 4fa9903b83c..cc926c98598 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -7,18 +7,20 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
- *
- * Basic entry code, called from the kernel's undefined instruction trap.
- *  r0  = faulted instruction
- *  r5  = faulted PC+4
- *  r9  = successful return
- *  r10 = thread_info structure
- *  lr  = failure return
  */
 #include <asm/thread_info.h>
 #include <asm/vfpmacros.h>
 #include "../kernel/entry-header.S"
 
+@ VFP entry point.
+@
+@  r0  = instruction opcode (32-bit ARM or two 16-bit Thumb)
+@  r2  = PC value to resume execution after successful emulation
+@  r9  = normal "successful" return address
+@  r10 = this threads thread_info structure
+@  lr  = unrecognised instruction return address
+@  IRQs disabled.
+@
 ENTRY(do_vfp)
 #ifdef CONFIG_PREEMPT
         ldr     r4, [r10, #TI_PREEMPT]  @ get preempt count
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 2d30c7f6edd..ea0349f6358 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -16,6 +16,7 @@
  */
 #include <asm/thread_info.h>
 #include <asm/vfpmacros.h>
+#include <linux/kern_levels.h>
 #include "../kernel/entry-header.S"
 
         .macro  DBGSTR, str
@@ -24,7 +25,7 @@
         add     r0, pc, #4
         bl      printk
         b       1f
-        .asciz  "<7>VFP: \str\n"
+        .asciz  KERN_DEBUG "VFP: \str\n"
         .balign 4
 1:      ldmfd   sp!, {r0-r3, ip, lr}
 #endif
@@ -37,7 +38,7 @@
         add     r0, pc, #4
         bl      printk
         b       1f
-        .asciz  "<7>VFP: \str\n"
+        .asciz  KERN_DEBUG "VFP: \str\n"
         .balign 4
 1:      ldmfd   sp!, {r0-r3, ip, lr}
 #endif
@@ -52,7 +53,7 @@
         add     r0, pc, #4
         bl      printk
         b       1f
-        .asciz  "<7>VFP: \str\n"
+        .asciz  KERN_DEBUG "VFP: \str\n"
         .balign 4
 1:      ldmfd   sp!, {r0-r3, ip, lr}
 #endif
@@ -61,13 +62,13 @@
 
 @ VFP hardware support entry point.
 @
-@  r0  = faulted instruction
-@  r2  = faulted PC+4
-@  r9  = successful return
+@  r0  = instruction opcode (32-bit ARM or two 16-bit Thumb)
+@  r2  = PC value to resume execution after successful emulation
+@  r9  = normal "successful" return address
 @  r10 = vfp_state union
 @  r11 = CPU number
-@  lr  = failure return
-
+@  lr  = unrecognised instruction return address
+@  IRQs enabled.
 ENTRY(vfp_support_entry)
         DBGSTR3 "instr %08x pc %08x state %p", r0, r2, r10
 
@@ -161,9 +162,12 @@ vfp_hw_state_valid:
                                         @ exception before retrying branch
                                         @ out before setting an FPEXC that
                                         @ stops us reading stuff
-        VFPFMXR FPEXC, r1               @ restore FPEXC last
-        sub     r2, r2, #4
-        str     r2, [sp, #S_PC]         @ retry the instruction
+        VFPFMXR FPEXC, r1               @ Restore FPEXC last
+        sub     r2, r2, #4              @ Retry current instruction - if Thumb
+        str     r2, [sp, #S_PC]         @ mode it's two 16-bit instructions,
+                                        @ else it's one 32-bit instruction, so
+                                        @ always subtract 4 from the following
+                                        @ instruction address.
 #ifdef CONFIG_PREEMPT
         get_thread_info r10
         ldr     r4, [r10, #TI_PREEMPT]  @ get preempt count
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 586961929e9..c834b32af27 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -457,10 +457,16 @@ static int vfp_pm_suspend(void)
 
                 /* disable, just in case */
                 fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
+        } else if (vfp_current_hw_state[ti->cpu]) {
+#ifndef CONFIG_SMP
+                fmxr(FPEXC, fpexc | FPEXC_EN);
+                vfp_save_state(vfp_current_hw_state[ti->cpu], fpexc);
+                fmxr(FPEXC, fpexc);
+#endif
         }
 
         /* clear any information we had about last context state */
-        memset(vfp_current_hw_state, 0, sizeof(vfp_current_hw_state));
+        vfp_current_hw_state[ti->cpu] = NULL;
 
         return 0;
 }
@@ -713,8 +719,10 @@ static int __init vfp_init(void)
                         if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
                                 elf_hwcap |= HWCAP_NEON;
 #endif
+#ifdef CONFIG_VFPv3
                         if ((fmrx(MVFR1) & 0xf0000000) == 0x10000000)
                                 elf_hwcap |= HWCAP_VFPv4;
+#endif
                 }
         }
         return 0;
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 71d38c76726..5ade51c8a87 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -12,6 +12,7 @@ config AVR32
         select HARDIRQS_SW_RESEND
         select GENERIC_IRQ_SHOW
         select ARCH_HAVE_CUSTOM_GPIO_H
+        select ARCH_WANT_IPC_PARSE_VERSION
         select ARCH_HAVE_NMI_SAFE_CMPXCHG
         select GENERIC_CLOCKEVENTS
         help
diff --git a/arch/avr32/boards/atstk1000/atstk1002.c b/arch/avr32/boards/atstk1000/atstk1002.c
index dc526332148..6c80aba7bf9 100644
--- a/arch/avr32/boards/atstk1000/atstk1002.c
+++ b/arch/avr32/boards/atstk1000/atstk1002.c
@@ -97,7 +97,7 @@ static struct atmel_nand_data atstk1006_nand_data __initdata = {
         .enable_pin     = GPIO_PIN_PB(29),
         .ecc_mode       = NAND_ECC_SOFT,
         .parts          = nand_partitions,
-        .num_parts      = ARRAY_SIZE(num_partitions),
+        .num_parts      = ARRAY_SIZE(nand_partitions),
 };
 #endif
 
diff --git a/arch/avr32/include/asm/kmap_types.h b/arch/avr32/include/asm/kmap_types.h
index b7f5c687010..479330b8979 100644
--- a/arch/avr32/include/asm/kmap_types.h
+++ b/arch/avr32/include/asm/kmap_types.h
@@ -2,29 +2,9 @@
 #define __ASM_AVR32_KMAP_TYPES_H
 
 #ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
+# define KM_TYPE_NR 29
 #else
-# define D(n)
+# define KM_TYPE_NR 14
 #endif
 
-enum km_type {
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_PTE2,
-D(10)   KM_IRQ0,
-D(11)   KM_IRQ1,
-D(12)   KM_SOFTIRQ0,
-D(13)   KM_SOFTIRQ1,
-D(14)   KM_TYPE_NR
-};
-
-#undef D
-
 #endif /* __ASM_AVR32_KMAP_TYPES_H */
diff --git a/arch/avr32/include/asm/unistd.h b/arch/avr32/include/asm/unistd.h
index f714544e556..1358e366f4b 100644
--- a/arch/avr32/include/asm/unistd.h
+++ b/arch/avr32/include/asm/unistd.h
@@ -318,7 +318,6 @@
 /* SMP stuff */
 #define __IGNORE_getcpu
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_ALARM
 #define __ARCH_WANT_SYS_GETHOSTNAME
diff --git a/arch/avr32/mm/fault.c b/arch/avr32/mm/fault.c
index f7040a1e399..b92e6095861 100644
--- a/arch/avr32/mm/fault.c
+++ b/arch/avr32/mm/fault.c
@@ -61,10 +61,10 @@ asmlinkage void do_page_fault(unsigned long ecr, struct pt_regs *regs)
         const struct exception_table_entry *fixup;
         unsigned long address;
         unsigned long page;
-        int writeaccess;
         long signr;
         int code;
         int fault;
+        unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
 
         if (notify_page_fault(regs, ecr))
                 return;
@@ -86,6 +86,7 @@ asmlinkage void do_page_fault(unsigned long ecr, struct pt_regs *regs)
 
         local_irq_enable();
 
+retry:
         down_read(&mm->mmap_sem);
 
         vma = find_vma(mm, address);
@@ -104,7 +105,6 @@ asmlinkage void do_page_fault(unsigned long ecr, struct pt_regs *regs)
          */
 good_area:
         code = SEGV_ACCERR;
-        writeaccess = 0;
 
         switch (ecr) {
         case ECR_PROTECTION_X:
@@ -121,7 +121,7 @@ good_area:
         case ECR_TLB_MISS_W:
                 if (!(vma->vm_flags & VM_WRITE))
                         goto bad_area;
-                writeaccess = 1;
+                flags |= FAULT_FLAG_WRITE;
                 break;
         default:
                 panic("Unhandled case %lu in do_page_fault!", ecr);
@@ -132,7 +132,11 @@ good_area:
          * sure we exit gracefully rather than endlessly redo the
          * fault.
          */
-        fault = handle_mm_fault(mm, vma, address, writeaccess ? FAULT_FLAG_WRITE : 0);
+        fault = handle_mm_fault(mm, vma, address, flags);
+
+        if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
+                return;
+
         if (unlikely(fault & VM_FAULT_ERROR)) {
                 if (fault & VM_FAULT_OOM)
                         goto out_of_memory;
@@ -140,10 +144,23 @@ good_area:
                         goto do_sigbus;
                 BUG();
         }
-        if (fault & VM_FAULT_MAJOR)
-                tsk->maj_flt++;
-        else
-                tsk->min_flt++;
+
+        if (flags & FAULT_FLAG_ALLOW_RETRY) {
+                if (fault & VM_FAULT_MAJOR)
+                        tsk->maj_flt++;
+                else
+                        tsk->min_flt++;
+                if (fault & VM_FAULT_RETRY) {
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+
+                        /*
+                         * No need to up_read(&mm->mmap_sem) as we would have
+                         * already released it in __lock_page_or_retry() in
+                         * mm/filemap.c.
+                         */
+                        goto retry;
+                }
+        }
 
         up_read(&mm->mmap_sem);
         return;
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index fef96f47876..f3486192063 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -33,6 +33,7 @@ config BLACKFIN
         select HAVE_PERF_EVENTS
         select ARCH_HAVE_CUSTOM_GPIO_H
         select ARCH_WANT_OPTIONAL_GPIOLIB
+        select ARCH_WANT_IPC_PARSE_VERSION
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_ATOMIC64
         select GENERIC_IRQ_PROBE
@@ -352,6 +353,11 @@ config MEM_MT48H32M16LFCJ_75
         depends on (BFIN526_EZBRD)
         default y
 
+config MEM_MT47H64M16
+        bool
+        depends on (BFIN609_EZKIT)
+        default y
+
 source "arch/blackfin/mach-bf518/Kconfig"
 source "arch/blackfin/mach-bf527/Kconfig"
 source "arch/blackfin/mach-bf533/Kconfig"
@@ -399,8 +405,9 @@ config ROM_BASE
         hex "Kernel ROM Base"
         depends on ROMKERNEL
         default "0x20040040"
-        range 0x20000000 0x20400000 if !(BF54x || BF561)
+        range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
         range 0x20000000 0x30000000 if (BF54x || BF561)
+        range 0xB0000000 0xC0000000 if (BF60x)
         help
           Make sure your ROM base does not include any file-header
           information that is prepended to the kernel.
@@ -996,19 +1003,15 @@ config BFIN_GPTIMERS
           To compile this driver as a module, choose M here: the module
           will be called gptimers.
 
-config HAVE_PWM
-        tristate "Enable PWM API support"
-        depends on BFIN_GPTIMERS
-        help
-          Enable support for the Pulse Width Modulation framework (as
-          found in linux/pwm.h).
-
-          To compile this driver as a module, choose M here: the module
-          will be called pwm.
-
 choice
         prompt "Uncached DMA region"
         default DMA_UNCACHED_1M
+config DMA_UNCACHED_32M
+        bool "Enable 32M DMA region"
+config DMA_UNCACHED_16M
+        bool "Enable 16M DMA region"
+config DMA_UNCACHED_8M
+        bool "Enable 8M DMA region"
 config DMA_UNCACHED_4M
         bool "Enable 4M DMA region"
 config DMA_UNCACHED_2M
@@ -1038,7 +1041,7 @@ config BFIN_EXTMEM_ICACHEABLE
 config BFIN_L2_ICACHEABLE
         bool "Enable ICACHE for L2 SRAM"
         depends on BFIN_ICACHE
-        depends on BF54x || BF561
+        depends on (BF54x || BF561 || BF60x) && !SMP
         default n
 
 config BFIN_DCACHE
diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig
index be9526bee4f..f4b02350e41 100644
--- a/arch/blackfin/configs/BF609-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF609-EZKIT_defconfig
@@ -90,6 +90,7 @@ CONFIG_INPUT_BFIN_ROTARY=y
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_SIMPLE_TIMER=m
+# CONFIG_BFIN_CRC is not set
 CONFIG_BFIN_LINKPORT=y
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
@@ -153,3 +154,4 @@ CONFIG_CRYPTO_MD4=y
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_ARC4=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_BFIN_CRC=y
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 608be5e6d25..dc47d79287f 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -14,7 +14,13 @@
 #include <linux/linkage.h>
 #include <linux/types.h>
 
-#if defined(CONFIG_DMA_UNCACHED_4M)
+#if defined(CONFIG_DMA_UNCACHED_32M)
+# define DMA_UNCACHED_REGION (32 * 1024 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_16M)
+# define DMA_UNCACHED_REGION (16 * 1024 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_8M)
+# define DMA_UNCACHED_REGION (8 * 1024 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_4M)
 # define DMA_UNCACHED_REGION (4 * 1024 * 1024)
 #elif defined(CONFIG_DMA_UNCACHED_2M)
 # define DMA_UNCACHED_REGION (2 * 1024 * 1024)
diff --git a/arch/blackfin/include/asm/bfin_crc.h b/arch/blackfin/include/asm/bfin_crc.h
index 3deb4452cee..75cef4dc85a 100644
--- a/arch/blackfin/include/asm/bfin_crc.h
+++ b/arch/blackfin/include/asm/bfin_crc.h
@@ -79,20 +79,6 @@ struct crc_register {
         u32 revid;
 };
 
-struct bfin_crc {
-        struct miscdevice mdev;
-        struct list_head list;
-        int irq;
-        int dma_ch_src;
-        int dma_ch_dest;
-        volatile struct crc_register *regs;
-        struct crc_info *info;
-        struct mutex mutex;
-        struct completion c;
-        unsigned short opmode;
-        char name[20];
-};
-
 /* CRC_STATUS Masks */
 #define CMPERR                  0x00000002      /* Compare error */
 #define DCNTEXP                 0x00000010      /* datacnt register expired */
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
index 8597158010b..2d90d62edc9 100644
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -282,7 +282,7 @@ struct bfin_uart_regs {
 #define UART_GET_GCTL(p)      UART_GET_CTL(p)
 #define UART_GET_LCR(p)       UART_GET_CTL(p)
 #define UART_GET_MCR(p)       UART_GET_CTL(p)
-#if ANOMALY_05001001
+#if ANOMALY_16000030
 #define UART_GET_STAT(p) \
 ({ \
         u32 __ret; \
diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h
index aadfb1ad1fa..b2d5e733079 100644
--- a/arch/blackfin/include/asm/bfin_simple_timer.h
+++ b/arch/blackfin/include/asm/bfin_simple_timer.h
@@ -17,5 +17,11 @@
 #define BFIN_SIMPLE_TIMER_START      _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  6)
 #define BFIN_SIMPLE_TIMER_STOP       _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  8)
 #define BFIN_SIMPLE_TIMER_READ       _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
+#define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11)
+
+#define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT              0
+#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT              1
+#define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP                 2
+#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ        3
 
 #endif
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
index 2f3339a4762..f4a07278743 100644
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ b/arch/blackfin/include/asm/bfin_twi.h
@@ -66,9 +66,9 @@ struct bfin_twi_iface {
 
 #define DEFINE_TWI_REG(reg_name, reg) \
 static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
-        { return iface->regs_base->reg; } \
+        { return bfin_read16(&iface->regs_base->reg); } \
 static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
-        { iface->regs_base->reg = v; }
+        { bfin_write16(&iface->regs_base->reg, v); }
 
 DEFINE_TWI_REG(CLKDIV, clkdiv)
 DEFINE_TWI_REG(CONTROL, control)
@@ -84,7 +84,7 @@ DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
 DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
 DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
 DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
-#if !ANOMALY_05001001
+#if !ANOMALY_16000030
 DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
 DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
 #else
@@ -94,7 +94,7 @@ static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
         unsigned long flags;
 
         flags = hard_local_irq_save();
-        ret = iface->regs_base->rcv_data8;
+        ret = bfin_read16(&iface->regs_base->rcv_data8);
         hard_local_irq_restore(flags);
 
         return ret;
@@ -106,7 +106,7 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
         unsigned long flags;
 
         flags = hard_local_irq_save();
-        ret = iface->regs_base->rcv_data16;
+        ret = bfin_read16(&iface->regs_base->rcv_data16);
         hard_local_irq_restore(flags);
 
         return ret;
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
index 1f9060395a0..507e7aa6a56 100644
--- a/arch/blackfin/include/asm/context.S
+++ b/arch/blackfin/include/asm/context.S
@@ -396,3 +396,12 @@
         call \func;
 #endif
 .endm
+
+#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
+# define EX_SCRATCH_REG RETN
+#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
+# define EX_SCRATCH_REG RETE
+#else
+# define EX_SCRATCH_REG CYCLES
+#endif
+
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index e91eae8330a..2673b11376f 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -280,7 +280,7 @@
         PM_POP_SYNC(9)
 #endif
 
-#ifdef EBIU_AMBCTL
+#ifdef EBIU_AMGCTL
         PM_SYS_POP(9, EBIU_AMBCTL1)
         PM_SYS_POP(8, EBIU_AMBCTL0)
         PM_SYS_POP16(7, EBIU_AMGCTL)
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 3d84d96f7c2..98d0133346b 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -141,6 +141,8 @@ static inline void bfin_pm_standby_restore(void)
 
 void bfin_gpio_pm_hibernate_restore(void);
 void bfin_gpio_pm_hibernate_suspend(void);
+void bfin_pint_suspend(void);
+void bfin_pint_resume(void);
 
 # if !BFIN_GPIO_PINT
 int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 89de539ed01..4ae1144a457 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -20,6 +20,16 @@
 /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
 #include <mach/irq.h>
 
+/*
+ * pm save bfin pint registers
+ */
+struct bfin_pm_pint_save {
+        u32 mask_set;
+        u32 assign;
+        u32 edge_set;
+        u32 invert_set;
+};
+
 #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
 # define NOP_PAD_ANOMALY_05000244 "nop; nop;"
 #else
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 237579935e2..f019e9bcefe 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -6,6 +6,9 @@
  * Licensed under the GPL-2 or later.
  */
 
+#ifndef __MEM_INIT_H__
+#define __MEM_INIT_H__
+
 #if defined(EBIU_SDGCTL)
 #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
     defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
@@ -277,3 +280,212 @@
 #else
 #define PLL_BYPASS       0
 #endif
+
+#ifdef CONFIG_BF60x
+
+/* DMC status bits */
+#define IDLE                    0x1
+#define MEMINITDONE             0x4
+#define SRACK                   0x8
+#define PDACK                   0x10
+#define DPDACK                  0x20
+#define DLLCALDONE              0x2000
+#define PENDREF                 0xF0000
+#define PHYRDPHASE              0xF00000
+#define PHYRDPHASE_OFFSET       20
+
+/* DMC control bits */
+#define LPDDR                   0x2
+#define INIT                    0x4
+#define SRREQ                   0x8
+#define PDREQ                   0x10
+#define DPDREQ                  0x20
+#define PREC                    0x40
+#define ADDRMODE                0x100
+#define RDTOWR                  0xE00
+#define PPREF                   0x1000
+#define DLLCAL                  0x2000
+
+/* DMC DLL control bits */
+#define DLLCALRDCNT             0xFF
+#define DATACYC                 0xF00
+#define DATACYC_OFFSET          8
+
+/* CGU Divisor bits */
+#define CSEL_OFFSET             0
+#define S0SEL_OFFSET            5
+#define SYSSEL_OFFSET           8
+#define S1SEL_OFFSET            13
+#define DSEL_OFFSET             16
+#define OSEL_OFFSET             22
+#define ALGN                    0x20000000
+#define UPDT                    0x40000000
+#define LOCK                    0x80000000
+
+/* CGU Status bits */
+#define PLLEN                   0x1
+#define PLLBP                   0x2
+#define PLOCK                   0x4
+#define CLKSALGN                0x8
+
+/* CGU Control bits */
+#define MSEL_MASK               0x7F00
+#define DF_MASK                 0x1
+
+struct ddr_config {
+        u32 ddr_clk;
+        u32 dmc_ddrctl;
+        u32 dmc_ddrcfg;
+        u32 dmc_ddrtr0;
+        u32 dmc_ddrtr1;
+        u32 dmc_ddrtr2;
+        u32 dmc_ddrmr;
+        u32 dmc_ddrmr1;
+};
+
+#if defined(CONFIG_MEM_MT47H64M16)
+static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
+        [0] = {
+                .ddr_clk    = 125,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20705212,
+                .dmc_ddrtr1 = 0x201003CF,
+                .dmc_ddrtr2 = 0x00320107,
+                .dmc_ddrmr  = 0x00000422,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [1] = {
+                .ddr_clk    = 133,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20806313,
+                .dmc_ddrtr1 = 0x2013040D,
+                .dmc_ddrtr2 = 0x00320108,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [2] = {
+                .ddr_clk    = 150,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20A07323,
+                .dmc_ddrtr1 = 0x20160492,
+                .dmc_ddrtr2 = 0x00320209,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [3] = {
+                .ddr_clk    = 166,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20A07323,
+                .dmc_ddrtr1 = 0x2016050E,
+                .dmc_ddrtr2 = 0x00320209,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [4] = {
+                .ddr_clk    = 200,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20a07323,
+                .dmc_ddrtr1 = 0x2016050f,
+                .dmc_ddrtr2 = 0x00320509,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [5] = {
+                .ddr_clk    = 225,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20E0A424,
+                .dmc_ddrtr1 = 0x302006DB,
+                .dmc_ddrtr2 = 0x0032020D,
+                .dmc_ddrmr  = 0x00000842,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [6] = {
+                .ddr_clk    = 250,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20E0A424,
+                .dmc_ddrtr1 = 0x3020079E,
+                .dmc_ddrtr2 = 0x0032020D,
+                .dmc_ddrmr  = 0x00000842,
+                .dmc_ddrmr1 = 0x4,
+        },
+};
+#endif
+
+static inline void dmc_enter_self_refresh(void)
+{
+        if (bfin_read_DMC0_STAT() & MEMINITDONE) {
+                bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
+                while (!(bfin_read_DMC0_STAT() & SRACK))
+                        continue;
+        }
+}
+
+static inline void dmc_exit_self_refresh(void)
+{
+        if (bfin_read_DMC0_STAT() & MEMINITDONE) {
+                bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
+                while (bfin_read_DMC0_STAT() & SRACK)
+                        continue;
+        }
+}
+
+static inline void init_cgu(u32 cgu_div, u32 cgu_ctl)
+{
+        dmc_enter_self_refresh();
+
+        /* Don't set the same value of MSEL and DF to CGU_CTL */
+        if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK))
+                != cgu_ctl) {
+                bfin_write32(CGU0_DIV, cgu_div);
+                bfin_write32(CGU0_CTL, cgu_ctl);
+                while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) ||
+                        !(bfin_read32(CGU0_STAT) & PLOCK))
+                        continue;
+        }
+
+        bfin_write32(CGU0_DIV, cgu_div | UPDT);
+        while (bfin_read32(CGU0_STAT) & CLKSALGN)
+                continue;
+
+        dmc_exit_self_refresh();
+}
+
+static inline void init_dmc(u32 dmc_clk)
+{
+        int i, dlldatacycle, dll_ctl;
+
+        for (i = 0; i < 7; i++) {
+                if (ddr_config_table[i].ddr_clk == dmc_clk) {
+                        bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
+                        bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
+                        bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
+                        bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
+                        bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
+                        bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
+                        bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
+                        break;
+                }
+        }
+
+        while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
+                continue;
+
+        dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET;
+        dll_ctl = bfin_read_DMC0_DLLCTL();
+        dll_ctl &= ~DATACYC;
+        bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
+
+        while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
+                continue;
+}
+#endif
+
+#endif /*__MEM_INIT_H__*/
+
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
index 70c4e511cae..cec771b8100 100644
--- a/arch/blackfin/include/asm/traps.h
+++ b/arch/blackfin/include/asm/traps.h
@@ -125,5 +125,7 @@
         level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
         level "   only instructions.\n"
 
+extern void double_fault_c(struct pt_regs *fp);
+
 #endif                          /* __ASSEMBLY__ */
 #endif                          /* _BFIN_TRAPS_H */
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 3287222cba3..5b2a0748d7d 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -434,7 +434,6 @@
 #define __IGNORE_getcpu
 
 #ifdef __KERNEL__
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_ALARM
 #define __ARCH_WANT_SYS_GETHOSTNAME
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 08e6625106b..735f24e0742 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -21,7 +21,6 @@ obj-$(CONFIG_FUNCTION_TRACER)        += ftrace-entry.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)  += ftrace.o
 CFLAGS_REMOVE_ftrace.o = -pg
 
-obj-$(CONFIG_HAVE_PWM)               += pwm.o
 obj-$(CONFIG_IPIPE)                  += ipipe.o
 obj-$(CONFIG_BFIN_GPTIMERS)          += gptimers.o
 obj-$(CONFIG_CPLB_INFO)              += cplbinfo.o
diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c
index c166939ffb2..4a32f2dd5dd 100644
--- a/arch/blackfin/kernel/bfin_dma.c
+++ b/arch/blackfin/kernel/bfin_dma.c
@@ -45,7 +45,7 @@ static int __init blackfin_dma_init(void)
                 atomic_set(&dma_ch[i].chan_status, 0);
                 dma_ch[i].regs = dma_io_base_addr[i];
         }
-#ifdef CH_MEM_STREAM3_SRC
+#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
         /* Mark MEMDMA Channel 3 as requested since we're using it internally */
         request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
         request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
@@ -361,7 +361,7 @@ void __init early_dma_memcpy_done(void)
         __builtin_bfin_ssync();
 }
 
-#ifdef CH_MEM_STREAM3_SRC
+#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
 #define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
 #define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
 #define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 3e366dc2d6e..34e96ce02aa 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -58,12 +58,20 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
 
 #ifdef CONFIG_ROMKERNEL
         /* Cover kernel XIP flash area */
+#ifdef CONFIG_BF60x
+        addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1);
+        d_tbl[i_d].addr = addr;
+        d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB;
+        i_tbl[i_i].addr = addr;
+        i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB;
+#else
         addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
         d_tbl[i_d].addr = addr;
         d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
         i_tbl[i_i].addr = addr;
         i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
 #endif
+#endif
 
         /* Cover L1 memory.  One 4M area for code and data each is enough.  */
         if (cpu == 0) {
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
index f0d1118f182..e7be6532d6a 100644
--- a/arch/blackfin/kernel/dma-mapping.c
+++ b/arch/blackfin/kernel/dma-mapping.c
@@ -122,12 +122,13 @@ void __dma_sync(dma_addr_t addr, size_t size,
 EXPORT_SYMBOL(__dma_sync);
 
 int
-dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+dma_map_sg(struct device *dev, struct scatterlist *sg_list, int nents,
            enum dma_data_direction direction)
 {
+        struct scatterlist *sg;
         int i;
 
-        for (i = 0; i < nents; i++, sg++) {
+        for_each_sg(sg_list, sg, nents, i) {
                 sg->dma_address = (dma_addr_t) sg_virt(sg);
                 __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
         }
@@ -136,12 +137,13 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 }
 EXPORT_SYMBOL(dma_map_sg);
 
-void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg_list,
                             int nelems, enum dma_data_direction direction)
 {
+        struct scatterlist *sg;
         int i;
 
-        for (i = 0; i < nelems; i++, sg++) {
+        for_each_sg(sg_list, sg, nelems, i) {
                 sg->dma_address = (dma_addr_t) sg_virt(sg);
                 __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
         }
diff --git a/arch/blackfin/kernel/pwm.c b/arch/blackfin/kernel/pwm.c
deleted file mode 100644
index 33f5942733b..00000000000
--- a/arch/blackfin/kernel/pwm.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Blackfin Pulse Width Modulation (PWM) core
- *
- * Copyright (c) 2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/pwm.h>
-#include <linux/slab.h>
-
-#include <asm/gptimers.h>
-#include <asm/portmux.h>
-
-struct pwm_device {
-        unsigned id;
-        unsigned short pin;
-};
-
-static const unsigned short pwm_to_gptimer_per[] = {
-        P_TMR0, P_TMR1, P_TMR2, P_TMR3, P_TMR4, P_TMR5,
-        P_TMR6, P_TMR7, P_TMR8, P_TMR9, P_TMR10, P_TMR11,
-};
-
-struct pwm_device *pwm_request(int pwm_id, const char *label)
-{
-        struct pwm_device *pwm;
-        int ret;
-
-        /* XXX: pwm_id really should be unsigned */
-        if (pwm_id < 0)
-                return NULL;
-
-        pwm = kzalloc(sizeof(*pwm), GFP_KERNEL);
-        if (!pwm)
-                return pwm;
-
-        pwm->id = pwm_id;
-        if (pwm->id >= ARRAY_SIZE(pwm_to_gptimer_per))
-                goto err;
-
-        pwm->pin = pwm_to_gptimer_per[pwm->id];
-        ret = peripheral_request(pwm->pin, label);
-        if (ret)
-                goto err;
-
-        return pwm;
- err:
-        kfree(pwm);
-        return NULL;
-}
-EXPORT_SYMBOL(pwm_request);
-
-void pwm_free(struct pwm_device *pwm)
-{
-        peripheral_free(pwm->pin);
-        kfree(pwm);
-}
-EXPORT_SYMBOL(pwm_free);
-
-int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
-{
-        unsigned long period, duty;
-        unsigned long long val;
-
-        if (duty_ns < 0 || duty_ns > period_ns)
-                return -EINVAL;
-
-        val = (unsigned long long)get_sclk() * period_ns;
-        do_div(val, NSEC_PER_SEC);
-        period = val;
-
-        val = (unsigned long long)period * duty_ns;
-        do_div(val, period_ns);
-        duty = period - val;
-
-        if (duty >= period)
-                duty = period - 1;
-
-        set_gptimer_config(pwm->id, TIMER_MODE_PWM | TIMER_PERIOD_CNT);
-        set_gptimer_pwidth(pwm->id, duty);
-        set_gptimer_period(pwm->id, period);
-
-        return 0;
-}
-EXPORT_SYMBOL(pwm_config);
-
-int pwm_enable(struct pwm_device *pwm)
-{
-        enable_gptimer(pwm->id);
-        return 0;
-}
-EXPORT_SYMBOL(pwm_enable);
-
-void pwm_disable(struct pwm_device *pwm)
-{
-        disable_gptimer(pwm->id);
-}
-EXPORT_SYMBOL(pwm_disable);
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index ada8f0fc71e..fb96e607adc 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -52,7 +52,6 @@ EXPORT_SYMBOL(reserved_mem_dcache_on);
 #ifdef CONFIG_MTD_UCLINUX
 extern struct map_info uclinux_ram_map;
 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
-unsigned long _ebss;
 EXPORT_SYMBOL(memory_mtd_end);
 EXPORT_SYMBOL(memory_mtd_start);
 EXPORT_SYMBOL(mtd_size);
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index af732eb3a68..fc179ca0779 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -114,9 +114,9 @@ static struct musb_hdrc_config musb_config = {
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
+#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
         .mode           = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
+#elif defined(CONFIG_USB_MUSB_HDRC)
         .mode           = MUSB_HOST,
 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
         .mode           = MUSB_PERIPHERAL,
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index c9d9473a5ab..5ed654ae66e 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -873,7 +873,7 @@ static struct adf702x_platform_data adf7021_platform_data = {
 };
 static inline void adf702x_mac_init(void)
 {
-        random_ether_addr(adf7021_platform_data.mac_addr);
+        eth_random_addr(adf7021_platform_data.mac_addr);
 }
 #else
 static inline void adf702x_mac_init(void) {}
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 3bd75bae750..c4d07f04094 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -635,9 +635,9 @@ static struct musb_hdrc_config musb_config = {
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
+#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
         .mode           = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
+#elif defined(CONFIG_USB_MUSB_HDRC)
         .mode           = MUSB_HOST,
 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
         .mode           = MUSB_PERIPHERAL,
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 35c8ced4615..be9edb28f96 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -171,6 +171,8 @@
 #define MAX_BLACKFIN_GPIOS 160
 
 #define BFIN_GPIO_PINT 1
+#define NR_PINT_SYS_IRQS        4
+#define NR_PINTS                160
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 838978808a1..7c36777c645 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -452,18 +452,21 @@ static struct v4l2_input adv7183_inputs[] = {
                 .name = "Composite",
                 .type = V4L2_INPUT_TYPE_CAMERA,
                 .std = V4L2_STD_ALL,
+                .capabilities = V4L2_IN_CAP_STD,
         },
         {
                 .index = 1,
                 .name = "S-Video",
                 .type = V4L2_INPUT_TYPE_CAMERA,
                 .std = V4L2_STD_ALL,
+                .capabilities = V4L2_IN_CAP_STD,
         },
         {
                 .index = 2,
                 .name = "Component",
                 .type = V4L2_INPUT_TYPE_CAMERA,
                 .std = V4L2_STD_ALL,
+                .capabilities = V4L2_IN_CAP_STD,
         },
 };
 
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
index 2cb72724377..101b33ee9bb 100644
--- a/arch/blackfin/mach-bf609/Kconfig
+++ b/arch/blackfin/mach-bf609/Kconfig
@@ -51,6 +51,14 @@ config PINT5_ASSIGN
 
 endmenu
 
+config SEC_IRQ_PRIORITY_LEVELS
+        int "SEC interrupt priority levels"
+        default 7
+        range 0 7
+        help
+          Devide the total number of interrupt priority levels into sub-levels.
+          There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
+
 endmenu
 
 endif
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile
index 2a27f817454..234fe1b4bb0 100644
--- a/arch/blackfin/mach-bf609/Makefile
+++ b/arch/blackfin/mach-bf609/Makefile
@@ -2,5 +2,5 @@
 # arch/blackfin/mach-bf609/Makefile
 #
 
-obj-y := dma.o clock.o
-obj-$(CONFIG_PM) += pm.o hibernate.o
+obj-y := dma.o clock.o ints-priority.o
+obj-$(CONFIG_PM) += pm.o dpm.o
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index ac64f47217c..c2cf1ae3118 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -677,11 +677,28 @@ int bf609_nor_flash_init(struct platform_device *dev)
         return 0;
 }
 
+void bf609_nor_flash_exit(struct platform_device *dev)
+{
+        const unsigned short pins[] = {
+                P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+                P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
+                P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
+        };
+
+        peripheral_free_list(pins);
+
+        bfin_write32(SMC_GCTL, 0);
+}
+
 static struct physmap_flash_data ezkit_flash_data = {
         .width      = 2,
         .parts      = ezkit_partitions,
-        .init       = bf609_nor_flash_init,
+        .init       = bf609_nor_flash_init,
+        .exit       = bf609_nor_flash_exit,
         .nr_parts   = ARRAY_SIZE(ezkit_partitions),
+#ifdef CONFIG_ROMKERNEL
+        .probe_type = "map_rom",
+#endif
 };
 
 static struct resource ezkit_flash_resource = {
@@ -739,7 +756,7 @@ static struct bfin6xx_spi_chip spidev_chip_info = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 static struct platform_device bfin_i2s_pcm = {
         .name = "bfin-i2s-pcm-audio",
         .id = -1,
@@ -825,6 +842,12 @@ static struct adau1761_platform_data adau1761_info = {
 static const unsigned short ppi_req[] = {
         P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
         P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+        P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+        P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+#if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
+        P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
+        P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
+#endif
         P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
         0,
 };
@@ -855,7 +878,7 @@ static struct bcap_route vs6624_routes[] = {
         },
 };
 
-static const unsigned vs6624_ce_pin = GPIO_PD1;
+static const unsigned vs6624_ce_pin = GPIO_PE4;
 
 static struct bfin_capture_config bfin_capture_data = {
         .card_name = "BF609",
@@ -871,7 +894,128 @@ static struct bfin_capture_config bfin_capture_data = {
         .ppi_info = &ppi_info,
         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
                         | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
-        .blank_clocks = 8,
+        .blank_pixels = 4,
+};
+#endif
+
+#if defined(CONFIG_VIDEO_ADV7842) \
+        || defined(CONFIG_VIDEO_ADV7842_MODULE)
+#include <media/adv7842.h>
+
+static struct v4l2_input adv7842_inputs[] = {
+        {
+                .index = 0,
+                .name = "Composite",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = V4L2_STD_ALL,
+                .capabilities = V4L2_IN_CAP_STD,
+        },
+        {
+                .index = 1,
+                .name = "S-Video",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = V4L2_STD_ALL,
+                .capabilities = V4L2_IN_CAP_STD,
+        },
+        {
+                .index = 2,
+                .name = "Component",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+        },
+        {
+                .index = 3,
+                .name = "VGA",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+        },
+        {
+                .index = 4,
+                .name = "HDMI",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+        },
+};
+
+static struct bcap_route adv7842_routes[] = {
+        {
+                .input = 3,
+                .output = 0,
+                .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
+                                | EPPI_CTL_ACTIVE656),
+        },
+        {
+                .input = 4,
+                .output = 0,
+        },
+        {
+                .input = 2,
+                .output = 0,
+        },
+        {
+                .input = 1,
+                .output = 0,
+        },
+        {
+                .input = 0,
+                .output = 1,
+                .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
+                                | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
+                                | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
+        },
+};
+
+static struct adv7842_output_format adv7842_opf[] = {
+        {
+                .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
+                .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
+                .op_656_range = 1,
+                .blank_data = 1,
+                .insert_av_codes = 1,
+        },
+        {
+                .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
+                .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
+                .op_656_range = 1,
+                .blank_data = 1,
+        },
+};
+
+static struct adv7842_platform_data adv7842_data = {
+        .opf = adv7842_opf,
+        .num_opf = ARRAY_SIZE(adv7842_opf),
+        .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
+        .prim_mode = ADV7842_PRIM_MODE_SDP,
+        .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
+        .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
+        .i2c_sdp_io = 0x40,
+        .i2c_sdp = 0x41,
+        .i2c_cp = 0x42,
+        .i2c_vdp = 0x43,
+        .i2c_afe = 0x44,
+        .i2c_hdmi = 0x45,
+        .i2c_repeater = 0x46,
+        .i2c_edid = 0x47,
+        .i2c_infoframe = 0x48,
+        .i2c_cec = 0x49,
+        .i2c_avlink = 0x4a,
+        .i2c_ex = 0x26,
+};
+
+static struct bfin_capture_config bfin_capture_data = {
+        .card_name = "BF609",
+        .inputs = adv7842_inputs,
+        .num_inputs = ARRAY_SIZE(adv7842_inputs),
+        .routes = adv7842_routes,
+        .i2c_adapter_id = 0,
+        .board_info = {
+                .type = "adv7842",
+                .addr = 0x20,
+                .platform_data = (void *)&adv7842_data,
+        },
+        .ppi_info = &ppi_info,
+        .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
+                        | EPPI_CTL_ACTIVE656),
 };
 #endif
 
@@ -883,6 +1027,80 @@ static struct platform_device bfin_capture_device = {
 };
 #endif
 
+#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
+        || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
+#include <linux/videodev2.h>
+#include <media/blackfin/bfin_display.h>
+#include <media/blackfin/ppi.h>
+
+static const unsigned short ppi_req_disp[] = {
+        P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+        P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+        P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+        P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+        P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+        0,
+};
+
+static const struct ppi_info ppi_info = {
+        .type = PPI_TYPE_EPPI3,
+        .dma_ch = CH_EPPI0_CH0,
+        .irq_err = IRQ_EPPI0_STAT,
+        .base = (void __iomem *)EPPI0_STAT,
+        .pin_req = ppi_req_disp,
+};
+
+#if defined(CONFIG_VIDEO_ADV7511) \
+        || defined(CONFIG_VIDEO_ADV7511_MODULE)
+#include <media/adv7511.h>
+
+static struct v4l2_output adv7511_outputs[] = {
+        {
+                .index = 0,
+                .name = "HDMI",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS,
+        },
+};
+
+static struct disp_route adv7511_routes[] = {
+        {
+                .output = 0,
+        },
+};
+
+static struct adv7511_platform_data adv7511_data = {
+        .edid_addr = 0x7e,
+        .i2c_ex = 0x25,
+};
+
+static struct bfin_display_config bfin_display_data = {
+        .card_name = "BF609",
+        .outputs = adv7511_outputs,
+        .num_outputs = ARRAY_SIZE(adv7511_outputs),
+        .routes = adv7511_routes,
+        .i2c_adapter_id = 0,
+        .board_info = {
+                .type = "adv7511",
+                .addr = 0x39,
+                .platform_data = (void *)&adv7511_data,
+        },
+        .ppi_info = &ppi_info,
+        .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
+                        | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
+                        | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
+                        | EPPI_CTL_NON656 | EPPI_CTL_DIR),
+};
+#endif
+
+static struct platform_device bfin_display_device = {
+        .name = "bfin_display",
+        .dev = {
+                .platform_data = &bfin_display_data,
+        },
+};
+#endif
+
 #if defined(CONFIG_BFIN_CRC)
 #define BFIN_CRC_NAME "bfin-crc"
 
@@ -947,6 +1165,39 @@ static struct platform_device bfin_crc1_device = {
 };
 #endif
 
+#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
+#define BFIN_CRYPTO_CRC_NAME            "bfin-hmac-crc"
+#define BFIN_CRYPTO_CRC_POLY_DATA       0x5c5c5c5c
+
+static struct resource bfin_crypto_crc_resources[] = {
+        {
+                .start = REG_CRC0_CTL,
+                .end = REG_CRC0_REVID+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_CRC0_DCNTEXP,
+                .end = IRQ_CRC0_DCNTEXP,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_MEM_STREAM0_SRC_CRC0,
+                .end = CH_MEM_STREAM0_SRC_CRC0,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_crypto_crc_device = {
+        .name = BFIN_CRYPTO_CRC_NAME,
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
+        .resource = bfin_crypto_crc_resources,
+        .dev = {
+                .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
+        },
+};
+#endif
+
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
@@ -963,6 +1214,28 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
 
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+        {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
+        {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+        .buttons        = bfin_gpio_keys_table,
+        .nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+        .name      = "gpio-keys",
+        .dev = {
+                .platform_data = &bfin_gpio_keys_data,
+        },
+};
+#endif
+
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -981,10 +1254,10 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         {
                 .modalias               = "ad7877",
                 .platform_data          = &bfin_ad7877_ts_info,
-                .irq                    = IRQ_PB4,      /* old boards (<=Rev 1.3) use IRQ_PJ11 */
+                .irq                    = IRQ_PD9,
                 .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num                = 0,
-                .chip_select            = 2,
+                .chip_select            = 4,
         },
 #endif
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1050,7 +1323,7 @@ static struct resource bfin_spi1_resource[] = {
 
 /* SPI controller data */
 static struct bfin6xx_spi_master bf60x_spi_master_info0 = {
-        .num_chipselect = 4,
+        .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
 };
 
@@ -1065,7 +1338,7 @@ static struct platform_device bf60x_spi_master0 = {
 };
 
 static struct bfin6xx_spi_master bf60x_spi_master_info1 = {
-        .num_chipselect = 4,
+        .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
         .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
 };
 
@@ -1146,6 +1419,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
                 .platform_data = (void *)&adau1761_info
         },
 #endif
+#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
+        {
+                I2C_BOARD_INFO("ssm2602", 0x1b),
+        },
+#endif
 };
 
 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
@@ -1261,6 +1539,9 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &bfin_crc0_device,
         &bfin_crc1_device,
 #endif
+#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
+        &bfin_crypto_crc_device,
+#endif
 
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
         &bfin_device_gpiokeys,
@@ -1269,7 +1550,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
         &ezkit_flash_device,
 #endif
-#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
         &bfin_i2s_pcm,
 #endif
 #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
@@ -1284,6 +1565,11 @@ static struct platform_device *ezkit_devices[] __initdata = {
         || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
         &bfin_capture_device,
 #endif
+#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
+        || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
+        &bfin_display_device,
+#endif
+
 };
 
 static int __init ezkit_init(void)
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
index 7f8f529693a..437d56c8228 100644
--- a/arch/blackfin/mach-bf609/clock.c
+++ b/arch/blackfin/mach-bf609/clock.c
@@ -97,9 +97,10 @@ int wait_for_pll_align(void)
         while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
 
         if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
-                printk(KERN_DEBUG "fail to align clk\n");
+                printk(KERN_CRIT "fail to align clk\n");
                 return -1;
         }
+
         return 0;
 }
 
diff --git a/arch/blackfin/mach-bf609/dpm.S b/arch/blackfin/mach-bf609/dpm.S
new file mode 100644
index 00000000000..54d50c689db
--- /dev/null
+++ b/arch/blackfin/mach-bf609/dpm.S
@@ -0,0 +1,157 @@
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+#include <asm/dpmc.h>
+
+#include <asm/context.S>
+
+#define PM_STACK   (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
+
+.section .l1.text
+ENTRY(_enter_hibernate)
+        /* switch stack to L1 scratch, prepare for ddr srfr */
+        P0.H = HI(PM_STACK);
+        P0.L = LO(PM_STACK);
+        SP = P0;
+
+        call _bf609_ddr_sr;
+        call _bfin_hibernate_syscontrol;
+
+        P0.H = HI(DPM0_RESTORE4);
+        P0.L = LO(DPM0_RESTORE4);
+        P1.H = _bf609_pm_data;
+        P1.L = _bf609_pm_data;
+        [P0] = P1;
+
+        P0.H = HI(DPM0_CTL);
+        P0.L = LO(DPM0_CTL);
+        R3.H = HI(0x00000010);
+        R3.L = LO(0x00000010);
+
+        bfin_init_pm_bench_cycles;
+
+        [P0] = R3;
+
+        SSYNC;
+ENDPROC(_enter_hibernate)
+
+/* DPM wake up interrupt won't wake up core on bf60x if its core IMASK
+ * is disabled. This behavior differ from bf5xx serial processor.
+ */
+ENTRY(_dummy_deepsleep)
+        [--sp] = SYSCFG;
+        [--sp] = (R7:0,P5:0);
+        cli r0;
+
+        /* get wake up interrupt ID */
+        P0.l = LO(SEC_SCI_BASE + SEC_CSID);
+        P0.h = HI(SEC_SCI_BASE + SEC_CSID);
+        R0 = [P0];
+
+        /* ACK wake up interrupt in SEC */
+        P1.l = LO(SEC_END);
+        P1.h = HI(SEC_END);
+
+        [P1] = R0;
+        SSYNC;
+
+        /* restore EVT 11 entry */
+        p0.h = hi(EVT11);
+        p0.l = lo(EVT11);
+        p1.h = _evt_evt11;
+        p1.l = _evt_evt11;
+
+        [p0] = p1;
+        SSYNC;
+
+        (R7:0,P5:0) = [sp++];
+        SYSCFG = [sp++];
+        RTI;
+ENDPROC(_dummy_deepsleep)
+
+ENTRY(_enter_deepsleep)
+        LINK 0xC;
+        [--sp] = (R7:0,P5:0);
+
+        /* Change EVT 11 entry to dummy handler for wake up event */
+        p0.h = hi(EVT11);
+        p0.l = lo(EVT11);
+        p1.h = _dummy_deepsleep;
+        p1.l = _dummy_deepsleep;
+
+        [p0] = p1;
+
+        P0.H = HI(PM_STACK);
+        P0.L = LO(PM_STACK);
+
+        EX_SCRATCH_REG = SP;
+        SP = P0;
+
+        SSYNC;
+
+        /* should put ddr to self refresh mode before sleep */
+        call _bf609_ddr_sr;
+
+        /* Set DPM controller to deep sleep mode */
+        P0.H = HI(DPM0_CTL);
+        P0.L = LO(DPM0_CTL);
+        R3.H = HI(0x00000008);
+        R3.L = LO(0x00000008);
+        [P0] = R3;
+        CSYNC;
+
+        /* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */
+        r0.l = 0x800;
+        r0.h = 0;
+        sti r0;
+        SSYNC;
+
+        bfin_init_pm_bench_cycles;
+
+        /* Fall into deep sleep in idle*/
+        idle;
+        SSYNC;
+
+        /* Restore PLL after wake up from deep sleep */
+        call _bf609_resume_ccbuf;
+
+        /* turn ddr out of self refresh mode */
+        call _bf609_ddr_sr_exit;
+
+        SP = EX_SCRATCH_REG;
+
+        (R7:0,P5:0) = [SP++];
+        UNLINK;
+        RTS;
+ENDPROC(_enter_deepsleep)
+
+.section .text
+ENTRY(_bf609_hibernate)
+        bfin_cpu_reg_save;
+        bfin_core_mmr_save;
+
+        P0.H = _bf609_pm_data;
+        P0.L = _bf609_pm_data;
+        R1.H = 0xDEAD;
+        R1.L = 0xBEEF;
+        R2.H = .Lpm_resume_here;
+        R2.L = .Lpm_resume_here;
+        [P0++] = R1;
+        [P0++] = R2;
+        [P0++] = SP;
+
+        P1.H = _enter_hibernate;
+        P1.L = _enter_hibernate;
+
+        call (P1);
+.Lpm_resume_here:
+
+        bfin_core_mmr_restore;
+        bfin_cpu_reg_restore;
+
+        [--sp] = RETI;  /* Clear Global Interrupt Disable */
+        SP += 4;
+
+        RTS;
+
+ENDPROC(_bf609_hibernate)
+
diff --git a/arch/blackfin/mach-bf609/hibernate.S b/arch/blackfin/mach-bf609/hibernate.S
deleted file mode 100644
index d37a532519c..00000000000
--- a/arch/blackfin/mach-bf609/hibernate.S
+++ /dev/null
@@ -1,65 +0,0 @@
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/dpmc.h>
-
-#define PM_STACK   (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-.section .l1.text
-ENTRY(_enter_hibernate)
-        /* switch stack to L1 scratch, prepare for ddr srfr */
-        P0.H = HI(PM_STACK);
-        P0.L = LO(PM_STACK);
-        SP = P0;
-
-        call _bf609_ddr_sr;
-        call _bfin_hibernate_syscontrol;
-
-        P0.H = HI(DPM0_RESTORE4);
-        P0.L = LO(DPM0_RESTORE4);
-        P1.H = _bf609_pm_data;
-        P1.L = _bf609_pm_data;
-        [P0] = P1;
-
-        P0.H = HI(DPM0_CTL);
-        P0.L = LO(DPM0_CTL);
-        R3.H = HI(0x00000010);
-        R3.L = LO(0x00000010);
-
-        bfin_init_pm_bench_cycles;
-
-        [P0] = R3;
-
-        SSYNC;
-ENDPROC(_enter_hibernate_mode)
-
-.section .text
-ENTRY(_bf609_hibernate)
-        bfin_cpu_reg_save;
-        bfin_core_mmr_save;
-
-        P0.H = _bf609_pm_data;
-        P0.L = _bf609_pm_data;
-        R1.H = 0xDEAD;
-        R1.L = 0xBEEF;
-        R2.H = .Lpm_resume_here;
-        R2.L = .Lpm_resume_here;
-        [P0++] = R1;
-        [P0++] = R2;
-        [P0++] = SP;
-
-        P1.H = _enter_hibernate;
-        P1.L = _enter_hibernate;
-
-        call (P1);
-.Lpm_resume_here:
-
-        bfin_core_mmr_restore;
-        bfin_cpu_reg_restore;
-
-        [--sp] = RETI;  /* Clear Global Interrupt Disable */
-        SP += 4;
-
-        RTS;
-
-ENDPROC(_bf609_hibernate)
-
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
index bdd39aefb56..7a07374308a 100644
--- a/arch/blackfin/mach-bf609/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h
@@ -5,126 +5,99 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2011 Analog Devices Inc.
+ * Copyright 2004-2012 Analog Devices Inc.
  * Licensed under the Clear BSD license.
  */
 
 /* This file should be up to date with:
+ *  - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
  */
 
 #if __SILICON_REVISION__ < 0
-# error will not work on BF506 silicon version
+# error will not work on BF609 silicon version
 #endif
 
 #ifndef _MACH_ANOMALY_H_
 #define _MACH_ANOMALY_H_
 
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
+/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
+#define ANOMALY_16000003 (1)
+/* The EPPI Data Enable (DEN) Signal is Not Functional */
+#define ANOMALY_16000004 (1)
+/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
+#define ANOMALY_16000005 (1)
+/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
+#define ANOMALY_16000006 (1)
+/* DDR2 Memory Reads May Fail Intermittently */
+#define ANOMALY_16000007 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
+#define ANOMALY_16000008 (1)
+/* TestSET Instruction Cannot Be Interrupted */
+#define ANOMALY_16000009 (1)
 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
+#define ANOMALY_16000010 (1)
 /* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
-#define ANOMALY_05000491 (1)
-/* Tempopary anomaly ID for data loss in MMR read operation if interrupted */
-#define ANOMALY_05001001 (__SILICON_REVISION__ < 1)
+#define ANOMALY_16000011 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_16000012 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_16000013 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_16000014 (1)
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+#define ANOMALY_16000015 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_16000017 (1)
+/* RSI Boot Cleanup Routine Does Not Clear Registers */
+#define ANOMALY_16000018 (1)
+/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
+#define ANOMALY_16000019 (1)
+/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
+#define ANOMALY_16000020 (1)
+/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
+#define ANOMALY_16000021 (1)
+/* Boot Code Fails to Enable Parity Fault Detection */
+#define ANOMALY_16000022 (1)
+/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
+#define ANOMALY_16000027 (1)
+/* Interrupted Core Reads of MMRs May Cause Data Loss */
+#define ANOMALY_16000030 (1)
 
 /* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
 #define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
 #define ANOMALY_05000189 (0)
 #define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
 #define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
 #define ANOMALY_05000230 (0)
 #define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
 #define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
 #define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
 #define ANOMALY_05000273 (0)
 #define ANOMALY_05000274 (0)
 #define ANOMALY_05000278 (0)
 #define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
 #define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
 #define ANOMALY_05000311 (0)
 #define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
 #define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
 #define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
 #define ANOMALY_05000380 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000440 (0)
 #define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
 #define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
+#define ANOMALY_05000456 (0)
 #define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
+#define ANOMALY_05000481 (1)
+
+/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
+#define ANOMALY_05000491 ANOMALY_16000008
+#define ANOMALY_05000477 ANOMALY_16000009
+#define ANOMALY_05000443 ANOMALY_16000010
+#define ANOMALY_05000461 ANOMALY_16000011
+#define ANOMALY_05000426 ANOMALY_16000012
+#define ANOMALY_05000310 ANOMALY_16000013
+#define ANOMALY_05000245 ANOMALY_16000014
+#define ANOMALY_05000074 ANOMALY_16000015
+#define ANOMALY_05000416 ANOMALY_16000017
+
 
 #endif
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
index 6aac38544cc..f1a6afae1a7 100644
--- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
+++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
@@ -2665,7 +2665,6 @@
 #define DEVSZ_1G                0x400         /* DMC External Bank Size = 1Gbit */
 #define DEVSZ_2G                0x500         /* DMC External Bank Size = 2Gbit */
 
-
 /* =========================
         L2CTL Registers
    ========================= */
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
index 127586b1e04..c32c8cc8db2 100644
--- a/arch/blackfin/mach-bf609/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf609/include/mach/gpio.h
@@ -123,6 +123,8 @@
 
 
 #define BFIN_GPIO_PINT 1
+#define NR_PINT_SYS_IRQS        6
+#define NR_PINTS                112
 
 
 #ifndef __ASSEMBLY__
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
index 0004552433b..23e74cdeeee 100644
--- a/arch/blackfin/mach-bf609/include/mach/irq.h
+++ b/arch/blackfin/mach-bf609/include/mach/irq.h
@@ -293,9 +293,13 @@
 
 #define NR_MACH_IRQS            (IRQ_PG15 + 1)
 
+#define SEC_SCTL_PRIO_OFFSET    8
+
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
 
+extern u8 sec_int_priority[];
+
 /*
  * bfin pint registers layout
  */
diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h
index 036d9bdc889..3ca0fb96563 100644
--- a/arch/blackfin/mach-bf609/include/mach/pm.h
+++ b/arch/blackfin/mach-bf609/include/mach/pm.h
@@ -11,11 +11,14 @@
 
 #include <linux/suspend.h>
 
-int bfin609_pm_enter(suspend_state_t state);
-int bf609_pm_prepare(void);
-void bf609_pm_finish(void);
+extern int bfin609_pm_enter(suspend_state_t state);
+extern int bf609_pm_prepare(void);
+extern void bf609_pm_finish(void);
 
 void bf609_hibernate(void);
 void bfin_sec_raise_irq(unsigned int sid);
 void coreb_enable(void);
+
+int bf609_nor_flash_init(void);
+void bf609_nor_flash_exit(void);
 #endif
diff --git a/arch/blackfin/mach-bf609/ints-priority.c b/arch/blackfin/mach-bf609/ints-priority.c
new file mode 100644
index 00000000000..f68abb9aa79
--- /dev/null
+++ b/arch/blackfin/mach-bf609/ints-priority.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ * Set up the interrupt priorities
+ */
+
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <asm/blackfin.h>
+
+u8 sec_int_priority[] = {
+        255,    /* IRQ_SEC_ERR */
+        255,    /* IRQ_CGU_EVT */
+        254,    /* IRQ_WATCH0 */
+        254,    /* IRQ_WATCH1 */
+        253,    /* IRQ_L2CTL0_ECC_ERR */
+        253,    /* IRQ_L2CTL0_ECC_WARN */
+        253,    /* IRQ_C0_DBL_FAULT */
+        253,    /* IRQ_C1_DBL_FAULT */
+        252,    /* IRQ_C0_HW_ERR */
+        252,    /* IRQ_C1_HW_ERR */
+        255,    /* IRQ_C0_NMI_L1_PARITY_ERR */
+        255,    /* IRQ_C1_NMI_L1_PARITY_ERR */
+
+        50,     /* IRQ_TIMER0 */
+        50,     /* IRQ_TIMER1 */
+        50,     /* IRQ_TIMER2 */
+        50,     /* IRQ_TIMER3 */
+        50,     /* IRQ_TIMER4 */
+        50,     /* IRQ_TIMER5 */
+        50,     /* IRQ_TIMER6 */
+        50,     /* IRQ_TIMER7 */
+        50,     /* IRQ_TIMER_STAT */
+        0,      /* IRQ_PINT0 */
+        0,      /* IRQ_PINT1 */
+        0,      /* IRQ_PINT2 */
+        0,      /* IRQ_PINT3 */
+        0,      /* IRQ_PINT4 */
+        0,      /* IRQ_PINT5 */
+        0,      /* IRQ_CNT */
+        50,     /* RQ_PWM0_TRIP */
+        50,     /* IRQ_PWM0_SYNC */
+        50,     /* IRQ_PWM1_TRIP */
+        50,     /* IRQ_PWM1_SYNC */
+        0,      /* IRQ_TWI0 */
+        0,      /* IRQ_TWI1 */
+        10,     /* IRQ_SOFT0 */
+        10,     /* IRQ_SOFT1 */
+        10,     /* IRQ_SOFT2 */
+        10,     /* IRQ_SOFT3 */
+        0,      /* IRQ_ACM_EVT_MISS */
+        0,      /* IRQ_ACM_EVT_COMPLETE */
+        0,      /* IRQ_CAN0_RX */
+        0,      /* IRQ_CAN0_TX */
+        0,      /* IRQ_CAN0_STAT */
+        100,    /* IRQ_SPORT0_TX */
+        100,    /* IRQ_SPORT0_TX_STAT */
+        100,    /* IRQ_SPORT0_RX */
+        100,    /* IRQ_SPORT0_RX_STAT */
+        100,    /* IRQ_SPORT1_TX */
+        100,    /* IRQ_SPORT1_TX_STAT */
+        100,    /* IRQ_SPORT1_RX */
+        100,    /* IRQ_SPORT1_RX_STAT */
+        100,    /* IRQ_SPORT2_TX */
+        100,    /* IRQ_SPORT2_TX_STAT */
+        100,    /* IRQ_SPORT2_RX */
+        100,    /* IRQ_SPORT2_RX_STAT */
+        0,      /* IRQ_SPI0_TX */
+        0,      /* IRQ_SPI0_RX */
+        0,      /* IRQ_SPI0_STAT */
+        0,      /* IRQ_SPI1_TX */
+        0,      /* IRQ_SPI1_RX */
+        0,      /* IRQ_SPI1_STAT */
+        0,      /* IRQ_RSI */
+        0,      /* IRQ_RSI_INT0 */
+        0,      /* IRQ_RSI_INT1 */
+        0,      /* DMA11 Data (SDU) */
+        0,      /* DMA12 Data (Reserved) */
+        0,      /* Reserved */
+        0,      /* Reserved */
+        30,     /* IRQ_EMAC0_STAT */
+        0,      /* EMAC0 Power (Reserved) */
+        30,     /* IRQ_EMAC1_STAT */
+        0,      /* EMAC1 Power (Reserved) */
+        0,      /* IRQ_LP0 */
+        0,      /* IRQ_LP0_STAT */
+        0,      /* IRQ_LP1 */
+        0,      /* IRQ_LP1_STAT */
+        0,      /* IRQ_LP2 */
+        0,      /* IRQ_LP2_STAT */
+        0,      /* IRQ_LP3 */
+        0,      /* IRQ_LP3_STAT */
+        0,      /* IRQ_UART0_TX */
+        0,      /* IRQ_UART0_RX */
+        0,      /* IRQ_UART0_STAT */
+        0,      /* IRQ_UART1_TX */
+        0,      /* IRQ_UART1_RX */
+        0,      /* IRQ_UART1_STAT */
+        0,      /* IRQ_MDMA0_SRC_CRC0 */
+        0,      /* IRQ_MDMA0_DEST_CRC0 */
+        0,      /* IRQ_CRC0_DCNTEXP */
+        0,      /* IRQ_CRC0_ERR */
+        0,      /* IRQ_MDMA1_SRC_CRC1 */
+        0,      /* IRQ_MDMA1_DEST_CRC1 */
+        0,      /* IRQ_CRC1_DCNTEXP */
+        0,      /* IRQ_CRC1_ERR */
+        0,      /* IRQ_MDMA2_SRC */
+        0,      /* IRQ_MDMA2_DEST */
+        0,      /* IRQ_MDMA3_SRC */
+        0,      /* IRQ_MDMA3_DEST */
+        120,    /* IRQ_EPPI0_CH0 */
+        120,    /* IRQ_EPPI0_CH1 */
+        120,    /* IRQ_EPPI0_STAT */
+        120,    /* IRQ_EPPI2_CH0 */
+        120,    /* IRQ_EPPI2_CH1 */
+        120,    /* IRQ_EPPI2_STAT */
+        120,    /* IRQ_EPPI1_CH0 */
+        120,    /* IRQ_EPPI1_CH1 */
+        120,    /* IRQ_EPPI1_STAT */
+        120,    /* IRQ_PIXC_CH0 */
+        120,    /* IRQ_PIXC_CH1 */
+        120,    /* IRQ_PIXC_CH2 */
+        120,    /* IRQ_PIXC_STAT */
+        120,    /* IRQ_PVP_CPDOB */
+        120,    /* IRQ_PVP_CPDOC */
+        120,    /* IRQ_PVP_CPSTAT */
+        120,    /* IRQ_PVP_CPCI */
+        120,    /* IRQ_PVP_STAT0 */
+        120,    /* IRQ_PVP_MPDO */
+        120,    /* IRQ_PVP_MPDI */
+        120,    /* IRQ_PVP_MPSTAT */
+        120,    /* IRQ_PVP_MPCI */
+        120,    /* IRQ_PVP_CPDOA */
+        120,    /* IRQ_PVP_STAT1 */
+        0,      /* IRQ_USB_STAT */
+        0,      /* IRQ_USB_DMA */
+        0,      /* IRQ_TRU_INT0 */
+        0,      /* IRQ_TRU_INT1 */
+        0,      /* IRQ_TRU_INT2 */
+        0,      /* IRQ_TRU_INT3 */
+        0,      /* IRQ_DMAC0_ERROR */
+        0,      /* IRQ_CGU0_ERROR */
+        0,      /* Reserved */
+        0,      /* IRQ_DPM */
+        0,      /* Reserved */
+        0,      /* IRQ_SWU0 */
+        0,      /* IRQ_SWU1 */
+        0,      /* IRQ_SWU2 */
+        0,      /* IRQ_SWU3 */
+        0,      /* IRQ_SWU4 */
+        0,      /* IRQ_SWU4 */
+        0,      /* IRQ_SWU6 */
+};
+
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c
index b76966eb16a..dacafc163f7 100644
--- a/arch/blackfin/mach-bf609/pm.c
+++ b/arch/blackfin/mach-bf609/pm.c
@@ -11,13 +11,14 @@
 #include <linux/interrupt.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
-
 #include <linux/delay.h>
+#include <linux/syscore_ops.h>
 
 #include <asm/dpmc.h>
 #include <asm/pm.h>
 #include <mach/pm.h>
 #include <asm/blackfin.h>
+#include <asm/mem_init.h>
 
 /***********************************************************/
 /*                                                         */
@@ -132,60 +133,30 @@ void bfin_cpu_suspend(void)
 }
 
 __attribute__((l1_text))
-void bfin_deepsleep(unsigned long mask)
+void bf609_ddr_sr(void)
 {
-        uint32_t dpm0_ctl;
-
-        bfin_write32(DPM0_WAKE_EN, 0x10);
-        bfin_write32(DPM0_WAKE_POL, 0x10);
-        dpm0_ctl = 0x00000008;
-        bfin_write32(DPM0_CTL, dpm0_ctl);
-        SSYNC();
-        __asm__ __volatile__( \
-                        ".align 8;" \
-                        "idle;" \
-                        : : \
-                        );
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
-        __asm__ __volatile__(
-                "R0 = 0;"
-                "CYCLES = R0;"
-                "CYCLES2 = R0;"
-                "R0 = SYSCFG;"
-                "BITSET(R0, 1);"
-                "SYSCFG = R0;"
-                : : : "R0"
-        );
-#endif
-
+        dmc_enter_self_refresh();
 }
 
 __attribute__((l1_text))
-void bf609_ddr_sr(void)
+void bf609_ddr_sr_exit(void)
 {
-        uint32_t reg;
-
-        reg = bfin_read_DMC0_CTL();
-        reg |= 0x8;
-        bfin_write_DMC0_CTL(reg);
+        dmc_exit_self_refresh();
 
-        while (!(bfin_read_DMC0_STAT() & 0x8))
+        /* After wake up from deep sleep and exit DDR from self refress mode,
+         * should wait till CGU PLL is locked.
+         */
+        while (bfin_read32(CGU0_STAT) & CLKSALGN)
                 continue;
 }
 
 __attribute__((l1_text))
-void bf609_ddr_sr_exit(void)
+void bf609_resume_ccbuf(void)
 {
-        uint32_t reg;
-        while (!(bfin_read_DMC0_STAT() & 0x1))
-                continue;
+        bfin_write32(DPM0_CCBF_EN, 3);
+        bfin_write32(DPM0_CTL, 2);
 
-        reg = bfin_read_DMC0_CTL();
-        reg &= ~0x8;
-        bfin_write_DMC0_CTL(reg);
-
-        while ((bfin_read_DMC0_STAT() & 0x8))
-                continue;
+        while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
 }
 
 __attribute__((l1_text))
@@ -203,20 +174,25 @@ void bfin_hibernate_syscontrol(void)
         bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
 }
 
-#ifndef CONFIG_BF60x
-# define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
-#else
-# define SIC_SYSIRQ(irq)        ((irq) - IVG15)
-#endif
-void bfin_hibernate(unsigned long mask)
+#define IRQ_SID(irq)   ((irq) - IVG15)
+asmlinkage void enter_deepsleep(void);
+
+__attribute__((l1_text))
+void bfin_deepsleep(unsigned long mask, unsigned long pol_mask)
 {
-        bfin_write32(DPM0_WAKE_EN, 0x10);
-        bfin_write32(DPM0_WAKE_POL, 0x10);
+        bfin_write32(DPM0_WAKE_EN, mask);
+        bfin_write32(DPM0_WAKE_POL, pol_mask);
+        SSYNC();
+        enter_deepsleep();
+}
+
+void bfin_hibernate(unsigned long mask, unsigned long pol_mask)
+{
+        bfin_write32(DPM0_WAKE_EN, mask);
+        bfin_write32(DPM0_WAKE_POL, pol_mask);
         bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
         bfin_write32(DPM0_HIB_DIS, 0xFFFF);
 
-        printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR));
-
         bf609_hibernate();
 }
 
@@ -290,10 +266,11 @@ void bf609_cpu_pm_enter(suspend_state_t state)
                 printk(KERN_DEBUG "Unable to get irq wake\n");
 
         if (state == PM_SUSPEND_STANDBY)
-                bfin_deepsleep(wakeup);
+                bfin_deepsleep(wakeup, wakeup_pol);
         else {
-                bfin_hibernate(wakeup);
+                bfin_hibernate(wakeup, wakeup_pol);
         }
+
 }
 
 int bf609_cpu_pm_prepare(void)
@@ -312,20 +289,36 @@ static struct bfin_cpu_pm_fns bf609_cpu_pm = {
         .finish         = bf609_cpu_pm_finish,
 };
 
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static int smc_pm_syscore_suspend(void)
+{
+        bf609_nor_flash_exit();
+        return 0;
+}
+
+static void smc_pm_syscore_resume(void)
+{
+        bf609_nor_flash_init();
+}
+
+static struct syscore_ops smc_pm_syscore_ops = {
+        .suspend        = smc_pm_syscore_suspend,
+        .resume         = smc_pm_syscore_resume,
+};
+#endif
+
 static irqreturn_t test_isr(int irq, void *dev_id)
 {
         printk(KERN_DEBUG "gpio irq %d\n", irq);
+        if (irq == 231)
+                bfin_sec_raise_irq(IRQ_SID(IRQ_SOFT1));
         return IRQ_HANDLED;
 }
 
 static irqreturn_t dpm0_isr(int irq, void *dev_id)
 {
-        uint32_t wake_stat;
-
-        wake_stat = bfin_read32(DPM0_WAKE_STAT);
-        printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat);
-
-        bfin_write32(DPM0_WAKE_STAT, wake_stat);
+        bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
+        bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
         return IRQ_HANDLED;
 }
 
@@ -334,7 +327,11 @@ static int __init bf609_init_pm(void)
         int irq;
         int error;
 
-#if CONFIG_PM_BFIN_WAKE_PE12
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+        register_syscore_ops(&smc_pm_syscore_ops);
+#endif
+
+#ifdef CONFIG_PM_BFIN_WAKE_PE12
         irq = gpio_to_irq(GPIO_PE12);
         if (irq < 0) {
                 error = irq;
@@ -342,16 +339,19 @@ static int __init bf609_init_pm(void)
                                 GPIO_PE12, error);
         }
 
-        error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL);
+        error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND
+                                | IRQF_FORCE_RESUME, "gpiope12", NULL);
         if(error < 0)
                 printk(KERN_DEBUG "Unable to get irq\n");
 #endif
 
-        error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL);
+        error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND |
+                                IRQF_FORCE_RESUME, "cgu0 event", NULL);
         if(error < 0)
                 printk(KERN_DEBUG "Unable to get irq\n");
 
-        error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL);
+        error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND |
+                                IRQF_FORCE_RESUME, "dpm0 event", NULL);
         if (error < 0)
                 printk(KERN_DEBUG "Unable to get irq\n");
 
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index 7ad2407d157..2308ce52f84 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -16,23 +16,14 @@
 #include <asm/dpmc.h>
 
 #ifdef CONFIG_BF60x
-#define CSEL_P                  0
-#define S0SEL_P                 5
-#define SYSSEL_P                8
-#define S1SEL_P                 13
-#define DSEL_P                  16
-#define OSEL_P                  22
-#define ALGN_P                  29
-#define UPDT_P                  30
-#define LOCK_P                  31
 
 #define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
 #define CGU_DIV_VAL \
-        ((CONFIG_CCLK_DIV   << CSEL_P)   | \
-        (CONFIG_SCLK_DIV << SYSSEL_P)   | \
-        (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
-        (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
-        (CONFIG_DCLK_DIV   << DSEL_P))
+        ((CONFIG_CCLK_DIV   << CSEL_OFFSET)   | \
+        (CONFIG_SCLK_DIV << SYSSEL_OFFSET)   | \
+        (CONFIG_SCLK0_DIV  << S0SEL_OFFSET)  | \
+        (CONFIG_SCLK1_DIV  << S1SEL_OFFSET)  | \
+        (CONFIG_DCLK_DIV   << DSEL_OFFSET))
 
 #define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
 #if ((CONFIG_BFIN_DCLK != 125) && \
@@ -41,89 +32,7 @@
         (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
 #error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
 #endif
-struct ddr_config {
-        u32 ddr_clk;
-        u32 dmc_ddrctl;
-        u32 dmc_ddrcfg;
-        u32 dmc_ddrtr0;
-        u32 dmc_ddrtr1;
-        u32 dmc_ddrtr2;
-        u32 dmc_ddrmr;
-        u32 dmc_ddrmr1;
-};
 
-struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
-        [0] = {
-                .ddr_clk    = 125,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20705212,
-                .dmc_ddrtr1 = 0x201003CF,
-                .dmc_ddrtr2 = 0x00320107,
-                .dmc_ddrmr  = 0x00000422,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [1] = {
-                .ddr_clk    = 133,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20806313,
-                .dmc_ddrtr1 = 0x2013040D,
-                .dmc_ddrtr2 = 0x00320108,
-                .dmc_ddrmr  = 0x00000632,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [2] = {
-                .ddr_clk    = 150,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20A07323,
-                .dmc_ddrtr1 = 0x20160492,
-                .dmc_ddrtr2 = 0x00320209,
-                .dmc_ddrmr  = 0x00000632,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [3] = {
-                .ddr_clk    = 166,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20A07323,
-                .dmc_ddrtr1 = 0x2016050E,
-                .dmc_ddrtr2 = 0x00320209,
-                .dmc_ddrmr  = 0x00000632,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [4] = {
-                .ddr_clk    = 200,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20a07323,
-                .dmc_ddrtr1 = 0x2016050f,
-                .dmc_ddrtr2 = 0x00320509,
-                .dmc_ddrmr  = 0x00000632,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [5] = {
-                .ddr_clk    = 225,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20E0A424,
-                .dmc_ddrtr1 = 0x302006DB,
-                .dmc_ddrtr2 = 0x0032020D,
-                .dmc_ddrmr  = 0x00000842,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [6] = {
-                .ddr_clk    = 250,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20E0A424,
-                .dmc_ddrtr1 = 0x3020079E,
-                .dmc_ddrtr2 = 0x0032020D,
-                .dmc_ddrmr  = 0x00000842,
-                .dmc_ddrmr1 = 0x4,
-        },
-};
 #else
 #define SDGCTL_WIDTH (1 << 31)  /* SDRAM external data path width */
 #define PLL_CTL_VAL \
@@ -144,43 +53,9 @@ void init_clocks(void)
          * in the middle of reprogramming things, and that'll screw us up.
          * For example, any automatic DMAs left by U-Boot for splash screens.
          */
-
 #ifdef CONFIG_BF60x
-        int i, dlldatacycle, dll_ctl;
-        bfin_write32(CGU0_DIV, CGU_DIV_VAL);
-        bfin_write32(CGU0_CTL, CGU_CTL_VAL);
-        while ((bfin_read32(CGU0_STAT) & 0x8) || !(bfin_read32(CGU0_STAT) & 0x4))
-                continue;
-
-        bfin_write32(CGU0_DIV, CGU_DIV_VAL | (1 << UPDT_P));
-        while (bfin_read32(CGU0_STAT) & (1 << 3))
-                continue;
-
-        for (i = 0; i < 7; i++) {
-                if (ddr_config_table[i].ddr_clk == CONFIG_BFIN_DCLK) {
-                        bfin_write_DDR0_CFG(ddr_config_table[i].dmc_ddrcfg);
-                        bfin_write_DDR0_TR0(ddr_config_table[i].dmc_ddrtr0);
-                        bfin_write_DDR0_TR1(ddr_config_table[i].dmc_ddrtr1);
-                        bfin_write_DDR0_TR2(ddr_config_table[i].dmc_ddrtr2);
-                        bfin_write_DDR0_MR(ddr_config_table[i].dmc_ddrmr);
-                        bfin_write_DDR0_EMR1(ddr_config_table[i].dmc_ddrmr1);
-                        bfin_write_DDR0_CTL(ddr_config_table[i].dmc_ddrctl);
-                        break;
-                }
-        }
-
-        do_sync();
-        while (!(bfin_read_DDR0_STAT() & 0x4))
-                continue;
-
-        dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20;
-        dll_ctl = bfin_read_DDR0_DLLCTL();
-        dll_ctl &= 0x0ff;
-        bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8));
-
-        do_sync();
-        while (!(bfin_read_DDR0_STAT() & 0x2000))
-                continue;
+        init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
+        init_dmc(CONFIG_BFIN_DCLK);
 #else
         size_t i;
         for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 6e87dc13f6b..c854a27cbea 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -64,7 +64,8 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
 
         /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
 #if ANOMALY_05000273 || ANOMALY_05000274 || \
-        (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
+        (!(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) \
+        && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
         min_cclk = sclk * 2;
 #else
         min_cclk = sclk;
@@ -173,7 +174,7 @@ static int bfin_target(struct cpufreq_policy *poli,
 #else
                         ret = cpu_set_cclk(cpu, freqs.new * 1000);
                         if (ret != 0) {
-                                pr_debug("cpufreq set freq failed %d\n", ret);
+                                WARN_ONCE(ret, "cpufreq set freq failed %d\n", ret);
                                 break;
                         }
 #endif
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 04c2fbe41a7..1c3d2c5bb0b 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -25,13 +25,6 @@
 
 #include <asm/context.S>
 
-#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
-# define EX_SCRATCH_REG RETN
-#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
-# define EX_SCRATCH_REG RETE
-#else
-# define EX_SCRATCH_REG CYCLES
-#endif
 
 #ifdef CONFIG_EXCPT_IRQ_SYSC_L1
 .section .l1.text
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 2729cba715b..7ca09ec2ca5 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -26,8 +26,9 @@
 #include <asm/gpio.h>
 #include <asm/irq_handler.h>
 #include <asm/dpmc.h>
+#include <asm/traps.h>
 
-#ifndef CONFIG_BF60x
+#ifndef SEC_GCTL
 # define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
 #else
 # define SIC_SYSIRQ(irq)        ((irq) - IVG15)
@@ -56,7 +57,7 @@ unsigned long bfin_sic_iwr[3];	/* Up to 3 SIC_IWRx registers */
 unsigned vr_wakeup;
 #endif
 
-#ifndef CONFIG_BF60x
+#ifndef SEC_GCTL
 static struct ivgx {
         /* irq number for request_irq, available in mach-bf5xx/irq.h */
         unsigned int irqno;
@@ -143,7 +144,7 @@ static void bfin_core_unmask_irq(struct irq_data *d)
 void bfin_internal_mask_irq(unsigned int irq)
 {
         unsigned long flags = hard_local_irq_save();
-#ifndef CONFIG_BF60x
+#ifndef SEC_GCTL
 #ifdef SIC_IMASK0
         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
@@ -175,7 +176,7 @@ void bfin_internal_unmask_irq(unsigned int irq)
 {
         unsigned long flags = hard_local_irq_save();
 
-#ifndef CONFIG_BF60x
+#ifndef SEC_GCTL
 #ifdef SIC_IMASK0
         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
@@ -199,7 +200,7 @@ void bfin_internal_unmask_irq(unsigned int irq)
         hard_local_irq_restore(flags);
 }
 
-#ifdef CONFIG_BF60x
+#ifdef SEC_GCTL
 static void bfin_sec_preflow_handler(struct irq_data *d)
 {
         unsigned long flags = hard_local_irq_save();
@@ -310,7 +311,24 @@ static void bfin_sec_disable(struct irq_data *d)
         hard_local_irq_restore(flags);
 }
 
-static void bfin_sec_raise_irq(unsigned int sid)
+static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl;
+        int i;
+
+        bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
+
+        for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
+                reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
+                reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
+                bfin_write_SEC_SCTL(i, reg_sctl);
+        }
+
+        hard_local_irq_restore(flags);
+}
+
+void bfin_sec_raise_irq(unsigned int sid)
 {
         unsigned long flags = hard_local_irq_save();
 
@@ -396,24 +414,34 @@ void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
         raw_spin_unlock(&desc->lock);
 }
 
-static int sec_suspend(void)
+void handle_core_fault(unsigned int irq, struct irq_desc *desc)
 {
-        return 0;
-}
+        struct pt_regs *fp = get_irq_regs();
 
-static void sec_resume(void)
-{
-        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
-        udelay(100);
-        bfin_write_SEC_GCTL(SEC_GCTL_EN);
-        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-}
+        raw_spin_lock(&desc->lock);
 
-static struct syscore_ops sec_pm_syscore_ops = {
-        .suspend = sec_suspend,
-        .resume = sec_resume,
-};
+        switch (irq) {
+        case IRQ_C0_DBL_FAULT:
+                double_fault_c(fp);
+                break;
+        case IRQ_C0_HW_ERR:
+                dump_bfin_process(fp);
+                dump_bfin_mem(fp);
+                show_regs(fp);
+                printk(KERN_NOTICE "Kernel Stack\n");
+                show_stack(current, NULL);
+                print_modules();
+                panic("Kernel core hardware error");
+                break;
+        case IRQ_C0_NMI_L1_PARITY_ERR:
+                panic("NMI occurs unexpectedly");
+                break;
+        default:
+                panic("Core 1 fault occurs unexpectedly");
+        }
 
+        raw_spin_unlock(&desc->lock);
+}
 #endif
 
 #ifdef CONFIG_SMP
@@ -437,7 +465,7 @@ static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 }
 #endif
 
-#if defined(CONFIG_PM) && !defined(CONFIG_BF60x)
+#if defined(CONFIG_PM) && !defined(SEC_GCTL)
 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 {
         u32 bank, bit, wakeup = 0;
@@ -496,7 +524,10 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
         return bfin_internal_set_wake(d->irq, state);
 }
 #else
-# define bfin_internal_set_wake(irq, state)
+inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
+{
+        return 0;
+}
 # define bfin_internal_set_wake_chip NULL
 #endif
 
@@ -518,7 +549,7 @@ static struct irq_chip bfin_internal_irqchip = {
         .irq_set_wake = bfin_internal_set_wake_chip,
 };
 
-#ifdef CONFIG_BF60x
+#ifdef SEC_GCTL
 static struct irq_chip bfin_sec_irqchip = {
         .name = "SEC",
         .irq_mask_ack = bfin_sec_mask_ack_irq,
@@ -868,14 +899,6 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
 
 #else
 
-# ifndef CONFIG_BF60x
-#define NR_PINT_SYS_IRQS        4
-#define NR_PINTS                160
-# else
-#define NR_PINT_SYS_IRQS        6
-#define NR_PINTS                112
-#endif
-
 #define NR_PINT_BITS            32
 #define IRQ_NOT_AVAIL           0xFF
 
@@ -897,29 +920,21 @@ static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
 #endif
 };
 
-#ifndef CONFIG_BF60x
 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 {
         unsigned int irq_base;
 
+#ifndef CONFIG_BF60x
         if (bank < 2) {         /*PA-PB */
                 irq_base = IRQ_PA0 + bmap * 16;
         } else {                /*PC-PJ */
                 irq_base = IRQ_PC0 + bmap * 16;
         }
-
-        return irq_base;
-}
 #else
-inline unsigned int get_irq_base(u32 bank, u8 bmap)
-{
-        unsigned int irq_base;
-
         irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
-
+#endif
         return irq_base;
 }
-#endif
 
         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 void init_pint_lut(void)
@@ -1089,6 +1104,9 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
 }
 
 #ifdef CONFIG_PM
+static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
+static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
+
 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 {
         u32 pint_irq;
@@ -1124,6 +1142,59 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 
         return 0;
 }
+
+void bfin_pint_suspend(void)
+{
+        u32 bank;
+
+        for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
+                save_pint_reg[bank].mask_set = pint[bank]->mask_set;
+                save_pint_reg[bank].assign = pint[bank]->assign;
+                save_pint_reg[bank].edge_set = pint[bank]->edge_set;
+                save_pint_reg[bank].invert_set = pint[bank]->invert_set;
+        }
+}
+
+void bfin_pint_resume(void)
+{
+        u32 bank;
+
+        for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
+                pint[bank]->mask_set = save_pint_reg[bank].mask_set;
+                pint[bank]->assign = save_pint_reg[bank].assign;
+                pint[bank]->edge_set = save_pint_reg[bank].edge_set;
+                pint[bank]->invert_set = save_pint_reg[bank].invert_set;
+        }
+}
+
+#ifdef SEC_GCTL
+static int sec_suspend(void)
+{
+        u32 bank;
+
+        for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
+                save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0));
+        return 0;
+}
+
+static void sec_resume(void)
+{
+        u32 bank;
+
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
+        udelay(100);
+        bfin_write_SEC_GCTL(SEC_GCTL_EN);
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+
+        for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
+                bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
+}
+
+static struct syscore_ops sec_pm_syscore_ops = {
+        .suspend = sec_suspend,
+        .resume = sec_resume,
+};
+#endif
 #else
 # define bfin_gpio_set_wake NULL
 #endif
@@ -1230,6 +1301,7 @@ void __cpuinit init_exception_vectors(void)
         CSYNC();
 }
 
+#ifndef SEC_GCTL
 /*
  * This function should be called during kernel startup to initialize
  * the BFin IRQ handling routines.
@@ -1240,7 +1312,6 @@ int __init init_arch_irq(void)
         int irq;
         unsigned long ilat = 0;
 
-#ifndef CONFIG_BF60x
         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
 #ifdef SIC_IMASK0
         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
@@ -1255,9 +1326,6 @@ int __init init_arch_irq(void)
 #else
         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 #endif
-#else /* CONFIG_BF60x */
-        bfin_write_SEC_GCTL(SEC_GCTL_RESET);
-#endif
 
         local_irq_disable();
 
@@ -1267,10 +1335,6 @@ int __init init_arch_irq(void)
         pint[1]->assign = CONFIG_PINT1_ASSIGN;
         pint[2]->assign = CONFIG_PINT2_ASSIGN;
         pint[3]->assign = CONFIG_PINT3_ASSIGN;
-# ifdef CONFIG_BF60x
-        pint[4]->assign = CONFIG_PINT4_ASSIGN;
-        pint[5]->assign = CONFIG_PINT5_ASSIGN;
-# endif
 # endif
         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
         init_pint_lut();
@@ -1283,7 +1347,6 @@ int __init init_arch_irq(void)
                         irq_set_chip(irq, &bfin_internal_irqchip);
 
                 switch (irq) {
-#ifndef CONFIG_BF60x
 #if BFIN_GPIO_PINT
                 case IRQ_PINT0:
                 case IRQ_PINT1:
@@ -1319,7 +1382,6 @@ int __init init_arch_irq(void)
                         irq_set_handler(irq, handle_percpu_irq);
                         break;
 #endif
-#endif
 
 #ifdef CONFIG_TICKSOURCE_CORETMR
                 case IRQ_CORETMR:
@@ -1349,8 +1411,7 @@ int __init init_arch_irq(void)
 
         init_mach_irq();
 
-#ifndef CONFIG_BF60x
-#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) && !defined(CONFIG_BF60x)
+#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
                 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
                                          handle_level_irq);
@@ -1360,28 +1421,6 @@ int __init init_arch_irq(void)
                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
                                          handle_level_irq);
-#else
-        for (irq = BFIN_IRQ(0); irq <= SYS_IRQS; irq++) {
-                if (irq < CORE_IRQS) {
-                        irq_set_chip(irq, &bfin_sec_irqchip);
-                        __irq_set_handler(irq, handle_sec_fault, 0, NULL);
-                } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
-                        irq_set_chip(irq, &bfin_sec_irqchip);
-                        irq_set_chained_handler(irq, bfin_demux_gpio_irq);
-                } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
-                        irq_set_chip(irq, &bfin_sec_irqchip);
-                        irq_set_handler(irq, handle_percpu_irq);
-                } else {
-                        irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
-                                        handle_fasteoi_irq);
-                        __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
-                }
-        }
-        for (irq = GPIO_IRQ_BASE;
-                irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
-                irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
-                                        handle_level_irq);
-#endif
         bfin_write_IMASK(0);
         CSYNC();
         ilat = bfin_read_ILAT();
@@ -1393,7 +1432,6 @@ int __init init_arch_irq(void)
         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
          * local_irq_enable()
          */
-#ifndef CONFIG_BF60x
         program_IAR();
         /* Therefore it's better to setup IARs before interrupts enabled */
         search_IAR();
@@ -1427,23 +1465,6 @@ int __init init_arch_irq(void)
 #else
         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
-#else  /* CONFIG_BF60x */
-        /* Enable interrupts IVG7-15 */
-        bfin_irq_flags |= IMASK_IVG15 |
-            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
-            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
-
-        bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
-        bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
-        bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
-        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
-        udelay(100);
-        bfin_write_SEC_GCTL(SEC_GCTL_EN);
-        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-        init_software_driven_irq();
-        register_syscore_ops(&sec_pm_syscore_ops);
-#endif
         return 0;
 }
 
@@ -1452,14 +1473,11 @@ __attribute__((l1_text))
 #endif
 static int vec_to_irq(int vec)
 {
-#ifndef CONFIG_BF60x
         struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
         struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
         unsigned long sic_status[3];
-#endif
         if (likely(vec == EVT_IVTMR_P))
                 return IRQ_CORETMR;
-#ifndef CONFIG_BF60x
 #ifdef SIC_ISR
         sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
 #else
@@ -1488,11 +1506,119 @@ static int vec_to_irq(int vec)
 #endif
                         return ivg->irqno;
         }
-#else
-        /* for bf60x read */
+}
+
+#else /* SEC_GCTL */
+
+/*
+ * This function should be called during kernel startup to initialize
+ * the BFin IRQ handling routines.
+ */
+
+int __init init_arch_irq(void)
+{
+        int irq;
+        unsigned long ilat = 0;
+
+        bfin_write_SEC_GCTL(SEC_GCTL_RESET);
+
+        local_irq_disable();
+
+#if BFIN_GPIO_PINT
+# ifdef CONFIG_PINTx_REASSIGN
+        pint[0]->assign = CONFIG_PINT0_ASSIGN;
+        pint[1]->assign = CONFIG_PINT1_ASSIGN;
+        pint[2]->assign = CONFIG_PINT2_ASSIGN;
+        pint[3]->assign = CONFIG_PINT3_ASSIGN;
+        pint[4]->assign = CONFIG_PINT4_ASSIGN;
+        pint[5]->assign = CONFIG_PINT5_ASSIGN;
+# endif
+        /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
+        init_pint_lut();
+#endif
+
+        for (irq = 0; irq <= SYS_IRQS; irq++) {
+                if (irq <= IRQ_CORETMR) {
+                        irq_set_chip(irq, &bfin_core_irqchip);
+#ifdef CONFIG_TICKSOURCE_CORETMR
+                        if (irq == IRQ_CORETMR)
+# ifdef CONFIG_SMP
+                                irq_set_handler(irq, handle_percpu_irq);
+# else
+                                irq_set_handler(irq, handle_simple_irq);
+# endif
+#endif
+                } else if (irq < BFIN_IRQ(0)) {
+                        irq_set_chip_and_handler(irq, &bfin_internal_irqchip,
+                                        handle_simple_irq);
+                } else if (irq == IRQ_SEC_ERR) {
+                        irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
+                                        handle_sec_fault);
+                } else if (irq < CORE_IRQS && irq >= IRQ_C0_DBL_FAULT) {
+                        irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
+                                        handle_core_fault);
+                } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
+                        irq_set_chip(irq, &bfin_sec_irqchip);
+                        irq_set_chained_handler(irq, bfin_demux_gpio_irq);
+                } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
+                        irq_set_chip(irq, &bfin_sec_irqchip);
+                        irq_set_handler(irq, handle_percpu_irq);
+                } else {
+                        irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
+                                        handle_fasteoi_irq);
+                        __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
+                }
+        }
+        for (irq = GPIO_IRQ_BASE;
+                irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
+                irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
+                                        handle_level_irq);
+
+        bfin_write_IMASK(0);
+        CSYNC();
+        ilat = bfin_read_ILAT();
+        CSYNC();
+        bfin_write_ILAT(ilat);
+        CSYNC();
+
+        printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
+
+        bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
+
+        bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
+
+        /* Enable interrupts IVG7-15 */
+        bfin_irq_flags |= IMASK_IVG15 |
+            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
+            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
+
+
+        bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
+        bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
+        bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
+        udelay(100);
+        bfin_write_SEC_GCTL(SEC_GCTL_EN);
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+        bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+
+        init_software_driven_irq();
+        register_syscore_ops(&sec_pm_syscore_ops);
+
+        return 0;
+}
+
+#ifdef CONFIG_DO_IRQ_L1
+__attribute__((l1_text))
+#endif
+static int vec_to_irq(int vec)
+{
+        if (likely(vec == EVT_IVTMR_P))
+                return IRQ_CORETMR;
+
         return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
-#endif  /* end of CONFIG_BF60x */
 }
+#endif  /* SEC_GCTL */
 
 #ifdef CONFIG_DO_IRQ_L1
 __attribute__((l1_text))
@@ -1514,6 +1640,10 @@ int __ipipe_get_irq_priority(unsigned irq)
         if (irq <= IRQ_CORETMR)
                 return irq;
 
+#ifdef SEC_GCTL
+        if (irq >= BFIN_IRQ(0))
+                return IVG11;
+#else
         for (ient = 0; ient < NR_PERI_INTS; ient++) {
                 struct ivgx *ivg = ivg_table + ient;
                 if (ivg->irqno == irq) {
@@ -1524,6 +1654,7 @@ int __ipipe_get_irq_priority(unsigned irq)
                         }
                 }
         }
+#endif
 
         return IVG15;
 }
@@ -1536,8 +1667,6 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
 {
         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
         struct ipipe_domain *this_domain = __ipipe_current_domain;
-        struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
-        struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
         int irq, s = 0;
 
         irq = vec_to_irq(vec);
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index ca6655e0d65..87bfe549ad3 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -172,6 +172,10 @@ int bfin_pm_suspend_mem_enter(void)
 
         bfin_gpio_pm_hibernate_suspend();
 
+#if BFIN_GPIO_PINT
+        bfin_pint_suspend();
+#endif
+
 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
         flushinv_all_dcache();
 #endif
@@ -190,6 +194,10 @@ int bfin_pm_suspend_mem_enter(void)
         _enable_icplb();
         _enable_dcplb();
 
+#if BFIN_GPIO_PINT
+        bfin_pint_resume();
+#endif
+
         bfin_gpio_pm_hibernate_restore();
         blackfin_dma_resume();
 
diff --git a/arch/c6x/Kconfig b/arch/c6x/Kconfig
index 052f81a7623..983c859e40b 100644
--- a/arch/c6x/Kconfig
+++ b/arch/c6x/Kconfig
@@ -6,6 +6,7 @@
 config C6X
         def_bool y
         select CLKDEV_LOOKUP
+        select GENERIC_ATOMIC64
         select GENERIC_IRQ_SHOW
         select HAVE_ARCH_TRACEHOOK
         select HAVE_DMA_API_DEBUG
diff --git a/arch/c6x/boot/dts/evmc6678.dts b/arch/c6x/boot/dts/evmc6678.dts
new file mode 100644
index 00000000000..ab686301d32
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6678.dts
@@ -0,0 +1,83 @@
+/*
+ * arch/c6x/boot/dts/evmc6678.dts
+ *
+ * EVMC6678 Evaluation Platform For TMS320C6678
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated
+ *
+ * Author: Ken Cox <jkc@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ */
+
+/dts-v1/;
+
+/include/ "tms320c6678.dtsi"
+
+/ {
+        model = "Advantech EVMC6678";
+        compatible = "advantech,evmc6678";
+
+        chosen {
+                bootargs = "root=/dev/nfs ip=dhcp rw";
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x20000000>;
+        };
+
+        soc {
+                megamod_pic: interrupt-controller@1800000 {
+                       interrupts = < 12 13 14 15 >;
+                };
+
+                timer8: timer@2280000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 66 >;
+                };
+
+                timer9: timer@2290000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 68 >;
+                };
+
+                timer10: timer@22A0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 70 >;
+                };
+
+                timer11: timer@22B0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 72 >;
+                };
+
+                timer12: timer@22C0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 74 >;
+                };
+
+                timer13: timer@22D0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 76 >;
+                };
+
+                timer14: timer@22E0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 78 >;
+                };
+
+                timer15: timer@22F0000 {
+                        interrupt-parent = <&megamod_pic>;
+                        interrupts = < 80 >;
+                };
+
+                clock-controller@2310000 {
+                        clock-frequency = <100000000>;
+                };
+        };
+};
diff --git a/arch/c6x/boot/dts/tms320c6678.dtsi b/arch/c6x/boot/dts/tms320c6678.dtsi
new file mode 100644
index 00000000000..386196e5eae
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6678.dtsi
@@ -0,0 +1,146 @@
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        reg = <0>;
+                        model = "ti,c66x";
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        reg = <1>;
+                        model = "ti,c66x";
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        reg = <2>;
+                        model = "ti,c66x";
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        reg = <3>;
+                        model = "ti,c66x";
+                };
+                cpu@4 {
+                        device_type = "cpu";
+                        reg = <4>;
+                        model = "ti,c66x";
+                };
+                cpu@5 {
+                        device_type = "cpu";
+                        reg = <5>;
+                        model = "ti,c66x";
+                };
+                cpu@6 {
+                        device_type = "cpu";
+                        reg = <6>;
+                        model = "ti,c66x";
+                };
+                cpu@7 {
+                        device_type = "cpu";
+                        reg = <7>;
+                        model = "ti,c66x";
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                model = "tms320c6678";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                core_pic: interrupt-controller {
+                        compatible = "ti,c64x+core-pic";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                megamod_pic: interrupt-controller@1800000 {
+                       compatible = "ti,c64x+megamod-pic";
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       reg = <0x1800000 0x1000>;
+                       interrupt-parent = <&core_pic>;
+                };
+
+                cache-controller@1840000 {
+                        compatible = "ti,c64x+cache";
+                        reg = <0x01840000 0x8400>;
+                };
+
+                timer8: timer@2280000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x01 >;
+                        reg = <0x2280000 0x40>;
+                };
+
+                timer9: timer@2290000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x02 >;
+                        reg = <0x2290000 0x40>;
+                };
+
+                timer10: timer@22A0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x04 >;
+                        reg = <0x22A0000 0x40>;
+                };
+
+                timer11: timer@22B0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x08 >;
+                        reg = <0x22B0000 0x40>;
+                };
+
+                timer12: timer@22C0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x10 >;
+                        reg = <0x22C0000 0x40>;
+                };
+
+                timer13: timer@22D0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x20 >;
+                        reg = <0x22D0000 0x40>;
+                };
+
+                timer14: timer@22E0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x40 >;
+                        reg = <0x22E0000 0x40>;
+                };
+
+                timer15: timer@22F0000 {
+                        compatible = "ti,c64x+timer64";
+                        ti,core-mask = < 0x80 >;
+                        reg = <0x22F0000 0x40>;
+                };
+
+                clock-controller@2310000 {
+                        compatible = "ti,c6678-pll", "ti,c64x+pll";
+                        reg = <0x02310000 0x200>;
+                        ti,c64x+pll-bypass-delay = <200>;
+                        ti,c64x+pll-reset-delay = <12000>;
+                        ti,c64x+pll-lock-delay = <80000>;
+                };
+
+                device-state-controller@2620000 {
+                        compatible = "ti,c64x+dscr";
+                        reg = <0x02620000 0x1000>;
+
+                        ti,dscr-devstat = <0x20>;
+                        ti,dscr-silicon-rev = <0x18 28 0xf>;
+
+                        ti,dscr-mac-fuse-regs = <0x110 1 2 3 4
+                                                 0x114 5 6 0 0>;
+
+                };
+        };
+};
diff --git a/arch/c6x/configs/evmc6678_defconfig b/arch/c6x/configs/evmc6678_defconfig
new file mode 100644
index 00000000000..5f126d4905b
--- /dev/null
+++ b/arch/c6x/configs/evmc6678_defconfig
@@ -0,0 +1,42 @@
+CONFIG_SOC_TMS320C6678=y
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EXPERT=y
+# CONFIG_FUTEX is not set
+# CONFIG_SLUB_DEBUG is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_FORCE is not set
+CONFIG_BOARD_EVM6678=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=2
+CONFIG_BLK_DEV_RAM_SIZE=17000
+CONFIG_MISC_DEVICES=y
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_CRC16=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
diff --git a/arch/c6x/include/asm/cache.h b/arch/c6x/include/asm/cache.h
index 6d521d96d94..09c5a0f5f4d 100644
--- a/arch/c6x/include/asm/cache.h
+++ b/arch/c6x/include/asm/cache.h
@@ -1,7 +1,7 @@
 /*
  *  Port on Texas Instruments TMS320C6x architecture
  *
- *  Copyright (C) 2005, 2006, 2009, 2010 Texas Instruments Incorporated
+ *  Copyright (C) 2005, 2006, 2009, 2010, 2012 Texas Instruments Incorporated
  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
  *
  *  This program is free software; you can redistribute it and/or modify
@@ -16,9 +16,14 @@
 /*
  * Cache line size
  */
-#define L1D_CACHE_BYTES   64
-#define L1P_CACHE_BYTES   32
-#define L2_CACHE_BYTES    128
+#define L1D_CACHE_SHIFT   6
+#define L1D_CACHE_BYTES   (1 << L1D_CACHE_SHIFT)
+
+#define L1P_CACHE_SHIFT   5
+#define L1P_CACHE_BYTES   (1 << L1P_CACHE_SHIFT)
+
+#define L2_CACHE_SHIFT    7
+#define L2_CACHE_BYTES    (1 << L2_CACHE_SHIFT)
 
 /*
  * L2 used as cache
@@ -29,7 +34,8 @@
  * For practical reasons the L1_CACHE_BYTES defines should not be smaller than
  * the L2 line size
  */
-#define L1_CACHE_BYTES        L2_CACHE_BYTES
+#define L1_CACHE_SHIFT        L2_CACHE_SHIFT
+#define L1_CACHE_BYTES        (1 << L1_CACHE_SHIFT)
 
 #define L2_CACHE_ALIGN_LOW(x) \
         (((x) & ~(L2_CACHE_BYTES - 1)))
diff --git a/arch/c6x/include/asm/irq.h b/arch/c6x/include/asm/irq.h
index ab4577f93d9..1324e62bd4e 100644
--- a/arch/c6x/include/asm/irq.h
+++ b/arch/c6x/include/asm/irq.h
@@ -34,8 +34,6 @@
  */
 #define NR_PRIORITY_IRQS 16
 
-#define NR_IRQS_LEGACY  NR_PRIORITY_IRQS
-
 /* Total number of virq in the platform */
 #define NR_IRQS         256
 
diff --git a/arch/c6x/kernel/irq.c b/arch/c6x/kernel/irq.c
index c90fb5e82ad..247e0eb5e46 100644
--- a/arch/c6x/kernel/irq.c
+++ b/arch/c6x/kernel/irq.c
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2011 Texas Instruments Incorporated
+ *  Copyright (C) 2011-2012 Texas Instruments Incorporated
  *
  *  This borrows heavily from powerpc version, which is:
  *
@@ -35,9 +35,7 @@ static DEFINE_RAW_SPINLOCK(core_irq_lock);
 
 static void mask_core_irq(struct irq_data *data)
 {
-        unsigned int prio = data->irq;
-
-        BUG_ON(prio < 4 || prio >= NR_PRIORITY_IRQS);
+        unsigned int prio = data->hwirq;
 
         raw_spin_lock(&core_irq_lock);
         and_creg(IER, ~(1 << prio));
@@ -46,7 +44,7 @@ static void mask_core_irq(struct irq_data *data)
 
 static void unmask_core_irq(struct irq_data *data)
 {
-        unsigned int prio = data->irq;
+        unsigned int prio = data->hwirq;
 
         raw_spin_lock(&core_irq_lock);
         or_creg(IER, 1 << prio);
@@ -59,15 +57,15 @@ static struct irq_chip core_chip = {
         .irq_unmask     = unmask_core_irq,
 };
 
+static int prio_to_virq[NR_PRIORITY_IRQS];
+
 asmlinkage void c6x_do_IRQ(unsigned int prio, struct pt_regs *regs)
 {
         struct pt_regs *old_regs = set_irq_regs(regs);
 
         irq_enter();
 
-        BUG_ON(prio < 4 || prio >= NR_PRIORITY_IRQS);
-
-        generic_handle_irq(prio);
+        generic_handle_irq(prio_to_virq[prio]);
 
         irq_exit();
 
@@ -82,6 +80,8 @@ static int core_domain_map(struct irq_domain *h, unsigned int virq,
         if (hw < 4 || hw >= NR_PRIORITY_IRQS)
                 return -EINVAL;
 
+        prio_to_virq[hw] = virq;
+
         irq_set_status_flags(virq, IRQ_LEVEL);
         irq_set_chip_and_handler(virq, &core_chip, handle_level_irq);
         return 0;
@@ -102,9 +102,8 @@ void __init init_IRQ(void)
         np = of_find_compatible_node(NULL, NULL, "ti,c64x+core-pic");
         if (np != NULL) {
                 /* create the core host */
-                core_domain = irq_domain_add_legacy(np, NR_PRIORITY_IRQS,
-                                                    0, 0, &core_domain_ops,
-                                                    NULL);
+                core_domain = irq_domain_add_linear(np, NR_PRIORITY_IRQS,
+                                                    &core_domain_ops, NULL);
                 if (core_domain)
                         irq_set_default_host(core_domain);
                 of_node_put(np);
diff --git a/arch/c6x/kernel/setup.c b/arch/c6x/kernel/setup.c
index ce46186600c..f4e72bd8c10 100644
--- a/arch/c6x/kernel/setup.c
+++ b/arch/c6x/kernel/setup.c
@@ -143,6 +143,10 @@ static void __init get_cpuinfo(void)
                 p->cpu_name = "C64x+";
                 p->cpu_voltage = "1.2";
                 break;
+        case 21:
+                p->cpu_name = "C66X";
+                p->cpu_voltage = "1.2";
+                break;
         default:
                 p->cpu_name = "unknown";
                 break;
diff --git a/arch/c6x/kernel/signal.c b/arch/c6x/kernel/signal.c
index 3d8f3c22a94..3998b24e26f 100644
--- a/arch/c6x/kernel/signal.c
+++ b/arch/c6x/kernel/signal.c
@@ -249,8 +249,6 @@ static void handle_signal(int sig,
                          siginfo_t *info, struct k_sigaction *ka,
                          struct pt_regs *regs, int syscall)
 {
-        int ret;
-
         /* Are we from a system call? */
         if (syscall) {
                 /* If so, check system call restarting.. */
diff --git a/arch/c6x/kernel/soc.c b/arch/c6x/kernel/soc.c
index 0748c94ebef..3ac74080fde 100644
--- a/arch/c6x/kernel/soc.c
+++ b/arch/c6x/kernel/soc.c
@@ -80,7 +80,7 @@ int soc_mac_addr(unsigned int index, u8 *addr)
                 if (have_fuse_mac)
                         memcpy(addr, c6x_fuse_mac, 6);
                 else
-                        random_ether_addr(addr);
+                        eth_random_addr(addr);
         }
 
         /* adjust for specific EMAC device */
diff --git a/arch/c6x/platforms/Kconfig b/arch/c6x/platforms/Kconfig
index 401ee678fd0..c4a0fad89aa 100644
--- a/arch/c6x/platforms/Kconfig
+++ b/arch/c6x/platforms/Kconfig
@@ -14,3 +14,7 @@ config SOC_TMS320C6472
 config SOC_TMS320C6474
         bool "TMS320C6474"
         default n
+
+config SOC_TMS320C6678
+        bool "TMS320C6678"
+        default n
diff --git a/arch/c6x/platforms/megamod-pic.c b/arch/c6x/platforms/megamod-pic.c
index c1c4e2ae3f8..74e3371eb82 100644
--- a/arch/c6x/platforms/megamod-pic.c
+++ b/arch/c6x/platforms/megamod-pic.c
@@ -243,27 +243,37 @@ static struct megamod_pic * __init init_megamod_pic(struct device_node *np)
          * as their interrupt parent.
          */
         for (i = 0; i < NR_COMBINERS; i++) {
+                struct irq_data *irq_data;
+                irq_hw_number_t hwirq;
 
                 irq = irq_of_parse_and_map(np, i);
                 if (irq == NO_IRQ)
                         continue;
 
+                irq_data = irq_get_irq_data(irq);
+                if (!irq_data) {
+                        pr_err("%s: combiner-%d no irq_data for virq %d!\n",
+                               np->full_name, i, irq);
+                        continue;
+                }
+
+                hwirq = irq_data->hwirq;
+
                 /*
-                 * We count on the core priority interrupts (4 - 15) being
-                 * direct mapped. Check that device tree provided something
-                 * in that range.
+                 * Check that device tree provided something in the range
+                 * of the core priority interrupts (4 - 15).
                  */
-                if (irq < 4 || irq >= NR_PRIORITY_IRQS) {
-                        pr_err("%s: combiner-%d virq %d out of range!\n",
-                                 np->full_name, i, irq);
+                if (hwirq < 4 || hwirq >= NR_PRIORITY_IRQS) {
+                        pr_err("%s: combiner-%d core irq %ld out of range!\n",
+                               np->full_name, i, hwirq);
                         continue;
                 }
 
                 /* record the mapping */
-                mapping[irq - 4] = i;
+                mapping[hwirq - 4] = i;
 
-                pr_debug("%s: combiner-%d cascading to virq %d\n",
-                         np->full_name, i, irq);
+                pr_debug("%s: combiner-%d cascading to hwirq %ld\n",
+                         np->full_name, i, hwirq);
 
                 cascade_data[i].pic = pic;
                 cascade_data[i].index = i;
diff --git a/arch/c6x/platforms/plldata.c b/arch/c6x/platforms/plldata.c
index 2cfd6f42968..755359eb628 100644
--- a/arch/c6x/platforms/plldata.c
+++ b/arch/c6x/platforms/plldata.c
@@ -335,6 +335,68 @@ static void __init c6474_setup_clocks(struct device_node *node)
 }
 #endif /* CONFIG_SOC_TMS320C6474 */
 
+#ifdef CONFIG_SOC_TMS320C6678
+static struct clk_lookup c6678_clks[] = {
+        CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
+        CLK(NULL, "pll1_refclk", &c6x_soc_pll1.sysclks[1]),
+        CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
+        CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
+        CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
+        CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
+        CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
+        CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
+        CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
+        CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
+        CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
+        CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
+        CLK(NULL, "core", &c6x_core_clk),
+        CLK("", NULL, NULL)
+};
+
+static void __init c6678_setup_clocks(struct device_node *node)
+{
+        struct pll_data *pll = &c6x_soc_pll1;
+        struct clk *sysclks = pll->sysclks;
+
+        pll->flags = PLL_HAS_MUL;
+
+        sysclks[1].flags |= FIXED_DIV_PLL;
+        sysclks[1].div = 1;
+
+        sysclks[2].div = PLLDIV2;
+
+        sysclks[3].flags |= FIXED_DIV_PLL;
+        sysclks[3].div = 2;
+
+        sysclks[4].flags |= FIXED_DIV_PLL;
+        sysclks[4].div = 3;
+
+        sysclks[5].div = PLLDIV5;
+
+        sysclks[6].flags |= FIXED_DIV_PLL;
+        sysclks[6].div = 64;
+
+        sysclks[7].flags |= FIXED_DIV_PLL;
+        sysclks[7].div = 6;
+
+        sysclks[8].div = PLLDIV8;
+
+        sysclks[9].flags |= FIXED_DIV_PLL;
+        sysclks[9].div = 12;
+
+        sysclks[10].flags |= FIXED_DIV_PLL;
+        sysclks[10].div = 3;
+
+        sysclks[11].flags |= FIXED_DIV_PLL;
+        sysclks[11].div = 6;
+
+        c6x_core_clk.parent = &sysclks[0];
+        c6x_i2c_clk.parent = &sysclks[7];
+
+        c6x_clks_init(c6678_clks);
+}
+#endif /* CONFIG_SOC_TMS320C6678 */
+
 static struct of_device_id c6x_clkc_match[] __initdata = {
 #ifdef CONFIG_SOC_TMS320C6455
         { .compatible = "ti,c6455-pll", .data = c6455_setup_clocks },
@@ -348,6 +410,9 @@ static struct of_device_id c6x_clkc_match[] __initdata = {
 #ifdef CONFIG_SOC_TMS320C6474
         { .compatible = "ti,c6474-pll", .data = c6474_setup_clocks },
 #endif
+#ifdef CONFIG_SOC_TMS320C6678
+        { .compatible = "ti,c6678-pll", .data = c6678_setup_clocks },
+#endif
         { .compatible = "ti,c64x+pll" },
         {}
 };
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index bb344650a14..e92215428a3 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -42,6 +42,7 @@ config CRIS
         select HAVE_IDE
         select GENERIC_ATOMIC64
         select HAVE_GENERIC_HARDIRQS
+        select ARCH_WANT_IPC_PARSE_VERSION
         select GENERIC_IRQ_SHOW
         select GENERIC_IOMAP
         select GENERIC_SMP_IDLE_THREAD if ETRAX_ARCH_V32
diff --git a/arch/cris/arch-v32/drivers/pci/bios.c b/arch/cris/arch-v32/drivers/pci/bios.c
index bc0cfdad1cb..5b1ee82f63c 100644
--- a/arch/cris/arch-v32/drivers/pci/bios.c
+++ b/arch/cris/arch-v32/drivers/pci/bios.c
@@ -6,11 +6,6 @@ void __devinit  pcibios_fixup_bus(struct pci_bus *b)
 {
 }
 
-char * __devinit  pcibios_setup(char *str)
-{
-        return NULL;
-}
-
 void pcibios_set_master(struct pci_dev *dev)
 {
         u8 lat;
diff --git a/arch/cris/include/asm/unistd.h b/arch/cris/include/asm/unistd.h
index f921b8b0f97..51873a446f8 100644
--- a/arch/cris/include/asm/unistd.h
+++ b/arch/cris/include/asm/unistd.h
@@ -347,7 +347,6 @@
 
 #include <arch/unistd.h>
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_OLD_STAT
 #define __ARCH_WANT_STAT64
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index a685910d2d5..971c0a19fac 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -9,6 +9,7 @@ config FRV
         select GENERIC_IRQ_SHOW
         select ARCH_HAVE_NMI_SAFE_CMPXCHG
         select GENERIC_CPU_DEVICES
+        select ARCH_WANT_IPC_PARSE_VERSION
 
 config ZONE_DMA
         bool
diff --git a/arch/frv/include/asm/cpumask.h b/arch/frv/include/asm/cpumask.h
deleted file mode 100644
index d999c20c84d..00000000000
--- a/arch/frv/include/asm/cpumask.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_CPUMASK_H
-#define _ASM_CPUMASK_H
-
-#include <asm-generic/cpumask.h>
-
-#endif /* _ASM_CPUMASK_H */
diff --git a/arch/frv/include/asm/highmem.h b/arch/frv/include/asm/highmem.h
index 716956a5317..b3adc93611f 100644
--- a/arch/frv/include/asm/highmem.h
+++ b/arch/frv/include/asm/highmem.h
@@ -76,15 +76,16 @@ extern struct page *kmap_atomic_to_page(void *ptr);
 
 #ifndef __ASSEMBLY__
 
-#define __kmap_atomic_primary(type, paddr, ampr)                                                \
+#define __kmap_atomic_primary(cached, paddr, ampr)                                              \
 ({                                                                                              \
         unsigned long damlr, dampr;                                                             \
                                                                                                 \
         dampr = paddr | xAMPRx_L | xAMPRx_M | xAMPRx_S | xAMPRx_SS_16Kb | xAMPRx_V;             \
                                                                                                 \
-        if (type != __KM_CACHE)                                                                 \
+        if (!cached)                                                                            \
                 asm volatile("movgs %0,dampr"#ampr :: "r"(dampr) : "memory");                   \
         else                                                                                    \
+                /* cache flush page attachment point */                                         \
                 asm volatile("movgs %0,iampr"#ampr"\n"                                          \
                              "movgs %0,dampr"#ampr"\n"                                          \
                              :: "r"(dampr) : "memory"                                           \
@@ -112,29 +113,20 @@ extern struct page *kmap_atomic_to_page(void *ptr);
         (void *) damlr;                                                                           \
 })
 
-static inline void *kmap_atomic_primary(struct page *page, enum km_type type)
+static inline void *kmap_atomic_primary(struct page *page)
 {
         unsigned long paddr;
 
         pagefault_disable();
         paddr = page_to_phys(page);
 
-        switch (type) {
-        case 0:         return __kmap_atomic_primary(0, paddr, 2);
-        case 1:         return __kmap_atomic_primary(1, paddr, 3);
-        case 2:         return __kmap_atomic_primary(2, paddr, 4);
-        case 3:         return __kmap_atomic_primary(3, paddr, 5);
-
-        default:
-                BUG();
-                return NULL;
-        }
+        return __kmap_atomic_primary(1, paddr, 2);
 }
 
-#define __kunmap_atomic_primary(type, ampr)                             \
+#define __kunmap_atomic_primary(cached, ampr)                           \
 do {                                                                    \
         asm volatile("movgs gr0,dampr"#ampr"\n" ::: "memory");          \
-        if (type == __KM_CACHE)                                         \
+        if (cached)                                                     \
                 asm volatile("movgs gr0,iampr"#ampr"\n" ::: "memory");  \
 } while(0)
 
@@ -143,17 +135,9 @@ do {									\
         asm volatile("tlbpr %0,gr0,#4,#1" : : "r"(vaddr) : "memory");   \
 } while(0)
 
-static inline void kunmap_atomic_primary(void *kvaddr, enum km_type type)
+static inline void kunmap_atomic_primary(void *kvaddr)
 {
-        switch (type) {
-        case 0:         __kunmap_atomic_primary(0, 2);  break;
-        case 1:         __kunmap_atomic_primary(1, 3);  break;
-        case 2:         __kunmap_atomic_primary(2, 4);  break;
-        case 3:         __kunmap_atomic_primary(3, 5);  break;
-
-        default:
-                BUG();
-        }
+        __kunmap_atomic_primary(1, 2);
         pagefault_enable();
 }
 
diff --git a/arch/frv/include/asm/kmap_types.h b/arch/frv/include/asm/kmap_types.h
index f8e16b2a580..43901f22096 100644
--- a/arch/frv/include/asm/kmap_types.h
+++ b/arch/frv/include/asm/kmap_types.h
@@ -2,28 +2,6 @@
 #ifndef _ASM_KMAP_TYPES_H
 #define _ASM_KMAP_TYPES_H
 
-enum km_type {
-        /* arch specific kmaps - change the numbers attached to these at your peril */
-        __KM_CACHE,             /* cache flush page attachment point */
-        __KM_PGD,               /* current page directory */
-        __KM_ITLB_PTD,          /* current instruction TLB miss page table lookup */
-        __KM_DTLB_PTD,          /* current data TLB miss page table lookup */
-
-        /* general kmaps */
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
+#define KM_TYPE_NR 17
 
 #endif
diff --git a/arch/frv/include/asm/unistd.h b/arch/frv/include/asm/unistd.h
index a569dff7cd5..67f23a311db 100644
--- a/arch/frv/include/asm/unistd.h
+++ b/arch/frv/include/asm/unistd.h
@@ -349,7 +349,6 @@
 
 #define NR_syscalls 338
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 /* #define __ARCH_WANT_OLD_READDIR */
 #define __ARCH_WANT_OLD_STAT
 #define __ARCH_WANT_STAT64
diff --git a/arch/frv/kernel/kernel_thread.S b/arch/frv/kernel/kernel_thread.S
index 4531c830d20..f0e52943f92 100644
--- a/arch/frv/kernel/kernel_thread.S
+++ b/arch/frv/kernel/kernel_thread.S
@@ -10,10 +10,10 @@
  */
 
 #include <linux/linkage.h>
+#include <linux/kern_levels.h>
 #include <asm/unistd.h>
 
 #define CLONE_VM        0x00000100      /* set if VM shared between processes */
-#define KERN_ERR        "<3>"
 
         .section .rodata
 kernel_thread_emsg:
diff --git a/arch/frv/mb93090-mb00/pci-dma.c b/arch/frv/mb93090-mb00/pci-dma.c
index 4f8d8bcdc7d..82478979ac9 100644
--- a/arch/frv/mb93090-mb00/pci-dma.c
+++ b/arch/frv/mb93090-mb00/pci-dma.c
@@ -62,14 +62,14 @@ int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
         dampr2 = __get_DAMPR(2);
 
         for (i = 0; i < nents; i++) {
-                vaddr = kmap_atomic_primary(sg_page(&sg[i]), __KM_CACHE);
+                vaddr = kmap_atomic_primary(sg_page(&sg[i]));
 
                 frv_dcache_writeback((unsigned long) vaddr,
                                      (unsigned long) vaddr + PAGE_SIZE);
 
         }
 
-        kunmap_atomic_primary(vaddr, __KM_CACHE);
+        kunmap_atomic_primary(vaddr);
         if (dampr2) {
                 __set_DAMPR(2, dampr2);
                 __set_IAMPR(2, dampr2);
diff --git a/arch/frv/mb93090-mb00/pci-vdk.c b/arch/frv/mb93090-mb00/pci-vdk.c
index 6b0b82ff441..d04ed14bbf0 100644
--- a/arch/frv/mb93090-mb00/pci-vdk.c
+++ b/arch/frv/mb93090-mb00/pci-vdk.c
@@ -268,7 +268,7 @@ static void __init pci_fixup_umc_ide(struct pci_dev *d)
                 d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
 }
 
-static void __init pci_fixup_ide_bases(struct pci_dev *d)
+static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
 {
         int i;
 
@@ -287,7 +287,7 @@ static void __init pci_fixup_ide_bases(struct pci_dev *d)
         }
 }
 
-static void __init pci_fixup_ide_trash(struct pci_dev *d)
+static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
 {
         int i;
 
diff --git a/arch/frv/mm/cache-page.c b/arch/frv/mm/cache-page.c
index b24ade27a0f..8e09dae0ec3 100644
--- a/arch/frv/mm/cache-page.c
+++ b/arch/frv/mm/cache-page.c
@@ -26,11 +26,11 @@ void flush_dcache_page(struct page *page)
 
         dampr2 = __get_DAMPR(2);
 
-        vaddr = kmap_atomic_primary(page, __KM_CACHE);
+        vaddr = kmap_atomic_primary(page);
 
         frv_dcache_writeback((unsigned long) vaddr, (unsigned long) vaddr + PAGE_SIZE);
 
-        kunmap_atomic_primary(vaddr, __KM_CACHE);
+        kunmap_atomic_primary(vaddr);
 
         if (dampr2) {
                 __set_DAMPR(2, dampr2);
@@ -54,12 +54,12 @@ void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
 
         dampr2 = __get_DAMPR(2);
 
-        vaddr = kmap_atomic_primary(page, __KM_CACHE);
+        vaddr = kmap_atomic_primary(page);
 
         start = (start & ~PAGE_MASK) | (unsigned long) vaddr;
         frv_cache_wback_inv(start, start + len);
 
-        kunmap_atomic_primary(vaddr, __KM_CACHE);
+        kunmap_atomic_primary(vaddr);
 
         if (dampr2) {
                 __set_DAMPR(2, dampr2);
diff --git a/arch/frv/mm/highmem.c b/arch/frv/mm/highmem.c
index 31902c9d5be..bed9a9bd3c1 100644
--- a/arch/frv/mm/highmem.c
+++ b/arch/frv/mm/highmem.c
@@ -50,11 +50,11 @@ void *kmap_atomic(struct page *page)
         /*
          * The first 4 primary maps are reserved for architecture code
          */
-        case 0:         return __kmap_atomic_primary(4, paddr, 6);
-        case 1:         return __kmap_atomic_primary(5, paddr, 7);
-        case 2:         return __kmap_atomic_primary(6, paddr, 8);
-        case 3:         return __kmap_atomic_primary(7, paddr, 9);
-        case 4:         return __kmap_atomic_primary(8, paddr, 10);
+        case 0:         return __kmap_atomic_primary(0, paddr, 6);
+        case 1:         return __kmap_atomic_primary(0, paddr, 7);
+        case 2:         return __kmap_atomic_primary(0, paddr, 8);
+        case 3:         return __kmap_atomic_primary(0, paddr, 9);
+        case 4:         return __kmap_atomic_primary(0, paddr, 10);
 
         case 5 ... 5 + NR_TLB_LINES - 1:
                 return __kmap_atomic_secondary(type - 5, paddr);
@@ -70,11 +70,11 @@ void __kunmap_atomic(void *kvaddr)
 {
         int type = kmap_atomic_idx();
         switch (type) {
-        case 0:         __kunmap_atomic_primary(4, 6);  break;
-        case 1:         __kunmap_atomic_primary(5, 7);  break;
-        case 2:         __kunmap_atomic_primary(6, 8);  break;
-        case 3:         __kunmap_atomic_primary(7, 9);  break;
-        case 4:         __kunmap_atomic_primary(8, 10); break;
+        case 0:         __kunmap_atomic_primary(0, 6);  break;
+        case 1:         __kunmap_atomic_primary(0, 7);  break;
+        case 2:         __kunmap_atomic_primary(0, 8);  break;
+        case 3:         __kunmap_atomic_primary(0, 9);  break;
+        case 4:         __kunmap_atomic_primary(0, 10); break;
 
         case 5 ... 5 + NR_TLB_LINES - 1:
                 __kunmap_atomic_secondary(type - 5, kvaddr);
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 56e890df505..5e8a0d9a09c 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -3,6 +3,7 @@ config H8300
         default y
         select HAVE_IDE
         select HAVE_GENERIC_HARDIRQS
+        select ARCH_WANT_IPC_PARSE_VERSION
         select GENERIC_IRQ_SHOW
         select GENERIC_CPU_DEVICES
 
diff --git a/arch/h8300/include/asm/unistd.h b/arch/h8300/include/asm/unistd.h
index 718511303b4..5cd882801d7 100644
--- a/arch/h8300/include/asm/unistd.h
+++ b/arch/h8300/include/asm/unistd.h
@@ -331,7 +331,6 @@
 
 #define NR_syscalls 321
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_OLD_STAT
 #define __ARCH_WANT_STAT64
diff --git a/arch/hexagon/include/asm/Kbuild b/arch/hexagon/include/asm/Kbuild
index 9aa17f1917e..06906427c0a 100644
--- a/arch/hexagon/include/asm/Kbuild
+++ b/arch/hexagon/include/asm/Kbuild
@@ -7,7 +7,6 @@ header-y += user.h
 generic-y += auxvec.h
 generic-y += bug.h
 generic-y += bugs.h
-generic-y += cpumask.h
 generic-y += cputime.h
 generic-y += current.h
 generic-y += device.h
@@ -23,7 +22,6 @@ generic-y += ioctl.h
 generic-y += ioctls.h
 generic-y += iomap.h
 generic-y += ipcbuf.h
-generic-y += ipc.h
 generic-y += irq_regs.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c
index f7264621e58..149fbefc1a4 100644
--- a/arch/hexagon/kernel/smp.c
+++ b/arch/hexagon/kernel/smp.c
@@ -180,9 +180,7 @@ void __cpuinit start_secondary(void)
 
         notify_cpu_starting(cpu);
 
-        ipi_call_lock();
         set_cpu_online(cpu, true);
-        ipi_call_unlock();
 
         local_irq_enable();
 
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 8186ec5ea15..310cf5781fa 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -126,6 +126,7 @@ config AUDIT_ARCH
 
 menuconfig PARAVIRT_GUEST
         bool "Paravirtualized guest support"
+        depends on BROKEN
         help
           Say Y here to get to see options related to running Linux under
           various hypervisors.  This option alone does not add any kernel code.
@@ -138,8 +139,6 @@ config PARAVIRT
         bool "Enable paravirtualization code"
         depends on PARAVIRT_GUEST
         default y
-        bool
-        default y
         help
           This changes the kernel so it can modify itself when it is run
           under a hypervisor, potentially improving performance significantly
diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig
index 954d81e2e83..7913695b2fc 100644
--- a/arch/ia64/configs/generic_defconfig
+++ b/arch/ia64/configs/generic_defconfig
@@ -234,5 +234,4 @@ CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_MD5=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRC_T10DIF=y
-CONFIG_MISC_DEVICES=y
 CONFIG_INTEL_IOMMU=y
diff --git a/arch/ia64/configs/gensparse_defconfig b/arch/ia64/configs/gensparse_defconfig
index 91c41ecfa6d..f8e91336542 100644
--- a/arch/ia64/configs/gensparse_defconfig
+++ b/arch/ia64/configs/gensparse_defconfig
@@ -209,4 +209,3 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_MUTEXES=y
 CONFIG_CRYPTO_MD5=y
-CONFIG_MISC_DEVICES=y
diff --git a/arch/ia64/include/asm/atomic.h b/arch/ia64/include/asm/atomic.h
index 7d9116600a3..6e6fe1839f5 100644
--- a/arch/ia64/include/asm/atomic.h
+++ b/arch/ia64/include/asm/atomic.h
@@ -17,8 +17,8 @@
 #include <asm/intrinsics.h>
 
 
-#define ATOMIC_INIT(i)          ((atomic_t) { (i) })
-#define ATOMIC64_INIT(i)        ((atomic64_t) { (i) })
+#define ATOMIC_INIT(i)          { (i) }
+#define ATOMIC64_INIT(i)        { (i) }
 
 #define atomic_read(v)          (*(volatile int *)&(v)->counter)
 #define atomic64_read(v)        (*(volatile long *)&(v)->counter)
diff --git a/arch/ia64/include/asm/iommu.h b/arch/ia64/include/asm/iommu.h
index b6a809fa299..105c93b00b1 100644
--- a/arch/ia64/include/asm/iommu.h
+++ b/arch/ia64/include/asm/iommu.h
@@ -11,12 +11,10 @@ extern void no_iommu_init(void);
 extern int force_iommu, no_iommu;
 extern int iommu_pass_through;
 extern int iommu_detected;
-extern int iommu_group_mf;
 #else
 #define iommu_pass_through      (0)
 #define no_iommu                (1)
 #define iommu_detected          (0)
-#define iommu_group_mf          (0)
 #endif
 extern void iommu_dma_init(void);
 extern void machvec_init(const char *name);
diff --git a/arch/ia64/include/asm/kvm.h b/arch/ia64/include/asm/kvm.h
index b9f82c84f09..ec6c6b30123 100644
--- a/arch/ia64/include/asm/kvm.h
+++ b/arch/ia64/include/asm/kvm.h
@@ -26,6 +26,7 @@
 
 /* Select x86 specific features in <linux/kvm.h> */
 #define __KVM_HAVE_IOAPIC
+#define __KVM_HAVE_IRQ_LINE
 #define __KVM_HAVE_DEVICE_ASSIGNMENT
 
 /* Architectural interrupt line count. */
diff --git a/arch/ia64/include/asm/machvec.h b/arch/ia64/include/asm/machvec.h
index 367d299d993..2d1ad4b11a8 100644
--- a/arch/ia64/include/asm/machvec.h
+++ b/arch/ia64/include/asm/machvec.h
@@ -120,7 +120,7 @@ extern void machvec_tlb_migrate_finish (struct mm_struct *);
 # ifdef MACHVEC_PLATFORM_HEADER
 #  include MACHVEC_PLATFORM_HEADER
 # else
-#  define platform_name         ia64_mv.name
+#  define ia64_platform_name    ia64_mv.name
 #  define platform_setup        ia64_mv.setup
 #  define platform_cpu_init     ia64_mv.cpu_init
 #  define platform_irq_init     ia64_mv.irq_init
diff --git a/arch/ia64/include/asm/machvec_dig.h b/arch/ia64/include/asm/machvec_dig.h
index 8a0752f4098..1f7403a2fbe 100644
--- a/arch/ia64/include/asm/machvec_dig.h
+++ b/arch/ia64/include/asm/machvec_dig.h
@@ -10,7 +10,7 @@ extern ia64_mv_setup_t dig_setup;
  * platform's machvec structure.  When compiling a non-generic kernel,
  * the macros are used directly.
  */
-#define platform_name           "dig"
+#define ia64_platform_name      "dig"
 #define platform_setup          dig_setup
 
 #endif /* _ASM_IA64_MACHVEC_DIG_h */
diff --git a/arch/ia64/include/asm/machvec_dig_vtd.h b/arch/ia64/include/asm/machvec_dig_vtd.h
index 6ab1de5c45e..44308b4c3f6 100644
--- a/arch/ia64/include/asm/machvec_dig_vtd.h
+++ b/arch/ia64/include/asm/machvec_dig_vtd.h
@@ -11,7 +11,7 @@ extern ia64_mv_dma_init			pci_iommu_alloc;
  * platform's machvec structure.  When compiling a non-generic kernel,
  * the macros are used directly.
  */
-#define platform_name                           "dig_vtd"
+#define ia64_platform_name                      "dig_vtd"
 #define platform_setup                          dig_setup
 #define platform_dma_init                       pci_iommu_alloc
 
diff --git a/arch/ia64/include/asm/machvec_hpsim.h b/arch/ia64/include/asm/machvec_hpsim.h
index cf72fc87fdf..e7571127936 100644
--- a/arch/ia64/include/asm/machvec_hpsim.h
+++ b/arch/ia64/include/asm/machvec_hpsim.h
@@ -11,7 +11,7 @@ extern ia64_mv_irq_init_t hpsim_irq_init;
  * platform's machvec structure.  When compiling a non-generic kernel,
  * the macros are used directly.
  */
-#define platform_name           "hpsim"
+#define ia64_platform_name      "hpsim"
 #define platform_setup          hpsim_setup
 #define platform_irq_init       hpsim_irq_init
 
diff --git a/arch/ia64/include/asm/machvec_hpzx1.h b/arch/ia64/include/asm/machvec_hpzx1.h
index 3bd83d78a41..c74d3159e9e 100644
--- a/arch/ia64/include/asm/machvec_hpzx1.h
+++ b/arch/ia64/include/asm/machvec_hpzx1.h
@@ -11,7 +11,7 @@ extern ia64_mv_dma_init			sba_dma_init;
  * platform's machvec structure.  When compiling a non-generic kernel,
  * the macros are used directly.
  */
-#define platform_name                           "hpzx1"
+#define ia64_platform_name                      "hpzx1"
 #define platform_setup                          dig_setup
 #define platform_dma_init                       sba_dma_init
 
diff --git a/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h b/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h
index 1091ac39740..906ef621077 100644
--- a/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h
+++ b/arch/ia64/include/asm/machvec_hpzx1_swiotlb.h
@@ -11,7 +11,7 @@ extern ia64_mv_dma_get_ops			hwsw_dma_get_ops;
  * platform's machvec structure.  When compiling a non-generic kernel,
  * the macros are used directly.
  */
-#define platform_name                           "hpzx1_swiotlb"
+#define ia64_platform_name                      "hpzx1_swiotlb"
 #define platform_setup                          dig_setup
 #define platform_dma_init                       machvec_noop
 #define platform_dma_get_ops                    hwsw_dma_get_ops
diff --git a/arch/ia64/include/asm/machvec_sn2.h b/arch/ia64/include/asm/machvec_sn2.h
index f061a30aac4..ece9fa85be8 100644
--- a/arch/ia64/include/asm/machvec_sn2.h
+++ b/arch/ia64/include/asm/machvec_sn2.h
@@ -71,7 +71,7 @@ extern ia64_mv_pci_fixup_bus_t		sn_pci_fixup_bus;
  * platform's machvec structure.  When compiling a non-generic kernel,
  * the macros are used directly.
  */
-#define platform_name                   "sn2"
+#define ia64_platform_name              "sn2"
 #define platform_setup                  sn_setup
 #define platform_cpu_init               sn_cpu_init
 #define platform_irq_init               sn_irq_init
diff --git a/arch/ia64/include/asm/machvec_uv.h b/arch/ia64/include/asm/machvec_uv.h
index 2931447f381..2c50853f35a 100644
--- a/arch/ia64/include/asm/machvec_uv.h
+++ b/arch/ia64/include/asm/machvec_uv.h
@@ -20,7 +20,7 @@ extern ia64_mv_setup_t uv_setup;
  * platform's machvec structure.  When compiling a non-generic kernel,
  * the macros are used directly.
  */
-#define platform_name                   "uv"
+#define ia64_platform_name              "uv"
 #define platform_setup                  uv_setup
 
 #endif /* _ASM_IA64_MACHVEC_UV_H */
diff --git a/arch/ia64/include/asm/machvec_xen.h b/arch/ia64/include/asm/machvec_xen.h
index 55f9228056c..8b8bd0eb392 100644
--- a/arch/ia64/include/asm/machvec_xen.h
+++ b/arch/ia64/include/asm/machvec_xen.h
@@ -13,7 +13,7 @@ extern ia64_mv_send_ipi_t		xen_platform_send_ipi;
  * platform's machvec structure.  When compiling a non-generic kernel,
  * the macros are used directly.
  */
-#define platform_name                           "xen"
+#define ia64_platform_name                      "xen"
 #define platform_setup                          dig_setup
 #define platform_cpu_init                       xen_cpu_init
 #define platform_irq_init                       xen_irq_init
diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h
index 832dd3789e9..944152a5091 100644
--- a/arch/ia64/include/asm/processor.h
+++ b/arch/ia64/include/asm/processor.h
@@ -719,7 +719,7 @@ enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_FORCE_MWAIT,
 
 void default_idle(void);
 
-#define ia64_platform_is(x) (strcmp(x, platform_name) == 0)
+#define ia64_platform_is(x) (strcmp(x, ia64_platform_name) == 0)
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 6f38b6120d9..440578850ae 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -497,7 +497,7 @@ acpi_numa_processor_affinity_init(struct acpi_srat_cpu_affinity *pa)
         srat_num_cpus++;
 }
 
-void __init
+int __init
 acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
 {
         unsigned long paddr, size;
@@ -512,7 +512,7 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
 
         /* Ignore disabled entries */
         if (!(ma->flags & ACPI_SRAT_MEM_ENABLED))
-                return;
+                return -1;
 
         /* record this node in proximity bitmap */
         pxm_bit_set(pxm);
@@ -531,6 +531,7 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
         p->size = size;
         p->nid = pxm;
         num_node_memblks++;
+        return 0;
 }
 
 void __init acpi_numa_arch_fixup(void)
diff --git a/arch/ia64/kernel/ia64_ksyms.c b/arch/ia64/kernel/ia64_ksyms.c
index 7f4a0ed2415..5b7791dd396 100644
--- a/arch/ia64/kernel/ia64_ksyms.c
+++ b/arch/ia64/kernel/ia64_ksyms.c
@@ -12,7 +12,7 @@ EXPORT_SYMBOL(memset);
 EXPORT_SYMBOL(memcpy);
 EXPORT_SYMBOL(strlen);
 
-#include<asm/pgtable.h>
+#include <asm/pgtable.h>
 EXPORT_SYMBOL_GPL(empty_zero_page);
 
 #include <asm/checksum.h>
diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c
index 5c3e0888265..1034884b77d 100644
--- a/arch/ia64/kernel/irq_ia64.c
+++ b/arch/ia64/kernel/irq_ia64.c
@@ -23,7 +23,6 @@
 #include <linux/ioport.h>
 #include <linux/kernel_stat.h>
 #include <linux/ptrace.h>
-#include <linux/random.h>       /* for rand_initialize_irq() */
 #include <linux/signal.h>
 #include <linux/smp.h>
 #include <linux/threads.h>
diff --git a/arch/ia64/kernel/pci-dma.c b/arch/ia64/kernel/pci-dma.c
index 7cdc89b2483..1ddcfe5ef35 100644
--- a/arch/ia64/kernel/pci-dma.c
+++ b/arch/ia64/kernel/pci-dma.c
@@ -32,7 +32,6 @@ int force_iommu __read_mostly;
 #endif
 
 int iommu_pass_through;
-int iommu_group_mf;
 
 /* Dummy device used for NULL arguments (normally ISA). Better would
    be probably a smaller DMA mask, but this is bug-to-bug compatible
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index d7f558c1e71..3fa4bc53695 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -2353,7 +2353,6 @@ pfm_smpl_buffer_alloc(struct task_struct *task, struct file *filp, pfm_context_t
          */
         insert_vm_struct(mm, vma);
 
-        mm->total_vm  += size >> PAGE_SHIFT;
         vm_stat_account(vma->vm_mm, vma->vm_flags, vma->vm_file,
                                                         vma_pages(vma));
         up_write(&task->mm->mmap_sem);
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index 1113b8aba07..963d2db53bf 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -382,7 +382,6 @@ smp_callin (void)
         set_numa_node(cpu_to_node_map[cpuid]);
         set_numa_mem(local_memory_node(cpu_to_node_map[cpuid]));
 
-        ipi_call_lock_irq();
         spin_lock(&vector_lock);
         /* Setup the per cpu irq handling data structures */
         __setup_vector_irq(cpuid);
@@ -390,7 +389,6 @@ smp_callin (void)
         set_cpu_online(cpuid, true);
         per_cpu(cpu_state, cpuid) = CPU_ONLINE;
         spin_unlock(&vector_lock);
-        ipi_call_unlock_irq();
 
         smp_setup_percpu_timer();
 
diff --git a/arch/ia64/kvm/Kconfig b/arch/ia64/kvm/Kconfig
index 9806e55f91b..e7947528aee 100644
--- a/arch/ia64/kvm/Kconfig
+++ b/arch/ia64/kvm/Kconfig
@@ -19,9 +19,11 @@ if VIRTUALIZATION
 
 config KVM
         tristate "Kernel-based Virtual Machine (KVM) support"
+        depends on BROKEN
         depends on HAVE_KVM && MODULES && EXPERIMENTAL
         # for device assignment:
         depends on PCI
+        depends on BROKEN
         select PREEMPT_NOTIFIERS
         select ANON_INODES
         select HAVE_KVM_IRQCHIP
diff --git a/arch/ia64/kvm/vmm.c b/arch/ia64/kvm/vmm.c
index f0b9cac8241..176a12cd56d 100644
--- a/arch/ia64/kvm/vmm.c
+++ b/arch/ia64/kvm/vmm.c
@@ -20,9 +20,9 @@
  */
 
 
-#include<linux/kernel.h>
-#include<linux/module.h>
-#include<asm/fpswa.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/fpswa.h>
 
 #include "vcpu.h"
 
diff --git a/arch/ia64/mm/fault.c b/arch/ia64/mm/fault.c
index 02d29c2a132..8443daf4f51 100644
--- a/arch/ia64/mm/fault.c
+++ b/arch/ia64/mm/fault.c
@@ -72,6 +72,10 @@ mapped_kernel_page_is_present (unsigned long address)
         return pte_present(pte);
 }
 
+#       define VM_READ_BIT      0
+#       define VM_WRITE_BIT     1
+#       define VM_EXEC_BIT      2
+
 void __kprobes
 ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *regs)
 {
@@ -81,6 +85,12 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re
         struct siginfo si;
         unsigned long mask;
         int fault;
+        unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
+
+        mask = ((((isr >> IA64_ISR_X_BIT) & 1UL) << VM_EXEC_BIT)
+                | (((isr >> IA64_ISR_W_BIT) & 1UL) << VM_WRITE_BIT));
+
+        flags |= ((mask & VM_WRITE) ? FAULT_FLAG_WRITE : 0);
 
         /* mmap_sem is performance critical.... */
         prefetchw(&mm->mmap_sem);
@@ -109,6 +119,7 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re
         if (notify_page_fault(regs, TRAP_BRKPT))
                 return;
 
+retry:
         down_read(&mm->mmap_sem);
 
         vma = find_vma_prev(mm, address, &prev_vma);
@@ -130,10 +141,6 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re
 
         /* OK, we've got a good vm_area for this memory area.  Check the access permissions: */
 
-#       define VM_READ_BIT      0
-#       define VM_WRITE_BIT     1
-#       define VM_EXEC_BIT      2
-
 #       if (((1 << VM_READ_BIT) != VM_READ || (1 << VM_WRITE_BIT) != VM_WRITE) \
             || (1 << VM_EXEC_BIT) != VM_EXEC)
 #               error File is out of sync with <linux/mm.h>.  Please update.
@@ -142,9 +149,6 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re
         if (((isr >> IA64_ISR_R_BIT) & 1UL) && (!(vma->vm_flags & (VM_READ | VM_WRITE))))
                 goto bad_area;
 
-        mask = (  (((isr >> IA64_ISR_X_BIT) & 1UL) << VM_EXEC_BIT)
-                | (((isr >> IA64_ISR_W_BIT) & 1UL) << VM_WRITE_BIT));
-
         if ((vma->vm_flags & mask) != mask)
                 goto bad_area;
 
@@ -153,7 +157,11 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re
          * sure we exit gracefully rather than endlessly redo the
          * fault.
          */
-        fault = handle_mm_fault(mm, vma, address, (mask & VM_WRITE) ? FAULT_FLAG_WRITE : 0);
+        fault = handle_mm_fault(mm, vma, address, flags);
+
+        if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
+                return;
+
         if (unlikely(fault & VM_FAULT_ERROR)) {
                 /*
                  * We ran out of memory, or some other thing happened
@@ -168,10 +176,24 @@ ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *re
                 }
                 BUG();
         }
-        if (fault & VM_FAULT_MAJOR)
-                current->maj_flt++;
-        else
-                current->min_flt++;
+
+        if (flags & FAULT_FLAG_ALLOW_RETRY) {
+                if (fault & VM_FAULT_MAJOR)
+                        current->maj_flt++;
+                else
+                        current->min_flt++;
+                if (fault & VM_FAULT_RETRY) {
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+
+                         /* No need to up_read(&mm->mmap_sem) as we would
+                         * have already released it in __lock_page_or_retry
+                         * in mm/filemap.c.
+                         */
+
+                        goto retry;
+                }
+        }
+
         up_read(&mm->mmap_sem);
         return;
 
diff --git a/arch/ia64/pci/fixup.c b/arch/ia64/pci/fixup.c
index f5959c0c181..eab28e31402 100644
--- a/arch/ia64/pci/fixup.c
+++ b/arch/ia64/pci/fixup.c
@@ -30,8 +30,8 @@ static void __devinit pci_fixup_video(struct pci_dev *pdev)
         struct pci_bus *bus;
         u16 config;
 
-        if ((strcmp(platform_name, "dig") != 0)
-            && (strcmp(platform_name, "hpzx1")  != 0))
+        if ((strcmp(ia64_platform_name, "dig") != 0)
+            && (strcmp(ia64_platform_name, "hpzx1")  != 0))
                 return;
         /* Maybe, this machine supports legacy memory map. */
 
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index 524df4295c9..81acc7a57f3 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -351,6 +351,8 @@ pci_acpi_scan_root(struct acpi_pci_root *root)
 #endif
 
         INIT_LIST_HEAD(&info.resources);
+        /* insert busn resource at first */
+        pci_add_resource(&info.resources, &root->secondary);
         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
                         &windows);
         if (windows) {
@@ -384,7 +386,7 @@ pci_acpi_scan_root(struct acpi_pci_root *root)
                 return NULL;
         }
 
-        pbus->subordinate = pci_scan_child_bus(pbus);
+        pci_scan_child_bus(pbus);
         return pbus;
 
 out3:
@@ -496,15 +498,6 @@ pcibios_align_resource (void *data, const struct resource *res,
         return res->start;
 }
 
-/*
- * PCI BIOS setup, always defaults to SAL interface
- */
-char * __init
-pcibios_setup (char *str)
-{
-        return str;
-}
-
 int
 pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
                      enum pci_mmap_state mmap_state, int write_combine)
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index b638d5bfa14..49498bbb961 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -7,6 +7,7 @@ config M32R
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_BZIP2
         select HAVE_KERNEL_LZMA
+        select ARCH_WANT_IPC_PARSE_VERSION
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_PROBE
         select GENERIC_IRQ_SHOW
diff --git a/arch/m32r/include/asm/smp.h b/arch/m32r/include/asm/smp.h
index cf7829a6155..c689b828dfe 100644
--- a/arch/m32r/include/asm/smp.h
+++ b/arch/m32r/include/asm/smp.h
@@ -79,11 +79,6 @@ static __inline__ int cpu_number_map(int cpu)
         return cpu;
 }
 
-static __inline__ unsigned int num_booting_cpus(void)
-{
-        return cpumask_weight(&cpu_callout_map);
-}
-
 extern void smp_send_timer(void);
 extern unsigned long send_IPI_mask_phys(const cpumask_t*, int, int);
 
diff --git a/arch/m32r/include/asm/unistd.h b/arch/m32r/include/asm/unistd.h
index 3e1db561aac..d5e66a48078 100644
--- a/arch/m32r/include/asm/unistd.h
+++ b/arch/m32r/include/asm/unistd.h
@@ -336,7 +336,6 @@
 
 #define NR_syscalls 326
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_ALARM
 #define __ARCH_WANT_SYS_GETHOSTNAME
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 14712012826..b22df9410dc 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -5,11 +5,13 @@ config M68K
         select HAVE_AOUT if MMU
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_SHOW
+        select GENERIC_ATOMIC64
         select ARCH_HAVE_NMI_SAFE_CMPXCHG if RMW_INSNS
         select GENERIC_CPU_DEVICES
         select GENERIC_STRNCPY_FROM_USER if MMU
         select GENERIC_STRNLEN_USER if MMU
         select FPU if MMU
+        select ARCH_WANT_IPC_PARSE_VERSION
         select ARCH_USES_GETTIMEOFFSET if MMU && !COLDFIRE
 
 config RWSEM_GENERIC_SPINLOCK
@@ -53,18 +55,6 @@ config ZONE_DMA
         bool
         default y
 
-config CPU_HAS_NO_BITFIELDS
-        bool
-
-config CPU_HAS_NO_MULDIV64
-        bool
-
-config CPU_HAS_ADDRESS_SPACES
-        bool
-
-config FPU
-        bool
-
 config HZ
         int
         default 1000 if CLEOPATRA
diff --git a/arch/m68k/Kconfig.bus b/arch/m68k/Kconfig.bus
index 3adb499584f..ffc0601a2a1 100644
--- a/arch/m68k/Kconfig.bus
+++ b/arch/m68k/Kconfig.bus
@@ -48,6 +48,13 @@ config ISA
 config GENERIC_ISA_DMA
         def_bool ISA
 
+config PCI
+        bool "PCI support"
+        depends on M54xx
+        help
+          Enable the PCI bus. Support for the PCI bus hardware built into the
+          ColdFire 547x and 548x processors.
+
 source "drivers/pci/Kconfig"
 
 source "drivers/zorro/Kconfig"
diff --git a/arch/m68k/Kconfig.cpu b/arch/m68k/Kconfig.cpu
index 2b53254ad99..c4eb79edece 100644
--- a/arch/m68k/Kconfig.cpu
+++ b/arch/m68k/Kconfig.cpu
@@ -23,11 +23,12 @@ config M68KCLASSIC
 config COLDFIRE
         bool "Coldfire CPU family support"
         select GENERIC_GPIO
-        select ARCH_REQUIRE_GPIOLIB
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         select ARCH_HAVE_CUSTOM_GPIO_H
         select CPU_HAS_NO_BITFIELDS
         select CPU_HAS_NO_MULDIV64
         select GENERIC_CSUM
+        select HAVE_CLK
 
 endchoice
 
@@ -37,6 +38,7 @@ config M68000
         bool
         select CPU_HAS_NO_BITFIELDS
         select CPU_HAS_NO_MULDIV64
+        select CPU_HAS_NO_UNALIGNED
         select GENERIC_CSUM
         help
           The Freescale (was Motorola) 68000 CPU is the first generation of
@@ -48,6 +50,7 @@ config M68000
 config MCPU32
         bool
         select CPU_HAS_NO_BITFIELDS
+        select CPU_HAS_NO_UNALIGNED
         help
           The Freescale (was then Motorola) CPU32 is a CPU core that is
           based on the 68020 processor. For the most part it is used in
@@ -56,7 +59,6 @@ config MCPU32
 config M68020
         bool "68020 support"
         depends on MMU
-        select GENERIC_ATOMIC64
         select CPU_HAS_ADDRESS_SPACES
         help
           If you anticipate running this kernel on a computer with a MC68020
@@ -67,7 +69,6 @@ config M68020
 config M68030
         bool "68030 support"
         depends on MMU && !MMU_SUN3
-        select GENERIC_ATOMIC64
         select CPU_HAS_ADDRESS_SPACES
         help
           If you anticipate running this kernel on a computer with a MC68030
@@ -77,7 +78,6 @@ config M68030
 config M68040
         bool "68040 support"
         depends on MMU && !MMU_SUN3
-        select GENERIC_ATOMIC64
         select CPU_HAS_ADDRESS_SPACES
         help
           If you anticipate running this kernel on a computer with a MC68LC040
@@ -88,7 +88,6 @@ config M68040
 config M68060
         bool "68060 support"
         depends on MMU && !MMU_SUN3
-        select GENERIC_ATOMIC64
         select CPU_HAS_ADDRESS_SPACES
         help
           If you anticipate running this kernel on a computer with a MC68060
@@ -167,6 +166,14 @@ config M5249
         help
           Motorola ColdFire 5249 processor support.
 
+config M525x
+        bool "MCF525x"
+        depends on !MMU
+        select COLDFIRE_SW_A7
+        select HAVE_MBAR
+        help
+          Freescale (Motorola) Coldfire 5251/5253 processor support.
+
 config M527x
         bool
 
@@ -253,6 +260,14 @@ config M548x
         help
           Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
 
+config M5441x
+        bool "MCF5441x"
+        depends on !MMU
+        select GENERIC_CLOCKEVENTS
+        select HAVE_CACHE_CB
+        help
+          Freescale Coldfire 54410/54415/54416/54417/54418 processor support.
+
 endif # COLDFIRE
 
 
@@ -360,6 +375,18 @@ config NODES_SHIFT
         default "3"
         depends on !SINGLE_MEMORY_CHUNK
 
+config CPU_HAS_NO_BITFIELDS
+        bool
+
+config CPU_HAS_NO_MULDIV64
+        bool
+
+config CPU_HAS_NO_UNALIGNED
+        bool
+
+config CPU_HAS_ADDRESS_SPACES
+        bool
+
 config FPU
         bool
 
diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile
index b7f2e2d5cd2..7636751f2f8 100644
--- a/arch/m68k/Makefile
+++ b/arch/m68k/Makefile
@@ -41,6 +41,7 @@ cpuflags-$(CONFIG_M68030)	:=
 cpuflags-$(CONFIG_M68020)       :=
 cpuflags-$(CONFIG_M68360)       := -m68332
 cpuflags-$(CONFIG_M68000)       := -m68000
+cpuflags-$(CONFIG_M5441x)       := $(call cc-option,-mcpu=54455,-mcfv4e)
 cpuflags-$(CONFIG_M54xx)        := $(call cc-option,-mcpu=5475,-m5200)
 cpuflags-$(CONFIG_M5407)        := $(call cc-option,-mcpu=5407,-m5200)
 cpuflags-$(CONFIG_M532x)        := $(call cc-option,-mcpu=532x,-m5307)
@@ -50,6 +51,7 @@ cpuflags-$(CONFIG_M5275)	:= $(call cc-option,-mcpu=5275,-m5307)
 cpuflags-$(CONFIG_M5272)        := $(call cc-option,-mcpu=5272,-m5307)
 cpuflags-$(CONFIG_M5271)        := $(call cc-option,-mcpu=5271,-m5307)
 cpuflags-$(CONFIG_M523x)        := $(call cc-option,-mcpu=523x,-m5307)
+cpuflags-$(CONFIG_M525x)        := $(call cc-option,-mcpu=5253,-m5200)
 cpuflags-$(CONFIG_M5249)        := $(call cc-option,-mcpu=5249,-m5200)
 cpuflags-$(CONFIG_M520x)        := $(call cc-option,-mcpu=5208,-m5200)
 cpuflags-$(CONFIG_M5206e)       := $(call cc-option,-mcpu=5206e,-m5200)
diff --git a/arch/m68k/apollo/config.c b/arch/m68k/apollo/config.c
index 0a30406b944..f5565d6eeb8 100644
--- a/arch/m68k/apollo/config.c
+++ b/arch/m68k/apollo/config.c
@@ -177,8 +177,8 @@ irqreturn_t dn_timer_int(int irq, void *dev_id)
 
         timer_handler(irq, dev_id);
 
-        x=*(volatile unsigned char *)(timer+3);
-        x=*(volatile unsigned char *)(timer+5);
+        x = *(volatile unsigned char *)(apollo_timer + 3);
+        x = *(volatile unsigned char *)(apollo_timer + 5);
 
         return IRQ_HANDLED;
 }
@@ -186,17 +186,17 @@ irqreturn_t dn_timer_int(int irq, void *dev_id)
 void dn_sched_init(irq_handler_t timer_routine)
 {
         /* program timer 1 */
-        *(volatile unsigned char *)(timer+3)=0x01;
-        *(volatile unsigned char *)(timer+1)=0x40;
-        *(volatile unsigned char *)(timer+5)=0x09;
-        *(volatile unsigned char *)(timer+7)=0xc4;
+        *(volatile unsigned char *)(apollo_timer + 3) = 0x01;
+        *(volatile unsigned char *)(apollo_timer + 1) = 0x40;
+        *(volatile unsigned char *)(apollo_timer + 5) = 0x09;
+        *(volatile unsigned char *)(apollo_timer + 7) = 0xc4;
 
         /* enable IRQ of PIC B */
         *(volatile unsigned char *)(pica+1)&=(~8);
 
 #if 0
-        printk("*(0x10803) %02x\n",*(volatile unsigned char *)(timer+0x3));
-        printk("*(0x10803) %02x\n",*(volatile unsigned char *)(timer+0x3));
+        printk("*(0x10803) %02x\n",*(volatile unsigned char *)(apollo_timer + 0x3));
+        printk("*(0x10803) %02x\n",*(volatile unsigned char *)(apollo_timer + 0x3));
 #endif
 
         if (request_irq(IRQ_APOLLO, dn_timer_int, 0, "time", timer_routine))
diff --git a/arch/m68k/include/asm/Kbuild b/arch/m68k/include/asm/Kbuild
index eafa2539a8e..a74e5d95c38 100644
--- a/arch/m68k/include/asm/Kbuild
+++ b/arch/m68k/include/asm/Kbuild
@@ -1,4 +1,29 @@
 include include/asm-generic/Kbuild.asm
 header-y += cachectl.h
 
+generic-y += bitsperlong.h
+generic-y += cputime.h
+generic-y += device.h
+generic-y += emergency-restart.h
+generic-y += errno.h
+generic-y += futex.h
+generic-y += ioctl.h
+generic-y += ipcbuf.h
+generic-y += irq_regs.h
+generic-y += kdebug.h
+generic-y += kmap_types.h
+generic-y += kvm_para.h
+generic-y += local64.h
+generic-y += local.h
+generic-y += mman.h
+generic-y += mutex.h
+generic-y += percpu.h
+generic-y += resource.h
+generic-y += scatterlist.h
+generic-y += sections.h
+generic-y += siginfo.h
+generic-y += statfs.h
+generic-y += topology.h
+generic-y += types.h
 generic-y += word-at-a-time.h
+generic-y += xor.h
diff --git a/arch/m68k/include/asm/MC68332.h b/arch/m68k/include/asm/MC68332.h
deleted file mode 100644
index 6bb8f02685a..00000000000
--- a/arch/m68k/include/asm/MC68332.h
+++ /dev/null
@@ -1,152 +0,0 @@
-
-/* include/asm-m68knommu/MC68332.h: '332 control registers
- *
- * Copyright (C) 1998  Kenneth Albanowski <kjahds@kjahds.com>,
- *
- */
-
-#ifndef _MC68332_H_
-#define _MC68332_H_
-
-#define BYTE_REF(addr) (*((volatile unsigned char*)addr))
-#define WORD_REF(addr) (*((volatile unsigned short*)addr))
-
-#define PORTE_ADDR      0xfffa11
-#define PORTE   BYTE_REF(PORTE_ADDR)
-#define DDRE_ADDR       0xfffa15
-#define DDRE    BYTE_REF(DDRE_ADDR)
-#define PEPAR_ADDR      0xfffa17
-#define PEPAR   BYTE_REF(PEPAR_ADDR)
-
-#define PORTF_ADDR      0xfffa19
-#define PORTF   BYTE_REF(PORTF_ADDR)
-#define DDRF_ADDR       0xfffa1d
-#define DDRF    BYTE_REF(DDRF_ADDR)
-#define PFPAR_ADDR      0xfffa1f
-#define PFPAR   BYTE_REF(PFPAR_ADDR)
-
-#define PORTQS_ADDR     0xfffc15
-#define PORTQS  BYTE_REF(PORTQS_ADDR)
-#define DDRQS_ADDR      0xfffc17
-#define DDRQS   BYTE_REF(DDRQS_ADDR)
-#define PQSPAR_ADDR     0xfffc16
-#define PQSPAR  BYTE_REF(PQSPAR_ADDR)
-
-#define CSPAR0_ADDR 0xFFFA44
-#define CSPAR0 WORD_REF(CSPAR0_ADDR)
-#define CSPAR1_ADDR 0xFFFA46
-#define CSPAR1 WORD_REF(CSPAR1_ADDR)
-#define CSARBT_ADDR 0xFFFA48
-#define CSARBT WORD_REF(CSARBT_ADDR)
-#define CSOPBT_ADDR 0xFFFA4A
-#define CSOPBT WORD_REF(CSOPBT_ADDR)
-#define CSBAR0_ADDR 0xFFFA4C
-#define CSBAR0 WORD_REF(CSBAR0_ADDR)
-#define CSOR0_ADDR 0xFFFA4E
-#define CSOR0 WORD_REF(CSOR0_ADDR)
-#define CSBAR1_ADDR 0xFFFA50
-#define CSBAR1 WORD_REF(CSBAR1_ADDR)
-#define CSOR1_ADDR 0xFFFA52
-#define CSOR1 WORD_REF(CSOR1_ADDR)
-#define CSBAR2_ADDR 0xFFFA54
-#define CSBAR2 WORD_REF(CSBAR2_ADDR)
-#define CSOR2_ADDR 0xFFFA56
-#define CSOR2 WORD_REF(CSOR2_ADDR)
-#define CSBAR3_ADDR 0xFFFA58
-#define CSBAR3 WORD_REF(CSBAR3_ADDR)
-#define CSOR3_ADDR 0xFFFA5A
-#define CSOR3 WORD_REF(CSOR3_ADDR)
-#define CSBAR4_ADDR 0xFFFA5C
-#define CSBAR4 WORD_REF(CSBAR4_ADDR)
-#define CSOR4_ADDR 0xFFFA5E
-#define CSOR4 WORD_REF(CSOR4_ADDR)
-#define CSBAR5_ADDR 0xFFFA60
-#define CSBAR5 WORD_REF(CSBAR5_ADDR)
-#define CSOR5_ADDR 0xFFFA62
-#define CSOR5 WORD_REF(CSOR5_ADDR)
-#define CSBAR6_ADDR 0xFFFA64
-#define CSBAR6 WORD_REF(CSBAR6_ADDR)
-#define CSOR6_ADDR 0xFFFA66
-#define CSOR6 WORD_REF(CSOR6_ADDR)
-#define CSBAR7_ADDR 0xFFFA68
-#define CSBAR7 WORD_REF(CSBAR7_ADDR)
-#define CSOR7_ADDR 0xFFFA6A
-#define CSOR7 WORD_REF(CSOR7_ADDR)
-#define CSBAR8_ADDR 0xFFFA6C
-#define CSBAR8 WORD_REF(CSBAR8_ADDR)
-#define CSOR8_ADDR 0xFFFA6E
-#define CSOR8 WORD_REF(CSOR8_ADDR)
-#define CSBAR9_ADDR 0xFFFA70
-#define CSBAR9 WORD_REF(CSBAR9_ADDR)
-#define CSOR9_ADDR 0xFFFA72
-#define CSOR9 WORD_REF(CSOR9_ADDR)
-#define CSBAR10_ADDR 0xFFFA74
-#define CSBAR10 WORD_REF(CSBAR10_ADDR)
-#define CSOR10_ADDR 0xFFFA76
-#define CSOR10 WORD_REF(CSOR10_ADDR)
-
-#define CSOR_MODE_ASYNC 0x0000
-#define CSOR_MODE_SYNC  0x8000
-#define CSOR_MODE_MASK  0x8000
-#define CSOR_BYTE_DISABLE       0x0000
-#define CSOR_BYTE_UPPER         0x4000
-#define CSOR_BYTE_LOWER         0x2000
-#define CSOR_BYTE_BOTH          0x6000
-#define CSOR_BYTE_MASK          0x6000
-#define CSOR_RW_RSVD            0x0000
-#define CSOR_RW_READ            0x0800
-#define CSOR_RW_WRITE           0x1000
-#define CSOR_RW_BOTH            0x1800
-#define CSOR_RW_MASK            0x1800
-#define CSOR_STROBE_DS          0x0400
-#define CSOR_STROBE_AS          0x0000
-#define CSOR_STROBE_MASK        0x0400
-#define CSOR_DSACK_WAIT(x)      (wait << 6)
-#define CSOR_DSACK_FTERM        (14 << 6)
-#define CSOR_DSACK_EXTERNAL     (15 << 6)
-#define CSOR_DSACK_MASK         0x03c0
-#define CSOR_SPACE_CPU          0x0000
-#define CSOR_SPACE_USER         0x0010
-#define CSOR_SPACE_SU           0x0020
-#define CSOR_SPACE_BOTH         0x0030
-#define CSOR_SPACE_MASK         0x0030
-#define CSOR_IPL_ALL            0x0000
-#define CSOR_IPL_PRIORITY(x)    (x << 1)
-#define CSOR_IPL_MASK           0x000e
-#define CSOR_AVEC_ON            0x0001
-#define CSOR_AVEC_OFF           0x0000
-#define CSOR_AVEC_MASK          0x0001
-
-#define CSBAR_ADDR(x)           ((addr >> 11) << 3) 
-#define CSBAR_ADDR_MASK         0xfff8
-#define CSBAR_BLKSIZE_2K        0x0000
-#define CSBAR_BLKSIZE_8K        0x0001
-#define CSBAR_BLKSIZE_16K       0x0002
-#define CSBAR_BLKSIZE_64K       0x0003
-#define CSBAR_BLKSIZE_128K      0x0004
-#define CSBAR_BLKSIZE_256K      0x0005
-#define CSBAR_BLKSIZE_512K      0x0006
-#define CSBAR_BLKSIZE_1M        0x0007
-#define CSBAR_BLKSIZE_MASK      0x0007
-
-#define CSPAR_DISC      0
-#define CSPAR_ALT       1
-#define CSPAR_CS8       2
-#define CSPAR_CS16      3
-#define CSPAR_MASK      3
-
-#define CSPAR0_CSBOOT(x) (x << 0)
-#define CSPAR0_CS0(x)   (x << 2)
-#define CSPAR0_CS1(x)   (x << 4)
-#define CSPAR0_CS2(x)   (x << 6)
-#define CSPAR0_CS3(x)   (x << 8)
-#define CSPAR0_CS4(x)   (x << 10)
-#define CSPAR0_CS5(x)   (x << 12)
-
-#define CSPAR1_CS6(x)   (x << 0)
-#define CSPAR1_CS7(x)   (x << 2)
-#define CSPAR1_CS8(x)   (x << 4)
-#define CSPAR1_CS9(x)   (x << 6)
-#define CSPAR1_CS10(x)  (x << 8)
-
-#endif
diff --git a/arch/m68k/include/asm/apollodma.h b/arch/m68k/include/asm/apollodma.h
deleted file mode 100644
index 954adc851ad..00000000000
--- a/arch/m68k/include/asm/apollodma.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- */
-
-#ifndef _ASM_APOLLO_DMA_H
-#define _ASM_APOLLO_DMA_H
-
-#include <asm/apollohw.h>               /* need byte IO */
-#include <linux/spinlock.h>             /* And spinlocks */
-#include <linux/delay.h>
-
-
-#define dma_outb(val,addr) (*((volatile unsigned char *)(addr+IO_BASE)) = (val))
-#define dma_inb(addr)      (*((volatile unsigned char *)(addr+IO_BASE)))
-
-/*
- * NOTES about DMA transfers:
- *
- *  controller 1: channels 0-3, byte operations, ports 00-1F
- *  controller 2: channels 4-7, word operations, ports C0-DF
- *
- *  - ALL registers are 8 bits only, regardless of transfer size
- *  - channel 4 is not used - cascades 1 into 2.
- *  - channels 0-3 are byte - addresses/counts are for physical bytes
- *  - channels 5-7 are word - addresses/counts are for physical words
- *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- *  - transfer count loaded to registers is 1 less than actual count
- *  - controller 2 offsets are all even (2x offsets for controller 1)
- *  - page registers for 5-7 don't use data bit 0, represent 128K pages
- *  - page registers for 0-3 use bit 0, represent 64K pages
- *
- * DMA transfers are limited to the lower 16MB of _physical_ memory.
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- *  Address mapping for channels 0-3:
- *
- *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *   P7  ...  P0  A7 ... A0  A7 ... A0
- * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
- *
- *  Address mapping for channels 5-7:
- *
- *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
- *    |  ...  |   \   \   ... \  \  \  ... \  \
- *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
- *    |  ...  |     \   \   ... \  \  \  ... \
- *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
- * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
- * the hardware level, so odd-byte transfers aren't possible).
- *
- * Transfer count (_not # bytes_) is limited to 64K, represented as actual
- * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation.
- *
- */
-
-#define MAX_DMA_CHANNELS        8
-
-/* The maximum address that we can perform a DMA transfer to on this platform */#define MAX_DMA_ADDRESS      (PAGE_OFFSET+0x1000000)
-
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE    0x10C00 /* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE    0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */
-
-/* DMA controller registers */
-#define DMA1_CMD_REG            (IO_DMA1_BASE+0x08) /* command register (w) */
-#define DMA1_STAT_REG           (IO_DMA1_BASE+0x08) /* status register (r) */
-#define DMA1_REQ_REG            (IO_DMA1_BASE+0x09) /* request register (w) */
-#define DMA1_MASK_REG           (IO_DMA1_BASE+0x0A) /* single-channel mask (w) */
-#define DMA1_MODE_REG           (IO_DMA1_BASE+0x0B) /* mode register (w) */
-#define DMA1_CLEAR_FF_REG       (IO_DMA1_BASE+0x0C) /* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG           (IO_DMA1_BASE+0x0D) /* Temporary Register (r) */
-#define DMA1_RESET_REG          (IO_DMA1_BASE+0x0D) /* Master Clear (w) */
-#define DMA1_CLR_MASK_REG       (IO_DMA1_BASE+0x0E) /* Clear Mask */
-#define DMA1_MASK_ALL_REG       (IO_DMA1_BASE+0x0F) /* all-channels mask (w) */
-
-#define DMA2_CMD_REG            (IO_DMA2_BASE+0x10) /* command register (w) */
-#define DMA2_STAT_REG           (IO_DMA2_BASE+0x10) /* status register (r) */
-#define DMA2_REQ_REG            (IO_DMA2_BASE+0x12) /* request register (w) */
-#define DMA2_MASK_REG           (IO_DMA2_BASE+0x14) /* single-channel mask (w) */
-#define DMA2_MODE_REG           (IO_DMA2_BASE+0x16) /* mode register (w) */
-#define DMA2_CLEAR_FF_REG       (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG           (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */
-#define DMA2_RESET_REG          (IO_DMA2_BASE+0x1A) /* Master Clear (w) */
-#define DMA2_CLR_MASK_REG       (IO_DMA2_BASE+0x1C) /* Clear Mask */
-#define DMA2_MASK_ALL_REG       (IO_DMA2_BASE+0x1E) /* all-channels mask (w) */
-
-#define DMA_ADDR_0              (IO_DMA1_BASE+0x00) /* DMA address registers */
-#define DMA_ADDR_1              (IO_DMA1_BASE+0x02)
-#define DMA_ADDR_2              (IO_DMA1_BASE+0x04)
-#define DMA_ADDR_3              (IO_DMA1_BASE+0x06)
-#define DMA_ADDR_4              (IO_DMA2_BASE+0x00)
-#define DMA_ADDR_5              (IO_DMA2_BASE+0x04)
-#define DMA_ADDR_6              (IO_DMA2_BASE+0x08)
-#define DMA_ADDR_7              (IO_DMA2_BASE+0x0C)
-
-#define DMA_CNT_0               (IO_DMA1_BASE+0x01)   /* DMA count registers */
-#define DMA_CNT_1               (IO_DMA1_BASE+0x03)
-#define DMA_CNT_2               (IO_DMA1_BASE+0x05)
-#define DMA_CNT_3               (IO_DMA1_BASE+0x07)
-#define DMA_CNT_4               (IO_DMA2_BASE+0x02)
-#define DMA_CNT_5               (IO_DMA2_BASE+0x06)
-#define DMA_CNT_6               (IO_DMA2_BASE+0x0A)
-#define DMA_CNT_7               (IO_DMA2_BASE+0x0E)
-
-#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
-#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
-#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
-
-#define DMA_AUTOINIT    0x10
-
-#define DMA_8BIT 0
-#define DMA_16BIT 1
-#define DMA_BUSMASTER 2
-
-extern spinlock_t  dma_spin_lock;
-
-static __inline__ unsigned long claim_dma_lock(void)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&dma_spin_lock, flags);
-        return flags;
-}
-
-static __inline__ void release_dma_lock(unsigned long flags)
-{
-        spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(dmanr,  DMA1_MASK_REG);
-        else
-                dma_outb(dmanr & 3,  DMA2_MASK_REG);
-}
-
-static __inline__ void disable_dma(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(dmanr | 4,  DMA1_MASK_REG);
-        else
-                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
-}
-
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while holding the DMA lock ! ---
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(0,  DMA1_CLEAR_FF_REG);
-        else
-                dma_outb(0,  DMA2_CLEAR_FF_REG);
-}
-
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
-        if (dmanr<=3)
-                dma_outb(mode | dmanr,  DMA1_MODE_REG);
-        else
-                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
-}
-
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
-        if (dmanr <= 3)  {
-            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-        }  else  {
-            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-        }
-}
-
-
-/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-        count--;
-        if (dmanr <= 3)  {
-            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-        } else {
-            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-        }
-}
-
-
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
-        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
-                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
-
-        /* using short to get 16-bit wrap around */
-        unsigned short count;
-
-        count = 1 + dma_inb(io_port);
-        count += dma_inb(io_port) << 8;
-
-        return (dmanr<=3)? count : (count<<1);
-}
-
-
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
-extern void free_dma(unsigned int dmanr);       /* release it again */
-
-/* These are in arch/m68k/apollo/dma.c: */
-extern unsigned short dma_map_page(unsigned long phys_addr,int count,int type);
-extern void dma_unmap_page(unsigned short dma_addr);
-
-#endif /* _ASM_APOLLO_DMA_H */
diff --git a/arch/m68k/include/asm/apollohw.h b/arch/m68k/include/asm/apollohw.h
index a1373b9aa28..635ef4f8901 100644
--- a/arch/m68k/include/asm/apollohw.h
+++ b/arch/m68k/include/asm/apollohw.h
@@ -98,7 +98,7 @@ extern u_long timer_physaddr;
 #define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr))
 #define pica (IO_BASE + pica_physaddr)
 #define picb (IO_BASE + picb_physaddr)
-#define timer (IO_BASE + timer_physaddr)
+#define apollo_timer (IO_BASE + timer_physaddr)
 #define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000))
 
 #define isaIO2mem(x) (((((x) & 0x3f8)  << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE)
diff --git a/arch/m68k/include/asm/bitsperlong.h b/arch/m68k/include/asm/bitsperlong.h
deleted file mode 100644
index 6dc0bb0c13b..00000000000
--- a/arch/m68k/include/asm/bitsperlong.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/bitsperlong.h>
diff --git a/arch/m68k/include/asm/cacheflush_mm.h b/arch/m68k/include/asm/cacheflush_mm.h
index 8104bd87464..fa2c3d681d8 100644
--- a/arch/m68k/include/asm/cacheflush_mm.h
+++ b/arch/m68k/include/asm/cacheflush_mm.h
@@ -16,7 +16,48 @@
 #define DCACHE_MAX_ADDR 0
 #define DCACHE_SETMASK  0
 #endif
+#ifndef CACHE_MODE
+#define CACHE_MODE      0
+#define CACR_ICINVA     0
+#define CACR_DCINVA     0
+#define CACR_BCINVA     0
+#endif
+
+/*
+ * ColdFire architecture has no way to clear individual cache lines, so we
+ * are stuck invalidating all the cache entries when we want a clear operation.
+ */
+static inline void clear_cf_icache(unsigned long start, unsigned long end)
+{
+        __asm__ __volatile__ (
+                "movec  %0,%%cacr\n\t"
+                "nop"
+                :
+                : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA));
+}
+
+static inline void clear_cf_dcache(unsigned long start, unsigned long end)
+{
+        __asm__ __volatile__ (
+                "movec  %0,%%cacr\n\t"
+                "nop"
+                :
+                : "r" (CACHE_MODE | CACR_DCINVA));
+}
 
+static inline void clear_cf_bcache(unsigned long start, unsigned long end)
+{
+        __asm__ __volatile__ (
+                "movec  %0,%%cacr\n\t"
+                "nop"
+                :
+                : "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA | CACR_DCINVA));
+}
+
+/*
+ * Use the ColdFire cpushl instruction to push (and invalidate) cache lines.
+ * The start and end addresses are cache line numbers not memory addresses.
+ */
 static inline void flush_cf_icache(unsigned long start, unsigned long end)
 {
         unsigned long set;
diff --git a/arch/m68k/include/asm/cputime.h b/arch/m68k/include/asm/cputime.h
deleted file mode 100644
index c79c5e89230..00000000000
--- a/arch/m68k/include/asm/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __M68K_CPUTIME_H
-#define __M68K_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __M68K_CPUTIME_H */
diff --git a/arch/m68k/include/asm/delay.h b/arch/m68k/include/asm/delay.h
index 9c09becfd4c..12d8fe4f1d3 100644
--- a/arch/m68k/include/asm/delay.h
+++ b/arch/m68k/include/asm/delay.h
@@ -43,7 +43,7 @@ static inline void __delay(unsigned long loops)
 extern void __bad_udelay(void);
 
 
-#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)
+#ifdef CONFIG_CPU_HAS_NO_MULDIV64
 /*
  * The simpler m68k and ColdFire processors do not have a 32*32->64
  * multiply instruction. So we need to handle them a little differently.
diff --git a/arch/m68k/include/asm/device.h b/arch/m68k/include/asm/device.h
deleted file mode 100644
index d8f9872b0e2..00000000000
--- a/arch/m68k/include/asm/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h
index 6fbdfe89510..0ff3fc6a6d9 100644
--- a/arch/m68k/include/asm/dma.h
+++ b/arch/m68k/include/asm/dma.h
@@ -33,7 +33,9 @@
  * Set number of channels of DMA on ColdFire for different implementations.
  */
 #if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
-        defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
+        defined(CONFIG_M523x) || defined(CONFIG_M527x) || \
+        defined(CONFIG_M528x) || defined(CONFIG_M525x)
+
 #define MAX_M68K_DMA_CHANNELS 4
 #elif defined(CONFIG_M5272)
 #define MAX_M68K_DMA_CHANNELS 1
@@ -486,6 +488,10 @@ static __inline__ int get_dma_residue(unsigned int dmanr)
 extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 extern void free_dma(unsigned int dmanr);       /* release it again */
 
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
 #define isa_dma_bridge_buggy    (0)
+#endif
 
 #endif /* _M68K_DMA_H */
diff --git a/arch/m68k/include/asm/emergency-restart.h b/arch/m68k/include/asm/emergency-restart.h
deleted file mode 100644
index 108d8c48e42..00000000000
--- a/arch/m68k/include/asm/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/arch/m68k/include/asm/errno.h b/arch/m68k/include/asm/errno.h
deleted file mode 100644
index 0d4e188d6ef..00000000000
--- a/arch/m68k/include/asm/errno.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _M68K_ERRNO_H
-#define _M68K_ERRNO_H
-
-#include <asm-generic/errno.h>
-
-#endif /* _M68K_ERRNO_H */
diff --git a/arch/m68k/include/asm/futex.h b/arch/m68k/include/asm/futex.h
deleted file mode 100644
index 6a332a9f099..00000000000
--- a/arch/m68k/include/asm/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 00d0071de4c..4395ffc51fd 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -17,170 +17,9 @@
 #define coldfire_gpio_h
 
 #include <linux/io.h>
-#include <asm-generic/gpio.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-
-/*
- * The Freescale Coldfire family is quite varied in how they implement GPIO.
- * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
- * only one port, others have multiple ports; some have a single data latch
- * for both input and output, others have a separate pin data register to read
- * input; some require a read-modify-write access to change an output, others
- * have set and clear registers for some of the outputs; Some have all the
- * GPIOs in a single control area, others have some GPIOs implemented in
- * different modules.
- *
- * This implementation attempts accommodate the differences while presenting
- * a generic interface that will optimize to as few instructions as possible.
- */
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
-    defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
-    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
-    defined(CONFIG_M532x) || defined(CONFIG_M54xx)
-
-/* These parts have GPIO organized by 8 bit ports */
-
-#define MCFGPIO_PORTTYPE                u8
-#define MCFGPIO_PORTSIZE                8
-#define mcfgpio_read(port)              __raw_readb(port)
-#define mcfgpio_write(data, port)       __raw_writeb(data, port)
-
-#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
-
-/* These parts have GPIO organized by 16 bit ports */
-
-#define MCFGPIO_PORTTYPE                u16
-#define MCFGPIO_PORTSIZE                16
-#define mcfgpio_read(port)              __raw_readw(port)
-#define mcfgpio_write(data, port)       __raw_writew(data, port)
-
-#elif defined(CONFIG_M5249)
-
-/* These parts have GPIO organized by 32 bit ports */
-
-#define MCFGPIO_PORTTYPE                u32
-#define MCFGPIO_PORTSIZE                32
-#define mcfgpio_read(port)              __raw_readl(port)
-#define mcfgpio_write(data, port)       __raw_writel(data, port)
-
-#endif
-
-#define mcfgpio_bit(gpio)               (1 << ((gpio) %  MCFGPIO_PORTSIZE))
-#define mcfgpio_port(gpio)              ((gpio) / MCFGPIO_PORTSIZE)
-
-#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
-    defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
-/*
- * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
- * read-modify-write to change an output and a GPIO module which has separate
- * set/clr registers to directly change outputs with a single write access.
- */
-#if defined(CONFIG_M528x)
-/*
- * The 528x also has GPIOs in other modules (GPT, QADC) which use
- * read-modify-write as well as those controlled by the EPORT and GPIO modules.
- */
-#define MCFGPIO_SCR_START               40
-#else
-#define MCFGPIO_SCR_START               8
-#endif
-
-#define MCFGPIO_SETR_PORT(gpio)         (MCFGPIO_SETR + \
-                                        mcfgpio_port(gpio - MCFGPIO_SCR_START))
-
-#define MCFGPIO_CLRR_PORT(gpio)         (MCFGPIO_CLRR + \
-                                        mcfgpio_port(gpio - MCFGPIO_SCR_START))
-#else
-
-#define MCFGPIO_SCR_START               MCFGPIO_PIN_MAX
-/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
-#define MCFGPIO_SETR_PORT(gpio)         0
-#define MCFGPIO_CLRR_PORT(gpio)         0
-
-#endif
-/*
- * Coldfire specific helper functions
- */
-
-/* return the port pin data register for a gpio */
-static inline u32 __mcf_gpio_ppdr(unsigned gpio)
-{
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
-    defined(CONFIG_M5307) || defined(CONFIG_M5407)
-        return MCFSIM_PADAT;
-#elif defined(CONFIG_M5272)
-        if (gpio < 16)
-                return MCFSIM_PADAT;
-        else if (gpio < 32)
-                return MCFSIM_PBDAT;
-        else
-                return MCFSIM_PCDAT;
-#elif defined(CONFIG_M5249)
-        if (gpio < 32)
-                return MCFSIM2_GPIOREAD;
-        else
-                return MCFSIM2_GPIO1READ;
-#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
-      defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
-        if (gpio < 8)
-                return MCFEPORT_EPPDR;
-#if defined(CONFIG_M528x)
-        else if (gpio < 16)
-                return MCFGPTA_GPTPORT;
-        else if (gpio < 24)
-                return MCFGPTB_GPTPORT;
-        else if (gpio < 32)
-                return MCFQADC_PORTQA;
-        else if (gpio < 40)
-                return MCFQADC_PORTQB;
-#endif
-        else
-                return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
-#else
-        return 0;
-#endif
-}
-
-/* return the port output data register for a gpio */
-static inline u32 __mcf_gpio_podr(unsigned gpio)
-{
-#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
-    defined(CONFIG_M5307) || defined(CONFIG_M5407)
-        return MCFSIM_PADAT;
-#elif defined(CONFIG_M5272)
-        if (gpio < 16)
-                return MCFSIM_PADAT;
-        else if (gpio < 32)
-                return MCFSIM_PBDAT;
-        else
-                return MCFSIM_PCDAT;
-#elif defined(CONFIG_M5249)
-        if (gpio < 32)
-                return MCFSIM2_GPIOWRITE;
-        else
-                return MCFSIM2_GPIO1WRITE;
-#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
-      defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
-        if (gpio < 8)
-                return MCFEPORT_EPDR;
-#if defined(CONFIG_M528x)
-        else if (gpio < 16)
-                return MCFGPTA_GPTPORT;
-        else if (gpio < 24)
-                return MCFGPTB_GPTPORT;
-        else if (gpio < 32)
-                return MCFQADC_PORTQA;
-        else if (gpio < 40)
-                return MCFQADC_PORTQB;
-#endif
-        else
-                return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
-#else
-        return 0;
-#endif
-}
-
+#include <asm/mcfgpio.h>
 /*
  * The Generic GPIO functions
  *
@@ -191,7 +30,7 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
 static inline int gpio_get_value(unsigned gpio)
 {
         if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
-                return mcfgpio_read(__mcf_gpio_ppdr(gpio)) & mcfgpio_bit(gpio);
+                return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
         else
                 return __gpio_get_value(gpio);
 }
@@ -204,12 +43,12 @@ static inline void gpio_set_value(unsigned gpio, int value)
                         MCFGPIO_PORTTYPE data;
 
                         local_irq_save(flags);
-                        data = mcfgpio_read(__mcf_gpio_podr(gpio));
+                        data = mcfgpio_read(__mcfgpio_podr(gpio));
                         if (value)
                                 data |= mcfgpio_bit(gpio);
                         else
                                 data &= ~mcfgpio_bit(gpio);
-                        mcfgpio_write(data, __mcf_gpio_podr(gpio));
+                        mcfgpio_write(data, __mcfgpio_podr(gpio));
                         local_irq_restore(flags);
                 } else {
                         if (value)
@@ -225,8 +64,14 @@ static inline void gpio_set_value(unsigned gpio, int value)
 
 static inline int gpio_to_irq(unsigned gpio)
 {
-        return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE
-                : __gpio_to_irq(gpio);
+#if defined(MCFGPIO_IRQ_MIN)
+        if ((gpio >= MCFGPIO_IRQ_MIN) && (gpio < MCFGPIO_IRQ_MAX))
+#else
+        if (gpio < MCFGPIO_IRQ_MAX)
+#endif
+                return gpio + MCFGPIO_IRQ_VECBASE;
+        else
+                return __gpio_to_irq(gpio);
 }
 
 static inline int irq_to_gpio(unsigned irq)
diff --git a/arch/m68k/include/asm/io_mm.h b/arch/m68k/include/asm/io_mm.h
index fa4324bcf56..a6686d26fe1 100644
--- a/arch/m68k/include/asm/io_mm.h
+++ b/arch/m68k/include/asm/io_mm.h
@@ -65,7 +65,53 @@
 
 
 
-#ifdef CONFIG_ISA
+#if defined(CONFIG_PCI) && defined(CONFIG_COLDFIRE)
+
+#define HAVE_ARCH_PIO_SIZE
+#define PIO_OFFSET      0
+#define PIO_MASK        0xffff
+#define PIO_RESERVED    0x10000
+
+u8 mcf_pci_inb(u32 addr);
+u16 mcf_pci_inw(u32 addr);
+u32 mcf_pci_inl(u32 addr);
+void mcf_pci_insb(u32 addr, u8 *buf, u32 len);
+void mcf_pci_insw(u32 addr, u16 *buf, u32 len);
+void mcf_pci_insl(u32 addr, u32 *buf, u32 len);
+
+void mcf_pci_outb(u8 v, u32 addr);
+void mcf_pci_outw(u16 v, u32 addr);
+void mcf_pci_outl(u32 v, u32 addr);
+void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len);
+void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len);
+void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len);
+
+#define inb     mcf_pci_inb
+#define inb_p   mcf_pci_inb
+#define inw     mcf_pci_inw
+#define inw_p   mcf_pci_inw
+#define inl     mcf_pci_inl
+#define inl_p   mcf_pci_inl
+#define insb    mcf_pci_insb
+#define insw    mcf_pci_insw
+#define insl    mcf_pci_insl
+
+#define outb    mcf_pci_outb
+#define outb_p  mcf_pci_outb
+#define outw    mcf_pci_outw
+#define outw_p  mcf_pci_outw
+#define outl    mcf_pci_outl
+#define outl_p  mcf_pci_outl
+#define outsb   mcf_pci_outsb
+#define outsw   mcf_pci_outsw
+#define outsl   mcf_pci_outsl
+
+#define readb(addr)     in_8(addr)
+#define writeb(v, addr) out_8((addr), (v))
+#define readw(addr)     in_le16(addr)
+#define writew(v, addr) out_le16((addr), (v))
+
+#elif defined(CONFIG_ISA)
 
 #if MULTI_ISA == 0
 #undef MULTI_ISA
@@ -340,4 +386,6 @@ static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int
  */
 #define xlate_dev_kmem_ptr(p)   p
 
+#define ioport_map(port, nr)    ((void __iomem *)(port))
+
 #endif /* _IO_H */
diff --git a/arch/m68k/include/asm/ioctl.h b/arch/m68k/include/asm/ioctl.h
deleted file mode 100644
index b279fe06dfe..00000000000
--- a/arch/m68k/include/asm/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctl.h>
diff --git a/arch/m68k/include/asm/ipcbuf.h b/arch/m68k/include/asm/ipcbuf.h
deleted file mode 100644
index 84c7e51cb6d..00000000000
--- a/arch/m68k/include/asm/ipcbuf.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ipcbuf.h>
diff --git a/arch/m68k/include/asm/irq_regs.h b/arch/m68k/include/asm/irq_regs.h
deleted file mode 100644
index 3dd9c0b7027..00000000000
--- a/arch/m68k/include/asm/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/arch/m68k/include/asm/kdebug.h b/arch/m68k/include/asm/kdebug.h
deleted file mode 100644
index 6ece1b03766..00000000000
--- a/arch/m68k/include/asm/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/arch/m68k/include/asm/kmap_types.h b/arch/m68k/include/asm/kmap_types.h
deleted file mode 100644
index 3413cc1390e..00000000000
--- a/arch/m68k/include/asm/kmap_types.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_M68K_KMAP_TYPES_H
-#define __ASM_M68K_KMAP_TYPES_H
-
-#include <asm-generic/kmap_types.h>
-
-#endif  /* __ASM_M68K_KMAP_TYPES_H */
diff --git a/arch/m68k/include/asm/kvm_para.h b/arch/m68k/include/asm/kvm_para.h
deleted file mode 100644
index 14fab8f0b95..00000000000
--- a/arch/m68k/include/asm/kvm_para.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kvm_para.h>
diff --git a/arch/m68k/include/asm/local.h b/arch/m68k/include/asm/local.h
deleted file mode 100644
index 6c259263e1f..00000000000
--- a/arch/m68k/include/asm/local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_M68K_LOCAL_H
-#define _ASM_M68K_LOCAL_H
-
-#include <asm-generic/local.h>
-
-#endif /* _ASM_M68K_LOCAL_H */
diff --git a/arch/m68k/include/asm/local64.h b/arch/m68k/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc23..00000000000
--- a/arch/m68k/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/local64.h>
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 17f2aab9cf9..db3f8ee4a6c 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -42,6 +42,9 @@
 #define MCFINTC1_SIMR       (0)
 #define MCFINTC1_CIMR       (0)
 #define MCFINTC1_ICR0       (0)
+#define MCFINTC2_SIMR       (0)
+#define MCFINTC2_CIMR       (0)
+#define MCFINTC2_ICR0       (0)
 
 #define MCFINT_VECBASE      64
 #define MCFINT_UART0        26          /* Interrupt number for UART0 */
@@ -62,6 +65,7 @@
 #define MCF_IRQ_FECENTC0    (MCFINT_VECBASE + MCFINT_FECENTC0)
 
 #define MCF_IRQ_QSPI        (MCFINT_VECBASE + MCFINT_QSPI)
+#define MCF_IRQ_PIT1        (MCFINT_VECBASE + MCFINT_PIT1)
 
 /*
  *  SDRAM configuration registers.
@@ -186,5 +190,15 @@
 #define MCF_RCR_SWRESET         0x80            /* Software reset bit */
 #define MCF_RCR_FRCSTOUT        0x40            /* Force external reset */
 
+/*
+ *  Power Management.
+ */
+#define MCFPM_WCR               0xfc040013
+#define MCFPM_PPMSR0            0xfc04002c
+#define MCFPM_PPMCR0            0xfc04002d
+#define MCFPM_PPMHR0            0xfc040030
+#define MCFPM_PPMLR0            0xfc040034
+#define MCFPM_LPCR              0xfc0a0007
+
 /****************************************************************************/
 #endif  /* m520xsim_h */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 075062d4eec..91d3abc3f2a 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -52,6 +52,7 @@
 #define MCF_IRQ_FECENTC0        (MCFINT_VECBASE + MCFINT_FECENTC0)
 
 #define MCF_IRQ_QSPI            (MCFINT_VECBASE + MCFINT_QSPI)
+#define MCF_IRQ_PIT1            (MCFINT_VECBASE + MCFINT_PIT1)
 
 /*
  *      SDRAM configuration registers.
diff --git a/arch/m68k/include/asm/m525xsim.h b/arch/m68k/include/asm/m525xsim.h
new file mode 100644
index 00000000000..6da24f65390
--- /dev/null
+++ b/arch/m68k/include/asm/m525xsim.h
@@ -0,0 +1,194 @@
+/****************************************************************************/
+
+/*
+ *      m525xsim.h -- ColdFire 525x System Integration Module support.
+ *
+ *      (C) Copyright 2012, Steven king <sfking@fdwdc.com>
+ *      (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
+ */
+
+/****************************************************************************/
+#ifndef m525xsim_h
+#define m525xsim_h
+/****************************************************************************/
+
+#define CPU_NAME                "COLDFIRE(m525x)"
+#define CPU_INSTR_PER_JIFFY     3
+#define MCF_BUSCLK              (MCF_CLK / 2)
+
+#include <asm/m52xxacr.h>
+
+/*
+ *      The 525x has a second MBAR region, define its address.
+ */
+#define MCF_MBAR2               0x80000000
+
+/*
+ *      Define the 525x SIM register set addresses.
+ */
+#define MCFSIM_RSR              0x00            /* Reset Status reg (r/w) */
+#define MCFSIM_SYPCR            0x01            /* System Protection reg (r/w)*/
+#define MCFSIM_SWIVR            0x02            /* SW Watchdog intr reg (r/w) */
+#define MCFSIM_SWSR             0x03            /* SW Watchdog service (r/w) */
+#define MCFSIM_MPARK            0x0C            /* BUS Master Control Reg*/
+#define MCFSIM_IPR              0x40            /* Interrupt Pend reg (r/w) */
+#define MCFSIM_IMR              0x44            /* Interrupt Mask reg (r/w) */
+#define MCFSIM_ICR0             0x4c            /* Intr Ctrl reg 0 (r/w) */
+#define MCFSIM_ICR1             0x4d            /* Intr Ctrl reg 1 (r/w) */
+#define MCFSIM_ICR2             0x4e            /* Intr Ctrl reg 2 (r/w) */
+#define MCFSIM_ICR3             0x4f            /* Intr Ctrl reg 3 (r/w) */
+#define MCFSIM_ICR4             0x50            /* Intr Ctrl reg 4 (r/w) */
+#define MCFSIM_ICR5             0x51            /* Intr Ctrl reg 5 (r/w) */
+#define MCFSIM_ICR6             0x52            /* Intr Ctrl reg 6 (r/w) */
+#define MCFSIM_ICR7             0x53            /* Intr Ctrl reg 7 (r/w) */
+#define MCFSIM_ICR8             0x54            /* Intr Ctrl reg 8 (r/w) */
+#define MCFSIM_ICR9             0x55            /* Intr Ctrl reg 9 (r/w) */
+#define MCFSIM_ICR10            0x56            /* Intr Ctrl reg 10 (r/w) */
+#define MCFSIM_ICR11            0x57            /* Intr Ctrl reg 11 (r/w) */
+
+#define MCFSIM_CSAR0            0x80            /* CS 0 Address 0 reg (r/w) */
+#define MCFSIM_CSMR0            0x84            /* CS 0 Mask 0 reg (r/w) */
+#define MCFSIM_CSCR0            0x8a            /* CS 0 Control reg (r/w) */
+#define MCFSIM_CSAR1            0x8c            /* CS 1 Address reg (r/w) */
+#define MCFSIM_CSMR1            0x90            /* CS 1 Mask reg (r/w) */
+#define MCFSIM_CSCR1            0x96            /* CS 1 Control reg (r/w) */
+#define MCFSIM_CSAR2            0x98            /* CS 2 Address reg (r/w) */
+#define MCFSIM_CSMR2            0x9c            /* CS 2 Mask reg (r/w) */
+#define MCFSIM_CSCR2            0xa2            /* CS 2 Control reg (r/w) */
+#define MCFSIM_CSAR3            0xa4            /* CS 3 Address reg (r/w) */
+#define MCFSIM_CSMR3            0xa8            /* CS 3 Mask reg (r/w) */
+#define MCFSIM_CSCR3            0xae            /* CS 3 Control reg (r/w) */
+#define MCFSIM_CSAR4            0xb0            /* CS 4 Address reg (r/w) */
+#define MCFSIM_CSMR4            0xb4            /* CS 4 Mask reg (r/w) */
+#define MCFSIM_CSCR4            0xba            /* CS 4 Control reg (r/w) */
+
+#define MCFSIM_DCR              (MCF_MBAR + 0x100)      /* DRAM Control */
+#define MCFSIM_DACR0            (MCF_MBAR + 0x108)      /* DRAM 0 Addr/Ctrl */
+#define MCFSIM_DMR0             (MCF_MBAR + 0x10c)      /* DRAM 0 Mask */
+
+/*
+ * Secondary Interrupt Controller (in MBAR2)
+*/
+#define MCFINTC2_INTBASE        (MCF_MBAR2 + 0x168)     /* Base Vector Reg */
+#define MCFINTC2_INTPRI1        (MCF_MBAR2 + 0x140)     /* 0-7 priority */
+#define MCFINTC2_INTPRI2        (MCF_MBAR2 + 0x144)     /* 8-15 priority */
+#define MCFINTC2_INTPRI3        (MCF_MBAR2 + 0x148)     /* 16-23 priority */
+#define MCFINTC2_INTPRI4        (MCF_MBAR2 + 0x14c)     /* 24-31 priority */
+#define MCFINTC2_INTPRI5        (MCF_MBAR2 + 0x150)     /* 32-39 priority */
+#define MCFINTC2_INTPRI6        (MCF_MBAR2 + 0x154)     /* 40-47 priority */
+#define MCFINTC2_INTPRI7        (MCF_MBAR2 + 0x158)     /* 48-55 priority */
+#define MCFINTC2_INTPRI8        (MCF_MBAR2 + 0x15c)     /* 56-63 priority */
+
+#define MCFINTC2_INTPRI_REG(i)  (MCFINTC2_INTPRI1 + \
+                                ((((i) - MCFINTC2_VECBASE) / 8) * 4))
+#define MCFINTC2_INTPRI_BITS(b, i)      ((b) << (((i) % 8) * 4))
+
+/*
+ *      Timer module.
+ */
+#define MCFTIMER_BASE1          (MCF_MBAR + 0x140)      /* Base of TIMER1 */
+#define MCFTIMER_BASE2          (MCF_MBAR + 0x180)      /* Base of TIMER2 */
+
+/*
+ *      UART module.
+ */
+#define MCFUART_BASE0           (MCF_MBAR + 0x1c0)      /* Base address UART0 */
+#define MCFUART_BASE1           (MCF_MBAR + 0x200)      /* Base address UART1 */
+
+/*
+ *      QSPI module.
+ */
+#define MCFQSPI_BASE            (MCF_MBAR + 0x300)      /* Base address QSPI */
+#define MCFQSPI_SIZE            0x40                    /* Register set size */
+
+
+#define MCFQSPI_CS0             15
+#define MCFQSPI_CS1             16
+#define MCFQSPI_CS2             24
+#define MCFQSPI_CS3             28
+
+/*
+ *      I2C module.
+ */
+#define MCFI2C_BASE0            (MCF_MBAR + 0x280)      /* Base addreess I2C0 */
+#define MCFI2C_SIZE0            0x20                    /* Register set size */
+
+#define MCFI2C_BASE1            (MCF_MBAR2 + 0x440)     /* Base addreess I2C1 */
+#define MCFI2C_SIZE1            0x20                    /* Register set size */
+/*
+ *      DMA unit base addresses.
+ */
+#define MCFDMA_BASE0            (MCF_MBAR + 0x300)      /* Base address DMA 0 */
+#define MCFDMA_BASE1            (MCF_MBAR + 0x340)      /* Base address DMA 1 */
+#define MCFDMA_BASE2            (MCF_MBAR + 0x380)      /* Base address DMA 2 */
+#define MCFDMA_BASE3            (MCF_MBAR + 0x3C0)      /* Base address DMA 3 */
+
+/*
+ *      Some symbol defines for the above...
+ */
+#define MCFSIM_SWDICR           MCFSIM_ICR0     /* Watchdog timer ICR */
+#define MCFSIM_TIMER1ICR        MCFSIM_ICR1     /* Timer 1 ICR */
+#define MCFSIM_TIMER2ICR        MCFSIM_ICR2     /* Timer 2 ICR */
+#define MCFSIM_I2CICR           MCFSIM_ICR3     /* I2C ICR */
+#define MCFSIM_UART1ICR         MCFSIM_ICR4     /* UART 1 ICR */
+#define MCFSIM_UART2ICR         MCFSIM_ICR5     /* UART 2 ICR */
+#define MCFSIM_DMA0ICR          MCFSIM_ICR6     /* DMA 0 ICR */
+#define MCFSIM_DMA1ICR          MCFSIM_ICR7     /* DMA 1 ICR */
+#define MCFSIM_DMA2ICR          MCFSIM_ICR8     /* DMA 2 ICR */
+#define MCFSIM_DMA3ICR          MCFSIM_ICR9     /* DMA 3 ICR */
+#define MCFSIM_QSPIICR          MCFSIM_ICR10    /* QSPI ICR */
+
+/*
+ *      Define system peripheral IRQ usage.
+ */
+#define MCF_IRQ_QSPI            28              /* QSPI, Level 4 */
+#define MCF_IRQ_I2C0            29
+#define MCF_IRQ_TIMER           30              /* Timer0, Level 6 */
+#define MCF_IRQ_PROFILER        31              /* Timer1, Level 7 */
+
+#define MCF_IRQ_UART0           73              /* UART0 */
+#define MCF_IRQ_UART1           74              /* UART1 */
+
+/*
+ * Define the base interrupt for the second interrupt controller.
+ * We set it to 128, out of the way of the base interrupts, and plenty
+ * of room for its 64 interrupts.
+ */
+#define MCFINTC2_VECBASE        128
+
+#define MCF_IRQ_GPIO0           (MCFINTC2_VECBASE + 32)
+#define MCF_IRQ_GPIO1           (MCFINTC2_VECBASE + 33)
+#define MCF_IRQ_GPIO2           (MCFINTC2_VECBASE + 34)
+#define MCF_IRQ_GPIO3           (MCFINTC2_VECBASE + 35)
+#define MCF_IRQ_GPIO4           (MCFINTC2_VECBASE + 36)
+#define MCF_IRQ_GPIO5           (MCFINTC2_VECBASE + 37)
+#define MCF_IRQ_GPIO6           (MCFINTC2_VECBASE + 38)
+
+#define MCF_IRQ_USBWUP          (MCFINTC2_VECBASE + 40)
+#define MCF_IRQ_I2C1            (MCFINTC2_VECBASE + 62)
+
+/*
+ *      General purpose IO registers (in MBAR2).
+ */
+#define MCFSIM2_GPIOREAD        (MCF_MBAR2 + 0x000)     /* GPIO read values */
+#define MCFSIM2_GPIOWRITE       (MCF_MBAR2 + 0x004)     /* GPIO write values */
+#define MCFSIM2_GPIOENABLE      (MCF_MBAR2 + 0x008)     /* GPIO enabled */
+#define MCFSIM2_GPIOFUNC        (MCF_MBAR2 + 0x00C)     /* GPIO function */
+#define MCFSIM2_GPIO1READ       (MCF_MBAR2 + 0x0B0)     /* GPIO1 read values */
+#define MCFSIM2_GPIO1WRITE      (MCF_MBAR2 + 0x0B4)     /* GPIO1 write values */
+#define MCFSIM2_GPIO1ENABLE     (MCF_MBAR2 + 0x0B8)     /* GPIO1 enabled */
+#define MCFSIM2_GPIO1FUNC       (MCF_MBAR2 + 0x0BC)     /* GPIO1 function */
+
+#define MCFSIM2_GPIOINTSTAT     (MCF_MBAR2 + 0xc0)      /* GPIO intr status */
+#define MCFSIM2_GPIOINTCLEAR    (MCF_MBAR2 + 0xc0)      /* GPIO intr clear */
+#define MCFSIM2_GPIOINTENABLE   (MCF_MBAR2 + 0xc4)      /* GPIO intr enable */
+
+/*
+ * Generic GPIO support
+ */
+#define MCFGPIO_PIN_MAX         64
+#define MCFGPIO_IRQ_MAX         7
+#define MCFGPIO_IRQ_VECBASE     MCF_IRQ_GPIO0
+
+/****************************************************************************/
+#endif  /* m525xsim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 83db8106f50..71aa5104d3d 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -60,6 +60,7 @@
 #define MCF_IRQ_FECENTC1        (MCFINT2_VECBASE + MCFINT2_FECENTC1)
 
 #define MCF_IRQ_QSPI            (MCFINT_VECBASE + MCFINT_QSPI)
+#define MCF_IRQ_PIT1            (MCFINT_VECBASE + MCFINT_PIT1)
 
 /*
  *      SDRAM configuration registers.
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index 497c31c803f..4acb3c0a642 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -52,7 +52,7 @@
 #define MCF_IRQ_FECENTC0        (MCFINT_VECBASE + MCFINT_FECENTC0)
 
 #define MCF_IRQ_QSPI            (MCFINT_VECBASE + MCFINT_QSPI)
-
+#define MCF_IRQ_PIT1            (MCFINT_VECBASE + MCFINT_PIT1)
 /*
  *      SDRAM configuration registers.
  */
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 29b66e21413..5ca7b298c6e 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -82,6 +82,9 @@
 #define MCFINTC1_SIMR           0xFC04C01C
 #define MCFINTC1_CIMR           0xFC04C01D
 #define MCFINTC1_ICR0           0xFC04C040
+#define MCFINTC2_SIMR           (0)
+#define MCFINTC2_CIMR           (0)
+#define MCFINTC2_ICR0           (0)
 
 #define MCFSIM_ICR_TIMER1       (0xFC048040+32)
 #define MCFSIM_ICR_TIMER2       (0xFC048040+33)
@@ -135,6 +138,20 @@
 #define MCF_RCR_SWRESET         0x80            /* Software reset bit */
 #define MCF_RCR_FRCSTOUT        0x40            /* Force external reset */
 
+
+/*
+ * Power Management
+ */
+#define MCFPM_WCR               0xfc040013
+#define MCFPM_PPMSR0            0xfc04002c
+#define MCFPM_PPMCR0            0xfc04002d
+#define MCFPM_PPMSR1            0xfc04002e
+#define MCFPM_PPMCR1            0xfc04002f
+#define MCFPM_PPMHR0            0xfc040030
+#define MCFPM_PPMLR0            0xfc040034
+#define MCFPM_PPMHR1            0xfc040038
+#define MCFPM_LPCR              0xec090007
+
 /*********************************************************************
  *
  * Inter-IC (I2C) Module
diff --git a/arch/m68k/include/asm/m5441xsim.h b/arch/m68k/include/asm/m5441xsim.h
new file mode 100644
index 00000000000..cc798ab9524
--- /dev/null
+++ b/arch/m68k/include/asm/m5441xsim.h
@@ -0,0 +1,276 @@
+/*
+ *      m5441xsim.h -- Coldfire 5441x register definitions
+ *
+ *      (C) Copyright 2012, Steven King <sfking@fdwdc.com>
+*/
+
+#ifndef m5441xsim_h
+#define m5441xsim_h
+
+#define CPU_NAME                "COLDFIRE(m5441x)"
+#define CPU_INSTR_PER_JIFFY     2
+#define MCF_BUSCLK              (MCF_CLK / 2)
+
+#include <asm/m54xxacr.h>
+
+/*
+ *  Reset Controller Module.
+ */
+
+#define MCF_RCR                 0xec090000
+#define MCF_RSR                 0xec090001
+
+#define MCF_RCR_SWRESET         0x80            /* Software reset bit */
+#define MCF_RCR_FRCSTOUT        0x40            /* Force external reset */
+
+/*
+ *  Interrupt Controller Modules.
+ */
+/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
+#define MCFINT_VECBASE          64
+#define MCFINT0_VECBASE         MCFINT_VECBASE
+#define MCFINT1_VECBASE         (MCFINT0_VECBASE + 64)
+#define MCFINT2_VECBASE         (MCFINT1_VECBASE + 64)
+
+/* interrupt controller 0 */
+#define MCFINTC0_SIMR           0xfc04801c
+#define MCFINTC0_CIMR           0xfc04801d
+#define MCFINTC0_ICR0           0xfc048040
+/* interrupt controller 1 */
+#define MCFINTC1_SIMR           0xfc04c01c
+#define MCFINTC1_CIMR           0xfc04c01d
+#define MCFINTC1_ICR0           0xfc04c040
+/* interrupt controller 2 */
+#define MCFINTC2_SIMR           0xfc05001c
+#define MCFINTC2_CIMR           0xfc05001d
+#define MCFINTC2_ICR0           0xfc050040
+
+/* on interrupt controller 0 */
+#define MCFINT0_EPORT0          1
+#define MCFINT0_UART0           26
+#define MCFINT0_UART1           27
+#define MCFINT0_UART2           28
+#define MCFINT0_UART3           29
+#define MCFINT0_I2C0            30
+#define MCFINT0_DSPI0           31
+
+#define MCFINT0_TIMER0          32
+#define MCFINT0_TIMER1          33
+#define MCFINT0_TIMER2          34
+#define MCFINT0_TIMER3          35
+
+#define MCFINT0_FECRX0          36
+#define MCFINT0_FECTX0          40
+#define MCFINT0_FECENTC0        42
+
+#define MCFINT0_FECRX1          49
+#define MCFINT0_FECTX1          53
+#define MCFINT0_FECENTC1        55
+
+/* on interrupt controller 1 */
+#define MCFINT1_UART4           48
+#define MCFINT1_UART5           49
+#define MCFINT1_UART6           50
+#define MCFINT1_UART7           51
+#define MCFINT1_UART8           52
+#define MCFINT1_UART9           53
+#define MCFINT1_DSPI1           54
+#define MCFINT1_DSPI2           55
+#define MCFINT1_DSPI3           56
+#define MCFINT1_I2C1            57
+#define MCFINT1_I2C2            58
+#define MCFINT1_I2C3            59
+#define MCFINT1_I2C4            60
+#define MCFINT1_I2C5            61
+
+/* on interrupt controller 2 */
+#define MCFINT2_PIT0            13
+#define MCFINT2_PIT1            14
+#define MCFINT2_PIT2            15
+#define MCFINT2_PIT3            16
+#define MCFINT2_RTC             26
+
+/*
+ *  PIT timer module.
+ */
+#define MCFPIT_BASE0            0xFC080000      /* Base address of TIMER0 */
+#define MCFPIT_BASE1            0xFC084000      /* Base address of TIMER1 */
+#define MCFPIT_BASE2            0xFC088000      /* Base address of TIMER2 */
+#define MCFPIT_BASE3            0xFC08C000      /* Base address of TIMER3 */
+
+
+#define MCF_IRQ_PIT1            (MCFINT2_VECBASE + MCFINT2_PIT1)
+
+/*
+ * Power Management
+ */
+#define MCFPM_WCR               0xfc040013
+#define MCFPM_PPMSR0            0xfc04002c
+#define MCFPM_PPMCR0            0xfc04002d
+#define MCFPM_PPMSR1            0xfc04002e
+#define MCFPM_PPMCR1            0xfc04002f
+#define MCFPM_PPMHR0            0xfc040030
+#define MCFPM_PPMLR0            0xfc040034
+#define MCFPM_PPMHR1            0xfc040038
+#define MCFPM_PPMLR1            0xfc04003c
+#define MCFPM_LPCR              0xec090007
+/*
+ *  UART module.
+ */
+#define MCFUART_BASE0           0xfc060000      /* Base address of UART0 */
+#define MCFUART_BASE1           0xfc064000      /* Base address of UART1 */
+#define MCFUART_BASE2           0xfc068000      /* Base address of UART2 */
+#define MCFUART_BASE3           0xfc06c000      /* Base address of UART3 */
+#define MCFUART_BASE4           0xec060000      /* Base address of UART4 */
+#define MCFUART_BASE5           0xec064000      /* Base address of UART5 */
+#define MCFUART_BASE6           0xec068000      /* Base address of UART6 */
+#define MCFUART_BASE7           0xec06c000      /* Base address of UART7 */
+#define MCFUART_BASE8           0xec070000      /* Base address of UART8 */
+#define MCFUART_BASE9           0xec074000      /* Base address of UART9 */
+
+#define MCF_IRQ_UART0           (MCFINT0_VECBASE + MCFINT0_UART0)
+#define MCF_IRQ_UART1           (MCFINT0_VECBASE + MCFINT0_UART1)
+#define MCF_IRQ_UART2           (MCFINT0_VECBASE + MCFINT0_UART2)
+#define MCF_IRQ_UART3           (MCFINT0_VECBASE + MCFINT0_UART3)
+#define MCF_IRQ_UART4           (MCFINT1_VECBASE + MCFINT1_UART4)
+#define MCF_IRQ_UART5           (MCFINT1_VECBASE + MCFINT1_UART5)
+#define MCF_IRQ_UART6           (MCFINT1_VECBASE + MCFINT1_UART6)
+#define MCF_IRQ_UART7           (MCFINT1_VECBASE + MCFINT1_UART7)
+#define MCF_IRQ_UART8           (MCFINT1_VECBASE + MCFINT1_UART8)
+#define MCF_IRQ_UART9           (MCFINT1_VECBASE + MCFINT1_UART9)
+/*
+ *  FEC modules.
+ */
+#define MCFFEC_BASE0            0xfc0d4000
+#define MCFFEC_SIZE0            0x800
+#define MCF_IRQ_FECRX0          (MCFINT0_VECBASE + MCFINT0_FECRX0)
+#define MCF_IRQ_FECTX0          (MCFINT0_VECBASE + MCFINT0_FECTX0)
+#define MCF_IRQ_FECENTC0        (MCFINT0_VECBASE + MCFINT0_FECENTC0)
+
+#define MCFFEC_BASE1            0xfc0d8000
+#define MCFFEC_SIZE1            0x800
+#define MCF_IRQ_FECRX1          (MCFINT0_VECBASE + MCFINT0_FECRX1)
+#define MCF_IRQ_FECTX1          (MCFINT0_VECBASE + MCFINT0_FECTX1)
+#define MCF_IRQ_FECENTC1        (MCFINT0_VECBASE + MCFINT0_FECENTC1)
+/*
+ *  I2C modules.
+ */
+#define MCFI2C_BASE0            0xfc058000
+#define MCFI2C_SIZE0            0x20
+#define MCFI2C_BASE1            0xfc038000
+#define MCFI2C_SIZE1            0x20
+#define MCFI2C_BASE2            0xec010000
+#define MCFI2C_SIZE2            0x20
+#define MCFI2C_BASE3            0xec014000
+#define MCFI2C_SIZE3            0x20
+#define MCFI2C_BASE4            0xec018000
+#define MCFI2C_SIZE4            0x20
+#define MCFI2C_BASE5            0xec01c000
+#define MCFI2C_SIZE5            0x20
+
+#define MCF_IRQ_I2C0            (MCFINT0_VECBASE + MCFINT0_I2C0)
+#define MCF_IRQ_I2C1            (MCFINT1_VECBASE + MCFINT1_I2C1)
+#define MCF_IRQ_I2C2            (MCFINT1_VECBASE + MCFINT1_I2C2)
+#define MCF_IRQ_I2C3            (MCFINT1_VECBASE + MCFINT1_I2C3)
+#define MCF_IRQ_I2C4            (MCFINT1_VECBASE + MCFINT1_I2C4)
+#define MCF_IRQ_I2C5            (MCFINT1_VECBASE + MCFINT1_I2C5)
+/*
+ *  EPORT Module.
+ */
+#define MCFEPORT_EPPAR          0xfc090000
+#define MCFEPORT_EPIER          0xfc090003
+#define MCFEPORT_EPFR           0xfc090006
+/*
+ *  RTC Module.
+ */
+#define MCFRTC_BASE             0xfc0a8000
+#define MCFRTC_SIZE             (0xfc0a8840 - 0xfc0a8000)
+#define MCF_IRQ_RTC             (MCFINT2_VECBASE + MCFINT2_RTC)
+
+/*
+ *  GPIO Module.
+ */
+#define MCFGPIO_PODR_A          0xec094000
+#define MCFGPIO_PODR_B          0xec094001
+#define MCFGPIO_PODR_C          0xec094002
+#define MCFGPIO_PODR_D          0xec094003
+#define MCFGPIO_PODR_E          0xec094004
+#define MCFGPIO_PODR_F          0xec094005
+#define MCFGPIO_PODR_G          0xec094006
+#define MCFGPIO_PODR_H          0xec094007
+#define MCFGPIO_PODR_I          0xec094008
+#define MCFGPIO_PODR_J          0xec094009
+#define MCFGPIO_PODR_K          0xec09400a
+
+#define MCFGPIO_PDDR_A          0xec09400c
+#define MCFGPIO_PDDR_B          0xec09400d
+#define MCFGPIO_PDDR_C          0xec09400e
+#define MCFGPIO_PDDR_D          0xec09400f
+#define MCFGPIO_PDDR_E          0xec094010
+#define MCFGPIO_PDDR_F          0xec094011
+#define MCFGPIO_PDDR_G          0xec094012
+#define MCFGPIO_PDDR_H          0xec094013
+#define MCFGPIO_PDDR_I          0xec094014
+#define MCFGPIO_PDDR_J          0xec094015
+#define MCFGPIO_PDDR_K          0xec094016
+
+#define MCFGPIO_PPDSDR_A        0xec094018
+#define MCFGPIO_PPDSDR_B        0xec094019
+#define MCFGPIO_PPDSDR_C        0xec09401a
+#define MCFGPIO_PPDSDR_D        0xec09401b
+#define MCFGPIO_PPDSDR_E        0xec09401c
+#define MCFGPIO_PPDSDR_F        0xec09401d
+#define MCFGPIO_PPDSDR_G        0xec09401e
+#define MCFGPIO_PPDSDR_H        0xec09401f
+#define MCFGPIO_PPDSDR_I        0xec094020
+#define MCFGPIO_PPDSDR_J        0xec094021
+#define MCFGPIO_PPDSDR_K        0xec094022
+
+#define MCFGPIO_PCLRR_A         0xec094024
+#define MCFGPIO_PCLRR_B         0xec094025
+#define MCFGPIO_PCLRR_C         0xec094026
+#define MCFGPIO_PCLRR_D         0xec094027
+#define MCFGPIO_PCLRR_E         0xec094028
+#define MCFGPIO_PCLRR_F         0xec094029
+#define MCFGPIO_PCLRR_G         0xec09402a
+#define MCFGPIO_PCLRR_H         0xec09402b
+#define MCFGPIO_PCLRR_I         0xec09402c
+#define MCFGPIO_PCLRR_J         0xec09402d
+#define MCFGPIO_PCLRR_K         0xec09402e
+
+#define MCFGPIO_PAR_FBCTL       0xec094048
+#define MCFGPIO_PAR_BE          0xec094049
+#define MCFGPIO_PAR_CS          0xec09404a
+#define MCFGPIO_PAR_CANI2C      0xec09404b
+#define MCFGPIO_PAR_IRQ0H       0xec09404c
+#define MCFGPIO_PAR_IRQ0L       0xec09404d
+#define MCFGPIO_PAR_DSPIOWH     0xec09404e
+#define MCFGPIO_PAR_DSPIOWL     0xec09404f
+#define MCFGPIO_PAR_TIMER       0xec094050
+#define MCFGPIO_PAR_UART2       0xec094051
+#define MCFGPIO_PAR_UART1       0xec094052
+#define MCFGPIO_PAR_UART0       0xec094053
+#define MCFGPIO_PAR_SDHCH       0xec094054
+#define MCFGPIO_PAR_SDHCL       0xec094055
+#define MCFGPIO_PAR_SIMP0H      0xec094056
+#define MCFGPIO_PAR_SIMP0L      0xec094057
+#define MCFGPIO_PAR_SSI0H       0xec094058
+#define MCFGPIO_PAR_SSI0L       0xec094059
+#define MCFGPIO_PAR_DEBUGH1     0xec09405a
+#define MCFGPIO_PAR_DEBUGH0     0xec09405b
+#define MCFGPIO_PAR_DEBUGl      0xec09405c
+#define MCFGPIO_PAR_FEC         0xec09405e
+
+/* generalization for generic gpio support */
+#define MCFGPIO_PODR            MCFGPIO_PODR_A
+#define MCFGPIO_PDDR            MCFGPIO_PDDR_A
+#define MCFGPIO_PPDR            MCFGPIO_PPDSDR_A
+#define MCFGPIO_SETR            MCFGPIO_PPDSDR_A
+#define MCFGPIO_CLRR            MCFGPIO_PCLRR_A
+
+#define MCFGPIO_IRQ_MIN         17
+#define MCFGPIO_IRQ_MAX         24
+#define MCFGPIO_IRQ_VECBASE     (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
+#define MCFGPIO_PIN_MAX         87
+
+#endif /* m5441xsim_h */
diff --git a/arch/m68k/include/asm/m54xxacr.h b/arch/m68k/include/asm/m54xxacr.h
index 47906aafbf6..192bbfeabf7 100644
--- a/arch/m68k/include/asm/m54xxacr.h
+++ b/arch/m68k/include/asm/m54xxacr.h
@@ -55,6 +55,10 @@
 #define ICACHE_SIZE 0x8000      /* instruction - 32k */
 #define DCACHE_SIZE 0x8000      /* data - 32k */
 
+#elif defined(CONFIG_M5441x)
+
+#define ICACHE_SIZE 0x2000      /* instruction - 8k */
+#define DCACHE_SIZE 0x2000      /* data - 8k */
 #endif
 
 #define CACHE_LINE_SIZE 0x0010  /* 16 bytes */
diff --git a/arch/m68k/include/asm/m54xxpci.h b/arch/m68k/include/asm/m54xxpci.h
new file mode 100644
index 00000000000..6fbf54f72f2
--- /dev/null
+++ b/arch/m68k/include/asm/m54xxpci.h
@@ -0,0 +1,138 @@
+/****************************************************************************/
+
+/*
+ *      m54xxpci.h -- ColdFire 547x and 548x PCI bus support
+ *
+ *      (C) Copyright 2011,  Greg Ungerer <gerg@uclinux.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+/****************************************************************************/
+#ifndef M54XXPCI_H
+#define M54XXPCI_H
+/****************************************************************************/
+
+/*
+ *      The core set of PCI support registers are mapped into the MBAR region.
+ */
+#define PCIIDR          (CONFIG_MBAR + 0xb00)   /* PCI device/vendor ID */
+#define PCISCR          (CONFIG_MBAR + 0xb04)   /* PCI status/command */
+#define PCICCRIR        (CONFIG_MBAR + 0xb08)   /* PCI class/revision */
+#define PCICR1          (CONFIG_MBAR + 0xb0c)   /* PCI configuration 1 */
+#define PCIBAR0         (CONFIG_MBAR + 0xb10)   /* PCI base address 0 */
+#define PCIBAR1         (CONFIG_MBAR + 0xb14)   /* PCI base address 1 */
+#define PCICCPR         (CONFIG_MBAR + 0xb28)   /* PCI cardbus CIS pointer */
+#define PCISID          (CONFIG_MBAR + 0xb2c)   /* PCI subsystem IDs */
+#define PCIERBAR        (CONFIG_MBAR + 0xb30)   /* PCI expansion ROM */
+#define PCICPR          (CONFIG_MBAR + 0xb34)   /* PCI capabilities pointer */
+#define PCICR2          (CONFIG_MBAR + 0xb3c)   /* PCI configuration 2 */
+
+#define PCIGSCR         (CONFIG_MBAR + 0xb60)   /* Global status/control */
+#define PCITBATR0       (CONFIG_MBAR + 0xb64)   /* Target base translation 0 */
+#define PCITBATR1       (CONFIG_MBAR + 0xb68)   /* Target base translation 1 */
+#define PCITCR          (CONFIG_MBAR + 0xb6c)   /* Target control */
+#define PCIIW0BTAR      (CONFIG_MBAR + 0xb70)   /* Initiator window 0 */
+#define PCIIW1BTAR      (CONFIG_MBAR + 0xb74)   /* Initiator window 1 */
+#define PCIIW2BTAR      (CONFIG_MBAR + 0xb78)   /* Initiator window 2 */
+#define PCIIWCR         (CONFIG_MBAR + 0xb80)   /* Initiator window config */
+#define PCIICR          (CONFIG_MBAR + 0xb84)   /* Initiator control */
+#define PCIISR          (CONFIG_MBAR + 0xb88)   /* Initiator status */
+#define PCICAR          (CONFIG_MBAR + 0xbf8)   /* Configuration address */
+
+#define PCITPSR         (CONFIG_MBAR + 0x8400)  /* TX packet size */
+#define PCITSAR         (CONFIG_MBAR + 0x8404)  /* TX start address */
+#define PCITTCR         (CONFIG_MBAR + 0x8408)  /* TX transaction control */
+#define PCITER          (CONFIG_MBAR + 0x840c)  /* TX enables */
+#define PCITNAR         (CONFIG_MBAR + 0x8410)  /* TX next address */
+#define PCITLWR         (CONFIG_MBAR + 0x8414)  /* TX last word */
+#define PCITDCR         (CONFIG_MBAR + 0x8418)  /* TX done counts */
+#define PCITSR          (CONFIG_MBAR + 0x841c)  /* TX status */
+#define PCITFDR         (CONFIG_MBAR + 0x8440)  /* TX FIFO data */
+#define PCITFSR         (CONFIG_MBAR + 0x8444)  /* TX FIFO status */
+#define PCITFCR         (CONFIG_MBAR + 0x8448)  /* TX FIFO control */
+#define PCITFAR         (CONFIG_MBAR + 0x844c)  /* TX FIFO alarm */
+#define PCITFRPR        (CONFIG_MBAR + 0x8450)  /* TX FIFO read pointer */
+#define PCITFWPR        (CONFIG_MBAR + 0x8454)  /* TX FIFO write pointer */
+
+#define PCIRPSR         (CONFIG_MBAR + 0x8480)  /* RX packet size */
+#define PCIRSAR         (CONFIG_MBAR + 0x8484)  /* RX start address */
+#define PCIRTCR         (CONFIG_MBAR + 0x8488)  /* RX transaction control */
+#define PCIRER          (CONFIG_MBAR + 0x848c)  /* RX enables */
+#define PCIRNAR         (CONFIG_MBAR + 0x8490)  /* RX next address */
+#define PCIRDCR         (CONFIG_MBAR + 0x8498)  /* RX done counts */
+#define PCIRSR          (CONFIG_MBAR + 0x849c)  /* RX status */
+#define PCIRFDR         (CONFIG_MBAR + 0x84c0)  /* RX FIFO data */
+#define PCIRFSR         (CONFIG_MBAR + 0x84c4)  /* RX FIFO status */
+#define PCIRFCR         (CONFIG_MBAR + 0x84c8)  /* RX FIFO control */
+#define PCIRFAR         (CONFIG_MBAR + 0x84cc)  /* RX FIFO alarm */
+#define PCIRFRPR        (CONFIG_MBAR + 0x84d0)  /* RX FIFO read pointer */
+#define PCIRFWPR        (CONFIG_MBAR + 0x84d4)  /* RX FIFO write pointer */
+
+#define PACR            (CONFIG_MBAR + 0xc00)   /* PCI arbiter control */
+#define PASR            (COFNIG_MBAR + 0xc04)   /* PCI arbiter status */
+
+/*
+ *      Definitions for the Global status and control register.
+ */
+#define PCIGSCR_PE      0x20000000              /* Parity error detected */
+#define PCIGSCR_SE      0x10000000              /* System error detected */
+#define PCIGSCR_XCLKBIN 0x07000000              /* XLB2CLKIN mask */
+#define PCIGSCR_PEE     0x00002000              /* Parity error intr enable */
+#define PCIGSCR_SEE     0x00001000              /* System error intr enable */
+#define PCIGSCR_RESET   0x00000001              /* Reset bit */
+
+/*
+ *      Bit definitions for the PCICAR configuration address register.
+ */
+#define PCICAR_E        0x80000000              /* Enable config space */
+#define PCICAR_BUSN     16                      /* Move bus bits */
+#define PCICAR_DEVFNN   8                       /* Move devfn bits */
+#define PCICAR_DWORDN   0                       /* Move dword bits */
+
+/*
+ *      The initiator windows hold the memory and IO mapping information.
+ *      This macro creates the register values from the desired addresses.
+ */
+#define WXBTAR(hostaddr, pciaddr, size) \
+                        (((hostaddr) & 0xff000000) | \
+                        ((((size) - 1) & 0xff000000) >> 8) | \
+                        (((pciaddr) & 0xff000000) >> 16))
+
+#define PCIIWCR_W0_MEM  0x00000000              /* Window 0 is memory */
+#define PCIIWCR_W0_IO   0x08000000              /* Window 0 is IO */
+#define PCIIWCR_W0_MRD  0x00000000              /* Window 0 memory read */
+#define PCIIWCR_W0_MRDL 0x02000000              /* Window 0 memory read line */
+#define PCIIWCR_W0_MRDM 0x04000000              /* Window 0 memory read mult */
+#define PCIIWCR_W0_E    0x01000000              /* Window 0 enable */
+
+#define PCIIWCR_W1_MEM  0x00000000              /* Window 0 is memory */
+#define PCIIWCR_W1_IO   0x00080000              /* Window 0 is IO */
+#define PCIIWCR_W1_MRD  0x00000000              /* Window 0 memory read */
+#define PCIIWCR_W1_MRDL 0x00020000              /* Window 0 memory read line */
+#define PCIIWCR_W1_MRDM 0x00040000              /* Window 0 memory read mult */
+#define PCIIWCR_W1_E    0x00010000              /* Window 0 enable */
+
+/*
+ *      Bit definitions for the PCIBATR registers.
+ */
+#define PCITBATR0_E     0x00000001              /* Enable window 0 */
+#define PCITBATR1_E     0x00000001              /* Enable window 1 */
+
+/*
+ *      PCI arbiter support definitions and macros.
+ */
+#define PACR_INTMPRI    0x00000001
+#define PACR_EXTMPRI(x) (((x) & 0x1f) << 1)
+#define PACR_INTMINTE   0x00010000
+#define PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
+#define PACR_PKMD       0x40000000
+#define PACR_DS         0x80000000
+
+#define PCICR1_CL(x)    ((x) & 0xf)             /* Cacheline size field */
+#define PCICR1_LT(x)    (((x) & 0xff) << 8)     /* Latency timer field */
+
+/****************************************************************************/
+#endif  /* M54XXPCI_H */
diff --git a/arch/m68k/include/asm/m54xxsim.h b/arch/m68k/include/asm/m54xxsim.h
index ae56b8848a9..d3c5e0dbdad 100644
--- a/arch/m68k/include/asm/m54xxsim.h
+++ b/arch/m68k/include/asm/m54xxsim.h
@@ -81,4 +81,7 @@
 #define MCF_PAR_PSC_RTS_RTS     (0x30)
 #define MCF_PAR_PSC_CANRX       (0x40)
 
+#define MCF_PAR_PCIBG           (CONFIG_MBAR + 0xa48)   /* PCI bus grant */
+#define MCF_PAR_PCIBR           (CONFIG_MBAR + 0xa4a)   /* PCI */
+
 #endif  /* m54xxsim_h */
diff --git a/arch/m68k/include/asm/mac_mouse.h b/arch/m68k/include/asm/mac_mouse.h
deleted file mode 100644
index 39a5c292eae..00000000000
--- a/arch/m68k/include/asm/mac_mouse.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef _ASM_MAC_MOUSE_H
-#define _ASM_MAC_MOUSE_H
-
-/*
- * linux/include/asm-m68k/mac_mouse.h
- * header file for Macintosh ADB mouse driver
- * 27-10-97 Michael Schmitz
- * copied from:
- * header file for Atari Mouse driver
- * by Robert de Vries (robert@and.nl) on 19Jul93
- */
-
-struct mouse_status {
-        char            buttons;
-        short           dx;
-        short           dy;
-        int             ready;
-        int             active;
-        wait_queue_head_t wait;
-        struct fasync_struct *fasyncptr;
-};
-
-#endif
diff --git a/arch/m68k/include/asm/mcfne.h b/arch/m68k/include/asm/mcf8390.h
index bf638be0958..a72a20819a5 100644
--- a/arch/m68k/include/asm/mcfne.h
+++ b/arch/m68k/include/asm/mcf8390.h
@@ -1,7 +1,7 @@
 /****************************************************************************/
 
 /*
- *      mcfne.h -- NE2000 in ColdFire eval boards.
+ *      mcf8390.h -- NS8390 support for ColdFire eval boards.
  *
  *      (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com)
  *      (C) Copyright 2000,      Lineo (www.lineo.com)
@@ -14,8 +14,8 @@
  */
 
 /****************************************************************************/
-#ifndef mcfne_h
-#define mcfne_h
+#ifndef mcf8390_h
+#define mcf8390_h
 /****************************************************************************/
 
 
@@ -37,6 +37,7 @@
 #if defined(CONFIG_ARN5206)
 #define NE2000_ADDR             0x40000300
 #define NE2000_ODDOFFSET        0x00010000
+#define NE2000_ADDRSIZE         0x00020000
 #define NE2000_IRQ_VECTOR       0xf0
 #define NE2000_IRQ_PRIORITY     2
 #define NE2000_IRQ_LEVEL        4
@@ -46,6 +47,7 @@
 #if defined(CONFIG_M5206eC3)
 #define NE2000_ADDR             0x40000300
 #define NE2000_ODDOFFSET        0x00010000
+#define NE2000_ADDRSIZE         0x00020000
 #define NE2000_IRQ_VECTOR       0x1c
 #define NE2000_IRQ_PRIORITY     2
 #define NE2000_IRQ_LEVEL        4
@@ -54,6 +56,7 @@
 
 #if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
 #define NE2000_ADDR             0x30000300
+#define NE2000_ADDRSIZE         0x00001000
 #define NE2000_IRQ_VECTOR       25
 #define NE2000_IRQ_PRIORITY     1
 #define NE2000_IRQ_LEVEL        3
@@ -63,6 +66,7 @@
 #if defined(CONFIG_M5307C3)
 #define NE2000_ADDR             0x40000300
 #define NE2000_ODDOFFSET        0x00010000
+#define NE2000_ADDRSIZE         0x00020000
 #define NE2000_IRQ_VECTOR       0x1b
 #define NE2000_BYTE             volatile unsigned short
 #endif
@@ -70,6 +74,7 @@
 #if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
 #define NE2000_ADDR             0x30600300
 #define NE2000_ODDOFFSET        0x00008000
+#define NE2000_ADDRSIZE         0x00010000
 #define NE2000_IRQ_VECTOR       67
 #undef  BSWAP
 #define BSWAP(w)                (w)
@@ -82,6 +87,7 @@
 #define NE2000_ADDR0            0x30600300
 #define NE2000_ADDR1            0x30800300
 #define NE2000_ODDOFFSET        0x00008000
+#define NE2000_ADDRSIZE         0x00010000
 #define NE2000_IRQ_VECTOR0      27
 #define NE2000_IRQ_VECTOR1      29
 #undef  BSWAP
@@ -94,6 +100,7 @@
 #if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3)
 #define NE2000_ADDR             0x30600300
 #define NE2000_ODDOFFSET        0x00008000
+#define NE2000_ADDRSIZE         0x00010000
 #define NE2000_IRQ_VECTOR       27
 #undef  BSWAP
 #define BSWAP(w)                (w)
@@ -105,6 +112,7 @@
 #if defined(CONFIG_ARN5307)
 #define NE2000_ADDR             0xfe600300
 #define NE2000_ODDOFFSET        0x00010000
+#define NE2000_ADDRSIZE         0x00020000
 #define NE2000_IRQ_VECTOR       0x1b
 #define NE2000_IRQ_PRIORITY     2
 #define NE2000_IRQ_LEVEL        3
@@ -114,129 +122,10 @@
 #if defined(CONFIG_M5407C3)
 #define NE2000_ADDR             0x40000300
 #define NE2000_ODDOFFSET        0x00010000
+#define NE2000_ADDRSIZE         0x00020000
 #define NE2000_IRQ_VECTOR       0x1b
 #define NE2000_BYTE             volatile unsigned short
 #endif
 
 /****************************************************************************/
-
-/*
- *      Side-band address space for odd address requires re-mapping
- *      many of the standard ISA access functions.
- */
-#ifdef NE2000_ODDOFFSET
-
-#undef outb
-#undef outb_p
-#undef inb
-#undef inb_p
-#undef outsb
-#undef outsw
-#undef insb
-#undef insw
-
-#define outb    ne2000_outb
-#define inb     ne2000_inb
-#define outb_p  ne2000_outb
-#define inb_p   ne2000_inb
-#define outsb   ne2000_outsb
-#define outsw   ne2000_outsw
-#define insb    ne2000_insb
-#define insw    ne2000_insw
-
-
-#ifndef COLDFIRE_NE2000_FUNCS
-
-void ne2000_outb(unsigned int val, unsigned int addr);
-int  ne2000_inb(unsigned int addr);
-void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len);
-void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len);
-void ne2000_outsb(unsigned int addr, void *vbuf, unsigned long len);
-void ne2000_outsw(unsigned int addr, void *vbuf, unsigned long len);
-
-#else
-
-/*
- *      This macro converts a conventional register address into the
- *      real memory pointer of the mapped NE2000 device.
- *      On most NE2000 implementations on ColdFire boards the chip is
- *      mapped in kinda funny, due to its ISA heritage.
- */
-#define NE2000_PTR(addr)        ((addr&0x1)?(NE2000_ODDOFFSET+addr-1):(addr))
-#define NE2000_DATA_PTR(addr)   (addr)
-
-
-void ne2000_outb(unsigned int val, unsigned int addr)
-{
-        NE2000_BYTE     *rp;
-
-        rp = (NE2000_BYTE *) NE2000_PTR(addr);
-        *rp = RSWAP(val);
-}
-
-int ne2000_inb(unsigned int addr)
-{
-        NE2000_BYTE     *rp, val;
-
-        rp = (NE2000_BYTE *) NE2000_PTR(addr);
-        val = *rp;
-        return((int) ((NE2000_BYTE) RSWAP(val)));
-}
-
-void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len)
-{
-        NE2000_BYTE     *rp, val;
-        unsigned char   *buf;
-
-        buf = (unsigned char *) vbuf;
-        rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
-        for (; (len > 0); len--) {
-                val = *rp;
-                *buf++ = RSWAP(val);
-        }
-}
-
-void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len)
-{
-        volatile unsigned short *rp;
-        unsigned short          w, *buf;
-
-        buf = (unsigned short *) vbuf;
-        rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
-        for (; (len > 0); len--) {
-                w = *rp;
-                *buf++ = BSWAP(w);
-        }
-}
-
-void ne2000_outsb(unsigned int addr, const void *vbuf, unsigned long len)
-{
-        NE2000_BYTE     *rp, val;
-        unsigned char   *buf;
-
-        buf = (unsigned char *) vbuf;
-        rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr);
-        for (; (len > 0); len--) {
-                val = *buf++;
-                *rp = RSWAP(val);
-        }
-}
-
-void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len)
-{
-        volatile unsigned short *rp;
-        unsigned short          w, *buf;
-
-        buf = (unsigned short *) vbuf;
-        rp = (volatile unsigned short *) NE2000_DATA_PTR(addr);
-        for (; (len > 0); len--) {
-                w = *buf++;
-                *rp = BSWAP(w);
-        }
-}
-
-#endif /* COLDFIRE_NE2000_FUNCS */
-#endif /* NE2000_OFFOFFSET */
-
-/****************************************************************************/
-#endif  /* mcfne_h */
+#endif  /* mcf8390_h */
diff --git a/arch/m68k/include/asm/mcfclk.h b/arch/m68k/include/asm/mcfclk.h
new file mode 100644
index 00000000000..b676a02bb39
--- /dev/null
+++ b/arch/m68k/include/asm/mcfclk.h
@@ -0,0 +1,43 @@
+/*
+ * mcfclk.h -- coldfire specific clock structure
+ */
+
+
+#ifndef mcfclk_h
+#define mcfclk_h
+
+struct clk;
+
+#ifdef MCFPM_PPMCR0
+struct clk_ops {
+        void (*enable)(struct clk *);
+        void (*disable)(struct clk *);
+};
+
+struct clk {
+        const char *name;
+        struct clk_ops *clk_ops;
+        unsigned long rate;
+        unsigned long enabled;
+        u8 slot;
+};
+
+extern struct clk *mcf_clks[];
+extern struct clk_ops clk_ops0;
+#ifdef MCFPM_PPMCR1
+extern struct clk_ops clk_ops1;
+#endif /* MCFPM_PPMCR1 */
+
+#define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
+static struct clk __clk_##clk_bank##_##clk_slot = { \
+        .name = clk_name, \
+        .clk_ops = &clk_ops##clk_bank, \
+        .rate = clk_rate, \
+        .slot = clk_slot, \
+}
+
+void __clk_init_enabled(struct clk *);
+void __clk_init_disabled(struct clk *);
+#endif /* MCFPM_PPMCR0 */
+
+#endif /* mcfclk_h */
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
index fe468eaa51e..fa1059f50df 100644
--- a/arch/m68k/include/asm/mcfgpio.h
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -16,82 +16,289 @@
 #ifndef mcfgpio_h
 #define mcfgpio_h
 
-#include <linux/io.h>
+#ifdef CONFIG_GPIOLIB
 #include <asm-generic/gpio.h>
+#else
+
+int __mcfgpio_get_value(unsigned gpio);
+void __mcfgpio_set_value(unsigned gpio, int value);
+int __mcfgpio_direction_input(unsigned gpio);
+int __mcfgpio_direction_output(unsigned gpio, int value);
+int __mcfgpio_request(unsigned gpio);
+void __mcfgpio_free(unsigned gpio);
+
+/* our alternate 'gpiolib' functions */
+static inline int __gpio_get_value(unsigned gpio)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                return __mcfgpio_get_value(gpio);
+        else
+                return -EINVAL;
+}
+
+static inline void __gpio_set_value(unsigned gpio, int value)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                __mcfgpio_set_value(gpio, value);
+}
+
+static inline int __gpio_cansleep(unsigned gpio)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                return 0;
+        else
+                return -EINVAL;
+}
+
+static inline int __gpio_to_irq(unsigned gpio)
+{
+        return -EINVAL;
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                return __mcfgpio_direction_input(gpio);
+        else
+                return -EINVAL;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                return __mcfgpio_direction_output(gpio, value);
+        else
+                return -EINVAL;
+}
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                return __mcfgpio_request(gpio);
+        else
+                return -EINVAL;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+        if (gpio < MCFGPIO_PIN_MAX)
+                __mcfgpio_free(gpio);
+}
+
+#endif /* CONFIG_GPIOLIB */
 
-struct mcf_gpio_chip {
-        struct gpio_chip gpio_chip;
-        void __iomem *pddr;
-        void __iomem *podr;
-        void __iomem *ppdr;
-        void __iomem *setr;
-        void __iomem *clrr;
-        const u8 *gpio_to_pinmux;
-};
-
-extern struct mcf_gpio_chip mcf_gpio_chips[];
-extern unsigned int mcf_gpio_chips_size;
-
-int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
-int mcf_gpio_get_value(struct gpio_chip *, unsigned);
-int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
-void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);
-void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
-int mcf_gpio_request(struct gpio_chip *, unsigned);
-void mcf_gpio_free(struct gpio_chip *, unsigned);
 
 /*
- *      Define macros to ease the pain of setting up the GPIO tables. There
- *      are two cases we need to deal with here, they cover all currently
- *      available ColdFire GPIO hardware. There are of course minor differences
- *      in the layout and number of bits in each ColdFire part, but the macros
- *      take all that in.
+ * The Freescale Coldfire family is quite varied in how they implement GPIO.
+ * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
+ * only one port, others have multiple ports; some have a single data latch
+ * for both input and output, others have a separate pin data register to read
+ * input; some require a read-modify-write access to change an output, others
+ * have set and clear registers for some of the outputs; Some have all the
+ * GPIOs in a single control area, others have some GPIOs implemented in
+ * different modules.
  *
- *      Firstly is the conventional GPIO registers where we toggle individual
- *      bits in a register, preserving the other bits in the register. For
- *      lack of a better term I have called this the slow method.
+ * This implementation attempts accommodate the differences while presenting
+ * a generic interface that will optimize to as few instructions as possible.
+ */
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+    defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+    defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
+    defined(CONFIG_M5441x)
+
+/* These parts have GPIO organized by 8 bit ports */
+
+#define MCFGPIO_PORTTYPE                u8
+#define MCFGPIO_PORTSIZE                8
+#define mcfgpio_read(port)              __raw_readb(port)
+#define mcfgpio_write(data, port)       __raw_writeb(data, port)
+
+#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
+
+/* These parts have GPIO organized by 16 bit ports */
+
+#define MCFGPIO_PORTTYPE                u16
+#define MCFGPIO_PORTSIZE                16
+#define mcfgpio_read(port)              __raw_readw(port)
+#define mcfgpio_write(data, port)       __raw_writew(data, port)
+
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+
+/* These parts have GPIO organized by 32 bit ports */
+
+#define MCFGPIO_PORTTYPE                u32
+#define MCFGPIO_PORTSIZE                32
+#define mcfgpio_read(port)              __raw_readl(port)
+#define mcfgpio_write(data, port)       __raw_writel(data, port)
+
+#endif
+
+#define mcfgpio_bit(gpio)               (1 << ((gpio) %  MCFGPIO_PORTSIZE))
+#define mcfgpio_port(gpio)              ((gpio) / MCFGPIO_PORTSIZE)
+
+#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+    defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+    defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+/*
+ * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
+ * read-modify-write to change an output and a GPIO module which has separate
+ * set/clr registers to directly change outputs with a single write access.
+ */
+#if defined(CONFIG_M528x)
+/*
+ * The 528x also has GPIOs in other modules (GPT, QADC) which use
+ * read-modify-write as well as those controlled by the EPORT and GPIO modules.
  */
-#define MCFGPS(mlabel, mbase, mngpio, mpddr, mpodr, mppdr)                  \
-        {                                                                   \
-                .gpio_chip                      = {                         \
-                        .label                  = #mlabel,                  \
-                        .request                = mcf_gpio_request,         \
-                        .free                   = mcf_gpio_free,            \
-                        .direction_input        = mcf_gpio_direction_input, \
-                        .direction_output       = mcf_gpio_direction_output,\
-                        .get                    = mcf_gpio_get_value,       \
-                        .set                    = mcf_gpio_set_value,       \
-                        .base                   = mbase,                    \
-                        .ngpio                  = mngpio,                   \
-                },                                                          \
-                .pddr           = (void __iomem *) mpddr,                   \
-                .podr           = (void __iomem *) mpodr,                   \
-                .ppdr           = (void __iomem *) mppdr,                   \
-        }
+#define MCFGPIO_SCR_START               40
+#elif defined(CONFIGM5441x)
+/* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
+#define MCFGPIO_SCR_START               0
+#else
+#define MCFGPIO_SCR_START               8
+#endif
 
+#define MCFGPIO_SETR_PORT(gpio)         (MCFGPIO_SETR + \
+                                        mcfgpio_port(gpio - MCFGPIO_SCR_START))
+
+#define MCFGPIO_CLRR_PORT(gpio)         (MCFGPIO_CLRR + \
+                                        mcfgpio_port(gpio - MCFGPIO_SCR_START))
+#else
+
+#define MCFGPIO_SCR_START               MCFGPIO_PIN_MAX
+/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
+#define MCFGPIO_SETR_PORT(gpio)         0
+#define MCFGPIO_CLRR_PORT(gpio)         0
+
+#endif
 /*
- *      Secondly is the faster case, where we have set and clear registers
- *      that allow us to set or clear a bit with a single write, not having
- *      to worry about preserving other bits.
+ * Coldfire specific helper functions
  */
-#define MCFGPF(mlabel, mbase, mngpio)                                       \
-        {                                                                   \
-                .gpio_chip                      = {                         \
-                        .label                  = #mlabel,                  \
-                        .request                = mcf_gpio_request,         \
-                        .free                   = mcf_gpio_free,            \
-                        .direction_input        = mcf_gpio_direction_input, \
-                        .direction_output       = mcf_gpio_direction_output,\
-                        .get                    = mcf_gpio_get_value,       \
-                        .set                    = mcf_gpio_set_value_fast,  \
-                        .base                   = mbase,                    \
-                        .ngpio                  = mngpio,                   \
-                },                                                          \
-                .pddr           = (void __iomem *) MCFGPIO_PDDR_##mlabel,   \
-                .podr           = (void __iomem *) MCFGPIO_PODR_##mlabel,   \
-                .ppdr           = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
-                .setr           = (void __iomem *) MCFGPIO_PPDSDR_##mlabel, \
-                .clrr           = (void __iomem *) MCFGPIO_PCLRR_##mlabel,  \
-        }
 
+/* return the port pin data register for a gpio */
+static inline u32 __mcfgpio_ppdr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+    defined(CONFIG_M5307) || defined(CONFIG_M5407)
+        return MCFSIM_PADAT;
+#elif defined(CONFIG_M5272)
+        if (gpio < 16)
+                return MCFSIM_PADAT;
+        else if (gpio < 32)
+                return MCFSIM_PBDAT;
+        else
+                return MCFSIM_PCDAT;
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+        if (gpio < 32)
+                return MCFSIM2_GPIOREAD;
+        else
+                return MCFSIM2_GPIO1READ;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+      defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
+        if (gpio < 8)
+                return MCFEPORT_EPPDR;
+#if defined(CONFIG_M528x)
+        else if (gpio < 16)
+                return MCFGPTA_GPTPORT;
+        else if (gpio < 24)
+                return MCFGPTB_GPTPORT;
+        else if (gpio < 32)
+                return MCFQADC_PORTQA;
+        else if (gpio < 40)
+                return MCFQADC_PORTQB;
+#endif /* defined(CONFIG_M528x) */
+        else
+#endif /* !defined(CONFIG_M5441x) */
+                return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+        return 0;
 #endif
+}
+
+/* return the port output data register for a gpio */
+static inline u32 __mcfgpio_podr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+    defined(CONFIG_M5307) || defined(CONFIG_M5407)
+        return MCFSIM_PADAT;
+#elif defined(CONFIG_M5272)
+        if (gpio < 16)
+                return MCFSIM_PADAT;
+        else if (gpio < 32)
+                return MCFSIM_PBDAT;
+        else
+                return MCFSIM_PCDAT;
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+        if (gpio < 32)
+                return MCFSIM2_GPIOWRITE;
+        else
+                return MCFSIM2_GPIO1WRITE;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+      defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
+        if (gpio < 8)
+                return MCFEPORT_EPDR;
+#if defined(CONFIG_M528x)
+        else if (gpio < 16)
+                return MCFGPTA_GPTPORT;
+        else if (gpio < 24)
+                return MCFGPTB_GPTPORT;
+        else if (gpio < 32)
+                return MCFQADC_PORTQA;
+        else if (gpio < 40)
+                return MCFQADC_PORTQB;
+#endif /* defined(CONFIG_M528x) */
+        else
+#endif /* !defined(CONFIG_M5441x) */
+                return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+        return 0;
+#endif
+}
+
+/* return the port direction data register for a gpio */
+static inline u32 __mcfgpio_pddr(unsigned gpio)
+{
+#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
+    defined(CONFIG_M5307) || defined(CONFIG_M5407)
+        return MCFSIM_PADDR;
+#elif defined(CONFIG_M5272)
+        if (gpio < 16)
+                return MCFSIM_PADDR;
+        else if (gpio < 32)
+                return MCFSIM_PBDDR;
+        else
+                return MCFSIM_PCDDR;
+#elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
+        if (gpio < 32)
+                return MCFSIM2_GPIOENABLE;
+        else
+                return MCFSIM2_GPIO1ENABLE;
+#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
+      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+      defined(CONFIG_M532x) || defined(CONFIG_M5441x)
+#if !defined(CONFIG_M5441x)
+        if (gpio < 8)
+                return MCFEPORT_EPDDR;
+#if defined(CONFIG_M528x)
+        else if (gpio < 16)
+                return MCFGPTA_GPTDDR;
+        else if (gpio < 24)
+                return MCFGPTB_GPTDDR;
+        else if (gpio < 32)
+                return MCFQADC_DDRQA;
+        else if (gpio < 40)
+                return MCFQADC_DDRQB;
+#endif /* defined(CONFIG_M528x) */
+        else
+#endif /* !defined(CONFIG_M5441x) */
+                return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
+#else
+        return 0;
+#endif
+}
+
+#endif /* mcfgpio_h */
diff --git a/arch/m68k/include/asm/mcfmbus.h b/arch/m68k/include/asm/mcfmbus.h
deleted file mode 100644
index 319899c47a2..00000000000
--- a/arch/m68k/include/asm/mcfmbus.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/****************************************************************************/
-
-/*
- *      mcfmbus.h -- Coldfire MBUS support defines.
- *
- *      (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de) 
- */
-
-/****************************************************************************/
-
-
-#ifndef mcfmbus_h
-#define mcfmbus_h
-
-
-#define MCFMBUS_BASE            0x280
-#define MCFMBUS_IRQ_VECTOR      0x19
-#define MCFMBUS_IRQ             0x1
-#define MCFMBUS_CLK             0x3f
-#define MCFMBUS_IRQ_LEVEL       0x07    /*IRQ Level 1*/
-#define MCFMBUS_ADDRESS         0x01
-
-
-/*
-*       Define the 5307 MBUS register set addresses
-*/
-
-#define MCFMBUS_MADR    0x00
-#define MCFMBUS_MFDR    0x04
-#define MCFMBUS_MBCR    0x08
-#define MCFMBUS_MBSR    0x0C
-#define MCFMBUS_MBDR    0x10
-
-
-#define MCFMBUS_MADR_ADDR(a)    (((a)&0x7F)<<0x01) /*Slave Address*/
-
-#define MCFMBUS_MFDR_MBC(a)     ((a)&0x3F)         /*M-Bus Clock*/
-
-/*
-*       Define bit flags in Control Register
-*/
-
-#define MCFMBUS_MBCR_MEN           (0x80)  /* M-Bus Enable                 */
-#define MCFMBUS_MBCR_MIEN          (0x40)  /* M-Bus Interrupt Enable       */
-#define MCFMBUS_MBCR_MSTA          (0x20)  /* Master/Slave Mode Select Bit */
-#define MCFMBUS_MBCR_MTX           (0x10)  /* Transmit/Rcv Mode Select Bit */
-#define MCFMBUS_MBCR_TXAK          (0x08)  /* Transmit Acknowledge Enable  */
-#define MCFMBUS_MBCR_RSTA          (0x04)  /* Repeat Start                 */
-
-/*
-*       Define bit flags in Status Register
-*/
-
-#define MCFMBUS_MBSR_MCF           (0x80)  /* Data Transfer Complete       */
-#define MCFMBUS_MBSR_MAAS          (0x40)  /* Addressed as a Slave         */
-#define MCFMBUS_MBSR_MBB           (0x20)  /* Bus Busy                     */
-#define MCFMBUS_MBSR_MAL           (0x10)  /* Arbitration Lost             */
-#define MCFMBUS_MBSR_SRW           (0x04)  /* Slave Transmit               */
-#define MCFMBUS_MBSR_MIF           (0x02)  /* M-Bus Interrupt              */
-#define MCFMBUS_MBSR_RXAK          (0x01)  /* No Acknowledge Received      */
-
-/*
-*       Define bit flags in DATA I/O Register
-*/
-
-#define MCFMBUS_MBDR_READ          (0x01)  /* 1=read 0=write MBUS */
-
-#define MBUSIOCSCLOCK           1
-#define MBUSIOCGCLOCK           2
-#define MBUSIOCSADDR                    3
-#define MBUSIOCGADDR                    4
-#define MBUSIOCSSLADDR                  5
-#define MBUSIOCGSLADDR                  6
-#define MBUSIOCSSUBADDR                 7
-#define MBUSIOCGSUBADDR                 8
-
-#endif
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index ebd0304054a..7a83e619e73 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -27,6 +27,9 @@
 #elif defined(CONFIG_M5249)
 #include <asm/m5249sim.h>
 #include <asm/mcfintc.h>
+#elif defined(CONFIG_M525x)
+#include <asm/m525xsim.h>
+#include <asm/mcfintc.h>
 #elif defined(CONFIG_M527x)
 #include <asm/m527xsim.h>
 #elif defined(CONFIG_M5272)
@@ -43,6 +46,8 @@
 #include <asm/mcfintc.h>
 #elif defined(CONFIG_M54xx)
 #include <asm/m54xxsim.h>
+#elif defined(CONFIG_M5441x)
+#include <asm/m5441xsim.h>
 #endif
 
 /****************************************************************************/
diff --git a/arch/m68k/include/asm/mcftimer.h b/arch/m68k/include/asm/mcftimer.h
index 351c2723787..da2fa43c2e4 100644
--- a/arch/m68k/include/asm/mcftimer.h
+++ b/arch/m68k/include/asm/mcftimer.h
@@ -19,7 +19,7 @@
 #define MCFTIMER_TRR            0x04            /* Timer Reference (r/w) */
 #define MCFTIMER_TCR            0x08            /* Timer Capture reg (r/w) */
 #define MCFTIMER_TCN            0x0C            /* Timer Counter reg (r/w) */
-#if defined(CONFIG_M532x)
+#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
 #define MCFTIMER_TER            0x03            /* Timer Event reg (r/w) */
 #else
 #define MCFTIMER_TER            0x11            /* Timer Event reg (r/w) */
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 2d3bc774b3c..b40c20f6664 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -43,8 +43,8 @@ struct mcf_platform_uart {
 #define MCFUART_UFPD            0x30            /* Frac Prec. Divider (r/w) */
 #endif
 #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
-        defined(CONFIG_M5249) || defined(CONFIG_M5307) || \
-        defined(CONFIG_M5407)
+        defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
+        defined(CONFIG_M5307) || defined(CONFIG_M5407)
 #define MCFUART_UIVR            0x30            /* Interrupt Vector (r/w) */
 #endif
 #define MCFUART_UIPR            0x34            /* Input Port (r) */
diff --git a/arch/m68k/include/asm/mman.h b/arch/m68k/include/asm/mman.h
deleted file mode 100644
index 8eebf89f5ab..00000000000
--- a/arch/m68k/include/asm/mman.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/mman.h>
diff --git a/arch/m68k/include/asm/mutex.h b/arch/m68k/include/asm/mutex.h
deleted file mode 100644
index 458c1f7fbc1..00000000000
--- a/arch/m68k/include/asm/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/arch/m68k/include/asm/pci.h b/arch/m68k/include/asm/pci.h
index 4ad0aea48ab..848c3dfaad5 100644
--- a/arch/m68k/include/asm/pci.h
+++ b/arch/m68k/include/asm/pci.h
@@ -2,6 +2,7 @@
 #define _ASM_M68K_PCI_H
 
 #include <asm-generic/pci-dma-compat.h>
+#include <asm-generic/pci.h>
 
 /* The PCI address space does equal the physical memory
  * address space.  The networking and block device layers use
@@ -9,4 +10,9 @@
  */
 #define PCI_DMA_BUS_IS_PHYS     (1)
 
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0x00000100
+#define PCIBIOS_MIN_MEM         0x02000000
+
 #endif /* _ASM_M68K_PCI_H */
diff --git a/arch/m68k/include/asm/percpu.h b/arch/m68k/include/asm/percpu.h
deleted file mode 100644
index 0859d048faf..00000000000
--- a/arch/m68k/include/asm/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_M68K_PERCPU_H
-#define __ASM_M68K_PERCPU_H
-
-#include <asm-generic/percpu.h>
-
-#endif  /* __ASM_M68K_PERCPU_H */
diff --git a/arch/m68k/include/asm/pinmux.h b/arch/m68k/include/asm/pinmux.h
deleted file mode 100644
index 119ee686dbd..00000000000
--- a/arch/m68k/include/asm/pinmux.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Coldfire generic GPIO pinmux support.
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef pinmux_h
-#define pinmux_h
-
-#define MCFPINMUX_NONE          -1
-
-extern int mcf_pinmux_request(unsigned, unsigned);
-extern void mcf_pinmux_release(unsigned, unsigned);
-
-static inline int mcf_pinmux_is_valid(unsigned pinmux)
-{
-        return pinmux != MCFPINMUX_NONE;
-}
-
-#endif
-
diff --git a/arch/m68k/include/asm/resource.h b/arch/m68k/include/asm/resource.h
deleted file mode 100644
index e7d35019f33..00000000000
--- a/arch/m68k/include/asm/resource.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _M68K_RESOURCE_H
-#define _M68K_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif /* _M68K_RESOURCE_H */
diff --git a/arch/m68k/include/asm/sbus.h b/arch/m68k/include/asm/sbus.h
deleted file mode 100644
index bfe3ba147f2..00000000000
--- a/arch/m68k/include/asm/sbus.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * some sbus structures and macros to make usage of sbus drivers possible
- */
-
-#ifndef __M68K_SBUS_H
-#define __M68K_SBUS_H
-
-struct sbus_dev {
-        struct {
-                unsigned int which_io;
-                unsigned int phys_addr;
-        } reg_addrs[1];
-};
-
-/* sbus IO functions stolen from include/asm-sparc/io.h for the serial driver */
-/* No SBUS on the Sun3, kludge -- sam */
-
-static inline void _sbus_writeb(unsigned char val, unsigned long addr)
-{
-        *(volatile unsigned char *)addr = val;
-}
-
-static inline unsigned char _sbus_readb(unsigned long addr)
-{
-        return *(volatile unsigned char *)addr;
-}
-
-static inline void _sbus_writel(unsigned long val, unsigned long addr)
-{
-        *(volatile unsigned long *)addr = val;
-
-}
-
-extern inline unsigned long _sbus_readl(unsigned long addr)
-{
-        return *(volatile unsigned long *)addr;
-}
-
-
-#define sbus_readb(a) _sbus_readb((unsigned long)a)
-#define sbus_writeb(v, a) _sbus_writeb(v, (unsigned long)a)
-#define sbus_readl(a) _sbus_readl((unsigned long)a)
-#define sbus_writel(v, a) _sbus_writel(v, (unsigned long)a)
-
-#endif
diff --git a/arch/m68k/include/asm/scatterlist.h b/arch/m68k/include/asm/scatterlist.h
deleted file mode 100644
index 312505452a1..00000000000
--- a/arch/m68k/include/asm/scatterlist.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _M68K_SCATTERLIST_H
-#define _M68K_SCATTERLIST_H
-
-#include <asm-generic/scatterlist.h>
-
-#endif /* !(_M68K_SCATTERLIST_H) */
diff --git a/arch/m68k/include/asm/sections.h b/arch/m68k/include/asm/sections.h
deleted file mode 100644
index 5277e52715e..00000000000
--- a/arch/m68k/include/asm/sections.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _ASM_M68K_SECTIONS_H
-#define _ASM_M68K_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-extern char _sbss[], _ebss[];
-
-#endif /* _ASM_M68K_SECTIONS_H */
diff --git a/arch/m68k/include/asm/shm.h b/arch/m68k/include/asm/shm.h
deleted file mode 100644
index fa56ec84a12..00000000000
--- a/arch/m68k/include/asm/shm.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _M68K_SHM_H
-#define _M68K_SHM_H
-
-
-/* format of page table entries that correspond to shared memory pages
-   currently out in swap space (see also mm/swap.c):
-   bits 0-1 (PAGE_PRESENT) is  = 0
-   bits 8..2 (SWP_TYPE) are = SHM_SWP_TYPE
-   bits 31..9 are used like this:
-   bits 15..9 (SHM_ID) the id of the shared memory segment
-   bits 30..16 (SHM_IDX) the index of the page within the shared memory segment
-                    (actually only bits 25..16 get used since SHMMAX is so low)
-   bit 31 (SHM_READ_ONLY) flag whether the page belongs to a read-only attach
-*/
-/* on the m68k both bits 0 and 1 must be zero */
-/* format on the sun3 is similar, but bits 30, 31 are set to zero and all
-   others are reduced by 2. --m */
-
-#ifndef CONFIG_SUN3
-#define SHM_ID_SHIFT    9
-#else
-#define SHM_ID_SHIFT    7
-#endif
-#define _SHM_ID_BITS    7
-#define SHM_ID_MASK     ((1<<_SHM_ID_BITS)-1)
-
-#define SHM_IDX_SHIFT   (SHM_ID_SHIFT+_SHM_ID_BITS)
-#define _SHM_IDX_BITS   15
-#define SHM_IDX_MASK    ((1<<_SHM_IDX_BITS)-1)
-
-#endif /* _M68K_SHM_H */
diff --git a/arch/m68k/include/asm/siginfo.h b/arch/m68k/include/asm/siginfo.h
deleted file mode 100644
index 851d3d784b5..00000000000
--- a/arch/m68k/include/asm/siginfo.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _M68K_SIGINFO_H
-#define _M68K_SIGINFO_H
-
-#include <asm-generic/siginfo.h>
-
-#endif
diff --git a/arch/m68k/include/asm/statfs.h b/arch/m68k/include/asm/statfs.h
deleted file mode 100644
index 08d93f14e06..00000000000
--- a/arch/m68k/include/asm/statfs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _M68K_STATFS_H
-#define _M68K_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif /* _M68K_STATFS_H */
diff --git a/arch/m68k/include/asm/topology.h b/arch/m68k/include/asm/topology.h
deleted file mode 100644
index ca173e9f26f..00000000000
--- a/arch/m68k/include/asm/topology.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_M68K_TOPOLOGY_H
-#define _ASM_M68K_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_M68K_TOPOLOGY_H */
diff --git a/arch/m68k/include/asm/types.h b/arch/m68k/include/asm/types.h
deleted file mode 100644
index 89705adcbd5..00000000000
--- a/arch/m68k/include/asm/types.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _M68K_TYPES_H
-#define _M68K_TYPES_H
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue.  However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-#include <asm-generic/int-ll64.h>
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-#endif /* __KERNEL__ */
-
-#endif /* _M68K_TYPES_H */
diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h
index f4043ae63db..2b3ca0bf7a0 100644
--- a/arch/m68k/include/asm/unaligned.h
+++ b/arch/m68k/include/asm/unaligned.h
@@ -2,7 +2,7 @@
 #define _ASM_M68K_UNALIGNED_H
 
 
-#if defined(CONFIG_COLDFIRE) || defined(CONFIG_M68000)
+#ifdef CONFIG_CPU_HAS_NO_UNALIGNED
 #include <linux/unaligned/be_struct.h>
 #include <linux/unaligned/le_byteshift.h>
 #include <linux/unaligned/generic.h>
@@ -12,7 +12,7 @@
 
 #else
 /*
- * The m68k can do unaligned accesses itself. 
+ * The m68k can do unaligned accesses itself.
  */
 #include <linux/unaligned/access_ok.h>
 #include <linux/unaligned/generic.h>
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index ea0b502f845..045cfd6a9e3 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -357,7 +357,6 @@
 
 #define NR_syscalls             347
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_OLD_STAT
 #define __ARCH_WANT_STAT64
diff --git a/arch/m68k/include/asm/xor.h b/arch/m68k/include/asm/xor.h
deleted file mode 100644
index c82eb12a5b1..00000000000
--- a/arch/m68k/include/asm/xor.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/xor.h>
diff --git a/arch/m68k/kernel/Makefile b/arch/m68k/kernel/Makefile
index 5c7070e21eb..068ad49210d 100644
--- a/arch/m68k/kernel/Makefile
+++ b/arch/m68k/kernel/Makefile
@@ -18,6 +18,7 @@ obj-y	+= setup.o signal.o sys_m68k.o syscalltable.o time.o traps.o
 
 obj-$(CONFIG_MMU_MOTOROLA) += ints.o vectors.o
 obj-$(CONFIG_MMU_SUN3) += ints.o vectors.o
+obj-$(CONFIG_PCI) += pcibios.o
 
 ifndef CONFIG_MMU_SUN3
 obj-y   += dma.o
diff --git a/arch/m68k/kernel/dma.c b/arch/m68k/kernel/dma.c
index f6daf6e15d2..e546a5534dd 100644
--- a/arch/m68k/kernel/dma.c
+++ b/arch/m68k/kernel/dma.c
@@ -16,7 +16,7 @@
 
 #include <asm/pgalloc.h>
 
-#ifdef CONFIG_MMU
+#if defined(CONFIG_MMU) && !defined(CONFIG_COLDFIRE)
 
 void *dma_alloc_coherent(struct device *dev, size_t size,
                          dma_addr_t *handle, gfp_t flag)
@@ -96,7 +96,7 @@ void dma_free_coherent(struct device *dev, size_t size,
         free_pages((unsigned long)vaddr, get_order(size));
 }
 
-#endif /* CONFIG_MMU */
+#endif /* CONFIG_MMU && !CONFIG_COLDFIRE */
 
 EXPORT_SYMBOL(dma_alloc_coherent);
 EXPORT_SYMBOL(dma_free_coherent);
@@ -105,6 +105,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t handle,
                                 size_t size, enum dma_data_direction dir)
 {
         switch (dir) {
+        case DMA_BIDIRECTIONAL:
         case DMA_TO_DEVICE:
                 cache_push(handle, size);
                 break;
diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S
index b8daf64e347..165ee9f9d5c 100644
--- a/arch/m68k/kernel/entry.S
+++ b/arch/m68k/kernel/entry.S
@@ -1,5 +1,451 @@
-#if defined(CONFIG_MMU) && !defined(CONFIG_COLDFIRE)
-#include "entry_mm.S"
+/* -*- mode: asm -*-
+ *
+ *  linux/arch/m68k/kernel/entry.S
+ *
+ *  Copyright (C) 1991, 1992  Linus Torvalds
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file README.legal in the main directory of this archive
+ * for more details.
+ *
+ * Linux/m68k support by Hamish Macdonald
+ *
+ * 68060 fixes by Jesper Skov
+ *
+ */
+
+/*
+ * entry.S  contains the system-call and fault low-level handling routines.
+ * This also contains the timer-interrupt handler, as well as all interrupts
+ * and faults that can result in a task-switch.
+ *
+ * NOTE: This code handles signal-recognition, which happens every time
+ * after a timer-interrupt and after each system call.
+ *
+ */
+
+/*
+ * 12/03/96 Jes: Currently we only support m68k single-cpu systems, so
+ *               all pointers that used to be 'current' are now entry
+ *               number 0 in the 'current_set' list.
+ *
+ *  6/05/00 RZ:  addedd writeback completion after return from sighandler
+ *               for 68040
+ */
+
+#include <linux/linkage.h>
+#include <asm/errno.h>
+#include <asm/setup.h>
+#include <asm/segment.h>
+#include <asm/traps.h>
+#include <asm/unistd.h>
+#include <asm/asm-offsets.h>
+#include <asm/entry.h>
+
+.globl system_call, buserr, trap, resume
+.globl sys_call_table
+.globl sys_fork, sys_clone, sys_vfork
+.globl ret_from_interrupt, bad_interrupt
+.globl auto_irqhandler_fixup
+.globl user_irqvec_fixup
+
+.text
+ENTRY(sys_fork)
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        jbsr    m68k_fork
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_clone)
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        jbsr    m68k_clone
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_vfork)
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        jbsr    m68k_vfork
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_sigreturn)
+        SAVE_SWITCH_STACK
+        jbsr    do_sigreturn
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(sys_rt_sigreturn)
+        SAVE_SWITCH_STACK
+        jbsr    do_rt_sigreturn
+        RESTORE_SWITCH_STACK
+        rts
+
+ENTRY(buserr)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        movel   %sp,%sp@-               | stack frame pointer argument
+        jbsr    buserr_c
+        addql   #4,%sp
+        jra     ret_from_exception
+
+ENTRY(trap)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        movel   %sp,%sp@-               | stack frame pointer argument
+        jbsr    trap_c
+        addql   #4,%sp
+        jra     ret_from_exception
+
+        | After a fork we jump here directly from resume,
+        | so that %d1 contains the previous task
+        | schedule_tail now used regardless of CONFIG_SMP
+ENTRY(ret_from_fork)
+        movel   %d1,%sp@-
+        jsr     schedule_tail
+        addql   #4,%sp
+        jra     ret_from_exception
+
+#if defined(CONFIG_COLDFIRE) || !defined(CONFIG_MMU)
+
+#ifdef TRAP_DBG_INTERRUPT
+
+.globl dbginterrupt
+ENTRY(dbginterrupt)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        movel   %sp,%sp@-               /* stack frame pointer argument */
+        jsr     dbginterrupt_c
+        addql   #4,%sp
+        jra     ret_from_exception
+#endif
+
+ENTRY(reschedule)
+        /* save top of frame */
+        pea     %sp@
+        jbsr    set_esp0
+        addql   #4,%sp
+        pea     ret_from_exception
+        jmp     schedule
+
+ENTRY(ret_from_user_signal)
+        moveq #__NR_sigreturn,%d0
+        trap #0
+
+ENTRY(ret_from_user_rt_signal)
+        movel #__NR_rt_sigreturn,%d0
+        trap #0
+
 #else
-#include "entry_no.S"
+
+do_trace_entry:
+        movel   #-ENOSYS,%sp@(PT_OFF_D0)| needed for strace
+        subql   #4,%sp
+        SAVE_SWITCH_STACK
+        jbsr    syscall_trace
+        RESTORE_SWITCH_STACK
+        addql   #4,%sp
+        movel   %sp@(PT_OFF_ORIG_D0),%d0
+        cmpl    #NR_syscalls,%d0
+        jcs     syscall
+badsys:
+        movel   #-ENOSYS,%sp@(PT_OFF_D0)
+        jra     ret_from_syscall
+
+do_trace_exit:
+        subql   #4,%sp
+        SAVE_SWITCH_STACK
+        jbsr    syscall_trace
+        RESTORE_SWITCH_STACK
+        addql   #4,%sp
+        jra     .Lret_from_exception
+
+ENTRY(ret_from_signal)
+        movel   %curptr@(TASK_STACK),%a1
+        tstb    %a1@(TINFO_FLAGS+2)
+        jge     1f
+        jbsr    syscall_trace
+1:      RESTORE_SWITCH_STACK
+        addql   #4,%sp
+/* on 68040 complete pending writebacks if any */
+#ifdef CONFIG_M68040
+        bfextu  %sp@(PT_OFF_FORMATVEC){#0,#4},%d0
+        subql   #7,%d0                          | bus error frame ?
+        jbne    1f
+        movel   %sp,%sp@-
+        jbsr    berr_040cleanup
+        addql   #4,%sp
+1:
+#endif
+        jra     .Lret_from_exception
+
+ENTRY(system_call)
+        SAVE_ALL_SYS
+
+        GET_CURRENT(%d1)
+        movel   %d1,%a1
+
+        | save top of frame
+        movel   %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
+
+        | syscall trace?
+        tstb    %a1@(TINFO_FLAGS+2)
+        jmi     do_trace_entry
+        cmpl    #NR_syscalls,%d0
+        jcc     badsys
+syscall:
+        jbsr    @(sys_call_table,%d0:l:4)@(0)
+        movel   %d0,%sp@(PT_OFF_D0)     | save the return value
+ret_from_syscall:
+        |oriw   #0x0700,%sr
+        movel   %curptr@(TASK_STACK),%a1
+        movew   %a1@(TINFO_FLAGS+2),%d0
+        jne     syscall_exit_work
+1:      RESTORE_ALL
+
+syscall_exit_work:
+        btst    #5,%sp@(PT_OFF_SR)      | check if returning to kernel
+        bnes    1b                      | if so, skip resched, signals
+        lslw    #1,%d0
+        jcs     do_trace_exit
+        jmi     do_delayed_trace
+        lslw    #8,%d0
+        jne     do_signal_return
+        pea     resume_userspace
+        jra     schedule
+
+
+ENTRY(ret_from_exception)
+.Lret_from_exception:
+        btst    #5,%sp@(PT_OFF_SR)      | check if returning to kernel
+        bnes    1f                      | if so, skip resched, signals
+        | only allow interrupts when we are really the last one on the
+        | kernel stack, otherwise stack overflow can occur during
+        | heavy interrupt load
+        andw    #ALLOWINT,%sr
+
+resume_userspace:
+        movel   %curptr@(TASK_STACK),%a1
+        moveb   %a1@(TINFO_FLAGS+3),%d0
+        jne     exit_work
+1:      RESTORE_ALL
+
+exit_work:
+        | save top of frame
+        movel   %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
+        lslb    #1,%d0
+        jne     do_signal_return
+        pea     resume_userspace
+        jra     schedule
+
+
+do_signal_return:
+        |andw   #ALLOWINT,%sr
+        subql   #4,%sp                  | dummy return address
+        SAVE_SWITCH_STACK
+        pea     %sp@(SWITCH_STACK_SIZE)
+        bsrl    do_notify_resume
+        addql   #4,%sp
+        RESTORE_SWITCH_STACK
+        addql   #4,%sp
+        jbra    resume_userspace
+
+do_delayed_trace:
+        bclr    #7,%sp@(PT_OFF_SR)      | clear trace bit in SR
+        pea     1                       | send SIGTRAP
+        movel   %curptr,%sp@-
+        pea     LSIGTRAP
+        jbsr    send_sig
+        addql   #8,%sp
+        addql   #4,%sp
+        jbra    resume_userspace
+
+
+/* This is the main interrupt handler for autovector interrupts */
+
+ENTRY(auto_inthandler)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        movel   %d0,%a1
+        addqb   #1,%a1@(TINFO_PREEMPT+1)
+                                        |  put exception # in d0
+        bfextu  %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
+        subw    #VEC_SPUR,%d0
+
+        movel   %sp,%sp@-
+        movel   %d0,%sp@-               |  put vector # on stack
+auto_irqhandler_fixup = . + 2
+        jsr     do_IRQ                  |  process the IRQ
+        addql   #8,%sp                  |  pop parameters off stack
+
+ret_from_interrupt:
+        movel   %curptr@(TASK_STACK),%a1
+        subqb   #1,%a1@(TINFO_PREEMPT+1)
+        jeq     ret_from_last_interrupt
+2:      RESTORE_ALL
+
+        ALIGN
+ret_from_last_interrupt:
+        moveq   #(~ALLOWINT>>8)&0xff,%d0
+        andb    %sp@(PT_OFF_SR),%d0
+        jne     2b
+
+        /* check if we need to do software interrupts */
+        tstl    irq_stat+CPUSTAT_SOFTIRQ_PENDING
+        jeq     .Lret_from_exception
+        pea     ret_from_exception
+        jra     do_softirq
+
+/* Handler for user defined interrupt vectors */
+
+ENTRY(user_inthandler)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        movel   %d0,%a1
+        addqb   #1,%a1@(TINFO_PREEMPT+1)
+                                        |  put exception # in d0
+        bfextu  %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
+user_irqvec_fixup = . + 2
+        subw    #VEC_USER,%d0
+
+        movel   %sp,%sp@-
+        movel   %d0,%sp@-               |  put vector # on stack
+        jsr     do_IRQ                  |  process the IRQ
+        addql   #8,%sp                  |  pop parameters off stack
+
+        movel   %curptr@(TASK_STACK),%a1
+        subqb   #1,%a1@(TINFO_PREEMPT+1)
+        jeq     ret_from_last_interrupt
+        RESTORE_ALL
+
+/* Handler for uninitialized and spurious interrupts */
+
+ENTRY(bad_inthandler)
+        SAVE_ALL_INT
+        GET_CURRENT(%d0)
+        movel   %d0,%a1
+        addqb   #1,%a1@(TINFO_PREEMPT+1)
+
+        movel   %sp,%sp@-
+        jsr     handle_badint
+        addql   #4,%sp
+
+        movel   %curptr@(TASK_STACK),%a1
+        subqb   #1,%a1@(TINFO_PREEMPT+1)
+        jeq     ret_from_last_interrupt
+        RESTORE_ALL
+
+
+resume:
+        /*
+         * Beware - when entering resume, prev (the current task) is
+         * in a0, next (the new task) is in a1,so don't change these
+         * registers until their contents are no longer needed.
+         */
+
+        /* save sr */
+        movew   %sr,%a0@(TASK_THREAD+THREAD_SR)
+
+        /* save fs (sfc,%dfc) (may be pointing to kernel memory) */
+        movec   %sfc,%d0
+        movew   %d0,%a0@(TASK_THREAD+THREAD_FS)
+
+        /* save usp */
+        /* it is better to use a movel here instead of a movew 8*) */
+        movec   %usp,%d0
+        movel   %d0,%a0@(TASK_THREAD+THREAD_USP)
+
+        /* save non-scratch registers on stack */
+        SAVE_SWITCH_STACK
+
+        /* save current kernel stack pointer */
+        movel   %sp,%a0@(TASK_THREAD+THREAD_KSP)
+
+        /* save floating point context */
+#ifndef CONFIG_M68KFPU_EMU_ONLY
+#ifdef CONFIG_M68KFPU_EMU
+        tstl    m68k_fputype
+        jeq     3f
+#endif
+        fsave   %a0@(TASK_THREAD+THREAD_FPSTATE)
+
+#if defined(CONFIG_M68060)
+#if !defined(CPU_M68060_ONLY)
+        btst    #3,m68k_cputype+3
+        beqs    1f
+#endif
+        /* The 060 FPU keeps status in bits 15-8 of the first longword */
+        tstb    %a0@(TASK_THREAD+THREAD_FPSTATE+2)
+        jeq     3f
+#if !defined(CPU_M68060_ONLY)
+        jra     2f
+#endif
+#endif /* CONFIG_M68060 */
+#if !defined(CPU_M68060_ONLY)
+1:      tstb    %a0@(TASK_THREAD+THREAD_FPSTATE)
+        jeq     3f
+#endif
+2:      fmovemx %fp0-%fp7,%a0@(TASK_THREAD+THREAD_FPREG)
+        fmoveml %fpcr/%fpsr/%fpiar,%a0@(TASK_THREAD+THREAD_FPCNTL)
+3:
+#endif  /* CONFIG_M68KFPU_EMU_ONLY */
+        /* Return previous task in %d1 */
+        movel   %curptr,%d1
+
+        /* switch to new task (a1 contains new task) */
+        movel   %a1,%curptr
+
+        /* restore floating point context */
+#ifndef CONFIG_M68KFPU_EMU_ONLY
+#ifdef CONFIG_M68KFPU_EMU
+        tstl    m68k_fputype
+        jeq     4f
+#endif
+#if defined(CONFIG_M68060)
+#if !defined(CPU_M68060_ONLY)
+        btst    #3,m68k_cputype+3
+        beqs    1f
+#endif
+        /* The 060 FPU keeps status in bits 15-8 of the first longword */
+        tstb    %a1@(TASK_THREAD+THREAD_FPSTATE+2)
+        jeq     3f
+#if !defined(CPU_M68060_ONLY)
+        jra     2f
+#endif
+#endif /* CONFIG_M68060 */
+#if !defined(CPU_M68060_ONLY)
+1:      tstb    %a1@(TASK_THREAD+THREAD_FPSTATE)
+        jeq     3f
 #endif
+2:      fmovemx %a1@(TASK_THREAD+THREAD_FPREG),%fp0-%fp7
+        fmoveml %a1@(TASK_THREAD+THREAD_FPCNTL),%fpcr/%fpsr/%fpiar
+3:      frestore %a1@(TASK_THREAD+THREAD_FPSTATE)
+4:
+#endif  /* CONFIG_M68KFPU_EMU_ONLY */
+
+        /* restore the kernel stack pointer */
+        movel   %a1@(TASK_THREAD+THREAD_KSP),%sp
+
+        /* restore non-scratch registers */
+        RESTORE_SWITCH_STACK
+
+        /* restore user stack pointer */
+        movel   %a1@(TASK_THREAD+THREAD_USP),%a0
+        movel   %a0,%usp
+
+        /* restore fs (sfc,%dfc) */
+        movew   %a1@(TASK_THREAD+THREAD_FS),%a0
+        movec   %a0,%sfc
+        movec   %a0,%dfc
+
+        /* restore status register */
+        movew   %a1@(TASK_THREAD+THREAD_SR),%sr
+
+        rts
+
+#endif /* CONFIG_MMU && !CONFIG_COLDFIRE */
diff --git a/arch/m68k/kernel/entry_mm.S b/arch/m68k/kernel/entry_mm.S
deleted file mode 100644
index f29e73ca9db..00000000000
--- a/arch/m68k/kernel/entry_mm.S
+++ /dev/null
@@ -1,419 +0,0 @@
-/* -*- mode: asm -*-
- *
- *  linux/arch/m68k/kernel/entry.S
- *
- *  Copyright (C) 1991, 1992  Linus Torvalds
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file README.legal in the main directory of this archive
- * for more details.
- *
- * Linux/m68k support by Hamish Macdonald
- *
- * 68060 fixes by Jesper Skov
- *
- */
-
-/*
- * entry.S  contains the system-call and fault low-level handling routines.
- * This also contains the timer-interrupt handler, as well as all interrupts
- * and faults that can result in a task-switch.
- *
- * NOTE: This code handles signal-recognition, which happens every time
- * after a timer-interrupt and after each system call.
- *
- */
-
-/*
- * 12/03/96 Jes: Currently we only support m68k single-cpu systems, so
- *               all pointers that used to be 'current' are now entry
- *               number 0 in the 'current_set' list.
- *
- *  6/05/00 RZ:  addedd writeback completion after return from sighandler
- *               for 68040
- */
-
-#include <linux/linkage.h>
-#include <asm/entry.h>
-#include <asm/errno.h>
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/traps.h>
-#include <asm/unistd.h>
-
-#include <asm/asm-offsets.h>
-
-.globl system_call, buserr, trap, resume
-.globl sys_call_table
-.globl sys_fork, sys_clone, sys_vfork
-.globl ret_from_interrupt, bad_interrupt
-.globl auto_irqhandler_fixup
-.globl user_irqvec_fixup
-
-.text
-ENTRY(buserr)
-        SAVE_ALL_INT
-        GET_CURRENT(%d0)
-        movel   %sp,%sp@-               | stack frame pointer argument
-        bsrl    buserr_c
-        addql   #4,%sp
-        jra     .Lret_from_exception
-
-ENTRY(trap)
-        SAVE_ALL_INT
-        GET_CURRENT(%d0)
-        movel   %sp,%sp@-               | stack frame pointer argument
-        bsrl    trap_c
-        addql   #4,%sp
-        jra     .Lret_from_exception
-
-        | After a fork we jump here directly from resume,
-        | so that %d1 contains the previous task
-        | schedule_tail now used regardless of CONFIG_SMP
-ENTRY(ret_from_fork)
-        movel   %d1,%sp@-
-        jsr     schedule_tail
-        addql   #4,%sp
-        jra     .Lret_from_exception
-
-do_trace_entry:
-        movel   #-ENOSYS,%sp@(PT_OFF_D0)| needed for strace
-        subql   #4,%sp
-        SAVE_SWITCH_STACK
-        jbsr    syscall_trace
-        RESTORE_SWITCH_STACK
-        addql   #4,%sp
-        movel   %sp@(PT_OFF_ORIG_D0),%d0
-        cmpl    #NR_syscalls,%d0
-        jcs     syscall
-badsys:
-        movel   #-ENOSYS,%sp@(PT_OFF_D0)
-        jra     ret_from_syscall
-
-do_trace_exit:
-        subql   #4,%sp
-        SAVE_SWITCH_STACK
-        jbsr    syscall_trace
-        RESTORE_SWITCH_STACK
-        addql   #4,%sp
-        jra     .Lret_from_exception
-
-ENTRY(ret_from_signal)
-        movel   %curptr@(TASK_STACK),%a1
-        tstb    %a1@(TINFO_FLAGS+2)
-        jge     1f
-        jbsr    syscall_trace
-1:      RESTORE_SWITCH_STACK
-        addql   #4,%sp
-/* on 68040 complete pending writebacks if any */
-#ifdef CONFIG_M68040
-        bfextu  %sp@(PT_OFF_FORMATVEC){#0,#4},%d0
-        subql   #7,%d0                          | bus error frame ?
-        jbne    1f
-        movel   %sp,%sp@-
-        jbsr    berr_040cleanup
-        addql   #4,%sp
-1:
-#endif
-        jra     .Lret_from_exception
-
-ENTRY(system_call)
-        SAVE_ALL_SYS
-
-        GET_CURRENT(%d1)
-        movel   %d1,%a1
-
-        | save top of frame
-        movel   %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
-
-        | syscall trace?
-        tstb    %a1@(TINFO_FLAGS+2)
-        jmi     do_trace_entry
-        cmpl    #NR_syscalls,%d0
-        jcc     badsys
-syscall:
-        jbsr    @(sys_call_table,%d0:l:4)@(0)
-        movel   %d0,%sp@(PT_OFF_D0)     | save the return value
-ret_from_syscall:
-        |oriw   #0x0700,%sr
-        movel   %curptr@(TASK_STACK),%a1
-        movew   %a1@(TINFO_FLAGS+2),%d0
-        jne     syscall_exit_work
-1:      RESTORE_ALL
-
-syscall_exit_work:
-        btst    #5,%sp@(PT_OFF_SR)      | check if returning to kernel
-        bnes    1b                      | if so, skip resched, signals
-        lslw    #1,%d0
-        jcs     do_trace_exit
-        jmi     do_delayed_trace
-        lslw    #8,%d0
-        jne     do_signal_return
-        pea     resume_userspace
-        jra     schedule
-
-
-ENTRY(ret_from_exception)
-.Lret_from_exception:
-        btst    #5,%sp@(PT_OFF_SR)      | check if returning to kernel
-        bnes    1f                      | if so, skip resched, signals
-        | only allow interrupts when we are really the last one on the
-        | kernel stack, otherwise stack overflow can occur during
-        | heavy interrupt load
-        andw    #ALLOWINT,%sr
-
-resume_userspace:
-        movel   %curptr@(TASK_STACK),%a1
-        moveb   %a1@(TINFO_FLAGS+3),%d0
-        jne     exit_work
-1:      RESTORE_ALL
-
-exit_work:
-        | save top of frame
-        movel   %sp,%curptr@(TASK_THREAD+THREAD_ESP0)
-        lslb    #1,%d0
-        jne     do_signal_return
-        pea     resume_userspace
-        jra     schedule
-
-
-do_signal_return:
-        |andw   #ALLOWINT,%sr
-        subql   #4,%sp                  | dummy return address
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        bsrl    do_notify_resume
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        addql   #4,%sp
-        jbra    resume_userspace
-
-do_delayed_trace:
-        bclr    #7,%sp@(PT_OFF_SR)      | clear trace bit in SR
-        pea     1                       | send SIGTRAP
-        movel   %curptr,%sp@-
-        pea     LSIGTRAP
-        jbsr    send_sig
-        addql   #8,%sp
-        addql   #4,%sp
-        jbra    resume_userspace
-
-
-/* This is the main interrupt handler for autovector interrupts */
-
-ENTRY(auto_inthandler)
-        SAVE_ALL_INT
-        GET_CURRENT(%d0)
-        movel   %d0,%a1
-        addqb   #1,%a1@(TINFO_PREEMPT+1)
-                                        |  put exception # in d0
-        bfextu  %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
-        subw    #VEC_SPUR,%d0
-
-        movel   %sp,%sp@-
-        movel   %d0,%sp@-               |  put vector # on stack
-auto_irqhandler_fixup = . + 2
-        jsr     do_IRQ                  |  process the IRQ
-        addql   #8,%sp                  |  pop parameters off stack
-
-ret_from_interrupt:
-        movel   %curptr@(TASK_STACK),%a1
-        subqb   #1,%a1@(TINFO_PREEMPT+1)
-        jeq     ret_from_last_interrupt
-2:      RESTORE_ALL
-
-        ALIGN
-ret_from_last_interrupt:
-        moveq   #(~ALLOWINT>>8)&0xff,%d0
-        andb    %sp@(PT_OFF_SR),%d0
-        jne     2b
-
-        /* check if we need to do software interrupts */
-        tstl    irq_stat+CPUSTAT_SOFTIRQ_PENDING
-        jeq     .Lret_from_exception
-        pea     ret_from_exception
-        jra     do_softirq
-
-/* Handler for user defined interrupt vectors */
-
-ENTRY(user_inthandler)
-        SAVE_ALL_INT
-        GET_CURRENT(%d0)
-        movel   %d0,%a1
-        addqb   #1,%a1@(TINFO_PREEMPT+1)
-                                        |  put exception # in d0
-        bfextu  %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
-user_irqvec_fixup = . + 2
-        subw    #VEC_USER,%d0
-
-        movel   %sp,%sp@-
-        movel   %d0,%sp@-               |  put vector # on stack
-        jsr     do_IRQ                  |  process the IRQ
-        addql   #8,%sp                  |  pop parameters off stack
-
-        movel   %curptr@(TASK_STACK),%a1
-        subqb   #1,%a1@(TINFO_PREEMPT+1)
-        jeq     ret_from_last_interrupt
-        RESTORE_ALL
-
-/* Handler for uninitialized and spurious interrupts */
-
-ENTRY(bad_inthandler)
-        SAVE_ALL_INT
-        GET_CURRENT(%d0)
-        movel   %d0,%a1
-        addqb   #1,%a1@(TINFO_PREEMPT+1)
-
-        movel   %sp,%sp@-
-        jsr     handle_badint
-        addql   #4,%sp
-
-        movel   %curptr@(TASK_STACK),%a1
-        subqb   #1,%a1@(TINFO_PREEMPT+1)
-        jeq     ret_from_last_interrupt
-        RESTORE_ALL
-
-
-ENTRY(sys_fork)
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        jbsr    m68k_fork
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(sys_clone)
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        jbsr    m68k_clone
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(sys_vfork)
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        jbsr    m68k_vfork
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(sys_sigreturn)
-        SAVE_SWITCH_STACK
-        jbsr    do_sigreturn
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(sys_rt_sigreturn)
-        SAVE_SWITCH_STACK
-        jbsr    do_rt_sigreturn
-        RESTORE_SWITCH_STACK
-        rts
-
-resume:
-        /*
-         * Beware - when entering resume, prev (the current task) is
-         * in a0, next (the new task) is in a1,so don't change these
-         * registers until their contents are no longer needed.
-         */
-
-        /* save sr */
-        movew   %sr,%a0@(TASK_THREAD+THREAD_SR)
-
-        /* save fs (sfc,%dfc) (may be pointing to kernel memory) */
-        movec   %sfc,%d0
-        movew   %d0,%a0@(TASK_THREAD+THREAD_FS)
-
-        /* save usp */
-        /* it is better to use a movel here instead of a movew 8*) */
-        movec   %usp,%d0
-        movel   %d0,%a0@(TASK_THREAD+THREAD_USP)
-
-        /* save non-scratch registers on stack */
-        SAVE_SWITCH_STACK
-
-        /* save current kernel stack pointer */
-        movel   %sp,%a0@(TASK_THREAD+THREAD_KSP)
-
-        /* save floating point context */
-#ifndef CONFIG_M68KFPU_EMU_ONLY
-#ifdef CONFIG_M68KFPU_EMU
-        tstl    m68k_fputype
-        jeq     3f
-#endif
-        fsave   %a0@(TASK_THREAD+THREAD_FPSTATE)
-
-#if defined(CONFIG_M68060)
-#if !defined(CPU_M68060_ONLY)
-        btst    #3,m68k_cputype+3
-        beqs    1f
-#endif
-        /* The 060 FPU keeps status in bits 15-8 of the first longword */
-        tstb    %a0@(TASK_THREAD+THREAD_FPSTATE+2)
-        jeq     3f
-#if !defined(CPU_M68060_ONLY)
-        jra     2f
-#endif
-#endif /* CONFIG_M68060 */
-#if !defined(CPU_M68060_ONLY)
-1:      tstb    %a0@(TASK_THREAD+THREAD_FPSTATE)
-        jeq     3f
-#endif
-2:      fmovemx %fp0-%fp7,%a0@(TASK_THREAD+THREAD_FPREG)
-        fmoveml %fpcr/%fpsr/%fpiar,%a0@(TASK_THREAD+THREAD_FPCNTL)
-3:
-#endif  /* CONFIG_M68KFPU_EMU_ONLY */
-        /* Return previous task in %d1 */
-        movel   %curptr,%d1
-
-        /* switch to new task (a1 contains new task) */
-        movel   %a1,%curptr
-
-        /* restore floating point context */
-#ifndef CONFIG_M68KFPU_EMU_ONLY
-#ifdef CONFIG_M68KFPU_EMU
-        tstl    m68k_fputype
-        jeq     4f
-#endif
-#if defined(CONFIG_M68060)
-#if !defined(CPU_M68060_ONLY)
-        btst    #3,m68k_cputype+3
-        beqs    1f
-#endif
-        /* The 060 FPU keeps status in bits 15-8 of the first longword */
-        tstb    %a1@(TASK_THREAD+THREAD_FPSTATE+2)
-        jeq     3f
-#if !defined(CPU_M68060_ONLY)
-        jra     2f
-#endif
-#endif /* CONFIG_M68060 */
-#if !defined(CPU_M68060_ONLY)
-1:      tstb    %a1@(TASK_THREAD+THREAD_FPSTATE)
-        jeq     3f
-#endif
-2:      fmovemx %a1@(TASK_THREAD+THREAD_FPREG),%fp0-%fp7
-        fmoveml %a1@(TASK_THREAD+THREAD_FPCNTL),%fpcr/%fpsr/%fpiar
-3:      frestore %a1@(TASK_THREAD+THREAD_FPSTATE)
-4:
-#endif  /* CONFIG_M68KFPU_EMU_ONLY */
-
-        /* restore the kernel stack pointer */
-        movel   %a1@(TASK_THREAD+THREAD_KSP),%sp
-
-        /* restore non-scratch registers */
-        RESTORE_SWITCH_STACK
-
-        /* restore user stack pointer */
-        movel   %a1@(TASK_THREAD+THREAD_USP),%a0
-        movel   %a0,%usp
-
-        /* restore fs (sfc,%dfc) */
-        movew   %a1@(TASK_THREAD+THREAD_FS),%a0
-        movec   %a0,%sfc
-        movec   %a0,%dfc
-
-        /* restore status register */
-        movew   %a1@(TASK_THREAD+THREAD_SR),%sr
-
-        rts
-
diff --git a/arch/m68k/kernel/entry_no.S b/arch/m68k/kernel/entry_no.S
deleted file mode 100644
index d80cba45589..00000000000
--- a/arch/m68k/kernel/entry_no.S
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- *  linux/arch/m68knommu/kernel/entry.S
- *
- *  Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
- *  Copyright (C) 1998  D. Jeff Dionne <jeff@lineo.ca>,
- *                      Kenneth Albanowski <kjahds@kjahds.com>,
- *  Copyright (C) 2000  Lineo Inc. (www.lineo.com) 
- *
- * Based on:
- *
- *  linux/arch/m68k/kernel/entry.S
- *
- *  Copyright (C) 1991, 1992  Linus Torvalds
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file README.legal in the main directory of this archive
- * for more details.
- *
- * Linux/m68k support by Hamish Macdonald
- *
- * 68060 fixes by Jesper Skov
- * ColdFire support by Greg Ungerer (gerg@snapgear.com)
- * 5307 fixes by David W. Miller
- * linux 2.4 support David McCullough <davidm@snapgear.com>
- */
-
-#include <linux/linkage.h>
-#include <asm/errno.h>
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/asm-offsets.h>
-#include <asm/entry.h>
-#include <asm/unistd.h>
-
-.text
-
-.globl buserr
-.globl trap
-.globl ret_from_exception
-.globl ret_from_signal
-.globl sys_fork
-.globl sys_clone
-.globl sys_vfork
-
-ENTRY(buserr)
-        SAVE_ALL_INT
-        GET_CURRENT(%d0)
-        movel   %sp,%sp@-               /* stack frame pointer argument */
-        jsr     buserr_c
-        addql   #4,%sp
-        jra     ret_from_exception
-
-ENTRY(trap)
-        SAVE_ALL_INT
-        GET_CURRENT(%d0)
-        movel   %sp,%sp@-               /* stack frame pointer argument */
-        jsr     trap_c
-        addql   #4,%sp
-        jra     ret_from_exception
-
-#ifdef TRAP_DBG_INTERRUPT
-
-.globl dbginterrupt
-ENTRY(dbginterrupt)
-        SAVE_ALL_INT
-        GET_CURRENT(%d0)
-        movel   %sp,%sp@-               /* stack frame pointer argument */
-        jsr     dbginterrupt_c
-        addql   #4,%sp
-        jra     ret_from_exception
-#endif
-
-ENTRY(reschedule)
-        /* save top of frame */
-        pea     %sp@
-        jbsr    set_esp0
-        addql   #4,%sp
-        pea     ret_from_exception
-        jmp     schedule
-
-ENTRY(ret_from_fork)
-        movel   %d1,%sp@-
-        jsr     schedule_tail
-        addql   #4,%sp
-        jra     ret_from_exception
-
-ENTRY(sys_fork)
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        jbsr    m68k_fork
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(sys_vfork)
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        jbsr    m68k_vfork
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(sys_clone)
-        SAVE_SWITCH_STACK
-        pea     %sp@(SWITCH_STACK_SIZE)
-        jbsr    m68k_clone
-        addql   #4,%sp
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(sys_sigreturn)
-        SAVE_SWITCH_STACK
-        jbsr    do_sigreturn
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(sys_rt_sigreturn)
-        SAVE_SWITCH_STACK
-        jbsr    do_rt_sigreturn
-        RESTORE_SWITCH_STACK
-        rts
-
-ENTRY(ret_from_user_signal)
-        moveq #__NR_sigreturn,%d0
-        trap #0
-
-ENTRY(ret_from_user_rt_signal)
-        movel #__NR_rt_sigreturn,%d0
-        trap #0
-
diff --git a/arch/m68k/kernel/module.c b/arch/m68k/kernel/module.c
index 34849c4c6e3..eb46fd6038c 100644
--- a/arch/m68k/kernel/module.c
+++ b/arch/m68k/kernel/module.c
@@ -47,7 +47,7 @@ int apply_relocate(Elf32_Shdr *sechdrs,
                         *location += sym->st_value;
                         break;
                 case R_68K_PC32:
-                        /* Add the value, subtract its postition */
+                        /* Add the value, subtract its position */
                         *location += sym->st_value - (uint32_t)location;
                         break;
                 default:
@@ -87,7 +87,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
                         *location = rel[i].r_addend + sym->st_value;
                         break;
                 case R_68K_PC32:
-                        /* Add the value, subtract its postition */
+                        /* Add the value, subtract its position */
                         *location = rel[i].r_addend + sym->st_value - (uint32_t)location;
                         break;
                 default:
diff --git a/arch/m68k/kernel/pcibios.c b/arch/m68k/kernel/pcibios.c
new file mode 100644
index 00000000000..b2988aa1840
--- /dev/null
+++ b/arch/m68k/kernel/pcibios.c
@@ -0,0 +1,109 @@
+/*
+ * pci.c -- basic PCI support code
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+
+/*
+ * From arch/i386/kernel/pci-i386.c:
+ *
+ * We need to avoid collisions with `mirrored' VGA ports
+ * and other strange ISA hardware, so we always want the
+ * addresses to be allocated in the 0x000-0x0ff region
+ * modulo 0x400.
+ *
+ * Why? Because some silly external IO cards only decode
+ * the low 10 bits of the IO address. The 0x00-0xff region
+ * is reserved for motherboard devices that decode all 16
+ * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
+ * but we want to try to avoid allocating at 0x2900-0x2bff
+ * which might be mirrored at 0x0100-0x03ff..
+ */
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+        resource_size_t size, resource_size_t align)
+{
+        resource_size_t start = res->start;
+
+        if ((res->flags & IORESOURCE_IO) && (start & 0x300))
+                start = (start + 0x3ff) & ~0x3ff;
+
+        start = (start + align - 1) & ~(align - 1);
+
+        return start;
+}
+
+/*
+ * This is taken from the ARM code for this.
+ */
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+        struct resource *r;
+        u16 cmd, newcmd;
+        int idx;
+
+        pci_read_config_word(dev, PCI_COMMAND, &cmd);
+        newcmd = cmd;
+
+        for (idx = 0; idx < 6; idx++) {
+                /* Only set up the requested stuff */
+                if (!(mask & (1 << idx)))
+                        continue;
+
+                r = dev->resource + idx;
+                if (!r->start && r->end) {
+                        pr_err(KERN_ERR "PCI: Device %s not available because of resource collisions\n",
+                                pci_name(dev));
+                        return -EINVAL;
+                }
+                if (r->flags & IORESOURCE_IO)
+                        newcmd |= PCI_COMMAND_IO;
+                if (r->flags & IORESOURCE_MEM)
+                        newcmd |= PCI_COMMAND_MEMORY;
+        }
+
+        /*
+         * Bridges (eg, cardbus bridges) need to be fully enabled
+         */
+        if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
+                newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+
+
+        if (newcmd != cmd) {
+                pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n",
+                        pci_name(dev), cmd, newcmd);
+                pci_write_config_word(dev, PCI_COMMAND, newcmd);
+        }
+        return 0;
+}
+
+void pcibios_update_irq(struct pci_dev *dev, int irq)
+{
+        pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
+}
+
+void __devinit pcibios_fixup_bus(struct pci_bus *bus)
+{
+        struct pci_dev *dev;
+
+        list_for_each_entry(dev, &bus->devices, bus_list) {
+                pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
+                pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);
+        }
+}
+
+char __devinit *pcibios_setup(char *str)
+{
+        return str;
+}
+
diff --git a/arch/m68k/kernel/setup_no.c b/arch/m68k/kernel/setup_no.c
index 7dc186b7a85..71fb29938db 100644
--- a/arch/m68k/kernel/setup_no.c
+++ b/arch/m68k/kernel/setup_no.c
@@ -218,13 +218,10 @@ void __init setup_arch(char **cmdline_p)
         printk(KERN_INFO "Motorola M5235EVB support (C)2005 Syn-tech Systems, Inc. (Jate Sujjavanich)\n");
 #endif
 
-        pr_debug("KERNEL -> TEXT=0x%06x-0x%06x DATA=0x%06x-0x%06x "
-                 "BSS=0x%06x-0x%06x\n", (int) &_stext, (int) &_etext,
-                 (int) &_sdata, (int) &_edata,
-                 (int) &_sbss, (int) &_ebss);
-        pr_debug("MEMORY -> ROMFS=0x%06x-0x%06x MEM=0x%06x-0x%06x\n ",
-                 (int) &_ebss, (int) memory_start,
-                 (int) memory_start, (int) memory_end);
+        pr_debug("KERNEL -> TEXT=0x%p-0x%p DATA=0x%p-0x%p BSS=0x%p-0x%p\n",
+                 _stext, _etext, _sdata, _edata, __bss_start, __bss_stop);
+        pr_debug("MEMORY -> ROMFS=0x%p-0x%06lx MEM=0x%06lx-0x%06lx\n ",
+                 __bss_stop, memory_start, memory_start, memory_end);
 
         /* Keep a copy of command line */
         *cmdline_p = &command_line[0];
diff --git a/arch/m68k/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k.c
index 8623f8dc16f..9a5932ec368 100644
--- a/arch/m68k/kernel/sys_m68k.c
+++ b/arch/m68k/kernel/sys_m68k.c
@@ -479,9 +479,13 @@ sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
                         goto bad_access;
                 }
 
-                mem_value = *mem;
+                /*
+                 * No need to check for EFAULT; we know that the page is
+                 * present and writable.
+                 */
+                __get_user(mem_value, mem);
                 if (mem_value == oldval)
-                        *mem = newval;
+                        __put_user(newval, mem);
 
                 pte_unmap_unlock(pte, ptl);
                 up_read(&mm->mmap_sem);
diff --git a/arch/m68k/kernel/vmlinux-nommu.lds b/arch/m68k/kernel/vmlinux-nommu.lds
index 40e02d9c38b..06a763f49fd 100644
--- a/arch/m68k/kernel/vmlinux-nommu.lds
+++ b/arch/m68k/kernel/vmlinux-nommu.lds
@@ -78,9 +78,7 @@ SECTIONS {
                 __init_end = .;
         }
 
-        _sbss = .;
         BSS_SECTION(0, 0, 0)
-        _ebss = .;
 
         _end = .;
 
diff --git a/arch/m68k/kernel/vmlinux-std.lds b/arch/m68k/kernel/vmlinux-std.lds
index 63407c83682..d0993594f55 100644
--- a/arch/m68k/kernel/vmlinux-std.lds
+++ b/arch/m68k/kernel/vmlinux-std.lds
@@ -31,9 +31,7 @@ SECTIONS
 
   RW_DATA_SECTION(16, PAGE_SIZE, THREAD_SIZE)
 
-  _sbss = .;
   BSS_SECTION(0, 0, 0)
-  _ebss = .;
 
   _edata = .;                   /* End of data section */
 
diff --git a/arch/m68k/kernel/vmlinux-sun3.lds b/arch/m68k/kernel/vmlinux-sun3.lds
index ad0f46d64c0..8080469ee6c 100644
--- a/arch/m68k/kernel/vmlinux-sun3.lds
+++ b/arch/m68k/kernel/vmlinux-sun3.lds
@@ -44,9 +44,7 @@ __init_begin = .;
         . = ALIGN(PAGE_SIZE);
         __init_end = .;
 
-  _sbss = .;
   BSS_SECTION(0, 0, 0)
-  _ebss = .;
 
   _end = . ;
 
diff --git a/arch/m68k/lib/muldi3.c b/arch/m68k/lib/muldi3.c
index 79e928a525d..ee5f0b1b5c5 100644
--- a/arch/m68k/lib/muldi3.c
+++ b/arch/m68k/lib/muldi3.c
@@ -19,7 +19,7 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 59 Temple Place - Suite 330,
 Boston, MA 02111-1307, USA.  */
 
-#if defined(CONFIG_M68000) || defined(CONFIG_COLDFIRE)
+#ifdef CONFIG_CPU_HAS_NO_MULDIV64
 
 #define SI_TYPE_SIZE 32
 #define __BITS4 (SI_TYPE_SIZE / 4)
diff --git a/arch/m68k/mm/init_mm.c b/arch/m68k/mm/init_mm.c
index f77f258dce3..282f9de6896 100644
--- a/arch/m68k/mm/init_mm.c
+++ b/arch/m68k/mm/init_mm.c
@@ -104,7 +104,7 @@ void __init print_memmap(void)
                 MLK_ROUNDUP(__init_begin, __init_end),
                 MLK_ROUNDUP(_stext, _etext),
                 MLK_ROUNDUP(_sdata, _edata),
-                MLK_ROUNDUP(_sbss, _ebss));
+                MLK_ROUNDUP(__bss_start, __bss_stop));
 }
 
 void __init mem_init(void)
diff --git a/arch/m68k/mm/init_no.c b/arch/m68k/mm/init_no.c
index 345ec0d83e3..688e3664aea 100644
--- a/arch/m68k/mm/init_no.c
+++ b/arch/m68k/mm/init_no.c
@@ -91,7 +91,7 @@ void __init mem_init(void)
         totalram_pages = free_all_bootmem();
 
         codek = (_etext - _stext) >> 10;
-        datak = (_ebss - _sdata) >> 10;
+        datak = (__bss_stop - _sdata) >> 10;
         initk = (__init_begin - __init_end) >> 10;
 
         tmp = nr_free_pages() << PAGE_SHIFT;
diff --git a/arch/m68k/mm/memory.c b/arch/m68k/mm/memory.c
index 250b8b786f4..51bc9d258ed 100644
--- a/arch/m68k/mm/memory.c
+++ b/arch/m68k/mm/memory.c
@@ -203,7 +203,7 @@ static inline void pushcl040(unsigned long paddr)
 void cache_clear (unsigned long paddr, int len)
 {
     if (CPU_IS_COLDFIRE) {
-        flush_cf_bcache(0, DCACHE_MAX_ADDR);
+        clear_cf_bcache(0, DCACHE_MAX_ADDR);
     } else if (CPU_IS_040_OR_060) {
         int tmp;
 
diff --git a/arch/m68k/platform/68328/head-de2.S b/arch/m68k/platform/68328/head-de2.S
index f632fdcb93e..537d3245b53 100644
--- a/arch/m68k/platform/68328/head-de2.S
+++ b/arch/m68k/platform/68328/head-de2.S
@@ -60,8 +60,8 @@ _start:
  *      Move ROM filesystem above bss :-)
  */
 
-        moveal  #_sbss, %a0                     /* romfs at the start of bss */
-        moveal  #_ebss, %a1                     /* Set up destination  */
+        moveal  #__bss_start, %a0               /* romfs at the start of bss */
+        moveal  #__bss_stop, %a1                /* Set up destination  */
         movel   %a0, %a2                        /* Copy of bss start */
 
         movel   8(%a0), %d1                     /* Get size of ROMFS */
@@ -84,8 +84,8 @@ _start:
  * Initialize BSS segment to 0
  */
 
-        lea     _sbss, %a0
-        lea     _ebss, %a1
+        lea     __bss_start, %a0
+        lea     __bss_stop, %a1
 
         /* Copy 0 to %a0 until %a0 == %a1 */
 2:      cmpal   %a0, %a1
diff --git a/arch/m68k/platform/68328/head-pilot.S b/arch/m68k/platform/68328/head-pilot.S
index 2ebfd642081..45a9dad29e3 100644
--- a/arch/m68k/platform/68328/head-pilot.S
+++ b/arch/m68k/platform/68328/head-pilot.S
@@ -110,7 +110,7 @@ L0:
         movel   #CONFIG_VECTORBASE, %d7
         addl    #16, %d7
         moveal  %d7, %a0
-        moveal  #_ebss, %a1
+        moveal  #__bss_stop, %a1
         lea     %a1@(512), %a2
 
         DBG_PUTC('C')
@@ -138,8 +138,8 @@ LD1:
 
         DBG_PUTC('E')
 
-        moveal  #_sbss, %a0
-        moveal  #_ebss, %a1
+        moveal  #__bss_start, %a0
+        moveal  #__bss_stop, %a1
 
         /* Copy 0 to %a0 until %a0 == %a1 */
 L1:
@@ -150,7 +150,7 @@ L1:
         DBG_PUTC('F')
 
         /* Copy command line from end of bss to command line */
-        moveal  #_ebss, %a0
+        moveal  #__bss_stop, %a0
         moveal  #command_line, %a1
         lea     %a1@(512), %a2
 
@@ -165,7 +165,7 @@ L3:
 
         movel   #_sdata, %d0    
         movel   %d0, _rambase   
-        movel   #_ebss, %d0
+        movel   #__bss_stop, %d0
         movel   %d0, _ramstart
 
         movel   %a4, %d0
diff --git a/arch/m68k/platform/68328/head-ram.S b/arch/m68k/platform/68328/head-ram.S
index 7f1aeeacb21..5189ef92609 100644
--- a/arch/m68k/platform/68328/head-ram.S
+++ b/arch/m68k/platform/68328/head-ram.S
@@ -76,8 +76,8 @@ pclp3:
         beq     pclp3
 #endif /* DEBUG */
         moveal  #0x007ffff0, %ssp
-        moveal  #_sbss, %a0
-        moveal  #_ebss, %a1
+        moveal  #__bss_start, %a0
+        moveal  #__bss_stop, %a1
 
         /* Copy 0 to %a0 until %a0 >= %a1 */
 L1:
diff --git a/arch/m68k/platform/68328/head-rom.S b/arch/m68k/platform/68328/head-rom.S
index a5ff96d0295..3dff98ba2e9 100644
--- a/arch/m68k/platform/68328/head-rom.S
+++ b/arch/m68k/platform/68328/head-rom.S
@@ -59,8 +59,8 @@ _stext:	movew	#0x2700,%sr
         cmpal   %a1, %a2
         bhi     1b
 
-        moveal  #_sbss, %a0
-        moveal  #_ebss, %a1
+        moveal  #__bss_start, %a0
+        moveal  #__bss_stop, %a1
         /* Copy 0 to %a0 until %a0 == %a1 */
         
 1:
@@ -70,7 +70,7 @@ _stext:	movew	#0x2700,%sr
 
         movel   #_sdata, %d0    
         movel   %d0, _rambase        
-        movel   #_ebss, %d0
+        movel   #__bss_stop, %d0
         movel   %d0, _ramstart
         movel   #RAMEND-CONFIG_MEMORY_RESERVE*0x100000, %d0
         movel   %d0, _ramend
diff --git a/arch/m68k/platform/68360/head-ram.S b/arch/m68k/platform/68360/head-ram.S
index 8eb94fb6b97..acd213170d8 100644
--- a/arch/m68k/platform/68360/head-ram.S
+++ b/arch/m68k/platform/68360/head-ram.S
@@ -219,8 +219,8 @@ LD1:
         cmp.l   #_edata, %a1
         blt     LD1
 
-        moveal  #_sbss, %a0
-        moveal  #_ebss, %a1
+        moveal  #__bss_start, %a0
+        moveal  #__bss_stop, %a1
 
         /* Copy 0 to %a0 until %a0 == %a1 */
 L1:
@@ -234,7 +234,7 @@ load_quicc:
 store_ram_size:
         /* Set ram size information */
         move.l  #_sdata, _rambase
-        move.l  #_ebss, _ramstart
+        move.l  #__bss_stop, _ramstart
         move.l  #RAMEND, %d0
         sub.l   #0x1000, %d0                    /* Reserve 4K for stack space.*/
         move.l  %d0, _ramend                    /* Different from RAMEND.*/
diff --git a/arch/m68k/platform/68360/head-rom.S b/arch/m68k/platform/68360/head-rom.S
index 97510e55b80..dfc756d9988 100644
--- a/arch/m68k/platform/68360/head-rom.S
+++ b/arch/m68k/platform/68360/head-rom.S
@@ -13,7 +13,7 @@
  */
 
 .global _stext
-.global _sbss
+.global __bss_start
 .global _start
 
 .global _rambase
@@ -229,8 +229,8 @@ LD1:
         cmp.l   #_edata, %a1
         blt     LD1
 
-        moveal  #_sbss, %a0
-        moveal  #_ebss, %a1
+        moveal  #__bss_start, %a0
+        moveal  #__bss_stop, %a1
 
         /* Copy 0 to %a0 until %a0 == %a1 */
 L1:
@@ -244,7 +244,7 @@ load_quicc:
 store_ram_size:
         /* Set ram size information */
         move.l  #_sdata, _rambase
-        move.l  #_ebss, _ramstart
+        move.l  #__bss_stop, _ramstart
         move.l  #RAMEND, %d0
         sub.l   #0x1000, %d0                    /* Reserve 4K for stack space.*/
         move.l  %d0, _ramend                    /* Different from RAMEND.*/
diff --git a/arch/m68k/platform/coldfire/Makefile b/arch/m68k/platform/coldfire/Makefile
index 76d389d9a84..02591a109f8 100644
--- a/arch/m68k/platform/coldfire/Makefile
+++ b/arch/m68k/platform/coldfire/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_M5206e)	+= m5206.o timers.o intc.o reset.o
 obj-$(CONFIG_M520x)     += m520x.o pit.o intc-simr.o reset.o
 obj-$(CONFIG_M523x)     += m523x.o pit.o dma_timer.o intc-2.o reset.o
 obj-$(CONFIG_M5249)     += m5249.o timers.o intc.o intc-5249.o reset.o
+obj-$(CONFIG_M525x)     += m525x.o timers.o intc.o intc-525x.o reset.o
 obj-$(CONFIG_M527x)     += m527x.o pit.o intc-2.o reset.o
 obj-$(CONFIG_M5272)     += m5272.o intc-5272.o timers.o
 obj-$(CONFIG_M528x)     += m528x.o pit.o intc-2.o reset.o
@@ -27,10 +28,14 @@ obj-$(CONFIG_M5307)	+= m5307.o timers.o intc.o reset.o
 obj-$(CONFIG_M532x)     += m532x.o timers.o intc-simr.o reset.o
 obj-$(CONFIG_M5407)     += m5407.o timers.o intc.o reset.o
 obj-$(CONFIG_M54xx)     += m54xx.o sltimers.o intc-2.o
+obj-$(CONFIG_M5441x)    += m5441x.o pit.o intc-simr.o reset.o
 
 obj-$(CONFIG_NETtel)    += nettel.o
 obj-$(CONFIG_CLEOPATRA) += nettel.o
 obj-$(CONFIG_FIREBEE)   += firebee.o
+obj-$(CONFIG_MCF8390)   += mcf8390.o
 
-obj-y                   += pinmux.o gpio.o
+obj-$(CONFIG_PCI)       += pci.o
+
+obj-y                   += gpio.o
 extra-y := head.o
diff --git a/arch/m68k/platform/coldfire/clk.c b/arch/m68k/platform/coldfire/clk.c
index 44da406897e..75f9ee967ea 100644
--- a/arch/m68k/platform/coldfire/clk.c
+++ b/arch/m68k/platform/coldfire/clk.c
@@ -10,11 +10,17 @@
 
 #include <linux/kernel.h>
 #include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
 #include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
 #include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfclk.h>
 
 /***************************************************************************/
-
+#ifndef MCFPM_PPMCR0
 struct clk *clk_get(struct device *dev, const char *id)
 {
         return NULL;
@@ -42,11 +48,107 @@ unsigned long clk_get_rate(struct clk *clk)
         return MCF_CLK;
 }
 EXPORT_SYMBOL(clk_get_rate);
+#else
+static DEFINE_SPINLOCK(clk_lock);
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        const char *clk_name = dev ? dev_name(dev) : id ? id : NULL;
+        struct clk *clk;
+        unsigned i;
+
+        for (i = 0; (clk = mcf_clks[i]) != NULL; ++i)
+                if (!strcmp(clk->name, clk_name))
+                        return clk;
+        pr_warn("clk_get: didn't find clock %s\n", clk_name);
+        return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&clk_lock, flags);
+        if ((clk->enabled++ == 0) && clk->clk_ops)
+                clk->clk_ops->enable(clk);
+        spin_unlock_irqrestore(&clk_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&clk_lock, flags);
+        if ((--clk->enabled == 0) && clk->clk_ops)
+                clk->clk_ops->disable(clk);
+        spin_unlock_irqrestore(&clk_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+void clk_put(struct clk *clk)
+{
+        if (clk->enabled != 0)
+                pr_warn("clk_put %s still enabled\n", clk->name);
+}
+EXPORT_SYMBOL(clk_put);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/***************************************************************************/
+
+void __clk_init_enabled(struct clk *clk)
+{
+        clk->enabled = 1;
+        clk->clk_ops->enable(clk);
+}
+
+void __clk_init_disabled(struct clk *clk)
+{
+        clk->enabled = 0;
+        clk->clk_ops->disable(clk);
+}
+
+static void __clk_enable0(struct clk *clk)
+{
+        __raw_writeb(clk->slot, MCFPM_PPMCR0);
+}
+
+static void __clk_disable0(struct clk *clk)
+{
+        __raw_writeb(clk->slot, MCFPM_PPMSR0);
+}
+
+struct clk_ops clk_ops0 = {
+        .enable         = __clk_enable0,
+        .disable        = __clk_disable0,
+};
+
+#ifdef MCFPM_PPMCR1
+static void __clk_enable1(struct clk *clk)
+{
+        __raw_writeb(clk->slot, MCFPM_PPMCR1);
+}
+
+static void __clk_disable1(struct clk *clk)
+{
+        __raw_writeb(clk->slot, MCFPM_PPMSR1);
+}
+
+struct clk_ops clk_ops1 = {
+        .enable         = __clk_enable1,
+        .disable        = __clk_disable1,
+};
+#endif /* MCFPM_PPMCR1 */
+#endif /* MCFPM_PPMCR0 */
 
 struct clk *devm_clk_get(struct device *dev, const char *id)
 {
         return NULL;
 }
 EXPORT_SYMBOL(devm_clk_get);
-
-/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
index 3aa77ddea89..81f0fb5e51c 100644
--- a/arch/m68k/platform/coldfire/device.c
+++ b/arch/m68k/platform/coldfire/device.c
@@ -13,6 +13,7 @@
 #include <linux/io.h>
 #include <linux/spi/spi.h>
 #include <linux/gpio.h>
+#include <linux/fec.h>
 #include <asm/traps.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
@@ -20,7 +21,7 @@
 #include <asm/mcfqspi.h>
 
 /*
- *      All current ColdFire parts contain from 2, 3 or 4 UARTS.
+ *      All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
  */
 static struct mcf_platform_uart mcf_uart_platform_data[] = {
         {
@@ -43,6 +44,42 @@ static struct mcf_platform_uart mcf_uart_platform_data[] = {
                 .irq            = MCF_IRQ_UART3,
         },
 #endif
+#ifdef MCFUART_BASE4
+        {
+                .mapbase        = MCFUART_BASE4,
+                .irq            = MCF_IRQ_UART4,
+        },
+#endif
+#ifdef MCFUART_BASE5
+        {
+                .mapbase        = MCFUART_BASE5,
+                .irq            = MCF_IRQ_UART5,
+        },
+#endif
+#ifdef MCFUART_BASE6
+        {
+                .mapbase        = MCFUART_BASE6,
+                .irq            = MCF_IRQ_UART6,
+        },
+#endif
+#ifdef MCFUART_BASE7
+        {
+                .mapbase        = MCFUART_BASE7,
+                .irq            = MCF_IRQ_UART7,
+        },
+#endif
+#ifdef MCFUART_BASE8
+        {
+                .mapbase        = MCFUART_BASE8,
+                .irq            = MCF_IRQ_UART8,
+        },
+#endif
+#ifdef MCFUART_BASE9
+        {
+                .mapbase        = MCFUART_BASE9,
+                .irq            = MCF_IRQ_UART9,
+        },
+#endif
         { },
 };
 
@@ -53,6 +90,18 @@ static struct platform_device mcf_uart = {
 };
 
 #ifdef CONFIG_FEC
+
+#ifdef CONFIG_M5441x
+#define FEC_NAME        "enet-fec"
+static struct fec_platform_data fec_pdata = {
+        .phy            = PHY_INTERFACE_MODE_RMII,
+};
+#define FEC_PDATA       (&fec_pdata)
+#else
+#define FEC_NAME        "fec"
+#define FEC_PDATA       NULL
+#endif
+
 /*
  *      Some ColdFire cores contain the Fast Ethernet Controller (FEC)
  *      block. It is Freescale's own hardware block. Some ColdFires
@@ -82,10 +131,11 @@ static struct resource mcf_fec0_resources[] = {
 };
 
 static struct platform_device mcf_fec0 = {
-        .name                   = "fec",
+        .name                   = FEC_NAME,
         .id                     = 0,
         .num_resources          = ARRAY_SIZE(mcf_fec0_resources),
         .resource               = mcf_fec0_resources,
+        .dev.platform_data      = FEC_PDATA,
 };
 
 #ifdef MCFFEC_BASE1
@@ -113,10 +163,11 @@ static struct resource mcf_fec1_resources[] = {
 };
 
 static struct platform_device mcf_fec1 = {
-        .name                   = "fec",
+        .name                   = FEC_NAME,
         .id                     = 1,
         .num_resources          = ARRAY_SIZE(mcf_fec1_resources),
         .resource               = mcf_fec1_resources,
+        .dev.platform_data      = FEC_PDATA,
 };
 #endif /* MCFFEC_BASE1 */
 #endif /* CONFIG_FEC */
diff --git a/arch/m68k/platform/coldfire/gpio.c b/arch/m68k/platform/coldfire/gpio.c
index 4c8c42450a4..9cd2b5c7051 100644
--- a/arch/m68k/platform/coldfire/gpio.c
+++ b/arch/m68k/platform/coldfire/gpio.c
@@ -14,119 +14,161 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/device.h>
 
-#include <asm/gpio.h>
-#include <asm/pinmux.h>
+#include <linux/io.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
 #include <asm/mcfgpio.h>
 
-#define MCF_CHIP(chip) container_of(chip, struct mcf_gpio_chip, gpio_chip)
+int __mcfgpio_get_value(unsigned gpio)
+{
+        return mcfgpio_read(__mcfgpio_ppdr(gpio)) & mcfgpio_bit(gpio);
+}
+EXPORT_SYMBOL(__mcfgpio_get_value);
+
+void __mcfgpio_set_value(unsigned gpio, int value)
+{
+        if (gpio < MCFGPIO_SCR_START) {
+                unsigned long flags;
+                MCFGPIO_PORTTYPE data;
+
+                local_irq_save(flags);
+                data = mcfgpio_read(__mcfgpio_podr(gpio));
+                if (value)
+                        data |= mcfgpio_bit(gpio);
+                else
+                        data &= ~mcfgpio_bit(gpio);
+                mcfgpio_write(data, __mcfgpio_podr(gpio));
+                local_irq_restore(flags);
+        } else {
+                if (value)
+                        mcfgpio_write(mcfgpio_bit(gpio),
+                                        MCFGPIO_SETR_PORT(gpio));
+                else
+                        mcfgpio_write(~mcfgpio_bit(gpio),
+                                        MCFGPIO_CLRR_PORT(gpio));
+        }
+}
+EXPORT_SYMBOL(__mcfgpio_set_value);
 
-int mcf_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+int __mcfgpio_direction_input(unsigned gpio)
 {
         unsigned long flags;
         MCFGPIO_PORTTYPE dir;
-        struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
 
         local_irq_save(flags);
-        dir = mcfgpio_read(mcf_chip->pddr);
-        dir &= ~mcfgpio_bit(chip->base + offset);
-        mcfgpio_write(dir, mcf_chip->pddr);
+        dir = mcfgpio_read(__mcfgpio_pddr(gpio));
+        dir &= ~mcfgpio_bit(gpio);
+        mcfgpio_write(dir, __mcfgpio_pddr(gpio));
         local_irq_restore(flags);
 
         return 0;
 }
+EXPORT_SYMBOL(__mcfgpio_direction_input);
 
-int mcf_gpio_get_value(struct gpio_chip *chip, unsigned offset)
-{
-        struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
-
-        return mcfgpio_read(mcf_chip->ppdr) & mcfgpio_bit(chip->base + offset);
-}
-
-int mcf_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
-                int value)
+int __mcfgpio_direction_output(unsigned gpio, int value)
 {
         unsigned long flags;
         MCFGPIO_PORTTYPE data;
-        struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
 
         local_irq_save(flags);
-        /* write the value to the output latch */
-        data = mcfgpio_read(mcf_chip->podr);
+        data = mcfgpio_read(__mcfgpio_pddr(gpio));
         if (value)
-                data |= mcfgpio_bit(chip->base + offset);
+                data |= mcfgpio_bit(gpio);
         else
-                data &= ~mcfgpio_bit(chip->base + offset);
-        mcfgpio_write(data, mcf_chip->podr);
-
-        /* now set the direction to output */
-        data = mcfgpio_read(mcf_chip->pddr);
-        data |= mcfgpio_bit(chip->base + offset);
-        mcfgpio_write(data, mcf_chip->pddr);
+                data &= mcfgpio_bit(gpio);
+        mcfgpio_write(data, __mcfgpio_pddr(gpio));
+
+        /* now set the data to output */
+        if (gpio < MCFGPIO_SCR_START) {
+                data = mcfgpio_read(__mcfgpio_podr(gpio));
+                if (value)
+                        data |= mcfgpio_bit(gpio);
+                else
+                        data &= ~mcfgpio_bit(gpio);
+                mcfgpio_write(data, __mcfgpio_podr(gpio));
+        } else {
+                 if (value)
+                        mcfgpio_write(mcfgpio_bit(gpio),
+                                        MCFGPIO_SETR_PORT(gpio));
+                 else
+                         mcfgpio_write(~mcfgpio_bit(gpio),
+                                         MCFGPIO_CLRR_PORT(gpio));
+        }
         local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(__mcfgpio_direction_output);
 
+int __mcfgpio_request(unsigned gpio)
+{
         return 0;
 }
+EXPORT_SYMBOL(__mcfgpio_request);
 
-void mcf_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
+void __mcfgpio_free(unsigned gpio)
 {
-        struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
+        __mcfgpio_direction_input(gpio);
+}
+EXPORT_SYMBOL(__mcfgpio_free);
 
-        unsigned long flags;
-        MCFGPIO_PORTTYPE data;
+#ifdef CONFIG_GPIOLIB
 
-        local_irq_save(flags);
-        data = mcfgpio_read(mcf_chip->podr);
-        if (value)
-                data |= mcfgpio_bit(chip->base + offset);
-        else
-                data &= ~mcfgpio_bit(chip->base + offset);
-        mcfgpio_write(data, mcf_chip->podr);
-        local_irq_restore(flags);
+int mcfgpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        return __mcfgpio_direction_input(offset);
 }
 
-void mcf_gpio_set_value_fast(struct gpio_chip *chip, unsigned offset, int value)
+int mcfgpio_get_value(struct gpio_chip *chip, unsigned offset)
 {
-        struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
-
-        if (value)
-                mcfgpio_write(mcfgpio_bit(chip->base + offset), mcf_chip->setr);
-        else
-                mcfgpio_write(~mcfgpio_bit(chip->base + offset), mcf_chip->clrr);
+        return __mcfgpio_get_value(offset);
 }
 
-int mcf_gpio_request(struct gpio_chip *chip, unsigned offset)
+int mcfgpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 {
-        struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
-
-        return mcf_chip->gpio_to_pinmux ?
-                mcf_pinmux_request(mcf_chip->gpio_to_pinmux[offset], 0) : 0;
+        return __mcfgpio_direction_output(offset, value);
 }
 
-void mcf_gpio_free(struct gpio_chip *chip, unsigned offset)
+void mcfgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
 {
-        struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
+        __mcfgpio_set_value(offset, value);
+}
 
-        mcf_gpio_direction_input(chip, offset);
+int mcfgpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        return __mcfgpio_request(offset);
+}
 
-        if (mcf_chip->gpio_to_pinmux)
-                mcf_pinmux_release(mcf_chip->gpio_to_pinmux[offset], 0);
+void mcfgpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        __mcfgpio_free(offset);
 }
 
-struct bus_type mcf_gpio_subsys = {
+struct bus_type mcfgpio_subsys = {
         .name           = "gpio",
         .dev_name       = "gpio",
 };
 
-static int __init mcf_gpio_sysinit(void)
-{
-        unsigned int i = 0;
+static struct gpio_chip mcfgpio_chip = {
+        .label                  = "mcfgpio",
+        .request                = mcfgpio_request,
+        .free                   = mcfgpio_free,
+        .direction_input        = mcfgpio_direction_input,
+        .direction_output       = mcfgpio_direction_output,
+        .get                    = mcfgpio_get_value,
+        .set                    = mcfgpio_set_value,
+        .base                   = 0,
+        .ngpio                  = MCFGPIO_PIN_MAX,
+};
 
-        while (i < mcf_gpio_chips_size)
-                gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
-        return subsys_system_register(&mcf_gpio_subsys, NULL);
+static int __init mcfgpio_sysinit(void)
+{
+        gpiochip_add(&mcfgpio_chip);
+        return subsys_system_register(&mcfgpio_subsys, NULL);
 }
 
-core_initcall(mcf_gpio_sysinit);
+core_initcall(mcfgpio_sysinit);
+#endif
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index c3db70ed33b..b88f5716f35 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -31,9 +31,9 @@
 .endm
 
 #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
-      defined(CONFIG_M5249) || defined(CONFIG_M527x) || \
-      defined(CONFIG_M528x) || defined(CONFIG_M5307) || \
-      defined(CONFIG_M5407)
+      defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
+      defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
+      defined(CONFIG_M5307) || defined(CONFIG_M5407)
 /*
  *      Not all these devices have exactly the same DRAM controller,
  *      but the DCMR register is virtually identical - give or take
@@ -230,8 +230,8 @@ _vstart:
         /*
          *      Move ROM filesystem above bss :-)
          */
-        lea     _sbss,%a0                       /* get start of bss */
-        lea     _ebss,%a1                       /* set up destination  */
+        lea     __bss_start,%a0                 /* get start of bss */
+        lea     __bss_stop,%a1                  /* set up destination  */
         movel   %a0,%a2                         /* copy of bss start */
 
         movel   8(%a0),%d0                      /* get size of ROMFS */
@@ -249,7 +249,7 @@ _copy_romfs:
         bne     _copy_romfs
 
 #else /* CONFIG_ROMFS_FS */
-        lea     _ebss,%a1
+        lea     __bss_stop,%a1
         movel   %a1,_ramstart
 #endif /* CONFIG_ROMFS_FS */
 
@@ -257,8 +257,8 @@ _copy_romfs:
         /*
          *      Zero out the bss region.
          */
-        lea     _sbss,%a0                       /* get start of bss */
-        lea     _ebss,%a1                       /* get end of bss */
+        lea     __bss_start,%a0                 /* get start of bss */
+        lea     __bss_stop,%a1                  /* get end of bss */
         clrl    %d0                             /* set value */
 _clear_bss:
         movel   %d0,(%a0)+                      /* clear each word */
diff --git a/arch/m68k/platform/coldfire/intc-525x.c b/arch/m68k/platform/coldfire/intc-525x.c
new file mode 100644
index 00000000000..b23204d059a
--- /dev/null
+++ b/arch/m68k/platform/coldfire/intc-525x.c
@@ -0,0 +1,91 @@
+/*
+ * intc2.c  -- support for the 2nd INTC controller of the 525x
+ *
+ * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
+ * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+
+static void intc2_irq_gpio_mask(struct irq_data *d)
+{
+        u32 imr = readl(MCFSIM2_GPIOINTENABLE);
+        u32 type = irqd_get_trigger_type(d);
+        int irq = d->irq - MCF_IRQ_GPIO0;
+
+        if (type & IRQ_TYPE_EDGE_RISING)
+                imr &= ~(0x001 << irq);
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                imr &= ~(0x100 << irq);
+        writel(imr, MCFSIM2_GPIOINTENABLE);
+}
+
+static void intc2_irq_gpio_unmask(struct irq_data *d)
+{
+        u32 imr = readl(MCFSIM2_GPIOINTENABLE);
+        u32 type = irqd_get_trigger_type(d);
+        int irq = d->irq - MCF_IRQ_GPIO0;
+
+        if (type & IRQ_TYPE_EDGE_RISING)
+                imr |= (0x001 << irq);
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                imr |= (0x100 << irq);
+        writel(imr, MCFSIM2_GPIOINTENABLE);
+}
+
+static void intc2_irq_gpio_ack(struct irq_data *d)
+{
+        u32 imr = 0;
+        u32 type = irqd_get_trigger_type(d);
+        int irq = d->irq - MCF_IRQ_GPIO0;
+
+        if (type & IRQ_TYPE_EDGE_RISING)
+                imr |= (0x001 << irq);
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                imr |= (0x100 << irq);
+        writel(imr, MCFSIM2_GPIOINTCLEAR);
+}
+
+static int intc2_irq_gpio_set_type(struct irq_data *d, unsigned int f)
+{
+        if (f & ~IRQ_TYPE_EDGE_BOTH)
+                return -EINVAL;
+        return 0;
+}
+
+static struct irq_chip intc2_irq_gpio_chip = {
+        .name           = "CF-INTC2",
+        .irq_mask       = intc2_irq_gpio_mask,
+        .irq_unmask     = intc2_irq_gpio_unmask,
+        .irq_ack        = intc2_irq_gpio_ack,
+        .irq_set_type   = intc2_irq_gpio_set_type,
+};
+
+static int __init mcf_intc2_init(void)
+{
+        int irq;
+
+        /* set the interrupt base for the second interrupt controller */
+        writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
+
+        /* GPIO interrupt sources */
+        for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO6); irq++) {
+                irq_set_chip(irq, &intc2_irq_gpio_chip);
+                irq_set_handler(irq, handle_edge_irq);
+        }
+
+        return 0;
+}
+
+arch_initcall(mcf_intc2_init);
diff --git a/arch/m68k/platform/coldfire/intc-simr.c b/arch/m68k/platform/coldfire/intc-simr.c
index 650d52e2927..7cf2c156f72 100644
--- a/arch/m68k/platform/coldfire/intc-simr.c
+++ b/arch/m68k/platform/coldfire/intc-simr.c
@@ -59,16 +59,18 @@ static unsigned int inline irq2ebit(unsigned int irq)
 #endif
 
 /*
- *      There maybe one or two interrupt control units, each has 64
- *      interrupts. If there is no second unit then MCFINTC1_* defines
- *      will be 0 (and code for them optimized away).
+ *      There maybe one, two or three interrupt control units, each has 64
+ *      interrupts. If there is no second or third unit then MCFINTC1_* or
+ *      MCFINTC2_* defines will be 0 (and code for them optimized away).
  */
 
 static void intc_irq_mask(struct irq_data *d)
 {
         unsigned int irq = d->irq - MCFINT_VECBASE;
 
-        if (MCFINTC1_SIMR && (irq > 64))
+        if (MCFINTC2_SIMR && (irq > 128))
+                __raw_writeb(irq - 128, MCFINTC2_SIMR);
+        else if (MCFINTC1_SIMR && (irq > 64))
                 __raw_writeb(irq - 64, MCFINTC1_SIMR);
         else
                 __raw_writeb(irq, MCFINTC0_SIMR);
@@ -78,7 +80,9 @@ static void intc_irq_unmask(struct irq_data *d)
 {
         unsigned int irq = d->irq - MCFINT_VECBASE;
 
-        if (MCFINTC1_CIMR && (irq > 64))
+        if (MCFINTC2_CIMR && (irq > 128))
+                __raw_writeb(irq - 128, MCFINTC2_CIMR);
+        else if (MCFINTC1_CIMR && (irq > 64))
                 __raw_writeb(irq - 64, MCFINTC1_CIMR);
         else
                 __raw_writeb(irq, MCFINTC0_CIMR);
@@ -99,9 +103,11 @@ static unsigned int intc_irq_startup(struct irq_data *d)
                 unsigned int ebit = irq2ebit(irq);
                 u8 v;
 
+#if defined(MCFEPORT_EPDDR)
                 /* Set EPORT line as input */
                 v = __raw_readb(MCFEPORT_EPDDR);
                 __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
+#endif
 
                 /* Set EPORT line as interrupt source */
                 v = __raw_readb(MCFEPORT_EPIER);
@@ -109,12 +115,13 @@ static unsigned int intc_irq_startup(struct irq_data *d)
         }
 
         irq -= MCFINT_VECBASE;
-        if (MCFINTC1_ICR0 && (irq > 64))
+        if (MCFINTC2_ICR0 && (irq > 128))
+                __raw_writeb(5, MCFINTC2_ICR0 + irq - 128);
+        else if (MCFINTC1_ICR0 && (irq > 64))
                 __raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
         else
                 __raw_writeb(5, MCFINTC0_ICR0 + irq);
 
-
         intc_irq_unmask(d);
         return 0;
 }
@@ -175,8 +182,11 @@ void __init init_IRQ(void)
         __raw_writeb(0xff, MCFINTC0_SIMR);
         if (MCFINTC1_SIMR)
                 __raw_writeb(0xff, MCFINTC1_SIMR);
+        if (MCFINTC2_SIMR)
+                __raw_writeb(0xff, MCFINTC2_SIMR);
 
-        eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
+        eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) +
+                                                (MCFINTC2_ICR0 ? 64 : 0);
         for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
                 if ((irq >= EINT1) && (irq <= EINT7))
                         irq_set_chip(irq, &intc_irq_chip_edge_port);
diff --git a/arch/m68k/platform/coldfire/m5206.c b/arch/m68k/platform/coldfire/m5206.c
index a8b81df653f..6bfbeebd231 100644
--- a/arch/m68k/platform/coldfire/m5206.c
+++ b/arch/m68k/platform/coldfire/m5206.c
@@ -16,15 +16,6 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-
-/***************************************************************************/
-
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-        MCFGPS(PP, 0, 8, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
-};
-
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
 
 /***************************************************************************/
 
diff --git a/arch/m68k/platform/coldfire/m520x.c b/arch/m68k/platform/coldfire/m520x.c
index 3264b8883d5..ea1be0e98ad 100644
--- a/arch/m68k/platform/coldfire/m520x.c
+++ b/arch/m68k/platform/coldfire/m520x.c
@@ -19,22 +19,102 @@
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
-#include <asm/mcfgpio.h>
+#include <asm/mcfclk.h>
 
 /***************************************************************************/
 
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-        MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
-        MCFGPF(CS, 9, 3),
-        MCFGPF(FECI2C, 16, 4),
-        MCFGPF(QSPI, 24, 4),
-        MCFGPF(TIMER, 32, 4),
-        MCFGPF(UART, 40, 8),
-        MCFGPF(FECH, 48, 8),
-        MCFGPF(FECL, 56, 8),
+DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
+DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
+DEFINE_CLK(0, "edma", 17, MCF_CLK);
+DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
+DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
+DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
+DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
+DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
+DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
+
+DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
+DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK);
+DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK);
+DEFINE_CLK(0, "pll.0", 36, MCF_CLK);
+DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
+DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
+DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
+
+struct clk *mcf_clks[] = {
+        &__clk_0_2, /* flexbus */
+        &__clk_0_12, /* fec.0 */
+        &__clk_0_17, /* edma */
+        &__clk_0_18, /* intc.0 */
+        &__clk_0_21, /* iack.0 */
+        &__clk_0_22, /* mcfi2c.0 */
+        &__clk_0_23, /* mcfqspi.0 */
+        &__clk_0_24, /* mcfuart.0 */
+        &__clk_0_25, /* mcfuart.1 */
+        &__clk_0_26, /* mcfuart.2 */
+        &__clk_0_28, /* mcftmr.0 */
+        &__clk_0_29, /* mcftmr.1 */
+        &__clk_0_30, /* mcftmr.2 */
+        &__clk_0_31, /* mcftmr.3 */
+
+        &__clk_0_32, /* mcfpit.0 */
+        &__clk_0_33, /* mcfpit.1 */
+        &__clk_0_34, /* mcfeport.0 */
+        &__clk_0_35, /* mcfwdt.0 */
+        &__clk_0_36, /* pll.0 */
+        &__clk_0_40, /* sys.0 */
+        &__clk_0_41, /* gpio.0 */
+        &__clk_0_42, /* sdram.0 */
+NULL,
 };
 
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+static struct clk * const enable_clks[] __initconst = {
+        &__clk_0_2, /* flexbus */
+        &__clk_0_18, /* intc.0 */
+        &__clk_0_21, /* iack.0 */
+        &__clk_0_24, /* mcfuart.0 */
+        &__clk_0_25, /* mcfuart.1 */
+        &__clk_0_26, /* mcfuart.2 */
+
+        &__clk_0_32, /* mcfpit.0 */
+        &__clk_0_33, /* mcfpit.1 */
+        &__clk_0_34, /* mcfeport.0 */
+        &__clk_0_36, /* pll.0 */
+        &__clk_0_40, /* sys.0 */
+        &__clk_0_41, /* gpio.0 */
+        &__clk_0_42, /* sdram.0 */
+};
+
+static struct clk * const disable_clks[] __initconst = {
+        &__clk_0_12, /* fec.0 */
+        &__clk_0_17, /* edma */
+        &__clk_0_22, /* mcfi2c.0 */
+        &__clk_0_23, /* mcfqspi.0 */
+        &__clk_0_28, /* mcftmr.0 */
+        &__clk_0_29, /* mcftmr.1 */
+        &__clk_0_30, /* mcftmr.2 */
+        &__clk_0_31, /* mcftmr.3 */
+        &__clk_0_35, /* mcfwdt.0 */
+};
+
+
+static void __init m520x_clk_init(void)
+{
+        unsigned i;
+
+        /* make sure these clocks are enabled */
+        for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
+                __clk_init_enabled(enable_clks[i]);
+        /* make sure these clocks are disabled */
+        for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
+                __clk_init_disabled(disable_clks[i]);
+}
 
 /***************************************************************************/
 
@@ -93,6 +173,7 @@ static void __init m520x_fec_init(void)
 void __init config_BSP(char *commandp, int size)
 {
         mach_sched_init = hw_timer_init;
+        m520x_clk_init();
         m520x_uarts_init();
         m520x_fec_init();
 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
diff --git a/arch/m68k/platform/coldfire/m523x.c b/arch/m68k/platform/coldfire/m523x.c
index 5d57a424941..d47dfd8f50a 100644
--- a/arch/m68k/platform/coldfire/m523x.c
+++ b/arch/m68k/platform/coldfire/m523x.c
@@ -19,28 +19,6 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-
-/***************************************************************************/
-
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-        MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
-        MCFGPF(ADDR, 13, 3),
-        MCFGPF(DATAH, 16, 8),
-        MCFGPF(DATAL, 24, 8),
-        MCFGPF(BUSCTL, 32, 8),
-        MCFGPF(BS, 40, 4),
-        MCFGPF(CS, 49, 7),
-        MCFGPF(SDRAM, 56, 6),
-        MCFGPF(FECI2C, 64, 4),
-        MCFGPF(UARTH, 72, 2),
-        MCFGPF(UARTL, 80, 8),
-        MCFGPF(QSPI, 88, 5),
-        MCFGPF(TIMER, 96, 8),
-        MCFGPF(ETPU, 104, 3),
-};
-
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
 
 /***************************************************************************/
 
diff --git a/arch/m68k/platform/coldfire/m5249.c b/arch/m68k/platform/coldfire/m5249.c
index fdfa1edfd1a..300e729a58d 100644
--- a/arch/m68k/platform/coldfire/m5249.c
+++ b/arch/m68k/platform/coldfire/m5249.c
@@ -16,16 +16,6 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-
-/***************************************************************************/
-
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-        MCFGPS(GPIO0, 0, 32, MCFSIM2_GPIOENABLE, MCFSIM2_GPIOWRITE, MCFSIM2_GPIOREAD),
-        MCFGPS(GPIO1, 32, 32, MCFSIM2_GPIO1ENABLE, MCFSIM2_GPIO1WRITE, MCFSIM2_GPIO1READ),
-};
-
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
 
 /***************************************************************************/
 
diff --git a/arch/m68k/platform/coldfire/m525x.c b/arch/m68k/platform/coldfire/m525x.c
new file mode 100644
index 00000000000..8ce905f9b84
--- /dev/null
+++ b/arch/m68k/platform/coldfire/m525x.c
@@ -0,0 +1,66 @@
+/***************************************************************************/
+
+/*
+ *      525x.c
+ *
+ *      Copyright (C) 2012, Steven King <sfking@fdwdc.com>
+ */
+
+/***************************************************************************/
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+
+/***************************************************************************/
+
+static void __init m525x_qspi_init(void)
+{
+#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
+        /* set the GPIO function for the qspi cs gpios */
+        /* FIXME: replace with pinmux/pinctl support */
+        u32 f = readl(MCFSIM2_GPIOFUNC);
+        f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
+        writel(f, MCFSIM2_GPIOFUNC);
+
+        /* QSPI irq setup */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
+               MCF_MBAR + MCFSIM_QSPIICR);
+        mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
+#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
+}
+
+static void __init m525x_i2c_init(void)
+{
+#if IS_ENABLED(CONFIG_I2C_COLDFIRE)
+        u32 r;
+
+        /* first I2C controller uses regular irq setup */
+        writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
+                        MCF_MBAR + MCFSIM_I2CICR);
+        mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
+
+        /* second I2C controller is completely different */
+        r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
+        r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
+        r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
+        writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
+#endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */
+}
+
+/***************************************************************************/
+
+void __init config_BSP(char *commandp, int size)
+{
+        mach_sched_init = hw_timer_init;
+
+        m525x_qspi_init();
+        m525x_i2c_init();
+}
+
+/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5272.c b/arch/m68k/platform/coldfire/m5272.c
index 43e36060da1..e68bc7a148e 100644
--- a/arch/m68k/platform/coldfire/m5272.c
+++ b/arch/m68k/platform/coldfire/m5272.c
@@ -19,7 +19,6 @@
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
-#include <asm/mcfgpio.h>
 
 /***************************************************************************/
 
@@ -31,16 +30,6 @@ unsigned char ledbank = 0xff;
 
 /***************************************************************************/
 
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-        MCFGPS(PA,  0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
-        MCFGPS(PB, 16, 16, MCFSIM_PBDDR, MCFSIM_PBDAT, MCFSIM_PBDAT),
-        MCFGPS(Pc, 32, 16, MCFSIM_PCDDR, MCFSIM_PCDAT, MCFSIM_PCDAT),
-};
-
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
-
-/***************************************************************************/
-
 static void __init m5272_uarts_init(void)
 {
         u32 v;
diff --git a/arch/m68k/platform/coldfire/m527x.c b/arch/m68k/platform/coldfire/m527x.c
index 9b0b66aabd1..b3cb378c5e9 100644
--- a/arch/m68k/platform/coldfire/m527x.c
+++ b/arch/m68k/platform/coldfire/m527x.c
@@ -20,49 +20,6 @@
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
-#include <asm/mcfgpio.h>
-
-/***************************************************************************/
-
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-#if defined(CONFIG_M5271)
-        MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
-        MCFGPF(ADDR, 13, 3),
-        MCFGPF(DATAH, 16, 8),
-        MCFGPF(DATAL, 24, 8),
-        MCFGPF(BUSCTL, 32, 8),
-        MCFGPF(BS, 40, 4),
-        MCFGPF(CS, 49, 7),
-        MCFGPF(SDRAM, 56, 6),
-        MCFGPF(FECI2C, 64, 4),
-        MCFGPF(UARTH, 72, 2),
-        MCFGPF(UARTL, 80, 8),
-        MCFGPF(QSPI, 88, 5),
-        MCFGPF(TIMER, 96, 8),
-#elif defined(CONFIG_M5275)
-        MCFGPS(PIRQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
-        MCFGPF(BUSCTL, 8, 8),
-        MCFGPF(ADDR, 21, 3),
-        MCFGPF(CS, 25, 7),
-        MCFGPF(FEC0H, 32, 8),
-        MCFGPF(FEC0L, 40, 8),
-        MCFGPF(FECI2C, 48, 6),
-        MCFGPF(QSPI, 56, 7),
-        MCFGPF(SDRAM, 64, 8),
-        MCFGPF(TIMERH, 72, 4),
-        MCFGPF(TIMERL, 80, 4),
-        MCFGPF(UARTL, 88, 8),
-        MCFGPF(FEC1H, 96, 8),
-        MCFGPF(FEC1L, 104, 8),
-        MCFGPF(BS, 114, 2),
-        MCFGPF(IRQ, 121, 7),
-        MCFGPF(USBH, 128, 1),
-        MCFGPF(USBL, 136, 8),
-        MCFGPF(UARTH, 144, 4),
-#endif
-};
-
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
 
 /***************************************************************************/
 
diff --git a/arch/m68k/platform/coldfire/m528x.c b/arch/m68k/platform/coldfire/m528x.c
index 7ed1276b29d..f1319e5d254 100644
--- a/arch/m68k/platform/coldfire/m528x.c
+++ b/arch/m68k/platform/coldfire/m528x.c
@@ -21,37 +21,6 @@
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
-#include <asm/mcfgpio.h>
-
-/***************************************************************************/
-
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-        MCFGPS(NQ, 1, 7, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
-        MCFGPS(TA, 8, 4, MCFGPTA_GPTDDR, MCFGPTA_GPTPORT, MCFGPTB_GPTPORT),
-        MCFGPS(TB, 16, 4, MCFGPTB_GPTDDR, MCFGPTB_GPTPORT, MCFGPTB_GPTPORT),
-        MCFGPS(QA, 24, 4, MCFQADC_DDRQA, MCFQADC_PORTQA, MCFQADC_PORTQA),
-        MCFGPS(QB, 32, 4, MCFQADC_DDRQB, MCFQADC_PORTQB, MCFQADC_PORTQB),
-        MCFGPF(A, 40, 8),
-        MCFGPF(B, 48, 8),
-        MCFGPF(C, 56, 8),
-        MCFGPF(D, 64, 8),
-        MCFGPF(E, 72, 8),
-        MCFGPF(F, 80, 8),
-        MCFGPF(G, 88, 8),
-        MCFGPF(H, 96, 8),
-        MCFGPF(J, 104, 8),
-        MCFGPF(DD, 112, 8),
-        MCFGPF(EH, 120, 8),
-        MCFGPF(EL, 128, 8),
-        MCFGPF(AS, 136, 6),
-        MCFGPF(QS, 144, 7),
-        MCFGPF(SD, 152, 6),
-        MCFGPF(TC, 160, 4),
-        MCFGPF(TD, 168, 4),
-        MCFGPF(UA, 176, 4),
-};
-
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
 
 /***************************************************************************/
 
@@ -74,7 +43,7 @@ static void __init m528x_uarts_init(void)
         /* make sure PUAPAR is set for UART0 and UART1 */
         port = readb(MCF5282_GPIO_PUAPAR);
         port |= 0x03 | (0x03 << 2);
-        writeb(port, MCF5282_GPIO_PUAPAR);
+        writeb(port, MCFGPIO_PUAPAR);
 }
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/m5307.c b/arch/m68k/platform/coldfire/m5307.c
index 93b484976ab..a568d2870d1 100644
--- a/arch/m68k/platform/coldfire/m5307.c
+++ b/arch/m68k/platform/coldfire/m5307.c
@@ -16,7 +16,6 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
 #include <asm/mcfwdebug.h>
 
 /***************************************************************************/
@@ -29,14 +28,6 @@ unsigned char ledbank = 0xff;
 
 /***************************************************************************/
 
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-        MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
-};
-
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
-
-/***************************************************************************/
-
 void __init config_BSP(char *commandp, int size)
 {
 #if defined(CONFIG_NETtel) || \
diff --git a/arch/m68k/platform/coldfire/m532x.c b/arch/m68k/platform/coldfire/m532x.c
index 5394223639f..4819a44991e 100644
--- a/arch/m68k/platform/coldfire/m532x.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -26,32 +26,144 @@
 #include <asm/mcfsim.h>
 #include <asm/mcfuart.h>
 #include <asm/mcfdma.h>
-#include <asm/mcfgpio.h>
 #include <asm/mcfwdebug.h>
+#include <asm/mcfclk.h>
 
 /***************************************************************************/
 
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-        MCFGPS(PIRQ, 0, 8, MCFEPORT_EPDDR, MCFEPORT_EPDR, MCFEPORT_EPPDR),
-        MCFGPF(FECH, 8, 8),
-        MCFGPF(FECL, 16, 8),
-        MCFGPF(SSI, 24, 5),
-        MCFGPF(BUSCTL, 32, 4),
-        MCFGPF(BE, 40, 4),
-        MCFGPF(CS, 49, 5),
-        MCFGPF(PWM, 58, 4),
-        MCFGPF(FECI2C, 64, 4),
-        MCFGPF(UART, 72, 8),
-        MCFGPF(QSPI, 80, 6),
-        MCFGPF(TIMER, 88, 4),
-        MCFGPF(LCDDATAH, 96, 2),
-        MCFGPF(LCDDATAM, 104, 8),
-        MCFGPF(LCDDATAL, 112, 8),
-        MCFGPF(LCDCTLH, 120, 1),
-        MCFGPF(LCDCTLL, 128, 8),
+DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
+DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
+DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
+DEFINE_CLK(0, "edma", 17, MCF_CLK);
+DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
+DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
+DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
+DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
+DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
+DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
+DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
+
+DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
+DEFINE_CLK(0, "mcfpwm.0", 36, MCF_CLK);
+DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
+DEFINE_CLK(0, "mcfwdt.0", 38, MCF_CLK);
+DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
+DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
+DEFINE_CLK(0, "mcflcd.0", 43, MCF_CLK);
+DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
+DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
+DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
+DEFINE_CLK(0, "ssi.0", 47, MCF_CLK);
+DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
+
+DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
+DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
+DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
+
+struct clk *mcf_clks[] = {
+        &__clk_0_2,     /* flexbus */
+        &__clk_0_8,     /* mcfcan.0 */
+        &__clk_0_12,    /* fec.0 */
+        &__clk_0_17,    /* edma */
+        &__clk_0_18,    /* intc.0 */
+        &__clk_0_19,    /* intc.1 */
+        &__clk_0_21,    /* iack.0 */
+        &__clk_0_22,    /* mcfi2c.0 */
+        &__clk_0_23,    /* mcfqspi.0 */
+        &__clk_0_24,    /* mcfuart.0 */
+        &__clk_0_25,    /* mcfuart.1 */
+        &__clk_0_26,    /* mcfuart.2 */
+        &__clk_0_28,    /* mcftmr.0 */
+        &__clk_0_29,    /* mcftmr.1 */
+        &__clk_0_30,    /* mcftmr.2 */
+        &__clk_0_31,    /* mcftmr.3 */
+
+        &__clk_0_32,    /* mcfpit.0 */
+        &__clk_0_33,    /* mcfpit.1 */
+        &__clk_0_34,    /* mcfpit.2 */
+        &__clk_0_35,    /* mcfpit.3 */
+        &__clk_0_36,    /* mcfpwm.0 */
+        &__clk_0_37,    /* mcfeport.0 */
+        &__clk_0_38,    /* mcfwdt.0 */
+        &__clk_0_40,    /* sys.0 */
+        &__clk_0_41,    /* gpio.0 */
+        &__clk_0_42,    /* mcfrtc.0 */
+        &__clk_0_43,    /* mcflcd.0 */
+        &__clk_0_44,    /* mcfusb-otg.0 */
+        &__clk_0_45,    /* mcfusb-host.0 */
+        &__clk_0_46,    /* sdram.0 */
+        &__clk_0_47,    /* ssi.0 */
+        &__clk_0_48,    /* pll.0 */
+
+        &__clk_1_32,    /* mdha.0 */
+        &__clk_1_33,    /* skha.0 */
+        &__clk_1_34,    /* rng.0 */
+        NULL,
+};
+
+static struct clk * const enable_clks[] __initconst = {
+        &__clk_0_2,     /* flexbus */
+        &__clk_0_18,    /* intc.0 */
+        &__clk_0_19,    /* intc.1 */
+        &__clk_0_21,    /* iack.0 */
+        &__clk_0_24,    /* mcfuart.0 */
+        &__clk_0_25,    /* mcfuart.1 */
+        &__clk_0_26,    /* mcfuart.2 */
+
+        &__clk_0_32,    /* mcfpit.0 */
+        &__clk_0_33,    /* mcfpit.1 */
+        &__clk_0_37,    /* mcfeport.0 */
+        &__clk_0_40,    /* sys.0 */
+        &__clk_0_41,    /* gpio.0 */
+        &__clk_0_46,    /* sdram.0 */
+        &__clk_0_48,    /* pll.0 */
+};
+
+static struct clk * const disable_clks[] __initconst = {
+        &__clk_0_8,     /* mcfcan.0 */
+        &__clk_0_12,    /* fec.0 */
+        &__clk_0_17,    /* edma */
+        &__clk_0_22,    /* mcfi2c.0 */
+        &__clk_0_23,    /* mcfqspi.0 */
+        &__clk_0_28,    /* mcftmr.0 */
+        &__clk_0_29,    /* mcftmr.1 */
+        &__clk_0_30,    /* mcftmr.2 */
+        &__clk_0_31,    /* mcftmr.3 */
+        &__clk_0_34,    /* mcfpit.2 */
+        &__clk_0_35,    /* mcfpit.3 */
+        &__clk_0_36,    /* mcfpwm.0 */
+        &__clk_0_38,    /* mcfwdt.0 */
+        &__clk_0_42,    /* mcfrtc.0 */
+        &__clk_0_43,    /* mcflcd.0 */
+        &__clk_0_44,    /* mcfusb-otg.0 */
+        &__clk_0_45,    /* mcfusb-host.0 */
+        &__clk_0_47,    /* ssi.0 */
+        &__clk_1_32,    /* mdha.0 */
+        &__clk_1_33,    /* skha.0 */
+        &__clk_1_34,    /* rng.0 */
 };
 
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
+
+static void __init m532x_clk_init(void)
+{
+        unsigned i;
+
+        /* make sure these clocks are enabled */
+        for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
+                __clk_init_enabled(enable_clks[i]);
+        /* make sure these clocks are disabled */
+        for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
+                __clk_init_disabled(disable_clks[i]);
+}
 
 /***************************************************************************/
 
@@ -98,8 +210,8 @@ void __init config_BSP(char *commandp, int size)
                 memset(commandp, 0, size);
         }
 #endif
-
         mach_sched_init = hw_timer_init;
+        m532x_clk_init();
         m532x_uarts_init();
         m532x_fec_init();
 #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
diff --git a/arch/m68k/platform/coldfire/m5407.c b/arch/m68k/platform/coldfire/m5407.c
index faa6680b340..bb6c746ae81 100644
--- a/arch/m68k/platform/coldfire/m5407.c
+++ b/arch/m68k/platform/coldfire/m5407.c
@@ -16,15 +16,6 @@
 #include <asm/machdep.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
-#include <asm/mcfgpio.h>
-
-/***************************************************************************/
-
-struct mcf_gpio_chip mcf_gpio_chips[] = {
-        MCFGPS(PP, 0, 16, MCFSIM_PADDR, MCFSIM_PADAT, MCFSIM_PADAT),
-};
-
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
 
 /***************************************************************************/
 
diff --git a/arch/m68k/platform/coldfire/m5441x.c b/arch/m68k/platform/coldfire/m5441x.c
new file mode 100644
index 00000000000..98a13cce93d
--- /dev/null
+++ b/arch/m68k/platform/coldfire/m5441x.c
@@ -0,0 +1,261 @@
+/*
+ *      m5441x.c -- support for Coldfire m5441x processors
+ *
+ *      (C) Copyright Steven King <sfking@fdwdc.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <asm/machdep.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/mcfuart.h>
+#include <asm/mcfdma.h>
+#include <asm/mcfclk.h>
+
+DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
+DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
+DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
+DEFINE_CLK(0, "mcfi2c.1", 14, MCF_CLK);
+DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
+DEFINE_CLK(0, "edma", 17, MCF_CLK);
+DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
+DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
+DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
+DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
+DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK);
+DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK);
+DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
+DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
+DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK);
+DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK);
+DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
+DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK);
+DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
+DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
+DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
+DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK);
+DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
+DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK);
+DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK);
+DEFINE_CLK(0, "mcfsdhc.0", 51, MCF_CLK);
+DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
+DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
+DEFINE_CLK(0, "switch.0", 55, MCF_CLK);
+DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
+DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
+
+DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
+DEFINE_CLK(1, "mcfi2c.2", 4, MCF_CLK);
+DEFINE_CLK(1, "mcfi2c.3", 5, MCF_CLK);
+DEFINE_CLK(1, "mcfi2c.4", 6, MCF_CLK);
+DEFINE_CLK(1, "mcfi2c.5", 7, MCF_CLK);
+DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfuart.7", 27, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfuart.8", 28, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfuart.9", 29, MCF_BUSCLK);
+DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK);
+DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK);
+DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK);
+
+struct clk *mcf_clks[] = {
+        &__clk_0_2,
+        &__clk_0_8,
+        &__clk_0_9,
+        &__clk_0_14,
+        &__clk_0_15,
+        &__clk_0_17,
+        &__clk_0_18,
+        &__clk_0_19,
+        &__clk_0_20,
+        &__clk_0_22,
+        &__clk_0_23,
+        &__clk_0_24,
+        &__clk_0_25,
+        &__clk_0_26,
+        &__clk_0_27,
+        &__clk_0_28,
+        &__clk_0_29,
+        &__clk_0_30,
+        &__clk_0_31,
+        &__clk_0_32,
+        &__clk_0_33,
+        &__clk_0_34,
+        &__clk_0_35,
+        &__clk_0_37,
+        &__clk_0_38,
+        &__clk_0_39,
+        &__clk_0_42,
+        &__clk_0_43,
+        &__clk_0_44,
+        &__clk_0_45,
+        &__clk_0_46,
+        &__clk_0_47,
+        &__clk_0_48,
+        &__clk_0_49,
+        &__clk_0_50,
+        &__clk_0_51,
+        &__clk_0_53,
+        &__clk_0_54,
+        &__clk_0_55,
+        &__clk_0_56,
+        &__clk_0_63,
+
+        &__clk_1_2,
+        &__clk_1_4,
+        &__clk_1_5,
+        &__clk_1_6,
+        &__clk_1_7,
+        &__clk_1_24,
+        &__clk_1_25,
+        &__clk_1_26,
+        &__clk_1_27,
+        &__clk_1_28,
+        &__clk_1_29,
+        &__clk_1_34,
+        &__clk_1_36,
+        &__clk_1_37,
+        NULL,
+};
+
+
+static struct clk * const enable_clks[] __initconst = {
+        /* make sure these clocks are enabled */
+        &__clk_0_18, /* intc0 */
+        &__clk_0_19, /* intc0 */
+        &__clk_0_20, /* intc0 */
+        &__clk_0_24, /* uart0 */
+        &__clk_0_25, /* uart1 */
+        &__clk_0_26, /* uart2 */
+        &__clk_0_27, /* uart3 */
+
+        &__clk_0_33, /* pit.1 */
+        &__clk_0_37, /* eport */
+        &__clk_0_48, /* pll */
+
+        &__clk_1_36, /* CCM/reset module/Power management */
+        &__clk_1_37, /* gpio */
+};
+static struct clk * const disable_clks[] __initconst = {
+        &__clk_0_8, /* can.0 */
+        &__clk_0_9, /* can.1 */
+        &__clk_0_14, /* i2c.1 */
+        &__clk_0_15, /* dspi.1 */
+        &__clk_0_17, /* eDMA */
+        &__clk_0_22, /* i2c.0 */
+        &__clk_0_23, /* dspi.0 */
+        &__clk_0_28, /* tmr.1 */
+        &__clk_0_29, /* tmr.2 */
+        &__clk_0_30, /* tmr.2 */
+        &__clk_0_31, /* tmr.3 */
+        &__clk_0_32, /* pit.0 */
+        &__clk_0_34, /* pit.2 */
+        &__clk_0_35, /* pit.3 */
+        &__clk_0_38, /* adc */
+        &__clk_0_39, /* dac */
+        &__clk_0_44, /* usb otg */
+        &__clk_0_45, /* usb host */
+        &__clk_0_47, /* ssi.0 */
+        &__clk_0_49, /* rng */
+        &__clk_0_50, /* ssi.1 */
+        &__clk_0_51, /* eSDHC */
+        &__clk_0_53, /* enet-fec */
+        &__clk_0_54, /* enet-fec */
+        &__clk_0_55, /* switch.0 */
+        &__clk_0_56, /* switch.1 */
+
+        &__clk_1_2, /* 1-wire */
+        &__clk_1_4, /* i2c.2 */
+        &__clk_1_5, /* i2c.3 */
+        &__clk_1_6, /* i2c.4 */
+        &__clk_1_7, /* i2c.5 */
+        &__clk_1_24, /* uart 4 */
+        &__clk_1_25, /* uart 5 */
+        &__clk_1_26, /* uart 6 */
+        &__clk_1_27, /* uart 7 */
+        &__clk_1_28, /* uart 8 */
+        &__clk_1_29, /* uart 9 */
+};
+
+static void __init m5441x_clk_init(void)
+{
+        unsigned i;
+
+        for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
+                __clk_init_enabled(enable_clks[i]);
+        /* make sure these clocks are disabled */
+        for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
+                __clk_init_disabled(disable_clks[i]);
+}
+
+static void __init m5441x_uarts_init(void)
+{
+        __raw_writeb(0x0f, MCFGPIO_PAR_UART0);
+        __raw_writeb(0x00, MCFGPIO_PAR_UART1);
+        __raw_writeb(0x00, MCFGPIO_PAR_UART2);
+}
+
+static void __init m5441x_fec_init(void)
+{
+        __raw_writeb(0x03, MCFGPIO_PAR_FEC);
+}
+
+void __init config_BSP(char *commandp, int size)
+{
+        m5441x_clk_init();
+        mach_sched_init = hw_timer_init;
+        m5441x_uarts_init();
+        m5441x_fec_init();
+}
+
+
+#if IS_ENABLED(CONFIG_RTC_DRV_M5441x)
+static struct resource m5441x_rtc_resources[] = {
+        {
+                .start          = MCFRTC_BASE,
+                .end            = MCFRTC_BASE + MCFRTC_SIZE - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = MCF_IRQ_RTC,
+                .end            = MCF_IRQ_RTC,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device m5441x_rtc = {
+        .name                   = "mcfrtc",
+        .id                     = 0,
+        .resource               = m5441x_rtc_resources,
+        .num_resources          = ARRAY_SIZE(m5441x_rtc_resources),
+};
+#endif
+
+static struct platform_device *m5441x_devices[] __initdata = {
+#if IS_ENABLED(CONFIG_RTC_DRV_M5441x)
+        &m5441x_rtc,
+#endif
+};
+
+static int __init init_BSP(void)
+{
+        platform_add_devices(m5441x_devices, ARRAY_SIZE(m5441x_devices));
+        return 0;
+}
+
+arch_initcall(init_BSP);
diff --git a/arch/m68k/platform/coldfire/m54xx.c b/arch/m68k/platform/coldfire/m54xx.c
index 20672dadb25..2081c6cbb3d 100644
--- a/arch/m68k/platform/coldfire/m54xx.c
+++ b/arch/m68k/platform/coldfire/m54xx.c
@@ -21,19 +21,12 @@
 #include <asm/m54xxsim.h>
 #include <asm/mcfuart.h>
 #include <asm/m54xxgpt.h>
-#include <asm/mcfgpio.h>
 #ifdef CONFIG_MMU
 #include <asm/mmu_context.h>
 #endif
 
 /***************************************************************************/
 
-struct mcf_gpio_chip mcf_gpio_chips[] = { };
-
-unsigned int mcf_gpio_chips_size = ARRAY_SIZE(mcf_gpio_chips);
-
-/***************************************************************************/
-
 static void __init m54xx_uarts_init(void)
 {
         /* enable io pins */
diff --git a/arch/m68k/platform/coldfire/mcf8390.c b/arch/m68k/platform/coldfire/mcf8390.c
new file mode 100644
index 00000000000..23a6874a324
--- /dev/null
+++ b/arch/m68k/platform/coldfire/mcf8390.c
@@ -0,0 +1,38 @@
+/*
+ * mcf8390.c  -- platform support for 8390 ethernet on many boards
+ *
+ * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.org>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <asm/mcf8390.h>
+
+static struct resource mcf8390_resources[] = {
+        {
+                .start  = NE2000_ADDR,
+                .end    = NE2000_ADDR + NE2000_ADDRSIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = NE2000_IRQ_VECTOR,
+                .end    = NE2000_IRQ_VECTOR,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static int __init mcf8390_platform_init(void)
+{
+        platform_device_register_simple("mcf8390", -1, mcf8390_resources,
+                ARRAY_SIZE(mcf8390_resources));
+        return 0;
+}
+
+arch_initcall(mcf8390_platform_init);
diff --git a/arch/m68k/platform/coldfire/pci.c b/arch/m68k/platform/coldfire/pci.c
new file mode 100644
index 00000000000..553210d3d4c
--- /dev/null
+++ b/arch/m68k/platform/coldfire/pci.c
@@ -0,0 +1,327 @@
+/*
+ * pci.c -- PCI bus support for ColdFire processors
+ *
+ * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
+#include <asm/m54xxpci.h>
+
+/*
+ * Memory and IO mappings. We use a 1:1 mapping for local host memory to
+ * PCI bus memory (no reason not to really). IO space doesn't matter, we
+ * always use access functions for that. The device configuration space is
+ * mapped over the IO map space when we enable it in the PCICAR register.
+ */
+#define PCI_MEM_PA      0xf0000000              /* Host physical address */
+#define PCI_MEM_BA      0xf0000000              /* Bus physical address */
+#define PCI_MEM_SIZE    0x08000000              /* 128 MB */
+#define PCI_MEM_MASK    (PCI_MEM_SIZE - 1)
+
+#define PCI_IO_PA       0xf8000000              /* Host physical address */
+#define PCI_IO_BA       0x00000000              /* Bus physical address */
+#define PCI_IO_SIZE     0x00010000              /* 64k */
+#define PCI_IO_MASK     (PCI_IO_SIZE - 1)
+
+static struct pci_bus *rootbus;
+static unsigned long iospace;
+
+/*
+ * We need to be carefull probing on bus 0 (directly connected to host
+ * bridge). We should only acccess the well defined possible devices in
+ * use, ignore aliases and the like.
+ */
+static unsigned char mcf_host_slot2sid[32] = {
+        0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0,
+        0, 1, 2, 0, 3, 4, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0,
+};
+
+static unsigned char mcf_host_irq[] = {
+        0, 69, 69, 71, 71,
+};
+
+
+static inline void syncio(void)
+{
+        /* The ColdFire "nop" instruction waits for all bus IO to complete */
+        __asm__ __volatile__ ("nop");
+}
+
+/*
+ * Configuration space access functions. Configuration space access is
+ * through the IO mapping window, enabling it via the PCICAR register.
+ */
+static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where)
+{
+        return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc);
+}
+
+static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
+        int where, int size, u32 *value)
+{
+        unsigned long addr;
+
+        *value = 0xffffffff;
+
+        if (bus->number == 0) {
+                if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
+                        return PCIBIOS_SUCCESSFUL;
+        }
+
+        syncio();
+        addr = mcf_mk_pcicar(bus->number, devfn, where);
+        __raw_writel(PCICAR_E | addr, PCICAR);
+        addr = iospace + (where & 0x3);
+
+        switch (size) {
+        case 1:
+                *value = __raw_readb(addr);
+                break;
+        case 2:
+                *value = le16_to_cpu(__raw_readw(addr));
+                break;
+        default:
+                *value = le32_to_cpu(__raw_readl(addr));
+                break;
+        }
+
+        syncio();
+        __raw_writel(0, PCICAR);
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
+        int where, int size, u32 value)
+{
+        unsigned long addr;
+
+        if (bus->number == 0) {
+                if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
+                        return PCIBIOS_SUCCESSFUL;
+        }
+
+        syncio();
+        addr = mcf_mk_pcicar(bus->number, devfn, where);
+        __raw_writel(PCICAR_E | addr, PCICAR);
+        addr = iospace + (where & 0x3);
+
+        switch (size) {
+        case 1:
+                 __raw_writeb(value, addr);
+                break;
+        case 2:
+                __raw_writew(cpu_to_le16(value), addr);
+                break;
+        default:
+                __raw_writel(cpu_to_le32(value), addr);
+                break;
+        }
+
+        syncio();
+        __raw_writel(0, PCICAR);
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static struct pci_ops mcf_pci_ops = {
+        .read   = mcf_pci_readconfig,
+        .write  = mcf_pci_writeconfig,
+};
+
+/*
+ *      IO address space access functions. Pretty strait forward, these are
+ *      directly mapped in to the IO mapping window. And that is mapped into
+ *      virtual address space.
+ */
+u8 mcf_pci_inb(u32 addr)
+{
+        return __raw_readb(iospace + (addr & PCI_IO_MASK));
+}
+EXPORT_SYMBOL(mcf_pci_inb);
+
+u16 mcf_pci_inw(u32 addr)
+{
+        return le16_to_cpu(__raw_readw(iospace + (addr & PCI_IO_MASK)));
+}
+EXPORT_SYMBOL(mcf_pci_inw);
+
+u32 mcf_pci_inl(u32 addr)
+{
+        return le32_to_cpu(__raw_readl(iospace + (addr & PCI_IO_MASK)));
+}
+EXPORT_SYMBOL(mcf_pci_inl);
+
+void mcf_pci_insb(u32 addr, u8 *buf, u32 len)
+{
+        for (; len; len--)
+                *buf++ = mcf_pci_inb(addr);
+}
+EXPORT_SYMBOL(mcf_pci_insb);
+
+void mcf_pci_insw(u32 addr, u16 *buf, u32 len)
+{
+        for (; len; len--)
+                *buf++ = mcf_pci_inw(addr);
+}
+EXPORT_SYMBOL(mcf_pci_insw);
+
+void mcf_pci_insl(u32 addr, u32 *buf, u32 len)
+{
+        for (; len; len--)
+                *buf++ = mcf_pci_inl(addr);
+}
+EXPORT_SYMBOL(mcf_pci_insl);
+
+void mcf_pci_outb(u8 v, u32 addr)
+{
+        __raw_writeb(v, iospace + (addr & PCI_IO_MASK));
+}
+EXPORT_SYMBOL(mcf_pci_outb);
+
+void mcf_pci_outw(u16 v, u32 addr)
+{
+        __raw_writew(cpu_to_le16(v), iospace + (addr & PCI_IO_MASK));
+}
+EXPORT_SYMBOL(mcf_pci_outw);
+
+void mcf_pci_outl(u32 v, u32 addr)
+{
+        __raw_writel(cpu_to_le32(v), iospace + (addr & PCI_IO_MASK));
+}
+EXPORT_SYMBOL(mcf_pci_outl);
+
+void mcf_pci_outsb(u32 addr, const u8 *buf, u32 len)
+{
+        for (; len; len--)
+                mcf_pci_outb(*buf++, addr);
+}
+EXPORT_SYMBOL(mcf_pci_outsb);
+
+void mcf_pci_outsw(u32 addr, const u16 *buf, u32 len)
+{
+        for (; len; len--)
+                mcf_pci_outw(*buf++, addr);
+}
+EXPORT_SYMBOL(mcf_pci_outsw);
+
+void mcf_pci_outsl(u32 addr, const u32 *buf, u32 len)
+{
+        for (; len; len--)
+                mcf_pci_outl(*buf++, addr);
+}
+EXPORT_SYMBOL(mcf_pci_outsl);
+
+/*
+ * Initialize the PCI bus registers, and scan the bus.
+ */
+static struct resource mcf_pci_mem = {
+        .name   = "PCI Memory space",
+        .start  = PCI_MEM_PA,
+        .end    = PCI_MEM_PA + PCI_MEM_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource mcf_pci_io = {
+        .name   = "PCI IO space",
+        .start  = 0x400,
+        .end    = 0x10000 - 1,
+        .flags  = IORESOURCE_IO,
+};
+
+/*
+ * Interrupt mapping and setting.
+ */
+static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int sid;
+
+        sid = mcf_host_slot2sid[slot];
+        if (sid)
+                return mcf_host_irq[sid];
+        return 0;
+}
+
+static int __init mcf_pci_init(void)
+{
+        pr_info("ColdFire: PCI bus initialization...\n");
+
+        /* Reset the external PCI bus */
+        __raw_writel(PCIGSCR_RESET, PCIGSCR);
+        __raw_writel(0, PCITCR);
+
+        request_resource(&iomem_resource, &mcf_pci_mem);
+        request_resource(&iomem_resource, &mcf_pci_io);
+
+        /* Configure PCI arbiter */
+        __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
+                PACR_EXTMINTE(0x1f), PACR);
+
+        /* Set required multi-function pins for PCI bus use */
+        __raw_writew(0x3ff, MCF_PAR_PCIBG);
+        __raw_writew(0x3ff, MCF_PAR_PCIBR);
+
+        /* Set up config space for local host bus controller */
+        __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+                PCI_COMMAND_INVALIDATE, PCISCR);
+        __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
+        __raw_writel(0, PCICR2);
+
+        /*
+         * Set up the initiator windows for memory and IO mapping.
+         * These give the CPU bus access onto the PCI bus. One for each of
+         * PCI memory and IO address spaces.
+         */
+        __raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
+                PCIIW0BTAR);
+        __raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
+                PCIIW1BTAR);
+        __raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
+                PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
+
+        /*
+         * Set up the target windows for access from the PCI bus back to the
+         * CPU bus. All we need is access to system RAM (for mastering).
+         */
+        __raw_writel(CONFIG_RAMBASE, PCIBAR1);
+        __raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
+
+        /* Keep a virtual mapping to IO/config space active */
+        iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
+        if (iospace == 0)
+                return -ENODEV;
+        pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n",
+                (u32) iospace);
+
+        /* Turn of PCI reset, and wait for devices to settle */
+        __raw_writel(0, PCIGSCR);
+        set_current_state(TASK_UNINTERRUPTIBLE);
+        schedule_timeout(msecs_to_jiffies(200));
+
+        rootbus = pci_scan_bus(0, &mcf_pci_ops, NULL);
+        rootbus->resource[0] = &mcf_pci_io;
+        rootbus->resource[1] = &mcf_pci_mem;
+
+        pci_fixup_irqs(pci_common_swizzle, mcf_pci_map_irq);
+        pci_bus_size_bridges(rootbus);
+        pci_bus_assign_resources(rootbus);
+        pci_enable_bridges(rootbus);
+        pci_bus_add_devices(rootbus);
+        return 0;
+}
+
+subsys_initcall(mcf_pci_init);
diff --git a/arch/m68k/platform/coldfire/pinmux.c b/arch/m68k/platform/coldfire/pinmux.c
deleted file mode 100644
index 8c62b825939..00000000000
--- a/arch/m68k/platform/coldfire/pinmux.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Coldfire generic GPIO pinmux support.
- *
- * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; version 2 of the License.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-
-#include <asm/pinmux.h>
-
-int mcf_pinmux_request(unsigned pinmux, unsigned func)
-{
-        return 0;
-}
-
-void mcf_pinmux_release(unsigned pinmux, unsigned func)
-{
-}
diff --git a/arch/m68k/platform/coldfire/pit.c b/arch/m68k/platform/coldfire/pit.c
index e62dbbcb10f..e8f3b97b0f7 100644
--- a/arch/m68k/platform/coldfire/pit.c
+++ b/arch/m68k/platform/coldfire/pit.c
@@ -93,7 +93,7 @@ struct clock_event_device cf_pit_clockevent = {
         .set_mode       = init_cf_pit_timer,
         .set_next_event = cf_pit_next_event,
         .shift          = 32,
-        .irq            = MCFINT_VECBASE + MCFINT_PIT1,
+        .irq            = MCF_IRQ_PIT1,
 };
 
 
@@ -159,7 +159,7 @@ void hw_timer_init(irq_handler_t handler)
                 clockevent_delta2ns(0x3f, &cf_pit_clockevent);
         clockevents_register_device(&cf_pit_clockevent);
 
-        setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
+        setup_irq(MCF_IRQ_PIT1, &pit_irq);
 
         clocksource_register_hz(&pit_clk, FREQ);
 }
diff --git a/arch/m68k/platform/coldfire/timers.c b/arch/m68k/platform/coldfire/timers.c
index ed96ce50d79..0a273e75408 100644
--- a/arch/m68k/platform/coldfire/timers.c
+++ b/arch/m68k/platform/coldfire/timers.c
@@ -36,7 +36,7 @@
  */
 void coldfire_profile_init(void);
 
-#if defined(CONFIG_M532x)
+#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
 #define __raw_readtrr   __raw_readl
 #define __raw_writetrr  __raw_writel
 #else
diff --git a/arch/m68k/sun3/prom/init.c b/arch/m68k/sun3/prom/init.c
index d8e6349336b..eeba067d565 100644
--- a/arch/m68k/sun3/prom/init.c
+++ b/arch/m68k/sun3/prom/init.c
@@ -22,57 +22,13 @@ int prom_root_node;
 struct linux_nodeops *prom_nodeops;
 
 /* You must call prom_init() before you attempt to use any of the
- * routines in the prom library.  It returns 0 on success, 1 on
- * failure.  It gets passed the pointer to the PROM vector.
+ * routines in the prom library.
+ * It gets passed the pointer to the PROM vector.
  */
 
-extern void prom_meminit(void);
-extern void prom_ranges_init(void);
-
 void __init prom_init(struct linux_romvec *rp)
 {
         romvec = rp;
-#ifndef CONFIG_SUN3
-        switch(romvec->pv_romvers) {
-        case 0:
-                prom_vers = PROM_V0;
-                break;
-        case 2:
-                prom_vers = PROM_V2;
-                break;
-        case 3:
-                prom_vers = PROM_V3;
-                break;
-        case 4:
-                prom_vers = PROM_P1275;
-                prom_printf("PROMLIB: Sun IEEE Prom not supported yet\n");
-                prom_halt();
-                break;
-        default:
-                prom_printf("PROMLIB: Bad PROM version %d\n",
-                            romvec->pv_romvers);
-                prom_halt();
-                break;
-        };
-
-        prom_rev = romvec->pv_plugin_revision;
-        prom_prev = romvec->pv_printrev;
-        prom_nodeops = romvec->pv_nodeops;
-
-        prom_root_node = prom_getsibling(0);
-        if((prom_root_node == 0) || (prom_root_node == -1))
-                prom_halt();
-
-        if((((unsigned long) prom_nodeops) == 0) ||
-           (((unsigned long) prom_nodeops) == -1))
-                prom_halt();
-
-        prom_meminit();
-
-        prom_ranges_init();
-#endif
-//      printk("PROMLIB: Sun Boot Prom Version %d Revision %d\n",
-//             romvec->pv_romvers, prom_rev);
 
         /* Initialization successful. */
         return;
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 0bf44231aaf..ab9afcaa7f6 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -15,6 +15,7 @@ config MICROBLAZE
         select TRACING_SUPPORT
         select OF
         select OF_EARLY_FLATTREE
+        select ARCH_WANT_IPC_PARSE_VERSION
         select IRQ_DOMAIN
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_PROBE
diff --git a/arch/microblaze/include/asm/sections.h b/arch/microblaze/include/asm/sections.h
index 4487e150b45..c07ed5d2a82 100644
--- a/arch/microblaze/include/asm/sections.h
+++ b/arch/microblaze/include/asm/sections.h
@@ -18,10 +18,6 @@ extern char _ssbss[], _esbss[];
 extern unsigned long __ivt_start[], __ivt_end[];
 extern char _etext[], _stext[];
 
-#  ifdef CONFIG_MTD_UCLINUX
-extern char *_ebss;
-#  endif
-
 extern u32 _fdt_start[], _fdt_end[];
 
 # endif /* !__ASSEMBLY__ */
diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h
index d20ffbc86be..6985e6e9d82 100644
--- a/arch/microblaze/include/asm/unistd.h
+++ b/arch/microblaze/include/asm/unistd.h
@@ -400,7 +400,6 @@
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 /* #define __ARCH_WANT_OLD_READDIR */
 /* #define __ARCH_WANT_OLD_STAT */
 #define __ARCH_WANT_STAT64
diff --git a/arch/microblaze/kernel/microblaze_ksyms.c b/arch/microblaze/kernel/microblaze_ksyms.c
index bb4907c828d..2b25bcf05c0 100644
--- a/arch/microblaze/kernel/microblaze_ksyms.c
+++ b/arch/microblaze/kernel/microblaze_ksyms.c
@@ -21,9 +21,6 @@
 #include <linux/ftrace.h>
 #include <linux/uaccess.h>
 
-extern char *_ebss;
-EXPORT_SYMBOL_GPL(_ebss);
-
 #ifdef CONFIG_FUNCTION_TRACER
 extern void _mcount(void);
 EXPORT_SYMBOL(_mcount);
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index 16d8dfd9094..4da971d4392 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -121,7 +121,7 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
 
         /* Move ROMFS out of BSS before clearing it */
         if (romfs_size > 0) {
-                memmove(&_ebss, (int *)romfs_base, romfs_size);
+                memmove(&__bss_stop, (int *)romfs_base, romfs_size);
                 klimit += romfs_size;
         }
 #endif
@@ -165,7 +165,7 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
         BUG_ON(romfs_size < 0); /* What else can we do? */
 
         printk("Moved 0x%08x bytes from 0x%08x to 0x%08x\n",
-                        romfs_size, romfs_base, (unsigned)&_ebss);
+                        romfs_size, romfs_base, (unsigned)&__bss_stop);
 
         printk("New klimit: 0x%08x\n", (unsigned)klimit);
 #endif
diff --git a/arch/microblaze/kernel/vmlinux.lds.S b/arch/microblaze/kernel/vmlinux.lds.S
index 109e9d86ade..936d01a689d 100644
--- a/arch/microblaze/kernel/vmlinux.lds.S
+++ b/arch/microblaze/kernel/vmlinux.lds.S
@@ -131,7 +131,6 @@ SECTIONS {
                         *(COMMON)
                 . = ALIGN (4) ;
                 __bss_stop = . ;
-                _ebss = . ;
         }
         . = ALIGN(PAGE_SIZE);
         _end = .;
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index ed22bfc5db1..4dbb5055d04 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -192,11 +192,6 @@ void pcibios_set_master(struct pci_dev *dev)
         /* No special bus mastering setup handling */
 }
 
-char __devinit *pcibios_setup(char *str)
-{
-        return str;
-}
-
 /*
  * Reads the interrupt pin to determine if interrupt is use by card.
  * If the interrupt is used, then gets the interrupt line from the
@@ -249,8 +244,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
         } else {
                 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
                          oirq.size, oirq.specifier[0], oirq.specifier[1],
-                         oirq.controller ? oirq.controller->full_name :
-                         "<default>");
+                         of_node_full_name(oirq.controller));
 
                 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
                                              oirq.size);
@@ -1493,8 +1487,7 @@ static void __devinit pcibios_scan_phb(struct pci_controller *hose)
         struct pci_bus *bus;
         struct device_node *node = hose->dn;
 
-        pr_debug("PCI: Scanning PHB %s\n",
-                 node ? node->full_name : "<NO NAME>");
+        pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
 
         pcibios_setup_phb_resources(hose, &resources);
 
@@ -1506,10 +1499,10 @@ static void __devinit pcibios_scan_phb(struct pci_controller *hose)
                 pci_free_resource_list(&resources);
                 return;
         }
-        bus->secondary = hose->first_busno;
+        bus->busn_res.start = hose->first_busno;
         hose->bus = bus;
 
-        hose->last_busno = bus->subordinate;
+        hose->last_busno = bus->busn_res.end;
 }
 
 static int __init pcibios_init(void)
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index 5ce8029f558..d64786d5e2f 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -14,6 +14,7 @@ platforms += jz4740
 platforms += lantiq
 platforms += lasat
 platforms += loongson
+platforms += loongson1
 platforms += mipssim
 platforms += mti-malta
 platforms += netlogic
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b3e10fdd389..faf65286574 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -20,12 +20,14 @@ config MIPS
         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
         select RTC_LIB if !MACH_LOONGSON
         select GENERIC_ATOMIC64 if !64BIT
+        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
         select HAVE_DMA_ATTRS
         select HAVE_DMA_API_DEBUG
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_PROBE
         select GENERIC_IRQ_SHOW
         select HAVE_ARCH_JUMP_LABEL
+        select ARCH_WANT_IPC_PARSE_VERSION
         select IRQ_FORCED_THREADING
         select HAVE_MEMBLOCK
         select HAVE_MEMBLOCK_NODE_MAP
@@ -75,6 +77,7 @@ config AR7
         select SYS_SUPPORTS_ZBOOT_UART16550
         select ARCH_REQUIRE_GPIOLIB
         select VLYNQ
+        select HAVE_CLK
         help
           Support for the Texas Instruments AR7 System-on-a-Chip
           family: TNETD7100, 7200 and 7300.
@@ -86,6 +89,7 @@ config ATH79
         select CEVT_R4K
         select CSRC_R4K
         select DMA_NONCOHERENT
+        select HAVE_CLK
         select IRQ_CPU
         select MIPS_MACHINE
         select SYS_HAS_CPU_MIPS32_R2
@@ -122,6 +126,7 @@ config BCM63XX
         select SYS_HAS_EARLY_PRINTK
         select SWAP_IO_SPACE
         select ARCH_REQUIRE_GPIOLIB
+        select HAVE_CLK
         help
          Support for BCM63XX based boards
 
@@ -209,6 +214,7 @@ config MACH_JZ4740
         select SYS_HAS_CPU_MIPS32_R1
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_ZBOOT_UART16550
         select DMA_NONCOHERENT
         select IRQ_CPU
         select GENERIC_GPIO
@@ -264,6 +270,16 @@ config MACH_LOONGSON
           Chinese Academy of Sciences (CAS) in the People's Republic
           of China. The chief architect is Professor Weiwu Hu.
 
+config MACH_LOONGSON1
+        bool "Loongson 1 family of machines"
+        select SYS_SUPPORTS_ZBOOT
+        help
+          This enables support for the Loongson 1 based machines.
+
+          Loongson 1 is a family of 32-bit MIPS-compatible SoCs developed by
+          the ICT (Institute of Computing Technology) and the Chinese Academy
+          of Sciences.
+
 config MIPS_MALTA
         bool "MIPS Malta board"
         select ARCH_MAY_HAVE_PC_FDC
@@ -787,6 +803,8 @@ config NLM_XLR_BOARD
         select ZONE_DMA if 64BIT
         select SYNC_R4K
         select SYS_HAS_EARLY_PRINTK
+        select USB_ARCH_HAS_OHCI if USB_SUPPORT
+        select USB_ARCH_HAS_EHCI if USB_SUPPORT
         help
           Support for systems based on Netlogic XLR and XLS processors.
           Say Y here if you have a XLR or XLS based board.
@@ -799,7 +817,6 @@ config NLM_XLP_BOARD
         select SYS_HAS_CPU_XLP
         select SYS_SUPPORTS_SMP
         select HW_HAS_PCI
-        select SWAP_IO_SPACE
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_64BIT_KERNEL
         select 64BIT_PHYS_ADDR
@@ -836,6 +853,7 @@ source "arch/mips/txx9/Kconfig"
 source "arch/mips/vr41xx/Kconfig"
 source "arch/mips/cavium-octeon/Kconfig"
 source "arch/mips/loongson/Kconfig"
+source "arch/mips/loongson1/Kconfig"
 source "arch/mips/netlogic/Kconfig"
 
 endmenu
@@ -1217,6 +1235,14 @@ config CPU_LOONGSON2F
           have a similar programming interface with FPGA northbridge used in
           Loongson2E.
 
+config CPU_LOONGSON1B
+        bool "Loongson 1B"
+        depends on SYS_HAS_CPU_LOONGSON1B
+        select CPU_LOONGSON1
+        help
+          The Loongson 1B is a 32-bit SoC, which implements the MIPS32
+          release 2 instruction set.
+
 config CPU_MIPS32_R1
         bool "MIPS32 Release 1"
         depends on SYS_HAS_CPU_MIPS32_R1
@@ -1432,6 +1458,8 @@ config CPU_CAVIUM_OCTEON
         select WEAK_ORDERING
         select CPU_SUPPORTS_HIGHMEM
         select CPU_SUPPORTS_HUGEPAGES
+        select LIBFDT
+        select USE_OF
         help
           The Cavium Octeon processor is a highly integrated chip containing
           many ethernet hardware widgets for networking tasks. The processor
@@ -1544,6 +1572,14 @@ config CPU_LOONGSON2
         select CPU_SUPPORTS_64BIT_KERNEL
         select CPU_SUPPORTS_HIGHMEM
 
+config CPU_LOONGSON1
+        bool
+        select CPU_MIPS32
+        select CPU_MIPSR2
+        select CPU_HAS_PREFETCH
+        select CPU_SUPPORTS_32BIT_KERNEL
+        select CPU_SUPPORTS_HIGHMEM
+
 config CPU_BMIPS
         bool
         select CPU_MIPS32
@@ -1562,6 +1598,9 @@ config SYS_HAS_CPU_LOONGSON2F
         select CPU_SUPPORTS_ADDRWINCFG if 64BIT
         select CPU_SUPPORTS_UNCACHED_ACCELERATED
 
+config SYS_HAS_CPU_LOONGSON1B
+        bool
+
 config SYS_HAS_CPU_MIPS32_R1
         bool
 
@@ -2366,6 +2405,8 @@ config PCI_DOMAINS
 
 source "drivers/pci/Kconfig"
 
+source "drivers/pci/pcie/Kconfig"
+
 #
 # ISA support is now enabled via select.  Too many systems still have the one
 # or other ISA chip on the board that users don't know about so don't expect
diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c
index 295f1a95f74..a124c251c0c 100644
--- a/arch/mips/alchemy/board-mtx1.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -81,10 +81,10 @@ static void mtx1_power_off(void)
 
 void __init board_setup(void)
 {
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
         /* Enable USB power switch */
         alchemy_gpio_direction_output(204, 0);
-#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
+#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
 
         /* Initialize sys_pinfunc */
         au_writel(SYS_PF_NI2, SYS_PINFUNC);
@@ -228,6 +228,8 @@ static int mtx1_pci_idsel(unsigned int devsel, int assert)
          * adapter on the mtx-1 "singleboard" variant. It triggers a custom
          * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
          */
+        udelay(1);
+
         if (assert && devsel != 0)
                 /* Suppress signal to Cardbus */
                 alchemy_gpio_set_value(1, 0);   /* set EXT_IO3 OFF */
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 95cb9113b12..c0f3ce6dcb5 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -334,13 +334,12 @@ static void __init alchemy_setup_macs(int ctype)
         if (alchemy_get_macs(ctype) < 1)
                 return;
 
-        macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
+        macres = kmemdup(au1xxx_eth0_resources[ctype],
+                         sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
         if (!macres) {
                 printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
                 return;
         }
-        memcpy(macres, au1xxx_eth0_resources[ctype],
-               sizeof(struct resource) * MAC_RES_COUNT);
         au1xxx_eth0_device.resource = macres;
 
         i = prom_get_ethernet_addr(ethaddr);
@@ -356,13 +355,12 @@ static void __init alchemy_setup_macs(int ctype)
         if (alchemy_get_macs(ctype) < 2)
                 return;
 
-        macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
+        macres = kmemdup(au1xxx_eth1_resources[ctype],
+                         sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
         if (!macres) {
                 printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
                 return;
         }
-        memcpy(macres, au1xxx_eth1_resources[ctype],
-               sizeof(struct resource) * MAC_RES_COUNT);
         au1xxx_eth1_device.resource = macres;
 
         ethaddr[5] += 1;        /* next addr for 2nd MAC */
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 3c37fb30336..c9e747dd9fc 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -2,7 +2,7 @@
 # Alchemy Develboards
 #
 
-obj-y += prom.o bcsr.o platform.o
+obj-y += bcsr.o platform.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_MIPS_PB1100)       += pb1100.o
 obj-$(CONFIG_MIPS_PB1500)       += pb1500.o
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index 1e83ce2e114..f2039ef2c29 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -90,10 +90,7 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
         unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
 
         disable_irq_nosync(irq);
-
-        for ( ; bisr; bisr &= bisr - 1)
-                generic_handle_irq(bcsr_csc_base + __ffs(bisr));
-
+        generic_handle_irq(bcsr_csc_base + __ffs(bisr));
         enable_irq(irq);
 }
 
diff --git a/arch/mips/alchemy/devboards/pb1100.c b/arch/mips/alchemy/devboards/pb1100.c
index cff50d05ddd..78c77a44a31 100644
--- a/arch/mips/alchemy/devboards/pb1100.c
+++ b/arch/mips/alchemy/devboards/pb1100.c
@@ -46,7 +46,7 @@ void __init board_setup(void)
         alchemy_gpio1_input_enable();
         udelay(100);
 
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
         {
                 u32 pin_func, sys_freqctrl, sys_clksrc;
 
@@ -93,7 +93,7 @@ void __init board_setup(void)
                 pin_func |= SYS_PF_USB;
                 au_writel(pin_func, SYS_PINFUNC);
         }
-#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
+#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
 
         /* Enable sys bus clock divider when IDLE state or no bus activity. */
         au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
diff --git a/arch/mips/alchemy/devboards/pb1500.c b/arch/mips/alchemy/devboards/pb1500.c
index e7b807b3ec5..232fee94200 100644
--- a/arch/mips/alchemy/devboards/pb1500.c
+++ b/arch/mips/alchemy/devboards/pb1500.c
@@ -53,7 +53,7 @@ void __init board_setup(void)
         alchemy_gpio_direction_input(201);
         alchemy_gpio_direction_input(203);
 
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#if IS_ENABLED(CONFIG_USB_OHCI_HCD)
 
         /* Zero and disable FREQ2 */
         sys_freqctrl = au_readl(SYS_FREQCTRL0);
@@ -87,7 +87,7 @@ void __init board_setup(void)
         /* 2nd USB port is USB host */
         pin_func |= SYS_PF_USB;
         au_writel(pin_func, SYS_PINFUNC);
-#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
+#endif /* IS_ENABLED(CONFIG_USB_OHCI_HCD) */
 
 #ifdef CONFIG_PCI
         {
diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c
index 621f70afb63..f39042e99d0 100644
--- a/arch/mips/alchemy/devboards/platform.c
+++ b/arch/mips/alchemy/devboards/platform.c
@@ -10,9 +10,39 @@
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 
+#include <asm/bootinfo.h>
 #include <asm/reboot.h>
+#include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-db1x00/bcsr.h>
 
+#include <prom.h>
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = (int)fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str || kstrtoul(memsize_str, 0, &memsize))
+                memsize = 64 << 20; /* all devboards have at least 64MB RAM */
+
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+#ifdef CONFIG_MIPS_DB1300
+        alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
+#else
+        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+#endif
+}
+
 
 static struct platform_device db1x00_rtc_dev = {
         .name   = "rtc-au1xxx",
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
deleted file mode 100644
index 93a22107cc4..00000000000
--- a/arch/mips/alchemy/devboards/prom.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Common code used by all Alchemy develboards.
- *
- * Extracted from files which had this to say:
- *
- * Copyright 2000, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <asm/bootinfo.h>
-#include <asm/mach-au1x00/au1000.h>
-#include <prom.h>
-
-#if defined(CONFIG_MIPS_DB1000) || \
-    defined(CONFIG_MIPS_PB1100) || \
-    defined(CONFIG_MIPS_PB1500)
-#define ALCHEMY_BOARD_DEFAULT_MEMSIZE   0x04000000
-
-#else   /* Au1550/Au1200-based develboards */
-#define ALCHEMY_BOARD_DEFAULT_MEMSIZE   0x08000000
-#endif
-
-void __init prom_init(void)
-{
-        unsigned char *memsize_str;
-        unsigned long memsize;
-
-        prom_argc = (int)fw_arg0;
-        prom_argv = (char **)fw_arg1;
-        prom_envp = (char **)fw_arg2;
-
-        prom_init_cmdline();
-        memsize_str = prom_getenv("memsize");
-        if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
-                memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE;
-
-        add_memory_region(0, memsize, BOOT_MEM_RAM);
-}
-
-void prom_putchar(unsigned char c)
-{
-#ifdef CONFIG_MIPS_DB1300
-        alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c);
-#else
-        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
-#endif
-}
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 1a24d317e7a..1bbc24b0868 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -310,10 +310,10 @@ static void __init cpmac_get_mac(int instance, unsigned char *dev_addr)
                                         &dev_addr[4], &dev_addr[5]) != 6) {
                         pr_warning("cannot parse mac address, "
                                         "using random address\n");
-                        random_ether_addr(dev_addr);
+                        eth_random_addr(dev_addr);
                 }
         } else
-                random_ether_addr(dev_addr);
+                eth_random_addr(dev_addr);
 }
 
 /*****************************************************************************
diff --git a/arch/mips/ath79/dev-usb.c b/arch/mips/ath79/dev-usb.c
index 36e9570e7bc..b2a2311ec85 100644
--- a/arch/mips/ath79/dev-usb.c
+++ b/arch/mips/ath79/dev-usb.c
@@ -145,6 +145,8 @@ static void __init ar7240_usb_setup(void)
 
         ath79_ohci_resources[0].start = AR7240_OHCI_BASE;
         ath79_ohci_resources[0].end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1;
+        ath79_ohci_resources[1].start = ATH79_CPU_IRQ_USB;
+        ath79_ohci_resources[1].end = ATH79_CPU_IRQ_USB;
         platform_device_register(&ath79_ohci_device);
 }
 
diff --git a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c
index 29054f21183..48fe762d252 100644
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -188,8 +188,10 @@ void __init ath79_gpio_init(void)
 
         if (soc_is_ar71xx())
                 ath79_gpio_count = AR71XX_GPIO_COUNT;
-        else if (soc_is_ar724x())
-                ath79_gpio_count = AR724X_GPIO_COUNT;
+        else if (soc_is_ar7240())
+                ath79_gpio_count = AR7240_GPIO_COUNT;
+        else if (soc_is_ar7241() || soc_is_ar7242())
+                ath79_gpio_count = AR7241_GPIO_COUNT;
         else if (soc_is_ar913x())
                 ath79_gpio_count = AR913X_GPIO_COUNT;
         else if (soc_is_ar933x())
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index 6b1b9ad8d85..d03e8799d1c 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -1,6 +1,10 @@
 menu "CPU support"
         depends on BCM63XX
 
+config BCM63XX_CPU_6328
+        bool "support 6328 CPU"
+        select HW_HAS_PCI
+
 config BCM63XX_CPU_6338
         bool "support 6338 CPU"
         select HW_HAS_PCI
diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile
index 6dfdc69928a..833af72c852 100644
--- a/arch/mips/bcm63xx/Makefile
+++ b/arch/mips/bcm63xx/Makefile
@@ -1,5 +1,6 @@
 obj-y           += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \
-                   dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o
+                   dev-dsp.o dev-enet.o dev-flash.o dev-pcmcia.o dev-rng.o \
+                   dev-spi.o dev-uart.o dev-wdt.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 
 obj-y           += boards/
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 2f1773f3fb7..feb05258a4d 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -11,9 +11,6 @@
 #include <linux/kernel.h>
 #include <linux/string.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/physmap.h>
 #include <linux/ssb/ssb.h>
 #include <asm/addrspace.h>
 #include <bcm63xx_board.h>
@@ -24,7 +21,9 @@
 #include <bcm63xx_dev_pci.h>
 #include <bcm63xx_dev_enet.h>
 #include <bcm63xx_dev_dsp.h>
+#include <bcm63xx_dev_flash.h>
 #include <bcm63xx_dev_pcmcia.h>
+#include <bcm63xx_dev_spi.h>
 #include <board_bcm963xx.h>
 
 #define PFX     "board_bcm963xx: "
@@ -34,6 +33,48 @@ static unsigned int mac_addr_used;
 static struct board_info board;
 
 /*
+ * known 6328 boards
+ */
+#ifdef CONFIG_BCM63XX_CPU_6328
+static struct board_info __initdata board_96328avng = {
+        .name                           = "96328avng",
+        .expected_cpu_id                = 0x6328,
+
+        .has_uart0                      = 1,
+        .has_pci                        = 1,
+
+        .leds = {
+                {
+                        .name           = "96328avng::ppp-fail",
+                        .gpio           = 2,
+                        .active_low     = 1,
+                },
+                {
+                        .name           = "96328avng::power",
+                        .gpio           = 4,
+                        .active_low     = 1,
+                        .default_trigger = "default-on",
+                },
+                {
+                        .name           = "96328avng::power-fail",
+                        .gpio           = 8,
+                        .active_low     = 1,
+                },
+                {
+                        .name           = "96328avng::wps",
+                        .gpio           = 9,
+                        .active_low     = 1,
+                },
+                {
+                        .name           = "96328avng::ppp",
+                        .gpio           = 11,
+                        .active_low     = 1,
+                },
+        },
+};
+#endif
+
+/*
  * known 6338 boards
  */
 #ifdef CONFIG_BCM63XX_CPU_6338
@@ -592,6 +633,9 @@ static struct board_info __initdata board_DWVS0 = {
  * all boards
  */
 static const struct board_info __initdata *bcm963xx_boards[] = {
+#ifdef CONFIG_BCM63XX_CPU_6328
+        &board_96328avng,
+#endif
 #ifdef CONFIG_BCM63XX_CPU_6338
         &board_96338gw,
         &board_96338w,
@@ -709,9 +753,15 @@ void __init board_prom_init(void)
         char cfe_version[32];
         u32 val;
 
-        /* read base address of boot chip select (0) */
-        val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-        val &= MPI_CSBASE_BASE_MASK;
+        /* read base address of boot chip select (0)
+         * 6328 does not have MPI but boots from a fixed address
+         */
+        if (BCMCPU_IS_6328())
+                val = 0x18000000;
+        else {
+                val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+                val &= MPI_CSBASE_BASE_MASK;
+        }
         boot_addr = (u8 *)KSEG1ADDR(val);
 
         /* dump cfe version */
@@ -808,40 +858,6 @@ void __init board_setup(void)
                 panic("unexpected CPU for bcm963xx board");
 }
 
-static struct mtd_partition mtd_partitions[] = {
-        {
-                .name           = "cfe",
-                .offset         = 0x0,
-                .size           = 0x40000,
-        }
-};
-
-static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL };
-
-static struct physmap_flash_data flash_data = {
-        .width                  = 2,
-        .nr_parts               = ARRAY_SIZE(mtd_partitions),
-        .parts                  = mtd_partitions,
-        .part_probe_types       = bcm63xx_part_types,
-};
-
-static struct resource mtd_resources[] = {
-        {
-                .start          = 0,    /* filled at runtime */
-                .end            = 0,    /* filled at runtime */
-                .flags          = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device mtd_dev = {
-        .name                   = "physmap-flash",
-        .resource               = mtd_resources,
-        .num_resources          = ARRAY_SIZE(mtd_resources),
-        .dev                    = {
-                .platform_data  = &flash_data,
-        },
-};
-
 static struct gpio_led_platform_data bcm63xx_led_data;
 
 static struct platform_device bcm63xx_gpio_leds = {
@@ -855,8 +871,6 @@ static struct platform_device bcm63xx_gpio_leds = {
  */
 int __init board_register_devices(void)
 {
-        u32 val;
-
         if (board.has_uart0)
                 bcm63xx_uart_register(0);
 
@@ -890,14 +904,9 @@ int __init board_register_devices(void)
         }
 #endif
 
-        /* read base address of boot chip select (0) */
-        val = bcm_mpi_readl(MPI_CSBASE_REG(0));
-        val &= MPI_CSBASE_BASE_MASK;
-
-        mtd_resources[0].start = val;
-        mtd_resources[0].end = 0x1FFFFFFF;
+        bcm63xx_spi_register();
 
-        platform_device_register(&mtd_dev);
+        bcm63xx_flash_register();
 
         bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds);
         bcm63xx_led_data.leds = board.leds;
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 9d57c71b7b5..1db48adb543 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -120,7 +120,7 @@ static void enetsw_set(struct clk *clk, int enable)
 {
         if (!BCMCPU_IS_6368())
                 return;
-        bcm_hwclock_set(CKCTL_6368_ROBOSW_CLK_EN |
+        bcm_hwclock_set(CKCTL_6368_ROBOSW_EN |
                         CKCTL_6368_SWPKT_USB_EN |
                         CKCTL_6368_SWPKT_SAR_EN, enable);
         if (enable) {
@@ -163,7 +163,7 @@ static void usbh_set(struct clk *clk, int enable)
         if (BCMCPU_IS_6348())
                 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
         else if (BCMCPU_IS_6368())
-                bcm_hwclock_set(CKCTL_6368_USBH_CLK_EN, enable);
+                bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
 }
 
 static struct clk clk_usbh = {
@@ -181,9 +181,11 @@ static void spi_set(struct clk *clk, int enable)
                 mask = CKCTL_6338_SPI_EN;
         else if (BCMCPU_IS_6348())
                 mask = CKCTL_6348_SPI_EN;
-        else
-                /* BCMCPU_IS_6358 */
+        else if (BCMCPU_IS_6358())
                 mask = CKCTL_6358_SPI_EN;
+        else
+                /* BCMCPU_IS_6368 */
+                mask = CKCTL_6368_SPI_EN;
         bcm_hwclock_set(mask, enable);
 }
 
@@ -199,7 +201,7 @@ static void xtm_set(struct clk *clk, int enable)
         if (!BCMCPU_IS_6368())
                 return;
 
-        bcm_hwclock_set(CKCTL_6368_SAR_CLK_EN |
+        bcm_hwclock_set(CKCTL_6368_SAR_EN |
                         CKCTL_6368_SWPKT_SAR_EN, enable);
 
         if (enable) {
@@ -222,6 +224,18 @@ static struct clk clk_xtm = {
 };
 
 /*
+ * IPsec clock
+ */
+static void ipsec_set(struct clk *clk, int enable)
+{
+        bcm_hwclock_set(CKCTL_6368_IPSEC_EN, enable);
+}
+
+static struct clk clk_ipsec = {
+        .set    = ipsec_set,
+};
+
+/*
  * Internal peripheral clock
  */
 static struct clk clk_periph = {
@@ -278,6 +292,8 @@ struct clk *clk_get(struct device *dev, const char *id)
                 return &clk_periph;
         if (BCMCPU_IS_6358() && !strcmp(id, "pcm"))
                 return &clk_pcm;
+        if (BCMCPU_IS_6368() && !strcmp(id, "ipsec"))
+                return &clk_ipsec;
         return ERR_PTR(-ENOENT);
 }
 
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 8f0d6c7725e..a7afb289b15 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev;
 static unsigned int bcm63xx_cpu_freq;
 static unsigned int bcm63xx_memory_size;
 
+static const unsigned long bcm6328_regs_base[] = {
+        __GEN_CPU_REGS_TABLE(6328)
+};
+
+static const int bcm6328_irqs[] = {
+        __GEN_CPU_IRQ_TABLE(6328)
+};
+
 static const unsigned long bcm6338_regs_base[] = {
         __GEN_CPU_REGS_TABLE(6338)
 };
@@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(void)
 static unsigned int detect_cpu_clock(void)
 {
         switch (bcm63xx_get_cpu_id()) {
+        case BCM6328_CPU_ID:
+        {
+                unsigned int tmp, mips_pll_fcvo;
+
+                tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
+                mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
+                                >> STRAPBUS_6328_FCVO_SHIFT;
+
+                switch (mips_pll_fcvo) {
+                case 0x12:
+                case 0x14:
+                case 0x19:
+                        return 160000000;
+                case 0x1c:
+                        return 192000000;
+                case 0x13:
+                case 0x15:
+                        return 200000000;
+                case 0x1a:
+                        return 384000000;
+                case 0x16:
+                        return 400000000;
+                default:
+                        return 320000000;
+                }
+
+        }
         case BCM6338_CPU_ID:
                 /* BCM6338 has a fixed 240 Mhz frequency */
                 return 240000000;
@@ -170,6 +205,9 @@ static unsigned int detect_memory_size(void)
         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
         u32 val;
 
+        if (BCMCPU_IS_6328())
+                return bcm_ddr_readl(DDR_CSEND_REG) << 24;
+
         if (BCMCPU_IS_6345()) {
                 val = bcm_sdram_readl(SDRAM_MBASE_REG);
                 return (val * 8 * 1024 * 1024);
@@ -228,17 +266,26 @@ void __init bcm63xx_cpu_init(void)
                 bcm63xx_irqs = bcm6345_irqs;
                 break;
         case CPU_BMIPS4350:
-                switch (read_c0_prid() & 0xf0) {
-                case 0x10:
+                if ((read_c0_prid() & 0xf0) == 0x10) {
                         expected_cpu_id = BCM6358_CPU_ID;
                         bcm63xx_regs_base = bcm6358_regs_base;
                         bcm63xx_irqs = bcm6358_irqs;
-                        break;
-                case 0x30:
-                        expected_cpu_id = BCM6368_CPU_ID;
-                        bcm63xx_regs_base = bcm6368_regs_base;
-                        bcm63xx_irqs = bcm6368_irqs;
-                        break;
+                } else {
+                        /* all newer chips have the same chip id location */
+                        u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
+
+                        switch (chip_id) {
+                        case BCM6328_CPU_ID:
+                                expected_cpu_id = BCM6328_CPU_ID;
+                                bcm63xx_regs_base = bcm6328_regs_base;
+                                bcm63xx_irqs = bcm6328_irqs;
+                                break;
+                        case BCM6368_CPU_ID:
+                                expected_cpu_id = BCM6368_CPU_ID;
+                                bcm63xx_regs_base = bcm6368_regs_base;
+                                bcm63xx_irqs = bcm6368_irqs;
+                                break;
+                        }
                 }
                 break;
         }
diff --git a/arch/mips/bcm63xx/dev-dsp.c b/arch/mips/bcm63xx/dev-dsp.c
index da46d1d3c77..5bb5b154c9b 100644
--- a/arch/mips/bcm63xx/dev-dsp.c
+++ b/arch/mips/bcm63xx/dev-dsp.c
@@ -31,7 +31,7 @@ static struct resource voip_dsp_resources[] = {
 
 static struct platform_device bcm63xx_voip_dsp_device = {
         .name           = "bcm63xx-voip-dsp",
-        .id             = 0,
+        .id             = -1,
         .num_resources  = ARRAY_SIZE(voip_dsp_resources),
         .resource       = voip_dsp_resources,
 };
diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c
new file mode 100644
index 00000000000..58371c7deac
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-flash.c
@@ -0,0 +1,123 @@
+/*
+ * Broadcom BCM63xx flash registration
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
+ * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+
+#include <bcm63xx_cpu.h>
+#include <bcm63xx_dev_flash.h>
+#include <bcm63xx_regs.h>
+#include <bcm63xx_io.h>
+
+static struct mtd_partition mtd_partitions[] = {
+        {
+                .name           = "cfe",
+                .offset         = 0x0,
+                .size           = 0x40000,
+        }
+};
+
+static const char *bcm63xx_part_types[] = { "bcm63xxpart", NULL };
+
+static struct physmap_flash_data flash_data = {
+        .width                  = 2,
+        .parts                  = mtd_partitions,
+        .part_probe_types       = bcm63xx_part_types,
+};
+
+static struct resource mtd_resources[] = {
+        {
+                .start          = 0,    /* filled at runtime */
+                .end            = 0,    /* filled at runtime */
+                .flags          = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device mtd_dev = {
+        .name                   = "physmap-flash",
+        .resource               = mtd_resources,
+        .num_resources          = ARRAY_SIZE(mtd_resources),
+        .dev                    = {
+                .platform_data  = &flash_data,
+        },
+};
+
+static int __init bcm63xx_detect_flash_type(void)
+{
+        u32 val;
+
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6328_CPU_ID:
+                val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
+                if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
+                        return BCM63XX_FLASH_TYPE_SERIAL;
+                else
+                        return BCM63XX_FLASH_TYPE_NAND;
+        case BCM6338_CPU_ID:
+        case BCM6345_CPU_ID:
+        case BCM6348_CPU_ID:
+                /* no way to auto detect so assume parallel */
+                return BCM63XX_FLASH_TYPE_PARALLEL;
+        case BCM6358_CPU_ID:
+                val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
+                if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
+                        return BCM63XX_FLASH_TYPE_PARALLEL;
+                else
+                        return BCM63XX_FLASH_TYPE_SERIAL;
+        case BCM6368_CPU_ID:
+                val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
+                switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
+                case STRAPBUS_6368_BOOT_SEL_NAND:
+                        return BCM63XX_FLASH_TYPE_NAND;
+                case STRAPBUS_6368_BOOT_SEL_SERIAL:
+                        return BCM63XX_FLASH_TYPE_SERIAL;
+                case STRAPBUS_6368_BOOT_SEL_PARALLEL:
+                        return BCM63XX_FLASH_TYPE_PARALLEL;
+                }
+        default:
+                return -EINVAL;
+        }
+}
+
+int __init bcm63xx_flash_register(void)
+{
+        int flash_type;
+        u32 val;
+
+        flash_type = bcm63xx_detect_flash_type();
+
+        switch (flash_type) {
+        case BCM63XX_FLASH_TYPE_PARALLEL:
+                /* read base address of boot chip select (0) */
+                val = bcm_mpi_readl(MPI_CSBASE_REG(0));
+                val &= MPI_CSBASE_BASE_MASK;
+
+                mtd_resources[0].start = val;
+                mtd_resources[0].end = 0x1FFFFFFF;
+
+                return platform_device_register(&mtd_dev);
+        case BCM63XX_FLASH_TYPE_SERIAL:
+                pr_warn("unsupported serial flash detected\n");
+                return -ENODEV;
+        case BCM63XX_FLASH_TYPE_NAND:
+                pr_warn("unsupported NAND flash detected\n");
+                return -ENODEV;
+        default:
+                pr_err("flash detection failed for BCM%x: %d\n",
+                       bcm63xx_get_cpu_id(), flash_type);
+                return -ENODEV;
+        }
+}
diff --git a/arch/mips/bcm63xx/dev-rng.c b/arch/mips/bcm63xx/dev-rng.c
new file mode 100644
index 00000000000..d277b4dc6c6
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-rng.c
@@ -0,0 +1,40 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011 Florian Fainelli <florian@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <bcm63xx_cpu.h>
+
+static struct resource rng_resources[] = {
+        {
+                .start          = -1, /* filled at runtime */
+                .end            = -1, /* filled at runtime */
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device bcm63xx_rng_device = {
+        .name           = "bcm63xx-rng",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rng_resources),
+        .resource       = rng_resources,
+};
+
+int __init bcm63xx_rng_register(void)
+{
+        if (!BCMCPU_IS_6368())
+                return -ENODEV;
+
+        rng_resources[0].start = bcm63xx_regset_address(RSET_RNG);
+        rng_resources[0].end = rng_resources[0].start;
+        rng_resources[0].end += RSET_RNG_SIZE - 1;
+
+        return platform_device_register(&bcm63xx_rng_device);
+}
+arch_initcall(bcm63xx_rng_register);
diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c
new file mode 100644
index 00000000000..f1c9c3e2f67
--- /dev/null
+++ b/arch/mips/bcm63xx/dev-spi.c
@@ -0,0 +1,123 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009-2011 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2010 Tanguy Bouzeloc <tanguy.bouzeloc@efixo.com>
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/export.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+
+#include <bcm63xx_cpu.h>
+#include <bcm63xx_dev_spi.h>
+#include <bcm63xx_regs.h>
+
+#ifdef BCMCPU_RUNTIME_DETECT
+/*
+ * register offsets
+ */
+static const unsigned long bcm6338_regs_spi[] = {
+        __GEN_SPI_REGS_TABLE(6338)
+};
+
+static const unsigned long bcm6348_regs_spi[] = {
+        __GEN_SPI_REGS_TABLE(6348)
+};
+
+static const unsigned long bcm6358_regs_spi[] = {
+        __GEN_SPI_REGS_TABLE(6358)
+};
+
+static const unsigned long bcm6368_regs_spi[] = {
+        __GEN_SPI_REGS_TABLE(6368)
+};
+
+const unsigned long *bcm63xx_regs_spi;
+EXPORT_SYMBOL(bcm63xx_regs_spi);
+
+static __init void bcm63xx_spi_regs_init(void)
+{
+        if (BCMCPU_IS_6338())
+                bcm63xx_regs_spi = bcm6338_regs_spi;
+        if (BCMCPU_IS_6348())
+                bcm63xx_regs_spi = bcm6348_regs_spi;
+        if (BCMCPU_IS_6358())
+                bcm63xx_regs_spi = bcm6358_regs_spi;
+        if (BCMCPU_IS_6368())
+                bcm63xx_regs_spi = bcm6368_regs_spi;
+}
+#else
+static __init void bcm63xx_spi_regs_init(void) { }
+#endif
+
+static struct resource spi_resources[] = {
+        {
+                .start          = -1, /* filled at runtime */
+                .end            = -1, /* filled at runtime */
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                .start          = -1, /* filled at runtime */
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct bcm63xx_spi_pdata spi_pdata = {
+        .bus_num                = 0,
+        .num_chipselect         = 8,
+};
+
+static struct platform_device bcm63xx_spi_device = {
+        .name           = "bcm63xx-spi",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(spi_resources),
+        .resource       = spi_resources,
+        .dev            = {
+                .platform_data = &spi_pdata,
+        },
+};
+
+int __init bcm63xx_spi_register(void)
+{
+        struct clk *periph_clk;
+
+        if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
+                return -ENODEV;
+
+        periph_clk = clk_get(NULL, "periph");
+        if (IS_ERR(periph_clk)) {
+                pr_err("unable to get periph clock\n");
+                return -ENODEV;
+        }
+
+        /* Set bus frequency */
+        spi_pdata.speed_hz = clk_get_rate(periph_clk);
+
+        spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
+        spi_resources[0].end = spi_resources[0].start;
+        spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
+
+        if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
+                spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;
+                spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;
+                spi_pdata.msg_type_shift = SPI_6338_MSG_TYPE_SHIFT;
+                spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;
+        }
+
+        if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
+                spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
+                spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
+                spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
+                spi_pdata.msg_ctl_width = SPI_6358_MSG_CTL_WIDTH;
+        }
+
+        bcm63xx_spi_regs_init();
+
+        return platform_device_register(&bcm63xx_spi_device);
+}
diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c
index 3e6c716a4c1..2a2346a99bc 100644
--- a/arch/mips/bcm63xx/dev-wdt.c
+++ b/arch/mips/bcm63xx/dev-wdt.c
@@ -21,7 +21,7 @@ static struct resource wdt_resources[] = {
 
 static struct platform_device bcm63xx_wdt_device = {
         .name           = "bcm63xx-wdt",
-        .id             = 0,
+        .id             = -1,
         .num_resources  = ARRAY_SIZE(wdt_resources),
         .resource       = wdt_resources,
 };
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 9a216a451d9..18e051ad18a 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
 static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
 
 #ifndef BCMCPU_RUNTIME_DETECT
+#ifdef CONFIG_BCM63XX_CPU_6328
+#define irq_stat_reg            PERF_IRQSTAT_6328_REG
+#define irq_mask_reg            PERF_IRQMASK_6328_REG
+#define irq_bits                64
+#define is_ext_irq_cascaded     1
+#define ext_irq_start           (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
+#define ext_irq_end             (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
+#define ext_irq_count           4
+#define ext_irq_cfg_reg1        PERF_EXTIRQ_CFG_REG_6328
+#define ext_irq_cfg_reg2        0
+#endif
 #ifdef CONFIG_BCM63XX_CPU_6338
 #define irq_stat_reg            PERF_IRQSTAT_6338_REG
 #define irq_mask_reg            PERF_IRQMASK_6338_REG
@@ -118,6 +129,16 @@ static void bcm63xx_init_irq(void)
         irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
 
         switch (bcm63xx_get_cpu_id()) {
+        case BCM6328_CPU_ID:
+                irq_stat_addr += PERF_IRQSTAT_6328_REG;
+                irq_mask_addr += PERF_IRQMASK_6328_REG;
+                irq_bits = 64;
+                ext_irq_count = 4;
+                is_ext_irq_cascaded = 1;
+                ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
+                ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
+                ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
+                break;
         case BCM6338_CPU_ID:
                 irq_stat_addr += PERF_IRQSTAT_6338_REG;
                 irq_mask_addr += PERF_IRQMASK_6338_REG;
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index 99d7f405cbe..10eaff45807 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -26,7 +26,9 @@ void __init prom_init(void)
         bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
 
         /* disable all hardware blocks clock for now */
-        if (BCMCPU_IS_6338())
+        if (BCMCPU_IS_6328())
+                mask = CKCTL_6328_ALL_SAFE_EN;
+        else if (BCMCPU_IS_6338())
                 mask = CKCTL_6338_ALL_SAFE_EN;
         else if (BCMCPU_IS_6345())
                 mask = CKCTL_6345_ALL_SAFE_EN;
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 356b05583e1..0e74a13639c 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
 
         /* mask and clear all external irq */
         switch (bcm63xx_get_cpu_id()) {
+        case BCM6328_CPU_ID:
+                perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
+                break;
         case BCM6338_CPU_ID:
                 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
                 break;
@@ -95,9 +98,13 @@ void bcm63xx_machine_reboot(void)
                 bcm6348_a1_reboot();
 
         printk(KERN_INFO "triggering watchdog soft-reset...\n");
-        reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
-        reg |= SYS_PLL_SOFT_RESET;
-        bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
+        if (BCMCPU_IS_6328()) {
+                bcm_wdt_writel(1, WDT_SOFTRESET_REG);
+        } else {
+                reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
+                reg |= SYS_PLL_SOFT_RESET;
+                bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
+        }
         while (1)
                 ;
 }
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index 5042d51b051..c2a3fb0ffc8 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -58,8 +58,12 @@ $(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
 # Calculate the load address of the compressed kernel image
 hostprogs-y := calc_vmlinuz_load_addr
 
+ifeq ($(CONFIG_MACH_JZ4740),y)
+VMLINUZ_LOAD_ADDRESS := 0x80600000
+else
 VMLINUZ_LOAD_ADDRESS = $(shell $(obj)/calc_vmlinuz_load_addr \
                 $(obj)/vmlinux.bin $(VMLINUX_LOAD_ADDRESS))
+endif
 
 vmlinuzobjs-y += $(obj)/piggy.o
 
diff --git a/arch/mips/boot/compressed/uart-16550.c b/arch/mips/boot/compressed/uart-16550.c
index c9caaf4fbf6..1c7b739b6a1 100644
--- a/arch/mips/boot/compressed/uart-16550.c
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -18,6 +18,11 @@
 #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset))
 #endif
 
+#ifdef CONFIG_MACH_JZ4740
+#define UART0_BASE  0xB0030000
+#define PORT(offset) (UART0_BASE + (4 * offset))
+#endif
+
 #ifndef PORT
 #error please define the serial port address for your own machine
 #endif
diff --git a/arch/mips/cavium-octeon/.gitignore b/arch/mips/cavium-octeon/.gitignore
new file mode 100644
index 00000000000..39c968605ff
--- /dev/null
+++ b/arch/mips/cavium-octeon/.gitignore
@@ -0,0 +1,2 @@
+*.dtb.S
+*.dtb
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 19eb0434269..bc96e2908f1 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -9,9 +9,25 @@
 # Copyright (C) 2005-2009 Cavium Networks
 #
 
+CFLAGS_octeon-platform.o = -I$(src)/../../../scripts/dtc/libfdt
+CFLAGS_setup.o = -I$(src)/../../../scripts/dtc/libfdt
+
 obj-y := cpu.o setup.o serial.o octeon-platform.o octeon-irq.o csrc-octeon.o
 obj-y += dma-octeon.o flash_setup.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
 
 obj-$(CONFIG_SMP)                     += smp.o
+
+DTS_FILES = octeon_3xxx.dts octeon_68xx.dts
+DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES))
+
+obj-y += $(patsubst %.dts, %.dtb.o, $(DTS_FILES))
+
+$(obj)/%.dtb: $(src)/%.dts FORCE
+        $(call if_changed_dep,dtc)
+
+# Let's keep the .dtb files around in case we want to look at them.
+.SECONDARY:  $(addprefix $(obj)/, $(DTB_FILES))
+
+clean-files += $(DTB_FILES) $(patsubst %.dtb, %.dtb.S, $(DTB_FILES))
diff --git a/arch/mips/cavium-octeon/executive/cvmx-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-fpa.c
deleted file mode 100644
index ad44b8bd805..00000000000
--- a/arch/mips/cavium-octeon/executive/cvmx-fpa.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Support library for the hardware Free Pool Allocator.
- *
- *
- */
-
-#include "cvmx-config.h"
-#include "cvmx.h"
-#include "cvmx-fpa.h"
-#include "cvmx-ipd.h"
-
-/**
- * Current state of all the pools. Use access functions
- * instead of using it directly.
- */
-CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS];
-
-/**
- * Setup a FPA pool to control a new block of memory. The
- * buffer pointer must be a physical address.
- *
- * @pool:       Pool to initialize
- *                   0 <= pool < 8
- * @name:       Constant character string to name this pool.
- *                   String is not copied.
- * @buffer:     Pointer to the block of memory to use. This must be
- *                   accessible by all processors and external hardware.
- * @block_size: Size for each block controlled by the FPA
- * @num_blocks: Number of blocks
- *
- * Returns 0 on Success,
- *         -1 on failure
- */
-int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
-                        uint64_t block_size, uint64_t num_blocks)
-{
-        char *ptr;
-        if (!buffer) {
-                cvmx_dprintf
-                    ("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n");
-                return -1;
-        }
-        if (pool >= CVMX_FPA_NUM_POOLS) {
-                cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n");
-                return -1;
-        }
-
-        if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) {
-                cvmx_dprintf
-                    ("ERROR: cvmx_fpa_setup_pool: Block size too small.\n");
-                return -1;
-        }
-
-        if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) {
-                cvmx_dprintf
-                    ("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n");
-                return -1;
-        }
-
-        cvmx_fpa_pool_info[pool].name = name;
-        cvmx_fpa_pool_info[pool].size = block_size;
-        cvmx_fpa_pool_info[pool].starting_element_count = num_blocks;
-        cvmx_fpa_pool_info[pool].base = buffer;
-
-        ptr = (char *)buffer;
-        while (num_blocks--) {
-                cvmx_fpa_free(ptr, pool, 0);
-                ptr += block_size;
-        }
-        return 0;
-}
-
-/**
- * Shutdown a Memory pool and validate that it had all of
- * the buffers originally placed in it.
- *
- * @pool:   Pool to shutdown
- * Returns Zero on success
- *         - Positive is count of missing buffers
- *         - Negative is too many buffers or corrupted pointers
- */
-uint64_t cvmx_fpa_shutdown_pool(uint64_t pool)
-{
-        uint64_t errors = 0;
-        uint64_t count = 0;
-        uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base);
-        uint64_t finish =
-            base +
-            cvmx_fpa_pool_info[pool].size *
-            cvmx_fpa_pool_info[pool].starting_element_count;
-        void *ptr;
-        uint64_t address;
-
-        count = 0;
-        do {
-                ptr = cvmx_fpa_alloc(pool);
-                if (ptr)
-                        address = cvmx_ptr_to_phys(ptr);
-                else
-                        address = 0;
-                if (address) {
-                        if ((address >= base) && (address < finish) &&
-                            (((address -
-                               base) % cvmx_fpa_pool_info[pool].size) == 0)) {
-                                count++;
-                        } else {
-                                cvmx_dprintf
-                                    ("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n",
-                                     (unsigned long long)address,
-                                     cvmx_fpa_pool_info[pool].name, (int)pool);
-                                errors++;
-                        }
-                }
-        } while (address);
-
-#ifdef CVMX_ENABLE_PKO_FUNCTIONS
-        if (pool == 0)
-                cvmx_ipd_free_ptr();
-#endif
-
-        if (errors) {
-                cvmx_dprintf
-                    ("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n",
-                     cvmx_fpa_pool_info[pool].name, (int)pool,
-                     (unsigned long long)base, (unsigned long long)finish,
-                     (unsigned long long)cvmx_fpa_pool_info[pool].size);
-                return -errors;
-        } else
-                return 0;
-}
-
-uint64_t cvmx_fpa_get_block_size(uint64_t pool)
-{
-        switch (pool) {
-        case 0:
-                return CVMX_FPA_POOL_0_SIZE;
-        case 1:
-                return CVMX_FPA_POOL_1_SIZE;
-        case 2:
-                return CVMX_FPA_POOL_2_SIZE;
-        case 3:
-                return CVMX_FPA_POOL_3_SIZE;
-        case 4:
-                return CVMX_FPA_POOL_4_SIZE;
-        case 5:
-                return CVMX_FPA_POOL_5_SIZE;
-        case 6:
-                return CVMX_FPA_POOL_6_SIZE;
-        case 7:
-                return CVMX_FPA_POOL_7_SIZE;
-        default:
-                return 0;
-        }
-}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c b/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
deleted file mode 100644
index c239e5f4ab9..00000000000
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-fpa.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Helper functions for FPA setup.
- *
- */
-#include "executive-config.h"
-#include "cvmx-config.h"
-#include "cvmx.h"
-#include "cvmx-bootmem.h"
-#include "cvmx-fpa.h"
-#include "cvmx-helper-fpa.h"
-
-/**
- * Allocate memory for and initialize a single FPA pool.
- *
- * @pool:    Pool to initialize
- * @buffer_size:  Size of buffers to allocate in bytes
- * @buffers: Number of buffers to put in the pool. Zero is allowed
- * @name:    String name of the pool for debugging purposes
- * Returns Zero on success, non-zero on failure
- */
-static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size,
-                                             uint64_t buffers, const char *name)
-{
-        uint64_t current_num;
-        void *memory;
-        uint64_t align = CVMX_CACHE_LINE_SIZE;
-
-        /*
-         * Align the allocation so that power of 2 size buffers are
-         * naturally aligned.
-         */
-        while (align < buffer_size)
-                align = align << 1;
-
-        if (buffers == 0)
-                return 0;
-
-        current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool));
-        if (current_num) {
-                cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. "
-                             "Skipping setup.\n",
-                     pool, name, (unsigned long long)current_num);
-                return 0;
-        }
-
-        memory = cvmx_bootmem_alloc(buffer_size * buffers, align);
-        if (memory == NULL) {
-                cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n",
-                             pool, name);
-                return -1;
-        }
-        cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers);
-        return 0;
-}
-
-/**
- * Allocate memory and initialize the FPA pools using memory
- * from cvmx-bootmem. Specifying zero for the number of
- * buffers will cause that FPA pool to not be setup. This is
- * useful if you aren't using some of the hardware and want
- * to save memory. Use cvmx_helper_initialize_fpa instead of
- * this function directly.
- *
- * @pip_pool: Should always be CVMX_FPA_PACKET_POOL
- * @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE
- * @pip_buffers:
- *                 Number of packet buffers.
- * @wqe_pool: Should always be CVMX_FPA_WQE_POOL
- * @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE
- * @wqe_entries:
- *                 Number of work queue entries
- * @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL
- * @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE
- * @pko_buffers:
- *                 PKO Command buffers. You should at minimum have two per
- *                 each PKO queue.
- * @tim_pool: Should always be CVMX_FPA_TIMER_POOL
- * @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE
- * @tim_buffers:
- *                 TIM ring buffer command queues. At least two per timer bucket
- *                 is recommened.
- * @dfa_pool: Should always be CVMX_FPA_DFA_POOL
- * @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE
- * @dfa_buffers:
- *                 DFA command buffer. A relatively small (32 for example)
- *                 number should work.
- * Returns Zero on success, non-zero if out of memory
- */
-static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size,
-                                        int pip_buffers, int wqe_pool,
-                                        int wqe_size, int wqe_entries,
-                                        int pko_pool, int pko_size,
-                                        int pko_buffers, int tim_pool,
-                                        int tim_size, int tim_buffers,
-                                        int dfa_pool, int dfa_size,
-                                        int dfa_buffers)
-{
-        int status;
-
-        cvmx_fpa_enable();
-
-        if ((pip_buffers > 0) && (pip_buffers <= 64))
-                cvmx_dprintf
-                    ("Warning: %d packet buffers may not be enough for hardware"
-                     " prefetch. 65 or more is recommended.\n", pip_buffers);
-
-        if (pip_pool >= 0) {
-                status =
-                    __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size,
-                                                      pip_buffers,
-                                                      "Packet Buffers");
-                if (status)
-                        return status;
-        }
-
-        if (wqe_pool >= 0) {
-                status =
-                    __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size,
-                                                      wqe_entries,
-                                                      "Work Queue Entries");
-                if (status)
-                        return status;
-        }
-
-        if (pko_pool >= 0) {
-                status =
-                    __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size,
-                                                      pko_buffers,
-                                                      "PKO Command Buffers");
-                if (status)
-                        return status;
-        }
-
-        if (tim_pool >= 0) {
-                status =
-                    __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size,
-                                                      tim_buffers,
-                                                      "TIM Command Buffers");
-                if (status)
-                        return status;
-        }
-
-        if (dfa_pool >= 0) {
-                status =
-                    __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size,
-                                                      dfa_buffers,
-                                                      "DFA Command Buffers");
-                if (status)
-                        return status;
-        }
-
-        return 0;
-}
-
-/**
- * Allocate memory and initialize the FPA pools using memory
- * from cvmx-bootmem. Sizes of each element in the pools is
- * controlled by the cvmx-config.h header file. Specifying
- * zero for any parameter will cause that FPA pool to not be
- * setup. This is useful if you aren't using some of the
- * hardware and want to save memory.
- *
- * @packet_buffers:
- *               Number of packet buffers to allocate
- * @work_queue_entries:
- *               Number of work queue entries
- * @pko_buffers:
- *               PKO Command buffers. You should at minimum have two per
- *               each PKO queue.
- * @tim_buffers:
- *               TIM ring buffer command queues. At least two per timer bucket
- *               is recommened.
- * @dfa_buffers:
- *               DFA command buffer. A relatively small (32 for example)
- *               number should work.
- * Returns Zero on success, non-zero if out of memory
- */
-int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries,
-                               int pko_buffers, int tim_buffers,
-                               int dfa_buffers)
-{
-#ifndef CVMX_FPA_PACKET_POOL
-#define CVMX_FPA_PACKET_POOL -1
-#define CVMX_FPA_PACKET_POOL_SIZE 0
-#endif
-#ifndef CVMX_FPA_WQE_POOL
-#define CVMX_FPA_WQE_POOL -1
-#define CVMX_FPA_WQE_POOL_SIZE 0
-#endif
-#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL
-#define CVMX_FPA_OUTPUT_BUFFER_POOL -1
-#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0
-#endif
-#ifndef CVMX_FPA_TIMER_POOL
-#define CVMX_FPA_TIMER_POOL -1
-#define CVMX_FPA_TIMER_POOL_SIZE 0
-#endif
-#ifndef CVMX_FPA_DFA_POOL
-#define CVMX_FPA_DFA_POOL -1
-#define CVMX_FPA_DFA_POOL_SIZE 0
-#endif
-        return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL,
-                                            CVMX_FPA_PACKET_POOL_SIZE,
-                                            packet_buffers, CVMX_FPA_WQE_POOL,
-                                            CVMX_FPA_WQE_POOL_SIZE,
-                                            work_queue_entries,
-                                            CVMX_FPA_OUTPUT_BUFFER_POOL,
-                                            CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE,
-                                            pko_buffers, CVMX_FPA_TIMER_POOL,
-                                            CVMX_FPA_TIMER_POOL_SIZE,
-                                            tim_buffers, CVMX_FPA_DFA_POOL,
-                                            CVMX_FPA_DFA_POOL_SIZE,
-                                            dfa_buffers);
-}
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index ffd4ae660f7..274cd4fad30 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -3,14 +3,17 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks
+ * Copyright (C) 2004-2012 Cavium, Inc.
  */
 
 #include <linux/interrupt.h>
+#include <linux/irqdomain.h>
 #include <linux/bitops.h>
 #include <linux/percpu.h>
+#include <linux/slab.h>
 #include <linux/irq.h>
 #include <linux/smp.h>
+#include <linux/of.h>
 
 #include <asm/octeon/octeon.h>
 
@@ -42,9 +45,9 @@ struct octeon_core_chip_data {
 
 static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
 
-static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit,
-                                              struct irq_chip *chip,
-                                              irq_flow_handler_t handler)
+static void octeon_irq_set_ciu_mapping(int irq, int line, int bit,
+                                       struct irq_chip *chip,
+                                       irq_flow_handler_t handler)
 {
         union octeon_ciu_chip_data cd;
 
@@ -58,6 +61,12 @@ static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit,
         octeon_irq_ciu_to_irq[line][bit] = irq;
 }
 
+static void octeon_irq_force_ciu_mapping(struct irq_domain *domain,
+                                         int irq, int line, int bit)
+{
+        irq_domain_associate(domain, irq, line << 6 | bit);
+}
+
 static int octeon_coreid_for_cpu(int cpu)
 {
 #ifdef CONFIG_SMP
@@ -180,19 +189,9 @@ static void __init octeon_irq_init_core(void)
                 mutex_init(&cd->core_irq_mutex);
 
                 irq = OCTEON_IRQ_SW0 + i;
-                switch (irq) {
-                case OCTEON_IRQ_TIMER:
-                case OCTEON_IRQ_SW0:
-                case OCTEON_IRQ_SW1:
-                case OCTEON_IRQ_5:
-                case OCTEON_IRQ_PERF:
-                        irq_set_chip_data(irq, cd);
-                        irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
-                                                 handle_percpu_irq);
-                        break;
-                default:
-                        break;
-                }
+                irq_set_chip_data(irq, cd);
+                irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
+                                         handle_percpu_irq);
         }
 }
 
@@ -505,6 +504,85 @@ static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
         }
 }
 
+static void octeon_irq_gpio_setup(struct irq_data *data)
+{
+        union cvmx_gpio_bit_cfgx cfg;
+        union octeon_ciu_chip_data cd;
+        u32 t = irqd_get_trigger_type(data);
+
+        cd.p = irq_data_get_irq_chip_data(data);
+
+        cfg.u64 = 0;
+        cfg.s.int_en = 1;
+        cfg.s.int_type = (t & IRQ_TYPE_EDGE_BOTH) != 0;
+        cfg.s.rx_xor = (t & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) != 0;
+
+        /* 140 nS glitch filter*/
+        cfg.s.fil_cnt = 7;
+        cfg.s.fil_sel = 3;
+
+        cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), cfg.u64);
+}
+
+static void octeon_irq_ciu_enable_gpio_v2(struct irq_data *data)
+{
+        octeon_irq_gpio_setup(data);
+        octeon_irq_ciu_enable_v2(data);
+}
+
+static void octeon_irq_ciu_enable_gpio(struct irq_data *data)
+{
+        octeon_irq_gpio_setup(data);
+        octeon_irq_ciu_enable(data);
+}
+
+static int octeon_irq_ciu_gpio_set_type(struct irq_data *data, unsigned int t)
+{
+        irqd_set_trigger_type(data, t);
+        octeon_irq_gpio_setup(data);
+
+        return IRQ_SET_MASK_OK;
+}
+
+static void octeon_irq_ciu_disable_gpio_v2(struct irq_data *data)
+{
+        union octeon_ciu_chip_data cd;
+
+        cd.p = irq_data_get_irq_chip_data(data);
+        cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0);
+
+        octeon_irq_ciu_disable_all_v2(data);
+}
+
+static void octeon_irq_ciu_disable_gpio(struct irq_data *data)
+{
+        union octeon_ciu_chip_data cd;
+
+        cd.p = irq_data_get_irq_chip_data(data);
+        cvmx_write_csr(CVMX_GPIO_BIT_CFGX(cd.s.bit - 16), 0);
+
+        octeon_irq_ciu_disable_all(data);
+}
+
+static void octeon_irq_ciu_gpio_ack(struct irq_data *data)
+{
+        union octeon_ciu_chip_data cd;
+        u64 mask;
+
+        cd.p = irq_data_get_irq_chip_data(data);
+        mask = 1ull << (cd.s.bit - 16);
+
+        cvmx_write_csr(CVMX_GPIO_INT_CLR, mask);
+}
+
+static void octeon_irq_handle_gpio(unsigned int irq, struct irq_desc *desc)
+{
+        if (irqd_get_trigger_type(irq_desc_get_irq_data(desc)) & IRQ_TYPE_EDGE_BOTH)
+                handle_edge_irq(irq, desc);
+        else
+                handle_level_irq(irq, desc);
+}
+
 #ifdef CONFIG_SMP
 
 static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
@@ -650,18 +728,6 @@ static struct irq_chip octeon_irq_chip_ciu_v2 = {
         .name = "CIU",
         .irq_enable = octeon_irq_ciu_enable_v2,
         .irq_disable = octeon_irq_ciu_disable_all_v2,
-        .irq_mask = octeon_irq_ciu_disable_local_v2,
-        .irq_unmask = octeon_irq_ciu_enable_v2,
-#ifdef CONFIG_SMP
-        .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
-        .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
-#endif
-};
-
-static struct irq_chip octeon_irq_chip_ciu_edge_v2 = {
-        .name = "CIU-E",
-        .irq_enable = octeon_irq_ciu_enable_v2,
-        .irq_disable = octeon_irq_ciu_disable_all_v2,
         .irq_ack = octeon_irq_ciu_ack,
         .irq_mask = octeon_irq_ciu_disable_local_v2,
         .irq_unmask = octeon_irq_ciu_enable_v2,
@@ -675,19 +741,8 @@ static struct irq_chip octeon_irq_chip_ciu = {
         .name = "CIU",
         .irq_enable = octeon_irq_ciu_enable,
         .irq_disable = octeon_irq_ciu_disable_all,
-        .irq_mask = octeon_irq_dummy_mask,
-#ifdef CONFIG_SMP
-        .irq_set_affinity = octeon_irq_ciu_set_affinity,
-        .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
-#endif
-};
-
-static struct irq_chip octeon_irq_chip_ciu_edge = {
-        .name = "CIU-E",
-        .irq_enable = octeon_irq_ciu_enable,
-        .irq_disable = octeon_irq_ciu_disable_all,
-        .irq_mask = octeon_irq_dummy_mask,
         .irq_ack = octeon_irq_ciu_ack,
+        .irq_mask = octeon_irq_dummy_mask,
 #ifdef CONFIG_SMP
         .irq_set_affinity = octeon_irq_ciu_set_affinity,
         .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
@@ -717,6 +772,33 @@ static struct irq_chip octeon_irq_chip_ciu_mbox = {
         .flags = IRQCHIP_ONOFFLINE_ENABLED,
 };
 
+static struct irq_chip octeon_irq_chip_ciu_gpio_v2 = {
+        .name = "CIU-GPIO",
+        .irq_enable = octeon_irq_ciu_enable_gpio_v2,
+        .irq_disable = octeon_irq_ciu_disable_gpio_v2,
+        .irq_ack = octeon_irq_ciu_gpio_ack,
+        .irq_mask = octeon_irq_ciu_disable_local_v2,
+        .irq_unmask = octeon_irq_ciu_enable_v2,
+        .irq_set_type = octeon_irq_ciu_gpio_set_type,
+#ifdef CONFIG_SMP
+        .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
+#endif
+        .flags = IRQCHIP_SET_TYPE_MASKED,
+};
+
+static struct irq_chip octeon_irq_chip_ciu_gpio = {
+        .name = "CIU-GPIO",
+        .irq_enable = octeon_irq_ciu_enable_gpio,
+        .irq_disable = octeon_irq_ciu_disable_gpio,
+        .irq_mask = octeon_irq_dummy_mask,
+        .irq_ack = octeon_irq_ciu_gpio_ack,
+        .irq_set_type = octeon_irq_ciu_gpio_set_type,
+#ifdef CONFIG_SMP
+        .irq_set_affinity = octeon_irq_ciu_set_affinity,
+#endif
+        .flags = IRQCHIP_SET_TYPE_MASKED,
+};
+
 /*
  * Watchdog interrupts are special.  They are associated with a single
  * core, so we hardwire the affinity to that core.
@@ -764,6 +846,178 @@ static struct irq_chip octeon_irq_chip_ciu_wd = {
         .irq_mask = octeon_irq_dummy_mask,
 };
 
+static bool octeon_irq_ciu_is_edge(unsigned int line, unsigned int bit)
+{
+        bool edge = false;
+
+        if (line == 0)
+                switch (bit) {
+                case 48 ... 49: /* GMX DRP */
+                case 50: /* IPD_DRP */
+                case 52 ... 55: /* Timers */
+                case 58: /* MPI */
+                        edge = true;
+                        break;
+                default:
+                        break;
+                }
+        else /* line == 1 */
+                switch (bit) {
+                case 47: /* PTP */
+                        edge = true;
+                        break;
+                default:
+                        break;
+                }
+        return edge;
+}
+
+struct octeon_irq_gpio_domain_data {
+        unsigned int base_hwirq;
+};
+
+static int octeon_irq_gpio_xlat(struct irq_domain *d,
+                                struct device_node *node,
+                                const u32 *intspec,
+                                unsigned int intsize,
+                                unsigned long *out_hwirq,
+                                unsigned int *out_type)
+{
+        unsigned int type;
+        unsigned int pin;
+        unsigned int trigger;
+
+        if (d->of_node != node)
+                return -EINVAL;
+
+        if (intsize < 2)
+                return -EINVAL;
+
+        pin = intspec[0];
+        if (pin >= 16)
+                return -EINVAL;
+
+        trigger = intspec[1];
+
+        switch (trigger) {
+        case 1:
+                type = IRQ_TYPE_EDGE_RISING;
+                break;
+        case 2:
+                type = IRQ_TYPE_EDGE_FALLING;
+                break;
+        case 4:
+                type = IRQ_TYPE_LEVEL_HIGH;
+                break;
+        case 8:
+                type = IRQ_TYPE_LEVEL_LOW;
+                break;
+        default:
+                pr_err("Error: (%s) Invalid irq trigger specification: %x\n",
+                       node->name,
+                       trigger);
+                type = IRQ_TYPE_LEVEL_LOW;
+                break;
+        }
+        *out_type = type;
+        *out_hwirq = pin;
+
+        return 0;
+}
+
+static int octeon_irq_ciu_xlat(struct irq_domain *d,
+                               struct device_node *node,
+                               const u32 *intspec,
+                               unsigned int intsize,
+                               unsigned long *out_hwirq,
+                               unsigned int *out_type)
+{
+        unsigned int ciu, bit;
+
+        ciu = intspec[0];
+        bit = intspec[1];
+
+        if (ciu > 1 || bit > 63)
+                return -EINVAL;
+
+        /* These are the GPIO lines */
+        if (ciu == 0 && bit >= 16 && bit < 32)
+                return -EINVAL;
+
+        *out_hwirq = (ciu << 6) | bit;
+        *out_type = 0;
+
+        return 0;
+}
+
+static struct irq_chip *octeon_irq_ciu_chip;
+static struct irq_chip *octeon_irq_gpio_chip;
+
+static bool octeon_irq_virq_in_range(unsigned int virq)
+{
+        /* We cannot let it overflow the mapping array. */
+        if (virq < (1ul << 8 * sizeof(octeon_irq_ciu_to_irq[0][0])))
+                return true;
+
+        WARN_ONCE(true, "virq out of range %u.\n", virq);
+        return false;
+}
+
+static int octeon_irq_ciu_map(struct irq_domain *d,
+                              unsigned int virq, irq_hw_number_t hw)
+{
+        unsigned int line = hw >> 6;
+        unsigned int bit = hw & 63;
+
+        if (!octeon_irq_virq_in_range(virq))
+                return -EINVAL;
+
+        if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
+                return -EINVAL;
+
+        if (octeon_irq_ciu_is_edge(line, bit))
+                octeon_irq_set_ciu_mapping(virq, line, bit,
+                                           octeon_irq_ciu_chip,
+                                           handle_edge_irq);
+        else
+                octeon_irq_set_ciu_mapping(virq, line, bit,
+                                           octeon_irq_ciu_chip,
+                                           handle_level_irq);
+
+        return 0;
+}
+
+static int octeon_irq_gpio_map(struct irq_domain *d,
+                               unsigned int virq, irq_hw_number_t hw)
+{
+        struct octeon_irq_gpio_domain_data *gpiod = d->host_data;
+        unsigned int line, bit;
+
+        if (!octeon_irq_virq_in_range(virq))
+                return -EINVAL;
+
+        hw += gpiod->base_hwirq;
+        line = hw >> 6;
+        bit = hw & 63;
+        if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)
+                return -EINVAL;
+
+        octeon_irq_set_ciu_mapping(virq, line, bit,
+                                   octeon_irq_gpio_chip,
+                                   octeon_irq_handle_gpio);
+        return 0;
+}
+
+static struct irq_domain_ops octeon_irq_domain_ciu_ops = {
+        .map = octeon_irq_ciu_map,
+        .xlate = octeon_irq_ciu_xlat,
+};
+
+static struct irq_domain_ops octeon_irq_domain_gpio_ops = {
+        .map = octeon_irq_gpio_map,
+        .xlate = octeon_irq_gpio_xlat,
+};
+
 static void octeon_irq_ip2_v1(void)
 {
         const unsigned long core_id = cvmx_get_core_num();
@@ -887,9 +1141,11 @@ static void __init octeon_irq_init_ciu(void)
 {
         unsigned int i;
         struct irq_chip *chip;
-        struct irq_chip *chip_edge;
         struct irq_chip *chip_mbox;
         struct irq_chip *chip_wd;
+        struct device_node *gpio_node;
+        struct device_node *ciu_node;
+        struct irq_domain *ciu_domain = NULL;
 
         octeon_irq_init_ciu_percpu();
         octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
@@ -901,99 +1157,69 @@ static void __init octeon_irq_init_ciu(void)
                 octeon_irq_ip2 = octeon_irq_ip2_v2;
                 octeon_irq_ip3 = octeon_irq_ip3_v2;
                 chip = &octeon_irq_chip_ciu_v2;
-                chip_edge = &octeon_irq_chip_ciu_edge_v2;
                 chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
                 chip_wd = &octeon_irq_chip_ciu_wd_v2;
+                octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio_v2;
         } else {
                 octeon_irq_ip2 = octeon_irq_ip2_v1;
                 octeon_irq_ip3 = octeon_irq_ip3_v1;
                 chip = &octeon_irq_chip_ciu;
-                chip_edge = &octeon_irq_chip_ciu_edge;
                 chip_mbox = &octeon_irq_chip_ciu_mbox;
                 chip_wd = &octeon_irq_chip_ciu_wd;
+                octeon_irq_gpio_chip = &octeon_irq_chip_ciu_gpio;
         }
+        octeon_irq_ciu_chip = chip;
         octeon_irq_ip4 = octeon_irq_ip4_mask;
 
         /* Mips internal */
         octeon_irq_init_core();
 
+        gpio_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-gpio");
+        if (gpio_node) {
+                struct octeon_irq_gpio_domain_data *gpiod;
+
+                gpiod = kzalloc(sizeof(*gpiod), GFP_KERNEL);
+                if (gpiod) {
+                        /* gpio domain host_data is the base hwirq number. */
+                        gpiod->base_hwirq = 16;
+                        irq_domain_add_linear(gpio_node, 16, &octeon_irq_domain_gpio_ops, gpiod);
+                        of_node_put(gpio_node);
+                } else
+                        pr_warn("Cannot allocate memory for GPIO irq_domain.\n");
+        } else
+                pr_warn("Cannot find device node for cavium,octeon-3860-gpio.\n");
+
+        ciu_node = of_find_compatible_node(NULL, NULL, "cavium,octeon-3860-ciu");
+        if (ciu_node) {
+                ciu_domain = irq_domain_add_tree(ciu_node, &octeon_irq_domain_ciu_ops, NULL);
+                of_node_put(ciu_node);
+        } else
+                panic("Cannot find device node for cavium,octeon-3860-ciu.");
+
         /* CIU_0 */
         for (i = 0; i < 16; i++)
-                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq);
-        for (i = 0; i < 16; i++)
-                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq);
+                octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_WORKQ0, 0, i + 0);
 
         octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
         octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
 
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq);
-
         for (i = 0; i < 4; i++)
-                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq);
+                octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_INT0, 0, i + 36);
         for (i = 0; i < 4; i++)
-                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq);
-
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq);
-
-        for (i = 0; i < 2; i++)
-                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq);
-
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq);
+                octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_PCI_MSI0, 0, i + 40);
 
+        octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_RML, 0, 46);
         for (i = 0; i < 4; i++)
-                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq);
+                octeon_irq_force_ciu_mapping(ciu_domain, i + OCTEON_IRQ_TIMER0, 0, i + 52);
 
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq);
+        octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB0, 0, 56);
+        octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_BOOTDMA, 0, 63);
 
         /* CIU_1 */
         for (i = 0; i < 16; i++)
                 octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
 
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq);
-
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq);
-
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq);
-
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq);
-
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq);
-        octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq);
+        octeon_irq_force_ciu_mapping(ciu_domain, OCTEON_IRQ_USB1, 1, 17);
 
         /* Enable the CIU lines */
         set_c0_status(STATUSF_IP3 | STATUSF_IP2);
diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S
index 88e0cddca20..db478dbb9c7 100644
--- a/arch/mips/cavium-octeon/octeon-memcpy.S
+++ b/arch/mips/cavium-octeon/octeon-memcpy.S
@@ -164,6 +164,14 @@
         .set    noat
 
 /*
+ * t7 is used as a flag to note inatomic mode.
+ */
+LEAF(__copy_user_inatomic)
+        b       __copy_user_common
+         li     t7, 1
+        END(__copy_user_inatomic)
+
+/*
  * A combined memcpy/__copy_user
  * __copy_user sets len to 0 for success; else to an upper bound of
  * the number of uncopied bytes.
@@ -174,6 +182,8 @@ LEAF(memcpy)					/* a0=dst a1=src a2=len */
         move    v0, dst                         /* return value */
 __memcpy:
 FEXPORT(__copy_user)
+        li      t7, 0                           /* not inatomic */
+__copy_user_common:
         /*
          * Note: dst & src may be unaligned, len may be 0
          * Temps
@@ -412,7 +422,6 @@ l_exc_copy:
          * Assumes src < THREAD_BUADDR($28)
          */
         LOAD    t0, TI_TASK($28)
-         nop
         LOAD    t0, THREAD_BUADDR(t0)
 1:
 EXC(    lb      t1, 0(src),     l_exc)
@@ -422,10 +431,9 @@ EXC(	lb	t1, 0(src),	l_exc)
          ADD    dst, dst, 1
 l_exc:
         LOAD    t0, TI_TASK($28)
-         nop
         LOAD    t0, THREAD_BUADDR(t0)   # t0 is just past last good address
-         nop
         SUB     len, AT, t0             # len number of uncopied bytes
+        bnez    t7, 2f          /* Skip the zeroing out part if inatomic */
         /*
          * Here's where we rely on src and dst being incremented in tandem,
          *   See (3) above.
@@ -443,7 +451,7 @@ l_exc:
         ADD     dst, dst, 1
         bnez    src, 1b
          SUB    src, src, 1
-        jr      ra
+2:      jr      ra
          nop
 
 
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index cd61d7281d9..0938df10a71 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2010 Cavium Networks
+ * Copyright (C) 2004-2011 Cavium Networks
  * Copyright (C) 2008 Wind River Systems
  */
 
@@ -13,10 +13,16 @@
 #include <linux/usb.h>
 #include <linux/dma-mapping.h>
 #include <linux/module.h>
+#include <linux/slab.h>
 #include <linux/platform_device.h>
+#include <linux/of_platform.h>
+#include <linux/of_fdt.h>
+#include <linux/libfdt.h>
 
 #include <asm/octeon/octeon.h>
 #include <asm/octeon/cvmx-rnm-defs.h>
+#include <asm/octeon/cvmx-helper.h>
+#include <asm/octeon/cvmx-helper-board.h>
 
 static struct octeon_cf_data octeon_cf_data;
 
@@ -162,182 +168,6 @@ out:
 }
 device_initcall(octeon_rng_device_init);
 
-static struct i2c_board_info __initdata octeon_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("ds1337", 0x68),
-        },
-};
-
-static int __init octeon_i2c_devices_init(void)
-{
-        return i2c_register_board_info(0, octeon_i2c_devices,
-                                       ARRAY_SIZE(octeon_i2c_devices));
-}
-arch_initcall(octeon_i2c_devices_init);
-
-#define OCTEON_I2C_IO_BASE 0x1180000001000ull
-#define OCTEON_I2C_IO_UNIT_OFFSET 0x200
-
-static struct octeon_i2c_data octeon_i2c_data[2];
-
-static int __init octeon_i2c_device_init(void)
-{
-        struct platform_device *pd;
-        int ret = 0;
-        int port, num_ports;
-
-        struct resource i2c_resources[] = {
-                {
-                        .flags  = IORESOURCE_MEM,
-                }, {
-                        .flags  = IORESOURCE_IRQ,
-                }
-        };
-
-        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
-                num_ports = 2;
-        else
-                num_ports = 1;
-
-        for (port = 0; port < num_ports; port++) {
-                octeon_i2c_data[port].sys_freq = octeon_get_io_clock_rate();
-                /*FIXME: should be examined. At the moment is set for 100Khz */
-                octeon_i2c_data[port].i2c_freq = 100000;
-
-                pd = platform_device_alloc("i2c-octeon", port);
-                if (!pd) {
-                        ret = -ENOMEM;
-                        goto out;
-                }
-
-                pd->dev.platform_data = octeon_i2c_data + port;
-
-                i2c_resources[0].start =
-                        OCTEON_I2C_IO_BASE + (port * OCTEON_I2C_IO_UNIT_OFFSET);
-                i2c_resources[0].end = i2c_resources[0].start + 0x1f;
-                switch (port) {
-                case 0:
-                        i2c_resources[1].start = OCTEON_IRQ_TWSI;
-                        i2c_resources[1].end = OCTEON_IRQ_TWSI;
-                        break;
-                case 1:
-                        i2c_resources[1].start = OCTEON_IRQ_TWSI2;
-                        i2c_resources[1].end = OCTEON_IRQ_TWSI2;
-                        break;
-                default:
-                        BUG();
-                }
-
-                ret = platform_device_add_resources(pd,
-                                                    i2c_resources,
-                                                    ARRAY_SIZE(i2c_resources));
-                if (ret)
-                        goto fail;
-
-                ret = platform_device_add(pd);
-                if (ret)
-                        goto fail;
-        }
-        return ret;
-fail:
-        platform_device_put(pd);
-out:
-        return ret;
-}
-device_initcall(octeon_i2c_device_init);
-
-/* Octeon SMI/MDIO interface.  */
-static int __init octeon_mdiobus_device_init(void)
-{
-        struct platform_device *pd;
-        int ret = 0;
-
-        if (octeon_is_simulation())
-                return 0; /* No mdio in the simulator. */
-
-        /* The bus number is the platform_device id.  */
-        pd = platform_device_alloc("mdio-octeon", 0);
-        if (!pd) {
-                ret = -ENOMEM;
-                goto out;
-        }
-
-        ret = platform_device_add(pd);
-        if (ret)
-                goto fail;
-
-        return ret;
-fail:
-        platform_device_put(pd);
-
-out:
-        return ret;
-
-}
-device_initcall(octeon_mdiobus_device_init);
-
-/* Octeon mgmt port Ethernet interface.  */
-static int __init octeon_mgmt_device_init(void)
-{
-        struct platform_device *pd;
-        int ret = 0;
-        int port, num_ports;
-
-        struct resource mgmt_port_resource = {
-                .flags  = IORESOURCE_IRQ,
-                .start  = -1,
-                .end    = -1
-        };
-
-        if (!OCTEON_IS_MODEL(OCTEON_CN56XX) && !OCTEON_IS_MODEL(OCTEON_CN52XX))
-                return 0;
-
-        if (OCTEON_IS_MODEL(OCTEON_CN56XX))
-                num_ports = 1;
-        else
-                num_ports = 2;
-
-        for (port = 0; port < num_ports; port++) {
-                pd = platform_device_alloc("octeon_mgmt", port);
-                if (!pd) {
-                        ret = -ENOMEM;
-                        goto out;
-                }
-                /* No DMA restrictions */
-                pd->dev.coherent_dma_mask = DMA_BIT_MASK(64);
-                pd->dev.dma_mask = &pd->dev.coherent_dma_mask;
-
-                switch (port) {
-                case 0:
-                        mgmt_port_resource.start = OCTEON_IRQ_MII0;
-                        break;
-                case 1:
-                        mgmt_port_resource.start = OCTEON_IRQ_MII1;
-                        break;
-                default:
-                        BUG();
-                }
-                mgmt_port_resource.end = mgmt_port_resource.start;
-
-                ret = platform_device_add_resources(pd, &mgmt_port_resource, 1);
-
-                if (ret)
-                        goto fail;
-
-                ret = platform_device_add(pd);
-                if (ret)
-                        goto fail;
-        }
-        return ret;
-fail:
-        platform_device_put(pd);
-
-out:
-        return ret;
-
-}
-device_initcall(octeon_mgmt_device_init);
-
 #ifdef CONFIG_USB
 
 static int __init octeon_ehci_device_init(void)
@@ -440,6 +270,521 @@ device_initcall(octeon_ohci_device_init);
 
 #endif /* CONFIG_USB */
 
+static struct of_device_id __initdata octeon_ids[] = {
+        { .compatible = "simple-bus", },
+        { .compatible = "cavium,octeon-6335-uctl", },
+        { .compatible = "cavium,octeon-3860-bootbus", },
+        { .compatible = "cavium,mdio-mux", },
+        { .compatible = "gpio-leds", },
+        {},
+};
+
+static bool __init octeon_has_88e1145(void)
+{
+        return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
+               !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
+               !OCTEON_IS_MODEL(OCTEON_CN56XX);
+}
+
+static void __init octeon_fdt_set_phy(int eth, int phy_addr)
+{
+        const __be32 *phy_handle;
+        const __be32 *alt_phy_handle;
+        const __be32 *reg;
+        u32 phandle;
+        int phy;
+        int alt_phy;
+        const char *p;
+        int current_len;
+        char new_name[20];
+
+        phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
+        if (!phy_handle)
+                return;
+
+        phandle = be32_to_cpup(phy_handle);
+        phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
+
+        alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
+        if (alt_phy_handle) {
+                u32 alt_phandle = be32_to_cpup(alt_phy_handle);
+                alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
+        } else {
+                alt_phy = -1;
+        }
+
+        if (phy_addr < 0 || phy < 0) {
+                /* Delete the PHY things */
+                fdt_nop_property(initial_boot_params, eth, "phy-handle");
+                /* This one may fail */
+                fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
+                if (phy >= 0)
+                        fdt_nop_node(initial_boot_params, phy);
+                if (alt_phy >= 0)
+                        fdt_nop_node(initial_boot_params, alt_phy);
+                return;
+        }
+
+        if (phy_addr >= 256 && alt_phy > 0) {
+                const struct fdt_property *phy_prop;
+                struct fdt_property *alt_prop;
+                u32 phy_handle_name;
+
+                /* Use the alt phy node instead.*/
+                phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
+                phy_handle_name = phy_prop->nameoff;
+                fdt_nop_node(initial_boot_params, phy);
+                fdt_nop_property(initial_boot_params, eth, "phy-handle");
+                alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
+                alt_prop->nameoff = phy_handle_name;
+                phy = alt_phy;
+        }
+
+        phy_addr &= 0xff;
+
+        if (octeon_has_88e1145()) {
+                fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
+                memset(new_name, 0, sizeof(new_name));
+                strcpy(new_name, "marvell,88e1145");
+                p = fdt_getprop(initial_boot_params, phy, "compatible",
+                                &current_len);
+                if (p && current_len >= strlen(new_name))
+                        fdt_setprop_inplace(initial_boot_params, phy,
+                                        "compatible", new_name, current_len);
+        }
+
+        reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
+        if (phy_addr == be32_to_cpup(reg))
+                return;
+
+        fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
+
+        snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
+
+        p = fdt_get_name(initial_boot_params, phy, &current_len);
+        if (p && current_len == strlen(new_name))
+                fdt_set_name(initial_boot_params, phy, new_name);
+        else
+                pr_err("Error: could not rename ethernet phy: <%s>", p);
+}
+
+static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
+{
+        u8 new_mac[6];
+        u64 mac = *pmac;
+        int r;
+
+        new_mac[0] = (mac >> 40) & 0xff;
+        new_mac[1] = (mac >> 32) & 0xff;
+        new_mac[2] = (mac >> 24) & 0xff;
+        new_mac[3] = (mac >> 16) & 0xff;
+        new_mac[4] = (mac >> 8) & 0xff;
+        new_mac[5] = mac & 0xff;
+
+        r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
+                                new_mac, sizeof(new_mac));
+
+        if (r) {
+                pr_err("Setting \"local-mac-address\" failed %d", r);
+                return;
+        }
+        *pmac = mac + 1;
+}
+
+static void __init octeon_fdt_rm_ethernet(int node)
+{
+        const __be32 *phy_handle;
+
+        phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
+        if (phy_handle) {
+                u32 ph = be32_to_cpup(phy_handle);
+                int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
+                if (p >= 0)
+                        fdt_nop_node(initial_boot_params, p);
+        }
+        fdt_nop_node(initial_boot_params, node);
+}
+
+static void __init octeon_fdt_pip_port(int iface, int i, int p, int max, u64 *pmac)
+{
+        char name_buffer[20];
+        int eth;
+        int phy_addr;
+        int ipd_port;
+
+        snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
+        eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
+        if (eth < 0)
+                return;
+        if (p > max) {
+                pr_debug("Deleting port %x:%x\n", i, p);
+                octeon_fdt_rm_ethernet(eth);
+                return;
+        }
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
+        else
+                ipd_port = 16 * i + p;
+
+        phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
+        octeon_fdt_set_phy(eth, phy_addr);
+        octeon_fdt_set_mac_addr(eth, pmac);
+}
+
+static void __init octeon_fdt_pip_iface(int pip, int idx, u64 *pmac)
+{
+        char name_buffer[20];
+        int iface;
+        int p;
+        int count;
+
+        count = cvmx_helper_interface_enumerate(idx);
+
+        snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
+        iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
+        if (iface < 0)
+                return;
+
+        for (p = 0; p < 16; p++)
+                octeon_fdt_pip_port(iface, idx, p, count - 1, pmac);
+}
+
+int __init octeon_prune_device_tree(void)
+{
+        int i, max_port, uart_mask;
+        const char *pip_path;
+        const char *alias_prop;
+        char name_buffer[20];
+        int aliases;
+        u64 mac_addr_base;
+
+        if (fdt_check_header(initial_boot_params))
+                panic("Corrupt Device Tree.");
+
+        aliases = fdt_path_offset(initial_boot_params, "/aliases");
+        if (aliases < 0) {
+                pr_err("Error: No /aliases node in device tree.");
+                return -EINVAL;
+        }
+
+
+        mac_addr_base =
+                ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
+                ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
+                ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
+                ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
+                ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
+                (octeon_bootinfo->mac_addr_base[5] & 0xffull);
+
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
+                max_port = 2;
+        else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
+                max_port = 1;
+        else
+                max_port = 0;
+
+        if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
+                max_port = 0;
+
+        for (i = 0; i < 2; i++) {
+                int mgmt;
+                snprintf(name_buffer, sizeof(name_buffer),
+                         "mix%d", i);
+                alias_prop = fdt_getprop(initial_boot_params, aliases,
+                                        name_buffer, NULL);
+                if (alias_prop) {
+                        mgmt = fdt_path_offset(initial_boot_params, alias_prop);
+                        if (mgmt < 0)
+                                continue;
+                        if (i >= max_port) {
+                                pr_debug("Deleting mix%d\n", i);
+                                octeon_fdt_rm_ethernet(mgmt);
+                                fdt_nop_property(initial_boot_params, aliases,
+                                                 name_buffer);
+                        } else {
+                                int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
+                                octeon_fdt_set_phy(mgmt, phy_addr);
+                                octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
+                        }
+                }
+        }
+
+        pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
+        if (pip_path) {
+                int pip = fdt_path_offset(initial_boot_params, pip_path);
+                if (pip  >= 0)
+                        for (i = 0; i <= 4; i++)
+                                octeon_fdt_pip_iface(pip, i, &mac_addr_base);
+        }
+
+        /* I2C */
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
+            OCTEON_IS_MODEL(OCTEON_CN63XX) ||
+            OCTEON_IS_MODEL(OCTEON_CN68XX) ||
+            OCTEON_IS_MODEL(OCTEON_CN56XX))
+                max_port = 2;
+        else
+                max_port = 1;
+
+        for (i = 0; i < 2; i++) {
+                int i2c;
+                snprintf(name_buffer, sizeof(name_buffer),
+                         "twsi%d", i);
+                alias_prop = fdt_getprop(initial_boot_params, aliases,
+                                        name_buffer, NULL);
+
+                if (alias_prop) {
+                        i2c = fdt_path_offset(initial_boot_params, alias_prop);
+                        if (i2c < 0)
+                                continue;
+                        if (i >= max_port) {
+                                pr_debug("Deleting twsi%d\n", i);
+                                fdt_nop_node(initial_boot_params, i2c);
+                                fdt_nop_property(initial_boot_params, aliases,
+                                                 name_buffer);
+                        }
+                }
+        }
+
+        /* SMI/MDIO */
+        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
+                max_port = 4;
+        else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
+                 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
+                 OCTEON_IS_MODEL(OCTEON_CN56XX))
+                max_port = 2;
+        else
+                max_port = 1;
+
+        for (i = 0; i < 2; i++) {
+                int i2c;
+                snprintf(name_buffer, sizeof(name_buffer),
+                         "smi%d", i);
+                alias_prop = fdt_getprop(initial_boot_params, aliases,
+                                        name_buffer, NULL);
+
+                if (alias_prop) {
+                        i2c = fdt_path_offset(initial_boot_params, alias_prop);
+                        if (i2c < 0)
+                                continue;
+                        if (i >= max_port) {
+                                pr_debug("Deleting smi%d\n", i);
+                                fdt_nop_node(initial_boot_params, i2c);
+                                fdt_nop_property(initial_boot_params, aliases,
+                                                 name_buffer);
+                        }
+                }
+        }
+
+        /* Serial */
+        uart_mask = 3;
+
+        /* Right now CN52XX is the only chip with a third uart */
+        if (OCTEON_IS_MODEL(OCTEON_CN52XX))
+                uart_mask |= 4; /* uart2 */
+
+        for (i = 0; i < 3; i++) {
+                int uart;
+                snprintf(name_buffer, sizeof(name_buffer),
+                         "uart%d", i);
+                alias_prop = fdt_getprop(initial_boot_params, aliases,
+                                        name_buffer, NULL);
+
+                if (alias_prop) {
+                        uart = fdt_path_offset(initial_boot_params, alias_prop);
+                        if (uart_mask & (1 << i))
+                                continue;
+                        pr_debug("Deleting uart%d\n", i);
+                        fdt_nop_node(initial_boot_params, uart);
+                        fdt_nop_property(initial_boot_params, aliases,
+                                         name_buffer);
+                }
+        }
+
+        /* Compact Flash */
+        alias_prop = fdt_getprop(initial_boot_params, aliases,
+                                 "cf0", NULL);
+        if (alias_prop) {
+                union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
+                unsigned long base_ptr, region_base, region_size;
+                unsigned long region1_base = 0;
+                unsigned long region1_size = 0;
+                int cs, bootbus;
+                bool is_16bit = false;
+                bool is_true_ide = false;
+                __be32 new_reg[6];
+                __be32 *ranges;
+                int len;
+
+                int cf = fdt_path_offset(initial_boot_params, alias_prop);
+                base_ptr = 0;
+                if (octeon_bootinfo->major_version == 1
+                        && octeon_bootinfo->minor_version >= 1) {
+                        if (octeon_bootinfo->compact_flash_common_base_addr)
+                                base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
+                } else {
+                        base_ptr = 0x1d000800;
+                }
+
+                if (!base_ptr)
+                        goto no_cf;
+
+                /* Find CS0 region. */
+                for (cs = 0; cs < 8; cs++) {
+                        mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
+                        region_base = mio_boot_reg_cfg.s.base << 16;
+                        region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
+                        if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
+                                && base_ptr < region_base + region_size) {
+                                is_16bit = mio_boot_reg_cfg.s.width;
+                                break;
+                        }
+                }
+                if (cs >= 7) {
+                        /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
+                        goto no_cf;
+                }
+
+                if (!(base_ptr & 0xfffful)) {
+                        /*
+                         * Boot loader signals availability of DMA (true_ide
+                         * mode) by setting low order bits of base_ptr to
+                         * zero.
+                         */
+
+                        /* Asume that CS1 immediately follows. */
+                        mio_boot_reg_cfg.u64 =
+                                cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
+                        region1_base = mio_boot_reg_cfg.s.base << 16;
+                        region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
+                        if (!mio_boot_reg_cfg.s.en)
+                                goto no_cf;
+                        is_true_ide = true;
+
+                } else {
+                        fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
+                        fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
+                        if (!is_16bit) {
+                                __be32 width = cpu_to_be32(8);
+                                fdt_setprop_inplace(initial_boot_params, cf,
+                                                "cavium,bus-width", &width, sizeof(width));
+                        }
+                }
+                new_reg[0] = cpu_to_be32(cs);
+                new_reg[1] = cpu_to_be32(0);
+                new_reg[2] = cpu_to_be32(0x10000);
+                new_reg[3] = cpu_to_be32(cs + 1);
+                new_reg[4] = cpu_to_be32(0);
+                new_reg[5] = cpu_to_be32(0x10000);
+                fdt_setprop_inplace(initial_boot_params, cf,
+                                    "reg",  new_reg, sizeof(new_reg));
+
+                bootbus = fdt_parent_offset(initial_boot_params, cf);
+                if (bootbus < 0)
+                        goto no_cf;
+                ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
+                if (!ranges || len < (5 * 8 * sizeof(__be32)))
+                        goto no_cf;
+
+                ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
+                ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
+                ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
+                if (is_true_ide) {
+                        cs++;
+                        ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
+                        ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
+                        ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
+                }
+                goto end_cf;
+no_cf:
+                fdt_nop_node(initial_boot_params, cf);
+
+end_cf:
+                ;
+        }
+
+        /* 8 char LED */
+        alias_prop = fdt_getprop(initial_boot_params, aliases,
+                                 "led0", NULL);
+        if (alias_prop) {
+                union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
+                unsigned long base_ptr, region_base, region_size;
+                int cs, bootbus;
+                __be32 new_reg[6];
+                __be32 *ranges;
+                int len;
+                int led = fdt_path_offset(initial_boot_params, alias_prop);
+
+                base_ptr = octeon_bootinfo->led_display_base_addr;
+                if (base_ptr == 0)
+                        goto no_led;
+                /* Find CS0 region. */
+                for (cs = 0; cs < 8; cs++) {
+                        mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
+                        region_base = mio_boot_reg_cfg.s.base << 16;
+                        region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
+                        if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
+                                && base_ptr < region_base + region_size)
+                                break;
+                }
+
+                if (cs > 7)
+                        goto no_led;
+
+                new_reg[0] = cpu_to_be32(cs);
+                new_reg[1] = cpu_to_be32(0x20);
+                new_reg[2] = cpu_to_be32(0x20);
+                new_reg[3] = cpu_to_be32(cs);
+                new_reg[4] = cpu_to_be32(0);
+                new_reg[5] = cpu_to_be32(0x20);
+                fdt_setprop_inplace(initial_boot_params, led,
+                                    "reg",  new_reg, sizeof(new_reg));
+
+                bootbus = fdt_parent_offset(initial_boot_params, led);
+                if (bootbus < 0)
+                        goto no_led;
+                ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
+                if (!ranges || len < (5 * 8 * sizeof(__be32)))
+                        goto no_led;
+
+                ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
+                ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
+                ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
+                goto end_led;
+
+no_led:
+                fdt_nop_node(initial_boot_params, led);
+end_led:
+                ;
+        }
+
+        /* OHCI/UHCI USB */
+        alias_prop = fdt_getprop(initial_boot_params, aliases,
+                                 "uctl", NULL);
+        if (alias_prop) {
+                int uctl = fdt_path_offset(initial_boot_params, alias_prop);
+
+                if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
+                                  octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
+                        pr_debug("Deleting uctl\n");
+                        fdt_nop_node(initial_boot_params, uctl);
+                        fdt_nop_property(initial_boot_params, aliases, "uctl");
+                } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
+                           octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
+                        /* Missing "refclk-type" defaults to crystal. */
+                        fdt_nop_property(initial_boot_params, uctl, "refclk-type");
+                }
+        }
+
+        return 0;
+}
+
+static int __init octeon_publish_devices(void)
+{
+        return of_platform_bus_probe(NULL, octeon_ids, NULL);
+}
+device_initcall(octeon_publish_devices);
+
 MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>");
 MODULE_LICENSE("GPL");
 MODULE_DESCRIPTION("Platform driver for Octeon SOC");
diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts
new file mode 100644
index 00000000000..f28b2d0fde2
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon_3xxx.dts
@@ -0,0 +1,571 @@
+/dts-v1/;
+/*
+ * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
+ *
+ * This device tree is pruned and patched by early boot code before
+ * use.  Because of this, it contains a super-set of the available
+ * devices and properties.
+ */
+/ {
+        compatible = "cavium,octeon-3860";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&ciu>;
+
+        soc@0 {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges; /* Direct mapping */
+
+                ciu: interrupt-controller@1070000000000 {
+                        compatible = "cavium,octeon-3860-ciu";
+                        interrupt-controller;
+                        /* Interrupts are specified by two parts:
+                         * 1) Controller register (0 or 1)
+                         * 2) Bit within the register (0..63)
+                         */
+                        #interrupt-cells = <2>;
+                        reg = <0x10700 0x00000000 0x0 0x7000>;
+                };
+
+                gpio: gpio-controller@1070000000800 {
+                        #gpio-cells = <2>;
+                        compatible = "cavium,octeon-3860-gpio";
+                        reg = <0x10700 0x00000800 0x0 0x100>;
+                        gpio-controller;
+                        /* Interrupts are specified by two parts:
+                         * 1) GPIO pin number (0..15)
+                         * 2) Triggering (1 - edge rising
+                         *                2 - edge falling
+                         *                4 - level active high
+                         *                8 - level active low)
+                         */
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        /* The GPIO pin connect to 16 consecutive CUI bits */
+                        interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
+                                     <0 20>, <0 21>, <0 22>, <0 23>,
+                                     <0 24>, <0 25>, <0 26>, <0 27>,
+                                     <0 28>, <0 29>, <0 30>, <0 31>;
+                };
+
+                smi0: mdio@1180000001800 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00001800 0x0 0x40>;
+
+                        phy0: ethernet-phy@0 {
+                                compatible = "marvell,88e1118";
+                                marvell,reg-init =
+                                        /* Fix rx and tx clock transition timing */
+                                        <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
+                                        /* Adjust LED drive. */
+                                        <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
+                                        /* irq, blink-activity, blink-link */
+                                        <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
+                                reg = <0>;
+                        };
+
+                        phy1: ethernet-phy@1 {
+                                compatible = "marvell,88e1118";
+                                marvell,reg-init =
+                                        /* Fix rx and tx clock transition timing */
+                                        <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
+                                        /* Adjust LED drive. */
+                                        <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
+                                        /* irq, blink-activity, blink-link */
+                                        <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
+                                reg = <1>;
+                        };
+
+                        phy2: ethernet-phy@2 {
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy3: ethernet-phy@3 {
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy4: ethernet-phy@4 {
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy5: ethernet-phy@5 {
+                                reg = <5>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+
+                        phy6: ethernet-phy@6 {
+                                reg = <6>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy7: ethernet-phy@7 {
+                                reg = <7>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy8: ethernet-phy@8 {
+                                reg = <8>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy9: ethernet-phy@9 {
+                                reg = <9>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                };
+
+                smi1: mdio@1180000001900 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00001900 0x0 0x40>;
+
+                        phy100: ethernet-phy@1 {
+                                reg = <1>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                                interrupt-parent = <&gpio>;
+                                interrupts = <12 8>; /* Pin 12, active low */
+                        };
+                        phy101: ethernet-phy@2 {
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                                interrupt-parent = <&gpio>;
+                                interrupts = <12 8>; /* Pin 12, active low */
+                        };
+                        phy102: ethernet-phy@3 {
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                                interrupt-parent = <&gpio>;
+                                interrupts = <12 8>; /* Pin 12, active low */
+                        };
+                        phy103: ethernet-phy@4 {
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                                interrupt-parent = <&gpio>;
+                                interrupts = <12 8>; /* Pin 12, active low */
+                        };
+                };
+
+                mix0: ethernet@1070000100000 {
+                        compatible = "cavium,octeon-5750-mix";
+                        reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
+                              <0x11800 0xE0000000 0x0 0x300>, /* AGL */
+                              <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
+                              <0x11800 0xE0002000 0x0 0x8>;   /* AGL_PRT_CTL */
+                        cell-index = <0>;
+                        interrupts = <0 62>, <1 46>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        phy-handle = <&phy0>;
+                };
+
+                mix1: ethernet@1070000100800 {
+                        compatible = "cavium,octeon-5750-mix";
+                        reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
+                              <0x11800 0xE0000800 0x0 0x300>, /* AGL */
+                              <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
+                              <0x11800 0xE0002008 0x0 0x8>;   /* AGL_PRT_CTL */
+                        cell-index = <1>;
+                        interrupts = <1 18>, < 1 46>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        phy-handle = <&phy1>;
+                };
+
+                pip: pip@11800a0000000 {
+                        compatible = "cavium,octeon-3860-pip";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0xa0000000 0x0 0x2000>;
+
+                        interface@0 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy2>;
+                                        cavium,alt-phy-handle = <&phy100>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy3>;
+                                        cavium,alt-phy-handle = <&phy101>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy4>;
+                                        cavium,alt-phy-handle = <&phy102>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy5>;
+                                        cavium,alt-phy-handle = <&phy103>;
+                                };
+                                ethernet@4 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x4>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@5 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x5>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@6 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x6>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@7 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x7>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@8 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x8>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@9 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x9>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@a {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xa>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@b {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xb>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@c {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xc>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@d {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xd>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@e {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xe>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                                ethernet@f {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0xf>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                        };
+
+                        interface@1 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <1>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy6>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy7>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy8>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy9>;
+                                };
+                        };
+                };
+
+                twsi0: i2c@1180000001000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "cavium,octeon-3860-twsi";
+                        reg = <0x11800 0x00001000 0x0 0x200>;
+                        interrupts = <0 45>;
+                        clock-frequency = <100000>;
+
+                        rtc@68 {
+                                compatible = "dallas,ds1337";
+                                reg = <0x68>;
+                        };
+                        tmp@4c {
+                                compatible = "ti,tmp421";
+                                reg = <0x4c>;
+                        };
+                };
+
+                twsi1: i2c@1180000001200 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "cavium,octeon-3860-twsi";
+                        reg = <0x11800 0x00001200 0x0 0x200>;
+                        interrupts = <0 59>;
+                        clock-frequency = <100000>;
+                };
+
+                uart0: serial@1180000000800 {
+                        compatible = "cavium,octeon-3860-uart","ns16550";
+                        reg = <0x11800 0x00000800 0x0 0x400>;
+                        clock-frequency = <0>;
+                        current-speed = <115200>;
+                        reg-shift = <3>;
+                        interrupts = <0 34>;
+                };
+
+                uart1: serial@1180000000c00 {
+                        compatible = "cavium,octeon-3860-uart","ns16550";
+                        reg = <0x11800 0x00000c00 0x0 0x400>;
+                        clock-frequency = <0>;
+                        current-speed = <115200>;
+                        reg-shift = <3>;
+                        interrupts = <0 35>;
+                };
+
+                uart2: serial@1180000000400 {
+                        compatible = "cavium,octeon-3860-uart","ns16550";
+                        reg = <0x11800 0x00000400 0x0 0x400>;
+                        clock-frequency = <0>;
+                        current-speed = <115200>;
+                        reg-shift = <3>;
+                        interrupts = <1 16>;
+                };
+
+                bootbus: bootbus@1180000000000 {
+                        compatible = "cavium,octeon-3860-bootbus";
+                        reg = <0x11800 0x00000000 0x0 0x200>;
+                        /* The chip select number and offset */
+                        #address-cells = <2>;
+                        /* The size of the chip select region */
+                        #size-cells = <1>;
+                        ranges = <0 0  0x0 0x1f400000  0xc00000>,
+                                 <1 0  0x10000 0x30000000  0>,
+                                 <2 0  0x10000 0x40000000  0>,
+                                 <3 0  0x10000 0x50000000  0>,
+                                 <4 0  0x0 0x1d020000  0x10000>,
+                                 <5 0  0x0 0x1d040000  0x10000>,
+                                 <6 0  0x0 0x1d050000  0x10000>,
+                                 <7 0  0x10000 0x90000000  0>;
+
+                        cavium,cs-config@0 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <0>;
+                                cavium,t-adr  = <20>;
+                                cavium,t-ce   = <60>;
+                                cavium,t-oe   = <60>;
+                                cavium,t-we   = <45>;
+                                cavium,t-rd-hld = <35>;
+                                cavium,t-wr-hld = <45>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <0>;
+                                cavium,t-page   = <35>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <8>;
+                        };
+                        cavium,cs-config@4 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <4>;
+                                cavium,t-adr  = <320>;
+                                cavium,t-ce   = <320>;
+                                cavium,t-oe   = <320>;
+                                cavium,t-we   = <320>;
+                                cavium,t-rd-hld = <320>;
+                                cavium,t-wr-hld = <320>;
+                                cavium,t-pause  = <320>;
+                                cavium,t-wait   = <320>;
+                                cavium,t-page   = <320>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <8>;
+                        };
+                        cavium,cs-config@5 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <5>;
+                                cavium,t-adr  = <5>;
+                                cavium,t-ce   = <300>;
+                                cavium,t-oe   = <125>;
+                                cavium,t-we   = <150>;
+                                cavium,t-rd-hld = <100>;
+                                cavium,t-wr-hld = <30>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <30>;
+                                cavium,t-page   = <320>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <16>;
+                        };
+                        cavium,cs-config@6 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <6>;
+                                cavium,t-adr  = <5>;
+                                cavium,t-ce   = <300>;
+                                cavium,t-oe   = <270>;
+                                cavium,t-we   = <150>;
+                                cavium,t-rd-hld = <100>;
+                                cavium,t-wr-hld = <70>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <0>;
+                                cavium,t-page   = <320>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,wait-mode;
+                                cavium,bus-width = <16>;
+                        };
+
+                        flash0: nor@0,0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0 0x800000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                        };
+
+                        led0: led-display@4,0 {
+                                compatible = "avago,hdsp-253x";
+                                reg = <4 0x20 0x20>, <4 0 0x20>;
+                        };
+
+                        cf0: compact-flash@5,0 {
+                                compatible = "cavium,ebt3000-compact-flash";
+                                reg = <5 0 0x10000>, <6 0 0x10000>;
+                                cavium,bus-width = <16>;
+                                cavium,true-ide;
+                                cavium,dma-engine-handle = <&dma0>;
+                        };
+                };
+
+                dma0: dma-engine@1180000000100 {
+                        compatible = "cavium,octeon-5750-bootbus-dma";
+                        reg = <0x11800 0x00000100 0x0 0x8>;
+                        interrupts = <0 63>;
+                };
+                dma1: dma-engine@1180000000108 {
+                        compatible = "cavium,octeon-5750-bootbus-dma";
+                        reg = <0x11800 0x00000108 0x0 0x8>;
+                        interrupts = <0 63>;
+                };
+
+                uctl: uctl@118006f000000 {
+                        compatible = "cavium,octeon-6335-uctl";
+                        reg = <0x11800 0x6f000000 0x0 0x100>;
+                        ranges; /* Direct mapping */
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        /* 12MHz, 24MHz and 48MHz allowed */
+                        refclk-frequency = <12000000>;
+                        /* Either "crystal" or "external" */
+                        refclk-type = "crystal";
+
+                        ehci@16f0000000000 {
+                                compatible = "cavium,octeon-6335-ehci","usb-ehci";
+                                reg = <0x16f00 0x00000000 0x0 0x100>;
+                                interrupts = <0 56>;
+                                big-endian-regs;
+                        };
+                        ohci@16f0000000400 {
+                                compatible = "cavium,octeon-6335-ohci","usb-ohci";
+                                reg = <0x16f00 0x00000400 0x0 0x100>;
+                                interrupts = <0 56>;
+                                big-endian-regs;
+                        };
+                };
+        };
+
+        aliases {
+                mix0 = &mix0;
+                mix1 = &mix1;
+                pip = &pip;
+                smi0 = &smi0;
+                smi1 = &smi1;
+                twsi0 = &twsi0;
+                twsi1 = &twsi1;
+                uart0 = &uart0;
+                uart1 = &uart1;
+                uart2 = &uart2;
+                flash0 = &flash0;
+                cf0 = &cf0;
+                uctl = &uctl;
+                led0 = &led0;
+        };
+ };
diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts
new file mode 100644
index 00000000000..1839468932b
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon_68xx.dts
@@ -0,0 +1,625 @@
+/dts-v1/;
+/*
+ * OCTEON 68XX device tree skeleton.
+ *
+ * This device tree is pruned and patched by early boot code before
+ * use.  Because of this, it contains a super-set of the available
+ * devices and properties.
+ */
+/ {
+        compatible = "cavium,octeon-6880";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&ciu2>;
+
+        soc@0 {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges; /* Direct mapping */
+
+                ciu2: interrupt-controller@1070100000000 {
+                        compatible = "cavium,octeon-6880-ciu2";
+                        interrupt-controller;
+                        /* Interrupts are specified by two parts:
+                         * 1) Controller register (0 or 7)
+                         * 2) Bit within the register (0..63)
+                         */
+                        #address-cells = <0>;
+                        #interrupt-cells = <2>;
+                        reg = <0x10701 0x00000000 0x0 0x4000000>;
+                };
+
+                gpio: gpio-controller@1070000000800 {
+                        #gpio-cells = <2>;
+                        compatible = "cavium,octeon-3860-gpio";
+                        reg = <0x10700 0x00000800 0x0 0x100>;
+                        gpio-controller;
+                        /* Interrupts are specified by two parts:
+                         * 1) GPIO pin number (0..15)
+                         * 2) Triggering (1 - edge rising
+                         *                2 - edge falling
+                         *                4 - level active high
+                         *                8 - level active low)
+                         */
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        /* The GPIO pins connect to 16 consecutive CUI bits */
+                        interrupts = <7 0>,  <7 1>,  <7 2>,  <7 3>,
+                                     <7 4>,  <7 5>,  <7 6>,  <7 7>,
+                                     <7 8>,  <7 9>,  <7 10>, <7 11>,
+                                     <7 12>, <7 13>, <7 14>, <7 15>;
+                };
+
+                smi0: mdio@1180000003800 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00003800 0x0 0x40>;
+
+                        phy0: ethernet-phy@6 {
+                                compatible = "marvell,88e1118";
+                                marvell,reg-init =
+                                        /* Fix rx and tx clock transition timing */
+                                        <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
+                                        /* Adjust LED drive. */
+                                        <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
+                                        /* irq, blink-activity, blink-link */
+                                        <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
+                                reg = <6>;
+                        };
+
+                        phy1: ethernet-phy@1 {
+                                cavium,qlm-trim = "4,sgmii";
+                                reg = <1>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy2: ethernet-phy@2 {
+                                cavium,qlm-trim = "4,sgmii";
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy3: ethernet-phy@3 {
+                                cavium,qlm-trim = "4,sgmii";
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy4: ethernet-phy@4 {
+                                cavium,qlm-trim = "4,sgmii";
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                };
+
+                smi1: mdio@1180000003880 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00003880 0x0 0x40>;
+
+                        phy41: ethernet-phy@1 {
+                                cavium,qlm-trim = "0,sgmii";
+                                reg = <1>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy42: ethernet-phy@2 {
+                                cavium,qlm-trim = "0,sgmii";
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy43: ethernet-phy@3 {
+                                cavium,qlm-trim = "0,sgmii";
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy44: ethernet-phy@4 {
+                                cavium,qlm-trim = "0,sgmii";
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                };
+
+                smi2: mdio@1180000003900 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00003900 0x0 0x40>;
+
+                        phy21: ethernet-phy@1 {
+                                cavium,qlm-trim = "2,sgmii";
+                                reg = <1>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy22: ethernet-phy@2 {
+                                cavium,qlm-trim = "2,sgmii";
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy23: ethernet-phy@3 {
+                                cavium,qlm-trim = "2,sgmii";
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy24: ethernet-phy@4 {
+                                cavium,qlm-trim = "2,sgmii";
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                };
+
+                smi3: mdio@1180000003980 {
+                        compatible = "cavium,octeon-3860-mdio";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0x00003980 0x0 0x40>;
+
+                        phy11: ethernet-phy@1 {
+                                cavium,qlm-trim = "3,sgmii";
+                                reg = <1>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy12: ethernet-phy@2 {
+                                cavium,qlm-trim = "3,sgmii";
+                                reg = <2>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy13: ethernet-phy@3 {
+                                cavium,qlm-trim = "3,sgmii";
+                                reg = <3>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                        phy14: ethernet-phy@4 {
+                                cavium,qlm-trim = "3,sgmii";
+                                reg = <4>;
+                                compatible = "marvell,88e1149r";
+                                marvell,reg-init = <3 0x10 0 0x5777>,
+                                        <3 0x11 0 0x00aa>,
+                                        <3 0x12 0 0x4105>,
+                                        <3 0x13 0 0x0a60>;
+                        };
+                };
+
+                mix0: ethernet@1070000100000 {
+                        compatible = "cavium,octeon-5750-mix";
+                        reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
+                              <0x11800 0xE0000000 0x0 0x300>, /* AGL */
+                              <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
+                              <0x11800 0xE0002000 0x0 0x8>;   /* AGL_PRT_CTL */
+                        cell-index = <0>;
+                        interrupts = <6 40>, <6 32>;
+                        local-mac-address = [ 00 00 00 00 00 00 ];
+                        phy-handle = <&phy0>;
+                };
+
+                pip: pip@11800a0000000 {
+                        compatible = "cavium,octeon-3860-pip";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x11800 0xa0000000 0x0 0x2000>;
+
+                        interface@4 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x4>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy1>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy2>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy3>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy4>;
+                                };
+                        };
+
+                        interface@3 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x3>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy11>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy12>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy13>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy14>;
+                                };
+                        };
+
+                        interface@2 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x2>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy21>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy22>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy23>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy24>;
+                                };
+                        };
+
+                        interface@1 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x1>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                };
+                        };
+
+                        interface@0 {
+                                compatible = "cavium,octeon-3860-pip-interface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x0>; /* interface */
+
+                                ethernet@0 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x0>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy41>;
+                                };
+                                ethernet@1 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x1>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy42>;
+                                };
+                                ethernet@2 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x2>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy43>;
+                                };
+                                ethernet@3 {
+                                        compatible = "cavium,octeon-3860-pip-port";
+                                        reg = <0x3>; /* Port */
+                                        local-mac-address = [ 00 00 00 00 00 00 ];
+                                        phy-handle = <&phy44>;
+                                };
+                        };
+                };
+
+                twsi0: i2c@1180000001000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "cavium,octeon-3860-twsi";
+                        reg = <0x11800 0x00001000 0x0 0x200>;
+                        interrupts = <3 32>;
+                        clock-frequency = <100000>;
+
+                        rtc@68 {
+                                compatible = "dallas,ds1337";
+                                reg = <0x68>;
+                        };
+                        tmp@4c {
+                                compatible = "ti,tmp421";
+                                reg = <0x4c>;
+                        };
+                };
+
+                twsi1: i2c@1180000001200 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "cavium,octeon-3860-twsi";
+                        reg = <0x11800 0x00001200 0x0 0x200>;
+                        interrupts = <3 33>;
+                        clock-frequency = <100000>;
+                };
+
+                uart0: serial@1180000000800 {
+                        compatible = "cavium,octeon-3860-uart","ns16550";
+                        reg = <0x11800 0x00000800 0x0 0x400>;
+                        clock-frequency = <0>;
+                        current-speed = <115200>;
+                        reg-shift = <3>;
+                        interrupts = <3 36>;
+                };
+
+                uart1: serial@1180000000c00 {
+                        compatible = "cavium,octeon-3860-uart","ns16550";
+                        reg = <0x11800 0x00000c00 0x0 0x400>;
+                        clock-frequency = <0>;
+                        current-speed = <115200>;
+                        reg-shift = <3>;
+                        interrupts = <3 37>;
+                };
+
+                bootbus: bootbus@1180000000000 {
+                        compatible = "cavium,octeon-3860-bootbus";
+                        reg = <0x11800 0x00000000 0x0 0x200>;
+                        /* The chip select number and offset */
+                        #address-cells = <2>;
+                        /* The size of the chip select region */
+                        #size-cells = <1>;
+                        ranges = <0 0  0       0x1f400000  0xc00000>,
+                                 <1 0  0x10000 0x30000000  0>,
+                                 <2 0  0x10000 0x40000000  0>,
+                                 <3 0  0x10000 0x50000000  0>,
+                                 <4 0  0       0x1d020000  0x10000>,
+                                 <5 0  0       0x1d040000  0x10000>,
+                                 <6 0  0       0x1d050000  0x10000>,
+                                 <7 0  0x10000 0x90000000  0>;
+
+                        cavium,cs-config@0 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <0>;
+                                cavium,t-adr  = <10>;
+                                cavium,t-ce   = <50>;
+                                cavium,t-oe   = <50>;
+                                cavium,t-we   = <35>;
+                                cavium,t-rd-hld = <25>;
+                                cavium,t-wr-hld = <35>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <300>;
+                                cavium,t-page   = <25>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <8>;
+                        };
+                        cavium,cs-config@4 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <4>;
+                                cavium,t-adr  = <320>;
+                                cavium,t-ce   = <320>;
+                                cavium,t-oe   = <320>;
+                                cavium,t-we   = <320>;
+                                cavium,t-rd-hld = <320>;
+                                cavium,t-wr-hld = <320>;
+                                cavium,t-pause  = <320>;
+                                cavium,t-wait   = <320>;
+                                cavium,t-page   = <320>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <8>;
+                        };
+                        cavium,cs-config@5 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <5>;
+                                cavium,t-adr  = <0>;
+                                cavium,t-ce   = <300>;
+                                cavium,t-oe   = <125>;
+                                cavium,t-we   = <150>;
+                                cavium,t-rd-hld = <100>;
+                                cavium,t-wr-hld = <300>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <300>;
+                                cavium,t-page   = <310>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,bus-width = <16>;
+                        };
+                        cavium,cs-config@6 {
+                                compatible = "cavium,octeon-3860-bootbus-config";
+                                cavium,cs-index = <6>;
+                                cavium,t-adr  = <0>;
+                                cavium,t-ce   = <30>;
+                                cavium,t-oe   = <125>;
+                                cavium,t-we   = <150>;
+                                cavium,t-rd-hld = <100>;
+                                cavium,t-wr-hld = <30>;
+                                cavium,t-pause  = <0>;
+                                cavium,t-wait   = <30>;
+                                cavium,t-page   = <310>;
+                                cavium,t-rd-dly = <0>;
+
+                                cavium,pages     = <0>;
+                                cavium,wait-mode;
+                                cavium,bus-width = <16>;
+                        };
+
+                        flash0: nor@0,0 {
+                                compatible = "cfi-flash";
+                                reg = <0 0 0x800000>;
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+
+                                partition@0 {
+                                        label = "bootloader";
+                                        reg = <0 0x200000>;
+                                        read-only;
+                                };
+                                partition@200000 {
+                                        label = "kernel";
+                                        reg = <0x200000 0x200000>;
+                                };
+                                partition@400000 {
+                                        label = "cramfs";
+                                        reg = <0x400000 0x3fe000>;
+                                };
+                                partition@7fe000 {
+                                        label = "environment";
+                                        reg = <0x7fe000 0x2000>;
+                                        read-only;
+                                };
+                        };
+
+                        led0: led-display@4,0 {
+                                compatible = "avago,hdsp-253x";
+                                reg = <4 0x20 0x20>, <4 0 0x20>;
+                        };
+
+                        compact-flash@5,0 {
+                                compatible = "cavium,ebt3000-compact-flash";
+                                reg = <5 0 0x10000>, <6 0 0x10000>;
+                                cavium,bus-width = <16>;
+                                cavium,true-ide;
+                                cavium,dma-engine-handle = <&dma0>;
+                        };
+                };
+
+                dma0: dma-engine@1180000000100 {
+                        compatible = "cavium,octeon-5750-bootbus-dma";
+                        reg = <0x11800 0x00000100 0x0 0x8>;
+                        interrupts = <0 63>;
+                };
+                dma1: dma-engine@1180000000108 {
+                        compatible = "cavium,octeon-5750-bootbus-dma";
+                        reg = <0x11800 0x00000108 0x0 0x8>;
+                        interrupts = <0 63>;
+                };
+
+                uctl: uctl@118006f000000 {
+                        compatible = "cavium,octeon-6335-uctl";
+                        reg = <0x11800 0x6f000000 0x0 0x100>;
+                        ranges; /* Direct mapping */
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        /* 12MHz, 24MHz and 48MHz allowed */
+                        refclk-frequency = <12000000>;
+                        /* Either "crystal" or "external" */
+                        refclk-type = "crystal";
+
+                        ehci@16f0000000000 {
+                                compatible = "cavium,octeon-6335-ehci","usb-ehci";
+                                reg = <0x16f00 0x00000000 0x0 0x100>;
+                                interrupts = <3 44>;
+                                big-endian-regs;
+                        };
+                        ohci@16f0000000400 {
+                                compatible = "cavium,octeon-6335-ohci","usb-ohci";
+                                reg = <0x16f00 0x00000400 0x0 0x100>;
+                                interrupts = <3 44>;
+                                big-endian-regs;
+                        };
+                };
+        };
+
+        aliases {
+                mix0 = &mix0;
+                pip = &pip;
+                smi0 = &smi0;
+                smi1 = &smi1;
+                smi2 = &smi2;
+                smi3 = &smi3;
+                twsi0 = &twsi0;
+                twsi1 = &twsi1;
+                uart0 = &uart0;
+                uart1 = &uart1;
+                uctl = &uctl;
+                led0 = &led0;
+                flash0 = &flash0;
+        };
+ };
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
index 057f0ae88c9..138b2216b4f 100644
--- a/arch/mips/cavium-octeon/serial.c
+++ b/arch/mips/cavium-octeon/serial.c
@@ -43,95 +43,67 @@ void octeon_serial_out(struct uart_port *up, int offset, int value)
         cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
 }
 
-/*
- * Allocated in .bss, so it is all zeroed.
- */
-#define OCTEON_MAX_UARTS 3
-static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1];
-static struct platform_device octeon_uart8250_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = octeon_uart8250_data,
-        },
-};
-
-static void __init octeon_uart_set_common(struct plat_serial8250_port *p)
+static int __devinit octeon_serial_probe(struct platform_device *pdev)
 {
-        p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
-        p->type = PORT_OCTEON;
-        p->iotype = UPIO_MEM;
-        p->regshift = 3;        /* I/O addresses are every 8 bytes */
+        int irq, res;
+        struct resource *res_mem;
+        struct uart_port port;
+
+        /* All adaptors have an irq.  */
+        irq = platform_get_irq(pdev, 0);
+        if (irq < 0)
+                return irq;
+
+        memset(&port, 0, sizeof(port));
+
+        port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
+        port.type = PORT_OCTEON;
+        port.iotype = UPIO_MEM;
+        port.regshift = 3;
+        port.dev = &pdev->dev;
+
         if (octeon_is_simulation())
                 /* Make simulator output fast*/
-                p->uartclk = 115200 * 16;
+                port.uartclk = 115200 * 16;
         else
-                p->uartclk = octeon_get_io_clock_rate();
-        p->serial_in = octeon_serial_in;
-        p->serial_out = octeon_serial_out;
-}
+                port.uartclk = octeon_get_io_clock_rate();
 
-static int __init octeon_serial_init(void)
-{
-        int enable_uart0;
-        int enable_uart1;
-        int enable_uart2;
-        struct plat_serial8250_port *p;
-
-#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
-        /*
-         * If we are configured to run as the second of two kernels,
-         * disable uart0 and enable uart1. Uart0 is owned by the first
-         * kernel
-         */
-        enable_uart0 = 0;
-        enable_uart1 = 1;
-#else
-        /*
-         * We are configured for the first kernel. We'll enable uart0
-         * if the bootloader told us to use 0, otherwise will enable
-         * uart 1.
-         */
-        enable_uart0 = (octeon_get_boot_uart() == 0);
-        enable_uart1 = (octeon_get_boot_uart() == 1);
-#ifdef CONFIG_KGDB
-        enable_uart1 = 1;
-#endif
-#endif
-
-        /* Right now CN52XX is the only chip with a third uart */
-        enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX);
-
-        p = octeon_uart8250_data;
-        if (enable_uart0) {
-                /* Add a ttyS device for hardware uart 0 */
-                octeon_uart_set_common(p);
-                p->membase = (void *) CVMX_MIO_UARTX_RBR(0);
-                p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1);
-                p->irq = OCTEON_IRQ_UART0;
-                p++;
-        }
+        port.serial_in = octeon_serial_in;
+        port.serial_out = octeon_serial_out;
+        port.irq = irq;
 
-        if (enable_uart1) {
-                /* Add a ttyS device for hardware uart 1 */
-                octeon_uart_set_common(p);
-                p->membase = (void *) CVMX_MIO_UARTX_RBR(1);
-                p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1);
-                p->irq = OCTEON_IRQ_UART1;
-                p++;
-        }
-        if (enable_uart2) {
-                /* Add a ttyS device for hardware uart 2 */
-                octeon_uart_set_common(p);
-                p->membase = (void *) CVMX_MIO_UART2_RBR;
-                p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1);
-                p->irq = OCTEON_IRQ_UART2;
-                p++;
+        res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res_mem == NULL) {
+                dev_err(&pdev->dev, "found no memory resource\n");
+                return -ENXIO;
         }
+        port.mapbase = res_mem->start;
+        port.membase = ioremap(res_mem->start, resource_size(res_mem));
 
-        BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]);
+        res = serial8250_register_port(&port);
 
-        return platform_device_register(&octeon_uart8250_device);
+        return res >= 0 ? 0 : res;
 }
 
-device_initcall(octeon_serial_init);
+static struct of_device_id octeon_serial_match[] = {
+        {
+                .compatible = "cavium,octeon-3860-uart",
+        },
+        {},
+};
+MODULE_DEVICE_TABLE(of, octeon_serial_match);
+
+static struct platform_driver octeon_serial_driver = {
+        .probe          = octeon_serial_probe,
+        .driver         = {
+                .owner  = THIS_MODULE,
+                .name   = "octeon_serial",
+                .of_match_table = octeon_serial_match,
+        },
+};
+
+static int __init octeon_serial_init(void)
+{
+        return platform_driver_register(&octeon_serial_driver);
+}
+late_initcall(octeon_serial_init);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 260dc247c05..919b0fb7bb1 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -21,6 +21,8 @@
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/serial_8250.h>
+#include <linux/of_fdt.h>
+#include <linux/libfdt.h>
 
 #include <asm/processor.h>
 #include <asm/reboot.h>
@@ -775,3 +777,46 @@ void prom_free_prom_memory(void)
         }
 #endif
 }
+
+int octeon_prune_device_tree(void);
+
+extern const char __dtb_octeon_3xxx_begin;
+extern const char __dtb_octeon_3xxx_end;
+extern const char __dtb_octeon_68xx_begin;
+extern const char __dtb_octeon_68xx_end;
+void __init device_tree_init(void)
+{
+        int dt_size;
+        struct boot_param_header *fdt;
+        bool do_prune;
+
+        if (octeon_bootinfo->minor_version >= 3 && octeon_bootinfo->fdt_addr) {
+                fdt = phys_to_virt(octeon_bootinfo->fdt_addr);
+                if (fdt_check_header(fdt))
+                        panic("Corrupt Device Tree passed to kernel.");
+                dt_size = be32_to_cpu(fdt->totalsize);
+                do_prune = false;
+        } else if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
+                fdt = (struct boot_param_header *)&__dtb_octeon_68xx_begin;
+                dt_size = &__dtb_octeon_68xx_end - &__dtb_octeon_68xx_begin;
+                do_prune = true;
+        } else {
+                fdt = (struct boot_param_header *)&__dtb_octeon_3xxx_begin;
+                dt_size = &__dtb_octeon_3xxx_end - &__dtb_octeon_3xxx_begin;
+                do_prune = true;
+        }
+
+        /* Copy the default tree from init memory. */
+        initial_boot_params = early_init_dt_alloc_memory_arch(dt_size, 8);
+        if (initial_boot_params == NULL)
+                panic("Could not allocate initial_boot_params\n");
+        memcpy(initial_boot_params, fdt, dt_size);
+
+        if (do_prune) {
+                octeon_prune_device_tree();
+                pr_info("Using internal Device Tree.\n");
+        } else {
+                pr_info("Using passed Device Tree.\n");
+        }
+        unflatten_device_tree();
+}
diff --git a/arch/mips/configs/ls1b_defconfig b/arch/mips/configs/ls1b_defconfig
new file mode 100644
index 00000000000..80cff8bea8e
--- /dev/null
+++ b/arch/mips/configs/ls1b_defconfig
@@ -0,0 +1,109 @@
+CONFIG_MACH_LOONGSON1=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_EXPERT=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SCSI=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=m
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_DA=y
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=8
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB_HID=m
+CONFIG_HID_GENERIC=m
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_STORAGE=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_LOONGSON1=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+# CONFIG_EARLY_PRINTK is not set
diff --git a/arch/mips/configs/nlm_xlr_defconfig b/arch/mips/configs/nlm_xlr_defconfig
index d0b857d98c9..138f698d7c0 100644
--- a/arch/mips/configs/nlm_xlr_defconfig
+++ b/arch/mips/configs/nlm_xlr_defconfig
@@ -367,6 +367,10 @@ CONFIG_SERIAL_8250_RSA=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_TIMERIOMEM=m
 CONFIG_RAW_DRIVER=m
+CONFIG_I2C=y
+CONFIG_I2C_XLR=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1374=y
 # CONFIG_HWMON is not set
 # CONFIG_VGA_CONSOLE is not set
 # CONFIG_HID_SUPPORT is not set
diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c
index e95ff3054ff..8c62316f22f 100644
--- a/arch/mips/dec/prom/memory.c
+++ b/arch/mips/dec/prom/memory.c
@@ -101,7 +101,7 @@ void __init prom_free_prom_memory(void)
          * the first page reserved for the exception handlers.
          */
 
-#if defined(CONFIG_DECLANCE) || defined(CONFIG_DECLANCE_MODULE)
+#if IS_ENABLED(CONFIG_DECLANCE)
         /*
          * Leave 128 KB reserved for Lance memory for
          * IOASIC DECstations.
diff --git a/arch/mips/include/asm/clock.h b/arch/mips/include/asm/clock.h
index 83894aa7932..c9456e7a728 100644
--- a/arch/mips/include/asm/clock.h
+++ b/arch/mips/include/asm/clock.h
@@ -50,15 +50,4 @@ void clk_recalc_rate(struct clk *);
 int clk_register(struct clk *);
 void clk_unregister(struct clk *);
 
-/* the exported API, in addition to clk_set_rate */
-/**
- * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
- * @clk: clock source
- * @rate: desired clock rate in Hz
- * @algo_id: algorithm id to be passed down to ops->set_rate
- *
- * Returns success (0) or negative errno.
- */
-int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
-
 #endif                          /* __ASM_MIPS_CLOCK_H */
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 95e40c1e8ed..f21b7c04e95 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -197,6 +197,7 @@
 #define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
 #define PRID_REV_VR4130         0x0080
 #define PRID_REV_34K_V1_0_2     0x0022
+#define PRID_REV_LOONGSON1B     0x0020
 #define PRID_REV_LOONGSON2E     0x0002
 #define PRID_REV_LOONGSON2F     0x0003
 
@@ -261,7 +262,7 @@ enum cpu_type_enum {
          */
         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
         CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
-        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC,
+        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_LOONGSON1, CPU_M14KC,
 
         /*
          * MIPS64 class processors
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index 1caa78ad06d..dde504477fa 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -393,7 +393,8 @@
 #define AR71XX_GPIO_REG_FUNC            0x28
 
 #define AR71XX_GPIO_COUNT               16
-#define AR724X_GPIO_COUNT               18
+#define AR7240_GPIO_COUNT               18
+#define AR7241_GPIO_COUNT               20
 #define AR913X_GPIO_COUNT               22
 #define AR933X_GPIO_COUNT               30
 #define AR934X_GPIO_COUNT               23
diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
index 4476fa03bf3..6ddae926bf7 100644
--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -42,7 +42,6 @@
 #define cpu_has_mips64r1        0
 #define cpu_has_mips64r2        0
 
-#define cpu_has_dsp             0
 #define cpu_has_mipsmt          0
 
 #define cpu_has_64bits          0
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 5b8d15bb5fe..e104ddb694a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
  * compile time if only one CPU support is enabled (idea stolen from
  * arm mach-types)
  */
+#define BCM6328_CPU_ID          0x6328
 #define BCM6338_CPU_ID          0x6338
 #define BCM6345_CPU_ID          0x6345
 #define BCM6348_CPU_ID          0x6348
@@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
 u16 bcm63xx_get_cpu_rev(void);
 unsigned int bcm63xx_get_cpu_freq(void);
 
+#ifdef CONFIG_BCM63XX_CPU_6328
+# ifdef bcm63xx_get_cpu_id
+#  undef bcm63xx_get_cpu_id
+#  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
+#  define BCMCPU_RUNTIME_DETECT
+# else
+#  define bcm63xx_get_cpu_id()  BCM6328_CPU_ID
+# endif
+# define BCMCPU_IS_6328()       (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
+#else
+# define BCMCPU_IS_6328()       (0)
+#endif
+
 #ifdef CONFIG_BCM63XX_CPU_6338
 # ifdef bcm63xx_get_cpu_id
 #  undef bcm63xx_get_cpu_id
@@ -102,13 +116,13 @@ enum bcm63xx_regs_set {
         RSET_UART1,
         RSET_GPIO,
         RSET_SPI,
-        RSET_SPI2,
         RSET_UDC0,
         RSET_OHCI0,
         RSET_OHCI_PRIV,
         RSET_USBH_PRIV,
         RSET_MPI,
         RSET_PCMCIA,
+        RSET_PCIE,
         RSET_DSL,
         RSET_ENET0,
         RSET_ENET1,
@@ -130,11 +144,17 @@ enum bcm63xx_regs_set {
         RSET_PCMDMA,
         RSET_PCMDMAC,
         RSET_PCMDMAS,
+        RSET_RNG,
+        RSET_MISC
 };
 
 #define RSET_DSL_LMEM_SIZE              (64 * 1024 * 4)
 #define RSET_DSL_SIZE                   4096
 #define RSET_WDT_SIZE                   12
+#define BCM_6338_RSET_SPI_SIZE          64
+#define BCM_6348_RSET_SPI_SIZE          64
+#define BCM_6358_RSET_SPI_SIZE          1804
+#define BCM_6368_RSET_SPI_SIZE          1804
 #define RSET_ENET_SIZE                  2048
 #define RSET_ENETDMA_SIZE               2048
 #define RSET_ENETSW_SIZE                65536
@@ -149,8 +169,53 @@ enum bcm63xx_regs_set {
 #define RSET_XTMDMA_SIZE                256
 #define RSET_XTMDMAC_SIZE(chans)        (16 * (chans))
 #define RSET_XTMDMAS_SIZE(chans)        (16 * (chans))
+#define RSET_RNG_SIZE                   20
 
 /*
+ * 6328 register sets base address
+ */
+#define BCM_6328_DSL_LMEM_BASE          (0xdeadbeef)
+#define BCM_6328_PERF_BASE              (0xb0000000)
+#define BCM_6328_TIMER_BASE             (0xb0000040)
+#define BCM_6328_WDT_BASE               (0xb000005c)
+#define BCM_6328_UART0_BASE             (0xb0000100)
+#define BCM_6328_UART1_BASE             (0xb0000120)
+#define BCM_6328_GPIO_BASE              (0xb0000080)
+#define BCM_6328_SPI_BASE               (0xdeadbeef)
+#define BCM_6328_UDC0_BASE              (0xdeadbeef)
+#define BCM_6328_USBDMA_BASE            (0xdeadbeef)
+#define BCM_6328_OHCI0_BASE             (0xdeadbeef)
+#define BCM_6328_OHCI_PRIV_BASE         (0xdeadbeef)
+#define BCM_6328_USBH_PRIV_BASE         (0xdeadbeef)
+#define BCM_6328_MPI_BASE               (0xdeadbeef)
+#define BCM_6328_PCMCIA_BASE            (0xdeadbeef)
+#define BCM_6328_PCIE_BASE              (0xb0e40000)
+#define BCM_6328_SDRAM_REGS_BASE        (0xdeadbeef)
+#define BCM_6328_DSL_BASE               (0xb0001900)
+#define BCM_6328_UBUS_BASE              (0xdeadbeef)
+#define BCM_6328_ENET0_BASE             (0xdeadbeef)
+#define BCM_6328_ENET1_BASE             (0xdeadbeef)
+#define BCM_6328_ENETDMA_BASE           (0xb000d800)
+#define BCM_6328_ENETDMAC_BASE          (0xb000da00)
+#define BCM_6328_ENETDMAS_BASE          (0xb000dc00)
+#define BCM_6328_ENETSW_BASE            (0xb0e00000)
+#define BCM_6328_EHCI0_BASE             (0x10002500)
+#define BCM_6328_SDRAM_BASE             (0xdeadbeef)
+#define BCM_6328_MEMC_BASE              (0xdeadbeef)
+#define BCM_6328_DDR_BASE               (0xb0003000)
+#define BCM_6328_M2M_BASE               (0xdeadbeef)
+#define BCM_6328_ATM_BASE               (0xdeadbeef)
+#define BCM_6328_XTM_BASE               (0xdeadbeef)
+#define BCM_6328_XTMDMA_BASE            (0xb000b800)
+#define BCM_6328_XTMDMAC_BASE           (0xdeadbeef)
+#define BCM_6328_XTMDMAS_BASE           (0xdeadbeef)
+#define BCM_6328_PCM_BASE               (0xb000a800)
+#define BCM_6328_PCMDMA_BASE            (0xdeadbeef)
+#define BCM_6328_PCMDMAC_BASE           (0xdeadbeef)
+#define BCM_6328_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_6328_RNG_BASE               (0xdeadbeef)
+#define BCM_6328_MISC_BASE              (0xb0001800)
+/*
  * 6338 register sets base address
  */
 #define BCM_6338_DSL_LMEM_BASE          (0xfff00000)
@@ -162,7 +227,6 @@ enum bcm63xx_regs_set {
 #define BCM_6338_UART1_BASE             (0xdeadbeef)
 #define BCM_6338_GPIO_BASE              (0xfffe0400)
 #define BCM_6338_SPI_BASE               (0xfffe0c00)
-#define BCM_6338_SPI2_BASE              (0xdeadbeef)
 #define BCM_6338_UDC0_BASE              (0xdeadbeef)
 #define BCM_6338_USBDMA_BASE            (0xfffe2400)
 #define BCM_6338_OHCI0_BASE             (0xdeadbeef)
@@ -170,6 +234,7 @@ enum bcm63xx_regs_set {
 #define BCM_6338_USBH_PRIV_BASE         (0xdeadbeef)
 #define BCM_6338_MPI_BASE               (0xfffe3160)
 #define BCM_6338_PCMCIA_BASE            (0xdeadbeef)
+#define BCM_6338_PCIE_BASE              (0xdeadbeef)
 #define BCM_6338_SDRAM_REGS_BASE        (0xfffe3100)
 #define BCM_6338_DSL_BASE               (0xfffe1000)
 #define BCM_6338_UBUS_BASE              (0xdeadbeef)
@@ -193,6 +258,8 @@ enum bcm63xx_regs_set {
 #define BCM_6338_PCMDMA_BASE            (0xdeadbeef)
 #define BCM_6338_PCMDMAC_BASE           (0xdeadbeef)
 #define BCM_6338_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_6338_RNG_BASE               (0xdeadbeef)
+#define BCM_6338_MISC_BASE              (0xdeadbeef)
 
 /*
  * 6345 register sets base address
@@ -206,7 +273,6 @@ enum bcm63xx_regs_set {
 #define BCM_6345_UART1_BASE             (0xdeadbeef)
 #define BCM_6345_GPIO_BASE              (0xfffe0400)
 #define BCM_6345_SPI_BASE               (0xdeadbeef)
-#define BCM_6345_SPI2_BASE              (0xdeadbeef)
 #define BCM_6345_UDC0_BASE              (0xdeadbeef)
 #define BCM_6345_USBDMA_BASE            (0xfffe2800)
 #define BCM_6345_ENET0_BASE             (0xfffe1800)
@@ -216,6 +282,7 @@ enum bcm63xx_regs_set {
 #define BCM_6345_ENETSW_BASE            (0xdeadbeef)
 #define BCM_6345_PCMCIA_BASE            (0xfffe2028)
 #define BCM_6345_MPI_BASE               (0xfffe2000)
+#define BCM_6345_PCIE_BASE              (0xdeadbeef)
 #define BCM_6345_OHCI0_BASE             (0xfffe2100)
 #define BCM_6345_OHCI_PRIV_BASE         (0xfffe2200)
 #define BCM_6345_USBH_PRIV_BASE         (0xdeadbeef)
@@ -237,6 +304,8 @@ enum bcm63xx_regs_set {
 #define BCM_6345_PCMDMA_BASE            (0xdeadbeef)
 #define BCM_6345_PCMDMAC_BASE           (0xdeadbeef)
 #define BCM_6345_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_6345_RNG_BASE               (0xdeadbeef)
+#define BCM_6345_MISC_BASE              (0xdeadbeef)
 
 /*
  * 6348 register sets base address
@@ -249,13 +318,13 @@ enum bcm63xx_regs_set {
 #define BCM_6348_UART1_BASE             (0xdeadbeef)
 #define BCM_6348_GPIO_BASE              (0xfffe0400)
 #define BCM_6348_SPI_BASE               (0xfffe0c00)
-#define BCM_6348_SPI2_BASE              (0xdeadbeef)
 #define BCM_6348_UDC0_BASE              (0xfffe1000)
 #define BCM_6348_OHCI0_BASE             (0xfffe1b00)
 #define BCM_6348_OHCI_PRIV_BASE         (0xfffe1c00)
 #define BCM_6348_USBH_PRIV_BASE         (0xdeadbeef)
 #define BCM_6348_MPI_BASE               (0xfffe2000)
 #define BCM_6348_PCMCIA_BASE            (0xfffe2054)
+#define BCM_6348_PCIE_BASE              (0xdeadbeef)
 #define BCM_6348_SDRAM_REGS_BASE        (0xfffe2300)
 #define BCM_6348_M2M_BASE               (0xfffe2800)
 #define BCM_6348_DSL_BASE               (0xfffe3000)
@@ -278,6 +347,8 @@ enum bcm63xx_regs_set {
 #define BCM_6348_PCMDMA_BASE            (0xdeadbeef)
 #define BCM_6348_PCMDMAC_BASE           (0xdeadbeef)
 #define BCM_6348_PCMDMAS_BASE           (0xdeadbeef)
+#define BCM_6348_RNG_BASE               (0xdeadbeef)
+#define BCM_6348_MISC_BASE              (0xdeadbeef)
 
 /*
  * 6358 register sets base address
@@ -289,14 +360,14 @@ enum bcm63xx_regs_set {
 #define BCM_6358_UART0_BASE             (0xfffe0100)
 #define BCM_6358_UART1_BASE             (0xfffe0120)
 #define BCM_6358_GPIO_BASE              (0xfffe0080)
-#define BCM_6358_SPI_BASE               (0xdeadbeef)
-#define BCM_6358_SPI2_BASE              (0xfffe0800)
+#define BCM_6358_SPI_BASE               (0xfffe0800)
 #define BCM_6358_UDC0_BASE              (0xfffe0800)
 #define BCM_6358_OHCI0_BASE             (0xfffe1400)
 #define BCM_6358_OHCI_PRIV_BASE         (0xdeadbeef)
 #define BCM_6358_USBH_PRIV_BASE         (0xfffe1500)
 #define BCM_6358_MPI_BASE               (0xfffe1000)
 #define BCM_6358_PCMCIA_BASE            (0xfffe1054)
+#define BCM_6358_PCIE_BASE              (0xdeadbeef)
 #define BCM_6358_SDRAM_REGS_BASE        (0xfffe2300)
 #define BCM_6358_M2M_BASE               (0xdeadbeef)
 #define BCM_6358_DSL_BASE               (0xfffe3000)
@@ -319,6 +390,8 @@ enum bcm63xx_regs_set {
 #define BCM_6358_PCMDMA_BASE            (0xfffe1800)
 #define BCM_6358_PCMDMAC_BASE           (0xfffe1900)
 #define BCM_6358_PCMDMAS_BASE           (0xfffe1a00)
+#define BCM_6358_RNG_BASE               (0xdeadbeef)
+#define BCM_6358_MISC_BASE              (0xdeadbeef)
 
 
 /*
@@ -331,14 +404,14 @@ enum bcm63xx_regs_set {
 #define BCM_6368_UART0_BASE             (0xb0000100)
 #define BCM_6368_UART1_BASE             (0xb0000120)
 #define BCM_6368_GPIO_BASE              (0xb0000080)
-#define BCM_6368_SPI_BASE               (0xdeadbeef)
-#define BCM_6368_SPI2_BASE              (0xb0000800)
+#define BCM_6368_SPI_BASE               (0xb0000800)
 #define BCM_6368_UDC0_BASE              (0xdeadbeef)
 #define BCM_6368_OHCI0_BASE             (0xb0001600)
 #define BCM_6368_OHCI_PRIV_BASE         (0xdeadbeef)
 #define BCM_6368_USBH_PRIV_BASE         (0xb0001700)
 #define BCM_6368_MPI_BASE               (0xb0001000)
 #define BCM_6368_PCMCIA_BASE            (0xb0001054)
+#define BCM_6368_PCIE_BASE              (0xdeadbeef)
 #define BCM_6368_SDRAM_REGS_BASE        (0xdeadbeef)
 #define BCM_6368_M2M_BASE               (0xdeadbeef)
 #define BCM_6368_DSL_BASE               (0xdeadbeef)
@@ -361,6 +434,8 @@ enum bcm63xx_regs_set {
 #define BCM_6368_PCMDMA_BASE            (0xb0005800)
 #define BCM_6368_PCMDMAC_BASE           (0xb0005a00)
 #define BCM_6368_PCMDMAS_BASE           (0xb0005c00)
+#define BCM_6368_RNG_BASE               (0xb0004180)
+#define BCM_6368_MISC_BASE              (0xdeadbeef)
 
 
 extern const unsigned long *bcm63xx_regs_base;
@@ -379,13 +454,13 @@ extern const unsigned long *bcm63xx_regs_base;
         __GEN_RSET_BASE(__cpu, UART1)                                   \
         __GEN_RSET_BASE(__cpu, GPIO)                                    \
         __GEN_RSET_BASE(__cpu, SPI)                                     \
-        __GEN_RSET_BASE(__cpu, SPI2)                                    \
         __GEN_RSET_BASE(__cpu, UDC0)                                    \
         __GEN_RSET_BASE(__cpu, OHCI0)                                   \
         __GEN_RSET_BASE(__cpu, OHCI_PRIV)                               \
         __GEN_RSET_BASE(__cpu, USBH_PRIV)                               \
         __GEN_RSET_BASE(__cpu, MPI)                                     \
         __GEN_RSET_BASE(__cpu, PCMCIA)                                  \
+        __GEN_RSET_BASE(__cpu, PCIE)                                    \
         __GEN_RSET_BASE(__cpu, DSL)                                     \
         __GEN_RSET_BASE(__cpu, ENET0)                                   \
         __GEN_RSET_BASE(__cpu, ENET1)                                   \
@@ -407,6 +482,8 @@ extern const unsigned long *bcm63xx_regs_base;
         __GEN_RSET_BASE(__cpu, PCMDMA)                                  \
         __GEN_RSET_BASE(__cpu, PCMDMAC)                                 \
         __GEN_RSET_BASE(__cpu, PCMDMAS)                                 \
+        __GEN_RSET_BASE(__cpu, RNG)                                     \
+        __GEN_RSET_BASE(__cpu, MISC)                                    \
         }
 
 #define __GEN_CPU_REGS_TABLE(__cpu)                                     \
@@ -418,13 +495,13 @@ extern const unsigned long *bcm63xx_regs_base;
         [RSET_UART1]            = BCM_## __cpu ##_UART1_BASE,           \
         [RSET_GPIO]             = BCM_## __cpu ##_GPIO_BASE,            \
         [RSET_SPI]              = BCM_## __cpu ##_SPI_BASE,             \
-        [RSET_SPI2]             = BCM_## __cpu ##_SPI2_BASE,            \
         [RSET_UDC0]             = BCM_## __cpu ##_UDC0_BASE,            \
         [RSET_OHCI0]            = BCM_## __cpu ##_OHCI0_BASE,           \
         [RSET_OHCI_PRIV]        = BCM_## __cpu ##_OHCI_PRIV_BASE,       \
         [RSET_USBH_PRIV]        = BCM_## __cpu ##_USBH_PRIV_BASE,       \
         [RSET_MPI]              = BCM_## __cpu ##_MPI_BASE,             \
         [RSET_PCMCIA]           = BCM_## __cpu ##_PCMCIA_BASE,          \
+        [RSET_PCIE]             = BCM_## __cpu ##_PCIE_BASE,            \
         [RSET_DSL]              = BCM_## __cpu ##_DSL_BASE,             \
         [RSET_ENET0]            = BCM_## __cpu ##_ENET0_BASE,           \
         [RSET_ENET1]            = BCM_## __cpu ##_ENET1_BASE,           \
@@ -446,6 +523,8 @@ extern const unsigned long *bcm63xx_regs_base;
         [RSET_PCMDMA]           = BCM_## __cpu ##_PCMDMA_BASE,          \
         [RSET_PCMDMAC]          = BCM_## __cpu ##_PCMDMAC_BASE,         \
         [RSET_PCMDMAS]          = BCM_## __cpu ##_PCMDMAS_BASE,         \
+        [RSET_RNG]              = BCM_## __cpu ##_RNG_BASE,             \
+        [RSET_MISC]             = BCM_## __cpu ##_MISC_BASE,            \
 
 
 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
@@ -453,6 +532,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 #ifdef BCMCPU_RUNTIME_DETECT
         return bcm63xx_regs_base[set];
 #else
+#ifdef CONFIG_BCM63XX_CPU_6328
+        __GEN_RSET(6328)
+#endif
 #ifdef CONFIG_BCM63XX_CPU_6338
         __GEN_RSET(6338)
 #endif
@@ -478,6 +560,7 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
  */
 enum bcm63xx_irq {
         IRQ_TIMER = 0,
+        IRQ_SPI,
         IRQ_UART0,
         IRQ_UART1,
         IRQ_DSL,
@@ -506,9 +589,51 @@ enum bcm63xx_irq {
 };
 
 /*
+ * 6328 irqs
+ */
+#define BCM_6328_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
+
+#define BCM_6328_TIMER_IRQ              (IRQ_INTERNAL_BASE + 31)
+#define BCM_6328_SPI_IRQ                0
+#define BCM_6328_UART0_IRQ              (IRQ_INTERNAL_BASE + 28)
+#define BCM_6328_UART1_IRQ              (BCM_6328_HIGH_IRQ_BASE + 7)
+#define BCM_6328_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
+#define BCM_6328_UDC0_IRQ               0
+#define BCM_6328_ENET0_IRQ              0
+#define BCM_6328_ENET1_IRQ              0
+#define BCM_6328_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
+#define BCM_6328_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 9)
+#define BCM_6328_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
+#define BCM_6328_PCMCIA_IRQ             0
+#define BCM_6328_ENET0_RXDMA_IRQ        0
+#define BCM_6328_ENET0_TXDMA_IRQ        0
+#define BCM_6328_ENET1_RXDMA_IRQ        0
+#define BCM_6328_ENET1_TXDMA_IRQ        0
+#define BCM_6328_PCI_IRQ                (IRQ_INTERNAL_BASE + 23)
+#define BCM_6328_ATM_IRQ                0
+#define BCM_6328_ENETSW_RXDMA0_IRQ      (BCM_6328_HIGH_IRQ_BASE + 0)
+#define BCM_6328_ENETSW_RXDMA1_IRQ      (BCM_6328_HIGH_IRQ_BASE + 1)
+#define BCM_6328_ENETSW_RXDMA2_IRQ      (BCM_6328_HIGH_IRQ_BASE + 2)
+#define BCM_6328_ENETSW_RXDMA3_IRQ      (BCM_6328_HIGH_IRQ_BASE + 3)
+#define BCM_6328_ENETSW_TXDMA0_IRQ      (BCM_6328_HIGH_IRQ_BASE + 4)
+#define BCM_6328_ENETSW_TXDMA1_IRQ      (BCM_6328_HIGH_IRQ_BASE + 5)
+#define BCM_6328_ENETSW_TXDMA2_IRQ      (BCM_6328_HIGH_IRQ_BASE + 6)
+#define BCM_6328_ENETSW_TXDMA3_IRQ      (BCM_6328_HIGH_IRQ_BASE + 7)
+#define BCM_6328_XTM_IRQ                (BCM_6328_HIGH_IRQ_BASE + 31)
+#define BCM_6328_XTM_DMA0_IRQ           (BCM_6328_HIGH_IRQ_BASE + 11)
+
+#define BCM_6328_PCM_DMA0_IRQ           (IRQ_INTERNAL_BASE + 2)
+#define BCM_6328_PCM_DMA1_IRQ           (IRQ_INTERNAL_BASE + 3)
+#define BCM_6328_EXT_IRQ0               (IRQ_INTERNAL_BASE + 24)
+#define BCM_6328_EXT_IRQ1               (IRQ_INTERNAL_BASE + 25)
+#define BCM_6328_EXT_IRQ2               (IRQ_INTERNAL_BASE + 26)
+#define BCM_6328_EXT_IRQ3               (IRQ_INTERNAL_BASE + 27)
+
+/*
  * 6338 irqs
  */
 #define BCM_6338_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6338_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 #define BCM_6338_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 #define BCM_6338_UART1_IRQ              0
 #define BCM_6338_DSL_IRQ                (IRQ_INTERNAL_BASE + 5)
@@ -539,6 +664,7 @@ enum bcm63xx_irq {
  * 6345 irqs
  */
 #define BCM_6345_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6345_SPI_IRQ                0
 #define BCM_6345_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 #define BCM_6345_UART1_IRQ              0
 #define BCM_6345_DSL_IRQ                (IRQ_INTERNAL_BASE + 3)
@@ -569,6 +695,7 @@ enum bcm63xx_irq {
  * 6348 irqs
  */
 #define BCM_6348_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6348_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 #define BCM_6348_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 #define BCM_6348_UART1_IRQ              0
 #define BCM_6348_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
@@ -599,6 +726,7 @@ enum bcm63xx_irq {
  * 6358 irqs
  */
 #define BCM_6358_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6358_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 #define BCM_6358_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 #define BCM_6358_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
 #define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
@@ -638,6 +766,7 @@ enum bcm63xx_irq {
 #define BCM_6368_HIGH_IRQ_BASE          (IRQ_INTERNAL_BASE + 32)
 
 #define BCM_6368_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
+#define BCM_6368_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 #define BCM_6368_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 #define BCM_6368_UART1_IRQ              (IRQ_INTERNAL_BASE + 3)
 #define BCM_6368_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
@@ -677,6 +806,7 @@ extern const int *bcm63xx_irqs;
 
 #define __GEN_CPU_IRQ_TABLE(__cpu)                                      \
         [IRQ_TIMER]             = BCM_## __cpu ##_TIMER_IRQ,            \
+        [IRQ_SPI]               = BCM_## __cpu ##_SPI_IRQ,              \
         [IRQ_UART0]             = BCM_## __cpu ##_UART0_IRQ,            \
         [IRQ_UART1]             = BCM_## __cpu ##_UART1_IRQ,            \
         [IRQ_DSL]               = BCM_## __cpu ##_DSL_IRQ,              \
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
new file mode 100644
index 00000000000..354b8481ec4
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
@@ -0,0 +1,12 @@
+#ifndef __BCM63XX_FLASH_H
+#define __BCM63XX_FLASH_H
+
+enum {
+        BCM63XX_FLASH_TYPE_PARALLEL,
+        BCM63XX_FLASH_TYPE_SERIAL,
+        BCM63XX_FLASH_TYPE_NAND,
+};
+
+int __init bcm63xx_flash_register(void);
+
+#endif /* __BCM63XX_FLASH_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
new file mode 100644
index 00000000000..c9bae136260
--- /dev/null
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
@@ -0,0 +1,91 @@
+#ifndef BCM63XX_DEV_SPI_H
+#define BCM63XX_DEV_SPI_H
+
+#include <linux/types.h>
+#include <bcm63xx_io.h>
+#include <bcm63xx_regs.h>
+
+int __init bcm63xx_spi_register(void);
+
+struct bcm63xx_spi_pdata {
+        unsigned int    fifo_size;
+        unsigned int    msg_type_shift;
+        unsigned int    msg_ctl_width;
+        int             bus_num;
+        int             num_chipselect;
+        u32             speed_hz;
+};
+
+enum bcm63xx_regs_spi {
+        SPI_CMD,
+        SPI_INT_STATUS,
+        SPI_INT_MASK_ST,
+        SPI_INT_MASK,
+        SPI_ST,
+        SPI_CLK_CFG,
+        SPI_FILL_BYTE,
+        SPI_MSG_TAIL,
+        SPI_RX_TAIL,
+        SPI_MSG_CTL,
+        SPI_MSG_DATA,
+        SPI_RX_DATA,
+};
+
+#define __GEN_SPI_RSET_BASE(__cpu, __rset)                              \
+        case SPI_## __rset:                                             \
+                return SPI_## __cpu ##_## __rset;
+
+#define __GEN_SPI_RSET(__cpu)                                           \
+        switch (reg) {                                                  \
+        __GEN_SPI_RSET_BASE(__cpu, CMD)                                 \
+        __GEN_SPI_RSET_BASE(__cpu, INT_STATUS)                          \
+        __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST)                         \
+        __GEN_SPI_RSET_BASE(__cpu, INT_MASK)                            \
+        __GEN_SPI_RSET_BASE(__cpu, ST)                                  \
+        __GEN_SPI_RSET_BASE(__cpu, CLK_CFG)                             \
+        __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE)                           \
+        __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL)                            \
+        __GEN_SPI_RSET_BASE(__cpu, RX_TAIL)                             \
+        __GEN_SPI_RSET_BASE(__cpu, MSG_CTL)                             \
+        __GEN_SPI_RSET_BASE(__cpu, MSG_DATA)                            \
+        __GEN_SPI_RSET_BASE(__cpu, RX_DATA)                             \
+        }
+
+#define __GEN_SPI_REGS_TABLE(__cpu)                                     \
+        [SPI_CMD]               = SPI_## __cpu ##_CMD,                  \
+        [SPI_INT_STATUS]        = SPI_## __cpu ##_INT_STATUS,           \
+        [SPI_INT_MASK_ST]       = SPI_## __cpu ##_INT_MASK_ST,          \
+        [SPI_INT_MASK]          = SPI_## __cpu ##_INT_MASK,             \
+        [SPI_ST]                = SPI_## __cpu ##_ST,                   \
+        [SPI_CLK_CFG]           = SPI_## __cpu ##_CLK_CFG,              \
+        [SPI_FILL_BYTE]         = SPI_## __cpu ##_FILL_BYTE,            \
+        [SPI_MSG_TAIL]          = SPI_## __cpu ##_MSG_TAIL,             \
+        [SPI_RX_TAIL]           = SPI_## __cpu ##_RX_TAIL,              \
+        [SPI_MSG_CTL]           = SPI_## __cpu ##_MSG_CTL,              \
+        [SPI_MSG_DATA]          = SPI_## __cpu ##_MSG_DATA,             \
+        [SPI_RX_DATA]           = SPI_## __cpu ##_RX_DATA,
+
+static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
+{
+#ifdef BCMCPU_RUNTIME_DETECT
+        extern const unsigned long *bcm63xx_regs_spi;
+
+        return bcm63xx_regs_spi[reg];
+#else
+#ifdef CONFIG_BCM63XX_CPU_6338
+        __GEN_SPI_RSET(6338)
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6348
+        __GEN_SPI_RSET(6348)
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6358
+        __GEN_SPI_RSET(6358)
+#endif
+#ifdef CONFIG_BCM63XX_CPU_6368
+        __GEN_SPI_RSET(6368)
+#endif
+#endif
+        return 0;
+}
+
+#endif /* BCM63XX_DEV_SPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 1d7dd96aa46..0a9891f7580 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
 static inline unsigned long bcm63xx_gpio_count(void)
 {
         switch (bcm63xx_get_cpu_id()) {
+        case BCM6328_CPU_ID:
+                return 32;
         case BCM6358_CPU_ID:
                 return 40;
         case BCM6338_CPU_ID:
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 72477a6441d..9203d90e610 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -40,6 +40,10 @@
 #define BCM_CB_MEM_END_PA               (BCM_CB_MEM_BASE_PA +           \
                                         BCM_CB_MEM_SIZE - 1)
 
+#define BCM_PCIE_MEM_BASE_PA            0x10f00000
+#define BCM_PCIE_MEM_SIZE               (16 * 1024 * 1024)
+#define BCM_PCIE_MEM_END_PA             (BCM_PCIE_MEM_BASE_PA +         \
+                                        BCM_PCIE_MEM_SIZE - 1)
 
 /*
  * Internal registers are accessed through KSEG3
@@ -85,11 +89,15 @@
 #define bcm_mpi_writel(v, o)    bcm_rset_writel(RSET_MPI, (v), (o))
 #define bcm_pcmcia_readl(o)     bcm_rset_readl(RSET_PCMCIA, (o))
 #define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
+#define bcm_pcie_readl(o)       bcm_rset_readl(RSET_PCIE, (o))
+#define bcm_pcie_writel(v, o)   bcm_rset_writel(RSET_PCIE, (v), (o))
 #define bcm_sdram_readl(o)      bcm_rset_readl(RSET_SDRAM, (o))
 #define bcm_sdram_writel(v, o)  bcm_rset_writel(RSET_SDRAM, (v), (o))
 #define bcm_memc_readl(o)       bcm_rset_readl(RSET_MEMC, (o))
 #define bcm_memc_writel(v, o)   bcm_rset_writel(RSET_MEMC, (v), (o))
 #define bcm_ddr_readl(o)        bcm_rset_readl(RSET_DDR, (o))
 #define bcm_ddr_writel(v, o)    bcm_rset_writel(RSET_DDR, (v), (o))
+#define bcm_misc_readl(o)       bcm_rset_readl(RSET_MISC, (o))
+#define bcm_misc_writel(v, o)   bcm_rset_writel(RSET_MISC, (v), (o))
 
 #endif /* ! BCM63XX_IO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index fdcd78ca1b0..61f2a2a5099 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,30 @@
 /* Clock Control register */
 #define PERF_CKCTL_REG                  0x4
 
+#define CKCTL_6328_PHYMIPS_EN           (1 << 0)
+#define CKCTL_6328_ADSL_QPROC_EN        (1 << 1)
+#define CKCTL_6328_ADSL_AFE_EN          (1 << 2)
+#define CKCTL_6328_ADSL_EN              (1 << 3)
+#define CKCTL_6328_MIPS_EN              (1 << 4)
+#define CKCTL_6328_SAR_EN               (1 << 5)
+#define CKCTL_6328_PCM_EN               (1 << 6)
+#define CKCTL_6328_USBD_EN              (1 << 7)
+#define CKCTL_6328_USBH_EN              (1 << 8)
+#define CKCTL_6328_HSSPI_EN             (1 << 9)
+#define CKCTL_6328_PCIE_EN              (1 << 10)
+#define CKCTL_6328_ROBOSW_EN            (1 << 11)
+
+#define CKCTL_6328_ALL_SAFE_EN          (CKCTL_6328_PHYMIPS_EN |        \
+                                        CKCTL_6328_ADSL_QPROC_EN |      \
+                                        CKCTL_6328_ADSL_AFE_EN |        \
+                                        CKCTL_6328_ADSL_EN |            \
+                                        CKCTL_6328_SAR_EN  |            \
+                                        CKCTL_6328_PCM_EN  |            \
+                                        CKCTL_6328_USBD_EN |            \
+                                        CKCTL_6328_USBH_EN |            \
+                                        CKCTL_6328_ROBOSW_EN |          \
+                                        CKCTL_6328_PCIE_EN)
+
 #define CKCTL_6338_ADSLPHY_EN           (1 << 0)
 #define CKCTL_6338_MPI_EN               (1 << 1)
 #define CKCTL_6338_DRAM_EN              (1 << 2)
@@ -90,35 +114,36 @@
 #define CKCTL_6368_PHYMIPS_EN           (1 << 6)
 #define CKCTL_6368_SWPKT_USB_EN         (1 << 7)
 #define CKCTL_6368_SWPKT_SAR_EN         (1 << 8)
-#define CKCTL_6368_SPI_CLK_EN           (1 << 9)
-#define CKCTL_6368_USBD_CLK_EN          (1 << 10)
-#define CKCTL_6368_SAR_CLK_EN           (1 << 11)
-#define CKCTL_6368_ROBOSW_CLK_EN        (1 << 12)
-#define CKCTL_6368_UTOPIA_CLK_EN        (1 << 13)
-#define CKCTL_6368_PCM_CLK_EN           (1 << 14)
-#define CKCTL_6368_USBH_CLK_EN          (1 << 15)
+#define CKCTL_6368_SPI_EN               (1 << 9)
+#define CKCTL_6368_USBD_EN              (1 << 10)
+#define CKCTL_6368_SAR_EN               (1 << 11)
+#define CKCTL_6368_ROBOSW_EN            (1 << 12)
+#define CKCTL_6368_UTOPIA_EN            (1 << 13)
+#define CKCTL_6368_PCM_EN               (1 << 14)
+#define CKCTL_6368_USBH_EN              (1 << 15)
 #define CKCTL_6368_DISABLE_GLESS_EN     (1 << 16)
-#define CKCTL_6368_NAND_CLK_EN          (1 << 17)
-#define CKCTL_6368_IPSEC_CLK_EN         (1 << 18)
+#define CKCTL_6368_NAND_EN              (1 << 17)
+#define CKCTL_6368_IPSEC_EN             (1 << 18)
 
 #define CKCTL_6368_ALL_SAFE_EN          (CKCTL_6368_SWPKT_USB_EN |      \
                                         CKCTL_6368_SWPKT_SAR_EN |       \
-                                        CKCTL_6368_SPI_CLK_EN |         \
-                                        CKCTL_6368_USBD_CLK_EN |        \
-                                        CKCTL_6368_SAR_CLK_EN |         \
-                                        CKCTL_6368_ROBOSW_CLK_EN |      \
-                                        CKCTL_6368_UTOPIA_CLK_EN |      \
-                                        CKCTL_6368_PCM_CLK_EN |         \
-                                        CKCTL_6368_USBH_CLK_EN |        \
+                                        CKCTL_6368_SPI_EN |             \
+                                        CKCTL_6368_USBD_EN |            \
+                                        CKCTL_6368_SAR_EN |             \
+                                        CKCTL_6368_ROBOSW_EN |          \
+                                        CKCTL_6368_UTOPIA_EN |          \
+                                        CKCTL_6368_PCM_EN |             \
+                                        CKCTL_6368_USBH_EN |            \
                                         CKCTL_6368_DISABLE_GLESS_EN |   \
-                                        CKCTL_6368_NAND_CLK_EN |        \
-                                        CKCTL_6368_IPSEC_CLK_EN)
+                                        CKCTL_6368_NAND_EN |            \
+                                        CKCTL_6368_IPSEC_EN)
 
 /* System PLL Control register  */
 #define PERF_SYS_PLL_CTL_REG            0x8
 #define SYS_PLL_SOFT_RESET              0x1
 
 /* Interrupt Mask register */
+#define PERF_IRQMASK_6328_REG           0x20
 #define PERF_IRQMASK_6338_REG           0xc
 #define PERF_IRQMASK_6345_REG           0xc
 #define PERF_IRQMASK_6348_REG           0xc
@@ -126,6 +151,7 @@
 #define PERF_IRQMASK_6368_REG           0x20
 
 /* Interrupt Status register */
+#define PERF_IRQSTAT_6328_REG           0x28
 #define PERF_IRQSTAT_6338_REG           0x10
 #define PERF_IRQSTAT_6345_REG           0x10
 #define PERF_IRQSTAT_6348_REG           0x10
@@ -133,6 +159,7 @@
 #define PERF_IRQSTAT_6368_REG           0x28
 
 /* External Interrupt Configuration register */
+#define PERF_EXTIRQ_CFG_REG_6328        0x18
 #define PERF_EXTIRQ_CFG_REG_6338        0x14
 #define PERF_EXTIRQ_CFG_REG_6348        0x14
 #define PERF_EXTIRQ_CFG_REG_6358        0x14
@@ -162,8 +189,21 @@
 
 /* Soft Reset register */
 #define PERF_SOFTRESET_REG              0x28
+#define PERF_SOFTRESET_6328_REG         0x10
 #define PERF_SOFTRESET_6368_REG         0x10
 
+#define SOFTRESET_6328_SPI_MASK         (1 << 0)
+#define SOFTRESET_6328_EPHY_MASK        (1 << 1)
+#define SOFTRESET_6328_SAR_MASK         (1 << 2)
+#define SOFTRESET_6328_ENETSW_MASK      (1 << 3)
+#define SOFTRESET_6328_USBS_MASK        (1 << 4)
+#define SOFTRESET_6328_USBH_MASK        (1 << 5)
+#define SOFTRESET_6328_PCM_MASK         (1 << 6)
+#define SOFTRESET_6328_PCIE_CORE_MASK   (1 << 7)
+#define SOFTRESET_6328_PCIE_MASK        (1 << 8)
+#define SOFTRESET_6328_PCIE_EXT_MASK    (1 << 9)
+#define SOFTRESET_6328_PCIE_HARD_MASK   (1 << 10)
+
 #define SOFTRESET_6338_SPI_MASK         (1 << 0)
 #define SOFTRESET_6338_ENET_MASK        (1 << 2)
 #define SOFTRESET_6338_USBH_MASK        (1 << 3)
@@ -307,6 +347,8 @@
 /* Watchdog reset length register */
 #define WDT_RSTLEN_REG                  0x8
 
+/* Watchdog soft reset register (BCM6328 only) */
+#define WDT_SOFTRESET_REG               0xc
 
 /*************************************************************************
  * _REG relative to RSET_UARTx
@@ -507,6 +549,15 @@
 #define GPIO_BASEMODE_6368_MASK         0x7
 /* those bits must be kept as read in gpio basemode register*/
 
+#define GPIO_STRAPBUS_REG               0x40
+#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
+#define STRAPBUS_6358_BOOT_SEL_SERIAL   (0 << 1)
+#define STRAPBUS_6368_BOOT_SEL_MASK     0x3
+#define STRAPBUS_6368_BOOT_SEL_NAND     0
+#define STRAPBUS_6368_BOOT_SEL_SERIAL   1
+#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
+
+
 /*************************************************************************
  * _REG relative to RSET_ENET
  *************************************************************************/
@@ -924,6 +975,8 @@
  * _REG relative to RSET_DDR
  *************************************************************************/
 
+#define DDR_CSEND_REG                   0x8
+
 #define DDR_DMIPSPLLCFG_REG             0x18
 #define DMIPSPLLCFG_M1_SHIFT            0
 #define DMIPSPLLCFG_M1_MASK             (0xff << DMIPSPLLCFG_M1_SHIFT)
@@ -973,4 +1026,208 @@
 #define M2M_SRCID_REG(x)                ((x) * 0x40 + 0x14)
 #define M2M_DSTID_REG(x)                ((x) * 0x40 + 0x18)
 
+/*************************************************************************
+ * _REG relative to RSET_RNG
+ *************************************************************************/
+
+#define RNG_CTRL                        0x00
+#define RNG_EN                          (1 << 0)
+
+#define RNG_STAT                        0x04
+#define RNG_AVAIL_MASK                  (0xff000000)
+
+#define RNG_DATA                        0x08
+#define RNG_THRES                       0x0c
+#define RNG_MASK                        0x10
+
+/*************************************************************************
+ * _REG relative to RSET_SPI
+ *************************************************************************/
+
+/* BCM 6338 SPI core */
+#define SPI_6338_CMD                    0x00    /* 16-bits register */
+#define SPI_6338_INT_STATUS             0x02
+#define SPI_6338_INT_MASK_ST            0x03
+#define SPI_6338_INT_MASK               0x04
+#define SPI_6338_ST                     0x05
+#define SPI_6338_CLK_CFG                0x06
+#define SPI_6338_FILL_BYTE              0x07
+#define SPI_6338_MSG_TAIL               0x09
+#define SPI_6338_RX_TAIL                0x0b
+#define SPI_6338_MSG_CTL                0x40    /* 8-bits register */
+#define SPI_6338_MSG_CTL_WIDTH          8
+#define SPI_6338_MSG_DATA               0x41
+#define SPI_6338_MSG_DATA_SIZE          0x3f
+#define SPI_6338_RX_DATA                0x80
+#define SPI_6338_RX_DATA_SIZE           0x3f
+
+/* BCM 6348 SPI core */
+#define SPI_6348_CMD                    0x00    /* 16-bits register */
+#define SPI_6348_INT_STATUS             0x02
+#define SPI_6348_INT_MASK_ST            0x03
+#define SPI_6348_INT_MASK               0x04
+#define SPI_6348_ST                     0x05
+#define SPI_6348_CLK_CFG                0x06
+#define SPI_6348_FILL_BYTE              0x07
+#define SPI_6348_MSG_TAIL               0x09
+#define SPI_6348_RX_TAIL                0x0b
+#define SPI_6348_MSG_CTL                0x40    /* 8-bits register */
+#define SPI_6348_MSG_CTL_WIDTH          8
+#define SPI_6348_MSG_DATA               0x41
+#define SPI_6348_MSG_DATA_SIZE          0x3f
+#define SPI_6348_RX_DATA                0x80
+#define SPI_6348_RX_DATA_SIZE           0x3f
+
+/* BCM 6358 SPI core */
+#define SPI_6358_MSG_CTL                0x00    /* 16-bits register */
+#define SPI_6358_MSG_CTL_WIDTH          16
+#define SPI_6358_MSG_DATA               0x02
+#define SPI_6358_MSG_DATA_SIZE          0x21e
+#define SPI_6358_RX_DATA                0x400
+#define SPI_6358_RX_DATA_SIZE           0x220
+#define SPI_6358_CMD                    0x700   /* 16-bits register */
+#define SPI_6358_INT_STATUS             0x702
+#define SPI_6358_INT_MASK_ST            0x703
+#define SPI_6358_INT_MASK               0x704
+#define SPI_6358_ST                     0x705
+#define SPI_6358_CLK_CFG                0x706
+#define SPI_6358_FILL_BYTE              0x707
+#define SPI_6358_MSG_TAIL               0x709
+#define SPI_6358_RX_TAIL                0x70B
+
+/* BCM 6358 SPI core */
+#define SPI_6368_MSG_CTL                0x00    /* 16-bits register */
+#define SPI_6368_MSG_CTL_WIDTH          16
+#define SPI_6368_MSG_DATA               0x02
+#define SPI_6368_MSG_DATA_SIZE          0x21e
+#define SPI_6368_RX_DATA                0x400
+#define SPI_6368_RX_DATA_SIZE           0x220
+#define SPI_6368_CMD                    0x700   /* 16-bits register */
+#define SPI_6368_INT_STATUS             0x702
+#define SPI_6368_INT_MASK_ST            0x703
+#define SPI_6368_INT_MASK               0x704
+#define SPI_6368_ST                     0x705
+#define SPI_6368_CLK_CFG                0x706
+#define SPI_6368_FILL_BYTE              0x707
+#define SPI_6368_MSG_TAIL               0x709
+#define SPI_6368_RX_TAIL                0x70B
+
+/* Shared SPI definitions */
+
+/* Message configuration */
+#define SPI_FD_RW                       0x00
+#define SPI_HD_W                        0x01
+#define SPI_HD_R                        0x02
+#define SPI_BYTE_CNT_SHIFT              0
+#define SPI_6338_MSG_TYPE_SHIFT         6
+#define SPI_6348_MSG_TYPE_SHIFT         6
+#define SPI_6358_MSG_TYPE_SHIFT         14
+#define SPI_6368_MSG_TYPE_SHIFT         14
+
+/* Command */
+#define SPI_CMD_NOOP                    0x00
+#define SPI_CMD_SOFT_RESET              0x01
+#define SPI_CMD_HARD_RESET              0x02
+#define SPI_CMD_START_IMMEDIATE         0x03
+#define SPI_CMD_COMMAND_SHIFT           0
+#define SPI_CMD_COMMAND_MASK            0x000f
+#define SPI_CMD_DEVICE_ID_SHIFT         4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
+#define SPI_CMD_ONE_BYTE_SHIFT          11
+#define SPI_CMD_ONE_WIRE_SHIFT          12
+#define SPI_DEV_ID_0                    0
+#define SPI_DEV_ID_1                    1
+#define SPI_DEV_ID_2                    2
+#define SPI_DEV_ID_3                    3
+
+/* Interrupt mask */
+#define SPI_INTR_CMD_DONE               0x01
+#define SPI_INTR_RX_OVERFLOW            0x02
+#define SPI_INTR_TX_UNDERFLOW           0x04
+#define SPI_INTR_TX_OVERFLOW            0x08
+#define SPI_INTR_RX_UNDERFLOW           0x10
+#define SPI_INTR_CLEAR_ALL              0x1f
+
+/* Status */
+#define SPI_RX_EMPTY                    0x02
+#define SPI_CMD_BUSY                    0x04
+#define SPI_SERIAL_BUSY                 0x08
+
+/* Clock configuration */
+#define SPI_CLK_20MHZ                   0x00
+#define SPI_CLK_0_391MHZ                0x01
+#define SPI_CLK_0_781MHZ                0x02 /* default */
+#define SPI_CLK_1_563MHZ                0x03
+#define SPI_CLK_3_125MHZ                0x04
+#define SPI_CLK_6_250MHZ                0x05
+#define SPI_CLK_12_50MHZ                0x06
+#define SPI_CLK_MASK                    0x07
+#define SPI_SSOFFTIME_MASK              0x38
+#define SPI_SSOFFTIME_SHIFT             3
+#define SPI_BYTE_SWAP                   0x80
+
+/*************************************************************************
+ * _REG relative to RSET_MISC
+ *************************************************************************/
+#define MISC_SERDES_CTRL_REG            0x0
+#define SERDES_PCIE_EN                  (1 << 0)
+#define SERDES_PCIE_EXD_EN              (1 << 15)
+
+#define MISC_STRAPBUS_6328_REG          0x240
+#define STRAPBUS_6328_FCVO_SHIFT        7
+#define STRAPBUS_6328_FCVO_MASK         (0x1f << STRAPBUS_6328_FCVO_SHIFT)
+#define STRAPBUS_6328_BOOT_SEL_SERIAL   (1 << 28)
+#define STRAPBUS_6328_BOOT_SEL_NAND     (0 << 28)
+
+/*************************************************************************
+ * _REG relative to RSET_PCIE
+ *************************************************************************/
+
+#define PCIE_CONFIG2_REG                0x408
+#define CONFIG2_BAR1_SIZE_EN            1
+#define CONFIG2_BAR1_SIZE_MASK          0xf
+
+#define PCIE_IDVAL3_REG                 0x43c
+#define IDVAL3_CLASS_CODE_MASK          0xffffff
+#define IDVAL3_SUBCLASS_SHIFT           8
+#define IDVAL3_CLASS_SHIFT              16
+
+#define PCIE_DLSTATUS_REG               0x1048
+#define DLSTATUS_PHYLINKUP              (1 << 13)
+
+#define PCIE_BRIDGE_OPT1_REG            0x2820
+#define OPT1_RD_BE_OPT_EN               (1 << 7)
+#define OPT1_RD_REPLY_BE_FIX_EN         (1 << 9)
+#define OPT1_PCIE_BRIDGE_HOLE_DET_EN    (1 << 11)
+#define OPT1_L1_INT_STATUS_MASK_POL     (1 << 12)
+
+#define PCIE_BRIDGE_OPT2_REG            0x2824
+#define OPT2_UBUS_UR_DECODE_DIS         (1 << 2)
+#define OPT2_TX_CREDIT_CHK_EN           (1 << 4)
+#define OPT2_CFG_TYPE1_BD_SEL           (1 << 7)
+#define OPT2_CFG_TYPE1_BUS_NO_SHIFT     16
+#define OPT2_CFG_TYPE1_BUS_NO_MASK      (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
+
+#define PCIE_BRIDGE_BAR0_BASEMASK_REG   0x2828
+#define PCIE_BRIDGE_BAR1_BASEMASK_REG   0x2830
+#define BASEMASK_REMAP_EN               (1 << 0)
+#define BASEMASK_SWAP_EN                (1 << 1)
+#define BASEMASK_MASK_SHIFT             4
+#define BASEMASK_MASK_MASK              (0xfff << BASEMASK_MASK_SHIFT)
+#define BASEMASK_BASE_SHIFT             20
+#define BASEMASK_BASE_MASK              (0xfff << BASEMASK_BASE_SHIFT)
+
+#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
+#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
+#define REBASE_ADDR_BASE_SHIFT          20
+#define REBASE_ADDR_BASE_MASK           (0xfff << REBASE_ADDR_BASE_SHIFT)
+
+#define PCIE_BRIDGE_RC_INT_MASK_REG     0x2854
+#define PCIE_RC_INT_A                   (1 << 0)
+#define PCIE_RC_INT_B                   (1 << 1)
+#define PCIE_RC_INT_C                   (1 << 2)
+#define PCIE_RC_INT_D                   (1 << 3)
+
+#define PCIE_DEVICE_OFFSET              0x8000
+
 #endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index ef94ba73646..30931c42379 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
                 if (offset >= 0xfff00000)
                         return 1;
                 break;
+        case BCM6328_CPU_ID:
         case BCM6368_CPU_ID:
                 if (offset >= 0xb0000000 && offset < 0xb1000000)
                         return 1;
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 5b05f186e39..c22a3078bf1 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -21,14 +21,10 @@ enum octeon_irq {
         OCTEON_IRQ_TIMER,
 /* sources in CIU_INTX_EN0 */
         OCTEON_IRQ_WORKQ0,
-        OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
-        OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
+        OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16,
         OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
         OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
         OCTEON_IRQ_MBOX1,
-        OCTEON_IRQ_UART0,
-        OCTEON_IRQ_UART1,
-        OCTEON_IRQ_UART2,
         OCTEON_IRQ_PCI_INT0,
         OCTEON_IRQ_PCI_INT1,
         OCTEON_IRQ_PCI_INT2,
@@ -38,64 +34,25 @@ enum octeon_irq {
         OCTEON_IRQ_PCI_MSI2,
         OCTEON_IRQ_PCI_MSI3,
 
-        OCTEON_IRQ_TWSI,
-        OCTEON_IRQ_TWSI2,
         OCTEON_IRQ_RML,
-        OCTEON_IRQ_TRACE0,
-        OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
-        OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
-        OCTEON_IRQ_KEY_ZERO,
         OCTEON_IRQ_TIMER0,
         OCTEON_IRQ_TIMER1,
         OCTEON_IRQ_TIMER2,
         OCTEON_IRQ_TIMER3,
         OCTEON_IRQ_USB0,
         OCTEON_IRQ_USB1,
-        OCTEON_IRQ_PCM,
-        OCTEON_IRQ_MPI,
-        OCTEON_IRQ_POWIQ,
-        OCTEON_IRQ_IPDPPTHR,
-        OCTEON_IRQ_MII0,
-        OCTEON_IRQ_MII1,
         OCTEON_IRQ_BOOTDMA,
-
-        OCTEON_IRQ_NAND,
-        OCTEON_IRQ_MIO,         /* Summary of MIO_BOOT_ERR */
-        OCTEON_IRQ_IOB,         /* Summary of IOB_INT_SUM */
-        OCTEON_IRQ_FPA,         /* Summary of FPA_INT_SUM */
-        OCTEON_IRQ_POW,         /* Summary of POW_ECC_ERR */
-        OCTEON_IRQ_L2C,         /* Summary of L2C_INT_STAT */
-        OCTEON_IRQ_IPD,         /* Summary of IPD_INT_SUM */
-        OCTEON_IRQ_PIP,         /* Summary of PIP_INT_REG */
-        OCTEON_IRQ_PKO,         /* Summary of PKO_REG_ERROR */
-        OCTEON_IRQ_ZIP,         /* Summary of ZIP_ERROR */
-        OCTEON_IRQ_TIM,         /* Summary of TIM_REG_ERROR */
-        OCTEON_IRQ_RAD,         /* Summary of RAD_REG_ERROR */
-        OCTEON_IRQ_KEY,         /* Summary of KEY_INT_SUM */
-        OCTEON_IRQ_DFA,         /* Summary of DFA */
-        OCTEON_IRQ_USBCTL,      /* Summary of USBN0_INT_SUM */
-        OCTEON_IRQ_SLI,         /* Summary of SLI_INT_SUM */
-        OCTEON_IRQ_DPI,         /* Summary of DPI_INT_SUM */
-        OCTEON_IRQ_AGX0,        /* Summary of GMX0*+PCS0_INT*_REG */
-        OCTEON_IRQ_AGL  = OCTEON_IRQ_AGX0 + 5,
-        OCTEON_IRQ_PTP,
-        OCTEON_IRQ_PEM0,
-        OCTEON_IRQ_PEM1,
-        OCTEON_IRQ_SRIO0,
-        OCTEON_IRQ_SRIO1,
-        OCTEON_IRQ_LMC0,
-        OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4,           /* Summary of DFM */
-        OCTEON_IRQ_RST,
+#ifndef CONFIG_PCI_MSI
+        OCTEON_IRQ_LAST = 127
+#endif
 };
 
 #ifdef CONFIG_PCI_MSI
-/* 152 - 407 represent the MSI interrupts 0-255 */
-#define OCTEON_IRQ_MSI_BIT0     (OCTEON_IRQ_RST + 1)
+/* 256 - 511 represent the MSI interrupts 0-255 */
+#define OCTEON_IRQ_MSI_BIT0     (256)
 
 #define OCTEON_IRQ_MSI_LAST      (OCTEON_IRQ_MSI_BIT0 + 255)
 #define OCTEON_IRQ_LAST          (OCTEON_IRQ_MSI_LAST + 1)
-#else
-#define OCTEON_IRQ_LAST         (OCTEON_IRQ_RST + 1)
 #endif
 
 #endif
diff --git a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
index bb5b9a4e29c..986982db7c3 100644
--- a/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
+++ b/arch/mips/include/asm/mach-jz4740/jz4740_nand.h
@@ -19,6 +19,8 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 
+#define JZ_NAND_NUM_BANKS 4
+
 struct jz_nand_platform_data {
         int                     num_partitions;
         struct mtd_partition    *partitions;
@@ -27,6 +29,8 @@ struct jz_nand_platform_data {
 
         unsigned int busy_gpio;
 
+        unsigned char banks[JZ_NAND_NUM_BANKS];
+
         void (*ident_callback)(struct platform_device *, struct nand_chip *,
                                 struct mtd_partition **, int *num_partitions);
 };
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index 1e29b9dd1d7..5222a007bc2 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/kconfig.h>
 
 /* loongson internal northbridge initialization */
 extern void bonito_irq_init(void);
@@ -66,7 +67,7 @@ extern int mach_i8259_irq(void);
 #include <linux/interrupt.h>
 static inline void do_perfcnt_IRQ(void)
 {
-#if defined(CONFIG_OPROFILE) || defined(CONFIG_OPROFILE_MODULE)
+#if IS_ENABLED(CONFIG_OPROFILE)
         do_IRQ(LOONGSON2_PERFCNT_IRQ);
 #endif
 }
@@ -244,7 +245,6 @@ static inline void do_perfcnt_IRQ(void)
 
 #ifdef CONFIG_CPU_SUPPORTS_CPUFREQ
 #include <linux/cpufreq.h>
-extern void loongson2_cpu_wait(void);
 extern struct cpufreq_frequency_table loongson2_clockmod_table[];
 
 /* Chip Config */
diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h
new file mode 100644
index 00000000000..da96ed42f73
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * IRQ mappings for Loongson 1
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_IRQ_H
+#define __ASM_MACH_LOONGSON1_IRQ_H
+
+/*
+ * CPU core Interrupt Numbers
+ */
+#define MIPS_CPU_IRQ_BASE               0
+#define MIPS_CPU_IRQ(x)                 (MIPS_CPU_IRQ_BASE + (x))
+
+#define SOFTINT0_IRQ                    MIPS_CPU_IRQ(0)
+#define SOFTINT1_IRQ                    MIPS_CPU_IRQ(1)
+#define INT0_IRQ                        MIPS_CPU_IRQ(2)
+#define INT1_IRQ                        MIPS_CPU_IRQ(3)
+#define INT2_IRQ                        MIPS_CPU_IRQ(4)
+#define INT3_IRQ                        MIPS_CPU_IRQ(5)
+#define INT4_IRQ                        MIPS_CPU_IRQ(6)
+#define TIMER_IRQ                       MIPS_CPU_IRQ(7)         /* cpu timer */
+
+#define MIPS_CPU_IRQS           (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
+
+/*
+ * INT0~3 Interrupt Numbers
+ */
+#define LS1X_IRQ_BASE                   MIPS_CPU_IRQS
+#define LS1X_IRQ(n, x)                  (LS1X_IRQ_BASE + (n << 5) + (x))
+
+#define LS1X_UART0_IRQ                  LS1X_IRQ(0, 2)
+#define LS1X_UART1_IRQ                  LS1X_IRQ(0, 3)
+#define LS1X_UART2_IRQ                  LS1X_IRQ(0, 4)
+#define LS1X_UART3_IRQ                  LS1X_IRQ(0, 5)
+#define LS1X_CAN0_IRQ                   LS1X_IRQ(0, 6)
+#define LS1X_CAN1_IRQ                   LS1X_IRQ(0, 7)
+#define LS1X_SPI0_IRQ                   LS1X_IRQ(0, 8)
+#define LS1X_SPI1_IRQ                   LS1X_IRQ(0, 9)
+#define LS1X_AC97_IRQ                   LS1X_IRQ(0, 10)
+#define LS1X_DMA0_IRQ                   LS1X_IRQ(0, 13)
+#define LS1X_DMA1_IRQ                   LS1X_IRQ(0, 14)
+#define LS1X_DMA2_IRQ                   LS1X_IRQ(0, 15)
+#define LS1X_PWM0_IRQ                   LS1X_IRQ(0, 17)
+#define LS1X_PWM1_IRQ                   LS1X_IRQ(0, 18)
+#define LS1X_PWM2_IRQ                   LS1X_IRQ(0, 19)
+#define LS1X_PWM3_IRQ                   LS1X_IRQ(0, 20)
+#define LS1X_RTC_INT0_IRQ               LS1X_IRQ(0, 21)
+#define LS1X_RTC_INT1_IRQ               LS1X_IRQ(0, 22)
+#define LS1X_RTC_INT2_IRQ               LS1X_IRQ(0, 23)
+#define LS1X_TOY_INT0_IRQ               LS1X_IRQ(0, 24)
+#define LS1X_TOY_INT1_IRQ               LS1X_IRQ(0, 25)
+#define LS1X_TOY_INT2_IRQ               LS1X_IRQ(0, 26)
+#define LS1X_RTC_TICK_IRQ               LS1X_IRQ(0, 27)
+#define LS1X_TOY_TICK_IRQ               LS1X_IRQ(0, 28)
+
+#define LS1X_EHCI_IRQ                   LS1X_IRQ(1, 0)
+#define LS1X_OHCI_IRQ                   LS1X_IRQ(1, 1)
+#define LS1X_GMAC0_IRQ                  LS1X_IRQ(1, 2)
+#define LS1X_GMAC1_IRQ                  LS1X_IRQ(1, 3)
+
+#define LS1X_IRQS               (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)
+
+#define NR_IRQS                 (MIPS_CPU_IRQS + LS1X_IRQS)
+
+#endif /* __ASM_MACH_LOONGSON1_IRQ_H */
diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h
new file mode 100644
index 00000000000..4e18e88cebb
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/loongson1.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Register mappings for Loongson 1
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_LOONGSON1_H
+#define __ASM_MACH_LOONGSON1_LOONGSON1_H
+
+#define DEFAULT_MEMSIZE                 256     /* If no memsize provided */
+
+/* Loongson 1 Register Bases */
+#define LS1X_INTC_BASE                  0x1fd01040
+#define LS1X_EHCI_BASE                  0x1fe00000
+#define LS1X_OHCI_BASE                  0x1fe08000
+#define LS1X_GMAC0_BASE                 0x1fe10000
+#define LS1X_GMAC1_BASE                 0x1fe20000
+
+#define LS1X_UART0_BASE                 0x1fe40000
+#define LS1X_UART1_BASE                 0x1fe44000
+#define LS1X_UART2_BASE                 0x1fe48000
+#define LS1X_UART3_BASE                 0x1fe4c000
+#define LS1X_CAN0_BASE                  0x1fe50000
+#define LS1X_CAN1_BASE                  0x1fe54000
+#define LS1X_I2C0_BASE                  0x1fe58000
+#define LS1X_I2C1_BASE                  0x1fe68000
+#define LS1X_I2C2_BASE                  0x1fe70000
+#define LS1X_PWM_BASE                   0x1fe5c000
+#define LS1X_WDT_BASE                   0x1fe5c060
+#define LS1X_RTC_BASE                   0x1fe64000
+#define LS1X_AC97_BASE                  0x1fe74000
+#define LS1X_NAND_BASE                  0x1fe78000
+#define LS1X_CLK_BASE                   0x1fe78030
+
+#include <regs-clk.h>
+#include <regs-wdt.h>
+
+#endif /* __ASM_MACH_LOONGSON1_LOONGSON1_H */
diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
new file mode 100644
index 00000000000..2f171617bad
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+#ifndef __ASM_MACH_LOONGSON1_PLATFORM_H
+#define __ASM_MACH_LOONGSON1_PLATFORM_H
+
+#include <linux/platform_device.h>
+
+extern struct platform_device ls1x_uart_device;
+extern struct platform_device ls1x_eth0_device;
+extern struct platform_device ls1x_ehci_device;
+extern struct platform_device ls1x_rtc_device;
+
+void ls1x_serial_setup(void);
+
+#endif /* __ASM_MACH_LOONGSON1_PLATFORM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h
new file mode 100644
index 00000000000..b871dc41b8d
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/prom.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_PROM_H
+#define __ASM_MACH_LOONGSON1_PROM_H
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+
+/* environment arguments from bootloader */
+extern unsigned long memsize, highmemsize;
+
+/* loongson-specific command line, env and memory initialization */
+extern char *prom_getenv(char *name);
+extern void __init prom_init_cmdline(void);
+
+#endif /* __ASM_MACH_LOONGSON1_PROM_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
new file mode 100644
index 00000000000..8efa7fb9f73
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 Clock Register Definitions.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
+#define __ASM_MACH_LOONGSON1_REGS_CLK_H
+
+#define LS1X_CLK_REG(x) \
+                ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))
+
+#define LS1X_CLK_PLL_FREQ               LS1X_CLK_REG(0x0)
+#define LS1X_CLK_PLL_DIV                LS1X_CLK_REG(0x4)
+
+/* Clock PLL Divisor Register Bits */
+#define DIV_DC_EN                       (0x1 << 31)
+#define DIV_DC                          (0x1f << 26)
+#define DIV_CPU_EN                      (0x1 << 25)
+#define DIV_CPU                         (0x1f << 20)
+#define DIV_DDR_EN                      (0x1 << 19)
+#define DIV_DDR                         (0x1f << 14)
+
+#define DIV_DC_SHIFT                    26
+#define DIV_CPU_SHIFT                   20
+#define DIV_DDR_SHIFT                   14
+
+#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
new file mode 100644
index 00000000000..f897de68c52
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Loongson 1 watchdog register definitions.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __ASM_MACH_LOONGSON1_REGS_WDT_H
+#define __ASM_MACH_LOONGSON1_REGS_WDT_H
+
+#define LS1X_WDT_REG(x) \
+                ((void __iomem *)KSEG1ADDR(LS1X_WDT_BASE + (x)))
+
+#define LS1X_WDT_EN                     LS1X_WDT_REG(0x0)
+#define LS1X_WDT_SET                    LS1X_WDT_REG(0x4)
+#define LS1X_WDT_TIMER                  LS1X_WDT_REG(0x8)
+
+#endif /* __ASM_MACH_LOONGSON1_REGS_WDT_H */
diff --git a/arch/mips/include/asm/mach-loongson1/war.h b/arch/mips/include/asm/mach-loongson1/war.h
new file mode 100644
index 00000000000..e3680a8fb34
--- /dev/null
+++ b/arch/mips/include/asm/mach-loongson1/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MACH_LOONGSON1_WAR_H
+#define __ASM_MACH_LOONGSON1_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MACH_LOONGSON1_WAR_H */
diff --git a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
index d193fb68cf2..966db4be377 100644
--- a/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-netlogic/cpu-feature-overrides.h
@@ -48,7 +48,6 @@
 #define cpu_has_userlocal       1
 #define cpu_has_mips32r2        1
 #define cpu_has_mips64r2        1
-#define cpu_has_dc_aliases      1
 #else
 #error "Unknown Netlogic CPU"
 #endif
diff --git a/arch/mips/include/asm/mach-tx49xx/mangle-port.h b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
index 5e6912fdd0e..490867b03c8 100644
--- a/arch/mips/include/asm/mach-tx49xx/mangle-port.h
+++ b/arch/mips/include/asm/mach-tx49xx/mangle-port.h
@@ -9,7 +9,7 @@
 #define ioswabb(a, x)           (x)
 #define __mem_ioswabb(a, x)     (x)
 #if defined(CONFIG_TOSHIBA_RBTX4939) && \
-        (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)) && \
+        IS_ENABLED(CONFIG_SMC91X) && \
         defined(__BIG_ENDIAN)
 #define NEEDS_TXX9_IOSWABW
 extern u16 (*ioswabw)(volatile u16 *a, u16 x);
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index e71ff4c317f..5b3cb8553e9 100644
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -28,6 +28,9 @@
 #define read_c0_vpeconf0()              __read_32bit_c0_register($1, 2)
 #define write_c0_vpeconf0(val)          __write_32bit_c0_register($1, 2, val)
 
+#define read_c0_vpeconf1()              __read_32bit_c0_register($1, 3)
+#define write_c0_vpeconf1(val)          __write_32bit_c0_register($1, 3, val)
+
 #define read_c0_tcstatus()              __read_32bit_c0_register($2, 1)
 #define write_c0_tcstatus(val)          __write_32bit_c0_register($2, 1, val)
 
@@ -124,6 +127,14 @@
 #define VPECONF0_XTC_SHIFT      21
 #define VPECONF0_XTC            (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
 
+/* VPEConf1 fields (per VPE) */
+#define VPECONF1_NCP1_SHIFT     0
+#define VPECONF1_NCP1           (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT)
+#define VPECONF1_NCP2_SHIFT     10
+#define VPECONF1_NCP2           (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT)
+#define VPECONF1_NCX_SHIFT      20
+#define VPECONF1_NCX            (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT)
+
 /* TCStatus fields (per TC) */
 #define TCSTATUS_TASID          (_ULCAST_(0xff))
 #define TCSTATUS_IXMT_SHIFT     10
@@ -350,6 +361,8 @@ do {									\
 #define write_vpe_c0_vpecontrol(val)    mttc0(1, 1, val)
 #define read_vpe_c0_vpeconf0()          mftc0(1, 2)
 #define write_vpe_c0_vpeconf0(val)      mttc0(1, 2, val)
+#define read_vpe_c0_vpeconf1()          mftc0(1, 3)
+#define write_vpe_c0_vpeconf1(val)      mttc0(1, 3, val)
 #define read_vpe_c0_count()             mftc0(9, 0)
 #define write_vpe_c0_count(val)         mttc0(9, 0, val)
 #define read_vpe_c0_status()            mftc0(12, 0)
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index 530008048c6..dca8bce8c7a 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -10,6 +10,7 @@ struct mod_arch_specific {
         struct list_head dbe_list;
         const struct exception_table_entry *dbe_start;
         const struct exception_table_entry *dbe_end;
+        struct mips_hi16 *r_mips_hi16_list;
 };
 
 typedef uint8_t Elf64_Byte;             /* Type for a 8-bit quantity.  */
@@ -117,6 +118,8 @@ search_module_dbetables(unsigned long addr)
 #define MODULE_PROC_FAMILY "RM9000 "
 #elif defined CONFIG_CPU_SB1
 #define MODULE_PROC_FAMILY "SB1 "
+#elif defined CONFIG_CPU_LOONGSON1
+#define MODULE_PROC_FAMILY "LOONGSON1 "
 #elif defined CONFIG_CPU_LOONGSON2
 #define MODULE_PROC_FAMILY "LOONGSON2 "
 #elif defined CONFIG_CPU_CAVIUM_OCTEON
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
index bf7d41deb9b..7b63a6b722a 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h
@@ -47,7 +47,9 @@
 #define CPU_BLOCKID_MAP         10
 
 #define LSU_DEFEATURE           0x304
-#define LSU_CERRLOG_REGID       0x09
+#define LSU_DEBUG_ADDR          0x305
+#define LSU_DEBUG_DATA0         0x306
+#define LSU_CERRLOG_REGID       0x309
 #define SCHED_DEFEATURE         0x700
 
 /* Offsets of interest from the 'MAP' Block */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 86cc3391e50..2c63f975464 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -36,6 +36,9 @@
 #define __NLM_HAL_IOMAP_H__
 
 #define XLP_DEFAULT_IO_BASE             0x18000000
+#define XLP_DEFAULT_PCI_ECFG_BASE       XLP_DEFAULT_IO_BASE
+#define XLP_DEFAULT_PCI_CFG_BASE        0x1c000000
+
 #define NMI_BASE                        0xbfc00000
 #define XLP_IO_CLK                      133333333
 
@@ -129,7 +132,7 @@
 #define PCI_DEVICE_ID_NLM_PIC           0x1003
 #define PCI_DEVICE_ID_NLM_PCIE          0x1004
 #define PCI_DEVICE_ID_NLM_EHCI          0x1007
-#define PCI_DEVICE_ID_NLM_ILK           0x1008
+#define PCI_DEVICE_ID_NLM_OHCI          0x1008
 #define PCI_DEVICE_ID_NLM_NAE           0x1009
 #define PCI_DEVICE_ID_NLM_POE           0x100A
 #define PCI_DEVICE_ID_NLM_FMN           0x100B
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
new file mode 100644
index 00000000000..66c323d1bd7
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_PCIBUS_H__
+#define __NLM_HAL_PCIBUS_H__
+
+/* PCIE Memory and IO regions */
+#define PCIE_MEM_BASE                   0xd0000000ULL
+#define PCIE_MEM_LIMIT                  0xdfffffffULL
+#define PCIE_IO_BASE                    0x14000000ULL
+#define PCIE_IO_LIMIT                   0x15ffffffULL
+
+#define PCIE_BRIDGE_CMD                 0x1
+#define PCIE_BRIDGE_MSI_CAP             0x14
+#define PCIE_BRIDGE_MSI_ADDRL           0x15
+#define PCIE_BRIDGE_MSI_ADDRH           0x16
+#define PCIE_BRIDGE_MSI_DATA            0x17
+
+/* XLP Global PCIE configuration space registers */
+#define PCIE_BYTE_SWAP_MEM_BASE         0x247
+#define PCIE_BYTE_SWAP_MEM_LIM          0x248
+#define PCIE_BYTE_SWAP_IO_BASE          0x249
+#define PCIE_BYTE_SWAP_IO_LIM           0x24A
+#define PCIE_MSI_STATUS                 0x25A
+#define PCIE_MSI_EN                     0x25B
+#define PCIE_INT_EN0                    0x261
+
+/* PCIE_MSI_EN */
+#define PCIE_MSI_VECTOR_INT_EN          0xFFFFFFFF
+
+/* PCIE_INT_EN0 */
+#define PCIE_MSI_INT_EN                 (1 << 9)
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_pcie_reg(b, r)         nlm_read_reg(b, r)
+#define nlm_write_pcie_reg(b, r, v)     nlm_write_reg(b, r, v)
+#define nlm_get_pcie_base(node, inst)   \
+                        nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
+#define nlm_get_pcie_regbase(node, inst)        \
+                        (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
+
+int xlp_pcie_link_irt(int link);
+#endif
+#endif /* __NLM_HAL_PCIBUS_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index b6628f7ccf7..ad8b80233a6 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -201,7 +201,11 @@
 #define PIC_NUM_USB_IRTS                6
 #define PIC_IRT_USB_0_INDEX             115
 #define PIC_IRT_EHCI_0_INDEX            115
+#define PIC_IRT_OHCI_0_INDEX            116
+#define PIC_IRT_OHCI_1_INDEX            117
 #define PIC_IRT_EHCI_1_INDEX            118
+#define PIC_IRT_OHCI_2_INDEX            119
+#define PIC_IRT_OHCI_3_INDEX            120
 #define PIC_IRT_USB_INDEX(num)          ((num) + PIC_IRT_USB_0_INDEX)
 /* 115 to 120 */
 #define PIC_IRT_GDX_INDEX               121
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/usb.h b/arch/mips/include/asm/netlogic/xlp-hal/usb.h
new file mode 100644
index 00000000000..a9cd350dfb6
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/usb.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_USB_H__
+#define __NLM_HAL_USB_H__
+
+#define USB_CTL_0                       0x01
+#define USB_PHY_0                       0x0A
+#define USB_PHY_RESET                   0x01
+#define USB_PHY_PORT_RESET_0            0x10
+#define USB_PHY_PORT_RESET_1            0x20
+#define USB_CONTROLLER_RESET            0x01
+#define USB_INT_STATUS                  0x0E
+#define USB_INT_EN                      0x0F
+#define USB_PHY_INTERRUPT_EN            0x01
+#define USB_OHCI_INTERRUPT_EN           0x02
+#define USB_OHCI_INTERRUPT1_EN          0x04
+#define USB_OHCI_INTERRUPT2_EN          0x08
+#define USB_CTRL_INTERRUPT_EN           0x10
+
+#ifndef __ASSEMBLY__
+
+#define nlm_read_usb_reg(b, r)                  nlm_read_reg(b, r)
+#define nlm_write_usb_reg(b, r, v)              nlm_write_reg(b, r, v)
+#define nlm_get_usb_pcibase(node, inst)         \
+        nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst))
+#define nlm_get_usb_hcd_base(node, inst)        \
+        nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst))
+#define nlm_get_usb_regbase(node, inst)         \
+        (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
+
+#endif
+#endif /* __NLM_HAL_USB_H__ */
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
index 1540588e396..7e47209327a 100644
--- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h
@@ -35,8 +35,21 @@
 #ifndef _NLM_HAL_XLP_H
 #define _NLM_HAL_XLP_H
 
-#define PIC_UART_0_IRQ           17
-#define PIC_UART_1_IRQ           18
+#define PIC_UART_0_IRQ                  17
+#define PIC_UART_1_IRQ                  18
+#define PIC_PCIE_LINK_0_IRQ             19
+#define PIC_PCIE_LINK_1_IRQ             20
+#define PIC_PCIE_LINK_2_IRQ             21
+#define PIC_PCIE_LINK_3_IRQ             22
+#define PIC_EHCI_0_IRQ                  23
+#define PIC_EHCI_1_IRQ                  24
+#define PIC_OHCI_0_IRQ                  25
+#define PIC_OHCI_1_IRQ                  26
+#define PIC_OHCI_2_IRQ                  27
+#define PIC_OHCI_3_IRQ                  28
+#define PIC_MMC_IRQ                     29
+#define PIC_I2C_0_IRQ                   30
+#define PIC_I2C_1_IRQ                   31
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/mips/include/asm/netlogic/xlr/bridge.h b/arch/mips/include/asm/netlogic/xlr/bridge.h
new file mode 100644
index 00000000000..2d02428c4f1
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/bridge.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NLM_BRIDGE_H_
+#define _ASM_NLM_BRIDGE_H_
+
+#define BRIDGE_DRAM_0_BAR               0
+#define BRIDGE_DRAM_1_BAR               1
+#define BRIDGE_DRAM_2_BAR               2
+#define BRIDGE_DRAM_3_BAR               3
+#define BRIDGE_DRAM_4_BAR               4
+#define BRIDGE_DRAM_5_BAR               5
+#define BRIDGE_DRAM_6_BAR               6
+#define BRIDGE_DRAM_7_BAR               7
+#define BRIDGE_DRAM_CHN_0_MTR_0_BAR     8
+#define BRIDGE_DRAM_CHN_0_MTR_1_BAR     9
+#define BRIDGE_DRAM_CHN_0_MTR_2_BAR     10
+#define BRIDGE_DRAM_CHN_0_MTR_3_BAR     11
+#define BRIDGE_DRAM_CHN_0_MTR_4_BAR     12
+#define BRIDGE_DRAM_CHN_0_MTR_5_BAR     13
+#define BRIDGE_DRAM_CHN_0_MTR_6_BAR     14
+#define BRIDGE_DRAM_CHN_0_MTR_7_BAR     15
+#define BRIDGE_DRAM_CHN_1_MTR_0_BAR     16
+#define BRIDGE_DRAM_CHN_1_MTR_1_BAR     17
+#define BRIDGE_DRAM_CHN_1_MTR_2_BAR     18
+#define BRIDGE_DRAM_CHN_1_MTR_3_BAR     19
+#define BRIDGE_DRAM_CHN_1_MTR_4_BAR     20
+#define BRIDGE_DRAM_CHN_1_MTR_5_BAR     21
+#define BRIDGE_DRAM_CHN_1_MTR_6_BAR     22
+#define BRIDGE_DRAM_CHN_1_MTR_7_BAR     23
+#define BRIDGE_CFG_BAR                  24
+#define BRIDGE_PHNX_IO_BAR              25
+#define BRIDGE_FLASH_BAR                26
+#define BRIDGE_SRAM_BAR                 27
+#define BRIDGE_HTMEM_BAR                28
+#define BRIDGE_HTINT_BAR                29
+#define BRIDGE_HTPIC_BAR                30
+#define BRIDGE_HTSM_BAR                 31
+#define BRIDGE_HTIO_BAR                 32
+#define BRIDGE_HTCFG_BAR                33
+#define BRIDGE_PCIXCFG_BAR              34
+#define BRIDGE_PCIXMEM_BAR              35
+#define BRIDGE_PCIXIO_BAR               36
+#define BRIDGE_DEVICE_MASK              37
+#define BRIDGE_AERR_INTR_LOG1           38
+#define BRIDGE_AERR_INTR_LOG2           39
+#define BRIDGE_AERR_INTR_LOG3           40
+#define BRIDGE_AERR_DEV_STAT            41
+#define BRIDGE_AERR1_LOG1               42
+#define BRIDGE_AERR1_LOG2               43
+#define BRIDGE_AERR1_LOG3               44
+#define BRIDGE_AERR1_DEV_STAT           45
+#define BRIDGE_AERR_INTR_EN             46
+#define BRIDGE_AERR_UPG                 47
+#define BRIDGE_AERR_CLEAR               48
+#define BRIDGE_AERR1_CLEAR              49
+#define BRIDGE_SBE_COUNTS               50
+#define BRIDGE_DBE_COUNTS               51
+#define BRIDGE_BITERR_INT_EN            52
+
+#define BRIDGE_SYS2IO_CREDITS           53
+#define BRIDGE_EVNT_CNT_CTRL1           54
+#define BRIDGE_EVNT_COUNTER1            55
+#define BRIDGE_EVNT_CNT_CTRL2           56
+#define BRIDGE_EVNT_COUNTER2            57
+#define BRIDGE_RESERVED1                58
+
+#define BRIDGE_DEFEATURE                59
+#define BRIDGE_SCRATCH0                 60
+#define BRIDGE_SCRATCH1                 61
+#define BRIDGE_SCRATCH2                 62
+#define BRIDGE_SCRATCH3                 63
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/flash.h b/arch/mips/include/asm/netlogic/xlr/flash.h
new file mode 100644
index 00000000000..f8aca5472b6
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlr/flash.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _ASM_NLM_FLASH_H_
+#define _ASM_NLM_FLASH_H_
+
+#define FLASH_CSBASE_ADDR(cs)           (cs)
+#define FLASH_CSADDR_MASK(cs)           (0x10 + (cs))
+#define FLASH_CSDEV_PARM(cs)            (0x20 + (cs))
+#define FLASH_CSTIME_PARMA(cs)          (0x30 + (cs))
+#define FLASH_CSTIME_PARMB(cs)          (0x40 + (cs))
+
+#define FLASH_INT_MASK                  0x50
+#define FLASH_INT_STATUS                0x60
+#define FLASH_ERROR_STATUS              0x70
+#define FLASH_ERROR_ADDR                0x80
+
+#define FLASH_NAND_CLE(cs)              (0x90 + (cs))
+#define FLASH_NAND_ALE(cs)              (0xa0 + (cs))
+
+#define FLASH_NAND_CSDEV_PARAM          0x000041e6
+#define FLASH_NAND_CSTIME_PARAMA        0x4f400e22
+#define FLASH_NAND_CSTIME_PARAMB        0x000083cf
+
+#endif
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h
index 51f6ad4aeb1..8492e835b11 100644
--- a/arch/mips/include/asm/netlogic/xlr/gpio.h
+++ b/arch/mips/include/asm/netlogic/xlr/gpio.h
@@ -35,39 +35,40 @@
 #ifndef _ASM_NLM_GPIO_H
 #define _ASM_NLM_GPIO_H
 
-#define NETLOGIC_GPIO_INT_EN_REG                0
-#define NETLOGIC_GPIO_INPUT_INVERSION_REG       1
-#define NETLOGIC_GPIO_IO_DIR_REG                2
-#define NETLOGIC_GPIO_IO_DATA_WR_REG            3
-#define NETLOGIC_GPIO_IO_DATA_RD_REG            4
+#define GPIO_INT_EN_REG                 0
+#define GPIO_INPUT_INVERSION_REG        1
+#define GPIO_IO_DIR_REG                 2
+#define GPIO_IO_DATA_WR_REG             3
+#define GPIO_IO_DATA_RD_REG             4
 
-#define NETLOGIC_GPIO_SWRESET_REG               8
-#define NETLOGIC_GPIO_DRAM1_CNTRL_REG           9
-#define NETLOGIC_GPIO_DRAM1_RATIO_REG           10
-#define NETLOGIC_GPIO_DRAM1_RESET_REG           11
-#define NETLOGIC_GPIO_DRAM1_STATUS_REG          12
-#define NETLOGIC_GPIO_DRAM2_CNTRL_REG           13
-#define NETLOGIC_GPIO_DRAM2_RATIO_REG           14
-#define NETLOGIC_GPIO_DRAM2_RESET_REG           15
-#define NETLOGIC_GPIO_DRAM2_STATUS_REG          16
+#define GPIO_SWRESET_REG                8
+#define GPIO_DRAM1_CNTRL_REG            9
+#define GPIO_DRAM1_RATIO_REG            10
+#define GPIO_DRAM1_RESET_REG            11
+#define GPIO_DRAM1_STATUS_REG           12
+#define GPIO_DRAM2_CNTRL_REG            13
+#define GPIO_DRAM2_RATIO_REG            14
+#define GPIO_DRAM2_RESET_REG            15
+#define GPIO_DRAM2_STATUS_REG           16
 
-#define NETLOGIC_GPIO_PWRON_RESET_CFG_REG       21
-#define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG    24
-#define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG    25
-#define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG    26
+#define GPIO_PWRON_RESET_CFG_REG        21
+#define GPIO_BIST_ALL_GO_STATUS_REG     24
+#define GPIO_BIST_CPU_GO_STATUS_REG     25
+#define GPIO_BIST_DEV_GO_STATUS_REG     26
 
-#define NETLOGIC_GPIO_FUSE_BANK_REG             35
-#define NETLOGIC_GPIO_CPU_RESET_REG             40
-#define NETLOGIC_GPIO_RNG_REG                   43
+#define GPIO_FUSE_BANK_REG              35
+#define GPIO_CPU_RESET_REG              40
+#define GPIO_RNG_REG                    43
 
-#define NETLOGIC_PWRON_RESET_PCMCIA_BOOT        17
-#define NETLOGIC_GPIO_LED_BITMAP        0x1700000
-#define NETLOGIC_GPIO_LED_0_SHIFT               20
-#define NETLOGIC_GPIO_LED_1_SHIFT               24
+#define PWRON_RESET_PCMCIA_BOOT         17
 
-#define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET     0x01
-#define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
-#define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
-#define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN      0x04
+#define GPIO_LED_BITMAP                 0x1700000
+#define GPIO_LED_0_SHIFT                20
+#define GPIO_LED_1_SHIFT                24
+
+#define GPIO_LED_OUTPUT_CODE_RESET      0x01
+#define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02
+#define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03
+#define GPIO_LED_OUTPUT_CODE_MAIN       0x04
 
 #endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h b/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
deleted file mode 100644
index 5ff8c93198d..00000000000
--- a/arch/mips/include/asm/octeon/cvmx-helper-fpa.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/***********************license start***************
- * Author: Cavium Networks
- *
- * Contact: support@caviumnetworks.com
- * This file is part of the OCTEON SDK
- *
- * Copyright (c) 2003-2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful, but
- * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
- * NONINFRINGEMENT.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this file; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * or visit http://www.gnu.org/licenses/.
- *
- * This file may also be available under a different license from Cavium.
- * Contact Cavium Networks for more information
- ***********************license end**************************************/
-
-/**
- * @file
- *
- * Helper functions for FPA setup.
- *
- */
-#ifndef __CVMX_HELPER_H_FPA__
-#define __CVMX_HELPER_H_FPA__
-
-/**
- * Allocate memory and initialize the FPA pools using memory
- * from cvmx-bootmem. Sizes of each element in the pools is
- * controlled by the cvmx-config.h header file. Specifying
- * zero for any parameter will cause that FPA pool to not be
- * setup. This is useful if you aren't using some of the
- * hardware and want to save memory.
- *
- * @packet_buffers:
- *               Number of packet buffers to allocate
- * @work_queue_entries:
- *               Number of work queue entries
- * @pko_buffers:
- *               PKO Command buffers. You should at minimum have two per
- *               each PKO queue.
- * @tim_buffers:
- *               TIM ring buffer command queues. At least two per timer bucket
- *               is recommened.
- * @dfa_buffers:
- *               DFA command buffer. A relatively small (32 for example)
- *               number should work.
- * Returns Zero on success, non-zero if out of memory
- */
-extern int cvmx_helper_initialize_fpa(int packet_buffers,
-                                      int work_queue_entries, int pko_buffers,
-                                      int tim_buffers, int dfa_buffers);
-
-#endif /* __CVMX_HELPER_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
index 3169cd79f2a..0ac6b9f412b 100644
--- a/arch/mips/include/asm/octeon/cvmx-helper.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper.h
@@ -61,8 +61,6 @@ typedef union {
         } s;
 } cvmx_helper_link_info_t;
 
-#include "cvmx-helper-fpa.h"
-
 #include <asm/octeon/cvmx-helper-errata.h>
 #include "cvmx-helper-loop.h"
 #include "cvmx-helper-npi.h"
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index f72f768cd3a..1e2486e2357 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -215,11 +215,6 @@ struct octeon_cf_data {
         int             dma_engine;     /* -1 for no DMA */
 };
 
-struct octeon_i2c_data {
-        unsigned int    sys_freq;
-        unsigned int    i2c_freq;
-};
-
 extern void octeon_write_lcd(const char *s);
 extern void octeon_check_cpu_bist(void);
 extern int octeon_get_boot_debug_flag(void);
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index 7206d445bab..8808bf548b9 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -20,9 +20,6 @@
 extern int early_init_dt_scan_memory_arch(unsigned long node,
         const char *uname, int depth, void *data);
 
-extern int reserve_mem_mach(unsigned long addr, unsigned long size);
-extern void free_mem_mach(unsigned long addr, unsigned long size);
-
 extern void device_tree_init(void);
 
 static inline unsigned long pci_address_to_pio(phys_addr_t address)
diff --git a/arch/mips/include/asm/r4k-timer.h b/arch/mips/include/asm/r4k-timer.h
index a37d12b3b61..afe9e0e03fe 100644
--- a/arch/mips/include/asm/r4k-timer.h
+++ b/arch/mips/include/asm/r4k-timer.h
@@ -12,16 +12,16 @@
 
 #ifdef CONFIG_SYNC_R4K
 
-extern void synchronise_count_master(void);
-extern void synchronise_count_slave(void);
+extern void synchronise_count_master(int cpu);
+extern void synchronise_count_slave(int cpu);
 
 #else
 
-static inline void synchronise_count_master(void)
+static inline void synchronise_count_master(int cpu)
 {
 }
 
-static inline void synchronise_count_slave(void)
+static inline void synchronise_count_slave(int cpu)
 {
 }
 
diff --git a/arch/mips/include/asm/smtc.h b/arch/mips/include/asm/smtc.h
index c9736fc0632..8935426a56a 100644
--- a/arch/mips/include/asm/smtc.h
+++ b/arch/mips/include/asm/smtc.h
@@ -33,6 +33,12 @@ typedef long asiduse;
 #endif
 #endif
 
+/*
+ * VPE Management information
+ */
+
+#define MAX_SMTC_VPES   MAX_SMTC_TLBS   /* FIXME: May not always be true. */
+
 extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
 
 struct mm_struct;
diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index 653a412c036..3b92efef56d 100644
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -687,7 +687,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
         __MODULE_JAL(__copy_user)                                       \
         : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
         :                                                               \
-        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
+        : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",  \
           DADDI_SCRATCH, "memory");                                     \
         __cu_len_r;                                                     \
 })
@@ -797,7 +797,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
         ".set\treorder"                                                 \
         : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
         :                                                               \
-        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
+        : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",  \
           DADDI_SCRATCH, "memory");                                     \
         __cu_len_r;                                                     \
 })
@@ -820,7 +820,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
         ".set\treorder"                                                 \
         : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
         :                                                               \
-        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
+        : "$8", "$9", "$10", "$11", "$12", "$14", "$15", "$24", "$31",  \
           DADDI_SCRATCH, "memory");                                     \
         __cu_len_r;                                                     \
 })
diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 440a21dab57..3d9f75f7ffc 100644
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -6,6 +6,7 @@
  * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
  * Copyright (C) 2005  Maciej W. Rozycki
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2012  MIPS Technologies, Inc.
  */
 
 #include <linux/types.h>
@@ -62,8 +63,10 @@ void __uasminit uasm_i##op(u32 **buf, unsigned int a, signed int b)
 
 Ip_u2u1s3(_addiu);
 Ip_u3u1u2(_addu);
-Ip_u2u1u3(_andi);
 Ip_u3u1u2(_and);
+Ip_u2u1u3(_andi);
+Ip_u1u2s3(_bbit0);
+Ip_u1u2s3(_bbit1);
 Ip_u1u2s3(_beq);
 Ip_u1u2s3(_beql);
 Ip_u1s2(_bgez);
@@ -72,55 +75,54 @@ Ip_u1s2(_bltz);
 Ip_u1s2(_bltzl);
 Ip_u1u2s3(_bne);
 Ip_u2s3u1(_cache);
-Ip_u1u2u3(_dmfc0);
-Ip_u1u2u3(_dmtc0);
 Ip_u2u1s3(_daddiu);
 Ip_u3u1u2(_daddu);
+Ip_u2u1msbu3(_dins);
+Ip_u2u1msbu3(_dinsm);
+Ip_u1u2u3(_dmfc0);
+Ip_u1u2u3(_dmtc0);
+Ip_u2u1u3(_drotr);
+Ip_u2u1u3(_drotr32);
 Ip_u2u1u3(_dsll);
 Ip_u2u1u3(_dsll32);
 Ip_u2u1u3(_dsra);
 Ip_u2u1u3(_dsrl);
 Ip_u2u1u3(_dsrl32);
-Ip_u2u1u3(_drotr);
-Ip_u2u1u3(_drotr32);
 Ip_u3u1u2(_dsubu);
 Ip_0(_eret);
 Ip_u1(_j);
 Ip_u1(_jal);
 Ip_u1(_jr);
 Ip_u2s3u1(_ld);
+Ip_u3u1u2(_ldx);
 Ip_u2s3u1(_ll);
 Ip_u2s3u1(_lld);
 Ip_u1s2(_lui);
 Ip_u2s3u1(_lw);
+Ip_u3u1u2(_lwx);
 Ip_u1u2u3(_mfc0);
 Ip_u1u2u3(_mtc0);
-Ip_u2u1u3(_ori);
 Ip_u3u1u2(_or);
+Ip_u2u1u3(_ori);
 Ip_u2s3u1(_pref);
 Ip_0(_rfe);
+Ip_u2u1u3(_rotr);
 Ip_u2s3u1(_sc);
 Ip_u2s3u1(_scd);
 Ip_u2s3u1(_sd);
 Ip_u2u1u3(_sll);
 Ip_u2u1u3(_sra);
 Ip_u2u1u3(_srl);
-Ip_u2u1u3(_rotr);
 Ip_u3u1u2(_subu);
 Ip_u2s3u1(_sw);
+Ip_u1(_syscall);
 Ip_0(_tlbp);
 Ip_0(_tlbr);
 Ip_0(_tlbwi);
 Ip_0(_tlbwr);
 Ip_u3u1u2(_xor);
 Ip_u2u1u3(_xori);
-Ip_u2u1msbu3(_dins);
-Ip_u2u1msbu3(_dinsm);
-Ip_u1(_syscall);
-Ip_u1u2s3(_bbit0);
-Ip_u1u2s3(_bbit1);
-Ip_u3u1u2(_lwx);
-Ip_u3u1u2(_ldx);
+
 
 /* Handle labels. */
 struct uasm_label {
@@ -145,37 +147,37 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
 
 /* convenience macros for instructions */
 #ifdef CONFIG_64BIT
+# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
+# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
+# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
 # define UASM_i_LW(buf, rs, rt, off) uasm_i_ld(buf, rs, rt, off)
-# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
+# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
+# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
+# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
+# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
+# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
 # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh)
 # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh)
 # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh)
 # define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_dsrl_safe(buf, rs, rt, sh)
-# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
-# define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
-# define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
-# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
-# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_daddu(buf, rs, rt, rd)
 # define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_dsubu(buf, rs, rt, rd)
-# define UASM_i_LL(buf, rs, rt, off) uasm_i_lld(buf, rs, rt, off)
-# define UASM_i_SC(buf, rs, rt, off) uasm_i_scd(buf, rs, rt, off)
-# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_ldx(buf, rs, rt, rd)
+# define UASM_i_SW(buf, rs, rt, off) uasm_i_sd(buf, rs, rt, off)
 #else
+# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
+# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
+# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
 # define UASM_i_LW(buf, rs, rt, off) uasm_i_lw(buf, rs, rt, off)
-# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
+# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
+# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
+# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
+# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
+# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
 # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh)
 # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh)
 # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
 # define UASM_i_SRL_SAFE(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
-# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
-# define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
-# define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
-# define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
-# define UASM_i_ADDU(buf, rs, rt, rd) uasm_i_addu(buf, rs, rt, rd)
 # define UASM_i_SUBU(buf, rs, rt, rd) uasm_i_subu(buf, rs, rt, rd)
-# define UASM_i_LL(buf, rs, rt, off) uasm_i_ll(buf, rs, rt, off)
-# define UASM_i_SC(buf, rs, rt, off) uasm_i_sc(buf, rs, rt, off)
-# define UASM_i_LWX(buf, rs, rt, rd) uasm_i_lwx(buf, rs, rt, rd)
+# define UASM_i_SW(buf, rs, rt, off) uasm_i_sw(buf, rs, rt, off)
 #endif
 
 #define uasm_i_b(buf, off) uasm_i_beq(buf, 0, 0, off)
@@ -183,19 +185,10 @@ static inline void __uasminit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
 #define uasm_i_beqzl(buf, rs, off) uasm_i_beql(buf, rs, 0, off)
 #define uasm_i_bnez(buf, rs, off) uasm_i_bne(buf, rs, 0, off)
 #define uasm_i_bnezl(buf, rs, off) uasm_i_bnel(buf, rs, 0, off)
+#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
 #define uasm_i_move(buf, a, b) UASM_i_ADDU(buf, a, 0, b)
 #define uasm_i_nop(buf) uasm_i_sll(buf, 0, 0, 0)
 #define uasm_i_ssnop(buf) uasm_i_sll(buf, 0, 0, 1)
-#define uasm_i_ehb(buf) uasm_i_sll(buf, 0, 0, 3)
-
-static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
-                                    unsigned int a2, unsigned int a3)
-{
-        if (a3 < 32)
-                uasm_i_dsrl(p, a1, a2, a3);
-        else
-                uasm_i_dsrl32(p, a1, a2, a3 - 32);
-}
 
 static inline void uasm_i_drotr_safe(u32 **p, unsigned int a1,
                                      unsigned int a2, unsigned int a3)
@@ -215,6 +208,15 @@ static inline void uasm_i_dsll_safe(u32 **p, unsigned int a1,
                 uasm_i_dsll32(p, a1, a2, a3 - 32);
 }
 
+static inline void uasm_i_dsrl_safe(u32 **p, unsigned int a1,
+                                    unsigned int a2, unsigned int a3)
+{
+        if (a3 < 32)
+                uasm_i_dsrl(p, a1, a2, a3);
+        else
+                uasm_i_dsrl32(p, a1, a2, a3 - 32);
+}
+
 /* Handle relocations. */
 struct uasm_reloc {
         u32 *addr;
@@ -234,16 +236,16 @@ void uasm_copy_handler(struct uasm_reloc *rel, struct uasm_label *lab,
 int uasm_insn_has_bdelay(struct uasm_reloc *rel, u32 *addr);
 
 /* Convenience functions for labeled branches. */
-void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_b(u32 **p, struct uasm_reloc **r, int lid);
+void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
+void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
+                   unsigned int bit, int lid);
 void uasm_il_beqz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_beqzl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
+void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
 void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
                  unsigned int reg2, int lid);
 void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void uasm_il_bgezl(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void uasm_il_bgez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
-void uasm_il_bbit0(u32 **p, struct uasm_reloc **r, unsigned int reg,
-                   unsigned int bit, int lid);
-void uasm_il_bbit1(u32 **p, struct uasm_reloc **r, unsigned int reg,
-                   unsigned int bit, int lid);
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index d8dad5340ea..bebbde01be9 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -1034,7 +1034,6 @@
 #ifndef __ASSEMBLY__
 
 #define __ARCH_OMIT_COMPAT_SYS_GETDENTS64
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_SYS_ALARM
 #define __ARCH_WANT_SYS_GETHOSTNAME
diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index 9a91fe9de69..9a3d9de4d04 100644
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -140,6 +140,7 @@ static void qi_lb60_nand_ident(struct platform_device *pdev,
 static struct jz_nand_platform_data qi_lb60_nand_pdata = {
         .ident_callback = qi_lb60_nand_ident,
         .busy_gpio = 94,
+        .banks = { 1 },
 };
 
 /* Keyboard*/
diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c
index 10929e2bc6d..e342ed4cbd4 100644
--- a/arch/mips/jz4740/platform.c
+++ b/arch/mips/jz4740/platform.c
@@ -157,11 +157,29 @@ static struct resource jz4740_nand_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         {
-                .name   = "bank",
+                .name   = "bank1",
                 .start  = 0x18000000,
                 .end    = 0x180C0000 - 1,
                 .flags = IORESOURCE_MEM,
         },
+        {
+                .name   = "bank2",
+                .start  = 0x14000000,
+                .end    = 0x140C0000 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name   = "bank3",
+                .start  = 0x0C000000,
+                .end    = 0x0C0C0000 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .name   = "bank4",
+                .start  = 0x08000000,
+                .end    = 0x080C0000 - 1,
+                .flags = IORESOURCE_MEM,
+        },
 };
 
 struct platform_device jz4740_nand_device = {
diff --git a/arch/mips/jz4740/reset.c b/arch/mips/jz4740/reset.c
index 5f1fb95c0d0..6c0da5afcf1 100644
--- a/arch/mips/jz4740/reset.c
+++ b/arch/mips/jz4740/reset.c
@@ -21,6 +21,9 @@
 #include <asm/mach-jz4740/base.h>
 #include <asm/mach-jz4740/timer.h>
 
+#include "reset.h"
+#include "clock.h"
+
 static void jz4740_halt(void)
 {
         while (1) {
@@ -53,21 +56,57 @@ static void jz4740_restart(char *command)
         jz4740_halt();
 }
 
-#define JZ_REG_RTC_CTRL         0x00
-#define JZ_REG_RTC_HIBERNATE    0x20
+#define JZ_REG_RTC_CTRL                 0x00
+#define JZ_REG_RTC_HIBERNATE            0x20
+#define JZ_REG_RTC_WAKEUP_FILTER        0x24
+#define JZ_REG_RTC_RESET_COUNTER        0x28
 
-#define JZ_RTC_CTRL_WRDY        BIT(7)
+#define JZ_RTC_CTRL_WRDY                BIT(7)
+#define JZ_RTC_WAKEUP_FILTER_MASK       0x0000FFE0
+#define JZ_RTC_RESET_COUNTER_MASK       0x00000FE0
 
-static void jz4740_power_off(void)
+static inline void jz4740_rtc_wait_ready(void __iomem *rtc_base)
 {
-        void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x24);
         uint32_t ctrl;
 
         do {
                 ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
         } while (!(ctrl & JZ_RTC_CTRL_WRDY));
+}
 
+static void jz4740_power_off(void)
+{
+        void __iomem *rtc_base = ioremap(JZ4740_RTC_BASE_ADDR, 0x38);
+        unsigned long wakeup_filter_ticks;
+        unsigned long reset_counter_ticks;
+
+        /*
+         * Set minimum wakeup pin assertion time: 100 ms.
+         * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
+         */
+        wakeup_filter_ticks = (100 * jz4740_clock_bdata.rtc_rate) / 1000;
+        if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
+                wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
+        else
+                wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
+        jz4740_rtc_wait_ready(rtc_base);
+        writel(wakeup_filter_ticks, rtc_base + JZ_REG_RTC_WAKEUP_FILTER);
+
+        /*
+         * Set reset pin low-level assertion time after wakeup: 60 ms.
+         * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
+         */
+        reset_counter_ticks = (60 * jz4740_clock_bdata.rtc_rate) / 1000;
+        if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
+                reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
+        else
+                reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
+        jz4740_rtc_wait_ready(rtc_base);
+        writel(reset_counter_ticks, rtc_base + JZ_REG_RTC_RESET_COUNTER);
+
+        jz4740_rtc_wait_ready(rtc_base);
         writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
+
         jz4740_halt();
 }
 
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f4630e1082a..1b51046191e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -190,6 +190,7 @@ void __init check_wait(void)
         case CPU_CAVIUM_OCTEON_PLUS:
         case CPU_CAVIUM_OCTEON2:
         case CPU_JZRISC:
+        case CPU_LOONGSON1:
         case CPU_XLR:
         case CPU_XLP:
                 cpu_wait = r4k_wait;
@@ -330,6 +331,154 @@ static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 #endif
 }
 
+static char unknown_isa[] __cpuinitdata = KERN_ERR \
+        "Unsupported ISA type, c0.config0: %d.";
+
+static inline unsigned int decode_config0(struct cpuinfo_mips *c)
+{
+        unsigned int config0;
+        int isa;
+
+        config0 = read_c0_config();
+
+        if (((config0 & MIPS_CONF_MT) >> 7) == 1)
+                c->options |= MIPS_CPU_TLB;
+        isa = (config0 & MIPS_CONF_AT) >> 13;
+        switch (isa) {
+        case 0:
+                switch ((config0 & MIPS_CONF_AR) >> 10) {
+                case 0:
+                        c->isa_level = MIPS_CPU_ISA_M32R1;
+                        break;
+                case 1:
+                        c->isa_level = MIPS_CPU_ISA_M32R2;
+                        break;
+                default:
+                        goto unknown;
+                }
+                break;
+        case 2:
+                switch ((config0 & MIPS_CONF_AR) >> 10) {
+                case 0:
+                        c->isa_level = MIPS_CPU_ISA_M64R1;
+                        break;
+                case 1:
+                        c->isa_level = MIPS_CPU_ISA_M64R2;
+                        break;
+                default:
+                        goto unknown;
+                }
+                break;
+        default:
+                goto unknown;
+        }
+
+        return config0 & MIPS_CONF_M;
+
+unknown:
+        panic(unknown_isa, config0);
+}
+
+static inline unsigned int decode_config1(struct cpuinfo_mips *c)
+{
+        unsigned int config1;
+
+        config1 = read_c0_config1();
+
+        if (config1 & MIPS_CONF1_MD)
+                c->ases |= MIPS_ASE_MDMX;
+        if (config1 & MIPS_CONF1_WR)
+                c->options |= MIPS_CPU_WATCH;
+        if (config1 & MIPS_CONF1_CA)
+                c->ases |= MIPS_ASE_MIPS16;
+        if (config1 & MIPS_CONF1_EP)
+                c->options |= MIPS_CPU_EJTAG;
+        if (config1 & MIPS_CONF1_FP) {
+                c->options |= MIPS_CPU_FPU;
+                c->options |= MIPS_CPU_32FPR;
+        }
+        if (cpu_has_tlb)
+                c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
+
+        return config1 & MIPS_CONF_M;
+}
+
+static inline unsigned int decode_config2(struct cpuinfo_mips *c)
+{
+        unsigned int config2;
+
+        config2 = read_c0_config2();
+
+        if (config2 & MIPS_CONF2_SL)
+                c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
+
+        return config2 & MIPS_CONF_M;
+}
+
+static inline unsigned int decode_config3(struct cpuinfo_mips *c)
+{
+        unsigned int config3;
+
+        config3 = read_c0_config3();
+
+        if (config3 & MIPS_CONF3_SM)
+                c->ases |= MIPS_ASE_SMARTMIPS;
+        if (config3 & MIPS_CONF3_DSP)
+                c->ases |= MIPS_ASE_DSP;
+        if (config3 & MIPS_CONF3_VINT)
+                c->options |= MIPS_CPU_VINT;
+        if (config3 & MIPS_CONF3_VEIC)
+                c->options |= MIPS_CPU_VEIC;
+        if (config3 & MIPS_CONF3_MT)
+                c->ases |= MIPS_ASE_MIPSMT;
+        if (config3 & MIPS_CONF3_ULRI)
+                c->options |= MIPS_CPU_ULRI;
+
+        return config3 & MIPS_CONF_M;
+}
+
+static inline unsigned int decode_config4(struct cpuinfo_mips *c)
+{
+        unsigned int config4;
+
+        config4 = read_c0_config4();
+
+        if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
+            && cpu_has_tlb)
+                c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
+
+        c->kscratch_mask = (config4 >> 16) & 0xff;
+
+        return config4 & MIPS_CONF_M;
+}
+
+static void __cpuinit decode_configs(struct cpuinfo_mips *c)
+{
+        int ok;
+
+        /* MIPS32 or MIPS64 compliant CPU.  */
+        c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
+                     MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
+
+        c->scache.flags = MIPS_CACHE_NOT_PRESENT;
+
+        ok = decode_config0(c);                 /* Read Config registers.  */
+        BUG_ON(!ok);                            /* Arch spec violation!  */
+        if (ok)
+                ok = decode_config1(c);
+        if (ok)
+                ok = decode_config2(c);
+        if (ok)
+                ok = decode_config3(c);
+        if (ok)
+                ok = decode_config4(c);
+
+        mips_probe_watch_registers(c);
+
+        if (cpu_has_mips_r2)
+                c->core = read_c0_ebase() & 0x3ff;
+}
+
 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
                 | MIPS_CPU_COUNTER)
 
@@ -638,155 +787,19 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                              MIPS_CPU_32FPR;
                 c->tlbsize = 64;
                 break;
-        }
-}
-
-static char unknown_isa[] __cpuinitdata = KERN_ERR \
-        "Unsupported ISA type, c0.config0: %d.";
+        case PRID_IMP_LOONGSON1:
+                decode_configs(c);
 
-static inline unsigned int decode_config0(struct cpuinfo_mips *c)
-{
-        unsigned int config0;
-        int isa;
+                c->cputype = CPU_LOONGSON1;
 
-        config0 = read_c0_config();
-
-        if (((config0 & MIPS_CONF_MT) >> 7) == 1)
-                c->options |= MIPS_CPU_TLB;
-        isa = (config0 & MIPS_CONF_AT) >> 13;
-        switch (isa) {
-        case 0:
-                switch ((config0 & MIPS_CONF_AR) >> 10) {
-                case 0:
-                        c->isa_level = MIPS_CPU_ISA_M32R1;
-                        break;
-                case 1:
-                        c->isa_level = MIPS_CPU_ISA_M32R2;
+                switch (c->processor_id & PRID_REV_MASK) {
+                case PRID_REV_LOONGSON1B:
+                        __cpu_name[cpu] = "Loongson 1B";
                         break;
-                default:
-                        goto unknown;
                 }
-                break;
-        case 2:
-                switch ((config0 & MIPS_CONF_AR) >> 10) {
-                case 0:
-                        c->isa_level = MIPS_CPU_ISA_M64R1;
-                        break;
-                case 1:
-                        c->isa_level = MIPS_CPU_ISA_M64R2;
-                        break;
-                default:
-                        goto unknown;
-                }
-                break;
-        default:
-                goto unknown;
-        }
-
-        return config0 & MIPS_CONF_M;
-
-unknown:
-        panic(unknown_isa, config0);
-}
 
-static inline unsigned int decode_config1(struct cpuinfo_mips *c)
-{
-        unsigned int config1;
-
-        config1 = read_c0_config1();
-
-        if (config1 & MIPS_CONF1_MD)
-                c->ases |= MIPS_ASE_MDMX;
-        if (config1 & MIPS_CONF1_WR)
-                c->options |= MIPS_CPU_WATCH;
-        if (config1 & MIPS_CONF1_CA)
-                c->ases |= MIPS_ASE_MIPS16;
-        if (config1 & MIPS_CONF1_EP)
-                c->options |= MIPS_CPU_EJTAG;
-        if (config1 & MIPS_CONF1_FP) {
-                c->options |= MIPS_CPU_FPU;
-                c->options |= MIPS_CPU_32FPR;
+                break;
         }
-        if (cpu_has_tlb)
-                c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
-
-        return config1 & MIPS_CONF_M;
-}
-
-static inline unsigned int decode_config2(struct cpuinfo_mips *c)
-{
-        unsigned int config2;
-
-        config2 = read_c0_config2();
-
-        if (config2 & MIPS_CONF2_SL)
-                c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
-
-        return config2 & MIPS_CONF_M;
-}
-
-static inline unsigned int decode_config3(struct cpuinfo_mips *c)
-{
-        unsigned int config3;
-
-        config3 = read_c0_config3();
-
-        if (config3 & MIPS_CONF3_SM)
-                c->ases |= MIPS_ASE_SMARTMIPS;
-        if (config3 & MIPS_CONF3_DSP)
-                c->ases |= MIPS_ASE_DSP;
-        if (config3 & MIPS_CONF3_VINT)
-                c->options |= MIPS_CPU_VINT;
-        if (config3 & MIPS_CONF3_VEIC)
-                c->options |= MIPS_CPU_VEIC;
-        if (config3 & MIPS_CONF3_MT)
-                c->ases |= MIPS_ASE_MIPSMT;
-        if (config3 & MIPS_CONF3_ULRI)
-                c->options |= MIPS_CPU_ULRI;
-
-        return config3 & MIPS_CONF_M;
-}
-
-static inline unsigned int decode_config4(struct cpuinfo_mips *c)
-{
-        unsigned int config4;
-
-        config4 = read_c0_config4();
-
-        if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
-            && cpu_has_tlb)
-                c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
-
-        c->kscratch_mask = (config4 >> 16) & 0xff;
-
-        return config4 & MIPS_CONF_M;
-}
-
-static void __cpuinit decode_configs(struct cpuinfo_mips *c)
-{
-        int ok;
-
-        /* MIPS32 or MIPS64 compliant CPU.  */
-        c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
-                     MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
-
-        c->scache.flags = MIPS_CACHE_NOT_PRESENT;
-
-        ok = decode_config0(c);                 /* Read Config registers.  */
-        BUG_ON(!ok);                            /* Arch spec violation!  */
-        if (ok)
-                ok = decode_config1(c);
-        if (ok)
-                ok = decode_config2(c);
-        if (ok)
-                ok = decode_config3(c);
-        if (ok)
-                ok = decode_config4(c);
-
-        mips_probe_watch_registers(c);
-
-        if (cpu_has_mips_r2)
-                c->core = read_c0_ebase() & 0x3ff;
 }
 
 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
diff --git a/arch/mips/kernel/cpufreq/Makefile b/arch/mips/kernel/cpufreq/Makefile
index c3479a432ef..05a5715ee38 100644
--- a/arch/mips/kernel/cpufreq/Makefile
+++ b/arch/mips/kernel/cpufreq/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the Linux/MIPS cpufreq.
 #
 
-obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o loongson2_clock.o
+obj-$(CONFIG_LOONGSON2_CPUFREQ) += loongson2_cpufreq.o
diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
index ae5db206347..e7c98e2b78b 100644
--- a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
+++ b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
@@ -19,7 +19,7 @@
 
 #include <asm/clock.h>
 
-#include <loongson.h>
+#include <asm/mach-loongson/loongson.h>
 
 static uint nowait;
 
@@ -181,6 +181,25 @@ static struct platform_driver platform_driver = {
         .id_table = platform_device_ids,
 };
 
+/*
+ * This is the simple version of Loongson-2 wait, Maybe we need do this in
+ * interrupt disabled context.
+ */
+
+static DEFINE_SPINLOCK(loongson2_wait_lock);
+
+static void loongson2_cpu_wait(void)
+{
+        unsigned long flags;
+        u32 cpu_freq;
+
+        spin_lock_irqsave(&loongson2_wait_lock, flags);
+        cpu_freq = LOONGSON_CHIPCFG0;
+        LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
+        LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */
+        spin_unlock_irqrestore(&loongson2_wait_lock, flags);
+}
+
 static int __init cpufreq_init(void)
 {
         int ret;
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index 84d0639e458..b77f56bbb47 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -323,7 +323,7 @@ static void sp_cleanup(void)
         fdt = files_fdtable(files);
         for (;;) {
                 unsigned long set;
-                i = j * __NFDBITS;
+                i = j * BITS_PER_LONG;
                 if (i >= fdt->max_fds)
                         break;
                 set = fdt->open_fds[j++];
diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index a5066b1c3de..4f8c3cba8c0 100644
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -39,8 +39,6 @@ struct mips_hi16 {
         Elf_Addr value;
 };
 
-static struct mips_hi16 *mips_hi16_list;
-
 static LIST_HEAD(dbe_list);
 static DEFINE_SPINLOCK(dbe_lock);
 
@@ -128,8 +126,8 @@ static int apply_r_mips_hi16_rel(struct module *me, u32 *location, Elf_Addr v)
 
         n->addr = (Elf_Addr *)location;
         n->value = v;
-        n->next = mips_hi16_list;
-        mips_hi16_list = n;
+        n->next = me->arch.r_mips_hi16_list;
+        me->arch.r_mips_hi16_list = n;
 
         return 0;
 }
@@ -142,18 +140,28 @@ static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v)
         return 0;
 }
 
+static void free_relocation_chain(struct mips_hi16 *l)
+{
+        struct mips_hi16 *next;
+
+        while (l) {
+                next = l->next;
+                kfree(l);
+                l = next;
+        }
+}
+
 static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
 {
         unsigned long insnlo = *location;
+        struct mips_hi16 *l;
         Elf_Addr val, vallo;
 
         /* Sign extend the addend we extract from the lo insn.  */
         vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
 
-        if (mips_hi16_list != NULL) {
-                struct mips_hi16 *l;
-
-                l = mips_hi16_list;
+        if (me->arch.r_mips_hi16_list != NULL) {
+                l = me->arch.r_mips_hi16_list;
                 while (l != NULL) {
                         struct mips_hi16 *next;
                         unsigned long insn;
@@ -188,7 +196,7 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
                         l = next;
                 }
 
-                mips_hi16_list = NULL;
+                me->arch.r_mips_hi16_list = NULL;
         }
 
         /*
@@ -201,6 +209,9 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
         return 0;
 
 out_danger:
+        free_relocation_chain(l);
+        me->arch.r_mips_hi16_list = NULL;
+
         pr_err("module %s: dangerous R_MIPS_LO16 REL relocation\n", me->name);
 
         return -ENOEXEC;
@@ -273,6 +284,7 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
         pr_debug("Applying relocate section %u to %u\n", relsec,
                sechdrs[relsec].sh_info);
 
+        me->arch.r_mips_hi16_list = NULL;
         for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
                 /* This is where to make the change */
                 location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
@@ -296,6 +308,19 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
                         return res;
         }
 
+        /*
+         * Normally the hi16 list should be deallocated at this point.  A
+         * malformed binary however could contain a series of R_MIPS_HI16
+         * relocations not followed by a R_MIPS_LO16 relocation.  In that
+         * case, free up the list and return an error.
+         */
+        if (me->arch.r_mips_hi16_list) {
+                free_relocation_chain(me->arch.r_mips_hi16_list);
+                me->arch.r_mips_hi16_list = NULL;
+
+                return -ENOEXEC;
+        }
+
         return 0;
 }
 
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index eb5e394a465..2f28d3b5568 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1559,6 +1559,11 @@ init_hw_perf_events(void)
                 mipspmu.general_event_map = &mipsxxcore_event_map;
                 mipspmu.cache_event_map = &mipsxxcore_cache_map;
                 break;
+        case CPU_LOONGSON1:
+                mipspmu.name = "mips/loongson1";
+                mipspmu.general_event_map = &mipsxxcore_event_map;
+                mipspmu.cache_event_map = &mipsxxcore_cache_map;
+                break;
         case CPU_CAVIUM_OCTEON:
         case CPU_CAVIUM_OCTEON_PLUS:
         case CPU_CAVIUM_OCTEON2:
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index f11b2bbb826..028f6f837ef 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -35,16 +35,6 @@ void __init early_init_dt_add_memory_arch(u64 base, u64 size)
         return add_memory_region(base, size, BOOT_MEM_RAM);
 }
 
-int __init reserve_mem_mach(unsigned long addr, unsigned long size)
-{
-        return reserve_bootmem(addr, size, BOOTMEM_DEFAULT);
-}
-
-void __init free_mem_mach(unsigned long addr, unsigned long size)
-{
-        return free_bootmem(addr, size);
-}
-
 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
 {
         return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
@@ -77,25 +67,6 @@ void __init early_init_devtree(void *params)
         of_scan_flat_dt(early_init_dt_scan_memory_arch, NULL);
 }
 
-void __init device_tree_init(void)
-{
-        unsigned long base, size;
-
-        if (!initial_boot_params)
-                return;
-
-        base = virt_to_phys((void *)initial_boot_params);
-        size = be32_to_cpu(initial_boot_params->totalsize);
-
-        /* Before we do anything, lets reserve the dt blob */
-        reserve_mem_mach(base, size);
-
-        unflatten_device_tree();
-
-        /* free the space reserved for the dt blob */
-        free_mem_mach(base, size);
-}
-
 void __init __dt_setup_arch(struct boot_param_header *bph)
 {
         if (be32_to_cpu(bph->magic) != OF_DT_HEADER) {
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 1268392f1d2..9005bf9fb85 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -102,7 +102,9 @@ asmlinkage __cpuinit void start_secondary(void)
 
 #ifdef CONFIG_MIPS_MT_SMTC
         /* Only do cpu_probe for first TC of CPU */
-        if ((read_c0_tcbind() & TCBIND_CURTC) == 0)
+        if ((read_c0_tcbind() & TCBIND_CURTC) != 0)
+                __cpu_name[smp_processor_id()] = __cpu_name[0];
+        else
 #endif /* CONFIG_MIPS_MT_SMTC */
         cpu_probe();
         cpu_report();
@@ -128,7 +130,7 @@ asmlinkage __cpuinit void start_secondary(void)
 
         cpu_set(cpu, cpu_callin_map);
 
-        synchronise_count_slave();
+        synchronise_count_slave(cpu);
 
         /*
          * irq will be enabled in ->smp_finish(), enabling it too early
@@ -171,7 +173,6 @@ void smp_send_stop(void)
 void __init smp_cpus_done(unsigned int max_cpus)
 {
         mp_ops->cpus_done();
-        synchronise_count_master();
 }
 
 /* called from main before smp_init() */
@@ -204,6 +205,7 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
         while (!cpu_isset(cpu, cpu_callin_map))
                 udelay(100);
 
+        synchronise_count_master(cpu);
         return 0;
 }
 
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 15b5f3cfd20..1d47843d3cc 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -86,6 +86,13 @@ struct smtc_ipi_q IPIQ[NR_CPUS];
 static struct smtc_ipi_q freeIPIq;
 
 
+/*
+ * Number of FPU contexts for each VPE
+ */
+
+static int smtc_nconf1[MAX_SMTC_VPES];
+
+
 /* Forward declarations */
 
 void ipi_decode(struct smtc_ipi *);
@@ -174,9 +181,9 @@ static int __init tintq(char *str)
 
 __setup("tintq=", tintq);
 
-static int imstuckcount[2][8];
+static int imstuckcount[MAX_SMTC_VPES][8];
 /* vpemask represents IM/IE bits of per-VPE Status registers, low-to-high */
-static int vpemask[2][8] = {
+static int vpemask[MAX_SMTC_VPES][8] = {
         {0, 0, 1, 0, 0, 0, 0, 1},
         {0, 0, 0, 0, 0, 0, 0, 1}
 };
@@ -331,6 +338,22 @@ int __init smtc_build_cpu_map(int start_cpu_slot)
 
 static void smtc_tc_setup(int vpe, int tc, int cpu)
 {
+        static int cp1contexts[MAX_SMTC_VPES];
+
+        /*
+         * Make a local copy of the available FPU contexts in order
+         * to keep track of TCs that can have one.
+         */
+        if (tc == 1)
+        {
+                /*
+                 * FIXME: Multi-core SMTC hasn't been tested and the
+                 *        maximum number of VPEs may change.
+                 */
+                cp1contexts[0] = smtc_nconf1[0] - 1;
+                cp1contexts[1] = smtc_nconf1[1];
+        }
+
         settc(tc);
         write_tc_c0_tchalt(TCHALT_H);
         mips_ihb();
@@ -343,22 +366,29 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
          * an active IPI queue.
          */
         write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
-        /* Bind tc to vpe */
+
+        /* Bind TC to VPE. */
         write_tc_c0_tcbind(vpe);
+
         /* In general, all TCs should have the same cpu_data indications. */
         memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
-        /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
-        if (cpu_data[0].cputype == CPU_34K ||
-            cpu_data[0].cputype == CPU_1004K)
+
+        /* Check to see if there is a FPU context available for this TC. */
+        if (!cp1contexts[vpe])
                 cpu_data[cpu].options &= ~MIPS_CPU_FPU;
+        else
+                cp1contexts[vpe]--;
+
+        /* Store the TC and VPE into the cpu_data structure. */
         cpu_data[cpu].vpe_id = vpe;
         cpu_data[cpu].tc_id = tc;
-        /* Multi-core SMTC hasn't been tested, but be prepared */
+
+        /* FIXME: Multi-core SMTC hasn't been tested, but be prepared. */
         cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff;
 }
 
 /*
- * Tweak to get Count registes in as close a sync as possible.  The
+ * Tweak to get Count registers synced as closely as possible. The
  * value seems good for 34K-class cores.
  */
 
@@ -466,6 +496,24 @@ void smtc_prepare_cpus(int cpus)
         smtc_configure_tlb();
 
         for (tc = 0, vpe = 0 ; (vpe < nvpe) && (tc < ntc) ; vpe++) {
+                /* Get number of CP1 contexts for each VPE. */
+                if (tc == 0)
+                {
+                        /*
+                         * Do not call settc() for TC0 or the FPU context
+                         * value will be incorrect. Besides, we know that
+                         * we are TC0 anyway.
+                         */
+                        smtc_nconf1[0] = ((read_vpe_c0_vpeconf1() &
+                                VPECONF1_NCP1) >> VPECONF1_NCP1_SHIFT);
+                        if (nvpe == 2)
+                        {
+                                settc(1);
+                                smtc_nconf1[1] = ((read_vpe_c0_vpeconf1() &
+                                        VPECONF1_NCP1) >> VPECONF1_NCP1_SHIFT);
+                                settc(0);
+                        }
+                }
                 if (tcpervpe[vpe] == 0)
                         continue;
                 if (vpe != 0)
@@ -479,6 +527,18 @@ void smtc_prepare_cpus(int cpus)
                          */
                         if (tc != 0) {
                                 smtc_tc_setup(vpe, tc, cpu);
+                                if (vpe != 0) {
+                                        /*
+                                         * Set MVP bit (possibly again).  Do it
+                                         * here to catch CPUs that have no TCs
+                                         * bound to the VPE at reset.  In that
+                                         * case, a TC must be bound to the VPE
+                                         * before we can set VPEControl[MVP]
+                                         */
+                                        write_vpe_c0_vpeconf0(
+                                                read_vpe_c0_vpeconf0() |
+                                                VPECONF0_MVP);
+                                }
                                 cpu++;
                         }
                         printk(" %d", tc);
diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c
index 842d55e411f..7f1eca3858d 100644
--- a/arch/mips/kernel/sync-r4k.c
+++ b/arch/mips/kernel/sync-r4k.c
@@ -28,12 +28,11 @@ static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0);
 #define COUNTON 100
 #define NR_LOOPS 5
 
-void __cpuinit synchronise_count_master(void)
+void __cpuinit synchronise_count_master(int cpu)
 {
         int i;
         unsigned long flags;
         unsigned int initcount;
-        int nslaves;
 
 #ifdef CONFIG_MIPS_MT_SMTC
         /*
@@ -43,8 +42,7 @@ void __cpuinit synchronise_count_master(void)
         return;
 #endif
 
-        printk(KERN_INFO "Synchronize counters across %u CPUs: ",
-               num_online_cpus());
+        printk(KERN_INFO "Synchronize counters for CPU %u: ", cpu);
 
         local_irq_save(flags);
 
@@ -52,7 +50,7 @@ void __cpuinit synchronise_count_master(void)
          * Notify the slaves that it's time to start
          */
         atomic_set(&count_reference, read_c0_count());
-        atomic_set(&count_start_flag, 1);
+        atomic_set(&count_start_flag, cpu);
         smp_wmb();
 
         /* Count will be initialised to current timer for all CPU's */
@@ -69,10 +67,9 @@ void __cpuinit synchronise_count_master(void)
          * two CPUs.
          */
 
-        nslaves = num_online_cpus()-1;
         for (i = 0; i < NR_LOOPS; i++) {
-                /* slaves loop on '!= ncpus' */
-                while (atomic_read(&count_count_start) != nslaves)
+                /* slaves loop on '!= 2' */
+                while (atomic_read(&count_count_start) != 1)
                         mb();
                 atomic_set(&count_count_stop, 0);
                 smp_wmb();
@@ -89,7 +86,7 @@ void __cpuinit synchronise_count_master(void)
                 /*
                  * Wait for all slaves to leave the synchronization point:
                  */
-                while (atomic_read(&count_count_stop) != nslaves)
+                while (atomic_read(&count_count_stop) != 1)
                         mb();
                 atomic_set(&count_count_start, 0);
                 smp_wmb();
@@ -97,6 +94,7 @@ void __cpuinit synchronise_count_master(void)
         }
         /* Arrange for an interrupt in a short while */
         write_c0_compare(read_c0_count() + COUNTON);
+        atomic_set(&count_start_flag, 0);
 
         local_irq_restore(flags);
 
@@ -108,11 +106,10 @@ void __cpuinit synchronise_count_master(void)
         printk("done.\n");
 }
 
-void __cpuinit synchronise_count_slave(void)
+void __cpuinit synchronise_count_slave(int cpu)
 {
         int i;
         unsigned int initcount;
-        int ncpus;
 
 #ifdef CONFIG_MIPS_MT_SMTC
         /*
@@ -127,16 +124,15 @@ void __cpuinit synchronise_count_slave(void)
          * so we first wait for the master to say everyone is ready
          */
 
-        while (!atomic_read(&count_start_flag))
+        while (atomic_read(&count_start_flag) != cpu)
                 mb();
 
         /* Count will be initialised to next expire for all CPU's */
         initcount = atomic_read(&count_reference);
 
-        ncpus = num_online_cpus();
         for (i = 0; i < NR_LOOPS; i++) {
                 atomic_inc(&count_count_start);
-                while (atomic_read(&count_count_start) != ncpus)
+                while (atomic_read(&count_count_start) != 2)
                         mb();
 
                 /*
@@ -146,7 +142,7 @@ void __cpuinit synchronise_count_slave(void)
                         write_c0_count(initcount);
 
                 atomic_inc(&count_count_stop);
-                while (atomic_read(&count_count_stop) != ncpus)
+                while (atomic_read(&count_count_stop) != 2)
                         mb();
         }
         /* Arrange for an interrupt in a short while */
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index c3c29354370..9be3df1fa8a 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1253,6 +1253,7 @@ static inline void parity_protection_init(void)
 
         case CPU_5KC:
         case CPU_5KE:
+        case CPU_LOONGSON1:
                 write_c0_ecc(0x80000000);
                 back_to_back_c0_hazard();
                 /* Set the PE bit (bit 31) in the c0_errctl register. */
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index d3bcc33f469..ce2f129b081 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -135,6 +135,11 @@ void clk_deactivate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_deactivate);
 
+struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec)
+{
+        return NULL;
+}
+
 static inline u32 get_counter_resolution(void)
 {
         u32 res;
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index d185e8477fd..6cfd6117fbf 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -8,7 +8,10 @@
 
 #include <linux/export.h>
 #include <linux/clk.h>
+#include <linux/bootmem.h>
 #include <linux/of_platform.h>
+#include <linux/of_fdt.h>
+
 #include <asm/bootinfo.h>
 #include <asm/time.h>
 
@@ -70,6 +73,25 @@ void __init plat_mem_setup(void)
         __dt_setup_arch(&__dtb_start);
 }
 
+void __init device_tree_init(void)
+{
+        unsigned long base, size;
+
+        if (!initial_boot_params)
+                return;
+
+        base = virt_to_phys((void *)initial_boot_params);
+        size = be32_to_cpu(initial_boot_params->totalsize);
+
+        /* Before we do anything, lets reserve the dt blob */
+        reserve_bootmem(base, size, BOOTMEM_DEFAULT);
+
+        unflatten_device_tree();
+
+        /* free the space reserved for the dt blob */
+        free_bootmem(base, size);
+}
+
 void __init prom_init(void)
 {
         /* call the soc specific detetcion code and get it to fill soc_info */
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 83780f7c842..befbb760ab7 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -20,10 +20,12 @@
 
 /* clock control register */
 #define CGU_IFCCR       0x0018
+#define CGU_IFCCR_VR9   0x0024
 /* system clock register */
 #define CGU_SYS         0x0010
 /* pci control register */
 #define CGU_PCICR       0x0034
+#define CGU_PCICR_VR9   0x0038
 /* ephy configuration register */
 #define CGU_EPHY        0x10
 /* power control register */
@@ -80,6 +82,9 @@ static void __iomem *pmu_membase;
 void __iomem *ltq_cgu_membase;
 void __iomem *ltq_ebu_membase;
 
+static u32 ifccr = CGU_IFCCR;
+static u32 pcicr = CGU_PCICR;
+
 /* legacy function kept alive to ease clkdev transition */
 void ltq_pmu_enable(unsigned int module)
 {
@@ -103,14 +108,14 @@ EXPORT_SYMBOL(ltq_pmu_disable);
 /* enable a hw clock */
 static int cgu_enable(struct clk *clk)
 {
-        ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR);
+        ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
         return 0;
 }
 
 /* disable a hw clock */
 static void cgu_disable(struct clk *clk)
 {
-        ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR);
+        ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
 }
 
 /* enable a clock gate */
@@ -138,22 +143,22 @@ static void pmu_disable(struct clk *clk)
 /* the pci enable helper */
 static int pci_enable(struct clk *clk)
 {
-        unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
+        unsigned int val = ltq_cgu_r32(ifccr);
         /* set bus clock speed */
         if (of_machine_is_compatible("lantiq,ar9")) {
-                ifccr &= ~0x1f00000;
+                val &= ~0x1f00000;
                 if (clk->rate == CLOCK_33M)
-                        ifccr |= 0xe00000;
+                        val |= 0xe00000;
                 else
-                        ifccr |= 0x700000; /* 62.5M */
+                        val |= 0x700000; /* 62.5M */
         } else {
-                ifccr &= ~0xf00000;
+                val &= ~0xf00000;
                 if (clk->rate == CLOCK_33M)
-                        ifccr |= 0x800000;
+                        val |= 0x800000;
                 else
-                        ifccr |= 0x400000; /* 62.5M */
+                        val |= 0x400000; /* 62.5M */
         }
-        ltq_cgu_w32(ifccr, CGU_IFCCR);
+        ltq_cgu_w32(val, ifccr);
         pmu_enable(clk);
         return 0;
 }
@@ -161,18 +166,16 @@ static int pci_enable(struct clk *clk)
 /* enable the external clock as a source */
 static int pci_ext_enable(struct clk *clk)
 {
-        ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16),
-                CGU_IFCCR);
-        ltq_cgu_w32((1 << 30), CGU_PCICR);
+        ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
+        ltq_cgu_w32((1 << 30), pcicr);
         return 0;
 }
 
 /* disable the external clock as a source */
 static void pci_ext_disable(struct clk *clk)
 {
-        ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
-                CGU_IFCCR);
-        ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
+        ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
+        ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
 }
 
 /* enable a clockout source */
@@ -184,11 +187,11 @@ static int clkout_enable(struct clk *clk)
         for (i = 0; i < 4; i++) {
                 if (clk->rates[i] == clk->rate) {
                         int shift = 14 - (2 * clk->module);
-                        unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
+                        unsigned int val = ltq_cgu_r32(ifccr);
 
-                        ifccr &= ~(3 << shift);
-                        ifccr |= i << shift;
-                        ltq_cgu_w32(ifccr, CGU_IFCCR);
+                        val &= ~(3 << shift);
+                        val |= i << shift;
+                        ltq_cgu_w32(val, ifccr);
                         return 0;
                 }
         }
@@ -336,8 +339,12 @@ void __init ltq_soc_init(void)
         clkdev_add_clkout();
 
         /* add the soc dependent clocks */
-        if (!of_machine_is_compatible("lantiq,vr9"))
+        if (of_machine_is_compatible("lantiq,vr9")) {
+                ifccr = CGU_IFCCR_VR9;
+                pcicr = CGU_PCICR_VR9;
+        } else {
                 clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);
+        }
 
         if (!of_machine_is_compatible("lantiq,ase")) {
                 clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 2a7c74fc15f..399a50a541d 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -2,7 +2,7 @@
 # Makefile for MIPS-specific library files..
 #
 
-lib-y   += csum_partial.o delay.o memcpy.o memcpy-inatomic.o memset.o \
+lib-y   += csum_partial.o delay.o memcpy.o memset.o \
            strlen_user.o strncpy_user.o strnlen_user.o uncached.o
 
 obj-y                   += iomap.o
diff --git a/arch/mips/lib/memcpy-inatomic.S b/arch/mips/lib/memcpy-inatomic.S
deleted file mode 100644
index 68853a038d3..00000000000
--- a/arch/mips/lib/memcpy-inatomic.S
+++ /dev/null
@@ -1,451 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Unified implementation of memcpy, memmove and the __copy_user backend.
- *
- * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org)
- * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
- * Copyright (C) 2002 Broadcom, Inc.
- *   memcpy/copy_user author: Mark Vandevoorde
- * Copyright (C) 2007  Maciej W. Rozycki
- *
- * Mnemonic names for arguments to memcpy/__copy_user
- */
-
-/*
- * Hack to resolve longstanding prefetch issue
- *
- * Prefetching may be fatal on some systems if we're prefetching beyond the
- * end of memory on some systems.  It's also a seriously bad idea on non
- * dma-coherent systems.
- */
-#ifdef CONFIG_DMA_NONCOHERENT
-#undef CONFIG_CPU_HAS_PREFETCH
-#endif
-#ifdef CONFIG_MIPS_MALTA
-#undef CONFIG_CPU_HAS_PREFETCH
-#endif
-
-#include <asm/asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/regdef.h>
-
-#define dst a0
-#define src a1
-#define len a2
-
-/*
- * Spec
- *
- * memcpy copies len bytes from src to dst and sets v0 to dst.
- * It assumes that
- *   - src and dst don't overlap
- *   - src is readable
- *   - dst is writable
- * memcpy uses the standard calling convention
- *
- * __copy_user copies up to len bytes from src to dst and sets a2 (len) to
- * the number of uncopied bytes due to an exception caused by a read or write.
- * __copy_user assumes that src and dst don't overlap, and that the call is
- * implementing one of the following:
- *   copy_to_user
- *     - src is readable  (no exceptions when reading src)
- *   copy_from_user
- *     - dst is writable  (no exceptions when writing dst)
- * __copy_user uses a non-standard calling convention; see
- * include/asm-mips/uaccess.h
- *
- * When an exception happens on a load, the handler must
- # ensure that all of the destination buffer is overwritten to prevent
- * leaking information to user mode programs.
- */
-
-/*
- * Implementation
- */
-
-/*
- * The exception handler for loads requires that:
- *  1- AT contain the address of the byte just past the end of the source
- *     of the copy,
- *  2- src_entry <= src < AT, and
- *  3- (dst - src) == (dst_entry - src_entry),
- * The _entry suffix denotes values when __copy_user was called.
- *
- * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user
- * (2) is met by incrementing src by the number of bytes copied
- * (3) is met by not doing loads between a pair of increments of dst and src
- *
- * The exception handlers for stores adjust len (if necessary) and return.
- * These handlers do not need to overwrite any data.
- *
- * For __rmemcpy and memmove an exception is always a kernel bug, therefore
- * they're not protected.
- */
-
-#define EXC(inst_reg,addr,handler)              \
-9:      inst_reg, addr;                         \
-        .section __ex_table,"a";                \
-        PTR     9b, handler;                    \
-        .previous
-
-/*
- * Only on the 64-bit kernel we can made use of 64-bit registers.
- */
-#ifdef CONFIG_64BIT
-#define USE_DOUBLE
-#endif
-
-#ifdef USE_DOUBLE
-
-#define LOAD   ld
-#define LOADL  ldl
-#define LOADR  ldr
-#define STOREL sdl
-#define STORER sdr
-#define STORE  sd
-#define ADD    daddu
-#define SUB    dsubu
-#define SRL    dsrl
-#define SRA    dsra
-#define SLL    dsll
-#define SLLV   dsllv
-#define SRLV   dsrlv
-#define NBYTES 8
-#define LOG_NBYTES 3
-
-/*
- * As we are sharing code base with the mips32 tree (which use the o32 ABI
- * register definitions). We need to redefine the register definitions from
- * the n64 ABI register naming to the o32 ABI register naming.
- */
-#undef t0
-#undef t1
-#undef t2
-#undef t3
-#define t0      $8
-#define t1      $9
-#define t2      $10
-#define t3      $11
-#define t4      $12
-#define t5      $13
-#define t6      $14
-#define t7      $15
-
-#else
-
-#define LOAD   lw
-#define LOADL  lwl
-#define LOADR  lwr
-#define STOREL swl
-#define STORER swr
-#define STORE  sw
-#define ADD    addu
-#define SUB    subu
-#define SRL    srl
-#define SLL    sll
-#define SRA    sra
-#define SLLV   sllv
-#define SRLV   srlv
-#define NBYTES 4
-#define LOG_NBYTES 2
-
-#endif /* USE_DOUBLE */
-
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-#define LDFIRST LOADR
-#define LDREST  LOADL
-#define STFIRST STORER
-#define STREST  STOREL
-#define SHIFT_DISCARD SLLV
-#else
-#define LDFIRST LOADL
-#define LDREST  LOADR
-#define STFIRST STOREL
-#define STREST  STORER
-#define SHIFT_DISCARD SRLV
-#endif
-
-#define FIRST(unit) ((unit)*NBYTES)
-#define REST(unit)  (FIRST(unit)+NBYTES-1)
-#define UNIT(unit)  FIRST(unit)
-
-#define ADDRMASK (NBYTES-1)
-
-        .text
-        .set    noreorder
-#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
-        .set    noat
-#else
-        .set    at=v1
-#endif
-
-/*
- * A combined memcpy/__copy_user
- * __copy_user sets len to 0 for success; else to an upper bound of
- * the number of uncopied bytes.
- * memcpy sets v0 to dst.
- */
-        .align  5
-LEAF(__copy_user_inatomic)
-        /*
-         * Note: dst & src may be unaligned, len may be 0
-         * Temps
-         */
-#define rem t8
-
-        /*
-         * The "issue break"s below are very approximate.
-         * Issue delays for dcache fills will perturb the schedule, as will
-         * load queue full replay traps, etc.
-         *
-         * If len < NBYTES use byte operations.
-         */
-        PREF(   0, 0(src) )
-        PREF(   1, 0(dst) )
-        sltu    t2, len, NBYTES
-        and     t1, dst, ADDRMASK
-        PREF(   0, 1*32(src) )
-        PREF(   1, 1*32(dst) )
-        bnez    t2, .Lcopy_bytes_checklen
-         and    t0, src, ADDRMASK
-        PREF(   0, 2*32(src) )
-        PREF(   1, 2*32(dst) )
-        bnez    t1, .Ldst_unaligned
-         nop
-        bnez    t0, .Lsrc_unaligned_dst_aligned
-        /*
-         * use delay slot for fall-through
-         * src and dst are aligned; need to compute rem
-         */
-.Lboth_aligned:
-         SRL    t0, len, LOG_NBYTES+3           # +3 for 8 units/iter
-        beqz    t0, .Lcleanup_both_aligned      # len < 8*NBYTES
-         and    rem, len, (8*NBYTES-1)          # rem = len % (8*NBYTES)
-        PREF(   0, 3*32(src) )
-        PREF(   1, 3*32(dst) )
-        .align  4
-1:
-EXC(    LOAD    t0, UNIT(0)(src),       .Ll_exc)
-EXC(    LOAD    t1, UNIT(1)(src),       .Ll_exc_copy)
-EXC(    LOAD    t2, UNIT(2)(src),       .Ll_exc_copy)
-EXC(    LOAD    t3, UNIT(3)(src),       .Ll_exc_copy)
-        SUB     len, len, 8*NBYTES
-EXC(    LOAD    t4, UNIT(4)(src),       .Ll_exc_copy)
-EXC(    LOAD    t7, UNIT(5)(src),       .Ll_exc_copy)
-        STORE   t0, UNIT(0)(dst)
-        STORE   t1, UNIT(1)(dst)
-EXC(    LOAD    t0, UNIT(6)(src),       .Ll_exc_copy)
-EXC(    LOAD    t1, UNIT(7)(src),       .Ll_exc_copy)
-        ADD     src, src, 8*NBYTES
-        ADD     dst, dst, 8*NBYTES
-        STORE   t2, UNIT(-6)(dst)
-        STORE   t3, UNIT(-5)(dst)
-        STORE   t4, UNIT(-4)(dst)
-        STORE   t7, UNIT(-3)(dst)
-        STORE   t0, UNIT(-2)(dst)
-        STORE   t1, UNIT(-1)(dst)
-        PREF(   0, 8*32(src) )
-        PREF(   1, 8*32(dst) )
-        bne     len, rem, 1b
-         nop
-
-        /*
-         * len == rem == the number of bytes left to copy < 8*NBYTES
-         */
-.Lcleanup_both_aligned:
-        beqz    len, .Ldone
-         sltu   t0, len, 4*NBYTES
-        bnez    t0, .Lless_than_4units
-         and    rem, len, (NBYTES-1)    # rem = len % NBYTES
-        /*
-         * len >= 4*NBYTES
-         */
-EXC(    LOAD    t0, UNIT(0)(src),       .Ll_exc)
-EXC(    LOAD    t1, UNIT(1)(src),       .Ll_exc_copy)
-EXC(    LOAD    t2, UNIT(2)(src),       .Ll_exc_copy)
-EXC(    LOAD    t3, UNIT(3)(src),       .Ll_exc_copy)
-        SUB     len, len, 4*NBYTES
-        ADD     src, src, 4*NBYTES
-        STORE   t0, UNIT(0)(dst)
-        STORE   t1, UNIT(1)(dst)
-        STORE   t2, UNIT(2)(dst)
-        STORE   t3, UNIT(3)(dst)
-        .set    reorder                         /* DADDI_WAR */
-        ADD     dst, dst, 4*NBYTES
-        beqz    len, .Ldone
-        .set    noreorder
-.Lless_than_4units:
-        /*
-         * rem = len % NBYTES
-         */
-        beq     rem, len, .Lcopy_bytes
-         nop
-1:
-EXC(    LOAD    t0, 0(src),             .Ll_exc)
-        ADD     src, src, NBYTES
-        SUB     len, len, NBYTES
-        STORE   t0, 0(dst)
-        .set    reorder                         /* DADDI_WAR */
-        ADD     dst, dst, NBYTES
-        bne     rem, len, 1b
-        .set    noreorder
-
-        /*
-         * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
-         * A loop would do only a byte at a time with possible branch
-         * mispredicts.  Can't do an explicit LOAD dst,mask,or,STORE
-         * because can't assume read-access to dst.  Instead, use
-         * STREST dst, which doesn't require read access to dst.
-         *
-         * This code should perform better than a simple loop on modern,
-         * wide-issue mips processors because the code has fewer branches and
-         * more instruction-level parallelism.
-         */
-#define bits t2
-        beqz    len, .Ldone
-         ADD    t1, dst, len    # t1 is just past last byte of dst
-        li      bits, 8*NBYTES
-        SLL     rem, len, 3     # rem = number of bits to keep
-EXC(    LOAD    t0, 0(src),             .Ll_exc)
-        SUB     bits, bits, rem # bits = number of bits to discard
-        SHIFT_DISCARD t0, t0, bits
-        STREST  t0, -1(t1)
-        jr      ra
-         move   len, zero
-.Ldst_unaligned:
-        /*
-         * dst is unaligned
-         * t0 = src & ADDRMASK
-         * t1 = dst & ADDRMASK; T1 > 0
-         * len >= NBYTES
-         *
-         * Copy enough bytes to align dst
-         * Set match = (src and dst have same alignment)
-         */
-#define match rem
-EXC(    LDFIRST t3, FIRST(0)(src),      .Ll_exc)
-        ADD     t2, zero, NBYTES
-EXC(    LDREST  t3, REST(0)(src),       .Ll_exc_copy)
-        SUB     t2, t2, t1      # t2 = number of bytes copied
-        xor     match, t0, t1
-        STFIRST t3, FIRST(0)(dst)
-        beq     len, t2, .Ldone
-         SUB    len, len, t2
-        ADD     dst, dst, t2
-        beqz    match, .Lboth_aligned
-         ADD    src, src, t2
-
-.Lsrc_unaligned_dst_aligned:
-        SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter
-        PREF(   0, 3*32(src) )
-        beqz    t0, .Lcleanup_src_unaligned
-         and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES
-        PREF(   1, 3*32(dst) )
-1:
-/*
- * Avoid consecutive LD*'s to the same register since some mips
- * implementations can't issue them in the same cycle.
- * It's OK to load FIRST(N+1) before REST(N) because the two addresses
- * are to the same unit (unless src is aligned, but it's not).
- */
-EXC(    LDFIRST t0, FIRST(0)(src),      .Ll_exc)
-EXC(    LDFIRST t1, FIRST(1)(src),      .Ll_exc_copy)
-        SUB     len, len, 4*NBYTES
-EXC(    LDREST  t0, REST(0)(src),       .Ll_exc_copy)
-EXC(    LDREST  t1, REST(1)(src),       .Ll_exc_copy)
-EXC(    LDFIRST t2, FIRST(2)(src),      .Ll_exc_copy)
-EXC(    LDFIRST t3, FIRST(3)(src),      .Ll_exc_copy)
-EXC(    LDREST  t2, REST(2)(src),       .Ll_exc_copy)
-EXC(    LDREST  t3, REST(3)(src),       .Ll_exc_copy)
-        PREF(   0, 9*32(src) )          # 0 is PREF_LOAD  (not streamed)
-        ADD     src, src, 4*NBYTES
-#ifdef CONFIG_CPU_SB1
-        nop                             # improves slotting
-#endif
-        STORE   t0, UNIT(0)(dst)
-        STORE   t1, UNIT(1)(dst)
-        STORE   t2, UNIT(2)(dst)
-        STORE   t3, UNIT(3)(dst)
-        PREF(   1, 9*32(dst) )          # 1 is PREF_STORE (not streamed)
-        .set    reorder                         /* DADDI_WAR */
-        ADD     dst, dst, 4*NBYTES
-        bne     len, rem, 1b
-        .set    noreorder
-
-.Lcleanup_src_unaligned:
-        beqz    len, .Ldone
-         and    rem, len, NBYTES-1  # rem = len % NBYTES
-        beq     rem, len, .Lcopy_bytes
-         nop
-1:
-EXC(    LDFIRST t0, FIRST(0)(src),      .Ll_exc)
-EXC(    LDREST  t0, REST(0)(src),       .Ll_exc_copy)
-        ADD     src, src, NBYTES
-        SUB     len, len, NBYTES
-        STORE   t0, 0(dst)
-        .set    reorder                         /* DADDI_WAR */
-        ADD     dst, dst, NBYTES
-        bne     len, rem, 1b
-        .set    noreorder
-
-.Lcopy_bytes_checklen:
-        beqz    len, .Ldone
-         nop
-.Lcopy_bytes:
-        /* 0 < len < NBYTES  */
-#define COPY_BYTE(N)                    \
-EXC(    lb      t0, N(src), .Ll_exc);   \
-        SUB     len, len, 1;            \
-        beqz    len, .Ldone;            \
-         sb     t0, N(dst)
-
-        COPY_BYTE(0)
-        COPY_BYTE(1)
-#ifdef USE_DOUBLE
-        COPY_BYTE(2)
-        COPY_BYTE(3)
-        COPY_BYTE(4)
-        COPY_BYTE(5)
-#endif
-EXC(    lb      t0, NBYTES-2(src), .Ll_exc)
-        SUB     len, len, 1
-        jr      ra
-         sb     t0, NBYTES-2(dst)
-.Ldone:
-        jr      ra
-         nop
-        END(__copy_user_inatomic)
-
-.Ll_exc_copy:
-        /*
-         * Copy bytes from src until faulting load address (or until a
-         * lb faults)
-         *
-         * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28)
-         * may be more than a byte beyond the last address.
-         * Hence, the lb below may get an exception.
-         *
-         * Assumes src < THREAD_BUADDR($28)
-         */
-        LOAD    t0, TI_TASK($28)
-         nop
-        LOAD    t0, THREAD_BUADDR(t0)
-1:
-EXC(    lb      t1, 0(src),     .Ll_exc)
-        ADD     src, src, 1
-        sb      t1, 0(dst)      # can't fault -- we're copy_from_user
-        .set    reorder                         /* DADDI_WAR */
-        ADD     dst, dst, 1
-        bne     src, t0, 1b
-        .set    noreorder
-.Ll_exc:
-        LOAD    t0, TI_TASK($28)
-         nop
-        LOAD    t0, THREAD_BUADDR(t0)   # t0 is just past last good address
-         nop
-        SUB     len, AT, t0             # len number of uncopied bytes
-        jr      ra
-         nop
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index 56a1f85a1ce..65192c06781 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -183,6 +183,14 @@
 #endif
 
 /*
+ * t6 is used as a flag to note inatomic mode.
+ */
+LEAF(__copy_user_inatomic)
+        b       __copy_user_common
+         li     t6, 1
+        END(__copy_user_inatomic)
+
+/*
  * A combined memcpy/__copy_user
  * __copy_user sets len to 0 for success; else to an upper bound of
  * the number of uncopied bytes.
@@ -193,6 +201,8 @@ LEAF(memcpy)					/* a0=dst a1=src a2=len */
         move    v0, dst                         /* return value */
 .L__memcpy:
 FEXPORT(__copy_user)
+        li      t6, 0   /* not inatomic */
+__copy_user_common:
         /*
          * Note: dst & src may be unaligned, len may be 0
          * Temps
@@ -458,6 +468,7 @@ EXC(	lb	t1, 0(src),	.Ll_exc)
         LOAD    t0, THREAD_BUADDR(t0)   # t0 is just past last good address
          nop
         SUB     len, AT, t0             # len number of uncopied bytes
+        bnez    t6, .Ldone      /* Skip the zeroing part if inatomic */
         /*
          * Here's where we rely on src and dst being incremented in tandem,
          *   See (3) above.
diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig
index aca93eed877..263beb9322a 100644
--- a/arch/mips/loongson/Kconfig
+++ b/arch/mips/loongson/Kconfig
@@ -41,6 +41,7 @@ config LEMOTE_MACH2F
         select CSRC_R4K if ! MIPS_EXTERNAL_TIMER
         select DMA_NONCOHERENT
         select GENERIC_ISA_DMA_SUPPORT_BROKEN
+        select HAVE_CLK
         select HW_HAS_PCI
         select I8259
         select IRQ_CPU
diff --git a/arch/mips/loongson/lemote-2f/Makefile b/arch/mips/loongson/lemote-2f/Makefile
index 8699a53f047..4f9eaa328a1 100644
--- a/arch/mips/loongson/lemote-2f/Makefile
+++ b/arch/mips/loongson/lemote-2f/Makefile
@@ -2,7 +2,7 @@
 # Makefile for lemote loongson2f family machines
 #
 
-obj-y += machtype.o irq.o reset.o ec_kb3310b.o
+obj-y += clock.o machtype.o irq.o reset.o ec_kb3310b.o
 
 #
 # Suspend Support
diff --git a/arch/mips/kernel/cpufreq/loongson2_clock.c b/arch/mips/loongson/lemote-2f/clock.c
index 5426779d9fd..bc739d4bab2 100644
--- a/arch/mips/kernel/cpufreq/loongson2_clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -6,14 +6,17 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
-
-#include <linux/module.h>
+#include <linux/clk.h>
 #include <linux/cpufreq.h>
-#include <linux/platform_device.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
 
 #include <asm/clock.h>
-
-#include <loongson.h>
+#include <asm/mach-loongson/loongson.h>
 
 static LIST_HEAD(clock_list);
 static DEFINE_SPINLOCK(clock_lock);
@@ -89,12 +92,6 @@ EXPORT_SYMBOL(clk_put);
 
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
-        return clk_set_rate_ex(clk, rate, 0);
-}
-EXPORT_SYMBOL_GPL(clk_set_rate);
-
-int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
-{
         int ret = 0;
         int regval;
         int i;
@@ -103,7 +100,7 @@ int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
                 unsigned long flags;
 
                 spin_lock_irqsave(&clock_lock, flags);
-                ret = clk->ops->set_rate(clk, rate, algo_id);
+                ret = clk->ops->set_rate(clk, rate, 0);
                 spin_unlock_irqrestore(&clock_lock, flags);
         }
 
@@ -129,7 +126,7 @@ int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
 
         return ret;
 }
-EXPORT_SYMBOL_GPL(clk_set_rate_ex);
+EXPORT_SYMBOL_GPL(clk_set_rate);
 
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
@@ -146,26 +143,3 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
         return rate;
 }
 EXPORT_SYMBOL_GPL(clk_round_rate);
-
-/*
- * This is the simple version of Loongson-2 wait, Maybe we need do this in
- * interrupt disabled content
- */
-
-DEFINE_SPINLOCK(loongson2_wait_lock);
-void loongson2_cpu_wait(void)
-{
-        u32 cpu_freq;
-        unsigned long flags;
-
-        spin_lock_irqsave(&loongson2_wait_lock, flags);
-        cpu_freq = LOONGSON_CHIPCFG0;
-        LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
-        LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */
-        spin_unlock_irqrestore(&loongson2_wait_lock, flags);
-}
-EXPORT_SYMBOL_GPL(loongson2_cpu_wait);
-
-MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
-MODULE_DESCRIPTION("cpufreq driver for Loongson 2F");
-MODULE_LICENSE("GPL");
diff --git a/arch/mips/loongson1/Kconfig b/arch/mips/loongson1/Kconfig
new file mode 100644
index 00000000000..a9a14d6e81a
--- /dev/null
+++ b/arch/mips/loongson1/Kconfig
@@ -0,0 +1,22 @@
+if MACH_LOONGSON1
+
+choice
+        prompt "Machine Type"
+
+config LOONGSON1_LS1B
+        bool "Loongson LS1B board"
+        select CEVT_R4K
+        select CSRC_R4K
+        select SYS_HAS_CPU_LOONGSON1B
+        select DMA_NONCOHERENT
+        select BOOT_ELF32
+        select IRQ_CPU
+        select SYS_SUPPORTS_32BIT_KERNEL
+        select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_SUPPORTS_HIGHMEM
+        select SYS_HAS_EARLY_PRINTK
+        select HAVE_CLK
+
+endchoice
+
+endif # MACH_LOONGSON1
diff --git a/arch/mips/loongson1/Makefile b/arch/mips/loongson1/Makefile
new file mode 100644
index 00000000000..9719c75886f
--- /dev/null
+++ b/arch/mips/loongson1/Makefile
@@ -0,0 +1,11 @@
+#
+# Common code for all Loongson 1 based systems
+#
+
+obj-$(CONFIG_MACH_LOONGSON1) += common/
+
+#
+# Loongson LS1B board
+#
+
+obj-$(CONFIG_LOONGSON1_LS1B)  += ls1b/
diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform
new file mode 100644
index 00000000000..99bdefe627a
--- /dev/null
+++ b/arch/mips/loongson1/Platform
@@ -0,0 +1,7 @@
+cflags-$(CONFIG_CPU_LOONGSON1)  += \
+        $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
+        -Wa,-mips32r2 -Wa,--trap
+
+platform-$(CONFIG_MACH_LOONGSON1)       += loongson1/
+cflags-$(CONFIG_MACH_LOONGSON1)         += -I$(srctree)/arch/mips/include/asm/mach-loongson1
+load-$(CONFIG_LOONGSON1_LS1B)           += 0xffffffff80100000
diff --git a/arch/mips/loongson1/common/Makefile b/arch/mips/loongson1/common/Makefile
new file mode 100644
index 00000000000..b2797709ef5
--- /dev/null
+++ b/arch/mips/loongson1/common/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for common code of loongson1 based machines.
+#
+
+obj-y   += clock.o irq.o platform.o prom.o reset.o setup.o
diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c
new file mode 100644
index 00000000000..1bbbbec1208
--- /dev/null
+++ b/arch/mips/loongson1/common/clock.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm/clock.h>
+#include <asm/time.h>
+
+#include <loongson1.h>
+
+static LIST_HEAD(clocks);
+static DEFINE_MUTEX(clocks_mutex);
+
+struct clk *clk_get(struct device *dev, const char *name)
+{
+        struct clk *c;
+        struct clk *ret = NULL;
+
+        mutex_lock(&clocks_mutex);
+        list_for_each_entry(c, &clocks, node) {
+                if (!strcmp(c->name, name)) {
+                        ret = c;
+                        break;
+                }
+        }
+        mutex_unlock(&clocks_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_get);
+
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+
+static void pll_clk_init(struct clk *clk)
+{
+        u32 pll;
+
+        pll = __raw_readl(LS1X_CLK_PLL_FREQ);
+        clk->rate = (12 + (pll & 0x3f)) * 33 / 2
+                        + ((pll >> 8) & 0x3ff) * 33 / 1024 / 2;
+        clk->rate *= 1000000;
+}
+
+static void cpu_clk_init(struct clk *clk)
+{
+        u32 pll, ctrl;
+
+        pll = clk_get_rate(clk->parent);
+        ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_CPU;
+        clk->rate = pll / (ctrl >> DIV_CPU_SHIFT);
+}
+
+static void ddr_clk_init(struct clk *clk)
+{
+        u32 pll, ctrl;
+
+        pll = clk_get_rate(clk->parent);
+        ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DDR;
+        clk->rate = pll / (ctrl >> DIV_DDR_SHIFT);
+}
+
+static void dc_clk_init(struct clk *clk)
+{
+        u32 pll, ctrl;
+
+        pll = clk_get_rate(clk->parent);
+        ctrl = __raw_readl(LS1X_CLK_PLL_DIV) & DIV_DC;
+        clk->rate = pll / (ctrl >> DIV_DC_SHIFT);
+}
+
+static struct clk_ops pll_clk_ops = {
+        .init   = pll_clk_init,
+};
+
+static struct clk_ops cpu_clk_ops = {
+        .init   = cpu_clk_init,
+};
+
+static struct clk_ops ddr_clk_ops = {
+        .init   = ddr_clk_init,
+};
+
+static struct clk_ops dc_clk_ops = {
+        .init   = dc_clk_init,
+};
+
+static struct clk pll_clk = {
+        .name   = "pll",
+        .ops    = &pll_clk_ops,
+};
+
+static struct clk cpu_clk = {
+        .name   = "cpu",
+        .parent = &pll_clk,
+        .ops    = &cpu_clk_ops,
+};
+
+static struct clk ddr_clk = {
+        .name   = "ddr",
+        .parent = &pll_clk,
+        .ops    = &ddr_clk_ops,
+};
+
+static struct clk dc_clk = {
+        .name   = "dc",
+        .parent = &pll_clk,
+        .ops    = &dc_clk_ops,
+};
+
+int clk_register(struct clk *clk)
+{
+        mutex_lock(&clocks_mutex);
+        list_add(&clk->node, &clocks);
+        if (clk->ops->init)
+                clk->ops->init(clk);
+        mutex_unlock(&clocks_mutex);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_register);
+
+static struct clk *ls1x_clks[] = {
+        &pll_clk,
+        &cpu_clk,
+        &ddr_clk,
+        &dc_clk,
+};
+
+int __init ls1x_clock_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(ls1x_clks); i++)
+                clk_register(ls1x_clks[i]);
+
+        return 0;
+}
+
+void __init plat_time_init(void)
+{
+        struct clk *clk;
+
+        /* Initialize LS1X clocks */
+        ls1x_clock_init();
+
+        /* setup mips r4k timer */
+        clk = clk_get(NULL, "cpu");
+        if (IS_ERR(clk))
+                panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
+
+        mips_hpt_frequency = clk_get_rate(clk) / 2;
+}
diff --git a/arch/mips/loongson1/common/irq.c b/arch/mips/loongson1/common/irq.c
new file mode 100644
index 00000000000..41bc8ffe7bb
--- /dev/null
+++ b/arch/mips/loongson1/common/irq.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/irq_cpu.h>
+
+#include <loongson1.h>
+#include <irq.h>
+
+#define LS1X_INTC_REG(n, x) \
+                ((void __iomem *)KSEG1ADDR(LS1X_INTC_BASE + (n * 0x18) + (x)))
+
+#define LS1X_INTC_INTISR(n)             LS1X_INTC_REG(n, 0x0)
+#define LS1X_INTC_INTIEN(n)             LS1X_INTC_REG(n, 0x4)
+#define LS1X_INTC_INTSET(n)             LS1X_INTC_REG(n, 0x8)
+#define LS1X_INTC_INTCLR(n)             LS1X_INTC_REG(n, 0xc)
+#define LS1X_INTC_INTPOL(n)             LS1X_INTC_REG(n, 0x10)
+#define LS1X_INTC_INTEDGE(n)            LS1X_INTC_REG(n, 0x14)
+
+static void ls1x_irq_ack(struct irq_data *d)
+{
+        unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
+        unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
+
+        __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
+                        | (1 << bit), LS1X_INTC_INTCLR(n));
+}
+
+static void ls1x_irq_mask(struct irq_data *d)
+{
+        unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
+        unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
+
+        __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
+                        & ~(1 << bit), LS1X_INTC_INTIEN(n));
+}
+
+static void ls1x_irq_mask_ack(struct irq_data *d)
+{
+        unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
+        unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
+
+        __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
+                        & ~(1 << bit), LS1X_INTC_INTIEN(n));
+        __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n))
+                        | (1 << bit), LS1X_INTC_INTCLR(n));
+}
+
+static void ls1x_irq_unmask(struct irq_data *d)
+{
+        unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
+        unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
+
+        __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n))
+                        | (1 << bit), LS1X_INTC_INTIEN(n));
+}
+
+static struct irq_chip ls1x_irq_chip = {
+        .name           = "LS1X-INTC",
+        .irq_ack        = ls1x_irq_ack,
+        .irq_mask       = ls1x_irq_mask,
+        .irq_mask_ack   = ls1x_irq_mask_ack,
+        .irq_unmask     = ls1x_irq_unmask,
+};
+
+static void ls1x_irq_dispatch(int n)
+{
+        u32 int_status, irq;
+
+        /* Get pending sources, masked by current enables */
+        int_status = __raw_readl(LS1X_INTC_INTISR(n)) &
+                        __raw_readl(LS1X_INTC_INTIEN(n));
+
+        if (int_status) {
+                irq = LS1X_IRQ(n, __ffs(int_status));
+                do_IRQ(irq);
+        }
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        unsigned int pending;
+
+        pending = read_c0_cause() & read_c0_status() & ST0_IM;
+
+        if (pending & CAUSEF_IP7)
+                do_IRQ(TIMER_IRQ);
+        else if (pending & CAUSEF_IP2)
+                ls1x_irq_dispatch(0); /* INT0 */
+        else if (pending & CAUSEF_IP3)
+                ls1x_irq_dispatch(1); /* INT1 */
+        else if (pending & CAUSEF_IP4)
+                ls1x_irq_dispatch(2); /* INT2 */
+        else if (pending & CAUSEF_IP5)
+                ls1x_irq_dispatch(3); /* INT3 */
+        else if (pending & CAUSEF_IP6)
+                ls1x_irq_dispatch(4); /* INT4 */
+        else
+                spurious_interrupt();
+
+}
+
+struct irqaction cascade_irqaction = {
+        .handler = no_action,
+        .name = "cascade",
+        .flags = IRQF_NO_THREAD,
+};
+
+static void __init ls1x_irq_init(int base)
+{
+        int n;
+
+        /* Disable interrupts and clear pending,
+         * setup all IRQs as high level triggered
+         */
+        for (n = 0; n < 4; n++) {
+                __raw_writel(0x0, LS1X_INTC_INTIEN(n));
+                __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n));
+                __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n));
+                /* set DMA0, DMA1 and DMA2 to edge trigger */
+                __raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n));
+        }
+
+
+        for (n = base; n < LS1X_IRQS; n++) {
+                irq_set_chip_and_handler(n, &ls1x_irq_chip,
+                                         handle_level_irq);
+        }
+
+        setup_irq(INT0_IRQ, &cascade_irqaction);
+        setup_irq(INT1_IRQ, &cascade_irqaction);
+        setup_irq(INT2_IRQ, &cascade_irqaction);
+        setup_irq(INT3_IRQ, &cascade_irqaction);
+}
+
+void __init arch_init_irq(void)
+{
+        mips_cpu_irq_init();
+        ls1x_irq_init(LS1X_IRQ_BASE);
+}
diff --git a/arch/mips/loongson1/common/platform.c b/arch/mips/loongson1/common/platform.c
new file mode 100644
index 00000000000..e92d59c4bd7
--- /dev/null
+++ b/arch/mips/loongson1/common/platform.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/phy.h>
+#include <linux/serial_8250.h>
+#include <linux/stmmac.h>
+#include <asm-generic/sizes.h>
+
+#include <loongson1.h>
+
+#define LS1X_UART(_id)                                          \
+        {                                                       \
+                .mapbase        = LS1X_UART ## _id ## _BASE,    \
+                .irq            = LS1X_UART ## _id ## _IRQ,     \
+                .iotype         = UPIO_MEM,                     \
+                .flags          = UPF_IOREMAP | UPF_FIXED_TYPE, \
+                .type           = PORT_16550A,                  \
+        }
+
+static struct plat_serial8250_port ls1x_serial8250_port[] = {
+        LS1X_UART(0),
+        LS1X_UART(1),
+        LS1X_UART(2),
+        LS1X_UART(3),
+        {},
+};
+
+struct platform_device ls1x_uart_device = {
+        .name           = "serial8250",
+        .id             = PLAT8250_DEV_PLATFORM,
+        .dev            = {
+                .platform_data = ls1x_serial8250_port,
+        },
+};
+
+void __init ls1x_serial_setup(void)
+{
+        struct clk *clk;
+        struct plat_serial8250_port *p;
+
+        clk = clk_get(NULL, "dc");
+        if (IS_ERR(clk))
+                panic("unable to get dc clock, err=%ld", PTR_ERR(clk));
+
+        for (p = ls1x_serial8250_port; p->flags != 0; ++p)
+                p->uartclk = clk_get_rate(clk);
+}
+
+/* Synopsys Ethernet GMAC */
+static struct resource ls1x_eth0_resources[] = {
+        [0] = {
+                .start  = LS1X_GMAC0_BASE,
+                .end    = LS1X_GMAC0_BASE + SZ_64K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name   = "macirq",
+                .start  = LS1X_GMAC0_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct stmmac_mdio_bus_data ls1x_mdio_bus_data = {
+        .bus_id         = 0,
+        .phy_mask       = 0,
+};
+
+static struct plat_stmmacenet_data ls1x_eth_data = {
+        .bus_id         = 0,
+        .phy_addr       = -1,
+        .mdio_bus_data  = &ls1x_mdio_bus_data,
+        .has_gmac       = 1,
+        .tx_coe         = 1,
+};
+
+struct platform_device ls1x_eth0_device = {
+        .name           = "stmmaceth",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(ls1x_eth0_resources),
+        .resource       = ls1x_eth0_resources,
+        .dev            = {
+                .platform_data = &ls1x_eth_data,
+        },
+};
+
+/* USB EHCI */
+static u64 ls1x_ehci_dmamask = DMA_BIT_MASK(32);
+
+static struct resource ls1x_ehci_resources[] = {
+        [0] = {
+                .start  = LS1X_EHCI_BASE,
+                .end    = LS1X_EHCI_BASE + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = LS1X_EHCI_IRQ,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device ls1x_ehci_device = {
+        .name           = "ls1x-ehci",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(ls1x_ehci_resources),
+        .resource       = ls1x_ehci_resources,
+        .dev            = {
+                .dma_mask = &ls1x_ehci_dmamask,
+        },
+};
+
+/* Real Time Clock */
+struct platform_device ls1x_rtc_device = {
+        .name           = "ls1x-rtc",
+        .id             = -1,
+};
diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common/prom.c
new file mode 100644
index 00000000000..1f8e49f9886
--- /dev/null
+++ b/arch/mips/loongson1/common/prom.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * Modified from arch/mips/pnx833x/common/prom.c.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/serial_reg.h>
+#include <asm/bootinfo.h>
+
+#include <loongson1.h>
+#include <prom.h>
+
+int prom_argc;
+char **prom_argv, **prom_envp;
+unsigned long memsize, highmemsize;
+
+char *prom_getenv(char *envname)
+{
+        char **env = prom_envp;
+        int i;
+
+        i = strlen(envname);
+
+        while (*env) {
+                if (strncmp(envname, *env, i) == 0 && *(*env+i) == '=')
+                        return *env + i + 1;
+                env++;
+        }
+
+        return 0;
+}
+
+static inline unsigned long env_or_default(char *env, unsigned long dfl)
+{
+        char *str = prom_getenv(env);
+        return str ? simple_strtol(str, 0, 0) : dfl;
+}
+
+void __init prom_init_cmdline(void)
+{
+        char *c = &(arcs_cmdline[0]);
+        int i;
+
+        for (i = 1; i < prom_argc; i++) {
+                strcpy(c, prom_argv[i]);
+                c += strlen(prom_argv[i]);
+                if (i < prom_argc-1)
+                        *c++ = ' ';
+        }
+        *c = 0;
+}
+
+void __init prom_init(void)
+{
+        prom_argc = fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+
+        memsize = env_or_default("memsize", DEFAULT_MEMSIZE);
+        highmemsize = env_or_default("highmemsize", 0x0);
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+#define PORT(offset)    (u8 *)(KSEG1ADDR(LS1X_UART0_BASE + offset))
+
+void __init prom_putchar(char c)
+{
+        int timeout;
+
+        timeout = 1024;
+
+        while (((readb(PORT(UART_LSR)) & UART_LSR_THRE) == 0)
+                        && (timeout-- > 0))
+                ;
+
+        writeb(c, PORT(UART_TX));
+}
diff --git a/arch/mips/loongson1/common/reset.c b/arch/mips/loongson1/common/reset.c
new file mode 100644
index 00000000000..fb979a784ec
--- /dev/null
+++ b/arch/mips/loongson1/common/reset.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/pm.h>
+#include <asm/reboot.h>
+
+#include <loongson1.h>
+
+static void ls1x_restart(char *command)
+{
+        __raw_writel(0x1, LS1X_WDT_EN);
+        __raw_writel(0x5000000, LS1X_WDT_TIMER);
+        __raw_writel(0x1, LS1X_WDT_SET);
+}
+
+static void ls1x_halt(void)
+{
+        while (1) {
+                if (cpu_wait)
+                        cpu_wait();
+        }
+}
+
+static void ls1x_power_off(void)
+{
+        ls1x_halt();
+}
+
+static int __init ls1x_reboot_setup(void)
+{
+        _machine_restart = ls1x_restart;
+        _machine_halt = ls1x_halt;
+        pm_power_off = ls1x_power_off;
+
+        return 0;
+}
+
+arch_initcall(ls1x_reboot_setup);
diff --git a/arch/mips/loongson1/common/setup.c b/arch/mips/loongson1/common/setup.c
new file mode 100644
index 00000000000..62128cc27e6
--- /dev/null
+++ b/arch/mips/loongson1/common/setup.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <asm/bootinfo.h>
+
+#include <prom.h>
+
+void __init plat_mem_setup(void)
+{
+        add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+}
+
+const char *get_system_type(void)
+{
+        unsigned int processor_id = (&current_cpu_data)->processor_id;
+
+        switch (processor_id & PRID_REV_MASK) {
+        case PRID_REV_LOONGSON1B:
+                return "LOONGSON LS1B";
+        default:
+                return "LOONGSON (unknown)";
+        }
+}
diff --git a/arch/mips/loongson1/ls1b/Makefile b/arch/mips/loongson1/ls1b/Makefile
new file mode 100644
index 00000000000..891eac482b8
--- /dev/null
+++ b/arch/mips/loongson1/ls1b/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for loongson1B based machines.
+#
+
+obj-y += board.o
diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/board.c
new file mode 100644
index 00000000000..295b1be893e
--- /dev/null
+++ b/arch/mips/loongson1/ls1b/board.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <platform.h>
+
+#include <linux/serial_8250.h>
+#include <loongson1.h>
+
+static struct platform_device *ls1b_platform_devices[] __initdata = {
+        &ls1x_uart_device,
+        &ls1x_eth0_device,
+        &ls1x_ehci_device,
+        &ls1x_rtc_device,
+};
+
+static int __init ls1b_platform_init(void)
+{
+        int err;
+
+        ls1x_serial_setup();
+
+        err = platform_add_devices(ls1b_platform_devices,
+                                   ARRAY_SIZE(ls1b_platform_devices));
+        return err;
+}
+
+arch_initcall(ls1b_platform_init);
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 5fa185151fc..64a28e81906 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -58,18 +58,16 @@ enum fields {
 
 enum opcode {
         insn_invalid,
-        insn_addu, insn_addiu, insn_and, insn_andi, insn_beq,
-        insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
-        insn_bne, insn_cache, insn_daddu, insn_daddiu, insn_dmfc0,
-        insn_dmtc0, insn_dsll, insn_dsll32, insn_dsra, insn_dsrl,
-        insn_dsrl32, insn_drotr, insn_drotr32, insn_dsubu, insn_eret,
-        insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld,
-        insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_or, insn_ori,
-        insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll,
-        insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp,
+        insn_addiu, insn_addu, insn_and, insn_andi, insn_bbit0, insn_bbit1,
+        insn_beq, insn_beql, insn_bgez, insn_bgezl, insn_bltz, insn_bltzl,
+        insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
+        insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
+        insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
+        insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, insn_ll, insn_lld,
+        insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, insn_or, insn_ori,
+        insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll,
+        insn_sra, insn_srl, insn_subu, insn_sw, insn_syscall, insn_tlbp,
         insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
-        insn_dins, insn_dinsm, insn_syscall, insn_bbit0, insn_bbit1,
-        insn_lwx, insn_ldx
 };
 
 struct insn {
@@ -90,65 +88,65 @@ struct insn {
 static struct insn insn_table[] __uasminitdata = {
         { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
         { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
-        { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
         { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
-        { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
+        { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
+        { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
         { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
-        { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
+        { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
         { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
-        { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
+        { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
         { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
+        { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
         { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
         { insn_cache,  M(cache_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
         { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
+        { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
+        { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
         { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
         { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
-        { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
+        { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
+        { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
+        { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
         { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
-        { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
-        { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
-        { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
+        { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
         { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
         { insn_eret,  M(cop0_op, cop_op, 0, 0, 0, eret_op),  0 },
-        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
         { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
+        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
         { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
         { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
-        { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
         { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
         { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
         { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
         { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
-        { insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },
         { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
+        { insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },
         { insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
-        { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
         { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
         { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
         { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
-        { insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
         { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
         { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+        { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
         { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
         { insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },
         { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
-        { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
         { insn_xori,  M(xori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
-        { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
-        { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
-        { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
-        { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
-        { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
-        { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
-        { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
+        { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
         { insn_invalid, 0, 0 }
 };
 
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
index 284dea54faf..2147cb34e70 100644
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/mti-malta/malta-pci.c
@@ -252,16 +252,3 @@ void __init mips_pcibios_init(void)
 
         register_pci_controller(controller);
 }
-
-/* Enable PCI 2.1 compatibility in PIIX4 */
-static void __devinit quirk_dlcsetup(struct pci_dev *dev)
-{
-        u8 odlc, ndlc;
-        (void) pci_read_config_byte(dev, 0x82, &odlc);
-        /* Enable passive releases and delayed transaction */
-        ndlc = odlc | 7;
-        (void) pci_write_config_byte(dev, 0x82, ndlc);
-}
-
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
-        quirk_dlcsetup);
diff --git a/arch/mips/netlogic/common/earlycons.c b/arch/mips/netlogic/common/earlycons.c
index f193f7b3bd8..1902fa22d27 100644
--- a/arch/mips/netlogic/common/earlycons.c
+++ b/arch/mips/netlogic/common/earlycons.c
@@ -54,7 +54,7 @@ void prom_putchar(char c)
 #elif defined(CONFIG_CPU_XLR)
         uartbase = nlm_mmio_base(NETLOGIC_IO_UART_0_OFFSET);
 #endif
-        while (nlm_read_reg(uartbase, UART_LSR) == 0)
+        while ((nlm_read_reg(uartbase, UART_LSR) & UART_LSR_THRE) == 0)
                 ;
         nlm_write_reg(uartbase, UART_TX, c);
 }
diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index c138b1a6dec..a13355cc97e 100644
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -54,28 +54,68 @@
                         XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
                         SYS_CPU_NONCOHERENT_MODE * 4
 
-.macro __config_lsu
-        li      t0, LSU_DEFEATURE
-        mfcr    t1, t0
+#define XLP_AX_WORKAROUND       /* enable Ax silicon workarounds */
 
-        lui     t2, 0x4080  /* Enable Unaligned Access, L2HPE */
-        or      t1, t1, t2
-        li      t2, ~0xe    /* S1RCM */
+/* Enable XLP features and workarounds in the LSU */
+.macro xlp_config_lsu
+        li      t0, LSU_DEFEATURE
+        mfcr    t1, t0
+
+        lui     t2, 0x4080      /* Enable Unaligned Access, L2HPE */
+        or      t1, t1, t2
+#ifdef XLP_AX_WORKAROUND
+        li      t2, ~0xe        /* S1RCM */
         and     t1, t1, t2
-        mtcr    t1, t0
+#endif
+        mtcr    t1, t0
 
-        li      t0, SCHED_DEFEATURE
-        lui     t1, 0x0100  /* Experimental: Disable BRU accepting ALU ops */
-        mtcr    t1, t0
+#ifdef XLP_AX_WORKAROUND
+        li      t0, SCHED_DEFEATURE
+        lui     t1, 0x0100      /* Disable BRU accepting ALU ops */
+        mtcr    t1, t0
+#endif
+.endm
+
+/*
+ * This is the code that will be copied to the reset entry point for
+ * XLR and XLP. The XLP cores start here when they are woken up. This
+ * is also the NMI entry point.
+ */
+.macro  xlp_flush_l1_dcache
+        li      t0, LSU_DEBUG_DATA0
+        li      t1, LSU_DEBUG_ADDR
+        li      t2, 0           /* index */
+        li      t3, 0x1000      /* loop count */
+1:
+        sll     v0, t2, 5
+        mtcr    zero, t0
+        ori     v1, v0, 0x3     /* way0 | write_enable | write_active */
+        mtcr    v1, t1
+2:
+        mfcr    v1, t1
+        andi    v1, 0x1         /* wait for write_active == 0 */
+        bnez    v1, 2b
+        nop
+        mtcr    zero, t0
+        ori     v1, v0, 0x7     /* way1 | write_enable | write_active */
+        mtcr    v1, t1
+3:
+        mfcr    v1, t1
+        andi    v1, 0x1         /* wait for write_active == 0 */
+        bnez    v1, 3b
+        nop
+        addi    t2, 1
+        bne     t3, t2, 1b
+        nop
 .endm
 
 /*
  * The cores can come start when they are woken up. This is also the NMI
  * entry, so check that first.
  *
- * The data corresponding to reset is stored at RESET_DATA_PHYS location,
- * this will have the thread mask (used when core is woken up) and the
- * current NMI handler in case we reached here for an NMI.
+ * The data corresponding to reset/NMI is stored at RESET_DATA_PHYS
+ * location, this will have the thread mask (used when core is woken up)
+ * and the current NMI handler in case we reached here for an NMI.
  *
  * When a core or thread is newly woken up, it loops in a 'wait'. When
  * the CPU really needs waking up, we send an NMI to it, with the NMI
@@ -89,12 +129,12 @@
 FEXPORT(nlm_reset_entry)
         dmtc0   k0, $22, 6
         dmtc0   k1, $22, 7
-        mfc0    k0, CP0_STATUS
-        li      k1, 0x80000
-        and     k1, k0, k1
-        beqz    k1, 1f         /* go to real reset entry */
+        mfc0    k0, CP0_STATUS
+        li      k1, 0x80000
+        and     k1, k0, k1
+        beqz    k1, 1f          /* go to real reset entry */
         nop
-        li      k1, CKSEG1ADDR(RESET_DATA_PHYS)   /* NMI */
+        li      k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
         ld      k0, BOOT_NMI_HANDLER(k1)
         jr      k0
         nop
@@ -114,21 +154,25 @@ FEXPORT(nlm_reset_entry)
         li      t2, SYS_CPU_COHERENT_BASE(0)
         add     t2, t2, t3              /* t2 <- SYS offset for node */
         lw      t1, 0(t2)
-        and     t1, t1, t0
-        sw      t1, 0(t2)
+        and     t1, t1, t0
+        sw      t1, 0(t2)
 
         /* read back to ensure complete */
-        lw      t1, 0(t2)
+        lw      t1, 0(t2)
         sync
 
         /* Configure LSU on Non-0 Cores. */
-        __config_lsu
+        xlp_config_lsu
+        /* FALL THROUGH */
 
 /*
  * Wake up sibling threads from the initial thread in
  * a core.
  */
 EXPORT(nlm_boot_siblings)
+        /* core L1D flush before enable threads */
+        xlp_flush_l1_dcache
+        /* Enable hw threads by writing to MAP_THREADMODE of the core */
         li      t0, CKSEG1ADDR(RESET_DATA_PHYS)
         lw      t1, BOOT_THREAD_MODE(t0)        /* t1 <- thread mode */
         li      t0, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
@@ -139,31 +183,28 @@ EXPORT(nlm_boot_siblings)
         /*
          * The new hardware thread starts at the next instruction
          * For all the cases other than core 0 thread 0, we will
-         * jump to the secondary wait function.
-         */
+        * jump to the secondary wait function.
+        */
         mfc0    v0, CP0_EBASE, 1
         andi    v0, 0x7f                /* v0 <- node/core */
 
-#if 1
-        /* A0 errata - Write MMU_SETUP after changing thread mode register. */
+        /* Init MMU in the first thread after changing THREAD_MODE
+         * register (Ax Errata?)
+         */
         andi    v1, v0, 0x3             /* v1 <- thread id */
         bnez    v1, 2f
         nop
 
-        li      t0, MMU_SETUP
-        li      t1, 0
-        mtcr    t1, t0
-        ehb
-#endif
+        li      t0, MMU_SETUP
+        li      t1, 0
+        mtcr    t1, t0
+        _ehb
 
-2:      beqz    v0, 4f
+2:      beqz    v0, 4f          /* boot cpu (cpuid == 0)? */
         nop
 
         /* setup status reg */
-        mfc0    t1, CP0_STATUS
-        li      t0, ST0_BEV
-        or      t1, t0
-        xor     t1, t0
+        move    t1, zero
 #ifdef CONFIG_64BIT
         ori     t1, ST0_KX
 #endif
@@ -183,9 +224,9 @@ EXPORT(nlm_boot_siblings)
          * For the boot CPU, we have to restore registers and
          * return
          */
-4:      dmfc0   t0, $4, 2       /* restore SP from UserLocal */
+4:      dmfc0   t0, $4, 2       /* restore SP from UserLocal */
         li      t1, 0xfadebeef
-        dmtc0   t1, $4, 2       /* restore SP from UserLocal */
+        dmtc0   t1, $4, 2       /* restore SP from UserLocal */
         PTR_SUBU sp, t0, PT_SIZE
         RESTORE_ALL
         jr   ra
@@ -193,7 +234,7 @@ EXPORT(nlm_boot_siblings)
 EXPORT(nlm_reset_entry_end)
 
 FEXPORT(xlp_boot_core0_siblings)        /* "Master" cpu starts from here */
-        __config_lsu
+        xlp_config_lsu
         dmtc0   sp, $4, 2               /* SP saved in UserLocal */
         SAVE_ALL
         sync
@@ -210,6 +251,12 @@ FEXPORT(xlp_boot_core0_siblings)	/* "Master" cpu starts from here */
 
         __CPUINIT
 NESTED(nlm_boot_secondary_cpus, 16, sp)
+        /* Initialize CP0 Status */
+        move    t1, zero
+#ifdef CONFIG_64BIT
+        ori     t1, ST0_KX
+#endif
+        mtc0    t1, CP0_STATUS
         PTR_LA  t1, nlm_next_sp
         PTR_L   sp, 0(t1)
         PTR_LA  t1, nlm_next_gp
@@ -234,36 +281,36 @@ END(nlm_boot_secondary_cpus)
  */
         __CPUINIT
 NESTED(nlm_rmiboot_preboot, 16, sp)
-        mfc0    t0, $15, 1      # read ebase
-        andi    t0, 0x1f        # t0 has the processor_id()
-        andi    t2, t0, 0x3     # thread no
-        sll     t0, 2           # offset in cpu array
+        mfc0    t0, $15, 1      /* read ebase */
+        andi    t0, 0x1f        /* t0 has the processor_id() */
+        andi    t2, t0, 0x3     /* thread num */
+        sll     t0, 2           /* offset in cpu array */
 
-        PTR_LA  t1, nlm_cpu_ready # mark CPU ready
+        PTR_LA  t1, nlm_cpu_ready /* mark CPU ready */
         PTR_ADDU t1, t0
         li      t3, 1
         sw      t3, 0(t1)
 
-        bnez    t2, 1f          # skip thread programming
-        nop                     # for non zero hw threads
+        bnez    t2, 1f          /* skip thread programming */
+        nop                     /* for thread id != 0 */
 
         /*
-         * MMU setup only for first thread in core
+         * XLR MMU setup only for first thread in core
          */
         li      t0, 0x400
         mfcr    t1, t0
-        li      t2, 6           # XLR thread mode mask
+        li      t2, 6           /* XLR thread mode mask */
         nor     t3, t2, zero
-        and     t2, t1, t2      # t2 - current thread mode
+        and     t2, t1, t2      /* t2 - current thread mode */
         li      v0, CKSEG1ADDR(RESET_DATA_PHYS)
-        lw      v1, BOOT_THREAD_MODE(v0) # v1 - new thread mode
+        lw      v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
         sll     v1, 1
-        beq     v1, t2, 1f      # same as request value
-        nop                     # nothing to do */
+        beq     v1, t2, 1f      /* same as request value */
+        nop                     /* nothing to do */
 
-        and     t2, t1, t3      # mask out old thread mode
-        or      t1, t2, v1      # put in new value
-        mtcr    t1, t0          # update core control
+        and     t2, t1, t3      /* mask out old thread mode */
+        or      t1, t2, v1      /* put in new value */
+        mtcr    t1, t0          /* update core control */
 
 1:      wait
         j       1b
diff --git a/arch/mips/netlogic/xlp/Makefile b/arch/mips/netlogic/xlp/Makefile
index b93ed83474e..6b4b972218f 100644
--- a/arch/mips/netlogic/xlp/Makefile
+++ b/arch/mips/netlogic/xlp/Makefile
@@ -1,2 +1,4 @@
 obj-y                           += setup.o platform.o nlm_hal.o
+obj-$(CONFIG_OF)                += of.o
 obj-$(CONFIG_SMP)               += wakeup.o
+obj-$(CONFIG_USB)               += usb-init.o
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 9428e7125fe..6c65ac70191 100644
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -69,6 +69,32 @@ int nlm_irq_to_irt(int irq)
                 return PIC_IRT_UART_0_INDEX;
         case PIC_UART_1_IRQ:
                 return PIC_IRT_UART_1_INDEX;
+        case PIC_PCIE_LINK_0_IRQ:
+               return PIC_IRT_PCIE_LINK_0_INDEX;
+        case PIC_PCIE_LINK_1_IRQ:
+               return PIC_IRT_PCIE_LINK_1_INDEX;
+        case PIC_PCIE_LINK_2_IRQ:
+               return PIC_IRT_PCIE_LINK_2_INDEX;
+        case PIC_PCIE_LINK_3_IRQ:
+               return PIC_IRT_PCIE_LINK_3_INDEX;
+        case PIC_EHCI_0_IRQ:
+               return PIC_IRT_EHCI_0_INDEX;
+        case PIC_EHCI_1_IRQ:
+               return PIC_IRT_EHCI_1_INDEX;
+        case PIC_OHCI_0_IRQ:
+               return PIC_IRT_OHCI_0_INDEX;
+        case PIC_OHCI_1_IRQ:
+               return PIC_IRT_OHCI_1_INDEX;
+        case PIC_OHCI_2_IRQ:
+               return PIC_IRT_OHCI_2_INDEX;
+        case PIC_OHCI_3_IRQ:
+               return PIC_IRT_OHCI_3_INDEX;
+        case PIC_MMC_IRQ:
+               return PIC_IRT_MMC_INDEX;
+        case PIC_I2C_0_IRQ:
+                return PIC_IRT_I2C_0_INDEX;
+        case PIC_I2C_1_IRQ:
+                return PIC_IRT_I2C_1_INDEX;
         default:
                 return -1;
         }
@@ -81,6 +107,32 @@ int nlm_irt_to_irq(int irt)
                 return PIC_UART_0_IRQ;
         case PIC_IRT_UART_1_INDEX:
                 return PIC_UART_1_IRQ;
+        case PIC_IRT_PCIE_LINK_0_INDEX:
+               return PIC_PCIE_LINK_0_IRQ;
+        case PIC_IRT_PCIE_LINK_1_INDEX:
+               return PIC_PCIE_LINK_1_IRQ;
+        case PIC_IRT_PCIE_LINK_2_INDEX:
+               return PIC_PCIE_LINK_2_IRQ;
+        case PIC_IRT_PCIE_LINK_3_INDEX:
+               return PIC_PCIE_LINK_3_IRQ;
+        case PIC_IRT_EHCI_0_INDEX:
+                return PIC_EHCI_0_IRQ;
+        case PIC_IRT_EHCI_1_INDEX:
+                return PIC_EHCI_1_IRQ;
+        case PIC_IRT_OHCI_0_INDEX:
+                return PIC_OHCI_0_IRQ;
+        case PIC_IRT_OHCI_1_INDEX:
+                return PIC_OHCI_1_IRQ;
+        case PIC_IRT_OHCI_2_INDEX:
+                return PIC_OHCI_2_IRQ;
+        case PIC_IRT_OHCI_3_INDEX:
+                return PIC_OHCI_3_IRQ;
+        case PIC_IRT_MMC_INDEX:
+               return PIC_MMC_IRQ;
+        case PIC_IRT_I2C_0_INDEX:
+                return PIC_I2C_0_IRQ;
+        case PIC_IRT_I2C_1_INDEX:
+                return PIC_I2C_1_IRQ;
         default:
                 return -1;
         }
diff --git a/arch/mips/netlogic/xlp/of.c b/arch/mips/netlogic/xlp/of.c
new file mode 100644
index 00000000000..8e3921c0c20
--- /dev/null
+++ b/arch/mips/netlogic/xlp/of.c
@@ -0,0 +1,34 @@
+#include <linux/bootmem.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of_fdt.h>
+#include <asm/byteorder.h>
+
+static int __init reserve_mem_mach(unsigned long addr, unsigned long size)
+{
+        return reserve_bootmem(addr, size, BOOTMEM_DEFAULT);
+}
+
+void __init free_mem_mach(unsigned long addr, unsigned long size)
+{
+        return free_bootmem(addr, size);
+}
+
+void __init device_tree_init(void)
+{
+        unsigned long base, size;
+
+        if (!initial_boot_params)
+                return;
+
+        base = virt_to_phys((void *)initial_boot_params);
+        size = be32_to_cpu(initial_boot_params->totalsize);
+
+        /* Before we do anything, lets reserve the dt blob */
+        reserve_mem_mach(base, size);
+
+        unflatten_device_tree();
+
+        /* free the space reserved for the dt blob */
+        free_mem_mach(base, size);
+}
diff --git a/arch/mips/netlogic/xlp/platform.c b/arch/mips/netlogic/xlp/platform.c
index 1f5e4cba891..2c510d58544 100644
--- a/arch/mips/netlogic/xlp/platform.c
+++ b/arch/mips/netlogic/xlp/platform.c
@@ -53,7 +53,7 @@
 
 static unsigned int nlm_xlp_uart_in(struct uart_port *p, int offset)
 {
-         return nlm_read_reg(p->iobase, offset);
+        return nlm_read_reg(p->iobase, offset);
 }
 
 static void nlm_xlp_uart_out(struct uart_port *p, int offset, int value)
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index b3df7c2aad1..3dec9f28b65 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -41,6 +41,8 @@
 #include <asm/bootinfo.h>
 
 #include <linux/of_fdt.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
 
 #include <asm/netlogic/haldefs.h>
 #include <asm/netlogic/common.h>
@@ -109,3 +111,17 @@ void __init prom_init(void)
         register_smp_ops(&nlm_smp_ops);
 #endif
 }
+
+static struct of_device_id __initdata xlp_ids[] = {
+        { .compatible = "simple-bus", },
+        {},
+};
+
+int __init xlp8xx_ds_publish_devices(void)
+{
+        if (!of_have_populated_dt())
+                return 0;
+        return of_platform_bus_probe(NULL, xlp_ids, NULL);
+}
+
+device_initcall(xlp8xx_ds_publish_devices);
diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c
new file mode 100644
index 00000000000..dbe083a9353
--- /dev/null
+++ b/arch/mips/netlogic/xlp/usb-init.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/usb.h>
+
+static void nlm_usb_intr_en(int node, int port)
+{
+        uint32_t val;
+        uint64_t port_addr;
+
+        port_addr = nlm_get_usb_regbase(node, port);
+        val = nlm_read_usb_reg(port_addr, USB_INT_EN);
+        val = USB_CTRL_INTERRUPT_EN  | USB_OHCI_INTERRUPT_EN |
+                USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN  |
+                USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
+        nlm_write_usb_reg(port_addr, USB_INT_EN, val);
+}
+
+static void nlm_usb_hw_reset(int node, int port)
+{
+        uint64_t port_addr;
+        uint32_t val;
+
+        /* reset USB phy */
+        port_addr = nlm_get_usb_regbase(node, port);
+        val = nlm_read_usb_reg(port_addr, USB_PHY_0);
+        val &= ~(USB_PHY_RESET | USB_PHY_PORT_RESET_0 | USB_PHY_PORT_RESET_1);
+        nlm_write_usb_reg(port_addr, USB_PHY_0, val);
+
+        mdelay(100);
+        val = nlm_read_usb_reg(port_addr, USB_CTL_0);
+        val &= ~(USB_CONTROLLER_RESET);
+        val |= 0x4;
+        nlm_write_usb_reg(port_addr, USB_CTL_0, val);
+}
+
+static int __init nlm_platform_usb_init(void)
+{
+        pr_info("Initializing USB Interface\n");
+        nlm_usb_hw_reset(0, 0);
+        nlm_usb_hw_reset(0, 3);
+
+        /* Enable PHY interrupts */
+        nlm_usb_intr_en(0, 0);
+        nlm_usb_intr_en(0, 3);
+
+        return 0;
+}
+
+arch_initcall(nlm_platform_usb_init);
+
+static u64 xlp_usb_dmamask = ~(u32)0;
+
+/* Fixup the IRQ for USB devices which is exist on XLP SOC PCIE bus */
+static void nlm_usb_fixup_final(struct pci_dev *dev)
+{
+        dev->dev.dma_mask               = &xlp_usb_dmamask;
+        dev->dev.coherent_dma_mask      = DMA_BIT_MASK(64);
+        switch (dev->devfn) {
+        case 0x10:
+               dev->irq = PIC_EHCI_0_IRQ;
+               break;
+        case 0x11:
+               dev->irq = PIC_OHCI_0_IRQ;
+               break;
+        case 0x12:
+               dev->irq = PIC_OHCI_1_IRQ;
+               break;
+        case 0x13:
+               dev->irq = PIC_EHCI_1_IRQ;
+               break;
+        case 0x14:
+               dev->irq = PIC_OHCI_2_IRQ;
+               break;
+        case 0x15:
+               dev->irq = PIC_OHCI_3_IRQ;
+               break;
+        }
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_EHCI,
+                nlm_usb_fixup_final);
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_NETLOGIC, PCI_DEVICE_ID_NLM_OHCI,
+                nlm_usb_fixup_final);
diff --git a/arch/mips/netlogic/xlr/Makefile b/arch/mips/netlogic/xlr/Makefile
index f01e4d7a060..c287dea8757 100644
--- a/arch/mips/netlogic/xlr/Makefile
+++ b/arch/mips/netlogic/xlr/Makefile
@@ -1,2 +1,2 @@
-obj-y                           += setup.o platform.o
+obj-y                           += setup.o platform.o platform-flash.o
 obj-$(CONFIG_SMP)               += wakeup.o
diff --git a/arch/mips/netlogic/xlr/platform-flash.c b/arch/mips/netlogic/xlr/platform-flash.c
new file mode 100644
index 00000000000..340ab1601c4
--- /dev/null
+++ b/arch/mips/netlogic/xlr/platform-flash.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2011, Netlogic Microsystems.
+ * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/resource.h>
+#include <linux/spi/flash.h>
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+#include <asm/netlogic/haldefs.h>
+#include <asm/netlogic/xlr/iomap.h>
+#include <asm/netlogic/xlr/flash.h>
+#include <asm/netlogic/xlr/bridge.h>
+#include <asm/netlogic/xlr/gpio.h>
+#include <asm/netlogic/xlr/xlr.h>
+
+/*
+ * Default NOR partition layout
+ */
+static struct mtd_partition xlr_nor_parts[] = {
+        {
+                .name = "User FS",
+                .offset = 0x800000,
+                .size   = MTDPART_SIZ_FULL,
+        }
+};
+
+/*
+ * Default NAND partition layout
+ */
+static struct mtd_partition xlr_nand_parts[] = {
+        {
+                .name   = "Root Filesystem",
+                .offset = 64 * 64 * 2048,
+                .size   = 432 * 64 * 2048,
+        },
+        {
+                .name   = "Home Filesystem",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+/* Use PHYSMAP flash for NOR */
+struct physmap_flash_data xlr_nor_data = {
+        .width          = 2,
+        .parts          = xlr_nor_parts,
+        .nr_parts       = ARRAY_SIZE(xlr_nor_parts),
+};
+
+static struct resource xlr_nor_res[] = {
+        {
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device xlr_nor_dev = {
+        .name   = "physmap-flash",
+        .dev    = {
+                .platform_data  = &xlr_nor_data,
+        },
+        .num_resources  = ARRAY_SIZE(xlr_nor_res),
+        .resource       = xlr_nor_res,
+};
+
+const char *xlr_part_probes[] = { "cmdlinepart", NULL };
+
+/*
+ * Use "gen_nand" driver for NAND flash
+ *
+ * There seems to be no way to store a private pointer containing
+ * platform specific info in gen_nand drivier. We will use a global
+ * struct for now, since we currently have only one NAND chip per board.
+ */
+struct xlr_nand_flash_priv {
+        int cs;
+        uint64_t flash_mmio;
+};
+
+static struct xlr_nand_flash_priv nand_priv;
+
+static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd,
+                unsigned int ctrl)
+{
+        if (ctrl & NAND_CLE)
+                nlm_write_reg(nand_priv.flash_mmio,
+                        FLASH_NAND_CLE(nand_priv.cs), cmd);
+        else if (ctrl & NAND_ALE)
+                nlm_write_reg(nand_priv.flash_mmio,
+                        FLASH_NAND_ALE(nand_priv.cs), cmd);
+}
+
+struct platform_nand_data xlr_nand_data = {
+        .chip = {
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(xlr_nand_parts),
+                .chip_delay     = 50,
+                .partitions     = xlr_nand_parts,
+                .part_probe_types = xlr_part_probes,
+        },
+        .ctrl = {
+                .cmd_ctrl       = xlr_nand_ctrl,
+        },
+};
+
+static struct resource xlr_nand_res[] = {
+        {
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device xlr_nand_dev = {
+        .name           = "gen_nand",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(xlr_nand_res),
+        .resource       = xlr_nand_res,
+        .dev            = {
+                .platform_data  = &xlr_nand_data,
+        }
+};
+
+/*
+ * XLR/XLS supports upto 8 devices on its FLASH interface. The value in
+ * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the
+ * flash devices.
+ * Under this, each flash device has an offset and size given by the
+ * CSBASE_ADDR and CSBASE_MASK registers for the device.
+ *
+ * The CSBASE_ registers are expected to be setup by the bootloader.
+ */
+static void setup_flash_resource(uint64_t flash_mmio,
+        uint64_t flash_map_base, int cs, struct resource *res)
+{
+        u32 base, mask;
+
+        base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs));
+        mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs));
+
+        res->start = flash_map_base + ((unsigned long)base << 16);
+        res->end = res->start + (mask + 1) * 64 * 1024;
+}
+
+static int __init xlr_flash_init(void)
+{
+        uint64_t gpio_mmio, flash_mmio, flash_map_base;
+        u32 gpio_resetcfg, flash_bar;
+        int cs, boot_nand, boot_nor;
+
+        /* Flash address bits 39:24 is in bridge flash BAR */
+        flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR);
+        flash_map_base = (flash_bar & 0xffff0000) << 8;
+
+        gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
+        flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET);
+
+        /* Get the chip reset config */
+        gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG);
+
+        /* Check for boot flash type */
+        boot_nor = boot_nand = 0;
+        if (nlm_chip_is_xls()) {
+                /* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */
+                if (gpio_resetcfg & (1 << 16))
+                        boot_nand = 1;
+
+                /* check boot from PCMCIA, (GPIO reset reg bit 15 */
+                if ((gpio_resetcfg & (1 << 15)) == 0)
+                        boot_nor = 1;   /* not set, booted from NOR */
+        } else { /* XLR */
+                /* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */
+                if ((gpio_resetcfg & (1 << 16)) == 0)
+                        boot_nor = 1;   /* not set, booted from NOR */
+        }
+
+        /* boot flash at chip select 0 */
+        cs = 0;
+
+        if (boot_nand) {
+                nand_priv.cs = cs;
+                nand_priv.flash_mmio = flash_mmio;
+                setup_flash_resource(flash_mmio, flash_map_base, cs,
+                         xlr_nand_res);
+
+                /* Initialize NAND flash at CS 0 */
+                nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs),
+                                FLASH_NAND_CSDEV_PARAM);
+                nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs),
+                                FLASH_NAND_CSTIME_PARAMA);
+                nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs),
+                                FLASH_NAND_CSTIME_PARAMB);
+
+                pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res);
+                return platform_device_register(&xlr_nand_dev);
+        }
+
+        if (boot_nor) {
+                setup_flash_resource(flash_mmio, flash_map_base, cs,
+                        xlr_nor_res);
+                pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res);
+                return platform_device_register(&xlr_nor_dev);
+        }
+        return 0;
+}
+
+arch_initcall(xlr_flash_init);
diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index eab64b45dff..71b44d82621 100644
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -14,6 +14,7 @@
 #include <linux/resource.h>
 #include <linux/serial_8250.h>
 #include <linux/serial_reg.h>
+#include <linux/i2c.h>
 
 #include <asm/netlogic/haldefs.h>
 #include <asm/netlogic/xlr/iomap.h>
@@ -97,3 +98,142 @@ static int __init nlm_uart_init(void)
 }
 
 arch_initcall(nlm_uart_init);
+
+#ifdef CONFIG_USB
+/* Platform USB devices, only on XLS chips */
+static u64 xls_usb_dmamask = ~(u32)0;
+#define USB_PLATFORM_DEV(n, i, irq)                                     \
+        {                                                               \
+                .name           = n,                                    \
+                .id             = i,                                    \
+                .num_resources  = 2,                                    \
+                .dev            = {                                     \
+                        .dma_mask       = &xls_usb_dmamask,             \
+                        .coherent_dma_mask = 0xffffffff,                \
+                },                                                      \
+                .resource       = (struct resource[]) {                 \
+                        {                                               \
+                                .flags = IORESOURCE_MEM,                \
+                        },                                              \
+                        {                                               \
+                                .start  = irq,                          \
+                                .end    = irq,                          \
+                                .flags = IORESOURCE_IRQ,                \
+                        },                                              \
+                },                                                      \
+        }
+
+static struct platform_device xls_usb_ehci_device =
+                         USB_PLATFORM_DEV("ehci-xls", 0, PIC_USB_IRQ);
+static struct platform_device xls_usb_ohci_device_0 =
+                         USB_PLATFORM_DEV("ohci-xls-0", 1, PIC_USB_IRQ);
+static struct platform_device xls_usb_ohci_device_1 =
+                         USB_PLATFORM_DEV("ohci-xls-1", 2, PIC_USB_IRQ);
+
+static struct platform_device *xls_platform_devices[] = {
+        &xls_usb_ehci_device,
+        &xls_usb_ohci_device_0,
+        &xls_usb_ohci_device_1,
+};
+
+int xls_platform_usb_init(void)
+{
+        uint64_t usb_mmio, gpio_mmio;
+        unsigned long memres;
+        uint32_t val;
+
+        if (!nlm_chip_is_xls())
+                return 0;
+
+        gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
+        usb_mmio  = nlm_mmio_base(NETLOGIC_IO_USB_1_OFFSET);
+
+        /* Clear Rogue Phy INTs */
+        nlm_write_reg(usb_mmio, 49, 0x10000000);
+        /* Enable all interrupts */
+        nlm_write_reg(usb_mmio, 50, 0x1f000000);
+
+        /* Enable ports */
+        nlm_write_reg(usb_mmio,  1, 0x07000500);
+
+        val = nlm_read_reg(gpio_mmio, 21);
+        if (((val >> 22) & 0x01) == 0) {
+                pr_info("Detected USB Device mode - Not supported!\n");
+                nlm_write_reg(usb_mmio,  0, 0x01000000);
+                return 0;
+        }
+
+        pr_info("Detected USB Host mode - Adding XLS USB devices.\n");
+        /* Clear reset, host mode */
+        nlm_write_reg(usb_mmio,  0, 0x02000000);
+
+        /* Memory resource for various XLS usb ports */
+        usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_0_OFFSET);
+        memres = CPHYSADDR((unsigned long)usb_mmio);
+        xls_usb_ehci_device.resource[0].start = memres;
+        xls_usb_ehci_device.resource[0].end = memres + 0x400 - 1;
+
+        memres += 0x400;
+        xls_usb_ohci_device_0.resource[0].start = memres;
+        xls_usb_ohci_device_0.resource[0].end = memres + 0x400 - 1;
+
+        memres += 0x400;
+        xls_usb_ohci_device_1.resource[0].start = memres;
+        xls_usb_ohci_device_1.resource[0].end = memres + 0x400 - 1;
+
+        return platform_add_devices(xls_platform_devices,
+                                ARRAY_SIZE(xls_platform_devices));
+}
+
+arch_initcall(xls_platform_usb_init);
+#endif
+
+#ifdef CONFIG_I2C
+static struct i2c_board_info nlm_i2c_board_info1[] __initdata = {
+        /* All XLR boards have this RTC and Max6657 Temp Chip */
+        [0] = {
+                .type   = "ds1374",
+                .addr   = 0x68
+        },
+        [1] = {
+                .type   = "lm90",
+                .addr   = 0x4c
+        },
+};
+
+static struct resource i2c_resources[] = {
+        [0] = {
+                .start  = 0,    /* filled at init */
+                .end    = 0,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device nlm_xlr_i2c_1 = {
+        .name           = "xlr-i2cbus",
+        .id             = 1,
+        .num_resources  = 1,
+        .resource       = i2c_resources,
+};
+
+static int __init nlm_i2c_init(void)
+{
+        int err = 0;
+        unsigned int offset;
+
+        /* I2C bus 0 does not have any useful devices, configure only bus 1 */
+        offset = NETLOGIC_IO_I2C_1_OFFSET;
+        nlm_xlr_i2c_1.resource[0].start = CPHYSADDR(nlm_mmio_base(offset));
+        nlm_xlr_i2c_1.resource[0].end = nlm_xlr_i2c_1.resource[0].start + 0xfff;
+
+        platform_device_register(&nlm_xlr_i2c_1);
+
+        err = i2c_register_board_info(1, nlm_i2c_board_info1,
+                                ARRAY_SIZE(nlm_i2c_board_info1));
+        if (err < 0)
+                pr_err("nlm-i2c: cannot register board I2C devices\n");
+        return err;
+}
+
+arch_initcall(nlm_i2c_init);
+#endif
diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index c9d066dedc4..81b1d311834 100644
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -85,7 +85,7 @@ static void nlm_linux_exit(void)
 
         gpiobase = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
         /* trigger a chip reset by writing 1 to GPIO_SWRESET_REG */
-        nlm_write_reg(gpiobase, NETLOGIC_GPIO_SWRESET_REG, 1);
+        nlm_write_reg(gpiobase, GPIO_SWRESET_REG, 1);
         for ( ; ; )
                 cpu_wait();
 }
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index b6e378211a2..f80480a5a03 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -85,6 +85,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
         case CPU_34K:
         case CPU_1004K:
         case CPU_74K:
+        case CPU_LOONGSON1:
         case CPU_SB1:
         case CPU_SB1A:
         case CPU_R10000:
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 4d80a856048..28ea1a4cc57 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -339,12 +339,6 @@ static int __init mipsxx_init(void)
                 break;
 
         case CPU_1004K:
-#if 0
-                /* FIXME: report as 34K for now */
-                op_model_mipsxx_ops.cpu_type = "mips/1004K";
-                break;
-#endif
-
         case CPU_34K:
                 op_model_mipsxx_ops.cpu_type = "mips/34K";
                 break;
@@ -374,6 +368,10 @@ static int __init mipsxx_init(void)
                 op_model_mipsxx_ops.cpu_type = "mips/sb1";
                 break;
 
+        case CPU_LOONGSON1:
+                op_model_mipsxx_ops.cpu_type = "mips/loongson1";
+                break;
+
         default:
                 printk(KERN_ERR "Profiling unsupported for this CPU\n");
 
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index c703f43a991..e13a71cbc3c 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_WR_PPMC)		+= fixup-wrppmc.o
 obj-$(CONFIG_MIKROTIK_RB532)    += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
 obj-$(CONFIG_CPU_XLR)           += pci-xlr.o
+obj-$(CONFIG_CPU_XLP)           += pci-xlp.o
 
 ifdef CONFIG_PCI_MSI
 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 9553b14002d..3e7ce65d776 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -37,7 +37,7 @@
 #define VIA_COBALT_BRD_ID_REG  0x94
 #define VIA_COBALT_BRD_REG_to_ID(reg)   ((unsigned char)(reg) >> 4)
 
-static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_galileo_early_fixup(struct pci_dev *dev)
 {
         if (dev->devfn == PCI_DEVFN(0, 0) &&
                 (dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
@@ -51,7 +51,7 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
          qube_raq_galileo_early_fixup);
 
-static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 {
         unsigned short cfgword;
         unsigned char lt;
@@ -74,7 +74,7 @@ static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
          qube_raq_via_bmIDE_fixup);
 
-static void qube_raq_galileo_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_galileo_fixup(struct pci_dev *dev)
 {
         if (dev->devfn != PCI_DEVFN(0, 0))
                 return;
@@ -129,7 +129,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
 
 int cobalt_board_id;
 
-static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
+static void __devinit qube_raq_via_board_id_fixup(struct pci_dev *dev)
 {
         u8 id;
         int retval;
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 70073c98ed3..819622f93e9 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -101,3 +101,17 @@ static void __devinit malta_piix_func1_fixup(struct pci_dev *pdev)
 
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
          malta_piix_func1_fixup);
+
+/* Enable PCI 2.1 compatibility in PIIX4 */
+static void __devinit quirk_dlcsetup(struct pci_dev *dev)
+{
+        u8 odlc, ndlc;
+
+        (void) pci_read_config_byte(dev, 0x82, &odlc);
+        /* Enable passive releases and delayed transaction */
+        ndlc = odlc | 7;
+        (void) pci_write_config_byte(dev, 0x82, ndlc);
+}
+
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
+        quirk_dlcsetup);
diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c
index 3d86823d03a..76bb1be99d4 100644
--- a/arch/mips/pci/fixup-rc32434.c
+++ b/arch/mips/pci/fixup-rc32434.c
@@ -47,7 +47,7 @@ int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
         return irq + GROUP4_IRQ_BASE + 4;
 }
 
-static void rc32434_pci_early_fixup(struct pci_dev *dev)
+static void __devinit rc32434_pci_early_fixup(struct pci_dev *dev)
 {
         if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
                 /* disable prefetched memory range */
diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
index 822ae179bc5..65c7bd10048 100644
--- a/arch/mips/pci/ops-bcm63xx.c
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -411,7 +411,7 @@ struct pci_ops bcm63xx_cb_ops = {
  * only one IO window, so it  cannot be shared by PCI and cardbus, use
  * fixup to choose and detect unhandled configuration
  */
-static void bcm63xx_fixup(struct pci_dev *dev)
+static void __devinit bcm63xx_fixup(struct pci_dev *dev)
 {
         static int io_window = -1;
         int i, found, new_io_window;
@@ -465,3 +465,64 @@ static void bcm63xx_fixup(struct pci_dev *dev)
 
 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
 #endif
+
+static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
+{
+        switch (bus->number) {
+        case PCIE_BUS_BRIDGE:
+                return (PCI_SLOT(devfn) == 0);
+        case PCIE_BUS_DEVICE:
+                if (PCI_SLOT(devfn) == 0)
+                        return bcm_pcie_readl(PCIE_DLSTATUS_REG)
+                                        & DLSTATUS_PHYLINKUP;
+        default:
+                return false;
+        }
+}
+
+static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
+                             int where, int size, u32 *val)
+{
+        u32 data;
+        u32 reg = where & ~3;
+
+        if (!bcm63xx_pcie_can_access(bus, devfn))
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (bus->number == PCIE_BUS_DEVICE)
+                reg += PCIE_DEVICE_OFFSET;
+
+        data = bcm_pcie_readl(reg);
+
+        *val = postprocess_read(data, where, size);
+
+        return PCIBIOS_SUCCESSFUL;
+
+}
+
+static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
+                              int where, int size, u32 val)
+{
+        u32 data;
+        u32 reg = where & ~3;
+
+        if (!bcm63xx_pcie_can_access(bus, devfn))
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (bus->number == PCIE_BUS_DEVICE)
+                reg += PCIE_DEVICE_OFFSET;
+
+
+        data = bcm_pcie_readl(reg);
+
+        data = preprocess_write(data, val, where, size);
+        bcm_pcie_writel(data, reg);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+
+struct pci_ops bcm63xx_pcie_ops = {
+        .read   = bcm63xx_pcie_read,
+        .write  = bcm63xx_pcie_write
+};
diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
index 414a7459858..86d77a66645 100644
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -23,9 +23,12 @@
 #define AR724X_PCI_MEM_BASE     0x10000000
 #define AR724X_PCI_MEM_SIZE     0x08000000
 
+#define AR724X_PCI_REG_RESET            0x18
 #define AR724X_PCI_REG_INT_STATUS       0x4c
 #define AR724X_PCI_REG_INT_MASK         0x50
 
+#define AR724X_PCI_RESET_LINK_UP        BIT(0)
+
 #define AR724X_PCI_INT_DEV0             BIT(14)
 
 #define AR724X_PCI_IRQ_COUNT            1
@@ -38,6 +41,15 @@ static void __iomem *ar724x_pci_ctrl_base;
 
 static u32 ar724x_pci_bar0_value;
 static bool ar724x_pci_bar0_is_cached;
+static bool ar724x_pci_link_up;
+
+static inline bool ar724x_pci_check_link(void)
+{
+        u32 reset;
+
+        reset = __raw_readl(ar724x_pci_ctrl_base + AR724X_PCI_REG_RESET);
+        return reset & AR724X_PCI_RESET_LINK_UP;
+}
 
 static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
                             int size, uint32_t *value)
@@ -46,6 +58,9 @@ static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
         void __iomem *base;
         u32 data;
 
+        if (!ar724x_pci_link_up)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
         if (devfn)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
@@ -96,6 +111,9 @@ static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
         u32 data;
         int s;
 
+        if (!ar724x_pci_link_up)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
         if (devfn)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
@@ -280,6 +298,10 @@ int __init ar724x_pcibios_init(int irq)
         if (ar724x_pci_ctrl_base == NULL)
                 goto err_unmap_devcfg;
 
+        ar724x_pci_link_up = ar724x_pci_check_link();
+        if (!ar724x_pci_link_up)
+                pr_warn("ar724x: PCIe link is down\n");
+
         ar724x_pci_irq_init(irq);
         register_pci_controller(&ar724x_pci_controller);
 
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 39eb7c417e2..8a48139d219 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -10,6 +10,7 @@
 #include <linux/pci.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/delay.h>
 #include <asm/bootinfo.h>
 
 #include "pci-bcm63xx.h"
@@ -71,6 +72,26 @@ struct pci_controller bcm63xx_cb_controller = {
 };
 #endif
 
+static struct resource bcm_pcie_mem_resource = {
+        .name   = "bcm63xx PCIe memory space",
+        .start  = BCM_PCIE_MEM_BASE_PA,
+        .end    = BCM_PCIE_MEM_END_PA,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct resource bcm_pcie_io_resource = {
+        .name   = "bcm63xx PCIe IO space",
+        .start  = 0,
+        .end    = 0,
+        .flags  = 0,
+};
+
+struct pci_controller bcm63xx_pcie_controller = {
+        .pci_ops        = &bcm63xx_pcie_ops,
+        .io_resource    = &bcm_pcie_io_resource,
+        .mem_resource   = &bcm_pcie_mem_resource,
+};
+
 static u32 bcm63xx_int_cfg_readl(u32 reg)
 {
         u32 tmp;
@@ -94,17 +115,99 @@ static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
 
 void __iomem *pci_iospace_start;
 
-static int __init bcm63xx_pci_init(void)
+static void __init bcm63xx_reset_pcie(void)
 {
-        unsigned int mem_size;
         u32 val;
 
-        if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358() && !BCMCPU_IS_6368())
-                return -ENODEV;
+        /* enable clock */
+        val = bcm_perf_readl(PERF_CKCTL_REG);
+        val |= CKCTL_6328_PCIE_EN;
+        bcm_perf_writel(val, PERF_CKCTL_REG);
+
+        /* enable SERDES */
+        val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
+        val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
+        bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
+
+        /* reset the PCIe core */
+        val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
+
+        val &= ~SOFTRESET_6328_PCIE_MASK;
+        val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
+        val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
+        val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
+        bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+        mdelay(10);
+
+        val |= SOFTRESET_6328_PCIE_MASK;
+        val |= SOFTRESET_6328_PCIE_CORE_MASK;
+        val |= SOFTRESET_6328_PCIE_HARD_MASK;
+        bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+        mdelay(10);
+
+        val |= SOFTRESET_6328_PCIE_EXT_MASK;
+        bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
+        mdelay(200);
+}
 
-        if (!bcm63xx_pci_enabled)
-                return -ENODEV;
+static int __init bcm63xx_register_pcie(void)
+{
+        u32 val;
 
+        bcm63xx_reset_pcie();
+
+        /* configure the PCIe bridge */
+        val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
+        val |= OPT1_RD_BE_OPT_EN;
+        val |= OPT1_RD_REPLY_BE_FIX_EN;
+        val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
+        val |= OPT1_L1_INT_STATUS_MASK_POL;
+        bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
+
+        /* setup the interrupts */
+        val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
+        val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
+        bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
+
+        val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
+        /* enable credit checking and error checking */
+        val |= OPT2_TX_CREDIT_CHK_EN;
+        val |= OPT2_UBUS_UR_DECODE_DIS;
+
+        /* set device bus/func for the pcie device */
+        val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
+        val |= OPT2_CFG_TYPE1_BD_SEL;
+        bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
+
+        /* setup class code as bridge */
+        val = bcm_pcie_readl(PCIE_IDVAL3_REG);
+        val &= ~IDVAL3_CLASS_CODE_MASK;
+        val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
+        bcm_pcie_writel(val, PCIE_IDVAL3_REG);
+
+        /* disable bar1 size */
+        val = bcm_pcie_readl(PCIE_CONFIG2_REG);
+        val &= ~CONFIG2_BAR1_SIZE_MASK;
+        bcm_pcie_writel(val, PCIE_CONFIG2_REG);
+
+        /* set bar0 to little endian */
+        val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
+        val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
+        val |= BASEMASK_REMAP_EN;
+        bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
+
+        val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
+        bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
+
+        register_pci_controller(&bcm63xx_pcie_controller);
+
+        return 0;
+}
+
+static int __init bcm63xx_register_pci(void)
+{
+        unsigned int mem_size;
+        u32 val;
         /*
          * configuration  access are  done through  IO space,  remap 4
          * first bytes to access it from CPU.
@@ -221,4 +324,22 @@ static int __init bcm63xx_pci_init(void)
         return 0;
 }
 
+
+static int __init bcm63xx_pci_init(void)
+{
+        if (!bcm63xx_pci_enabled)
+                return -ENODEV;
+
+        switch (bcm63xx_get_cpu_id()) {
+        case BCM6328_CPU_ID:
+                return bcm63xx_register_pcie();
+        case BCM6348_CPU_ID:
+        case BCM6358_CPU_ID:
+        case BCM6368_CPU_ID:
+                return bcm63xx_register_pci();
+        default:
+                return -ENODEV;
+        }
+}
+
 arch_initcall(bcm63xx_pci_init);
diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h
index a6e594ef3d6..e6736d558ac 100644
--- a/arch/mips/pci/pci-bcm63xx.h
+++ b/arch/mips/pci/pci-bcm63xx.h
@@ -13,11 +13,16 @@
  */
 #define CARDBUS_PCI_IDSEL       0x8
 
+
+#define PCIE_BUS_BRIDGE         0
+#define PCIE_BUS_DEVICE         1
+
 /*
  * defined in ops-bcm63xx.c
  */
 extern struct pci_ops bcm63xx_pci_ops;
 extern struct pci_ops bcm63xx_cb_ops;
+extern struct pci_ops bcm63xx_pcie_ops;
 
 /*
  * defined in pci-bcm63xx.c
diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
new file mode 100644
index 00000000000..140557a2048
--- /dev/null
+++ b/arch/mips/pci/pci-xlp.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2003-2012 Broadcom Corporation
+ * All Rights Reserved
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the Broadcom
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/msi.h>
+#include <linux/mm.h>
+#include <linux/irq.h>
+#include <linux/irqdesc.h>
+#include <linux/console.h>
+
+#include <asm/io.h>
+
+#include <asm/netlogic/interrupt.h>
+#include <asm/netlogic/haldefs.h>
+
+#include <asm/netlogic/xlp-hal/iomap.h>
+#include <asm/netlogic/xlp-hal/pic.h>
+#include <asm/netlogic/xlp-hal/xlp.h>
+#include <asm/netlogic/xlp-hal/pcibus.h>
+#include <asm/netlogic/xlp-hal/bridge.h>
+
+static void *pci_config_base;
+
+#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
+
+/* PCI ops */
+static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
+        int where)
+{
+        u32 data;
+        u32 *cfgaddr;
+
+        cfgaddr = (u32 *)(pci_config_base +
+                        pci_cfg_addr(bus->number, devfn, where & ~3));
+        data = *cfgaddr;
+        return data;
+}
+
+static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
+        int where, u32 data)
+{
+        u32 *cfgaddr;
+
+        cfgaddr = (u32 *)(pci_config_base +
+                        pci_cfg_addr(bus->number, devfn, where & ~3));
+        *cfgaddr = data;
+}
+
+static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
+        int where, int size, u32 *val)
+{
+        u32 data;
+
+        if ((size == 2) && (where & 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        else if ((size == 4) && (where & 3))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        data = pci_cfg_read_32bit(bus, devfn, where);
+
+        if (size == 1)
+                *val = (data >> ((where & 3) << 3)) & 0xff;
+        else if (size == 2)
+                *val = (data >> ((where & 3) << 3)) & 0xffff;
+        else
+                *val = data;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
+                int where, int size, u32 val)
+{
+        u32 data;
+
+        if ((size == 2) && (where & 1))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        else if ((size == 4) && (where & 3))
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        data = pci_cfg_read_32bit(bus, devfn, where);
+
+        if (size == 1)
+                data = (data & ~(0xff << ((where & 3) << 3))) |
+                        (val << ((where & 3) << 3));
+        else if (size == 2)
+                data = (data & ~(0xffff << ((where & 3) << 3))) |
+                        (val << ((where & 3) << 3));
+        else
+                data = val;
+
+        pci_cfg_write_32bit(bus, devfn, where, data);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops nlm_pci_ops = {
+        .read  = nlm_pcibios_read,
+        .write = nlm_pcibios_write
+};
+
+static struct resource nlm_pci_mem_resource = {
+        .name           = "XLP PCI MEM",
+        .start          = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
+        .end            = 0xdfffffffUL,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct resource nlm_pci_io_resource = {
+        .name           = "XLP IO MEM",
+        .start          = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
+        .end            = 0x17ffffffUL,
+        .flags          = IORESOURCE_IO,
+};
+
+struct pci_controller nlm_pci_controller = {
+        .index          = 0,
+        .pci_ops        = &nlm_pci_ops,
+        .mem_resource   = &nlm_pci_mem_resource,
+        .mem_offset     = 0x00000000UL,
+        .io_resource    = &nlm_pci_io_resource,
+        .io_offset      = 0x00000000UL,
+};
+
+static int get_irq_vector(const struct pci_dev *dev)
+{
+        /*
+         * For XLP PCIe, there is an IRQ per Link, find out which
+         * link the device is on to assign interrupts
+        */
+        if (dev->bus->self == NULL)
+                return 0;
+
+        switch  (dev->bus->self->devfn) {
+        case 0x8:
+                return PIC_PCIE_LINK_0_IRQ;
+        case 0x9:
+                return PIC_PCIE_LINK_1_IRQ;
+        case 0xa:
+                return PIC_PCIE_LINK_2_IRQ;
+        case 0xb:
+                return PIC_PCIE_LINK_3_IRQ;
+        }
+        WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
+        return 0;
+}
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return get_irq_vector(dev);
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
+
+static int xlp_enable_pci_bswap(void)
+{
+        uint64_t pciebase, sysbase;
+        int node, i;
+        u32 reg;
+
+        /* Chip-0 so node set to 0 */
+        node = 0;
+        sysbase = nlm_get_bridge_regbase(node);
+        /*
+         *  Enable byte swap in hardware. Program each link's PCIe SWAP regions
+         * from the link's address ranges.
+         */
+        for (i = 0; i < 4; i++) {
+                pciebase = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, i));
+                if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff)
+                        continue;
+
+                reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_BASE0 + i);
+                nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_BASE, reg);
+
+                reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEMEM_LIMIT0 + i);
+                nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_MEM_LIM,
+                        reg | 0xfff);
+
+                reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_BASE0 + i);
+                nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_BASE, reg);
+
+                reg = nlm_read_bridge_reg(sysbase, BRIDGE_PCIEIO_LIMIT0 + i);
+                nlm_write_pci_reg(pciebase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff);
+        }
+        return 0;
+}
+
+static int __init pcibios_init(void)
+{
+        /* Firmware assigns PCI resources */
+        pci_set_flags(PCI_PROBE_ONLY);
+        pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
+
+        /* Extend IO port for memory mapped io */
+        ioport_resource.start =  0;
+        ioport_resource.end   = ~0;
+
+        xlp_enable_pci_bswap();
+        set_io_port_base(CKSEG1);
+        nlm_pci_controller.io_map_base = CKSEG1;
+
+        register_pci_controller(&nlm_pci_controller);
+        pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource,
+                &nlm_pci_mem_resource);
+
+        return 0;
+}
+arch_initcall(pcibios_init);
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 172af1cd586..18af021d289 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -375,7 +375,3 @@ static int __init pcibios_init(void)
 }
 
 arch_initcall(pcibios_init);
-
-struct pci_fixup pcibios_fixups[] = {
-        {0}
-};
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 271e8c4a54c..690356808f8 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -102,7 +102,7 @@ static void __devinit pcibios_scanbus(struct pci_controller *hose)
         need_domain_info = need_domain_info || hose->index;
         hose->need_domain_info = need_domain_info;
         if (bus) {
-                next_busno = bus->subordinate + 1;
+                next_busno = bus->busn_res.end + 1;
                 /* Don't allow 8-bit bus number overflow inside the hose -
                    reserve some space for bridges. */
                 if (next_busno > 224) {
@@ -348,9 +348,9 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                 vma->vm_end - vma->vm_start, vma->vm_page_prot);
 }
 
-char * (*pcibios_plat_setup)(char *str) __devinitdata;
+char * (*pcibios_plat_setup)(char *str) __initdata;
 
-char *__devinit pcibios_setup(char *str)
+char *__init pcibios_setup(char *str)
 {
         if (pcibios_plat_setup)
                 return pcibios_plat_setup(str);
diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c
index 63be40e470d..14dc9c8fff0 100644
--- a/arch/mips/pmc-sierra/yosemite/ht.c
+++ b/arch/mips/pmc-sierra/yosemite/ht.c
@@ -395,17 +395,6 @@ void __init pcibios_init(void)
         pci_scan_bus(3, &titan_pci_ops, NULL);
 }
 
-/*
- * for parsing "pci=" kernel boot arguments.
- */
-char *pcibios_setup(char *str)
-{
-        printk(KERN_INFO "rr: pcibios_setup\n");
-        /* Nothing to do for now.  */
-
-        return str;
-}
-
 unsigned __init int pcibios_assign_all_busses(void)
 {
         /* We want to use the PCI bus detection done by PMON */
diff --git a/arch/mips/pnx833x/stb22x/board.c b/arch/mips/pnx833x/stb22x/board.c
index 644eb7c3210..4b328ac4305 100644
--- a/arch/mips/pnx833x/stb22x/board.c
+++ b/arch/mips/pnx833x/stb22x/board.c
@@ -91,7 +91,7 @@ void __init pnx833x_board_setup(void)
         pnx833x_gpio_select_function_alt(32);
         pnx833x_gpio_select_function_alt(33);
 
-#if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_PLATFORM)
         /* Setup MIU for NAND access on CS0...
          *
          * (it seems that we must also configure CS1 for reliable operation,
@@ -117,7 +117,7 @@ void __init pnx833x_board_setup(void)
         pnx833x_gpio_select_output(5);
         pnx833x_gpio_write(1, 5);
 
-#elif defined(CONFIG_MTD_CFI) || defined(CONFIG_MTD_CFI_MODULE)
+#elif IS_ENABLED(CONFIG_MTD_CFI)
 
         /* Set up MIU for 16-bit NOR access on CS0 and CS1... */
 
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
index 3933c373a43..820b8480f22 100644
--- a/arch/mips/powertv/powertv_setup.c
+++ b/arch/mips/powertv/powertv_setup.c
@@ -254,7 +254,7 @@ early_param("rfmac", rfmac_param);
  * Generates an Ethernet MAC address that is highly likely to be unique for
  * this particular system on a network with other systems of the same type.
  *
- * The problem we are solving is that, when random_ether_addr() is used to
+ * The problem we are solving is that, when eth_random_addr() is used to
  * generate MAC addresses at startup, there isn't much entropy for the random
  * number generator to use and the addresses it produces are fairly likely to
  * be the same as those of other identical systems on the same local network.
@@ -269,7 +269,7 @@ early_param("rfmac", rfmac_param);
  * Still, this does give us something to work with.
  *
  * The approach we take is:
- * 1.   If we can't get the RF MAC Address, just call random_ether_addr.
+ * 1.   If we can't get the RF MAC Address, just call eth_random_addr.
  * 2.   Use the 24-bit NIC-specific bits of the RF MAC address as the last 24
  *      bits of the new address. This is very likely to be unique, except for
  *      the current box.
@@ -299,7 +299,7 @@ void platform_random_ether_addr(u8 addr[ETH_ALEN])
         if (!have_rfmac) {
                 pr_warning("rfmac not available on command line; "
                         "generating random MAC address\n");
-                random_ether_addr(addr);
+                eth_random_addr(addr);
         }
 
         else {
diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c
index b105eca3c02..cd8fcab6b05 100644
--- a/arch/mips/sgi-ip27/ip27-memory.c
+++ b/arch/mips/sgi-ip27/ip27-memory.c
@@ -401,6 +401,7 @@ static void __init node_mem_init(cnodeid_t node)
          * Allocate the node data structures on the node first.
          */
         __node_data[node] = __va(slot_freepfn << PAGE_SHIFT);
+        memset(__node_data[node], 0, PAGE_SIZE);
 
         NODE_DATA(node)->bdata = &bootmem_node_data[node];
         NODE_DATA(node)->node_start_pfn = start_pfn;
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 852ae4bb7a8..6d40bc78345 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -20,6 +20,7 @@ config MACH_TXX9
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_SUPPORTS_BIG_ENDIAN
+        select HAVE_CLK
 
 config TOSHIBA_JMR3927
         bool "Toshiba JMR-TX3927 board"
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 64eb71b1528..4efd9185f29 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -256,7 +256,7 @@ static irqreturn_t i8259_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static int __init
+static int __devinit
 txx9_i8259_irq_setup(int irq)
 {
         int err;
@@ -304,7 +304,7 @@ static void __devinit quirk_slc90e66_bridge(struct pci_dev *dev)
         smsc_fdc37m81x_config_end();
 }
 
-static void quirk_slc90e66_ide(struct pci_dev *dev)
+static void __devinit quirk_slc90e66_ide(struct pci_dev *dev)
 {
         unsigned char dat;
         int regs[2] = {0x41, 0x43};
@@ -339,7 +339,7 @@ static void quirk_slc90e66_ide(struct pci_dev *dev)
 }
 #endif /* CONFIG_TOSHIBA_FPCIB0 */
 
-static void tc35815_fixup(struct pci_dev *dev)
+static void __devinit tc35815_fixup(struct pci_dev *dev)
 {
         /* This device may have PM registers but not they are not suported. */
         if (dev->pm_cap) {
@@ -348,7 +348,7 @@ static void tc35815_fixup(struct pci_dev *dev)
         }
 }
 
-static void final_fixup(struct pci_dev *dev)
+static void __devinit final_fixup(struct pci_dev *dev)
 {
         unsigned char bist;
 
@@ -398,9 +398,9 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
         return txx9_board_vec->pci_map_irq(dev, slot, pin);
 }
 
-char * (*txx9_board_pcibios_setup)(char *str) __devinitdata;
+char * (*txx9_board_pcibios_setup)(char *str) __initdata;
 
-char *__devinit txx9_pcibios_setup(char *str)
+char *__init txx9_pcibios_setup(char *str)
 {
         if (txx9_board_pcibios_setup && !txx9_board_pcibios_setup(str))
                 return NULL;
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index ae77a7916c0..560fe899175 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -632,7 +632,7 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr,
                                     unsigned long size,
                                     const struct physmap_flash_data *pdata)
 {
-#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
         struct resource res = {
                 .start = addr,
                 .end = addr + size - 1,
@@ -670,8 +670,7 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr,
 void __init txx9_ndfmc_init(unsigned long baseaddr,
                             const struct txx9ndfmc_platform_data *pdata)
 {
-#if defined(CONFIG_MTD_NAND_TXX9NDFMC) || \
-        defined(CONFIG_MTD_NAND_TXX9NDFMC_MODULE)
+#if IS_ENABLED(CONFIG_MTD_NAND_TXX9NDFMC)
         struct resource res = {
                 .start = baseaddr,
                 .end = baseaddr + 0x1000 - 1,
@@ -687,7 +686,7 @@ void __init txx9_ndfmc_init(unsigned long baseaddr,
 #endif
 }
 
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+#if IS_ENABLED(CONFIG_LEDS_GPIO)
 static DEFINE_SPINLOCK(txx9_iocled_lock);
 
 #define TXX9_IOCLED_MAXLEDS 8
@@ -810,7 +809,7 @@ void __init txx9_iocled_init(unsigned long baseaddr,
 void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq,
                            const struct txx9dmac_platform_data *pdata)
 {
-#if defined(CONFIG_TXX9_DMAC) || defined(CONFIG_TXX9_DMAC_MODULE)
+#if IS_ENABLED(CONFIG_TXX9_DMAC)
         struct resource res[] = {
                 {
                         .start = baseaddr,
@@ -866,8 +865,7 @@ void __init txx9_aclc_init(unsigned long baseaddr, int irq,
                            unsigned int dma_chan_out,
                            unsigned int dma_chan_in)
 {
-#if defined(CONFIG_SND_SOC_TXX9ACLC) || \
-        defined(CONFIG_SND_SOC_TXX9ACLC_MODULE)
+#if IS_ENABLED(CONFIG_SND_SOC_TXX9ACLC)
         unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
         struct resource res[] = {
                 {
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index 6567895d1f5..5ff7a9584da 100644
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -317,7 +317,7 @@ void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
         }
 }
 
-#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
+#if IS_ENABLED(CONFIG_TC35815)
 static u32 tx4939_get_eth_speed(struct net_device *dev)
 {
         struct ethtool_cmd cmd;
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 2ad8973ba13..e15641d9309 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -40,8 +40,7 @@ static void __init rbtx4939_time_init(void)
         tx4939_time_init(0);
 }
 
-#if defined(__BIG_ENDIAN) && \
-        (defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE))
+#if defined(__BIG_ENDIAN) && IS_ENABLED(CONFIG_SMC91X)
 #define HAVE_RBTX4939_IOSWAB
 #define IS_CE1_ADDR(addr) \
         ((((unsigned long)(addr) - IO_BASE) & 0xfff00000) == TXX9_CE(1))
@@ -187,7 +186,7 @@ static void __init rbtx4939_update_ioc_pen(void)
 
 #define RBTX4939_MAX_7SEGLEDS   8
 
-#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
+#if IS_ENABLED(CONFIG_LEDS_CLASS)
 static u8 led_val[RBTX4939_MAX_7SEGLEDS];
 struct rbtx4939_led_data {
         struct led_classdev cdev;
@@ -263,7 +262,7 @@ static inline void rbtx4939_led_setup(void)
 
 static void __rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
 {
-#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
+#if IS_ENABLED(CONFIG_LEDS_CLASS)
         unsigned long flags;
         local_irq_save(flags);
         /* bit7: reserved for LED class */
@@ -287,7 +286,7 @@ static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val)
         __rbtx4939_7segled_putc(pos, val);
 }
 
-#if defined(CONFIG_MTD_RBTX4939) || defined(CONFIG_MTD_RBTX4939_MODULE)
+#if IS_ENABLED(CONFIG_MTD_RBTX4939)
 /* special mapping for boot rom */
 static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs)
 {
@@ -463,7 +462,7 @@ static void __init rbtx4939_device_init(void)
                 .flags = SMC91X_USE_16BIT,
         };
         struct platform_device *pdev;
-#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
+#if IS_ENABLED(CONFIG_TC35815)
         int i, j;
         unsigned char ethaddr[2][6];
         u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 687f9b4a2ed..5cfb086b390 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -3,6 +3,7 @@ config MN10300
         select HAVE_OPROFILE
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_SHOW
+        select ARCH_WANT_IPC_PARSE_VERSION
         select HAVE_ARCH_TRACEHOOK
         select HAVE_ARCH_KGDB
         select HAVE_NMI_WATCHDOG if MN10300_WD_TIMER
diff --git a/arch/mn10300/include/asm/ipc.h b/arch/mn10300/include/asm/ipc.h
deleted file mode 100644
index a46e3d9c2a3..00000000000
--- a/arch/mn10300/include/asm/ipc.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ipc.h>
diff --git a/arch/mn10300/include/asm/unistd.h b/arch/mn10300/include/asm/unistd.h
index 9051f921cbc..866eb14749d 100644
--- a/arch/mn10300/include/asm/unistd.h
+++ b/arch/mn10300/include/asm/unistd.h
@@ -358,7 +358,6 @@
 /*
  * specify the deprecated syscalls we want to support on this arch
  */
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_OLD_STAT
 #define __ARCH_WANT_STAT64
diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c
index 090d35d3697..e62c223e4c4 100644
--- a/arch/mn10300/kernel/smp.c
+++ b/arch/mn10300/kernel/smp.c
@@ -876,9 +876,7 @@ static void __init smp_online(void)
 
         notify_cpu_starting(cpu);
 
-        ipi_call_lock();
         set_cpu_online(cpu, true);
-        ipi_call_unlock();
 
         local_irq_enable();
 }
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 3f35c38d7b6..0922959663a 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -13,7 +13,6 @@ generic-y += cacheflush.h
 generic-y += checksum.h
 generic-y += cmpxchg.h
 generic-y += cmpxchg-local.h
-generic-y += cpumask.h
 generic-y += cputime.h
 generic-y += current.h
 generic-y += device.h
@@ -43,7 +42,6 @@ generic-y += percpu.h
 generic-y += poll.h
 generic-y += posix_types.h
 generic-y += resource.h
-generic-y += rmap.h
 generic-y += scatterlist.h
 generic-y += sections.h
 generic-y += segment.h
diff --git a/arch/parisc/include/asm/atomic.h b/arch/parisc/include/asm/atomic.h
index 6c6defc2461..af9cf30ed47 100644
--- a/arch/parisc/include/asm/atomic.h
+++ b/arch/parisc/include/asm/atomic.h
@@ -141,7 +141,7 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
 
 #define atomic_sub_and_test(i,v)        (atomic_sub_return((i),(v)) == 0)
 
-#define ATOMIC_INIT(i)  ((atomic_t) { (i) })
+#define ATOMIC_INIT(i)  { (i) }
 
 #define smp_mb__before_atomic_dec()     smp_mb()
 #define smp_mb__after_atomic_dec()      smp_mb()
@@ -150,7 +150,7 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
 
 #ifdef CONFIG_64BIT
 
-#define ATOMIC64_INIT(i) ((atomic64_t) { (i) })
+#define ATOMIC64_INIT(i) { (i) }
 
 static __inline__ s64
 __atomic64_add_return(s64 i, atomic64_t *v)
diff --git a/arch/parisc/include/asm/compat_rt_sigframe.h b/arch/parisc/include/asm/compat_rt_sigframe.h
index 81bec28bdc4..b3f95a7f18b 100644
--- a/arch/parisc/include/asm/compat_rt_sigframe.h
+++ b/arch/parisc/include/asm/compat_rt_sigframe.h
@@ -1,6 +1,6 @@
-#include<linux/compat.h>
-#include<linux/compat_siginfo.h>
-#include<asm/compat_ucontext.h>
+#include <linux/compat.h>
+#include <linux/compat_siginfo.h>
+#include <asm/compat_ucontext.h>
 
 #ifndef _ASM_PARISC_COMPAT_RT_SIGFRAME_H
 #define _ASM_PARISC_COMPAT_RT_SIGFRAME_H
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index 24644aca10c..60309051875 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -139,11 +139,6 @@ void pcibios_fixup_bus(struct pci_bus *bus)
 }
 
 
-char *pcibios_setup(char *str)
-{
-        return str;
-}
-
 /*
  * Called by pci_set_master() - a driver interface.
  *
diff --git a/arch/parisc/kernel/process.c b/arch/parisc/kernel/process.c
index d4b94b395c1..2c05a9292a8 100644
--- a/arch/parisc/kernel/process.c
+++ b/arch/parisc/kernel/process.c
@@ -309,7 +309,7 @@ copy_thread(unsigned long clone_flags, unsigned long usp,
                 cregs->ksp = (unsigned long)stack
                         + (pregs->gr[21] & (THREAD_SIZE - 1));
                 cregs->gr[30] = usp;
-                if (p->personality == PER_HPUX) {
+                if (personality(p->personality) == PER_HPUX) {
 #ifdef CONFIG_HPUX
                         cregs->kpc = (unsigned long) &hpux_child_return;
 #else
diff --git a/arch/parisc/kernel/smp.c b/arch/parisc/kernel/smp.c
index a47828d31fe..6266730efd6 100644
--- a/arch/parisc/kernel/smp.c
+++ b/arch/parisc/kernel/smp.c
@@ -300,9 +300,7 @@ smp_cpu_init(int cpunum)
 
         notify_cpu_starting(cpunum);
 
-        ipi_call_lock();
         set_cpu_online(cpunum, true);
-        ipi_call_unlock();
 
         /* Initialise the idle task for this CPU */
         atomic_inc(&init_mm.mm_count);
diff --git a/arch/parisc/kernel/sys_parisc.c b/arch/parisc/kernel/sys_parisc.c
index c9b932260f4..7426e40699b 100644
--- a/arch/parisc/kernel/sys_parisc.c
+++ b/arch/parisc/kernel/sys_parisc.c
@@ -225,12 +225,12 @@ long parisc_personality(unsigned long personality)
         long err;
 
         if (personality(current->personality) == PER_LINUX32
-            && personality == PER_LINUX)
-                personality = PER_LINUX32;
+            && personality(personality) == PER_LINUX)
+                personality = (personality & ~PER_MASK) | PER_LINUX32;
 
         err = sys_personality(personality);
-        if (err == PER_LINUX32)
-                err = PER_LINUX;
+        if (personality(err) == PER_LINUX32)
+                err = (err & ~PER_MASK) | PER_LINUX;
 
         return err;
 }
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 050cb371a69..352f416269c 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -115,11 +115,13 @@ config PPC
         select HAVE_OPROFILE
         select HAVE_SYSCALL_WRAPPERS if PPC64
         select GENERIC_ATOMIC64 if PPC32
+        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
         select HAVE_IRQ_WORK
         select HAVE_PERF_EVENTS
         select HAVE_REGS_AND_STACK_ACCESS_API
         select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
         select HAVE_GENERIC_HARDIRQS
+        select ARCH_WANT_IPC_PARSE_VERSION
         select SPARSE_IRQ
         select IRQ_PER_CPU
         select IRQ_DOMAIN
@@ -653,7 +655,7 @@ config SBUS
 config FSL_SOC
         bool
         select HAVE_CAN_FLEXCAN if NET && CAN
-        select PPC_CLOCK if CAN_FLEXCAN
+        select PPC_CLOCK
 
 config FSL_PCI
         bool
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index e5f26890a69..5416e28a753 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -331,4 +331,13 @@ config STRICT_DEVMEM
 
           If you are unsure, say Y.
 
+config FAIL_IOMMU
+        bool "Fault-injection capability for IOMMU"
+        depends on FAULT_INJECTION
+        help
+          Provide fault-injection capability for IOMMU. Each device can
+          be selectively enabled via the fail_iommu property.
+
+          If you are unsure, say N.
+
 endmenu
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 950d1f7a5a3..159e94f4b22 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -149,7 +149,6 @@ core-$(CONFIG_KVM) 		+= arch/powerpc/kvm/
 core-$(CONFIG_PERF_EVENTS)      += arch/powerpc/perf/
 
 drivers-$(CONFIG_OPROFILE)      += arch/powerpc/oprofile/
-drivers-$(CONFIG_CRYPTO_DEV_NX) += drivers/crypto/nx/
 
 # Default to zImage, override when needed
 all: zImage
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index e8461cb18d0..b7d833382be 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -62,26 +62,45 @@ libfdtheader := fdt.h libfdt.h libfdt_internal.h
 $(addprefix $(obj)/,$(libfdt) libfdt-wrapper.o simpleboot.o epapr.o): \
         $(addprefix $(obj)/,$(libfdtheader))
 
-src-wlib := string.S crt0.S crtsavres.S stdio.c main.c \
+src-wlib-y := string.S crt0.S crtsavres.S stdio.c main.c \
                 $(libfdt) libfdt-wrapper.c \
                 ns16550.c serial.c simple_alloc.c div64.S util.S \
-                gunzip_util.c elf_util.c $(zlib) devtree.c oflib.c ofconsole.c \
-                4xx.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c cuboot.c bamboo.c \
-                cpm-serial.c stdlib.c mpc52xx-psc.c planetcore.c uartlite.c \
-                fsl-soc.c mpc8xx.c pq2.c ugecon.c
-src-plat := of.c cuboot-52xx.c cuboot-824x.c cuboot-83xx.c cuboot-85xx.c holly.c \
-                cuboot-ebony.c cuboot-hotfoot.c epapr.c treeboot-ebony.c \
-                prpmc2800.c \
-                ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \
-                cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
-                cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
-                fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \
-                cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
-                cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
-                virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
-                cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
-                gamecube-head.S gamecube.c wii-head.S wii.c treeboot-iss4xx.c \
-                treeboot-currituck.c
+                gunzip_util.c elf_util.c $(zlib) devtree.c stdlib.c \
+                oflib.c ofconsole.c cuboot.c mpsc.c cpm-serial.c \
+                uartlite.c mpc52xx-psc.c
+src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c
+src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
+src-wlib-$(CONFIG_8xx) += mpc8xx.c planetcore.c
+src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
+src-wlib-$(CONFIG_EMBEDDED6xx) += mv64x60.c mv64x60_i2c.c ugecon.c
+
+src-plat-y := of.c
+src-plat-$(CONFIG_40x) += fixed-head.S ep405.c cuboot-hotfoot.c \
+                                treeboot-walnut.c cuboot-acadia.c \
+                                cuboot-kilauea.c simpleboot.c \
+                                virtex405-head.S virtex.c
+src-plat-$(CONFIG_44x) += treeboot-ebony.c cuboot-ebony.c treeboot-bamboo.c \
+                                cuboot-bamboo.c cuboot-sam440ep.c \
+                                cuboot-sequoia.c cuboot-rainier.c \
+                                cuboot-taishan.c cuboot-katmai.c \
+                                cuboot-warp.c cuboot-yosemite.c \
+                                treeboot-iss4xx.c treeboot-currituck.c \
+                                simpleboot.c fixed-head.S virtex.c
+src-plat-$(CONFIG_8xx) += cuboot-8xx.c fixed-head.S ep88xc.c redboot-8xx.c
+src-plat-$(CONFIG_PPC_MPC52xx) += cuboot-52xx.c
+src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
+src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
+src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
+src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
+                                        cuboot-c2k.c gamecube-head.S \
+                                        gamecube.c wii-head.S wii.c holly.c \
+                                        prpmc2800.c
+src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
+src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
+src-plat-$(CONFIG_EPAPR_BOOT) += epapr.c
+
+src-wlib := $(sort $(src-wlib-y))
+src-plat := $(sort $(src-plat-y))
 src-boot := $(src-wlib) $(src-plat) empty.c
 
 src-boot := $(addprefix $(obj)/, $(src-boot))
@@ -257,7 +276,6 @@ image-$(CONFIG_TQM8548)			+= cuImage.tqm8548
 image-$(CONFIG_TQM8555)                 += cuImage.tqm8555
 image-$(CONFIG_TQM8560)                 += cuImage.tqm8560
 image-$(CONFIG_SBC8548)                 += cuImage.sbc8548
-image-$(CONFIG_SBC8560)                 += cuImage.sbc8560
 image-$(CONFIG_KSI8560)                 += cuImage.ksi8560
 
 # Board ports in arch/powerpc/platform/embedded6xx/Kconfig
@@ -412,4 +430,3 @@ $(wrapper-installed): $(DESTDIR)$(WRAPPER_BINDIR) $(srctree)/$(obj)/wrapper | $(
         $(call cmd,install_wrapper)
 
 $(obj)/bootwrapper_install: $(all-installed)
-
diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dts b/arch/powerpc/boot/dts/bsc9131rdb.dts
new file mode 100644
index 00000000000..e13d2d4877b
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9131rdb.dts
@@ -0,0 +1,34 @@
+/*
+ * BSC9131 RDB Device Tree Source
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/include/ "fsl/bsc9131si-pre.dtsi"
+
+/ {
+        model = "fsl,bsc9131rdb";
+        compatible = "fsl,bsc9131rdb";
+
+        memory {
+                device_type = "memory";
+        };
+
+        board_ifc: ifc: ifc@ff71e000 {
+                /* NAND Flash on board */
+                ranges = <0x0 0x0 0x0 0xff800000 0x00004000>;
+                reg = <0x0 0xff71e000 0x0 0x2000>;
+        };
+
+        board_soc: soc: soc@ff700000 {
+                ranges = <0x0 0x0 0xff700000 0x100000>;
+        };
+};
+
+/include/ "bsc9131rdb.dtsi"
+/include/ "fsl/bsc9131si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/bsc9131rdb.dtsi b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
new file mode 100644
index 00000000000..638adda2c21
--- /dev/null
+++ b/arch/powerpc/boot/dts/bsc9131rdb.dtsi
@@ -0,0 +1,142 @@
+/*
+ * BSC9131 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&board_ifc {
+
+        nand@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,ifc-nand";
+                reg = <0x0 0x0 0x4000>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 3MB for u-boot Bootloader Image */
+                        reg = <0x0 0x00300000>;
+                        label = "NAND U-Boot Image";
+                        read-only;
+                };
+
+                partition@300000 {
+                        /* 1MB for DTB Image */
+                        reg = <0x00300000 0x00100000>;
+                        label = "NAND DTB Image";
+                };
+
+                partition@400000 {
+                        /* 8MB for Linux Kernel Image */
+                        reg = <0x00400000 0x00800000>;
+                        label = "NAND Linux Kernel Image";
+                };
+
+                partition@c00000 {
+                        /* Rest space for Root file System Image */
+                        reg = <0x00c00000 0x07400000>;
+                        label = "NAND RFS Image";
+                };
+        };
+};
+
+&board_soc {
+        /* BSC9131RDB does not have any device on i2c@3100 */
+        i2c@3100 {
+                status = "disabled";
+        };
+
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,s25sl12801";
+                        reg = <0>;
+                        spi-max-frequency = <50000000>;
+
+                        /* 512KB for u-boot Bootloader Image */
+                        partition@0 {
+                                reg = <0x0 0x00080000>;
+                                label = "SPI Flash U-Boot Image";
+                                read-only;
+                        };
+
+                        /* 512KB for DTB Image */
+                        partition@80000 {
+                                reg = <0x00080000 0x00080000>;
+                                label = "SPI Flash DTB Image";
+                        };
+
+                        /* 4MB for Linux Kernel Image */
+                        partition@100000 {
+                                reg = <0x00100000 0x00400000>;
+                                label = "SPI Flash Kernel Image";
+                        };
+
+                        /*11MB for RFS Image */
+                        partition@500000 {
+                                reg = <0x00500000 0x00B00000>;
+                                label = "SPI Flash RFS Image";
+                        };
+
+                };
+        };
+
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <3 1 0 0>;
+                        reg = <0x0>;
+                };
+
+                phy1: ethernet-phy@1 {
+                        interrupts = <2 1 0 0>;
+                        reg = <0x3>;
+                };
+        };
+
+        sdhci@2e000 {
+                status = "disabled";
+        };
+
+        enet0: ethernet@b0000 {
+                phy-handle = <&phy0>;
+                phy-connection-type = "rgmii-id";
+        };
+
+        enet1: ethernet@b1000 {
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
new file mode 100644
index 00000000000..5180d9d3798
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
@@ -0,0 +1,193 @@
+/*
+ * BSC9131 Silicon/SoC Device Tree Source (post include)
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&ifc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        compatible = "fsl,ifc", "simple-bus";
+        interrupts = <16 2 0 0 20 2 0 0>;
+};
+
+&soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        device_type = "soc";
+        compatible = "fsl,bsc9131-immr", "simple-bus";
+        bus-frequency = <0>;            // Filled out by uboot.
+
+        ecm-law@0 {
+                compatible = "fsl,ecm-law";
+                reg = <0x0 0x1000>;
+                fsl,num-laws = <12>;
+        };
+
+        ecm@1000 {
+                compatible = "fsl,bsc9131-ecm", "fsl,ecm";
+                reg = <0x1000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+
+        memory-controller@2000 {
+                compatible = "fsl,bsc9131-memory-controller";
+                reg = <0x2000 0x1000>;
+                interrupts = <16 2 0 0>;
+        };
+
+/include/ "pq3-i2c-0.dtsi"
+        i2c@3000 {
+                interrupts = <17 2 0 0>;
+        };
+
+/include/ "pq3-i2c-1.dtsi"
+        i2c@3100 {
+                interrupts = <17 2 0 0>;
+        };
+
+/include/ "pq3-duart-0.dtsi"
+        serial0: serial@4500 {
+                interrupts = <18 2 0 0>;
+        };
+
+        serial1: serial@4600 {
+                interrupts = <18 2 0 0 >;
+        };
+/include/ "pq3-espi-0.dtsi"
+        spi0: spi@7000 {
+                fsl,espi-num-chipselects = <1>;
+                interrupts = <22 0x2 0 0>;
+        };
+
+/include/ "pq3-gpio-0.dtsi"
+        gpio-controller@f000 {
+                interrupts = <19 0x2 0 0>;
+                };
+
+        L2: l2-cache-controller@20000 {
+                compatible = "fsl,bsc9131-l2-cache-controller";
+                reg = <0x20000 0x1000>;
+                cache-line-size = <32>; // 32 bytes
+                cache-size = <0x40000>; // L2,256K
+                interrupts = <16 2 0 0>;
+        };
+
+/include/ "pq3-dma-0.dtsi"
+
+dma@21300 {
+
+        dma-channel@0 {
+                interrupts = <62 2 0 0>;
+        };
+
+        dma-channel@80 {
+                interrupts = <63 2 0 0>;
+        };
+
+        dma-channel@100 {
+                interrupts = <64 2 0 0>;
+        };
+
+        dma-channel@180 {
+                interrupts = <65 2 0 0>;
+        };
+};
+
+/include/ "pq3-usb2-dr-0.dtsi"
+usb@22000 {
+        compatible = "fsl-usb2-dr","fsl-usb2-dr-v2.2";
+        interrupts = <40 0x2 0 0>;
+};
+
+/include/ "pq3-esdhc-0.dtsi"
+        sdhc@2e000 {
+                fsl,sdhci-auto-cmd12;
+                interrupts = <41 0x2 0 0>;
+        };
+
+/include/ "pq3-sec4.4-0.dtsi"
+crypto@30000 {
+        interrupts       = <57 2 0 0>;
+
+        sec_jr0: jr@1000 {
+                interrupts       = <58 2 0 0>;
+        };
+
+        sec_jr1: jr@2000 {
+                interrupts       = <59 2 0 0>;
+        };
+
+        sec_jr2: jr@3000 {
+                interrupts       = <60 2 0 0>;
+        };
+
+        sec_jr3: jr@4000 {
+                interrupts       = <61 2 0 0>;
+        };
+};
+
+/include/ "pq3-mpic.dtsi"
+
+timer@41100 {
+        compatible = "fsl,mpic-v1.2-msgr", "fsl,mpic-msg";
+        reg = <0x41400 0x200>;
+        interrupts = <
+                0xb0 2
+                0xb1 2
+                0xb2 2
+                0xb3 2>;
+};
+
+/include/ "pq3-etsec2-0.dtsi"
+enet0: ethernet@b0000 {
+        queue-group@b0000 {
+                fsl,rx-bit-map = <0xff>;
+                fsl,tx-bit-map = <0xff>;
+                interrupts = <26 2 0 0 27 2 0 0 28 2 0 0>;
+        };
+};
+
+/include/ "pq3-etsec2-1.dtsi"
+enet1: ethernet@b1000 {
+        queue-group@b1000 {
+                fsl,rx-bit-map = <0xff>;
+                fsl,tx-bit-map = <0xff>;
+                interrupts = <33 2 0 0 34 2 0 0 35 2 0 0>;
+        };
+};
+
+global-utilities@e0000 {
+                compatible = "fsl,bsc9131-guts";
+                reg = <0xe0000 0x1000>;
+                fsl,has-rstcr;
+        };
+};
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi b/arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
index 00c8e70e7b9..743e4aeda34 100644
--- a/arch/powerpc/boot/dts/fsl/p3060si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
@@ -1,7 +1,7 @@
 /*
- * P3060 Silicon/SoC Device Tree Source (pre include)
+ * BSC9131 Silicon/SoC Device Tree Source (pre include)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -34,92 +34,26 @@
 
 /dts-v1/;
 / {
-        compatible = "fsl,P3060";
+        compatible = "fsl,BSC9131";
         #address-cells = <2>;
         #size-cells = <2>;
         interrupt-parent = <&mpic>;
 
         aliases {
-                ccsr = &soc;
-                dcsr = &dcsr;
-
                 serial0 = &serial0;
-                serial1 = &serial1;
-                serial2 = &serial2;
-                serial3 = &serial3;
-                pci0 = &pci0;
-                pci1 = &pci1;
-                usb0 = &usb0;
-                usb1 = &usb1;
-                dma0 = &dma0;
-                dma1 = &dma1;
-                msi0 = &msi0;
-                msi1 = &msi1;
-                msi2 = &msi2;
-
-                crypto = &crypto;
-                sec_jr0 = &sec_jr0;
-                sec_jr1 = &sec_jr1;
-                sec_jr2 = &sec_jr2;
-                sec_jr3 = &sec_jr3;
-                rtic_a = &rtic_a;
-                rtic_b = &rtic_b;
-                rtic_c = &rtic_c;
-                rtic_d = &rtic_d;
-                sec_mon = &sec_mon;
+                ethernet0 = &enet0;
+                ethernet1 = &enet1;
         };
 
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                cpu0: PowerPC,e500mc@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        next-level-cache = <&L2_0>;
-                        L2_0: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu1: PowerPC,e500mc@1 {
-                        device_type = "cpu";
-                        reg = <1>;
-                        next-level-cache = <&L2_1>;
-                        L2_1: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu4: PowerPC,e500mc@4 {
-                        device_type = "cpu";
-                        reg = <4>;
-                        next-level-cache = <&L2_4>;
-                        L2_4: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu5: PowerPC,e500mc@5 {
-                        device_type = "cpu";
-                        reg = <5>;
-                        next-level-cache = <&L2_5>;
-                        L2_5: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu6: PowerPC,e500mc@6 {
-                        device_type = "cpu";
-                        reg = <6>;
-                        next-level-cache = <&L2_6>;
-                        L2_6: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
-                };
-                cpu7: PowerPC,e500mc@7 {
+                PowerPC,BSC9131@0 {
                         device_type = "cpu";
-                        reg = <7>;
-                        next-level-cache = <&L2_7>;
-                        L2_7: l2-cache {
-                                next-level-cache = <&cpc>;
-                        };
+                        compatible = "fsl,e500v2";
+                        reg = <0x0>;
+                        next-level-cache = <&L2>;
                 };
         };
 };
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
index 4252ef85fb7..adb82fd9057 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -1,7 +1,7 @@
 /*
  * P1021/P1012 Silicon/SoC Device Tree Source (post include)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -213,6 +213,20 @@
                 interrupt-parent = <&qeic>;
         };
 
+        ucc@2600 {
+                cell-index = <7>;
+                reg = <0x2600 0x200>;
+                interrupts = <42>;
+                interrupt-parent = <&qeic>;
+        };
+
+        ucc@2200 {
+                cell-index = <3>;
+                reg = <0x2200 0x200>;
+                interrupts = <34>;
+                interrupt-parent = <&qeic>;
+        };
+
         muram@10000 {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
deleted file mode 100644
index b3e56929eee..00000000000
--- a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * P3060 Silicon/SoC Device Tree Source (post include)
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-&lbc {
-        compatible = "fsl,p3060-elbc", "fsl,elbc", "simple-bus";
-        interrupts = <25 2 0 0>;
-        #address-cells = <2>;
-        #size-cells = <1>;
-};
-
-/* controller at 0x200000 */
-&pci0 {
-        compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
-        device_type = "pci";
-        #size-cells = <2>;
-        #address-cells = <3>;
-        bus-range = <0x0 0xff>;
-        clock-frequency = <33333333>;
-        interrupts = <16 2 1 15>;
-        pcie@0 {
-                reg = <0 0 0 0 0>;
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                device_type = "pci";
-                interrupts = <16 2 1 15>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 40 1 0 0
-                        0000 0 0 2 &mpic 1 1 0 0
-                        0000 0 0 3 &mpic 2 1 0 0
-                        0000 0 0 4 &mpic 3 1 0 0
-                        >;
-        };
-};
-
-/* controller at 0x201000 */
-&pci1 {
-        compatible = "fsl,p3060-pcie", "fsl,qoriq-pcie-v2.2";
-        device_type = "pci";
-        #size-cells = <2>;
-        #address-cells = <3>;
-        bus-range = <0 0xff>;
-        clock-frequency = <33333333>;
-        interrupts = <16 2 1 14>;
-        pcie@0 {
-                reg = <0 0 0 0 0>;
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                device_type = "pci";
-                interrupts = <16 2 1 14>;
-                interrupt-map-mask = <0xf800 0 0 7>;
-                interrupt-map = <
-                        /* IDSEL 0x0 */
-                        0000 0 0 1 &mpic 41 1 0 0
-                        0000 0 0 2 &mpic 5 1 0 0
-                        0000 0 0 3 &mpic 6 1 0 0
-                        0000 0 0 4 &mpic 7 1 0 0
-                        >;
-        };
-};
-
-&rio {
-        compatible = "fsl,srio";
-        interrupts = <16 2 1 11>;
-        #address-cells = <2>;
-        #size-cells = <2>;
-        fsl,srio-rmu-handle = <&rmu>;
-        ranges;
-
-        port1 {
-                #address-cells = <2>;
-                #size-cells = <2>;
-                cell-index = <1>;
-        };
-
-        port2 {
-                #address-cells = <2>;
-                #size-cells = <2>;
-                cell-index = <2>;
-        };
-};
-
-&dcsr {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        compatible = "fsl,dcsr", "simple-bus";
-
-        dcsr-epu@0 {
-                compatible = "fsl,dcsr-epu";
-                interrupts = <52 2 0 0
-                              84 2 0 0
-                              85 2 0 0>;
-                reg = <0x0 0x1000>;
-        };
-        dcsr-npc {
-                compatible = "fsl,dcsr-npc";
-                reg = <0x1000 0x1000 0x1000000 0x8000>;
-        };
-        dcsr-nxc@2000 {
-                compatible = "fsl,dcsr-nxc";
-                reg = <0x2000 0x1000>;
-        };
-        dcsr-corenet {
-                compatible = "fsl,dcsr-corenet";
-                reg = <0x8000 0x1000 0xB0000 0x1000>;
-        };
-        dcsr-dpaa@9000 {
-                compatible = "fsl,p3060-dcsr-dpaa", "fsl,dcsr-dpaa";
-                reg = <0x9000 0x1000>;
-        };
-        dcsr-ocn@11000 {
-                compatible = "fsl,p3060-dcsr-ocn", "fsl,dcsr-ocn";
-                reg = <0x11000 0x1000>;
-        };
-        dcsr-ddr@12000 {
-                compatible = "fsl,dcsr-ddr";
-                dev-handle = <&ddr1>;
-                reg = <0x12000 0x1000>;
-        };
-        dcsr-nal@18000 {
-                compatible = "fsl,p3060-dcsr-nal", "fsl,dcsr-nal";
-                reg = <0x18000 0x1000>;
-        };
-        dcsr-rcpm@22000 {
-                compatible = "fsl,p3060-dcsr-rcpm", "fsl,dcsr-rcpm";
-                reg = <0x22000 0x1000>;
-        };
-        dcsr-cpu-sb-proxy@40000 {
-                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                cpu-handle = <&cpu0>;
-                reg = <0x40000 0x1000>;
-        };
-        dcsr-cpu-sb-proxy@41000 {
-                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                cpu-handle = <&cpu1>;
-                reg = <0x41000 0x1000>;
-        };
-        dcsr-cpu-sb-proxy@44000 {
-                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                cpu-handle = <&cpu4>;
-                reg = <0x44000 0x1000>;
-        };
-        dcsr-cpu-sb-proxy@45000 {
-                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                cpu-handle = <&cpu5>;
-                reg = <0x45000 0x1000>;
-        };
-        dcsr-cpu-sb-proxy@46000 {
-                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                cpu-handle = <&cpu6>;
-                reg = <0x46000 0x1000>;
-        };
-        dcsr-cpu-sb-proxy@47000 {
-                compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
-                cpu-handle = <&cpu7>;
-                reg = <0x47000 0x1000>;
-        };
-
-};
-
-&soc {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        device_type = "soc";
-        compatible = "simple-bus";
-
-        soc-sram-error {
-                compatible = "fsl,soc-sram-error";
-                interrupts = <16 2 1 29>;
-        };
-
-        corenet-law@0 {
-                compatible = "fsl,corenet-law";
-                reg = <0x0 0x1000>;
-                fsl,num-laws = <32>;
-        };
-
-        ddr1: memory-controller@8000 {
-                compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
-                reg = <0x8000 0x1000>;
-                interrupts = <16 2 1 23>;
-        };
-
-        cpc: l3-cache-controller@10000 {
-                compatible = "fsl,p3060-l3-cache-controller", "cache";
-                reg = <0x10000 0x1000
-                       0x11000 0x1000>;
-                interrupts = <16 2 1 27
-                              16 2 1 26>;
-        };
-
-        corenet-cf@18000 {
-                compatible = "fsl,corenet-cf";
-                reg = <0x18000 0x1000>;
-                interrupts = <16 2 1 31>;
-                fsl,ccf-num-csdids = <32>;
-                fsl,ccf-num-snoopids = <32>;
-        };
-
-        iommu@20000 {
-                compatible = "fsl,pamu-v1.0", "fsl,pamu";
-                reg = <0x20000 0x5000>;
-                interrupts = <
-                        24 2 0 0
-                        16 2 1 30>;
-        };
-
-/include/ "qoriq-rmu-0.dtsi"
-/include/ "qoriq-mpic.dtsi"
-
-        guts: global-utilities@e0000 {
-                compatible = "fsl,qoriq-device-config-1.0";
-                reg = <0xe0000 0xe00>;
-                fsl,has-rstcr;
-                #sleep-cells = <1>;
-                fsl,liodn-bits = <12>;
-        };
-
-        pins: global-utilities@e0e00 {
-                compatible = "fsl,qoriq-pin-control-1.0";
-                reg = <0xe0e00 0x200>;
-                #sleep-cells = <2>;
-        };
-
-        clockgen: global-utilities@e1000 {
-                compatible = "fsl,p3060-clockgen", "fsl,qoriq-clockgen-1.0";
-                reg = <0xe1000 0x1000>;
-                clock-frequency = <0>;
-        };
-
-        rcpm: global-utilities@e2000 {
-                compatible = "fsl,qoriq-rcpm-1.0";
-                reg = <0xe2000 0x1000>;
-                #sleep-cells = <1>;
-        };
-
-        sfp: sfp@e8000 {
-                compatible = "fsl,p3060-sfp", "fsl,qoriq-sfp-1.0";
-                reg        = <0xe8000 0x1000>;
-        };
-
-        serdes: serdes@ea000 {
-                compatible = "fsl,p3060-serdes";
-                reg        = <0xea000 0x1000>;
-        };
-
-/include/ "qoriq-dma-0.dtsi"
-/include/ "qoriq-dma-1.dtsi"
-/include/ "qoriq-espi-0.dtsi"
-        spi@110000 {
-                fsl,espi-num-chipselects = <4>;
-        };
-
-/include/ "qoriq-i2c-0.dtsi"
-/include/ "qoriq-i2c-1.dtsi"
-/include/ "qoriq-duart-0.dtsi"
-/include/ "qoriq-duart-1.dtsi"
-/include/ "qoriq-gpio-0.dtsi"
-/include/ "qoriq-usb2-mph-0.dtsi"
-        usb@210000 {
-                compatible = "fsl-usb2-mph-v2.2", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
-        };
-/include/ "qoriq-usb2-dr-0.dtsi"
-        usb@211000 {
-                compatible = "fsl-usb2-dr-v2.2", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
-        };
-/include/ "qoriq-sec4.1-0.dtsi"
-};
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 8d35d2c1f69..4f9c9f682ec 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -345,6 +345,13 @@
 /include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-usb2-mph-0.dtsi"
+        usb@210000 {
+                compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
+                port0;
+        };
 /include/ "qoriq-usb2-dr-0.dtsi"
+        usb@211000 {
+                compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
+        };
 /include/ "qoriq-sec4.0-0.dtsi"
 };
diff --git a/arch/powerpc/boot/dts/mgcoge.dts b/arch/powerpc/boot/dts/mgcoge.dts
index ededaf5ac01..d72fb5e219d 100644
--- a/arch/powerpc/boot/dts/mgcoge.dts
+++ b/arch/powerpc/boot/dts/mgcoge.dts
@@ -222,6 +222,29 @@
                                 interrupt-parent = <&PIC>;
                                 usb-clock = <5>;
                         };
+                        spi@11aa0 {
+                                cell-index = <0>;
+                                compatible = "fsl,spi", "fsl,cpm2-spi";
+                                reg = <0x11a80 0x40 0x89fc 0x2>;
+                                interrupts = <2 8>;
+                                interrupt-parent = <&PIC>;
+                                gpios = < &cpm2_pio_d 19 0>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                ds3106@1 {
+                                        compatible = "gen,spidev";
+                                        reg = <0>;
+                                        spi-max-frequency = <8000000>;
+                                };
+                        };
+
+                };
+
+                cpm2_pio_d: gpio-controller@10d60 {
+                        #gpio-cells = <2>;
+                        compatible = "fsl,cpm2-pario-bank";
+                        reg = <0x10d60 0x14>;
+                        gpio-controller;
                 };
 
                 cpm2_pio_c: gpio-controller@10d40 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
index cc46dbd9746..d304a2d68c6 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -203,6 +203,14 @@
                         reg = <1>;
                         device_type = "ethernet-phy";
                 };
+                sgmii_phy0: sgmii-phy@0 {
+                        interrupts = <6 1 0 0>;
+                        reg = <0x1d>;
+                };
+                sgmii_phy1: sgmii-phy@1 {
+                        interrupts = <6 1 0 0>;
+                        reg = <0x1c>;
+                };
                 tbi0: tbi-phy@11 {
                         reg = <0x11>;
                         device_type = "tbi-phy";
diff --git a/arch/powerpc/boot/dts/mpc8544ds.dtsi b/arch/powerpc/boot/dts/mpc8544ds.dtsi
index 270f64b90f4..77ebc9f1d37 100644
--- a/arch/powerpc/boot/dts/mpc8544ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8544ds.dtsi
@@ -51,6 +51,15 @@
                         device_type = "ethernet-phy";
                 };
 
+                sgmii_phy0: sgmii-phy@0 {
+                        interrupts = <6 1 0 0>;
+                        reg = <0x1c>;
+                };
+                sgmii_phy1: sgmii-phy@1 {
+                        interrupts = <6 1 0 0>;
+                        reg = <0x1d>;
+                };
+
                 tbi0: tbi-phy@11 {
                         reg = <0x11>;
                         device_type = "tbi-phy";
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi b/arch/powerpc/boot/dts/mpc8572ds.dtsi
index 14178944e22..357490bb84d 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -169,6 +169,23 @@
                         reg = <0x3>;
                 };
 
+                sgmii_phy0: sgmii-phy@0 {
+                        interrupts = <6 1 0 0>;
+                        reg = <0x1c>;
+                };
+                sgmii_phy1: sgmii-phy@1 {
+                        interrupts = <6 1 0 0>;
+                        reg = <0x1d>;
+                };
+                sgmii_phy2: sgmii-phy@2 {
+                        interrupts = <7 1 0 0>;
+                        reg = <0x1e>;
+                };
+                sgmii_phy3: sgmii-phy@3 {
+                        interrupts = <7 1 0 0>;
+                        reg = <0x1f>;
+                };
+
                 tbi0: tbi-phy@11 {
                         reg = <0x11>;
                         device_type = "tbi-phy";
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
index d34d1271212..ef9ef56b3ee 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts
@@ -67,10 +67,10 @@
                 msi@41600 {
                         msi-available-ranges = <0 0x80>;
                         interrupts = <
-                                0xe0 0
-                                0xe1 0
-                                0xe2 0
-                                0xe3 0>;
+                                0xe0 0 0 0
+                                0xe1 0 0 0
+                                0xe2 0 0 0
+                                0xe3 0 0 0>;
                 };
                 timer@42100 {
                         status = "disabled";
diff --git a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
index d6a8fafc0d0..24564ee108e 100644
--- a/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds_camp_core1.dts
@@ -67,9 +67,6 @@
                 ethernet@24000 {
                         status = "disabled";
                 };
-                mdio@24520 {
-                        status = "disabled";
-                };
                 ptp_clock@24e00 {
                         status = "disabled";
                 };
@@ -100,10 +97,10 @@
                 msi@41600 {
                         msi-available-ranges = <0x80 0x80>;
                         interrupts = <
-                                0xe4 0
-                                0xe5 0
-                                0xe6 0
-                                0xe7 0>;
+                                0xe4 0 0 0
+                                0xe5 0 0 0
+                                0xe6 0 0 0
+                                0xe7 0 0 0>;
                 };
                 global-utilities@e0000 {
                         status = "disabled";
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi
index 49776143a1b..ec7c27a6467 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -126,12 +126,24 @@
 
 &board_soc {
         i2c@3000 {
+                eeprom@50 {
+                        compatible = "st,24c256";
+                        reg = <0x50>;
+                };
+
                 rtc@68 {
                         compatible = "pericom,pt7c4338";
                         reg = <0x68>;
                 };
         };
 
+        i2c@3100 {
+                eeprom@52 {
+                        compatible = "atmel,24c01";
+                        reg = <0x52>;
+                };
+        };
+
         spi@7000 {
                 flash@0 {
                         #address-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p1021rdb.dtsi b/arch/powerpc/boot/dts/p1021rdb-pc.dtsi
index b973461ab75..c13abfbbe2e 100644
--- a/arch/powerpc/boot/dts/p1021rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1021rdb-pc.dtsi
@@ -1,7 +1,7 @@
 /*
  * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
diff --git a/arch/powerpc/boot/dts/p1021rdb.dts b/arch/powerpc/boot/dts/p1021rdb-pc_32b.dts
index 90b6b4caa27..7cefa12b629 100644
--- a/arch/powerpc/boot/dts/p1021rdb.dts
+++ b/arch/powerpc/boot/dts/p1021rdb-pc_32b.dts
@@ -1,7 +1,7 @@
 /*
  * P1021 RDB Device Tree Source
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -92,5 +92,5 @@
         };
 };
 
-/include/ "p1021rdb.dtsi"
+/include/ "p1021rdb-pc.dtsi"
 /include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1021rdb_36b.dts b/arch/powerpc/boot/dts/p1021rdb-pc_36b.dts
index ea6d8b5fa10..53d0c889039 100644
--- a/arch/powerpc/boot/dts/p1021rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1021rdb-pc_36b.dts
@@ -1,7 +1,7 @@
 /*
  * P1021 RDB Device Tree Source (36-bit address map)
  *
- * Copyright 2011 Freescale Semiconductor Inc.
+ * Copyright 2012 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -92,5 +92,5 @@
         };
 };
 
-/include/ "p1021rdb.dtsi"
+/include/ "p1021rdb-pc.dtsi"
 /include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi b/arch/powerpc/boot/dts/p1022ds.dtsi
index 7cdb505036b..c3344b04d8f 100644
--- a/arch/powerpc/boot/dts/p1022ds.dtsi
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -33,22 +33,6 @@
  */
 
 &board_lbc {
-        /*
-         * This node is used to access the pixis via "indirect" mode,
-         * which is done by writing the pixis register index to chip
-         * select 0 and the value to/from chip select 1.  Indirect
-         * mode is the only way to access the pixis when DIU video
-         * is enabled.  Note that this assumes that the first column
-         * of the 'ranges' property above is the chip select number.
-         */
-        board-control@0,0 {
-                compatible = "fsl,p1022ds-indirect-pixis";
-                reg = <0x0 0x0 1        /* CS0 */
-                       0x1 0x0 1>;      /* CS1 */
-                interrupt-parent = <&mpic>;
-                interrupts = <8 0 0 0>;
-        };
-
         nor@0,0 {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -161,6 +145,10 @@
                          * the clock is enabled.
                          */
                 };
+                rtc@68 {
+                        compatible = "dallas,ds1339";
+                        reg = <0x68>;
+                };
         };
 
         spi@7000 {
diff --git a/arch/powerpc/boot/dts/p1024rdb.dtsi b/arch/powerpc/boot/dts/p1024rdb.dtsi
new file mode 100644
index 00000000000..b05dcb40f80
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1024rdb.dtsi
@@ -0,0 +1,228 @@
+/*
+ * P1024 RDB Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&lbc {
+        nor@0,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "cfi-flash";
+                reg = <0x0 0x0 0x1000000>;
+                bank-width = <2>;
+                device-width = <1>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 256KB for Vitesse 7385 Switch firmware */
+                        reg = <0x0 0x00040000>;
+                        label = "NOR Vitesse-7385 Firmware";
+                        read-only;
+                };
+
+                partition@40000 {
+                        /* 256KB for DTB Image */
+                        reg = <0x00040000 0x00040000>;
+                        label = "NOR DTB Image";
+                };
+
+                partition@80000 {
+                        /* 3.5 MB for Linux Kernel Image */
+                        reg = <0x00080000 0x00380000>;
+                        label = "NOR Linux Kernel Image";
+                };
+
+                partition@400000 {
+                        /* 11MB for JFFS2 based Root file System */
+                        reg = <0x00400000 0x00b00000>;
+                        label = "NOR JFFS2 Root File System";
+                };
+
+                partition@f00000 {
+                        /* This location must not be altered  */
+                        /* 512KB for u-boot Bootloader Image */
+                        /* 512KB for u-boot Environment Variables */
+                        reg = <0x00f00000 0x00100000>;
+                        label = "NOR U-Boot Image";
+                        read-only;
+                };
+        };
+
+        nand@1,0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "fsl,p1020-fcm-nand",
+                                 "fsl,elbc-fcm-nand";
+                reg = <0x1 0x0 0x40000>;
+
+                partition@0 {
+                        /* This location must not be altered  */
+                        /* 1MB for u-boot Bootloader Image */
+                        reg = <0x0 0x00100000>;
+                        label = "NAND U-Boot Image";
+                        read-only;
+                };
+
+                partition@100000 {
+                        /* 1MB for DTB Image */
+                        reg = <0x00100000 0x00100000>;
+                        label = "NAND DTB Image";
+                };
+
+                partition@200000 {
+                        /* 4MB for Linux Kernel Image */
+                        reg = <0x00200000 0x00400000>;
+                        label = "NAND Linux Kernel Image";
+                };
+
+                partition@600000 {
+                        /* 4MB for Compressed Root file System Image */
+                        reg = <0x00600000 0x00400000>;
+                        label = "NAND Compressed RFS Image";
+                };
+
+                partition@a00000 {
+                        /* 15MB for JFFS2 based Root file System */
+                        reg = <0x00a00000 0x00f00000>;
+                        label = "NAND JFFS2 Root File System";
+                };
+
+                partition@1900000 {
+                        /* 7MB for User Writable Area */
+                        reg = <0x01900000 0x00700000>;
+                        label = "NAND Writable User area";
+                };
+        };
+};
+
+&soc {
+        spi@7000 {
+                flash@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "spansion,m25p80";
+                        reg = <0>;
+                        spi-max-frequency = <40000000>;
+
+                        partition@0 {
+                                /* 512KB for u-boot Bootloader Image */
+                                reg = <0x0 0x00080000>;
+                                label = "SPI U-Boot Image";
+                                read-only;
+                        };
+
+                        partition@80000 {
+                                /* 512KB for DTB Image */
+                                reg = <0x00080000 0x00080000>;
+                                label = "SPI DTB Image";
+                        };
+
+                        partition@100000 {
+                                /* 4MB for Linux Kernel Image */
+                                reg = <0x00100000 0x00400000>;
+                                label = "SPI Linux Kernel Image";
+                        };
+
+                        partition@500000 {
+                                /* 4MB for Compressed RFS Image */
+                                reg = <0x00500000 0x00400000>;
+                                label = "SPI Compressed RFS Image";
+                        };
+
+                        partition@900000 {
+                                /* 7MB for JFFS2 based RFS */
+                                reg = <0x00900000 0x00700000>;
+                                label = "SPI JFFS2 RFS";
+                        };
+                };
+        };
+
+        i2c@3000 {
+                rtc@68 {
+                        compatible = "dallas,ds1339";
+                        reg = <0x68>;
+                };
+        };
+
+        usb@22000 {
+                phy_type = "ulpi";
+        };
+
+        usb@23000 {
+                status = "disabled";
+        };
+
+        mdio@24000 {
+                phy0: ethernet-phy@0 {
+                        interrupts = <3 1 0 0>;
+                        reg = <0x0>;
+                };
+                phy1: ethernet-phy@1 {
+                        interrupts = <2 1 0 0>;
+                        reg = <0x1>;
+                };
+                phy2: ethernet-phy@2 {
+                        interrupts = <1 1 0 0>;
+                        reg = <0x2>;
+                };
+        };
+
+        mdio@25000 {
+                tbi0: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        mdio@26000 {
+                tbi1: tbi-phy@11 {
+                        reg = <0x11>;
+                        device_type = "tbi-phy";
+                };
+        };
+
+        ethernet@b0000 {
+                phy-handle = <&phy2>;
+                phy-connection-type = "rgmii-id";
+        };
+
+        ethernet@b1000 {
+                phy-handle = <&phy0>;
+                tbi-handle = <&tbi0>;
+                phy-connection-type = "sgmii";
+        };
+
+        ethernet@b2000 {
+                phy-handle = <&phy1>;
+                phy-connection-type = "rgmii-id";
+        };
+};
diff --git a/arch/powerpc/boot/dts/p1024rdb_32b.dts b/arch/powerpc/boot/dts/p1024rdb_32b.dts
new file mode 100644
index 00000000000..90e803e9ba5
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1024rdb_32b.dts
@@ -0,0 +1,87 @@
+/*
+ * P1024 RDB 32Bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+        model = "fsl,P1024RDB";
+        compatible = "fsl,P1024RDB";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@ffe05000 {
+                reg = <0x0 0xffe05000 0 0x1000>;
+                ranges = <0x0 0x0 0x0 0xef000000 0x01000000
+                          0x1 0x0 0x0 0xff800000 0x00040000>;
+        };
+
+        soc: soc@ffe00000 {
+                ranges = <0x0 0x0 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@ffe09000 {
+                reg = <0x0 0xffe09000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0x0 0xa0000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@ffe0a000 {
+                reg = <0x0 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0x0 0x80000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p1024rdb.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1024rdb_36b.dts b/arch/powerpc/boot/dts/p1024rdb_36b.dts
new file mode 100644
index 00000000000..3656825b65a
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1024rdb_36b.dts
@@ -0,0 +1,87 @@
+/*
+ * P1024 RDB 36Bit Physical Address Map Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+        model = "fsl,P1024RDB";
+        compatible = "fsl,P1024RDB";
+
+        memory {
+                device_type = "memory";
+        };
+
+        lbc: localbus@fffe05000 {
+                reg = <0xf 0xffe05000 0 0x1000>;
+                ranges = <0x0 0x0 0xf 0xef000000 0x01000000
+                          0x1 0x0 0xf 0xff800000 0x00040000>;
+        };
+
+        soc: soc@fffe00000 {
+                ranges = <0x0 0xf 0xffe00000 0x100000>;
+        };
+
+        pci0: pcie@fffe09000 {
+                reg = <0xf 0xffe09000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
+                pcie@0 {
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+
+        pci1: pcie@fffe0a000 {
+                reg = <0xf 0xffe0a000 0 0x1000>;
+                ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
+                pcie@0 {
+                        reg = <0x0 0x0 0x0 0x0 0x0>;
+                        ranges = <0x2000000 0x0 0xe0000000
+                                  0x2000000 0x0 0xe0000000
+                                  0x0 0x20000000
+
+                                  0x1000000 0x0 0x0
+                                  0x1000000 0x0 0x0
+                                  0x0 0x100000>;
+                };
+        };
+};
+
+/include/ "p1024rdb.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025rdb.dtsi b/arch/powerpc/boot/dts/p1025rdb.dtsi
index cf3676fc714..f5025648229 100644
--- a/arch/powerpc/boot/dts/p1025rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1025rdb.dtsi
@@ -282,5 +282,45 @@
                                 0x1  0x4  0x2  0x0  0x2  0x0    /* ENET5_RX_DV_SER5_CTS_B */
                                 0x1  0x8  0x2  0x0  0x2  0x0>;    /* ENET5_RX_ER_SER5_CD_B */
                 };
+
+                pio3: ucc_pin@03 {
+                        pio-map = <
+                /* port  pin  dir  open_drain  assignment  has_irq */
+                                0x0  0x16 0x2  0x0  0x2  0x0    /* SER7_CD_B*/
+                                0x0  0x12 0x2  0x0  0x2  0x0    /* SER7_CTS_B*/
+                                0x0  0x13 0x1  0x0  0x2  0x0    /* SER7_RTS_B*/
+                                0x0  0x14 0x2  0x0  0x2  0x0    /* SER7_RXD0*/
+                                0x0  0x15 0x1  0x0  0x2  0x0>;    /* SER7_TXD0*/
+                };
+
+                pio4: ucc_pin@04 {
+                        pio-map = <
+                /* port  pin  dir  open_drain  assignment  has_irq */
+                                0x1  0x0  0x2  0x0  0x2  0x0    /* SER3_CD_B*/
+                                0x0  0x1c 0x2  0x0  0x2  0x0    /* SER3_CTS_B*/
+                                0x0  0x1d 0x1  0x0  0x2  0x0    /* SER3_RTS_B*/
+                                0x0  0x1e 0x2  0x0  0x2  0x0    /* SER3_RXD0*/
+                                0x0  0x1f 0x1  0x0  0x2  0x0>;    /* SER3_TXD0*/
+                };
+        };
+};
+
+&qe {
+        serial2: ucc@2600 {
+                device_type = "serial";
+                compatible = "ucc_uart";
+                port-number = <0>;
+                rx-clock-name = "brg6";
+                tx-clock-name = "brg6";
+                pio-handle = <&pio3>;
+        };
+
+        serial3: ucc@2200 {
+                device_type = "serial";
+                compatible = "ucc_uart";
+                port-number = <1>;
+                rx-clock-name = "brg2";
+                tx-clock-name = "brg2";
+                pio-handle = <&pio4>;
         };
 };
diff --git a/arch/powerpc/boot/dts/p2020ds.dtsi b/arch/powerpc/boot/dts/p2020ds.dtsi
index d3b939c573b..e699cf95b06 100644
--- a/arch/powerpc/boot/dts/p2020ds.dtsi
+++ b/arch/powerpc/boot/dts/p2020ds.dtsi
@@ -150,6 +150,16 @@
                         interrupts = <3 1 0 0>;
                         reg = <0x2>;
                 };
+
+                sgmii_phy1: sgmii-phy@1 {
+                        interrupts = <5 1 0 0>;
+                        reg = <0x1c>;
+                };
+                sgmii_phy2: sgmii-phy@2 {
+                        interrupts = <5 1 0 0>;
+                        reg = <0x1d>;
+                };
+
                 tbi0: tbi-phy@11 {
                         reg = <0x11>;
                         device_type = "tbi-phy";
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
index 852e5b27485..57573bd52ca 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
@@ -56,7 +56,7 @@
                 ranges = <0x0 0x0 0xffe00000 0x100000>;
         };
 
-        pci0: pcie@ffe08000 {
+        pci2: pcie@ffe08000 {
                 reg = <0 0xffe08000 0 0x1000>;
                 status = "disabled";
         };
@@ -76,7 +76,7 @@
                 };
         };
 
-        pci2: pcie@ffe0a000 {
+        pci0: pcie@ffe0a000 {
                 reg = <0 0xffe0a000 0 0x1000>;
                 ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
                           0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
index b5a56ca51cf..470247ea68b 100644
--- a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
@@ -56,7 +56,7 @@
                 ranges = <0x0 0xf 0xffe00000 0x100000>;
         };
 
-        pci0: pcie@fffe08000 {
+        pci2: pcie@fffe08000 {
                 reg = <0xf 0xffe08000 0 0x1000>;
                 status = "disabled";
         };
@@ -76,7 +76,7 @@
                 };
         };
 
-        pci2: pcie@fffe0a000 {
+        pci0: pcie@fffe0a000 {
                 reg = <0xf 0xffe0a000 0 0x1000>;
                 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
                           0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index 153bc76bb48..4d52bce1d5b 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -34,7 +34,7 @@
 
                 /* NOR and NAND Flashes */
                 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
-                          0x1 0x0 0x0 0xff800000 0x00040000
+                          0x1 0x0 0x0 0xffa00000 0x00040000
                           0x2 0x0 0x0 0xffb00000 0x00020000>;
 
                 nor@0,0 {
diff --git a/arch/powerpc/boot/dts/p2041rdb.dts b/arch/powerpc/boot/dts/p2041rdb.dts
index 285213976a7..baab0347dab 100644
--- a/arch/powerpc/boot/dts/p2041rdb.dts
+++ b/arch/powerpc/boot/dts/p2041rdb.dts
@@ -121,7 +121,8 @@
 
         lbc: localbus@ffe124000 {
                 reg = <0xf 0xfe124000 0 0x1000>;
-                ranges = <0 0 0xf 0xe8000000 0x08000000>;
+                ranges = <0 0 0xf 0xe8000000 0x08000000
+                          1 0 0xf 0xffa00000 0x00040000>;
 
                 flash@0,0 {
                         compatible = "cfi-flash";
@@ -129,6 +130,44 @@
                         bank-width = <2>;
                         device-width = <2>;
                 };
+
+                nand@1,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x1 0x0 0x40000>;
+
+                        partition@0 {
+                                label = "NAND U-Boot Image";
+                                reg = <0x0 0x02000000>;
+                                read-only;
+                        };
+
+                        partition@2000000 {
+                                label = "NAND Root File System";
+                                reg = <0x02000000 0x10000000>;
+                        };
+
+                        partition@12000000 {
+                                label = "NAND Compressed RFS Image";
+                                reg = <0x12000000 0x08000000>;
+                        };
+
+                        partition@1a000000 {
+                                label = "NAND Linux Kernel Image";
+                                reg = <0x1a000000 0x04000000>;
+                        };
+
+                        partition@1e000000 {
+                                label = "NAND DTB Image";
+                                reg = <0x1e000000 0x01000000>;
+                        };
+
+                        partition@1f000000 {
+                                label = "NAND Writable User area";
+                                reg = <0x1f000000 0x01000000>;
+                        };
+                };
         };
 
         pci0: pcie@ffe200000 {
diff --git a/arch/powerpc/boot/dts/p3041ds.dts b/arch/powerpc/boot/dts/p3041ds.dts
index 22a215e9416..6cdcadc80c3 100644
--- a/arch/powerpc/boot/dts/p3041ds.dts
+++ b/arch/powerpc/boot/dts/p3041ds.dts
@@ -58,7 +58,7 @@
                                 #size-cells = <1>;
                                 compatible = "spansion,s25sl12801";
                                 reg = <0>;
-                                spi-max-frequency = <40000000>; /* input clock */
+                                spi-max-frequency = <35000000>; /* input clock */
                                 partition@u-boot {
                                         label = "u-boot";
                                         reg = <0x00000000 0x00100000>;
diff --git a/arch/powerpc/boot/dts/p3060qds.dts b/arch/powerpc/boot/dts/p3060qds.dts
deleted file mode 100644
index 9ae875c8a21..00000000000
--- a/arch/powerpc/boot/dts/p3060qds.dts
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * P3060QDS Device Tree Source
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Freescale Semiconductor nor the
- *       names of its contributors may be used to endorse or promote products
- *       derived from this software without specific prior written permission.
- *
- *
- * ALTERNATIVELY, this software may be distributed under the terms of the
- * GNU General Public License ("GPL") as published by the Free Software
- * Foundation, either version 2 of that License or (at your option) any
- * later version.
- *
- * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/include/ "fsl/p3060si-pre.dtsi"
-
-/ {
-        model = "fsl,P3060QDS";
-        compatible = "fsl,P3060QDS";
-        #address-cells = <2>;
-        #size-cells = <2>;
-        interrupt-parent = <&mpic>;
-
-        memory {
-                device_type = "memory";
-        };
-
-        dcsr: dcsr@f00000000 {
-                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
-        };
-
-        soc: soc@ffe000000 {
-                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
-                reg = <0xf 0xfe000000 0 0x00001000>;
-                spi@110000 {
-                        flash@0 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "spansion,s25sl12801";
-                                reg = <0>;
-                                spi-max-frequency = <40000000>; /* input clock */
-                                partition@u-boot {
-                                        label = "u-boot";
-                                        reg = <0x00000000 0x00100000>;
-                                        read-only;
-                                };
-                                partition@kernel {
-                                        label = "kernel";
-                                        reg = <0x00100000 0x00500000>;
-                                        read-only;
-                                };
-                                partition@dtb {
-                                        label = "dtb";
-                                        reg = <0x00600000 0x00100000>;
-                                        read-only;
-                                };
-                                partition@fs {
-                                        label = "file system";
-                                        reg = <0x00700000 0x00900000>;
-                                };
-                        };
-                        flash@1 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "spansion,en25q32b";
-                                reg = <1>;
-                                spi-max-frequency = <40000000>; /* input clock */
-                                partition@spi1 {
-                                        label = "spi1";
-                                        reg = <0x00000000 0x00400000>;
-                                };
-                        };
-                        flash@2 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "atmel,at45db081d";
-                                reg = <2>;
-                                spi-max-frequency = <40000000>; /* input clock */
-                                partition@spi1 {
-                                        label = "spi2";
-                                        reg = <0x00000000 0x00100000>;
-                                };
-                        };
-                        flash@3 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                compatible = "spansion,sst25wf040";
-                                reg = <3>;
-                                spi-max-frequency = <40000000>; /* input clock */
-                                partition@spi3 {
-                                        label = "spi3";
-                                        reg = <0x00000000 0x00080000>;
-                                };
-                        };
-                };
-
-                i2c@118000 {
-                        eeprom@51 {
-                                compatible = "at24,24c256";
-                                reg = <0x51>;
-                        };
-                        eeprom@53 {
-                                compatible = "at24,24c256";
-                                reg = <0x53>;
-                        };
-                        rtc@68 {
-                                compatible = "dallas,ds3232";
-                                reg = <0x68>;
-                                interrupts = <0x1 0x1 0 0>;
-                        };
-                };
-
-                usb0: usb@210000 {
-                        phy_type = "ulpi";
-                };
-
-                usb1: usb@211000 {
-                        dr_mode = "host";
-                        phy_type = "ulpi";
-                };
-        };
-
-        rio: rapidio@ffe0c0000 {
-                reg = <0xf 0xfe0c0000 0 0x11000>;
-
-                port1 {
-                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
-                };
-                port2 {
-                        ranges = <0 0 0xc 0x30000000 0 0x10000000>;
-                };
-        };
-
-        lbc: localbus@ffe124000 {
-                reg = <0xf 0xfe124000 0 0x1000>;
-                ranges = <0 0 0xf 0xe8000000 0x08000000
-                          2 0 0xf 0xffa00000 0x00040000
-                          3 0 0xf 0xffdf0000 0x00008000>;
-
-                flash@0,0 {
-                        compatible = "cfi-flash";
-                        reg = <0 0 0x08000000>;
-                        bank-width = <2>;
-                        device-width = <2>;
-                };
-
-                nand@2,0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,elbc-fcm-nand";
-                        reg = <0x2 0x0 0x40000>;
-
-                        partition@0 {
-                                label = "NAND U-Boot Image";
-                                reg = <0x0 0x02000000>;
-                                read-only;
-                        };
-
-                        partition@2000000 {
-                                label = "NAND Root File System";
-                                reg = <0x02000000 0x10000000>;
-                        };
-
-                        partition@12000000 {
-                                label = "NAND Compressed RFS Image";
-                                reg = <0x12000000 0x08000000>;
-                        };
-
-                        partition@1a000000 {
-                                label = "NAND Linux Kernel Image";
-                                reg = <0x1a000000 0x04000000>;
-                        };
-
-                        partition@1e000000 {
-                                label = "NAND DTB Image";
-                                reg = <0x1e000000 0x01000000>;
-                        };
-
-                        partition@1f000000 {
-                                label = "NAND Writable User area";
-                                reg = <0x1f000000 0x21000000>;
-                        };
-                };
-
-                board-control@3,0 {
-                        compatible = "fsl,p3060qds-fpga", "fsl,fpga-qixis";
-                        reg = <3 0 0x100>;
-                };
-        };
-
-        pci0: pcie@ffe200000 {
-                reg = <0xf 0xfe200000 0 0x1000>;
-                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
-                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
-                pcie@0 {
-                        ranges = <0x02000000 0 0xe0000000
-                                  0x02000000 0 0xe0000000
-                                  0 0x20000000
-
-                                  0x01000000 0 0x00000000
-                                  0x01000000 0 0x00000000
-                                  0 0x00010000>;
-                };
-        };
-
-        pci1: pcie@ffe201000 {
-                reg = <0xf 0xfe201000 0 0x1000>;
-                ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
-                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
-                pcie@0 {
-                        ranges = <0x02000000 0 0xe0000000
-                                  0x02000000 0 0xe0000000
-                                  0 0x20000000
-
-                                  0x01000000 0 0x00000000
-                                  0x01000000 0 0x00000000
-                                  0 0x00010000>;
-                };
-        };
-};
-
-/include/ "fsl/p3060si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/sbc8560.dts b/arch/powerpc/boot/dts/sbc8560.dts
deleted file mode 100644
index 72078eb1561..00000000000
--- a/arch/powerpc/boot/dts/sbc8560.dts
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
- * SBC8560 Device Tree Source
- *
- * Copyright 2007 Wind River Systems Inc.
- *
- * Paul Gortmaker (see MAINTAINERS for contact information)
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/dts-v1/;
-
-/ {
-        model = "SBC8560";
-        compatible = "SBC8560";
-        #address-cells = <1>;
-        #size-cells = <1>;
-
-        aliases {
-                ethernet0 = &enet0;
-                ethernet1 = &enet1;
-                ethernet2 = &enet2;
-                ethernet3 = &enet3;
-                serial0 = &serial0;
-                serial1 = &serial1;
-                pci0 = &pci0;
-        };
-
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                PowerPC,8560@0 {
-                        device_type = "cpu";
-                        reg = <0>;
-                        d-cache-line-size = <0x20>;     // 32 bytes
-                        i-cache-line-size = <0x20>;     // 32 bytes
-                        d-cache-size = <0x8000>;        // L1, 32K
-                        i-cache-size = <0x8000>;        // L1, 32K
-                        timebase-frequency = <0>;       // From uboot
-                        bus-frequency = <0>;
-                        clock-frequency = <0>;
-                        next-level-cache = <&L2>;
-                };
-        };
-
-        memory {
-                device_type = "memory";
-                reg = <0x00000000 0x20000000>;
-        };
-
-        soc@ff700000 {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                device_type = "soc";
-                ranges = <0x0 0xff700000 0x00100000>;
-                clock-frequency = <0>;
-
-                ecm-law@0 {
-                        compatible = "fsl,ecm-law";
-                        reg = <0x0 0x1000>;
-                        fsl,num-laws = <8>;
-                };
-
-                ecm@1000 {
-                        compatible = "fsl,mpc8560-ecm", "fsl,ecm";
-                        reg = <0x1000 0x1000>;
-                        interrupts = <17 2>;
-                        interrupt-parent = <&mpic>;
-                };
-
-                memory-controller@2000 {
-                        compatible = "fsl,mpc8560-memory-controller";
-                        reg = <0x2000 0x1000>;
-                        interrupt-parent = <&mpic>;
-                        interrupts = <0x12 0x2>;
-                };
-
-                L2: l2-cache-controller@20000 {
-                        compatible = "fsl,mpc8560-l2-cache-controller";
-                        reg = <0x20000 0x1000>;
-                        cache-line-size = <0x20>;       // 32 bytes
-                        cache-size = <0x40000>;         // L2, 256K
-                        interrupt-parent = <&mpic>;
-                        interrupts = <0x10 0x2>;
-                };
-
-                i2c@3000 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <0>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3000 0x100>;
-                        interrupts = <0x2b 0x2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-
-                i2c@3100 {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-                        cell-index = <1>;
-                        compatible = "fsl-i2c";
-                        reg = <0x3100 0x100>;
-                        interrupts = <0x2b 0x2>;
-                        interrupt-parent = <&mpic>;
-                        dfsrr;
-                };
-
-                dma@21300 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
-                        reg = <0x21300 0x4>;
-                        ranges = <0x0 0x21100 0x200>;
-                        cell-index = <0>;
-                        dma-channel@0 {
-                                compatible = "fsl,mpc8560-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x0 0x80>;
-                                cell-index = <0>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <20 2>;
-                        };
-                        dma-channel@80 {
-                                compatible = "fsl,mpc8560-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x80 0x80>;
-                                cell-index = <1>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <21 2>;
-                        };
-                        dma-channel@100 {
-                                compatible = "fsl,mpc8560-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x100 0x80>;
-                                cell-index = <2>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <22 2>;
-                        };
-                        dma-channel@180 {
-                                compatible = "fsl,mpc8560-dma-channel",
-                                                "fsl,eloplus-dma-channel";
-                                reg = <0x180 0x80>;
-                                cell-index = <3>;
-                                interrupt-parent = <&mpic>;
-                                interrupts = <23 2>;
-                        };
-                };
-
-                enet0: ethernet@24000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <0>;
-                        device_type = "network";
-                        model = "TSEC";
-                        compatible = "gianfar";
-                        reg = <0x24000 0x1000>;
-                        ranges = <0x0 0x24000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi0>;
-                        phy-handle = <&phy0>;
-
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-mdio";
-                                reg = <0x520 0x20>;
-                                phy0: ethernet-phy@19 {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <0x6 0x1>;
-                                        reg = <0x19>;
-                                        device_type = "ethernet-phy";
-                                };
-                                phy1: ethernet-phy@1a {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <0x7 0x1>;
-                                        reg = <0x1a>;
-                                        device_type = "ethernet-phy";
-                                };
-                                phy2: ethernet-phy@1b {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <0x8 0x1>;
-                                        reg = <0x1b>;
-                                        device_type = "ethernet-phy";
-                                };
-                                phy3: ethernet-phy@1c {
-                                        interrupt-parent = <&mpic>;
-                                        interrupts = <0x8 0x1>;
-                                        reg = <0x1c>;
-                                        device_type = "ethernet-phy";
-                                };
-                                tbi0: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-
-                enet1: ethernet@25000 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        cell-index = <1>;
-                        device_type = "network";
-                        model = "TSEC";
-                        compatible = "gianfar";
-                        reg = <0x25000 0x1000>;
-                        ranges = <0x0 0x25000 0x1000>;
-                        local-mac-address = [ 00 00 00 00 00 00 ];
-                        interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
-                        interrupt-parent = <&mpic>;
-                        tbi-handle = <&tbi1>;
-                        phy-handle = <&phy1>;
-
-                        mdio@520 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,gianfar-tbi";
-                                reg = <0x520 0x20>;
-
-                                tbi1: tbi-phy@11 {
-                                        reg = <0x11>;
-                                        device_type = "tbi-phy";
-                                };
-                        };
-                };
-
-                mpic: pic@40000 {
-                        interrupt-controller;
-                        #address-cells = <0>;
-                        #interrupt-cells = <2>;
-                        compatible = "chrp,open-pic";
-                        reg = <0x40000 0x40000>;
-                        device_type = "open-pic";
-                };
-
-                cpm@919c0 {
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
-                        reg = <0x919c0 0x30>;
-                        ranges;
-
-                        muram@80000 {
-                                #address-cells = <1>;
-                                #size-cells = <1>;
-                                ranges = <0x0 0x80000 0x10000>;
-
-                                data@0 {
-                                        compatible = "fsl,cpm-muram-data";
-                                        reg = <0x0 0x4000 0x9000 0x2000>;
-                                };
-                        };
-
-                        brg@919f0 {
-                                compatible = "fsl,mpc8560-brg",
-                                             "fsl,cpm2-brg",
-                                             "fsl,cpm-brg";
-                                reg = <0x919f0 0x10 0x915f0 0x10>;
-                                clock-frequency = <165000000>;
-                        };
-
-                        cpmpic: pic@90c00 {
-                                interrupt-controller;
-                                #address-cells = <0>;
-                                #interrupt-cells = <2>;
-                                interrupts = <0x2e 0x2>;
-                                interrupt-parent = <&mpic>;
-                                reg = <0x90c00 0x80>;
-                                compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
-                        };
-
-                        enet2: ethernet@91320 {
-                                device_type = "network";
-                                compatible = "fsl,mpc8560-fcc-enet",
-                                             "fsl,cpm2-fcc-enet";
-                                reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
-                                local-mac-address = [ 00 00 00 00 00 00 ];
-                                fsl,cpm-command = <0x16200300>;
-                                interrupts = <0x21 0x8>;
-                                interrupt-parent = <&cpmpic>;
-                                phy-handle = <&phy2>;
-                        };
-
-                        enet3: ethernet@91340 {
-                                device_type = "network";
-                                compatible = "fsl,mpc8560-fcc-enet",
-                                             "fsl,cpm2-fcc-enet";
-                                reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
-                                local-mac-address = [ 00 00 00 00 00 00 ];
-                                fsl,cpm-command = <0x1a400300>;
-                                interrupts = <0x22 0x8>;
-                                interrupt-parent = <&cpmpic>;
-                                phy-handle = <&phy3>;
-                        };
-                };
-
-                global-utilities@e0000 {
-                        compatible = "fsl,mpc8560-guts";
-                        reg = <0xe0000 0x1000>;
-                };
-        };
-
-        pci0: pci@ff708000 {
-                #interrupt-cells = <1>;
-                #size-cells = <2>;
-                #address-cells = <3>;
-                compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
-                device_type = "pci";
-                reg = <0xff708000 0x1000>;
-                clock-frequency = <66666666>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-                interrupt-map = <
-
-                        /* IDSEL 0x02 */
-                        0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
-                        0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
-                        0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
-                        0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
-
-                interrupt-parent = <&mpic>;
-                interrupts = <0x18 0x2>;
-                bus-range = <0x0 0x0>;
-                ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
-                          0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
-        };
-
-        localbus@ff705000 {
-                compatible = "fsl,mpc8560-localbus", "simple-bus";
-                #address-cells = <2>;
-                #size-cells = <1>;
-                reg = <0xff705000 0x100>;       // BRx, ORx, etc.
-
-                ranges = <
-                        0x0 0x0 0xff800000 0x0800000    // 8MB boot flash
-                        0x1 0x0 0xe4000000 0x4000000    // 64MB flash
-                        0x3 0x0 0x20000000 0x4000000    // 64MB SDRAM
-                        0x4 0x0 0x24000000 0x4000000    // 64MB SDRAM
-                        0x5 0x0 0xfc000000 0x0c00000    // EPLD
-                        0x6 0x0 0xe0000000 0x4000000    // 64MB flash
-                        0x7 0x0 0x80000000 0x0200000    // ATM1,2
-                >;
-
-                epld@5,0 {
-                        compatible = "wrs,epld-localbus";
-                        #address-cells = <2>;
-                        #size-cells = <1>;
-                        reg = <0x5 0x0 0xc00000>;
-                        ranges = <
-                                0x0 0x0 0x5 0x000000 0x1fff     // LED disp.
-                                0x1 0x0 0x5 0x100000 0x1fff     // switches
-                                0x2 0x0 0x5 0x200000 0x1fff     // ID reg.
-                                0x3 0x0 0x5 0x300000 0x1fff     // status reg.
-                                0x4 0x0 0x5 0x400000 0x1fff     // reset reg.
-                                0x5 0x0 0x5 0x500000 0x1fff     // Wind port
-                                0x7 0x0 0x5 0x700000 0x1fff     // UART #1
-                                0x8 0x0 0x5 0x800000 0x1fff     // UART #2
-                                0x9 0x0 0x5 0x900000 0x1fff     // RTC
-                                0xb 0x0 0x5 0xb00000 0x1fff     // EEPROM
-                        >;
-
-                        bidr@2,0 {
-                                compatible = "wrs,sbc8560-bidr";
-                                reg = <0x2 0x0 0x10>;
-                        };
-
-                        bcsr@3,0 {
-                                compatible = "wrs,sbc8560-bcsr";
-                                reg = <0x3 0x0 0x10>;
-                        };
-
-                        brstcr@4,0 {
-                                compatible = "wrs,sbc8560-brstcr";
-                                reg = <0x4 0x0 0x10>;
-                        };
-
-                        serial0: serial@7,0 {
-                                device_type = "serial";
-                                compatible = "ns16550";
-                                reg = <0x7 0x0 0x100>;
-                                clock-frequency = <1843200>;
-                                interrupts = <0x9 0x2>;
-                                interrupt-parent = <&mpic>;
-                        };
-
-                        serial1: serial@8,0 {
-                                device_type = "serial";
-                                compatible = "ns16550";
-                                reg = <0x8 0x0 0x100>;
-                                clock-frequency = <1843200>;
-                                interrupts = <0xa 0x2>;
-                                interrupt-parent = <&mpic>;
-                        };
-
-                        rtc@9,0 {
-                                compatible = "m48t59";
-                                reg = <0x9 0x0 0x1fff>;
-                        };
-                };
-        };
-};
diff --git a/arch/powerpc/boot/flatdevtree_env.h b/arch/powerpc/boot/flatdevtree_env.h
deleted file mode 100644
index 66e0ebb1a36..00000000000
--- a/arch/powerpc/boot/flatdevtree_env.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file adds the header file glue so that the shared files
- * flatdevicetree.[ch] can compile and work in the powerpc bootwrapper.
- *
- * strncmp & strchr copied from <file:lib/string.c>
- * Copyright (C) 1991, 1992  Linus Torvalds
- *
- * Maintained by: Mark A. Greer <mgreer@mvista.com>
- */
-#ifndef _PPC_BOOT_FLATDEVTREE_ENV_H_
-#define _PPC_BOOT_FLATDEVTREE_ENV_H_
-
-#include <stdarg.h>
-#include <stddef.h>
-#include "types.h"
-#include "string.h"
-#include "stdio.h"
-#include "ops.h"
-
-#define be16_to_cpu(x)          (x)
-#define cpu_to_be16(x)          (x)
-#define be32_to_cpu(x)          (x)
-#define cpu_to_be32(x)          (x)
-#define be64_to_cpu(x)          (x)
-#define cpu_to_be64(x)          (x)
-
-#endif /* _PPC_BOOT_FLATDEVTREE_ENV_H_ */
diff --git a/arch/powerpc/configs/83xx/kmeter1_defconfig b/arch/powerpc/configs/83xx/kmeter1_defconfig
index 07e1bbadebf..a0dfef1fcdb 100644
--- a/arch/powerpc/configs/83xx/kmeter1_defconfig
+++ b/arch/powerpc/configs/83xx/kmeter1_defconfig
@@ -2,14 +2,14 @@ CONFIG_EXPERIMENTAL=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
-CONFIG_SPARSE_IRQ=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_EXPERT=y
-# CONFIG_HOTPLUG is not set
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_MSDOS_PARTITION is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 # CONFIG_PPC_CHRP is not set
@@ -31,11 +31,10 @@ CONFIG_IP_PNP=y
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
+CONFIG_TIPC=y
 CONFIG_BRIDGE=m
 CONFIG_VLAN_8021Q=y
 CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -50,17 +49,15 @@ CONFIG_MTD_UBI_DEBUG=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
-CONFIG_TUN=y
 CONFIG_MII=y
-CONFIG_MARVELL_PHY=y
-CONFIG_NET_ETHERNET=y
+CONFIG_TUN=y
 CONFIG_UCC_GETH=y
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WAN=y
-CONFIG_HDLC=y
+CONFIG_MARVELL_PHY=y
 CONFIG_PPP=y
 CONFIG_PPP_MULTILINK=y
 CONFIG_PPPOE=y
+CONFIG_WAN=y
+CONFIG_HDLC=y
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
@@ -77,10 +74,7 @@ CONFIG_UIO=y
 # CONFIG_DNOTIFY is not set
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/powerpc/configs/85xx/p1023rds_defconfig b/arch/powerpc/configs/85xx/p1023rds_defconfig
index f4337bacd0e..26e541c4662 100644
--- a/arch/powerpc/configs/85xx/p1023rds_defconfig
+++ b/arch/powerpc/configs/85xx/p1023rds_defconfig
@@ -6,28 +6,27 @@ CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_AUDIT=y
-CONFIG_SPARSE_IRQ=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_KALLSYMS_ALL=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
 CONFIG_EMBEDDED=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
 CONFIG_P1023_RDS=y
 CONFIG_QUICC_ENGINE=y
 CONFIG_QE_GPIO=y
 CONFIG_CPM2=y
-CONFIG_GPIO_MPC8XXX=y
 CONFIG_HIGHMEM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
@@ -63,11 +62,11 @@ CONFIG_INET_ESP=y
 CONFIG_IPV6=y
 CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_LEGACY=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=y
@@ -80,15 +79,14 @@ CONFIG_SATA_FSL=y
 CONFIG_SATA_SIL24=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
+CONFIG_FS_ENET=y
+CONFIG_FSL_PQ_MDIO=y
+CONFIG_E1000E=y
 CONFIG_MARVELL_PHY=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_CICADA_PHY=y
 CONFIG_VITESSE_PHY=y
 CONFIG_FIXED_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_FS_ENET=y
-CONFIG_E1000E=y
-CONFIG_FSL_PQ_MDIO=y
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
@@ -98,16 +96,15 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=2
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_DETECT_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
 CONFIG_SERIAL_QE=m
-CONFIG_HW_RANDOM=y
 CONFIG_NVRAM=y
 CONFIG_I2C=y
 CONFIG_I2C_CPM=m
 CONFIG_I2C_MPC=y
+CONFIG_GPIO_MPC8XXX=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_SOUND=y
@@ -123,7 +120,6 @@ CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
 # CONFIG_NET_DMA is not set
 CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
@@ -150,22 +146,15 @@ CONFIG_QNX4FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
 CONFIG_CRC_T10DIF=y
 CONFIG_FRAME_WARN=8092
 CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
diff --git a/arch/powerpc/configs/85xx/sbc8560_defconfig b/arch/powerpc/configs/85xx/sbc8560_defconfig
deleted file mode 100644
index f7fdb0318e4..00000000000
--- a/arch/powerpc/configs/85xx/sbc8560_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_PPC_85xx=y
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_SBC8560=y
-CONFIG_BINFMT_MISC=y
-CONFIG_SPARSE_IRQ=y
-# CONFIG_SECCOMP is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM_USER=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_PROC_DEVICETREE=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=32768
-CONFIG_NETDEVICES=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_GIANFAR=y
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_NR_UARTS=2
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-# CONFIG_HW_RANDOM is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_M48T59=y
-CONFIG_INOTIFY=y
-CONFIG_PROC_KCORE=y
-CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_MSDOS_PARTITION is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_PPC_EARLY_DEBUG=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/chroma_defconfig b/arch/powerpc/configs/chroma_defconfig
index b1f9597fe31..29bb11ec6c6 100644
--- a/arch/powerpc/configs/chroma_defconfig
+++ b/arch/powerpc/configs/chroma_defconfig
@@ -21,8 +21,8 @@ CONFIG_CGROUP_DEVICE=y
 CONFIG_CPUSETS=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_MEM_RES_CTLR=y
-CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
+CONFIG_CGROUP_MEMCG=y
+CONFIG_CGROUP_MEMCG_SWAP=y
 CONFIG_NAMESPACES=y
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 91db656294e..8b3d57c1ebe 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -6,8 +6,8 @@ CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_AUDIT=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_RCU_TRACE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -21,22 +21,22 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
 CONFIG_P2041_RDB=y
 CONFIG_P3041_DS=y
-CONFIG_P3060_QDS=y
 CONFIG_P4080_DS=y
 CONFIG_P5020_DS=y
 CONFIG_HIGHMEM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
 CONFIG_KEXEC=y
+CONFIG_IRQ_ALL_CPUS=y
 CONFIG_FORCE_MAX_ZONEORDER=13
-CONFIG_FSL_LBC=y
 CONFIG_PCI=y
 CONFIG_PCIEPORTBUS=y
 # CONFIG_PCIEASPM is not set
+CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
 CONFIG_FSL_RIO=y
 CONFIG_NET=y
@@ -69,6 +69,7 @@ CONFIG_INET_IPCOMP=y
 CONFIG_IPV6=y
 CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
@@ -77,11 +78,13 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_MTD_NAND_FSL_IFC=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_MISC_DEVICES=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=y
 CONFIG_BLK_DEV_SR=y
@@ -109,11 +112,9 @@ CONFIG_SERIO_LIBPS2=y
 CONFIG_PPC_EPAPR_HV_BYTECHAN=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_DETECT_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
-CONFIG_HW_RANDOM=y
 CONFIG_NVRAM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
@@ -126,7 +127,6 @@ CONFIG_SPI_FSL_ESPI=y
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_USB_HID=m
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_FSL=y
@@ -162,19 +162,16 @@ CONFIG_HUGETLBFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=m
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_RCU_TRACE=y
 CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_MD4=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 6798343580f..0516e22ca3d 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -6,7 +6,9 @@ CONFIG_NR_CPUS=2
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_SPARSE_IRQ=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -18,11 +20,14 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
 CONFIG_P5020_DS=y
 # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BINFMT_MISC=m
+CONFIG_IRQ_ALL_CPUS=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_MSI=y
 CONFIG_RAPIDIO=y
 CONFIG_FSL_RIO=y
 CONFIG_NET=y
@@ -51,12 +56,26 @@ CONFIG_INET_ESP=y
 CONFIG_IPV6=y
 CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_MTD_NAND_FSL_IFC=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_LEGACY=y
+CONFIG_ATA=y
+CONFIG_SATA_FSL=y
+CONFIG_SATA_SIL24=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
 CONFIG_INPUT_FF_MEMLESS=m
@@ -66,39 +85,59 @@ CONFIG_INPUT_FF_MEMLESS=m
 CONFIG_SERIO_LIBPS2=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_DETECT_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MPC=y
+CONFIG_SPI=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_FSL_SPI=y
+CONFIG_SPI_FSL_ESPI=y
 # CONFIG_HWMON is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_HID=m
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=y
 CONFIG_DMADEVICES=y
 CONFIG_FSL_DMA=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
-CONFIG_NLS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NLS_ISO8859_1=y
 CONFIG_NLS_UTF8=m
 CONFIG_CRC_T10DIF=y
-CONFIG_CRC_ITU_T=m
 CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_SHIRQ=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_CRYPTO_NULL=y
 CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_MD4=y
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
 CONFIG_CRYPTO_AES=y
diff --git a/arch/powerpc/configs/mgcoge_defconfig b/arch/powerpc/configs/mgcoge_defconfig
index 0d36b0e1e26..8fa84f156ef 100644
--- a/arch/powerpc/configs/mgcoge_defconfig
+++ b/arch/powerpc/configs/mgcoge_defconfig
@@ -2,7 +2,6 @@ CONFIG_EXPERIMENTAL=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
-CONFIG_SPARSE_IRQ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -12,6 +11,7 @@ CONFIG_KALLSYMS_ALL=y
 # CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
+CONFIG_PARTITION_ADVANCED=y
 # CONFIG_IOSCHED_CFQ is not set
 # CONFIG_PPC_PMAC is not set
 CONFIG_PPC_82xx=y
@@ -49,12 +49,9 @@ CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
-CONFIG_FIXED_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_FS_ENET=y
 CONFIG_FS_ENET_MDIO_FCC=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+CONFIG_FIXED_PHY=y
 # CONFIG_WLAN is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
@@ -64,6 +61,8 @@ CONFIG_SERIAL_CPM_CONSOLE=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_CPM=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_SPI=y
 # CONFIG_HWMON is not set
 CONFIG_USB_GADGET=y
 CONFIG_USB_FSL_USB2=y
@@ -80,8 +79,6 @@ CONFIG_SQUASHFS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
 CONFIG_NLS_ISO8859_1=y
@@ -90,7 +87,6 @@ CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
 CONFIG_DEBUG_INFO=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_BDI_SWITCH=y
 CONFIG_CRYPTO_ECB=y
 CONFIG_CRYPTO_PCBC=y
diff --git a/arch/powerpc/configs/mpc83xx_defconfig b/arch/powerpc/configs/mpc83xx_defconfig
index 5aac9a8bc53..9352e4430c3 100644
--- a/arch/powerpc/configs/mpc83xx_defconfig
+++ b/arch/powerpc/configs/mpc83xx_defconfig
@@ -2,12 +2,12 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_EXPERT=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
 # CONFIG_PPC_CHRP is not set
 # CONFIG_PPC_PMAC is not set
 CONFIG_PPC_83xx=y
@@ -25,7 +25,6 @@ CONFIG_ASP834x=y
 CONFIG_QUICC_ENGINE=y
 CONFIG_QE_GPIO=y
 CONFIG_MATH_EMULATION=y
-CONFIG_SPARSE_IRQ=y
 CONFIG_PCI=y
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -42,10 +41,9 @@ CONFIG_INET_ESP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
 # CONFIG_FW_LOADER is not set
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_OF_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
@@ -64,15 +62,14 @@ CONFIG_ATA=y
 CONFIG_SATA_FSL=y
 CONFIG_SATA_SIL=y
 CONFIG_NETDEVICES=y
+CONFIG_MII=y
+CONFIG_UCC_GETH=y
+CONFIG_GIANFAR=y
 CONFIG_MARVELL_PHY=y
 CONFIG_DAVICOM_PHY=y
 CONFIG_VITESSE_PHY=y
 CONFIG_ICPLUS_PHY=y
 CONFIG_FIXED_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_GIANFAR=y
-CONFIG_UCC_GETH=y
 CONFIG_INPUT_FF_MEMLESS=m
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_KEYBOARD is not set
@@ -112,17 +109,12 @@ CONFIG_RTC_DRV_DS1374=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_INOTIFY=y
 CONFIG_PROC_KCORE=y
 CONFIG_TMPFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
 CONFIG_CRC_T10DIF=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 CONFIG_CRYPTO_ECB=m
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_SHA256=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index 62bb723c5b5..8b5bda27d24 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -5,7 +5,9 @@ CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_AUDIT=y
-CONFIG_SPARSE_IRQ=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -17,6 +19,8 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
 CONFIG_MPC8540_ADS=y
 CONFIG_MPC8560_ADS=y
 CONFIG_MPC85xx_CDS=y
@@ -40,8 +44,6 @@ CONFIG_SBC8548=y
 CONFIG_QUICC_ENGINE=y
 CONFIG_QE_GPIO=y
 CONFIG_HIGHMEM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
 CONFIG_FORCE_MAX_ZONEORDER=12
@@ -74,12 +76,25 @@ CONFIG_INET_ESP=y
 CONFIG_IPV6=y
 CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_MTD_NAND_FSL_IFC=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_LEGACY=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=y
@@ -91,6 +106,7 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_FSL=y
 CONFIG_PATA_ALI=y
+CONFIG_PATA_VIA=y
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
 CONFIG_FS_ENET=y
@@ -110,7 +126,6 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=2
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_DETECT_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
@@ -159,7 +174,6 @@ CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_FSL=y
@@ -205,18 +219,13 @@ CONFIG_QNX4FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
 CONFIG_CRC_T10DIF=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index d1828427ae5..b0974e7e98a 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -7,7 +7,9 @@ CONFIG_SYSVIPC=y
 CONFIG_POSIX_MQUEUE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_AUDIT=y
-CONFIG_SPARSE_IRQ=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -19,6 +21,8 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 # CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MAC_PARTITION=y
 CONFIG_MPC8540_ADS=y
 CONFIG_MPC8560_ADS=y
 CONFIG_MPC85xx_CDS=y
@@ -42,10 +46,9 @@ CONFIG_SBC8548=y
 CONFIG_QUICC_ENGINE=y
 CONFIG_QE_GPIO=y
 CONFIG_HIGHMEM=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BINFMT_MISC=m
 CONFIG_MATH_EMULATION=y
+CONFIG_IRQ_ALL_CPUS=y
 CONFIG_FORCE_MAX_ZONEORDER=12
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
@@ -76,12 +79,25 @@ CONFIG_INET_ESP=y
 CONFIG_IPV6=y
 CONFIG_IP_SCTP=m
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_FTL=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSL_ELBC=y
+CONFIG_MTD_NAND_FSL_IFC=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=131072
-CONFIG_MISC_DEVICES=y
 CONFIG_EEPROM_LEGACY=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_CHR_DEV_ST=y
@@ -112,7 +128,6 @@ CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=2
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_DETECT_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
@@ -161,7 +176,6 @@ CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_FSL=y
@@ -207,18 +221,13 @@ CONFIG_QNX4FS_FS=m
 CONFIG_SYSV_FS=m
 CONFIG_UFS_FS=m
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NFSD=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
 CONFIG_CRC_T10DIF=y
 CONFIG_DEBUG_FS=y
 CONFIG_DETECT_HUNG_TASK=y
 CONFIG_DEBUG_INFO=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_CRYPTO_PCBC=m
 CONFIG_CRYPTO_SHA256=y
 CONFIG_CRYPTO_SHA512=y
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index c1442a3758a..db27c82e054 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -16,6 +16,7 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
@@ -278,7 +279,8 @@ CONFIG_HVC_RTAS=y
 CONFIG_HVC_BEAT=y
 CONFIG_HVCS=m
 CONFIG_IBM_BSR=m
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_PSERIES=m
 CONFIG_RAW_DRIVER=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_AMD8111=y
@@ -484,8 +486,10 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_NX=m
 CONFIG_VIRTUALIZATION=y
 CONFIG_KVM_BOOK3S_64=m
 CONFIG_KVM_BOOK3S_64_HV=y
 CONFIG_VHOST_NET=m
+CONFIG_BPF_JIT=y
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index 6608232663c..1f65b3c9b59 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -24,6 +24,7 @@ CONFIG_BLK_DEV_INITRD=y
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
 CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_MODVERSIONS=y
@@ -225,7 +226,8 @@ CONFIG_HVC_CONSOLE=y
 CONFIG_HVC_RTAS=y
 CONFIG_HVCS=m
 CONFIG_IBM_BSR=m
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=m
+CONFIG_HW_RANDOM_PSERIES=m
 CONFIG_GEN_RTC=y
 CONFIG_RAW_DRIVER=y
 CONFIG_MAX_RAW_DEVS=1024
@@ -366,7 +368,8 @@ CONFIG_CRYPTO_TEA=m
 CONFIG_CRYPTO_TWOFISH=m
 CONFIG_CRYPTO_LZO=m
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_NX=m
 CONFIG_VIRTUALIZATION=y
 CONFIG_KVM_BOOK3S_64=m
 CONFIG_KVM_BOOK3S_64_HV=y
diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h
index 5d7fbe1950f..6e82f5f9a6f 100644
--- a/arch/powerpc/include/asm/asm-compat.h
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -29,7 +29,7 @@
 #define PPC_LLARX(t, a, b, eh)  PPC_LDARX(t, a, b, eh)
 #define PPC_STLCX       stringify_in_c(stdcx.)
 #define PPC_CNTLZL      stringify_in_c(cntlzd)
-#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), (RS))
+#define PPC_MTOCRF(FXM, RS) MTOCRF((FXM), RS)
 #define PPC_LR_STKOFF   16
 #define PPC_MIN_STKFRM  112
 #else /* 32-bit */
diff --git a/arch/powerpc/include/asm/code-patching.h b/arch/powerpc/include/asm/code-patching.h
index 37c32aba79b..a6f8c7a5cbb 100644
--- a/arch/powerpc/include/asm/code-patching.h
+++ b/arch/powerpc/include/asm/code-patching.h
@@ -26,8 +26,8 @@ unsigned int create_branch(const unsigned int *addr,
                            unsigned long target, int flags);
 unsigned int create_cond_branch(const unsigned int *addr,
                                 unsigned long target, int flags);
-void patch_branch(unsigned int *addr, unsigned long target, int flags);
-void patch_instruction(unsigned int *addr, unsigned int instr);
+int patch_branch(unsigned int *addr, unsigned long target, int flags);
+int patch_instruction(unsigned int *addr, unsigned int instr);
 
 int instr_is_relative_branch(unsigned int instr);
 int instr_is_branch_to_addr(const unsigned int *instr, unsigned long addr);
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 50d82c8a037..b3c083de17a 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -553,9 +553,7 @@ static inline int cpu_has_feature(unsigned long feature)
                 & feature);
 }
 
-#ifdef CONFIG_HAVE_HW_BREAKPOINT
 #define HBP_NUM 1
-#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index 63d5ca49cec..77e97dd0c15 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -34,6 +34,9 @@ struct dev_archdata {
 #ifdef CONFIG_EEH
         struct eeh_dev          *edev;
 #endif
+#ifdef CONFIG_FAIL_IOMMU
+        int fail_iommu;
+#endif
 };
 
 struct pdev_archdata {
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index 62678e365ca..78160874809 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -27,7 +27,10 @@ extern void *dma_direct_alloc_coherent(struct device *dev, size_t size,
 extern void dma_direct_free_coherent(struct device *dev, size_t size,
                                      void *vaddr, dma_addr_t dma_handle,
                                      struct dma_attrs *attrs);
-
+extern int dma_direct_mmap_coherent(struct device *dev,
+                                    struct vm_area_struct *vma,
+                                    void *cpu_addr, dma_addr_t handle,
+                                    size_t size, struct dma_attrs *attrs);
 
 #ifdef CONFIG_NOT_COHERENT_CACHE
 /*
@@ -207,11 +210,8 @@ static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 
-extern int dma_mmap_coherent(struct device *, struct vm_area_struct *,
-                             void *, dma_addr_t, size_t);
 #define ARCH_HAS_DMA_MMAP_COHERENT
 
-
 static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                 enum dma_data_direction direction)
 {
diff --git a/arch/powerpc/include/asm/epapr_hcalls.h b/arch/powerpc/include/asm/epapr_hcalls.h
index 976835d8f22..bf2c06c3387 100644
--- a/arch/powerpc/include/asm/epapr_hcalls.h
+++ b/arch/powerpc/include/asm/epapr_hcalls.h
@@ -153,6 +153,8 @@
 #define EV_HCALL_CLOBBERS2 EV_HCALL_CLOBBERS3, "r5"
 #define EV_HCALL_CLOBBERS1 EV_HCALL_CLOBBERS2, "r4"
 
+extern bool epapr_paravirt_enabled;
+extern u32 epapr_hypercall_start[];
 
 /*
  * We use "uintptr_t" to define a register because it's guaranteed to be a
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index d58fc4e4149..a43c1473915 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -293,7 +293,7 @@ label##_hv:								\
 
 #define RUNLATCH_ON                             \
 BEGIN_FTR_SECTION                               \
-        clrrdi  r3,r1,THREAD_SHIFT;             \
+        CURRENT_THREAD_INFO(r3, r1);            \
         ld      r4,TI_LOCAL_FLAGS(r3);          \
         andi.   r0,r4,_TLF_RUNLATCH;            \
         beql    ppc64_runlatch_on_trampoline;   \
@@ -332,7 +332,7 @@ label##_common:							\
 #ifdef CONFIG_PPC_970_NAP
 #define FINISH_NAP                              \
 BEGIN_FTR_SECTION                               \
-        clrrdi  r11,r1,THREAD_SHIFT;            \
+        CURRENT_THREAD_INFO(r11, r1);           \
         ld      r9,TI_LOCAL_FLAGS(r11);         \
         andi.   r10,r9,_TLF_NAPPING;            \
         bnel    power4_fixup_nap;               \
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 0554ab062bd..e45c4947a77 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -34,6 +34,8 @@ extern void __replay_interrupt(unsigned int vector);
 
 extern void timer_interrupt(struct pt_regs *);
 extern void performance_monitor_exception(struct pt_regs *regs);
+extern void WatchdogException(struct pt_regs *regs);
+extern void unknown_exception(struct pt_regs *regs);
 
 #ifdef CONFIG_PPC64
 #include <asm/paca.h>
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index 0edb6842b13..61e8490786b 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -26,7 +26,9 @@
 struct qe_iram {
         __be32  iadd;           /* I-RAM Address Register */
         __be32  idata;          /* I-RAM Data Register */
-        u8      res0[0x78];
+        u8      res0[0x04];
+        __be32  iready;         /* I-RAM Ready Register */
+        u8      res1[0x70];
 } __attribute__ ((packed));
 
 /* QE Interrupt Controller */
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index a3855b81ead..f94ef4213e9 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -20,6 +20,14 @@ extern int check_legacy_ioport(unsigned long base_port);
 #define _PNPWRP         0xa79
 #define PNPBIOS_BASE    0xf000
 
+#if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
+extern struct pci_dev *isa_bridge_pcidev;
+/*
+ * has legacy ISA devices ?
+ */
+#define arch_has_dev_port()     (isa_bridge_pcidev != NULL)
+#endif
+
 #include <linux/device.h>
 #include <linux/io.h>
 
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index 957a83f4364..cbfe678e3db 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -53,6 +53,16 @@ static __inline__ __attribute_const__ int get_iommu_order(unsigned long size)
  */
 #define IOMAP_MAX_ORDER         13
 
+#define IOMMU_POOL_HASHBITS     2
+#define IOMMU_NR_POOLS          (1 << IOMMU_POOL_HASHBITS)
+
+struct iommu_pool {
+        unsigned long start;
+        unsigned long end;
+        unsigned long hint;
+        spinlock_t lock;
+} ____cacheline_aligned_in_smp;
+
 struct iommu_table {
         unsigned long  it_busno;     /* Bus number this table belongs to */
         unsigned long  it_size;      /* Size of iommu table in entries */
@@ -61,10 +71,10 @@ struct iommu_table {
         unsigned long  it_index;     /* which iommu table this is */
         unsigned long  it_type;      /* type: PCI or Virtual Bus */
         unsigned long  it_blocksize; /* Entries in each block (cacheline) */
-        unsigned long  it_hint;      /* Hint for next alloc */
-        unsigned long  it_largehint; /* Hint for large allocs */
-        unsigned long  it_halfpoint; /* Breaking point for small/large allocs */
-        spinlock_t     it_lock;      /* Protects it_map */
+        unsigned long  poolsize;
+        unsigned long  nr_pools;
+        struct iommu_pool large_pool;
+        struct iommu_pool pools[IOMMU_NR_POOLS];
         unsigned long *it_map;       /* A simple allocation bitmap for now */
 };
 
diff --git a/arch/powerpc/include/asm/kmap_types.h b/arch/powerpc/include/asm/kmap_types.h
index bca8fdcd254..5acabbd7ac6 100644
--- a/arch/powerpc/include/asm/kmap_types.h
+++ b/arch/powerpc/include/asm/kmap_types.h
@@ -10,36 +10,7 @@
  * 2 of the License, or (at your option) any later version.
  */
 
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_PPC_SYNC_PAGE,
-        KM_PPC_SYNC_ICACHE,
-        KM_KDB,
-        KM_TYPE_NR
-};
-
-/*
- * This is a temporary build fix that (so they say on lkml....) should no longer
- * be required after 2.6.33, because of changes planned to the kmap code.
- * Let's try to remove this cruft then.
- */
-#ifdef CONFIG_DEBUG_HIGHMEM
-#define KM_NMI          (-1)
-#define KM_NMI_PTE      (-1)
-#define KM_IRQ_PTE      (-1)
-#endif
+#define KM_TYPE_NR 16
 
 #endif  /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_KMAP_TYPES_H */
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index b0c08b14277..0dd1d86d3e3 100644
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -36,11 +36,8 @@ static inline void svcpu_put(struct kvmppc_book3s_shadow_vcpu *svcpu)
 #define SPAPR_TCE_SHIFT         12
 
 #ifdef CONFIG_KVM_BOOK3S_64_HV
-/* For now use fixed-size 16MB page table */
-#define HPT_ORDER       24
-#define HPT_NPTEG       (1ul << (HPT_ORDER - 7))        /* 128B per pteg */
-#define HPT_NPTE        (HPT_NPTEG << 3)                /* 8 PTEs per PTEG */
-#define HPT_HASH_MASK   (HPT_NPTEG - 1)
+#define KVM_DEFAULT_HPT_ORDER   24      /* 16MB HPT by default */
+extern int kvm_hpt_order;               /* order of preallocated HPTs */
 #endif
 
 #define VRMA_VSID       0x1ffffffUL     /* 1TB VSID reserved for VRMA */
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 88609b23b77..bfcd00c1485 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -74,6 +74,7 @@ struct kvmppc_host_state {
         ulong vmhandler;
         ulong scratch0;
         ulong scratch1;
+        ulong sprg3;
         u8 in_guest;
         u8 restore_hid5;
         u8 napping;
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index d848cdc4971..a8bf5c673a3 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -33,6 +33,7 @@
 #include <asm/kvm_asm.h>
 #include <asm/processor.h>
 #include <asm/page.h>
+#include <asm/cacheflush.h>
 
 #define KVM_MAX_VCPUS           NR_CPUS
 #define KVM_MAX_VCORES          NR_CPUS
@@ -237,6 +238,10 @@ struct kvm_arch {
         unsigned long vrma_slb_v;
         int rma_setup_done;
         int using_mmu_notifiers;
+        u32 hpt_order;
+        atomic_t vcpus_running;
+        unsigned long hpt_npte;
+        unsigned long hpt_mask;
         spinlock_t slot_phys_lock;
         unsigned long *slot_phys[KVM_MEM_SLOTS_NUM];
         int slot_npages[KVM_MEM_SLOTS_NUM];
@@ -414,7 +419,9 @@ struct kvm_vcpu_arch {
         ulong mcsrr1;
         ulong mcsr;
         u32 dec;
+#ifdef CONFIG_BOOKE
         u32 decar;
+#endif
         u32 tbl;
         u32 tbu;
         u32 tcr;
diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h
index f68c22fa2fc..e006f0bdea9 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -119,7 +119,8 @@ extern void kvmppc_core_destroy_mmu(struct kvm_vcpu *vcpu);
 extern int kvmppc_kvm_pv(struct kvm_vcpu *vcpu);
 extern void kvmppc_map_magic(struct kvm_vcpu *vcpu);
 
-extern long kvmppc_alloc_hpt(struct kvm *kvm);
+extern long kvmppc_alloc_hpt(struct kvm *kvm, u32 *htab_orderp);
+extern long kvmppc_alloc_reset_hpt(struct kvm *kvm, u32 *htab_orderp);
 extern void kvmppc_free_hpt(struct kvm *kvm);
 extern long kvmppc_prepare_vrma(struct kvm *kvm,
                                 struct kvm_userspace_memory_region *mem);
@@ -218,4 +219,16 @@ void kvmppc_claim_lpid(long lpid);
 void kvmppc_free_lpid(long lpid);
 void kvmppc_init_lpid(unsigned long nr_lpids);
 
+static inline void kvmppc_mmu_flush_icache(pfn_t pfn)
+{
+        /* Clear i-cache for new pages */
+        struct page *page;
+        page = pfn_to_page(pfn);
+        if (!test_bit(PG_arch_1, &page->flags)) {
+                flush_dcache_icache_page(page);
+                set_bit(PG_arch_1, &page->flags);
+        }
+}
+
+
 #endif /* __POWERPC_KVM_PPC_H__ */
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index f0145522cfb..e8a26db2e8f 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -163,12 +163,7 @@ extern u64 ppc64_rma_size;
  * to think about, feedback welcome. --BenH.
  */
 
-/* There are #define as they have to be used in assembly
- *
- * WARNING: If you change this list, make sure to update the array of
- * names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
- * happen
- */
+/* These are #defines as they have to be used in assembly */
 #define MMU_PAGE_4K     0
 #define MMU_PAGE_16K    1
 #define MMU_PAGE_64K    2
diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h
index 326d33ca55c..d4f471fb103 100644
--- a/arch/powerpc/include/asm/mpic_msgr.h
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -14,6 +14,7 @@
 #include <linux/types.h>
 #include <linux/spinlock.h>
 #include <asm/smp.h>
+#include <asm/io.h>
 
 struct mpic_msgr {
         u32 __iomem *base;
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index ac39e6a3b25..8cccbee6151 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -30,6 +30,7 @@ struct pci_controller {
         int first_busno;
         int last_busno;
         int self_busno;
+        struct resource busn;
 
         void __iomem *io_base_virt;
 #ifdef CONFIG_PPC64
diff --git a/arch/powerpc/include/asm/perf_event.h b/arch/powerpc/include/asm/perf_event.h
index 5c16b891d50..0bb23725b1e 100644
--- a/arch/powerpc/include/asm/perf_event.h
+++ b/arch/powerpc/include/asm/perf_event.h
@@ -26,8 +26,13 @@
 #include <asm/ptrace.h>
 #include <asm/reg.h>
 
+/*
+ * Overload regs->result to specify whether we should use the MSR (result
+ * is zero) or the SIAR (result is non zero).
+ */
 #define perf_arch_fetch_caller_regs(regs, __ip)                 \
         do {                                                    \
+                (regs)->result = 0;                             \
                 (regs)->nip = __ip;                             \
                 (regs)->gpr[1] = *(unsigned long *)__get_SP();  \
                 asm volatile("mfmsr %0" : "=r" ((regs)->msr));  \
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index d81f99430fe..4c25319f2fb 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -15,6 +15,72 @@
 #include <linux/stringify.h>
 #include <asm/asm-compat.h>
 
+#define __REG_R0        0
+#define __REG_R1        1
+#define __REG_R2        2
+#define __REG_R3        3
+#define __REG_R4        4
+#define __REG_R5        5
+#define __REG_R6        6
+#define __REG_R7        7
+#define __REG_R8        8
+#define __REG_R9        9
+#define __REG_R10       10
+#define __REG_R11       11
+#define __REG_R12       12
+#define __REG_R13       13
+#define __REG_R14       14
+#define __REG_R15       15
+#define __REG_R16       16
+#define __REG_R17       17
+#define __REG_R18       18
+#define __REG_R19       19
+#define __REG_R20       20
+#define __REG_R21       21
+#define __REG_R22       22
+#define __REG_R23       23
+#define __REG_R24       24
+#define __REG_R25       25
+#define __REG_R26       26
+#define __REG_R27       27
+#define __REG_R28       28
+#define __REG_R29       29
+#define __REG_R30       30
+#define __REG_R31       31
+
+#define __REGA0_0       0
+#define __REGA0_R1      1
+#define __REGA0_R2      2
+#define __REGA0_R3      3
+#define __REGA0_R4      4
+#define __REGA0_R5      5
+#define __REGA0_R6      6
+#define __REGA0_R7      7
+#define __REGA0_R8      8
+#define __REGA0_R9      9
+#define __REGA0_R10     10
+#define __REGA0_R11     11
+#define __REGA0_R12     12
+#define __REGA0_R13     13
+#define __REGA0_R14     14
+#define __REGA0_R15     15
+#define __REGA0_R16     16
+#define __REGA0_R17     17
+#define __REGA0_R18     18
+#define __REGA0_R19     19
+#define __REGA0_R20     20
+#define __REGA0_R21     21
+#define __REGA0_R22     22
+#define __REGA0_R23     23
+#define __REGA0_R24     24
+#define __REGA0_R25     25
+#define __REGA0_R26     26
+#define __REGA0_R27     27
+#define __REGA0_R28     28
+#define __REGA0_R29     29
+#define __REGA0_R30     30
+#define __REGA0_R31     31
+
 /* sorted alphabetically */
 #define PPC_INST_DCBA                   0x7c0005ec
 #define PPC_INST_DCBA_MASK              0xfc0007fe
@@ -107,12 +173,19 @@
 #define PPC_INST_NEG                    0x7c0000d0
 #define PPC_INST_BRANCH                 0x48000000
 #define PPC_INST_BRANCH_COND            0x40800000
+#define PPC_INST_LBZCIX                 0x7c0006aa
+#define PPC_INST_STBCIX                 0x7c0007aa
 
 /* macros to insert fields into opcodes */
-#define __PPC_RA(a)     (((a) & 0x1f) << 16)
-#define __PPC_RB(b)     (((b) & 0x1f) << 11)
-#define __PPC_RS(s)     (((s) & 0x1f) << 21)
-#define __PPC_RT(s)     __PPC_RS(s)
+#define ___PPC_RA(a)    (((a) & 0x1f) << 16)
+#define ___PPC_RB(b)    (((b) & 0x1f) << 11)
+#define ___PPC_RS(s)    (((s) & 0x1f) << 21)
+#define ___PPC_RT(t)    ___PPC_RS(t)
+#define __PPC_RA(a)     ___PPC_RA(__REG_##a)
+#define __PPC_RA0(a)    ___PPC_RA(__REGA0_##a)
+#define __PPC_RB(b)     ___PPC_RB(__REG_##b)
+#define __PPC_RS(s)     ___PPC_RS(__REG_##s)
+#define __PPC_RT(t)     ___PPC_RT(__REG_##t)
 #define __PPC_XA(a)     ((((a) & 0x1f) << 16) | (((a) & 0x20) >> 3))
 #define __PPC_XB(b)     ((((b) & 0x1f) << 11) | (((b) & 0x20) >> 4))
 #define __PPC_XS(s)     ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
@@ -141,13 +214,13 @@
 #define PPC_DCBZL(a, b)         stringify_in_c(.long PPC_INST_DCBZL | \
                                         __PPC_RA(a) | __PPC_RB(b))
 #define PPC_LDARX(t, a, b, eh)  stringify_in_c(.long PPC_INST_LDARX | \
-                                        __PPC_RT(t) | __PPC_RA(a) | \
-                                        __PPC_RB(b) | __PPC_EH(eh))
+                                        ___PPC_RT(t) | ___PPC_RA(a) | \
+                                        ___PPC_RB(b) | __PPC_EH(eh))
 #define PPC_LWARX(t, a, b, eh)  stringify_in_c(.long PPC_INST_LWARX | \
-                                        __PPC_RT(t) | __PPC_RA(a) | \
-                                        __PPC_RB(b) | __PPC_EH(eh))
+                                        ___PPC_RT(t) | ___PPC_RA(a) | \
+                                        ___PPC_RB(b) | __PPC_EH(eh))
 #define PPC_MSGSND(b)           stringify_in_c(.long PPC_INST_MSGSND | \
-                                        __PPC_RB(b))
+                                        ___PPC_RB(b))
 #define PPC_POPCNTB(a, s)       stringify_in_c(.long PPC_INST_POPCNTB | \
                                         __PPC_RA(a) | __PPC_RS(s))
 #define PPC_POPCNTD(a, s)       stringify_in_c(.long PPC_INST_POPCNTD | \
@@ -158,34 +231,39 @@
 #define PPC_RFDI                stringify_in_c(.long PPC_INST_RFDI)
 #define PPC_RFMCI               stringify_in_c(.long PPC_INST_RFMCI)
 #define PPC_TLBILX(t, a, b)     stringify_in_c(.long PPC_INST_TLBILX | \
-                                        __PPC_T_TLB(t) | __PPC_RA(a) | __PPC_RB(b))
+                                        __PPC_T_TLB(t) | __PPC_RA0(a) | __PPC_RB(b))
 #define PPC_TLBILX_ALL(a, b)    PPC_TLBILX(0, a, b)
 #define PPC_TLBILX_PID(a, b)    PPC_TLBILX(1, a, b)
 #define PPC_TLBILX_VA(a, b)     PPC_TLBILX(3, a, b)
 #define PPC_WAIT(w)             stringify_in_c(.long PPC_INST_WAIT | \
                                         __PPC_WC(w))
 #define PPC_TLBIE(lp,a)         stringify_in_c(.long PPC_INST_TLBIE | \
-                                               __PPC_RB(a) | __PPC_RS(lp))
+                                               ___PPC_RB(a) | ___PPC_RS(lp))
 #define PPC_TLBSRX_DOT(a,b)     stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
-                                        __PPC_RA(a) | __PPC_RB(b))
+                                        __PPC_RA0(a) | __PPC_RB(b))
 #define PPC_TLBIVAX(a,b)        stringify_in_c(.long PPC_INST_TLBIVAX | \
-                                        __PPC_RA(a) | __PPC_RB(b))
+                                        __PPC_RA0(a) | __PPC_RB(b))
 
 #define PPC_ERATWE(s, a, w)     stringify_in_c(.long PPC_INST_ERATWE | \
                                         __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
 #define PPC_ERATRE(s, a, w)     stringify_in_c(.long PPC_INST_ERATRE | \
                                         __PPC_RS(s) | __PPC_RA(a) | __PPC_WS(w))
 #define PPC_ERATILX(t, a, b)    stringify_in_c(.long PPC_INST_ERATILX | \
-                                        __PPC_T_TLB(t) | __PPC_RA(a) | \
+                                        __PPC_T_TLB(t) | __PPC_RA0(a) | \
                                         __PPC_RB(b))
 #define PPC_ERATIVAX(s, a, b)   stringify_in_c(.long PPC_INST_ERATIVAX | \
-                                        __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
+                                        __PPC_RS(s) | __PPC_RA0(a) | __PPC_RB(b))
 #define PPC_ERATSX(t, a, w)     stringify_in_c(.long PPC_INST_ERATSX | \
-                                        __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
+                                        __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
 #define PPC_ERATSX_DOT(t, a, w) stringify_in_c(.long PPC_INST_ERATSX_DOT | \
-                                        __PPC_RS(t) | __PPC_RA(a) | __PPC_RB(b))
+                                        __PPC_RS(t) | __PPC_RA0(a) | __PPC_RB(b))
 #define PPC_SLBFEE_DOT(t, b)    stringify_in_c(.long PPC_INST_SLBFEE | \
                                         __PPC_RT(t) | __PPC_RB(b))
+/* PASemi instructions */
+#define LBZCIX(t,a,b)           stringify_in_c(.long PPC_INST_LBZCIX | \
+                                       __PPC_RT(t) | __PPC_RA(a) | __PPC_RB(b))
+#define STBCIX(s,a,b)           stringify_in_c(.long PPC_INST_STBCIX | \
+                                       __PPC_RS(s) | __PPC_RA(a) | __PPC_RB(b))
 
 /*
  * Define what the VSX XX1 form instructions will look like, then add
@@ -194,11 +272,11 @@
 #define VSX_XX1(s, a, b)        (__PPC_XS(s) | __PPC_RA(a) | __PPC_RB(b))
 #define VSX_XX3(t, a, b)        (__PPC_XT(t) | __PPC_XA(a) | __PPC_XB(b))
 #define STXVD2X(s, a, b)        stringify_in_c(.long PPC_INST_STXVD2X | \
-                                               VSX_XX1((s), (a), (b)))
+                                               VSX_XX1((s), a, b))
 #define LXVD2X(s, a, b)         stringify_in_c(.long PPC_INST_LXVD2X | \
-                                               VSX_XX1((s), (a), (b)))
+                                               VSX_XX1((s), a, b))
 #define XXLOR(t, a, b)          stringify_in_c(.long PPC_INST_XXLOR | \
-                                               VSX_XX3((t), (a), (b)))
+                                               VSX_XX3((t), a, b))
 
 #define PPC_NAP                 stringify_in_c(.long PPC_INST_NAP)
 #define PPC_SLEEP               stringify_in_c(.long PPC_INST_SLEEP)
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 15444204a3a..ea2a86e8ff9 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -126,26 +126,26 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
 #define REST_32VRS(n,b,base)    REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
 
 /* Save the lower 32 VSRs in the thread VSR region */
-#define SAVE_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n));  STXVD2X(n,base,b)
+#define SAVE_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n));  STXVD2X(n,R##base,R##b)
 #define SAVE_2VSRS(n,b,base)    SAVE_VSR(n,b,base); SAVE_VSR(n+1,b,base)
 #define SAVE_4VSRS(n,b,base)    SAVE_2VSRS(n,b,base); SAVE_2VSRS(n+2,b,base)
 #define SAVE_8VSRS(n,b,base)    SAVE_4VSRS(n,b,base); SAVE_4VSRS(n+4,b,base)
 #define SAVE_16VSRS(n,b,base)   SAVE_8VSRS(n,b,base); SAVE_8VSRS(n+8,b,base)
 #define SAVE_32VSRS(n,b,base)   SAVE_16VSRS(n,b,base); SAVE_16VSRS(n+16,b,base)
-#define REST_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n)); LXVD2X(n,base,b)
+#define REST_VSR(n,b,base)      li b,THREAD_VSR0+(16*(n)); LXVD2X(n,R##base,R##b)
 #define REST_2VSRS(n,b,base)    REST_VSR(n,b,base); REST_VSR(n+1,b,base)
 #define REST_4VSRS(n,b,base)    REST_2VSRS(n,b,base); REST_2VSRS(n+2,b,base)
 #define REST_8VSRS(n,b,base)    REST_4VSRS(n,b,base); REST_4VSRS(n+4,b,base)
 #define REST_16VSRS(n,b,base)   REST_8VSRS(n,b,base); REST_8VSRS(n+8,b,base)
 #define REST_32VSRS(n,b,base)   REST_16VSRS(n,b,base); REST_16VSRS(n+16,b,base)
 /* Save the upper 32 VSRs (32-63) in the thread VSX region (0-31) */
-#define SAVE_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n));  STXVD2X(n+32,base,b)
+#define SAVE_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n));  STXVD2X(n+32,R##base,R##b)
 #define SAVE_2VSRSU(n,b,base)   SAVE_VSRU(n,b,base); SAVE_VSRU(n+1,b,base)
 #define SAVE_4VSRSU(n,b,base)   SAVE_2VSRSU(n,b,base); SAVE_2VSRSU(n+2,b,base)
 #define SAVE_8VSRSU(n,b,base)   SAVE_4VSRSU(n,b,base); SAVE_4VSRSU(n+4,b,base)
 #define SAVE_16VSRSU(n,b,base)  SAVE_8VSRSU(n,b,base); SAVE_8VSRSU(n+8,b,base)
 #define SAVE_32VSRSU(n,b,base)  SAVE_16VSRSU(n,b,base); SAVE_16VSRSU(n+16,b,base)
-#define REST_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,base,b)
+#define REST_VSRU(n,b,base)     li b,THREAD_VR0+(16*(n)); LXVD2X(n+32,R##base,R##b)
 #define REST_2VSRSU(n,b,base)   REST_VSRU(n,b,base); REST_VSRU(n+1,b,base)
 #define REST_4VSRSU(n,b,base)   REST_2VSRSU(n,b,base); REST_2VSRSU(n+2,b,base)
 #define REST_8VSRSU(n,b,base)   REST_4VSRSU(n,b,base); REST_4VSRSU(n+4,b,base)
@@ -178,9 +178,24 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
 #define HMT_HIGH        or      3,3,3
 #define HMT_EXTRA_HIGH  or      7,7,7           # power7 only
 
+#ifdef CONFIG_PPC64
+#define ULONG_SIZE      8
+#else
+#define ULONG_SIZE      4
+#endif
+#define __VCPU_GPR(n)   (VCPU_GPRS + (n * ULONG_SIZE))
+#define VCPU_GPR(n)     __VCPU_GPR(__REG_##n)
+
 #ifdef __KERNEL__
 #ifdef CONFIG_PPC64
 
+#define STACKFRAMESIZE 256
+#define __STK_REG(i)   (112 + ((i)-14)*8)
+#define STK_REG(i)     __STK_REG(__REG_##i)
+
+#define __STK_PARAM(i)  (48 + ((i)-3)*8)
+#define STK_PARAM(i)    __STK_PARAM(__REG_##i)
+
 #define XGLUE(a,b) a##b
 #define GLUE(a,b) XGLUE(a,b)
 
@@ -295,14 +310,14 @@ n:
  */
 #ifdef __powerpc64__
 #define LOAD_REG_IMMEDIATE(reg,expr)            \
-        lis     (reg),(expr)@highest;           \
-        ori     (reg),(reg),(expr)@higher;      \
-        rldicr  (reg),(reg),32,31;              \
-        oris    (reg),(reg),(expr)@h;           \
-        ori     (reg),(reg),(expr)@l;
+        lis     reg,(expr)@highest;             \
+        ori     reg,reg,(expr)@higher;  \
+        rldicr  reg,reg,32,31;          \
+        oris    reg,reg,(expr)@h;               \
+        ori     reg,reg,(expr)@l;
 
 #define LOAD_REG_ADDR(reg,name)                 \
-        ld      (reg),name@got(r2)
+        ld      reg,name@got(r2)
 
 #define LOAD_REG_ADDRBASE(reg,name)     LOAD_REG_ADDR(reg,name)
 #define ADDROFF(name)                   0
@@ -313,12 +328,12 @@ n:
 #else /* 32-bit */
 
 #define LOAD_REG_IMMEDIATE(reg,expr)            \
-        lis     (reg),(expr)@ha;                \
-        addi    (reg),(reg),(expr)@l;
+        lis     reg,(expr)@ha;          \
+        addi    reg,reg,(expr)@l;
 
 #define LOAD_REG_ADDR(reg,name)         LOAD_REG_IMMEDIATE(reg, name)
 
-#define LOAD_REG_ADDRBASE(reg, name)    lis     (reg),name@ha
+#define LOAD_REG_ADDRBASE(reg, name)    lis     reg,name@ha
 #define ADDROFF(name)                   name@l
 
 /* offsets for stack frame layout */
@@ -372,9 +387,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #ifdef CONFIG_PPC64
 #define MTOCRF(FXM, RS)                 \
         BEGIN_FTR_SECTION_NESTED(848);  \
-        mtcrf   (FXM), (RS);            \
+        mtcrf   (FXM), RS;              \
         FTR_SECTION_ELSE_NESTED(848);   \
-        mtocrf (FXM), (RS);             \
+        mtocrf (FXM), RS;               \
         ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_NOEXECUTE, 848)
 #endif
 
@@ -463,6 +478,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #ifdef CONFIG_PPC_BOOK3S_64
 #define RFI             rfid
 #define MTMSRD(r)       mtmsrd  r
+#define MTMSR_EERI(reg) mtmsrd  reg,1
 #else
 #define FIX_SRR1(ra, rb)
 #ifndef CONFIG_40x
@@ -471,6 +487,7 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define RFI             rfi; b .        /* Prevent prefetch past rfi */
 #endif
 #define MTMSRD(r)       mtmsr   r
+#define MTMSR_EERI(reg) mtmsr   reg
 #define CLR_TOP32(r)
 #endif
 
@@ -490,40 +507,46 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
 #define cr7     7
 
 
-/* General Purpose Registers (GPRs) */
-
-#define r0      0
-#define r1      1
-#define r2      2
-#define r3      3
-#define r4      4
-#define r5      5
-#define r6      6
-#define r7      7
-#define r8      8
-#define r9      9
-#define r10     10
-#define r11     11
-#define r12     12
-#define r13     13
-#define r14     14
-#define r15     15
-#define r16     16
-#define r17     17
-#define r18     18
-#define r19     19
-#define r20     20
-#define r21     21
-#define r22     22
-#define r23     23
-#define r24     24
-#define r25     25
-#define r26     26
-#define r27     27
-#define r28     28
-#define r29     29
-#define r30     30
-#define r31     31
+/*
+ * General Purpose Registers (GPRs)
+ *
+ * The lower case r0-r31 should be used in preference to the upper
+ * case R0-R31 as they provide more error checking in the assembler.
+ * Use R0-31 only when really nessesary.
+ */
+
+#define r0      %r0
+#define r1      %r1
+#define r2      %r2
+#define r3      %r3
+#define r4      %r4
+#define r5      %r5
+#define r6      %r6
+#define r7      %r7
+#define r8      %r8
+#define r9      %r9
+#define r10     %r10
+#define r11     %r11
+#define r12     %r12
+#define r13     %r13
+#define r14     %r14
+#define r15     %r15
+#define r16     %r16
+#define r17     %r17
+#define r18     %r18
+#define r19     %r19
+#define r20     %r20
+#define r21     %r21
+#define r22     %r22
+#define r23     %r23
+#define r24     %r24
+#define r25     %r25
+#define r26     %r26
+#define r27     %r27
+#define r28     %r28
+#define r29     %r29
+#define r30     %r30
+#define r31     %r31
 
 
 /* Floating Point Registers (FPRs) */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 413a5eaef56..54b73a28c20 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -386,13 +386,12 @@ extern unsigned long cpuidle_disable;
 enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 
 extern int powersave_nap;       /* set if nap mode can be used in idle loop */
+extern void power7_nap(void);
 
 #ifdef CONFIG_PSERIES_IDLE
 extern void update_smt_snooze_delay(int snooze);
-extern int pseries_notify_cpuidle_add_cpu(int cpu);
 #else
 static inline void update_smt_snooze_delay(int snooze) {}
-static inline int pseries_notify_cpuidle_add_cpu(int cpu) { return 0; }
 #endif
 
 extern void flush_instruction_cache(void);
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 5e0b6d511e1..229571a4939 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -499,6 +499,7 @@ enum comm_dir {
 /* I-RAM */
 #define QE_IRAM_IADD_AIE        0x80000000      /* Auto Increment Enable */
 #define QE_IRAM_IADD_BADDR      0x00080000      /* Base Address */
+#define QE_IRAM_READY           0x80000000      /* Ready */
 
 /* UPC */
 #define UPGCR_PROTOCOL  0x80000000      /* protocol ul2 or pl2 */
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index f0cb7f461b9..638608677e2 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -491,6 +491,7 @@
 #define SPRN_SPRG1      0x111   /* Special Purpose Register General 1 */
 #define SPRN_SPRG2      0x112   /* Special Purpose Register General 2 */
 #define SPRN_SPRG3      0x113   /* Special Purpose Register General 3 */
+#define SPRN_USPRG3     0x103   /* SPRG3 userspace read */
 #define SPRN_SPRG4      0x114   /* Special Purpose Register General 4 */
 #define SPRN_SPRG5      0x115   /* Special Purpose Register General 5 */
 #define SPRN_SPRG6      0x116   /* Special Purpose Register General 6 */
@@ -753,14 +754,14 @@
  * 64-bit server:
  *      - SPRG0 unused (reserved for HV on Power4)
  *      - SPRG2 scratch for exception vectors
- *      - SPRG3 unused (user visible)
+ *      - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
  *      - HSPRG0 stores PACA in HV mode
  *      - HSPRG1 scratch for "HV" exceptions
  *
  * 64-bit embedded
  *      - SPRG0 generic exception scratch
  *      - SPRG2 TLB exception stack
- *      - SPRG3 unused (user visible)
+ *      - SPRG3 CPU and NUMA node for VDSO getcpu (user visible)
  *      - SPRG4 unused (user visible)
  *      - SPRG6 TLB miss scratch (user visible, sorry !)
  *      - SPRG7 critical exception scratch
@@ -1024,7 +1025,8 @@
 /* Macros for setting and retrieving special purpose registers */
 #ifndef __ASSEMBLY__
 #define mfmsr()         ({unsigned long rval; \
-                        asm volatile("mfmsr %0" : "=r" (rval)); rval;})
+                        asm volatile("mfmsr %0" : "=r" (rval) : \
+                                                : "memory"); rval;})
 #ifdef CONFIG_PPC_BOOK3S_64
 #define __mtmsrd(v, l)  asm volatile("mtmsrd %0," __stringify(l) \
                                      : : "r" (v) : "memory")
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index 68831e9cf82..faf93529cbf 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -22,6 +22,12 @@
 
 #define THREAD_SIZE             (1 << THREAD_SHIFT)
 
+#ifdef CONFIG_PPC64
+#define CURRENT_THREAD_INFO(dest, sp)   clrrdi dest, sp, THREAD_SHIFT
+#else
+#define CURRENT_THREAD_INFO(dest, sp)   rlwinm dest, sp, 0, 0, 31-THREAD_SHIFT
+#endif
+
 #ifndef __ASSEMBLY__
 #include <linux/cache.h>
 #include <asm/processor.h>
diff --git a/arch/powerpc/include/asm/trace.h b/arch/powerpc/include/asm/trace.h
index cbe2297d68b..5712f06905a 100644
--- a/arch/powerpc/include/asm/trace.h
+++ b/arch/powerpc/include/asm/trace.h
@@ -8,7 +8,7 @@
 
 struct pt_regs;
 
-TRACE_EVENT(irq_entry,
+DECLARE_EVENT_CLASS(ppc64_interrupt_class,
 
         TP_PROTO(struct pt_regs *regs),
 
@@ -25,55 +25,32 @@ TRACE_EVENT(irq_entry,
         TP_printk("pt_regs=%p", __entry->regs)
 );
 
-TRACE_EVENT(irq_exit,
+DEFINE_EVENT(ppc64_interrupt_class, irq_entry,
 
         TP_PROTO(struct pt_regs *regs),
 
-        TP_ARGS(regs),
-
-        TP_STRUCT__entry(
-                __field(struct pt_regs *, regs)
-        ),
-
-        TP_fast_assign(
-                __entry->regs = regs;
-        ),
-
-        TP_printk("pt_regs=%p", __entry->regs)
+        TP_ARGS(regs)
 );
 
-TRACE_EVENT(timer_interrupt_entry,
+DEFINE_EVENT(ppc64_interrupt_class, irq_exit,
 
         TP_PROTO(struct pt_regs *regs),
 
-        TP_ARGS(regs),
-
-        TP_STRUCT__entry(
-                __field(struct pt_regs *, regs)
-        ),
-
-        TP_fast_assign(
-                __entry->regs = regs;
-        ),
-
-        TP_printk("pt_regs=%p", __entry->regs)
+        TP_ARGS(regs)
 );
 
-TRACE_EVENT(timer_interrupt_exit,
+DEFINE_EVENT(ppc64_interrupt_class, timer_interrupt_entry,
 
         TP_PROTO(struct pt_regs *regs),
 
-        TP_ARGS(regs),
+        TP_ARGS(regs)
+);
 
-        TP_STRUCT__entry(
-                __field(struct pt_regs *, regs)
-        ),
+DEFINE_EVENT(ppc64_interrupt_class, timer_interrupt_exit,
 
-        TP_fast_assign(
-                __entry->regs = regs;
-        ),
+        TP_PROTO(struct pt_regs *regs),
 
-        TP_printk("pt_regs=%p", __entry->regs)
+        TP_ARGS(regs)
 );
 
 #ifdef CONFIG_PPC_PSERIES
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index d3d1b5efd7e..bd377a36861 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -389,7 +389,6 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_ALARM
diff --git a/arch/powerpc/include/asm/vdso.h b/arch/powerpc/include/asm/vdso.h
index dc0419b66f1..50f261bc3e9 100644
--- a/arch/powerpc/include/asm/vdso.h
+++ b/arch/powerpc/include/asm/vdso.h
@@ -22,6 +22,8 @@ extern unsigned long vdso64_rt_sigtramp;
 extern unsigned long vdso32_sigtramp;
 extern unsigned long vdso32_rt_sigtramp;
 
+int __cpuinit vdso_getcpu_init(void);
+
 #else /* __ASSEMBLY__ */
 
 #ifdef __VDSO64__
diff --git a/arch/powerpc/include/asm/vio.h b/arch/powerpc/include/asm/vio.h
index b19adf751dd..df81cb72d1e 100644
--- a/arch/powerpc/include/asm/vio.h
+++ b/arch/powerpc/include/asm/vio.h
@@ -44,6 +44,8 @@
  */
 #define VIO_CMO_MIN_ENT 1562624
 
+extern struct bus_type vio_bus_type;
+
 struct iommu_table;
 
 /*
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 83afacd3ba7..bb282dd8161 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -128,6 +128,7 @@ ifneq ($(CONFIG_XMON)$(CONFIG_KEXEC),)
 obj-y                           += ppc_save_regs.o
 endif
 
+obj-$(CONFIG_EPAPR_PARAVIRT)    += epapr_paravirt.o epapr_hcalls.o
 obj-$(CONFIG_KVM_GUEST)         += kvm.o kvm_emul.o
 
 # Disable GCOV in odd or sensitive code
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 52c7ad78242..e8995727b1c 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -76,6 +76,7 @@ int main(void)
         DEFINE(SIGSEGV, SIGSEGV);
         DEFINE(NMI_MASK, NMI_MASK);
         DEFINE(THREAD_DSCR, offsetof(struct thread_struct, dscr));
+        DEFINE(THREAD_DSCR_INHERIT, offsetof(struct thread_struct, dscr_inherit));
 #else
         DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
 #endif /* CONFIG_PPC64 */
@@ -533,6 +534,7 @@ int main(void)
         HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
         HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
         HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
+        HSTATE_FIELD(HSTATE_SPRG3, sprg3);
         HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
         HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
         HSTATE_FIELD(HSTATE_NAPPING, napping);
diff --git a/arch/powerpc/kernel/cpu_setup_a2.S b/arch/powerpc/kernel/cpu_setup_a2.S
index ebc62f42a23..61f079e05b6 100644
--- a/arch/powerpc/kernel/cpu_setup_a2.S
+++ b/arch/powerpc/kernel/cpu_setup_a2.S
@@ -100,19 +100,19 @@ _icswx_skip_guest:
         lis     r4,(MMUCR0_TLBSEL_I|MMUCR0_ECL)@h
         mtspr   SPRN_MMUCR0, r4
         li      r4,A2_IERAT_SIZE-1
-        PPC_ERATWE(r4,r4,3)
+        PPC_ERATWE(R4,R4,3)
 
         /* Now set the D-ERAT watermark to 31 */
         lis     r4,(MMUCR0_TLBSEL_D|MMUCR0_ECL)@h
         mtspr   SPRN_MMUCR0, r4
         li      r4,A2_DERAT_SIZE-1
-        PPC_ERATWE(r4,r4,3)
+        PPC_ERATWE(R4,R4,3)
 
         /* And invalidate the beast just in case. That won't get rid of
          * a bolted entry though it will be in LRU and so will go away eventually
          * but let's not bother for now
          */
-        PPC_ERATILX(0,0,0)
+        PPC_ERATILX(0,0,R0)
 1:
         blr
 
diff --git a/arch/powerpc/kernel/dbell.c b/arch/powerpc/kernel/dbell.c
index 5b25c8060fd..a892680668d 100644
--- a/arch/powerpc/kernel/dbell.c
+++ b/arch/powerpc/kernel/dbell.c
@@ -28,6 +28,8 @@ void doorbell_setup_this_cpu(void)
 
 void doorbell_cause_ipi(int cpu, unsigned long data)
 {
+        /* Order previous accesses vs. msgsnd, which is treated as a store */
+        mb();
         ppc_msgsnd(PPC_DBELL, 0, data);
 }
 
diff --git a/arch/powerpc/kernel/dma-iommu.c b/arch/powerpc/kernel/dma-iommu.c
index bcfdcd22c76..e4897523de4 100644
--- a/arch/powerpc/kernel/dma-iommu.c
+++ b/arch/powerpc/kernel/dma-iommu.c
@@ -83,11 +83,10 @@ static int dma_iommu_dma_supported(struct device *dev, u64 mask)
                 return 0;
         }
 
-        if ((tbl->it_offset + tbl->it_size) > (mask >> IOMMU_PAGE_SHIFT)) {
-                dev_info(dev, "Warning: IOMMU window too big for device mask\n");
-                dev_info(dev, "mask: 0x%08llx, table end: 0x%08lx\n",
-                                mask, (tbl->it_offset + tbl->it_size) <<
-                                IOMMU_PAGE_SHIFT);
+        if (tbl->it_offset > (mask >> IOMMU_PAGE_SHIFT)) {
+                dev_info(dev, "Warning: IOMMU offset too big for device mask\n");
+                dev_info(dev, "mask: 0x%08llx, table offset: 0x%08lx\n",
+                                mask, tbl->it_offset << IOMMU_PAGE_SHIFT);
                 return 0;
         } else
                 return 1;
@@ -109,6 +108,7 @@ static u64 dma_iommu_get_required_mask(struct device *dev)
 struct dma_map_ops dma_iommu_ops = {
         .alloc                  = dma_iommu_alloc_coherent,
         .free                   = dma_iommu_free_coherent,
+        .mmap                   = dma_direct_mmap_coherent,
         .map_sg                 = dma_iommu_map_sg,
         .unmap_sg               = dma_iommu_unmap_sg,
         .dma_supported          = dma_iommu_dma_supported,
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index 4ab88dafb23..46943651da2 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -49,6 +49,7 @@ static u64 swiotlb_powerpc_get_required(struct device *dev)
 struct dma_map_ops swiotlb_dma_ops = {
         .alloc = dma_direct_alloc_coherent,
         .free = dma_direct_free_coherent,
+        .mmap = dma_direct_mmap_coherent,
         .map_sg = swiotlb_map_sg_attrs,
         .unmap_sg = swiotlb_unmap_sg_attrs,
         .dma_supported = swiotlb_dma_supported,
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index b1ec983dcec..355b9d84b0f 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -11,6 +11,8 @@
 #include <linux/gfp.h>
 #include <linux/memblock.h>
 #include <linux/export.h>
+#include <linux/pci.h>
+#include <asm/vio.h>
 #include <asm/bug.h>
 #include <asm/abs_addr.h>
 #include <asm/machdep.h>
@@ -65,6 +67,24 @@ void dma_direct_free_coherent(struct device *dev, size_t size,
 #endif
 }
 
+int dma_direct_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
+                             void *cpu_addr, dma_addr_t handle, size_t size,
+                             struct dma_attrs *attrs)
+{
+        unsigned long pfn;
+
+#ifdef CONFIG_NOT_COHERENT_CACHE
+        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+        pfn = __dma_get_coherent_pfn((unsigned long)cpu_addr);
+#else
+        pfn = page_to_pfn(virt_to_page(cpu_addr));
+#endif
+        return remap_pfn_range(vma, vma->vm_start,
+                               pfn + vma->vm_pgoff,
+                               vma->vm_end - vma->vm_start,
+                               vma->vm_page_prot);
+}
+
 static int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl,
                              int nents, enum dma_data_direction direction,
                              struct dma_attrs *attrs)
@@ -154,6 +174,7 @@ static inline void dma_direct_sync_single(struct device *dev,
 struct dma_map_ops dma_direct_ops = {
         .alloc                          = dma_direct_alloc_coherent,
         .free                           = dma_direct_free_coherent,
+        .mmap                           = dma_direct_mmap_coherent,
         .map_sg                         = dma_direct_map_sg,
         .unmap_sg                       = dma_direct_unmap_sg,
         .dma_supported                  = dma_direct_dma_supported,
@@ -205,26 +226,15 @@ EXPORT_SYMBOL_GPL(dma_get_required_mask);
 
 static int __init dma_init(void)
 {
-       dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+        dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
+#ifdef CONFIG_PCI
+        dma_debug_add_bus(&pci_bus_type);
+#endif
+#ifdef CONFIG_IBMVIO
+        dma_debug_add_bus(&vio_bus_type);
+#endif
 
        return 0;
 }
 fs_initcall(dma_init);
 
-int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
-                      void *cpu_addr, dma_addr_t handle, size_t size)
-{
-        unsigned long pfn;
-
-#ifdef CONFIG_NOT_COHERENT_CACHE
-        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-        pfn = __dma_get_coherent_pfn((unsigned long)cpu_addr);
-#else
-        pfn = page_to_pfn(virt_to_page(cpu_addr));
-#endif
-        return remap_pfn_range(vma, vma->vm_start,
-                               pfn + vma->vm_pgoff,
-                               vma->vm_end - vma->vm_start,
-                               vma->vm_page_prot);
-}
-EXPORT_SYMBOL_GPL(dma_mmap_coherent);
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index ba3aeb4bc06..ead5016b02d 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -89,6 +89,10 @@ crit_transfer_to_handler:
         mfspr   r0,SPRN_SRR1
         stw     r0,_SRR1(r11)
 
+        /* set the stack limit to the current stack
+         * and set the limit to protect the thread_info
+         * struct
+         */
         mfspr   r8,SPRN_SPRG_THREAD
         lwz     r0,KSP_LIMIT(r8)
         stw     r0,SAVED_KSP_LIMIT(r11)
@@ -109,6 +113,10 @@ crit_transfer_to_handler:
         mfspr   r0,SPRN_SRR1
         stw     r0,crit_srr1@l(0)
 
+        /* set the stack limit to the current stack
+         * and set the limit to protect the thread_info
+         * struct
+         */
         mfspr   r8,SPRN_SPRG_THREAD
         lwz     r0,KSP_LIMIT(r8)
         stw     r0,saved_ksp_limit@l(0)
@@ -158,7 +166,7 @@ transfer_to_handler:
         tophys(r11,r11)
         addi    r11,r11,global_dbcr0@l
 #ifdef CONFIG_SMP
-        rlwinm  r9,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r9, r1)
         lwz     r9,TI_CPU(r9)
         slwi    r9,r9,3
         add     r11,r11,r9
@@ -179,7 +187,7 @@ transfer_to_handler:
         ble-    stack_ovf               /* then the kernel stack overflowed */
 5:
 #if defined(CONFIG_6xx) || defined(CONFIG_E500)
-        rlwinm  r9,r1,0,0,31-THREAD_SHIFT
+        CURRENT_THREAD_INFO(r9, r1)
         tophys(r9,r9)                   /* check local flags */
         lwz     r12,TI_LOCAL_FLAGS(r9)
         mtcrf   0x01,r12
@@ -226,13 +234,7 @@ reenable_mmu:				/* re-enable mmu so we can */
         stw     r3,16(r1)
         stw     r4,20(r1)
         stw     r5,24(r1)
-        andi.   r12,r12,MSR_PR
-        b       11f
-        bl      trace_hardirqs_off
-        b       12f
-11:
         bl      trace_hardirqs_off
-12:
         lwz     r5,24(r1)
         lwz     r4,20(r1)
         lwz     r3,16(r1)
@@ -333,7 +335,7 @@ _GLOBAL(DoSyscall)
         mtmsr   r11
 1:
 #endif /* CONFIG_TRACE_IRQFLAGS */
-        rlwinm  r10,r1,0,0,(31-THREAD_SHIFT)    /* current_thread_info() */
+        CURRENT_THREAD_INFO(r10, r1)
         lwz     r11,TI_FLAGS(r10)
         andi.   r11,r11,_TIF_SYSCALL_T_OR_A
         bne-    syscall_dotrace
@@ -354,7 +356,7 @@ ret_from_syscall:
         bl      do_show_syscall_exit
 #endif
         mr      r6,r3
-        rlwinm  r12,r1,0,0,(31-THREAD_SHIFT)    /* current_thread_info() */
+        CURRENT_THREAD_INFO(r12, r1)
         /* disable interrupts so current_thread_info()->flags can't change */
         LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */
         /* Note: We don't bother telling lockdep about it */
@@ -815,7 +817,7 @@ ret_from_except:
 
 user_exc_return:                /* r10 contains MSR_KERNEL here */
         /* Check current_thread_info()->flags */
-        rlwinm  r9,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r9, r1)
         lwz     r9,TI_FLAGS(r9)
         andi.   r0,r9,_TIF_USER_WORK_MASK
         bne     do_work
@@ -835,7 +837,7 @@ restore_user:
 /* N.B. the only way to get here is from the beq following ret_from_except. */
 resume_kernel:
         /* check current_thread_info->preempt_count */
-        rlwinm  r9,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r9, r1)
         lwz     r0,TI_PREEMPT(r9)
         cmpwi   0,r0,0          /* if non-zero, just restore regs and return */
         bne     restore
@@ -852,7 +854,7 @@ resume_kernel:
         bl      trace_hardirqs_off
 #endif
 1:      bl      preempt_schedule_irq
-        rlwinm  r9,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r9, r1)
         lwz     r3,TI_FLAGS(r9)
         andi.   r0,r3,_TIF_NEED_RESCHED
         bne-    1b
@@ -1122,7 +1124,7 @@ ret_from_debug_exc:
         lwz     r10,SAVED_KSP_LIMIT(r1)
         stw     r10,KSP_LIMIT(r9)
         lwz     r9,THREAD_INFO-THREAD(r9)
-        rlwinm  r10,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r10, r1)
         lwz     r10,TI_PREEMPT(r10)
         stw     r10,TI_PREEMPT(r9)
         RESTORE_xSRR(SRR0,SRR1);
@@ -1156,7 +1158,7 @@ load_dbcr0:
         lis     r11,global_dbcr0@ha
         addi    r11,r11,global_dbcr0@l
 #ifdef CONFIG_SMP
-        rlwinm  r9,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r9, r1)
         lwz     r9,TI_CPU(r9)
         slwi    r9,r9,3
         add     r11,r11,r9
@@ -1197,7 +1199,7 @@ recheck:
         LOAD_MSR_KERNEL(r10,MSR_KERNEL)
         SYNC
         MTMSRD(r10)             /* disable interrupts */
-        rlwinm  r9,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r9, r1)
         lwz     r9,TI_FLAGS(r9)
         andi.   r0,r9,_TIF_NEED_RESCHED
         bne-    do_resched
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 5971c85df13..b40e0b4815b 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -146,7 +146,7 @@ END_FW_FTR_SECTION_IFSET(FW_FEATURE_SPLPAR)
         REST_2GPRS(7,r1)
         addi    r9,r1,STACK_FRAME_OVERHEAD
 #endif
-        clrrdi  r11,r1,THREAD_SHIFT
+        CURRENT_THREAD_INFO(r11, r1)
         ld      r10,TI_FLAGS(r11)
         andi.   r11,r10,_TIF_SYSCALL_T_OR_A
         bne-    syscall_dotrace
@@ -181,7 +181,7 @@ syscall_exit:
         bl      .do_show_syscall_exit
         ld      r3,RESULT(r1)
 #endif
-        clrrdi  r12,r1,THREAD_SHIFT
+        CURRENT_THREAD_INFO(r12, r1)
 
         ld      r8,_MSR(r1)
 #ifdef CONFIG_PPC_BOOK3S
@@ -197,7 +197,16 @@ syscall_exit:
         wrteei  0
 #else
         ld      r10,PACAKMSR(r13)
-        mtmsrd  r10,1
+        /*
+         * For performance reasons we clear RI the same time that we
+         * clear EE. We only need to clear RI just before we restore r13
+         * below, but batching it with EE saves us one expensive mtmsrd call.
+         * We have to be careful to restore RI if we branch anywhere from
+         * here (eg syscall_exit_work).
+         */
+        li      r9,MSR_RI
+        andc    r11,r10,r9
+        mtmsrd  r11,1
 #endif /* CONFIG_PPC_BOOK3E */
 
         ld      r9,TI_FLAGS(r12)
@@ -214,17 +223,6 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_IFCLR(CPU_FTR_STCX_CHECKS_ADDRESS)
         andi.   r6,r8,MSR_PR
         ld      r4,_LINK(r1)
-        /*
-         * Clear RI before restoring r13.  If we are returning to
-         * userspace and we take an exception after restoring r13,
-         * we end up corrupting the userspace r13 value.
-         */
-#ifdef CONFIG_PPC_BOOK3S
-        /* No MSR:RI on BookE */
-        li      r12,MSR_RI
-        andc    r11,r10,r12
-        mtmsrd  r11,1                   /* clear MSR.RI */
-#endif /* CONFIG_PPC_BOOK3S */
 
         beq-    1f
         ACCOUNT_CPU_USER_EXIT(r11, r12)
@@ -262,7 +260,7 @@ syscall_dotrace:
         ld      r7,GPR7(r1)
         ld      r8,GPR8(r1)
         addi    r9,r1,STACK_FRAME_OVERHEAD
-        clrrdi  r10,r1,THREAD_SHIFT
+        CURRENT_THREAD_INFO(r10, r1)
         ld      r10,TI_FLAGS(r10)
         b       .Lsyscall_dotrace_cont
 
@@ -271,6 +269,9 @@ syscall_enosys:
         b       syscall_exit
         
 syscall_exit_work:
+#ifdef CONFIG_PPC_BOOK3S
+        mtmsrd  r10,1           /* Restore RI */
+#endif
         /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
          If TIF_NOERROR is set, just save r3 as it is. */
 
@@ -369,6 +370,12 @@ _GLOBAL(ret_from_fork)
         li      r3,0
         b       syscall_exit
 
+        .section        ".toc","aw"
+DSCR_DEFAULT:
+        .tc dscr_default[TC],dscr_default
+
+        .section        ".text"
+
 /*
  * This routine switches between two different tasks.  The process
  * state of one is saved on its kernel stack.  Then the state
@@ -499,7 +506,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
 2:
 #endif /* !CONFIG_PPC_BOOK3S */
 
-        clrrdi  r7,r8,THREAD_SHIFT      /* base of new stack */
+        CURRENT_THREAD_INFO(r7, r8)  /* base of new stack */
         /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
            because we don't need to leave the 288-byte ABI gap at the
            top of the kernel stack. */
@@ -508,9 +515,6 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
         mr      r1,r8           /* start using new stack pointer */
         std     r7,PACAKSAVE(r13)
 
-        ld      r6,_CCR(r1)
-        mtcrf   0xFF,r6
-
 #ifdef CONFIG_ALTIVEC
 BEGIN_FTR_SECTION
         ld      r0,THREAD_VRSAVE(r4)
@@ -519,14 +523,22 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 #endif /* CONFIG_ALTIVEC */
 #ifdef CONFIG_PPC64
 BEGIN_FTR_SECTION
+        lwz     r6,THREAD_DSCR_INHERIT(r4)
+        ld      r7,DSCR_DEFAULT@toc(2)
         ld      r0,THREAD_DSCR(r4)
-        cmpd    r0,r25
-        beq     1f
+        cmpwi   r6,0
+        bne     1f
+        ld      r0,0(r7)
+1:      cmpd    r0,r25
+        beq     2f
         mtspr   SPRN_DSCR,r0
-1:      
+2:
 END_FTR_SECTION_IFSET(CPU_FTR_DSCR)
 #endif
 
+        ld      r6,_CCR(r1)
+        mtcrf   0xFF,r6
+
         /* r3-r13 are destroyed -- Cort */
         REST_8GPRS(14, r1)
         REST_10GPRS(22, r1)
@@ -558,7 +570,7 @@ _GLOBAL(ret_from_except_lite)
         mtmsrd  r10,1             /* Update machine state */
 #endif /* CONFIG_PPC_BOOK3E */
 
-        clrrdi  r9,r1,THREAD_SHIFT      /* current_thread_info() */
+        CURRENT_THREAD_INFO(r9, r1)
         ld      r3,_MSR(r1)
         ld      r4,TI_FLAGS(r9)
         andi.   r3,r3,MSR_PR
@@ -601,7 +613,7 @@ resume_kernel:
 1:      bl      .preempt_schedule_irq
 
         /* Re-test flags and eventually loop */
-        clrrdi  r9,r1,THREAD_SHIFT
+        CURRENT_THREAD_INFO(r9, r1)
         ld      r4,TI_FLAGS(r9)
         andi.   r0,r4,_TIF_NEED_RESCHED
         bne     1b
diff --git a/arch/powerpc/kernel/epapr_hcalls.S b/arch/powerpc/kernel/epapr_hcalls.S
new file mode 100644
index 00000000000..697b390ebfd
--- /dev/null
+++ b/arch/powerpc/kernel/epapr_hcalls.S
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/threads.h>
+#include <asm/reg.h>
+#include <asm/page.h>
+#include <asm/cputable.h>
+#include <asm/thread_info.h>
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+
+/* Hypercall entry point. Will be patched with device tree instructions. */
+.global epapr_hypercall_start
+epapr_hypercall_start:
+        li      r3, -1
+        nop
+        nop
+        nop
+        blr
diff --git a/arch/powerpc/kernel/epapr_paravirt.c b/arch/powerpc/kernel/epapr_paravirt.c
new file mode 100644
index 00000000000..028aeae370b
--- /dev/null
+++ b/arch/powerpc/kernel/epapr_paravirt.c
@@ -0,0 +1,52 @@
+/*
+ * ePAPR para-virtualization support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ */
+
+#include <linux/of.h>
+#include <asm/epapr_hcalls.h>
+#include <asm/cacheflush.h>
+#include <asm/code-patching.h>
+
+bool epapr_paravirt_enabled;
+
+static int __init epapr_paravirt_init(void)
+{
+        struct device_node *hyper_node;
+        const u32 *insts;
+        int len, i;
+
+        hyper_node = of_find_node_by_path("/hypervisor");
+        if (!hyper_node)
+                return -ENODEV;
+
+        insts = of_get_property(hyper_node, "hcall-instructions", &len);
+        if (!insts)
+                return -ENODEV;
+
+        if (len % 4 || len > (4 * 4))
+                return -ENODEV;
+
+        for (i = 0; i < (len / 4); i++)
+                patch_instruction(epapr_hypercall_start + i, insts[i]);
+
+        epapr_paravirt_enabled = true;
+
+        return 0;
+}
+
+early_initcall(epapr_paravirt_init);
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 7215cc2495d..98be7f0cd22 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -222,7 +222,7 @@ exc_##n##_bad_stack:							    \
  * interrupts happen before the wait instruction.
  */
 #define CHECK_NAPPING()                                                 \
-        clrrdi  r11,r1,THREAD_SHIFT;                                    \
+        CURRENT_THREAD_INFO(r11, r1);                                   \
         ld      r10,TI_LOCAL_FLAGS(r11);                                \
         andi.   r9,r10,_TLF_NAPPING;                                    \
         beq+    1f;                                                     \
@@ -903,7 +903,7 @@ skpinv:	addi	r6,r6,1				/* Increment */
         bne     1b                              /* If not, repeat */
 
         /* Invalidate all TLBs */
-        PPC_TLBILX_ALL(0,0)
+        PPC_TLBILX_ALL(0,R0)
         sync
         isync
 
@@ -961,7 +961,7 @@ skpinv:	addi	r6,r6,1				/* Increment */
         tlbwe
 
         /* Invalidate TLB1 */
-        PPC_TLBILX_ALL(0,0)
+        PPC_TLBILX_ALL(0,R0)
         sync
         isync
 
@@ -1020,7 +1020,7 @@ skpinv:	addi	r6,r6,1				/* Increment */
         tlbwe
 
         /* Invalidate TLB1 */
-        PPC_TLBILX_ALL(0,0)
+        PPC_TLBILX_ALL(0,R0)
         sync
         isync
 
@@ -1138,7 +1138,7 @@ a2_tlbinit_after_iprot_flush:
         tlbwe
 #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */
 
-        PPC_TLBILX(0,0,0)
+        PPC_TLBILX(0,0,R0)
         sync
         isync
 
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 1c06d297154..39aa97d3ff8 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -186,7 +186,7 @@ hardware_interrupt_hv:
         KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x800)
 
         MASKABLE_EXCEPTION_PSERIES(0x900, 0x900, decrementer)
-        MASKABLE_EXCEPTION_HV(0x980, 0x982, decrementer)
+        STD_EXCEPTION_HV(0x980, 0x982, hdecrementer)
 
         STD_EXCEPTION_PSERIES(0xa00, 0xa00, trap_0a)
         KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0xa00)
@@ -239,6 +239,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE)
          * out of line to handle them
          */
         . = 0xe00
+hv_exception_trampoline:
         b       h_data_storage_hv
         . = 0xe20
         b       h_instr_storage_hv
@@ -485,6 +486,7 @@ machine_check_common:
 
         STD_EXCEPTION_COMMON_ASYNC(0x500, hardware_interrupt, do_IRQ)
         STD_EXCEPTION_COMMON_ASYNC(0x900, decrementer, .timer_interrupt)
+        STD_EXCEPTION_COMMON(0x980, hdecrementer, .hdec_interrupt)
         STD_EXCEPTION_COMMON(0xa00, trap_0a, .unknown_exception)
         STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
         STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
@@ -851,7 +853,7 @@ BEGIN_FTR_SECTION
         bne-    do_ste_alloc            /* If so handle it */
 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
 
-        clrrdi  r11,r1,THREAD_SHIFT
+        CURRENT_THREAD_INFO(r11, r1)
         lwz     r0,TI_PREEMPT(r11)      /* If we're in an "NMI" */
         andis.  r0,r0,NMI_MASK@h        /* (i.e. an irq when soft-disabled) */
         bne     77f                     /* then don't call hash_page now */
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index de369558bf0..e0ada05f2df 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -26,7 +26,7 @@
 #include <asm/ptrace.h>
 
 #ifdef CONFIG_VSX
-#define REST_32FPVSRS(n,c,base)                                         \
+#define __REST_32FPVSRS(n,c,base)                                       \
 BEGIN_FTR_SECTION                                                       \
         b       2f;                                                     \
 END_FTR_SECTION_IFSET(CPU_FTR_VSX);                                     \
@@ -35,7 +35,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
 2:      REST_32VSRS(n,c,base);                                          \
 3:
 
-#define SAVE_32FPVSRS(n,c,base)                                         \
+#define __SAVE_32FPVSRS(n,c,base)                                       \
 BEGIN_FTR_SECTION                                                       \
         b       2f;                                                     \
 END_FTR_SECTION_IFSET(CPU_FTR_VSX);                                     \
@@ -44,9 +44,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
 2:      SAVE_32VSRS(n,c,base);                                          \
 3:
 #else
-#define REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
-#define SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
+#define __REST_32FPVSRS(n,b,base)       REST_32FPRS(n, base)
+#define __SAVE_32FPVSRS(n,b,base)       SAVE_32FPRS(n, base)
 #endif
+#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
+#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
 
 /*
  * This task wants to use the FPU now.
@@ -79,7 +81,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
         beq     1f
         toreal(r4)
         addi    r4,r4,THREAD            /* want last_task_used_math->thread */
-        SAVE_32FPVSRS(0, r5, r4)
+        SAVE_32FPVSRS(0, R5, R4)
         mffs    fr0
         stfd    fr0,THREAD_FPSCR(r4)
         PPC_LL  r5,PT_REGS(r4)
@@ -106,7 +108,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
 #endif
         lfd     fr0,THREAD_FPSCR(r5)
         MTFSF_L(fr0)
-        REST_32FPVSRS(0, r4, r5)
+        REST_32FPVSRS(0, R4, R5)
 #ifndef CONFIG_SMP
         subi    r4,r5,THREAD
         fromreal(r4)
@@ -140,7 +142,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
         addi    r3,r3,THREAD            /* want THREAD of task */
         PPC_LL  r5,PT_REGS(r3)
         PPC_LCMPI       0,r5,0
-        SAVE_32FPVSRS(0, r4 ,r3)
+        SAVE_32FPVSRS(0, R4 ,R3)
         mffs    fr0
         stfd    fr0,THREAD_FPSCR(r3)
         beq     1f
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
index bf99cfa6bbf..1fb78561096 100644
--- a/arch/powerpc/kernel/ftrace.c
+++ b/arch/powerpc/kernel/ftrace.c
@@ -63,11 +63,9 @@ ftrace_modify_code(unsigned long ip, unsigned int old, unsigned int new)
                 return -EINVAL;
 
         /* replace the text with the new text */
-        if (probe_kernel_write((void *)ip, &new, MCOUNT_INSN_SIZE))
+        if (patch_instruction((unsigned int *)ip, new))
                 return -EPERM;
 
-        flush_icache_range(ip, ip + 8);
-
         return 0;
 }
 
@@ -212,12 +210,9 @@ __ftrace_make_nop(struct module *mod,
          */
         op = 0x48000008;        /* b +8 */
 
-        if (probe_kernel_write((void *)ip, &op, MCOUNT_INSN_SIZE))
+        if (patch_instruction((unsigned int *)ip, op))
                 return -EPERM;
 
-
-        flush_icache_range(ip, ip + 8);
-
         return 0;
 }
 
@@ -245,9 +240,9 @@ __ftrace_make_nop(struct module *mod,
 
         /*
          * On PPC32 the trampoline looks like:
-         *  0x3d, 0x60, 0x00, 0x00  lis r11,sym@ha
-         *  0x39, 0x6b, 0x00, 0x00  addi r11,r11,sym@l
-         *  0x7d, 0x69, 0x03, 0xa6  mtctr r11
+         *  0x3d, 0x80, 0x00, 0x00  lis r12,sym@ha
+         *  0x39, 0x8c, 0x00, 0x00  addi r12,r12,sym@l
+         *  0x7d, 0x89, 0x03, 0xa6  mtctr r12
          *  0x4e, 0x80, 0x04, 0x20  bctr
          */
 
@@ -262,9 +257,9 @@ __ftrace_make_nop(struct module *mod,
         pr_devel(" %08x %08x ", jmp[0], jmp[1]);
 
         /* verify that this is what we expect it to be */
-        if (((jmp[0] & 0xffff0000) != 0x3d600000) ||
-            ((jmp[1] & 0xffff0000) != 0x396b0000) ||
-            (jmp[2] != 0x7d6903a6) ||
+        if (((jmp[0] & 0xffff0000) != 0x3d800000) ||
+            ((jmp[1] & 0xffff0000) != 0x398c0000) ||
+            (jmp[2] != 0x7d8903a6) ||
             (jmp[3] != 0x4e800420)) {
                 printk(KERN_ERR "Not a trampoline\n");
                 return -EINVAL;
@@ -286,11 +281,9 @@ __ftrace_make_nop(struct module *mod,
 
         op = PPC_INST_NOP;
 
-        if (probe_kernel_write((void *)ip, &op, MCOUNT_INSN_SIZE))
+        if (patch_instruction((unsigned int *)ip, op))
                 return -EPERM;
 
-        flush_icache_range(ip, ip + 8);
-
         return 0;
 }
 #endif /* PPC64 */
@@ -426,11 +419,9 @@ __ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
 
         pr_devel("write to %lx\n", rec->ip);
 
-        if (probe_kernel_write((void *)ip, &op, MCOUNT_INSN_SIZE))
+        if (patch_instruction((unsigned int *)ip, op))
                 return -EPERM;
 
-        flush_icache_range(ip, ip + 8);
-
         return 0;
 }
 #endif /* CONFIG_PPC64 */
@@ -484,6 +475,58 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
         return ret;
 }
 
+static int __ftrace_replace_code(struct dyn_ftrace *rec, int enable)
+{
+        unsigned long ftrace_addr = (unsigned long)FTRACE_ADDR;
+        int ret;
+
+        ret = ftrace_update_record(rec, enable);
+
+        switch (ret) {
+        case FTRACE_UPDATE_IGNORE:
+                return 0;
+        case FTRACE_UPDATE_MAKE_CALL:
+                return ftrace_make_call(rec, ftrace_addr);
+        case FTRACE_UPDATE_MAKE_NOP:
+                return ftrace_make_nop(NULL, rec, ftrace_addr);
+        }
+
+        return 0;
+}
+
+void ftrace_replace_code(int enable)
+{
+        struct ftrace_rec_iter *iter;
+        struct dyn_ftrace *rec;
+        int ret;
+
+        for (iter = ftrace_rec_iter_start(); iter;
+             iter = ftrace_rec_iter_next(iter)) {
+                rec = ftrace_rec_iter_record(iter);
+                ret = __ftrace_replace_code(rec, enable);
+                if (ret) {
+                        ftrace_bug(ret, rec->ip);
+                        return;
+                }
+        }
+}
+
+void arch_ftrace_update_code(int command)
+{
+        if (command & FTRACE_UPDATE_CALLS)
+                ftrace_replace_code(1);
+        else if (command & FTRACE_DISABLE_CALLS)
+                ftrace_replace_code(0);
+
+        if (command & FTRACE_UPDATE_TRACE_FUNC)
+                ftrace_update_ftrace_func(ftrace_trace_function);
+
+        if (command & FTRACE_START_FUNC_RET)
+                ftrace_enable_ftrace_graph_caller();
+        else if (command & FTRACE_STOP_FUNC_RET)
+                ftrace_disable_ftrace_graph_caller();
+}
+
 int __init ftrace_dyn_arch_init(void *data)
 {
         /* caller expects data to be zero */
@@ -587,18 +630,17 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
                 return;
         }
 
-        if (ftrace_push_return_trace(old, self_addr, &trace.depth, 0) == -EBUSY) {
-                *parent = old;
-                return;
-        }
-
         trace.func = self_addr;
+        trace.depth = current->curr_ret_stack + 1;
 
         /* Only trace if the calling function expects to */
         if (!ftrace_graph_entry(&trace)) {
-                current->curr_ret_stack--;
                 *parent = old;
+                return;
         }
+
+        if (ftrace_push_return_trace(old, self_addr, &trace.depth, 0) == -EBUSY)
+                *parent = old;
 }
 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
 
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 1f4434a3860..0f59863c3ad 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -192,7 +192,7 @@ _ENTRY(__early_start)
         li      r0,0
         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 
-        rlwinm  r22,r1,0,0,31-THREAD_SHIFT      /* current thread_info */
+        CURRENT_THREAD_INFO(r22, r1)
         stw     r24, TI_CPU(r22)
 
         bl      early_init
@@ -556,8 +556,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
         /* SPE Unavailable */
         START_EXCEPTION(SPEUnavailable)
         NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
-        bne     load_up_spe
-        addi    r3,r1,STACK_FRAME_OVERHEAD
+        beq     1f
+        bl      load_up_spe
+        b       fast_exception_return
+1:      addi    r3,r1,STACK_FRAME_OVERHEAD
         EXC_XFER_EE_LITE(0x2010, KernelSPE)
 #else
         EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
@@ -778,7 +780,7 @@ tlb_write_entry:
 /* Note that the SPE support is closely modeled after the AltiVec
  * support.  Changes to one are likely to be applicable to the
  * other!  */
-load_up_spe:
+_GLOBAL(load_up_spe)
 /*
  * Disable SPE for the task which had SPE previously,
  * and save its SPE registers in its thread_struct.
@@ -826,20 +828,7 @@ load_up_spe:
         subi    r4,r5,THREAD
         stw     r4,last_task_used_spe@l(r3)
 #endif /* !CONFIG_SMP */
-        /* restore registers and return */
-2:      REST_4GPRS(3, r11)
-        lwz     r10,_CCR(r11)
-        REST_GPR(1, r11)
-        mtcr    r10
-        lwz     r10,_LINK(r11)
-        mtlr    r10
-        REST_GPR(10, r11)
-        mtspr   SPRN_SRR1,r9
-        mtspr   SPRN_SRR0,r12
-        REST_GPR(9, r11)
-        REST_GPR(12, r11)
-        lwz     r11,GPR11(r11)
-        rfi
+        blr
 
 /*
  * SPE unavailable trap from kernel - print a message, but let
diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
index 2bc0584be81..956a4c496de 100644
--- a/arch/powerpc/kernel/hw_breakpoint.c
+++ b/arch/powerpc/kernel/hw_breakpoint.c
@@ -111,7 +111,7 @@ void arch_unregister_hw_breakpoint(struct perf_event *bp)
          * and the single_step_dabr_instruction(), then cleanup the breakpoint
          * restoration variables to prevent dangling pointers.
          */
-        if (bp->ctx->task)
+        if (bp->ctx && bp->ctx->task)
                 bp->ctx->task->thread.last_hit_ubp = NULL;
 }
 
@@ -253,7 +253,7 @@ int __kprobes hw_breakpoint_handler(struct die_args *args)
 
         /* Do not emulate user-space instructions, instead single-step them */
         if (user_mode(regs)) {
-                bp->ctx->task->thread.last_hit_ubp = bp;
+                current->thread.last_hit_ubp = bp;
                 regs->msr |= MSR_SE;
                 goto out;
         }
diff --git a/arch/powerpc/kernel/idle_6xx.S b/arch/powerpc/kernel/idle_6xx.S
index 15c611de1ee..1686916cc7f 100644
--- a/arch/powerpc/kernel/idle_6xx.S
+++ b/arch/powerpc/kernel/idle_6xx.S
@@ -135,7 +135,7 @@ BEGIN_FTR_SECTION
         DSSALL
         sync
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
-        rlwinm  r9,r1,0,0,31-THREAD_SHIFT       /* current thread_info */
+        CURRENT_THREAD_INFO(r9, r1)
         lwz     r8,TI_LOCAL_FLAGS(r9)   /* set napping bit */
         ori     r8,r8,_TLF_NAPPING      /* so when we take an exception */
         stw     r8,TI_LOCAL_FLAGS(r9)   /* it will return to our caller */
@@ -158,7 +158,7 @@ _GLOBAL(power_save_ppc32_restore)
         stw     r9,_NIP(r11)            /* make it do a blr */
 
 #ifdef CONFIG_SMP
-        rlwinm  r12,r11,0,0,31-THREAD_SHIFT
+        CURRENT_THREAD_INFO(r12, r11)
         lwz     r11,TI_CPU(r12)         /* get cpu number * 4 */
         slwi    r11,r11,2
 #else
diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S
index ff007b59448..4c7cb400858 100644
--- a/arch/powerpc/kernel/idle_book3e.S
+++ b/arch/powerpc/kernel/idle_book3e.S
@@ -60,7 +60,7 @@ _GLOBAL(book3e_idle)
 1:      /* Let's set the _TLF_NAPPING flag so interrupts make us return
          * to the right spot
         */
-        clrrdi  r11,r1,THREAD_SHIFT
+        CURRENT_THREAD_INFO(r11, r1)
         ld      r10,TI_LOCAL_FLAGS(r11)
         ori     r10,r10,_TLF_NAPPING
         std     r10,TI_LOCAL_FLAGS(r11)
diff --git a/arch/powerpc/kernel/idle_e500.S b/arch/powerpc/kernel/idle_e500.S
index 4f0ab85f378..15448668988 100644
--- a/arch/powerpc/kernel/idle_e500.S
+++ b/arch/powerpc/kernel/idle_e500.S
@@ -21,7 +21,7 @@
         .text
 
 _GLOBAL(e500_idle)
-        rlwinm  r3,r1,0,0,31-THREAD_SHIFT       /* current thread_info */
+        CURRENT_THREAD_INFO(r3, r1)
         lwz     r4,TI_LOCAL_FLAGS(r3)   /* set napping bit */
         ori     r4,r4,_TLF_NAPPING      /* so when we take an exception */
         stw     r4,TI_LOCAL_FLAGS(r3)   /* it will return to our caller */
@@ -96,7 +96,7 @@ _GLOBAL(power_save_ppc32_restore)
         stw     r9,_NIP(r11)            /* make it do a blr */
 
 #ifdef CONFIG_SMP
-        rlwinm  r12,r1,0,0,31-THREAD_SHIFT
+        CURRENT_THREAD_INFO(r12, r1)
         lwz     r11,TI_CPU(r12)         /* get cpu number * 4 */
         slwi    r11,r11,2
 #else
diff --git a/arch/powerpc/kernel/idle_power4.S b/arch/powerpc/kernel/idle_power4.S
index 2c71b0fc9f9..e3edaa18991 100644
--- a/arch/powerpc/kernel/idle_power4.S
+++ b/arch/powerpc/kernel/idle_power4.S
@@ -59,7 +59,7 @@ BEGIN_FTR_SECTION
         DSSALL
         sync
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
-        clrrdi  r9,r1,THREAD_SHIFT      /* current thread_info */
+        CURRENT_THREAD_INFO(r9, r1)
         ld      r8,TI_LOCAL_FLAGS(r9)   /* set napping bit */
         ori     r8,r8,_TLF_NAPPING      /* so when we take an exception */
         std     r8,TI_LOCAL_FLAGS(r9)   /* it will return to our caller */
diff --git a/arch/powerpc/kernel/idle_power7.S b/arch/powerpc/kernel/idle_power7.S
index 7140d838339..e11863f4e59 100644
--- a/arch/powerpc/kernel/idle_power7.S
+++ b/arch/powerpc/kernel/idle_power7.S
@@ -28,7 +28,9 @@ _GLOBAL(power7_idle)
         lwz     r4,ADDROFF(powersave_nap)(r3)
         cmpwi   0,r4,0
         beqlr
+        /* fall through */
 
+_GLOBAL(power7_nap)
         /* NAP is a state loss, we create a regs frame on the
          * stack, fill it up with the state we care about and
          * stick a pointer to it in PACAR1. We really only
diff --git a/arch/powerpc/kernel/iommu.c b/arch/powerpc/kernel/iommu.c
index 359f078571c..ff5a6ce027b 100644
--- a/arch/powerpc/kernel/iommu.c
+++ b/arch/powerpc/kernel/iommu.c
@@ -33,6 +33,9 @@
 #include <linux/bitmap.h>
 #include <linux/iommu-helper.h>
 #include <linux/crash_dump.h>
+#include <linux/hash.h>
+#include <linux/fault-inject.h>
+#include <linux/pci.h>
 #include <asm/io.h>
 #include <asm/prom.h>
 #include <asm/iommu.h>
@@ -40,6 +43,7 @@
 #include <asm/machdep.h>
 #include <asm/kdump.h>
 #include <asm/fadump.h>
+#include <asm/vio.h>
 
 #define DBG(...)
 
@@ -58,6 +62,114 @@ static int __init setup_iommu(char *str)
 
 __setup("iommu=", setup_iommu);
 
+static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
+
+/*
+ * We precalculate the hash to avoid doing it on every allocation.
+ *
+ * The hash is important to spread CPUs across all the pools. For example,
+ * on a POWER7 with 4 way SMT we want interrupts on the primary threads and
+ * with 4 pools all primary threads would map to the same pool.
+ */
+static int __init setup_iommu_pool_hash(void)
+{
+        unsigned int i;
+
+        for_each_possible_cpu(i)
+                per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
+
+        return 0;
+}
+subsys_initcall(setup_iommu_pool_hash);
+
+#ifdef CONFIG_FAIL_IOMMU
+
+static DECLARE_FAULT_ATTR(fail_iommu);
+
+static int __init setup_fail_iommu(char *str)
+{
+        return setup_fault_attr(&fail_iommu, str);
+}
+__setup("fail_iommu=", setup_fail_iommu);
+
+static bool should_fail_iommu(struct device *dev)
+{
+        return dev->archdata.fail_iommu && should_fail(&fail_iommu, 1);
+}
+
+static int __init fail_iommu_debugfs(void)
+{
+        struct dentry *dir = fault_create_debugfs_attr("fail_iommu",
+                                                       NULL, &fail_iommu);
+
+        return IS_ERR(dir) ? PTR_ERR(dir) : 0;
+}
+late_initcall(fail_iommu_debugfs);
+
+static ssize_t fail_iommu_show(struct device *dev,
+                               struct device_attribute *attr, char *buf)
+{
+        return sprintf(buf, "%d\n", dev->archdata.fail_iommu);
+}
+
+static ssize_t fail_iommu_store(struct device *dev,
+                                struct device_attribute *attr, const char *buf,
+                                size_t count)
+{
+        int i;
+
+        if (count > 0 && sscanf(buf, "%d", &i) > 0)
+                dev->archdata.fail_iommu = (i == 0) ? 0 : 1;
+
+        return count;
+}
+
+static DEVICE_ATTR(fail_iommu, S_IRUGO|S_IWUSR, fail_iommu_show,
+                   fail_iommu_store);
+
+static int fail_iommu_bus_notify(struct notifier_block *nb,
+                                 unsigned long action, void *data)
+{
+        struct device *dev = data;
+
+        if (action == BUS_NOTIFY_ADD_DEVICE) {
+                if (device_create_file(dev, &dev_attr_fail_iommu))
+                        pr_warn("Unable to create IOMMU fault injection sysfs "
+                                "entries\n");
+        } else if (action == BUS_NOTIFY_DEL_DEVICE) {
+                device_remove_file(dev, &dev_attr_fail_iommu);
+        }
+
+        return 0;
+}
+
+static struct notifier_block fail_iommu_bus_notifier = {
+        .notifier_call = fail_iommu_bus_notify
+};
+
+static int __init fail_iommu_setup(void)
+{
+#ifdef CONFIG_PCI
+        bus_register_notifier(&pci_bus_type, &fail_iommu_bus_notifier);
+#endif
+#ifdef CONFIG_IBMVIO
+        bus_register_notifier(&vio_bus_type, &fail_iommu_bus_notifier);
+#endif
+
+        return 0;
+}
+/*
+ * Must execute after PCI and VIO subsystem have initialised but before
+ * devices are probed.
+ */
+arch_initcall(fail_iommu_setup);
+#else
+static inline bool should_fail_iommu(struct device *dev)
+{
+        return false;
+}
+#endif
+
 static unsigned long iommu_range_alloc(struct device *dev,
                                        struct iommu_table *tbl,
                                        unsigned long npages,
@@ -71,6 +183,9 @@ static unsigned long iommu_range_alloc(struct device *dev,
         int pass = 0;
         unsigned long align_mask;
         unsigned long boundary_size;
+        unsigned long flags;
+        unsigned int pool_nr;
+        struct iommu_pool *pool;
 
         align_mask = 0xffffffffffffffffl >> (64 - align_order);
 
@@ -83,36 +198,49 @@ static unsigned long iommu_range_alloc(struct device *dev,
                 return DMA_ERROR_CODE;
         }
 
-        if (handle && *handle)
-                start = *handle;
+        if (should_fail_iommu(dev))
+                return DMA_ERROR_CODE;
+
+        /*
+         * We don't need to disable preemption here because any CPU can
+         * safely use any IOMMU pool.
+         */
+        pool_nr = __raw_get_cpu_var(iommu_pool_hash) & (tbl->nr_pools - 1);
+
+        if (largealloc)
+                pool = &(tbl->large_pool);
         else
-                start = largealloc ? tbl->it_largehint : tbl->it_hint;
+                pool = &(tbl->pools[pool_nr]);
 
-        /* Use only half of the table for small allocs (15 pages or less) */
-        limit = largealloc ? tbl->it_size : tbl->it_halfpoint;
+        spin_lock_irqsave(&(pool->lock), flags);
 
-        if (largealloc && start < tbl->it_halfpoint)
-                start = tbl->it_halfpoint;
+again:
+        if ((pass == 0) && handle && *handle)
+                start = *handle;
+        else
+                start = pool->hint;
+
+        limit = pool->end;
 
         /* The case below can happen if we have a small segment appended
          * to a large, or when the previous alloc was at the very end of
          * the available space. If so, go back to the initial start.
          */
         if (start >= limit)
-                start = largealloc ? tbl->it_largehint : tbl->it_hint;
-
- again:
+                start = pool->start;
 
         if (limit + tbl->it_offset > mask) {
                 limit = mask - tbl->it_offset + 1;
                 /* If we're constrained on address range, first try
                  * at the masked hint to avoid O(n) search complexity,
-                 * but on second pass, start at 0.
+                 * but on second pass, start at 0 in pool 0.
                  */
-                if ((start & mask) >= limit || pass > 0)
-                        start = 0;
-                else
+                if ((start & mask) >= limit || pass > 0) {
+                        pool = &(tbl->pools[0]);
+                        start = pool->start;
+                } else {
                         start &= mask;
+                }
         }
 
         if (dev)
@@ -126,16 +254,25 @@ static unsigned long iommu_range_alloc(struct device *dev,
                              tbl->it_offset, boundary_size >> IOMMU_PAGE_SHIFT,
                              align_mask);
         if (n == -1) {
-                if (likely(pass < 2)) {
-                        /* First failure, just rescan the half of the table.
-                         * Second failure, rescan the other half of the table.
-                         */
-                        start = (largealloc ^ pass) ? tbl->it_halfpoint : 0;
-                        limit = pass ? tbl->it_size : limit;
+                if (likely(pass == 0)) {
+                        /* First try the pool from the start */
+                        pool->hint = pool->start;
                         pass++;
                         goto again;
+
+                } else if (pass <= tbl->nr_pools) {
+                        /* Now try scanning all the other pools */
+                        spin_unlock(&(pool->lock));
+                        pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
+                        pool = &tbl->pools[pool_nr];
+                        spin_lock(&(pool->lock));
+                        pool->hint = pool->start;
+                        pass++;
+                        goto again;
+
                 } else {
-                        /* Third failure, give up */
+                        /* Give up */
+                        spin_unlock_irqrestore(&(pool->lock), flags);
                         return DMA_ERROR_CODE;
                 }
         }
@@ -145,10 +282,10 @@ static unsigned long iommu_range_alloc(struct device *dev,
         /* Bump the hint to a new block for small allocs. */
         if (largealloc) {
                 /* Don't bump to new block to avoid fragmentation */
-                tbl->it_largehint = end;
+                pool->hint = end;
         } else {
                 /* Overflow will be taken care of at the next allocation */
-                tbl->it_hint = (end + tbl->it_blocksize - 1) &
+                pool->hint = (end + tbl->it_blocksize - 1) &
                                 ~(tbl->it_blocksize - 1);
         }
 
@@ -156,6 +293,8 @@ static unsigned long iommu_range_alloc(struct device *dev,
         if (handle)
                 *handle = end;
 
+        spin_unlock_irqrestore(&(pool->lock), flags);
+
         return n;
 }
 
@@ -165,18 +304,14 @@ static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
                               unsigned long mask, unsigned int align_order,
                               struct dma_attrs *attrs)
 {
-        unsigned long entry, flags;
+        unsigned long entry;
         dma_addr_t ret = DMA_ERROR_CODE;
         int build_fail;
 
-        spin_lock_irqsave(&(tbl->it_lock), flags);
-
         entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
 
-        if (unlikely(entry == DMA_ERROR_CODE)) {
-                spin_unlock_irqrestore(&(tbl->it_lock), flags);
+        if (unlikely(entry == DMA_ERROR_CODE))
                 return DMA_ERROR_CODE;
-        }
 
         entry += tbl->it_offset;        /* Offset into real TCE table */
         ret = entry << IOMMU_PAGE_SHIFT;        /* Set the return dma address */
@@ -193,8 +328,6 @@ static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
          */
         if (unlikely(build_fail)) {
                 __iommu_free(tbl, ret, npages);
-
-                spin_unlock_irqrestore(&(tbl->it_lock), flags);
                 return DMA_ERROR_CODE;
         }
 
@@ -202,16 +335,14 @@ static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
         if (ppc_md.tce_flush)
                 ppc_md.tce_flush(tbl);
 
-        spin_unlock_irqrestore(&(tbl->it_lock), flags);
-
         /* Make sure updates are seen by hardware */
         mb();
 
         return ret;
 }
 
-static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr, 
-                         unsigned int npages)
+static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
+                             unsigned int npages)
 {
         unsigned long entry, free_entry;
 
@@ -231,20 +362,57 @@ static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
                         printk(KERN_INFO "\tindex     = 0x%llx\n", (u64)tbl->it_index);
                         WARN_ON(1);
                 }
-                return;
+
+                return false;
+        }
+
+        return true;
+}
+
+static struct iommu_pool *get_pool(struct iommu_table *tbl,
+                                   unsigned long entry)
+{
+        struct iommu_pool *p;
+        unsigned long largepool_start = tbl->large_pool.start;
+
+        /* The large pool is the last pool at the top of the table */
+        if (entry >= largepool_start) {
+                p = &tbl->large_pool;
+        } else {
+                unsigned int pool_nr = entry / tbl->poolsize;
+
+                BUG_ON(pool_nr > tbl->nr_pools);
+                p = &tbl->pools[pool_nr];
         }
 
+        return p;
+}
+
+static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
+                         unsigned int npages)
+{
+        unsigned long entry, free_entry;
+        unsigned long flags;
+        struct iommu_pool *pool;
+
+        entry = dma_addr >> IOMMU_PAGE_SHIFT;
+        free_entry = entry - tbl->it_offset;
+
+        pool = get_pool(tbl, free_entry);
+
+        if (!iommu_free_check(tbl, dma_addr, npages))
+                return;
+
         ppc_md.tce_free(tbl, entry, npages);
+
+        spin_lock_irqsave(&(pool->lock), flags);
         bitmap_clear(tbl->it_map, free_entry, npages);
+        spin_unlock_irqrestore(&(pool->lock), flags);
 }
 
 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
                 unsigned int npages)
 {
-        unsigned long flags;
-
-        spin_lock_irqsave(&(tbl->it_lock), flags);
-
         __iommu_free(tbl, dma_addr, npages);
 
         /* Make sure TLB cache is flushed if the HW needs it. We do
@@ -253,8 +421,6 @@ static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
          */
         if (ppc_md.tce_flush)
                 ppc_md.tce_flush(tbl);
-
-        spin_unlock_irqrestore(&(tbl->it_lock), flags);
 }
 
 int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
@@ -263,7 +429,6 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
                  struct dma_attrs *attrs)
 {
         dma_addr_t dma_next = 0, dma_addr;
-        unsigned long flags;
         struct scatterlist *s, *outs, *segstart;
         int outcount, incount, i, build_fail = 0;
         unsigned int align;
@@ -285,8 +450,6 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
 
         DBG("sg mapping %d elements:\n", nelems);
 
-        spin_lock_irqsave(&(tbl->it_lock), flags);
-
         max_seg_size = dma_get_max_seg_size(dev);
         for_each_sg(sglist, s, nelems, i) {
                 unsigned long vaddr, npages, entry, slen;
@@ -369,8 +532,6 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
         if (ppc_md.tce_flush)
                 ppc_md.tce_flush(tbl);
 
-        spin_unlock_irqrestore(&(tbl->it_lock), flags);
-
         DBG("mapped %d elements:\n", outcount);
 
         /* For the sake of iommu_unmap_sg, we clear out the length in the
@@ -402,7 +563,6 @@ int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
                 if (s == outs)
                         break;
         }
-        spin_unlock_irqrestore(&(tbl->it_lock), flags);
         return 0;
 }
 
@@ -412,15 +572,12 @@ void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
                 struct dma_attrs *attrs)
 {
         struct scatterlist *sg;
-        unsigned long flags;
 
         BUG_ON(direction == DMA_NONE);
 
         if (!tbl)
                 return;
 
-        spin_lock_irqsave(&(tbl->it_lock), flags);
-
         sg = sglist;
         while (nelems--) {
                 unsigned int npages;
@@ -440,8 +597,6 @@ void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
          */
         if (ppc_md.tce_flush)
                 ppc_md.tce_flush(tbl);
-
-        spin_unlock_irqrestore(&(tbl->it_lock), flags);
 }
 
 static void iommu_table_clear(struct iommu_table *tbl)
@@ -494,9 +649,8 @@ struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
         unsigned long sz;
         static int welcomed = 0;
         struct page *page;
-
-        /* Set aside 1/4 of the table for large allocations. */
-        tbl->it_halfpoint = tbl->it_size * 3 / 4;
+        unsigned int i;
+        struct iommu_pool *p;
 
         /* number of bytes needed for the bitmap */
         sz = (tbl->it_size + 7) >> 3;
@@ -515,9 +669,28 @@ struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
         if (tbl->it_offset == 0)
                 set_bit(0, tbl->it_map);
 
-        tbl->it_hint = 0;
-        tbl->it_largehint = tbl->it_halfpoint;
-        spin_lock_init(&tbl->it_lock);
+        /* We only split the IOMMU table if we have 1GB or more of space */
+        if ((tbl->it_size << IOMMU_PAGE_SHIFT) >= (1UL * 1024 * 1024 * 1024))
+                tbl->nr_pools = IOMMU_NR_POOLS;
+        else
+                tbl->nr_pools = 1;
+
+        /* We reserve the top 1/4 of the table for large allocations */
+        tbl->poolsize = (tbl->it_size * 3 / 4) / tbl->nr_pools;
+
+        for (i = 0; i < tbl->nr_pools; i++) {
+                p = &tbl->pools[i];
+                spin_lock_init(&(p->lock));
+                p->start = tbl->poolsize * i;
+                p->hint = p->start;
+                p->end = p->start + tbl->poolsize;
+        }
+
+        p = &tbl->large_pool;
+        spin_lock_init(&(p->lock));
+        p->start = tbl->poolsize * i;
+        p->hint = p->start;
+        p->end = tbl->it_size;
 
         iommu_table_clear(tbl);
 
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c
index 782bd0a3c2f..c470a40b29f 100644
--- a/arch/powerpc/kernel/kgdb.c
+++ b/arch/powerpc/kernel/kgdb.c
@@ -25,6 +25,7 @@
 #include <asm/processor.h>
 #include <asm/machdep.h>
 #include <asm/debug.h>
+#include <linux/slab.h>
 
 /*
  * This table contains the mapping between PowerPC hardware trap types, and
@@ -101,6 +102,21 @@ static int computeSignal(unsigned int tt)
         return SIGHUP;          /* default for things we don't know about */
 }
 
+/**
+ *
+ *      kgdb_skipexception - Bail out of KGDB when we've been triggered.
+ *      @exception: Exception vector number
+ *      @regs: Current &struct pt_regs.
+ *
+ *      On some architectures we need to skip a breakpoint exception when
+ *      it occurs after a breakpoint has been removed.
+ *
+ */
+int kgdb_skipexception(int exception, struct pt_regs *regs)
+{
+        return kgdb_isremovedbreak(regs->nip);
+}
+
 static int kgdb_call_nmi_hook(struct pt_regs *regs)
 {
         kgdb_nmicallback(raw_smp_processor_id(), regs);
@@ -138,6 +154,8 @@ static int kgdb_handle_breakpoint(struct pt_regs *regs)
 static int kgdb_singlestep(struct pt_regs *regs)
 {
         struct thread_info *thread_info, *exception_thread_info;
+        struct thread_info *backup_current_thread_info = \
+                (struct thread_info *)kmalloc(sizeof(struct thread_info), GFP_KERNEL);
 
         if (user_mode(regs))
                 return 0;
@@ -155,13 +173,17 @@ static int kgdb_singlestep(struct pt_regs *regs)
         thread_info = (struct thread_info *)(regs->gpr[1] & ~(THREAD_SIZE-1));
         exception_thread_info = current_thread_info();
 
-        if (thread_info != exception_thread_info)
+        if (thread_info != exception_thread_info) {
+                /* Save the original current_thread_info. */
+                memcpy(backup_current_thread_info, exception_thread_info, sizeof *thread_info);
                 memcpy(exception_thread_info, thread_info, sizeof *thread_info);
+        }
 
         kgdb_handle_exception(0, SIGTRAP, 0, regs);
 
         if (thread_info != exception_thread_info)
-                memcpy(thread_info, exception_thread_info, sizeof *thread_info);
+                /* Restore current_thread_info lastly. */
+                memcpy(exception_thread_info, backup_current_thread_info, sizeof *thread_info);
 
         return 1;
 }
@@ -410,7 +432,6 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code,
 #else
                         linux_regs->msr |= MSR_SE;
 #endif
-                        kgdb_single_step = 1;
                         atomic_set(&kgdb_cpu_doing_single_step,
                                    raw_smp_processor_id());
                 }
diff --git a/arch/powerpc/kernel/kvm.c b/arch/powerpc/kernel/kvm.c
index 62bdf238966..867db1de894 100644
--- a/arch/powerpc/kernel/kvm.c
+++ b/arch/powerpc/kernel/kvm.c
@@ -31,6 +31,7 @@
 #include <asm/cacheflush.h>
 #include <asm/disassemble.h>
 #include <asm/ppc-opcode.h>
+#include <asm/epapr_hcalls.h>
 
 #define KVM_MAGIC_PAGE          (-4096L)
 #define magic_var(x) KVM_MAGIC_PAGE + offsetof(struct kvm_vcpu_arch_shared, x)
@@ -302,7 +303,7 @@ static void kvm_patch_ins_wrtee(u32 *inst, u32 rt, int imm_one)
 
         if (imm_one) {
                 p[kvm_emulate_wrtee_reg_offs] =
-                        KVM_INST_LI | __PPC_RT(30) | MSR_EE;
+                        KVM_INST_LI | __PPC_RT(R30) | MSR_EE;
         } else {
                 /* Make clobbered registers work too */
                 switch (get_rt(rt)) {
@@ -726,7 +727,7 @@ unsigned long kvm_hypercall(unsigned long *in,
         unsigned long register r11 asm("r11") = nr;
         unsigned long register r12 asm("r12");
 
-        asm volatile("bl        kvm_hypercall_start"
+        asm volatile("bl        epapr_hypercall_start"
                      : "=r"(r0), "=r"(r3), "=r"(r4), "=r"(r5), "=r"(r6),
                        "=r"(r7), "=r"(r8), "=r"(r9), "=r"(r10), "=r"(r11),
                        "=r"(r12)
@@ -747,29 +748,6 @@ unsigned long kvm_hypercall(unsigned long *in,
 }
 EXPORT_SYMBOL_GPL(kvm_hypercall);
 
-static int kvm_para_setup(void)
-{
-        extern u32 kvm_hypercall_start;
-        struct device_node *hyper_node;
-        u32 *insts;
-        int len, i;
-
-        hyper_node = of_find_node_by_path("/hypervisor");
-        if (!hyper_node)
-                return -1;
-
-        insts = (u32*)of_get_property(hyper_node, "hcall-instructions", &len);
-        if (len % 4)
-                return -1;
-        if (len > (4 * 4))
-                return -1;
-
-        for (i = 0; i < (len / 4); i++)
-                kvm_patch_ins(&(&kvm_hypercall_start)[i], insts[i]);
-
-        return 0;
-}
-
 static __init void kvm_free_tmp(void)
 {
         unsigned long start, end;
@@ -791,7 +769,7 @@ static int __init kvm_guest_init(void)
         if (!kvm_para_available())
                 goto free_tmp;
 
-        if (kvm_para_setup())
+        if (!epapr_paravirt_enabled)
                 goto free_tmp;
 
         if (kvm_para_has_feature(KVM_FEATURE_MAGIC_PAGE))
diff --git a/arch/powerpc/kernel/kvm_emul.S b/arch/powerpc/kernel/kvm_emul.S
index e291cf3cf95..e100ff324a8 100644
--- a/arch/powerpc/kernel/kvm_emul.S
+++ b/arch/powerpc/kernel/kvm_emul.S
@@ -24,16 +24,6 @@
 #include <asm/page.h>
 #include <asm/asm-offsets.h>
 
-/* Hypercall entry point. Will be patched with device tree instructions. */
-
-.global kvm_hypercall_start
-kvm_hypercall_start:
-        li      r3, -1
-        nop
-        nop
-        nop
-        blr
-
 #define KVM_MAGIC_PAGE          (-4096)
 
 #ifdef CONFIG_64BIT
@@ -132,7 +122,7 @@ kvm_emulate_mtmsrd_len:
         .long (kvm_emulate_mtmsrd_end - kvm_emulate_mtmsrd) / 4
 
 
-#define MSR_SAFE_BITS (MSR_EE | MSR_CE | MSR_ME | MSR_RI)
+#define MSR_SAFE_BITS (MSR_EE | MSR_RI)
 #define MSR_CRITICAL_BITS ~MSR_SAFE_BITS
 
 .global kvm_emulate_mtmsr
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 386d57f66f2..407e293aad2 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -179,7 +179,7 @@ _GLOBAL(low_choose_750fx_pll)
         mtspr   SPRN_HID1,r4
 
         /* Store new HID1 image */
-        rlwinm  r6,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r6, r1)
         lwz     r6,TI_CPU(r6)
         slwi    r6,r6,2
         addis   r6,r6,nap_save_hid1@ha
@@ -699,7 +699,7 @@ _GLOBAL(kernel_thread)
 #ifdef CONFIG_SMP
 _GLOBAL(start_secondary_resume)
         /* Reset stack */
-        rlwinm  r1,r1,0,0,(31-THREAD_SHIFT)     /* current_thread_info() */
+        CURRENT_THREAD_INFO(r1, r1)
         addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
         li      r3,0
         stw     r3,0(r1)                /* Zero the stack frame pointer */
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 616921ef143..565b78625a3 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -301,11 +301,6 @@ _GLOBAL(real_writeb)
 
 #ifdef CONFIG_PPC_PASEMI
 
-/* No support in all binutils for these yet, so use defines */
-#define LBZCIX(RT,RA,RB)  .long (0x7c0006aa|(RT<<21)|(RA<<16)|(RB << 11))
-#define STBCIX(RS,RA,RB)  .long (0x7c0007aa|(RS<<21)|(RA<<16)|(RB << 11))
-
-
 _GLOBAL(real_205_readb)
         mfmsr   r7
         ori     r0,r7,MSR_DR
@@ -314,7 +309,7 @@ _GLOBAL(real_205_readb)
         mtmsrd  r0
         sync
         isync
-        LBZCIX(r3,0,r3)
+        LBZCIX(R3,R0,R3)
         isync
         mtmsrd  r7
         sync
@@ -329,7 +324,7 @@ _GLOBAL(real_205_writeb)
         mtmsrd  r0
         sync
         isync
-        STBCIX(r3,0,r4)
+        STBCIX(R3,R0,R4)
         isync
         mtmsrd  r7
         sync
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 8e78e93c818..2aa04f29e1d 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -200,11 +200,6 @@ int pcibios_add_platform_entries(struct pci_dev *pdev)
         return device_create_file(&pdev->dev, &dev_attr_devspec);
 }
 
-char __devinit *pcibios_setup(char *str)
-{
-        return str;
-}
-
 /*
  * Reads the interrupt pin to determine if interrupt is use by card.
  * If the interrupt is used, then gets the interrupt line from the
@@ -248,8 +243,7 @@ static int pci_read_irq_line(struct pci_dev *pci_dev)
         } else {
                 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
                          oirq.size, oirq.specifier[0], oirq.specifier[1],
-                         oirq.controller ? oirq.controller->full_name :
-                         "<default>");
+                         of_node_full_name(oirq.controller));
 
                 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
                                              oirq.size);
@@ -1628,8 +1622,7 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
         struct device_node *node = hose->dn;
         int mode;
 
-        pr_debug("PCI: Scanning PHB %s\n",
-                 node ? node->full_name : "<NO NAME>");
+        pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
 
         /* Get some IO space for the new PHB */
         pcibios_setup_phb_io_space(hose);
@@ -1637,6 +1630,11 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
         /* Wire up PHB bus resources */
         pcibios_setup_phb_resources(hose, &resources);
 
+        hose->busn.start = hose->first_busno;
+        hose->busn.end   = hose->last_busno;
+        hose->busn.flags = IORESOURCE_BUS;
+        pci_add_resource(&resources, &hose->busn);
+
         /* Create an empty bus for the toplevel */
         bus = pci_create_root_bus(hose->parent, hose->first_busno,
                                   hose->ops, hose, &resources);
@@ -1646,7 +1644,6 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
                 pci_free_resource_list(&resources);
                 return;
         }
-        bus->secondary = hose->first_busno;
         hose->bus = bus;
 
         /* Get probe mode and perform scan */
@@ -1654,13 +1651,14 @@ void __devinit pcibios_scan_phb(struct pci_controller *hose)
         if (node && ppc_md.pci_probe_mode)
                 mode = ppc_md.pci_probe_mode(bus);
         pr_debug("    probe mode: %d\n", mode);
-        if (mode == PCI_PROBE_DEVTREE) {
-                bus->subordinate = hose->last_busno;
+        if (mode == PCI_PROBE_DEVTREE)
                 of_scan_bus(node, bus);
-        }
 
-        if (mode == PCI_PROBE_NORMAL)
-                hose->last_busno = bus->subordinate = pci_scan_child_bus(bus);
+        if (mode == PCI_PROBE_NORMAL) {
+                pci_bus_update_busn_res_end(bus, 255);
+                hose->last_busno = pci_scan_child_bus(bus);
+                pci_bus_update_busn_res_end(bus, hose->last_busno);
+        }
 
         /* Platform gets a chance to do some global fixups before
          * we proceed to resource allocation
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 94a54f61d34..4ff190ff24a 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -236,7 +236,7 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus,
 
         for (ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
                 bus = pci_bus_b(ln);
-                if (in_bus >= bus->number && in_bus <= bus->subordinate)
+                if (in_bus >= bus->number && in_bus <= bus->busn_res.end)
                         break;
                 bus = NULL;
         }
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index 89dde171a6f..30378a19f65 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -198,7 +198,6 @@ EXPORT_SYMBOL(of_create_pci_dev);
 
 /**
  * of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
- * @node: device tree node of bridge
  * @dev: pci_dev structure for the bridge
  *
  * of_scan_bus() calls this routine for each PCI bridge that it finds, and
@@ -240,7 +239,7 @@ void __devinit of_scan_pci_bridge(struct pci_dev *dev)
         }
 
         bus->primary = dev->bus->number;
-        bus->subordinate = busrange[1];
+        pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
         bus->bridge_ctl = 0;
 
         /* parse ranges property */
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 710f400476d..1a1f2ddfb58 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -802,16 +802,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
 #endif /* CONFIG_PPC_STD_MMU_64 */
 #ifdef CONFIG_PPC64 
         if (cpu_has_feature(CPU_FTR_DSCR)) {
-                if (current->thread.dscr_inherit) {
-                        p->thread.dscr_inherit = 1;
-                        p->thread.dscr = current->thread.dscr;
-                } else if (0 != dscr_default) {
-                        p->thread.dscr_inherit = 1;
-                        p->thread.dscr = dscr_default;
-                } else {
-                        p->thread.dscr_inherit = 0;
-                        p->thread.dscr = 0;
-                }
+                p->thread.dscr_inherit = current->thread.dscr_inherit;
+                p->thread.dscr = current->thread.dscr;
         }
 #endif
 
diff --git a/arch/powerpc/kernel/rtas_flash.c b/arch/powerpc/kernel/rtas_flash.c
index 4174b4b2324..2c0ee640563 100644
--- a/arch/powerpc/kernel/rtas_flash.c
+++ b/arch/powerpc/kernel/rtas_flash.c
@@ -709,7 +709,7 @@ static int __init rtas_flash_init(void)
 
         if (rtas_token("ibm,update-flash-64-and-reboot") ==
                        RTAS_UNKNOWN_SERVICE) {
-                printk(KERN_ERR "rtas_flash: no firmware flash support\n");
+                pr_info("rtas_flash: no firmware flash support\n");
                 return 1;
         }
 
diff --git a/arch/powerpc/kernel/setup-common.c b/arch/powerpc/kernel/setup-common.c
index afd4f051f3f..bdc499c1787 100644
--- a/arch/powerpc/kernel/setup-common.c
+++ b/arch/powerpc/kernel/setup-common.c
@@ -720,6 +720,33 @@ static int powerpc_debugfs_init(void)
 arch_initcall(powerpc_debugfs_init);
 #endif
 
+#ifdef CONFIG_BOOKE_WDT
+extern u32 booke_wdt_enabled;
+extern u32 booke_wdt_period;
+
+/* Checks wdt=x and wdt_period=xx command-line option */
+notrace int __init early_parse_wdt(char *p)
+{
+        if (p && strncmp(p, "0", 1) != 0)
+                booke_wdt_enabled = 1;
+
+        return 0;
+}
+early_param("wdt", early_parse_wdt);
+
+int __init early_parse_wdt_period(char *p)
+{
+        unsigned long ret;
+        if (p) {
+                if (!kstrtol(p, 0, &ret))
+                        booke_wdt_period = ret;
+        }
+
+        return 0;
+}
+early_param("wdt_period", early_parse_wdt_period);
+#endif  /* CONFIG_BOOKE_WDT */
+
 void ppc_printk_progress(char *s, unsigned short hex)
 {
         pr_info("%s\n", s);
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index ec8a53fa9e8..a8f54ecb091 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -149,30 +149,6 @@ notrace void __init machine_init(u64 dt_ptr)
                 ppc_md.progress("id mach(): done", 0x200);
 }
 
-#ifdef CONFIG_BOOKE_WDT
-extern u32 booke_wdt_enabled;
-extern u32 booke_wdt_period;
-
-/* Checks wdt=x and wdt_period=xx command-line option */
-notrace int __init early_parse_wdt(char *p)
-{
-        if (p && strncmp(p, "0", 1) != 0)
-               booke_wdt_enabled = 1;
-
-        return 0;
-}
-early_param("wdt", early_parse_wdt);
-
-int __init early_parse_wdt_period (char *p)
-{
-        if (p)
-                booke_wdt_period = simple_strtoul(p, NULL, 0);
-
-        return 0;
-}
-early_param("wdt_period", early_parse_wdt_period);
-#endif  /* CONFIG_BOOKE_WDT */
-
 /* Checks "l2cr=xxxx" command-line option */
 int __init ppc_setup_l2cr(char *str)
 {
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index e4cb34322de..8d4214afc21 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -48,6 +48,7 @@
 #ifdef CONFIG_PPC64
 #include <asm/paca.h>
 #endif
+#include <asm/vdso.h>
 #include <asm/debug.h>
 
 #ifdef DEBUG
@@ -197,8 +198,15 @@ void smp_muxed_ipi_message_pass(int cpu, int msg)
         struct cpu_messages *info = &per_cpu(ipi_message, cpu);
         char *message = (char *)&info->messages;
 
+        /*
+         * Order previous accesses before accesses in the IPI handler.
+         */
+        smp_mb();
         message[msg] = 1;
-        mb();
+        /*
+         * cause_ipi functions are required to include a full barrier
+         * before doing whatever causes the IPI.
+         */
         smp_ops->cause_ipi(cpu, info->data);
 }
 
@@ -210,7 +218,7 @@ irqreturn_t smp_ipi_demux(void)
         mb();   /* order any irq clear */
 
         do {
-                all = xchg_local(&info->messages, 0);
+                all = xchg(&info->messages, 0);
 
 #ifdef __BIG_ENDIAN
                 if (all & (1 << (24 - 8 * PPC_MSG_CALL_FUNCTION)))
@@ -570,8 +578,9 @@ void __devinit start_secondary(void *unused)
 #ifdef CONFIG_PPC64
         if (system_state == SYSTEM_RUNNING)
                 vdso_data->processorCount++;
+
+        vdso_getcpu_init();
 #endif
-        ipi_call_lock();
         notify_cpu_starting(cpu);
         set_cpu_online(cpu, true);
         /* Update sibling maps */
@@ -601,7 +610,6 @@ void __devinit start_secondary(void *unused)
                 of_node_put(np);
         }
         of_node_put(l2_cache);
-        ipi_call_unlock();
 
         local_irq_enable();
 
diff --git a/arch/powerpc/kernel/syscalls.c b/arch/powerpc/kernel/syscalls.c
index f2496f2faec..4e3cc47f26b 100644
--- a/arch/powerpc/kernel/syscalls.c
+++ b/arch/powerpc/kernel/syscalls.c
@@ -107,11 +107,11 @@ long ppc64_personality(unsigned long personality)
         long ret;
 
         if (personality(current->personality) == PER_LINUX32
-            && personality == PER_LINUX)
-                personality = PER_LINUX32;
+            && personality(personality) == PER_LINUX)
+                personality = (personality & ~PER_MASK) | PER_LINUX32;
         ret = sys_personality(personality);
-        if (ret == PER_LINUX32)
-                ret = PER_LINUX;
+        if (personality(ret) == PER_LINUX32)
+                ret = (ret & ~PER_MASK) | PER_LINUX;
         return ret;
 }
 #endif
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 3529446c2ab..8302af64921 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -194,6 +194,14 @@ static ssize_t show_dscr_default(struct device *dev,
         return sprintf(buf, "%lx\n", dscr_default);
 }
 
+static void update_dscr(void *dummy)
+{
+        if (!current->thread.dscr_inherit) {
+                current->thread.dscr = dscr_default;
+                mtspr(SPRN_DSCR, dscr_default);
+        }
+}
+
 static ssize_t __used store_dscr_default(struct device *dev,
                 struct device_attribute *attr, const char *buf,
                 size_t count)
@@ -206,6 +214,8 @@ static ssize_t __used store_dscr_default(struct device *dev,
                 return -EINVAL;
         dscr_default = val;
 
+        on_each_cpu(update_dscr, NULL, 1);
+
         return count;
 }
 
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index be171ee73bf..e49e93191b6 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -535,6 +535,15 @@ void timer_interrupt(struct pt_regs * regs)
         trace_timer_interrupt_exit(regs);
 }
 
+/*
+ * Hypervisor decrementer interrupts shouldn't occur but are sometimes
+ * left pending on exit from a KVM guest.  We don't need to do anything
+ * to clear them, as they are edge-triggered.
+ */
+void hdec_interrupt(struct pt_regs *regs)
+{
+}
+
 #ifdef CONFIG_SUSPEND
 static void generic_suspend_disable_irqs(void)
 {
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 158972341a2..ae0843fa7a6 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -972,8 +972,9 @@ static int emulate_instruction(struct pt_regs *regs)
                         cpu_has_feature(CPU_FTR_DSCR)) {
                 PPC_WARN_EMULATED(mtdscr, regs);
                 rd = (instword >> 21) & 0x1f;
-                mtspr(SPRN_DSCR, regs->gpr[rd]);
+                current->thread.dscr = regs->gpr[rd];
                 current->thread.dscr_inherit = 1;
+                mtspr(SPRN_DSCR, current->thread.dscr);
                 return 0;
         }
 #endif
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c
index 9eb5b9b536a..b67db22e102 100644
--- a/arch/powerpc/kernel/vdso.c
+++ b/arch/powerpc/kernel/vdso.c
@@ -706,6 +706,34 @@ static void __init vdso_setup_syscall_map(void)
         }
 }
 
+#ifdef CONFIG_PPC64
+int __cpuinit vdso_getcpu_init(void)
+{
+        unsigned long cpu, node, val;
+
+        /*
+         * SPRG3 contains the CPU in the bottom 16 bits and the NUMA node in
+         * the next 16 bits. The VDSO uses this to implement getcpu().
+         */
+        cpu = get_cpu();
+        WARN_ON_ONCE(cpu > 0xffff);
+
+        node = cpu_to_node(cpu);
+        WARN_ON_ONCE(node > 0xffff);
+
+        val = (cpu & 0xfff) | ((node & 0xffff) << 16);
+        mtspr(SPRN_SPRG3, val);
+#ifdef CONFIG_KVM_BOOK3S_HANDLER
+        get_paca()->kvm_hstate.sprg3 = val;
+#endif
+
+        put_cpu();
+
+        return 0;
+}
+/* We need to call this before SMP init */
+early_initcall(vdso_getcpu_init);
+#endif
 
 static int __init vdso_init(void)
 {
diff --git a/arch/powerpc/kernel/vdso32/Makefile b/arch/powerpc/kernel/vdso32/Makefile
index 9a7946c4173..53e6c9b979e 100644
--- a/arch/powerpc/kernel/vdso32/Makefile
+++ b/arch/powerpc/kernel/vdso32/Makefile
@@ -1,7 +1,9 @@
 
 # List of files in the vdso, has to be asm only for now
 
-obj-vdso32 = sigtramp.o gettimeofday.o datapage.o cacheflush.o note.o
+obj-vdso32-$(CONFIG_PPC64) = getcpu.o
+obj-vdso32 = sigtramp.o gettimeofday.o datapage.o cacheflush.o note.o \
+                $(obj-vdso32-y)
 
 # Build rules
 
diff --git a/arch/powerpc/kernel/vdso32/getcpu.S b/arch/powerpc/kernel/vdso32/getcpu.S
new file mode 100644
index 00000000000..47afd08c90f
--- /dev/null
+++ b/arch/powerpc/kernel/vdso32/getcpu.S
@@ -0,0 +1,45 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2012
+ *
+ * Author: Anton Blanchard <anton@au.ibm.com>
+ */
+#include <asm/ppc_asm.h>
+#include <asm/vdso.h>
+
+        .text
+/*
+ * Exact prototype of getcpu
+ *
+ * int __kernel_getcpu(unsigned *cpu, unsigned *node);
+ *
+ */
+V_FUNCTION_BEGIN(__kernel_getcpu)
+  .cfi_startproc
+        mfspr   r5,SPRN_USPRG3
+        cmpdi   cr0,r3,0
+        cmpdi   cr1,r4,0
+        clrlwi  r6,r5,16
+        rlwinm  r7,r5,16,31-15,31-0
+        beq     cr0,1f
+        stw     r6,0(r3)
+1:      beq     cr1,2f
+        stw     r7,0(r4)
+2:      crclr   cr0*4+so
+        li      r3,0                    /* always success */
+        blr
+  .cfi_endproc
+V_FUNCTION_END(__kernel_getcpu)
diff --git a/arch/powerpc/kernel/vdso32/vdso32.lds.S b/arch/powerpc/kernel/vdso32/vdso32.lds.S
index 0546bcd49cd..43200ba2e57 100644
--- a/arch/powerpc/kernel/vdso32/vdso32.lds.S
+++ b/arch/powerpc/kernel/vdso32/vdso32.lds.S
@@ -147,6 +147,9 @@ VERSION
                 __kernel_sync_dicache_p5;
                 __kernel_sigtramp32;
                 __kernel_sigtramp_rt32;
+#ifdef CONFIG_PPC64
+                __kernel_getcpu;
+#endif
 
         local: *;
         };
diff --git a/arch/powerpc/kernel/vdso64/Makefile b/arch/powerpc/kernel/vdso64/Makefile
index 8c500d8622e..effca9404b1 100644
--- a/arch/powerpc/kernel/vdso64/Makefile
+++ b/arch/powerpc/kernel/vdso64/Makefile
@@ -1,6 +1,6 @@
 # List of files in the vdso, has to be asm only for now
 
-obj-vdso64 = sigtramp.o gettimeofday.o datapage.o cacheflush.o note.o
+obj-vdso64 = sigtramp.o gettimeofday.o datapage.o cacheflush.o note.o getcpu.o
 
 # Build rules
 
diff --git a/arch/powerpc/kernel/vdso64/getcpu.S b/arch/powerpc/kernel/vdso64/getcpu.S
new file mode 100644
index 00000000000..47afd08c90f
--- /dev/null
+++ b/arch/powerpc/kernel/vdso64/getcpu.S
@@ -0,0 +1,45 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2012
+ *
+ * Author: Anton Blanchard <anton@au.ibm.com>
+ */
+#include <asm/ppc_asm.h>
+#include <asm/vdso.h>
+
+        .text
+/*
+ * Exact prototype of getcpu
+ *
+ * int __kernel_getcpu(unsigned *cpu, unsigned *node);
+ *
+ */
+V_FUNCTION_BEGIN(__kernel_getcpu)
+  .cfi_startproc
+        mfspr   r5,SPRN_USPRG3
+        cmpdi   cr0,r3,0
+        cmpdi   cr1,r4,0
+        clrlwi  r6,r5,16
+        rlwinm  r7,r5,16,31-15,31-0
+        beq     cr0,1f
+        stw     r6,0(r3)
+1:      beq     cr1,2f
+        stw     r7,0(r4)
+2:      crclr   cr0*4+so
+        li      r3,0                    /* always success */
+        blr
+  .cfi_endproc
+V_FUNCTION_END(__kernel_getcpu)
diff --git a/arch/powerpc/kernel/vdso64/vdso64.lds.S b/arch/powerpc/kernel/vdso64/vdso64.lds.S
index 0e615404e24..e6c1758f358 100644
--- a/arch/powerpc/kernel/vdso64/vdso64.lds.S
+++ b/arch/powerpc/kernel/vdso64/vdso64.lds.S
@@ -146,6 +146,7 @@ VERSION
                 __kernel_sync_dicache;
                 __kernel_sync_dicache_p5;
                 __kernel_sigtramp_rt64;
+                __kernel_getcpu;
 
         local: *;
         };
diff --git a/arch/powerpc/kernel/vio.c b/arch/powerpc/kernel/vio.c
index cb87301ccd5..02b32216bbc 100644
--- a/arch/powerpc/kernel/vio.c
+++ b/arch/powerpc/kernel/vio.c
@@ -37,8 +37,6 @@
 #include <asm/page.h>
 #include <asm/hvcall.h>
 
-static struct bus_type vio_bus_type;
-
 static struct vio_dev vio_bus_device  = { /* fake "parent" device */
         .name = "vio",
         .type = "",
@@ -613,6 +611,7 @@ static u64 vio_dma_get_required_mask(struct device *dev)
 struct dma_map_ops vio_dma_mapping_ops = {
         .alloc             = vio_dma_iommu_alloc_coherent,
         .free              = vio_dma_iommu_free_coherent,
+        .mmap              = dma_direct_mmap_coherent,
         .map_sg            = vio_dma_iommu_map_sg,
         .unmap_sg          = vio_dma_iommu_unmap_sg,
         .map_page          = vio_dma_iommu_map_page,
@@ -625,7 +624,7 @@ struct dma_map_ops vio_dma_mapping_ops = {
  * vio_cmo_set_dev_desired - Set desired entitlement for a device
  *
  * @viodev: struct vio_dev for device to alter
- * @new_desired: new desired entitlement level in bytes
+ * @desired: new desired entitlement level in bytes
  *
  * For use by devices to request a change to their entitlement at runtime or
  * through sysfs.  The desired entitlement level is changed and a balancing
@@ -1262,7 +1261,7 @@ static int vio_bus_remove(struct device *dev)
 
 /**
  * vio_register_driver: - Register a new vio driver
- * @drv:        The vio_driver structure to be registered.
+ * @viodrv:     The vio_driver structure to be registered.
  */
 int __vio_register_driver(struct vio_driver *viodrv, struct module *owner,
                           const char *mod_name)
@@ -1282,7 +1281,7 @@ EXPORT_SYMBOL(__vio_register_driver);
 
 /**
  * vio_unregister_driver - Remove registration of vio driver.
- * @driver:     The vio_driver struct to be removed form registration
+ * @viodrv:     The vio_driver struct to be removed form registration
  */
 void vio_unregister_driver(struct vio_driver *viodrv)
 {
@@ -1296,8 +1295,7 @@ static void __devinit vio_dev_release(struct device *dev)
         struct iommu_table *tbl = get_iommu_table_base(dev);
 
         if (tbl)
-                iommu_free_table(tbl, dev->of_node ?
-                        dev->of_node->full_name : dev_name(dev));
+                iommu_free_table(tbl, of_node_full_name(dev->of_node));
         of_node_put(dev->of_node);
         kfree(to_vio_dev(dev));
 }
@@ -1397,21 +1395,27 @@ struct vio_dev *vio_register_device_node(struct device_node *of_node)
         viodev->name = of_node->name;
         viodev->dev.of_node = of_node_get(of_node);
 
-        if (firmware_has_feature(FW_FEATURE_CMO))
-                vio_cmo_set_dma_ops(viodev);
-        else
-                set_dma_ops(&viodev->dev, &dma_iommu_ops);
-        set_iommu_table_base(&viodev->dev, vio_build_iommu_table(viodev));
         set_dev_node(&viodev->dev, of_node_to_nid(of_node));
 
         /* init generic 'struct device' fields: */
         viodev->dev.parent = &vio_bus_device.dev;
         viodev->dev.bus = &vio_bus_type;
         viodev->dev.release = vio_dev_release;
-        /* needed to ensure proper operation of coherent allocations
-         * later, in case driver doesn't set it explicitly */
-        dma_set_mask(&viodev->dev, DMA_BIT_MASK(64));
-        dma_set_coherent_mask(&viodev->dev, DMA_BIT_MASK(64));
+
+        if (of_get_property(viodev->dev.of_node, "ibm,my-dma-window", NULL)) {
+                if (firmware_has_feature(FW_FEATURE_CMO))
+                        vio_cmo_set_dma_ops(viodev);
+                else
+                        set_dma_ops(&viodev->dev, &dma_iommu_ops);
+
+                set_iommu_table_base(&viodev->dev,
+                                     vio_build_iommu_table(viodev));
+
+                /* needed to ensure proper operation of coherent allocations
+                 * later, in case driver doesn't set it explicitly */
+                dma_set_mask(&viodev->dev, DMA_BIT_MASK(64));
+                dma_set_coherent_mask(&viodev->dev, DMA_BIT_MASK(64));
+        }
 
         /* register with generic device framework */
         if (device_register(&viodev->dev)) {
@@ -1491,12 +1495,18 @@ static int __init vio_bus_init(void)
         if (firmware_has_feature(FW_FEATURE_CMO))
                 vio_cmo_bus_init();
 
+        return 0;
+}
+postcore_initcall(vio_bus_init);
+
+static int __init vio_device_init(void)
+{
         vio_bus_scan_register_devices("vdevice");
         vio_bus_scan_register_devices("ibm,platform-facilities");
 
         return 0;
 }
-__initcall(vio_bus_init);
+device_initcall(vio_device_init);
 
 static ssize_t name_show(struct device *dev,
                 struct device_attribute *attr, char *buf)
@@ -1509,7 +1519,7 @@ static ssize_t devspec_show(struct device *dev,
 {
         struct device_node *of_node = dev->of_node;
 
-        return sprintf(buf, "%s\n", of_node ? of_node->full_name : "none");
+        return sprintf(buf, "%s\n", of_node_full_name(of_node));
 }
 
 static ssize_t modalias_show(struct device *dev, struct device_attribute *attr,
@@ -1568,7 +1578,7 @@ static int vio_hotplug(struct device *dev, struct kobj_uevent_env *env)
         return 0;
 }
 
-static struct bus_type vio_bus_type = {
+struct bus_type vio_bus_type = {
         .name = "vio",
         .dev_attrs = vio_dev_attrs,
         .uevent = vio_hotplug,
diff --git a/arch/powerpc/kvm/book3s_32_mmu_host.c b/arch/powerpc/kvm/book3s_32_mmu_host.c
index f922c29bb23..837f13e7b6b 100644
--- a/arch/powerpc/kvm/book3s_32_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_32_mmu_host.c
@@ -211,6 +211,9 @@ next_pteg:
                 pteg1 |= PP_RWRX;
         }
 
+        if (orig_pte->may_execute)
+                kvmppc_mmu_flush_icache(hpaddr >> PAGE_SHIFT);
+
         local_irq_disable();
 
         if (pteg[rr]) {
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
index 10fc8ec9d2a..0688b6b3958 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -126,6 +126,8 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
 
         if (!orig_pte->may_execute)
                 rflags |= HPTE_R_N;
+        else
+                kvmppc_mmu_flush_icache(hpaddr >> PAGE_SHIFT);
 
         hash = hpt_hash(va, PTE_SIZE, MMU_SEGSIZE_256M);
 
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index 80a57751758..d03eb6f7b05 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -37,56 +37,121 @@
 /* POWER7 has 10-bit LPIDs, PPC970 has 6-bit LPIDs */
 #define MAX_LPID_970    63
 
-long kvmppc_alloc_hpt(struct kvm *kvm)
+/* Power architecture requires HPT is at least 256kB */
+#define PPC_MIN_HPT_ORDER       18
+
+long kvmppc_alloc_hpt(struct kvm *kvm, u32 *htab_orderp)
 {
         unsigned long hpt;
-        long lpid;
         struct revmap_entry *rev;
         struct kvmppc_linear_info *li;
+        long order = kvm_hpt_order;
 
-        /* Allocate guest's hashed page table */
-        li = kvm_alloc_hpt();
-        if (li) {
-                /* using preallocated memory */
-                hpt = (ulong)li->base_virt;
-                kvm->arch.hpt_li = li;
-        } else {
-                /* using dynamic memory */
+        if (htab_orderp) {
+                order = *htab_orderp;
+                if (order < PPC_MIN_HPT_ORDER)
+                        order = PPC_MIN_HPT_ORDER;
+        }
+
+        /*
+         * If the user wants a different size from default,
+         * try first to allocate it from the kernel page allocator.
+         */
+        hpt = 0;
+        if (order != kvm_hpt_order) {
                 hpt = __get_free_pages(GFP_KERNEL|__GFP_ZERO|__GFP_REPEAT|
-                                       __GFP_NOWARN, HPT_ORDER - PAGE_SHIFT);
+                                       __GFP_NOWARN, order - PAGE_SHIFT);
+                if (!hpt)
+                        --order;
         }
 
+        /* Next try to allocate from the preallocated pool */
         if (!hpt) {
-                pr_err("kvm_alloc_hpt: Couldn't alloc HPT\n");
-                return -ENOMEM;
+                li = kvm_alloc_hpt();
+                if (li) {
+                        hpt = (ulong)li->base_virt;
+                        kvm->arch.hpt_li = li;
+                        order = kvm_hpt_order;
+                }
         }
+
+        /* Lastly try successively smaller sizes from the page allocator */
+        while (!hpt && order > PPC_MIN_HPT_ORDER) {
+                hpt = __get_free_pages(GFP_KERNEL|__GFP_ZERO|__GFP_REPEAT|
+                                       __GFP_NOWARN, order - PAGE_SHIFT);
+                if (!hpt)
+                        --order;
+        }
+
+        if (!hpt)
+                return -ENOMEM;
+
         kvm->arch.hpt_virt = hpt;
+        kvm->arch.hpt_order = order;
+        /* HPTEs are 2**4 bytes long */
+        kvm->arch.hpt_npte = 1ul << (order - 4);
+        /* 128 (2**7) bytes in each HPTEG */
+        kvm->arch.hpt_mask = (1ul << (order - 7)) - 1;
 
         /* Allocate reverse map array */
-        rev = vmalloc(sizeof(struct revmap_entry) * HPT_NPTE);
+        rev = vmalloc(sizeof(struct revmap_entry) * kvm->arch.hpt_npte);
         if (!rev) {
                 pr_err("kvmppc_alloc_hpt: Couldn't alloc reverse map array\n");
                 goto out_freehpt;
         }
         kvm->arch.revmap = rev;
+        kvm->arch.sdr1 = __pa(hpt) | (order - 18);
 
-        lpid = kvmppc_alloc_lpid();
-        if (lpid < 0)
-                goto out_freeboth;
+        pr_info("KVM guest htab at %lx (order %ld), LPID %x\n",
+                hpt, order, kvm->arch.lpid);
 
-        kvm->arch.sdr1 = __pa(hpt) | (HPT_ORDER - 18);
-        kvm->arch.lpid = lpid;
-
-        pr_info("KVM guest htab at %lx, LPID %lx\n", hpt, lpid);
+        if (htab_orderp)
+                *htab_orderp = order;
         return 0;
 
- out_freeboth:
-        vfree(rev);
  out_freehpt:
-        free_pages(hpt, HPT_ORDER - PAGE_SHIFT);
+        if (kvm->arch.hpt_li)
+                kvm_release_hpt(kvm->arch.hpt_li);
+        else
+                free_pages(hpt, order - PAGE_SHIFT);
         return -ENOMEM;
 }
 
+long kvmppc_alloc_reset_hpt(struct kvm *kvm, u32 *htab_orderp)
+{
+        long err = -EBUSY;
+        long order;
+
+        mutex_lock(&kvm->lock);
+        if (kvm->arch.rma_setup_done) {
+                kvm->arch.rma_setup_done = 0;
+                /* order rma_setup_done vs. vcpus_running */
+                smp_mb();
+                if (atomic_read(&kvm->arch.vcpus_running)) {
+                        kvm->arch.rma_setup_done = 1;
+                        goto out;
+                }
+        }
+        if (kvm->arch.hpt_virt) {
+                order = kvm->arch.hpt_order;
+                /* Set the entire HPT to 0, i.e. invalid HPTEs */
+                memset((void *)kvm->arch.hpt_virt, 0, 1ul << order);
+                /*
+                 * Set the whole last_vcpu array to an invalid vcpu number.
+                 * This ensures that each vcpu will flush its TLB on next entry.
+                 */
+                memset(kvm->arch.last_vcpu, 0xff, sizeof(kvm->arch.last_vcpu));
+                *htab_orderp = order;
+                err = 0;
+        } else {
+                err = kvmppc_alloc_hpt(kvm, htab_orderp);
+                order = *htab_orderp;
+        }
+ out:
+        mutex_unlock(&kvm->lock);
+        return err;
+}
+
 void kvmppc_free_hpt(struct kvm *kvm)
 {
         kvmppc_free_lpid(kvm->arch.lpid);
@@ -94,7 +159,8 @@ void kvmppc_free_hpt(struct kvm *kvm)
         if (kvm->arch.hpt_li)
                 kvm_release_hpt(kvm->arch.hpt_li);
         else
-                free_pages(kvm->arch.hpt_virt, HPT_ORDER - PAGE_SHIFT);
+                free_pages(kvm->arch.hpt_virt,
+                           kvm->arch.hpt_order - PAGE_SHIFT);
 }
 
 /* Bits in first HPTE dword for pagesize 4k, 64k or 16M */
@@ -119,6 +185,7 @@ void kvmppc_map_vrma(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot,
         unsigned long psize;
         unsigned long hp0, hp1;
         long ret;
+        struct kvm *kvm = vcpu->kvm;
 
         psize = 1ul << porder;
         npages = memslot->npages >> (porder - PAGE_SHIFT);
@@ -127,8 +194,8 @@ void kvmppc_map_vrma(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot,
         if (npages > 1ul << (40 - porder))
                 npages = 1ul << (40 - porder);
         /* Can't use more than 1 HPTE per HPTEG */
-        if (npages > HPT_NPTEG)
-                npages = HPT_NPTEG;
+        if (npages > kvm->arch.hpt_mask + 1)
+                npages = kvm->arch.hpt_mask + 1;
 
         hp0 = HPTE_V_1TB_SEG | (VRMA_VSID << (40 - 16)) |
                 HPTE_V_BOLTED | hpte0_pgsize_encoding(psize);
@@ -138,7 +205,7 @@ void kvmppc_map_vrma(struct kvm_vcpu *vcpu, struct kvm_memory_slot *memslot,
         for (i = 0; i < npages; ++i) {
                 addr = i << porder;
                 /* can't use hpt_hash since va > 64 bits */
-                hash = (i ^ (VRMA_VSID ^ (VRMA_VSID << 25))) & HPT_HASH_MASK;
+                hash = (i ^ (VRMA_VSID ^ (VRMA_VSID << 25))) & kvm->arch.hpt_mask;
                 /*
                  * We assume that the hash table is empty and no
                  * vcpus are using it at this stage.  Since we create
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 3abe1b86e58..83e929e66f9 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -56,7 +56,7 @@
 /* #define EXIT_DEBUG_INT */
 
 static void kvmppc_end_cede(struct kvm_vcpu *vcpu);
-static int kvmppc_hv_setup_rma(struct kvm_vcpu *vcpu);
+static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu);
 
 void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 {
@@ -1104,11 +1104,15 @@ int kvmppc_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu)
                 return -EINTR;
         }
 
-        /* On the first time here, set up VRMA or RMA */
+        atomic_inc(&vcpu->kvm->arch.vcpus_running);
+        /* Order vcpus_running vs. rma_setup_done, see kvmppc_alloc_reset_hpt */
+        smp_mb();
+
+        /* On the first time here, set up HTAB and VRMA or RMA */
         if (!vcpu->kvm->arch.rma_setup_done) {
-                r = kvmppc_hv_setup_rma(vcpu);
+                r = kvmppc_hv_setup_htab_rma(vcpu);
                 if (r)
-                        return r;
+                        goto out;
         }
 
         flush_fp_to_thread(current);
@@ -1126,6 +1130,9 @@ int kvmppc_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu)
                         kvmppc_core_prepare_to_enter(vcpu);
                 }
         } while (r == RESUME_GUEST);
+
+ out:
+        atomic_dec(&vcpu->kvm->arch.vcpus_running);
         return r;
 }
 
@@ -1341,7 +1348,7 @@ void kvmppc_core_commit_memory_region(struct kvm *kvm,
 {
 }
 
-static int kvmppc_hv_setup_rma(struct kvm_vcpu *vcpu)
+static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu)
 {
         int err = 0;
         struct kvm *kvm = vcpu->kvm;
@@ -1360,6 +1367,15 @@ static int kvmppc_hv_setup_rma(struct kvm_vcpu *vcpu)
         if (kvm->arch.rma_setup_done)
                 goto out;       /* another vcpu beat us to it */
 
+        /* Allocate hashed page table (if not done already) and reset it */
+        if (!kvm->arch.hpt_virt) {
+                err = kvmppc_alloc_hpt(kvm, NULL);
+                if (err) {
+                        pr_err("KVM: Couldn't alloc HPT\n");
+                        goto out;
+                }
+        }
+
         /* Look up the memslot for guest physical address 0 */
         memslot = gfn_to_memslot(kvm, 0);
 
@@ -1471,13 +1487,14 @@ static int kvmppc_hv_setup_rma(struct kvm_vcpu *vcpu)
 
 int kvmppc_core_init_vm(struct kvm *kvm)
 {
-        long r;
-        unsigned long lpcr;
+        unsigned long lpcr, lpid;
 
-        /* Allocate hashed page table */
-        r = kvmppc_alloc_hpt(kvm);
-        if (r)
-                return r;
+        /* Allocate the guest's logical partition ID */
+
+        lpid = kvmppc_alloc_lpid();
+        if (lpid < 0)
+                return -ENOMEM;
+        kvm->arch.lpid = lpid;
 
         INIT_LIST_HEAD(&kvm->arch.spapr_tce_tables);
 
@@ -1487,7 +1504,6 @@ int kvmppc_core_init_vm(struct kvm *kvm)
 
         if (cpu_has_feature(CPU_FTR_ARCH_201)) {
                 /* PPC970; HID4 is effectively the LPCR */
-                unsigned long lpid = kvm->arch.lpid;
                 kvm->arch.host_lpid = 0;
                 kvm->arch.host_lpcr = lpcr = mfspr(SPRN_HID4);
                 lpcr &= ~((3 << HID4_LPID1_SH) | (0xful << HID4_LPID5_SH));
diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c
index e1b60f56f2a..fb4eac290fe 100644
--- a/arch/powerpc/kvm/book3s_hv_builtin.c
+++ b/arch/powerpc/kvm/book3s_hv_builtin.c
@@ -25,6 +25,9 @@ static void __init kvm_linear_init_one(ulong size, int count, int type);
 static struct kvmppc_linear_info *kvm_alloc_linear(int type);
 static void kvm_release_linear(struct kvmppc_linear_info *ri);
 
+int kvm_hpt_order = KVM_DEFAULT_HPT_ORDER;
+EXPORT_SYMBOL_GPL(kvm_hpt_order);
+
 /*************** RMA *************/
 
 /*
@@ -209,7 +212,7 @@ static void kvm_release_linear(struct kvmppc_linear_info *ri)
 void __init kvm_linear_init(void)
 {
         /* HPT */
-        kvm_linear_init_one(1 << HPT_ORDER, kvm_hpt_count, KVM_LINEAR_HPT);
+        kvm_linear_init_one(1 << kvm_hpt_order, kvm_hpt_count, KVM_LINEAR_HPT);
 
         /* RMA */
         /* Only do this on PPC970 in HV mode */
diff --git a/arch/powerpc/kvm/book3s_hv_rm_mmu.c b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
index cec4daddbf3..5c70d19494f 100644
--- a/arch/powerpc/kvm/book3s_hv_rm_mmu.c
+++ b/arch/powerpc/kvm/book3s_hv_rm_mmu.c
@@ -237,7 +237,7 @@ long kvmppc_h_enter(struct kvm_vcpu *vcpu, unsigned long flags,
 
         /* Find and lock the HPTEG slot to use */
  do_insert:
-        if (pte_index >= HPT_NPTE)
+        if (pte_index >= kvm->arch.hpt_npte)
                 return H_PARAMETER;
         if (likely((flags & H_EXACT) == 0)) {
                 pte_index &= ~7UL;
@@ -352,7 +352,7 @@ long kvmppc_h_remove(struct kvm_vcpu *vcpu, unsigned long flags,
         unsigned long v, r, rb;
         struct revmap_entry *rev;
 
-        if (pte_index >= HPT_NPTE)
+        if (pte_index >= kvm->arch.hpt_npte)
                 return H_PARAMETER;
         hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
         while (!try_lock_hpte(hpte, HPTE_V_HVLOCK))
@@ -419,7 +419,8 @@ long kvmppc_h_bulk_remove(struct kvm_vcpu *vcpu)
                                 i = 4;
                                 break;
                         }
-                        if (req != 1 || flags == 3 || pte_index >= HPT_NPTE) {
+                        if (req != 1 || flags == 3 ||
+                            pte_index >= kvm->arch.hpt_npte) {
                                 /* parameter error */
                                 args[j] = ((0xa0 | flags) << 56) + pte_index;
                                 ret = H_PARAMETER;
@@ -521,7 +522,7 @@ long kvmppc_h_protect(struct kvm_vcpu *vcpu, unsigned long flags,
         struct revmap_entry *rev;
         unsigned long v, r, rb, mask, bits;
 
-        if (pte_index >= HPT_NPTE)
+        if (pte_index >= kvm->arch.hpt_npte)
                 return H_PARAMETER;
 
         hpte = (unsigned long *)(kvm->arch.hpt_virt + (pte_index << 4));
@@ -583,7 +584,7 @@ long kvmppc_h_read(struct kvm_vcpu *vcpu, unsigned long flags,
         int i, n = 1;
         struct revmap_entry *rev = NULL;
 
-        if (pte_index >= HPT_NPTE)
+        if (pte_index >= kvm->arch.hpt_npte)
                 return H_PARAMETER;
         if (flags & H_READ_4) {
                 pte_index &= ~3;
@@ -678,7 +679,7 @@ long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
                 somask = (1UL << 28) - 1;
                 vsid = (slb_v & ~SLB_VSID_B) >> SLB_VSID_SHIFT;
         }
-        hash = (vsid ^ ((eaddr & somask) >> pshift)) & HPT_HASH_MASK;
+        hash = (vsid ^ ((eaddr & somask) >> pshift)) & kvm->arch.hpt_mask;
         avpn = slb_v & ~(somask >> 16); /* also includes B */
         avpn |= (eaddr & somask) >> 16;
 
@@ -723,7 +724,7 @@ long kvmppc_hv_find_lock_hpte(struct kvm *kvm, gva_t eaddr, unsigned long slb_v,
                 if (val & HPTE_V_SECONDARY)
                         break;
                 val |= HPTE_V_SECONDARY;
-                hash = hash ^ HPT_HASH_MASK;
+                hash = hash ^ kvm->arch.hpt_mask;
         }
         return -1;
 }
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index a1044f43bec..44b72feaff7 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -72,9 +72,6 @@ _GLOBAL(kvmppc_hv_entry_trampoline)
         mtsrr1  r6
         RFI
 
-#define ULONG_SIZE              8
-#define VCPU_GPR(n)             (VCPU_GPRS + (n * ULONG_SIZE))
-
 /******************************************************************************
  *                                                                            *
  *                               Entry code                                   *
@@ -206,24 +203,24 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         /* Load up FP, VMX and VSX registers */
         bl      kvmppc_load_fp
 
-        ld      r14, VCPU_GPR(r14)(r4)
-        ld      r15, VCPU_GPR(r15)(r4)
-        ld      r16, VCPU_GPR(r16)(r4)
-        ld      r17, VCPU_GPR(r17)(r4)
-        ld      r18, VCPU_GPR(r18)(r4)
-        ld      r19, VCPU_GPR(r19)(r4)
-        ld      r20, VCPU_GPR(r20)(r4)
-        ld      r21, VCPU_GPR(r21)(r4)
-        ld      r22, VCPU_GPR(r22)(r4)
-        ld      r23, VCPU_GPR(r23)(r4)
-        ld      r24, VCPU_GPR(r24)(r4)
-        ld      r25, VCPU_GPR(r25)(r4)
-        ld      r26, VCPU_GPR(r26)(r4)
-        ld      r27, VCPU_GPR(r27)(r4)
-        ld      r28, VCPU_GPR(r28)(r4)
-        ld      r29, VCPU_GPR(r29)(r4)
-        ld      r30, VCPU_GPR(r30)(r4)
-        ld      r31, VCPU_GPR(r31)(r4)
+        ld      r14, VCPU_GPR(R14)(r4)
+        ld      r15, VCPU_GPR(R15)(r4)
+        ld      r16, VCPU_GPR(R16)(r4)
+        ld      r17, VCPU_GPR(R17)(r4)
+        ld      r18, VCPU_GPR(R18)(r4)
+        ld      r19, VCPU_GPR(R19)(r4)
+        ld      r20, VCPU_GPR(R20)(r4)
+        ld      r21, VCPU_GPR(R21)(r4)
+        ld      r22, VCPU_GPR(R22)(r4)
+        ld      r23, VCPU_GPR(R23)(r4)
+        ld      r24, VCPU_GPR(R24)(r4)
+        ld      r25, VCPU_GPR(R25)(r4)
+        ld      r26, VCPU_GPR(R26)(r4)
+        ld      r27, VCPU_GPR(R27)(r4)
+        ld      r28, VCPU_GPR(R28)(r4)
+        ld      r29, VCPU_GPR(R29)(r4)
+        ld      r30, VCPU_GPR(R30)(r4)
+        ld      r31, VCPU_GPR(R31)(r4)
 
 BEGIN_FTR_SECTION
         /* Switch DSCR to guest value */
@@ -547,21 +544,21 @@ fast_guest_return:
         mtlr    r5
         mtcr    r6
 
-        ld      r0, VCPU_GPR(r0)(r4)
-        ld      r1, VCPU_GPR(r1)(r4)
-        ld      r2, VCPU_GPR(r2)(r4)
-        ld      r3, VCPU_GPR(r3)(r4)
-        ld      r5, VCPU_GPR(r5)(r4)
-        ld      r6, VCPU_GPR(r6)(r4)
-        ld      r7, VCPU_GPR(r7)(r4)
-        ld      r8, VCPU_GPR(r8)(r4)
-        ld      r9, VCPU_GPR(r9)(r4)
-        ld      r10, VCPU_GPR(r10)(r4)
-        ld      r11, VCPU_GPR(r11)(r4)
-        ld      r12, VCPU_GPR(r12)(r4)
-        ld      r13, VCPU_GPR(r13)(r4)
-
-        ld      r4, VCPU_GPR(r4)(r4)
+        ld      r0, VCPU_GPR(R0)(r4)
+        ld      r1, VCPU_GPR(R1)(r4)
+        ld      r2, VCPU_GPR(R2)(r4)
+        ld      r3, VCPU_GPR(R3)(r4)
+        ld      r5, VCPU_GPR(R5)(r4)
+        ld      r6, VCPU_GPR(R6)(r4)
+        ld      r7, VCPU_GPR(R7)(r4)
+        ld      r8, VCPU_GPR(R8)(r4)
+        ld      r9, VCPU_GPR(R9)(r4)
+        ld      r10, VCPU_GPR(R10)(r4)
+        ld      r11, VCPU_GPR(R11)(r4)
+        ld      r12, VCPU_GPR(R12)(r4)
+        ld      r13, VCPU_GPR(R13)(r4)
+
+        ld      r4, VCPU_GPR(R4)(r4)
 
         hrfid
         b       .
@@ -590,22 +587,22 @@ kvmppc_interrupt:
 
         /* Save registers */
 
-        std     r0, VCPU_GPR(r0)(r9)
-        std     r1, VCPU_GPR(r1)(r9)
-        std     r2, VCPU_GPR(r2)(r9)
-        std     r3, VCPU_GPR(r3)(r9)
-        std     r4, VCPU_GPR(r4)(r9)
-        std     r5, VCPU_GPR(r5)(r9)
-        std     r6, VCPU_GPR(r6)(r9)
-        std     r7, VCPU_GPR(r7)(r9)
-        std     r8, VCPU_GPR(r8)(r9)
+        std     r0, VCPU_GPR(R0)(r9)
+        std     r1, VCPU_GPR(R1)(r9)
+        std     r2, VCPU_GPR(R2)(r9)
+        std     r3, VCPU_GPR(R3)(r9)
+        std     r4, VCPU_GPR(R4)(r9)
+        std     r5, VCPU_GPR(R5)(r9)
+        std     r6, VCPU_GPR(R6)(r9)
+        std     r7, VCPU_GPR(R7)(r9)
+        std     r8, VCPU_GPR(R8)(r9)
         ld      r0, HSTATE_HOST_R2(r13)
-        std     r0, VCPU_GPR(r9)(r9)
-        std     r10, VCPU_GPR(r10)(r9)
-        std     r11, VCPU_GPR(r11)(r9)
+        std     r0, VCPU_GPR(R9)(r9)
+        std     r10, VCPU_GPR(R10)(r9)
+        std     r11, VCPU_GPR(R11)(r9)
         ld      r3, HSTATE_SCRATCH0(r13)
         lwz     r4, HSTATE_SCRATCH1(r13)
-        std     r3, VCPU_GPR(r12)(r9)
+        std     r3, VCPU_GPR(R12)(r9)
         stw     r4, VCPU_CR(r9)
 
         /* Restore R1/R2 so we can handle faults */
@@ -626,7 +623,7 @@ kvmppc_interrupt:
 
         GET_SCRATCH0(r3)
         mflr    r4
-        std     r3, VCPU_GPR(r13)(r9)
+        std     r3, VCPU_GPR(R13)(r9)
         std     r4, VCPU_LR(r9)
 
         /* Unset guest mode */
@@ -968,24 +965,24 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 
         /* Save non-volatile GPRs */
-        std     r14, VCPU_GPR(r14)(r9)
-        std     r15, VCPU_GPR(r15)(r9)
-        std     r16, VCPU_GPR(r16)(r9)
-        std     r17, VCPU_GPR(r17)(r9)
-        std     r18, VCPU_GPR(r18)(r9)
-        std     r19, VCPU_GPR(r19)(r9)
-        std     r20, VCPU_GPR(r20)(r9)
-        std     r21, VCPU_GPR(r21)(r9)
-        std     r22, VCPU_GPR(r22)(r9)
-        std     r23, VCPU_GPR(r23)(r9)
-        std     r24, VCPU_GPR(r24)(r9)
-        std     r25, VCPU_GPR(r25)(r9)
-        std     r26, VCPU_GPR(r26)(r9)
-        std     r27, VCPU_GPR(r27)(r9)
-        std     r28, VCPU_GPR(r28)(r9)
-        std     r29, VCPU_GPR(r29)(r9)
-        std     r30, VCPU_GPR(r30)(r9)
-        std     r31, VCPU_GPR(r31)(r9)
+        std     r14, VCPU_GPR(R14)(r9)
+        std     r15, VCPU_GPR(R15)(r9)
+        std     r16, VCPU_GPR(R16)(r9)
+        std     r17, VCPU_GPR(R17)(r9)
+        std     r18, VCPU_GPR(R18)(r9)
+        std     r19, VCPU_GPR(R19)(r9)
+        std     r20, VCPU_GPR(R20)(r9)
+        std     r21, VCPU_GPR(R21)(r9)
+        std     r22, VCPU_GPR(R22)(r9)
+        std     r23, VCPU_GPR(R23)(r9)
+        std     r24, VCPU_GPR(R24)(r9)
+        std     r25, VCPU_GPR(R25)(r9)
+        std     r26, VCPU_GPR(R26)(r9)
+        std     r27, VCPU_GPR(R27)(r9)
+        std     r28, VCPU_GPR(R28)(r9)
+        std     r29, VCPU_GPR(R29)(r9)
+        std     r30, VCPU_GPR(R30)(r9)
+        std     r31, VCPU_GPR(R31)(r9)
 
         /* Save SPRGs */
         mfspr   r3, SPRN_SPRG0
@@ -1067,6 +1064,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
         mtspr   SPRN_DABR,r5
         mtspr   SPRN_DABRX,r6
 
+        /* Restore SPRG3 */
+        ld      r3,HSTATE_SPRG3(r13)
+        mtspr   SPRN_SPRG3,r3
+
         /*
          * Reload DEC.  HDEC interrupts were disabled when
          * we reloaded the host's LPCR value.
@@ -1160,7 +1161,7 @@ kvmppc_hdsi:
         andi.   r0, r11, MSR_DR         /* data relocation enabled? */
         beq     3f
         clrrdi  r0, r4, 28
-        PPC_SLBFEE_DOT(r5, r0)          /* if so, look up SLB */
+        PPC_SLBFEE_DOT(R5, R0)          /* if so, look up SLB */
         bne     1f                      /* if no SLB entry found */
 4:      std     r4, VCPU_FAULT_DAR(r9)
         stw     r6, VCPU_FAULT_DSISR(r9)
@@ -1234,7 +1235,7 @@ kvmppc_hisi:
         andi.   r0, r11, MSR_IR         /* instruction relocation enabled? */
         beq     3f
         clrrdi  r0, r10, 28
-        PPC_SLBFEE_DOT(r5, r0)          /* if so, look up SLB */
+        PPC_SLBFEE_DOT(R5, R0)          /* if so, look up SLB */
         bne     1f                      /* if no SLB entry found */
 4:
         /* Search the hash table. */
@@ -1278,7 +1279,7 @@ kvmppc_hisi:
  */
         .globl  hcall_try_real_mode
 hcall_try_real_mode:
-        ld      r3,VCPU_GPR(r3)(r9)
+        ld      r3,VCPU_GPR(R3)(r9)
         andi.   r0,r11,MSR_PR
         bne     hcall_real_cont
         clrrdi  r3,r3,2
@@ -1291,12 +1292,12 @@ hcall_try_real_mode:
         add     r3,r3,r4
         mtctr   r3
         mr      r3,r9           /* get vcpu pointer */
-        ld      r4,VCPU_GPR(r4)(r9)
+        ld      r4,VCPU_GPR(R4)(r9)
         bctrl
         cmpdi   r3,H_TOO_HARD
         beq     hcall_real_fallback
         ld      r4,HSTATE_KVM_VCPU(r13)
-        std     r3,VCPU_GPR(r3)(r4)
+        std     r3,VCPU_GPR(R3)(r4)
         ld      r10,VCPU_PC(r4)
         ld      r11,VCPU_MSR(r4)
         b       fast_guest_return
@@ -1420,13 +1421,13 @@ _GLOBAL(kvmppc_h_cede)
         sync                    /* order setting ceded vs. testing prodded */
         lbz     r5,VCPU_PRODDED(r3)
         cmpwi   r5,0
-        bne     1f
+        bne     kvm_cede_prodded
         li      r0,0            /* set trap to 0 to say hcall is handled */
         stw     r0,VCPU_TRAP(r3)
         li      r0,H_SUCCESS
-        std     r0,VCPU_GPR(r3)(r3)
+        std     r0,VCPU_GPR(R3)(r3)
 BEGIN_FTR_SECTION
-        b       2f              /* just send it up to host on 970 */
+        b       kvm_cede_exit   /* just send it up to host on 970 */
 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
 
         /*
@@ -1443,9 +1444,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
         addi    r6,r5,VCORE_NAPPING_THREADS
 31:     lwarx   r4,0,r6
         or      r4,r4,r0
-        PPC_POPCNTW(r7,r4)
+        PPC_POPCNTW(R7,R4)
         cmpw    r7,r8
-        bge     2f
+        bge     kvm_cede_exit
         stwcx.  r4,0,r6
         bne     31b
         li      r0,1
@@ -1464,24 +1465,24 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_206)
  * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
  */
         /* Save non-volatile GPRs */
-        std     r14, VCPU_GPR(r14)(r3)
-        std     r15, VCPU_GPR(r15)(r3)
-        std     r16, VCPU_GPR(r16)(r3)
-        std     r17, VCPU_GPR(r17)(r3)
-        std     r18, VCPU_GPR(r18)(r3)
-        std     r19, VCPU_GPR(r19)(r3)
-        std     r20, VCPU_GPR(r20)(r3)
-        std     r21, VCPU_GPR(r21)(r3)
-        std     r22, VCPU_GPR(r22)(r3)
-        std     r23, VCPU_GPR(r23)(r3)
-        std     r24, VCPU_GPR(r24)(r3)
-        std     r25, VCPU_GPR(r25)(r3)
-        std     r26, VCPU_GPR(r26)(r3)
-        std     r27, VCPU_GPR(r27)(r3)
-        std     r28, VCPU_GPR(r28)(r3)
-        std     r29, VCPU_GPR(r29)(r3)
-        std     r30, VCPU_GPR(r30)(r3)
-        std     r31, VCPU_GPR(r31)(r3)
+        std     r14, VCPU_GPR(R14)(r3)
+        std     r15, VCPU_GPR(R15)(r3)
+        std     r16, VCPU_GPR(R16)(r3)
+        std     r17, VCPU_GPR(R17)(r3)
+        std     r18, VCPU_GPR(R18)(r3)
+        std     r19, VCPU_GPR(R19)(r3)
+        std     r20, VCPU_GPR(R20)(r3)
+        std     r21, VCPU_GPR(R21)(r3)
+        std     r22, VCPU_GPR(R22)(r3)
+        std     r23, VCPU_GPR(R23)(r3)
+        std     r24, VCPU_GPR(R24)(r3)
+        std     r25, VCPU_GPR(R25)(r3)
+        std     r26, VCPU_GPR(R26)(r3)
+        std     r27, VCPU_GPR(R27)(r3)
+        std     r28, VCPU_GPR(R28)(r3)
+        std     r29, VCPU_GPR(R29)(r3)
+        std     r30, VCPU_GPR(R30)(r3)
+        std     r31, VCPU_GPR(R31)(r3)
 
         /* save FP state */
         bl      .kvmppc_save_fp
@@ -1513,24 +1514,24 @@ kvm_end_cede:
         bl      kvmppc_load_fp
 
         /* Load NV GPRS */
-        ld      r14, VCPU_GPR(r14)(r4)
-        ld      r15, VCPU_GPR(r15)(r4)
-        ld      r16, VCPU_GPR(r16)(r4)
-        ld      r17, VCPU_GPR(r17)(r4)
-        ld      r18, VCPU_GPR(r18)(r4)
-        ld      r19, VCPU_GPR(r19)(r4)
-        ld      r20, VCPU_GPR(r20)(r4)
-        ld      r21, VCPU_GPR(r21)(r4)
-        ld      r22, VCPU_GPR(r22)(r4)
-        ld      r23, VCPU_GPR(r23)(r4)
-        ld      r24, VCPU_GPR(r24)(r4)
-        ld      r25, VCPU_GPR(r25)(r4)
-        ld      r26, VCPU_GPR(r26)(r4)
-        ld      r27, VCPU_GPR(r27)(r4)
-        ld      r28, VCPU_GPR(r28)(r4)
-        ld      r29, VCPU_GPR(r29)(r4)
-        ld      r30, VCPU_GPR(r30)(r4)
-        ld      r31, VCPU_GPR(r31)(r4)
+        ld      r14, VCPU_GPR(R14)(r4)
+        ld      r15, VCPU_GPR(R15)(r4)
+        ld      r16, VCPU_GPR(R16)(r4)
+        ld      r17, VCPU_GPR(R17)(r4)
+        ld      r18, VCPU_GPR(R18)(r4)
+        ld      r19, VCPU_GPR(R19)(r4)
+        ld      r20, VCPU_GPR(R20)(r4)
+        ld      r21, VCPU_GPR(R21)(r4)
+        ld      r22, VCPU_GPR(R22)(r4)
+        ld      r23, VCPU_GPR(R23)(r4)
+        ld      r24, VCPU_GPR(R24)(r4)
+        ld      r25, VCPU_GPR(R25)(r4)
+        ld      r26, VCPU_GPR(R26)(r4)
+        ld      r27, VCPU_GPR(R27)(r4)
+        ld      r28, VCPU_GPR(R28)(r4)
+        ld      r29, VCPU_GPR(R29)(r4)
+        ld      r30, VCPU_GPR(R30)(r4)
+        ld      r31, VCPU_GPR(R31)(r4)
 
         /* clear our bit in vcore->napping_threads */
 33:     ld      r5,HSTATE_KVM_VCORE(r13)
@@ -1554,7 +1555,8 @@ kvm_end_cede:
         b       hcall_real_fallback
 
         /* cede when already previously prodded case */
-1:      li      r0,0
+kvm_cede_prodded:
+        li      r0,0
         stb     r0,VCPU_PRODDED(r3)
         sync                    /* order testing prodded vs. clearing ceded */
         stb     r0,VCPU_CEDED(r3)
@@ -1562,7 +1564,8 @@ kvm_end_cede:
         blr
 
         /* we've ceded but we want to give control to the host */
-2:      li      r3,H_TOO_HARD
+kvm_cede_exit:
+        li      r3,H_TOO_HARD
         blr
 
 secondary_too_late:
@@ -1649,7 +1652,7 @@ BEGIN_FTR_SECTION
         reg = 0
         .rept   32
         li      r6,reg*16+VCPU_VSRS
-        STXVD2X(reg,r6,r3)
+        STXVD2X(reg,R6,R3)
         reg = reg + 1
         .endr
 FTR_SECTION_ELSE
@@ -1711,7 +1714,7 @@ BEGIN_FTR_SECTION
         reg = 0
         .rept   32
         li      r7,reg*16+VCPU_VSRS
-        LXVD2X(reg,r7,r4)
+        LXVD2X(reg,R7,R4)
         reg = reg + 1
         .endr
 FTR_SECTION_ELSE
diff --git a/arch/powerpc/kvm/book3s_interrupts.S b/arch/powerpc/kvm/book3s_interrupts.S
index 3e35383bdb2..48cbbf86295 100644
--- a/arch/powerpc/kvm/book3s_interrupts.S
+++ b/arch/powerpc/kvm/book3s_interrupts.S
@@ -25,38 +25,30 @@
 #include <asm/exception-64s.h>
 
 #if defined(CONFIG_PPC_BOOK3S_64)
-
-#define ULONG_SIZE              8
 #define FUNC(name)              GLUE(.,name)
-
 #elif defined(CONFIG_PPC_BOOK3S_32)
-
-#define ULONG_SIZE              4
 #define FUNC(name)              name
-
 #endif /* CONFIG_PPC_BOOK3S_XX */
 
-
-#define VCPU_GPR(n)             (VCPU_GPRS + (n * ULONG_SIZE))
 #define VCPU_LOAD_NVGPRS(vcpu) \
-        PPC_LL  r14, VCPU_GPR(r14)(vcpu); \
-        PPC_LL  r15, VCPU_GPR(r15)(vcpu); \
-        PPC_LL  r16, VCPU_GPR(r16)(vcpu); \
-        PPC_LL  r17, VCPU_GPR(r17)(vcpu); \
-        PPC_LL  r18, VCPU_GPR(r18)(vcpu); \
-        PPC_LL  r19, VCPU_GPR(r19)(vcpu); \
-        PPC_LL  r20, VCPU_GPR(r20)(vcpu); \
-        PPC_LL  r21, VCPU_GPR(r21)(vcpu); \
-        PPC_LL  r22, VCPU_GPR(r22)(vcpu); \
-        PPC_LL  r23, VCPU_GPR(r23)(vcpu); \
-        PPC_LL  r24, VCPU_GPR(r24)(vcpu); \
-        PPC_LL  r25, VCPU_GPR(r25)(vcpu); \
-        PPC_LL  r26, VCPU_GPR(r26)(vcpu); \
-        PPC_LL  r27, VCPU_GPR(r27)(vcpu); \
-        PPC_LL  r28, VCPU_GPR(r28)(vcpu); \
-        PPC_LL  r29, VCPU_GPR(r29)(vcpu); \
-        PPC_LL  r30, VCPU_GPR(r30)(vcpu); \
-        PPC_LL  r31, VCPU_GPR(r31)(vcpu); \
+        PPC_LL  r14, VCPU_GPR(R14)(vcpu); \
+        PPC_LL  r15, VCPU_GPR(R15)(vcpu); \
+        PPC_LL  r16, VCPU_GPR(R16)(vcpu); \
+        PPC_LL  r17, VCPU_GPR(R17)(vcpu); \
+        PPC_LL  r18, VCPU_GPR(R18)(vcpu); \
+        PPC_LL  r19, VCPU_GPR(R19)(vcpu); \
+        PPC_LL  r20, VCPU_GPR(R20)(vcpu); \
+        PPC_LL  r21, VCPU_GPR(R21)(vcpu); \
+        PPC_LL  r22, VCPU_GPR(R22)(vcpu); \
+        PPC_LL  r23, VCPU_GPR(R23)(vcpu); \
+        PPC_LL  r24, VCPU_GPR(R24)(vcpu); \
+        PPC_LL  r25, VCPU_GPR(R25)(vcpu); \
+        PPC_LL  r26, VCPU_GPR(R26)(vcpu); \
+        PPC_LL  r27, VCPU_GPR(R27)(vcpu); \
+        PPC_LL  r28, VCPU_GPR(R28)(vcpu); \
+        PPC_LL  r29, VCPU_GPR(R29)(vcpu); \
+        PPC_LL  r30, VCPU_GPR(R30)(vcpu); \
+        PPC_LL  r31, VCPU_GPR(R31)(vcpu); \
 
 /*****************************************************************************
  *                                                                           *
@@ -131,24 +123,24 @@ kvmppc_handler_highmem:
         /* R7 = vcpu */
         PPC_LL  r7, GPR4(r1)
 
-        PPC_STL r14, VCPU_GPR(r14)(r7)
-        PPC_STL r15, VCPU_GPR(r15)(r7)
-        PPC_STL r16, VCPU_GPR(r16)(r7)
-        PPC_STL r17, VCPU_GPR(r17)(r7)
-        PPC_STL r18, VCPU_GPR(r18)(r7)
-        PPC_STL r19, VCPU_GPR(r19)(r7)
-        PPC_STL r20, VCPU_GPR(r20)(r7)
-        PPC_STL r21, VCPU_GPR(r21)(r7)
-        PPC_STL r22, VCPU_GPR(r22)(r7)
-        PPC_STL r23, VCPU_GPR(r23)(r7)
-        PPC_STL r24, VCPU_GPR(r24)(r7)
-        PPC_STL r25, VCPU_GPR(r25)(r7)
-        PPC_STL r26, VCPU_GPR(r26)(r7)
-        PPC_STL r27, VCPU_GPR(r27)(r7)
-        PPC_STL r28, VCPU_GPR(r28)(r7)
-        PPC_STL r29, VCPU_GPR(r29)(r7)
-        PPC_STL r30, VCPU_GPR(r30)(r7)
-        PPC_STL r31, VCPU_GPR(r31)(r7)
+        PPC_STL r14, VCPU_GPR(R14)(r7)
+        PPC_STL r15, VCPU_GPR(R15)(r7)
+        PPC_STL r16, VCPU_GPR(R16)(r7)
+        PPC_STL r17, VCPU_GPR(R17)(r7)
+        PPC_STL r18, VCPU_GPR(R18)(r7)
+        PPC_STL r19, VCPU_GPR(R19)(r7)
+        PPC_STL r20, VCPU_GPR(R20)(r7)
+        PPC_STL r21, VCPU_GPR(R21)(r7)
+        PPC_STL r22, VCPU_GPR(R22)(r7)
+        PPC_STL r23, VCPU_GPR(R23)(r7)
+        PPC_STL r24, VCPU_GPR(R24)(r7)
+        PPC_STL r25, VCPU_GPR(R25)(r7)
+        PPC_STL r26, VCPU_GPR(R26)(r7)
+        PPC_STL r27, VCPU_GPR(R27)(r7)
+        PPC_STL r28, VCPU_GPR(R28)(r7)
+        PPC_STL r29, VCPU_GPR(R29)(r7)
+        PPC_STL r30, VCPU_GPR(R30)(r7)
+        PPC_STL r31, VCPU_GPR(R31)(r7)
 
         /* Pass the exit number as 3rd argument to kvmppc_handle_exit */
         mr      r5, r12
diff --git a/arch/powerpc/kvm/book3s_rmhandlers.S b/arch/powerpc/kvm/book3s_rmhandlers.S
index 34187585c50..9ecf6e35cd8 100644
--- a/arch/powerpc/kvm/book3s_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_rmhandlers.S
@@ -37,7 +37,6 @@
 #if defined(CONFIG_PPC_BOOK3S_64)
 
 #define FUNC(name)              GLUE(.,name)
-#define MTMSR_EERI(reg)         mtmsrd  (reg),1
 
         .globl  kvmppc_skip_interrupt
 kvmppc_skip_interrupt:
@@ -68,7 +67,6 @@ kvmppc_skip_Hinterrupt:
 #elif defined(CONFIG_PPC_BOOK3S_32)
 
 #define FUNC(name)              name
-#define MTMSR_EERI(reg)         mtmsr   (reg)
 
 .macro INTERRUPT_TRAMPOLINE intno
 
diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S
index 798491a268b..1abe4788191 100644
--- a/arch/powerpc/kvm/book3s_segment.S
+++ b/arch/powerpc/kvm/book3s_segment.S
@@ -23,7 +23,6 @@
 
 #define GET_SHADOW_VCPU(reg)    \
         mr      reg, r13
-#define MTMSR_EERI(reg)         mtmsrd  (reg),1
 
 #elif defined(CONFIG_PPC_BOOK3S_32)
 
@@ -31,7 +30,6 @@
         tophys(reg, r2);                        \
         lwz     reg, (THREAD + THREAD_KVM_SVCPU)(reg);  \
         tophys(reg, reg)
-#define MTMSR_EERI(reg)         mtmsr   (reg)
 
 #endif
 
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 72f13f4a06e..d25a097c852 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -612,6 +612,12 @@ static void kvmppc_fill_pt_regs(struct pt_regs *regs)
         regs->link = lr;
 }
 
+/*
+ * For interrupts needed to be handled by host interrupt handlers,
+ * corresponding host handler are called from here in similar way
+ * (but not exact) as they are called from low level handler
+ * (such as from arch/powerpc/kernel/head_fsl_booke.S).
+ */
 static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu,
                                      unsigned int exit_nr)
 {
@@ -639,6 +645,17 @@ static void kvmppc_restart_interrupt(struct kvm_vcpu *vcpu,
                 kvmppc_fill_pt_regs(&regs);
                 performance_monitor_exception(&regs);
                 break;
+        case BOOKE_INTERRUPT_WATCHDOG:
+                kvmppc_fill_pt_regs(&regs);
+#ifdef CONFIG_BOOKE_WDT
+                WatchdogException(&regs);
+#else
+                unknown_exception(&regs);
+#endif
+                break;
+        case BOOKE_INTERRUPT_CRITICAL:
+                unknown_exception(&regs);
+                break;
         }
 }
 
@@ -683,6 +700,10 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 r = RESUME_GUEST;
                 break;
 
+        case BOOKE_INTERRUPT_WATCHDOG:
+                r = RESUME_GUEST;
+                break;
+
         case BOOKE_INTERRUPT_DOORBELL:
                 kvmppc_account_exit(vcpu, DBELL_EXITS);
                 r = RESUME_GUEST;
@@ -1267,6 +1288,11 @@ void kvmppc_decrementer_func(unsigned long data)
 {
         struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
 
+        if (vcpu->arch.tcr & TCR_ARE) {
+                vcpu->arch.dec = vcpu->arch.decar;
+                kvmppc_emulate_dec(vcpu);
+        }
+
         kvmppc_set_tsr_bits(vcpu, TSR_DIS);
 }
 
diff --git a/arch/powerpc/kvm/booke_emulate.c b/arch/powerpc/kvm/booke_emulate.c
index 6c76397f2af..12834bb608a 100644
--- a/arch/powerpc/kvm/booke_emulate.c
+++ b/arch/powerpc/kvm/booke_emulate.c
@@ -24,6 +24,7 @@
 #include "booke.h"
 
 #define OP_19_XOP_RFI     50
+#define OP_19_XOP_RFCI    51
 
 #define OP_31_XOP_MFMSR   83
 #define OP_31_XOP_WRTEE   131
@@ -36,6 +37,12 @@ static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
         kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
 }
 
+static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
+{
+        vcpu->arch.pc = vcpu->arch.csrr0;
+        kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
+}
+
 int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
                             unsigned int inst, int *advance)
 {
@@ -52,6 +59,12 @@ int kvmppc_booke_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu,
                         *advance = 0;
                         break;
 
+                case OP_19_XOP_RFCI:
+                        kvmppc_emul_rfci(vcpu);
+                        kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
+                        *advance = 0;
+                        break;
+
                 default:
                         emulated = EMULATE_FAIL;
                         break;
@@ -113,6 +126,12 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
         case SPRN_ESR:
                 vcpu->arch.shared->esr = spr_val;
                 break;
+        case SPRN_CSRR0:
+                vcpu->arch.csrr0 = spr_val;
+                break;
+        case SPRN_CSRR1:
+                vcpu->arch.csrr1 = spr_val;
+                break;
         case SPRN_DBCR0:
                 vcpu->arch.dbcr0 = spr_val;
                 break;
@@ -129,6 +148,9 @@ int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
                 kvmppc_set_tcr(vcpu, spr_val);
                 break;
 
+        case SPRN_DECAR:
+                vcpu->arch.decar = spr_val;
+                break;
         /*
          * Note: SPRG4-7 are user-readable.
          * These values are loaded into the real SPRGs when resuming the
@@ -229,6 +251,12 @@ int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
         case SPRN_ESR:
                 *spr_val = vcpu->arch.shared->esr;
                 break;
+        case SPRN_CSRR0:
+                *spr_val = vcpu->arch.csrr0;
+                break;
+        case SPRN_CSRR1:
+                *spr_val = vcpu->arch.csrr1;
+                break;
         case SPRN_DBCR0:
                 *spr_val = vcpu->arch.dbcr0;
                 break;
diff --git a/arch/powerpc/kvm/booke_interrupts.S b/arch/powerpc/kvm/booke_interrupts.S
index 8feec2ff392..bb46b32f981 100644
--- a/arch/powerpc/kvm/booke_interrupts.S
+++ b/arch/powerpc/kvm/booke_interrupts.S
@@ -25,8 +25,6 @@
 #include <asm/page.h>
 #include <asm/asm-offsets.h>
 
-#define VCPU_GPR(n)     (VCPU_GPRS + (n * 4))
-
 /* The host stack layout: */
 #define HOST_R1         0 /* Implied by stwu. */
 #define HOST_CALLEE_LR  4
@@ -36,8 +34,9 @@
 #define HOST_R2         12
 #define HOST_CR         16
 #define HOST_NV_GPRS    20
-#define HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * 4))
-#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + 4)
+#define __HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * 4))
+#define HOST_NV_GPR(n)  __HOST_NV_GPR(__REG_##n)
+#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + 4)
 #define HOST_STACK_SIZE (((HOST_MIN_STACK_SIZE + 15) / 16) * 16) /* Align. */
 #define HOST_STACK_LR   (HOST_STACK_SIZE + 4) /* In caller stack frame. */
 
@@ -53,16 +52,21 @@
                        (1<<BOOKE_INTERRUPT_PROGRAM) | \
                        (1<<BOOKE_INTERRUPT_DTLB_MISS))
 
-.macro KVM_HANDLER ivor_nr
+.macro KVM_HANDLER ivor_nr scratch srr0
 _GLOBAL(kvmppc_handler_\ivor_nr)
         /* Get pointer to vcpu and record exit number. */
-        mtspr   SPRN_SPRG_WSCRATCH0, r4
+        mtspr   \scratch , r4
         mfspr   r4, SPRN_SPRG_RVCPU
-        stw     r5, VCPU_GPR(r5)(r4)
-        stw     r6, VCPU_GPR(r6)(r4)
+        stw     r3, VCPU_GPR(R3)(r4)
+        stw     r5, VCPU_GPR(R5)(r4)
+        stw     r6, VCPU_GPR(R6)(r4)
+        mfspr   r3, \scratch
         mfctr   r5
-        lis     r6, kvmppc_resume_host@h
+        stw     r3, VCPU_GPR(R4)(r4)
         stw     r5, VCPU_CTR(r4)
+        mfspr   r3, \srr0
+        lis     r6, kvmppc_resume_host@h
+        stw     r3, VCPU_PC(r4)
         li      r5, \ivor_nr
         ori     r6, r6, kvmppc_resume_host@l
         mtctr   r6
@@ -70,42 +74,40 @@ _GLOBAL(kvmppc_handler_\ivor_nr)
 .endm
 
 _GLOBAL(kvmppc_handlers_start)
-KVM_HANDLER BOOKE_INTERRUPT_CRITICAL
-KVM_HANDLER BOOKE_INTERRUPT_MACHINE_CHECK
-KVM_HANDLER BOOKE_INTERRUPT_DATA_STORAGE
-KVM_HANDLER BOOKE_INTERRUPT_INST_STORAGE
-KVM_HANDLER BOOKE_INTERRUPT_EXTERNAL
-KVM_HANDLER BOOKE_INTERRUPT_ALIGNMENT
-KVM_HANDLER BOOKE_INTERRUPT_PROGRAM
-KVM_HANDLER BOOKE_INTERRUPT_FP_UNAVAIL
-KVM_HANDLER BOOKE_INTERRUPT_SYSCALL
-KVM_HANDLER BOOKE_INTERRUPT_AP_UNAVAIL
-KVM_HANDLER BOOKE_INTERRUPT_DECREMENTER
-KVM_HANDLER BOOKE_INTERRUPT_FIT
-KVM_HANDLER BOOKE_INTERRUPT_WATCHDOG
-KVM_HANDLER BOOKE_INTERRUPT_DTLB_MISS
-KVM_HANDLER BOOKE_INTERRUPT_ITLB_MISS
-KVM_HANDLER BOOKE_INTERRUPT_DEBUG
-KVM_HANDLER BOOKE_INTERRUPT_SPE_UNAVAIL
-KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_DATA
-KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_ROUND
+KVM_HANDLER BOOKE_INTERRUPT_CRITICAL SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
+KVM_HANDLER BOOKE_INTERRUPT_MACHINE_CHECK  SPRN_SPRG_RSCRATCH_MC SPRN_MCSRR0
+KVM_HANDLER BOOKE_INTERRUPT_DATA_STORAGE SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_INST_STORAGE SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_EXTERNAL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_ALIGNMENT SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_PROGRAM SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_FP_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_SYSCALL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_AP_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_DECREMENTER SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_FIT SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_WATCHDOG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
+KVM_HANDLER BOOKE_INTERRUPT_DTLB_MISS SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_ITLB_MISS SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_DEBUG SPRN_SPRG_RSCRATCH_CRIT SPRN_CSRR0
+KVM_HANDLER BOOKE_INTERRUPT_SPE_UNAVAIL SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_DATA SPRN_SPRG_RSCRATCH0 SPRN_SRR0
+KVM_HANDLER BOOKE_INTERRUPT_SPE_FP_ROUND SPRN_SPRG_RSCRATCH0 SPRN_SRR0
 
 _GLOBAL(kvmppc_handler_len)
         .long kvmppc_handler_1 - kvmppc_handler_0
 
-
 /* Registers:
  *  SPRG_SCRATCH0: guest r4
  *  r4: vcpu pointer
  *  r5: KVM exit number
  */
 _GLOBAL(kvmppc_resume_host)
-        stw     r3, VCPU_GPR(r3)(r4)
         mfcr    r3
         stw     r3, VCPU_CR(r4)
-        stw     r7, VCPU_GPR(r7)(r4)
-        stw     r8, VCPU_GPR(r8)(r4)
-        stw     r9, VCPU_GPR(r9)(r4)
+        stw     r7, VCPU_GPR(R7)(r4)
+        stw     r8, VCPU_GPR(R8)(r4)
+        stw     r9, VCPU_GPR(R9)(r4)
 
         li      r6, 1
         slw     r6, r6, r5
@@ -135,23 +137,23 @@ _GLOBAL(kvmppc_resume_host)
         isync
         stw     r9, VCPU_LAST_INST(r4)
 
-        stw     r15, VCPU_GPR(r15)(r4)
-        stw     r16, VCPU_GPR(r16)(r4)
-        stw     r17, VCPU_GPR(r17)(r4)
-        stw     r18, VCPU_GPR(r18)(r4)
-        stw     r19, VCPU_GPR(r19)(r4)
-        stw     r20, VCPU_GPR(r20)(r4)
-        stw     r21, VCPU_GPR(r21)(r4)
-        stw     r22, VCPU_GPR(r22)(r4)
-        stw     r23, VCPU_GPR(r23)(r4)
-        stw     r24, VCPU_GPR(r24)(r4)
-        stw     r25, VCPU_GPR(r25)(r4)
-        stw     r26, VCPU_GPR(r26)(r4)
-        stw     r27, VCPU_GPR(r27)(r4)
-        stw     r28, VCPU_GPR(r28)(r4)
-        stw     r29, VCPU_GPR(r29)(r4)
-        stw     r30, VCPU_GPR(r30)(r4)
-        stw     r31, VCPU_GPR(r31)(r4)
+        stw     r15, VCPU_GPR(R15)(r4)
+        stw     r16, VCPU_GPR(R16)(r4)
+        stw     r17, VCPU_GPR(R17)(r4)
+        stw     r18, VCPU_GPR(R18)(r4)
+        stw     r19, VCPU_GPR(R19)(r4)
+        stw     r20, VCPU_GPR(R20)(r4)
+        stw     r21, VCPU_GPR(R21)(r4)
+        stw     r22, VCPU_GPR(R22)(r4)
+        stw     r23, VCPU_GPR(R23)(r4)
+        stw     r24, VCPU_GPR(R24)(r4)
+        stw     r25, VCPU_GPR(R25)(r4)
+        stw     r26, VCPU_GPR(R26)(r4)
+        stw     r27, VCPU_GPR(R27)(r4)
+        stw     r28, VCPU_GPR(R28)(r4)
+        stw     r29, VCPU_GPR(R29)(r4)
+        stw     r30, VCPU_GPR(R30)(r4)
+        stw     r31, VCPU_GPR(R31)(r4)
 ..skip_inst_copy:
 
         /* Also grab DEAR and ESR before the host can clobber them. */
@@ -169,22 +171,18 @@ _GLOBAL(kvmppc_resume_host)
 ..skip_esr:
 
         /* Save remaining volatile guest register state to vcpu. */
-        stw     r0, VCPU_GPR(r0)(r4)
-        stw     r1, VCPU_GPR(r1)(r4)
-        stw     r2, VCPU_GPR(r2)(r4)
-        stw     r10, VCPU_GPR(r10)(r4)
-        stw     r11, VCPU_GPR(r11)(r4)
-        stw     r12, VCPU_GPR(r12)(r4)
-        stw     r13, VCPU_GPR(r13)(r4)
-        stw     r14, VCPU_GPR(r14)(r4) /* We need a NV GPR below. */
+        stw     r0, VCPU_GPR(R0)(r4)
+        stw     r1, VCPU_GPR(R1)(r4)
+        stw     r2, VCPU_GPR(R2)(r4)
+        stw     r10, VCPU_GPR(R10)(r4)
+        stw     r11, VCPU_GPR(R11)(r4)
+        stw     r12, VCPU_GPR(R12)(r4)
+        stw     r13, VCPU_GPR(R13)(r4)
+        stw     r14, VCPU_GPR(R14)(r4) /* We need a NV GPR below. */
         mflr    r3
         stw     r3, VCPU_LR(r4)
         mfxer   r3
         stw     r3, VCPU_XER(r4)
-        mfspr   r3, SPRN_SPRG_RSCRATCH0
-        stw     r3, VCPU_GPR(r4)(r4)
-        mfspr   r3, SPRN_SRR0
-        stw     r3, VCPU_PC(r4)
 
         /* Restore host stack pointer and PID before IVPR, since the host
          * exception handlers use them. */
@@ -214,28 +212,28 @@ _GLOBAL(kvmppc_resume_host)
 
         /* Restore vcpu pointer and the nonvolatiles we used. */
         mr      r4, r14
-        lwz     r14, VCPU_GPR(r14)(r4)
+        lwz     r14, VCPU_GPR(R14)(r4)
 
         /* Sometimes instruction emulation must restore complete GPR state. */
         andi.   r5, r3, RESUME_FLAG_NV
         beq     ..skip_nv_load
-        lwz     r15, VCPU_GPR(r15)(r4)
-        lwz     r16, VCPU_GPR(r16)(r4)
-        lwz     r17, VCPU_GPR(r17)(r4)
-        lwz     r18, VCPU_GPR(r18)(r4)
-        lwz     r19, VCPU_GPR(r19)(r4)
-        lwz     r20, VCPU_GPR(r20)(r4)
-        lwz     r21, VCPU_GPR(r21)(r4)
-        lwz     r22, VCPU_GPR(r22)(r4)
-        lwz     r23, VCPU_GPR(r23)(r4)
-        lwz     r24, VCPU_GPR(r24)(r4)
-        lwz     r25, VCPU_GPR(r25)(r4)
-        lwz     r26, VCPU_GPR(r26)(r4)
-        lwz     r27, VCPU_GPR(r27)(r4)
-        lwz     r28, VCPU_GPR(r28)(r4)
-        lwz     r29, VCPU_GPR(r29)(r4)
-        lwz     r30, VCPU_GPR(r30)(r4)
-        lwz     r31, VCPU_GPR(r31)(r4)
+        lwz     r15, VCPU_GPR(R15)(r4)
+        lwz     r16, VCPU_GPR(R16)(r4)
+        lwz     r17, VCPU_GPR(R17)(r4)
+        lwz     r18, VCPU_GPR(R18)(r4)
+        lwz     r19, VCPU_GPR(R19)(r4)
+        lwz     r20, VCPU_GPR(R20)(r4)
+        lwz     r21, VCPU_GPR(R21)(r4)
+        lwz     r22, VCPU_GPR(R22)(r4)
+        lwz     r23, VCPU_GPR(R23)(r4)
+        lwz     r24, VCPU_GPR(R24)(r4)
+        lwz     r25, VCPU_GPR(R25)(r4)
+        lwz     r26, VCPU_GPR(R26)(r4)
+        lwz     r27, VCPU_GPR(R27)(r4)
+        lwz     r28, VCPU_GPR(R28)(r4)
+        lwz     r29, VCPU_GPR(R29)(r4)
+        lwz     r30, VCPU_GPR(R30)(r4)
+        lwz     r31, VCPU_GPR(R31)(r4)
 ..skip_nv_load:
 
         /* Should we return to the guest? */
@@ -257,43 +255,43 @@ heavyweight_exit:
 
         /* We already saved guest volatile register state; now save the
          * non-volatiles. */
-        stw     r15, VCPU_GPR(r15)(r4)
-        stw     r16, VCPU_GPR(r16)(r4)
-        stw     r17, VCPU_GPR(r17)(r4)
-        stw     r18, VCPU_GPR(r18)(r4)
-        stw     r19, VCPU_GPR(r19)(r4)
-        stw     r20, VCPU_GPR(r20)(r4)
-        stw     r21, VCPU_GPR(r21)(r4)
-        stw     r22, VCPU_GPR(r22)(r4)
-        stw     r23, VCPU_GPR(r23)(r4)
-        stw     r24, VCPU_GPR(r24)(r4)
-        stw     r25, VCPU_GPR(r25)(r4)
-        stw     r26, VCPU_GPR(r26)(r4)
-        stw     r27, VCPU_GPR(r27)(r4)
-        stw     r28, VCPU_GPR(r28)(r4)
-        stw     r29, VCPU_GPR(r29)(r4)
-        stw     r30, VCPU_GPR(r30)(r4)
-        stw     r31, VCPU_GPR(r31)(r4)
+        stw     r15, VCPU_GPR(R15)(r4)
+        stw     r16, VCPU_GPR(R16)(r4)
+        stw     r17, VCPU_GPR(R17)(r4)
+        stw     r18, VCPU_GPR(R18)(r4)
+        stw     r19, VCPU_GPR(R19)(r4)
+        stw     r20, VCPU_GPR(R20)(r4)
+        stw     r21, VCPU_GPR(R21)(r4)
+        stw     r22, VCPU_GPR(R22)(r4)
+        stw     r23, VCPU_GPR(R23)(r4)
+        stw     r24, VCPU_GPR(R24)(r4)
+        stw     r25, VCPU_GPR(R25)(r4)
+        stw     r26, VCPU_GPR(R26)(r4)
+        stw     r27, VCPU_GPR(R27)(r4)
+        stw     r28, VCPU_GPR(R28)(r4)
+        stw     r29, VCPU_GPR(R29)(r4)
+        stw     r30, VCPU_GPR(R30)(r4)
+        stw     r31, VCPU_GPR(R31)(r4)
 
         /* Load host non-volatile register state from host stack. */
-        lwz     r14, HOST_NV_GPR(r14)(r1)
-        lwz     r15, HOST_NV_GPR(r15)(r1)
-        lwz     r16, HOST_NV_GPR(r16)(r1)
-        lwz     r17, HOST_NV_GPR(r17)(r1)
-        lwz     r18, HOST_NV_GPR(r18)(r1)
-        lwz     r19, HOST_NV_GPR(r19)(r1)
-        lwz     r20, HOST_NV_GPR(r20)(r1)
-        lwz     r21, HOST_NV_GPR(r21)(r1)
-        lwz     r22, HOST_NV_GPR(r22)(r1)
-        lwz     r23, HOST_NV_GPR(r23)(r1)
-        lwz     r24, HOST_NV_GPR(r24)(r1)
-        lwz     r25, HOST_NV_GPR(r25)(r1)
-        lwz     r26, HOST_NV_GPR(r26)(r1)
-        lwz     r27, HOST_NV_GPR(r27)(r1)
-        lwz     r28, HOST_NV_GPR(r28)(r1)
-        lwz     r29, HOST_NV_GPR(r29)(r1)
-        lwz     r30, HOST_NV_GPR(r30)(r1)
-        lwz     r31, HOST_NV_GPR(r31)(r1)
+        lwz     r14, HOST_NV_GPR(R14)(r1)
+        lwz     r15, HOST_NV_GPR(R15)(r1)
+        lwz     r16, HOST_NV_GPR(R16)(r1)
+        lwz     r17, HOST_NV_GPR(R17)(r1)
+        lwz     r18, HOST_NV_GPR(R18)(r1)
+        lwz     r19, HOST_NV_GPR(R19)(r1)
+        lwz     r20, HOST_NV_GPR(R20)(r1)
+        lwz     r21, HOST_NV_GPR(R21)(r1)
+        lwz     r22, HOST_NV_GPR(R22)(r1)
+        lwz     r23, HOST_NV_GPR(R23)(r1)
+        lwz     r24, HOST_NV_GPR(R24)(r1)
+        lwz     r25, HOST_NV_GPR(R25)(r1)
+        lwz     r26, HOST_NV_GPR(R26)(r1)
+        lwz     r27, HOST_NV_GPR(R27)(r1)
+        lwz     r28, HOST_NV_GPR(R28)(r1)
+        lwz     r29, HOST_NV_GPR(R29)(r1)
+        lwz     r30, HOST_NV_GPR(R30)(r1)
+        lwz     r31, HOST_NV_GPR(R31)(r1)
 
         /* Return to kvm_vcpu_run(). */
         lwz     r4, HOST_STACK_LR(r1)
@@ -321,44 +319,44 @@ _GLOBAL(__kvmppc_vcpu_run)
         stw     r5, HOST_CR(r1)
 
         /* Save host non-volatile register state to stack. */
-        stw     r14, HOST_NV_GPR(r14)(r1)
-        stw     r15, HOST_NV_GPR(r15)(r1)
-        stw     r16, HOST_NV_GPR(r16)(r1)
-        stw     r17, HOST_NV_GPR(r17)(r1)
-        stw     r18, HOST_NV_GPR(r18)(r1)
-        stw     r19, HOST_NV_GPR(r19)(r1)
-        stw     r20, HOST_NV_GPR(r20)(r1)
-        stw     r21, HOST_NV_GPR(r21)(r1)
-        stw     r22, HOST_NV_GPR(r22)(r1)
-        stw     r23, HOST_NV_GPR(r23)(r1)
-        stw     r24, HOST_NV_GPR(r24)(r1)
-        stw     r25, HOST_NV_GPR(r25)(r1)
-        stw     r26, HOST_NV_GPR(r26)(r1)
-        stw     r27, HOST_NV_GPR(r27)(r1)
-        stw     r28, HOST_NV_GPR(r28)(r1)
-        stw     r29, HOST_NV_GPR(r29)(r1)
-        stw     r30, HOST_NV_GPR(r30)(r1)
-        stw     r31, HOST_NV_GPR(r31)(r1)
+        stw     r14, HOST_NV_GPR(R14)(r1)
+        stw     r15, HOST_NV_GPR(R15)(r1)
+        stw     r16, HOST_NV_GPR(R16)(r1)
+        stw     r17, HOST_NV_GPR(R17)(r1)
+        stw     r18, HOST_NV_GPR(R18)(r1)
+        stw     r19, HOST_NV_GPR(R19)(r1)
+        stw     r20, HOST_NV_GPR(R20)(r1)
+        stw     r21, HOST_NV_GPR(R21)(r1)
+        stw     r22, HOST_NV_GPR(R22)(r1)
+        stw     r23, HOST_NV_GPR(R23)(r1)
+        stw     r24, HOST_NV_GPR(R24)(r1)
+        stw     r25, HOST_NV_GPR(R25)(r1)
+        stw     r26, HOST_NV_GPR(R26)(r1)
+        stw     r27, HOST_NV_GPR(R27)(r1)
+        stw     r28, HOST_NV_GPR(R28)(r1)
+        stw     r29, HOST_NV_GPR(R29)(r1)
+        stw     r30, HOST_NV_GPR(R30)(r1)
+        stw     r31, HOST_NV_GPR(R31)(r1)
 
         /* Load guest non-volatiles. */
-        lwz     r14, VCPU_GPR(r14)(r4)
-        lwz     r15, VCPU_GPR(r15)(r4)
-        lwz     r16, VCPU_GPR(r16)(r4)
-        lwz     r17, VCPU_GPR(r17)(r4)
-        lwz     r18, VCPU_GPR(r18)(r4)
-        lwz     r19, VCPU_GPR(r19)(r4)
-        lwz     r20, VCPU_GPR(r20)(r4)
-        lwz     r21, VCPU_GPR(r21)(r4)
-        lwz     r22, VCPU_GPR(r22)(r4)
-        lwz     r23, VCPU_GPR(r23)(r4)
-        lwz     r24, VCPU_GPR(r24)(r4)
-        lwz     r25, VCPU_GPR(r25)(r4)
-        lwz     r26, VCPU_GPR(r26)(r4)
-        lwz     r27, VCPU_GPR(r27)(r4)
-        lwz     r28, VCPU_GPR(r28)(r4)
-        lwz     r29, VCPU_GPR(r29)(r4)
-        lwz     r30, VCPU_GPR(r30)(r4)
-        lwz     r31, VCPU_GPR(r31)(r4)
+        lwz     r14, VCPU_GPR(R14)(r4)
+        lwz     r15, VCPU_GPR(R15)(r4)
+        lwz     r16, VCPU_GPR(R16)(r4)
+        lwz     r17, VCPU_GPR(R17)(r4)
+        lwz     r18, VCPU_GPR(R18)(r4)
+        lwz     r19, VCPU_GPR(R19)(r4)
+        lwz     r20, VCPU_GPR(R20)(r4)
+        lwz     r21, VCPU_GPR(R21)(r4)
+        lwz     r22, VCPU_GPR(R22)(r4)
+        lwz     r23, VCPU_GPR(R23)(r4)
+        lwz     r24, VCPU_GPR(R24)(r4)
+        lwz     r25, VCPU_GPR(R25)(r4)
+        lwz     r26, VCPU_GPR(R26)(r4)
+        lwz     r27, VCPU_GPR(R27)(r4)
+        lwz     r28, VCPU_GPR(R28)(r4)
+        lwz     r29, VCPU_GPR(R29)(r4)
+        lwz     r30, VCPU_GPR(R30)(r4)
+        lwz     r31, VCPU_GPR(R31)(r4)
 
 #ifdef CONFIG_SPE
         /* save host SPEFSCR and load guest SPEFSCR */
@@ -386,13 +384,13 @@ lightweight_exit:
 #endif
 
         /* Load some guest volatiles. */
-        lwz     r0, VCPU_GPR(r0)(r4)
-        lwz     r2, VCPU_GPR(r2)(r4)
-        lwz     r9, VCPU_GPR(r9)(r4)
-        lwz     r10, VCPU_GPR(r10)(r4)
-        lwz     r11, VCPU_GPR(r11)(r4)
-        lwz     r12, VCPU_GPR(r12)(r4)
-        lwz     r13, VCPU_GPR(r13)(r4)
+        lwz     r0, VCPU_GPR(R0)(r4)
+        lwz     r2, VCPU_GPR(R2)(r4)
+        lwz     r9, VCPU_GPR(R9)(r4)
+        lwz     r10, VCPU_GPR(R10)(r4)
+        lwz     r11, VCPU_GPR(R11)(r4)
+        lwz     r12, VCPU_GPR(R12)(r4)
+        lwz     r13, VCPU_GPR(R13)(r4)
         lwz     r3, VCPU_LR(r4)
         mtlr    r3
         lwz     r3, VCPU_XER(r4)
@@ -411,7 +409,7 @@ lightweight_exit:
 
         /* Can't switch the stack pointer until after IVPR is switched,
          * because host interrupt handlers would get confused. */
-        lwz     r1, VCPU_GPR(r1)(r4)
+        lwz     r1, VCPU_GPR(R1)(r4)
 
         /*
          * Host interrupt handlers may have clobbered these
@@ -449,10 +447,10 @@ lightweight_exit:
         mtcr    r5
         mtsrr0  r6
         mtsrr1  r7
-        lwz     r5, VCPU_GPR(r5)(r4)
-        lwz     r6, VCPU_GPR(r6)(r4)
-        lwz     r7, VCPU_GPR(r7)(r4)
-        lwz     r8, VCPU_GPR(r8)(r4)
+        lwz     r5, VCPU_GPR(R5)(r4)
+        lwz     r6, VCPU_GPR(R6)(r4)
+        lwz     r7, VCPU_GPR(R7)(r4)
+        lwz     r8, VCPU_GPR(R8)(r4)
 
         /* Clear any debug events which occurred since we disabled MSR[DE].
          * XXX This gives us a 3-instruction window in which a breakpoint
@@ -461,8 +459,8 @@ lightweight_exit:
         ori     r3, r3, 0xffff
         mtspr   SPRN_DBSR, r3
 
-        lwz     r3, VCPU_GPR(r3)(r4)
-        lwz     r4, VCPU_GPR(r4)(r4)
+        lwz     r3, VCPU_GPR(R3)(r4)
+        lwz     r4, VCPU_GPR(R4)(r4)
         rfi
 
 #ifdef CONFIG_SPE
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S
index 6048a00515d..099fe8272b5 100644
--- a/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/arch/powerpc/kvm/bookehv_interrupts.S
@@ -37,7 +37,6 @@
 
 #define LONGBYTES               (BITS_PER_LONG / 8)
 
-#define VCPU_GPR(n)             (VCPU_GPRS + (n * LONGBYTES))
 #define VCPU_GUEST_SPRG(n)      (VCPU_GUEST_SPRGS + (n * LONGBYTES))
 
 /* The host stack layout: */
@@ -51,8 +50,9 @@
 #define HOST_R2         (3 * LONGBYTES)
 #define HOST_CR         (4 * LONGBYTES)
 #define HOST_NV_GPRS    (5 * LONGBYTES)
-#define HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
-#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(31) + LONGBYTES)
+#define __HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
+#define HOST_NV_GPR(n)  __HOST_NV_GPR(__REG_##n)
+#define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + LONGBYTES)
 #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
 #define HOST_STACK_LR   (HOST_STACK_SIZE + LONGBYTES) /* In caller stack frame. */
 
@@ -67,15 +67,15 @@
  */
 .macro kvm_handler_common intno, srr0, flags
         /* Restore host stack pointer */
-        PPC_STL r1, VCPU_GPR(r1)(r4)
-        PPC_STL r2, VCPU_GPR(r2)(r4)
+        PPC_STL r1, VCPU_GPR(R1)(r4)
+        PPC_STL r2, VCPU_GPR(R2)(r4)
         PPC_LL  r1, VCPU_HOST_STACK(r4)
         PPC_LL  r2, HOST_R2(r1)
 
         mfspr   r10, SPRN_PID
         lwz     r8, VCPU_HOST_PID(r4)
         PPC_LL  r11, VCPU_SHARED(r4)
-        PPC_STL r14, VCPU_GPR(r14)(r4) /* We need a non-volatile GPR. */
+        PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */
         li      r14, \intno
 
         stw     r10, VCPU_GUEST_PID(r4)
@@ -137,35 +137,31 @@
          */
 
         mfspr   r3, SPRN_EPLC   /* will already have correct ELPID and EGS */
-        PPC_STL r15, VCPU_GPR(r15)(r4)
-        PPC_STL r16, VCPU_GPR(r16)(r4)
-        PPC_STL r17, VCPU_GPR(r17)(r4)
-        PPC_STL r18, VCPU_GPR(r18)(r4)
-        PPC_STL r19, VCPU_GPR(r19)(r4)
+        PPC_STL r15, VCPU_GPR(R15)(r4)
+        PPC_STL r16, VCPU_GPR(R16)(r4)
+        PPC_STL r17, VCPU_GPR(R17)(r4)
+        PPC_STL r18, VCPU_GPR(R18)(r4)
+        PPC_STL r19, VCPU_GPR(R19)(r4)
         mr      r8, r3
-        PPC_STL r20, VCPU_GPR(r20)(r4)
+        PPC_STL r20, VCPU_GPR(R20)(r4)
         rlwimi  r8, r6, EPC_EAS_SHIFT - MSR_IR_LG, EPC_EAS
-        PPC_STL r21, VCPU_GPR(r21)(r4)
+        PPC_STL r21, VCPU_GPR(R21)(r4)
         rlwimi  r8, r6, EPC_EPR_SHIFT - MSR_PR_LG, EPC_EPR
-        PPC_STL r22, VCPU_GPR(r22)(r4)
+        PPC_STL r22, VCPU_GPR(R22)(r4)
         rlwimi  r8, r10, EPC_EPID_SHIFT, EPC_EPID
-        PPC_STL r23, VCPU_GPR(r23)(r4)
-        PPC_STL r24, VCPU_GPR(r24)(r4)
-        PPC_STL r25, VCPU_GPR(r25)(r4)
-        PPC_STL r26, VCPU_GPR(r26)(r4)
-        PPC_STL r27, VCPU_GPR(r27)(r4)
-        PPC_STL r28, VCPU_GPR(r28)(r4)
-        PPC_STL r29, VCPU_GPR(r29)(r4)
-        PPC_STL r30, VCPU_GPR(r30)(r4)
-        PPC_STL r31, VCPU_GPR(r31)(r4)
+        PPC_STL r23, VCPU_GPR(R23)(r4)
+        PPC_STL r24, VCPU_GPR(R24)(r4)
+        PPC_STL r25, VCPU_GPR(R25)(r4)
+        PPC_STL r26, VCPU_GPR(R26)(r4)
+        PPC_STL r27, VCPU_GPR(R27)(r4)
+        PPC_STL r28, VCPU_GPR(R28)(r4)
+        PPC_STL r29, VCPU_GPR(R29)(r4)
+        PPC_STL r30, VCPU_GPR(R30)(r4)
+        PPC_STL r31, VCPU_GPR(R31)(r4)
         mtspr   SPRN_EPLC, r8
 
         /* disable preemption, so we are sure we hit the fixup handler */
-#ifdef CONFIG_PPC64
-        clrrdi  r8,r1,THREAD_SHIFT
-#else
-        rlwinm  r8,r1,0,0,31-THREAD_SHIFT       /* current thread_info */
-#endif
+        CURRENT_THREAD_INFO(r8, r1)
         li      r7, 1
         stw     r7, TI_PREEMPT(r8)
 
@@ -211,24 +207,24 @@
 .macro kvm_handler intno srr0, srr1, flags
 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
         GET_VCPU(r11, r10)
-        PPC_STL r3, VCPU_GPR(r3)(r11)
+        PPC_STL r3, VCPU_GPR(R3)(r11)
         mfspr   r3, SPRN_SPRG_RSCRATCH0
-        PPC_STL r4, VCPU_GPR(r4)(r11)
+        PPC_STL r4, VCPU_GPR(R4)(r11)
         PPC_LL  r4, THREAD_NORMSAVE(0)(r10)
-        PPC_STL r5, VCPU_GPR(r5)(r11)
+        PPC_STL r5, VCPU_GPR(R5)(r11)
         stw     r13, VCPU_CR(r11)
         mfspr   r5, \srr0
-        PPC_STL r3, VCPU_GPR(r10)(r11)
+        PPC_STL r3, VCPU_GPR(R10)(r11)
         PPC_LL  r3, THREAD_NORMSAVE(2)(r10)
-        PPC_STL r6, VCPU_GPR(r6)(r11)
-        PPC_STL r4, VCPU_GPR(r11)(r11)
+        PPC_STL r6, VCPU_GPR(R6)(r11)
+        PPC_STL r4, VCPU_GPR(R11)(r11)
         mfspr   r6, \srr1
-        PPC_STL r7, VCPU_GPR(r7)(r11)
-        PPC_STL r8, VCPU_GPR(r8)(r11)
-        PPC_STL r9, VCPU_GPR(r9)(r11)
-        PPC_STL r3, VCPU_GPR(r13)(r11)
+        PPC_STL r7, VCPU_GPR(R7)(r11)
+        PPC_STL r8, VCPU_GPR(R8)(r11)
+        PPC_STL r9, VCPU_GPR(R9)(r11)
+        PPC_STL r3, VCPU_GPR(R13)(r11)
         mfctr   r7
-        PPC_STL r12, VCPU_GPR(r12)(r11)
+        PPC_STL r12, VCPU_GPR(R12)(r11)
         PPC_STL r7, VCPU_CTR(r11)
         mr      r4, r11
         kvm_handler_common \intno, \srr0, \flags
@@ -238,25 +234,25 @@ _GLOBAL(kvmppc_handler_\intno\()_\srr1)
 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
         mfspr   r10, SPRN_SPRG_THREAD
         GET_VCPU(r11, r10)
-        PPC_STL r3, VCPU_GPR(r3)(r11)
+        PPC_STL r3, VCPU_GPR(R3)(r11)
         mfspr   r3, \scratch
-        PPC_STL r4, VCPU_GPR(r4)(r11)
+        PPC_STL r4, VCPU_GPR(R4)(r11)
         PPC_LL  r4, GPR9(r8)
-        PPC_STL r5, VCPU_GPR(r5)(r11)
+        PPC_STL r5, VCPU_GPR(R5)(r11)
         stw     r9, VCPU_CR(r11)
         mfspr   r5, \srr0
-        PPC_STL r3, VCPU_GPR(r8)(r11)
+        PPC_STL r3, VCPU_GPR(R8)(r11)
         PPC_LL  r3, GPR10(r8)
-        PPC_STL r6, VCPU_GPR(r6)(r11)
-        PPC_STL r4, VCPU_GPR(r9)(r11)
+        PPC_STL r6, VCPU_GPR(R6)(r11)
+        PPC_STL r4, VCPU_GPR(R9)(r11)
         mfspr   r6, \srr1
         PPC_LL  r4, GPR11(r8)
-        PPC_STL r7, VCPU_GPR(r7)(r11)
-        PPC_STL r3, VCPU_GPR(r10)(r11)
+        PPC_STL r7, VCPU_GPR(R7)(r11)
+        PPC_STL r3, VCPU_GPR(R10)(r11)
         mfctr   r7
-        PPC_STL r12, VCPU_GPR(r12)(r11)
-        PPC_STL r13, VCPU_GPR(r13)(r11)
-        PPC_STL r4, VCPU_GPR(r11)(r11)
+        PPC_STL r12, VCPU_GPR(R12)(r11)
+        PPC_STL r13, VCPU_GPR(R13)(r11)
+        PPC_STL r4, VCPU_GPR(R11)(r11)
         PPC_STL r7, VCPU_CTR(r11)
         mr      r4, r11
         kvm_handler_common \intno, \srr0, \flags
@@ -267,7 +263,7 @@ kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
 kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
         SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
 kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
-        SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR)
+        SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
 kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
 kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
@@ -310,7 +306,7 @@ kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
 _GLOBAL(kvmppc_resume_host)
         /* Save remaining volatile guest register state to vcpu. */
         mfspr   r3, SPRN_VRSAVE
-        PPC_STL r0, VCPU_GPR(r0)(r4)
+        PPC_STL r0, VCPU_GPR(R0)(r4)
         mflr    r5
         mfspr   r6, SPRN_SPRG4
         PPC_STL r5, VCPU_LR(r4)
@@ -358,27 +354,27 @@ _GLOBAL(kvmppc_resume_host)
 
         /* Restore vcpu pointer and the nonvolatiles we used. */
         mr      r4, r14
-        PPC_LL  r14, VCPU_GPR(r14)(r4)
+        PPC_LL  r14, VCPU_GPR(R14)(r4)
 
         andi.   r5, r3, RESUME_FLAG_NV
         beq     skip_nv_load
-        PPC_LL  r15, VCPU_GPR(r15)(r4)
-        PPC_LL  r16, VCPU_GPR(r16)(r4)
-        PPC_LL  r17, VCPU_GPR(r17)(r4)
-        PPC_LL  r18, VCPU_GPR(r18)(r4)
-        PPC_LL  r19, VCPU_GPR(r19)(r4)
-        PPC_LL  r20, VCPU_GPR(r20)(r4)
-        PPC_LL  r21, VCPU_GPR(r21)(r4)
-        PPC_LL  r22, VCPU_GPR(r22)(r4)
-        PPC_LL  r23, VCPU_GPR(r23)(r4)
-        PPC_LL  r24, VCPU_GPR(r24)(r4)
-        PPC_LL  r25, VCPU_GPR(r25)(r4)
-        PPC_LL  r26, VCPU_GPR(r26)(r4)
-        PPC_LL  r27, VCPU_GPR(r27)(r4)
-        PPC_LL  r28, VCPU_GPR(r28)(r4)
-        PPC_LL  r29, VCPU_GPR(r29)(r4)
-        PPC_LL  r30, VCPU_GPR(r30)(r4)
-        PPC_LL  r31, VCPU_GPR(r31)(r4)
+        PPC_LL  r15, VCPU_GPR(R15)(r4)
+        PPC_LL  r16, VCPU_GPR(R16)(r4)
+        PPC_LL  r17, VCPU_GPR(R17)(r4)
+        PPC_LL  r18, VCPU_GPR(R18)(r4)
+        PPC_LL  r19, VCPU_GPR(R19)(r4)
+        PPC_LL  r20, VCPU_GPR(R20)(r4)
+        PPC_LL  r21, VCPU_GPR(R21)(r4)
+        PPC_LL  r22, VCPU_GPR(R22)(r4)
+        PPC_LL  r23, VCPU_GPR(R23)(r4)
+        PPC_LL  r24, VCPU_GPR(R24)(r4)
+        PPC_LL  r25, VCPU_GPR(R25)(r4)
+        PPC_LL  r26, VCPU_GPR(R26)(r4)
+        PPC_LL  r27, VCPU_GPR(R27)(r4)
+        PPC_LL  r28, VCPU_GPR(R28)(r4)
+        PPC_LL  r29, VCPU_GPR(R29)(r4)
+        PPC_LL  r30, VCPU_GPR(R30)(r4)
+        PPC_LL  r31, VCPU_GPR(R31)(r4)
 skip_nv_load:
         /* Should we return to the guest? */
         andi.   r5, r3, RESUME_FLAG_HOST
@@ -396,43 +392,43 @@ heavyweight_exit:
          * non-volatiles.
          */
 
-        PPC_STL r15, VCPU_GPR(r15)(r4)
-        PPC_STL r16, VCPU_GPR(r16)(r4)
-        PPC_STL r17, VCPU_GPR(r17)(r4)
-        PPC_STL r18, VCPU_GPR(r18)(r4)
-        PPC_STL r19, VCPU_GPR(r19)(r4)
-        PPC_STL r20, VCPU_GPR(r20)(r4)
-        PPC_STL r21, VCPU_GPR(r21)(r4)
-        PPC_STL r22, VCPU_GPR(r22)(r4)
-        PPC_STL r23, VCPU_GPR(r23)(r4)
-        PPC_STL r24, VCPU_GPR(r24)(r4)
-        PPC_STL r25, VCPU_GPR(r25)(r4)
-        PPC_STL r26, VCPU_GPR(r26)(r4)
-        PPC_STL r27, VCPU_GPR(r27)(r4)
-        PPC_STL r28, VCPU_GPR(r28)(r4)
-        PPC_STL r29, VCPU_GPR(r29)(r4)
-        PPC_STL r30, VCPU_GPR(r30)(r4)
-        PPC_STL r31, VCPU_GPR(r31)(r4)
+        PPC_STL r15, VCPU_GPR(R15)(r4)
+        PPC_STL r16, VCPU_GPR(R16)(r4)
+        PPC_STL r17, VCPU_GPR(R17)(r4)
+        PPC_STL r18, VCPU_GPR(R18)(r4)
+        PPC_STL r19, VCPU_GPR(R19)(r4)
+        PPC_STL r20, VCPU_GPR(R20)(r4)
+        PPC_STL r21, VCPU_GPR(R21)(r4)
+        PPC_STL r22, VCPU_GPR(R22)(r4)
+        PPC_STL r23, VCPU_GPR(R23)(r4)
+        PPC_STL r24, VCPU_GPR(R24)(r4)
+        PPC_STL r25, VCPU_GPR(R25)(r4)
+        PPC_STL r26, VCPU_GPR(R26)(r4)
+        PPC_STL r27, VCPU_GPR(R27)(r4)
+        PPC_STL r28, VCPU_GPR(R28)(r4)
+        PPC_STL r29, VCPU_GPR(R29)(r4)
+        PPC_STL r30, VCPU_GPR(R30)(r4)
+        PPC_STL r31, VCPU_GPR(R31)(r4)
 
         /* Load host non-volatile register state from host stack. */
-        PPC_LL  r14, HOST_NV_GPR(r14)(r1)
-        PPC_LL  r15, HOST_NV_GPR(r15)(r1)
-        PPC_LL  r16, HOST_NV_GPR(r16)(r1)
-        PPC_LL  r17, HOST_NV_GPR(r17)(r1)
-        PPC_LL  r18, HOST_NV_GPR(r18)(r1)
-        PPC_LL  r19, HOST_NV_GPR(r19)(r1)
-        PPC_LL  r20, HOST_NV_GPR(r20)(r1)
-        PPC_LL  r21, HOST_NV_GPR(r21)(r1)
-        PPC_LL  r22, HOST_NV_GPR(r22)(r1)
-        PPC_LL  r23, HOST_NV_GPR(r23)(r1)
-        PPC_LL  r24, HOST_NV_GPR(r24)(r1)
-        PPC_LL  r25, HOST_NV_GPR(r25)(r1)
-        PPC_LL  r26, HOST_NV_GPR(r26)(r1)
-        PPC_LL  r27, HOST_NV_GPR(r27)(r1)
-        PPC_LL  r28, HOST_NV_GPR(r28)(r1)
-        PPC_LL  r29, HOST_NV_GPR(r29)(r1)
-        PPC_LL  r30, HOST_NV_GPR(r30)(r1)
-        PPC_LL  r31, HOST_NV_GPR(r31)(r1)
+        PPC_LL  r14, HOST_NV_GPR(R14)(r1)
+        PPC_LL  r15, HOST_NV_GPR(R15)(r1)
+        PPC_LL  r16, HOST_NV_GPR(R16)(r1)
+        PPC_LL  r17, HOST_NV_GPR(R17)(r1)
+        PPC_LL  r18, HOST_NV_GPR(R18)(r1)
+        PPC_LL  r19, HOST_NV_GPR(R19)(r1)
+        PPC_LL  r20, HOST_NV_GPR(R20)(r1)
+        PPC_LL  r21, HOST_NV_GPR(R21)(r1)
+        PPC_LL  r22, HOST_NV_GPR(R22)(r1)
+        PPC_LL  r23, HOST_NV_GPR(R23)(r1)
+        PPC_LL  r24, HOST_NV_GPR(R24)(r1)
+        PPC_LL  r25, HOST_NV_GPR(R25)(r1)
+        PPC_LL  r26, HOST_NV_GPR(R26)(r1)
+        PPC_LL  r27, HOST_NV_GPR(R27)(r1)
+        PPC_LL  r28, HOST_NV_GPR(R28)(r1)
+        PPC_LL  r29, HOST_NV_GPR(R29)(r1)
+        PPC_LL  r30, HOST_NV_GPR(R30)(r1)
+        PPC_LL  r31, HOST_NV_GPR(R31)(r1)
 
         /* Return to kvm_vcpu_run(). */
         mtlr    r5
@@ -458,44 +454,44 @@ _GLOBAL(__kvmppc_vcpu_run)
         stw     r5, HOST_CR(r1)
 
         /* Save host non-volatile register state to stack. */
-        PPC_STL r14, HOST_NV_GPR(r14)(r1)
-        PPC_STL r15, HOST_NV_GPR(r15)(r1)
-        PPC_STL r16, HOST_NV_GPR(r16)(r1)
-        PPC_STL r17, HOST_NV_GPR(r17)(r1)
-        PPC_STL r18, HOST_NV_GPR(r18)(r1)
-        PPC_STL r19, HOST_NV_GPR(r19)(r1)
-        PPC_STL r20, HOST_NV_GPR(r20)(r1)
-        PPC_STL r21, HOST_NV_GPR(r21)(r1)
-        PPC_STL r22, HOST_NV_GPR(r22)(r1)
-        PPC_STL r23, HOST_NV_GPR(r23)(r1)
-        PPC_STL r24, HOST_NV_GPR(r24)(r1)
-        PPC_STL r25, HOST_NV_GPR(r25)(r1)
-        PPC_STL r26, HOST_NV_GPR(r26)(r1)
-        PPC_STL r27, HOST_NV_GPR(r27)(r1)
-        PPC_STL r28, HOST_NV_GPR(r28)(r1)
-        PPC_STL r29, HOST_NV_GPR(r29)(r1)
-        PPC_STL r30, HOST_NV_GPR(r30)(r1)
-        PPC_STL r31, HOST_NV_GPR(r31)(r1)
+        PPC_STL r14, HOST_NV_GPR(R14)(r1)
+        PPC_STL r15, HOST_NV_GPR(R15)(r1)
+        PPC_STL r16, HOST_NV_GPR(R16)(r1)
+        PPC_STL r17, HOST_NV_GPR(R17)(r1)
+        PPC_STL r18, HOST_NV_GPR(R18)(r1)
+        PPC_STL r19, HOST_NV_GPR(R19)(r1)
+        PPC_STL r20, HOST_NV_GPR(R20)(r1)
+        PPC_STL r21, HOST_NV_GPR(R21)(r1)
+        PPC_STL r22, HOST_NV_GPR(R22)(r1)
+        PPC_STL r23, HOST_NV_GPR(R23)(r1)
+        PPC_STL r24, HOST_NV_GPR(R24)(r1)
+        PPC_STL r25, HOST_NV_GPR(R25)(r1)
+        PPC_STL r26, HOST_NV_GPR(R26)(r1)
+        PPC_STL r27, HOST_NV_GPR(R27)(r1)
+        PPC_STL r28, HOST_NV_GPR(R28)(r1)
+        PPC_STL r29, HOST_NV_GPR(R29)(r1)
+        PPC_STL r30, HOST_NV_GPR(R30)(r1)
+        PPC_STL r31, HOST_NV_GPR(R31)(r1)
 
         /* Load guest non-volatiles. */
-        PPC_LL  r14, VCPU_GPR(r14)(r4)
-        PPC_LL  r15, VCPU_GPR(r15)(r4)
-        PPC_LL  r16, VCPU_GPR(r16)(r4)
-        PPC_LL  r17, VCPU_GPR(r17)(r4)
-        PPC_LL  r18, VCPU_GPR(r18)(r4)
-        PPC_LL  r19, VCPU_GPR(r19)(r4)
-        PPC_LL  r20, VCPU_GPR(r20)(r4)
-        PPC_LL  r21, VCPU_GPR(r21)(r4)
-        PPC_LL  r22, VCPU_GPR(r22)(r4)
-        PPC_LL  r23, VCPU_GPR(r23)(r4)
-        PPC_LL  r24, VCPU_GPR(r24)(r4)
-        PPC_LL  r25, VCPU_GPR(r25)(r4)
-        PPC_LL  r26, VCPU_GPR(r26)(r4)
-        PPC_LL  r27, VCPU_GPR(r27)(r4)
-        PPC_LL  r28, VCPU_GPR(r28)(r4)
-        PPC_LL  r29, VCPU_GPR(r29)(r4)
-        PPC_LL  r30, VCPU_GPR(r30)(r4)
-        PPC_LL  r31, VCPU_GPR(r31)(r4)
+        PPC_LL  r14, VCPU_GPR(R14)(r4)
+        PPC_LL  r15, VCPU_GPR(R15)(r4)
+        PPC_LL  r16, VCPU_GPR(R16)(r4)
+        PPC_LL  r17, VCPU_GPR(R17)(r4)
+        PPC_LL  r18, VCPU_GPR(R18)(r4)
+        PPC_LL  r19, VCPU_GPR(R19)(r4)
+        PPC_LL  r20, VCPU_GPR(R20)(r4)
+        PPC_LL  r21, VCPU_GPR(R21)(r4)
+        PPC_LL  r22, VCPU_GPR(R22)(r4)
+        PPC_LL  r23, VCPU_GPR(R23)(r4)
+        PPC_LL  r24, VCPU_GPR(R24)(r4)
+        PPC_LL  r25, VCPU_GPR(R25)(r4)
+        PPC_LL  r26, VCPU_GPR(R26)(r4)
+        PPC_LL  r27, VCPU_GPR(R27)(r4)
+        PPC_LL  r28, VCPU_GPR(R28)(r4)
+        PPC_LL  r29, VCPU_GPR(R29)(r4)
+        PPC_LL  r30, VCPU_GPR(R30)(r4)
+        PPC_LL  r31, VCPU_GPR(R31)(r4)
 
 
 lightweight_exit:
@@ -554,13 +550,13 @@ lightweight_exit:
         lwz     r7, VCPU_CR(r4)
         PPC_LL  r8, VCPU_PC(r4)
         PPC_LD(r9, VCPU_SHARED_MSR, r11)
-        PPC_LL  r0, VCPU_GPR(r0)(r4)
-        PPC_LL  r1, VCPU_GPR(r1)(r4)
-        PPC_LL  r2, VCPU_GPR(r2)(r4)
-        PPC_LL  r10, VCPU_GPR(r10)(r4)
-        PPC_LL  r11, VCPU_GPR(r11)(r4)
-        PPC_LL  r12, VCPU_GPR(r12)(r4)
-        PPC_LL  r13, VCPU_GPR(r13)(r4)
+        PPC_LL  r0, VCPU_GPR(R0)(r4)
+        PPC_LL  r1, VCPU_GPR(R1)(r4)
+        PPC_LL  r2, VCPU_GPR(R2)(r4)
+        PPC_LL  r10, VCPU_GPR(R10)(r4)
+        PPC_LL  r11, VCPU_GPR(R11)(r4)
+        PPC_LL  r12, VCPU_GPR(R12)(r4)
+        PPC_LL  r13, VCPU_GPR(R13)(r4)
         mtlr    r3
         mtxer   r5
         mtctr   r6
@@ -586,12 +582,12 @@ lightweight_exit:
         mtcr    r7
 
         /* Finish loading guest volatiles and jump to guest. */
-        PPC_LL  r5, VCPU_GPR(r5)(r4)
-        PPC_LL  r6, VCPU_GPR(r6)(r4)
-        PPC_LL  r7, VCPU_GPR(r7)(r4)
-        PPC_LL  r8, VCPU_GPR(r8)(r4)
-        PPC_LL  r9, VCPU_GPR(r9)(r4)
-
-        PPC_LL  r3, VCPU_GPR(r3)(r4)
-        PPC_LL  r4, VCPU_GPR(r4)(r4)
+        PPC_LL  r5, VCPU_GPR(R5)(r4)
+        PPC_LL  r6, VCPU_GPR(R6)(r4)
+        PPC_LL  r7, VCPU_GPR(R7)(r4)
+        PPC_LL  r8, VCPU_GPR(R8)(r4)
+        PPC_LL  r9, VCPU_GPR(R9)(r4)
+
+        PPC_LL  r3, VCPU_GPR(R3)(r4)
+        PPC_LL  r4, VCPU_GPR(R4)(r4)
         rfi
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index 8b99e076dc8..e04b0ef55ce 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/kvm/e500_emulate.c
@@ -269,6 +269,9 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
                 *spr_val = vcpu->arch.shared->mas7_3 >> 32;
                 break;
 #endif
+        case SPRN_DECAR:
+                *spr_val = vcpu->arch.decar;
+                break;
         case SPRN_TLB0CFG:
                 *spr_val = vcpu->arch.tlbcfg[0];
                 break;
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index c510fc96130..a2b66717813 100644
--- a/arch/powerpc/kvm/e500_tlb.c
+++ b/arch/powerpc/kvm/e500_tlb.c
@@ -322,11 +322,11 @@ static inline void kvmppc_e500_ref_release(struct tlbe_ref *ref)
 static void clear_tlb1_bitmap(struct kvmppc_vcpu_e500 *vcpu_e500)
 {
         if (vcpu_e500->g2h_tlb1_map)
-                memset(vcpu_e500->g2h_tlb1_map,
-                       sizeof(u64) * vcpu_e500->gtlb_params[1].entries, 0);
+                memset(vcpu_e500->g2h_tlb1_map, 0,
+                       sizeof(u64) * vcpu_e500->gtlb_params[1].entries);
         if (vcpu_e500->h2g_tlb1_rmap)
-                memset(vcpu_e500->h2g_tlb1_rmap,
-                       sizeof(unsigned int) * host_tlb_params[1].entries, 0);
+                memset(vcpu_e500->h2g_tlb1_rmap, 0,
+                       sizeof(unsigned int) * host_tlb_params[1].entries);
 }
 
 static void clear_tlb_privs(struct kvmppc_vcpu_e500 *vcpu_e500)
@@ -539,6 +539,9 @@ static inline void kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
 
         kvmppc_e500_setup_stlbe(&vcpu_e500->vcpu, gtlbe, tsize,
                                 ref, gvaddr, stlbe);
+
+        /* Clear i-cache for new pages */
+        kvmppc_mmu_flush_icache(pfn);
 }
 
 /* XXX only map the one-one case, for now use TLB0 */
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index fe6c1de6b70..1f89d26e65f 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2010,2012 Freescale Semiconductor, Inc. All rights reserved.
  *
  * Author: Varun Sethi, <varun.sethi@freescale.com>
  *
@@ -57,7 +57,8 @@ void kvmppc_e500_tlbil_one(struct kvmppc_vcpu_e500 *vcpu_e500,
                            struct kvm_book3e_206_tlb_entry *gtlbe)
 {
         unsigned int tid, ts;
-        u32 val, eaddr, lpid;
+        gva_t eaddr;
+        u32 val, lpid;
         unsigned long flags;
 
         ts = get_tlb_ts(gtlbe);
@@ -183,6 +184,9 @@ int kvmppc_core_vcpu_setup(struct kvm_vcpu *vcpu)
 
         vcpu->arch.shadow_epcr = SPRN_EPCR_DSIGS | SPRN_EPCR_DGTMI | \
                                  SPRN_EPCR_DUVD;
+#ifdef CONFIG_64BIT
+        vcpu->arch.shadow_epcr |= SPRN_EPCR_ICM;
+#endif
         vcpu->arch.shadow_msrp = MSRP_UCLEP | MSRP_DEP | MSRP_PMMP;
         vcpu->arch.eplc = EPC_EGS | (vcpu->kvm->arch.lpid << EPC_ELPID_SHIFT);
         vcpu->arch.epsc = vcpu->arch.eplc;
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index f90e86dea7a..ee04abaefe2 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -59,11 +59,13 @@
 #define OP_31_XOP_STHBRX    918
 
 #define OP_LWZ  32
+#define OP_LD   58
 #define OP_LWZU 33
 #define OP_LBZ  34
 #define OP_LBZU 35
 #define OP_STW  36
 #define OP_STWU 37
+#define OP_STD  62
 #define OP_STB  38
 #define OP_STBU 39
 #define OP_LHZ  40
@@ -392,6 +394,12 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
                 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
                 break;
 
+        /* TBD: Add support for other 64 bit load variants like ldu, ldux, ldx etc. */
+        case OP_LD:
+                rt = get_rt(inst);
+                emulated = kvmppc_handle_load(run, vcpu, rt, 8, 1);
+                break;
+
         case OP_LWZU:
                 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
                 kvmppc_set_gpr(vcpu, ra, vcpu->arch.vaddr_accessed);
@@ -412,6 +420,14 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
                                                4, 1);
                 break;
 
+        /* TBD: Add support for other 64 bit store variants like stdu, stdux, stdx etc. */
+        case OP_STD:
+                rs = get_rs(inst);
+                emulated = kvmppc_handle_store(run, vcpu,
+                                               kvmppc_get_gpr(vcpu, rs),
+                                               8, 1);
+                break;
+
         case OP_STWU:
                 emulated = kvmppc_handle_store(run, vcpu,
                                                kvmppc_get_gpr(vcpu, rs),
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 1493c8de947..87f4dc88607 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -246,6 +246,7 @@ int kvm_dev_ioctl_check_extension(long ext)
 #endif
 #ifdef CONFIG_PPC_BOOK3S_64
         case KVM_CAP_SPAPR_TCE:
+        case KVM_CAP_PPC_ALLOC_HTAB:
                 r = 1;
                 break;
 #endif /* CONFIG_PPC_BOOK3S_64 */
@@ -802,6 +803,23 @@ long kvm_arch_vm_ioctl(struct file *filp,
                         r = -EFAULT;
                 break;
         }
+
+        case KVM_PPC_ALLOCATE_HTAB: {
+                struct kvm *kvm = filp->private_data;
+                u32 htab_order;
+
+                r = -EFAULT;
+                if (get_user(htab_order, (u32 __user *)argp))
+                        break;
+                r = kvmppc_alloc_reset_hpt(kvm, &htab_order);
+                if (r)
+                        break;
+                r = -EFAULT;
+                if (put_user(htab_order, (u32 __user *)argp))
+                        break;
+                r = 0;
+                break;
+        }
 #endif /* CONFIG_KVM_BOOK3S_64_HV */
 
 #ifdef CONFIG_PPC_BOOK3S_64
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 7735a2c2e6d..746e0c895cd 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -17,14 +17,15 @@ obj-$(CONFIG_HAS_IOMEM)	+= devres.o
 obj-$(CONFIG_PPC64)     += copypage_64.o copyuser_64.o \
                            memcpy_64.o usercopy_64.o mem_64.o string.o \
                            checksum_wrappers_64.o hweight_64.o \
-                           copyuser_power7.o
+                           copyuser_power7.o string_64.o copypage_power7.o \
+                           memcpy_power7.o
 obj-$(CONFIG_XMON)      += sstep.o ldstfp.o
 obj-$(CONFIG_KPROBES)   += sstep.o ldstfp.o
 obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += sstep.o ldstfp.o
 
 ifeq ($(CONFIG_PPC64),y)
 obj-$(CONFIG_SMP)       += locks.o
-obj-$(CONFIG_ALTIVEC)   += copyuser_power7_vmx.o
+obj-$(CONFIG_ALTIVEC)   += vmx-helper.o
 endif
 
 obj-$(CONFIG_PPC_LIB_RHEAP) += rheap.o
diff --git a/arch/powerpc/lib/checksum_64.S b/arch/powerpc/lib/checksum_64.S
index 18245af38ae..167f72555d6 100644
--- a/arch/powerpc/lib/checksum_64.S
+++ b/arch/powerpc/lib/checksum_64.S
@@ -65,9 +65,6 @@ _GLOBAL(csum_tcpudp_magic)
         srwi    r3,r3,16
         blr
 
-#define STACKFRAMESIZE 256
-#define STK_REG(i)      (112 + ((i)-14)*8)
-
 /*
  * Computes the checksum of a memory block at buff, length len,
  * and adds in "sum" (32-bit).
@@ -114,9 +111,9 @@ _GLOBAL(csum_partial)
         mtctr   r6
 
         stdu    r1,-STACKFRAMESIZE(r1)
-        std     r14,STK_REG(r14)(r1)
-        std     r15,STK_REG(r15)(r1)
-        std     r16,STK_REG(r16)(r1)
+        std     r14,STK_REG(R14)(r1)
+        std     r15,STK_REG(R15)(r1)
+        std     r16,STK_REG(R16)(r1)
 
         ld      r6,0(r3)
         ld      r9,8(r3)
@@ -175,9 +172,9 @@ _GLOBAL(csum_partial)
         adde    r0,r0,r15
         adde    r0,r0,r16
 
-        ld      r14,STK_REG(r14)(r1)
-        ld      r15,STK_REG(r15)(r1)
-        ld      r16,STK_REG(r16)(r1)
+        ld      r14,STK_REG(R14)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r16,STK_REG(R16)(r1)
         addi    r1,r1,STACKFRAMESIZE
 
         andi.   r4,r4,63
@@ -299,9 +296,9 @@ dest;	sth	r6,0(r4)
         mtctr   r6
 
         stdu    r1,-STACKFRAMESIZE(r1)
-        std     r14,STK_REG(r14)(r1)
-        std     r15,STK_REG(r15)(r1)
-        std     r16,STK_REG(r16)(r1)
+        std     r14,STK_REG(R14)(r1)
+        std     r15,STK_REG(R15)(r1)
+        std     r16,STK_REG(R16)(r1)
 
 source; ld      r6,0(r3)
 source; ld      r9,8(r3)
@@ -382,9 +379,9 @@ dest;	std	r16,56(r4)
         adde    r0,r0,r15
         adde    r0,r0,r16
 
-        ld      r14,STK_REG(r14)(r1)
-        ld      r15,STK_REG(r15)(r1)
-        ld      r16,STK_REG(r16)(r1)
+        ld      r14,STK_REG(R14)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r16,STK_REG(R16)(r1)
         addi    r1,r1,STACKFRAMESIZE
 
         andi.   r5,r5,63
diff --git a/arch/powerpc/lib/code-patching.c b/arch/powerpc/lib/code-patching.c
index 7c975d43e3f..17e5b236431 100644
--- a/arch/powerpc/lib/code-patching.c
+++ b/arch/powerpc/lib/code-patching.c
@@ -13,17 +13,23 @@
 #include <linux/mm.h>
 #include <asm/page.h>
 #include <asm/code-patching.h>
+#include <asm/uaccess.h>
 
 
-void patch_instruction(unsigned int *addr, unsigned int instr)
+int patch_instruction(unsigned int *addr, unsigned int instr)
 {
-        *addr = instr;
+        int err;
+
+        __put_user_size(instr, addr, 4, err);
+        if (err)
+                return err;
         asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (addr));
+        return 0;
 }
 
-void patch_branch(unsigned int *addr, unsigned long target, int flags)
+int patch_branch(unsigned int *addr, unsigned long target, int flags)
 {
-        patch_instruction(addr, create_branch(addr, target, flags));
+        return patch_instruction(addr, create_branch(addr, target, flags));
 }
 
 unsigned int create_branch(const unsigned int *addr,
diff --git a/arch/powerpc/lib/copypage_64.S b/arch/powerpc/lib/copypage_64.S
index 53dcb6b1b70..9f9434a8526 100644
--- a/arch/powerpc/lib/copypage_64.S
+++ b/arch/powerpc/lib/copypage_64.S
@@ -17,7 +17,11 @@ PPC64_CACHES:
         .section        ".text"
 
 _GLOBAL(copy_page)
+BEGIN_FTR_SECTION
         lis     r5,PAGE_SIZE@h
+FTR_SECTION_ELSE
+        b       .copypage_power7
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
         ori     r5,r5,PAGE_SIZE@l
 BEGIN_FTR_SECTION
         ld      r10,PPC64_CACHES@toc(r2)
diff --git a/arch/powerpc/lib/copypage_power7.S b/arch/powerpc/lib/copypage_power7.S
new file mode 100644
index 00000000000..0ef75bf0695
--- /dev/null
+++ b/arch/powerpc/lib/copypage_power7.S
@@ -0,0 +1,165 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2012
+ *
+ * Author: Anton Blanchard <anton@au.ibm.com>
+ */
+#include <asm/page.h>
+#include <asm/ppc_asm.h>
+
+_GLOBAL(copypage_power7)
+        /*
+         * We prefetch both the source and destination using enhanced touch
+         * instructions. We use a stream ID of 0 for the load side and
+         * 1 for the store side. Since source and destination are page
+         * aligned we don't need to clear the bottom 7 bits of either
+         * address.
+         */
+        ori     r9,r3,1         /* stream=1 */
+
+#ifdef CONFIG_PPC_64K_PAGES
+        lis     r7,0x0E01       /* depth=7, units=512 */
+#else
+        lis     r7,0x0E00       /* depth=7 */
+        ori     r7,r7,0x1000    /* units=32 */
+#endif
+        ori     r10,r7,1        /* stream=1 */
+
+        lis     r8,0x8000       /* GO=1 */
+        clrldi  r8,r8,32
+
+.machine push
+.machine "power4"
+        dcbt    r0,r4,0b01000
+        dcbt    r0,r7,0b01010
+        dcbtst  r0,r9,0b01000
+        dcbtst  r0,r10,0b01010
+        eieio
+        dcbt    r0,r8,0b01010   /* GO */
+.machine pop
+
+#ifdef CONFIG_ALTIVEC
+        mflr    r0
+        std     r3,48(r1)
+        std     r4,56(r1)
+        std     r0,16(r1)
+        stdu    r1,-STACKFRAMESIZE(r1)
+        bl      .enter_vmx_copy
+        cmpwi   r3,0
+        ld      r0,STACKFRAMESIZE+16(r1)
+        ld      r3,STACKFRAMESIZE+48(r1)
+        ld      r4,STACKFRAMESIZE+56(r1)
+        mtlr    r0
+
+        li      r0,(PAGE_SIZE/128)
+        mtctr   r0
+
+        beq     .Lnonvmx_copy
+
+        addi    r1,r1,STACKFRAMESIZE
+
+        li      r6,16
+        li      r7,32
+        li      r8,48
+        li      r9,64
+        li      r10,80
+        li      r11,96
+        li      r12,112
+
+        .align  5
+1:      lvx     vr7,r0,r4
+        lvx     vr6,r4,r6
+        lvx     vr5,r4,r7
+        lvx     vr4,r4,r8
+        lvx     vr3,r4,r9
+        lvx     vr2,r4,r10
+        lvx     vr1,r4,r11
+        lvx     vr0,r4,r12
+        addi    r4,r4,128
+        stvx    vr7,r0,r3
+        stvx    vr6,r3,r6
+        stvx    vr5,r3,r7
+        stvx    vr4,r3,r8
+        stvx    vr3,r3,r9
+        stvx    vr2,r3,r10
+        stvx    vr1,r3,r11
+        stvx    vr0,r3,r12
+        addi    r3,r3,128
+        bdnz    1b
+
+        b       .exit_vmx_copy          /* tail call optimise */
+
+#else
+        li      r0,(PAGE_SIZE/128)
+        mtctr   r0
+
+        stdu    r1,-STACKFRAMESIZE(r1)
+#endif
+
+.Lnonvmx_copy:
+        std     r14,STK_REG(R14)(r1)
+        std     r15,STK_REG(R15)(r1)
+        std     r16,STK_REG(R16)(r1)
+        std     r17,STK_REG(R17)(r1)
+        std     r18,STK_REG(R18)(r1)
+        std     r19,STK_REG(R19)(r1)
+        std     r20,STK_REG(R20)(r1)
+
+1:      ld      r0,0(r4)
+        ld      r5,8(r4)
+        ld      r6,16(r4)
+        ld      r7,24(r4)
+        ld      r8,32(r4)
+        ld      r9,40(r4)
+        ld      r10,48(r4)
+        ld      r11,56(r4)
+        ld      r12,64(r4)
+        ld      r14,72(r4)
+        ld      r15,80(r4)
+        ld      r16,88(r4)
+        ld      r17,96(r4)
+        ld      r18,104(r4)
+        ld      r19,112(r4)
+        ld      r20,120(r4)
+        addi    r4,r4,128
+        std     r0,0(r3)
+        std     r5,8(r3)
+        std     r6,16(r3)
+        std     r7,24(r3)
+        std     r8,32(r3)
+        std     r9,40(r3)
+        std     r10,48(r3)
+        std     r11,56(r3)
+        std     r12,64(r3)
+        std     r14,72(r3)
+        std     r15,80(r3)
+        std     r16,88(r3)
+        std     r17,96(r3)
+        std     r18,104(r3)
+        std     r19,112(r3)
+        std     r20,120(r3)
+        addi    r3,r3,128
+        bdnz    1b
+
+        ld      r14,STK_REG(R14)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r16,STK_REG(R16)(r1)
+        ld      r17,STK_REG(R17)(r1)
+        ld      r18,STK_REG(R18)(r1)
+        ld      r19,STK_REG(R19)(r1)
+        ld      r20,STK_REG(R20)(r1)
+        addi    r1,r1,STACKFRAMESIZE
+        blr
diff --git a/arch/powerpc/lib/copyuser_power7.S b/arch/powerpc/lib/copyuser_power7.S
index 497db7b23bb..0d24ff15f5f 100644
--- a/arch/powerpc/lib/copyuser_power7.S
+++ b/arch/powerpc/lib/copyuser_power7.S
@@ -19,9 +19,6 @@
  */
 #include <asm/ppc_asm.h>
 
-#define STACKFRAMESIZE  256
-#define STK_REG(i)      (112 + ((i)-14)*8)
-
         .macro err1
 100:
         .section __ex_table,"a"
@@ -57,26 +54,26 @@
 
 
 .Ldo_err4:
-        ld      r16,STK_REG(r16)(r1)
-        ld      r15,STK_REG(r15)(r1)
-        ld      r14,STK_REG(r14)(r1)
+        ld      r16,STK_REG(R16)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r14,STK_REG(R14)(r1)
 .Ldo_err3:
-        bl      .exit_vmx_copy
+        bl      .exit_vmx_usercopy
         ld      r0,STACKFRAMESIZE+16(r1)
         mtlr    r0
         b       .Lexit
 #endif /* CONFIG_ALTIVEC */
 
 .Ldo_err2:
-        ld      r22,STK_REG(r22)(r1)
-        ld      r21,STK_REG(r21)(r1)
-        ld      r20,STK_REG(r20)(r1)
-        ld      r19,STK_REG(r19)(r1)
-        ld      r18,STK_REG(r18)(r1)
-        ld      r17,STK_REG(r17)(r1)
-        ld      r16,STK_REG(r16)(r1)
-        ld      r15,STK_REG(r15)(r1)
-        ld      r14,STK_REG(r14)(r1)
+        ld      r22,STK_REG(R22)(r1)
+        ld      r21,STK_REG(R21)(r1)
+        ld      r20,STK_REG(R20)(r1)
+        ld      r19,STK_REG(R19)(r1)
+        ld      r18,STK_REG(R18)(r1)
+        ld      r17,STK_REG(R17)(r1)
+        ld      r16,STK_REG(R16)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r14,STK_REG(R14)(r1)
 .Lexit:
         addi    r1,r1,STACKFRAMESIZE
 .Ldo_err1:
@@ -137,15 +134,15 @@ err1;	stw	r0,0(r3)
 
         mflr    r0
         stdu    r1,-STACKFRAMESIZE(r1)
-        std     r14,STK_REG(r14)(r1)
-        std     r15,STK_REG(r15)(r1)
-        std     r16,STK_REG(r16)(r1)
-        std     r17,STK_REG(r17)(r1)
-        std     r18,STK_REG(r18)(r1)
-        std     r19,STK_REG(r19)(r1)
-        std     r20,STK_REG(r20)(r1)
-        std     r21,STK_REG(r21)(r1)
-        std     r22,STK_REG(r22)(r1)
+        std     r14,STK_REG(R14)(r1)
+        std     r15,STK_REG(R15)(r1)
+        std     r16,STK_REG(R16)(r1)
+        std     r17,STK_REG(R17)(r1)
+        std     r18,STK_REG(R18)(r1)
+        std     r19,STK_REG(R19)(r1)
+        std     r20,STK_REG(R20)(r1)
+        std     r21,STK_REG(R21)(r1)
+        std     r22,STK_REG(R22)(r1)
         std     r0,STACKFRAMESIZE+16(r1)
 
         srdi    r6,r5,7
@@ -192,15 +189,15 @@ err2;	std	r21,120(r3)
 
         clrldi  r5,r5,(64-7)
 
-        ld      r14,STK_REG(r14)(r1)
-        ld      r15,STK_REG(r15)(r1)
-        ld      r16,STK_REG(r16)(r1)
-        ld      r17,STK_REG(r17)(r1)
-        ld      r18,STK_REG(r18)(r1)
-        ld      r19,STK_REG(r19)(r1)
-        ld      r20,STK_REG(r20)(r1)
-        ld      r21,STK_REG(r21)(r1)
-        ld      r22,STK_REG(r22)(r1)
+        ld      r14,STK_REG(R14)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r16,STK_REG(R16)(r1)
+        ld      r17,STK_REG(R17)(r1)
+        ld      r18,STK_REG(R18)(r1)
+        ld      r19,STK_REG(R19)(r1)
+        ld      r20,STK_REG(R20)(r1)
+        ld      r21,STK_REG(R21)(r1)
+        ld      r22,STK_REG(R22)(r1)
         addi    r1,r1,STACKFRAMESIZE
 
         /* Up to 127B to go */
@@ -290,15 +287,46 @@ err1;	stb	r0,0(r3)
         mflr    r0
         std     r0,16(r1)
         stdu    r1,-STACKFRAMESIZE(r1)
-        bl      .enter_vmx_copy
-        cmpwi   r3,0
+        bl      .enter_vmx_usercopy
+        cmpwi   cr1,r3,0
         ld      r0,STACKFRAMESIZE+16(r1)
         ld      r3,STACKFRAMESIZE+48(r1)
         ld      r4,STACKFRAMESIZE+56(r1)
         ld      r5,STACKFRAMESIZE+64(r1)
         mtlr    r0
 
-        beq     .Lunwind_stack_nonvmx_copy
+        /*
+         * We prefetch both the source and destination using enhanced touch
+         * instructions. We use a stream ID of 0 for the load side and
+         * 1 for the store side.
+         */
+        clrrdi  r6,r4,7
+        clrrdi  r9,r3,7
+        ori     r9,r9,1         /* stream=1 */
+
+        srdi    r7,r5,7         /* length in cachelines, capped at 0x3FF */
+        cmpldi  r7,0x3FF
+        ble     1f
+        li      r7,0x3FF
+1:      lis     r0,0x0E00       /* depth=7 */
+        sldi    r7,r7,7
+        or      r7,r7,r0
+        ori     r10,r7,1        /* stream=1 */
+
+        lis     r8,0x8000       /* GO=1 */
+        clrldi  r8,r8,32
+
+.machine push
+.machine "power4"
+        dcbt    r0,r6,0b01000
+        dcbt    r0,r7,0b01010
+        dcbtst  r0,r9,0b01000
+        dcbtst  r0,r10,0b01010
+        eieio
+        dcbt    r0,r8,0b01010   /* GO */
+.machine pop
+
+        beq     cr1,.Lunwind_stack_nonvmx_copy
 
         /*
          * If source and destination are not relatively aligned we use a
@@ -378,9 +406,9 @@ err3;	stvx	vr0,r3,r11
 7:      sub     r5,r5,r6
         srdi    r6,r5,7
 
-        std     r14,STK_REG(r14)(r1)
-        std     r15,STK_REG(r15)(r1)
-        std     r16,STK_REG(r16)(r1)
+        std     r14,STK_REG(R14)(r1)
+        std     r15,STK_REG(R15)(r1)
+        std     r16,STK_REG(R16)(r1)
 
         li      r12,64
         li      r14,80
@@ -415,9 +443,9 @@ err4;	stvx	vr0,r3,r16
         addi    r3,r3,128
         bdnz    8b
 
-        ld      r14,STK_REG(r14)(r1)
-        ld      r15,STK_REG(r15)(r1)
-        ld      r16,STK_REG(r16)(r1)
+        ld      r14,STK_REG(R14)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r16,STK_REG(R16)(r1)
 
         /* Up to 127B to go */
         clrldi  r5,r5,(64-7)
@@ -476,7 +504,7 @@ err3;	lbz	r0,0(r4)
 err3;   stb     r0,0(r3)
 
 15:     addi    r1,r1,STACKFRAMESIZE
-        b       .exit_vmx_copy          /* tail call optimise */
+        b       .exit_vmx_usercopy      /* tail call optimise */
 
 .Lvmx_unaligned_copy:
         /* Get the destination 16B aligned */
@@ -563,9 +591,9 @@ err3;	stvx	vr11,r3,r11
 7:      sub     r5,r5,r6
         srdi    r6,r5,7
 
-        std     r14,STK_REG(r14)(r1)
-        std     r15,STK_REG(r15)(r1)
-        std     r16,STK_REG(r16)(r1)
+        std     r14,STK_REG(R14)(r1)
+        std     r15,STK_REG(R15)(r1)
+        std     r16,STK_REG(R16)(r1)
 
         li      r12,64
         li      r14,80
@@ -608,9 +636,9 @@ err4;	stvx	vr15,r3,r16
         addi    r3,r3,128
         bdnz    8b
 
-        ld      r14,STK_REG(r14)(r1)
-        ld      r15,STK_REG(r15)(r1)
-        ld      r16,STK_REG(r16)(r1)
+        ld      r14,STK_REG(R14)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r16,STK_REG(R16)(r1)
 
         /* Up to 127B to go */
         clrldi  r5,r5,(64-7)
@@ -679,5 +707,5 @@ err3;	lbz	r0,0(r4)
 err3;   stb     r0,0(r3)
 
 15:     addi    r1,r1,STACKFRAMESIZE
-        b       .exit_vmx_copy          /* tail call optimise */
+        b       .exit_vmx_usercopy      /* tail call optimise */
 #endif /* CONFiG_ALTIVEC */
diff --git a/arch/powerpc/lib/crtsavres.S b/arch/powerpc/lib/crtsavres.S
index 1c893f05d22..b2c68ce139a 100644
--- a/arch/powerpc/lib/crtsavres.S
+++ b/arch/powerpc/lib/crtsavres.S
@@ -41,12 +41,13 @@
 #include <asm/ppc_asm.h>
 
         .file   "crtsavres.S"
-        .section ".text"
 
 #ifdef CONFIG_CC_OPTIMIZE_FOR_SIZE
 
 #ifndef CONFIG_PPC64
 
+        .section ".text"
+
 /* Routines for saving integer registers, called by the compiler.  */
 /* Called with r11 pointing to the stack header word of the caller of the */
 /* function, just beyond the end of the integer save area.  */
@@ -232,6 +233,8 @@ _GLOBAL(_rest32gpr_31_x)
 
 #else /* CONFIG_PPC64 */
 
+        .section ".text.save.restore","ax",@progbits
+
 .globl  _savegpr0_14
 _savegpr0_14:
         std     r14,-144(r1)
diff --git a/arch/powerpc/lib/hweight_64.S b/arch/powerpc/lib/hweight_64.S
index fda27868cf8..9b96ff2ecd4 100644
--- a/arch/powerpc/lib/hweight_64.S
+++ b/arch/powerpc/lib/hweight_64.S
@@ -28,7 +28,7 @@ BEGIN_FTR_SECTION
         nop
         nop
 FTR_SECTION_ELSE
-        PPC_POPCNTB(r3,r3)
+        PPC_POPCNTB(R3,R3)
         clrldi  r3,r3,64-8
         blr
 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_POPCNTB)
@@ -42,14 +42,14 @@ BEGIN_FTR_SECTION
         nop
 FTR_SECTION_ELSE
   BEGIN_FTR_SECTION_NESTED(50)
-        PPC_POPCNTB(r3,r3)
+        PPC_POPCNTB(R3,R3)
         srdi    r4,r3,8
         add     r3,r4,r3
         clrldi  r3,r3,64-8
         blr
   FTR_SECTION_ELSE_NESTED(50)
         clrlwi  r3,r3,16
-        PPC_POPCNTW(r3,r3)
+        PPC_POPCNTW(R3,R3)
         clrldi  r3,r3,64-8
         blr
   ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 50)
@@ -66,7 +66,7 @@ BEGIN_FTR_SECTION
         nop
 FTR_SECTION_ELSE
   BEGIN_FTR_SECTION_NESTED(51)
-        PPC_POPCNTB(r3,r3)
+        PPC_POPCNTB(R3,R3)
         srdi    r4,r3,16
         add     r3,r4,r3
         srdi    r4,r3,8
@@ -74,7 +74,7 @@ FTR_SECTION_ELSE
         clrldi  r3,r3,64-8
         blr
   FTR_SECTION_ELSE_NESTED(51)
-        PPC_POPCNTW(r3,r3)
+        PPC_POPCNTW(R3,R3)
         clrldi  r3,r3,64-8
         blr
   ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 51)
@@ -93,7 +93,7 @@ BEGIN_FTR_SECTION
         nop
 FTR_SECTION_ELSE
   BEGIN_FTR_SECTION_NESTED(52)
-        PPC_POPCNTB(r3,r3)
+        PPC_POPCNTB(R3,R3)
         srdi    r4,r3,32
         add     r3,r4,r3
         srdi    r4,r3,16
@@ -103,7 +103,7 @@ FTR_SECTION_ELSE
         clrldi  r3,r3,64-8
         blr
   FTR_SECTION_ELSE_NESTED(52)
-        PPC_POPCNTD(r3,r3)
+        PPC_POPCNTD(R3,R3)
         clrldi  r3,r3,64-8
         blr
   ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_POPCNTD, 52)
diff --git a/arch/powerpc/lib/ldstfp.S b/arch/powerpc/lib/ldstfp.S
index 6a85380520b..85aec08ab23 100644
--- a/arch/powerpc/lib/ldstfp.S
+++ b/arch/powerpc/lib/ldstfp.S
@@ -330,13 +330,13 @@ _GLOBAL(do_lxvd2x)
         MTMSRD(r7)
         isync
         beq     cr7,1f
-        STXVD2X(0,r1,r8)
+        STXVD2X(0,R1,R8)
 1:      li      r9,-EFAULT
-2:      LXVD2X(0,0,r4)
+2:      LXVD2X(0,R0,R4)
         li      r9,0
 3:      beq     cr7,4f
         bl      put_vsr
-        LXVD2X(0,r1,r8)
+        LXVD2X(0,R1,R8)
 4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
         mtlr    r0
         MTMSRD(r6)
@@ -358,13 +358,13 @@ _GLOBAL(do_stxvd2x)
         MTMSRD(r7)
         isync
         beq     cr7,1f
-        STXVD2X(0,r1,r8)
+        STXVD2X(0,R1,R8)
         bl      get_vsr
 1:      li      r9,-EFAULT
-2:      STXVD2X(0,0,r4)
+2:      STXVD2X(0,R0,R4)
         li      r9,0
 3:      beq     cr7,4f
-        LXVD2X(0,r1,r8)
+        LXVD2X(0,R1,R8)
 4:      PPC_LL  r0,STKFRM+PPC_LR_STKOFF(r1)
         mtlr    r0
         MTMSRD(r6)
diff --git a/arch/powerpc/lib/memcpy_64.S b/arch/powerpc/lib/memcpy_64.S
index 82fea3963e1..d2bbbc8d7dc 100644
--- a/arch/powerpc/lib/memcpy_64.S
+++ b/arch/powerpc/lib/memcpy_64.S
@@ -11,7 +11,11 @@
 
         .align  7
 _GLOBAL(memcpy)
+BEGIN_FTR_SECTION
         std     r3,48(r1)       /* save destination pointer for return value */
+FTR_SECTION_ELSE
+        b       memcpy_power7
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
         PPC_MTOCRF(0x01,r5)
         cmpldi  cr1,r5,16
         neg     r6,r3           # LS 3 bits = # bytes to 8-byte dest bdry
diff --git a/arch/powerpc/lib/memcpy_power7.S b/arch/powerpc/lib/memcpy_power7.S
new file mode 100644
index 00000000000..7ba6c96de77
--- /dev/null
+++ b/arch/powerpc/lib/memcpy_power7.S
@@ -0,0 +1,647 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2012
+ *
+ * Author: Anton Blanchard <anton@au.ibm.com>
+ */
+#include <asm/ppc_asm.h>
+
+_GLOBAL(memcpy_power7)
+#ifdef CONFIG_ALTIVEC
+        cmpldi  r5,16
+        cmpldi  cr1,r5,4096
+
+        std     r3,48(r1)
+
+        blt     .Lshort_copy
+        bgt     cr1,.Lvmx_copy
+#else
+        cmpldi  r5,16
+
+        std     r3,48(r1)
+
+        blt     .Lshort_copy
+#endif
+
+.Lnonvmx_copy:
+        /* Get the source 8B aligned */
+        neg     r6,r4
+        mtocrf  0x01,r6
+        clrldi  r6,r6,(64-3)
+
+        bf      cr7*4+3,1f
+        lbz     r0,0(r4)
+        addi    r4,r4,1
+        stb     r0,0(r3)
+        addi    r3,r3,1
+
+1:      bf      cr7*4+2,2f
+        lhz     r0,0(r4)
+        addi    r4,r4,2
+        sth     r0,0(r3)
+        addi    r3,r3,2
+
+2:      bf      cr7*4+1,3f
+        lwz     r0,0(r4)
+        addi    r4,r4,4
+        stw     r0,0(r3)
+        addi    r3,r3,4
+
+3:      sub     r5,r5,r6
+        cmpldi  r5,128
+        blt     5f
+
+        mflr    r0
+        stdu    r1,-STACKFRAMESIZE(r1)
+        std     r14,STK_REG(R14)(r1)
+        std     r15,STK_REG(R15)(r1)
+        std     r16,STK_REG(R16)(r1)
+        std     r17,STK_REG(R17)(r1)
+        std     r18,STK_REG(R18)(r1)
+        std     r19,STK_REG(R19)(r1)
+        std     r20,STK_REG(R20)(r1)
+        std     r21,STK_REG(R21)(r1)
+        std     r22,STK_REG(R22)(r1)
+        std     r0,STACKFRAMESIZE+16(r1)
+
+        srdi    r6,r5,7
+        mtctr   r6
+
+        /* Now do cacheline (128B) sized loads and stores. */
+        .align  5
+4:
+        ld      r0,0(r4)
+        ld      r6,8(r4)
+        ld      r7,16(r4)
+        ld      r8,24(r4)
+        ld      r9,32(r4)
+        ld      r10,40(r4)
+        ld      r11,48(r4)
+        ld      r12,56(r4)
+        ld      r14,64(r4)
+        ld      r15,72(r4)
+        ld      r16,80(r4)
+        ld      r17,88(r4)
+        ld      r18,96(r4)
+        ld      r19,104(r4)
+        ld      r20,112(r4)
+        ld      r21,120(r4)
+        addi    r4,r4,128
+        std     r0,0(r3)
+        std     r6,8(r3)
+        std     r7,16(r3)
+        std     r8,24(r3)
+        std     r9,32(r3)
+        std     r10,40(r3)
+        std     r11,48(r3)
+        std     r12,56(r3)
+        std     r14,64(r3)
+        std     r15,72(r3)
+        std     r16,80(r3)
+        std     r17,88(r3)
+        std     r18,96(r3)
+        std     r19,104(r3)
+        std     r20,112(r3)
+        std     r21,120(r3)
+        addi    r3,r3,128
+        bdnz    4b
+
+        clrldi  r5,r5,(64-7)
+
+        ld      r14,STK_REG(R14)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r16,STK_REG(R16)(r1)
+        ld      r17,STK_REG(R17)(r1)
+        ld      r18,STK_REG(R18)(r1)
+        ld      r19,STK_REG(R19)(r1)
+        ld      r20,STK_REG(R20)(r1)
+        ld      r21,STK_REG(R21)(r1)
+        ld      r22,STK_REG(R22)(r1)
+        addi    r1,r1,STACKFRAMESIZE
+
+        /* Up to 127B to go */
+5:      srdi    r6,r5,4
+        mtocrf  0x01,r6
+
+6:      bf      cr7*4+1,7f
+        ld      r0,0(r4)
+        ld      r6,8(r4)
+        ld      r7,16(r4)
+        ld      r8,24(r4)
+        ld      r9,32(r4)
+        ld      r10,40(r4)
+        ld      r11,48(r4)
+        ld      r12,56(r4)
+        addi    r4,r4,64
+        std     r0,0(r3)
+        std     r6,8(r3)
+        std     r7,16(r3)
+        std     r8,24(r3)
+        std     r9,32(r3)
+        std     r10,40(r3)
+        std     r11,48(r3)
+        std     r12,56(r3)
+        addi    r3,r3,64
+
+        /* Up to 63B to go */
+7:      bf      cr7*4+2,8f
+        ld      r0,0(r4)
+        ld      r6,8(r4)
+        ld      r7,16(r4)
+        ld      r8,24(r4)
+        addi    r4,r4,32
+        std     r0,0(r3)
+        std     r6,8(r3)
+        std     r7,16(r3)
+        std     r8,24(r3)
+        addi    r3,r3,32
+
+        /* Up to 31B to go */
+8:      bf      cr7*4+3,9f
+        ld      r0,0(r4)
+        ld      r6,8(r4)
+        addi    r4,r4,16
+        std     r0,0(r3)
+        std     r6,8(r3)
+        addi    r3,r3,16
+
+9:      clrldi  r5,r5,(64-4)
+
+        /* Up to 15B to go */
+.Lshort_copy:
+        mtocrf  0x01,r5
+        bf      cr7*4+0,12f
+        lwz     r0,0(r4)        /* Less chance of a reject with word ops */
+        lwz     r6,4(r4)
+        addi    r4,r4,8
+        stw     r0,0(r3)
+        stw     r6,4(r3)
+        addi    r3,r3,8
+
+12:     bf      cr7*4+1,13f
+        lwz     r0,0(r4)
+        addi    r4,r4,4
+        stw     r0,0(r3)
+        addi    r3,r3,4
+
+13:     bf      cr7*4+2,14f
+        lhz     r0,0(r4)
+        addi    r4,r4,2
+        sth     r0,0(r3)
+        addi    r3,r3,2
+
+14:     bf      cr7*4+3,15f
+        lbz     r0,0(r4)
+        stb     r0,0(r3)
+
+15:     ld      r3,48(r1)
+        blr
+
+.Lunwind_stack_nonvmx_copy:
+        addi    r1,r1,STACKFRAMESIZE
+        b       .Lnonvmx_copy
+
+#ifdef CONFIG_ALTIVEC
+.Lvmx_copy:
+        mflr    r0
+        std     r4,56(r1)
+        std     r5,64(r1)
+        std     r0,16(r1)
+        stdu    r1,-STACKFRAMESIZE(r1)
+        bl      .enter_vmx_copy
+        cmpwi   cr1,r3,0
+        ld      r0,STACKFRAMESIZE+16(r1)
+        ld      r3,STACKFRAMESIZE+48(r1)
+        ld      r4,STACKFRAMESIZE+56(r1)
+        ld      r5,STACKFRAMESIZE+64(r1)
+        mtlr    r0
+
+        /*
+         * We prefetch both the source and destination using enhanced touch
+         * instructions. We use a stream ID of 0 for the load side and
+         * 1 for the store side.
+         */
+        clrrdi  r6,r4,7
+        clrrdi  r9,r3,7
+        ori     r9,r9,1         /* stream=1 */
+
+        srdi    r7,r5,7         /* length in cachelines, capped at 0x3FF */
+        cmpldi  cr1,r7,0x3FF
+        ble     cr1,1f
+        li      r7,0x3FF
+1:      lis     r0,0x0E00       /* depth=7 */
+        sldi    r7,r7,7
+        or      r7,r7,r0
+        ori     r10,r7,1        /* stream=1 */
+
+        lis     r8,0x8000       /* GO=1 */
+        clrldi  r8,r8,32
+
+.machine push
+.machine "power4"
+        dcbt    r0,r6,0b01000
+        dcbt    r0,r7,0b01010
+        dcbtst  r0,r9,0b01000
+        dcbtst  r0,r10,0b01010
+        eieio
+        dcbt    r0,r8,0b01010   /* GO */
+.machine pop
+
+        beq     cr1,.Lunwind_stack_nonvmx_copy
+
+        /*
+         * If source and destination are not relatively aligned we use a
+         * slower permute loop.
+         */
+        xor     r6,r4,r3
+        rldicl. r6,r6,0,(64-4)
+        bne     .Lvmx_unaligned_copy
+
+        /* Get the destination 16B aligned */
+        neg     r6,r3
+        mtocrf  0x01,r6
+        clrldi  r6,r6,(64-4)
+
+        bf      cr7*4+3,1f
+        lbz     r0,0(r4)
+        addi    r4,r4,1
+        stb     r0,0(r3)
+        addi    r3,r3,1
+
+1:      bf      cr7*4+2,2f
+        lhz     r0,0(r4)
+        addi    r4,r4,2
+        sth     r0,0(r3)
+        addi    r3,r3,2
+
+2:      bf      cr7*4+1,3f
+        lwz     r0,0(r4)
+        addi    r4,r4,4
+        stw     r0,0(r3)
+        addi    r3,r3,4
+
+3:      bf      cr7*4+0,4f
+        ld      r0,0(r4)
+        addi    r4,r4,8
+        std     r0,0(r3)
+        addi    r3,r3,8
+
+4:      sub     r5,r5,r6
+
+        /* Get the desination 128B aligned */
+        neg     r6,r3
+        srdi    r7,r6,4
+        mtocrf  0x01,r7
+        clrldi  r6,r6,(64-7)
+
+        li      r9,16
+        li      r10,32
+        li      r11,48
+
+        bf      cr7*4+3,5f
+        lvx     vr1,r0,r4
+        addi    r4,r4,16
+        stvx    vr1,r0,r3
+        addi    r3,r3,16
+
+5:      bf      cr7*4+2,6f
+        lvx     vr1,r0,r4
+        lvx     vr0,r4,r9
+        addi    r4,r4,32
+        stvx    vr1,r0,r3
+        stvx    vr0,r3,r9
+        addi    r3,r3,32
+
+6:      bf      cr7*4+1,7f
+        lvx     vr3,r0,r4
+        lvx     vr2,r4,r9
+        lvx     vr1,r4,r10
+        lvx     vr0,r4,r11
+        addi    r4,r4,64
+        stvx    vr3,r0,r3
+        stvx    vr2,r3,r9
+        stvx    vr1,r3,r10
+        stvx    vr0,r3,r11
+        addi    r3,r3,64
+
+7:      sub     r5,r5,r6
+        srdi    r6,r5,7
+
+        std     r14,STK_REG(R14)(r1)
+        std     r15,STK_REG(R15)(r1)
+        std     r16,STK_REG(R16)(r1)
+
+        li      r12,64
+        li      r14,80
+        li      r15,96
+        li      r16,112
+
+        mtctr   r6
+
+        /*
+         * Now do cacheline sized loads and stores. By this stage the
+         * cacheline stores are also cacheline aligned.
+         */
+        .align  5
+8:
+        lvx     vr7,r0,r4
+        lvx     vr6,r4,r9
+        lvx     vr5,r4,r10
+        lvx     vr4,r4,r11
+        lvx     vr3,r4,r12
+        lvx     vr2,r4,r14
+        lvx     vr1,r4,r15
+        lvx     vr0,r4,r16
+        addi    r4,r4,128
+        stvx    vr7,r0,r3
+        stvx    vr6,r3,r9
+        stvx    vr5,r3,r10
+        stvx    vr4,r3,r11
+        stvx    vr3,r3,r12
+        stvx    vr2,r3,r14
+        stvx    vr1,r3,r15
+        stvx    vr0,r3,r16
+        addi    r3,r3,128
+        bdnz    8b
+
+        ld      r14,STK_REG(R14)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r16,STK_REG(R16)(r1)
+
+        /* Up to 127B to go */
+        clrldi  r5,r5,(64-7)
+        srdi    r6,r5,4
+        mtocrf  0x01,r6
+
+        bf      cr7*4+1,9f
+        lvx     vr3,r0,r4
+        lvx     vr2,r4,r9
+        lvx     vr1,r4,r10
+        lvx     vr0,r4,r11
+        addi    r4,r4,64
+        stvx    vr3,r0,r3
+        stvx    vr2,r3,r9
+        stvx    vr1,r3,r10
+        stvx    vr0,r3,r11
+        addi    r3,r3,64
+
+9:      bf      cr7*4+2,10f
+        lvx     vr1,r0,r4
+        lvx     vr0,r4,r9
+        addi    r4,r4,32
+        stvx    vr1,r0,r3
+        stvx    vr0,r3,r9
+        addi    r3,r3,32
+
+10:     bf      cr7*4+3,11f
+        lvx     vr1,r0,r4
+        addi    r4,r4,16
+        stvx    vr1,r0,r3
+        addi    r3,r3,16
+
+        /* Up to 15B to go */
+11:     clrldi  r5,r5,(64-4)
+        mtocrf  0x01,r5
+        bf      cr7*4+0,12f
+        ld      r0,0(r4)
+        addi    r4,r4,8
+        std     r0,0(r3)
+        addi    r3,r3,8
+
+12:     bf      cr7*4+1,13f
+        lwz     r0,0(r4)
+        addi    r4,r4,4
+        stw     r0,0(r3)
+        addi    r3,r3,4
+
+13:     bf      cr7*4+2,14f
+        lhz     r0,0(r4)
+        addi    r4,r4,2
+        sth     r0,0(r3)
+        addi    r3,r3,2
+
+14:     bf      cr7*4+3,15f
+        lbz     r0,0(r4)
+        stb     r0,0(r3)
+
+15:     addi    r1,r1,STACKFRAMESIZE
+        ld      r3,48(r1)
+        b       .exit_vmx_copy          /* tail call optimise */
+
+.Lvmx_unaligned_copy:
+        /* Get the destination 16B aligned */
+        neg     r6,r3
+        mtocrf  0x01,r6
+        clrldi  r6,r6,(64-4)
+
+        bf      cr7*4+3,1f
+        lbz     r0,0(r4)
+        addi    r4,r4,1
+        stb     r0,0(r3)
+        addi    r3,r3,1
+
+1:      bf      cr7*4+2,2f
+        lhz     r0,0(r4)
+        addi    r4,r4,2
+        sth     r0,0(r3)
+        addi    r3,r3,2
+
+2:      bf      cr7*4+1,3f
+        lwz     r0,0(r4)
+        addi    r4,r4,4
+        stw     r0,0(r3)
+        addi    r3,r3,4
+
+3:      bf      cr7*4+0,4f
+        lwz     r0,0(r4)        /* Less chance of a reject with word ops */
+        lwz     r7,4(r4)
+        addi    r4,r4,8
+        stw     r0,0(r3)
+        stw     r7,4(r3)
+        addi    r3,r3,8
+
+4:      sub     r5,r5,r6
+
+        /* Get the desination 128B aligned */
+        neg     r6,r3
+        srdi    r7,r6,4
+        mtocrf  0x01,r7
+        clrldi  r6,r6,(64-7)
+
+        li      r9,16
+        li      r10,32
+        li      r11,48
+
+        lvsl    vr16,0,r4       /* Setup permute control vector */
+        lvx     vr0,0,r4
+        addi    r4,r4,16
+
+        bf      cr7*4+3,5f
+        lvx     vr1,r0,r4
+        vperm   vr8,vr0,vr1,vr16
+        addi    r4,r4,16
+        stvx    vr8,r0,r3
+        addi    r3,r3,16
+        vor     vr0,vr1,vr1
+
+5:      bf      cr7*4+2,6f
+        lvx     vr1,r0,r4
+        vperm   vr8,vr0,vr1,vr16
+        lvx     vr0,r4,r9
+        vperm   vr9,vr1,vr0,vr16
+        addi    r4,r4,32
+        stvx    vr8,r0,r3
+        stvx    vr9,r3,r9
+        addi    r3,r3,32
+
+6:      bf      cr7*4+1,7f
+        lvx     vr3,r0,r4
+        vperm   vr8,vr0,vr3,vr16
+        lvx     vr2,r4,r9
+        vperm   vr9,vr3,vr2,vr16
+        lvx     vr1,r4,r10
+        vperm   vr10,vr2,vr1,vr16
+        lvx     vr0,r4,r11
+        vperm   vr11,vr1,vr0,vr16
+        addi    r4,r4,64
+        stvx    vr8,r0,r3
+        stvx    vr9,r3,r9
+        stvx    vr10,r3,r10
+        stvx    vr11,r3,r11
+        addi    r3,r3,64
+
+7:      sub     r5,r5,r6
+        srdi    r6,r5,7
+
+        std     r14,STK_REG(R14)(r1)
+        std     r15,STK_REG(R15)(r1)
+        std     r16,STK_REG(R16)(r1)
+
+        li      r12,64
+        li      r14,80
+        li      r15,96
+        li      r16,112
+
+        mtctr   r6
+
+        /*
+         * Now do cacheline sized loads and stores. By this stage the
+         * cacheline stores are also cacheline aligned.
+         */
+        .align  5
+8:
+        lvx     vr7,r0,r4
+        vperm   vr8,vr0,vr7,vr16
+        lvx     vr6,r4,r9
+        vperm   vr9,vr7,vr6,vr16
+        lvx     vr5,r4,r10
+        vperm   vr10,vr6,vr5,vr16
+        lvx     vr4,r4,r11
+        vperm   vr11,vr5,vr4,vr16
+        lvx     vr3,r4,r12
+        vperm   vr12,vr4,vr3,vr16
+        lvx     vr2,r4,r14
+        vperm   vr13,vr3,vr2,vr16
+        lvx     vr1,r4,r15
+        vperm   vr14,vr2,vr1,vr16
+        lvx     vr0,r4,r16
+        vperm   vr15,vr1,vr0,vr16
+        addi    r4,r4,128
+        stvx    vr8,r0,r3
+        stvx    vr9,r3,r9
+        stvx    vr10,r3,r10
+        stvx    vr11,r3,r11
+        stvx    vr12,r3,r12
+        stvx    vr13,r3,r14
+        stvx    vr14,r3,r15
+        stvx    vr15,r3,r16
+        addi    r3,r3,128
+        bdnz    8b
+
+        ld      r14,STK_REG(R14)(r1)
+        ld      r15,STK_REG(R15)(r1)
+        ld      r16,STK_REG(R16)(r1)
+
+        /* Up to 127B to go */
+        clrldi  r5,r5,(64-7)
+        srdi    r6,r5,4
+        mtocrf  0x01,r6
+
+        bf      cr7*4+1,9f
+        lvx     vr3,r0,r4
+        vperm   vr8,vr0,vr3,vr16
+        lvx     vr2,r4,r9
+        vperm   vr9,vr3,vr2,vr16
+        lvx     vr1,r4,r10
+        vperm   vr10,vr2,vr1,vr16
+        lvx     vr0,r4,r11
+        vperm   vr11,vr1,vr0,vr16
+        addi    r4,r4,64
+        stvx    vr8,r0,r3
+        stvx    vr9,r3,r9
+        stvx    vr10,r3,r10
+        stvx    vr11,r3,r11
+        addi    r3,r3,64
+
+9:      bf      cr7*4+2,10f
+        lvx     vr1,r0,r4
+        vperm   vr8,vr0,vr1,vr16
+        lvx     vr0,r4,r9
+        vperm   vr9,vr1,vr0,vr16
+        addi    r4,r4,32
+        stvx    vr8,r0,r3
+        stvx    vr9,r3,r9
+        addi    r3,r3,32
+
+10:     bf      cr7*4+3,11f
+        lvx     vr1,r0,r4
+        vperm   vr8,vr0,vr1,vr16
+        addi    r4,r4,16
+        stvx    vr8,r0,r3
+        addi    r3,r3,16
+
+        /* Up to 15B to go */
+11:     clrldi  r5,r5,(64-4)
+        addi    r4,r4,-16       /* Unwind the +16 load offset */
+        mtocrf  0x01,r5
+        bf      cr7*4+0,12f
+        lwz     r0,0(r4)        /* Less chance of a reject with word ops */
+        lwz     r6,4(r4)
+        addi    r4,r4,8
+        stw     r0,0(r3)
+        stw     r6,4(r3)
+        addi    r3,r3,8
+
+12:     bf      cr7*4+1,13f
+        lwz     r0,0(r4)
+        addi    r4,r4,4
+        stw     r0,0(r3)
+        addi    r3,r3,4
+
+13:     bf      cr7*4+2,14f
+        lhz     r0,0(r4)
+        addi    r4,r4,2
+        sth     r0,0(r3)
+        addi    r3,r3,2
+
+14:     bf      cr7*4+3,15f
+        lbz     r0,0(r4)
+        stb     r0,0(r3)
+
+15:     addi    r1,r1,STACKFRAMESIZE
+        ld      r3,48(r1)
+        b       .exit_vmx_copy          /* tail call optimise */
+#endif /* CONFiG_ALTIVEC */
diff --git a/arch/powerpc/lib/string.S b/arch/powerpc/lib/string.S
index 093d6316435..1b5a0a09d60 100644
--- a/arch/powerpc/lib/string.S
+++ b/arch/powerpc/lib/string.S
@@ -119,6 +119,7 @@ _GLOBAL(memchr)
 2:      li      r3,0
         blr
 
+#ifdef CONFIG_PPC32
 _GLOBAL(__clear_user)
         addi    r6,r3,-4
         li      r3,0
@@ -160,3 +161,4 @@ _GLOBAL(__clear_user)
         PPC_LONG        1b,91b
         PPC_LONG        8b,92b
         .text
+#endif
diff --git a/arch/powerpc/lib/string_64.S b/arch/powerpc/lib/string_64.S
new file mode 100644
index 00000000000..3b1e48049fa
--- /dev/null
+++ b/arch/powerpc/lib/string_64.S
@@ -0,0 +1,202 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) IBM Corporation, 2012
+ *
+ * Author: Anton Blanchard <anton@au.ibm.com>
+ */
+
+#include <asm/ppc_asm.h>
+#include <asm/asm-offsets.h>
+
+        .section        ".toc","aw"
+PPC64_CACHES:
+        .tc             ppc64_caches[TC],ppc64_caches
+        .section        ".text"
+
+/**
+ * __clear_user: - Zero a block of memory in user space, with less checking.
+ * @to:   Destination address, in user space.
+ * @n:    Number of bytes to zero.
+ *
+ * Zero a block of memory in user space.  Caller must check
+ * the specified block with access_ok() before calling this function.
+ *
+ * Returns number of bytes that could not be cleared.
+ * On success, this will be zero.
+ */
+
+        .macro err1
+100:
+        .section __ex_table,"a"
+        .align 3
+        .llong 100b,.Ldo_err1
+        .previous
+        .endm
+
+        .macro err2
+200:
+        .section __ex_table,"a"
+        .align 3
+        .llong 200b,.Ldo_err2
+        .previous
+        .endm
+
+        .macro err3
+300:
+        .section __ex_table,"a"
+        .align 3
+        .llong 300b,.Ldo_err3
+        .previous
+        .endm
+
+.Ldo_err1:
+        mr      r3,r8
+
+.Ldo_err2:
+        mtctr   r4
+1:
+err3;   stb     r0,0(r3)
+        addi    r3,r3,1
+        addi    r4,r4,-1
+        bdnz    1b
+
+.Ldo_err3:
+        mr      r3,r4
+        blr
+
+_GLOBAL(__clear_user)
+        cmpdi   r4,32
+        neg     r6,r3
+        li      r0,0
+        blt     .Lshort_clear
+        mr      r8,r3
+        mtocrf  0x01,r6
+        clrldi  r6,r6,(64-3)
+
+        /* Get the destination 8 byte aligned */
+        bf      cr7*4+3,1f
+err1;   stb     r0,0(r3)
+        addi    r3,r3,1
+
+1:      bf      cr7*4+2,2f
+err1;   sth     r0,0(r3)
+        addi    r3,r3,2
+
+2:      bf      cr7*4+1,3f
+err1;   stw     r0,0(r3)
+        addi    r3,r3,4
+
+3:      sub     r4,r4,r6
+
+        cmpdi   r4,32
+        cmpdi   cr1,r4,512
+        blt     .Lshort_clear
+        bgt     cr1,.Llong_clear
+
+.Lmedium_clear:
+        srdi    r6,r4,5
+        mtctr   r6
+
+        /* Do 32 byte chunks */
+4:
+err2;   std     r0,0(r3)
+err2;   std     r0,8(r3)
+err2;   std     r0,16(r3)
+err2;   std     r0,24(r3)
+        addi    r3,r3,32
+        addi    r4,r4,-32
+        bdnz    4b
+
+.Lshort_clear:
+        /* up to 31 bytes to go */
+        cmpdi   r4,16
+        blt     6f
+err2;   std     r0,0(r3)
+err2;   std     r0,8(r3)
+        addi    r3,r3,16
+        addi    r4,r4,-16
+
+        /* Up to 15 bytes to go */
+6:      mr      r8,r3
+        clrldi  r4,r4,(64-4)
+        mtocrf  0x01,r4
+        bf      cr7*4+0,7f
+err1;   std     r0,0(r3)
+        addi    r3,r3,8
+
+7:      bf      cr7*4+1,8f
+err1;   stw     r0,0(r3)
+        addi    r3,r3,4
+
+8:      bf      cr7*4+2,9f
+err1;   sth     r0,0(r3)
+        addi    r3,r3,2
+
+9:      bf      cr7*4+3,10f
+err1;   stb     r0,0(r3)
+
+10:     li      r3,0
+        blr
+
+.Llong_clear:
+        ld      r5,PPC64_CACHES@toc(r2)
+
+        bf      cr7*4+0,11f
+err2;   std     r0,0(r3)
+        addi    r3,r3,8
+        addi    r4,r4,-8
+
+        /* Destination is 16 byte aligned, need to get it cacheline aligned */
+11:     lwz     r7,DCACHEL1LOGLINESIZE(r5)
+        lwz     r9,DCACHEL1LINESIZE(r5)
+
+        /*
+         * With worst case alignment the long clear loop takes a minimum
+         * of 1 byte less than 2 cachelines.
+         */
+        sldi    r10,r9,2
+        cmpd    r4,r10
+        blt     .Lmedium_clear
+
+        neg     r6,r3
+        addi    r10,r9,-1
+        and.    r5,r6,r10
+        beq     13f
+
+        srdi    r6,r5,4
+        mtctr   r6
+        mr      r8,r3
+12:
+err1;   std     r0,0(r3)
+err1;   std     r0,8(r3)
+        addi    r3,r3,16
+        bdnz    12b
+
+        sub     r4,r4,r5
+
+13:     srd     r6,r4,r7
+        mtctr   r6
+        mr      r8,r3
+14:
+err1;   dcbz    r0,r3
+        add     r3,r3,r9
+        bdnz    14b
+
+        and     r4,r4,r10
+
+        cmpdi   r4,32
+        blt     .Lshort_clear
+        b       .Lmedium_clear
diff --git a/arch/powerpc/lib/copyuser_power7_vmx.c b/arch/powerpc/lib/vmx-helper.c
index bf2654f2b68..3cf529ceec5 100644
--- a/arch/powerpc/lib/copyuser_power7_vmx.c
+++ b/arch/powerpc/lib/vmx-helper.c
@@ -22,7 +22,7 @@
 #include <linux/hardirq.h>
 #include <asm/switch_to.h>
 
-int enter_vmx_copy(void)
+int enter_vmx_usercopy(void)
 {
         if (in_interrupt())
                 return 0;
@@ -44,8 +44,31 @@ int enter_vmx_copy(void)
  * This function must return 0 because we tail call optimise when calling
  * from __copy_tofrom_user_power7 which returns 0 on success.
  */
-int exit_vmx_copy(void)
+int exit_vmx_usercopy(void)
 {
         pagefault_enable();
         return 0;
 }
+
+int enter_vmx_copy(void)
+{
+        if (in_interrupt())
+                return 0;
+
+        preempt_disable();
+
+        enable_kernel_altivec();
+
+        return 1;
+}
+
+/*
+ * All calls to this function will be optimised into tail calls. We are
+ * passed a pointer to the destination which we return as required by a
+ * memcpy implementation.
+ */
+void *exit_vmx_copy(void *dest)
+{
+        preempt_enable();
+        return dest;
+}
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index b13d58932bf..115347f74ce 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -184,7 +184,7 @@ _GLOBAL(add_hash_page)
         add     r3,r3,r0                /* note create_hpte trims to 24 bits */
 
 #ifdef CONFIG_SMP
-        rlwinm  r8,r1,0,0,(31-THREAD_SHIFT) /* use cpu number to make tag */
+        CURRENT_THREAD_INFO(r8, r1)     /* use cpu number to make tag */
         lwz     r8,TI_CPU(r8)           /* to go in mmu_hash_lock */
         oris    r8,r8,12
 #endif /* CONFIG_SMP */
@@ -545,7 +545,7 @@ _GLOBAL(flush_hash_pages)
 #ifdef CONFIG_SMP
         addis   r9,r7,mmu_hash_lock@ha
         addi    r9,r9,mmu_hash_lock@l
-        rlwinm  r8,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r8, r1)
         add     r8,r8,r7
         lwz     r8,TI_CPU(r8)
         oris    r8,r8,9
@@ -639,7 +639,7 @@ _GLOBAL(flush_hash_patch_B)
  */
 _GLOBAL(_tlbie)
 #ifdef CONFIG_SMP
-        rlwinm  r8,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r8, r1)
         lwz     r8,TI_CPU(r8)
         oris    r8,r8,11
         mfmsr   r10
@@ -677,7 +677,7 @@ _GLOBAL(_tlbie)
  */
 _GLOBAL(_tlbia)
 #if defined(CONFIG_SMP)
-        rlwinm  r8,r1,0,0,(31-THREAD_SHIFT)
+        CURRENT_THREAD_INFO(r8, r1)
         lwz     r8,TI_CPU(r8)
         oris    r8,r8,10
         mfmsr   r10
diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
index a242b5d7cbe..602aeb06d29 100644
--- a/arch/powerpc/mm/hash_low_64.S
+++ b/arch/powerpc/mm/hash_low_64.S
@@ -34,14 +34,6 @@
  *         |   CR save area                     (SP + 8)
  * SP ---> +-- Back chain                       (SP + 0)
  */
-#define STACKFRAMESIZE  256
-
-/* Save parameters offsets */
-#define STK_PARM(i)     (STACKFRAMESIZE + 48 + ((i)-3)*8)
-
-/* Save non-volatile offsets */
-#define STK_REG(i)      (112 + ((i)-14)*8)
-
 
 #ifndef CONFIG_PPC_64K_PAGES
 
@@ -64,9 +56,9 @@ _GLOBAL(__hash_page_4K)
         std     r0,16(r1)
         stdu    r1,-STACKFRAMESIZE(r1)
         /* Save all params that we need after a function call */
-        std     r6,STK_PARM(r6)(r1)
-        std     r8,STK_PARM(r8)(r1)
-        std     r9,STK_PARM(r9)(r1)
+        std     r6,STK_PARAM(R6)(r1)
+        std     r8,STK_PARAM(R8)(r1)
+        std     r9,STK_PARAM(R9)(r1)
         
         /* Save non-volatile registers.
          * r31 will hold "old PTE"
@@ -75,11 +67,11 @@ _GLOBAL(__hash_page_4K)
          * r28 is a hash value
          * r27 is hashtab mask (maybe dynamic patched instead ?)
          */
-        std     r27,STK_REG(r27)(r1)
-        std     r28,STK_REG(r28)(r1)
-        std     r29,STK_REG(r29)(r1)
-        std     r30,STK_REG(r30)(r1)
-        std     r31,STK_REG(r31)(r1)
+        std     r27,STK_REG(R27)(r1)
+        std     r28,STK_REG(R28)(r1)
+        std     r29,STK_REG(R29)(r1)
+        std     r30,STK_REG(R30)(r1)
+        std     r31,STK_REG(R31)(r1)
         
         /* Step 1:
          *
@@ -162,7 +154,7 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
         /* At this point, r3 contains new PP bits, save them in
          * place of "access" in the param area (sic)
          */
-        std     r3,STK_PARM(r4)(r1)
+        std     r3,STK_PARAM(R4)(r1)
 
         /* Get htab_hash_mask */
         ld      r4,htab_hash_mask@got(2)
@@ -192,11 +184,11 @@ htab_insert_pte:
         rldicr  r3,r0,3,63-3            /* r3 = (hash & mask) << 3 */
 
         /* Call ppc_md.hpte_insert */
-        ld      r6,STK_PARM(r4)(r1)     /* Retrieve new pp bits */
+        ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
         mr      r4,r29                  /* Retrieve va */
         li      r7,0                    /* !bolted, !secondary */
         li      r8,MMU_PAGE_4K          /* page size */
-        ld      r9,STK_PARM(r9)(r1)     /* segment size */
+        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
 _GLOBAL(htab_call_hpte_insert1)
         bl      .                       /* Patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -215,11 +207,11 @@ _GLOBAL(htab_call_hpte_insert1)
         rldicr  r3,r0,3,63-3    /* r0 = (~hash & mask) << 3 */
         
         /* Call ppc_md.hpte_insert */
-        ld      r6,STK_PARM(r4)(r1)     /* Retrieve new pp bits */
+        ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
         mr      r4,r29                  /* Retrieve va */
         li      r7,HPTE_V_SECONDARY     /* !bolted, secondary */
         li      r8,MMU_PAGE_4K          /* page size */
-        ld      r9,STK_PARM(r9)(r1)     /* segment size */
+        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
 _GLOBAL(htab_call_hpte_insert2)
         bl      .                       /* Patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -255,15 +247,15 @@ htab_pte_insert_ok:
          * (maybe add eieio may be good still ?)
          */
 htab_write_out_pte:
-        ld      r6,STK_PARM(r6)(r1)
+        ld      r6,STK_PARAM(R6)(r1)
         std     r30,0(r6)
         li      r3, 0
 htab_bail:
-        ld      r27,STK_REG(r27)(r1)
-        ld      r28,STK_REG(r28)(r1)
-        ld      r29,STK_REG(r29)(r1)
-        ld      r30,STK_REG(r30)(r1)
-        ld      r31,STK_REG(r31)(r1)
+        ld      r27,STK_REG(R27)(r1)
+        ld      r28,STK_REG(R28)(r1)
+        ld      r29,STK_REG(R29)(r1)
+        ld      r30,STK_REG(R30)(r1)
+        ld      r31,STK_REG(R31)(r1)
         addi    r1,r1,STACKFRAMESIZE
         ld      r0,16(r1)
         mtlr    r0
@@ -288,8 +280,8 @@ htab_modify_pte:
         /* Call ppc_md.hpte_updatepp */
         mr      r5,r29                  /* va */
         li      r6,MMU_PAGE_4K          /* page size */
-        ld      r7,STK_PARM(r9)(r1)     /* segment size */
-        ld      r8,STK_PARM(r8)(r1)     /* get "local" param */
+        ld      r7,STK_PARAM(R9)(r1)    /* segment size */
+        ld      r8,STK_PARAM(R8)(r1)    /* get "local" param */
 _GLOBAL(htab_call_hpte_updatepp)
         bl      .                       /* Patched by htab_finish_init() */
 
@@ -312,7 +304,7 @@ htab_wrong_access:
 
 htab_pte_insert_failure:
         /* Bail out restoring old PTE */
-        ld      r6,STK_PARM(r6)(r1)
+        ld      r6,STK_PARAM(R6)(r1)
         std     r31,0(r6)
         li      r3,-1
         b       htab_bail
@@ -340,9 +332,9 @@ _GLOBAL(__hash_page_4K)
         std     r0,16(r1)
         stdu    r1,-STACKFRAMESIZE(r1)
         /* Save all params that we need after a function call */
-        std     r6,STK_PARM(r6)(r1)
-        std     r8,STK_PARM(r8)(r1)
-        std     r9,STK_PARM(r9)(r1)
+        std     r6,STK_PARAM(R6)(r1)
+        std     r8,STK_PARAM(R8)(r1)
+        std     r9,STK_PARAM(R9)(r1)
 
         /* Save non-volatile registers.
          * r31 will hold "old PTE"
@@ -353,13 +345,13 @@ _GLOBAL(__hash_page_4K)
          * r26 is the hidx mask
          * r25 is the index in combo page
          */
-        std     r25,STK_REG(r25)(r1)
-        std     r26,STK_REG(r26)(r1)
-        std     r27,STK_REG(r27)(r1)
-        std     r28,STK_REG(r28)(r1)
-        std     r29,STK_REG(r29)(r1)
-        std     r30,STK_REG(r30)(r1)
-        std     r31,STK_REG(r31)(r1)
+        std     r25,STK_REG(R25)(r1)
+        std     r26,STK_REG(R26)(r1)
+        std     r27,STK_REG(R27)(r1)
+        std     r28,STK_REG(R28)(r1)
+        std     r29,STK_REG(R29)(r1)
+        std     r30,STK_REG(R30)(r1)
+        std     r31,STK_REG(R31)(r1)
 
         /* Step 1:
          *
@@ -452,7 +444,7 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
         /* At this point, r3 contains new PP bits, save them in
          * place of "access" in the param area (sic)
          */
-        std     r3,STK_PARM(r4)(r1)
+        std     r3,STK_PARAM(R4)(r1)
 
         /* Get htab_hash_mask */
         ld      r4,htab_hash_mask@got(2)
@@ -473,7 +465,7 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
         andis.  r0,r31,_PAGE_COMBO@h
         beq     htab_inval_old_hpte
 
-        ld      r6,STK_PARM(r6)(r1)
+        ld      r6,STK_PARAM(R6)(r1)
         ori     r26,r6,0x8000           /* Load the hidx mask */
         ld      r26,0(r26)
         addi    r5,r25,36               /* Check actual HPTE_SUB bit, this */
@@ -495,11 +487,11 @@ htab_special_pfn:
         rldicr  r3,r0,3,63-3            /* r0 = (hash & mask) << 3 */
 
         /* Call ppc_md.hpte_insert */
-        ld      r6,STK_PARM(r4)(r1)     /* Retrieve new pp bits */
+        ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
         mr      r4,r29                  /* Retrieve va */
         li      r7,0                    /* !bolted, !secondary */
         li      r8,MMU_PAGE_4K          /* page size */
-        ld      r9,STK_PARM(r9)(r1)     /* segment size */
+        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
 _GLOBAL(htab_call_hpte_insert1)
         bl      .                       /* patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -522,11 +514,11 @@ _GLOBAL(htab_call_hpte_insert1)
         rldicr  r3,r0,3,63-3            /* r0 = (~hash & mask) << 3 */
 
         /* Call ppc_md.hpte_insert */
-        ld      r6,STK_PARM(r4)(r1)     /* Retrieve new pp bits */
+        ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
         mr      r4,r29                  /* Retrieve va */
         li      r7,HPTE_V_SECONDARY     /* !bolted, secondary */
         li      r8,MMU_PAGE_4K          /* page size */
-        ld      r9,STK_PARM(r9)(r1)     /* segment size */
+        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
 _GLOBAL(htab_call_hpte_insert2)
         bl      .                       /* patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -559,8 +551,8 @@ htab_inval_old_hpte:
         mr      r4,r31                  /* PTE.pte */
         li      r5,0                    /* PTE.hidx */
         li      r6,MMU_PAGE_64K         /* psize */
-        ld      r7,STK_PARM(r9)(r1)     /* ssize */
-        ld      r8,STK_PARM(r8)(r1)     /* local */
+        ld      r7,STK_PARAM(R9)(r1)    /* ssize */
+        ld      r8,STK_PARAM(R8)(r1)    /* local */
         bl      .flush_hash_page
         /* Clear out _PAGE_HPTE_SUB bits in the new linux PTE */
         lis     r0,_PAGE_HPTE_SUB@h
@@ -576,7 +568,7 @@ htab_pte_insert_ok:
         /* Insert slot number & secondary bit in PTE second half,
          * clear _PAGE_BUSY and set approriate HPTE slot bit
          */
-        ld      r6,STK_PARM(r6)(r1)
+        ld      r6,STK_PARAM(R6)(r1)
         li      r0,_PAGE_BUSY
         andc    r30,r30,r0
         /* HPTE SUB bit */
@@ -597,13 +589,13 @@ htab_pte_insert_ok:
         std     r30,0(r6)
         li      r3, 0
 htab_bail:
-        ld      r25,STK_REG(r25)(r1)
-        ld      r26,STK_REG(r26)(r1)
-        ld      r27,STK_REG(r27)(r1)
-        ld      r28,STK_REG(r28)(r1)
-        ld      r29,STK_REG(r29)(r1)
-        ld      r30,STK_REG(r30)(r1)
-        ld      r31,STK_REG(r31)(r1)
+        ld      r25,STK_REG(R25)(r1)
+        ld      r26,STK_REG(R26)(r1)
+        ld      r27,STK_REG(R27)(r1)
+        ld      r28,STK_REG(R28)(r1)
+        ld      r29,STK_REG(R29)(r1)
+        ld      r30,STK_REG(R30)(r1)
+        ld      r31,STK_REG(R31)(r1)
         addi    r1,r1,STACKFRAMESIZE
         ld      r0,16(r1)
         mtlr    r0
@@ -630,8 +622,8 @@ htab_modify_pte:
         /* Call ppc_md.hpte_updatepp */
         mr      r5,r29                  /* va */
         li      r6,MMU_PAGE_4K          /* page size */
-        ld      r7,STK_PARM(r9)(r1)     /* segment size */
-        ld      r8,STK_PARM(r8)(r1)     /* get "local" param */
+        ld      r7,STK_PARAM(R9)(r1)    /* segment size */
+        ld      r8,STK_PARAM(R8)(r1)    /* get "local" param */
 _GLOBAL(htab_call_hpte_updatepp)
         bl      .                       /* patched by htab_finish_init() */
 
@@ -644,7 +636,7 @@ _GLOBAL(htab_call_hpte_updatepp)
         /* Clear the BUSY bit and Write out the PTE */
         li      r0,_PAGE_BUSY
         andc    r30,r30,r0
-        ld      r6,STK_PARM(r6)(r1)
+        ld      r6,STK_PARAM(R6)(r1)
         std     r30,0(r6)
         li      r3,0
         b       htab_bail
@@ -657,7 +649,7 @@ htab_wrong_access:
 
 htab_pte_insert_failure:
         /* Bail out restoring old PTE */
-        ld      r6,STK_PARM(r6)(r1)
+        ld      r6,STK_PARAM(R6)(r1)
         std     r31,0(r6)
         li      r3,-1
         b       htab_bail
@@ -677,9 +669,9 @@ _GLOBAL(__hash_page_64K)
         std     r0,16(r1)
         stdu    r1,-STACKFRAMESIZE(r1)
         /* Save all params that we need after a function call */
-        std     r6,STK_PARM(r6)(r1)
-        std     r8,STK_PARM(r8)(r1)
-        std     r9,STK_PARM(r9)(r1)
+        std     r6,STK_PARAM(R6)(r1)
+        std     r8,STK_PARAM(R8)(r1)
+        std     r9,STK_PARAM(R9)(r1)
 
         /* Save non-volatile registers.
          * r31 will hold "old PTE"
@@ -688,11 +680,11 @@ _GLOBAL(__hash_page_64K)
          * r28 is a hash value
          * r27 is hashtab mask (maybe dynamic patched instead ?)
          */
-        std     r27,STK_REG(r27)(r1)
-        std     r28,STK_REG(r28)(r1)
-        std     r29,STK_REG(r29)(r1)
-        std     r30,STK_REG(r30)(r1)
-        std     r31,STK_REG(r31)(r1)
+        std     r27,STK_REG(R27)(r1)
+        std     r28,STK_REG(R28)(r1)
+        std     r29,STK_REG(R29)(r1)
+        std     r30,STK_REG(R30)(r1)
+        std     r31,STK_REG(R31)(r1)
 
         /* Step 1:
          *
@@ -780,7 +772,7 @@ END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)
         /* At this point, r3 contains new PP bits, save them in
          * place of "access" in the param area (sic)
          */
-        std     r3,STK_PARM(r4)(r1)
+        std     r3,STK_PARAM(R4)(r1)
 
         /* Get htab_hash_mask */
         ld      r4,htab_hash_mask@got(2)
@@ -813,11 +805,11 @@ ht64_insert_pte:
         rldicr  r3,r0,3,63-3    /* r0 = (hash & mask) << 3 */
 
         /* Call ppc_md.hpte_insert */
-        ld      r6,STK_PARM(r4)(r1)     /* Retrieve new pp bits */
+        ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
         mr      r4,r29                  /* Retrieve va */
         li      r7,0                    /* !bolted, !secondary */
         li      r8,MMU_PAGE_64K
-        ld      r9,STK_PARM(r9)(r1)     /* segment size */
+        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
 _GLOBAL(ht64_call_hpte_insert1)
         bl      .                       /* patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -836,11 +828,11 @@ _GLOBAL(ht64_call_hpte_insert1)
         rldicr  r3,r0,3,63-3    /* r0 = (~hash & mask) << 3 */
 
         /* Call ppc_md.hpte_insert */
-        ld      r6,STK_PARM(r4)(r1)     /* Retrieve new pp bits */
+        ld      r6,STK_PARAM(R4)(r1)    /* Retrieve new pp bits */
         mr      r4,r29                  /* Retrieve va */
         li      r7,HPTE_V_SECONDARY     /* !bolted, secondary */
         li      r8,MMU_PAGE_64K
-        ld      r9,STK_PARM(r9)(r1)     /* segment size */
+        ld      r9,STK_PARAM(R9)(r1)    /* segment size */
 _GLOBAL(ht64_call_hpte_insert2)
         bl      .                       /* patched by htab_finish_init() */
         cmpdi   0,r3,0
@@ -876,15 +868,15 @@ ht64_pte_insert_ok:
          * (maybe add eieio may be good still ?)
          */
 ht64_write_out_pte:
-        ld      r6,STK_PARM(r6)(r1)
+        ld      r6,STK_PARAM(R6)(r1)
         std     r30,0(r6)
         li      r3, 0
 ht64_bail:
-        ld      r27,STK_REG(r27)(r1)
-        ld      r28,STK_REG(r28)(r1)
-        ld      r29,STK_REG(r29)(r1)
-        ld      r30,STK_REG(r30)(r1)
-        ld      r31,STK_REG(r31)(r1)
+        ld      r27,STK_REG(R27)(r1)
+        ld      r28,STK_REG(R28)(r1)
+        ld      r29,STK_REG(R29)(r1)
+        ld      r30,STK_REG(R30)(r1)
+        ld      r31,STK_REG(R31)(r1)
         addi    r1,r1,STACKFRAMESIZE
         ld      r0,16(r1)
         mtlr    r0
@@ -909,8 +901,8 @@ ht64_modify_pte:
         /* Call ppc_md.hpte_updatepp */
         mr      r5,r29                  /* va */
         li      r6,MMU_PAGE_64K
-        ld      r7,STK_PARM(r9)(r1)     /* segment size */
-        ld      r8,STK_PARM(r8)(r1)     /* get "local" param */
+        ld      r7,STK_PARAM(R9)(r1)    /* segment size */
+        ld      r8,STK_PARAM(R8)(r1)    /* get "local" param */
 _GLOBAL(ht64_call_hpte_updatepp)
         bl      .                       /* patched by htab_finish_init() */
 
@@ -933,7 +925,7 @@ ht64_wrong_access:
 
 ht64_pte_insert_failure:
         /* Bail out restoring old PTE */
-        ld      r6,STK_PARM(r6)(r1)
+        ld      r6,STK_PARAM(R6)(r1)
         std     r31,0(r6)
         li      r3,-1
         b       ht64_bail
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index baaafde7d13..fbdad0e3929 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -469,6 +469,7 @@ void flush_dcache_icache_page(struct page *page)
         __flush_dcache_icache_phys(page_to_pfn(page) << PAGE_SHIFT);
 #endif
 }
+EXPORT_SYMBOL(flush_dcache_icache_page);
 
 void clear_user_page(void *page, unsigned long vaddr, struct page *pg)
 {
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 1e95556dc69..59213cfaeca 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -340,6 +340,8 @@ static int __init find_min_common_depth(void)
                                 dbg("Using form 1 affinity\n");
                                 form1_affinity = 1;
                         }
+
+                        of_node_put(chosen);
                 }
         }
 
@@ -1434,11 +1436,11 @@ static long vphn_get_associativity(unsigned long cpu,
 
 /*
  * Update the node maps and sysfs entries for each cpu whose home node
- * has changed.
+ * has changed. Returns 1 when the topology has changed, and 0 otherwise.
  */
 int arch_update_cpu_topology(void)
 {
-        int cpu, nid, old_nid;
+        int cpu, nid, old_nid, changed = 0;
         unsigned int associativity[VPHN_ASSOC_BUFSIZE] = {0};
         struct device *dev;
 
@@ -1464,9 +1466,10 @@ int arch_update_cpu_topology(void)
                 dev = get_cpu_device(cpu);
                 if (dev)
                         kobject_uevent(&dev->kobj, KOBJ_CHANGE);
+                changed = 1;
         }
 
-        return 1;
+        return changed;
 }
 
 static void topology_work_fn(struct work_struct *work)
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index ff672bd8fea..f09d48e3268 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -126,7 +126,7 @@ BEGIN_MMU_FTR_SECTION
         /* Set the TLB reservation and search for existing entry. Then load
          * the entry.
          */
-        PPC_TLBSRX_DOT(0,r16)
+        PPC_TLBSRX_DOT(0,R16)
         ldx     r14,r14,r15             /* grab pgd entry */
         beq     normal_tlb_miss_done    /* tlb exists already, bail */
 MMU_FTR_SECTION_ELSE
@@ -395,7 +395,7 @@ BEGIN_MMU_FTR_SECTION
         /* Set the TLB reservation and search for existing entry. Then load
          * the entry.
          */
-        PPC_TLBSRX_DOT(0,r16)
+        PPC_TLBSRX_DOT(0,R16)
         ld      r14,0(r10)
         beq     normal_tlb_miss_done
 MMU_FTR_SECTION_ELSE
@@ -528,7 +528,7 @@ BEGIN_MMU_FTR_SECTION
         /* Search if we already have a TLB entry for that virtual address, and
          * if we do, bail out.
          */
-        PPC_TLBSRX_DOT(0,r16)
+        PPC_TLBSRX_DOT(0,R16)
         beq     virt_page_table_tlb_miss_done
 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
 
@@ -779,7 +779,7 @@ htw_tlb_miss:
          *
          * MAS1:IND should be already set based on MAS4
          */
-        PPC_TLBSRX_DOT(0,r16)
+        PPC_TLBSRX_DOT(0,R16)
         beq     htw_tlb_miss_done
 
         /* Now, we need to walk the page tables. First check if we are in
@@ -919,7 +919,7 @@ tlb_load_linear:
         mtspr   SPRN_MAS1,r15
 
         /* Already somebody there ? */
-        PPC_TLBSRX_DOT(0,r16)
+        PPC_TLBSRX_DOT(0,R16)
         beq     tlb_load_linear_done
 
         /* Now we build the remaining MAS. MAS0 and 2 should be fine
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 7c63c0ed4f1..fab919fd138 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -266,7 +266,7 @@ BEGIN_MMU_FTR_SECTION
         andi.   r3,r3,MMUCSR0_TLBFI@l
         bne     1b
 MMU_FTR_SECTION_ELSE
-        PPC_TLBILX_ALL(0,0)
+        PPC_TLBILX_ALL(0,R0)
 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
         msync
         isync
@@ -279,7 +279,7 @@ BEGIN_MMU_FTR_SECTION
         wrteei  0
         mfspr   r4,SPRN_MAS6    /* save MAS6 */
         mtspr   SPRN_MAS6,r3
-        PPC_TLBILX_PID(0,0)
+        PPC_TLBILX_PID(0,R0)
         mtspr   SPRN_MAS6,r4    /* restore MAS6 */
         wrtee   r10
 MMU_FTR_SECTION_ELSE
@@ -313,7 +313,7 @@ BEGIN_MMU_FTR_SECTION
         mtspr   SPRN_MAS1,r4
         tlbwe
 MMU_FTR_SECTION_ELSE
-        PPC_TLBILX_VA(0,r3)
+        PPC_TLBILX_VA(0,R3)
 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
         msync
         isync
@@ -331,7 +331,7 @@ _GLOBAL(_tlbil_pid)
         mfmsr   r10
         wrteei  0
         mtspr   SPRN_MAS6,r4
-        PPC_TLBILX_PID(0,0)
+        PPC_TLBILX_PID(0,R0)
         wrtee   r10
         msync
         isync
@@ -343,14 +343,14 @@ _GLOBAL(_tlbil_pid_noind)
         ori     r4,r4,MAS6_SIND
         wrteei  0
         mtspr   SPRN_MAS6,r4
-        PPC_TLBILX_PID(0,0)
+        PPC_TLBILX_PID(0,R0)
         wrtee   r10
         msync
         isync
         blr
 
 _GLOBAL(_tlbil_all)
-        PPC_TLBILX_ALL(0,0)
+        PPC_TLBILX_ALL(0,R0)
         msync
         isync
         blr
@@ -364,7 +364,7 @@ _GLOBAL(_tlbil_va)
         beq     1f
         rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
 1:      mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
-        PPC_TLBILX_VA(0,r3)
+        PPC_TLBILX_VA(0,R3)
         msync
         isync
         wrtee   r10
@@ -379,7 +379,7 @@ _GLOBAL(_tlbivax_bcast)
         beq     1f
         rlwimi  r4,r6,MAS6_SIND_SHIFT,MAS6_SIND
 1:      mtspr   SPRN_MAS6,r4            /* assume AS=0 for now */
-        PPC_TLBIVAX(0,r3)
+        PPC_TLBIVAX(0,R3)
         eieio
         tlbsync
         sync
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index 5c3cf2d04e4..1fc8109bf2f 100644
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -75,23 +75,23 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
 #define PPC_NOP()               EMIT(PPC_INST_NOP)
 #define PPC_BLR()               EMIT(PPC_INST_BLR)
 #define PPC_BLRL()              EMIT(PPC_INST_BLRL)
-#define PPC_MTLR(r)             EMIT(PPC_INST_MTLR | __PPC_RT(r))
-#define PPC_ADDI(d, a, i)       EMIT(PPC_INST_ADDI | __PPC_RT(d) |            \
-                                     __PPC_RA(a) | IMM_L(i))
+#define PPC_MTLR(r)             EMIT(PPC_INST_MTLR | ___PPC_RT(r))
+#define PPC_ADDI(d, a, i)       EMIT(PPC_INST_ADDI | ___PPC_RT(d) |           \
+                                     ___PPC_RA(a) | IMM_L(i))
 #define PPC_MR(d, a)            PPC_OR(d, a, a)
 #define PPC_LI(r, i)            PPC_ADDI(r, 0, i)
 #define PPC_ADDIS(d, a, i)      EMIT(PPC_INST_ADDIS |                         \
-                                     __PPC_RS(d) | __PPC_RA(a) | IMM_L(i))
+                                     ___PPC_RS(d) | ___PPC_RA(a) | IMM_L(i))
 #define PPC_LIS(r, i)           PPC_ADDIS(r, 0, i)
-#define PPC_STD(r, base, i)     EMIT(PPC_INST_STD | __PPC_RS(r) |             \
-                                     __PPC_RA(base) | ((i) & 0xfffc))
-
-#define PPC_LD(r, base, i)      EMIT(PPC_INST_LD | __PPC_RT(r) |              \
-                                     __PPC_RA(base) | IMM_L(i))
-#define PPC_LWZ(r, base, i)     EMIT(PPC_INST_LWZ | __PPC_RT(r) |             \
-                                     __PPC_RA(base) | IMM_L(i))
-#define PPC_LHZ(r, base, i)     EMIT(PPC_INST_LHZ | __PPC_RT(r) |             \
-                                     __PPC_RA(base) | IMM_L(i))
+#define PPC_STD(r, base, i)     EMIT(PPC_INST_STD | ___PPC_RS(r) |            \
+                                     ___PPC_RA(base) | ((i) & 0xfffc))
+
+#define PPC_LD(r, base, i)      EMIT(PPC_INST_LD | ___PPC_RT(r) |             \
+                                     ___PPC_RA(base) | IMM_L(i))
+#define PPC_LWZ(r, base, i)     EMIT(PPC_INST_LWZ | ___PPC_RT(r) |            \
+                                     ___PPC_RA(base) | IMM_L(i))
+#define PPC_LHZ(r, base, i)     EMIT(PPC_INST_LHZ | ___PPC_RT(r) |            \
+                                     ___PPC_RA(base) | IMM_L(i))
 /* Convenience helpers for the above with 'far' offsets: */
 #define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i);     \
                 else {  PPC_ADDIS(r, base, IMM_HA(i));                        \
@@ -105,52 +105,52 @@ DECLARE_LOAD_FUNC(sk_load_byte_msh);
                 else {  PPC_ADDIS(r, base, IMM_HA(i));                        \
                         PPC_LHZ(r, r, IMM_L(i)); } } while(0)
 
-#define PPC_CMPWI(a, i)         EMIT(PPC_INST_CMPWI | __PPC_RA(a) | IMM_L(i))
-#define PPC_CMPDI(a, i)         EMIT(PPC_INST_CMPDI | __PPC_RA(a) | IMM_L(i))
-#define PPC_CMPLWI(a, i)        EMIT(PPC_INST_CMPLWI | __PPC_RA(a) | IMM_L(i))
-#define PPC_CMPLW(a, b)         EMIT(PPC_INST_CMPLW | __PPC_RA(a) | __PPC_RB(b))
-
-#define PPC_SUB(d, a, b)        EMIT(PPC_INST_SUB | __PPC_RT(d) |             \
-                                     __PPC_RB(a) | __PPC_RA(b))
-#define PPC_ADD(d, a, b)        EMIT(PPC_INST_ADD | __PPC_RT(d) |             \
-                                     __PPC_RA(a) | __PPC_RB(b))
-#define PPC_MUL(d, a, b)        EMIT(PPC_INST_MULLW | __PPC_RT(d) |           \
-                                     __PPC_RA(a) | __PPC_RB(b))
-#define PPC_MULHWU(d, a, b)     EMIT(PPC_INST_MULHWU | __PPC_RT(d) |          \
-                                     __PPC_RA(a) | __PPC_RB(b))
-#define PPC_MULI(d, a, i)       EMIT(PPC_INST_MULLI | __PPC_RT(d) |           \
-                                     __PPC_RA(a) | IMM_L(i))
-#define PPC_DIVWU(d, a, b)      EMIT(PPC_INST_DIVWU | __PPC_RT(d) |           \
-                                     __PPC_RA(a) | __PPC_RB(b))
-#define PPC_AND(d, a, b)        EMIT(PPC_INST_AND | __PPC_RA(d) |             \
-                                     __PPC_RS(a) | __PPC_RB(b))
-#define PPC_ANDI(d, a, i)       EMIT(PPC_INST_ANDI | __PPC_RA(d) |            \
-                                     __PPC_RS(a) | IMM_L(i))
-#define PPC_AND_DOT(d, a, b)    EMIT(PPC_INST_ANDDOT | __PPC_RA(d) |          \
-                                     __PPC_RS(a) | __PPC_RB(b))
-#define PPC_OR(d, a, b)         EMIT(PPC_INST_OR | __PPC_RA(d) |              \
-                                     __PPC_RS(a) | __PPC_RB(b))
-#define PPC_ORI(d, a, i)        EMIT(PPC_INST_ORI | __PPC_RA(d) |             \
-                                     __PPC_RS(a) | IMM_L(i))
-#define PPC_ORIS(d, a, i)       EMIT(PPC_INST_ORIS | __PPC_RA(d) |            \
-                                     __PPC_RS(a) | IMM_L(i))
-#define PPC_SLW(d, a, s)        EMIT(PPC_INST_SLW | __PPC_RA(d) |             \
-                                     __PPC_RS(a) | __PPC_RB(s))
-#define PPC_SRW(d, a, s)        EMIT(PPC_INST_SRW | __PPC_RA(d) |             \
-                                     __PPC_RS(a) | __PPC_RB(s))
+#define PPC_CMPWI(a, i)         EMIT(PPC_INST_CMPWI | ___PPC_RA(a) | IMM_L(i))
+#define PPC_CMPDI(a, i)         EMIT(PPC_INST_CMPDI | ___PPC_RA(a) | IMM_L(i))
+#define PPC_CMPLWI(a, i)        EMIT(PPC_INST_CMPLWI | ___PPC_RA(a) | IMM_L(i))
+#define PPC_CMPLW(a, b)         EMIT(PPC_INST_CMPLW | ___PPC_RA(a) | ___PPC_RB(b))
+
+#define PPC_SUB(d, a, b)        EMIT(PPC_INST_SUB | ___PPC_RT(d) |            \
+                                     ___PPC_RB(a) | ___PPC_RA(b))
+#define PPC_ADD(d, a, b)        EMIT(PPC_INST_ADD | ___PPC_RT(d) |            \
+                                     ___PPC_RA(a) | ___PPC_RB(b))
+#define PPC_MUL(d, a, b)        EMIT(PPC_INST_MULLW | ___PPC_RT(d) |          \
+                                     ___PPC_RA(a) | ___PPC_RB(b))
+#define PPC_MULHWU(d, a, b)     EMIT(PPC_INST_MULHWU | ___PPC_RT(d) |         \
+                                     ___PPC_RA(a) | ___PPC_RB(b))
+#define PPC_MULI(d, a, i)       EMIT(PPC_INST_MULLI | ___PPC_RT(d) |          \
+                                     ___PPC_RA(a) | IMM_L(i))
+#define PPC_DIVWU(d, a, b)      EMIT(PPC_INST_DIVWU | ___PPC_RT(d) |          \
+                                     ___PPC_RA(a) | ___PPC_RB(b))
+#define PPC_AND(d, a, b)        EMIT(PPC_INST_AND | ___PPC_RA(d) |            \
+                                     ___PPC_RS(a) | ___PPC_RB(b))
+#define PPC_ANDI(d, a, i)       EMIT(PPC_INST_ANDI | ___PPC_RA(d) |           \
+                                     ___PPC_RS(a) | IMM_L(i))
+#define PPC_AND_DOT(d, a, b)    EMIT(PPC_INST_ANDDOT | ___PPC_RA(d) |         \
+                                     ___PPC_RS(a) | ___PPC_RB(b))
+#define PPC_OR(d, a, b)         EMIT(PPC_INST_OR | ___PPC_RA(d) |             \
+                                     ___PPC_RS(a) | ___PPC_RB(b))
+#define PPC_ORI(d, a, i)        EMIT(PPC_INST_ORI | ___PPC_RA(d) |            \
+                                     ___PPC_RS(a) | IMM_L(i))
+#define PPC_ORIS(d, a, i)       EMIT(PPC_INST_ORIS | ___PPC_RA(d) |           \
+                                     ___PPC_RS(a) | IMM_L(i))
+#define PPC_SLW(d, a, s)        EMIT(PPC_INST_SLW | ___PPC_RA(d) |            \
+                                     ___PPC_RS(a) | ___PPC_RB(s))
+#define PPC_SRW(d, a, s)        EMIT(PPC_INST_SRW | ___PPC_RA(d) |            \
+                                     ___PPC_RS(a) | ___PPC_RB(s))
 /* slwi = rlwinm Rx, Ry, n, 0, 31-n */
-#define PPC_SLWI(d, a, i)       EMIT(PPC_INST_RLWINM | __PPC_RA(d) |          \
-                                     __PPC_RS(a) | __PPC_SH(i) |              \
+#define PPC_SLWI(d, a, i)       EMIT(PPC_INST_RLWINM | ___PPC_RA(d) |         \
+                                     ___PPC_RS(a) | __PPC_SH(i) |             \
                                      __PPC_MB(0) | __PPC_ME(31-(i)))
 /* srwi = rlwinm Rx, Ry, 32-n, n, 31 */
-#define PPC_SRWI(d, a, i)       EMIT(PPC_INST_RLWINM | __PPC_RA(d) |          \
-                                     __PPC_RS(a) | __PPC_SH(32-(i)) |         \
+#define PPC_SRWI(d, a, i)       EMIT(PPC_INST_RLWINM | ___PPC_RA(d) |         \
+                                     ___PPC_RS(a) | __PPC_SH(32-(i)) |        \
                                      __PPC_MB(i) | __PPC_ME(31))
 /* sldi = rldicr Rx, Ry, n, 63-n */
-#define PPC_SLDI(d, a, i)       EMIT(PPC_INST_RLDICR | __PPC_RA(d) |          \
-                                     __PPC_RS(a) | __PPC_SH(i) |              \
+#define PPC_SLDI(d, a, i)       EMIT(PPC_INST_RLDICR | ___PPC_RA(d) |         \
+                                     ___PPC_RS(a) | __PPC_SH(i) |             \
                                      __PPC_MB(63-(i)) | (((i) & 0x20) >> 4))
-#define PPC_NEG(d, a)           EMIT(PPC_INST_NEG | __PPC_RT(d) | __PPC_RA(a))
+#define PPC_NEG(d, a)           EMIT(PPC_INST_NEG | ___PPC_RT(d) | ___PPC_RA(a))
 
 /* Long jump; (unconditional 'branch') */
 #define PPC_JMP(dest)           EMIT(PPC_INST_BRANCH |                        \
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index 2dc8b148484..dd1130642d0 100644
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -39,7 +39,7 @@ static void bpf_jit_build_prologue(struct sk_filter *fp, u32 *image,
                 /* Make stackframe */
                 if (ctx->seen & SEEN_DATAREF) {
                         /* If we call any helpers (for loads), save LR */
-                        EMIT(PPC_INST_MFLR | __PPC_RT(0));
+                        EMIT(PPC_INST_MFLR | __PPC_RT(R0));
                         PPC_STD(0, 1, 16);
 
                         /* Back up non-volatile regs. */
@@ -56,7 +56,7 @@ static void bpf_jit_build_prologue(struct sk_filter *fp, u32 *image,
                                         PPC_STD(i, 1, -(8*(32-i)));
                         }
                 }
-                EMIT(PPC_INST_STDU | __PPC_RS(1) | __PPC_RA(1) |
+                EMIT(PPC_INST_STDU | __PPC_RS(R1) | __PPC_RA(R1) |
                      (-BPF_PPC_STACKFRAME & 0xfffc));
         }
 
diff --git a/arch/powerpc/perf/callchain.c b/arch/powerpc/perf/callchain.c
index e8a18d1cc7c..74d1e780748 100644
--- a/arch/powerpc/perf/callchain.c
+++ b/arch/powerpc/perf/callchain.c
@@ -57,7 +57,7 @@ perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
 
         lr = regs->link;
         sp = regs->gpr[1];
-        perf_callchain_store(entry, regs->nip);
+        perf_callchain_store(entry, perf_instruction_pointer(regs));
 
         if (!validate_sp(sp, current, STACK_FRAME_OVERHEAD))
                 return;
@@ -238,7 +238,7 @@ static void perf_callchain_user_64(struct perf_callchain_entry *entry,
         struct signal_frame_64 __user *sigframe;
         unsigned long __user *fp, *uregs;
 
-        next_ip = regs->nip;
+        next_ip = perf_instruction_pointer(regs);
         lr = regs->link;
         sp = regs->gpr[1];
         perf_callchain_store(entry, next_ip);
@@ -444,7 +444,7 @@ static void perf_callchain_user_32(struct perf_callchain_entry *entry,
         long level = 0;
         unsigned int __user *fp, *uregs;
 
-        next_ip = regs->nip;
+        next_ip = perf_instruction_pointer(regs);
         lr = regs->link;
         sp = regs->gpr[1];
         perf_callchain_store(entry, next_ip);
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 8f84bcba18d..7cd2dbd6e4c 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -73,7 +73,10 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 {
         return 0;
 }
-static inline void perf_read_regs(struct pt_regs *regs) { }
+static inline void perf_read_regs(struct pt_regs *regs)
+{
+        regs->result = 0;
+}
 static inline int perf_intr_is_nmi(struct pt_regs *regs)
 {
         return 0;
@@ -116,6 +119,26 @@ static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
                 *addrp = mfspr(SPRN_SDAR);
 }
 
+static bool mmcra_sihv(unsigned long mmcra)
+{
+        unsigned long sihv = MMCRA_SIHV;
+
+        if (ppmu->flags & PPMU_ALT_SIPR)
+                sihv = POWER6_MMCRA_SIHV;
+
+        return !!(mmcra & sihv);
+}
+
+static bool mmcra_sipr(unsigned long mmcra)
+{
+        unsigned long sipr = MMCRA_SIPR;
+
+        if (ppmu->flags & PPMU_ALT_SIPR)
+                sipr = POWER6_MMCRA_SIPR;
+
+        return !!(mmcra & sipr);
+}
+
 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
 {
         if (regs->msr & MSR_PR)
@@ -128,19 +151,9 @@ static inline u32 perf_flags_from_msr(struct pt_regs *regs)
 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 {
         unsigned long mmcra = regs->dsisr;
-        unsigned long sihv = MMCRA_SIHV;
-        unsigned long sipr = MMCRA_SIPR;
+        unsigned long use_siar = regs->result;
 
-        /* Not a PMU interrupt: Make up flags from regs->msr */
-        if (TRAP(regs) != 0xf00)
-                return perf_flags_from_msr(regs);
-
-        /*
-         * If we don't support continuous sampling and this
-         * is not a marked event, same deal
-         */
-        if ((ppmu->flags & PPMU_NO_CONT_SAMPLING) &&
-            !(mmcra & MMCRA_SAMPLE_ENABLE))
+        if (!use_siar)
                 return perf_flags_from_msr(regs);
 
         /*
@@ -156,15 +169,10 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs)
                 return PERF_RECORD_MISC_USER;
         }
 
-        if (ppmu->flags & PPMU_ALT_SIPR) {
-                sihv = POWER6_MMCRA_SIHV;
-                sipr = POWER6_MMCRA_SIPR;
-        }
-
         /* PR has priority over HV, so order below is important */
-        if (mmcra & sipr)
+        if (mmcra_sipr(mmcra))
                 return PERF_RECORD_MISC_USER;
-        if ((mmcra & sihv) && (freeze_events_kernel != MMCR0_FCHV))
+        if (mmcra_sihv(mmcra) && (freeze_events_kernel != MMCR0_FCHV))
                 return PERF_RECORD_MISC_HYPERVISOR;
         return PERF_RECORD_MISC_KERNEL;
 }
@@ -172,10 +180,45 @@ static inline u32 perf_get_misc_flags(struct pt_regs *regs)
 /*
  * Overload regs->dsisr to store MMCRA so we only need to read it once
  * on each interrupt.
+ * Overload regs->result to specify whether we should use the MSR (result
+ * is zero) or the SIAR (result is non zero).
  */
 static inline void perf_read_regs(struct pt_regs *regs)
 {
-        regs->dsisr = mfspr(SPRN_MMCRA);
+        unsigned long mmcra = mfspr(SPRN_MMCRA);
+        int marked = mmcra & MMCRA_SAMPLE_ENABLE;
+        int use_siar;
+
+        /*
+         * If this isn't a PMU exception (eg a software event) the SIAR is
+         * not valid. Use pt_regs.
+         *
+         * If it is a marked event use the SIAR.
+         *
+         * If the PMU doesn't update the SIAR for non marked events use
+         * pt_regs.
+         *
+         * If the PMU has HV/PR flags then check to see if they
+         * place the exception in userspace. If so, use pt_regs. In
+         * continuous sampling mode the SIAR and the PMU exception are
+         * not synchronised, so they may be many instructions apart.
+         * This can result in confusing backtraces. We still want
+         * hypervisor samples as well as samples in the kernel with
+         * interrupts off hence the userspace check.
+         */
+        if (TRAP(regs) != 0xf00)
+                use_siar = 0;
+        else if (marked)
+                use_siar = 1;
+        else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
+                use_siar = 0;
+        else if (!(ppmu->flags & PPMU_NO_SIPR) && mmcra_sipr(mmcra))
+                use_siar = 0;
+        else
+                use_siar = 1;
+
+        regs->dsisr = mmcra;
+        regs->result = use_siar;
 }
 
 /*
@@ -1329,18 +1372,12 @@ unsigned long perf_misc_flags(struct pt_regs *regs)
  */
 unsigned long perf_instruction_pointer(struct pt_regs *regs)
 {
-        unsigned long mmcra = regs->dsisr;
+        unsigned long use_siar = regs->result;
 
-        /* Not a PMU interrupt */
-        if (TRAP(regs) != 0xf00)
-                return regs->nip;
-
-        /* Processor doesn't support sampling non marked events */
-        if ((ppmu->flags & PPMU_NO_CONT_SAMPLING) &&
-            !(mmcra & MMCRA_SAMPLE_ENABLE))
+        if (use_siar)
+                return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
+        else
                 return regs->nip;
-
-        return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
 }
 
 static bool pmc_overflow(unsigned long val)
@@ -1394,7 +1431,7 @@ static void perf_event_interrupt(struct pt_regs *regs)
                 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
                         continue;
                 val = read_pmc(event->hw.idx);
-                if ((int)val < 0) {
+                if (pmc_overflow(val)) {
                         /* event has overflowed */
                         found = 1;
                         record_and_restart(event, val, regs);
diff --git a/arch/powerpc/platforms/44x/currituck.c b/arch/powerpc/platforms/44x/currituck.c
index 583e67fee37..9f6c33d63a4 100644
--- a/arch/powerpc/platforms/44x/currituck.c
+++ b/arch/powerpc/platforms/44x/currituck.c
@@ -160,7 +160,7 @@ static void __init ppc47x_setup_arch(void)
         /* No need to check the DMA config as we /know/ our windows are all of
          * RAM.  Lets hope that doesn't change */
 #ifdef CONFIG_SWIOTLB
-        if (memblock_end_of_DRAM() > 0xffffffff) {
+        if ((memblock_end_of_DRAM() - 1) > 0xffffffff) {
                 ppc_swiotlb_enable = 1;
                 set_pci_dma_ops(&swiotlb_dma_ops);
                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
diff --git a/arch/powerpc/platforms/82xx/km82xx.c b/arch/powerpc/platforms/82xx/km82xx.c
index 3661bcdc326..cf964e19573 100644
--- a/arch/powerpc/platforms/82xx/km82xx.c
+++ b/arch/powerpc/platforms/82xx/km82xx.c
@@ -128,6 +128,11 @@ static __initdata struct cpm_pin km82xx_pins[] = {
         {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXP */
         {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY}, /* TXN */
         {3, 25, CPM_PIN_INPUT  | CPM_PIN_PRIMARY}, /* RXD */
+
+        /* SPI */
+        {3, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_MISO PD16 */
+        {3, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_MOSI PD17 */
+        {3, 18, CPM_PIN_INPUT | CPM_PIN_SECONDARY},/* SPI_CLK PD18 */
 };
 
 static void __init init_ioports(void)
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index a266ba87686..89923d72334 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -3,7 +3,7 @@
  * Author: Heiko Schocher <hs@denx.de>
  *
  * Description:
- * Keymile KMETER1 board specific routines.
+ * Keymile 83xx platform specific routines.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -70,54 +70,88 @@ static void __init mpc83xx_km_setup_arch(void)
                 for_each_node_by_name(np, "spi")
                         par_io_of_config(np);
 
-                for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
+                for_each_node_by_name(np, "ucc")
                         par_io_of_config(np);
         }
 
         np = of_find_compatible_node(NULL, "network", "ucc_geth");
         if (np != NULL) {
-                uint svid;
+                /*
+                 * handle mpc8360E Erratum QE_ENET10:
+                 * RGMII AC values do not meet the specification
+                 */
+                uint svid = mfspr(SPRN_SVR);
+                struct  device_node *np_par;
+                struct  resource res;
+                void    __iomem *base;
+                int     ret;
+
+                np_par = of_find_node_by_name(NULL, "par_io");
+                if (np_par == NULL) {
+                        printk(KERN_WARNING "%s couldn;t find par_io node\n",
+                                __func__);
+                        return;
+                }
+                /* Map Parallel I/O ports registers */
+                ret = of_address_to_resource(np_par, 0, &res);
+                if (ret) {
+                        printk(KERN_WARNING "%s couldn;t map par_io registers\n",
+                                __func__);
+                        return;
+                }
+
+                base = ioremap(res.start, res.end - res.start + 1);
+
+                /*
+                 * set output delay adjustments to default values according
+                 * table 5 in Errata Rev. 5, 9/2011:
+                 *
+                 * write 0b01 to UCC1 bits 18:19
+                 * write 0b01 to UCC2 option 1 bits 4:5
+                 * write 0b01 to UCC2 option 2 bits 16:17
+                 */
+                clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
+
+                /*
+                 * set output delay adjustments to default values according
+                 * table 3-13 in Reference Manual Rev.3 05/2010:
+                 *
+                 * write 0b01 to UCC2 option 2 bits 16:17
+                 * write 0b0101 to UCC1 bits 20:23
+                 * write 0b0101 to UCC2 option 1 bits 24:27
+                 */
+                clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
 
-                /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
-                svid = mfspr(SPRN_SVR);
                 if (SVR_REV(svid) == 0x0021) {
-                        struct  device_node *np_par;
-                        struct  resource res;
-                        void    __iomem *base;
-                        int     ret;
-
-                        np_par = of_find_node_by_name(NULL, "par_io");
-                        if (np_par == NULL) {
-                                printk(KERN_WARNING "%s couldn;t find par_io node\n",
-                                        __func__);
-                                return;
-                        }
-                        /* Map Parallel I/O ports registers */
-                        ret = of_address_to_resource(np_par, 0, &res);
-                        if (ret) {
-                                printk(KERN_WARNING "%s couldn;t map par_io registers\n",
-                                        __func__);
-                                return;
-                        }
-                        base = ioremap(res.start, resource_size(&res));
+                        /*
+                         * UCC2 option 1: write 0b1010 to bits 24:27
+                         * at address IMMRBAR+0x14AC
+                         */
+                        clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
+                } else if (SVR_REV(svid) == 0x0020) {
+                        /*
+                         * UCC1: write 0b11 to bits 18:19
+                         * at address IMMRBAR+0x14A8
+                         */
+                        setbits32((base + 0xa8), 0x00003000);
 
                         /*
-                         * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
-                         * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
+                         * UCC2 option 1: write 0b11 to bits 4:5
+                         * at address IMMRBAR+0x14A8
                          */
-                        setbits32((base + 0xa8), 0x0c003000);
+                        setbits32((base + 0xa8), 0x0c000000);
 
                         /*
-                         * IMMR + 0x14AC[20:27] = 10101010
-                         * (data delay for both UCC's)
+                         * UCC2 option 2: write 0b11 to bits 16:17
+                         * at address IMMRBAR+0x14AC
                          */
-                        clrsetbits_be32((base + 0xac), 0xff0, 0xaa0);
-                        iounmap(base);
-                        of_node_put(np_par);
+                        setbits32((base + 0xac), 0x0000c000);
                 }
+                iounmap(base);
+                of_node_put(np_par);
                 of_node_put(np);
         }
-#endif                          /* CONFIG_QUICC_ENGINE */
+#endif  /* CONFIG_QUICC_ENGINE */
 }
 
 machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index f000d81c4e3..159c01e9146 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -23,6 +23,15 @@ config FSL_85XX_CACHE_SRAM
           cache-sram-size and cache-sram-offset kernel boot
           parameters should be passed when this option is enabled.
 
+config BSC9131_RDB
+        bool "Freescale BSC9131RDB"
+        select DEFAULT_UIMAGE
+        help
+          This option enables support for the Freescale BSC9131RDB board.
+          The BSC9131 is a heterogeneous SoC containing an e500v2 powerpc and a
+          StarCore SC3850 DSP
+          Manufacturer : Freescale Semiconductor, Inc
+
 config MPC8540_ADS
         bool "Freescale MPC8540 ADS"
         select DEFAULT_UIMAGE
@@ -175,12 +184,6 @@ config SBC8548
         help
           This option enables support for the Wind River SBC8548 board
 
-config SBC8560
-        bool "Wind River SBC8560"
-        select DEFAULT_UIMAGE
-        help
-          This option enables support for the Wind River SBC8560 board
-
 config GE_IMP3A
         bool "GE Intelligent Platforms IMP3A"
         select DEFAULT_UIMAGE
@@ -222,18 +225,6 @@ config P3041_DS
         help
           This option enables support for the P3041 DS board
 
-config P3060_QDS
-        bool "Freescale P3060 QDS"
-        select DEFAULT_UIMAGE
-        select PPC_E500MC
-        select PHYS_64BIT
-        select SWIOTLB
-        select GPIO_MPC8XXX
-        select HAS_RAPIDIO
-        select PPC_EPAPR_HV_PIC
-        help
-          This option enables support for the P3060 QDS board
-
 config P4080_DS
         bool "Freescale P4080 DS"
         select DEFAULT_UIMAGE
@@ -263,6 +254,22 @@ config P5020_DS
         help
           This option enables support for the P5020 DS board
 
+config PPC_QEMU_E500
+        bool "QEMU generic e500 platform"
+        depends on EXPERIMENTAL
+        select DEFAULT_UIMAGE
+        help
+          This option enables support for running as a QEMU guest using
+          QEMU's generic e500 machine.  This is not required if you're
+          using a QEMU machine that targets a specific board, such as
+          mpc8544ds.
+
+          Unlike most e500 boards that target a specific CPU, this
+          platform works with any e500-family CPU that QEMU supports.
+          Thus, you'll need to make sure CONFIG_PPC_E500MC is set or
+          unset based on the emulated CPU (or actual host CPU in the case
+          of KVM).
+
 endif # FSL_SOC_BOOKE
 
 config TQM85xx
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 2125d4ca068..3dfe8117503 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_SMP) += smp.o
 
 obj-y += common.o
 
+obj-$(CONFIG_BSC9131_RDB) += bsc913x_rdb.o
 obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
 obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
@@ -17,14 +18,13 @@ obj-$(CONFIG_P1022_DS)    += p1022_ds.o
 obj-$(CONFIG_P1023_RDS)   += p1023_rds.o
 obj-$(CONFIG_P2041_RDB)   += p2041_rdb.o corenet_ds.o
 obj-$(CONFIG_P3041_DS)    += p3041_ds.o corenet_ds.o
-obj-$(CONFIG_P3060_QDS)   += p3060_qds.o corenet_ds.o
 obj-$(CONFIG_P4080_DS)    += p4080_ds.o corenet_ds.o
 obj-$(CONFIG_P5020_DS)    += p5020_ds.o corenet_ds.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
-obj-$(CONFIG_SBC8560)     += sbc8560.o
 obj-$(CONFIG_SBC8548)     += sbc8548.o
 obj-$(CONFIG_SOCRATES)    += socrates.o socrates_fpga_pic.o
 obj-$(CONFIG_KSI8560)     += ksi8560.o
 obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
 obj-$(CONFIG_GE_IMP3A)    += ge_imp3a.o
+obj-$(CONFIG_PPC_QEMU_E500) += qemu_e500.o
diff --git a/arch/powerpc/platforms/85xx/bsc913x_rdb.c b/arch/powerpc/platforms/85xx/bsc913x_rdb.c
new file mode 100644
index 00000000000..9d57bedb940
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/bsc913x_rdb.c
@@ -0,0 +1,67 @@
+/*
+ * BSC913xRDB Board Setup
+ *
+ * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
+ *
+ * Copyright 2011-2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <asm/mpic.h>
+#include <sysdev/fsl_soc.h>
+#include <asm/udbg.h>
+
+#include "mpc85xx.h"
+
+void __init bsc913x_rdb_pic_init(void)
+{
+        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
+          MPIC_SINGLE_DEST_CPU,
+          0, 256, " OpenPIC  ");
+
+        if (!mpic)
+                pr_err("bsc913x: Failed to allocate MPIC structure\n");
+        else
+                mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init bsc913x_rdb_setup_arch(void)
+{
+        if (ppc_md.progress)
+                ppc_md.progress("bsc913x_rdb_setup_arch()", 0);
+
+        pr_info("bsc913x board from Freescale Semiconductor\n");
+}
+
+machine_device_initcall(bsc9131_rdb, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+
+static int __init bsc9131_rdb_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,bsc9131rdb");
+}
+
+define_machine(bsc9131_rdb) {
+        .name                   = "BSC9131 RDB",
+        .probe                  = bsc9131_rdb_probe,
+        .setup_arch             = bsc913x_rdb_setup_arch,
+        .init_IRQ               = bsc913x_rdb_pic_init,
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index dd3617c531d..925b0287423 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -77,7 +77,7 @@ void __init corenet_ds_setup_arch(void)
 #endif
 
 #ifdef CONFIG_SWIOTLB
-        if (memblock_end_of_DRAM() > max) {
+        if ((memblock_end_of_DRAM() - 1) > max) {
                 ppc_swiotlb_enable = 1;
                 set_pci_dma_ops(&swiotlb_dma_ops);
                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c b/arch/powerpc/platforms/85xx/ge_imp3a.c
index 18014629416..b6a728b0a8c 100644
--- a/arch/powerpc/platforms/85xx/ge_imp3a.c
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -125,7 +125,7 @@ static void __init ge_imp3a_setup_arch(void)
         mpc85xx_smp_init();
 
 #ifdef CONFIG_SWIOTLB
-        if (memblock_end_of_DRAM() > max) {
+        if ((memblock_end_of_DRAM() - 1) > max) {
                 ppc_swiotlb_enable = 1;
                 set_pci_dma_ops(&swiotlb_dma_ops);
                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
diff --git a/arch/powerpc/platforms/85xx/mpc8536_ds.c b/arch/powerpc/platforms/85xx/mpc8536_ds.c
index 585bd22b140..767c7cf18a9 100644
--- a/arch/powerpc/platforms/85xx/mpc8536_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc8536_ds.c
@@ -75,7 +75,7 @@ static void __init mpc8536_ds_setup_arch(void)
 #endif
 
 #ifdef CONFIG_SWIOTLB
-        if (memblock_end_of_DRAM() > max) {
+        if ((memblock_end_of_DRAM() - 1) > max) {
                 ppc_swiotlb_enable = 1;
                 set_pci_dma_ops(&swiotlb_dma_ops);
                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 1fd91e9e0ff..6d3265fe771 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -114,71 +114,53 @@ void __init mpc85xx_ds_pic_init(void)
 }
 
 #ifdef CONFIG_PCI
-static int primary_phb_addr;
 extern int uli_exclude_device(struct pci_controller *hose,
                                 u_char bus, u_char devfn);
 
+static struct device_node *pci_with_uli;
+
 static int mpc85xx_exclude_device(struct pci_controller *hose,
                                    u_char bus, u_char devfn)
 {
-        struct device_node* node;
-        struct resource rsrc;
-
-        node = hose->dn;
-        of_address_to_resource(node, 0, &rsrc);
-
-        if ((rsrc.start & 0xfffff) == primary_phb_addr) {
+        if (hose->dn == pci_with_uli)
                 return uli_exclude_device(hose, bus, devfn);
-        }
 
         return PCIBIOS_SUCCESSFUL;
 }
 #endif  /* CONFIG_PCI */
 
-/*
- * Setup the architecture
- */
-static void __init mpc85xx_ds_setup_arch(void)
+static void __init mpc85xx_ds_pci_init(void)
 {
 #ifdef CONFIG_PCI
-        struct device_node *np;
-        struct pci_controller *hose;
-#endif
-        dma_addr_t max = 0xffffffff;
+        struct device_node *node;
 
-        if (ppc_md.progress)
-                ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
+        fsl_pci_init();
 
-#ifdef CONFIG_PCI
-        for_each_node_by_type(np, "pci") {
-                if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
-                    of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
-                    of_device_is_compatible(np, "fsl,p2020-pcie")) {
-                        struct resource rsrc;
-                        of_address_to_resource(np, 0, &rsrc);
-                        if ((rsrc.start & 0xfffff) == primary_phb_addr)
-                                fsl_add_bridge(np, 1);
-                        else
-                                fsl_add_bridge(np, 0);
-
-                        hose = pci_find_hose_for_OF_device(np);
-                        max = min(max, hose->dma_window_base_cur +
-                                        hose->dma_window_size);
+        /* See if we have a ULI under the primary */
+
+        node = of_find_node_by_name(NULL, "uli1575");
+        while ((pci_with_uli = of_get_parent(node))) {
+                of_node_put(node);
+                node = pci_with_uli;
+
+                if (pci_with_uli == fsl_pci_primary) {
+                        ppc_md.pci_exclude_device = mpc85xx_exclude_device;
+                        break;
                 }
         }
-
-        ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 #endif
+}
 
-        mpc85xx_smp_init();
+/*
+ * Setup the architecture
+ */
+static void __init mpc85xx_ds_setup_arch(void)
+{
+        if (ppc_md.progress)
+                ppc_md.progress("mpc85xx_ds_setup_arch()", 0);
 
-#ifdef CONFIG_SWIOTLB
-        if (memblock_end_of_DRAM() > max) {
-                ppc_swiotlb_enable = 1;
-                set_pci_dma_ops(&swiotlb_dma_ops);
-                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
-        }
-#endif
+        mpc85xx_ds_pci_init();
+        mpc85xx_smp_init();
 
         printk("MPC85xx DS board from Freescale Semiconductor\n");
 }
@@ -190,14 +172,7 @@ static int __init mpc8544_ds_probe(void)
 {
         unsigned long root = of_get_flat_dt_root();
 
-        if (of_flat_dt_is_compatible(root, "MPC8544DS")) {
-#ifdef CONFIG_PCI
-                primary_phb_addr = 0xb000;
-#endif
-                return 1;
-        }
-
-        return 0;
+        return !!of_flat_dt_is_compatible(root, "MPC8544DS");
 }
 
 machine_device_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
@@ -215,14 +190,7 @@ static int __init mpc8572_ds_probe(void)
 {
         unsigned long root = of_get_flat_dt_root();
 
-        if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS")) {
-#ifdef CONFIG_PCI
-                primary_phb_addr = 0x8000;
-#endif
-                return 1;
-        }
-
-        return 0;
+        return !!of_flat_dt_is_compatible(root, "fsl,MPC8572DS");
 }
 
 /*
@@ -232,14 +200,7 @@ static int __init p2020_ds_probe(void)
 {
         unsigned long root = of_get_flat_dt_root();
 
-        if (of_flat_dt_is_compatible(root, "fsl,P2020DS")) {
-#ifdef CONFIG_PCI
-                primary_phb_addr = 0x9000;
-#endif
-                return 1;
-        }
-
-        return 0;
+        return !!of_flat_dt_is_compatible(root, "fsl,P2020DS");
 }
 
 define_machine(mpc8544_ds) {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index d208ebccb91..8e4b094c553 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -359,7 +359,7 @@ static void __init mpc85xx_mds_setup_arch(void)
         mpc85xx_mds_qe_init();
 
 #ifdef CONFIG_SWIOTLB
-        if (memblock_end_of_DRAM() > max) {
+        if ((memblock_end_of_DRAM() - 1) > max) {
                 ppc_swiotlb_enable = 1;
                 set_pci_dma_ops(&swiotlb_dma_ops);
                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 313fce4f557..1910fdcb75b 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -169,6 +169,7 @@ machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
 machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
 machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
 machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
+machine_device_initcall(p1024_rdb, mpc85xx_common_publish_devices);
 
 /*
  * Called very early, device-tree isn't unflattened
@@ -237,6 +238,13 @@ static int __init p1020_utm_pc_probe(void)
         return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC");
 }
 
+static int __init p1024_rdb_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return of_flat_dt_is_compatible(root, "fsl,P1024RDB");
+}
+
 define_machine(p2020_rdb) {
         .name                   = "P2020 RDB",
         .probe                  = p2020_rdb_probe,
@@ -348,3 +356,17 @@ define_machine(p1020_rdb_pc) {
         .calibrate_decr         = generic_calibrate_decr,
         .progress               = udbg_progress,
 };
+
+define_machine(p1024_rdb) {
+        .name                   = "P1024 RDB",
+        .probe                  = p1024_rdb_probe,
+        .setup_arch             = mpc85xx_rdb_setup_arch,
+        .init_IRQ               = mpc85xx_rdb_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index f700c81a132..3c732acf331 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -27,6 +27,7 @@
 #include <sysdev/fsl_pci.h>
 #include <asm/udbg.h>
 #include <asm/fsl_guts.h>
+#include <asm/fsl_lbc.h>
 #include "smp.h"
 
 #include "mpc85xx.h"
@@ -142,17 +143,74 @@ static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
 {
 }
 
+struct fsl_law {
+        u32     lawbar;
+        u32     reserved1;
+        u32     lawar;
+        u32     reserved[5];
+};
+
+#define LAWBAR_MASK     0x00F00000
+#define LAWBAR_SHIFT    12
+
+#define LAWAR_EN        0x80000000
+#define LAWAR_TGT_MASK  0x01F00000
+#define LAW_TRGT_IF_LBC (0x04 << 20)
+
+#define LAWAR_MASK      (LAWAR_EN | LAWAR_TGT_MASK)
+#define LAWAR_MATCH     (LAWAR_EN | LAW_TRGT_IF_LBC)
+
+#define BR_BA           0xFFFF8000
+
+/*
+ * Map a BRx value to a physical address
+ *
+ * The localbus BRx registers only store the lower 32 bits of the address.  To
+ * obtain the upper four bits, we need to scan the LAW table.  The entry which
+ * maps to the localbus will contain the upper four bits.
+ */
+static phys_addr_t lbc_br_to_phys(const void *ecm, unsigned int count, u32 br)
+{
+#ifndef CONFIG_PHYS_64BIT
+        /*
+         * If we only have 32-bit addressing, then the BRx address *is* the
+         * physical address.
+         */
+        return br & BR_BA;
+#else
+        const struct fsl_law *law = ecm + 0xc08;
+        unsigned int i;
+
+        for (i = 0; i < count; i++) {
+                u64 lawbar = in_be32(&law[i].lawbar);
+                u32 lawar = in_be32(&law[i].lawar);
+
+                if ((lawar & LAWAR_MASK) == LAWAR_MATCH)
+                        /* Extract the upper four bits */
+                        return (br & BR_BA) | ((lawbar & LAWBAR_MASK) << 12);
+        }
+
+        return 0;
+#endif
+}
+
 /**
  * p1022ds_set_monitor_port: switch the output to a different monitor port
- *
  */
 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
 {
         struct device_node *guts_node;
-        struct device_node *indirect_node = NULL;
+        struct device_node *lbc_node = NULL;
+        struct device_node *law_node = NULL;
         struct ccsr_guts __iomem *guts;
+        struct fsl_lbc_regs *lbc = NULL;
+        void *ecm = NULL;
         u8 __iomem *lbc_lcs0_ba = NULL;
         u8 __iomem *lbc_lcs1_ba = NULL;
+        phys_addr_t cs0_addr, cs1_addr;
+        u32 br0, or0, br1, or1;
+        const __be32 *iprop;
+        unsigned int num_laws;
         u8 b;
 
         /* Map the global utilities registers. */
@@ -168,22 +226,99 @@ static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
                 goto exit;
         }
 
-        indirect_node = of_find_compatible_node(NULL, NULL,
-                                             "fsl,p1022ds-indirect-pixis");
-        if (!indirect_node) {
-                pr_err("p1022ds: missing pixis indirect mode node\n");
+        lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
+        if (!lbc_node) {
+                pr_err("p1022ds: missing localbus node\n");
                 goto exit;
         }
 
-        lbc_lcs0_ba = of_iomap(indirect_node, 0);
-        if (!lbc_lcs0_ba) {
-                pr_err("p1022ds: could not map localbus chip select 0\n");
+        lbc = of_iomap(lbc_node, 0);
+        if (!lbc) {
+                pr_err("p1022ds: could not map localbus node\n");
+                goto exit;
+        }
+
+        law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law");
+        if (!law_node) {
+                pr_err("p1022ds: missing local access window node\n");
+                goto exit;
+        }
+
+        ecm = of_iomap(law_node, 0);
+        if (!ecm) {
+                pr_err("p1022ds: could not map local access window node\n");
+                goto exit;
+        }
+
+        iprop = of_get_property(law_node, "fsl,num-laws", 0);
+        if (!iprop) {
+                pr_err("p1022ds: LAW node is missing fsl,num-laws property\n");
+                goto exit;
+        }
+        num_laws = be32_to_cpup(iprop);
+
+        /*
+         * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
+         * otherwise writes to these addresses won't actually appear on the
+         * local bus, and so the PIXIS won't see them.
+         *
+         * In FCM mode, writes go to the NAND controller, which does not pass
+         * them to the localbus directly.  So we force BR0 and BR1 into GPCM
+         * mode, since we don't care about what's behind the localbus any
+         * more.
+         */
+        br0 = in_be32(&lbc->bank[0].br);
+        br1 = in_be32(&lbc->bank[1].br);
+        or0 = in_be32(&lbc->bank[0].or);
+        or1 = in_be32(&lbc->bank[1].or);
+
+        /* Make sure CS0 and CS1 are programmed */
+        if (!(br0 & BR_V) || !(br1 & BR_V)) {
+                pr_err("p1022ds: CS0 and/or CS1 is not programmed\n");
+                goto exit;
+        }
+
+        /*
+         * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
+         * force the values to simple 32KB GPCM windows with the most
+         * conservative timing.
+         */
+        if ((br0 & BR_MSEL) != BR_MS_GPCM) {
+                br0 = (br0 & BR_BA) | BR_V;
+                or0 = 0xFFFF8000 | 0xFF7;
+                out_be32(&lbc->bank[0].br, br0);
+                out_be32(&lbc->bank[0].or, or0);
+        }
+        if ((br1 & BR_MSEL) != BR_MS_GPCM) {
+                br1 = (br1 & BR_BA) | BR_V;
+                or1 = 0xFFFF8000 | 0xFF7;
+                out_be32(&lbc->bank[1].br, br1);
+                out_be32(&lbc->bank[1].or, or1);
+        }
+
+        cs0_addr = lbc_br_to_phys(ecm, num_laws, br0);
+        if (!cs0_addr) {
+                pr_err("p1022ds: could not determine physical address for CS0"
+                       " (BR0=%08x)\n", br0);
+                goto exit;
+        }
+        cs1_addr = lbc_br_to_phys(ecm, num_laws, br1);
+        if (!cs0_addr) {
+                pr_err("p1022ds: could not determine physical address for CS1"
+                       " (BR1=%08x)\n", br1);
                 goto exit;
         }
 
-        lbc_lcs1_ba = of_iomap(indirect_node, 1);
+        lbc_lcs0_ba = ioremap(cs0_addr, 1);
+        if (!lbc_lcs0_ba) {
+                pr_err("p1022ds: could not ioremap CS0 address %llx\n",
+                       (unsigned long long)cs0_addr);
+                goto exit;
+        }
+        lbc_lcs1_ba = ioremap(cs1_addr, 1);
         if (!lbc_lcs1_ba) {
-                pr_err("p1022ds: could not map localbus chip select 1\n");
+                pr_err("p1022ds: could not ioremap CS1 address %llx\n",
+                       (unsigned long long)cs1_addr);
                 goto exit;
         }
 
@@ -254,10 +389,15 @@ exit:
                 iounmap(lbc_lcs1_ba);
         if (lbc_lcs0_ba)
                 iounmap(lbc_lcs0_ba);
+        if (lbc)
+                iounmap(lbc);
+        if (ecm)
+                iounmap(ecm);
         if (guts)
                 iounmap(guts);
 
-        of_node_put(indirect_node);
+        of_node_put(law_node);
+        of_node_put(lbc_node);
         of_node_put(guts_node);
 }
 
@@ -339,24 +479,6 @@ void __init p1022_ds_pic_init(void)
 
 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 
-/*
- * Disables a node in the device tree.
- *
- * This function is called before kmalloc() is available, so the 'new' object
- * should be allocated in the global area.  The easiest way is to do that is
- * to allocate one static local variable for each call to this function.
- */
-static void __init disable_one_node(struct device_node *np, struct property *new)
-{
-        struct property *old;
-
-        old = of_find_property(np, new->name, NULL);
-        if (old)
-                prom_update_property(np, new, old);
-        else
-                prom_add_property(np, new);
-}
-
 /* TRUE if there is a "video=fslfb" command-line parameter. */
 static bool fslfb;
 
@@ -419,28 +541,58 @@ static void __init p1022_ds_setup_arch(void)
         diu_ops.valid_monitor_port      = p1022ds_valid_monitor_port;
 
         /*
-         * Disable the NOR flash node if there is video=fslfb... command-line
-         * parameter.  When the DIU is active, NOR flash is unavailable, so we
-         * have to disable the node before the MTD driver loads.
+         * Disable the NOR and NAND flash nodes if there is video=fslfb...
+         * command-line parameter.  When the DIU is active, the localbus is
+         * unavailable, so we have to disable these nodes before the MTD
+         * driver loads.
          */
         if (fslfb) {
                 struct device_node *np =
                         of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
 
                 if (np) {
-                        np = of_find_compatible_node(np, NULL, "cfi-flash");
-                        if (np) {
+                        struct device_node *np2;
+
+                        of_node_get(np);
+                        np2 = of_find_compatible_node(np, NULL, "cfi-flash");
+                        if (np2) {
                                 static struct property nor_status = {
                                         .name = "status",
                                         .value = "disabled",
                                         .length = sizeof("disabled"),
                                 };
 
+                                /*
+                                 * prom_update_property() is called before
+                                 * kmalloc() is available, so the 'new' object
+                                 * should be allocated in the global area.
+                                 * The easiest way is to do that is to
+                                 * allocate one static local variable for each
+                                 * call to this function.
+                                 */
+                                pr_info("p1022ds: disabling %s node",
+                                        np2->full_name);
+                                prom_update_property(np2, &nor_status);
+                                of_node_put(np2);
+                        }
+
+                        of_node_get(np);
+                        np2 = of_find_compatible_node(np, NULL,
+                                                      "fsl,elbc-fcm-nand");
+                        if (np2) {
+                                static struct property nand_status = {
+                                        .name = "status",
+                                        .value = "disabled",
+                                        .length = sizeof("disabled"),
+                                };
+
                                 pr_info("p1022ds: disabling %s node",
-                                        np->full_name);
-                                disable_one_node(np, &nor_status);
-                                of_node_put(np);
+                                        np2->full_name);
+                                prom_update_property(np2, &nand_status);
+                                of_node_put(np2);
                         }
+
+                        of_node_put(np);
                 }
 
         }
@@ -450,7 +602,7 @@ static void __init p1022_ds_setup_arch(void)
         mpc85xx_smp_init();
 
 #ifdef CONFIG_SWIOTLB
-        if (memblock_end_of_DRAM() > max) {
+        if ((memblock_end_of_DRAM() - 1) > max) {
                 ppc_swiotlb_enable = 1;
                 set_pci_dma_ops(&swiotlb_dma_ops);
                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
diff --git a/arch/powerpc/platforms/85xx/p3060_qds.c b/arch/powerpc/platforms/85xx/p3060_qds.c
deleted file mode 100644
index 081cf4ac188..00000000000
--- a/arch/powerpc/platforms/85xx/p3060_qds.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * P3060 QDS Setup
- *
- * Copyright 2011 Freescale Semiconductor Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/phy.h>
-#include <asm/machdep.h>
-#include <asm/udbg.h>
-#include <asm/mpic.h>
-#include <linux/of_platform.h>
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-#include <asm/ehv_pic.h>
-#include "corenet_ds.h"
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init p3060_qds_probe(void)
-{
-        unsigned long root = of_get_flat_dt_root();
-#ifdef CONFIG_SMP
-        extern struct smp_ops_t smp_85xx_ops;
-#endif
-
-        if (of_flat_dt_is_compatible(root, "fsl,P3060QDS"))
-                return 1;
-
-        /* Check if we're running under the Freescale hypervisor */
-        if (of_flat_dt_is_compatible(root, "fsl,P3060QDS-hv")) {
-                ppc_md.init_IRQ = ehv_pic_init;
-                ppc_md.get_irq = ehv_pic_get_irq;
-                ppc_md.restart = fsl_hv_restart;
-                ppc_md.power_off = fsl_hv_halt;
-                ppc_md.halt = fsl_hv_halt;
-#ifdef CONFIG_SMP
-                /*
-                 * Disable the timebase sync operations because we can't write
-                 * to the timebase registers under the hypervisor.
-                 */
-                smp_85xx_ops.give_timebase = NULL;
-                smp_85xx_ops.take_timebase = NULL;
-#endif
-                return 1;
-        }
-
-        return 0;
-}
-
-define_machine(p3060_qds) {
-        .name                   = "P3060 QDS",
-        .probe                  = p3060_qds_probe,
-        .setup_arch             = corenet_ds_setup_arch,
-        .init_IRQ               = corenet_ds_pic_init,
-#ifdef CONFIG_PCI
-        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
-#endif
-        .get_irq                = mpic_get_coreint_irq,
-        .restart                = fsl_rstcr_restart,
-        .calibrate_decr         = generic_calibrate_decr,
-        .progress               = udbg_progress,
-        .power_save             = e500_idle,
-};
-
-machine_device_initcall(p3060_qds, corenet_ds_publish_devices);
-
-#ifdef CONFIG_SWIOTLB
-machine_arch_initcall(p3060_qds, swiotlb_setup_bus_notifier);
-#endif
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c
new file mode 100644
index 00000000000..95a2e53af71
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/qemu_e500.c
@@ -0,0 +1,72 @@
+/*
+ * Paravirt target for a generic QEMU e500 machine
+ *
+ * This is intended to be a flexible device-tree-driven platform, not fixed
+ * to a particular piece of hardware or a particular spec of virtual hardware,
+ * beyond the assumption of an e500-family CPU.  Some things are still hardcoded
+ * here, such as MPIC, but this is a limitation of the current code rather than
+ * an interface contract with QEMU.
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of_fdt.h>
+#include <asm/machdep.h>
+#include <asm/time.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+#include "mpc85xx.h"
+
+void __init qemu_e500_pic_init(void)
+{
+        struct mpic *mpic;
+
+        mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU,
+                        0, 256, " OpenPIC  ");
+
+        BUG_ON(mpic == NULL);
+        mpic_init(mpic);
+}
+
+static void __init qemu_e500_setup_arch(void)
+{
+        ppc_md.progress("qemu_e500_setup_arch()", 0);
+
+        fsl_pci_init();
+        mpc85xx_smp_init();
+}
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init qemu_e500_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+
+        return !!of_flat_dt_is_compatible(root, "fsl,qemu-e500");
+}
+
+machine_device_initcall(qemu_e500, mpc85xx_common_publish_devices);
+
+define_machine(qemu_e500) {
+        .name                   = "QEMU e500",
+        .probe                  = qemu_e500_probe,
+        .setup_arch             = qemu_e500_setup_arch,
+        .init_IRQ               = qemu_e500_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+        .get_irq                = mpic_get_irq,
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+};
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
deleted file mode 100644
index b1be632ede4..00000000000
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ /dev/null
@@ -1,254 +0,0 @@
-/*
- * Wind River SBC8560 setup and early boot code.
- *
- * Copyright 2007 Wind River Systems Inc.
- *
- * By Paul Gortmaker (see MAINTAINERS for contact information)
- *
- * Based largely on the MPC8560ADS support - Copyright 2005 Freescale Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/of_platform.h>
-
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/mpic.h>
-#include <mm/mmu_decl.h>
-#include <asm/udbg.h>
-
-#include <sysdev/fsl_soc.h>
-#include <sysdev/fsl_pci.h>
-
-#include "mpc85xx.h"
-
-#ifdef CONFIG_CPM2
-#include <asm/cpm2.h>
-#include <sysdev/cpm2_pic.h>
-#endif
-
-static void __init sbc8560_pic_init(void)
-{
-        struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
-                        0, 256, " OpenPIC  ");
-        BUG_ON(mpic == NULL);
-        mpic_init(mpic);
-
-        mpc85xx_cpm2_pic_init();
-}
-
-/*
- * Setup the architecture
- */
-#ifdef CONFIG_CPM2
-struct cpm_pin {
-        int port, pin, flags;
-};
-
-static const struct cpm_pin sbc8560_pins[] = {
-        /* SCC1 */
-        {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
-        {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-
-        /* SCC2 */
-        {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-
-        /* FCC2 */
-        {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
-        {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
-        {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
-
-        /* FCC3 */
-        {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
-        {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
-        {2, 16, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK16 */
-        {2, 17, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* CLK15 */
-};
-
-static void __init init_ioports(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(sbc8560_pins); i++) {
-                const struct cpm_pin *pin = &sbc8560_pins[i];
-                cpm2_set_pin(pin->port, pin->pin, pin->flags);
-        }
-
-        cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
-        cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
-        cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
-        cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
-        cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
-        cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
-        cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
-        cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
-}
-#endif
-
-static void __init sbc8560_setup_arch(void)
-{
-#ifdef CONFIG_PCI
-        struct device_node *np;
-#endif
-
-        if (ppc_md.progress)
-                ppc_md.progress("sbc8560_setup_arch()", 0);
-
-#ifdef CONFIG_CPM2
-        cpm2_reset();
-        init_ioports();
-#endif
-
-#ifdef CONFIG_PCI
-        for_each_compatible_node(np, "pci", "fsl,mpc8540-pci")
-                fsl_add_bridge(np, 1);
-#endif
-}
-
-static void sbc8560_show_cpuinfo(struct seq_file *m)
-{
-        uint pvid, svid, phid1;
-
-        pvid = mfspr(SPRN_PVR);
-        svid = mfspr(SPRN_SVR);
-
-        seq_printf(m, "Vendor\t\t: Wind River\n");
-        seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
-        seq_printf(m, "SVR\t\t: 0x%x\n", svid);
-
-        /* Display cpu Pll setting */
-        phid1 = mfspr(SPRN_HID1);
-        seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
-}
-
-machine_device_initcall(sbc8560, mpc85xx_common_publish_devices);
-
-/*
- * Called very early, device-tree isn't unflattened
- */
-static int __init sbc8560_probe(void)
-{
-        unsigned long root = of_get_flat_dt_root();
-
-        return of_flat_dt_is_compatible(root, "SBC8560");
-}
-
-#ifdef CONFIG_RTC_DRV_M48T59
-static int __init sbc8560_rtc_init(void)
-{
-        struct device_node *np;
-        struct resource res;
-        struct platform_device *rtc_dev;
-
-        np = of_find_compatible_node(NULL, NULL, "m48t59");
-        if (np == NULL) {
-                printk("No RTC in DTB. Has it been eaten by wild dogs?\n");
-                return -ENODEV;
-        }
-
-        of_address_to_resource(np, 0, &res);
-        of_node_put(np);
-
-        printk("Found RTC (m48t59) at i/o 0x%x\n", res.start);
-
-        rtc_dev = platform_device_register_simple("rtc-m48t59", 0, &res, 1);
-
-        if (IS_ERR(rtc_dev)) {
-                printk("Registering sbc8560 RTC device failed\n");
-                return PTR_ERR(rtc_dev);
-        }
-
-        return 0;
-}
-
-arch_initcall(sbc8560_rtc_init);
-
-#endif  /* M48T59 */
-
-static __u8 __iomem *brstcr;
-
-static int __init sbc8560_bdrstcr_init(void)
-{
-        struct device_node *np;
-        struct resource res;
-
-        np = of_find_compatible_node(NULL, NULL, "wrs,sbc8560-brstcr");
-        if (np == NULL) {
-                printk(KERN_WARNING "sbc8560: No board specific RSTCR in DTB.\n");
-                return -ENODEV;
-        }
-
-        of_address_to_resource(np, 0, &res);
-
-        printk(KERN_INFO "sbc8560: Found BRSTCR at %pR\n", &res);
-
-        brstcr = ioremap(res.start, resource_size(&res));
-        if(!brstcr)
-                printk(KERN_WARNING "sbc8560: ioremap of brstcr failed.\n");
-
-        of_node_put(np);
-
-        return 0;
-}
-
-arch_initcall(sbc8560_bdrstcr_init);
-
-void sbc8560_rstcr_restart(char * cmd)
-{
-        local_irq_disable();
-        if(brstcr)
-                clrbits8(brstcr, 0x80);
-
-        while(1);
-}
-
-define_machine(sbc8560) {
-        .name                   = "SBC8560",
-        .probe                  = sbc8560_probe,
-        .setup_arch             = sbc8560_setup_arch,
-        .init_IRQ               = sbc8560_pic_init,
-        .show_cpuinfo           = sbc8560_show_cpuinfo,
-        .get_irq                = mpic_get_irq,
-        .restart                = sbc8560_rstcr_restart,
-        .calibrate_decr         = generic_calibrate_decr,
-        .progress               = udbg_progress,
-};
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 4d786c25d3e..3e70a2035e5 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -102,7 +102,7 @@ static void tqm85xx_show_cpuinfo(struct seq_file *m)
         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 }
 
-static void __init tqm85xx_ti1520_fixup(struct pci_dev *pdev)
+static void __devinit tqm85xx_ti1520_fixup(struct pci_dev *pdev)
 {
         unsigned int val;
 
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 1fca663f1b2..563aafa8629 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -164,7 +164,7 @@ static void gef_ppc9a_show_cpuinfo(struct seq_file *m)
                 gef_ppc9a_get_vme_is_syscon() ? "yes" : "no");
 }
 
-static void __init gef_ppc9a_nec_fixup(struct pci_dev *pdev)
+static void __devinit gef_ppc9a_nec_fixup(struct pci_dev *pdev)
 {
         unsigned int val;
 
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
index 14e0e576bcb..cc6a91ae088 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -152,7 +152,7 @@ static void gef_sbc310_show_cpuinfo(struct seq_file *m)
 
 }
 
-static void __init gef_sbc310_nec_fixup(struct pci_dev *pdev)
+static void __devinit gef_sbc310_nec_fixup(struct pci_dev *pdev)
 {
         unsigned int val;
 
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 1638f43599f..aead6b337f4 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -141,7 +141,7 @@ static void gef_sbc610_show_cpuinfo(struct seq_file *m)
         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 }
 
-static void __init gef_sbc610_nec_fixup(struct pci_dev *pdev)
+static void __devinit gef_sbc610_nec_fixup(struct pci_dev *pdev)
 {
         unsigned int val;
 
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 3755e61d7ec..817245bc021 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -102,7 +102,7 @@ mpc86xx_hpcn_setup_arch(void)
 #endif
 
 #ifdef CONFIG_SWIOTLB
-        if (memblock_end_of_DRAM() > max) {
+        if ((memblock_end_of_DRAM() - 1) > max) {
                 ppc_swiotlb_enable = 1;
                 set_pci_dma_ops(&swiotlb_dma_ops);
                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index a35ca44ade6..e7a896acd98 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -25,6 +25,7 @@ source "arch/powerpc/platforms/wsp/Kconfig"
 config KVM_GUEST
         bool "KVM Guest support"
         default n
+        select EPAPR_PARAVIRT
         ---help---
           This option enables various optimizations for running under the KVM
           hypervisor. Overhead for the kernel when not running inside KVM should
@@ -32,6 +33,14 @@ config KVM_GUEST
 
           In case of doubt, say Y
 
+config EPAPR_PARAVIRT
+        bool "ePAPR para-virtualization support"
+        default n
+        help
+          Enables ePAPR para-virtualization support for guests.
+
+          In case of doubt, say Y
+
 config PPC_NATIVE
         bool
         depends on 6xx || PPC64
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 61c9550819a..30fd01de6be 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -159,6 +159,10 @@ config PPC_E500MC
         bool "e500mc Support"
         select PPC_FPU
         depends on E500
+        help
+          This must be enabled for running on e500mc (and derivatives
+          such as e5500/e6500), and must be disabled for running on
+          e500v1 or e500v2.
 
 config PPC_FPU
         bool
diff --git a/arch/powerpc/platforms/cell/beat_hvCall.S b/arch/powerpc/platforms/cell/beat_hvCall.S
index 74c81744894..96c80190712 100644
--- a/arch/powerpc/platforms/cell/beat_hvCall.S
+++ b/arch/powerpc/platforms/cell/beat_hvCall.S
@@ -22,8 +22,6 @@
 
 #include <asm/ppc_asm.h>
 
-#define STK_PARM(i)     (48 + ((i)-3)*8)
-
 /* Not implemented on Beat, now */
 #define HCALL_INST_PRECALL
 #define HCALL_INST_POSTCALL
@@ -74,7 +72,7 @@ _GLOBAL(beat_hcall_norets8)
         mr      r6,r7
         mr      r7,r8
         mr      r8,r9
-        ld      r10,STK_PARM(r10)(r1)
+        ld      r10,STK_PARAM(R10)(r1)
 
         HVSC                            /* invoke the hypervisor */
 
@@ -94,7 +92,7 @@ _GLOBAL(beat_hcall1)
 
         HCALL_INST_PRECALL
 
-        std     r4,STK_PARM(r4)(r1)     /* save ret buffer */
+        std     r4,STK_PARAM(R4)(r1)    /* save ret buffer */
 
         mr      r11,r3
         mr      r3,r5
@@ -108,7 +106,7 @@ _GLOBAL(beat_hcall1)
 
         HCALL_INST_POSTCALL
 
-        ld      r12,STK_PARM(r4)(r1)
+        ld      r12,STK_PARAM(R4)(r1)
         std     r4,  0(r12)
 
         lwz     r0,8(r1)
@@ -125,7 +123,7 @@ _GLOBAL(beat_hcall2)
 
         HCALL_INST_PRECALL
 
-        std     r4,STK_PARM(r4)(r1)     /* save ret buffer */
+        std     r4,STK_PARAM(R4)(r1)    /* save ret buffer */
 
         mr      r11,r3
         mr      r3,r5
@@ -139,7 +137,7 @@ _GLOBAL(beat_hcall2)
 
         HCALL_INST_POSTCALL
 
-        ld      r12,STK_PARM(r4)(r1)
+        ld      r12,STK_PARAM(R4)(r1)
         std     r4,  0(r12)
         std     r5,  8(r12)
 
@@ -157,7 +155,7 @@ _GLOBAL(beat_hcall3)
 
         HCALL_INST_PRECALL
 
-        std     r4,STK_PARM(r4)(r1)     /* save ret buffer */
+        std     r4,STK_PARAM(R4)(r1)    /* save ret buffer */
 
         mr      r11,r3
         mr      r3,r5
@@ -171,7 +169,7 @@ _GLOBAL(beat_hcall3)
 
         HCALL_INST_POSTCALL
 
-        ld      r12,STK_PARM(r4)(r1)
+        ld      r12,STK_PARAM(R4)(r1)
         std     r4,  0(r12)
         std     r5,  8(r12)
         std     r6, 16(r12)
@@ -190,7 +188,7 @@ _GLOBAL(beat_hcall4)
 
         HCALL_INST_PRECALL
 
-        std     r4,STK_PARM(r4)(r1)     /* save ret buffer */
+        std     r4,STK_PARAM(R4)(r1)    /* save ret buffer */
 
         mr      r11,r3
         mr      r3,r5
@@ -204,7 +202,7 @@ _GLOBAL(beat_hcall4)
 
         HCALL_INST_POSTCALL
 
-        ld      r12,STK_PARM(r4)(r1)
+        ld      r12,STK_PARAM(R4)(r1)
         std     r4,  0(r12)
         std     r5,  8(r12)
         std     r6, 16(r12)
@@ -224,7 +222,7 @@ _GLOBAL(beat_hcall5)
 
         HCALL_INST_PRECALL
 
-        std     r4,STK_PARM(r4)(r1)     /* save ret buffer */
+        std     r4,STK_PARAM(R4)(r1)    /* save ret buffer */
 
         mr      r11,r3
         mr      r3,r5
@@ -238,7 +236,7 @@ _GLOBAL(beat_hcall5)
 
         HCALL_INST_POSTCALL
 
-        ld      r12,STK_PARM(r4)(r1)
+        ld      r12,STK_PARAM(R4)(r1)
         std     r4,  0(r12)
         std     r5,  8(r12)
         std     r6, 16(r12)
@@ -259,7 +257,7 @@ _GLOBAL(beat_hcall6)
 
         HCALL_INST_PRECALL
 
-        std     r4,STK_PARM(r4)(r1)     /* save ret buffer */
+        std     r4,STK_PARAM(R4)(r1)    /* save ret buffer */
 
         mr      r11,r3
         mr      r3,r5
@@ -273,7 +271,7 @@ _GLOBAL(beat_hcall6)
 
         HCALL_INST_POSTCALL
 
-        ld      r12,STK_PARM(r4)(r1)
+        ld      r12,STK_PARAM(R4)(r1)
         std     r4,  0(r12)
         std     r5,  8(r12)
         std     r6, 16(r12)
diff --git a/arch/powerpc/platforms/cell/iommu.c b/arch/powerpc/platforms/cell/iommu.c
index b9f509a34c0..dca21366674 100644
--- a/arch/powerpc/platforms/cell/iommu.c
+++ b/arch/powerpc/platforms/cell/iommu.c
@@ -518,7 +518,6 @@ cell_iommu_setup_window(struct cbe_iommu *iommu, struct device_node *np,
         __set_bit(0, window->table.it_map);
         tce_build_cell(&window->table, window->table.it_offset, 1,
                        (unsigned long)iommu->pad_page, DMA_TO_DEVICE, NULL);
-        window->table.it_hint = window->table.it_blocksize;
 
         return window;
 }
@@ -552,8 +551,7 @@ static struct iommu_table *cell_get_iommu_table(struct device *dev)
         iommu = cell_iommu_for_node(dev_to_node(dev));
         if (iommu == NULL || list_empty(&iommu->windows)) {
                 printk(KERN_ERR "iommu: missing iommu for %s (node %d)\n",
-                       dev->of_node ? dev->of_node->full_name : "?",
-                       dev_to_node(dev));
+                       of_node_full_name(dev->of_node), dev_to_node(dev));
                 return NULL;
         }
         window = list_entry(iommu->windows.next, struct iommu_window, list);
diff --git a/arch/powerpc/platforms/cell/spufs/inode.c b/arch/powerpc/platforms/cell/spufs/inode.c
index 66519d263da..dba1ce235da 100644
--- a/arch/powerpc/platforms/cell/spufs/inode.c
+++ b/arch/powerpc/platforms/cell/spufs/inode.c
@@ -186,10 +186,13 @@ static void spufs_prune_dir(struct dentry *dir)
 static int spufs_rmdir(struct inode *parent, struct dentry *dir)
 {
         /* remove all entries */
+        int res;
         spufs_prune_dir(dir);
         d_drop(dir);
-
-        return simple_rmdir(parent, dir);
+        res = simple_rmdir(parent, dir);
+        /* We have to give up the mm_struct */
+        spu_forget(SPUFS_I(dir->d_inode)->i_ctx);
+        return res;
 }
 
 static int spufs_fill_dir(struct dentry *dir,
@@ -245,9 +248,6 @@ static int spufs_dir_close(struct inode *inode, struct file *file)
         mutex_unlock(&parent->i_mutex);
         WARN_ON(ret);
 
-        /* We have to give up the mm_struct */
-        spu_forget(ctx);
-
         return dcache_dir_close(inode, file);
 }
 
@@ -317,28 +317,23 @@ out:
         return ret;
 }
 
-static int spufs_context_open(struct dentry *dentry, struct vfsmount *mnt)
+static int spufs_context_open(struct path *path)
 {
         int ret;
         struct file *filp;
 
         ret = get_unused_fd();
-        if (ret < 0) {
-                dput(dentry);
-                mntput(mnt);
-                goto out;
-        }
+        if (ret < 0)
+                return ret;
 
-        filp = dentry_open(dentry, mnt, O_RDONLY, current_cred());
+        filp = dentry_open(path, O_RDONLY, current_cred());
         if (IS_ERR(filp)) {
                 put_unused_fd(ret);
-                ret = PTR_ERR(filp);
-                goto out;
+                return PTR_ERR(filp);
         }
 
         filp->f_op = &spufs_context_fops;
         fd_install(ret, filp);
-out:
         return ret;
 }
 
@@ -453,29 +448,26 @@ spufs_create_context(struct inode *inode, struct dentry *dentry,
         int affinity;
         struct spu_gang *gang;
         struct spu_context *neighbor;
+        struct path path = {.mnt = mnt, .dentry = dentry};
 
-        ret = -EPERM;
         if ((flags & SPU_CREATE_NOSCHED) &&
             !capable(CAP_SYS_NICE))
-                goto out_unlock;
+                return -EPERM;
 
-        ret = -EINVAL;
         if ((flags & (SPU_CREATE_NOSCHED | SPU_CREATE_ISOLATE))
             == SPU_CREATE_ISOLATE)
-                goto out_unlock;
+                return -EINVAL;
 
-        ret = -ENODEV;
         if ((flags & SPU_CREATE_ISOLATE) && !isolated_loader)
-                goto out_unlock;
+                return -ENODEV;
 
         gang = NULL;
         neighbor = NULL;
         affinity = flags & (SPU_CREATE_AFFINITY_MEM | SPU_CREATE_AFFINITY_SPU);
         if (affinity) {
                 gang = SPUFS_I(inode)->i_gang;
-                ret = -EINVAL;
                 if (!gang)
-                        goto out_unlock;
+                        return -EINVAL;
                 mutex_lock(&gang->aff_mutex);
                 neighbor = spufs_assert_affinity(flags, gang, aff_filp);
                 if (IS_ERR(neighbor)) {
@@ -495,27 +487,13 @@ spufs_create_context(struct inode *inode, struct dentry *dentry,
                         put_spu_context(neighbor);
         }
 
-        /*
-         * get references for dget and mntget, will be released
-         * in error path of *_open().
-         */
-        ret = spufs_context_open(dget(dentry), mntget(mnt));
-        if (ret < 0) {
+        ret = spufs_context_open(&path);
+        if (ret < 0)
                 WARN_ON(spufs_rmdir(inode, dentry));
-                if (affinity)
-                        mutex_unlock(&gang->aff_mutex);
-                mutex_unlock(&inode->i_mutex);
-                spu_forget(SPUFS_I(dentry->d_inode)->i_ctx);
-                goto out;
-        }
 
 out_aff_unlock:
         if (affinity)
                 mutex_unlock(&gang->aff_mutex);
-out_unlock:
-        mutex_unlock(&inode->i_mutex);
-out:
-        dput(dentry);
         return ret;
 }
 
@@ -556,28 +534,27 @@ out:
         return ret;
 }
 
-static int spufs_gang_open(struct dentry *dentry, struct vfsmount *mnt)
+static int spufs_gang_open(struct path *path)
 {
         int ret;
         struct file *filp;
 
         ret = get_unused_fd();
-        if (ret < 0) {
-                dput(dentry);
-                mntput(mnt);
-                goto out;
-        }
+        if (ret < 0)
+                return ret;
 
-        filp = dentry_open(dentry, mnt, O_RDONLY, current_cred());
+        /*
+         * get references for dget and mntget, will be released
+         * in error path of *_open().
+         */
+        filp = dentry_open(path, O_RDONLY, current_cred());
         if (IS_ERR(filp)) {
                 put_unused_fd(ret);
-                ret = PTR_ERR(filp);
-                goto out;
+                return PTR_ERR(filp);
         }
 
         filp->f_op = &simple_dir_operations;
         fd_install(ret, filp);
-out:
         return ret;
 }
 
@@ -585,25 +562,17 @@ static int spufs_create_gang(struct inode *inode,
                         struct dentry *dentry,
                         struct vfsmount *mnt, umode_t mode)
 {
+        struct path path = {.mnt = mnt, .dentry = dentry};
         int ret;
 
         ret = spufs_mkgang(inode, dentry, mode & S_IRWXUGO);
-        if (ret)
-                goto out;
-
-        /*
-         * get references for dget and mntget, will be released
-         * in error path of *_open().
-         */
-        ret = spufs_gang_open(dget(dentry), mntget(mnt));
-        if (ret < 0) {
-                int err = simple_rmdir(inode, dentry);
-                WARN_ON(err);
+        if (!ret) {
+                ret = spufs_gang_open(&path);
+                if (ret < 0) {
+                        int err = simple_rmdir(inode, dentry);
+                        WARN_ON(err);
+                }
         }
-
-out:
-        mutex_unlock(&inode->i_mutex);
-        dput(dentry);
         return ret;
 }
 
@@ -613,40 +582,32 @@ static struct file_system_type spufs_type;
 long spufs_create(struct path *path, struct dentry *dentry,
                 unsigned int flags, umode_t mode, struct file *filp)
 {
+        struct inode *dir = path->dentry->d_inode;
         int ret;
 
-        ret = -EINVAL;
         /* check if we are on spufs */
         if (path->dentry->d_sb->s_type != &spufs_type)
-                goto out;
+                return -EINVAL;
 
         /* don't accept undefined flags */
         if (flags & (~SPU_CREATE_FLAG_ALL))
-                goto out;
+                return -EINVAL;
 
         /* only threads can be underneath a gang */
-        if (path->dentry != path->dentry->d_sb->s_root) {
-                if ((flags & SPU_CREATE_GANG) ||
-                    !SPUFS_I(path->dentry->d_inode)->i_gang)
-                        goto out;
-        }
+        if (path->dentry != path->dentry->d_sb->s_root)
+                if ((flags & SPU_CREATE_GANG) || !SPUFS_I(dir)->i_gang)
+                        return -EINVAL;
 
         mode &= ~current_umask();
 
         if (flags & SPU_CREATE_GANG)
-                ret = spufs_create_gang(path->dentry->d_inode,
-                                         dentry, path->mnt, mode);
+                ret = spufs_create_gang(dir, dentry, path->mnt, mode);
         else
-                ret = spufs_create_context(path->dentry->d_inode,
-                                            dentry, path->mnt, flags, mode,
+                ret = spufs_create_context(dir, dentry, path->mnt, flags, mode,
                                             filp);
         if (ret >= 0)
-                fsnotify_mkdir(path->dentry->d_inode, dentry);
-        return ret;
+                fsnotify_mkdir(dir, dentry);
 
-out:
-        mutex_unlock(&path->dentry->d_inode->i_mutex);
-        dput(dentry);
         return ret;
 }
 
diff --git a/arch/powerpc/platforms/cell/spufs/syscalls.c b/arch/powerpc/platforms/cell/spufs/syscalls.c
index 5665dcc382c..5b7d8ffbf89 100644
--- a/arch/powerpc/platforms/cell/spufs/syscalls.c
+++ b/arch/powerpc/platforms/cell/spufs/syscalls.c
@@ -70,7 +70,7 @@ static long do_spu_create(const char __user *pathname, unsigned int flags,
         ret = PTR_ERR(dentry);
         if (!IS_ERR(dentry)) {
                 ret = spufs_create(&path, dentry, flags, mode, neighbor);
-                path_put(&path);
+                done_path_create(&path, dentry);
         }
 
         return ret;
diff --git a/arch/powerpc/platforms/powernv/opal-takeover.S b/arch/powerpc/platforms/powernv/opal-takeover.S
index 77b48b2b930..3cd262897c2 100644
--- a/arch/powerpc/platforms/powernv/opal-takeover.S
+++ b/arch/powerpc/platforms/powernv/opal-takeover.S
@@ -14,8 +14,6 @@
 #include <asm/asm-offsets.h>
 #include <asm/opal.h>
 
-#define STK_PARAM(i)    (48 + ((i)-3)*8)
-
 #define H_HAL_TAKEOVER                  0x5124
 #define H_HAL_TAKEOVER_QUERY_MAGIC      -1
 
@@ -23,14 +21,14 @@
 _GLOBAL(opal_query_takeover)
         mfcr    r0
         stw     r0,8(r1)
-        std     r3,STK_PARAM(r3)(r1)
-        std     r4,STK_PARAM(r4)(r1)
+        std     r3,STK_PARAM(R3)(r1)
+        std     r4,STK_PARAM(R4)(r1)
         li      r3,H_HAL_TAKEOVER
         li      r4,H_HAL_TAKEOVER_QUERY_MAGIC
         HVSC
-        ld      r10,STK_PARAM(r3)(r1)
+        ld      r10,STK_PARAM(R3)(r1)
         std     r4,0(r10)
-        ld      r10,STK_PARAM(r4)(r1)
+        ld      r10,STK_PARAM(R4)(r1)
         std     r5,0(r10)
         lwz     r0,8(r1)
         mtcrf   0xff,r0
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index fbdd74dac3a..9cda6a1ad0c 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -589,7 +589,7 @@ static int __devinit pnv_ioda_configure_pe(struct pnv_phb *phb,
                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
                 parent = pe->pbus->self;
-                count = pe->pbus->subordinate - pe->pbus->secondary + 1;
+                count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
                 switch(count) {
                 case  1: bcomp = OpalPciBusAll;         break;
                 case  2: bcomp = OpalPciBus7Bits;       break;
@@ -816,11 +816,11 @@ static void __devinit pnv_ioda_setup_bus_PE(struct pci_dev *dev,
         pe->pdev = NULL;
         pe->tce32_seg = -1;
         pe->mve_number = -1;
-        pe->rid = bus->secondary << 8;
+        pe->rid = bus->busn_res.start << 8;
         pe->dma_weight = 0;
 
-        pe_info(pe, "Secondary busses %d..%d associated with PE\n",
-                bus->secondary, bus->subordinate);
+        pe_info(pe, "Secondary busses %pR associated with PE\n",
+                &bus->busn_res);
 
         if (pnv_ioda_configure_pe(phb, pe)) {
                 /* XXX What do we do here ? */
diff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c
index 3ef46254c35..7698b6e13c5 100644
--- a/arch/powerpc/platforms/powernv/smp.c
+++ b/arch/powerpc/platforms/powernv/smp.c
@@ -106,14 +106,6 @@ static void pnv_smp_cpu_kill_self(void)
 {
         unsigned int cpu;
 
-        /* If powersave_nap is enabled, use NAP mode, else just
-         * spin aimlessly
-         */
-        if (!powersave_nap) {
-                generic_mach_cpu_die();
-                return;
-        }
-
         /* Standard hot unplug procedure */
         local_irq_disable();
         idle_task_exit();
@@ -128,7 +120,7 @@ static void pnv_smp_cpu_kill_self(void)
          */
         mtspr(SPRN_LPCR, mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1);
         while (!generic_check_cpu_restart(cpu)) {
-                power7_idle();
+                power7_nap();
                 if (!generic_check_cpu_restart(cpu)) {
                         DBG("CPU%d Unexpected exit while offline !\n", cpu);
                         /* We may be getting an IPI, so we re-enable
diff --git a/arch/powerpc/platforms/pseries/eeh_event.c b/arch/powerpc/platforms/pseries/eeh_event.c
index 4cb375c0f8d..fb506317ebb 100644
--- a/arch/powerpc/platforms/pseries/eeh_event.c
+++ b/arch/powerpc/platforms/pseries/eeh_event.c
@@ -85,8 +85,10 @@ static int eeh_event_handler(void * dummy)
         set_current_state(TASK_INTERRUPTIBLE);  /* Don't add to load average */
         edev = handle_eeh_events(event);
 
-        eeh_clear_slot(eeh_dev_to_of_node(edev), EEH_MODE_RECOVERING);
-        pci_dev_put(edev->pdev);
+        if (edev) {
+                eeh_clear_slot(eeh_dev_to_of_node(edev), EEH_MODE_RECOVERING);
+                pci_dev_put(edev->pdev);
+        }
 
         kfree(event);
         mutex_unlock(&eeh_event_mutex);
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index 8752f79a6af..c33360ec4f4 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -81,7 +81,7 @@ static int pseries_eeh_init(void)
         ibm_get_config_addr_info2       = rtas_token("ibm,get-config-addr-info2");
         ibm_get_config_addr_info        = rtas_token("ibm,get-config-addr-info");
         ibm_configure_pe                = rtas_token("ibm,configure-pe");
-        ibm_configure_bridge            = rtas_token ("ibm,configure-bridge");
+        ibm_configure_bridge            = rtas_token("ibm,configure-bridge");
 
         /* necessary sanity check */
         if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) {
@@ -89,7 +89,7 @@ static int pseries_eeh_init(void)
                         __func__);
                 return -EINVAL;
         } else if (ibm_set_slot_reset == RTAS_UNKNOWN_SERVICE) {
-                pr_warning("%s: RTAS service <ibm, set-slot-reset> invalid\n",
+                pr_warning("%s: RTAS service <ibm,set-slot-reset> invalid\n",
                         __func__);
                 return -EINVAL;
         } else if (ibm_read_slot_reset_state2 == RTAS_UNKNOWN_SERVICE &&
diff --git a/arch/powerpc/platforms/pseries/hvCall.S b/arch/powerpc/platforms/pseries/hvCall.S
index 3ce73d0052b..444fe7759e5 100644
--- a/arch/powerpc/platforms/pseries/hvCall.S
+++ b/arch/powerpc/platforms/pseries/hvCall.S
@@ -13,8 +13,6 @@
 #include <asm/asm-offsets.h>
 #include <asm/ptrace.h>
         
-#define STK_PARM(i)     (48 + ((i)-3)*8)
-
 #ifdef CONFIG_TRACEPOINTS
 
         .section        ".toc","aw"
@@ -26,7 +24,7 @@ hcall_tracepoint_refcount:
         .section        ".text"
 
 /*
- * precall must preserve all registers.  use unused STK_PARM()
+ * precall must preserve all registers.  use unused STK_PARAM()
  * areas to save snapshots and opcode. We branch around this
  * in early init (eg when populating the MMU hashtable) by using an
  * unconditional cpu feature.
@@ -40,28 +38,28 @@ END_FTR_SECTION(0, 1);						\
         cmpdi   r12,0;                                          \
         beq+    1f;                                             \
         mflr    r0;                                             \
-        std     r3,STK_PARM(r3)(r1);                            \
-        std     r4,STK_PARM(r4)(r1);                            \
-        std     r5,STK_PARM(r5)(r1);                            \
-        std     r6,STK_PARM(r6)(r1);                            \
-        std     r7,STK_PARM(r7)(r1);                            \
-        std     r8,STK_PARM(r8)(r1);                            \
-        std     r9,STK_PARM(r9)(r1);                            \
-        std     r10,STK_PARM(r10)(r1);                          \
+        std     r3,STK_PARAM(R3)(r1);                           \
+        std     r4,STK_PARAM(R4)(r1);                           \
+        std     r5,STK_PARAM(R5)(r1);                           \
+        std     r6,STK_PARAM(R6)(r1);                           \
+        std     r7,STK_PARAM(R7)(r1);                           \
+        std     r8,STK_PARAM(R8)(r1);                           \
+        std     r9,STK_PARAM(R9)(r1);                           \
+        std     r10,STK_PARAM(R10)(r1);                         \
         std     r0,16(r1);                                      \
-        addi    r4,r1,STK_PARM(FIRST_REG);                      \
+        addi    r4,r1,STK_PARAM(FIRST_REG);                     \
         stdu    r1,-STACK_FRAME_OVERHEAD(r1);                   \
         bl      .__trace_hcall_entry;                           \
         addi    r1,r1,STACK_FRAME_OVERHEAD;                     \
         ld      r0,16(r1);                                      \
-        ld      r3,STK_PARM(r3)(r1);                            \
-        ld      r4,STK_PARM(r4)(r1);                            \
-        ld      r5,STK_PARM(r5)(r1);                            \
-        ld      r6,STK_PARM(r6)(r1);                            \
-        ld      r7,STK_PARM(r7)(r1);                            \
-        ld      r8,STK_PARM(r8)(r1);                            \
-        ld      r9,STK_PARM(r9)(r1);                            \
-        ld      r10,STK_PARM(r10)(r1);                          \
+        ld      r3,STK_PARAM(R3)(r1);                           \
+        ld      r4,STK_PARAM(R4)(r1);                           \
+        ld      r5,STK_PARAM(R5)(r1);                           \
+        ld      r6,STK_PARAM(R6)(r1);                           \
+        ld      r7,STK_PARAM(R7)(r1);                           \
+        ld      r8,STK_PARAM(R8)(r1);                           \
+        ld      r9,STK_PARAM(R9)(r1);                           \
+        ld      r10,STK_PARAM(R10)(r1);                         \
         mtlr    r0;                                             \
 1:
 
@@ -79,8 +77,8 @@ END_FTR_SECTION(0, 1);						\
         cmpdi   r12,0;                                          \
         beq+    1f;                                             \
         mflr    r0;                                             \
-        ld      r6,STK_PARM(r3)(r1);                            \
-        std     r3,STK_PARM(r3)(r1);                            \
+        ld      r6,STK_PARAM(R3)(r1);                           \
+        std     r3,STK_PARAM(R3)(r1);                           \
         mr      r4,r3;                                          \
         mr      r3,r6;                                          \
         std     r0,16(r1);                                      \
@@ -88,7 +86,7 @@ END_FTR_SECTION(0, 1);						\
         bl      .__trace_hcall_exit;                            \
         addi    r1,r1,STACK_FRAME_OVERHEAD;                     \
         ld      r0,16(r1);                                      \
-        ld      r3,STK_PARM(r3)(r1);                            \
+        ld      r3,STK_PARAM(R3)(r1);                           \
         mtlr    r0;                                             \
 1:
 
@@ -114,7 +112,7 @@ _GLOBAL(plpar_hcall_norets)
         mfcr    r0
         stw     r0,8(r1)
 
-        HCALL_INST_PRECALL(r4)
+        HCALL_INST_PRECALL(R4)
 
         HVSC                            /* invoke the hypervisor */
 
@@ -130,9 +128,9 @@ _GLOBAL(plpar_hcall)
         mfcr    r0
         stw     r0,8(r1)
 
-        HCALL_INST_PRECALL(r5)
+        HCALL_INST_PRECALL(R5)
 
-        std     r4,STK_PARM(r4)(r1)     /* Save ret buffer */
+        std     r4,STK_PARAM(R4)(r1)     /* Save ret buffer */
 
         mr      r4,r5
         mr      r5,r6
@@ -143,7 +141,7 @@ _GLOBAL(plpar_hcall)
 
         HVSC                            /* invoke the hypervisor */
 
-        ld      r12,STK_PARM(r4)(r1)
+        ld      r12,STK_PARAM(R4)(r1)
         std     r4,  0(r12)
         std     r5,  8(r12)
         std     r6, 16(r12)
@@ -168,7 +166,7 @@ _GLOBAL(plpar_hcall_raw)
         mfcr    r0
         stw     r0,8(r1)
 
-        std     r4,STK_PARM(r4)(r1)     /* Save ret buffer */
+        std     r4,STK_PARAM(R4)(r1)     /* Save ret buffer */
 
         mr      r4,r5
         mr      r5,r6
@@ -179,7 +177,7 @@ _GLOBAL(plpar_hcall_raw)
 
         HVSC                            /* invoke the hypervisor */
 
-        ld      r12,STK_PARM(r4)(r1)
+        ld      r12,STK_PARAM(R4)(r1)
         std     r4,  0(r12)
         std     r5,  8(r12)
         std     r6, 16(r12)
@@ -196,9 +194,9 @@ _GLOBAL(plpar_hcall9)
         mfcr    r0
         stw     r0,8(r1)
 
-        HCALL_INST_PRECALL(r5)
+        HCALL_INST_PRECALL(R5)
 
-        std     r4,STK_PARM(r4)(r1)     /* Save ret buffer */
+        std     r4,STK_PARAM(R4)(r1)     /* Save ret buffer */
 
         mr      r4,r5
         mr      r5,r6
@@ -206,14 +204,14 @@ _GLOBAL(plpar_hcall9)
         mr      r7,r8
         mr      r8,r9
         mr      r9,r10
-        ld      r10,STK_PARM(r11)(r1)    /* put arg7 in R10 */
-        ld      r11,STK_PARM(r12)(r1)    /* put arg8 in R11 */
-        ld      r12,STK_PARM(r13)(r1)    /* put arg9 in R12 */
+        ld      r10,STK_PARAM(R11)(r1)   /* put arg7 in R10 */
+        ld      r11,STK_PARAM(R12)(r1)   /* put arg8 in R11 */
+        ld      r12,STK_PARAM(R13)(r1)    /* put arg9 in R12 */
 
         HVSC                            /* invoke the hypervisor */
 
         mr      r0,r12
-        ld      r12,STK_PARM(r4)(r1)
+        ld      r12,STK_PARAM(R4)(r1)
         std     r4,  0(r12)
         std     r5,  8(r12)
         std     r6, 16(r12)
@@ -238,7 +236,7 @@ _GLOBAL(plpar_hcall9_raw)
         mfcr    r0
         stw     r0,8(r1)
 
-        std     r4,STK_PARM(r4)(r1)     /* Save ret buffer */
+        std     r4,STK_PARAM(R4)(r1)     /* Save ret buffer */
 
         mr      r4,r5
         mr      r5,r6
@@ -246,14 +244,14 @@ _GLOBAL(plpar_hcall9_raw)
         mr      r7,r8
         mr      r8,r9
         mr      r9,r10
-        ld      r10,STK_PARM(r11)(r1)    /* put arg7 in R10 */
-        ld      r11,STK_PARM(r12)(r1)    /* put arg8 in R11 */
-        ld      r12,STK_PARM(r13)(r1)    /* put arg9 in R12 */
+        ld      r10,STK_PARAM(R11)(r1)   /* put arg7 in R10 */
+        ld      r11,STK_PARAM(R12)(r1)   /* put arg8 in R11 */
+        ld      r12,STK_PARAM(R13)(r1)    /* put arg9 in R12 */
 
         HVSC                            /* invoke the hypervisor */
 
         mr      r0,r12
-        ld      r12,STK_PARM(r4)(r1)
+        ld      r12,STK_PARAM(R4)(r1)
         std     r4,  0(r12)
         std     r5,  8(r12)
         std     r6, 16(r12)
diff --git a/arch/powerpc/platforms/pseries/iommu.c b/arch/powerpc/platforms/pseries/iommu.c
index 2d311c0caf8..bca220f2873 100644
--- a/arch/powerpc/platforms/pseries/iommu.c
+++ b/arch/powerpc/platforms/pseries/iommu.c
@@ -192,12 +192,15 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
         long l, limit;
         long tcenum_start = tcenum, npages_start = npages;
         int ret = 0;
+        unsigned long flags;
 
         if (npages == 1) {
                 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
                                            direction, attrs);
         }
 
+        local_irq_save(flags);  /* to protect tcep and the page behind it */
+
         tcep = __get_cpu_var(tce_page);
 
         /* This is safe to do since interrupts are off when we're called
@@ -207,6 +210,7 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
                 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
                 /* If allocation fails, fall back to the loop implementation */
                 if (!tcep) {
+                        local_irq_restore(flags);
                         return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
                                             direction, attrs);
                 }
@@ -240,6 +244,8 @@ static int tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
                 tcenum += limit;
         } while (npages > 0 && !rc);
 
+        local_irq_restore(flags);
+
         if (unlikely(rc == H_NOT_ENOUGH_RESOURCES)) {
                 ret = (int)rc;
                 tce_freemulti_pSeriesLP(tbl, tcenum_start,
@@ -707,6 +713,21 @@ static int __init disable_ddw_setup(char *str)
 
 early_param("disable_ddw", disable_ddw_setup);
 
+static inline void __remove_ddw(struct device_node *np, const u32 *ddw_avail, u64 liobn)
+{
+        int ret;
+
+        ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
+        if (ret)
+                pr_warning("%s: failed to remove DMA window: rtas returned "
+                        "%d to ibm,remove-pe-dma-window(%x) %llx\n",
+                        np->full_name, ret, ddw_avail[2], liobn);
+        else
+                pr_debug("%s: successfully removed DMA window: rtas returned "
+                        "%d to ibm,remove-pe-dma-window(%x) %llx\n",
+                        np->full_name, ret, ddw_avail[2], liobn);
+}
+
 static void remove_ddw(struct device_node *np)
 {
         struct dynamic_dma_window_prop *dwp;
@@ -736,15 +757,7 @@ static void remove_ddw(struct device_node *np)
                 pr_debug("%s successfully cleared tces in window.\n",
                          np->full_name);
 
-        ret = rtas_call(ddw_avail[2], 1, 1, NULL, liobn);
-        if (ret)
-                pr_warning("%s: failed to remove direct window: rtas returned "
-                        "%d to ibm,remove-pe-dma-window(%x) %llx\n",
-                        np->full_name, ret, ddw_avail[2], liobn);
-        else
-                pr_debug("%s: successfully removed direct window: rtas returned "
-                        "%d to ibm,remove-pe-dma-window(%x) %llx\n",
-                        np->full_name, ret, ddw_avail[2], liobn);
+        __remove_ddw(np, ddw_avail, liobn);
 
 delprop:
         ret = prom_remove_property(np, win64);
@@ -869,6 +882,35 @@ static int create_ddw(struct pci_dev *dev, const u32 *ddw_avail,
         return ret;
 }
 
+static void restore_default_window(struct pci_dev *dev,
+                                u32 ddw_restore_token, unsigned long liobn)
+{
+        struct eeh_dev *edev;
+        u32 cfg_addr;
+        u64 buid;
+        int ret;
+
+        /*
+         * Get the config address and phb buid of the PE window.
+         * Rely on eeh to retrieve this for us.
+         * Retrieve them from the pci device, not the node with the
+         * dma-window property
+         */
+        edev = pci_dev_to_eeh_dev(dev);
+        cfg_addr = edev->config_addr;
+        if (edev->pe_config_addr)
+                cfg_addr = edev->pe_config_addr;
+        buid = edev->phb->buid;
+
+        do {
+                ret = rtas_call(ddw_restore_token, 3, 1, NULL, cfg_addr,
+                                        BUID_HI(buid), BUID_LO(buid));
+        } while (rtas_busy_delay(ret));
+        dev_info(&dev->dev,
+                "ibm,reset-pe-dma-windows(%x) %x %x %x returned %d\n",
+                 ddw_restore_token, cfg_addr, BUID_HI(buid), BUID_LO(buid), ret);
+}
+
 /*
  * If the PE supports dynamic dma windows, and there is space for a table
  * that can map all pages in a linear offset, then setup such a table,
@@ -889,9 +931,13 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
         u64 dma_addr, max_addr;
         struct device_node *dn;
         const u32 *uninitialized_var(ddw_avail);
+        const u32 *uninitialized_var(ddw_extensions);
+        u32 ddw_restore_token = 0;
         struct direct_window *window;
         struct property *win64;
         struct dynamic_dma_window_prop *ddwprop;
+        const void *dma_window = NULL;
+        unsigned long liobn, offset, size;
 
         mutex_lock(&direct_window_init_mutex);
 
@@ -911,7 +957,40 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
         if (!ddw_avail || len < 3 * sizeof(u32))
                 goto out_unlock;
 
-       /*
+        /*
+         * the extensions property is only required to exist in certain
+         * levels of firmware and later
+         * the ibm,ddw-extensions property is a list with the first
+         * element containing the number of extensions and each
+         * subsequent entry is a value corresponding to that extension
+         */
+        ddw_extensions = of_get_property(pdn, "ibm,ddw-extensions", &len);
+        if (ddw_extensions) {
+                /*
+                 * each new defined extension length should be added to
+                 * the top of the switch so the "earlier" entries also
+                 * get picked up
+                 */
+                switch (ddw_extensions[0]) {
+                        /* ibm,reset-pe-dma-windows */
+                        case 1:
+                                ddw_restore_token = ddw_extensions[1];
+                                break;
+                }
+        }
+
+        /*
+         * Only remove the existing DMA window if we can restore back to
+         * the default state. Removing the existing window maximizes the
+         * resources available to firmware for dynamic window creation.
+         */
+        if (ddw_restore_token) {
+                dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
+                of_parse_dma_window(pdn, dma_window, &liobn, &offset, &size);
+                __remove_ddw(pdn, ddw_avail, liobn);
+        }
+
+        /*
          * Query if there is a second window of size to map the
          * whole partition.  Query returns number of windows, largest
          * block assigned to PE (partition endpoint), and two bitmasks
@@ -920,7 +999,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
         dn = pci_device_to_OF_node(dev);
         ret = query_ddw(dev, ddw_avail, &query);
         if (ret != 0)
-                goto out_unlock;
+                goto out_restore_window;
 
         if (query.windows_available == 0) {
                 /*
@@ -929,7 +1008,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
                  * trading in for a larger page size.
                  */
                 dev_dbg(&dev->dev, "no free dynamic windows");
-                goto out_unlock;
+                goto out_restore_window;
         }
         if (query.page_size & 4) {
                 page_shift = 24; /* 16MB */
@@ -940,7 +1019,7 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
         } else {
                 dev_dbg(&dev->dev, "no supported direct page size in mask %x",
                           query.page_size);
-                goto out_unlock;
+                goto out_restore_window;
         }
         /* verify the window * number of ptes will map the partition */
         /* check largest block * page size > max memory hotplug addr */
@@ -949,14 +1028,14 @@ static u64 enable_ddw(struct pci_dev *dev, struct device_node *pdn)
                 dev_dbg(&dev->dev, "can't map partiton max 0x%llx with %u "
                           "%llu-sized pages\n", max_addr,  query.largest_available_block,
                           1ULL << page_shift);
-                goto out_unlock;
+                goto out_restore_window;
         }
         len = order_base_2(max_addr);
         win64 = kzalloc(sizeof(struct property), GFP_KERNEL);
         if (!win64) {
                 dev_info(&dev->dev,
                         "couldn't allocate property for 64bit dma window\n");
-                goto out_unlock;
+                goto out_restore_window;
         }
         win64->name = kstrdup(DIRECT64_PROPNAME, GFP_KERNEL);
         win64->value = ddwprop = kmalloc(sizeof(*ddwprop), GFP_KERNEL);
@@ -1018,6 +1097,10 @@ out_free_prop:
         kfree(win64->value);
         kfree(win64);
 
+out_restore_window:
+        if (ddw_restore_token)
+                restore_default_window(dev, ddw_restore_token, liobn);
+
 out_unlock:
         mutex_unlock(&direct_window_init_mutex);
         return dma_addr;
@@ -1051,7 +1134,7 @@ static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
         if (!pdn || !PCI_DN(pdn)) {
                 printk(KERN_WARNING "pci_dma_dev_setup_pSeriesLP: "
                        "no DMA window found for pci dev=%s dn=%s\n",
-                                 pci_name(dev), dn? dn->full_name : "<null>");
+                                 pci_name(dev), of_node_full_name(dn));
                 return;
         }
         pr_debug("  parent is %s\n", pdn->full_name);
diff --git a/arch/powerpc/platforms/pseries/mobility.c b/arch/powerpc/platforms/pseries/mobility.c
index 029a562af37..dd30b12edfe 100644
--- a/arch/powerpc/platforms/pseries/mobility.c
+++ b/arch/powerpc/platforms/pseries/mobility.c
@@ -67,7 +67,6 @@ static int update_dt_property(struct device_node *dn, struct property **prop,
                               const char *name, u32 vd, char *value)
 {
         struct property *new_prop = *prop;
-        struct property *old_prop;
         int more = 0;
 
         /* A negative 'vd' value indicates that only part of the new property
@@ -117,12 +116,7 @@ static int update_dt_property(struct device_node *dn, struct property **prop,
         }
 
         if (!more) {
-                old_prop = of_find_property(dn, new_prop->name, NULL);
-                if (old_prop)
-                        prom_update_property(dn, new_prop, old_prop);
-                else
-                        prom_add_property(dn, new_prop);
-
+                prom_update_property(dn, new_prop);
                 new_prop = NULL;
         }
 
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index 8b7bafa489c..3ccebc83dc0 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -121,7 +121,7 @@ void pcibios_add_pci_devices(struct pci_bus * bus)
                 if (!num)
                         return;
                 pcibios_setup_bus_devices(bus);
-                max = bus->secondary;
+                max = bus->busn_res.start;
                 for (pass=0; pass < 2; pass++)
                         list_for_each_entry(dev, &bus->devices, bus_list) {
                         if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
diff --git a/arch/powerpc/platforms/pseries/processor_idle.c b/arch/powerpc/platforms/pseries/processor_idle.c
index c71be66bd5d..455760b1fe6 100644
--- a/arch/powerpc/platforms/pseries/processor_idle.c
+++ b/arch/powerpc/platforms/pseries/processor_idle.c
@@ -11,6 +11,7 @@
 #include <linux/moduleparam.h>
 #include <linux/cpuidle.h>
 #include <linux/cpu.h>
+#include <linux/notifier.h>
 
 #include <asm/paca.h>
 #include <asm/reg.h>
@@ -189,17 +190,40 @@ static struct cpuidle_state shared_states[MAX_IDLE_STATE_COUNT] = {
                 .enter = &shared_cede_loop },
 };
 
-int pseries_notify_cpuidle_add_cpu(int cpu)
+static int pseries_cpuidle_add_cpu_notifier(struct notifier_block *n,
+                        unsigned long action, void *hcpu)
 {
+        int hotcpu = (unsigned long)hcpu;
         struct cpuidle_device *dev =
-                        per_cpu_ptr(pseries_cpuidle_devices, cpu);
+                        per_cpu_ptr(pseries_cpuidle_devices, hotcpu);
+
         if (dev && cpuidle_get_driver()) {
-                cpuidle_disable_device(dev);
-                cpuidle_enable_device(dev);
+                switch (action) {
+                case CPU_ONLINE:
+                case CPU_ONLINE_FROZEN:
+                        cpuidle_pause_and_lock();
+                        cpuidle_enable_device(dev);
+                        cpuidle_resume_and_unlock();
+                        break;
+
+                case CPU_DEAD:
+                case CPU_DEAD_FROZEN:
+                        cpuidle_pause_and_lock();
+                        cpuidle_disable_device(dev);
+                        cpuidle_resume_and_unlock();
+                        break;
+
+                default:
+                        return NOTIFY_DONE;
+                }
         }
-        return 0;
+        return NOTIFY_OK;
 }
 
+static struct notifier_block setup_hotplug_notifier = {
+        .notifier_call = pseries_cpuidle_add_cpu_notifier,
+};
+
 /*
  * pseries_cpuidle_driver_init()
  */
@@ -324,6 +348,7 @@ static int __init pseries_processor_idle_init(void)
                 return retval;
         }
 
+        register_cpu_notifier(&setup_hotplug_notifier);
         printk(KERN_DEBUG "pseries_idle_driver registered\n");
 
         return 0;
@@ -332,6 +357,7 @@ static int __init pseries_processor_idle_init(void)
 static void __exit pseries_processor_idle_exit(void)
 {
 
+        unregister_cpu_notifier(&setup_hotplug_notifier);
         pseries_idle_devices_uninit();
         cpuidle_unregister_driver(&pseries_idle_driver);
 
diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c
index 7b3bf76ef83..39f71fba9b3 100644
--- a/arch/powerpc/platforms/pseries/reconfig.c
+++ b/arch/powerpc/platforms/pseries/reconfig.c
@@ -432,7 +432,7 @@ static int do_update_property(char *buf, size_t bufsize)
         unsigned char *value;
         char *name, *end, *next_prop;
         int rc, length;
-        struct property *newprop, *oldprop;
+        struct property *newprop;
         buf = parse_node(buf, bufsize, &np);
         end = buf + bufsize;
 
@@ -443,6 +443,9 @@ static int do_update_property(char *buf, size_t bufsize)
         if (!next_prop)
                 return -EINVAL;
 
+        if (!strlen(name))
+                return -ENODEV;
+
         newprop = new_property(name, length, value, NULL);
         if (!newprop)
                 return -ENOMEM;
@@ -450,18 +453,11 @@ static int do_update_property(char *buf, size_t bufsize)
         if (!strcmp(name, "slb-size") || !strcmp(name, "ibm,slb-size"))
                 slb_set_size(*(int *)value);
 
-        oldprop = of_find_property(np, name,NULL);
-        if (!oldprop) {
-                if (strlen(name))
-                        return prom_add_property(np, newprop);
-                return -ENODEV;
-        }
-
         upd_value.node = np;
         upd_value.property = newprop;
         pSeries_reconfig_notify(PSERIES_UPDATE_PROPERTY, &upd_value);
 
-        rc = prom_update_property(np, newprop, oldprop);
+        rc = prom_update_property(np, newprop);
         if (rc)
                 return rc;
 
@@ -486,7 +482,7 @@ static int do_update_property(char *buf, size_t bufsize)
 
                 rc = pSeries_reconfig_notify(action, value);
                 if (rc) {
-                        prom_update_property(np, oldprop, newprop);
+                        prom_update_property(np, newprop);
                         return rc;
                 }
         }
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index e16bb8d4855..71706bc34a0 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -147,7 +147,6 @@ static void __devinit smp_xics_setup_cpu(int cpu)
         set_cpu_current_state(cpu, CPU_STATE_ONLINE);
         set_default_offline_state(cpu);
 #endif
-        pseries_notify_cpuidle_add_cpu(cpu);
 }
 
 static int __devinit smp_pSeries_kick_cpu(int nr)
diff --git a/arch/powerpc/sysdev/6xx-suspend.S b/arch/powerpc/sysdev/6xx-suspend.S
index 21cda085d92..cf48e9cb257 100644
--- a/arch/powerpc/sysdev/6xx-suspend.S
+++ b/arch/powerpc/sysdev/6xx-suspend.S
@@ -29,7 +29,7 @@ _GLOBAL(mpc6xx_enter_standby)
         ori     r5, r5, ret_from_standby@l
         mtlr    r5
 
-        rlwinm  r5, r1, 0, 0, 31-THREAD_SHIFT
+        CURRENT_THREAD_INFO(r5, r1)
         lwz     r6, TI_LOCAL_FLAGS(r5)
         ori     r6, r6, _TLF_SLEEPING
         stw     r6, TI_LOCAL_FLAGS(r5)
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
index 60c9c0bd5ba..2aa97ddb7b7 100644
--- a/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_ctlr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc
+ * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc
  *
  * QorIQ based Cache Controller Memory Mapped Registers
  *
@@ -91,7 +91,7 @@ struct mpc85xx_l2ctlr {
 
 struct sram_parameters {
         unsigned int sram_size;
-        uint64_t sram_offset;
+        phys_addr_t sram_offset;
 };
 
 extern int instantiate_cache_sram(struct platform_device *dev,
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index cedabd0f4bf..68ac3aacb19 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
  *
  * QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
  *
@@ -31,24 +31,21 @@ static char *sram_size;
 static char *sram_offset;
 struct mpc85xx_l2ctlr __iomem *l2ctlr;
 
-static long get_cache_sram_size(void)
+static int get_cache_sram_params(struct sram_parameters *sram_params)
 {
-        unsigned long val;
+        unsigned long long addr;
+        unsigned int size;
 
-        if (!sram_size || (strict_strtoul(sram_size, 0, &val) < 0))
+        if (!sram_size || (kstrtouint(sram_size, 0, &size) < 0))
                 return -EINVAL;
 
-        return val;
-}
-
-static long get_cache_sram_offset(void)
-{
-        unsigned long val;
-
-        if (!sram_offset || (strict_strtoul(sram_offset, 0, &val) < 0))
+        if (!sram_offset || (kstrtoull(sram_offset, 0, &addr) < 0))
                 return -EINVAL;
 
-        return val;
+        sram_params->sram_offset = addr;
+        sram_params->sram_size = size;
+
+        return 0;
 }
 
 static int __init get_size_from_cmdline(char *str)
@@ -93,17 +90,9 @@ static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
         }
         l2cache_size = *prop;
 
-        sram_params.sram_size  = get_cache_sram_size();
-        if ((int)sram_params.sram_size <= 0) {
-                dev_err(&dev->dev,
-                        "Entire L2 as cache, Aborting Cache-SRAM stuff\n");
-                return -EINVAL;
-        }
-
-        sram_params.sram_offset  = get_cache_sram_offset();
-        if ((int64_t)sram_params.sram_offset <= 0) {
+        if (get_cache_sram_params(&sram_params)) {
                 dev_err(&dev->dev,
-                        "Entire L2 as cache, provide a valid sram offset\n");
+                        "Entire L2 as cache, provide valid sram offset and size\n");
                 return -EINVAL;
         }
 
@@ -125,14 +114,14 @@ static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
          * Write bits[0-17] to srbar0
          */
         out_be32(&l2ctlr->srbar0,
-                sram_params.sram_offset & L2SRAM_BAR_MSK_LO18);
+                lower_32_bits(sram_params.sram_offset) & L2SRAM_BAR_MSK_LO18);
 
         /*
          * Write bits[18-21] to srbare0
          */
 #ifdef CONFIG_PHYS_64BIT
         out_be32(&l2ctlr->srbarea0,
-                (sram_params.sram_offset >> 32) & L2SRAM_BARE_MSK_HI4);
+                upper_32_bits(sram_params.sram_offset) & L2SRAM_BARE_MSK_HI4);
 #endif
 
         clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 6073288fed2..c37f4613632 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,7 +1,7 @@
 /*
  * MPC83xx/85xx/86xx PCI/PCIE support routing.
  *
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
+ * Copyright 2007-2012 Freescale Semiconductor, Inc.
  * Copyright 2008-2009 MontaVista Software, Inc.
  *
  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
@@ -36,7 +36,7 @@
 
 static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
 
-static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
+static void __devinit quirk_fsl_pcie_header(struct pci_dev *dev)
 {
         u8 progif;
 
@@ -465,7 +465,7 @@ int __init fsl_add_bridge(struct device_node *dev, int is_primary)
                         iounmap(hose->cfg_data);
                 iounmap(hose->cfg_addr);
                 pcibios_free_controller(hose);
-                return 0;
+                return -ENODEV;
         }
 
         setup_pci_cmd(hose);
@@ -807,3 +807,75 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
 
         return 0;
 }
+
+#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
+static const struct of_device_id pci_ids[] = {
+        { .compatible = "fsl,mpc8540-pci", },
+        { .compatible = "fsl,mpc8548-pcie", },
+        { .compatible = "fsl,mpc8610-pci", },
+        { .compatible = "fsl,mpc8641-pcie", },
+        { .compatible = "fsl,p1022-pcie", },
+        { .compatible = "fsl,p1010-pcie", },
+        { .compatible = "fsl,p1023-pcie", },
+        { .compatible = "fsl,p4080-pcie", },
+        { .compatible = "fsl,qoriq-pcie-v2.3", },
+        { .compatible = "fsl,qoriq-pcie-v2.2", },
+        {},
+};
+
+struct device_node *fsl_pci_primary;
+
+void __devinit fsl_pci_init(void)
+{
+        int ret;
+        struct device_node *node;
+        struct pci_controller *hose;
+        dma_addr_t max = 0xffffffff;
+
+        /* Callers can specify the primary bus using other means. */
+        if (!fsl_pci_primary) {
+                /* If a PCI host bridge contains an ISA node, it's primary. */
+                node = of_find_node_by_type(NULL, "isa");
+                while ((fsl_pci_primary = of_get_parent(node))) {
+                        of_node_put(node);
+                        node = fsl_pci_primary;
+
+                        if (of_match_node(pci_ids, node))
+                                break;
+                }
+        }
+
+        node = NULL;
+        for_each_node_by_type(node, "pci") {
+                if (of_match_node(pci_ids, node)) {
+                        /*
+                         * If there's no PCI host bridge with ISA, arbitrarily
+                         * designate one as primary.  This can go away once
+                         * various bugs with primary-less systems are fixed.
+                         */
+                        if (!fsl_pci_primary)
+                                fsl_pci_primary = node;
+
+                        ret = fsl_add_bridge(node, fsl_pci_primary == node);
+                        if (ret == 0) {
+                                hose = pci_find_hose_for_OF_device(node);
+                                max = min(max, hose->dma_window_base_cur +
+                                                hose->dma_window_size);
+                        }
+                }
+        }
+
+#ifdef CONFIG_SWIOTLB
+        /*
+         * if we couldn't map all of DRAM via the dma windows
+         * we need SWIOTLB to handle buffers located outside of
+         * dma capable memory region
+         */
+        if (memblock_end_of_DRAM() - 1 > max) {
+                ppc_swiotlb_enable = 1;
+                set_pci_dma_ops(&swiotlb_dma_ops);
+                ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
+        }
+#endif
+}
+#endif
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index a39ed5cc2c5..baa0fd18289 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -93,5 +93,13 @@ extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
 extern int mpc83xx_add_bridge(struct device_node *dev);
 u64 fsl_pci_immrbar_base(struct pci_controller *hose);
 
+extern struct device_node *fsl_pci_primary;
+
+#ifdef CONFIG_FSL_PCI
+void fsl_pci_init(void);
+#else
+static inline void fsl_pci_init(void) {}
+#endif
+
 #endif /* __POWERPC_FSL_PCI_H */
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 395af134774..bfc6211e542 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -1211,7 +1211,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         if (of_get_property(node, "single-cpu-affinity", NULL))
                 flags |= MPIC_SINGLE_DEST_CPU;
         if (of_device_is_compatible(node, "fsl,mpic"))
-                flags |= MPIC_FSL;
+                flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
 
         mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
         if (mpic == NULL)
@@ -1376,7 +1376,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
 
         mpic->irqhost = irq_domain_add_linear(mpic->node,
-                                       last_irq + 1,
+                                       intvec_top,
                                        &mpic_host_ops, mpic);
 
         /*
diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c
index 483d8fa72e8..e961f8c4a8f 100644
--- a/arch/powerpc/sysdev/mpic_msgr.c
+++ b/arch/powerpc/sysdev/mpic_msgr.c
@@ -14,6 +14,9 @@
 #include <linux/list.h>
 #include <linux/of_platform.h>
 #include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/slab.h>
 #include <asm/prom.h>
 #include <asm/hw_irq.h>
 #include <asm/ppc-pci.h>
diff --git a/arch/powerpc/sysdev/mv64x60_pci.c b/arch/powerpc/sysdev/mv64x60_pci.c
index b0037cefaad..364b14d4754 100644
--- a/arch/powerpc/sysdev/mv64x60_pci.c
+++ b/arch/powerpc/sysdev/mv64x60_pci.c
@@ -104,7 +104,7 @@ subsys_initcall(mv64x60_sysfs_init);
 
 #endif /* CONFIG_SYSFS */
 
-static void __init mv64x60_pci_fixup_early(struct pci_dev *dev)
+static void __devinit mv64x60_pci_fixup_early(struct pci_dev *dev)
 {
         /*
          * Set the host bridge hdr_type to an invalid value so that
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 818e763f826..b0436752972 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -395,6 +395,9 @@ static void qe_upload_microcode(const void *base,
 
         for (i = 0; i < be32_to_cpu(ucode->count); i++)
                 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
+        
+        /* Set I-RAM Ready Register */
+        out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
 }
 
 /*
diff --git a/arch/powerpc/sysdev/xics/icp-hv.c b/arch/powerpc/sysdev/xics/icp-hv.c
index 253dce98c16..df0fc582146 100644
--- a/arch/powerpc/sysdev/xics/icp-hv.c
+++ b/arch/powerpc/sysdev/xics/icp-hv.c
@@ -65,7 +65,11 @@ static inline void icp_hv_set_xirr(unsigned int value)
 static inline void icp_hv_set_qirr(int n_cpu , u8 value)
 {
         int hw_cpu = get_hard_smp_processor_id(n_cpu);
-        long rc = plpar_hcall_norets(H_IPI, hw_cpu, value);
+        long rc;
+
+        /* Make sure all previous accesses are ordered before IPI sending */
+        mb();
+        rc = plpar_hcall_norets(H_IPI, hw_cpu, value);
         if (rc != H_SUCCESS) {
                 pr_err("%s: bad return code qirr cpu=%d hw_cpu=%d mfrr=0x%x "
                         "returned %ld\n", __func__, n_cpu, hw_cpu, value, rc);
@@ -111,7 +115,7 @@ static unsigned int icp_hv_get_irq(void)
         if (vec == XICS_IRQ_SPURIOUS)
                 return NO_IRQ;
 
-        irq = irq_radix_revmap_lookup(xics_host, vec);
+        irq = irq_find_mapping(xics_host, vec);
         if (likely(irq != NO_IRQ)) {
                 xics_push_cppr(vec);
                 return irq;
diff --git a/arch/powerpc/sysdev/xics/icp-native.c b/arch/powerpc/sysdev/xics/icp-native.c
index 4c79b6fbee1..48861d3fcd0 100644
--- a/arch/powerpc/sysdev/xics/icp-native.c
+++ b/arch/powerpc/sysdev/xics/icp-native.c
@@ -119,7 +119,7 @@ static unsigned int icp_native_get_irq(void)
         if (vec == XICS_IRQ_SPURIOUS)
                 return NO_IRQ;
 
-        irq = irq_radix_revmap_lookup(xics_host, vec);
+        irq = irq_find_mapping(xics_host, vec);
         if (likely(irq != NO_IRQ)) {
                 xics_push_cppr(vec);
                 return irq;
diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c
index cd1d18db92c..9049d9f4448 100644
--- a/arch/powerpc/sysdev/xics/xics-common.c
+++ b/arch/powerpc/sysdev/xics/xics-common.c
@@ -329,9 +329,6 @@ static int xics_host_map(struct irq_domain *h, unsigned int virq,
 
         pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
 
-        /* Insert the interrupt mapping into the radix tree for fast lookup */
-        irq_radix_revmap_insert(xics_host, virq, hw);
-
         /* They aren't all level sensitive but we just don't really know */
         irq_set_status_flags(virq, IRQ_LEVEL);
 
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index eab3492a45c..9b49c65ee7a 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -17,6 +17,7 @@
 #include <linux/reboot.h>
 #include <linux/delay.h>
 #include <linux/kallsyms.h>
+#include <linux/kmsg_dump.h>
 #include <linux/cpumask.h>
 #include <linux/export.h>
 #include <linux/sysrq.h>
@@ -894,13 +895,13 @@ cmds(struct pt_regs *excp)
 #endif
                 default:
                         printf("Unrecognized command: ");
-                        do {
+                        do {
                                 if (' ' < cmd && cmd <= '~')
                                         putchar(cmd);
                                 else
                                         printf("\\x%x", cmd);
                                 cmd = inchar();
-                        } while (cmd != '\n'); 
+                        } while (cmd != '\n');
                         printf(" (type ? for help)\n");
                         break;
                 }
@@ -1097,7 +1098,7 @@ static long check_bp_loc(unsigned long addr)
         return 1;
 }
 
-static char *breakpoint_help_string = 
+static char *breakpoint_help_string =
     "Breakpoint command usage:\n"
     "b                show breakpoints\n"
     "b <addr> [cnt]   set breakpoint at given instr addr\n"
@@ -1193,7 +1194,7 @@ bpt_cmds(void)
 
         default:
                 termch = cmd;
-                cmd = skipbl();
+                cmd = skipbl();
                 if (cmd == '?') {
                         printf(breakpoint_help_string);
                         break;
@@ -1359,7 +1360,7 @@ static void xmon_show_stack(unsigned long sp, unsigned long lr,
                                        sp + REGS_OFFSET);
                                 break;
                         }
-                        printf("--- Exception: %lx %s at ", regs.trap,
+                        printf("--- Exception: %lx %s at ", regs.trap,
                                getvecname(TRAP(&regs)));
                         pc = regs.nip;
                         lr = regs.link;
@@ -1623,14 +1624,14 @@ static void super_regs(void)
 
         cmd = skipbl();
         if (cmd == '\n') {
-                unsigned long sp, toc;
+                unsigned long sp, toc;
                 asm("mr %0,1" : "=r" (sp) :);
                 asm("mr %0,2" : "=r" (toc) :);
 
                 printf("msr  = "REG"  sprg0= "REG"\n",
                        mfmsr(), mfspr(SPRN_SPRG0));
                 printf("pvr  = "REG"  sprg1= "REG"\n",
-                       mfspr(SPRN_PVR), mfspr(SPRN_SPRG1)); 
+                       mfspr(SPRN_PVR), mfspr(SPRN_SPRG1));
                 printf("dec  = "REG"  sprg2= "REG"\n",
                        mfspr(SPRN_DEC), mfspr(SPRN_SPRG2));
                 printf("sp   = "REG"  sprg3= "REG"\n", sp, mfspr(SPRN_SPRG3));
@@ -1783,7 +1784,7 @@ byterev(unsigned char *val, int size)
 static int brev;
 static int mnoread;
 
-static char *memex_help_string = 
+static char *memex_help_string =
     "Memory examine command usage:\n"
     "m [addr] [flags] examine/change memory\n"
     "  addr is optional.  will start where left off.\n"
@@ -1798,7 +1799,7 @@ static char *memex_help_string =
     "NOTE: flags are saved as defaults\n"
     "";
 
-static char *memex_subcmd_help_string = 
+static char *memex_subcmd_help_string =
     "Memory examine subcommands:\n"
     "  hexval   write this val to current location\n"
     "  'string' write chars from string to this location\n"
@@ -2064,7 +2065,7 @@ prdump(unsigned long adrs, long ndump)
                 nr = mread(adrs, temp, r);
                 adrs += nr;
                 for (m = 0; m < r; ++m) {
-                        if ((m & (sizeof(long) - 1)) == 0 && m > 0)
+                        if ((m & (sizeof(long) - 1)) == 0 && m > 0)
                                 putchar(' ');
                         if (m < nr)
                                 printf("%.2x", temp[m]);
@@ -2072,7 +2073,7 @@ prdump(unsigned long adrs, long ndump)
                                 printf("%s", fault_chars[fault_type]);
                 }
                 for (; m < 16; ++m) {
-                        if ((m & (sizeof(long) - 1)) == 0)
+                        if ((m & (sizeof(long) - 1)) == 0)
                                 putchar(' ');
                         printf("  ");
                 }
@@ -2148,45 +2149,28 @@ print_address(unsigned long addr)
 void
 dump_log_buf(void)
 {
-        const unsigned long size = 128;
-        unsigned long end, addr;
-        unsigned char buf[size + 1];
-
-        addr = 0;
-        buf[size] = '\0';
-
-        if (setjmp(bus_error_jmp) != 0) {
-                printf("Unable to lookup symbol __log_buf!\n");
-                return;
-        }
-
-        catch_memory_errors = 1;
-        sync();
-        addr = kallsyms_lookup_name("__log_buf");
-
-        if (! addr)
-                printf("Symbol __log_buf not found!\n");
-        else {
-                end = addr + (1 << CONFIG_LOG_BUF_SHIFT);
-                while (addr < end) {
-                        if (! mread(addr, buf, size)) {
-                                printf("Can't read memory at address 0x%lx\n", addr);
-                                break;
-                        }
-
-                        printf("%s", buf);
-
-                        if (strlen(buf) < size)
-                                break;
-
-                        addr += size;
-                }
-        }
-
-        sync();
-        /* wait a little while to see if we get a machine check */
-        __delay(200);
-        catch_memory_errors = 0;
+        struct kmsg_dumper dumper = { .active = 1 };
+        unsigned char buf[128];
+        size_t len;
+
+        if (setjmp(bus_error_jmp) != 0) {
+                printf("Error dumping printk buffer!\n");
+                return;
+        }
+
+        catch_memory_errors = 1;
+        sync();
+
+        kmsg_dump_rewind_nolock(&dumper);
+        while (kmsg_dump_get_line_nolock(&dumper, false, buf, sizeof(buf), &len)) {
+                buf[len] = '\0';
+                printf("%s", buf);
+        }
+
+        sync();
+        /* wait a little while to see if we get a machine check */
+        __delay(200);
+        catch_memory_errors = 0;
 }
 
 /*
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index a39b4690c17..107610e01a2 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -85,10 +85,12 @@ config S390
         select HAVE_ARCH_MUTEX_CPU_RELAX
         select HAVE_ARCH_JUMP_LABEL if !MARCH_G5
         select ARCH_SAVE_PAGE_KEYS if HIBERNATION
+        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
         select HAVE_MEMBLOCK
         select HAVE_MEMBLOCK_NODE_MAP
         select HAVE_CMPXCHG_LOCAL
         select ARCH_DISCARD_MEMBLOCK
+        select BUILDTIME_EXTABLE_SORT
         select ARCH_INLINE_SPIN_TRYLOCK
         select ARCH_INLINE_SPIN_TRYLOCK_BH
         select ARCH_INLINE_SPIN_LOCK
@@ -117,10 +119,12 @@ config S390
         select ARCH_INLINE_WRITE_UNLOCK_BH
         select ARCH_INLINE_WRITE_UNLOCK_IRQ
         select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE
+        select ARCH_WANT_IPC_PARSE_VERSION
         select GENERIC_SMP_IDLE_THREAD
         select GENERIC_TIME_VSYSCALL
         select GENERIC_CLOCKEVENTS
         select KTIME_SCALAR if 32BIT
+        select HAVE_ARCH_SECCOMP_FILTER
 
 config SCHED_OMIT_FRAME_POINTER
         def_bool y
diff --git a/arch/s390/appldata/appldata.h b/arch/s390/appldata/appldata.h
index f0b23fc759b..4a67f2b5f6a 100644
--- a/arch/s390/appldata/appldata.h
+++ b/arch/s390/appldata/appldata.h
@@ -1,6 +1,4 @@
 /*
- * arch/s390/appldata/appldata.h
- *
  * Definitions and interface for Linux - z/VM Monitor Stream.
  *
  * Copyright IBM Corp. 2003, 2008
diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c
index 24bff4f1cc5..bae0f402bf2 100644
--- a/arch/s390/appldata/appldata_base.c
+++ b/arch/s390/appldata/appldata_base.c
@@ -1,6 +1,4 @@
 /*
- * arch/s390/appldata/appldata_base.c
- *
  * Base infrastructure for Linux-z/VM Monitor Stream, Stage 1.
  * Exports appldata_register_ops() and appldata_unregister_ops() for the
  * data gathering modules.
@@ -29,7 +27,7 @@
 #include <linux/suspend.h>
 #include <linux/platform_device.h>
 #include <asm/appldata.h>
-#include <asm/timer.h>
+#include <asm/vtimer.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 #include <asm/smp.h>
@@ -84,8 +82,7 @@ static struct ctl_table appldata_dir_table[] = {
 /*
  * Timer
  */
-static DEFINE_PER_CPU(struct vtimer_list, appldata_timer);
-static atomic_t appldata_expire_count = ATOMIC_INIT(0);
+static struct vtimer_list appldata_timer;
 
 static DEFINE_SPINLOCK(appldata_timer_lock);
 static int appldata_interval = APPLDATA_CPU_INTERVAL;
@@ -115,10 +112,7 @@ static LIST_HEAD(appldata_ops_list);
  */
 static void appldata_timer_function(unsigned long data)
 {
-        if (atomic_dec_and_test(&appldata_expire_count)) {
-                atomic_set(&appldata_expire_count, num_online_cpus());
-                queue_work(appldata_wq, (struct work_struct *) data);
-        }
+        queue_work(appldata_wq, (struct work_struct *) data);
 }
 
 /*
@@ -131,7 +125,6 @@ static void appldata_work_fn(struct work_struct *work)
         struct list_head *lh;
         struct appldata_ops *ops;
 
-        get_online_cpus();
         mutex_lock(&appldata_ops_mutex);
         list_for_each(lh, &appldata_ops_list) {
                 ops = list_entry(lh, struct appldata_ops, list);
@@ -140,7 +133,6 @@ static void appldata_work_fn(struct work_struct *work)
                 }
         }
         mutex_unlock(&appldata_ops_mutex);
-        put_online_cpus();
 }
 
 /*
@@ -168,20 +160,6 @@ int appldata_diag(char record_nr, u16 function, unsigned long buffer,
 
 /****************************** /proc stuff **********************************/
 
-/*
- * appldata_mod_vtimer_wrap()
- *
- * wrapper function for mod_virt_timer(), because smp_call_function_single()
- * accepts only one parameter.
- */
-static void __appldata_mod_vtimer_wrap(void *p) {
-        struct {
-                struct vtimer_list *timer;
-                u64    expires;
-        } *args = p;
-        mod_virt_timer_periodic(args->timer, args->expires);
-}
-
 #define APPLDATA_ADD_TIMER      0
 #define APPLDATA_DEL_TIMER      1
 #define APPLDATA_MOD_TIMER      2
@@ -192,49 +170,28 @@ static void __appldata_mod_vtimer_wrap(void *p) {
  * Add, delete or modify virtual timers on all online cpus.
  * The caller needs to get the appldata_timer_lock spinlock.
  */
-static void
-__appldata_vtimer_setup(int cmd)
+static void __appldata_vtimer_setup(int cmd)
 {
-        u64 per_cpu_interval;
-        int i;
+        u64 timer_interval = (u64) appldata_interval * 1000 * TOD_MICRO;
 
         switch (cmd) {
         case APPLDATA_ADD_TIMER:
                 if (appldata_timer_active)
                         break;
-                per_cpu_interval = (u64) (appldata_interval*1000 /
-                                          num_online_cpus()) * TOD_MICRO;
-                for_each_online_cpu(i) {
-                        per_cpu(appldata_timer, i).expires = per_cpu_interval;
-                        smp_call_function_single(i, add_virt_timer_periodic,
-                                                 &per_cpu(appldata_timer, i),
-                                                 1);
-                }
+                appldata_timer.expires = timer_interval;
+                add_virt_timer_periodic(&appldata_timer);
                 appldata_timer_active = 1;
                 break;
         case APPLDATA_DEL_TIMER:
-                for_each_online_cpu(i)
-                        del_virt_timer(&per_cpu(appldata_timer, i));
+                del_virt_timer(&appldata_timer);
                 if (!appldata_timer_active)
                         break;
                 appldata_timer_active = 0;
-                atomic_set(&appldata_expire_count, num_online_cpus());
                 break;
         case APPLDATA_MOD_TIMER:
-                per_cpu_interval = (u64) (appldata_interval*1000 /
-                                          num_online_cpus()) * TOD_MICRO;
                 if (!appldata_timer_active)
                         break;
-                for_each_online_cpu(i) {
-                        struct {
-                                struct vtimer_list *timer;
-                                u64    expires;
-                        } args;
-                        args.timer = &per_cpu(appldata_timer, i);
-                        args.expires = per_cpu_interval;
-                        smp_call_function_single(i, __appldata_mod_vtimer_wrap,
-                                                 &args, 1);
-                }
+                mod_virt_timer_periodic(&appldata_timer, timer_interval);
         }
 }
 
@@ -265,14 +222,12 @@ appldata_timer_handler(ctl_table *ctl, int write,
         len = *lenp;
         if (copy_from_user(buf, buffer, len > sizeof(buf) ? sizeof(buf) : len))
                 return -EFAULT;
-        get_online_cpus();
         spin_lock(&appldata_timer_lock);
         if (buf[0] == '1')
                 __appldata_vtimer_setup(APPLDATA_ADD_TIMER);
         else if (buf[0] == '0')
                 __appldata_vtimer_setup(APPLDATA_DEL_TIMER);
         spin_unlock(&appldata_timer_lock);
-        put_online_cpus();
 out:
         *lenp = len;
         *ppos += len;
@@ -305,20 +260,17 @@ appldata_interval_handler(ctl_table *ctl, int write,
                 goto out;
         }
         len = *lenp;
-        if (copy_from_user(buf, buffer, len > sizeof(buf) ? sizeof(buf) : len)) {
+        if (copy_from_user(buf, buffer, len > sizeof(buf) ? sizeof(buf) : len))
                 return -EFAULT;
-        }
         interval = 0;
         sscanf(buf, "%i", &interval);
         if (interval <= 0)
                 return -EINVAL;
 
-        get_online_cpus();
         spin_lock(&appldata_timer_lock);
         appldata_interval = interval;
         __appldata_vtimer_setup(APPLDATA_MOD_TIMER);
         spin_unlock(&appldata_timer_lock);
-        put_online_cpus();
 out:
         *lenp = len;
         *ppos += len;
@@ -485,14 +437,12 @@ static int appldata_freeze(struct device *dev)
         int rc;
         struct list_head *lh;
 
-        get_online_cpus();
         spin_lock(&appldata_timer_lock);
         if (appldata_timer_active) {
                 __appldata_vtimer_setup(APPLDATA_DEL_TIMER);
                 appldata_timer_suspended = 1;
         }
         spin_unlock(&appldata_timer_lock);
-        put_online_cpus();
 
         mutex_lock(&appldata_ops_mutex);
         list_for_each(lh, &appldata_ops_list) {
@@ -516,14 +466,12 @@ static int appldata_restore(struct device *dev)
         int rc;
         struct list_head *lh;
 
-        get_online_cpus();
         spin_lock(&appldata_timer_lock);
         if (appldata_timer_suspended) {
                 __appldata_vtimer_setup(APPLDATA_ADD_TIMER);
                 appldata_timer_suspended = 0;
         }
         spin_unlock(&appldata_timer_lock);
-        put_online_cpus();
 
         mutex_lock(&appldata_ops_mutex);
         list_for_each(lh, &appldata_ops_list) {
@@ -567,53 +515,6 @@ static struct platform_driver appldata_pdrv = {
 
 /******************************* init / exit *********************************/
 
-static void __cpuinit appldata_online_cpu(int cpu)
-{
-        init_virt_timer(&per_cpu(appldata_timer, cpu));
-        per_cpu(appldata_timer, cpu).function = appldata_timer_function;
-        per_cpu(appldata_timer, cpu).data = (unsigned long)
-                &appldata_work;
-        atomic_inc(&appldata_expire_count);
-        spin_lock(&appldata_timer_lock);
-        __appldata_vtimer_setup(APPLDATA_MOD_TIMER);
-        spin_unlock(&appldata_timer_lock);
-}
-
-static void __cpuinit appldata_offline_cpu(int cpu)
-{
-        del_virt_timer(&per_cpu(appldata_timer, cpu));
-        if (atomic_dec_and_test(&appldata_expire_count)) {
-                atomic_set(&appldata_expire_count, num_online_cpus());
-                queue_work(appldata_wq, &appldata_work);
-        }
-        spin_lock(&appldata_timer_lock);
-        __appldata_vtimer_setup(APPLDATA_MOD_TIMER);
-        spin_unlock(&appldata_timer_lock);
-}
-
-static int __cpuinit appldata_cpu_notify(struct notifier_block *self,
-                                         unsigned long action,
-                                         void *hcpu)
-{
-        switch (action) {
-        case CPU_ONLINE:
-        case CPU_ONLINE_FROZEN:
-                appldata_online_cpu((long) hcpu);
-                break;
-        case CPU_DEAD:
-        case CPU_DEAD_FROZEN:
-                appldata_offline_cpu((long) hcpu);
-                break;
-        default:
-                break;
-        }
-        return NOTIFY_OK;
-}
-
-static struct notifier_block __cpuinitdata appldata_nb = {
-        .notifier_call = appldata_cpu_notify,
-};
-
 /*
  * appldata_init()
  *
@@ -621,7 +522,10 @@ static struct notifier_block __cpuinitdata appldata_nb = {
  */
 static int __init appldata_init(void)
 {
-        int i, rc;
+        int rc;
+
+        appldata_timer.function = appldata_timer_function;
+        appldata_timer.data = (unsigned long) &appldata_work;
 
         rc = platform_driver_register(&appldata_pdrv);
         if (rc)
@@ -639,14 +543,6 @@ static int __init appldata_init(void)
                 goto out_device;
         }
 
-        get_online_cpus();
-        for_each_online_cpu(i)
-                appldata_online_cpu(i);
-        put_online_cpus();
-
-        /* Register cpu hotplug notifier */
-        register_hotcpu_notifier(&appldata_nb);
-
         appldata_sysctl_header = register_sysctl_table(appldata_dir_table);
         return 0;
 
diff --git a/arch/s390/appldata/appldata_mem.c b/arch/s390/appldata/appldata_mem.c
index f7d3dc555bd..02d9a1cf505 100644
--- a/arch/s390/appldata/appldata_mem.c
+++ b/arch/s390/appldata/appldata_mem.c
@@ -1,10 +1,8 @@
 /*
- * arch/s390/appldata/appldata_mem.c
- *
  * Data gathering module for Linux-VM Monitor Stream, Stage 1.
  * Collects data related to memory management.
  *
- * Copyright (C) 2003,2006 IBM Corporation, IBM Deutschland Entwicklung GmbH.
+ * Copyright IBM Corp. 2003, 2006
  *
  * Author: Gerald Schaefer <gerald.schaefer@de.ibm.com>
  */
diff --git a/arch/s390/appldata/appldata_net_sum.c b/arch/s390/appldata/appldata_net_sum.c
index 5da7c562a90..1370e358d49 100644
--- a/arch/s390/appldata/appldata_net_sum.c
+++ b/arch/s390/appldata/appldata_net_sum.c
@@ -1,11 +1,9 @@
 /*
- * arch/s390/appldata/appldata_net_sum.c
- *
  * Data gathering module for Linux-VM Monitor Stream, Stage 1.
  * Collects accumulated network statistics (Packets received/transmitted,
  * dropped, errors, ...).
  *
- * Copyright (C) 2003,2006 IBM Corporation, IBM Deutschland Entwicklung GmbH.
+ * Copyright IBM Corp. 2003, 2006
  *
  * Author: Gerald Schaefer <gerald.schaefer@de.ibm.com>
  */
diff --git a/arch/s390/appldata/appldata_os.c b/arch/s390/appldata/appldata_os.c
index 4de031d6b76..87521ba682e 100644
--- a/arch/s390/appldata/appldata_os.c
+++ b/arch/s390/appldata/appldata_os.c
@@ -1,10 +1,8 @@
 /*
- * arch/s390/appldata/appldata_os.c
- *
  * Data gathering module for Linux-VM Monitor Stream, Stage 1.
  * Collects misc. OS related data (CPU utilization, running processes).
  *
- * Copyright (C) 2003,2006 IBM Corporation, IBM Deutschland Entwicklung GmbH.
+ * Copyright IBM Corp. 2003, 2006
  *
  * Author: Gerald Schaefer <gerald.schaefer@de.ibm.com>
  */
diff --git a/arch/s390/crypto/aes_s390.c b/arch/s390/crypto/aes_s390.c
index a9ce135893f..e402a9dd4ed 100644
--- a/arch/s390/crypto/aes_s390.c
+++ b/arch/s390/crypto/aes_s390.c
@@ -4,7 +4,7 @@
  * s390 implementation of the AES Cipher Algorithm.
  *
  * s390 Version:
- *   Copyright IBM Corp. 2005,2007
+ *   Copyright IBM Corp. 2005, 2007
  *   Author(s): Jan Glauber (jang@de.ibm.com)
  *              Sebastian Siewior (sebastian@breakpoint.cc> SW-Fallback
  *
diff --git a/arch/s390/crypto/crypt_s390.h b/arch/s390/crypto/crypt_s390.h
index 9178db6db0a..6c5cc6da711 100644
--- a/arch/s390/crypto/crypt_s390.h
+++ b/arch/s390/crypto/crypt_s390.h
@@ -3,7 +3,7 @@
  *
  * Support for s390 cryptographic instructions.
  *
- *   Copyright IBM Corp. 2003,2007
+ *   Copyright IBM Corp. 2003, 2007
  *   Author(s): Thomas Spatzier
  *              Jan Glauber (jan.glauber@de.ibm.com)
  *
diff --git a/arch/s390/crypto/crypto_des.h b/arch/s390/crypto/crypto_des.h
deleted file mode 100644
index 6210457ceeb..00000000000
--- a/arch/s390/crypto/crypto_des.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Cryptographic API.
- *
- * Function for checking keys for the DES and Tripple DES Encryption
- * algorithms.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-#ifndef __CRYPTO_DES_H__
-#define __CRYPTO_DES_H__
-
-extern int crypto_des_check_key(const u8*, unsigned int, u32*);
-
-#endif /*__CRYPTO_DES_H__*/
diff --git a/arch/s390/crypto/des_s390.c b/arch/s390/crypto/des_s390.c
index a52bfd124d8..1eaa371ca3e 100644
--- a/arch/s390/crypto/des_s390.c
+++ b/arch/s390/crypto/des_s390.c
@@ -3,7 +3,7 @@
  *
  * s390 implementation of the DES Cipher Algorithm.
  *
- * Copyright IBM Corp. 2003,2011
+ * Copyright IBM Corp. 2003, 2011
  * Author(s): Thomas Spatzier
  *            Jan Glauber (jan.glauber@de.ibm.com)
  *
diff --git a/arch/s390/crypto/prng.c b/arch/s390/crypto/prng.c
index 0808fbf0f7d..94a35a4c1b4 100644
--- a/arch/s390/crypto/prng.c
+++ b/arch/s390/crypto/prng.c
@@ -1,5 +1,5 @@
 /*
- * Copyright IBM Corp. 2006,2007
+ * Copyright IBM Corp. 2006, 2007
  * Author(s): Jan Glauber <jan.glauber@de.ibm.com>
  * Driver for the s390 pseudo random number generator
  */
diff --git a/arch/s390/crypto/sha1_s390.c b/arch/s390/crypto/sha1_s390.c
index e9868c6e0a0..a1b3a9dc9d8 100644
--- a/arch/s390/crypto/sha1_s390.c
+++ b/arch/s390/crypto/sha1_s390.c
@@ -8,7 +8,7 @@
  * implementation written by Steve Reid.
  *
  * s390 Version:
- *   Copyright IBM Corp. 2003,2007
+ *   Copyright IBM Corp. 2003, 2007
  *   Author(s): Thomas Spatzier
  *              Jan Glauber (jan.glauber@de.ibm.com)
  *
diff --git a/arch/s390/crypto/sha256_s390.c b/arch/s390/crypto/sha256_s390.c
index 0317a3547cb..9b853809a49 100644
--- a/arch/s390/crypto/sha256_s390.c
+++ b/arch/s390/crypto/sha256_s390.c
@@ -4,7 +4,7 @@
  * s390 implementation of the SHA256 and SHA224 Secure Hash Algorithm.
  *
  * s390 Version:
- *   Copyright IBM Corp. 2005,2011
+ *   Copyright IBM Corp. 2005, 2011
  *   Author(s): Jan Glauber (jang@de.ibm.com)
  *
  * This program is free software; you can redistribute it and/or modify it
diff --git a/arch/s390/defconfig b/arch/s390/defconfig
index 37d2bf26796..f39cd710980 100644
--- a/arch/s390/defconfig
+++ b/arch/s390/defconfig
@@ -7,13 +7,16 @@ CONFIG_TASK_DELAY_ACCT=y
 CONFIG_TASK_XACCT=y
 CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_RCU_FAST_NO_HZ=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_CGROUPS=y
 CONFIG_CPUSETS=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_CGROUP_MEMCG=y
 CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_RT_GROUP_SCHED=y
@@ -35,8 +38,6 @@ CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_IBM_PARTITION=y
 CONFIG_DEFAULT_DEADLINE=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_MEMORY_HOTPLUG=y
 CONFIG_MEMORY_HOTREMOVE=y
diff --git a/arch/s390/hypfs/hypfs.h b/arch/s390/hypfs/hypfs.h
index d9df5a060a8..f41e0ef7fdf 100644
--- a/arch/s390/hypfs/hypfs.h
+++ b/arch/s390/hypfs/hypfs.h
@@ -1,8 +1,7 @@
 /*
- *  arch/s390/hypfs/hypfs.h
  *    Hypervisor filesystem for Linux on s390.
  *
- *    Copyright (C) IBM Corp. 2006
+ *    Copyright IBM Corp. 2006
  *    Author(s): Michael Holzheu <holzheu@de.ibm.com>
  */
 
diff --git a/arch/s390/hypfs/hypfs_dbfs.c b/arch/s390/hypfs/hypfs_dbfs.c
index b478013b7fe..13e76dabbe8 100644
--- a/arch/s390/hypfs/hypfs_dbfs.c
+++ b/arch/s390/hypfs/hypfs_dbfs.c
@@ -1,7 +1,7 @@
 /*
  * Hypervisor filesystem for Linux on s390 - debugfs interface
  *
- * Copyright (C) IBM Corp. 2010
+ * Copyright IBM Corp. 2010
  * Author(s): Michael Holzheu <holzheu@linux.vnet.ibm.com>
  */
 
diff --git a/arch/s390/hypfs/hypfs_diag.c b/arch/s390/hypfs/hypfs_diag.c
index 74c8f5e76ce..7fd3690b676 100644
--- a/arch/s390/hypfs/hypfs_diag.c
+++ b/arch/s390/hypfs/hypfs_diag.c
@@ -1,5 +1,4 @@
 /*
- *  arch/s390/hypfs/hypfs_diag.c
  *    Hypervisor filesystem for Linux on s390. Diag 204 and 224
  *    implementation.
  *
diff --git a/arch/s390/hypfs/hypfs_vm.c b/arch/s390/hypfs/hypfs_vm.c
index e54796002f6..4f6afaa8bd8 100644
--- a/arch/s390/hypfs/hypfs_vm.c
+++ b/arch/s390/hypfs/hypfs_vm.c
@@ -1,7 +1,7 @@
 /*
  *    Hypervisor filesystem for Linux on s390. z/VM implementation.
  *
- *    Copyright (C) IBM Corp. 2006
+ *    Copyright IBM Corp. 2006
  *    Author(s): Michael Holzheu <holzheu@de.ibm.com>
  */
 
diff --git a/arch/s390/hypfs/inode.c b/arch/s390/hypfs/inode.c
index 73dae8b9b77..6767b437a10 100644
--- a/arch/s390/hypfs/inode.c
+++ b/arch/s390/hypfs/inode.c
@@ -1,5 +1,4 @@
 /*
- *  arch/s390/hypfs/inode.c
  *    Hypervisor filesystem for Linux on s390.
  *
  *    Copyright IBM Corp. 2006, 2008
@@ -103,6 +102,7 @@ static struct inode *hypfs_make_inode(struct super_block *sb, umode_t mode)
 
         if (ret) {
                 struct hypfs_sb_info *hypfs_info = sb->s_fs_info;
+                ret->i_ino = get_next_ino();
                 ret->i_mode = mode;
                 ret->i_uid = hypfs_info->uid;
                 ret->i_gid = hypfs_info->gid;
diff --git a/arch/s390/include/asm/airq.h b/arch/s390/include/asm/airq.h
index 1ac80d6b058..9819891ed7a 100644
--- a/arch/s390/include/asm/airq.h
+++ b/arch/s390/include/asm/airq.h
@@ -1,7 +1,5 @@
 /*
- *  include/asm-s390/airq.h
- *
- *    Copyright IBM Corp. 2002,2007
+ *    Copyright IBM Corp. 2002, 2007
  *    Author(s): Ingo Adlung <adlung@de.ibm.com>
  *               Cornelia Huck <cornelia.huck@de.ibm.com>
  *               Arnd Bergmann <arndb@de.ibm.com>
diff --git a/arch/s390/include/asm/appldata.h b/arch/s390/include/asm/appldata.h
index 79283dac828..f328294faea 100644
--- a/arch/s390/include/asm/appldata.h
+++ b/arch/s390/include/asm/appldata.h
@@ -1,7 +1,5 @@
 /*
- * include/asm-s390/appldata.h
- *
- * Copyright (C) IBM Corp. 2006
+ * Copyright IBM Corp. 2006
  *
  * Author(s): Melissa Howland <melissah@us.ibm.com>
  */
diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h
index 748347baecb..c797832daa5 100644
--- a/arch/s390/include/asm/atomic.h
+++ b/arch/s390/include/asm/atomic.h
@@ -1,8 +1,5 @@
-#ifndef __ARCH_S390_ATOMIC__
-#define __ARCH_S390_ATOMIC__
-
 /*
- * Copyright 1999,2009 IBM Corp.
+ * Copyright IBM Corp. 1999, 2009
  * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *            Denis Joseph Barrow,
  *            Arnd Bergmann <arndb@de.ibm.com>,
@@ -13,6 +10,9 @@
  *
  */
 
+#ifndef __ARCH_S390_ATOMIC__
+#define __ARCH_S390_ATOMIC__
+
 #include <linux/compiler.h>
 #include <linux/types.h>
 #include <asm/cmpxchg.h>
diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h
index a6ff5a83e22..6f573890fb2 100644
--- a/arch/s390/include/asm/bitops.h
+++ b/arch/s390/include/asm/bitops.h
@@ -1,11 +1,6 @@
-#ifndef _S390_BITOPS_H
-#define _S390_BITOPS_H
-
 /*
- *  include/asm-s390/bitops.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
  *  Derived from "include/asm-i386/bitops.h"
@@ -13,6 +8,9 @@
  *
  */
 
+#ifndef _S390_BITOPS_H
+#define _S390_BITOPS_H
+
 #ifndef _LINUX_BITOPS_H
 #error only <linux/bitops.h> can be included directly
 #endif
diff --git a/arch/s390/include/asm/bugs.h b/arch/s390/include/asm/bugs.h
index 011f1e6a2a6..0f5bd894f4d 100644
--- a/arch/s390/include/asm/bugs.h
+++ b/arch/s390/include/asm/bugs.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/bugs.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
  *  Derived from "include/asm-i386/bugs.h"
diff --git a/arch/s390/include/asm/cache.h b/arch/s390/include/asm/cache.h
index 2a30d5ac066..4d7ccac5fd1 100644
--- a/arch/s390/include/asm/cache.h
+++ b/arch/s390/include/asm/cache.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/cache.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *
  *  Derived from "include/asm-i386/cache.h"
  *    Copyright (C) 1992, Linus Torvalds
diff --git a/arch/s390/include/asm/ccwdev.h b/arch/s390/include/asm/ccwdev.h
index 9381c92cc77..1cb4bb3f32d 100644
--- a/arch/s390/include/asm/ccwdev.h
+++ b/arch/s390/include/asm/ccwdev.h
@@ -1,5 +1,5 @@
 /*
- * Copyright  IBM Corp. 2002, 2009
+ * Copyright IBM Corp. 2002, 2009
  *
  * Author(s): Arnd Bergmann <arndb@de.ibm.com>
  *
diff --git a/arch/s390/include/asm/ccwgroup.h b/arch/s390/include/asm/ccwgroup.h
index f2ef34f6d6e..01a905eb11e 100644
--- a/arch/s390/include/asm/ccwgroup.h
+++ b/arch/s390/include/asm/ccwgroup.h
@@ -6,14 +6,12 @@ struct ccw_driver;
 
 /**
  * struct ccwgroup_device - ccw group device
- * @creator_id: unique number of the driver
  * @state: online/offline state
  * @count: number of attached slave devices
  * @dev: embedded device structure
  * @cdev: variable number of slave devices, allocated as needed
  */
 struct ccwgroup_device {
-        unsigned long creator_id;
         enum {
                 CCWGROUP_OFFLINE,
                 CCWGROUP_ONLINE,
diff --git a/arch/s390/include/asm/checksum.h b/arch/s390/include/asm/checksum.h
index 6c00f6800a3..4f57a4f3909 100644
--- a/arch/s390/include/asm/checksum.h
+++ b/arch/s390/include/asm/checksum.h
@@ -1,18 +1,16 @@
-#ifndef _S390_CHECKSUM_H
-#define _S390_CHECKSUM_H
-
 /*
- *  include/asm-s390/checksum.h
  *    S390 fast network checksum routines
- *    see also arch/S390/lib/checksum.c
  *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Ulrich Hild        (first version)
  *               Martin Schwidefsky (heavily optimized CKSM version)
  *               D.J. Barrow        (third attempt) 
  */
 
+#ifndef _S390_CHECKSUM_H
+#define _S390_CHECKSUM_H
+
 #include <asm/uaccess.h>
 
 /*
diff --git a/arch/s390/include/asm/chpid.h b/arch/s390/include/asm/chpid.h
index 8e88e222177..e5bde9f9291 100644
--- a/arch/s390/include/asm/chpid.h
+++ b/arch/s390/include/asm/chpid.h
@@ -1,6 +1,4 @@
 /*
- *  drivers/s390/cio/chpid.h
- *
  *    Copyright IBM Corp. 2007
  *    Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
  */
diff --git a/arch/s390/include/asm/chsc.h b/arch/s390/include/asm/chsc.h
index 4943654ed7f..bf115b49f44 100644
--- a/arch/s390/include/asm/chsc.h
+++ b/arch/s390/include/asm/chsc.h
@@ -1,7 +1,7 @@
 /*
  * ioctl interface for /dev/chsc
  *
- * Copyright 2008 IBM Corp.
+ * Copyright IBM Corp. 2008
  * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
  */
 
diff --git a/arch/s390/include/asm/cio.h b/arch/s390/include/asm/cio.h
index 4c8d4d5b8bd..77043aa44d6 100644
--- a/arch/s390/include/asm/cio.h
+++ b/arch/s390/include/asm/cio.h
@@ -1,7 +1,4 @@
 /*
- *  include/asm-s390/cio.h
- *  include/asm-s390x/cio.h
- *
  * Common interface for I/O on S/390
  */
 #ifndef _ASM_S390_CIO_H_
diff --git a/arch/s390/include/asm/cpcmd.h b/arch/s390/include/asm/cpcmd.h
index 48a9eab1642..3dfadb5d648 100644
--- a/arch/s390/include/asm/cpcmd.h
+++ b/arch/s390/include/asm/cpcmd.h
@@ -1,8 +1,6 @@
 /*
- *  arch/s390/kernel/cpcmd.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Christian Borntraeger (cborntra@de.ibm.com),
  */
diff --git a/arch/s390/include/asm/cpu.h b/arch/s390/include/asm/cpu.h
index e0b69540216..f5a8e2fcde0 100644
--- a/arch/s390/include/asm/cpu.h
+++ b/arch/s390/include/asm/cpu.h
@@ -1,5 +1,5 @@
 /*
- *    Copyright IBM Corp. 2000,2009
+ *    Copyright IBM Corp. 2000, 2009
  *    Author(s): Hartmut Penner <hp@de.ibm.com>,
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Christian Ehrhardt <ehrhardt@de.ibm.com>,
diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h
index 718374de9c7..8709bdef233 100644
--- a/arch/s390/include/asm/cputime.h
+++ b/arch/s390/include/asm/cputime.h
@@ -1,7 +1,5 @@
 /*
- *  include/asm-s390/cputime.h
- *
- *  (C) Copyright IBM Corp. 2004
+ *  Copyright IBM Corp. 2004
  *
  *  Author: Martin Schwidefsky <schwidefsky@de.ibm.com>
  */
@@ -167,12 +165,14 @@ static inline clock_t cputime64_to_clock_t(cputime64_t cputime)
 }
 
 struct s390_idle_data {
+        int nohz_delay;
         unsigned int sequence;
         unsigned long long idle_count;
-        unsigned long long idle_enter;
-        unsigned long long idle_exit;
         unsigned long long idle_time;
-        int nohz_delay;
+        unsigned long long clock_idle_enter;
+        unsigned long long clock_idle_exit;
+        unsigned long long timer_idle_enter;
+        unsigned long long timer_idle_exit;
 };
 
 DECLARE_PER_CPU(struct s390_idle_data, s390_idle);
diff --git a/arch/s390/include/asm/crw.h b/arch/s390/include/asm/crw.h
index 749a97e61be..7c31d3e25cd 100644
--- a/arch/s390/include/asm/crw.h
+++ b/arch/s390/include/asm/crw.h
@@ -1,6 +1,6 @@
 /*
  *   Data definitions for channel report processing
- *    Copyright IBM Corp. 2000,2009
+ *    Copyright IBM Corp. 2000, 2009
  *    Author(s): Ingo Adlung <adlung@de.ibm.com>,
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Cornelia Huck <cornelia.huck@de.ibm.com>,
diff --git a/arch/s390/include/asm/current.h b/arch/s390/include/asm/current.h
index 7a68084ec2f..b80941f30df 100644
--- a/arch/s390/include/asm/current.h
+++ b/arch/s390/include/asm/current.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/current.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
  *  Derived from "include/asm-i386/current.h"
diff --git a/arch/s390/include/asm/dasd.h b/arch/s390/include/asm/dasd.h
index 0be28efe5b6..38eca3ba40e 100644
--- a/arch/s390/include/asm/dasd.h
+++ b/arch/s390/include/asm/dasd.h
@@ -1,8 +1,7 @@
 /* 
- * File...........: linux/drivers/s390/block/dasd.c
  * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
  * Bugreports.to..: <Linux390@de.ibm.com>
- * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 1999,2000
+ * Copyright IBM Corp. 1999, 2000
  * EMC Symmetrix ioctl Copyright EMC Corporation, 2008
  * Author.........: Nigel Hislop <hislop_nigel@emc.com>
  *
diff --git a/arch/s390/include/asm/debug.h b/arch/s390/include/asm/debug.h
index 8a8245ed14d..f39677e6ccd 100644
--- a/arch/s390/include/asm/debug.h
+++ b/arch/s390/include/asm/debug.h
@@ -1,9 +1,7 @@
 /*
- *  include/asm-s390/debug.h
  *   S/390 debug facility
  *
- *    Copyright (C) 1999, 2000 IBM Deutschland Entwicklung GmbH,
- *                             IBM Corporation
+ *    Copyright IBM Corp. 1999, 2000
  */
 
 #ifndef DEBUG_H
diff --git a/arch/s390/include/asm/delay.h b/arch/s390/include/asm/delay.h
index 0e3b35f96be..3f6e4095f47 100644
--- a/arch/s390/include/asm/delay.h
+++ b/arch/s390/include/asm/delay.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/delay.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
  *  Derived from "include/asm-i386/delay.h"
diff --git a/arch/s390/include/asm/dma.h b/arch/s390/include/asm/dma.h
index 7425c6af6cd..6fb6de4f15b 100644
--- a/arch/s390/include/asm/dma.h
+++ b/arch/s390/include/asm/dma.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/dma.h
- *
  *  S390 version
  */
 
diff --git a/arch/s390/include/asm/ebcdic.h b/arch/s390/include/asm/ebcdic.h
index 7f6f641d32f..c5befc5a3bf 100644
--- a/arch/s390/include/asm/ebcdic.h
+++ b/arch/s390/include/asm/ebcdic.h
@@ -1,9 +1,8 @@
 /*
- *  include/asm-s390/ebcdic.h
  *    EBCDIC -> ASCII, ASCII -> EBCDIC conversion routines.
  *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
  */
 
diff --git a/arch/s390/include/asm/elf.h b/arch/s390/include/asm/elf.h
index 06151e6a309..9b94a160fe7 100644
--- a/arch/s390/include/asm/elf.h
+++ b/arch/s390/include/asm/elf.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/elf.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/elf.h"
@@ -182,7 +180,8 @@ extern char elf_platform[];
 #define ELF_PLATFORM (elf_platform)
 
 #ifndef CONFIG_64BIT
-#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) \
+        set_personality(PER_LINUX | (current->personality & (~PER_MASK)))
 #else /* CONFIG_64BIT */
 #define SET_PERSONALITY(ex)                                     \
 do {                                                            \
diff --git a/arch/s390/include/asm/errno.h b/arch/s390/include/asm/errno.h
index e41d5b37c4d..395e97d8005 100644
--- a/arch/s390/include/asm/errno.h
+++ b/arch/s390/include/asm/errno.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/errno.h
- *
  *  S390 version
  *
  */
diff --git a/arch/s390/include/asm/etr.h b/arch/s390/include/asm/etr.h
index 538e1b36a72..a24b03b9fb6 100644
--- a/arch/s390/include/asm/etr.h
+++ b/arch/s390/include/asm/etr.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/etr.h
- *
  *  Copyright IBM Corp. 2006
  *  Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  */
diff --git a/arch/s390/include/asm/extmem.h b/arch/s390/include/asm/extmem.h
index 33837d75618..6276002d76b 100644
--- a/arch/s390/include/asm/extmem.h
+++ b/arch/s390/include/asm/extmem.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390x/extmem.h
- *
  *  definitions for external memory segment support
- *  Copyright (C) 2003 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *  Copyright IBM Corp. 2003
  */
 
 #ifndef _ASM_S390X_DCSS_H
diff --git a/arch/s390/include/asm/hardirq.h b/arch/s390/include/asm/hardirq.h
index 510ba9ef424..0c82ba86e99 100644
--- a/arch/s390/include/asm/hardirq.h
+++ b/arch/s390/include/asm/hardirq.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/hardirq.h
- *
  *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2000
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
  *
diff --git a/arch/s390/include/asm/idals.h b/arch/s390/include/asm/idals.h
index aef0dde340d..ea5a6e45fd9 100644
--- a/arch/s390/include/asm/idals.h
+++ b/arch/s390/include/asm/idals.h
@@ -1,10 +1,9 @@
 /* 
- * File...........: linux/include/asm-s390x/idals.h
  * Author(s)......: Holger Smolinski <Holger.Smolinski@de.ibm.com>
  *                  Martin Schwidefsky <schwidefsky@de.ibm.com>
  * Bugreports.to..: <Linux390@de.ibm.com>
- * (C) IBM Corporation, IBM Deutschland Entwicklung GmbH, 2000a
- 
+ * Copyright IBM Corp. 2000
+ *
  * History of changes
  * 07/24/00 new file
  * 05/04/02 code restructuring.
diff --git a/arch/s390/include/asm/io.h b/arch/s390/include/asm/io.h
index f81a0975cbe..559e921a6bb 100644
--- a/arch/s390/include/asm/io.h
+++ b/arch/s390/include/asm/io.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/io.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
  *  Derived from "include/asm-i386/io.h"
diff --git a/arch/s390/include/asm/irqflags.h b/arch/s390/include/asm/irqflags.h
index 38fdf451feb..37b9091ab8c 100644
--- a/arch/s390/include/asm/irqflags.h
+++ b/arch/s390/include/asm/irqflags.h
@@ -1,5 +1,5 @@
 /*
- *    Copyright IBM Corp. 2006,2010
+ *    Copyright IBM Corp. 2006, 2010
  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
  */
 
diff --git a/arch/s390/include/asm/kexec.h b/arch/s390/include/asm/kexec.h
index f4f38826eeb..694bcd6bd92 100644
--- a/arch/s390/include/asm/kexec.h
+++ b/arch/s390/include/asm/kexec.h
@@ -1,7 +1,5 @@
 /*
- * include/asm-s390/kexec.h
- *
- * (C) Copyright IBM Corp. 2005
+ * Copyright IBM Corp. 2005
  *
  * Author(s): Rolf Adelsberger <adelsberger@de.ibm.com>
  *
diff --git a/arch/s390/include/asm/kprobes.h b/arch/s390/include/asm/kprobes.h
index a231a9439c4..dcf6948a875 100644
--- a/arch/s390/include/asm/kprobes.h
+++ b/arch/s390/include/asm/kprobes.h
@@ -17,7 +17,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  *
- * Copyright (C) IBM Corporation, 2002, 2006
+ * Copyright IBM Corp. 2002, 2006
  *
  * 2002-Oct     Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
  *              Probes initial implementation ( includes suggestions from
diff --git a/arch/s390/include/asm/kvm.h b/arch/s390/include/asm/kvm.h
index bdcbe0f8dd7..d25da598ec6 100644
--- a/arch/s390/include/asm/kvm.h
+++ b/arch/s390/include/asm/kvm.h
@@ -1,7 +1,7 @@
 #ifndef __LINUX_KVM_S390_H
 #define __LINUX_KVM_S390_H
 /*
- * asm-s390/kvm.h - KVM s390 specific structures and definitions
+ * KVM s390 specific structures and definitions
  *
  * Copyright IBM Corp. 2008
  *
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
index dd17537b9a9..b7841546991 100644
--- a/arch/s390/include/asm/kvm_host.h
+++ b/arch/s390/include/asm/kvm_host.h
@@ -1,7 +1,7 @@
 /*
- * asm-s390/kvm_host.h - definition for kernel virtual machines on s390
+ * definition for kernel virtual machines on s390
  *
- * Copyright IBM Corp. 2008,2009
+ * Copyright IBM Corp. 2008, 2009
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License (version 2 only)
diff --git a/arch/s390/include/asm/kvm_para.h b/arch/s390/include/asm/kvm_para.h
index a9883296103..da44867de60 100644
--- a/arch/s390/include/asm/kvm_para.h
+++ b/arch/s390/include/asm/kvm_para.h
@@ -1,5 +1,5 @@
 /*
- * asm-s390/kvm_para.h - definition for paravirtual devices on s390
+ * definition for paravirtual devices on s390
  *
  * Copyright IBM Corp. 2008
  *
diff --git a/arch/s390/include/asm/kvm_virtio.h b/arch/s390/include/asm/kvm_virtio.h
index 72f614181ef..44a438ca9e7 100644
--- a/arch/s390/include/asm/kvm_virtio.h
+++ b/arch/s390/include/asm/kvm_virtio.h
@@ -1,5 +1,5 @@
 /*
- * kvm_virtio.h - definition for virtio for kvm on s390
+ * definition for virtio for kvm on s390
  *
  * Copyright IBM Corp. 2008
  *
diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h
index 47853debb3b..aab5555bbbd 100644
--- a/arch/s390/include/asm/lowcore.h
+++ b/arch/s390/include/asm/lowcore.h
@@ -1,5 +1,5 @@
 /*
- *    Copyright IBM Corp. 1999,2012
+ *    Copyright IBM Corp. 1999, 2012
  *    Author(s): Hartmut Penner <hp@de.ibm.com>,
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Denis Joseph Barrow,
@@ -302,12 +302,7 @@ struct _lowcore {
          */
         __u64   ipib;                           /* 0x0e00 */
         __u32   ipib_checksum;                  /* 0x0e08 */
-        /*
-         * Because the vmcore_info pointer is not 8 byte aligned it never
-         * should not be accessed directly. For accessing the pointer, first
-         * copy it to a local pointer variable.
-         */
-        __u8    vmcore_info[8];                 /* 0x0e0c */
+        __u64   vmcore_info;                    /* 0x0e0c */
         __u8    pad_0x0e14[0x0e18-0x0e14];      /* 0x0e14 */
         __u64   os_info;                        /* 0x0e18 */
         __u8    pad_0x0e20[0x0f00-0x0e20];      /* 0x0e20 */
diff --git a/arch/s390/include/asm/mathemu.h b/arch/s390/include/asm/mathemu.h
index e8dd1ba8edb..614dfaf47f7 100644
--- a/arch/s390/include/asm/mathemu.h
+++ b/arch/s390/include/asm/mathemu.h
@@ -1,9 +1,8 @@
 /*
- *  arch/s390/kernel/mathemu.h
  *    IEEE floating point emulation.
  *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  */
 
diff --git a/arch/s390/include/asm/mman.h b/arch/s390/include/asm/mman.h
index d49760e6350..abc1932ac4e 100644
--- a/arch/s390/include/asm/mman.h
+++ b/arch/s390/include/asm/mman.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/mman.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/mman.h"
diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h
index 69bdf72e95e..b749c573365 100644
--- a/arch/s390/include/asm/mmu_context.h
+++ b/arch/s390/include/asm/mmu_context.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/mmu_context.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/mmu_context.h"
@@ -13,7 +11,6 @@
 #include <asm/uaccess.h>
 #include <asm/tlbflush.h>
 #include <asm/ctl_reg.h>
-#include <asm-generic/mm_hooks.h>
 
 static inline int init_new_context(struct task_struct *tsk,
                                    struct mm_struct *mm)
@@ -60,7 +57,7 @@ static inline void update_mm(struct mm_struct *mm, struct task_struct *tsk)
         pgd_t *pgd = mm->pgd;
 
         S390_lowcore.user_asce = mm->context.asce_bits | __pa(pgd);
-        if (user_mode != HOME_SPACE_MODE) {
+        if (addressing_mode != HOME_SPACE_MODE) {
                 /* Load primary space page table origin. */
                 asm volatile(LCTL_OPCODE" 1,1,%0\n"
                              : : "m" (S390_lowcore.user_asce) );
@@ -93,4 +90,17 @@ static inline void activate_mm(struct mm_struct *prev,
         switch_mm(prev, next, current);
 }
 
+static inline void arch_dup_mmap(struct mm_struct *oldmm,
+                                 struct mm_struct *mm)
+{
+#ifdef CONFIG_64BIT
+        if (oldmm->context.asce_limit < mm->context.asce_limit)
+                crst_table_downgrade(mm, oldmm->context.asce_limit);
+#endif
+}
+
+static inline void arch_exit_mmap(struct mm_struct *mm)
+{
+}
+
 #endif /* __S390_MMU_CONTEXT_H */
diff --git a/arch/s390/include/asm/monwriter.h b/arch/s390/include/asm/monwriter.h
index f0cbf96c52e..f845c8e2f86 100644
--- a/arch/s390/include/asm/monwriter.h
+++ b/arch/s390/include/asm/monwriter.h
@@ -1,7 +1,5 @@
 /*
- * include/asm-s390/monwriter.h
- *
- * Copyright (C) IBM Corp. 2006
+ * Copyright IBM Corp. 2006
  * Character device driver for writing z/VM APPLDATA monitor records
  * Version 1.0
  * Author(s): Melissa Howland <melissah@us.ibm.com>
diff --git a/arch/s390/include/asm/nmi.h b/arch/s390/include/asm/nmi.h
index f4b60441adc..35f8ec18561 100644
--- a/arch/s390/include/asm/nmi.h
+++ b/arch/s390/include/asm/nmi.h
@@ -1,7 +1,7 @@
 /*
  *   Machine check handler definitions
  *
- *    Copyright IBM Corp. 2000,2009
+ *    Copyright IBM Corp. 2000, 2009
  *    Author(s): Ingo Adlung <adlung@de.ibm.com>,
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Cornelia Huck <cornelia.huck@de.ibm.com>,
diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h
index f7ec548c2b9..27ab3c7c1e8 100644
--- a/arch/s390/include/asm/page.h
+++ b/arch/s390/include/asm/page.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/page.h
- *
  *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2000
  *    Author(s): Hartmut Penner (hp@de.ibm.com)
  */
 
diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h
index 43078c19439..590c3219c63 100644
--- a/arch/s390/include/asm/pgalloc.h
+++ b/arch/s390/include/asm/pgalloc.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/pgalloc.h
- *
  *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2000
  *    Author(s): Hartmut Penner (hp@de.ibm.com)
  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index b3227415abd..6bd7d748301 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/pgtable.h
- *
  *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2000
  *    Author(s): Hartmut Penner (hp@de.ibm.com)
  *               Ulrich Weigand (weigand@de.ibm.com)
  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
diff --git a/arch/s390/include/asm/posix_types.h b/arch/s390/include/asm/posix_types.h
index 7be104c0f19..bf2a2ad2f80 100644
--- a/arch/s390/include/asm/posix_types.h
+++ b/arch/s390/include/asm/posix_types.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/posix_types.h
- *
  *  S390 version
  *
  */
@@ -15,6 +13,7 @@
  */
 
 typedef unsigned long   __kernel_size_t;
+typedef long            __kernel_ssize_t;
 #define __kernel_size_t __kernel_size_t
 
 typedef unsigned short  __kernel_old_dev_t;
@@ -27,7 +26,6 @@ typedef unsigned short  __kernel_mode_t;
 typedef unsigned short  __kernel_ipc_pid_t;
 typedef unsigned short  __kernel_uid_t;
 typedef unsigned short  __kernel_gid_t;
-typedef int             __kernel_ssize_t;
 typedef int             __kernel_ptrdiff_t;
 
 #else /* __s390x__ */
@@ -37,7 +35,6 @@ typedef unsigned int    __kernel_mode_t;
 typedef int             __kernel_ipc_pid_t;
 typedef unsigned int    __kernel_uid_t;
 typedef unsigned int    __kernel_gid_t;
-typedef long            __kernel_ssize_t;
 typedef long            __kernel_ptrdiff_t;
 typedef unsigned long   __kernel_sigset_t;      /* at least 32 bits */
 
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
index 20d0585cf90..11e4e323693 100644
--- a/arch/s390/include/asm/processor.h
+++ b/arch/s390/include/asm/processor.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/processor.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Hartmut Penner (hp@de.ibm.com),
  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
@@ -122,7 +120,9 @@ struct stack_frame {
         regs->psw.mask  = psw_user_bits | PSW_MASK_BA;                  \
         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
         regs->gprs[15]  = new_stackp;                                   \
+        __tlb_flush_mm(current->mm);                                    \
         crst_table_downgrade(current->mm, 1UL << 31);                   \
+        update_mm(current->mm, current);                                \
 } while (0)
 
 /* Forward declaration, a strange C thing */
@@ -348,4 +348,14 @@ extern void (*s390_base_ext_handler_fn)(void);
         ".previous\n"
 #endif
 
+extern int memcpy_real(void *, void *, size_t);
+extern void memcpy_absolute(void *, void *, size_t);
+
+#define mem_assign_absolute(dest, val) {                        \
+        __typeof__(dest) __tmp = (val);                         \
+                                                                \
+        BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));             \
+        memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));        \
+}
+
 #endif                                 /* __ASM_S390_PROCESSOR_H           */
diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h
index aeb77f01798..d5f08ea566e 100644
--- a/arch/s390/include/asm/ptrace.h
+++ b/arch/s390/include/asm/ptrace.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/ptrace.h
- *
  *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2000
  *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
  */
 
diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h
index f039d86adf6..57d0d7e794b 100644
--- a/arch/s390/include/asm/qdio.h
+++ b/arch/s390/include/asm/qdio.h
@@ -1,7 +1,5 @@
 /*
- * linux/include/asm-s390/qdio.h
- *
- * Copyright 2000,2008 IBM Corp.
+ * Copyright IBM Corp. 2000, 2008
  * Author(s): Utz Bacher <utz.bacher@de.ibm.com>
  *            Jan Glauber <jang@linux.vnet.ibm.com>
  *
diff --git a/arch/s390/include/asm/qeth.h b/arch/s390/include/asm/qeth.h
index 2c7c898c03e..3a896cf5258 100644
--- a/arch/s390/include/asm/qeth.h
+++ b/arch/s390/include/asm/qeth.h
@@ -1,9 +1,7 @@
 /*
- * include/asm-s390/qeth.h
- *
  * ioctl definitions for qeth driver
  *
- * Copyright (C) 2004 IBM Corporation
+ * Copyright IBM Corp. 2004
  *
  * Author(s):   Thomas Spatzier <tspat@de.ibm.com>
  *
diff --git a/arch/s390/include/asm/reset.h b/arch/s390/include/asm/reset.h
index 3d6ad4ad2a3..804578587a7 100644
--- a/arch/s390/include/asm/reset.h
+++ b/arch/s390/include/asm/reset.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/reset.h
- *
  *    Copyright IBM Corp. 2006
  *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
  */
diff --git a/arch/s390/include/asm/resource.h b/arch/s390/include/asm/resource.h
index 366c01de04f..ec23d1c73c9 100644
--- a/arch/s390/include/asm/resource.h
+++ b/arch/s390/include/asm/resource.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/resource.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/resources.h"
diff --git a/arch/s390/include/asm/rwsem.h b/arch/s390/include/asm/rwsem.h
index 1ceee10264c..487f9b64efb 100644
--- a/arch/s390/include/asm/rwsem.h
+++ b/arch/s390/include/asm/rwsem.h
@@ -2,10 +2,8 @@
 #define _S390_RWSEM_H
 
 /*
- *  include/asm-s390/rwsem.h
- *
  *  S390 version
- *    Copyright (C) 2002 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 2002
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
  *  Based on asm-alpha/semaphore.h and asm-i386/rwsem.h
diff --git a/arch/s390/include/asm/sclp.h b/arch/s390/include/asm/sclp.h
index bf238c55740..e62a555557e 100644
--- a/arch/s390/include/asm/sclp.h
+++ b/arch/s390/include/asm/sclp.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/sclp.h
- *
  *    Copyright IBM Corp. 2007
  *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
  */
@@ -55,5 +53,7 @@ int sclp_chp_configure(struct chp_id chpid);
 int sclp_chp_deconfigure(struct chp_id chpid);
 int sclp_chp_read_info(struct sclp_chp_info *info);
 void sclp_get_ipl_info(struct sclp_ipl_info *info);
+bool sclp_has_linemode(void);
+bool sclp_has_vt220(void);
 
 #endif /* _ASM_S390_SCLP_H */
diff --git a/arch/s390/include/asm/scsw.h b/arch/s390/include/asm/scsw.h
index de389cb54d2..4071d00978c 100644
--- a/arch/s390/include/asm/scsw.h
+++ b/arch/s390/include/asm/scsw.h
@@ -1,7 +1,7 @@
 /*
  *  Helper functions for scsw access.
  *
- *    Copyright IBM Corp. 2008,2009
+ *    Copyright IBM Corp. 2008, 2009
  *    Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
  */
 
diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h
index 40eb2ff88e9..e6859d16ee2 100644
--- a/arch/s390/include/asm/setup.h
+++ b/arch/s390/include/asm/setup.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/setup.h
- *
  *  S390 version
- *    Copyright IBM Corp. 1999,2010
+ *    Copyright IBM Corp. 1999, 2010
  */
 
 #ifndef _ASM_S390_SETUP_H
@@ -62,7 +60,7 @@ void create_mem_hole(struct mem_chunk memory_chunk[], unsigned long addr,
 #define SECONDARY_SPACE_MODE    2
 #define HOME_SPACE_MODE         3
 
-extern unsigned int user_mode;
+extern unsigned int addressing_mode;
 
 /*
  * Machine features detected in head.S
diff --git a/arch/s390/include/asm/shmparam.h b/arch/s390/include/asm/shmparam.h
index c2e0c0508e7..e985182738f 100644
--- a/arch/s390/include/asm/shmparam.h
+++ b/arch/s390/include/asm/shmparam.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/shmparam.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/shmparam.h"
diff --git a/arch/s390/include/asm/sigcontext.h b/arch/s390/include/asm/sigcontext.h
index aeb6e0b1332..584787f6ce4 100644
--- a/arch/s390/include/asm/sigcontext.h
+++ b/arch/s390/include/asm/sigcontext.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/sigcontext.h
- *
  *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2000
  */
 
 #ifndef _ASM_S390_SIGCONTEXT_H
diff --git a/arch/s390/include/asm/siginfo.h b/arch/s390/include/asm/siginfo.h
index e0ff1ab054b..91fd3e4b70c 100644
--- a/arch/s390/include/asm/siginfo.h
+++ b/arch/s390/include/asm/siginfo.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/siginfo.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/siginfo.h"
diff --git a/arch/s390/include/asm/signal.h b/arch/s390/include/asm/signal.h
index cdf5cb2fe03..6d4d9d1faee 100644
--- a/arch/s390/include/asm/signal.h
+++ b/arch/s390/include/asm/signal.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/signal.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/signal.h"
diff --git a/arch/s390/include/asm/sigp.h b/arch/s390/include/asm/sigp.h
new file mode 100644
index 00000000000..5a87d16d3e7
--- /dev/null
+++ b/arch/s390/include/asm/sigp.h
@@ -0,0 +1,32 @@
+#ifndef __S390_ASM_SIGP_H
+#define __S390_ASM_SIGP_H
+
+/* SIGP order codes */
+#define SIGP_SENSE                    1
+#define SIGP_EXTERNAL_CALL            2
+#define SIGP_EMERGENCY_SIGNAL         3
+#define SIGP_STOP                     5
+#define SIGP_RESTART                  6
+#define SIGP_STOP_AND_STORE_STATUS    9
+#define SIGP_INITIAL_CPU_RESET       11
+#define SIGP_SET_PREFIX              13
+#define SIGP_STORE_STATUS_AT_ADDRESS 14
+#define SIGP_SET_ARCHITECTURE        18
+#define SIGP_SENSE_RUNNING           21
+
+/* SIGP condition codes */
+#define SIGP_CC_ORDER_CODE_ACCEPTED 0
+#define SIGP_CC_STATUS_STORED       1
+#define SIGP_CC_BUSY                2
+#define SIGP_CC_NOT_OPERATIONAL     3
+
+/* SIGP cpu status bits */
+
+#define SIGP_STATUS_CHECK_STOP          0x00000010UL
+#define SIGP_STATUS_STOPPED             0x00000040UL
+#define SIGP_STATUS_EXT_CALL_PENDING    0x00000080UL
+#define SIGP_STATUS_INVALID_PARAMETER   0x00000100UL
+#define SIGP_STATUS_INCORRECT_STATE     0x00000200UL
+#define SIGP_STATUS_NOT_RUNNING         0x00000400UL
+
+#endif /* __S390_ASM_SIGP_H */
diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h
index 0b6f586c138..ce26ac3cb16 100644
--- a/arch/s390/include/asm/smp.h
+++ b/arch/s390/include/asm/smp.h
@@ -1,5 +1,5 @@
 /*
- *    Copyright IBM Corp. 1999,2012
+ *    Copyright IBM Corp. 1999, 2012
  *    Author(s): Denis Joseph Barrow,
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Heiko Carstens <heiko.carstens@de.ibm.com>,
@@ -44,6 +44,7 @@ static inline void smp_call_online_cpu(void (*func)(void *), void *data)
 }
 
 static inline int smp_find_processor_id(int address) { return 0; }
+static inline int smp_store_status(int cpu) { return 0; }
 static inline int smp_vcpu_scheduled(int cpu) { return 1; }
 static inline void smp_yield_cpu(int cpu) { }
 static inline void smp_yield(void) { }
diff --git a/arch/s390/include/asm/socket.h b/arch/s390/include/asm/socket.h
index c91b720965c..69718cd6d63 100644
--- a/arch/s390/include/asm/socket.h
+++ b/arch/s390/include/asm/socket.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/socket.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/socket.h"
diff --git a/arch/s390/include/asm/sparsemem.h b/arch/s390/include/asm/sparsemem.h
index 0fb34027d3f..a60d085ddb4 100644
--- a/arch/s390/include/asm/sparsemem.h
+++ b/arch/s390/include/asm/sparsemem.h
@@ -4,13 +4,11 @@
 #ifdef CONFIG_64BIT
 
 #define SECTION_SIZE_BITS       28
-#define MAX_PHYSADDR_BITS       46
 #define MAX_PHYSMEM_BITS        46
 
 #else
 
 #define SECTION_SIZE_BITS       25
-#define MAX_PHYSADDR_BITS       31
 #define MAX_PHYSMEM_BITS        31
 
 #endif /* CONFIG_64BIT */
diff --git a/arch/s390/include/asm/spinlock.h b/arch/s390/include/asm/spinlock.h
index fd94dfec8d0..701fe8c59e1 100644
--- a/arch/s390/include/asm/spinlock.h
+++ b/arch/s390/include/asm/spinlock.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/spinlock.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
  *  Derived from "include/asm-i386/spinlock.h"
diff --git a/arch/s390/include/asm/stat.h b/arch/s390/include/asm/stat.h
index d92959eebb6..b4ca97d9146 100644
--- a/arch/s390/include/asm/stat.h
+++ b/arch/s390/include/asm/stat.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/stat.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/stat.h"
diff --git a/arch/s390/include/asm/statfs.h b/arch/s390/include/asm/statfs.h
index 3be7fbd406c..5acca0a34c2 100644
--- a/arch/s390/include/asm/statfs.h
+++ b/arch/s390/include/asm/statfs.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/statfs.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/statfs.h"
diff --git a/arch/s390/include/asm/string.h b/arch/s390/include/asm/string.h
index 8cc160c9e1c..1bd1352fa3b 100644
--- a/arch/s390/include/asm/string.h
+++ b/arch/s390/include/asm/string.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/string.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  */
 
diff --git a/arch/s390/include/asm/swab.h b/arch/s390/include/asm/swab.h
index a3e4ebb3209..da3bfe5cc16 100644
--- a/arch/s390/include/asm/swab.h
+++ b/arch/s390/include/asm/swab.h
@@ -2,10 +2,8 @@
 #define _S390_SWAB_H
 
 /*
- *  include/asm-s390/swab.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  */
 
diff --git a/arch/s390/include/asm/syscall.h b/arch/s390/include/asm/syscall.h
index fb214dd9b7e..fe7b99759e1 100644
--- a/arch/s390/include/asm/syscall.h
+++ b/arch/s390/include/asm/syscall.h
@@ -12,6 +12,7 @@
 #ifndef _ASM_SYSCALL_H
 #define _ASM_SYSCALL_H  1
 
+#include <linux/audit.h>
 #include <linux/sched.h>
 #include <linux/err.h>
 #include <asm/ptrace.h>
@@ -87,4 +88,13 @@ static inline void syscall_set_arguments(struct task_struct *task,
                 regs->orig_gpr2 = args[0];
 }
 
+static inline int syscall_get_arch(struct task_struct *task,
+                                   struct pt_regs *regs)
+{
+#ifdef CONFIG_COMPAT
+        if (test_tsk_thread_flag(task, TIF_31BIT))
+                return AUDIT_ARCH_S390;
+#endif
+        return sizeof(long) == 8 ? AUDIT_ARCH_S390X : AUDIT_ARCH_S390;
+}
 #endif  /* _ASM_SYSCALL_H */
diff --git a/arch/s390/include/asm/sysinfo.h b/arch/s390/include/asm/sysinfo.h
index 79d3d6e2e9c..282ee36f616 100644
--- a/arch/s390/include/asm/sysinfo.h
+++ b/arch/s390/include/asm/sysinfo.h
@@ -1,7 +1,7 @@
 /*
  * definition for store system information stsi
  *
- * Copyright IBM Corp. 2001,2008
+ * Copyright IBM Corp. 2001, 2008
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License (version 2 only)
diff --git a/arch/s390/include/asm/tape390.h b/arch/s390/include/asm/tape390.h
index 884fba48f1f..b2bc4bab792 100644
--- a/arch/s390/include/asm/tape390.h
+++ b/arch/s390/include/asm/tape390.h
@@ -1,10 +1,9 @@
 /*************************************************************************
  *
- * tape390.h
  *         enables user programs to display messages and control encryption
  *         on s390 tape devices
  *
- *         Copyright IBM Corp. 2001,2006
+ *         Copyright IBM Corp. 2001, 2006
  *         Author(s): Michael Holzheu <holzheu@de.ibm.com>
  *
  *************************************************************************/
diff --git a/arch/s390/include/asm/termios.h b/arch/s390/include/asm/termios.h
index bc3a35cefc9..cb9fe2786b8 100644
--- a/arch/s390/include/asm/termios.h
+++ b/arch/s390/include/asm/termios.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/termios.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/termios.h"
diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
index 4e40b25cd06..bb08e2afc5d 100644
--- a/arch/s390/include/asm/thread_info.h
+++ b/arch/s390/include/asm/thread_info.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/thread_info.h
- *
  *  S390 version
- *    Copyright (C) IBM Corp. 2002,2006
+ *    Copyright IBM Corp. 2002, 2006
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  */
 
diff --git a/arch/s390/include/asm/timer.h b/arch/s390/include/asm/timer.h
deleted file mode 100644
index 15d647901e5..00000000000
--- a/arch/s390/include/asm/timer.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- *  include/asm-s390/timer.h
- *
- *  (C) Copyright IBM Corp. 2003,2006
- *  Virtual CPU timer
- *
- *  Author: Jan Glauber (jang@de.ibm.com)
- */
-
-#ifndef _ASM_S390_TIMER_H
-#define _ASM_S390_TIMER_H
-
-#include <linux/timer.h>
-
-#define VTIMER_MAX_SLICE (0x7ffffffffffff000LL)
-
-struct vtimer_list {
-        struct list_head entry;
-
-        int cpu;
-        __u64 expires;
-        __u64 interval;
-
-        void (*function)(unsigned long);
-        unsigned long data;
-};
-
-/* the vtimer value will wrap after ca. 71 years */
-struct vtimer_queue {
-        struct list_head list;
-        spinlock_t lock;
-        __u64 timer;            /* last programmed timer */
-        __u64 elapsed;          /* elapsed time of timer expire values */
-        __u64 idle_enter;       /* cpu timer on idle enter */
-        __u64 idle_exit;        /* cpu timer on idle exit */
-};
-
-extern void init_virt_timer(struct vtimer_list *timer);
-extern void add_virt_timer(void *new);
-extern void add_virt_timer_periodic(void *new);
-extern int mod_virt_timer(struct vtimer_list *timer, __u64 expires);
-extern int mod_virt_timer_periodic(struct vtimer_list *timer, __u64 expires);
-extern int del_virt_timer(struct vtimer_list *timer);
-
-extern void init_cpu_vtimer(void);
-extern void vtime_init(void);
-
-extern void vtime_stop_cpu(void);
-extern void vtime_start_leave(void);
-
-#endif /* _ASM_S390_TIMER_H */
diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h
index 239ece9e53c..fba4d66788a 100644
--- a/arch/s390/include/asm/timex.h
+++ b/arch/s390/include/asm/timex.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/timex.h
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *
  *  Derived from "include/asm-i386/timex.h"
  *    Copyright (C) 1992, Linus Torvalds
diff --git a/arch/s390/include/asm/types.h b/arch/s390/include/asm/types.h
index 6c8c35f8df1..6ba7c2c7217 100644
--- a/arch/s390/include/asm/types.h
+++ b/arch/s390/include/asm/types.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/types.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/types.h"
diff --git a/arch/s390/include/asm/uaccess.h b/arch/s390/include/asm/uaccess.h
index 1f3a79bcd26..a8ab18b18b5 100644
--- a/arch/s390/include/asm/uaccess.h
+++ b/arch/s390/include/asm/uaccess.h
@@ -1,8 +1,6 @@
 /*
- *  include/asm-s390/uaccess.h
- *
  *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2000
  *    Author(s): Hartmut Penner (hp@de.ibm.com),
  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
@@ -381,8 +379,6 @@ clear_user(void __user *to, unsigned long n)
         return n;
 }
 
-extern int memcpy_real(void *, void *, size_t);
-extern void memcpy_absolute(void *, void *, size_t);
 extern int copy_to_user_real(void __user *dest, void *src, size_t count);
 extern int copy_from_user_real(void *dest, void __user *src, size_t count);
 
diff --git a/arch/s390/include/asm/ucontext.h b/arch/s390/include/asm/ucontext.h
index cfb874e66c9..200e06325c6 100644
--- a/arch/s390/include/asm/ucontext.h
+++ b/arch/s390/include/asm/ucontext.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/ucontext.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/ucontext.h"
diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h
index 8a8008fe7b8..6756e78f480 100644
--- a/arch/s390/include/asm/unistd.h
+++ b/arch/s390/include/asm/unistd.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/unistd.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/unistd.h"
@@ -390,7 +388,6 @@
 #define __IGNORE_recvmmsg
 #define __IGNORE_sendmmsg
 
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_SYS_ALARM
 #define __ARCH_WANT_SYS_GETHOSTNAME
diff --git a/arch/s390/include/asm/user.h b/arch/s390/include/asm/user.h
index 1b050e35fdc..6ed1d188633 100644
--- a/arch/s390/include/asm/user.h
+++ b/arch/s390/include/asm/user.h
@@ -1,6 +1,4 @@
 /*
- *  include/asm-s390/user.h
- *
  *  S390 version
  *
  *  Derived from "include/asm-i386/usr.h"
diff --git a/arch/s390/include/asm/vtimer.h b/arch/s390/include/asm/vtimer.h
new file mode 100644
index 00000000000..bfe25d513ad
--- /dev/null
+++ b/arch/s390/include/asm/vtimer.h
@@ -0,0 +1,33 @@
+/*
+ *  Copyright IBM Corp. 2003, 2012
+ *  Virtual CPU timer
+ *
+ *  Author(s): Jan Glauber <jan.glauber@de.ibm.com>
+ */
+
+#ifndef _ASM_S390_TIMER_H
+#define _ASM_S390_TIMER_H
+
+#define VTIMER_MAX_SLICE (0x7fffffffffffffffULL)
+
+struct vtimer_list {
+        struct list_head entry;
+        u64 expires;
+        u64 interval;
+        void (*function)(unsigned long);
+        unsigned long data;
+};
+
+extern void init_virt_timer(struct vtimer_list *timer);
+extern void add_virt_timer(struct vtimer_list *timer);
+extern void add_virt_timer_periodic(struct vtimer_list *timer);
+extern int mod_virt_timer(struct vtimer_list *timer, u64 expires);
+extern int mod_virt_timer_periodic(struct vtimer_list *timer, u64 expires);
+extern int del_virt_timer(struct vtimer_list *timer);
+
+extern void init_cpu_vtimer(void);
+extern void vtime_init(void);
+
+extern void vtime_stop_cpu(void);
+
+#endif /* _ASM_S390_TIMER_H */
diff --git a/arch/s390/include/asm/vtoc.h b/arch/s390/include/asm/vtoc.h
index 8406a2b3157..221419de275 100644
--- a/arch/s390/include/asm/vtoc.h
+++ b/arch/s390/include/asm/vtoc.h
@@ -1,9 +1,7 @@
 /*
- * include/asm-s390/vtoc.h
- *
  * This file contains volume label definitions for DASD devices.
  *
- * (C) Copyright IBM Corp. 2005
+ * Copyright IBM Corp. 2005
  *
  * Author(s): Volker Sameske <sameske@de.ibm.com>
  *
diff --git a/arch/s390/include/asm/zcrypt.h b/arch/s390/include/asm/zcrypt.h
index 00d3bbd4411..e83fc116f5b 100644
--- a/arch/s390/include/asm/zcrypt.h
+++ b/arch/s390/include/asm/zcrypt.h
@@ -3,7 +3,7 @@
  *
  *  zcrypt 2.1.0 (user-visible header)
  *
- *  Copyright (C)  2001, 2006 IBM Corporation
+ *  Copyright IBM Corp. 2001, 2006
  *  Author(s): Robert Burroughs
  *             Eric Rossman (edrossma@us.ibm.com)
  *
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index 83e6edf5cf1..45ef1a7b08f 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -9,7 +9,6 @@
 #include <linux/kbuild.h>
 #include <linux/sched.h>
 #include <asm/cputime.h>
-#include <asm/timer.h>
 #include <asm/vdso.h>
 #include <asm/pgtable.h>
 
@@ -72,11 +71,10 @@ int main(void)
         DEFINE(__CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
         BLANK();
         /* idle data offsets */
-        DEFINE(__IDLE_ENTER, offsetof(struct s390_idle_data, idle_enter));
-        DEFINE(__IDLE_EXIT, offsetof(struct s390_idle_data, idle_exit));
-        /* vtimer queue offsets */
-        DEFINE(__VQ_IDLE_ENTER, offsetof(struct vtimer_queue, idle_enter));
-        DEFINE(__VQ_IDLE_EXIT, offsetof(struct vtimer_queue, idle_exit));
+        DEFINE(__CLOCK_IDLE_ENTER, offsetof(struct s390_idle_data, clock_idle_enter));
+        DEFINE(__CLOCK_IDLE_EXIT, offsetof(struct s390_idle_data, clock_idle_exit));
+        DEFINE(__TIMER_IDLE_ENTER, offsetof(struct s390_idle_data, timer_idle_enter));
+        DEFINE(__TIMER_IDLE_EXIT, offsetof(struct s390_idle_data, timer_idle_exit));
         /* lowcore offsets */
         DEFINE(__LC_EXT_PARAMS, offsetof(struct _lowcore, ext_params));
         DEFINE(__LC_EXT_CPU_ADDR, offsetof(struct _lowcore, ext_cpu_addr));
@@ -131,6 +129,8 @@ int main(void)
         DEFINE(__LC_PANIC_STACK, offsetof(struct _lowcore, panic_stack));
         DEFINE(__LC_RESTART_STACK, offsetof(struct _lowcore, restart_stack));
         DEFINE(__LC_RESTART_FN, offsetof(struct _lowcore, restart_fn));
+        DEFINE(__LC_RESTART_DATA, offsetof(struct _lowcore, restart_data));
+        DEFINE(__LC_RESTART_SOURCE, offsetof(struct _lowcore, restart_source));
         DEFINE(__LC_USER_ASCE, offsetof(struct _lowcore, user_asce));
         DEFINE(__LC_INT_CLOCK, offsetof(struct _lowcore, int_clock));
         DEFINE(__LC_MCCK_CLOCK, offsetof(struct _lowcore, mcck_clock));
diff --git a/arch/s390/kernel/base.S b/arch/s390/kernel/base.S
index c880ff72db4..797a823a227 100644
--- a/arch/s390/kernel/base.S
+++ b/arch/s390/kernel/base.S
@@ -1,7 +1,7 @@
 /*
  *  arch/s390/kernel/base.S
  *
- *    Copyright IBM Corp. 2006,2007
+ *    Copyright IBM Corp. 2006, 2007
  *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
  *               Michael Holzheu <holzheu@de.ibm.com>
  */
@@ -9,6 +9,7 @@
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
 #include <asm/ptrace.h>
+#include <asm/sigp.h>
 
 #ifdef CONFIG_64BIT
 
@@ -100,7 +101,7 @@ ENTRY(diag308_reset)
 .Lrestart_part2:
         lhi     %r0,0                   # Load r0 with zero
         lhi     %r1,2                   # Use mode 2 = ESAME (dump)
-        sigp    %r1,%r0,0x12            # Switch to ESAME mode
+        sigp    %r1,%r0,SIGP_SET_ARCHITECTURE   # Switch to ESAME mode
         sam64                           # Switch to 64 bit addressing mode
         larl    %r4,.Lctlregs           # Restore control registers
         lctlg   %c0,%c15,0(%r4)
diff --git a/arch/s390/kernel/bitmap.c b/arch/s390/kernel/bitmap.c
index 3ae4757b006..102da5e2303 100644
--- a/arch/s390/kernel/bitmap.c
+++ b/arch/s390/kernel/bitmap.c
@@ -2,7 +2,7 @@
  *    Bitmaps for set_bit, clear_bit, test_and_set_bit, ...
  *    See include/asm/{bitops.h|posix_types.h} for details
  *
- *    Copyright IBM Corp. 1999,2009
+ *    Copyright IBM Corp. 1999, 2009
  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
  */
 
diff --git a/arch/s390/kernel/compat_exec_domain.c b/arch/s390/kernel/compat_exec_domain.c
index 914d49444f9..765fabdada9 100644
--- a/arch/s390/kernel/compat_exec_domain.c
+++ b/arch/s390/kernel/compat_exec_domain.c
@@ -1,7 +1,7 @@
 /*
  * Support for 32-bit Linux for S390 personality.
  *
- * Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ * Copyright IBM Corp. 2000
  * Author(s): Gerhard Tonn (ton@de.ibm.com)
  *
  *
diff --git a/arch/s390/kernel/compat_linux.c b/arch/s390/kernel/compat_linux.c
index 65426525d9f..f606d935f49 100644
--- a/arch/s390/kernel/compat_linux.c
+++ b/arch/s390/kernel/compat_linux.c
@@ -1,8 +1,6 @@
 /*
- *  arch/s390x/kernel/linux32.c
- *
  *  S390 version
- *    Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 2000
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Gerhard Tonn (ton@de.ibm.com)   
  *               Thomas Spatzier (tspat@de.ibm.com)
@@ -622,7 +620,6 @@ asmlinkage unsigned long old32_mmap(struct mmap_arg_struct_emu31 __user *arg)
                 return -EFAULT;
         if (a.offset & ~PAGE_MASK)
                 return -EINVAL;
-        a.addr = (unsigned long) compat_ptr(a.addr);
         return sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd,
                               a.offset >> PAGE_SHIFT);
 }
@@ -633,7 +630,6 @@ asmlinkage long sys32_mmap2(struct mmap_arg_struct_emu31 __user *arg)
 
         if (copy_from_user(&a, arg, sizeof(a)))
                 return -EFAULT;
-        a.addr = (unsigned long) compat_ptr(a.addr);
         return sys_mmap_pgoff(a.addr, a.len, a.prot, a.flags, a.fd, a.offset);
 }
 
diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c
index 3c0c19830c3..a1e8a8694bb 100644
--- a/arch/s390/kernel/compat_signal.c
+++ b/arch/s390/kernel/compat_signal.c
@@ -1,7 +1,5 @@
 /*
- *  arch/s390/kernel/compat_signal.c
- *
- *    Copyright (C) IBM Corp. 2000,2006
+ *    Copyright IBM Corp. 2000, 2006
  *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
  *               Gerhard Tonn (ton@de.ibm.com)                  
  *
diff --git a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S
index ff605a39cf4..2d82cfcbce5 100644
--- a/arch/s390/kernel/compat_wrapper.S
+++ b/arch/s390/kernel/compat_wrapper.S
@@ -1,8 +1,7 @@
 /*
-*  arch/s390/kernel/compat_wrapper.S
 *    wrapper for 31 bit compatible system calls.
 *
-*    Copyright (C) IBM Corp. 2000,2006
+*    Copyright IBM Corp. 2000, 2006
 *    Author(s): Gerhard Tonn (ton@de.ibm.com),
 *               Thomas Spatzier (tspat@de.ibm.com)
 */
@@ -1636,7 +1635,7 @@ ENTRY(compat_sys_process_vm_readv_wrapper)
         llgfr   %r6,%r6                 # unsigned long
         llgf    %r0,164(%r15)           # unsigned long
         stg     %r0,160(%r15)
-        jg      sys_process_vm_readv
+        jg      compat_sys_process_vm_readv
 
 ENTRY(compat_sys_process_vm_writev_wrapper)
         lgfr    %r2,%r2                 # compat_pid_t
@@ -1646,4 +1645,4 @@ ENTRY(compat_sys_process_vm_writev_wrapper)
         llgfr   %r6,%r6                 # unsigned long
         llgf    %r0,164(%r15)           # unsigned long
         stg     %r0,160(%r15)
-        jg      sys_process_vm_writev
+        jg      compat_sys_process_vm_writev
diff --git a/arch/s390/kernel/cpcmd.c b/arch/s390/kernel/cpcmd.c
index e3dd886e1b3..d7b0c4d2788 100644
--- a/arch/s390/kernel/cpcmd.c
+++ b/arch/s390/kernel/cpcmd.c
@@ -1,8 +1,6 @@
 /*
- *  arch/s390/kernel/cpcmd.c
- *
  *  S390 version
- *    Copyright IBM Corp. 1999,2007
+ *    Copyright IBM Corp. 1999, 2007
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Christian Borntraeger (cborntra@de.ibm.com),
  */
diff --git a/arch/s390/kernel/crash.c b/arch/s390/kernel/crash.c
index 8cc7c9fa64f..3819153de8b 100644
--- a/arch/s390/kernel/crash.c
+++ b/arch/s390/kernel/crash.c
@@ -1,7 +1,5 @@
 /*
- * arch/s390/kernel/crash.c
- *
- * (C) Copyright IBM Corp. 2005
+ * Copyright IBM Corp. 2005
  *
  * Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
  *
diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c
index 19e5e9eba54..ba500d8dc39 100644
--- a/arch/s390/kernel/debug.c
+++ b/arch/s390/kernel/debug.c
@@ -1,5 +1,4 @@
 /*
- *  arch/s390/kernel/debug.c
  *   S/390 debug facility
  *
  *    Copyright IBM Corp. 1999, 2012
@@ -111,6 +110,7 @@ struct debug_view debug_raw_view = {
         NULL,
         NULL
 };
+EXPORT_SYMBOL(debug_raw_view);
 
 struct debug_view debug_hex_ascii_view = {
         "hex_ascii",
@@ -120,6 +120,7 @@ struct debug_view debug_hex_ascii_view = {
         NULL,
         NULL
 };
+EXPORT_SYMBOL(debug_hex_ascii_view);
 
 static struct debug_view debug_level_view = {
         "level",
@@ -156,6 +157,7 @@ struct debug_view debug_sprintf_view = {
         NULL,
         NULL
 };
+EXPORT_SYMBOL(debug_sprintf_view);
 
 /* used by dump analysis tools to determine version of debug feature */
 static unsigned int __used debug_feature_version = __DEBUG_FEATURE_VERSION;
@@ -731,6 +733,7 @@ debug_info_t *debug_register(const char *name, int pages_per_area,
         return debug_register_mode(name, pages_per_area, nr_areas, buf_size,
                                    S_IRUSR | S_IWUSR, 0, 0);
 }
+EXPORT_SYMBOL(debug_register);
 
 /*
  * debug_unregister:
@@ -749,6 +752,7 @@ debug_unregister(debug_info_t * id)
 out:
         return;
 }
+EXPORT_SYMBOL(debug_unregister);
 
 /*
  * debug_set_size:
@@ -811,7 +815,7 @@ debug_set_level(debug_info_t* id, int new_level)
         }
         spin_unlock_irqrestore(&id->lock,flags);
 }
-
+EXPORT_SYMBOL(debug_set_level);
 
 /*
  * proceed_active_entry:
@@ -931,7 +935,7 @@ debug_stop_all(void)
         if (debug_stoppable)
                 debug_active = 0;
 }
-
+EXPORT_SYMBOL(debug_stop_all);
 
 void debug_set_critical(void)
 {
@@ -964,6 +968,7 @@ debug_event_common(debug_info_t * id, int level, const void *buf, int len)
 
         return active;
 }
+EXPORT_SYMBOL(debug_event_common);
 
 /*
  * debug_exception_common:
@@ -991,6 +996,7 @@ debug_entry_t
 
         return active;
 }
+EXPORT_SYMBOL(debug_exception_common);
 
 /*
  * counts arguments in format string for sprintf view
@@ -1044,6 +1050,7 @@ debug_sprintf_event(debug_info_t* id, int level,char *string,...)
 
         return active;
 }
+EXPORT_SYMBOL(debug_sprintf_event);
 
 /*
  * debug_sprintf_exception:
@@ -1082,25 +1089,7 @@ debug_sprintf_exception(debug_info_t* id, int level,char *string,...)
 
         return active;
 }
-
-/*
- * debug_init:
- * - is called exactly once to initialize the debug feature
- */
-
-static int
-__init debug_init(void)
-{
-        int rc = 0;
-
-        s390dbf_sysctl_header = register_sysctl_table(s390dbf_dir_table);
-        mutex_lock(&debug_mutex);
-        debug_debugfs_root_entry = debugfs_create_dir(DEBUG_DIR_ROOT,NULL);
-        initialized = 1;
-        mutex_unlock(&debug_mutex);
-
-        return rc;
-}
+EXPORT_SYMBOL(debug_sprintf_exception);
 
 /*
  * debug_register_view:
@@ -1148,6 +1137,7 @@ debug_register_view(debug_info_t * id, struct debug_view *view)
 out:
         return rc;
 }
+EXPORT_SYMBOL(debug_register_view);
 
 /*
  * debug_unregister_view:
@@ -1177,6 +1167,7 @@ debug_unregister_view(debug_info_t * id, struct debug_view *view)
 out:
         return rc;
 }
+EXPORT_SYMBOL(debug_unregister_view);
 
 static inline char *
 debug_get_user_string(const char __user *user_buf, size_t user_len)
@@ -1486,6 +1477,7 @@ debug_dflt_header_fn(debug_info_t * id, struct debug_view *view,
                       except_str, entry->id.fields.cpuid, (void *) caller);
         return rc;
 }
+EXPORT_SYMBOL(debug_dflt_header_fn);
 
 /*
  * prints debug data sprintf-formated:
@@ -1534,33 +1526,16 @@ out:
 }
 
 /*
- * clean up module
+ * debug_init:
+ * - is called exactly once to initialize the debug feature
  */
-static void __exit debug_exit(void)
+static int __init debug_init(void)
 {
-        debugfs_remove(debug_debugfs_root_entry);
-        unregister_sysctl_table(s390dbf_sysctl_header);
-        return;
+        s390dbf_sysctl_header = register_sysctl_table(s390dbf_dir_table);
+        mutex_lock(&debug_mutex);
+        debug_debugfs_root_entry = debugfs_create_dir(DEBUG_DIR_ROOT, NULL);
+        initialized = 1;
+        mutex_unlock(&debug_mutex);
+        return 0;
 }
-
-/*
- * module definitions
- */
 postcore_initcall(debug_init);
-module_exit(debug_exit);
-MODULE_LICENSE("GPL");
-
-EXPORT_SYMBOL(debug_register);
-EXPORT_SYMBOL(debug_unregister); 
-EXPORT_SYMBOL(debug_set_level);
-EXPORT_SYMBOL(debug_stop_all);
-EXPORT_SYMBOL(debug_register_view);
-EXPORT_SYMBOL(debug_unregister_view);
-EXPORT_SYMBOL(debug_event_common);
-EXPORT_SYMBOL(debug_exception_common);
-EXPORT_SYMBOL(debug_hex_ascii_view);
-EXPORT_SYMBOL(debug_raw_view);
-EXPORT_SYMBOL(debug_dflt_header_fn);
-EXPORT_SYMBOL(debug_sprintf_view);
-EXPORT_SYMBOL(debug_sprintf_exception);
-EXPORT_SYMBOL(debug_sprintf_event);
diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c
index 3221c6fca8b..619c5d35072 100644
--- a/arch/s390/kernel/dis.c
+++ b/arch/s390/kernel/dis.c
@@ -1,6 +1,4 @@
 /*
- * arch/s390/kernel/dis.c
- *
  * Disassemble s390 instructions.
  *
  * Copyright IBM Corp. 2007
@@ -613,6 +611,7 @@ static struct insn opcode_b2[] = {
         { "sie", 0x14, INSTR_S_RD },
         { "pc", 0x18, INSTR_S_RD },
         { "sac", 0x19, INSTR_S_RD },
+        { "servc", 0x20, INSTR_RRE_RR },
         { "cfc", 0x1a, INSTR_S_RD },
         { "ipte", 0x21, INSTR_RRE_RR },
         { "ipm", 0x22, INSTR_RRE_R0 },
@@ -1532,7 +1531,7 @@ static int print_insn(char *buffer, unsigned char *code, unsigned long addr)
 
 void show_code(struct pt_regs *regs)
 {
-        char *mode = (regs->psw.mask & PSW_MASK_PSTATE) ? "User" : "Krnl";
+        char *mode = user_mode(regs) ? "User" : "Krnl";
         unsigned char code[64];
         char buffer[64], *ptr;
         mm_segment_t old_fs;
@@ -1541,7 +1540,7 @@ void show_code(struct pt_regs *regs)
 
         /* Get a snapshot of the 64 bytes surrounding the fault address. */
         old_fs = get_fs();
-        set_fs((regs->psw.mask & PSW_MASK_PSTATE) ? USER_DS : KERNEL_DS);
+        set_fs(user_mode(regs) ? USER_DS : KERNEL_DS);
         for (start = 32; start && regs->psw.addr >= 34 - start; start -= 2) {
                 addr = regs->psw.addr - 34 + start;
                 if (__copy_from_user(code + start - 2,
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index 6684fff1755..83c3271c442 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -1,6 +1,4 @@
 /*
- *  arch/s390/kernel/early.c
- *
  *    Copyright IBM Corp. 2007, 2009
  *    Author(s): Hongjie Yang <hongjie@us.ibm.com>,
  *               Heiko Carstens <heiko.carstens@de.ibm.com>
@@ -457,7 +455,6 @@ void __init startup_init(void)
         init_kernel_storage_key();
         lockdep_init();
         lockdep_off();
-        sort_main_extable();
         setup_lowcore_early();
         setup_facility_list();
         detect_machine_type();
diff --git a/arch/s390/kernel/ebcdic.c b/arch/s390/kernel/ebcdic.c
index cc0dc609d73..b971c6be629 100644
--- a/arch/s390/kernel/ebcdic.c
+++ b/arch/s390/kernel/ebcdic.c
@@ -1,10 +1,9 @@
 /*
- *  arch/s390/kernel/ebcdic.c
  *    ECBDIC -> ASCII, ASCII -> ECBDIC,
  *    upper to lower case (EBCDIC) conversion tables.
  *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
  *               Martin Peschke <peschke@fh-brandenburg.de>
  */
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 1ae93b573d7..870bad6d56f 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -1,8 +1,7 @@
 /*
- *  arch/s390/kernel/entry.S
  *    S390 low-level entry points.
  *
- *    Copyright (C) IBM Corp. 1999,2012
+ *    Copyright IBM Corp. 1999, 2012
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Hartmut Penner (hp@de.ibm.com),
  *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
@@ -18,6 +17,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/unistd.h>
 #include <asm/page.h>
+#include <asm/sigp.h>
 
 __PT_R0      =  __PT_GPRS
 __PT_R1      =  __PT_GPRS + 4
@@ -616,17 +616,13 @@ ext_skip:
  * Load idle PSW. The second "half" of this function is in cleanup_idle.
  */
 ENTRY(psw_idle)
-        st      %r4,__SF_EMPTY(%r15)
+        st      %r3,__SF_EMPTY(%r15)
         basr    %r1,0
         la      %r1,psw_idle_lpsw+4-.(%r1)
         st      %r1,__SF_EMPTY+4(%r15)
         oi      __SF_EMPTY+4(%r15),0x80
-        la      %r1,.Lvtimer_max-psw_idle_lpsw-4(%r1)
-        stck    __IDLE_ENTER(%r2)
-        ltr     %r5,%r5
-        stpt    __VQ_IDLE_ENTER(%r3)
-        jz      psw_idle_lpsw
-        spt     0(%r1)
+        stck    __CLOCK_IDLE_ENTER(%r2)
+        stpt    __TIMER_IDLE_ENTER(%r2)
 psw_idle_lpsw:
         lpsw    __SF_EMPTY(%r15)
         br      %r14
@@ -723,15 +719,17 @@ ENTRY(restart_int_handler)
         mvc     __PT_PSW(8,%r15),__LC_RST_OLD_PSW # store restart old psw
         ahi     %r15,-STACK_FRAME_OVERHEAD      # create stack frame on stack
         xc      0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
-        lm      %r1,%r3,__LC_RESTART_FN         # load fn, parm & source cpu
+        l       %r1,__LC_RESTART_FN             # load fn, parm & source cpu
+        l       %r2,__LC_RESTART_DATA
+        l       %r3,__LC_RESTART_SOURCE
         ltr     %r3,%r3                         # test source cpu address
         jm      1f                              # negative -> skip source stop
-0:      sigp    %r4,%r3,1                       # sigp sense to source cpu
+0:      sigp    %r4,%r3,SIGP_SENSE              # sigp sense to source cpu
         brc     10,0b                           # wait for status stored
 1:      basr    %r14,%r1                        # call function
         stap    __SF_EMPTY(%r15)                # store cpu address
         lh      %r3,__SF_EMPTY(%r15)
-2:      sigp    %r4,%r3,5                       # sigp stop to current cpu
+2:      sigp    %r4,%r3,SIGP_STOP               # sigp stop to current cpu
         brc     2,2b
 3:      j       3b
 
@@ -883,33 +881,28 @@ cleanup_io_restore_insn:
 
 cleanup_idle:
         # copy interrupt clock & cpu timer
-        mvc     __IDLE_EXIT(8,%r2),__LC_INT_CLOCK
-        mvc     __VQ_IDLE_EXIT(8,%r3),__LC_ASYNC_ENTER_TIMER
+        mvc     __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
+        mvc     __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
         chi     %r11,__LC_SAVE_AREA_ASYNC
         je      0f
-        mvc     __IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
-        mvc     __VQ_IDLE_EXIT(8,%r3),__LC_MCCK_ENTER_TIMER
+        mvc     __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
+        mvc     __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
 0:      # check if stck has been executed
         cl      %r9,BASED(cleanup_idle_insn)
         jhe     1f
-        mvc     __IDLE_ENTER(8,%r2),__IDLE_EXIT(%r2)
-        mvc     __VQ_IDLE_ENTER(8,%r3),__VQ_IDLE_EXIT(%r3)
-        j       2f
-1:      # check if the cpu timer has been reprogrammed
-        ltr     %r5,%r5
-        jz      2f
-        spt     __VQ_IDLE_ENTER(%r3)
-2:      # account system time going idle
+        mvc     __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
+        mvc     __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r3)
+1:      # account system time going idle
         lm      %r9,%r10,__LC_STEAL_TIMER
-        ADD64   %r9,%r10,__IDLE_ENTER(%r2)
+        ADD64   %r9,%r10,__CLOCK_IDLE_ENTER(%r2)
         SUB64   %r9,%r10,__LC_LAST_UPDATE_CLOCK
         stm     %r9,%r10,__LC_STEAL_TIMER
-        mvc     __LC_LAST_UPDATE_CLOCK(8),__IDLE_EXIT(%r2)
+        mvc     __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
         lm      %r9,%r10,__LC_SYSTEM_TIMER
         ADD64   %r9,%r10,__LC_LAST_UPDATE_TIMER
-        SUB64   %r9,%r10,__VQ_IDLE_ENTER(%r3)
+        SUB64   %r9,%r10,__TIMER_IDLE_ENTER(%r2)
         stm     %r9,%r10,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__VQ_IDLE_EXIT(%r3)
+        mvc     __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
         # prepare return psw
         n       %r8,BASED(cleanup_idle_wait)    # clear wait state bit
         l       %r9,24(%r11)                    # return from psw_idle
diff --git a/arch/s390/kernel/entry.h b/arch/s390/kernel/entry.h
index f66a229ab0b..a5f4dc42a5d 100644
--- a/arch/s390/kernel/entry.h
+++ b/arch/s390/kernel/entry.h
@@ -5,7 +5,6 @@
 #include <linux/signal.h>
 #include <asm/ptrace.h>
 #include <asm/cputime.h>
-#include <asm/timer.h>
 
 extern void (*pgm_check_table[128])(struct pt_regs *);
 extern void *restart_stack;
@@ -17,8 +16,7 @@ void io_int_handler(void);
 void mcck_int_handler(void);
 void restart_int_handler(void);
 void restart_call_handler(void);
-void psw_idle(struct s390_idle_data *, struct vtimer_queue *,
-              unsigned long, int);
+void psw_idle(struct s390_idle_data *, unsigned long);
 
 asmlinkage long do_syscall_trace_enter(struct pt_regs *regs);
 asmlinkage void do_syscall_trace_exit(struct pt_regs *regs);
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 229fe1d0774..349b7eeb348 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -1,8 +1,7 @@
 /*
- *  arch/s390/kernel/entry64.S
  *    S390 low-level entry points.
  *
- *    Copyright (C) IBM Corp. 1999,2012
+ *    Copyright IBM Corp. 1999, 2012
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Hartmut Penner (hp@de.ibm.com),
  *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
@@ -18,6 +17,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/unistd.h>
 #include <asm/page.h>
+#include <asm/sigp.h>
 
 __PT_R0      =  __PT_GPRS
 __PT_R1      =  __PT_GPRS + 8
@@ -642,15 +642,11 @@ ext_skip:
  * Load idle PSW. The second "half" of this function is in cleanup_idle.
  */
 ENTRY(psw_idle)
-        stg     %r4,__SF_EMPTY(%r15)
+        stg     %r3,__SF_EMPTY(%r15)
         larl    %r1,psw_idle_lpsw+4
         stg     %r1,__SF_EMPTY+8(%r15)
-        larl    %r1,.Lvtimer_max
-        STCK    __IDLE_ENTER(%r2)
-        ltr     %r5,%r5
-        stpt    __VQ_IDLE_ENTER(%r3)
-        jz      psw_idle_lpsw
-        spt     0(%r1)
+        STCK    __CLOCK_IDLE_ENTER(%r2)
+        stpt    __TIMER_IDLE_ENTER(%r2)
 psw_idle_lpsw:
         lpswe   __SF_EMPTY(%r15)
         br      %r14
@@ -750,15 +746,17 @@ ENTRY(restart_int_handler)
         mvc     __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
         aghi    %r15,-STACK_FRAME_OVERHEAD      # create stack frame on stack
         xc      0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
-        lmg     %r1,%r3,__LC_RESTART_FN         # load fn, parm & source cpu
+        lg      %r1,__LC_RESTART_FN             # load fn, parm & source cpu
+        lg      %r2,__LC_RESTART_DATA
+        lg      %r3,__LC_RESTART_SOURCE
         ltgr    %r3,%r3                         # test source cpu address
         jm      1f                              # negative -> skip source stop
-0:      sigp    %r4,%r3,1                       # sigp sense to source cpu
+0:      sigp    %r4,%r3,SIGP_SENSE              # sigp sense to source cpu
         brc     10,0b                           # wait for status stored
 1:      basr    %r14,%r1                        # call function
         stap    __SF_EMPTY(%r15)                # store cpu address
         llgh    %r3,__SF_EMPTY(%r15)
-2:      sigp    %r4,%r3,5                       # sigp stop to current cpu
+2:      sigp    %r4,%r3,SIGP_STOP               # sigp stop to current cpu
         brc     2,2b
 3:      j       3b
 
@@ -916,33 +914,28 @@ cleanup_io_restore_insn:
 
 cleanup_idle:
         # copy interrupt clock & cpu timer
-        mvc     __IDLE_EXIT(8,%r2),__LC_INT_CLOCK
-        mvc     __VQ_IDLE_EXIT(8,%r3),__LC_ASYNC_ENTER_TIMER
+        mvc     __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
+        mvc     __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
         cghi    %r11,__LC_SAVE_AREA_ASYNC
         je      0f
-        mvc     __IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
-        mvc     __VQ_IDLE_EXIT(8,%r3),__LC_MCCK_ENTER_TIMER
+        mvc     __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
+        mvc     __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
 0:      # check if stck & stpt have been executed
         clg     %r9,BASED(cleanup_idle_insn)
         jhe     1f
-        mvc     __IDLE_ENTER(8,%r2),__IDLE_EXIT(%r2)
-        mvc     __VQ_IDLE_ENTER(8,%r3),__VQ_IDLE_EXIT(%r3)
-        j       2f
-1:      # check if the cpu timer has been reprogrammed
-        ltr     %r5,%r5
-        jz      2f
-        spt     __VQ_IDLE_ENTER(%r3)
-2:      # account system time going idle
+        mvc     __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
+        mvc     __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
+1:      # account system time going idle
         lg      %r9,__LC_STEAL_TIMER
-        alg     %r9,__IDLE_ENTER(%r2)
+        alg     %r9,__CLOCK_IDLE_ENTER(%r2)
         slg     %r9,__LC_LAST_UPDATE_CLOCK
         stg     %r9,__LC_STEAL_TIMER
-        mvc     __LC_LAST_UPDATE_CLOCK(8),__IDLE_EXIT(%r2)
+        mvc     __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
         lg      %r9,__LC_SYSTEM_TIMER
         alg     %r9,__LC_LAST_UPDATE_TIMER
-        slg     %r9,__VQ_IDLE_ENTER(%r3)
+        slg     %r9,__TIMER_IDLE_ENTER(%r2)
         stg     %r9,__LC_SYSTEM_TIMER
-        mvc     __LC_LAST_UPDATE_TIMER(8),__VQ_IDLE_EXIT(%r3)
+        mvc     __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
         # prepare return psw
         nihh    %r8,0xfffd              # clear wait state bit
         lg      %r9,48(%r11)            # return from psw_idle
@@ -958,8 +951,6 @@ cleanup_idle_insn:
         .quad   __critical_start
 .Lcritical_length:
         .quad   __critical_end - __critical_start
-.Lvtimer_max:
-        .quad   0x7fffffffffffffff
 
 
 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_MODULE)
@@ -974,7 +965,6 @@ ENTRY(sie64a)
         stg     %r3,__SF_EMPTY+8(%r15)          # save guest register save area
         xc      __SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # host id == 0
         lmg     %r0,%r13,0(%r3)                 # load guest gprs 0-13
-        lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
 sie_loop:
         lg      %r14,__LC_THREAD_INFO           # pointer thread_info struct
         tm      __TI_flags+7(%r14),_TIF_EXIT_SIE
diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S
index 4939d15375a..805b6686b64 100644
--- a/arch/s390/kernel/head.S
+++ b/arch/s390/kernel/head.S
@@ -1,5 +1,5 @@
 /*
- * Copyright IBM Corp. 1999,2010
+ * Copyright IBM Corp. 1999, 2010
  *
  *    Author(s): Hartmut Penner <hp@de.ibm.com>
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>
diff --git a/arch/s390/kernel/head31.S b/arch/s390/kernel/head31.S
index d3f1ab7d90a..a1372ae24ae 100644
--- a/arch/s390/kernel/head31.S
+++ b/arch/s390/kernel/head31.S
@@ -1,7 +1,5 @@
 /*
- * arch/s390/kernel/head31.S
- *
- * Copyright (C) IBM Corp. 2005,2010
+ * Copyright IBM Corp. 2005, 2010
  *
  *   Author(s): Hartmut Penner <hp@de.ibm.com>
  *              Martin Schwidefsky <schwidefsky@de.ibm.com>
diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index 99348c0eaa4..c108af28bbe 100644
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -1,7 +1,5 @@
 /*
- * arch/s390/kernel/head64.S
- *
- * Copyright (C) IBM Corp. 1999,2010
+ * Copyright IBM Corp. 1999, 2010
  *
  *   Author(s): Hartmut Penner <hp@de.ibm.com>
  *              Martin Schwidefsky <schwidefsky@de.ibm.com>
diff --git a/arch/s390/kernel/head_kdump.S b/arch/s390/kernel/head_kdump.S
index 796c976b5fd..acaaaf4b705 100644
--- a/arch/s390/kernel/head_kdump.S
+++ b/arch/s390/kernel/head_kdump.S
@@ -5,6 +5,8 @@
  * Author(s): Michael Holzheu <holzheu@linux.vnet.ibm.com>
  */
 
+#include <asm/sigp.h>
+
 #define DATAMOVER_ADDR  0x4000
 #define COPY_PAGE_ADDR  0x6000
 
@@ -19,7 +21,7 @@
 .align 2
 .Lep_startup_kdump:
         lhi     %r1,2                           # mode 2 = esame (dump)
-        sigp    %r1,%r0,0x12                    # Switch to esame mode
+        sigp    %r1,%r0,SIGP_SET_ARCHITECTURE   # Switch to esame mode
         sam64                                   # Switch to 64 bit addressing
         basr    %r13,0
 .Lbase:
@@ -88,7 +90,7 @@ startup_kdump_relocated:
         sam31                                   # Switch to 31 bit addr mode
         sr      %r1,%r1                         # Erase register r1
         sr      %r2,%r2                         # Erase register r2
-        sigp    %r1,%r2,0x12                    # Switch to 31 bit arch mode
+        sigp    %r1,%r2,SIGP_SET_ARCHITECTURE   # Switch to 31 bit arch mode
         lpsw    0                               # Start new kernel...
 .align  8
 .Lrestart_psw:
diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c
index 2f6cfd460cb..6ffcd320321 100644
--- a/arch/s390/kernel/ipl.c
+++ b/arch/s390/kernel/ipl.c
@@ -1,8 +1,7 @@
 /*
- *  arch/s390/kernel/ipl.c
  *    ipl/reipl/dump support for Linux on s390.
  *
- *    Copyright IBM Corp. 2005,2012
+ *    Copyright IBM Corp. 2005, 2012
  *    Author(s): Michael Holzheu <holzheu@de.ibm.com>
  *               Heiko Carstens <heiko.carstens@de.ibm.com>
  *               Volker Sameske <sameske@de.ibm.com>
@@ -1528,15 +1527,12 @@ static struct shutdown_action __refdata dump_action = {
 
 static void dump_reipl_run(struct shutdown_trigger *trigger)
 {
-        struct {
-                void    *addr;
-                __u32   csum;
-        } __packed ipib;
+        unsigned long ipib = (unsigned long) reipl_block_actual;
+        unsigned int csum;
 
-        ipib.csum = csum_partial(reipl_block_actual,
-                                 reipl_block_actual->hdr.len, 0);
-        ipib.addr = reipl_block_actual;
-        memcpy_absolute(&S390_lowcore.ipib, &ipib, sizeof(ipib));
+        csum = csum_partial(reipl_block_actual, reipl_block_actual->hdr.len, 0);
+        mem_assign_absolute(S390_lowcore.ipib, ipib);
+        mem_assign_absolute(S390_lowcore.ipib_checksum, csum);
         dump_run(trigger);
 }
 
@@ -1587,7 +1583,7 @@ static struct kset *vmcmd_kset;
 
 static void vmcmd_run(struct shutdown_trigger *trigger)
 {
-        char *cmd, *next_cmd;
+        char *cmd;
 
         if (strcmp(trigger->name, ON_REIPL_STR) == 0)
                 cmd = vmcmd_on_reboot;
@@ -1604,15 +1600,7 @@ static void vmcmd_run(struct shutdown_trigger *trigger)
 
         if (strlen(cmd) == 0)
                 return;
-        do {
-                next_cmd = strchr(cmd, '\n');
-                if (next_cmd) {
-                        next_cmd[0] = 0;
-                        next_cmd += 1;
-                }
-                __cpcmd(cmd, NULL, 0, NULL);
-                cmd = next_cmd;
-        } while (cmd != NULL);
+        __cpcmd(cmd, NULL, 0, NULL);
 }
 
 static int vmcmd_init(void)
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index b4f4a7133fa..dd7630d8aab 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -1,5 +1,5 @@
 /*
- *    Copyright IBM Corp. 2004,2011
+ *    Copyright IBM Corp. 2004, 2011
  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Holger Smolinski <Holger.Smolinski@de.ibm.com>,
  *               Thomas Spatzier <tspat@de.ibm.com>,
diff --git a/arch/s390/kernel/kprobes.c b/arch/s390/kernel/kprobes.c
index 64b761aef00..8aa634f5944 100644
--- a/arch/s390/kernel/kprobes.c
+++ b/arch/s390/kernel/kprobes.c
@@ -15,7 +15,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  *
- * Copyright (C) IBM Corporation, 2002, 2006
+ * Copyright IBM Corp. 2002, 2006
  *
  * s390 port, used ppc64 as template. Mike Grundy <grundym@us.ibm.com>
  */
diff --git a/arch/s390/kernel/lgr.c b/arch/s390/kernel/lgr.c
index 87f080b17af..eca94e74d19 100644
--- a/arch/s390/kernel/lgr.c
+++ b/arch/s390/kernel/lgr.c
@@ -45,7 +45,7 @@ struct lgr_info {
 /*
  * LGR globals
  */
-static void *lgr_page;
+static char lgr_page[PAGE_SIZE] __aligned(PAGE_SIZE);
 static struct lgr_info lgr_info_last;
 static struct lgr_info lgr_info_cur;
 static struct debug_info *lgr_dbf;
@@ -74,7 +74,7 @@ static void cpascii(char *dst, char *src, int size)
  */
 static void lgr_stsi_1_1_1(struct lgr_info *lgr_info)
 {
-        struct sysinfo_1_1_1 *si = lgr_page;
+        struct sysinfo_1_1_1 *si = (void *) lgr_page;
 
         if (stsi(si, 1, 1, 1) == -ENOSYS)
                 return;
@@ -91,7 +91,7 @@ static void lgr_stsi_1_1_1(struct lgr_info *lgr_info)
  */
 static void lgr_stsi_2_2_2(struct lgr_info *lgr_info)
 {
-        struct sysinfo_2_2_2 *si = lgr_page;
+        struct sysinfo_2_2_2 *si = (void *) lgr_page;
 
         if (stsi(si, 2, 2, 2) == -ENOSYS)
                 return;
@@ -105,7 +105,7 @@ static void lgr_stsi_2_2_2(struct lgr_info *lgr_info)
  */
 static void lgr_stsi_3_2_2(struct lgr_info *lgr_info)
 {
-        struct sysinfo_3_2_2 *si = lgr_page;
+        struct sysinfo_3_2_2 *si = (void *) lgr_page;
         int i;
 
         if (stsi(si, 3, 2, 2) == -ENOSYS)
@@ -183,14 +183,9 @@ static void lgr_timer_set(void)
  */
 static int __init lgr_init(void)
 {
-        lgr_page = (void *) __get_free_pages(GFP_KERNEL, 0);
-        if (!lgr_page)
-                return -ENOMEM;
         lgr_dbf = debug_register("lgr", 1, 1, sizeof(struct lgr_info));
-        if (!lgr_dbf) {
-                free_page((unsigned long) lgr_page);
+        if (!lgr_dbf)
                 return -ENOMEM;
-        }
         debug_register_view(lgr_dbf, &debug_hex_ascii_view);
         lgr_info_get(&lgr_info_last);
         debug_event(lgr_dbf, 1, &lgr_info_last, sizeof(lgr_info_last));
diff --git a/arch/s390/kernel/machine_kexec.c b/arch/s390/kernel/machine_kexec.c
index cdacf8f91b2..493304bdf1c 100644
--- a/arch/s390/kernel/machine_kexec.c
+++ b/arch/s390/kernel/machine_kexec.c
@@ -1,7 +1,5 @@
 /*
- * arch/s390/kernel/machine_kexec.c
- *
- * Copyright IBM Corp. 2005,2011
+ * Copyright IBM Corp. 2005, 2011
  *
  * Author(s): Rolf Adelsberger,
  *            Heiko Carstens <heiko.carstens@de.ibm.com>
diff --git a/arch/s390/kernel/mcount.S b/arch/s390/kernel/mcount.S
index 7e2c38ba137..4567ce20d90 100644
--- a/arch/s390/kernel/mcount.S
+++ b/arch/s390/kernel/mcount.S
@@ -1,5 +1,5 @@
 /*
- * Copyright IBM Corp. 2008,2009
+ * Copyright IBM Corp. 2008, 2009
  *
  *   Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>,
  *
diff --git a/arch/s390/kernel/mcount64.S b/arch/s390/kernel/mcount64.S
index f70cadec68f..11332193db3 100644
--- a/arch/s390/kernel/mcount64.S
+++ b/arch/s390/kernel/mcount64.S
@@ -1,5 +1,5 @@
 /*
- * Copyright IBM Corp. 2008,2009
+ * Copyright IBM Corp. 2008, 2009
  *
  *   Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>,
  *
diff --git a/arch/s390/kernel/module.c b/arch/s390/kernel/module.c
index dfcb3436bad..46412b1d7e1 100644
--- a/arch/s390/kernel/module.c
+++ b/arch/s390/kernel/module.c
@@ -1,9 +1,8 @@
 /*
- *  arch/s390/kernel/module.c - Kernel module help for s390.
+ *  Kernel module help for s390.
  *
  *  S390 version
- *    Copyright (C) 2002, 2003 IBM Deutschland Entwicklung GmbH,
- *                             IBM Corporation
+ *    Copyright IBM Corp. 2002, 2003
  *    Author(s): Arnd Bergmann (arndb@de.ibm.com)
  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
diff --git a/arch/s390/kernel/nmi.c b/arch/s390/kernel/nmi.c
index 8c372ca6135..a6daa5c5cdb 100644
--- a/arch/s390/kernel/nmi.c
+++ b/arch/s390/kernel/nmi.c
@@ -1,7 +1,7 @@
 /*
  *   Machine check handler
  *
- *    Copyright IBM Corp. 2000,2009
+ *    Copyright IBM Corp. 2000, 2009
  *    Author(s): Ingo Adlung <adlung@de.ibm.com>,
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Cornelia Huck <cornelia.huck@de.ibm.com>,
diff --git a/arch/s390/kernel/os_info.c b/arch/s390/kernel/os_info.c
index 95fa5ac6c4c..46480d81df0 100644
--- a/arch/s390/kernel/os_info.c
+++ b/arch/s390/kernel/os_info.c
@@ -60,7 +60,7 @@ void __init os_info_init(void)
         os_info.version_minor = OS_INFO_VERSION_MINOR;
         os_info.magic = OS_INFO_MAGIC;
         os_info.csum = os_info_csum(&os_info);
-        memcpy_absolute(&S390_lowcore.os_info, &ptr, sizeof(ptr));
+        mem_assign_absolute(S390_lowcore.os_info, (unsigned long) ptr);
 }
 
 #ifdef CONFIG_CRASH_DUMP
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index 60055cefdd0..733175373a4 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -1,7 +1,7 @@
 /*
  * This file handles the architecture dependent parts of process handling.
  *
- *    Copyright IBM Corp. 1999,2009
+ *    Copyright IBM Corp. 1999, 2009
  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Hartmut Penner <hp@de.ibm.com>,
  *               Denis Joseph Barrow,
@@ -25,8 +25,8 @@
 #include <linux/module.h>
 #include <asm/io.h>
 #include <asm/processor.h>
+#include <asm/vtimer.h>
 #include <asm/irq.h>
-#include <asm/timer.h>
 #include <asm/nmi.h>
 #include <asm/smp.h>
 #include <asm/switch_to.h>
diff --git a/arch/s390/kernel/processor.c b/arch/s390/kernel/processor.c
index 6e0073e43f5..572d4c9cb33 100644
--- a/arch/s390/kernel/processor.c
+++ b/arch/s390/kernel/processor.c
@@ -1,6 +1,4 @@
 /*
- *  arch/s390/kernel/processor.c
- *
  *  Copyright IBM Corp. 2008
  *  Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  */
@@ -25,13 +23,15 @@ static DEFINE_PER_CPU(struct cpuid, cpu_id);
  */
 void __cpuinit cpu_init(void)
 {
-        struct cpuid *id = &per_cpu(cpu_id, smp_processor_id());
+        struct s390_idle_data *idle = &__get_cpu_var(s390_idle);
+        struct cpuid *id = &__get_cpu_var(cpu_id);
 
         get_cpu_id(id);
         atomic_inc(&init_mm.mm_count);
         current->active_mm = &init_mm;
         BUG_ON(current->mm);
         enter_lazy_tlb(&init_mm, current);
+        memset(idle, 0, sizeof(*idle));
 }
 
 /*
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index 4993e689b2c..e4be113fbac 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -1,7 +1,7 @@
 /*
  *  Ptrace user space interface.
  *
- *    Copyright IBM Corp. 1999,2010
+ *    Copyright IBM Corp. 1999, 2010
  *    Author(s): Denis Joseph Barrow
  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
  */
@@ -719,7 +719,11 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
         long ret = 0;
 
         /* Do the secure computing check first. */
-        secure_computing_strict(regs->gprs[2]);
+        if (secure_computing(regs->gprs[2])) {
+                /* seccomp failures shouldn't expose any additional code. */
+                ret = -1;
+                goto out;
+        }
 
         /*
          * The sysc_tracesys code in entry.S stored the system
@@ -745,6 +749,7 @@ asmlinkage long do_syscall_trace_enter(struct pt_regs *regs)
                             regs->gprs[2], regs->orig_gpr2,
                             regs->gprs[3], regs->gprs[4],
                             regs->gprs[5]);
+out:
         return ret ?: regs->gprs[2];
 }
 
diff --git a/arch/s390/kernel/reipl.S b/arch/s390/kernel/reipl.S
index ad67c214be0..dd8016b0477 100644
--- a/arch/s390/kernel/reipl.S
+++ b/arch/s390/kernel/reipl.S
@@ -1,13 +1,12 @@
 /*
- *  arch/s390/kernel/reipl.S
- *
  *  S390 version
- *    Copyright (C) 2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 2000
  *    Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com)
  */
 
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
+#include <asm/sigp.h>
 
 #
 # store_status: Empty implementation until kdump is supported on 31 bit
@@ -60,7 +59,7 @@ ENTRY(do_reipl_asm)
                 bas     %r14,.Ldisab-.Lpg0(%r13)
 .L003:          st      %r1,__LC_SUBCHANNEL_ID
                 lpsw    0
-                sigp    0,0,0(6)
+                sigp    0,0,SIGP_RESTART
 .Ldisab:        st      %r14,.Ldispsw+4-.Lpg0(%r13)
                 lpsw    .Ldispsw-.Lpg0(%r13)
                 .align  8
diff --git a/arch/s390/kernel/reipl64.S b/arch/s390/kernel/reipl64.S
index 36b32658fb2..dc3b1273c4d 100644
--- a/arch/s390/kernel/reipl64.S
+++ b/arch/s390/kernel/reipl64.S
@@ -1,11 +1,12 @@
 /*
- *    Copyright IBM Corp 2000,2011
+ *    Copyright IBM Corp 2000, 2011
  *    Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
  *               Denis Joseph Barrow,
  */
 
 #include <linux/linkage.h>
 #include <asm/asm-offsets.h>
+#include <asm/sigp.h>
 
 #
 # store_status
@@ -106,7 +107,7 @@ ENTRY(do_reipl_asm)
 .L003:          st      %r1,__LC_SUBCHANNEL_ID
                 lhi     %r1,0            # mode 0 = esa
                 slr     %r0,%r0          # set cpuid to zero
-                sigp    %r1,%r0,0x12     # switch to esa mode
+                sigp    %r1,%r0,SIGP_SET_ARCHITECTURE # switch to esa mode
                 lpsw    0
 .Ldisab:        sll     %r14,1
                 srl     %r14,1           # need to kill hi bit to avoid specification exceptions.
diff --git a/arch/s390/kernel/relocate_kernel.S b/arch/s390/kernel/relocate_kernel.S
index c91d70aede9..f4e6f20e117 100644
--- a/arch/s390/kernel/relocate_kernel.S
+++ b/arch/s390/kernel/relocate_kernel.S
@@ -1,7 +1,5 @@
 /*
- * arch/s390/kernel/relocate_kernel.S
- *
- * (C) Copyright IBM Corp. 2005
+ * Copyright IBM Corp. 2005
  *
  * Author(s): Rolf Adelsberger,
  *            Heiko Carstens <heiko.carstens@de.ibm.com>
@@ -9,6 +7,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/sigp.h>
 
 /*
  * moves the new kernel to its destination...
@@ -93,7 +92,7 @@ ENTRY(relocate_kernel)
         .no_diag308:
                 sr      %r1,%r1         # clear %r1
                 sr      %r2,%r2         # clear %r2
-                sigp    %r1,%r2,0x12    # set cpuid to zero
+                sigp    %r1,%r2,SIGP_SET_ARCHITECTURE # set cpuid to zero
                 lpsw    0               # hopefully start new kernel...
 
                 .align  8
diff --git a/arch/s390/kernel/relocate_kernel64.S b/arch/s390/kernel/relocate_kernel64.S
index 7c3ce589a7f..cfac28330b0 100644
--- a/arch/s390/kernel/relocate_kernel64.S
+++ b/arch/s390/kernel/relocate_kernel64.S
@@ -1,7 +1,5 @@
 /*
- * arch/s390/kernel/relocate_kernel64.S
- *
- * (C) Copyright IBM Corp. 2005
+ * Copyright IBM Corp. 2005
  *
  * Author(s): Rolf Adelsberger,
  *            Heiko Carstens <heiko.carstens@de.ibm.com>
@@ -9,6 +7,7 @@
  */
 
 #include <linux/linkage.h>
+#include <asm/sigp.h>
 
 /*
  * moves the new kernel to its destination...
@@ -45,7 +44,7 @@ ENTRY(relocate_kernel)
                 diag    %r0,%r0,0x308
         .back:
                 lhi     %r1,1           # mode 1 = esame
-                sigp    %r1,%r0,0x12    # switch to esame mode
+                sigp    %r1,%r0,SIGP_SET_ARCHITECTURE # switch to esame mode
                 sam64                   # switch to 64 bit addressing mode
                 basr    %r13,0
         .back_base:
@@ -96,7 +95,7 @@ ENTRY(relocate_kernel)
                 sam31                   # 31 bit mode
                 sr      %r1,%r1         # erase register r1
                 sr      %r2,%r2         # erase register r2
-                sigp    %r1,%r2,0x12    # set cpuid to zero
+                sigp    %r1,%r2,SIGP_SET_ARCHITECTURE # set cpuid to zero
                 lpsw    0               # hopefully start new kernel...
 
                 .align  8
diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S
index 95792d846bb..bf053898630 100644
--- a/arch/s390/kernel/sclp.S
+++ b/arch/s390/kernel/sclp.S
@@ -1,7 +1,7 @@
 /*
  * Mini SCLP driver.
  *
- * Copyright IBM Corp. 2004,2009
+ * Copyright IBM Corp. 2004, 2009
  *
  *   Author(s): Peter Oberparleiter <Peter.Oberparleiter@de.ibm.com>,
  *              Heiko Carstens <heiko.carstens@de.ibm.com>,
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index 489d1d8d96b..f86c81e13c3 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -1,8 +1,6 @@
 /*
- *  arch/s390/kernel/setup.c
- *
  *  S390 version
- *    Copyright (C) IBM Corp. 1999,2012
+ *    Copyright IBM Corp. 1999, 2012
  *    Author(s): Hartmut Penner (hp@de.ibm.com),
  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
  *
@@ -63,6 +61,7 @@
 #include <asm/kvm_virtio.h>
 #include <asm/diag.h>
 #include <asm/os_info.h>
+#include <asm/sclp.h>
 #include "entry.h"
 
 long psw_kernel_bits    = PSW_DEFAULT_KEY | PSW_MASK_BASE | PSW_ASC_PRIMARY |
@@ -138,9 +137,14 @@ __setup("condev=", condev_setup);
 
 static void __init set_preferred_console(void)
 {
-        if (MACHINE_IS_KVM)
-                add_preferred_console("hvc", 0, NULL);
-        else if (CONSOLE_IS_3215 || CONSOLE_IS_SCLP)
+        if (MACHINE_IS_KVM) {
+                if (sclp_has_vt220())
+                        add_preferred_console("ttyS", 1, NULL);
+                else if (sclp_has_linemode())
+                        add_preferred_console("ttyS", 0, NULL);
+                else
+                        add_preferred_console("hvc", 0, NULL);
+        } else if (CONSOLE_IS_3215 || CONSOLE_IS_SCLP)
                 add_preferred_console("ttyS", 0, NULL);
         else if (CONSOLE_IS_3270)
                 add_preferred_console("tty3270", 0, NULL);
@@ -298,8 +302,8 @@ static int __init parse_vmalloc(char *arg)
 }
 early_param("vmalloc", parse_vmalloc);
 
-unsigned int user_mode = HOME_SPACE_MODE;
-EXPORT_SYMBOL_GPL(user_mode);
+unsigned int addressing_mode = HOME_SPACE_MODE;
+EXPORT_SYMBOL_GPL(addressing_mode);
 
 static int set_amode_primary(void)
 {
@@ -324,7 +328,7 @@ static int set_amode_primary(void)
  */
 static int __init early_parse_switch_amode(char *p)
 {
-        user_mode = PRIMARY_SPACE_MODE;
+        addressing_mode = PRIMARY_SPACE_MODE;
         return 0;
 }
 early_param("switch_amode", early_parse_switch_amode);
@@ -332,9 +336,9 @@ early_param("switch_amode", early_parse_switch_amode);
 static int __init early_parse_user_mode(char *p)
 {
         if (p && strcmp(p, "primary") == 0)
-                user_mode = PRIMARY_SPACE_MODE;
+                addressing_mode = PRIMARY_SPACE_MODE;
         else if (!p || strcmp(p, "home") == 0)
-                user_mode = HOME_SPACE_MODE;
+                addressing_mode = HOME_SPACE_MODE;
         else
                 return 1;
         return 0;
@@ -343,7 +347,7 @@ early_param("user_mode", early_parse_user_mode);
 
 static void setup_addressing_mode(void)
 {
-        if (user_mode == PRIMARY_SPACE_MODE) {
+        if (addressing_mode == PRIMARY_SPACE_MODE) {
                 if (set_amode_primary())
                         pr_info("Address spaces switched, "
                                 "mvcos available\n");
@@ -430,10 +434,11 @@ static void __init setup_lowcore(void)
         lc->restart_source = -1UL;
 
         /* Setup absolute zero lowcore */
-        memcpy_absolute(&S390_lowcore.restart_stack, &lc->restart_stack,
-                        4 * sizeof(unsigned long));
-        memcpy_absolute(&S390_lowcore.restart_psw, &lc->restart_psw,
-                        sizeof(lc->restart_psw));
+        mem_assign_absolute(S390_lowcore.restart_stack, lc->restart_stack);
+        mem_assign_absolute(S390_lowcore.restart_fn, lc->restart_fn);
+        mem_assign_absolute(S390_lowcore.restart_data, lc->restart_data);
+        mem_assign_absolute(S390_lowcore.restart_source, lc->restart_source);
+        mem_assign_absolute(S390_lowcore.restart_psw, lc->restart_psw);
 
         set_prefix((u32)(unsigned long) lc);
         lowcore_ptr[0] = lc;
@@ -598,9 +603,7 @@ static void __init setup_memory_end(void)
 static void __init setup_vmcoreinfo(void)
 {
 #ifdef CONFIG_KEXEC
-        unsigned long ptr = paddr_vmcoreinfo_note();
-
-        memcpy_absolute(&S390_lowcore.vmcore_info, &ptr, sizeof(ptr));
+        mem_assign_absolute(S390_lowcore.vmcore_info, paddr_vmcoreinfo_note());
 #endif
 }
 
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index ac565b44aab..c13a2a37ef0 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -1,7 +1,5 @@
 /*
- *  arch/s390/kernel/signal.c
- *
- *    Copyright (C) IBM Corp. 1999,2006
+ *    Copyright IBM Corp. 1999, 2006
  *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
  *
  *    Based on Intel version
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 15cca26ccb6..720fda1620f 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -1,7 +1,7 @@
 /*
  *  SMP related functions
  *
- *    Copyright IBM Corp. 1999,2012
+ *    Copyright IBM Corp. 1999, 2012
  *    Author(s): Denis Joseph Barrow,
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Heiko Carstens <heiko.carstens@de.ibm.com>,
@@ -38,40 +38,16 @@
 #include <asm/setup.h>
 #include <asm/irq.h>
 #include <asm/tlbflush.h>
-#include <asm/timer.h>
+#include <asm/vtimer.h>
 #include <asm/lowcore.h>
 #include <asm/sclp.h>
 #include <asm/vdso.h>
 #include <asm/debug.h>
 #include <asm/os_info.h>
+#include <asm/sigp.h>
 #include "entry.h"
 
 enum {
-        sigp_sense = 1,
-        sigp_external_call = 2,
-        sigp_emergency_signal = 3,
-        sigp_start = 4,
-        sigp_stop = 5,
-        sigp_restart = 6,
-        sigp_stop_and_store_status = 9,
-        sigp_initial_cpu_reset = 11,
-        sigp_cpu_reset = 12,
-        sigp_set_prefix = 13,
-        sigp_store_status_at_address = 14,
-        sigp_store_extended_status_at_address = 15,
-        sigp_set_architecture = 18,
-        sigp_conditional_emergency_signal = 19,
-        sigp_sense_running = 21,
-};
-
-enum {
-        sigp_order_code_accepted = 0,
-        sigp_status_stored = 1,
-        sigp_busy = 2,
-        sigp_not_operational = 3,
-};
-
-enum {
         ec_schedule = 0,
         ec_call_function,
         ec_call_function_single,
@@ -124,7 +100,7 @@ static inline int __pcpu_sigp_relax(u16 addr, u8 order, u32 parm, u32 *status)
 
         while (1) {
                 cc = __pcpu_sigp(addr, order, parm, status);
-                if (cc != sigp_busy)
+                if (cc != SIGP_CC_BUSY)
                         return cc;
                 cpu_relax();
         }
@@ -136,7 +112,7 @@ static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
 
         for (retry = 0; ; retry++) {
                 cc = __pcpu_sigp(pcpu->address, order, parm, &pcpu->status);
-                if (cc != sigp_busy)
+                if (cc != SIGP_CC_BUSY)
                         break;
                 if (retry >= 3)
                         udelay(10);
@@ -146,20 +122,19 @@ static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
 
 static inline int pcpu_stopped(struct pcpu *pcpu)
 {
-        if (__pcpu_sigp(pcpu->address, sigp_sense,
-                        0, &pcpu->status) != sigp_status_stored)
+        if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
+                        0, &pcpu->status) != SIGP_CC_STATUS_STORED)
                 return 0;
-        /* Check for stopped and check stop state */
-        return !!(pcpu->status & 0x50);
+        return !!(pcpu->status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
 }
 
 static inline int pcpu_running(struct pcpu *pcpu)
 {
-        if (__pcpu_sigp(pcpu->address, sigp_sense_running,
-                        0, &pcpu->status) != sigp_status_stored)
+        if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
+                        0, &pcpu->status) != SIGP_CC_STATUS_STORED)
                 return 1;
-        /* Check for running status */
-        return !(pcpu->status & 0x400);
+        /* Status stored condition code is equivalent to cpu not running. */
+        return 0;
 }
 
 /*
@@ -181,7 +156,7 @@ static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
 
         set_bit(ec_bit, &pcpu->ec_mask);
         order = pcpu_running(pcpu) ?
-                sigp_external_call : sigp_emergency_signal;
+                SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
         pcpu_sigp_retry(pcpu, order, 0);
 }
 
@@ -214,7 +189,7 @@ static int __cpuinit pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
                 goto out;
 #endif
         lowcore_ptr[cpu] = lc;
-        pcpu_sigp_retry(pcpu, sigp_set_prefix, (u32)(unsigned long) lc);
+        pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, (u32)(unsigned long) lc);
         return 0;
 out:
         if (pcpu != &pcpu_devices[0]) {
@@ -229,7 +204,7 @@ out:
 
 static void pcpu_free_lowcore(struct pcpu *pcpu)
 {
-        pcpu_sigp_retry(pcpu, sigp_set_prefix, 0);
+        pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
         lowcore_ptr[pcpu - pcpu_devices] = NULL;
 #ifndef CONFIG_64BIT
         if (MACHINE_HAS_IEEE) {
@@ -288,7 +263,7 @@ static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
         lc->restart_fn = (unsigned long) func;
         lc->restart_data = (unsigned long) data;
         lc->restart_source = -1UL;
-        pcpu_sigp_retry(pcpu, sigp_restart, 0);
+        pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
 }
 
 /*
@@ -298,26 +273,26 @@ static void pcpu_delegate(struct pcpu *pcpu, void (*func)(void *),
                           void *data, unsigned long stack)
 {
         struct _lowcore *lc = lowcore_ptr[pcpu - pcpu_devices];
-        struct {
-                unsigned long   stack;
-                void            *func;
-                void            *data;
-                unsigned long   source;
-        } restart = { stack, func, data, stap() };
+        unsigned long source_cpu = stap();
 
         __load_psw_mask(psw_kernel_bits);
-        if (pcpu->address == restart.source)
+        if (pcpu->address == source_cpu)
                 func(data);     /* should not return */
         /* Stop target cpu (if func returns this stops the current cpu). */
-        pcpu_sigp_retry(pcpu, sigp_stop, 0);
+        pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
         /* Restart func on the target cpu and stop the current cpu. */
-        memcpy_absolute(&lc->restart_stack, &restart, sizeof(restart));
+        mem_assign_absolute(lc->restart_stack, stack);
+        mem_assign_absolute(lc->restart_fn, (unsigned long) func);
+        mem_assign_absolute(lc->restart_data, (unsigned long) data);
+        mem_assign_absolute(lc->restart_source, source_cpu);
         asm volatile(
-                "0:     sigp    0,%0,6  # sigp restart to target cpu\n"
+                "0:     sigp    0,%0,%2 # sigp restart to target cpu\n"
                 "       brc     2,0b    # busy, try again\n"
-                "1:     sigp    0,%1,5  # sigp stop to current cpu\n"
+                "1:     sigp    0,%1,%3 # sigp stop to current cpu\n"
                 "       brc     2,1b    # busy, try again\n"
-                : : "d" (pcpu->address), "d" (restart.source) : "0", "1", "cc");
+                : : "d" (pcpu->address), "d" (source_cpu),
+                    "K" (SIGP_RESTART), "K" (SIGP_STOP)
+                : "0", "1", "cc");
         for (;;) ;
 }
 
@@ -388,8 +363,8 @@ void smp_emergency_stop(cpumask_t *cpumask)
         for_each_cpu(cpu, cpumask) {
                 struct pcpu *pcpu = pcpu_devices + cpu;
                 set_bit(ec_stop_cpu, &pcpu->ec_mask);
-                while (__pcpu_sigp(pcpu->address, sigp_emergency_signal,
-                                   0, NULL) == sigp_busy &&
+                while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
+                                   0, NULL) == SIGP_CC_BUSY &&
                        get_clock() < end)
                         cpu_relax();
         }
@@ -425,7 +400,7 @@ void smp_send_stop(void)
         /* stop all processors */
         for_each_cpu(cpu, &cpumask) {
                 struct pcpu *pcpu = pcpu_devices + cpu;
-                pcpu_sigp_retry(pcpu, sigp_stop, 0);
+                pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
                 while (!pcpu_stopped(pcpu))
                         cpu_relax();
         }
@@ -436,7 +411,7 @@ void smp_send_stop(void)
  */
 void smp_stop_cpu(void)
 {
-        pcpu_sigp_retry(pcpu_devices + smp_processor_id(), sigp_stop, 0);
+        pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
         for (;;) ;
 }
 
@@ -590,7 +565,7 @@ static void __init smp_get_save_area(int cpu, u16 address)
         }
 #endif
         /* Get the registers of a non-boot cpu. */
-        __pcpu_sigp_relax(address, sigp_stop_and_store_status, 0, NULL);
+        __pcpu_sigp_relax(address, SIGP_STOP_AND_STORE_STATUS, 0, NULL);
         memcpy_real(save_area, lc + SAVE_AREA_BASE, sizeof(*save_area));
 }
 
@@ -599,8 +574,8 @@ int smp_store_status(int cpu)
         struct pcpu *pcpu;
 
         pcpu = pcpu_devices + cpu;
-        if (__pcpu_sigp_relax(pcpu->address, sigp_stop_and_store_status,
-                              0, NULL) != sigp_order_code_accepted)
+        if (__pcpu_sigp_relax(pcpu->address, SIGP_STOP_AND_STORE_STATUS,
+                              0, NULL) != SIGP_CC_ORDER_CODE_ACCEPTED)
                 return -EIO;
         return 0;
 }
@@ -621,8 +596,8 @@ static struct sclp_cpu_info *smp_get_cpu_info(void)
         if (info && (use_sigp_detection || sclp_get_cpu_info(info))) {
                 use_sigp_detection = 1;
                 for (address = 0; address <= MAX_CPU_ADDRESS; address++) {
-                        if (__pcpu_sigp_relax(address, sigp_sense, 0, NULL) ==
-                            sigp_not_operational)
+                        if (__pcpu_sigp_relax(address, SIGP_SENSE, 0, NULL) ==
+                            SIGP_CC_NOT_OPERATIONAL)
                                 continue;
                         info->cpu[info->configured].address = address;
                         info->configured++;
@@ -717,9 +692,7 @@ static void __cpuinit smp_start_secondary(void *cpuvoid)
         init_cpu_vtimer();
         pfault_init();
         notify_cpu_starting(smp_processor_id());
-        ipi_call_lock();
         set_cpu_online(smp_processor_id(), true);
-        ipi_call_unlock();
         local_irq_enable();
         /* cpu_idle will call schedule for us */
         cpu_idle();
@@ -734,8 +707,8 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
         pcpu = pcpu_devices + cpu;
         if (pcpu->state != CPU_STATE_CONFIGURED)
                 return -EIO;
-        if (pcpu_sigp_retry(pcpu, sigp_initial_cpu_reset, 0) !=
-            sigp_order_code_accepted)
+        if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) !=
+            SIGP_CC_ORDER_CODE_ACCEPTED)
                 return -EIO;
 
         rc = pcpu_alloc_lowcore(pcpu, cpu);
@@ -795,7 +768,7 @@ void __cpu_die(unsigned int cpu)
 void __noreturn cpu_die(void)
 {
         idle_task_exit();
-        pcpu_sigp_retry(pcpu_devices + smp_processor_id(), sigp_stop, 0);
+        pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
         for (;;) ;
 }
 
@@ -942,7 +915,7 @@ static ssize_t show_idle_count(struct device *dev,
         do {
                 sequence = ACCESS_ONCE(idle->sequence);
                 idle_count = ACCESS_ONCE(idle->idle_count);
-                if (ACCESS_ONCE(idle->idle_enter))
+                if (ACCESS_ONCE(idle->clock_idle_enter))
                         idle_count++;
         } while ((sequence & 1) || (idle->sequence != sequence));
         return sprintf(buf, "%llu\n", idle_count);
@@ -960,8 +933,8 @@ static ssize_t show_idle_time(struct device *dev,
                 now = get_clock();
                 sequence = ACCESS_ONCE(idle->sequence);
                 idle_time = ACCESS_ONCE(idle->idle_time);
-                idle_enter = ACCESS_ONCE(idle->idle_enter);
-                idle_exit = ACCESS_ONCE(idle->idle_exit);
+                idle_enter = ACCESS_ONCE(idle->clock_idle_enter);
+                idle_exit = ACCESS_ONCE(idle->clock_idle_exit);
         } while ((sequence & 1) || (idle->sequence != sequence));
         idle_time += idle_enter ? ((idle_exit ? : now) - idle_enter) : 0;
         return sprintf(buf, "%llu\n", idle_time >> 12);
@@ -984,14 +957,11 @@ static int __cpuinit smp_cpu_notify(struct notifier_block *self,
         unsigned int cpu = (unsigned int)(long)hcpu;
         struct cpu *c = &pcpu_devices[cpu].cpu;
         struct device *s = &c->dev;
-        struct s390_idle_data *idle;
         int err = 0;
 
         switch (action) {
         case CPU_ONLINE:
         case CPU_ONLINE_FROZEN:
-                idle = &per_cpu(s390_idle, cpu);
-                memset(idle, 0, sizeof(struct s390_idle_data));
                 err = sysfs_create_group(&s->kobj, &cpu_online_attr_group);
                 break;
         case CPU_DEAD:
diff --git a/arch/s390/kernel/stacktrace.c b/arch/s390/kernel/stacktrace.c
index 8841919ef7e..1785cd82253 100644
--- a/arch/s390/kernel/stacktrace.c
+++ b/arch/s390/kernel/stacktrace.c
@@ -1,9 +1,7 @@
 /*
- * arch/s390/kernel/stacktrace.c
- *
  * Stack trace management functions
  *
- *  Copyright (C) IBM Corp. 2006
+ *  Copyright IBM Corp. 2006
  *  Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
  */
 
diff --git a/arch/s390/kernel/swsusp_asm64.S b/arch/s390/kernel/swsusp_asm64.S
index dd70ef04605..d4ca4e0617b 100644
--- a/arch/s390/kernel/swsusp_asm64.S
+++ b/arch/s390/kernel/swsusp_asm64.S
@@ -12,6 +12,7 @@
 #include <asm/ptrace.h>
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
+#include <asm/sigp.h>
 
 /*
  * Save register context in absolute 0 lowcore and call swsusp_save() to
@@ -163,7 +164,7 @@ ENTRY(swsusp_arch_resume)
         diag    %r0,%r0,0x308
 restart_entry:
         lhi     %r1,1
-        sigp    %r1,%r0,0x12
+        sigp    %r1,%r0,SIGP_SET_ARCHITECTURE
         sam64
         larl    %r1,.Lnew_pgm_check_psw
         lpswe   0(%r1)
@@ -179,7 +180,7 @@ pgm_check_entry:
         larl    %r4,.Lrestart_suspend_psw       /* Set new restart PSW */
         mvc     __LC_RST_NEW_PSW(16,%r0),0(%r4)
 3:
-        sigp    %r9,%r1,11                      /* sigp initial cpu reset */
+        sigp    %r9,%r1,SIGP_INITIAL_CPU_RESET  /* sigp initial cpu reset */
         brc     8,4f                            /* accepted */
         brc     2,3b                            /* busy, try again */
 
@@ -190,16 +191,16 @@ pgm_check_entry:
         larl    %r3,_sclp_print_early
         lghi    %r1,0
         sam31
-        sigp    %r1,%r0,0x12
+        sigp    %r1,%r0,SIGP_SET_ARCHITECTURE
         basr    %r14,%r3
         larl    %r3,.Ldisabled_wait_31
         lpsw    0(%r3)
 4:
         /* Switch to suspend CPU */
-        sigp    %r9,%r1,6               /* sigp restart to suspend CPU */
+        sigp    %r9,%r1,SIGP_RESTART    /* sigp restart to suspend CPU */
         brc     2,4b                    /* busy, try again */
 5:
-        sigp    %r9,%r2,5               /* sigp stop to current resume CPU */
+        sigp    %r9,%r2,SIGP_STOP       /* sigp stop to current resume CPU */
         brc     2,5b                    /* busy, try again */
 6:      j       6b
 
@@ -207,7 +208,7 @@ restart_suspend:
         larl    %r1,.Lresume_cpu
         llgh    %r2,0(%r1)
 7:
-        sigp    %r9,%r2,1               /* sigp sense, wait for resume CPU */
+        sigp    %r9,%r2,SIGP_SENSE      /* sigp sense, wait for resume CPU */
         brc     8,7b                    /* accepted, status 0, still running */
         brc     2,7b                    /* busy, try again */
         tmll    %r9,0x40                /* Test if resume CPU is stopped */
diff --git a/arch/s390/kernel/sys_s390.c b/arch/s390/kernel/sys_s390.c
index 78ea1948ff5..d0964d22adb 100644
--- a/arch/s390/kernel/sys_s390.c
+++ b/arch/s390/kernel/sys_s390.c
@@ -1,8 +1,6 @@
 /*
- *  arch/s390/kernel/sys_s390.c
- *
  *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2000
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Thomas Spatzier (tspat@de.ibm.com)
  *
@@ -83,11 +81,12 @@ SYSCALL_DEFINE1(s390_personality, unsigned int, personality)
 {
         unsigned int ret;
 
-        if (current->personality == PER_LINUX32 && personality == PER_LINUX)
-                personality = PER_LINUX32;
+        if (personality(current->personality) == PER_LINUX32 &&
+            personality(personality) == PER_LINUX)
+                personality |= PER_LINUX32;
         ret = sys_personality(personality);
-        if (ret == PER_LINUX32)
-                ret = PER_LINUX;
+        if (personality(ret) == PER_LINUX32)
+                ret &= ~PER_LINUX32;
 
         return ret;
 }
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index d4e1cb1dbcd..dcec960fc72 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -1,5 +1,4 @@
 /*
- *  arch/s390/kernel/time.c
  *    Time of day based timer functions.
  *
  *  S390 version
@@ -45,7 +44,7 @@
 #include <asm/vdso.h>
 #include <asm/irq.h>
 #include <asm/irq_regs.h>
-#include <asm/timer.h>
+#include <asm/vtimer.h>
 #include <asm/etr.h>
 #include <asm/cio.h>
 #include "entry.h"
diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
index 4f8dc942257..05151e06c38 100644
--- a/arch/s390/kernel/topology.c
+++ b/arch/s390/kernel/topology.c
@@ -1,5 +1,5 @@
 /*
- *    Copyright IBM Corp. 2007,2011
+ *    Copyright IBM Corp. 2007, 2011
  *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
  */
 
diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c
index 77cdf4234eb..01775c04a90 100644
--- a/arch/s390/kernel/traps.c
+++ b/arch/s390/kernel/traps.c
@@ -1,8 +1,6 @@
 /*
- *  arch/s390/kernel/traps.c
- *
  *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2000
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
  *
@@ -187,7 +185,7 @@ void show_registers(struct pt_regs *regs)
 {
         char *mode;
 
-        mode = (regs->psw.mask & PSW_MASK_PSTATE) ? "User" : "Krnl";
+        mode = user_mode(regs) ? "User" : "Krnl";
         printk("%s PSW : %p %p",
                mode, (void *) regs->psw.mask,
                (void *) regs->psw.addr);
@@ -227,7 +225,7 @@ void show_regs(struct pt_regs *regs)
                (void *) current->thread.ksp);
         show_registers(regs);
         /* Show stack backtrace if pt_regs is from kernel mode */
-        if (!(regs->psw.mask & PSW_MASK_PSTATE))
+        if (!user_mode(regs))
                 show_trace(NULL, (unsigned long *) regs->gprs[15]);
         show_last_breaking_event(regs);
 }
@@ -302,7 +300,7 @@ static void __kprobes do_trap(struct pt_regs *regs,
                        regs->int_code, si_signo) == NOTIFY_STOP)
                 return;
 
-        if (regs->psw.mask & PSW_MASK_PSTATE) {
+        if (user_mode(regs)) {
                 info.si_signo = si_signo;
                 info.si_errno = 0;
                 info.si_code = si_code;
@@ -343,7 +341,7 @@ void __kprobes do_per_trap(struct pt_regs *regs)
 
 static void default_trap_handler(struct pt_regs *regs)
 {
-        if (regs->psw.mask & PSW_MASK_PSTATE) {
+        if (user_mode(regs)) {
                 report_user_fault(regs, SIGSEGV);
                 do_exit(SIGSEGV);
         } else
@@ -412,7 +410,7 @@ static void __kprobes illegal_op(struct pt_regs *regs)
 
         location = get_psw_address(regs);
 
-        if (regs->psw.mask & PSW_MASK_PSTATE) {
+        if (user_mode(regs)) {
                 if (get_user(*((__u16 *) opcode), (__u16 __user *) location))
                         return;
                 if (*((__u16 *) opcode) == S390_BREAKPOINT_U16) {
@@ -480,7 +478,7 @@ void specification_exception(struct pt_regs *regs)
 
         location = (__u16 __user *) get_psw_address(regs);
 
-        if (regs->psw.mask & PSW_MASK_PSTATE) {
+        if (user_mode(regs)) {
                 get_user(*((__u16 *) opcode), location);
                 switch (opcode[0]) {
                 case 0x28: /* LDR Rx,Ry   */
@@ -533,7 +531,7 @@ static void data_exception(struct pt_regs *regs)
                 asm volatile("stfpc %0" : "=m" (current->thread.fp_regs.fpc));
 
 #ifdef CONFIG_MATHEMU
-        else if (regs->psw.mask & PSW_MASK_PSTATE) {
+        else if (user_mode(regs)) {
                 __u8 opcode[6];
                 get_user(*((__u16 *) opcode), location);
                 switch (opcode[0]) {
@@ -600,7 +598,7 @@ static void data_exception(struct pt_regs *regs)
 static void space_switch_exception(struct pt_regs *regs)
 {
         /* Set user psw back to home space mode. */
-        if (regs->psw.mask & PSW_MASK_PSTATE)
+        if (user_mode(regs))
                 regs->psw.mask |= PSW_ASC_HOME;
         /* Send SIGILL. */
         do_trap(regs, SIGILL, ILL_PRVOPC, "space switch event");
diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c
index ea5590fdca3..9a19ca367c1 100644
--- a/arch/s390/kernel/vdso.c
+++ b/arch/s390/kernel/vdso.c
@@ -84,7 +84,8 @@ struct vdso_data *vdso_data = &vdso_data_store.data;
  */
 static void vdso_init_data(struct vdso_data *vd)
 {
-        vd->ectg_available = user_mode != HOME_SPACE_MODE && test_facility(31);
+        vd->ectg_available =
+                addressing_mode != HOME_SPACE_MODE && test_facility(31);
 }
 
 #ifdef CONFIG_64BIT
@@ -101,7 +102,7 @@ int vdso_alloc_per_cpu(struct _lowcore *lowcore)
 
         lowcore->vdso_per_cpu_data = __LC_PASTE;
 
-        if (user_mode == HOME_SPACE_MODE || !vdso_enabled)
+        if (addressing_mode == HOME_SPACE_MODE || !vdso_enabled)
                 return 0;
 
         segment_table = __get_free_pages(GFP_KERNEL, SEGMENT_ORDER);
@@ -146,7 +147,7 @@ void vdso_free_per_cpu(struct _lowcore *lowcore)
         unsigned long segment_table, page_table, page_frame;
         u32 *psal, *aste;
 
-        if (user_mode == HOME_SPACE_MODE || !vdso_enabled)
+        if (addressing_mode == HOME_SPACE_MODE || !vdso_enabled)
                 return;
 
         psal = (u32 *)(addr_t) lowcore->paste[4];
@@ -164,7 +165,7 @@ static void vdso_init_cr5(void)
 {
         unsigned long cr5;
 
-        if (user_mode == HOME_SPACE_MODE || !vdso_enabled)
+        if (addressing_mode == HOME_SPACE_MODE || !vdso_enabled)
                 return;
         cr5 = offsetof(struct _lowcore, paste);
         __ctl_load(cr5, 5, 5);
diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S
index 21109c63eb1..de8fa9bbd35 100644
--- a/arch/s390/kernel/vmlinux.lds.S
+++ b/arch/s390/kernel/vmlinux.lds.S
@@ -45,7 +45,7 @@ SECTIONS
 
         .dummy : { *(.dummy) } :data
 
-        RODATA
+        RO_DATA_SECTION(PAGE_SIZE)
 
 #ifdef CONFIG_SHARED_KERNEL
         . = ALIGN(0x100000);    /* VM shared segments are 1MB aligned */
diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c
index 39ebff50694..4fc97b40a6e 100644
--- a/arch/s390/kernel/vtime.c
+++ b/arch/s390/kernel/vtime.c
@@ -1,71 +1,82 @@
 /*
- *  arch/s390/kernel/vtime.c
  *    Virtual cpu timer based timer functions.
  *
- *  S390 version
- *    Copyright (C) 2004 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 2004, 2012
  *    Author(s): Jan Glauber <jan.glauber@de.ibm.com>
  */
 
-#include <linux/module.h>
+#include <linux/kernel_stat.h>
+#include <linux/notifier.h>
+#include <linux/kprobes.h>
+#include <linux/export.h>
 #include <linux/kernel.h>
-#include <linux/time.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/types.h>
 #include <linux/timex.h>
-#include <linux/notifier.h>
-#include <linux/kernel_stat.h>
-#include <linux/rcupdate.h>
-#include <linux/posix-timers.h>
+#include <linux/types.h>
+#include <linux/time.h>
 #include <linux/cpu.h>
-#include <linux/kprobes.h>
+#include <linux/smp.h>
 
-#include <asm/timer.h>
 #include <asm/irq_regs.h>
 #include <asm/cputime.h>
+#include <asm/vtimer.h>
 #include <asm/irq.h>
 #include "entry.h"
 
-static DEFINE_PER_CPU(struct vtimer_queue, virt_cpu_timer);
+static void virt_timer_expire(void);
 
 DEFINE_PER_CPU(struct s390_idle_data, s390_idle);
 
-static inline __u64 get_vtimer(void)
+static LIST_HEAD(virt_timer_list);
+static DEFINE_SPINLOCK(virt_timer_lock);
+static atomic64_t virt_timer_current;
+static atomic64_t virt_timer_elapsed;
+
+static inline u64 get_vtimer(void)
 {
-        __u64 timer;
+        u64 timer;
 
-        asm volatile("STPT %0" : "=m" (timer));
+        asm volatile("stpt %0" : "=m" (timer));
         return timer;
 }
 
-static inline void set_vtimer(__u64 expires)
+static inline void set_vtimer(u64 expires)
 {
-        __u64 timer;
+        u64 timer;
 
-        asm volatile ("  STPT %0\n"  /* Store current cpu timer value */
-                      "  SPT %1"     /* Set new value immediately afterwards */
-                      : "=m" (timer) : "m" (expires) );
+        asm volatile(
+                "       stpt    %0\n"   /* Store current cpu timer value */
+                "       spt     %1"     /* Set new value imm. afterwards */
+                : "=m" (timer) : "m" (expires));
         S390_lowcore.system_timer += S390_lowcore.last_update_timer - timer;
         S390_lowcore.last_update_timer = expires;
 }
 
+static inline int virt_timer_forward(u64 elapsed)
+{
+        BUG_ON(!irqs_disabled());
+
+        if (list_empty(&virt_timer_list))
+                return 0;
+        elapsed = atomic64_add_return(elapsed, &virt_timer_elapsed);
+        return elapsed >= atomic64_read(&virt_timer_current);
+}
+
 /*
  * Update process times based on virtual cpu times stored by entry.S
  * to the lowcore fields user_timer, system_timer & steal_clock.
  */
-static void do_account_vtime(struct task_struct *tsk, int hardirq_offset)
+static int do_account_vtime(struct task_struct *tsk, int hardirq_offset)
 {
         struct thread_info *ti = task_thread_info(tsk);
-        __u64 timer, clock, user, system, steal;
+        u64 timer, clock, user, system, steal;
 
         timer = S390_lowcore.last_update_timer;
         clock = S390_lowcore.last_update_clock;
-        asm volatile ("  STPT %0\n"    /* Store current cpu timer value */
-                      "  STCK %1"      /* Store current tod clock value */
-                      : "=m" (S390_lowcore.last_update_timer),
-                        "=m" (S390_lowcore.last_update_clock) );
+        asm volatile(
+                "       stpt    %0\n"   /* Store current cpu timer value */
+                "       stck    %1"     /* Store current tod clock value */
+                : "=m" (S390_lowcore.last_update_timer),
+                  "=m" (S390_lowcore.last_update_clock));
         S390_lowcore.system_timer += timer - S390_lowcore.last_update_timer;
         S390_lowcore.steal_timer += S390_lowcore.last_update_clock - clock;
 
@@ -84,6 +95,8 @@ static void do_account_vtime(struct task_struct *tsk, int hardirq_offset)
                 S390_lowcore.steal_timer = 0;
                 account_steal_time(steal);
         }
+
+        return virt_timer_forward(user + system);
 }
 
 void account_vtime(struct task_struct *prev, struct task_struct *next)
@@ -101,7 +114,8 @@ void account_vtime(struct task_struct *prev, struct task_struct *next)
 
 void account_process_tick(struct task_struct *tsk, int user_tick)
 {
-        do_account_vtime(tsk, HARDIRQ_OFFSET);
+        if (do_account_vtime(tsk, HARDIRQ_OFFSET))
+                virt_timer_expire();
 }
 
 /*
@@ -111,7 +125,7 @@ void account_process_tick(struct task_struct *tsk, int user_tick)
 void account_system_vtime(struct task_struct *tsk)
 {
         struct thread_info *ti = task_thread_info(tsk);
-        __u64 timer, system;
+        u64 timer, system;
 
         timer = S390_lowcore.last_update_timer;
         S390_lowcore.last_update_timer = get_vtimer();
@@ -121,13 +135,14 @@ void account_system_vtime(struct task_struct *tsk)
         S390_lowcore.steal_timer -= system;
         ti->system_timer = S390_lowcore.system_timer;
         account_system_time(tsk, 0, system, system);
+
+        virt_timer_forward(system);
 }
 EXPORT_SYMBOL_GPL(account_system_vtime);
 
 void __kprobes vtime_stop_cpu(void)
 {
         struct s390_idle_data *idle = &__get_cpu_var(s390_idle);
-        struct vtimer_queue *vq = &__get_cpu_var(virt_cpu_timer);
         unsigned long long idle_time;
         unsigned long psw_mask;
 
@@ -141,7 +156,7 @@ void __kprobes vtime_stop_cpu(void)
         idle->nohz_delay = 0;
 
         /* Call the assembler magic in entry.S */
-        psw_idle(idle, vq, psw_mask, !list_empty(&vq->list));
+        psw_idle(idle, psw_mask);
 
         /* Reenable preemption tracer. */
         start_critical_timings();
@@ -149,9 +164,9 @@ void __kprobes vtime_stop_cpu(void)
         /* Account time spent with enabled wait psw loaded as idle time. */
         idle->sequence++;
         smp_wmb();
-        idle_time = idle->idle_exit - idle->idle_enter;
+        idle_time = idle->clock_idle_exit - idle->clock_idle_enter;
+        idle->clock_idle_enter = idle->clock_idle_exit = 0ULL;
         idle->idle_time += idle_time;
-        idle->idle_enter = idle->idle_exit = 0ULL;
         idle->idle_count++;
         account_idle_time(idle_time);
         smp_wmb();
@@ -167,10 +182,10 @@ cputime64_t s390_get_idle_time(int cpu)
         do {
                 now = get_clock();
                 sequence = ACCESS_ONCE(idle->sequence);
-                idle_enter = ACCESS_ONCE(idle->idle_enter);
-                idle_exit = ACCESS_ONCE(idle->idle_exit);
+                idle_enter = ACCESS_ONCE(idle->clock_idle_enter);
+                idle_exit = ACCESS_ONCE(idle->clock_idle_exit);
         } while ((sequence & 1) || (idle->sequence != sequence));
-        return idle_enter ? ((idle_exit ? : now) - idle_enter) : 0;
+        return idle_enter ? ((idle_exit ?: now) - idle_enter) : 0;
 }
 
 /*
@@ -179,11 +194,11 @@ cputime64_t s390_get_idle_time(int cpu)
  */
 static void list_add_sorted(struct vtimer_list *timer, struct list_head *head)
 {
-        struct vtimer_list *event;
+        struct vtimer_list *tmp;
 
-        list_for_each_entry(event, head, entry) {
-                if (event->expires > timer->expires) {
-                        list_add_tail(&timer->entry, &event->entry);
+        list_for_each_entry(tmp, head, entry) {
+                if (tmp->expires > timer->expires) {
+                        list_add_tail(&timer->entry, &tmp->entry);
                         return;
                 }
         }
@@ -191,82 +206,45 @@ static void list_add_sorted(struct vtimer_list *timer, struct list_head *head)
 }
 
 /*
- * Do the callback functions of expired vtimer events.
- * Called from within the interrupt handler.
- */
-static void do_callbacks(struct list_head *cb_list)
-{
-        struct vtimer_queue *vq;
-        struct vtimer_list *event, *tmp;
-
-        if (list_empty(cb_list))
-                return;
-
-        vq = &__get_cpu_var(virt_cpu_timer);
-
-        list_for_each_entry_safe(event, tmp, cb_list, entry) {
-                list_del_init(&event->entry);
-                (event->function)(event->data);
-                if (event->interval) {
-                        /* Recharge interval timer */
-                        event->expires = event->interval + vq->elapsed;
-                        spin_lock(&vq->lock);
-                        list_add_sorted(event, &vq->list);
-                        spin_unlock(&vq->lock);
-                }
-        }
-}
-
-/*
- * Handler for the virtual CPU timer.
+ * Handler for expired virtual CPU timer.
  */
-static void do_cpu_timer_interrupt(struct ext_code ext_code,
-                                   unsigned int param32, unsigned long param64)
+static void virt_timer_expire(void)
 {
-        struct vtimer_queue *vq;
-        struct vtimer_list *event, *tmp;
-        struct list_head cb_list;       /* the callback queue */
-        __u64 elapsed, next;
-
-        kstat_cpu(smp_processor_id()).irqs[EXTINT_TMR]++;
-        INIT_LIST_HEAD(&cb_list);
-        vq = &__get_cpu_var(virt_cpu_timer);
-
-        /* walk timer list, fire all expired events */
-        spin_lock(&vq->lock);
-
-        elapsed = vq->elapsed + (vq->timer - S390_lowcore.async_enter_timer);
-        BUG_ON((s64) elapsed < 0);
-        vq->elapsed = 0;
-        list_for_each_entry_safe(event, tmp, &vq->list, entry) {
-                if (event->expires < elapsed)
+        struct vtimer_list *timer, *tmp;
+        unsigned long elapsed;
+        LIST_HEAD(cb_list);
+
+        /* walk timer list, fire all expired timers */
+        spin_lock(&virt_timer_lock);
+        elapsed = atomic64_read(&virt_timer_elapsed);
+        list_for_each_entry_safe(timer, tmp, &virt_timer_list, entry) {
+                if (timer->expires < elapsed)
                         /* move expired timer to the callback queue */
-                        list_move_tail(&event->entry, &cb_list);
+                        list_move_tail(&timer->entry, &cb_list);
                 else
-                        event->expires -= elapsed;
+                        timer->expires -= elapsed;
         }
-        spin_unlock(&vq->lock);
-
-        do_callbacks(&cb_list);
-
-        /* next event is first in list */
-        next = VTIMER_MAX_SLICE;
-        spin_lock(&vq->lock);
-        if (!list_empty(&vq->list)) {
-                event = list_first_entry(&vq->list, struct vtimer_list, entry);
-                next = event->expires;
+        if (!list_empty(&virt_timer_list)) {
+                timer = list_first_entry(&virt_timer_list,
+                                         struct vtimer_list, entry);
+                atomic64_set(&virt_timer_current, timer->expires);
+        }
+        atomic64_sub(elapsed, &virt_timer_elapsed);
+        spin_unlock(&virt_timer_lock);
+
+        /* Do callbacks and recharge periodic timers */
+        list_for_each_entry_safe(timer, tmp, &cb_list, entry) {
+                list_del_init(&timer->entry);
+                timer->function(timer->data);
+                if (timer->interval) {
+                        /* Recharge interval timer */
+                        timer->expires = timer->interval +
+                                atomic64_read(&virt_timer_elapsed);
+                        spin_lock(&virt_timer_lock);
+                        list_add_sorted(timer, &virt_timer_list);
+                        spin_unlock(&virt_timer_lock);
+                }
         }
-        spin_unlock(&vq->lock);
-        /*
-         * To improve precision add the time spent by the
-         * interrupt handler to the elapsed time.
-         * Note: CPU timer counts down and we got an interrupt,
-         *       the current content is negative
-         */
-        elapsed = S390_lowcore.async_enter_timer - get_vtimer();
-        set_vtimer(next - elapsed);
-        vq->timer = next - elapsed;
-        vq->elapsed = elapsed;
 }
 
 void init_virt_timer(struct vtimer_list *timer)
@@ -278,179 +256,108 @@ EXPORT_SYMBOL(init_virt_timer);
 
 static inline int vtimer_pending(struct vtimer_list *timer)
 {
-        return (!list_empty(&timer->entry));
+        return !list_empty(&timer->entry);
 }
 
-/*
- * this function should only run on the specified CPU
- */
 static void internal_add_vtimer(struct vtimer_list *timer)
 {
-        struct vtimer_queue *vq;
-        unsigned long flags;
-        __u64 left, expires;
-
-        vq = &per_cpu(virt_cpu_timer, timer->cpu);
-        spin_lock_irqsave(&vq->lock, flags);
-
-        BUG_ON(timer->cpu != smp_processor_id());
-
-        if (list_empty(&vq->list)) {
-                /* First timer on this cpu, just program it. */
-                list_add(&timer->entry, &vq->list);
-                set_vtimer(timer->expires);
-                vq->timer = timer->expires;
-                vq->elapsed = 0;
+        if (list_empty(&virt_timer_list)) {
+                /* First timer, just program it. */
+                atomic64_set(&virt_timer_current, timer->expires);
+                atomic64_set(&virt_timer_elapsed, 0);
+                list_add(&timer->entry, &virt_timer_list);
         } else {
-                /* Check progress of old timers. */
-                expires = timer->expires;
-                left = get_vtimer();
-                if (likely((s64) expires < (s64) left)) {
+                /* Update timer against current base. */
+                timer->expires += atomic64_read(&virt_timer_elapsed);
+                if (likely((s64) timer->expires <
+                           (s64) atomic64_read(&virt_timer_current)))
                         /* The new timer expires before the current timer. */
-                        set_vtimer(expires);
-                        vq->elapsed += vq->timer - left;
-                        vq->timer = expires;
-                } else {
-                        vq->elapsed += vq->timer - left;
-                        vq->timer = left;
-                }
-                /* Insert new timer into per cpu list. */
-                timer->expires += vq->elapsed;
-                list_add_sorted(timer, &vq->list);
+                        atomic64_set(&virt_timer_current, timer->expires);
+                /* Insert new timer into the list. */
+                list_add_sorted(timer, &virt_timer_list);
         }
-
-        spin_unlock_irqrestore(&vq->lock, flags);
-        /* release CPU acquired in prepare_vtimer or mod_virt_timer() */
-        put_cpu();
 }
 
-static inline void prepare_vtimer(struct vtimer_list *timer)
+static void __add_vtimer(struct vtimer_list *timer, int periodic)
 {
-        BUG_ON(!timer->function);
-        BUG_ON(!timer->expires || timer->expires > VTIMER_MAX_SLICE);
-        BUG_ON(vtimer_pending(timer));
-        timer->cpu = get_cpu();
+        unsigned long flags;
+
+        timer->interval = periodic ? timer->expires : 0;
+        spin_lock_irqsave(&virt_timer_lock, flags);
+        internal_add_vtimer(timer);
+        spin_unlock_irqrestore(&virt_timer_lock, flags);
 }
 
 /*
  * add_virt_timer - add an oneshot virtual CPU timer
  */
-void add_virt_timer(void *new)
+void add_virt_timer(struct vtimer_list *timer)
 {
-        struct vtimer_list *timer;
-
-        timer = (struct vtimer_list *)new;
-        prepare_vtimer(timer);
-        timer->interval = 0;
-        internal_add_vtimer(timer);
+        __add_vtimer(timer, 0);
 }
 EXPORT_SYMBOL(add_virt_timer);
 
 /*
  * add_virt_timer_int - add an interval virtual CPU timer
  */
-void add_virt_timer_periodic(void *new)
+void add_virt_timer_periodic(struct vtimer_list *timer)
 {
-        struct vtimer_list *timer;
-
-        timer = (struct vtimer_list *)new;
-        prepare_vtimer(timer);
-        timer->interval = timer->expires;
-        internal_add_vtimer(timer);
+        __add_vtimer(timer, 1);
 }
 EXPORT_SYMBOL(add_virt_timer_periodic);
 
-static int __mod_vtimer(struct vtimer_list *timer, __u64 expires, int periodic)
+static int __mod_vtimer(struct vtimer_list *timer, u64 expires, int periodic)
 {
-        struct vtimer_queue *vq;
         unsigned long flags;
-        int cpu;
+        int rc;
 
         BUG_ON(!timer->function);
-        BUG_ON(!expires || expires > VTIMER_MAX_SLICE);
 
         if (timer->expires == expires && vtimer_pending(timer))
                 return 1;
-
-        cpu = get_cpu();
-        vq = &per_cpu(virt_cpu_timer, cpu);
-
-        /* disable interrupts before test if timer is pending */
-        spin_lock_irqsave(&vq->lock, flags);
-
-        /* if timer isn't pending add it on the current CPU */
-        if (!vtimer_pending(timer)) {
-                spin_unlock_irqrestore(&vq->lock, flags);
-
-                if (periodic)
-                        timer->interval = expires;
-                else
-                        timer->interval = 0;
-                timer->expires = expires;
-                timer->cpu = cpu;
-                internal_add_vtimer(timer);
-                return 0;
-        }
-
-        /* check if we run on the right CPU */
-        BUG_ON(timer->cpu != cpu);
-
-        list_del_init(&timer->entry);
+        spin_lock_irqsave(&virt_timer_lock, flags);
+        rc = vtimer_pending(timer);
+        if (rc)
+                list_del_init(&timer->entry);
+        timer->interval = periodic ? expires : 0;
         timer->expires = expires;
-        if (periodic)
-                timer->interval = expires;
-
-        /* the timer can't expire anymore so we can release the lock */
-        spin_unlock_irqrestore(&vq->lock, flags);
         internal_add_vtimer(timer);
-        return 1;
+        spin_unlock_irqrestore(&virt_timer_lock, flags);
+        return rc;
 }
 
 /*
- * If we change a pending timer the function must be called on the CPU
- * where the timer is running on.
- *
  * returns whether it has modified a pending timer (1) or not (0)
  */
-int mod_virt_timer(struct vtimer_list *timer, __u64 expires)
+int mod_virt_timer(struct vtimer_list *timer, u64 expires)
 {
         return __mod_vtimer(timer, expires, 0);
 }
 EXPORT_SYMBOL(mod_virt_timer);
 
 /*
- * If we change a pending timer the function must be called on the CPU
- * where the timer is running on.
- *
  * returns whether it has modified a pending timer (1) or not (0)
  */
-int mod_virt_timer_periodic(struct vtimer_list *timer, __u64 expires)
+int mod_virt_timer_periodic(struct vtimer_list *timer, u64 expires)
 {
         return __mod_vtimer(timer, expires, 1);
 }
 EXPORT_SYMBOL(mod_virt_timer_periodic);
 
 /*
- * delete a virtual timer
+ * Delete a virtual timer.
  *
  * returns whether the deleted timer was pending (1) or not (0)
  */
 int del_virt_timer(struct vtimer_list *timer)
 {
         unsigned long flags;
-        struct vtimer_queue *vq;
 
-        /* check if timer is pending */
         if (!vtimer_pending(timer))
                 return 0;
-
-        vq = &per_cpu(virt_cpu_timer, timer->cpu);
-        spin_lock_irqsave(&vq->lock, flags);
-
-        /* we don't interrupt a running timer, just let it expire! */
+        spin_lock_irqsave(&virt_timer_lock, flags);
         list_del_init(&timer->entry);
-
-        spin_unlock_irqrestore(&vq->lock, flags);
+        spin_unlock_irqrestore(&virt_timer_lock, flags);
         return 1;
 }
 EXPORT_SYMBOL(del_virt_timer);
@@ -458,20 +365,10 @@ EXPORT_SYMBOL(del_virt_timer);
 /*
  * Start the virtual CPU timer on the current CPU.
  */
-void init_cpu_vtimer(void)
+void __cpuinit init_cpu_vtimer(void)
 {
-        struct vtimer_queue *vq;
-
-        /* initialize per cpu vtimer structure */
-        vq = &__get_cpu_var(virt_cpu_timer);
-        INIT_LIST_HEAD(&vq->list);
-        spin_lock_init(&vq->lock);
-
-        /* enable cpu timer interrupts */
-        __ctl_set_bit(0,10);
-
         /* set initial cpu timer */
-        set_vtimer(0x7fffffffffffffffULL);
+        set_vtimer(VTIMER_MAX_SLICE);
 }
 
 static int __cpuinit s390_nohz_notify(struct notifier_block *self,
@@ -493,12 +390,7 @@ static int __cpuinit s390_nohz_notify(struct notifier_block *self,
 
 void __init vtime_init(void)
 {
-        /* request the cpu timer external interrupt */
-        if (register_external_interrupt(0x1005, do_cpu_timer_interrupt))
-                panic("Couldn't request external interrupt 0x1005");
-
         /* Enable cpu timer interrupts on the boot cpu. */
         init_cpu_vtimer();
         cpu_notifier(s390_nohz_notify, 0);
 }
-
diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c
index b23d9ac77df..c88bb779339 100644
--- a/arch/s390/kvm/diag.c
+++ b/arch/s390/kvm/diag.c
@@ -1,7 +1,7 @@
 /*
- * diag.c - handling diagnose instructions
+ * handling diagnose instructions
  *
- * Copyright IBM Corp. 2008,2011
+ * Copyright IBM Corp. 2008, 2011
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License (version 2 only)
diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h
index c86f6ae43f7..4703f129e95 100644
--- a/arch/s390/kvm/gaccess.h
+++ b/arch/s390/kvm/gaccess.h
@@ -1,7 +1,7 @@
 /*
- * access.h -  access guest memory
+ * access guest memory
  *
- * Copyright IBM Corp. 2008,2009
+ * Copyright IBM Corp. 2008, 2009
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License (version 2 only)
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index 979cbe55bf5..adae539f12e 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -1,7 +1,7 @@
 /*
- * intercept.c - in-kernel handling for sie intercepts
+ * in-kernel handling for sie intercepts
  *
- * Copyright IBM Corp. 2008,2009
+ * Copyright IBM Corp. 2008, 2009
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License (version 2 only)
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index 2d9f9a72bb8..b7bc1aac8ed 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * interrupt.c - handling kvm guest interrupts
+ * handling kvm guest interrupts
  *
  * Copyright IBM Corp. 2008
  *
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index 664766d0c83..d470ccbfaba 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -1,7 +1,7 @@
 /*
- * s390host.c --  hosting zSeries kernel virtual machines
+ * hosting zSeries kernel virtual machines
  *
- * Copyright IBM Corp. 2008,2009
+ * Copyright IBM Corp. 2008, 2009
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License (version 2 only)
@@ -347,6 +347,7 @@ static void kvm_s390_vcpu_initial_reset(struct kvm_vcpu *vcpu)
         vcpu->arch.guest_fpregs.fpc = 0;
         asm volatile("lfpc %0" : : "Q" (vcpu->arch.guest_fpregs.fpc));
         vcpu->arch.sie_block->gbea = 1;
+        atomic_set_mask(CPUSTAT_STOPPED, &vcpu->arch.sie_block->cpuflags);
 }
 
 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index 2294377975e..d75bc5e92c5 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -1,7 +1,7 @@
 /*
- * kvm_s390.h -  definition for kvm on s390
+ * definition for kvm on s390
  *
- * Copyright IBM Corp. 2008,2009
+ * Copyright IBM Corp. 2008, 2009
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License (version 2 only)
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index 68a6b2ed16b..60da903d6f3 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -1,5 +1,5 @@
 /*
- * priv.c - handling privileged instructions
+ * handling privileged instructions
  *
  * Copyright IBM Corp. 2008
  *
diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c
index 0ad4cf23839..56f80e1f98f 100644
--- a/arch/s390/kvm/sigp.c
+++ b/arch/s390/kvm/sigp.c
@@ -1,7 +1,7 @@
 /*
- * sigp.c - handlinge interprocessor communication
+ * handling interprocessor communication
  *
- * Copyright IBM Corp. 2008,2009
+ * Copyright IBM Corp. 2008, 2009
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License (version 2 only)
@@ -15,38 +15,10 @@
 #include <linux/kvm.h>
 #include <linux/kvm_host.h>
 #include <linux/slab.h>
+#include <asm/sigp.h>
 #include "gaccess.h"
 #include "kvm-s390.h"
 
-/* sigp order codes */
-#define SIGP_SENSE             0x01
-#define SIGP_EXTERNAL_CALL     0x02
-#define SIGP_EMERGENCY         0x03
-#define SIGP_START             0x04
-#define SIGP_STOP              0x05
-#define SIGP_RESTART           0x06
-#define SIGP_STOP_STORE_STATUS 0x09
-#define SIGP_INITIAL_CPU_RESET 0x0b
-#define SIGP_CPU_RESET         0x0c
-#define SIGP_SET_PREFIX        0x0d
-#define SIGP_STORE_STATUS_ADDR 0x0e
-#define SIGP_SET_ARCH          0x12
-#define SIGP_SENSE_RUNNING     0x15
-
-/* cpu status bits */
-#define SIGP_STAT_EQUIPMENT_CHECK   0x80000000UL
-#define SIGP_STAT_NOT_RUNNING       0x00000400UL
-#define SIGP_STAT_INCORRECT_STATE   0x00000200UL
-#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
-#define SIGP_STAT_EXT_CALL_PENDING  0x00000080UL
-#define SIGP_STAT_STOPPED           0x00000040UL
-#define SIGP_STAT_OPERATOR_INTERV   0x00000020UL
-#define SIGP_STAT_CHECK_STOP        0x00000010UL
-#define SIGP_STAT_INOPERATIVE       0x00000004UL
-#define SIGP_STAT_INVALID_ORDER     0x00000002UL
-#define SIGP_STAT_RECEIVER_CHECK    0x00000001UL
-
-
 static int __sigp_sense(struct kvm_vcpu *vcpu, u16 cpu_addr,
                         u64 *reg)
 {
@@ -54,19 +26,23 @@ static int __sigp_sense(struct kvm_vcpu *vcpu, u16 cpu_addr,
         int rc;
 
         if (cpu_addr >= KVM_MAX_VCPUS)
-                return 3; /* not operational */
+                return SIGP_CC_NOT_OPERATIONAL;
 
         spin_lock(&fi->lock);
         if (fi->local_int[cpu_addr] == NULL)
-                rc = 3; /* not operational */
+                rc = SIGP_CC_NOT_OPERATIONAL;
         else if (!(atomic_read(fi->local_int[cpu_addr]->cpuflags)
-                  & CPUSTAT_STOPPED)) {
-                *reg &= 0xffffffff00000000UL;
-                rc = 1; /* status stored */
-        } else {
+                   & (CPUSTAT_ECALL_PEND | CPUSTAT_STOPPED)))
+                rc = SIGP_CC_ORDER_CODE_ACCEPTED;
+        else {
                 *reg &= 0xffffffff00000000UL;
-                *reg |= SIGP_STAT_STOPPED;
-                rc = 1; /* status stored */
+                if (atomic_read(fi->local_int[cpu_addr]->cpuflags)
+                    & CPUSTAT_ECALL_PEND)
+                        *reg |= SIGP_STATUS_EXT_CALL_PENDING;
+                if (atomic_read(fi->local_int[cpu_addr]->cpuflags)
+                    & CPUSTAT_STOPPED)
+                        *reg |= SIGP_STATUS_STOPPED;
+                rc = SIGP_CC_STATUS_STORED;
         }
         spin_unlock(&fi->lock);
 
@@ -82,7 +58,7 @@ static int __sigp_emergency(struct kvm_vcpu *vcpu, u16 cpu_addr)
         int rc;
 
         if (cpu_addr >= KVM_MAX_VCPUS)
-                return 3; /* not operational */
+                return SIGP_CC_NOT_OPERATIONAL;
 
         inti = kzalloc(sizeof(*inti), GFP_KERNEL);
         if (!inti)
@@ -94,7 +70,7 @@ static int __sigp_emergency(struct kvm_vcpu *vcpu, u16 cpu_addr)
         spin_lock(&fi->lock);
         li = fi->local_int[cpu_addr];
         if (li == NULL) {
-                rc = 3; /* not operational */
+                rc = SIGP_CC_NOT_OPERATIONAL;
                 kfree(inti);
                 goto unlock;
         }
@@ -105,7 +81,7 @@ static int __sigp_emergency(struct kvm_vcpu *vcpu, u16 cpu_addr)
         if (waitqueue_active(&li->wq))
                 wake_up_interruptible(&li->wq);
         spin_unlock_bh(&li->lock);
-        rc = 0; /* order accepted */
+        rc = SIGP_CC_ORDER_CODE_ACCEPTED;
         VCPU_EVENT(vcpu, 4, "sent sigp emerg to cpu %x", cpu_addr);
 unlock:
         spin_unlock(&fi->lock);
@@ -120,7 +96,7 @@ static int __sigp_external_call(struct kvm_vcpu *vcpu, u16 cpu_addr)
         int rc;
 
         if (cpu_addr >= KVM_MAX_VCPUS)
-                return 3; /* not operational */
+                return SIGP_CC_NOT_OPERATIONAL;
 
         inti = kzalloc(sizeof(*inti), GFP_KERNEL);
         if (!inti)
@@ -132,7 +108,7 @@ static int __sigp_external_call(struct kvm_vcpu *vcpu, u16 cpu_addr)
         spin_lock(&fi->lock);
         li = fi->local_int[cpu_addr];
         if (li == NULL) {
-                rc = 3; /* not operational */
+                rc = SIGP_CC_NOT_OPERATIONAL;
                 kfree(inti);
                 goto unlock;
         }
@@ -143,7 +119,7 @@ static int __sigp_external_call(struct kvm_vcpu *vcpu, u16 cpu_addr)
         if (waitqueue_active(&li->wq))
                 wake_up_interruptible(&li->wq);
         spin_unlock_bh(&li->lock);
-        rc = 0; /* order accepted */
+        rc = SIGP_CC_ORDER_CODE_ACCEPTED;
         VCPU_EVENT(vcpu, 4, "sent sigp ext call to cpu %x", cpu_addr);
 unlock:
         spin_unlock(&fi->lock);
@@ -171,7 +147,7 @@ static int __inject_sigp_stop(struct kvm_s390_local_interrupt *li, int action)
 out:
         spin_unlock_bh(&li->lock);
 
-        return 0; /* order accepted */
+        return SIGP_CC_ORDER_CODE_ACCEPTED;
 }
 
 static int __sigp_stop(struct kvm_vcpu *vcpu, u16 cpu_addr, int action)
@@ -181,12 +157,12 @@ static int __sigp_stop(struct kvm_vcpu *vcpu, u16 cpu_addr, int action)
         int rc;
 
         if (cpu_addr >= KVM_MAX_VCPUS)
-                return 3; /* not operational */
+                return SIGP_CC_NOT_OPERATIONAL;
 
         spin_lock(&fi->lock);
         li = fi->local_int[cpu_addr];
         if (li == NULL) {
-                rc = 3; /* not operational */
+                rc = SIGP_CC_NOT_OPERATIONAL;
                 goto unlock;
         }
 
@@ -210,11 +186,11 @@ static int __sigp_set_arch(struct kvm_vcpu *vcpu, u32 parameter)
 
         switch (parameter & 0xff) {
         case 0:
-                rc = 3; /* not operational */
+                rc = SIGP_CC_NOT_OPERATIONAL;
                 break;
         case 1:
         case 2:
-                rc = 0; /* order accepted */
+                rc = SIGP_CC_ORDER_CODE_ACCEPTED;
                 break;
         default:
                 rc = -EOPNOTSUPP;
@@ -235,21 +211,23 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
         address = address & 0x7fffe000u;
         if (copy_from_guest_absolute(vcpu, &tmp, address, 1) ||
            copy_from_guest_absolute(vcpu, &tmp, address + PAGE_SIZE, 1)) {
-                *reg |= SIGP_STAT_INVALID_PARAMETER;
-                return 1; /* invalid parameter */
+                *reg &= 0xffffffff00000000UL;
+                *reg |= SIGP_STATUS_INVALID_PARAMETER;
+                return SIGP_CC_STATUS_STORED;
         }
 
         inti = kzalloc(sizeof(*inti), GFP_KERNEL);
         if (!inti)
-                return 2; /* busy */
+                return SIGP_CC_BUSY;
 
         spin_lock(&fi->lock);
         if (cpu_addr < KVM_MAX_VCPUS)
                 li = fi->local_int[cpu_addr];
 
         if (li == NULL) {
-                rc = 1; /* incorrect state */
-                *reg &= SIGP_STAT_INCORRECT_STATE;
+                *reg &= 0xffffffff00000000UL;
+                *reg |= SIGP_STATUS_INCORRECT_STATE;
+                rc = SIGP_CC_STATUS_STORED;
                 kfree(inti);
                 goto out_fi;
         }
@@ -257,8 +235,9 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
         spin_lock_bh(&li->lock);
         /* cpu must be in stopped state */
         if (!(atomic_read(li->cpuflags) & CPUSTAT_STOPPED)) {
-                rc = 1; /* incorrect state */
-                *reg &= SIGP_STAT_INCORRECT_STATE;
+                *reg &= 0xffffffff00000000UL;
+                *reg |= SIGP_STATUS_INCORRECT_STATE;
+                rc = SIGP_CC_STATUS_STORED;
                 kfree(inti);
                 goto out_li;
         }
@@ -270,7 +249,7 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
         atomic_set(&li->active, 1);
         if (waitqueue_active(&li->wq))
                 wake_up_interruptible(&li->wq);
-        rc = 0; /* order accepted */
+        rc = SIGP_CC_ORDER_CODE_ACCEPTED;
 
         VCPU_EVENT(vcpu, 4, "set prefix of cpu %02x to %x", cpu_addr, address);
 out_li:
@@ -287,21 +266,21 @@ static int __sigp_sense_running(struct kvm_vcpu *vcpu, u16 cpu_addr,
         struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
 
         if (cpu_addr >= KVM_MAX_VCPUS)
-                return 3; /* not operational */
+                return SIGP_CC_NOT_OPERATIONAL;
 
         spin_lock(&fi->lock);
         if (fi->local_int[cpu_addr] == NULL)
-                rc = 3; /* not operational */
+                rc = SIGP_CC_NOT_OPERATIONAL;
         else {
                 if (atomic_read(fi->local_int[cpu_addr]->cpuflags)
                     & CPUSTAT_RUNNING) {
                         /* running */
-                        rc = 1;
+                        rc = SIGP_CC_ORDER_CODE_ACCEPTED;
                 } else {
                         /* not running */
                         *reg &= 0xffffffff00000000UL;
-                        *reg |= SIGP_STAT_NOT_RUNNING;
-                        rc = 0;
+                        *reg |= SIGP_STATUS_NOT_RUNNING;
+                        rc = SIGP_CC_STATUS_STORED;
                 }
         }
         spin_unlock(&fi->lock);
@@ -314,23 +293,23 @@ static int __sigp_sense_running(struct kvm_vcpu *vcpu, u16 cpu_addr,
 
 static int __sigp_restart(struct kvm_vcpu *vcpu, u16 cpu_addr)
 {
-        int rc = 0;
         struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
         struct kvm_s390_local_interrupt *li;
+        int rc = SIGP_CC_ORDER_CODE_ACCEPTED;
 
         if (cpu_addr >= KVM_MAX_VCPUS)
-                return 3; /* not operational */
+                return SIGP_CC_NOT_OPERATIONAL;
 
         spin_lock(&fi->lock);
         li = fi->local_int[cpu_addr];
         if (li == NULL) {
-                rc = 3; /* not operational */
+                rc = SIGP_CC_NOT_OPERATIONAL;
                 goto out;
         }
 
         spin_lock_bh(&li->lock);
         if (li->action_bits & ACTION_STOP_ON_STOP)
-                rc = 2; /* busy */
+                rc = SIGP_CC_BUSY;
         else
                 VCPU_EVENT(vcpu, 4, "sigp restart %x to handle userspace",
                         cpu_addr);
@@ -375,7 +354,7 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
                 vcpu->stat.instruction_sigp_external_call++;
                 rc = __sigp_external_call(vcpu, cpu_addr);
                 break;
-        case SIGP_EMERGENCY:
+        case SIGP_EMERGENCY_SIGNAL:
                 vcpu->stat.instruction_sigp_emergency++;
                 rc = __sigp_emergency(vcpu, cpu_addr);
                 break;
@@ -383,12 +362,12 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
                 vcpu->stat.instruction_sigp_stop++;
                 rc = __sigp_stop(vcpu, cpu_addr, ACTION_STOP_ON_STOP);
                 break;
-        case SIGP_STOP_STORE_STATUS:
+        case SIGP_STOP_AND_STORE_STATUS:
                 vcpu->stat.instruction_sigp_stop++;
                 rc = __sigp_stop(vcpu, cpu_addr, ACTION_STORE_ON_STOP |
                                                  ACTION_STOP_ON_STOP);
                 break;
-        case SIGP_SET_ARCH:
+        case SIGP_SET_ARCHITECTURE:
                 vcpu->stat.instruction_sigp_arch++;
                 rc = __sigp_set_arch(vcpu, parameter);
                 break;
@@ -405,7 +384,7 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
         case SIGP_RESTART:
                 vcpu->stat.instruction_sigp_restart++;
                 rc = __sigp_restart(vcpu, cpu_addr);
-                if (rc == 2) /* busy */
+                if (rc == SIGP_CC_BUSY)
                         break;
                 /* user space must know about restart */
         default:
diff --git a/arch/s390/lib/delay.c b/arch/s390/lib/delay.c
index 9f1f71e8577..42d0cf89121 100644
--- a/arch/s390/lib/delay.c
+++ b/arch/s390/lib/delay.c
@@ -1,7 +1,7 @@
 /*
  *    Precise Delay Loops for S390
  *
- *    Copyright IBM Corp. 1999,2008
+ *    Copyright IBM Corp. 1999, 2008
  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *               Heiko Carstens <heiko.carstens@de.ibm.com>,
  */
@@ -12,8 +12,8 @@
 #include <linux/module.h>
 #include <linux/irqflags.h>
 #include <linux/interrupt.h>
+#include <asm/vtimer.h>
 #include <asm/div64.h>
-#include <asm/timer.h>
 
 void __delay(unsigned long loops)
 {
diff --git a/arch/s390/lib/div64.c b/arch/s390/lib/div64.c
index d9e62c0b576..261152f8324 100644
--- a/arch/s390/lib/div64.c
+++ b/arch/s390/lib/div64.c
@@ -1,9 +1,7 @@
 /*
- *  arch/s390/lib/div64.c
- *
  *  __div64_32 implementation for 31 bit.
  *
- *    Copyright (C) IBM Corp. 2006
+ *    Copyright IBM Corp. 2006
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  */
 
diff --git a/arch/s390/lib/spinlock.c b/arch/s390/lib/spinlock.c
index 093eb694d9c..f709983f41f 100644
--- a/arch/s390/lib/spinlock.c
+++ b/arch/s390/lib/spinlock.c
@@ -1,8 +1,7 @@
 /*
- *  arch/s390/lib/spinlock.c
  *    Out of line spinlock code.
  *
- *    Copyright (C) IBM Corp. 2004, 2006
+ *    Copyright IBM Corp. 2004, 2006
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  */
 
diff --git a/arch/s390/lib/string.c b/arch/s390/lib/string.c
index 4143b7c1909..846ec64ab2c 100644
--- a/arch/s390/lib/string.c
+++ b/arch/s390/lib/string.c
@@ -1,9 +1,8 @@
 /*
- *  arch/s390/lib/string.c
  *    Optimized string functions
  *
  *  S390 version
- *    Copyright (C) 2004 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 2004
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
  */
 
diff --git a/arch/s390/lib/uaccess.h b/arch/s390/lib/uaccess.h
index 1d2536cb630..315dbe09983 100644
--- a/arch/s390/lib/uaccess.h
+++ b/arch/s390/lib/uaccess.h
@@ -1,6 +1,4 @@
 /*
- *  arch/s390/uaccess.h
- *
  *    Copyright IBM Corp. 2007
  *
  */
diff --git a/arch/s390/lib/uaccess_mvcos.c b/arch/s390/lib/uaccess_mvcos.c
index 58a75a8ae90..2443ae476e3 100644
--- a/arch/s390/lib/uaccess_mvcos.c
+++ b/arch/s390/lib/uaccess_mvcos.c
@@ -1,9 +1,7 @@
 /*
- *  arch/s390/lib/uaccess_mvcos.c
- *
  *  Optimized user space space access functions based on mvcos.
  *
- *    Copyright (C) IBM Corp. 2006
+ *    Copyright IBM Corp. 2006
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Gerald Schaefer (gerald.schaefer@de.ibm.com)
  */
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c
index 342ae35a5ba..60ee2b88379 100644
--- a/arch/s390/lib/uaccess_pt.c
+++ b/arch/s390/lib/uaccess_pt.c
@@ -1,6 +1,4 @@
 /*
- *  arch/s390/lib/uaccess_pt.c
- *
  *  User access functions based on page table walks for enhanced
  *  system layout without hardware support.
  *
diff --git a/arch/s390/lib/uaccess_std.c b/arch/s390/lib/uaccess_std.c
index 57e94298539..6fbd0633827 100644
--- a/arch/s390/lib/uaccess_std.c
+++ b/arch/s390/lib/uaccess_std.c
@@ -1,10 +1,8 @@
 /*
- *  arch/s390/lib/uaccess_std.c
- *
  *  Standard user space access functions based on mvcp/mvcs and doing
  *  interesting things in the secondary space mode.
  *
- *    Copyright (C) IBM Corp. 2006
+ *    Copyright IBM Corp. 2006
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *               Gerald Schaefer (gerald.schaefer@de.ibm.com)
  */
diff --git a/arch/s390/math-emu/math.c b/arch/s390/math-emu/math.c
index cd4e9c168dd..58bff541fde 100644
--- a/arch/s390/math-emu/math.c
+++ b/arch/s390/math-emu/math.c
@@ -1,8 +1,6 @@
 /*
- *  arch/s390/math-emu/math.c
- *
  *  S390 version
- *    Copyright (C) 1999-2001 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999, 2001
  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
  *
  * 'math.c' emulates IEEE instructions on a S390 processor
diff --git a/arch/s390/mm/cmm.c b/arch/s390/mm/cmm.c
index 1f1dba9dcf5..479e9428291 100644
--- a/arch/s390/mm/cmm.c
+++ b/arch/s390/mm/cmm.c
@@ -1,7 +1,7 @@
 /*
  *  Collaborative memory management interface.
  *
- *    Copyright IBM Corp 2003,2010
+ *    Copyright IBM Corp 2003, 2010
  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
  *
  */
diff --git a/arch/s390/mm/extmem.c b/arch/s390/mm/extmem.c
index 075ddada491..519bba716cc 100644
--- a/arch/s390/mm/extmem.c
+++ b/arch/s390/mm/extmem.c
@@ -1,10 +1,9 @@
 /*
- * File...........: arch/s390/mm/extmem.c
  * Author(s)......: Carsten Otte <cotte@de.ibm.com>
  *                  Rob M van der Heij <rvdheij@nl.ibm.com>
  *                  Steven Shultz <shultzss@us.ibm.com>
  * Bugreports.to..: <Linux390@de.ibm.com>
- * (C) IBM Corporation 2002-2004
+ * Copyright IBM Corp. 2002, 2004
  */
 
 #define KMSG_COMPONENT "extmem"
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index 72cec9ecd96..6c013f54414 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -1,8 +1,6 @@
 /*
- *  arch/s390/mm/fault.c
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Hartmut Penner (hp@de.ibm.com)
  *               Ulrich Weigand (uweigand@de.ibm.com)
  *
@@ -51,6 +49,7 @@
 #define VM_FAULT_BADCONTEXT     0x010000
 #define VM_FAULT_BADMAP         0x020000
 #define VM_FAULT_BADACCESS      0x040000
+#define VM_FAULT_SIGNAL 0x080000
 
 static unsigned long store_indication;
 
@@ -112,7 +111,7 @@ static inline int user_space_fault(unsigned long trans_exc_code)
         if (trans_exc_code == 2)
                 /* Access via secondary space, set_fs setting decides */
                 return current->thread.mm_segment.ar4;
-        if (user_mode == HOME_SPACE_MODE)
+        if (addressing_mode == HOME_SPACE_MODE)
                 /* User space if the access has been done via home space. */
                 return trans_exc_code == 3;
         /*
@@ -221,7 +220,7 @@ static noinline void do_fault_error(struct pt_regs *regs, int fault)
         case VM_FAULT_BADACCESS:
         case VM_FAULT_BADMAP:
                 /* Bad memory access. Check if it is kernel or user space. */
-                if (regs->psw.mask & PSW_MASK_PSTATE) {
+                if (user_mode(regs)) {
                         /* User mode accesses just cause a SIGSEGV */
                         si_code = (fault == VM_FAULT_BADMAP) ?
                                 SEGV_MAPERR : SEGV_ACCERR;
@@ -231,15 +230,19 @@ static noinline void do_fault_error(struct pt_regs *regs, int fault)
         case VM_FAULT_BADCONTEXT:
                 do_no_context(regs);
                 break;
+        case VM_FAULT_SIGNAL:
+                if (!user_mode(regs))
+                        do_no_context(regs);
+                break;
         default: /* fault & VM_FAULT_ERROR */
                 if (fault & VM_FAULT_OOM) {
-                        if (!(regs->psw.mask & PSW_MASK_PSTATE))
+                        if (!user_mode(regs))
                                 do_no_context(regs);
                         else
                                 pagefault_out_of_memory();
                 } else if (fault & VM_FAULT_SIGBUS) {
                         /* Kernel mode? Handle exceptions or die */
-                        if (!(regs->psw.mask & PSW_MASK_PSTATE))
+                        if (!user_mode(regs))
                                 do_no_context(regs);
                         else
                                 do_sigbus(regs);
@@ -288,7 +291,7 @@ static inline int do_exception(struct pt_regs *regs, int access)
 
         address = trans_exc_code & __FAIL_ADDR_MASK;
         perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
-        flags = FAULT_FLAG_ALLOW_RETRY;
+        flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
         if (access == VM_WRITE || (trans_exc_code & store_indication) == 0x400)
                 flags |= FAULT_FLAG_WRITE;
         down_read(&mm->mmap_sem);
@@ -337,6 +340,11 @@ retry:
          * the fault.
          */
         fault = handle_mm_fault(mm, vma, address, flags);
+        /* No reason to continue if interrupted by SIGKILL. */
+        if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) {
+                fault = VM_FAULT_SIGNAL;
+                goto out;
+        }
         if (unlikely(fault & VM_FAULT_ERROR))
                 goto out_up;
 
@@ -428,7 +436,7 @@ void __kprobes do_asce_exception(struct pt_regs *regs)
         }
 
         /* User mode accesses just cause a SIGSEGV */
-        if (regs->psw.mask & PSW_MASK_PSTATE) {
+        if (user_mode(regs)) {
                 do_sigsegv(regs, SEGV_MAPERR);
                 return;
         }
@@ -443,6 +451,7 @@ int __handle_fault(unsigned long uaddr, unsigned long pgm_int_code, int write)
         struct pt_regs regs;
         int access, fault;
 
+        /* Emulate a uaccess fault from kernel mode. */
         regs.psw.mask = psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK;
         if (!irqs_disabled())
                 regs.psw.mask |= PSW_MASK_IO | PSW_MASK_EXT;
@@ -452,12 +461,12 @@ int __handle_fault(unsigned long uaddr, unsigned long pgm_int_code, int write)
         regs.int_parm_long = (uaddr & PAGE_MASK) | 2;
         access = write ? VM_WRITE : VM_READ;
         fault = do_exception(&regs, access);
-        if (unlikely(fault)) {
-                if (fault & VM_FAULT_OOM)
-                        return -EFAULT;
-                else if (fault & VM_FAULT_SIGBUS)
-                        do_sigbus(&regs);
-        }
+        /*
+         * Since the fault happened in kernel mode while performing a uaccess
+         * all we need to do now is emulating a fixup in case "fault" is not
+         * zero.
+         * For the calling uaccess functions this results always in -EFAULT.
+         */
         return fault ? -EFAULT : 0;
 }
 
diff --git a/arch/s390/mm/hugetlbpage.c b/arch/s390/mm/hugetlbpage.c
index 900de2b3cf2..532525ec88c 100644
--- a/arch/s390/mm/hugetlbpage.c
+++ b/arch/s390/mm/hugetlbpage.c
@@ -1,7 +1,7 @@
 /*
  *  IBM System z Huge TLB Page Support for Kernel.
  *
- *    Copyright 2007 IBM Corp.
+ *    Copyright IBM Corp. 2007
  *    Author(s): Gerald Schaefer <gerald.schaefer@de.ibm.com>
  */
 
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 2bea0605856..6adbc082618 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -1,8 +1,6 @@
 /*
- *  arch/s390/mm/init.c
- *
  *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *    Copyright IBM Corp. 1999
  *    Author(s): Hartmut Penner (hp@de.ibm.com)
  *
  *  Derived from "arch/i386/mm/init.c"
diff --git a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c
index 2857c48486e..c59a5efa58b 100644
--- a/arch/s390/mm/mmap.c
+++ b/arch/s390/mm/mmap.c
@@ -1,6 +1,4 @@
 /*
- *  linux/arch/s390/mm/mmap.c
- *
  *  flexible mmap layout support
  *
  * Copyright 2003-2004 Red Hat Inc., Durham, North Carolina.
@@ -105,9 +103,15 @@ void arch_pick_mmap_layout(struct mm_struct *mm)
 
 int s390_mmap_check(unsigned long addr, unsigned long len)
 {
+        int rc;
+
         if (!is_compat_task() &&
-            len >= TASK_SIZE && TASK_SIZE < (1UL << 53))
-                return crst_table_upgrade(current->mm, 1UL << 53);
+            len >= TASK_SIZE && TASK_SIZE < (1UL << 53)) {
+                rc = crst_table_upgrade(current->mm, 1UL << 53);
+                if (rc)
+                        return rc;
+                update_mm(current->mm, current);
+        }
         return 0;
 }
 
@@ -127,6 +131,7 @@ s390_get_unmapped_area(struct file *filp, unsigned long addr,
                 rc = crst_table_upgrade(mm, 1UL << 53);
                 if (rc)
                         return (unsigned long) rc;
+                update_mm(mm, current);
                 area = arch_get_unmapped_area(filp, addr, len, pgoff, flags);
         }
         return area;
@@ -149,6 +154,7 @@ s390_get_unmapped_area_topdown(struct file *filp, const unsigned long addr,
                 rc = crst_table_upgrade(mm, 1UL << 53);
                 if (rc)
                         return (unsigned long) rc;
+                update_mm(mm, current);
                 area = arch_get_unmapped_area_topdown(filp, addr, len,
                                                       pgoff, flags);
         }
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index a3db5a3ea08..18df31d1f2c 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -1,5 +1,5 @@
 /*
- *    Copyright IBM Corp. 2007,2011
+ *    Copyright IBM Corp. 2007, 2011
  *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
  */
 
@@ -85,7 +85,6 @@ repeat:
                 crst_table_free(mm, table);
         if (mm->context.asce_limit < limit)
                 goto repeat;
-        update_mm(mm, current);
         return 0;
 }
 
@@ -93,9 +92,6 @@ void crst_table_downgrade(struct mm_struct *mm, unsigned long limit)
 {
         pgd_t *pgd;
 
-        if (mm->context.asce_limit <= limit)
-                return;
-        __tlb_flush_mm(mm);
         while (mm->context.asce_limit > limit) {
                 pgd = mm->pgd;
                 switch (pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) {
@@ -118,7 +114,6 @@ void crst_table_downgrade(struct mm_struct *mm, unsigned long limit)
                 mm->task_size = mm->context.asce_limit;
                 crst_table_free(mm, (unsigned long *) pgd);
         }
-        update_mm(mm, current);
 }
 #endif
 
@@ -801,7 +796,7 @@ int s390_enable_sie(void)
         struct mm_struct *mm, *old_mm;
 
         /* Do we have switched amode? If no, we cannot do sie */
-        if (user_mode == HOME_SPACE_MODE)
+        if (addressing_mode == HOME_SPACE_MODE)
                 return -EINVAL;
 
         /* Do we have pgstes? if yes, we are done */
diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c
index 71ae20df674..6f896e75ab4 100644
--- a/arch/s390/mm/vmem.c
+++ b/arch/s390/mm/vmem.c
@@ -1,6 +1,4 @@
 /*
- *  arch/s390/mm/vmem.c
- *
  *    Copyright IBM Corp. 2006
  *    Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>
  */
diff --git a/arch/s390/oprofile/backtrace.c b/arch/s390/oprofile/backtrace.c
index bc4b84a35ca..8a6811b2cdb 100644
--- a/arch/s390/oprofile/backtrace.c
+++ b/arch/s390/oprofile/backtrace.c
@@ -1,8 +1,6 @@
-/**
- * arch/s390/oprofile/backtrace.c
- *
+/*
  * S390 Version
- *   Copyright (C) 2005 IBM Corporation, IBM Deutschland Entwicklung GmbH.
+ *   Copyright IBM Corp. 2005
  *   Author(s): Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
  */
 
@@ -60,7 +58,7 @@ void s390_backtrace(struct pt_regs * const regs, unsigned int depth)
         unsigned long head;
         struct stack_frame* head_sf;
 
-        if (user_mode (regs))
+        if (user_mode(regs))
                 return;
 
         head = regs->gprs[15];
diff --git a/arch/s390/oprofile/hwsampler.c b/arch/s390/oprofile/hwsampler.c
index a4a89fa980d..0cb385da202 100644
--- a/arch/s390/oprofile/hwsampler.c
+++ b/arch/s390/oprofile/hwsampler.c
@@ -1,6 +1,4 @@
-/**
- * arch/s390/oprofile/hwsampler.c
- *
+/*
  * Copyright IBM Corp. 2010
  * Author: Heinz Graalfs <graalfs@de.ibm.com>
  */
diff --git a/arch/s390/oprofile/init.c b/arch/s390/oprofile/init.c
index 2297be406c6..a1e9d69a9c9 100644
--- a/arch/s390/oprofile/init.c
+++ b/arch/s390/oprofile/init.c
@@ -1,8 +1,6 @@
-/**
- * arch/s390/oprofile/init.c
- *
+/*
  * S390 Version
- *   Copyright (C) 2002-2011 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ *   Copyright IBM Corp. 2002, 2011
  *   Author(s): Thomas Spatzier (tspat@de.ibm.com)
  *   Author(s): Mahesh Salgaonkar (mahesh@linux.vnet.ibm.com)
  *   Author(s): Heinz Graalfs (graalfs@linux.vnet.ibm.com)
diff --git a/arch/s390/oprofile/op_counter.h b/arch/s390/oprofile/op_counter.h
index 1a8d3ca0901..61b2531eef1 100644
--- a/arch/s390/oprofile/op_counter.h
+++ b/arch/s390/oprofile/op_counter.h
@@ -1,7 +1,5 @@
-/**
- * arch/s390/oprofile/op_counter.h
- *
- *   Copyright (C) 2011 IBM Deutschland Entwicklung GmbH, IBM Corporation
+/*
+ *   Copyright IBM Corp. 2011
  *   Author(s): Andreas Krebbel (krebbel@linux.vnet.ibm.com)
  *
  * @remark Copyright 2011 OProfile authors
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 31d9db7913e..36f5141e804 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -21,6 +21,7 @@ config SUPERH
         select HAVE_KERNEL_LZMA
         select HAVE_KERNEL_XZ
         select HAVE_KERNEL_LZO
+        select ARCH_WANT_IPC_PARSE_VERSION
         select HAVE_SYSCALL_TRACEPOINTS
         select HAVE_REGS_AND_STACK_ACCESS_API
         select HAVE_GENERIC_HARDIRQS
@@ -50,6 +51,7 @@ config SUPERH32
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
         select HAVE_FTRACE_NMI_ENTER if DYNAMIC_FTRACE
+        select ARCH_WANT_IPC_PARSE_VERSION
         select HAVE_FUNCTION_GRAPH_TRACER
         select HAVE_ARCH_KGDB
         select HAVE_HW_BREAKPOINT
@@ -60,6 +62,7 @@ config SUPERH32
 
 config SUPERH64
         def_bool ARCH = "sh64"
+        select KALLSYMS
 
 config ARCH_DEFCONFIG
         string
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index 1f56b35d324..fb5805745ac 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -44,6 +44,8 @@ config SH_7721_SOLUTION_ENGINE
 config SH_7722_SOLUTION_ENGINE
         bool "SolutionEngine7722"
         select SOLUTION_ENGINE
+        select GENERIC_IRQ_CHIP
+        select IRQ_DOMAIN
         depends on CPU_SUBTYPE_SH7722
         help
           Select 7722 SolutionEngine if configuring for a Hitachi SH772
@@ -55,6 +57,7 @@ config SH_7724_SOLUTION_ENGINE
         depends on CPU_SUBTYPE_SH7724
         select ARCH_REQUIRE_GPIOLIB
         select SND_SOC_AK4642 if SND_SIMPLE_CARD
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
           Select 7724 SolutionEngine if configuring for a Hitachi SH7724
           evaluation board.
@@ -80,6 +83,8 @@ config SH_7780_SOLUTION_ENGINE
 config SH_7343_SOLUTION_ENGINE
         bool "SolutionEngine7343"
         select SOLUTION_ENGINE
+        select GENERIC_IRQ_CHIP
+        select IRQ_DOMAIN
         depends on CPU_SUBTYPE_SH7343
         help
           Select 7343 SolutionEngine if configuring for a Hitachi
@@ -136,6 +141,7 @@ config SH_RSK
         bool "Renesas Starter Kit"
         depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || \
           CPU_SUBTYPE_SH7264 || CPU_SUBTYPE_SH7269
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
          Select this option if configuring for any of the RSK+ MCU
          evaluation platforms.
@@ -155,6 +161,7 @@ config SH_SDK7786
         select NO_IOPORT if !PCI
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select HAVE_SRAM_POOL
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
           Select SDK7786 if configuring for a Renesas Technology Europe
           SH7786-65nm board.
@@ -169,6 +176,7 @@ config SH_SH7757LCR
         bool "SH7757LCR"
         depends on CPU_SUBTYPE_SH7757
         select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
 config SH_SH7785LCR
         bool "SH7785LCR"
@@ -202,6 +210,7 @@ config SH_MIGOR
         bool "Migo-R"
         depends on CPU_SUBTYPE_SH7722
         select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
           Select Migo-R if configuring for the SH7722 Migo-R platform
           by Renesas System Solutions Asia Pte. Ltd.
@@ -210,6 +219,7 @@ config SH_AP325RXA
         bool "AP-325RXA"
         depends on CPU_SUBTYPE_SH7723
         select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
           Renesas "AP-325RXA" support.
           Compatible with ALGO SYSTEM CO.,LTD. "AP-320A"
@@ -218,6 +228,7 @@ config SH_KFR2R09
         bool "KFR2R09"
         depends on CPU_SUBTYPE_SH7724
         select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
           "Kit For R2R for 2009" support.
 
@@ -226,6 +237,7 @@ config SH_ECOVEC
         depends on CPU_SUBTYPE_SH7724
         select ARCH_REQUIRE_GPIOLIB
         select SND_SOC_DA7210 if SND_SIMPLE_CARD
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
           Renesas "R0P7724LC0011/21RL (EcoVec)" support.
 
@@ -295,11 +307,13 @@ config SH_X3PROTO
         bool "SH-X3 Prototype board"
         depends on CPU_SUBTYPE_SHX3
         select NO_IOPORT if !PCI
+        select IRQ_DOMAIN
 
 config SH_MAGIC_PANEL_R2
         bool "Magic Panel R2"
         depends on CPU_SUBTYPE_SH7720
         select ARCH_REQUIRE_GPIOLIB
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
           Select Magic Panel R2 if configuring for Magic Panel R2.
 
@@ -311,6 +325,7 @@ config SH_CAYMAN
 config SH_POLARIS
         bool "SMSC Polaris"
         select CPU_HAS_IPR_IRQ
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         depends on CPU_SUBTYPE_SH7709
         help
           Select if configuring for an SMSC Polaris development board
@@ -318,6 +333,7 @@ config SH_POLARIS
 config SH_SH2007
         bool "SH-2007 board"
         select NO_IOPORT
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         depends on CPU_SUBTYPE_SH7780
         help
           SH-2007 is a single-board computer based around SH7780 chip
@@ -329,6 +345,7 @@ config SH_SH2007
 config SH_APSH4A3A
         bool "AP-SH4A-3A"
         select SH_ALPHA_BOARD
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         depends on CPU_SUBTYPE_SH7785
         help
           Select AP-SH4A-3A if configuring for an ALPHAPROJECT AP-SH4A-3A.
@@ -337,6 +354,7 @@ config SH_APSH4AD0A
         bool "AP-SH4AD-0A"
         select SH_ALPHA_BOARD
         select SYS_SUPPORTS_PCI
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         depends on CPU_SUBTYPE_SH7786
         help
           Select AP-SH4AD-0A if configuring for an ALPHAPROJECT AP-SH4AD-0A.
diff --git a/arch/sh/boards/board-apsh4a3a.c b/arch/sh/boards/board-apsh4a3a.c
index 2823619c600..0a39c241628 100644
--- a/arch/sh/boards/board-apsh4a3a.c
+++ b/arch/sh/boards/board-apsh4a3a.c
@@ -13,6 +13,8 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/mtd/physmap.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/irq.h>
 #include <linux/clk.h>
@@ -66,6 +68,12 @@ static struct platform_device nor_flash_device = {
         .resource       = nor_flash_resources,
 };
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static struct resource smsc911x_resources[] = {
         [0] = {
                 .name           = "smsc911x-memory",
@@ -105,6 +113,8 @@ static struct platform_device *apsh4a3a_devices[] __initdata = {
 
 static int __init apsh4a3a_devices_setup(void)
 {
+        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         return platform_add_devices(apsh4a3a_devices,
                                     ARRAY_SIZE(apsh4a3a_devices));
 }
diff --git a/arch/sh/boards/board-apsh4ad0a.c b/arch/sh/boards/board-apsh4ad0a.c
index b4d6292a924..92eac3a9918 100644
--- a/arch/sh/boards/board-apsh4ad0a.c
+++ b/arch/sh/boards/board-apsh4ad0a.c
@@ -12,12 +12,20 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/irq.h>
 #include <linux/clk.h>
 #include <asm/machvec.h>
 #include <asm/sizes.h>
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static struct resource smsc911x_resources[] = {
         [0] = {
                 .name           = "smsc911x-memory",
@@ -56,6 +64,8 @@ static struct platform_device *apsh4ad0a_devices[] __initdata = {
 
 static int __init apsh4ad0a_devices_setup(void)
 {
+        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         return platform_add_devices(apsh4ad0a_devices,
                                     ARRAY_SIZE(apsh4ad0a_devices));
 }
diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c
index 90568f9de3a..20500858b56 100644
--- a/arch/sh/boards/board-magicpanelr2.c
+++ b/arch/sh/boards/board-magicpanelr2.c
@@ -14,6 +14,8 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -24,6 +26,12 @@
 #include <asm/heartbeat.h>
 #include <cpu/sh7720.h>
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 #define LAN9115_READY   (__raw_readl(0xA8000084UL) & 0x00000001UL)
 
 /* Wait until reset finished. Timeout is 100ms. */
@@ -348,6 +356,8 @@ static struct platform_device *mpr2_devices[] __initdata = {
 
 static int __init mpr2_devices_setup(void)
 {
+        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         return platform_add_devices(mpr2_devices, ARRAY_SIZE(mpr2_devices));
 }
 device_initcall(mpr2_devices_setup);
diff --git a/arch/sh/boards/board-polaris.c b/arch/sh/boards/board-polaris.c
index 37d03c097ae..37a08d09472 100644
--- a/arch/sh/boards/board-polaris.c
+++ b/arch/sh/boards/board-polaris.c
@@ -1,5 +1,5 @@
 /*
- * June 2006 steve.glendinning@smsc.com
+ * June 2006 Steve Glendinning <steve.glendinning@shawell.net>
  *
  * Polaris-specific resource declaration
  *
@@ -9,6 +9,8 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/io.h>
 #include <asm/irq.h>
@@ -22,6 +24,12 @@
 #define AREA5_WAIT_CTRL (0x1C00)
 #define WAIT_STATES_10  (0x7)
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
+};
+
 static struct resource smsc911x_resources[] = {
         [0] = {
                 .name           = "smsc911x-memory",
@@ -88,6 +96,8 @@ static int __init polaris_initialise(void)
 
         printk(KERN_INFO "Configuring Polaris external bus\n");
 
+        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         /* Configure area 5 with 2 wait states */
         wcr = __raw_readw(WCR2);
         wcr &= (~AREA5_WAIT_CTRL);
diff --git a/arch/sh/boards/board-sh2007.c b/arch/sh/boards/board-sh2007.c
index b90b78f6a82..1980bb7e578 100644
--- a/arch/sh/boards/board-sh2007.c
+++ b/arch/sh/boards/board-sh2007.c
@@ -6,6 +6,8 @@
  */
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
@@ -13,6 +15,14 @@
 #include <asm/machvec.h>
 #include <mach/sh2007.h>
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
+        REGULATOR_SUPPLY("vddvario", "smsc911x.1"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x.1"),
+};
+
 struct smsc911x_platform_config smc911x_info = {
         .flags          = SMSC911X_USE_32BIT,
         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
@@ -98,6 +108,8 @@ static struct platform_device *sh2007_devices[] __initdata = {
 
 static int __init sh2007_io_init(void)
 {
+        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         platform_add_devices(sh2007_devices, ARRAY_SIZE(sh2007_devices));
         return 0;
 }
diff --git a/arch/sh/boards/board-sh7757lcr.c b/arch/sh/boards/board-sh7757lcr.c
index 5087f8bb4cf..41f86702eb9 100644
--- a/arch/sh/boards/board-sh7757lcr.c
+++ b/arch/sh/boards/board-sh7757lcr.c
@@ -12,6 +12,8 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
 #include <linux/io.h>
@@ -199,6 +201,15 @@ static struct platform_device sh7757_eth_giga1_device = {
         },
 };
 
+/* Fixed 3.3V regulator to be used by SDHI0, MMCIF */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
+};
+
 /* SH_MMCIF */
 static struct resource sh_mmcif_resources[] = {
         [0] = {
@@ -329,6 +340,9 @@ static struct spi_board_info spi_board_info[] = {
 
 static int __init sh7757lcr_devices_setup(void)
 {
+        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+
         /* RGMII (PTA) */
         gpio_request(GPIO_FN_ET0_MDC, NULL);
         gpio_request(GPIO_FN_ET0_MDIO, NULL);
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index f33ebf44707..9e963c1d144 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -20,6 +20,8 @@
 #include <linux/mtd/sh_flctl.h>
 #include <linux/delay.h>
 #include <linux/i2c.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/gpio.h>
 #include <linux/videodev2.h>
@@ -34,6 +36,12 @@
 #include <asm/suspend.h>
 #include <cpu/sh7723.h>
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static struct smsc911x_platform_config smsc911x_config = {
         .phy_interface  = PHY_INTERFACE_MODE_MII,
         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
@@ -423,6 +431,15 @@ static struct platform_device ceu_device = {
         },
 };
 
+/* Fixed 3.3V regulators to be used by SDHI0, SDHI1 */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
+};
+
 static struct resource sdhi0_cn3_resources[] = {
         [0] = {
                 .name   = "SDHI0",
@@ -544,6 +561,10 @@ static int __init ap325rxa_devices_setup(void)
                                         &ap325rxa_sdram_leave_start,
                                         &ap325rxa_sdram_leave_end);
 
+        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+        regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         /* LD3 and LD4 LEDs */
         gpio_request(GPIO_PTX5, NULL); /* RUN */
         gpio_direction_output(GPIO_PTX5, 1);
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c
index f63d323f411..2789647abeb 100644
--- a/arch/sh/boards/mach-dreamcast/irq.c
+++ b/arch/sh/boards/mach-dreamcast/irq.c
@@ -8,10 +8,11 @@
  * This file is part of the LinuxDC project (www.linuxdc.org)
  * Released under the terms of the GNU GPL v2.0
  */
-
 #include <linux/irq.h>
 #include <linux/io.h>
-#include <asm/irq.h>
+#include <linux/irq.h>
+#include <linux/export.h>
+#include <linux/err.h>
 #include <mach/sysasic.h>
 
 /*
@@ -141,26 +142,15 @@ int systemasic_irq_demux(int irq)
 
 void systemasic_irq_init(void)
 {
-        int i, nid = cpu_to_node(boot_cpu_data);
-
-        /* Assign all virtual IRQs to the System ASIC int. handler */
-        for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) {
-                unsigned int irq;
-
-                irq = create_irq_nr(i, nid);
-                if (unlikely(irq == 0)) {
-                        pr_err("%s: failed hooking irq %d for systemasic\n",
-                               __func__, i);
-                        return;
-                }
+        int irq_base, i;
 
-                if (unlikely(irq != i)) {
-                        pr_err("%s: got irq %d but wanted %d, bailing.\n",
-                               __func__, irq, i);
-                        destroy_irq(irq);
-                        return;
-                }
+        irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,
+                                   HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1);
+        if (IS_ERR_VALUE(irq_base)) {
+                pr_err("%s: failed hooking irqs\n", __func__);
+                return;
+        }
 
+        for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
                 irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
-        }
 }
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 4158d70c0de..64559e8af14 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -19,6 +19,8 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/usb/r8a66597.h>
 #include <linux/usb/renesas_usbhs.h>
 #include <linux/i2c.h>
@@ -242,9 +244,17 @@ static int usbhs_get_id(struct platform_device *pdev)
         return gpio_get_value(GPIO_PTB3);
 }
 
+static void usbhs_phy_reset(struct platform_device *pdev)
+{
+        /* enable vbus if HOST */
+        if (!gpio_get_value(GPIO_PTB3))
+                gpio_set_value(GPIO_PTB5, 1);
+}
+
 static struct renesas_usbhs_platform_info usbhs_info = {
         .platform_callback = {
                 .get_id         = usbhs_get_id,
+                .phy_reset      = usbhs_phy_reset,
         },
         .driver_param = {
                 .buswait_bwait          = 4,
@@ -518,10 +528,86 @@ static struct i2c_board_info ts_i2c_clients = {
         .irq            = IRQ0,
 };
 
+static struct regulator_consumer_supply cn12_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
+};
+
+static struct regulator_init_data cn12_power_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(cn12_power_consumers),
+        .consumer_supplies      = cn12_power_consumers,
+};
+
+static struct fixed_voltage_config cn12_power_info = {
+        .supply_name = "CN12 SD/MMC Vdd",
+        .microvolts = 3300000,
+        .gpio = GPIO_PTB7,
+        .enable_high = 1,
+        .init_data = &cn12_power_init_data,
+};
+
+static struct platform_device cn12_power = {
+        .name = "reg-fixed-voltage",
+        .id   = 0,
+        .dev  = {
+                .platform_data = &cn12_power_info,
+        },
+};
+
 #if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
 /* SDHI0 */
+static struct regulator_consumer_supply sdhi0_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_init_data sdhi0_power_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(sdhi0_power_consumers),
+        .consumer_supplies      = sdhi0_power_consumers,
+};
+
+static struct fixed_voltage_config sdhi0_power_info = {
+        .supply_name = "CN11 SD/MMC Vdd",
+        .microvolts = 3300000,
+        .gpio = GPIO_PTB6,
+        .enable_high = 1,
+        .init_data = &sdhi0_power_init_data,
+};
+
+static struct platform_device sdhi0_power = {
+        .name = "reg-fixed-voltage",
+        .id   = 1,
+        .dev  = {
+                .platform_data = &sdhi0_power_info,
+        },
+};
+
 static void sdhi0_set_pwr(struct platform_device *pdev, int state)
 {
+        static int power_gpio = -EINVAL;
+
+        if (power_gpio < 0) {
+                int ret = gpio_request(GPIO_PTB6, NULL);
+                if (!ret) {
+                        power_gpio = GPIO_PTB6;
+                        gpio_direction_output(power_gpio, 0);
+                }
+        }
+
+        /*
+         * Toggle the GPIO regardless, whether we managed to grab it above or
+         * the fixed regulator driver did.
+         */
         gpio_set_value(GPIO_PTB6, state);
 }
 
@@ -562,13 +648,27 @@ static struct platform_device sdhi0_device = {
         },
 };
 
-#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
-/* SDHI1 */
-static void sdhi1_set_pwr(struct platform_device *pdev, int state)
+static void cn12_set_pwr(struct platform_device *pdev, int state)
 {
+        static int power_gpio = -EINVAL;
+
+        if (power_gpio < 0) {
+                int ret = gpio_request(GPIO_PTB7, NULL);
+                if (!ret) {
+                        power_gpio = GPIO_PTB7;
+                        gpio_direction_output(power_gpio, 0);
+                }
+        }
+
+        /*
+         * Toggle the GPIO regardless, whether we managed to grab it above or
+         * the fixed regulator driver did.
+         */
         gpio_set_value(GPIO_PTB7, state);
 }
 
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+/* SDHI1 */
 static int sdhi1_get_cd(struct platform_device *pdev)
 {
         return !gpio_get_value(GPIO_PTW7);
@@ -579,7 +679,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
         .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
         .tmio_caps      = MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD |
                           MMC_CAP_NEEDS_POLL,
-        .set_pwr        = sdhi1_set_pwr,
+        .set_pwr        = cn12_set_pwr,
         .get_cd         = sdhi1_get_cd,
 };
 
@@ -899,14 +999,9 @@ static struct platform_device vou_device = {
 
 #if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
 /* SH_MMCIF */
-static void mmcif_set_pwr(struct platform_device *pdev, int state)
-{
-        gpio_set_value(GPIO_PTB7, state);
-}
-
 static void mmcif_down_pwr(struct platform_device *pdev)
 {
-        gpio_set_value(GPIO_PTB7, 0);
+        cn12_set_pwr(pdev, 0);
 }
 
 static struct resource sh_mmcif_resources[] = {
@@ -929,7 +1024,7 @@ static struct resource sh_mmcif_resources[] = {
 };
 
 static struct sh_mmcif_plat_data sh_mmcif_plat = {
-        .set_pwr        = mmcif_set_pwr,
+        .set_pwr        = cn12_set_pwr,
         .down_pwr       = mmcif_down_pwr,
         .sup_pclk       = 0, /* SH7724: Max Pclk/2 */
         .caps           = MMC_CAP_4_BIT_DATA |
@@ -960,7 +1055,9 @@ static struct platform_device *ecovec_devices[] __initdata = {
         &ceu0_device,
         &ceu1_device,
         &keysc_device,
+        &cn12_power,
 #if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
+        &sdhi0_power,
         &sdhi0_device,
 #if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
         &sdhi1_device,
@@ -1258,8 +1355,6 @@ static int __init arch_setup(void)
         gpio_request(GPIO_FN_SDHI0D2,  NULL);
         gpio_request(GPIO_FN_SDHI0D1,  NULL);
         gpio_request(GPIO_FN_SDHI0D0,  NULL);
-        gpio_request(GPIO_PTB6, NULL);
-        gpio_direction_output(GPIO_PTB6, 0);
 #else
         /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
         gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
@@ -1288,8 +1383,6 @@ static int __init arch_setup(void)
         gpio_request(GPIO_FN_MMC_D0, NULL);
         gpio_request(GPIO_FN_MMC_CLK, NULL);
         gpio_request(GPIO_FN_MMC_CMD, NULL);
-        gpio_request(GPIO_PTB7, NULL);
-        gpio_direction_output(GPIO_PTB7, 0);
 
         cn12_enabled = true;
 #elif defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
@@ -1301,8 +1394,6 @@ static int __init arch_setup(void)
         gpio_request(GPIO_FN_SDHI1D2,  NULL);
         gpio_request(GPIO_FN_SDHI1D1,  NULL);
         gpio_request(GPIO_FN_SDHI1D0,  NULL);
-        gpio_request(GPIO_PTB7, NULL);
-        gpio_direction_output(GPIO_PTB7, 0);
 
         /* Card-detect, used on CN12 with SDHI1 */
         gpio_request(GPIO_PTW7, NULL);
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index 43a179ce9af..f2a4304fbe2 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -21,6 +21,8 @@
 #include <linux/input.h>
 #include <linux/input/sh_keysc.h>
 #include <linux/i2c.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/usb/r8a66597.h>
 #include <linux/videodev2.h>
 #include <linux/sh_intc.h>
@@ -341,6 +343,13 @@ static struct platform_device kfr2r09_camera = {
         },
 };
 
+/* Fixed 3.3V regulator to be used by SDHI0 */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
 static struct resource kfr2r09_sh_sdhi0_resources[] = {
         [0] = {
                 .name   = "SDHI0",
@@ -523,6 +532,9 @@ static int __init kfr2r09_devices_setup(void)
                                         &kfr2r09_sdram_leave_start,
                                         &kfr2r09_sdram_leave_end);
 
+        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+
         /* enable SCIF1 serial port for YC401 console support */
         gpio_request(GPIO_FN_SCIF1_RXD, NULL);
         gpio_request(GPIO_FN_SCIF1_TXD, NULL);
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index a8a1ca741c8..8b73194ed2c 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -17,6 +17,8 @@
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
 #include <linux/i2c.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smc91x.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
@@ -386,6 +388,13 @@ static struct platform_device migor_ceu_device = {
         },
 };
 
+/* Fixed 3.3V regulator to be used by SDHI0 */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
 static struct resource sdhi_cn9_resources[] = {
         [0] = {
                 .name   = "SDHI",
@@ -498,6 +507,10 @@ static int __init migor_devices_setup(void)
                                         &migor_sdram_enter_end,
                                         &migor_sdram_leave_start,
                                         &migor_sdram_leave_end);
+
+        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+
         /* Let D11 LED show STATUS0 */
         gpio_request(GPIO_FN_STATUS0, NULL);
 
diff --git a/arch/sh/boards/mach-rsk/setup.c b/arch/sh/boards/mach-rsk/setup.c
index 895f030070d..2685ea03b06 100644
--- a/arch/sh/boards/mach-rsk/setup.c
+++ b/arch/sh/boards/mach-rsk/setup.c
@@ -16,9 +16,17 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/map.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <asm/machvec.h>
 #include <asm/io.h>
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static const char *part_probes[] = { "cmdlinepart", NULL };
 
 static struct mtd_partition rsk_partitions[] = {
@@ -67,6 +75,8 @@ static struct platform_device *rsk_devices[] __initdata = {
 
 static int __init rsk_devices_setup(void)
 {
+        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         return platform_add_devices(rsk_devices,
                                     ARRAY_SIZE(rsk_devices));
 }
diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c
index 27a2314f50a..c29268bfd34 100644
--- a/arch/sh/boards/mach-sdk7786/setup.c
+++ b/arch/sh/boards/mach-sdk7786/setup.c
@@ -11,6 +11,8 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smsc911x.h>
 #include <linux/i2c.h>
 #include <linux/irq.h>
@@ -38,6 +40,12 @@ static struct platform_device heartbeat_device = {
         .resource       = &heartbeat_resource,
 };
 
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static struct resource smsc911x_resources[] = {
         [0] = {
                 .name           = "smsc911x-memory",
@@ -236,6 +244,8 @@ static void __init sdk7786_setup(char **cmdline_p)
 {
         pr_info("Renesas Technology Europe SDK7786 support:\n");
 
+        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
         sdk7786_fpga_init();
         sdk7786_nmi_init();
 
diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c
index fd45ffc4834..7646bf0486c 100644
--- a/arch/sh/boards/mach-se/7343/irq.c
+++ b/arch/sh/boards/mach-se/7343/irq.c
@@ -1,86 +1,129 @@
 /*
- * linux/arch/sh/boards/se/7343/irq.c
+ * Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
  *
  * Copyright (C) 2008  Yoshihiro Shimoda
+ * Copyright (C) 2012  Paul Mundt
  *
- * Based on linux/arch/sh/boards/se/7722/irq.c
+ * Based on linux/arch/sh/boards/se/7343/irq.c
  * Copyright (C) 2007  Nobuhiro Iwamatsu
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
+#define DRV_NAME "SE7343-FPGA"
+#define pr_fmt(fmt) DRV_NAME ": " fmt
+
+#define irq_reg_readl   ioread16
+#define irq_reg_writel  iowrite16
+
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <asm/sizes.h>
 #include <mach-se/mach/se7343.h>
 
-unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
+#define PA_CPLD_BASE_ADDR       0x11400000
+#define PA_CPLD_ST_REG          0x08    /* CPLD Interrupt status register */
+#define PA_CPLD_IMSK_REG        0x0a    /* CPLD Interrupt mask register */
 
-static void disable_se7343_irq(struct irq_data *data)
-{
-        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
-        __raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
-}
+static void __iomem *se7343_irq_regs;
+struct irq_domain *se7343_irq_domain;
 
-static void enable_se7343_irq(struct irq_data *data)
+static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
-        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
-        __raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
-}
+        struct irq_data *data = irq_get_irq_data(irq);
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
+        unsigned long mask;
+        int bit;
 
-static struct irq_chip se7343_irq_chip __read_mostly = {
-        .name           = "SE7343-FPGA",
-        .irq_mask       = disable_se7343_irq,
-        .irq_unmask     = enable_se7343_irq,
-};
+        chip->irq_mask_ack(data);
 
-static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
+        mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
+
+        for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
+                generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit));
+
+        chip->irq_unmask(data);
+}
+
+static void __init se7343_domain_init(void)
 {
-        unsigned short intv = __raw_readw(PA_CPLD_ST);
-        unsigned int ext_irq = 0;
+        int i;
 
-        intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
+        se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR,
+                                                  &irq_domain_simple_ops, NULL);
+        if (unlikely(!se7343_irq_domain)) {
+                printk("Failed to get IRQ domain\n");
+                return;
+        }
 
-        for (; intv; intv >>= 1, ext_irq++) {
-                if (!(intv & 1))
-                        continue;
+        for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
+                int irq = irq_create_mapping(se7343_irq_domain, i);
 
-                generic_handle_irq(se7343_fpga_irq[ext_irq]);
+                if (unlikely(irq == 0)) {
+                        printk("Failed to allocate IRQ %d\n", i);
+                        return;
+                }
         }
 }
 
-/*
- * Initialize IRQ setting
- */
-void __init init_7343se_IRQ(void)
+static void __init se7343_gc_init(void)
 {
-        int i, irq;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        unsigned int irq_base;
 
-        __raw_writew(0, PA_CPLD_IMSK);  /* disable all irqs */
-        __raw_writew(0x2000, 0xb03fffec);       /* mrshpc irq enable */
+        irq_base = irq_linear_revmap(se7343_irq_domain, 0);
 
-        for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
-                irq = create_irq();
-                if (irq < 0)
-                        return;
-                se7343_fpga_irq[i] = irq;
+        gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs,
+                                    handle_level_irq);
+        if (unlikely(!gc))
+                return;
 
-                irq_set_chip_and_handler_name(se7343_fpga_irq[i],
-                                              &se7343_irq_chip,
-                                              handle_level_irq,
-                                              "level");
+        ct = gc->chip_types;
+        ct->chip.irq_mask = irq_gc_mask_set_bit;
+        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 
-                irq_set_chip_data(se7343_fpga_irq[i], (void *)i);
-        }
+        ct->regs.mask = PA_CPLD_IMSK_REG;
+
+        irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
+                               IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 
         irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
         irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
+
         irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
         irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
+
         irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
         irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
+
         irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
         irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
 }
+
+/*
+ * Initialize IRQ setting
+ */
+void __init init_7343se_IRQ(void)
+{
+        se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16);
+        if (unlikely(!se7343_irq_regs)) {
+                pr_err("Failed to remap CPLD\n");
+                return;
+        }
+
+        /*
+         * All FPGA IRQs disabled by default
+         */
+        iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG);
+
+        __raw_writew(0x2000, 0xb03fffec);       /* mrshpc irq enable */
+
+        se7343_domain_init();
+        se7343_gc_init();
+}
diff --git a/arch/sh/boards/mach-se/7343/setup.c b/arch/sh/boards/mach-se/7343/setup.c
index d2370af56d7..8ce4f2a202a 100644
--- a/arch/sh/boards/mach-se/7343/setup.c
+++ b/arch/sh/boards/mach-se/7343/setup.c
@@ -5,6 +5,7 @@
 #include <linux/serial_reg.h>
 #include <linux/usb/isp116x.h>
 #include <linux/delay.h>
+#include <linux/irqdomain.h>
 #include <asm/machvec.h>
 #include <mach-se/mach/se7343.h>
 #include <asm/heartbeat.h>
@@ -145,11 +146,12 @@ static struct platform_device *sh7343se_platform_devices[] __initdata = {
 static int __init sh7343se_devices_setup(void)
 {
         /* Wire-up dynamic vectors */
-        serial_platform_data[0].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTA];
-        serial_platform_data[1].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTB];
-
+        serial_platform_data[0].irq = irq_find_mapping(se7343_irq_domain,
+                                                       SE7343_FPGA_IRQ_UARTA);
+        serial_platform_data[1].irq = irq_find_mapping(se7343_irq_domain,
+                                                       SE7343_FPGA_IRQ_UARTB);
         usb_resources[2].start = usb_resources[2].end =
-                se7343_fpga_irq[SE7343_FPGA_IRQ_USB];
+                irq_find_mapping(se7343_irq_domain, SE7343_FPGA_IRQ_USB);
 
         return platform_add_devices(sh7343se_platform_devices,
                                     ARRAY_SIZE(sh7343se_platform_devices));
diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c
index aac92f21ebd..f5e2af1bf04 100644
--- a/arch/sh/boards/mach-se/7722/irq.c
+++ b/arch/sh/boards/mach-se/7722/irq.c
@@ -1,79 +1,96 @@
 /*
- * linux/arch/sh/boards/se/7722/irq.c
+ * Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
  *
  * Copyright (C) 2007  Nobuhiro Iwamatsu
- *
- * Hitachi UL SolutionEngine 7722 Support.
+ * Copyright (C) 2012  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  */
+#define DRV_NAME "SE7722-FPGA"
+#define pr_fmt(fmt) DRV_NAME ": " fmt
+
+#define irq_reg_readl   ioread16
+#define irq_reg_writel  iowrite16
+
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
-#include <asm/irq.h>
-#include <asm/io.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <asm/sizes.h>
 #include <mach-se/mach/se7722.h>
 
-unsigned int se7722_fpga_irq[SE7722_FPGA_IRQ_NR] = { 0, };
+#define IRQ01_BASE_ADDR 0x11800000
+#define IRQ01_MODE_REG  0
+#define IRQ01_STS_REG   4
+#define IRQ01_MASK_REG  8
 
-static void disable_se7722_irq(struct irq_data *data)
-{
-        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
-        __raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
-}
+static void __iomem *se7722_irq_regs;
+struct irq_domain *se7722_irq_domain;
 
-static void enable_se7722_irq(struct irq_data *data)
+static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
-        unsigned int bit = (unsigned int)irq_data_get_irq_chip_data(data);
-        __raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);
-}
+        struct irq_data *data = irq_get_irq_data(irq);
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
+        unsigned long mask;
+        int bit;
 
-static struct irq_chip se7722_irq_chip __read_mostly = {
-        .name           = "SE7722-FPGA",
-        .irq_mask       = disable_se7722_irq,
-        .irq_unmask     = enable_se7722_irq,
-};
+        chip->irq_mask_ack(data);
 
-static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
+        mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
+
+        for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
+                generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));
+
+        chip->irq_unmask(data);
+}
+
+static void __init se7722_domain_init(void)
 {
-        unsigned short intv = __raw_readw(IRQ01_STS);
-        unsigned int ext_irq = 0;
+        int i;
 
-        intv &= (1 << SE7722_FPGA_IRQ_NR) - 1;
+        se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
+                                                  &irq_domain_simple_ops, NULL);
+        if (unlikely(!se7722_irq_domain)) {
+                printk("Failed to get IRQ domain\n");
+                return;
+        }
 
-        for (; intv; intv >>= 1, ext_irq++) {
-                if (!(intv & 1))
-                        continue;
+        for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
+                int irq = irq_create_mapping(se7722_irq_domain, i);
 
-                generic_handle_irq(se7722_fpga_irq[ext_irq]);
+                if (unlikely(irq == 0)) {
+                        printk("Failed to allocate IRQ %d\n", i);
+                        return;
+                }
         }
 }
 
-/*
- * Initialize IRQ setting
- */
-void __init init_se7722_IRQ(void)
+static void __init se7722_gc_init(void)
 {
-        int i, irq;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        unsigned int irq_base;
 
-        __raw_writew(0, IRQ01_MASK);       /* disable all irqs */
-        __raw_writew(0x2000, 0xb03fffec);  /* mrshpc irq enable */
+        irq_base = irq_linear_revmap(se7722_irq_domain, 0);
 
-        for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
-                irq = create_irq();
-                if (irq < 0)
-                        return;
-                se7722_fpga_irq[i] = irq;
+        gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
+                                    handle_level_irq);
+        if (unlikely(!gc))
+                return;
 
-                irq_set_chip_and_handler_name(se7722_fpga_irq[i],
-                                              &se7722_irq_chip,
-                                              handle_level_irq,
-                                              "level");
+        ct = gc->chip_types;
+        ct->chip.irq_mask = irq_gc_mask_set_bit;
+        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 
-                irq_set_chip_data(se7722_fpga_irq[i], (void *)i);
-        }
+        ct->regs.mask = IRQ01_MASK_REG;
+
+        irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
+                               IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 
         irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
         irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
@@ -81,3 +98,25 @@ void __init init_se7722_IRQ(void)
         irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
         irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
 }
+
+/*
+ * Initialize FPGA IRQs
+ */
+void __init init_se7722_IRQ(void)
+{
+        se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
+        if (unlikely(!se7722_irq_regs)) {
+                printk("Failed to remap IRQ01 regs\n");
+                return;
+        }
+
+        /*
+         * All FPGA IRQs disabled by default
+         */
+        iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);
+
+        __raw_writew(0x2000, 0xb03fffec);  /* mrshpc irq enable */
+
+        se7722_domain_init();
+        se7722_gc_init();
+}
diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c
index 8f7f0550cfd..e04e2bc4698 100644
--- a/arch/sh/boards/mach-se/7722/setup.c
+++ b/arch/sh/boards/mach-se/7722/setup.c
@@ -2,6 +2,7 @@
  * linux/arch/sh/boards/se/7722/setup.c
  *
  * Copyright (C) 2007 Nobuhiro Iwamatsu
+ * Copyright (C) 2012 Paul Mundt
  *
  * Hitachi UL SolutionEngine 7722 Support.
  *
@@ -15,6 +16,7 @@
 #include <linux/ata_platform.h>
 #include <linux/input.h>
 #include <linux/input/sh_keysc.h>
+#include <linux/irqdomain.h>
 #include <linux/smc91x.h>
 #include <linux/sh_intc.h>
 #include <mach-se/mach/se7722.h>
@@ -143,10 +145,10 @@ static int __init se7722_devices_setup(void)
 
         /* Wire-up dynamic vectors */
         cf_ide_resources[2].start = cf_ide_resources[2].end =
-                se7722_fpga_irq[SE7722_FPGA_IRQ_MRSHPC0];
+                irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_MRSHPC0);
 
         smc91x_eth_resources[1].start = smc91x_eth_resources[1].end =
-                se7722_fpga_irq[SE7722_FPGA_IRQ_SMC];
+                irq_find_mapping(se7722_irq_domain, SE7722_FPGA_IRQ_SMC);
 
         return platform_add_devices(se7722_devices, ARRAY_SIZE(se7722_devices));
 }
diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c
index c6342ce7768..5d1d3ec9a6c 100644
--- a/arch/sh/boards/mach-se/7724/irq.c
+++ b/arch/sh/boards/mach-se/7724/irq.c
@@ -17,8 +17,10 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/interrupt.h>
-#include <asm/irq.h>
-#include <asm/io.h>
+#include <linux/export.h>
+#include <linux/topology.h>
+#include <linux/io.h>
+#include <linux/err.h>
 #include <mach-se/mach/se7724.h>
 
 struct fpga_irq {
@@ -111,7 +113,7 @@ static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
  */
 void __init init_se7724_IRQ(void)
 {
-        int i, nid = cpu_to_node(boot_cpu_data);
+        int irq_base, i;
 
         __raw_writew(0xffff, IRQ0_MR);  /* mask all */
         __raw_writew(0xffff, IRQ1_MR);  /* mask all */
@@ -121,28 +123,16 @@ void __init init_se7724_IRQ(void)
         __raw_writew(0x0000, IRQ2_SR);  /* clear irq */
         __raw_writew(0x002a, IRQ_MODE); /* set irq type */
 
-        for (i = 0; i < SE7724_FPGA_IRQ_NR; i++) {
-                int irq, wanted;
-
-                wanted = SE7724_FPGA_IRQ_BASE + i;
-
-                irq = create_irq_nr(wanted, nid);
-                if (unlikely(irq == 0)) {
-                        pr_err("%s: failed hooking irq %d for FPGA\n",
-                               __func__, wanted);
-                        return;
-                }
-
-                if (unlikely(irq != wanted)) {
-                        pr_err("%s: got irq %d but wanted %d, bailing.\n",
-                               __func__, irq, wanted);
-                        destroy_irq(irq);
-                        return;
-                }
+        irq_base = irq_alloc_descs(SE7724_FPGA_IRQ_BASE, SE7724_FPGA_IRQ_BASE,
+                                   SE7724_FPGA_IRQ_NR, numa_node_id());
+        if (IS_ERR_VALUE(irq_base)) {
+                pr_err("%s: failed hooking irqs for FPGA\n", __func__);
+                return;
+        }
 
-                irq_set_chip_and_handler_name(irq, &se7724_irq_chip,
+        for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
+                irq_set_chip_and_handler_name(irq_base + i, &se7724_irq_chip,
                                               handle_level_irq, "level");
-        }
 
         irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux);
         irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index ffbf5bc7366..35f6efa3ac0 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -18,6 +18,8 @@
 #include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/physmap.h>
 #include <linux/delay.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <linux/smc91x.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
@@ -454,6 +456,15 @@ static struct platform_device sh7724_usb1_gadget_device = {
         .resource       = sh7724_usb1_gadget_resources,
 };
 
+/* Fixed 3.3V regulator to be used by SDHI0, SDHI1 */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] =
+{
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+        REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
+};
+
 static struct resource sdhi0_cn7_resources[] = {
         [0] = {
                 .name   = "SDHI0",
@@ -684,6 +695,10 @@ static int __init devices_setup(void)
                                         &ms7724se_sdram_enter_end,
                                         &ms7724se_sdram_leave_start,
                                         &ms7724se_sdram_leave_end);
+
+        regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
+                                     ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+
         /* Reset Release */
         fpga_out = __raw_readw(FPGA_OUT);
         /* bit4: NTSC_PDN, bit5: NTSC_RESET */
diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c
index f33b2b57019..3ea65e9b56e 100644
--- a/arch/sh/boards/mach-x3proto/gpio.c
+++ b/arch/sh/boards/mach-x3proto/gpio.c
@@ -3,7 +3,7 @@
  *
  * Renesas SH-X3 Prototype Baseboard GPIO Support.
  *
- * Copyright (C) 2010  Paul Mundt
+ * Copyright (C) 2010 - 2012  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -17,6 +17,7 @@
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/spinlock.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
 #include <mach/ilsel.h>
 #include <mach/hardware.h>
@@ -26,7 +27,7 @@
 #define KEYDETR 0xb81c0004
 
 static DEFINE_SPINLOCK(x3proto_gpio_lock);
-static unsigned int x3proto_gpio_irq_map[NR_BASEBOARD_GPIOS] = { 0, };
+static struct irq_domain *x3proto_irq_domain;
 
 static int x3proto_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 {
@@ -49,7 +50,14 @@ static int x3proto_gpio_get(struct gpio_chip *chip, unsigned gpio)
 
 static int x3proto_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
 {
-        return x3proto_gpio_irq_map[gpio];
+        int virq;
+
+        if (gpio < chip->ngpio)
+                virq = irq_create_mapping(x3proto_irq_domain, gpio);
+        else
+                virq = -ENXIO;
+
+        return virq;
 }
 
 static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
@@ -62,9 +70,8 @@ static void x3proto_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
         chip->irq_mask_ack(data);
 
         mask = __raw_readw(KEYDETR);
-
         for_each_set_bit(pin, &mask, NR_BASEBOARD_GPIOS)
-                generic_handle_irq(x3proto_gpio_to_irq(NULL, pin));
+                generic_handle_irq(irq_linear_revmap(x3proto_irq_domain, pin));
 
         chip->irq_unmask(data);
 }
@@ -78,10 +85,23 @@ struct gpio_chip x3proto_gpio_chip = {
         .ngpio                  = NR_BASEBOARD_GPIOS,
 };
 
+static int x3proto_gpio_irq_map(struct irq_domain *domain, unsigned int virq,
+                                irq_hw_number_t hwirq)
+{
+        irq_set_chip_and_handler_name(virq, &dummy_irq_chip, handle_simple_irq,
+                                      "gpio");
+
+        return 0;
+}
+
+static struct irq_domain_ops x3proto_gpio_irq_ops = {
+        .map    = x3proto_gpio_irq_map,
+        .xlate  = irq_domain_xlate_twocell,
+};
+
 int __init x3proto_gpio_setup(void)
 {
-        int ilsel;
-        int ret, i;
+        int ilsel, ret;
 
         ilsel = ilsel_enable(ILSEL_KEY);
         if (unlikely(ilsel < 0))
@@ -91,21 +111,10 @@ int __init x3proto_gpio_setup(void)
         if (unlikely(ret))
                 goto err_gpio;
 
-        for (i = 0; i < NR_BASEBOARD_GPIOS; i++) {
-                unsigned long flags;
-                int irq = create_irq();
-
-                if (unlikely(irq < 0)) {
-                        ret = -EINVAL;
-                        goto err_irq;
-                }
-
-                spin_lock_irqsave(&x3proto_gpio_lock, flags);
-                x3proto_gpio_irq_map[i] = irq;
-                irq_set_chip_and_handler_name(irq, &dummy_irq_chip,
-                                              handle_simple_irq, "gpio");
-                spin_unlock_irqrestore(&x3proto_gpio_lock, flags);
-        }
+        x3proto_irq_domain = irq_domain_add_linear(NULL, NR_BASEBOARD_GPIOS,
+                                                   &x3proto_gpio_irq_ops, NULL);
+        if (unlikely(!x3proto_irq_domain))
+                goto err_irq;
 
         pr_info("registering '%s' support, handling GPIOs %u -> %u, "
                 "bound to IRQ %u\n",
@@ -119,10 +128,6 @@ int __init x3proto_gpio_setup(void)
         return 0;
 
 err_irq:
-        for (; i >= 0; --i)
-                if (x3proto_gpio_irq_map[i])
-                        destroy_irq(x3proto_gpio_irq_map[i]);
-
         ret = gpiochip_remove(&x3proto_gpio_chip);
         if (unlikely(ret))
                 pr_err("Failed deregistering GPIO\n");
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c
index eb4ea4d44d5..e9735616bdc 100644
--- a/arch/sh/cchips/hd6446x/hd64461.c
+++ b/arch/sh/cchips/hd6446x/hd64461.c
@@ -73,10 +73,7 @@ static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
 
 int __init setup_hd64461(void)
 {
-        int i, nid = cpu_to_node(boot_cpu_data);
-
-        if (!MACH_HD64461)
-                return 0;
+        int irq_base, i;
 
         printk(KERN_INFO
                "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
@@ -89,28 +86,16 @@ int __init setup_hd64461(void)
 #endif
         __raw_writew(0xffff, HD64461_NIMR);
 
-        /*  IRQ 80 -> 95 belongs to HD64461  */
-        for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) {
-                unsigned int irq;
-
-                irq = create_irq_nr(i, nid);
-                if (unlikely(irq == 0)) {
-                        pr_err("%s: failed hooking irq %d for HD64461\n",
-                               __func__, i);
-                        return -EBUSY;
-                }
-
-                if (unlikely(irq != i)) {
-                        pr_err("%s: got irq %d but wanted %d, bailing.\n",
-                               __func__, irq, i);
-                        destroy_irq(irq);
-                        return -EINVAL;
-                }
-
-                irq_set_chip_and_handler(i, &hd64461_irq_chip,
-                                         handle_level_irq);
+        irq_base = irq_alloc_descs(HD64461_IRQBASE, HD64461_IRQBASE, 16, -1);
+        if (IS_ERR_VALUE(irq_base)) {
+                pr_err("%s: failed hooking irqs for HD64461\n", __func__);
+                return irq_base;
         }
 
+        for (i = 0; i < 16; i++)
+                irq_set_chip_and_handler(irq_base + i, &hd64461_irq_chip,
+                                         handle_level_irq);
+
         irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
         irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
 
diff --git a/arch/sh/configs/apsh4ad0a_defconfig b/arch/sh/configs/apsh4ad0a_defconfig
index e7583484cc0..95ae23fcfdd 100644
--- a/arch/sh/configs/apsh4ad0a_defconfig
+++ b/arch/sh/configs/apsh4ad0a_defconfig
@@ -11,7 +11,7 @@ CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_CGROUP_MEMCG=y
 CONFIG_BLK_CGROUP=y
 CONFIG_NAMESPACES=y
 CONFIG_BLK_DEV_INITRD=y
diff --git a/arch/sh/configs/sdk7786_defconfig b/arch/sh/configs/sdk7786_defconfig
index 8a7dd7b59c5..76a76a295d7 100644
--- a/arch/sh/configs/sdk7786_defconfig
+++ b/arch/sh/configs/sdk7786_defconfig
@@ -18,8 +18,8 @@ CONFIG_CPUSETS=y
 # CONFIG_PROC_PID_CPUSET is not set
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_MEM_RES_CTLR=y
-CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
+CONFIG_CGROUP_MEMCG=y
+CONFIG_CGROUP_MEMCG_SWAP=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_CGROUP=y
diff --git a/arch/sh/configs/se7206_defconfig b/arch/sh/configs/se7206_defconfig
index 72c3fad7383..6bc30ab9fd1 100644
--- a/arch/sh/configs/se7206_defconfig
+++ b/arch/sh/configs/se7206_defconfig
@@ -11,7 +11,7 @@ CONFIG_CGROUP_DEBUG=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_CGROUP_MEMCG=y
 CONFIG_RELAY=y
 CONFIG_NAMESPACES=y
 CONFIG_UTS_NS=y
diff --git a/arch/sh/configs/shx3_defconfig b/arch/sh/configs/shx3_defconfig
index 6bb41303689..cd6c519f8fa 100644
--- a/arch/sh/configs/shx3_defconfig
+++ b/arch/sh/configs/shx3_defconfig
@@ -13,7 +13,7 @@ CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_CGROUP_MEMCG=y
 CONFIG_RELAY=y
 CONFIG_NAMESPACES=y
 CONFIG_UTS_NS=y
diff --git a/arch/sh/configs/urquell_defconfig b/arch/sh/configs/urquell_defconfig
index 8bfa4d056d7..d7f89be9f47 100644
--- a/arch/sh/configs/urquell_defconfig
+++ b/arch/sh/configs/urquell_defconfig
@@ -15,8 +15,8 @@ CONFIG_CPUSETS=y
 # CONFIG_PROC_PID_CPUSET is not set
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_MEM_RES_CTLR=y
-CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
+CONFIG_CGROUP_MEMCG=y
+CONFIG_CGROUP_MEMCG_SWAP=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_DEV_INITRD=y
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 4c171f13b0e..b2256562314 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -335,7 +335,7 @@ static int dmae_irq_init(void)
 
         for (n = 0; n < NR_DMAE; n++) {
                 int i = request_irq(get_dma_error_irq(n), dma_err,
-                                    IRQF_SHARED, dmae_name[n], NULL);
+                                    IRQF_SHARED, dmae_name[n], (void *)dmae_name[n]);
                 if (unlikely(i < 0)) {
                         printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
                         return i;
diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c
index edeea8960c3..a5fe1b54c95 100644
--- a/arch/sh/drivers/pci/fixups-dreamcast.c
+++ b/arch/sh/drivers/pci/fixups-dreamcast.c
@@ -28,7 +28,7 @@
 #include <asm/irq.h>
 #include <mach/pci.h>
 
-static void __init gapspci_fixup_resources(struct pci_dev *dev)
+static void __devinit gapspci_fixup_resources(struct pci_dev *dev)
 {
         struct pci_channel *p = dev->sysdata;
 
diff --git a/arch/sh/drivers/pci/fixups-sdk7786.c b/arch/sh/drivers/pci/fixups-sdk7786.c
index 0e18ee33255..36eb6fc3c18 100644
--- a/arch/sh/drivers/pci/fixups-sdk7786.c
+++ b/arch/sh/drivers/pci/fixups-sdk7786.c
@@ -23,9 +23,9 @@
  * Misconfigurations can be detected through the FPGA via the slot
  * resistors to determine card presence. Hotplug remains unsupported.
  */
-static unsigned int slot4en __devinitdata;
+static unsigned int slot4en __initdata;
 
-char *__devinit pcibios_setup(char *str)
+char *__init pcibios_setup(char *str)
 {
         if (strcmp(str, "slot4en") == 0) {
                 slot4en = 1;
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 9d10a3cb879..40db2d0aef3 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -59,7 +59,7 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
         need_domain_info = need_domain_info || hose->index;
         hose->need_domain_info = need_domain_info;
         if (bus) {
-                next_busno = bus->subordinate + 1;
+                next_busno = bus->busn_res.end + 1;
                 /* Don't allow 8-bit bus number overflow inside the hose -
                    reserve some space for bridges. */
                 if (next_busno > 224) {
@@ -197,11 +197,6 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq)
         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 }
 
-char * __devinit __weak pcibios_setup(char *str)
-{
-        return str;
-}
-
 static void __init
 pcibios_bus_report_status_early(struct pci_channel *hose,
                                 int top_bus, int current_bus,
diff --git a/arch/sh/include/asm/bug.h b/arch/sh/include/asm/bug.h
index 2b87d86bfc4..dcf27807542 100644
--- a/arch/sh/include/asm/bug.h
+++ b/arch/sh/include/asm/bug.h
@@ -110,6 +110,10 @@ do {							\
 #include <asm-generic/bug.h>
 
 struct pt_regs;
+
+/* arch/sh/kernel/traps.c */
 extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
+extern void die_if_kernel(const char *str, struct pt_regs *regs, long err);
+extern void die_if_no_fixup(const char *str, struct pt_regs *regs, long err);
 
 #endif /* __ASM_SH_BUG_H */
diff --git a/arch/sh/include/asm/kdebug.h b/arch/sh/include/asm/kdebug.h
index a6201f10c27..8d6a831e7ba 100644
--- a/arch/sh/include/asm/kdebug.h
+++ b/arch/sh/include/asm/kdebug.h
@@ -10,6 +10,8 @@ enum die_val {
         DIE_SSTEP,
 };
 
+/* arch/sh/kernel/dumpstack.c */
 extern void printk_address(unsigned long address, int reliable);
+extern void dump_mem(const char *str, unsigned long bottom, unsigned long top);
 
 #endif /* __ASM_SH_KDEBUG_H */
diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h
index 4a5350037c8..1b6199740e9 100644
--- a/arch/sh/include/asm/sections.h
+++ b/arch/sh/include/asm/sections.h
@@ -6,7 +6,6 @@
 extern long __nosave_begin, __nosave_end;
 extern long __machvec_start, __machvec_end;
 extern char __uncached_start, __uncached_end;
-extern char _ebss[];
 extern char __start_eh_frame[], __stop_eh_frame[];
 
 #endif /* __ASM_SH_SECTIONS_H */
diff --git a/arch/sh/include/asm/siu.h b/arch/sh/include/asm/siu.h
index 1d95c78808d..580b7ac228b 100644
--- a/arch/sh/include/asm/siu.h
+++ b/arch/sh/include/asm/siu.h
@@ -14,7 +14,6 @@
 struct device;
 
 struct siu_platform {
-        struct device *dma_dev;
         unsigned int dma_slave_tx_a;
         unsigned int dma_slave_rx_a;
         unsigned int dma_slave_tx_b;
diff --git a/arch/sh/include/asm/unistd.h b/arch/sh/include/asm/unistd.h
index e800a38c9f8..7bc67076baa 100644
--- a/arch/sh/include/asm/unistd.h
+++ b/arch/sh/include/asm/unistd.h
@@ -6,7 +6,6 @@
 # endif
 
 # define __ARCH_WANT_SYS_RT_SIGSUSPEND
-# define __ARCH_WANT_IPC_PARSE_VERSION
 # define __ARCH_WANT_OLD_READDIR
 # define __ARCH_WANT_OLD_STAT
 # define __ARCH_WANT_STAT64
diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7269.h b/arch/sh/include/cpu-sh2a/cpu/sh7269.h
index 48d14498e77..2a0ca8780f0 100644
--- a/arch/sh/include/cpu-sh2a/cpu/sh7269.h
+++ b/arch/sh/include/cpu-sh2a/cpu/sh7269.h
@@ -183,18 +183,30 @@ enum {
         GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0,
         GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK,
         GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE,
-        GPIO_FN_LCD_DATA23, GPIO_FN_LCD_DATA22,
-        GPIO_FN_LCD_DATA21, GPIO_FN_LCD_DATA20,
-        GPIO_FN_LCD_DATA19, GPIO_FN_LCD_DATA18,
-        GPIO_FN_LCD_DATA17, GPIO_FN_LCD_DATA16,
-        GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
-        GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
-        GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
-        GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
-        GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
-        GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
-        GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
-        GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
+        GPIO_FN_LCD_DATA23_PG23, GPIO_FN_LCD_DATA22_PG22,
+        GPIO_FN_LCD_DATA21_PG21, GPIO_FN_LCD_DATA20_PG20,
+        GPIO_FN_LCD_DATA19_PG19, GPIO_FN_LCD_DATA18_PG18,
+        GPIO_FN_LCD_DATA17_PG17, GPIO_FN_LCD_DATA16_PG16,
+        GPIO_FN_LCD_DATA15_PG15, GPIO_FN_LCD_DATA14_PG14,
+        GPIO_FN_LCD_DATA13_PG13, GPIO_FN_LCD_DATA12_PG12,
+        GPIO_FN_LCD_DATA11_PG11, GPIO_FN_LCD_DATA10_PG10,
+        GPIO_FN_LCD_DATA9_PG9, GPIO_FN_LCD_DATA8_PG8,
+        GPIO_FN_LCD_DATA7_PG7, GPIO_FN_LCD_DATA6_PG6,
+        GPIO_FN_LCD_DATA5_PG5, GPIO_FN_LCD_DATA4_PG4,
+        GPIO_FN_LCD_DATA3_PG3, GPIO_FN_LCD_DATA2_PG2,
+        GPIO_FN_LCD_DATA1_PG1, GPIO_FN_LCD_DATA0_PG0,
+        GPIO_FN_LCD_DATA23_PJ23, GPIO_FN_LCD_DATA22_PJ22,
+        GPIO_FN_LCD_DATA21_PJ21, GPIO_FN_LCD_DATA20_PJ20,
+        GPIO_FN_LCD_DATA19_PJ19, GPIO_FN_LCD_DATA18_PJ18,
+        GPIO_FN_LCD_DATA17_PJ17, GPIO_FN_LCD_DATA16_PJ16,
+        GPIO_FN_LCD_DATA15_PJ15, GPIO_FN_LCD_DATA14_PJ14,
+        GPIO_FN_LCD_DATA13_PJ13, GPIO_FN_LCD_DATA12_PJ12,
+        GPIO_FN_LCD_DATA11_PJ11, GPIO_FN_LCD_DATA10_PJ10,
+        GPIO_FN_LCD_DATA9_PJ9, GPIO_FN_LCD_DATA8_PJ8,
+        GPIO_FN_LCD_DATA7_PJ7, GPIO_FN_LCD_DATA6_PJ6,
+        GPIO_FN_LCD_DATA5_PJ5, GPIO_FN_LCD_DATA4_PJ4,
+        GPIO_FN_LCD_DATA3_PJ3, GPIO_FN_LCD_DATA2_PJ2,
+        GPIO_FN_LCD_DATA1_PJ1, GPIO_FN_LCD_DATA0_PJ0,
         GPIO_FN_LCD_M_DISP,
 };
 
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h
index 41f9f8b9db7..5340f3bc186 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7757.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h
@@ -283,5 +283,7 @@ enum {
         SHDMA_SLAVE_RIIC8_RX,
         SHDMA_SLAVE_RIIC9_TX,
         SHDMA_SLAVE_RIIC9_RX,
+        SHDMA_SLAVE_RSPI_TX,
+        SHDMA_SLAVE_RSPI_RX,
 };
 #endif /* __ASM_SH7757_H__ */
diff --git a/arch/sh/include/mach-se/mach/se7343.h b/arch/sh/include/mach-se/mach/se7343.h
index 50b5d575dff..542521c970c 100644
--- a/arch/sh/include/mach-se/mach/se7343.h
+++ b/arch/sh/include/mach-se/mach/se7343.h
@@ -50,9 +50,6 @@
 #define PA_LED          0xb0C00000      /* LED */
 #define LED_SHIFT       0
 #define PA_DIPSW        0xb0900000      /* Dip switch 31 */
-#define PA_CPLD_MODESET 0xb1400004      /* CPLD Mode set register */
-#define PA_CPLD_ST      0xb1400008      /* CPLD Interrupt status register */
-#define PA_CPLD_IMSK    0xb140000a      /* CPLD Interrupt mask register */
 /* Area 5 */
 #define PA_EXT5         0x14000000
 #define PA_EXT5_SIZE    0x04000000
@@ -135,8 +132,10 @@
 
 #define SE7343_FPGA_IRQ_NR      12
 
+struct irq_domain;
+
 /* arch/sh/boards/se/7343/irq.c */
-extern unsigned int se7343_fpga_irq[];
+extern struct irq_domain *se7343_irq_domain;
 
 void init_7343se_IRQ(void);
 
diff --git a/arch/sh/include/mach-se/mach/se7722.h b/arch/sh/include/mach-se/mach/se7722.h
index 201081ebdbc..637e7ac753f 100644
--- a/arch/sh/include/mach-se/mach/se7722.h
+++ b/arch/sh/include/mach-se/mach/se7722.h
@@ -81,12 +81,6 @@
 #define IRQ0_IRQ        evt2irq(0x600)
 #define IRQ1_IRQ        evt2irq(0x620)
 
-#define IRQ01_MODE      0xb1800000
-#define IRQ01_STS       0xb1800004
-#define IRQ01_MASK      0xb1800008
-
-/* Bits in IRQ01_* registers */
-
 #define SE7722_FPGA_IRQ_USB     0 /* IRQ0 */
 #define SE7722_FPGA_IRQ_SMC     1 /* IRQ0 */
 #define SE7722_FPGA_IRQ_MRSHPC0 2 /* IRQ1 */
@@ -95,8 +89,10 @@
 #define SE7722_FPGA_IRQ_MRSHPC3 5 /* IRQ1 */
 #define SE7722_FPGA_IRQ_NR      6
 
+struct irq_domain;
+
 /* arch/sh/boards/se/7722/irq.c */
-extern unsigned int se7722_fpga_irq[];
+extern struct irq_domain *se7722_irq_domain;
 
 void init_se7722_IRQ(void);
 
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
index f25127c46ec..039e4587dd9 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -758,12 +758,22 @@ enum {
         DV_DATA3_MARK, DV_DATA2_MARK, DV_DATA1_MARK, DV_DATA0_MARK,
         LCD_CLK_MARK, LCD_EXTCLK_MARK,
         LCD_VSYNC_MARK, LCD_HSYNC_MARK, LCD_DE_MARK,
-        LCD_DATA23_MARK, LCD_DATA22_MARK, LCD_DATA21_MARK, LCD_DATA20_MARK,
-        LCD_DATA19_MARK, LCD_DATA18_MARK, LCD_DATA17_MARK, LCD_DATA16_MARK,
-        LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK,
-        LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK,
-        LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK,
-        LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK,
+        LCD_DATA23_PG23_MARK, LCD_DATA22_PG22_MARK, LCD_DATA21_PG21_MARK,
+        LCD_DATA20_PG20_MARK, LCD_DATA19_PG19_MARK, LCD_DATA18_PG18_MARK,
+        LCD_DATA17_PG17_MARK, LCD_DATA16_PG16_MARK, LCD_DATA15_PG15_MARK,
+        LCD_DATA14_PG14_MARK, LCD_DATA13_PG13_MARK, LCD_DATA12_PG12_MARK,
+        LCD_DATA11_PG11_MARK, LCD_DATA10_PG10_MARK, LCD_DATA9_PG9_MARK,
+        LCD_DATA8_PG8_MARK, LCD_DATA7_PG7_MARK, LCD_DATA6_PG6_MARK,
+        LCD_DATA5_PG5_MARK, LCD_DATA4_PG4_MARK, LCD_DATA3_PG3_MARK,
+        LCD_DATA2_PG2_MARK, LCD_DATA1_PG1_MARK, LCD_DATA0_PG0_MARK,
+        LCD_DATA23_PJ23_MARK, LCD_DATA22_PJ22_MARK, LCD_DATA21_PJ21_MARK,
+        LCD_DATA20_PJ20_MARK, LCD_DATA19_PJ19_MARK, LCD_DATA18_PJ18_MARK,
+        LCD_DATA17_PJ17_MARK, LCD_DATA16_PJ16_MARK, LCD_DATA15_PJ15_MARK,
+        LCD_DATA14_PJ14_MARK, LCD_DATA13_PJ13_MARK, LCD_DATA12_PJ12_MARK,
+        LCD_DATA11_PJ11_MARK, LCD_DATA10_PJ10_MARK, LCD_DATA9_PJ9_MARK,
+        LCD_DATA8_PJ8_MARK, LCD_DATA7_PJ7_MARK, LCD_DATA6_PJ6_MARK,
+        LCD_DATA5_PJ5_MARK, LCD_DATA4_PJ4_MARK, LCD_DATA3_PJ3_MARK,
+        LCD_DATA2_PJ2_MARK, LCD_DATA1_PJ1_MARK, LCD_DATA0_PJ0_MARK,
         LCD_TCON6_MARK, LCD_TCON5_MARK, LCD_TCON4_MARK,
         LCD_TCON3_MARK, LCD_TCON2_MARK, LCD_TCON1_MARK, LCD_TCON0_MARK,
         LCD_M_DISP_MARK,
@@ -1036,6 +1046,7 @@ static pinmux_enum_t pinmux_data[] = {
 
         PINMUX_DATA(PF1_DATA, PF1MD_000),
         PINMUX_DATA(BACK_MARK, PF1MD_001),
+        PINMUX_DATA(SSL10_MARK, PF1MD_011),
         PINMUX_DATA(TIOC4B_MARK, PF1MD_100),
         PINMUX_DATA(DACK0_MARK, PF1MD_101),
 
@@ -1049,47 +1060,50 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(PG27_DATA, PG27MD_00),
         PINMUX_DATA(LCD_TCON2_MARK, PG27MD_10),
         PINMUX_DATA(LCD_EXTCLK_MARK, PG27MD_11),
+        PINMUX_DATA(LCD_DE_MARK, PG27MD_11),
 
         PINMUX_DATA(PG26_DATA, PG26MD_00),
         PINMUX_DATA(LCD_TCON1_MARK, PG26MD_10),
+        PINMUX_DATA(LCD_HSYNC_MARK, PG26MD_10),
 
         PINMUX_DATA(PG25_DATA, PG25MD_00),
         PINMUX_DATA(LCD_TCON0_MARK, PG25MD_10),
+        PINMUX_DATA(LCD_VSYNC_MARK, PG25MD_10),
 
         PINMUX_DATA(PG24_DATA, PG24MD_00),
         PINMUX_DATA(LCD_CLK_MARK, PG24MD_10),
 
         PINMUX_DATA(PG23_DATA, PG23MD_000),
-        PINMUX_DATA(LCD_DATA23_MARK, PG23MD_010),
+        PINMUX_DATA(LCD_DATA23_PG23_MARK, PG23MD_010),
         PINMUX_DATA(LCD_TCON6_MARK, PG23MD_011),
         PINMUX_DATA(TXD5_MARK, PG23MD_100),
 
         PINMUX_DATA(PG22_DATA, PG22MD_000),
-        PINMUX_DATA(LCD_DATA22_MARK, PG22MD_010),
+        PINMUX_DATA(LCD_DATA22_PG22_MARK, PG22MD_010),
         PINMUX_DATA(LCD_TCON5_MARK, PG22MD_011),
         PINMUX_DATA(RXD5_MARK, PG22MD_100),
 
         PINMUX_DATA(PG21_DATA, PG21MD_000),
         PINMUX_DATA(DV_DATA7_MARK, PG21MD_001),
-        PINMUX_DATA(LCD_DATA21_MARK, PG21MD_010),
+        PINMUX_DATA(LCD_DATA21_PG21_MARK, PG21MD_010),
         PINMUX_DATA(LCD_TCON4_MARK, PG21MD_011),
         PINMUX_DATA(TXD4_MARK, PG21MD_100),
 
         PINMUX_DATA(PG20_DATA, PG20MD_000),
         PINMUX_DATA(DV_DATA6_MARK, PG20MD_001),
-        PINMUX_DATA(LCD_DATA20_MARK, PG21MD_010),
+        PINMUX_DATA(LCD_DATA20_PG20_MARK, PG21MD_010),
         PINMUX_DATA(LCD_TCON3_MARK, PG20MD_011),
         PINMUX_DATA(RXD4_MARK, PG20MD_100),
 
         PINMUX_DATA(PG19_DATA, PG19MD_000),
         PINMUX_DATA(DV_DATA5_MARK, PG19MD_001),
-        PINMUX_DATA(LCD_DATA19_MARK, PG19MD_010),
+        PINMUX_DATA(LCD_DATA19_PG19_MARK, PG19MD_010),
         PINMUX_DATA(SPDIF_OUT_MARK, PG19MD_011),
         PINMUX_DATA(SCK5_MARK, PG19MD_100),
 
         PINMUX_DATA(PG18_DATA, PG18MD_000),
         PINMUX_DATA(DV_DATA4_MARK, PG18MD_001),
-        PINMUX_DATA(LCD_DATA18_MARK, PG18MD_010),
+        PINMUX_DATA(LCD_DATA18_PG18_MARK, PG18MD_010),
         PINMUX_DATA(SPDIF_IN_MARK, PG18MD_011),
         PINMUX_DATA(SCK4_MARK, PG18MD_100),
 
@@ -1097,103 +1111,103 @@ static pinmux_enum_t pinmux_data[] = {
 // we're going with 2 bits
         PINMUX_DATA(PG17_DATA, PG17MD_00),
         PINMUX_DATA(WE3ICIOWRAHDQMUU_MARK, PG17MD_01),
-        PINMUX_DATA(LCD_DATA17_MARK, PG17MD_10),
+        PINMUX_DATA(LCD_DATA17_PG17_MARK, PG17MD_10),
 
 // TODO hardware manual has PG16 3 bits wide in reg picture and 2 bits in description
 // we're going with 2 bits
         PINMUX_DATA(PG16_DATA, PG16MD_00),
         PINMUX_DATA(WE2ICIORDDQMUL_MARK, PG16MD_01),
-        PINMUX_DATA(LCD_DATA16_MARK, PG16MD_10),
+        PINMUX_DATA(LCD_DATA16_PG16_MARK, PG16MD_10),
 
         PINMUX_DATA(PG15_DATA, PG15MD_00),
         PINMUX_DATA(D31_MARK, PG15MD_01),
-        PINMUX_DATA(LCD_DATA15_MARK, PG15MD_10),
+        PINMUX_DATA(LCD_DATA15_PG15_MARK, PG15MD_10),
         PINMUX_DATA(PINT7_PG_MARK, PG15MD_11),
 
         PINMUX_DATA(PG14_DATA, PG14MD_00),
         PINMUX_DATA(D30_MARK, PG14MD_01),
-        PINMUX_DATA(LCD_DATA14_MARK, PG14MD_10),
+        PINMUX_DATA(LCD_DATA14_PG14_MARK, PG14MD_10),
         PINMUX_DATA(PINT6_PG_MARK, PG14MD_11),
 
         PINMUX_DATA(PG13_DATA, PG13MD_00),
         PINMUX_DATA(D29_MARK, PG13MD_01),
-        PINMUX_DATA(LCD_DATA13_MARK, PG13MD_10),
+        PINMUX_DATA(LCD_DATA13_PG13_MARK, PG13MD_10),
         PINMUX_DATA(PINT5_PG_MARK, PG13MD_11),
 
         PINMUX_DATA(PG12_DATA, PG12MD_00),
         PINMUX_DATA(D28_MARK, PG12MD_01),
-        PINMUX_DATA(LCD_DATA12_MARK, PG12MD_10),
+        PINMUX_DATA(LCD_DATA12_PG12_MARK, PG12MD_10),
         PINMUX_DATA(PINT4_PG_MARK, PG12MD_11),
 
         PINMUX_DATA(PG11_DATA, PG11MD_000),
         PINMUX_DATA(D27_MARK, PG11MD_001),
-        PINMUX_DATA(LCD_DATA11_MARK, PG11MD_010),
+        PINMUX_DATA(LCD_DATA11_PG11_MARK, PG11MD_010),
         PINMUX_DATA(PINT3_PG_MARK, PG11MD_011),
         PINMUX_DATA(TIOC3D_MARK, PG11MD_100),
 
         PINMUX_DATA(PG10_DATA, PG10MD_000),
         PINMUX_DATA(D26_MARK, PG10MD_001),
-        PINMUX_DATA(LCD_DATA10_MARK, PG10MD_010),
+        PINMUX_DATA(LCD_DATA10_PG10_MARK, PG10MD_010),
         PINMUX_DATA(PINT2_PG_MARK, PG10MD_011),
         PINMUX_DATA(TIOC3C_MARK, PG10MD_100),
 
         PINMUX_DATA(PG9_DATA, PG9MD_000),
         PINMUX_DATA(D25_MARK, PG9MD_001),
-        PINMUX_DATA(LCD_DATA9_MARK, PG9MD_010),
+        PINMUX_DATA(LCD_DATA9_PG9_MARK, PG9MD_010),
         PINMUX_DATA(PINT1_PG_MARK, PG9MD_011),
         PINMUX_DATA(TIOC3B_MARK, PG9MD_100),
 
         PINMUX_DATA(PG8_DATA, PG8MD_000),
         PINMUX_DATA(D24_MARK, PG8MD_001),
-        PINMUX_DATA(LCD_DATA8_MARK, PG8MD_010),
+        PINMUX_DATA(LCD_DATA8_PG8_MARK, PG8MD_010),
         PINMUX_DATA(PINT0_PG_MARK, PG8MD_011),
         PINMUX_DATA(TIOC3A_MARK, PG8MD_100),
 
         PINMUX_DATA(PG7_DATA, PG7MD_000),
         PINMUX_DATA(D23_MARK, PG7MD_001),
-        PINMUX_DATA(LCD_DATA7_MARK, PG7MD_010),
+        PINMUX_DATA(LCD_DATA7_PG7_MARK, PG7MD_010),
         PINMUX_DATA(IRQ7_PG_MARK, PG7MD_011),
         PINMUX_DATA(TIOC2B_MARK, PG7MD_100),
 
         PINMUX_DATA(PG6_DATA, PG6MD_000),
         PINMUX_DATA(D22_MARK, PG6MD_001),
-        PINMUX_DATA(LCD_DATA6_MARK, PG6MD_010),
+        PINMUX_DATA(LCD_DATA6_PG6_MARK, PG6MD_010),
         PINMUX_DATA(IRQ6_PG_MARK, PG6MD_011),
         PINMUX_DATA(TIOC2A_MARK, PG6MD_100),
 
         PINMUX_DATA(PG5_DATA, PG5MD_000),
         PINMUX_DATA(D21_MARK, PG5MD_001),
-        PINMUX_DATA(LCD_DATA5_MARK, PG5MD_010),
+        PINMUX_DATA(LCD_DATA5_PG5_MARK, PG5MD_010),
         PINMUX_DATA(IRQ5_PG_MARK, PG5MD_011),
         PINMUX_DATA(TIOC1B_MARK, PG5MD_100),
 
         PINMUX_DATA(PG4_DATA, PG4MD_000),
         PINMUX_DATA(D20_MARK, PG4MD_001),
-        PINMUX_DATA(LCD_DATA4_MARK, PG4MD_010),
+        PINMUX_DATA(LCD_DATA4_PG4_MARK, PG4MD_010),
         PINMUX_DATA(IRQ4_PG_MARK, PG4MD_011),
         PINMUX_DATA(TIOC1A_MARK, PG4MD_100),
 
         PINMUX_DATA(PG3_DATA, PG3MD_000),
         PINMUX_DATA(D19_MARK, PG3MD_001),
-        PINMUX_DATA(LCD_DATA3_MARK, PG3MD_010),
+        PINMUX_DATA(LCD_DATA3_PG3_MARK, PG3MD_010),
         PINMUX_DATA(IRQ3_PG_MARK, PG3MD_011),
         PINMUX_DATA(TIOC0D_MARK, PG3MD_100),
 
         PINMUX_DATA(PG2_DATA, PG2MD_000),
         PINMUX_DATA(D18_MARK, PG2MD_001),
-        PINMUX_DATA(LCD_DATA2_MARK, PG2MD_010),
+        PINMUX_DATA(LCD_DATA2_PG2_MARK, PG2MD_010),
         PINMUX_DATA(IRQ2_PG_MARK, PG2MD_011),
         PINMUX_DATA(TIOC0C_MARK, PG2MD_100),
 
         PINMUX_DATA(PG1_DATA, PG1MD_000),
         PINMUX_DATA(D17_MARK, PG1MD_001),
-        PINMUX_DATA(LCD_DATA1_MARK, PG1MD_010),
+        PINMUX_DATA(LCD_DATA1_PG1_MARK, PG1MD_010),
         PINMUX_DATA(IRQ1_PG_MARK, PG1MD_011),
         PINMUX_DATA(TIOC0B_MARK, PG1MD_100),
 
         PINMUX_DATA(PG0_DATA, PG0MD_000),
         PINMUX_DATA(D16_MARK, PG0MD_001),
-        PINMUX_DATA(LCD_DATA0_MARK, PG0MD_010),
+        PINMUX_DATA(LCD_DATA0_PG0_MARK, PG0MD_010),
         PINMUX_DATA(IRQ0_PG_MARK, PG0MD_011),
         PINMUX_DATA(TIOC0A_MARK, PG0MD_100),
 
@@ -1275,14 +1289,14 @@ static pinmux_enum_t pinmux_data[] = {
 
         PINMUX_DATA(PJ23_DATA, PJ23MD_000),
         PINMUX_DATA(DV_DATA23_MARK, PJ23MD_001),
-        PINMUX_DATA(LCD_DATA23_MARK, PJ23MD_010),
+        PINMUX_DATA(LCD_DATA23_PJ23_MARK, PJ23MD_010),
         PINMUX_DATA(LCD_TCON6_MARK, PJ23MD_011),
         PINMUX_DATA(IRQ3_PJ_MARK, PJ23MD_100),
         PINMUX_DATA(CTX1_MARK, PJ23MD_101),
 
         PINMUX_DATA(PJ22_DATA, PJ22MD_000),
         PINMUX_DATA(DV_DATA22_MARK, PJ22MD_001),
-        PINMUX_DATA(LCD_DATA22_MARK, PJ22MD_010),
+        PINMUX_DATA(LCD_DATA22_PJ22_MARK, PJ22MD_010),
         PINMUX_DATA(LCD_TCON5_MARK, PJ22MD_011),
         PINMUX_DATA(IRQ2_PJ_MARK, PJ22MD_100),
         PINMUX_DATA(CRX1_MARK, PJ22MD_101),
@@ -1290,14 +1304,14 @@ static pinmux_enum_t pinmux_data[] = {
 
         PINMUX_DATA(PJ21_DATA, PJ21MD_000),
         PINMUX_DATA(DV_DATA21_MARK, PJ21MD_001),
-        PINMUX_DATA(LCD_DATA21_MARK, PJ21MD_010),
+        PINMUX_DATA(LCD_DATA21_PJ21_MARK, PJ21MD_010),
         PINMUX_DATA(LCD_TCON4_MARK, PJ21MD_011),
         PINMUX_DATA(IRQ1_PJ_MARK, PJ21MD_100),
         PINMUX_DATA(CTX2_MARK, PJ21MD_101),
 
         PINMUX_DATA(PJ20_DATA, PJ20MD_000),
         PINMUX_DATA(DV_DATA20_MARK, PJ20MD_001),
-        PINMUX_DATA(LCD_DATA20_MARK, PJ20MD_010),
+        PINMUX_DATA(LCD_DATA20_PJ20_MARK, PJ20MD_010),
         PINMUX_DATA(LCD_TCON3_MARK, PJ20MD_011),
         PINMUX_DATA(IRQ0_PJ_MARK, PJ20MD_100),
         PINMUX_DATA(CRX2_MARK, PJ20MD_101),
@@ -1305,7 +1319,7 @@ static pinmux_enum_t pinmux_data[] = {
 
         PINMUX_DATA(PJ19_DATA, PJ19MD_000),
         PINMUX_DATA(DV_DATA19_MARK, PJ19MD_001),
-        PINMUX_DATA(LCD_DATA19_MARK, PJ19MD_010),
+        PINMUX_DATA(LCD_DATA19_PJ19_MARK, PJ19MD_010),
         PINMUX_DATA(MISO0_PJ19_MARK, PJ19MD_011),
         PINMUX_DATA(TIOC0D_MARK, PJ19MD_100),
         PINMUX_DATA(SIOFRXD_MARK, PJ19MD_101),
@@ -1313,126 +1327,126 @@ static pinmux_enum_t pinmux_data[] = {
 
         PINMUX_DATA(PJ18_DATA, PJ18MD_000),
         PINMUX_DATA(DV_DATA18_MARK, PJ18MD_001),
-        PINMUX_DATA(LCD_DATA18_MARK, PJ18MD_010),
+        PINMUX_DATA(LCD_DATA18_PJ18_MARK, PJ18MD_010),
         PINMUX_DATA(MOSI0_PJ18_MARK, PJ18MD_011),
         PINMUX_DATA(TIOC0C_MARK, PJ18MD_100),
         PINMUX_DATA(SIOFTXD_MARK, PJ18MD_101),
 
         PINMUX_DATA(PJ17_DATA, PJ17MD_000),
         PINMUX_DATA(DV_DATA17_MARK, PJ17MD_001),
-        PINMUX_DATA(LCD_DATA17_MARK, PJ17MD_010),
+        PINMUX_DATA(LCD_DATA17_PJ17_MARK, PJ17MD_010),
         PINMUX_DATA(SSL00_PJ17_MARK, PJ17MD_011),
         PINMUX_DATA(TIOC0B_MARK, PJ17MD_100),
         PINMUX_DATA(SIOFSYNC_MARK, PJ17MD_101),
 
         PINMUX_DATA(PJ16_DATA, PJ16MD_000),
         PINMUX_DATA(DV_DATA16_MARK, PJ16MD_001),
-        PINMUX_DATA(LCD_DATA16_MARK, PJ16MD_010),
+        PINMUX_DATA(LCD_DATA16_PJ16_MARK, PJ16MD_010),
         PINMUX_DATA(RSPCK0_PJ16_MARK, PJ16MD_011),
         PINMUX_DATA(TIOC0A_MARK, PJ16MD_100),
         PINMUX_DATA(SIOFSCK_MARK, PJ16MD_101),
 
         PINMUX_DATA(PJ15_DATA, PJ15MD_000),
         PINMUX_DATA(DV_DATA15_MARK, PJ15MD_001),
-        PINMUX_DATA(LCD_DATA15_MARK, PJ15MD_010),
+        PINMUX_DATA(LCD_DATA15_PJ15_MARK, PJ15MD_010),
         PINMUX_DATA(PINT7_PJ_MARK, PJ15MD_011),
         PINMUX_DATA(PWM2H_MARK, PJ15MD_100),
         PINMUX_DATA(TXD7_MARK, PJ15MD_101),
 
         PINMUX_DATA(PJ14_DATA, PJ14MD_000),
         PINMUX_DATA(DV_DATA14_MARK, PJ14MD_001),
-        PINMUX_DATA(LCD_DATA14_MARK, PJ14MD_010),
+        PINMUX_DATA(LCD_DATA14_PJ14_MARK, PJ14MD_010),
         PINMUX_DATA(PINT6_PJ_MARK, PJ14MD_011),
         PINMUX_DATA(PWM2G_MARK, PJ14MD_100),
         PINMUX_DATA(TXD6_MARK, PJ14MD_101),
 
         PINMUX_DATA(PJ13_DATA, PJ13MD_000),
         PINMUX_DATA(DV_DATA13_MARK, PJ13MD_001),
-        PINMUX_DATA(LCD_DATA13_MARK, PJ13MD_010),
+        PINMUX_DATA(LCD_DATA13_PJ13_MARK, PJ13MD_010),
         PINMUX_DATA(PINT5_PJ_MARK, PJ13MD_011),
         PINMUX_DATA(PWM2F_MARK, PJ13MD_100),
         PINMUX_DATA(TXD5_MARK, PJ13MD_101),
 
         PINMUX_DATA(PJ12_DATA, PJ12MD_000),
         PINMUX_DATA(DV_DATA12_MARK, PJ12MD_001),
-        PINMUX_DATA(LCD_DATA12_MARK, PJ12MD_010),
+        PINMUX_DATA(LCD_DATA12_PJ12_MARK, PJ12MD_010),
         PINMUX_DATA(PINT4_PJ_MARK, PJ12MD_011),
         PINMUX_DATA(PWM2E_MARK, PJ12MD_100),
         PINMUX_DATA(SCK7_MARK, PJ12MD_101),
 
         PINMUX_DATA(PJ11_DATA, PJ11MD_000),
         PINMUX_DATA(DV_DATA11_MARK, PJ11MD_001),
-        PINMUX_DATA(LCD_DATA11_MARK, PJ11MD_010),
+        PINMUX_DATA(LCD_DATA11_PJ11_MARK, PJ11MD_010),
         PINMUX_DATA(PINT3_PJ_MARK, PJ11MD_011),
         PINMUX_DATA(PWM2D_MARK, PJ11MD_100),
         PINMUX_DATA(SCK6_MARK, PJ11MD_101),
 
         PINMUX_DATA(PJ10_DATA, PJ10MD_000),
         PINMUX_DATA(DV_DATA10_MARK, PJ10MD_001),
-        PINMUX_DATA(LCD_DATA10_MARK, PJ10MD_010),
+        PINMUX_DATA(LCD_DATA10_PJ10_MARK, PJ10MD_010),
         PINMUX_DATA(PINT2_PJ_MARK, PJ10MD_011),
         PINMUX_DATA(PWM2C_MARK, PJ10MD_100),
         PINMUX_DATA(SCK5_MARK, PJ10MD_101),
 
         PINMUX_DATA(PJ9_DATA, PJ9MD_000),
         PINMUX_DATA(DV_DATA9_MARK, PJ9MD_001),
-        PINMUX_DATA(LCD_DATA9_MARK, PJ9MD_010),
+        PINMUX_DATA(LCD_DATA9_PJ9_MARK, PJ9MD_010),
         PINMUX_DATA(PINT1_PJ_MARK, PJ9MD_011),
         PINMUX_DATA(PWM2B_MARK, PJ9MD_100),
         PINMUX_DATA(RTS5_MARK, PJ9MD_101),
 
         PINMUX_DATA(PJ8_DATA, PJ8MD_000),
         PINMUX_DATA(DV_DATA8_MARK, PJ8MD_001),
-        PINMUX_DATA(LCD_DATA8_MARK, PJ8MD_010),
+        PINMUX_DATA(LCD_DATA8_PJ8_MARK, PJ8MD_010),
         PINMUX_DATA(PINT0_PJ_MARK, PJ8MD_011),
         PINMUX_DATA(PWM2A_MARK, PJ8MD_100),
         PINMUX_DATA(CTS5_MARK, PJ8MD_101),
 
         PINMUX_DATA(PJ7_DATA, PJ7MD_000),
         PINMUX_DATA(DV_DATA7_MARK, PJ7MD_001),
-        PINMUX_DATA(LCD_DATA7_MARK, PJ7MD_010),
+        PINMUX_DATA(LCD_DATA7_PJ7_MARK, PJ7MD_010),
         PINMUX_DATA(SD_D2_MARK, PJ7MD_011),
         PINMUX_DATA(PWM1H_MARK, PJ7MD_100),
 
         PINMUX_DATA(PJ6_DATA, PJ6MD_000),
         PINMUX_DATA(DV_DATA6_MARK, PJ6MD_001),
-        PINMUX_DATA(LCD_DATA6_MARK, PJ6MD_010),
+        PINMUX_DATA(LCD_DATA6_PJ6_MARK, PJ6MD_010),
         PINMUX_DATA(SD_D3_MARK, PJ6MD_011),
         PINMUX_DATA(PWM1G_MARK, PJ6MD_100),
 
         PINMUX_DATA(PJ5_DATA, PJ5MD_000),
         PINMUX_DATA(DV_DATA5_MARK, PJ5MD_001),
-        PINMUX_DATA(LCD_DATA5_MARK, PJ5MD_010),
+        PINMUX_DATA(LCD_DATA5_PJ5_MARK, PJ5MD_010),
         PINMUX_DATA(SD_CMD_MARK, PJ5MD_011),
         PINMUX_DATA(PWM1F_MARK, PJ5MD_100),
 
         PINMUX_DATA(PJ4_DATA, PJ4MD_000),
         PINMUX_DATA(DV_DATA4_MARK, PJ4MD_001),
-        PINMUX_DATA(LCD_DATA4_MARK, PJ4MD_010),
+        PINMUX_DATA(LCD_DATA4_PJ4_MARK, PJ4MD_010),
         PINMUX_DATA(SD_CLK_MARK, PJ4MD_011),
         PINMUX_DATA(PWM1E_MARK, PJ4MD_100),
 
         PINMUX_DATA(PJ3_DATA, PJ3MD_000),
         PINMUX_DATA(DV_DATA3_MARK, PJ3MD_001),
-        PINMUX_DATA(LCD_DATA3_MARK, PJ3MD_010),
+        PINMUX_DATA(LCD_DATA3_PJ3_MARK, PJ3MD_010),
         PINMUX_DATA(SD_D0_MARK, PJ3MD_011),
         PINMUX_DATA(PWM1D_MARK, PJ3MD_100),
 
         PINMUX_DATA(PJ2_DATA, PJ2MD_000),
         PINMUX_DATA(DV_DATA2_MARK, PJ2MD_001),
-        PINMUX_DATA(LCD_DATA2_MARK, PJ2MD_010),
+        PINMUX_DATA(LCD_DATA2_PJ2_MARK, PJ2MD_010),
         PINMUX_DATA(SD_D1_MARK, PJ2MD_011),
         PINMUX_DATA(PWM1C_MARK, PJ2MD_100),
 
         PINMUX_DATA(PJ1_DATA, PJ1MD_000),
         PINMUX_DATA(DV_DATA1_MARK, PJ1MD_001),
-        PINMUX_DATA(LCD_DATA1_MARK, PJ1MD_010),
+        PINMUX_DATA(LCD_DATA1_PJ1_MARK, PJ1MD_010),
         PINMUX_DATA(SD_WP_MARK, PJ1MD_011),
         PINMUX_DATA(PWM1B_MARK, PJ1MD_100),
 
         PINMUX_DATA(PJ0_DATA, PJ0MD_000),
         PINMUX_DATA(DV_DATA0_MARK, PJ0MD_001),
-        PINMUX_DATA(LCD_DATA0_MARK, PJ0MD_010),
+        PINMUX_DATA(LCD_DATA0_PJ0_MARK, PJ0MD_010),
         PINMUX_DATA(SD_CD_MARK, PJ0MD_011),
         PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
 };
@@ -1877,30 +1891,55 @@ static struct pinmux_gpio pinmux_gpios[] = {
         PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
         PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
 
-        PINMUX_GPIO(GPIO_FN_LCD_DATA23, LCD_DATA23_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA22, LCD_DATA22_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA21, LCD_DATA21_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA20, LCD_DATA20_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA19, LCD_DATA19_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA18, LCD_DATA18_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA17, LCD_DATA17_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA16, LCD_DATA16_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
-        PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA23_PG23, LCD_DATA23_PG23_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA22_PG22, LCD_DATA22_PG22_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA21_PG21, LCD_DATA21_PG21_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA20_PG20, LCD_DATA20_PG20_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA19_PG19, LCD_DATA19_PG19_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA18_PG18, LCD_DATA18_PG18_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA17_PG17, LCD_DATA17_PG17_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA16_PG16, LCD_DATA16_PG16_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA15_PG15, LCD_DATA15_PG15_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA14_PG14, LCD_DATA14_PG14_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA13_PG13, LCD_DATA13_PG13_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA12_PG12, LCD_DATA12_PG12_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA11_PG11, LCD_DATA11_PG11_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA10_PG10, LCD_DATA10_PG10_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA9_PG9, LCD_DATA9_PG9_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA8_PG8, LCD_DATA8_PG8_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA7_PG7, LCD_DATA7_PG7_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA6_PG6, LCD_DATA6_PG6_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA5_PG5, LCD_DATA5_PG5_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA4_PG4, LCD_DATA4_PG4_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA3_PG3, LCD_DATA3_PG3_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA2_PG2, LCD_DATA2_PG2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA1_PG1, LCD_DATA1_PG1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA0_PG0, LCD_DATA0_PG0_MARK),
+
+        PINMUX_GPIO(GPIO_FN_LCD_DATA23_PJ23, LCD_DATA23_PJ23_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA22_PJ22, LCD_DATA22_PJ22_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA21_PJ21, LCD_DATA21_PJ21_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA20_PJ20, LCD_DATA20_PJ20_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA19_PJ19, LCD_DATA19_PJ19_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA18_PJ18, LCD_DATA18_PJ18_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA17_PJ17, LCD_DATA17_PJ17_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA16_PJ16, LCD_DATA16_PJ16_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA15_PJ15, LCD_DATA15_PJ15_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA14_PJ14, LCD_DATA14_PJ14_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA13_PJ13, LCD_DATA13_PJ13_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA12_PJ12, LCD_DATA12_PJ12_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA11_PJ11, LCD_DATA11_PJ11_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA10_PJ10, LCD_DATA10_PJ10_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA9_PJ9, LCD_DATA9_PJ9_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA8_PJ8, LCD_DATA8_PJ8_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA7_PJ7, LCD_DATA7_PJ7_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA6_PJ6, LCD_DATA6_PJ6_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA5_PJ5, LCD_DATA5_PJ5_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA4_PJ4, LCD_DATA4_PJ4_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA3_PJ3, LCD_DATA3_PJ3_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA2_PJ2, LCD_DATA2_PJ2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA1_PJ1, LCD_DATA1_PJ1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA0_PJ0, LCD_DATA0_PJ0_MARK),
 
         PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
 };
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index c87e78f7323..5f30f805d2f 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -334,8 +334,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
         CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
         CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
-        CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
-        CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
+        CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[HWBLK_USB1]),
+        CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[HWBLK_USB0]),
         CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]),
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]),
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 0f5a21907da..6a868b091c2 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -12,6 +12,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_timer.h>
 #include <linux/sh_intc.h>
 #include <linux/uio_driver.h>
@@ -512,7 +513,6 @@ static struct platform_device tmu2_device = {
 };
 
 static struct siu_platform siu_platform_data = {
-        .dma_dev        = &dma_device.dev,
         .dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
         .dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
         .dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index a7708425afa..4a2f357f4df 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -216,6 +216,20 @@ static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
                                   TS_INDEX2VAL(XMIT_SZ_8BIT),
                 .mid_rid        = 0x42,
         },
+        {
+                .slave_id       = SHDMA_SLAVE_RSPI_TX,
+                .addr           = 0xfe480004,
+                .chcr           = SM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc1,
+        },
+        {
+                .slave_id       = SHDMA_SLAVE_RSPI_RX,
+                .addr           = 0xfe480004,
+                .chcr           = DM_INC | 0x800 | 0x40000000 |
+                                  TS_INDEX2VAL(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc2,
+        },
 };
 
 static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
diff --git a/arch/sh/kernel/cpu/sh5/unwind.c b/arch/sh/kernel/cpu/sh5/unwind.c
index b205b25eaf4..10aed41757f 100644
--- a/arch/sh/kernel/cpu/sh5/unwind.c
+++ b/arch/sh/kernel/cpu/sh5/unwind.c
@@ -16,6 +16,8 @@
 #include <asm/ptrace.h>
 #include <asm/processor.h>
 #include <asm/io.h>
+#include <asm/unwinder.h>
+#include <asm/stacktrace.h>
 
 static u8 regcache[63];
 
@@ -199,8 +201,11 @@ static int lookup_prev_stack_frame(unsigned long fp, unsigned long pc,
         return 0;
 }
 
-/* Don't put this on the stack since we'll want to call sh64_unwind
- * when we're close to underflowing the stack anyway. */
+/*
+ * Don't put this on the stack since we'll want to call in to
+ * sh64_unwinder_dump() when we're close to underflowing the stack
+ * anyway.
+ */
 static struct pt_regs here_regs;
 
 extern const char syscall_ret;
@@ -208,17 +213,19 @@ extern const char ret_from_syscall;
 extern const char ret_from_exception;
 extern const char ret_from_irq;
 
-static void sh64_unwind_inner(struct pt_regs *regs);
+static void sh64_unwind_inner(const struct stacktrace_ops *ops,
+                              void *data, struct pt_regs *regs);
 
-static void unwind_nested (unsigned long pc, unsigned long fp)
+static inline void unwind_nested(const struct stacktrace_ops *ops, void *data,
+                                 unsigned long pc, unsigned long fp)
 {
         if ((fp >= __MEMORY_START) &&
-            ((fp & 7) == 0)) {
-                sh64_unwind_inner((struct pt_regs *) fp);
-        }
+            ((fp & 7) == 0))
+                sh64_unwind_inner(ops, data, (struct pt_regs *)fp);
 }
 
-static void sh64_unwind_inner(struct pt_regs *regs)
+static void sh64_unwind_inner(const struct stacktrace_ops *ops,
+                              void *data, struct pt_regs *regs)
 {
         unsigned long pc, fp;
         int ofs = 0;
@@ -232,29 +239,29 @@ static void sh64_unwind_inner(struct pt_regs *regs)
                 int cond;
                 unsigned long next_fp, next_pc;
 
-                if (pc == ((unsigned long) &syscall_ret & ~1)) {
+                if (pc == ((unsigned long)&syscall_ret & ~1)) {
                         printk("SYSCALL\n");
-                        unwind_nested(pc,fp);
+                        unwind_nested(ops, data, pc, fp);
                         return;
                 }
 
-                if (pc == ((unsigned long) &ret_from_syscall & ~1)) {
+                if (pc == ((unsigned long)&ret_from_syscall & ~1)) {
                         printk("SYSCALL (PREEMPTED)\n");
-                        unwind_nested(pc,fp);
+                        unwind_nested(ops, data, pc, fp);
                         return;
                 }
 
                 /* In this case, the PC is discovered by lookup_prev_stack_frame but
                    it has 4 taken off it to look like the 'caller' */
-                if (pc == ((unsigned long) &ret_from_exception & ~1)) {
+                if (pc == ((unsigned long)&ret_from_exception & ~1)) {
                         printk("EXCEPTION\n");
-                        unwind_nested(pc,fp);
+                        unwind_nested(ops, data, pc, fp);
                         return;
                 }
 
-                if (pc == ((unsigned long) &ret_from_irq & ~1)) {
+                if (pc == ((unsigned long)&ret_from_irq & ~1)) {
                         printk("IRQ\n");
-                        unwind_nested(pc,fp);
+                        unwind_nested(ops, data, pc, fp);
                         return;
                 }
 
@@ -263,8 +270,7 @@ static void sh64_unwind_inner(struct pt_regs *regs)
 
                 pc -= ofs;
 
-                printk("[<%08lx>] ", pc);
-                print_symbol("%s\n", pc);
+                ops->address(data, pc, 1);
 
                 if (first_pass) {
                         /* If the innermost frame is a leaf function, it's
@@ -287,10 +293,13 @@ static void sh64_unwind_inner(struct pt_regs *regs)
         }
 
         printk("\n");
-
 }
 
-void sh64_unwind(struct pt_regs *regs)
+static void sh64_unwinder_dump(struct task_struct *task,
+                               struct pt_regs *regs,
+                               unsigned long *sp,
+                               const struct stacktrace_ops *ops,
+                               void *data)
 {
         if (!regs) {
                 /*
@@ -320,7 +329,17 @@ void sh64_unwind(struct pt_regs *regs)
                 );
         }
 
-        printk("\nCall Trace:\n");
-        sh64_unwind_inner(regs);
+        sh64_unwind_inner(ops, data, regs);
 }
 
+static struct unwinder sh64_unwinder = {
+        .name   = "sh64-unwinder",
+        .dump   = sh64_unwinder_dump,
+        .rating = 150,
+};
+
+static int __init sh64_unwinder_init(void)
+{
+        return unwinder_register(&sh64_unwinder);
+}
+early_initcall(sh64_unwinder_init);
diff --git a/arch/sh/kernel/dumpstack.c b/arch/sh/kernel/dumpstack.c
index 694158b9a50..7617dc4129a 100644
--- a/arch/sh/kernel/dumpstack.c
+++ b/arch/sh/kernel/dumpstack.c
@@ -2,13 +2,48 @@
  *  Copyright (C) 1991, 1992  Linus Torvalds
  *  Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs
  *  Copyright (C) 2009  Matt Fleming
+ *  Copyright (C) 2002 - 2012  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  */
 #include <linux/kallsyms.h>
 #include <linux/ftrace.h>
 #include <linux/debug_locks.h>
+#include <linux/kdebug.h>
+#include <linux/export.h>
+#include <linux/uaccess.h>
 #include <asm/unwinder.h>
 #include <asm/stacktrace.h>
 
+void dump_mem(const char *str, unsigned long bottom, unsigned long top)
+{
+        unsigned long p;
+        int i;
+
+        printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
+
+        for (p = bottom & ~31; p < top; ) {
+                printk("%04lx: ", p & 0xffff);
+
+                for (i = 0; i < 8; i++, p += 4) {
+                        unsigned int val;
+
+                        if (p < bottom || p >= top)
+                                printk("         ");
+                        else {
+                                if (__get_user(val, (unsigned int __user *)p)) {
+                                        printk("\n");
+                                        return;
+                                }
+                                printk("%08x ", val);
+                        }
+                }
+                printk("\n");
+        }
+}
+
 void printk_address(unsigned long address, int reliable)
 {
         printk(" [<%p>] %s%pS\n", (void *) address,
@@ -106,3 +141,26 @@ void show_trace(struct task_struct *tsk, unsigned long *sp,
 
         debug_show_held_locks(tsk);
 }
+
+void show_stack(struct task_struct *tsk, unsigned long *sp)
+{
+        unsigned long stack;
+
+        if (!tsk)
+                tsk = current;
+        if (tsk == current)
+                sp = (unsigned long *)current_stack_pointer;
+        else
+                sp = (unsigned long *)tsk->thread.sp;
+
+        stack = (unsigned long)sp;
+        dump_mem("Stack: ", stack, THREAD_SIZE +
+                 (unsigned long)task_stack_page(tsk));
+        show_trace(tsk, sp, NULL);
+}
+
+void dump_stack(void)
+{
+        show_stack(NULL, NULL);
+}
+EXPORT_SYMBOL(dump_stack);
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index dadce735f74..063af10ff3c 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -231,16 +231,6 @@ void __init init_IRQ(void)
         irq_ctx_init(smp_processor_id());
 }
 
-#ifdef CONFIG_SPARSE_IRQ
-int __init arch_probe_nr_irqs(void)
-{
-        /*
-         * No pre-allocated IRQs.
-         */
-        return 0;
-}
-#endif
-
 #ifdef CONFIG_HOTPLUG_CPU
 static void route_irq(struct irq_data *data, unsigned int irq, unsigned int cpu)
 {
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 7b57bf1dc85..ebe7a7d9721 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -273,7 +273,7 @@ void __init setup_arch(char **cmdline_p)
         data_resource.start = virt_to_phys(_etext);
         data_resource.end = virt_to_phys(_edata)-1;
         bss_resource.start = virt_to_phys(__bss_start);
-        bss_resource.end = virt_to_phys(_ebss)-1;
+        bss_resource.end = virt_to_phys(__bss_stop)-1;
 
 #ifdef CONFIG_CMDLINE_OVERWRITE
         strlcpy(command_line, CONFIG_CMDLINE, sizeof(command_line));
diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c
index 3896f26efa4..2a0a596ebf6 100644
--- a/arch/sh/kernel/sh_ksyms_32.c
+++ b/arch/sh/kernel/sh_ksyms_32.c
@@ -19,7 +19,6 @@ EXPORT_SYMBOL(csum_partial);
 EXPORT_SYMBOL(csum_partial_copy_generic);
 EXPORT_SYMBOL(copy_page);
 EXPORT_SYMBOL(__clear_user);
-EXPORT_SYMBOL(_ebss);
 EXPORT_SYMBOL(empty_zero_page);
 
 #define DECLARE_EXPORT(name)            \
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index a87e58a9e38..72246bc0688 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -6,9 +6,80 @@
 #include <linux/sched.h>
 #include <linux/uaccess.h>
 #include <linux/hardirq.h>
+#include <linux/kernel.h>
+#include <linux/kexec.h>
+#include <linux/module.h>
 #include <asm/unwinder.h>
 #include <asm/traps.h>
 
+static DEFINE_SPINLOCK(die_lock);
+
+void die(const char *str, struct pt_regs *regs, long err)
+{
+        static int die_counter;
+
+        oops_enter();
+
+        spin_lock_irq(&die_lock);
+        console_verbose();
+        bust_spinlocks(1);
+
+        printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
+        print_modules();
+        show_regs(regs);
+
+        printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
+                        task_pid_nr(current), task_stack_page(current) + 1);
+
+        if (!user_mode(regs) || in_interrupt())
+                dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
+                         (unsigned long)task_stack_page(current));
+
+        notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
+
+        bust_spinlocks(0);
+        add_taint(TAINT_DIE);
+        spin_unlock_irq(&die_lock);
+        oops_exit();
+
+        if (kexec_should_crash(current))
+                crash_kexec(regs);
+
+        if (in_interrupt())
+                panic("Fatal exception in interrupt");
+
+        if (panic_on_oops)
+                panic("Fatal exception");
+
+        do_exit(SIGSEGV);
+}
+
+void die_if_kernel(const char *str, struct pt_regs *regs, long err)
+{
+        if (!user_mode(regs))
+                die(str, regs, err);
+}
+
+/*
+ * try and fix up kernelspace address errors
+ * - userspace errors just cause EFAULT to be returned, resulting in SEGV
+ * - kernel/userspace interfaces cause a jump to an appropriate handler
+ * - other kernel errors are bad
+ */
+void die_if_no_fixup(const char *str, struct pt_regs *regs, long err)
+{
+        if (!user_mode(regs)) {
+                const struct exception_table_entry *fixup;
+                fixup = search_exception_tables(regs->pc);
+                if (fixup) {
+                        regs->pc = fixup->fixup;
+                        return;
+                }
+
+                die(str, regs, err);
+        }
+}
+
 #ifdef CONFIG_GENERIC_BUG
 static void handle_BUG(struct pt_regs *regs)
 {
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index a37175deb73..5f513a64ded 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -16,13 +16,11 @@
 #include <linux/hardirq.h>
 #include <linux/init.h>
 #include <linux/spinlock.h>
-#include <linux/module.h>
 #include <linux/kallsyms.h>
 #include <linux/io.h>
 #include <linux/bug.h>
 #include <linux/debug_locks.h>
 #include <linux/kdebug.h>
-#include <linux/kexec.h>
 #include <linux/limits.h>
 #include <linux/sysfs.h>
 #include <linux/uaccess.h>
@@ -48,102 +46,6 @@
 #define TRAP_ILLEGAL_SLOT_INST  13
 #endif
 
-static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
-{
-        unsigned long p;
-        int i;
-
-        printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
-
-        for (p = bottom & ~31; p < top; ) {
-                printk("%04lx: ", p & 0xffff);
-
-                for (i = 0; i < 8; i++, p += 4) {
-                        unsigned int val;
-
-                        if (p < bottom || p >= top)
-                                printk("         ");
-                        else {
-                                if (__get_user(val, (unsigned int __user *)p)) {
-                                        printk("\n");
-                                        return;
-                                }
-                                printk("%08x ", val);
-                        }
-                }
-                printk("\n");
-        }
-}
-
-static DEFINE_SPINLOCK(die_lock);
-
-void die(const char * str, struct pt_regs * regs, long err)
-{
-        static int die_counter;
-
-        oops_enter();
-
-        spin_lock_irq(&die_lock);
-        console_verbose();
-        bust_spinlocks(1);
-
-        printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
-        print_modules();
-        show_regs(regs);
-
-        printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
-                        task_pid_nr(current), task_stack_page(current) + 1);
-
-        if (!user_mode(regs) || in_interrupt())
-                dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
-                         (unsigned long)task_stack_page(current));
-
-        notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
-
-        bust_spinlocks(0);
-        add_taint(TAINT_DIE);
-        spin_unlock_irq(&die_lock);
-        oops_exit();
-
-        if (kexec_should_crash(current))
-                crash_kexec(regs);
-
-        if (in_interrupt())
-                panic("Fatal exception in interrupt");
-
-        if (panic_on_oops)
-                panic("Fatal exception");
-
-        do_exit(SIGSEGV);
-}
-
-static inline void die_if_kernel(const char *str, struct pt_regs *regs,
-                                 long err)
-{
-        if (!user_mode(regs))
-                die(str, regs, err);
-}
-
-/*
- * try and fix up kernelspace address errors
- * - userspace errors just cause EFAULT to be returned, resulting in SEGV
- * - kernel/userspace interfaces cause a jump to an appropriate handler
- * - other kernel errors are bad
- */
-static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
-{
-        if (!user_mode(regs)) {
-                const struct exception_table_entry *fixup;
-                fixup = search_exception_tables(regs->pc);
-                if (fixup) {
-                        regs->pc = fixup->fixup;
-                        return;
-                }
-
-                die(str, regs, err);
-        }
-}
-
 static inline void sign_extend(unsigned int count, unsigned char *dst)
 {
 #ifdef __LITTLE_ENDIAN__
@@ -900,26 +802,3 @@ void __init trap_init(void)
         set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
 #endif
 }
-
-void show_stack(struct task_struct *tsk, unsigned long *sp)
-{
-        unsigned long stack;
-
-        if (!tsk)
-                tsk = current;
-        if (tsk == current)
-                sp = (unsigned long *)current_stack_pointer;
-        else
-                sp = (unsigned long *)tsk->thread.sp;
-
-        stack = (unsigned long)sp;
-        dump_mem("Stack: ", stack, THREAD_SIZE +
-                 (unsigned long)task_stack_page(tsk));
-        show_trace(tsk, sp, NULL);
-}
-
-void dump_stack(void)
-{
-        show_stack(NULL, NULL);
-}
-EXPORT_SYMBOL(dump_stack);
diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c
index 8dae93ed8af..f87d20da179 100644
--- a/arch/sh/kernel/traps_64.c
+++ b/arch/sh/kernel/traps_64.c
@@ -27,283 +27,25 @@
 #include <linux/perf_event.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
-#include <linux/atomic.h>
+#include <asm/alignment.h>
 #include <asm/processor.h>
 #include <asm/pgtable.h>
 #include <asm/fpu.h>
 
-#undef DEBUG_EXCEPTION
-#ifdef DEBUG_EXCEPTION
-/* implemented in ../lib/dbg.c */
-extern void show_excp_regs(char *fname, int trapnr, int signr,
-                           struct pt_regs *regs);
-#else
-#define show_excp_regs(a, b, c, d)
-#endif
-
-static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
-                unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
-
-#define DO_ERROR(trapnr, signr, str, name, tsk) \
-asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
-{ \
-        do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
-}
-
-static DEFINE_SPINLOCK(die_lock);
-
-void die(const char * str, struct pt_regs * regs, long err)
-{
-        console_verbose();
-        spin_lock_irq(&die_lock);
-        printk("%s: %lx\n", str, (err & 0xffffff));
-        show_regs(regs);
-        spin_unlock_irq(&die_lock);
-        do_exit(SIGSEGV);
-}
-
-static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
-{
-        if (!user_mode(regs))
-                die(str, regs, err);
-}
-
-static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
-{
-        if (!user_mode(regs)) {
-                const struct exception_table_entry *fixup;
-                fixup = search_exception_tables(regs->pc);
-                if (fixup) {
-                        regs->pc = fixup->fixup;
-                        return;
-                }
-                die(str, regs, err);
-        }
-}
-
-DO_ERROR(13, SIGILL,  "illegal slot instruction", illegal_slot_inst, current)
-DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
-
-
-/* Implement misaligned load/store handling for kernel (and optionally for user
-   mode too).  Limitation : only SHmedia mode code is handled - there is no
-   handling at all for misaligned accesses occurring in SHcompact code yet. */
-
-static int misaligned_fixup(struct pt_regs *regs);
-
-asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
-{
-        if (misaligned_fixup(regs) < 0) {
-                do_unhandled_exception(7, SIGSEGV, "address error(load)",
-                                "do_address_error_load",
-                                error_code, regs, current);
-        }
-        return;
-}
-
-asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
-{
-        if (misaligned_fixup(regs) < 0) {
-                do_unhandled_exception(8, SIGSEGV, "address error(store)",
-                                "do_address_error_store",
-                                error_code, regs, current);
-        }
-        return;
-}
-
-#if defined(CONFIG_SH64_ID2815_WORKAROUND)
-
-#define OPCODE_INVALID      0
-#define OPCODE_USER_VALID   1
-#define OPCODE_PRIV_VALID   2
-
-/* getcon/putcon - requires checking which control register is referenced. */
-#define OPCODE_CTRL_REG     3
-
-/* Table of valid opcodes for SHmedia mode.
-   Form a 10-bit value by concatenating the major/minor opcodes i.e.
-   opcode[31:26,20:16].  The 6 MSBs of this value index into the following
-   array.  The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
-   LSBs==4'b0000 etc). */
-static unsigned long shmedia_opcode_table[64] = {
-        0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
-        0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
-        0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
-        0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
-        0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
-        0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
-        0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
-        0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
-};
-
-void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
-{
-        /* Workaround SH5-101 cut2 silicon defect #2815 :
-           in some situations, inter-mode branches from SHcompact -> SHmedia
-           which should take ITLBMISS or EXECPROT exceptions at the target
-           falsely take RESINST at the target instead. */
-
-        unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
-        unsigned long pc, aligned_pc;
-        int get_user_error;
-        int trapnr = 12;
-        int signr = SIGILL;
-        char *exception_name = "reserved_instruction";
-
-        pc = regs->pc;
-        if ((pc & 3) == 1) {
-                /* SHmedia : check for defect.  This requires executable vmas
-                   to be readable too. */
-                aligned_pc = pc & ~3;
-                if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
-                        get_user_error = -EFAULT;
-                } else {
-                        get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
-                }
-                if (get_user_error >= 0) {
-                        unsigned long index, shift;
-                        unsigned long major, minor, combined;
-                        unsigned long reserved_field;
-                        reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
-                        major = (opcode >> 26) & 0x3f;
-                        minor = (opcode >> 16) & 0xf;
-                        combined = (major << 4) | minor;
-                        index = major;
-                        shift = minor << 1;
-                        if (reserved_field == 0) {
-                                int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
-                                switch (opcode_state) {
-                                        case OPCODE_INVALID:
-                                                /* Trap. */
-                                                break;
-                                        case OPCODE_USER_VALID:
-                                                /* Restart the instruction : the branch to the instruction will now be from an RTE
-                                                   not from SHcompact so the silicon defect won't be triggered. */
-                                                return;
-                                        case OPCODE_PRIV_VALID:
-                                                if (!user_mode(regs)) {
-                                                        /* Should only ever get here if a module has
-                                                           SHcompact code inside it.  If so, the same fix up is needed. */
-                                                        return; /* same reason */
-                                                }
-                                                /* Otherwise, user mode trying to execute a privileged instruction -
-                                                   fall through to trap. */
-                                                break;
-                                        case OPCODE_CTRL_REG:
-                                                /* If in privileged mode, return as above. */
-                                                if (!user_mode(regs)) return;
-                                                /* In user mode ... */
-                                                if (combined == 0x9f) { /* GETCON */
-                                                        unsigned long regno = (opcode >> 20) & 0x3f;
-                                                        if (regno >= 62) {
-                                                                return;
-                                                        }
-                                                        /* Otherwise, reserved or privileged control register, => trap */
-                                                } else if (combined == 0x1bf) { /* PUTCON */
-                                                        unsigned long regno = (opcode >> 4) & 0x3f;
-                                                        if (regno >= 62) {
-                                                                return;
-                                                        }
-                                                        /* Otherwise, reserved or privileged control register, => trap */
-                                                } else {
-                                                        /* Trap */
-                                                }
-                                                break;
-                                        default:
-                                                /* Fall through to trap. */
-                                                break;
-                                }
-                        }
-                        /* fall through to normal resinst processing */
-                } else {
-                        /* Error trying to read opcode.  This typically means a
-                           real fault, not a RESINST any more.  So change the
-                           codes. */
-                        trapnr = 87;
-                        exception_name = "address error (exec)";
-                        signr = SIGSEGV;
-                }
-        }
-
-        do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
-}
-
-#else /* CONFIG_SH64_ID2815_WORKAROUND */
-
-/* If the workaround isn't needed, this is just a straightforward reserved
-   instruction */
-DO_ERROR(12, SIGILL,  "reserved instruction", reserved_inst, current)
-
-#endif /* CONFIG_SH64_ID2815_WORKAROUND */
-
-/* Called with interrupts disabled */
-asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
-{
-        show_excp_regs(__func__, -1, -1, regs);
-        die_if_kernel("exception", regs, ex);
-}
-
-int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
-{
-        /* Syscall debug */
-        printk("System call ID error: [0x1#args:8 #syscall:16  0x%lx]\n", scId);
-
-        die_if_kernel("unknown trapa", regs, scId);
-
-        return -ENOSYS;
-}
-
-void show_stack(struct task_struct *tsk, unsigned long *sp)
-{
-#ifdef CONFIG_KALLSYMS
-        extern void sh64_unwind(struct pt_regs *regs);
-        struct pt_regs *regs;
-
-        regs = tsk ? tsk->thread.kregs : NULL;
-
-        sh64_unwind(regs);
-#else
-        printk(KERN_ERR "Can't backtrace on sh64 without CONFIG_KALLSYMS\n");
-#endif
-}
-
-void show_task(unsigned long *sp)
-{
-        show_stack(NULL, sp);
-}
-
-void dump_stack(void)
-{
-        show_task(NULL);
-}
-/* Needed by any user of WARN_ON in view of the defn in include/asm-sh/bug.h */
-EXPORT_SYMBOL(dump_stack);
-
-static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
-                unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
-{
-        show_excp_regs(fn_name, trapnr, signr, regs);
-
-        if (user_mode(regs))
-                force_sig(signr, tsk);
-
-        die_if_no_fixup(str, regs, error_code);
-}
-
-static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int from_user_mode)
+static int read_opcode(reg_size_t pc, insn_size_t *result_opcode, int from_user_mode)
 {
         int get_user_error;
         unsigned long aligned_pc;
-        unsigned long opcode;
+        insn_size_t opcode;
 
         if ((pc & 3) == 1) {
                 /* SHmedia */
                 aligned_pc = pc & ~3;
                 if (from_user_mode) {
-                        if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
+                        if (!access_ok(VERIFY_READ, aligned_pc, sizeof(insn_size_t))) {
                                 get_user_error = -EFAULT;
                         } else {
-                                get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
+                                get_user_error = __get_user(opcode, (insn_size_t *)aligned_pc);
                                 *result_opcode = opcode;
                         }
                         return get_user_error;
@@ -311,7 +53,7 @@ static int read_opcode(unsigned long long pc, unsigned long *result_opcode, int
                         /* If the fault was in the kernel, we can either read
                          * this directly, or if not, we fault.
                         */
-                        *result_opcode = *(unsigned long *) aligned_pc;
+                        *result_opcode = *(insn_size_t *)aligned_pc;
                         return 0;
                 }
         } else if ((pc & 1) == 0) {
@@ -337,17 +79,23 @@ static int address_is_sign_extended(__u64 a)
 #endif
 }
 
+/* return -1 for fault, 0 for OK */
 static int generate_and_check_address(struct pt_regs *regs,
-                                      __u32 opcode,
+                                      insn_size_t opcode,
                                       int displacement_not_indexed,
                                       int width_shift,
                                       __u64 *address)
 {
-        /* return -1 for fault, 0 for OK */
-
         __u64 base_address, addr;
         int basereg;
 
+        switch (1 << width_shift) {
+        case 1: inc_unaligned_byte_access(); break;
+        case 2: inc_unaligned_word_access(); break;
+        case 4: inc_unaligned_dword_access(); break;
+        case 8: inc_unaligned_multi_access(); break;
+        }
+
         basereg = (opcode >> 20) & 0x3f;
         base_address = regs->regs[basereg];
         if (displacement_not_indexed) {
@@ -364,28 +112,28 @@ static int generate_and_check_address(struct pt_regs *regs,
         }
 
         /* Check sign extended */
-        if (!address_is_sign_extended(addr)) {
+        if (!address_is_sign_extended(addr))
                 return -1;
-        }
 
         /* Check accessible.  For misaligned access in the kernel, assume the
            address is always accessible (and if not, just fault when the
            load/store gets done.) */
         if (user_mode(regs)) {
-                if (addr >= TASK_SIZE) {
+                inc_unaligned_user_access();
+
+                if (addr >= TASK_SIZE)
                         return -1;
-                }
-                /* Do access_ok check later - it depends on whether it's a load or a store. */
-        }
+        } else
+                inc_unaligned_kernel_access();
 
         *address = addr;
+
+        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, addr);
+        unaligned_fixups_notify(current, opcode, regs);
+
         return 0;
 }
 
-static int user_mode_unaligned_fixup_count = 10;
-static int user_mode_unaligned_fixup_enable = 1;
-static int kernel_mode_unaligned_fixup_count = 32;
-
 static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
 {
         unsigned short x;
@@ -415,7 +163,7 @@ static void misaligned_kernel_word_store(__u64 address, __u64 value)
 }
 
 static int misaligned_load(struct pt_regs *regs,
-                           __u32 opcode,
+                           insn_size_t opcode,
                            int displacement_not_indexed,
                            int width_shift,
                            int do_sign_extend)
@@ -427,11 +175,8 @@ static int misaligned_load(struct pt_regs *regs,
 
         error = generate_and_check_address(regs, opcode,
                         displacement_not_indexed, width_shift, &address);
-        if (error < 0) {
+        if (error < 0)
                 return error;
-        }
-
-        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, address);
 
         destreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
@@ -490,11 +235,10 @@ static int misaligned_load(struct pt_regs *regs,
         }
 
         return 0;
-
 }
 
 static int misaligned_store(struct pt_regs *regs,
-                            __u32 opcode,
+                            insn_size_t opcode,
                             int displacement_not_indexed,
                             int width_shift)
 {
@@ -505,11 +249,8 @@ static int misaligned_store(struct pt_regs *regs,
 
         error = generate_and_check_address(regs, opcode,
                         displacement_not_indexed, width_shift, &address);
-        if (error < 0) {
+        if (error < 0)
                 return error;
-        }
-
-        perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, address);
 
         srcreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
@@ -563,13 +304,12 @@ static int misaligned_store(struct pt_regs *regs,
         }
 
         return 0;
-
 }
 
 /* Never need to fix up misaligned FPU accesses within the kernel since that's a real
    error. */
 static int misaligned_fpu_load(struct pt_regs *regs,
-                           __u32 opcode,
+                           insn_size_t opcode,
                            int displacement_not_indexed,
                            int width_shift,
                            int do_paired_load)
@@ -581,11 +321,8 @@ static int misaligned_fpu_load(struct pt_regs *regs,
 
         error = generate_and_check_address(regs, opcode,
                         displacement_not_indexed, width_shift, &address);
-        if (error < 0) {
+        if (error < 0)
                 return error;
-        }
-
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, address);
 
         destreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
@@ -641,12 +378,10 @@ static int misaligned_fpu_load(struct pt_regs *regs,
                 die ("Misaligned FPU load inside kernel", regs, 0);
                 return -1;
         }
-
-
 }
 
 static int misaligned_fpu_store(struct pt_regs *regs,
-                           __u32 opcode,
+                           insn_size_t opcode,
                            int displacement_not_indexed,
                            int width_shift,
                            int do_paired_load)
@@ -658,11 +393,8 @@ static int misaligned_fpu_store(struct pt_regs *regs,
 
         error = generate_and_check_address(regs, opcode,
                         displacement_not_indexed, width_shift, &address);
-        if (error < 0) {
+        if (error < 0)
                 return error;
-        }
-
-        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, address);
 
         srcreg = (opcode >> 4) & 0x3f;
         if (user_mode(regs)) {
@@ -723,11 +455,13 @@ static int misaligned_fpu_store(struct pt_regs *regs,
 
 static int misaligned_fixup(struct pt_regs *regs)
 {
-        unsigned long opcode;
+        insn_size_t opcode;
         int error;
         int major, minor;
+        unsigned int user_action;
 
-        if (!user_mode_unaligned_fixup_enable)
+        user_action = unaligned_user_action();
+        if (!(user_action & UM_FIXUP))
                 return -1;
 
         error = read_opcode(regs->pc, &opcode, user_mode(regs));
@@ -737,23 +471,6 @@ static int misaligned_fixup(struct pt_regs *regs)
         major = (opcode >> 26) & 0x3f;
         minor = (opcode >> 16) & 0xf;
 
-        if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
-                --user_mode_unaligned_fixup_count;
-                /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
-                printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
-                       current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
-        } else if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
-                --kernel_mode_unaligned_fixup_count;
-                if (in_interrupt()) {
-                        printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
-                               (__u32)regs->pc, opcode);
-                } else {
-                        printk("Fixing up unaligned kernelspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
-                               current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
-                }
-        }
-
-
         switch (major) {
                 case (0x84>>2): /* LD.W */
                         error = misaligned_load(regs, opcode, 1, 1, 1);
@@ -878,59 +595,202 @@ static int misaligned_fixup(struct pt_regs *regs)
                 regs->pc += 4; /* Skip the instruction that's just been emulated */
                 return 0;
         }
+}
+
+static void do_unhandled_exception(int signr, char *str, unsigned long error,
+                                   struct pt_regs *regs)
+{
+        if (user_mode(regs))
+                force_sig(signr, current);
 
+        die_if_no_fixup(str, regs, error);
 }
 
-static ctl_table unaligned_table[] = {
-        {
-                .procname       = "kernel_reports",
-                .data           = &kernel_mode_unaligned_fixup_count,
-                .maxlen         = sizeof(int),
-                .mode           = 0644,
-                .proc_handler   = proc_dointvec
-        },
-        {
-                .procname       = "user_reports",
-                .data           = &user_mode_unaligned_fixup_count,
-                .maxlen         = sizeof(int),
-                .mode           = 0644,
-                .proc_handler   = proc_dointvec
-        },
-        {
-                .procname       = "user_enable",
-                .data           = &user_mode_unaligned_fixup_enable,
-                .maxlen         = sizeof(int),
-                .mode           = 0644,
-                .proc_handler   = proc_dointvec},
-        {}
-};
+#define DO_ERROR(signr, str, name) \
+asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
+{ \
+        do_unhandled_exception(signr, str, error_code, regs); \
+}
 
-static ctl_table unaligned_root[] = {
-        {
-                .procname       = "unaligned_fixup",
-                .mode           = 0555,
-                .child          = unaligned_table
-        },
-        {}
-};
+DO_ERROR(SIGILL,  "illegal slot instruction", illegal_slot_inst)
+DO_ERROR(SIGSEGV, "address error (exec)", address_error_exec)
+
+#if defined(CONFIG_SH64_ID2815_WORKAROUND)
+
+#define OPCODE_INVALID      0
+#define OPCODE_USER_VALID   1
+#define OPCODE_PRIV_VALID   2
 
-static ctl_table sh64_root[] = {
-        {
-                .procname       = "sh64",
-                .mode           = 0555,
-                .child          = unaligned_root
-        },
-        {}
+/* getcon/putcon - requires checking which control register is referenced. */
+#define OPCODE_CTRL_REG     3
+
+/* Table of valid opcodes for SHmedia mode.
+   Form a 10-bit value by concatenating the major/minor opcodes i.e.
+   opcode[31:26,20:16].  The 6 MSBs of this value index into the following
+   array.  The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
+   LSBs==4'b0000 etc). */
+static unsigned long shmedia_opcode_table[64] = {
+        0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
+        0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
+        0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
+        0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
+        0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
+        0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
+        0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
+        0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
 };
-static struct ctl_table_header *sysctl_header;
-static int __init init_sysctl(void)
+
+/* Workaround SH5-101 cut2 silicon defect #2815 :
+   in some situations, inter-mode branches from SHcompact -> SHmedia
+   which should take ITLBMISS or EXECPROT exceptions at the target
+   falsely take RESINST at the target instead. */
+void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
 {
-        sysctl_header = register_sysctl_table(sh64_root);
-        return 0;
+        insn_size_t opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
+        unsigned long pc, aligned_pc;
+        unsigned long index, shift;
+        unsigned long major, minor, combined;
+        unsigned long reserved_field;
+        int opcode_state;
+        int get_user_error;
+        int signr = SIGILL;
+        char *exception_name = "reserved_instruction";
+
+        pc = regs->pc;
+
+        /* SHcompact is not handled */
+        if (unlikely((pc & 3) == 0))
+                goto out;
+
+        /* SHmedia : check for defect.  This requires executable vmas
+           to be readable too. */
+        aligned_pc = pc & ~3;
+        if (!access_ok(VERIFY_READ, aligned_pc, sizeof(insn_size_t)))
+                get_user_error = -EFAULT;
+        else
+                get_user_error = __get_user(opcode, (insn_size_t *)aligned_pc);
+
+        if (get_user_error < 0) {
+                /*
+                 * Error trying to read opcode.  This typically means a
+                 * real fault, not a RESINST any more.  So change the
+                 * codes.
+                 */
+                exception_name = "address error (exec)";
+                signr = SIGSEGV;
+                goto out;
+        }
+
+        /* These bits are currently reserved as zero in all valid opcodes */
+        reserved_field = opcode & 0xf;
+        if (unlikely(reserved_field))
+                goto out;       /* invalid opcode */
+
+        major = (opcode >> 26) & 0x3f;
+        minor = (opcode >> 16) & 0xf;
+        combined = (major << 4) | minor;
+        index = major;
+        shift = minor << 1;
+        opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
+        switch (opcode_state) {
+        case OPCODE_INVALID:
+                /* Trap. */
+                break;
+        case OPCODE_USER_VALID:
+                /*
+                 * Restart the instruction: the branch to the instruction
+                 * will now be from an RTE not from SHcompact so the
+                 * silicon defect won't be triggered.
+                 */
+                return;
+        case OPCODE_PRIV_VALID:
+                if (!user_mode(regs)) {
+                        /*
+                         * Should only ever get here if a module has
+                         * SHcompact code inside it. If so, the same fix
+                         * up is needed.
+                         */
+                        return; /* same reason */
+                }
+
+                /*
+                 * Otherwise, user mode trying to execute a privileged
+                 * instruction - fall through to trap.
+                 */
+                break;
+        case OPCODE_CTRL_REG:
+                /* If in privileged mode, return as above. */
+                if (!user_mode(regs))
+                        return;
+
+                /* In user mode ... */
+                if (combined == 0x9f) { /* GETCON */
+                        unsigned long regno = (opcode >> 20) & 0x3f;
+
+                        if (regno >= 62)
+                                return;
+
+                        /* reserved/privileged control register => trap */
+                } else if (combined == 0x1bf) { /* PUTCON */
+                        unsigned long regno = (opcode >> 4) & 0x3f;
+
+                        if (regno >= 62)
+                                return;
+
+                        /* reserved/privileged control register => trap */
+                }
+
+                break;
+        default:
+                /* Fall through to trap. */
+                break;
+        }
+
+out:
+        do_unhandled_exception(signr, exception_name, error_code, regs);
 }
 
-__initcall(init_sysctl);
+#else /* CONFIG_SH64_ID2815_WORKAROUND */
 
+/* If the workaround isn't needed, this is just a straightforward reserved
+   instruction */
+DO_ERROR(SIGILL, "reserved instruction", reserved_inst)
+
+#endif /* CONFIG_SH64_ID2815_WORKAROUND */
+
+/* Called with interrupts disabled */
+asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
+{
+        die_if_kernel("exception", regs, ex);
+}
+
+asmlinkage int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
+{
+        /* Syscall debug */
+        printk("System call ID error: [0x1#args:8 #syscall:16  0x%lx]\n", scId);
+
+        die_if_kernel("unknown trapa", regs, scId);
+
+        return -ENOSYS;
+}
+
+/* Implement misaligned load/store handling for kernel (and optionally for user
+   mode too).  Limitation : only SHmedia mode code is handled - there is no
+   handling at all for misaligned accesses occurring in SHcompact code yet. */
+
+asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
+{
+        if (misaligned_fixup(regs) < 0)
+                do_unhandled_exception(SIGSEGV, "address error(load)",
+                                       error_code, regs);
+}
+
+asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
+{
+        if (misaligned_fixup(regs) < 0)
+                do_unhandled_exception(SIGSEGV, "address error(store)",
+                                error_code, regs);
+}
 
 asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
 {
@@ -942,10 +802,9 @@ asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
            of access we make to them - just go direct to their physical
            addresses. */
         exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
-        if (exp_cause & ~4) {
+        if (exp_cause & ~4)
                 printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
                         (unsigned long)(exp_cause & 0xffffffff));
-        }
         show_state();
         /* Clear all DEBUGINT causes */
         poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index c98905f71e2..db88cbf9eaf 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -78,7 +78,6 @@ SECTIONS
         . = ALIGN(PAGE_SIZE);
         __init_end = .;
         BSS_SECTION(0, PAGE_SIZE, 4)
-        _ebss = .;                      /* uClinux MTD sucks */
         _end = . ;
 
         STABS_DEBUG
diff --git a/arch/sh/lib/mcount.S b/arch/sh/lib/mcount.S
index 84a57761f17..60164e65d66 100644
--- a/arch/sh/lib/mcount.S
+++ b/arch/sh/lib/mcount.S
@@ -39,7 +39,7 @@
  *
  * Make sure the stack pointer contains a valid address. Valid
  * addresses for kernel stacks are anywhere after the bss
- * (after _ebss) and anywhere in init_thread_union (init_stack).
+ * (after __bss_stop) and anywhere in init_thread_union (init_stack).
  */
 #define STACK_CHECK()                                   \
         mov     #(THREAD_SIZE >> 10), r0;               \
@@ -60,7 +60,7 @@
         cmp/hi  r2, r1;                                 \
         bf      stack_panic;                            \
                                                         \
-        /* If sp > _ebss then we're OK. */              \
+        /* If sp > __bss_stop then we're OK. */         \
         mov.l   .L_ebss, r1;                            \
         cmp/hi  r1, r15;                                \
         bt      1f;                                     \
@@ -70,7 +70,7 @@
         cmp/hs  r1, r15;                                \
         bf      stack_panic;                            \
                                                         \
-        /* If sp > init_stack && sp < _ebss, not OK. */ \
+        /* If sp > init_stack && sp < __bss_stop, not OK. */    \
         add     r0, r1;                                 \
         cmp/hs  r1, r15;                                \
         bt      stack_panic;                            \
@@ -292,8 +292,6 @@ stack_panic:
          nop
 
         .align 2
-.L_ebss:
-        .long   _ebss
 .L_init_thread_union:
         .long   init_thread_union
 .Lpanic:
diff --git a/arch/sh/lib64/Makefile b/arch/sh/lib64/Makefile
index 1fee75aa1f9..69779ff741d 100644
--- a/arch/sh/lib64/Makefile
+++ b/arch/sh/lib64/Makefile
@@ -10,7 +10,7 @@
 #
 
 # Panic should really be compiled as PIC
-lib-y  := udelay.o dbg.o panic.o memcpy.o memset.o \
+lib-y  := udelay.o panic.o memcpy.o memset.o \
           copy_user_memcpy.o copy_page.o strcpy.o strlen.o
 
 # Extracted from libgcc
diff --git a/arch/sh/lib64/dbg.c b/arch/sh/lib64/dbg.c
deleted file mode 100644
index 6152a6a6d9c..00000000000
--- a/arch/sh/lib64/dbg.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*--------------------------------------------------------------------------
---
--- Identity : Linux50 Debug Funcions
---
--- File     : arch/sh/lib64/dbg.c
---
--- Copyright 2000, 2001 STMicroelectronics Limited.
--- Copyright 2004 Richard Curnow (evt_debug etc)
---
---------------------------------------------------------------------------*/
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <asm/mmu_context.h>
-
-typedef u64 regType_t;
-
-static regType_t getConfigReg(u64 id)
-{
-        register u64 reg __asm__("r2");
-        asm volatile ("getcfg   %1, 0, %0":"=r" (reg):"r"(id));
-        return (reg);
-}
-
-/* ======================================================================= */
-
-static char *szTab[] = { "4k", "64k", "1M", "512M" };
-static char *protTab[] = { "----",
-        "---R",
-        "--X-",
-        "--XR",
-        "-W--",
-        "-W-R",
-        "-WX-",
-        "-WXR",
-        "U---",
-        "U--R",
-        "U-X-",
-        "U-XR",
-        "UW--",
-        "UW-R",
-        "UWX-",
-        "UWXR"
-};
-#define  ITLB_BASE      0x00000000
-#define  DTLB_BASE      0x00800000
-#define  MAX_TLBs               64
-/* PTE High */
-#define  GET_VALID(pte)        ((pte) & 0x1)
-#define  GET_SHARED(pte)       ((pte) & 0x2)
-#define  GET_ASID(pte)         ((pte >> 2) & 0x0ff)
-#define  GET_EPN(pte)          ((pte) & 0xfffff000)
-
-/* PTE Low */
-#define  GET_CBEHAVIOR(pte)    ((pte) & 0x3)
-#define  GET_PAGE_SIZE(pte)    szTab[((pte >> 3) & 0x3)]
-#define  GET_PROTECTION(pte)   protTab[((pte >> 6) & 0xf)]
-#define  GET_PPN(pte)          ((pte) & 0xfffff000)
-
-#define PAGE_1K_MASK           0x00000000
-#define PAGE_4K_MASK           0x00000010
-#define PAGE_64K_MASK          0x00000080
-#define MMU_PAGESIZE_MASK      (PAGE_64K_MASK | PAGE_4K_MASK)
-#define PAGE_1MB_MASK          MMU_PAGESIZE_MASK
-#define PAGE_1K                (1024)
-#define PAGE_4K                (1024 * 4)
-#define PAGE_64K               (1024 * 64)
-#define PAGE_1MB               (1024 * 1024)
-
-#define HOW_TO_READ_TLB_CONTENT  \
-       "[ ID]  PPN         EPN        ASID  Share  CB  P.Size   PROT.\n"
-
-void print_single_tlb(unsigned long tlb, int single_print)
-{
-        regType_t pteH;
-        regType_t pteL;
-        unsigned int valid, shared, asid, epn, cb, ppn;
-        char *pSize;
-        char *pProt;
-
-        /*
-           ** in case of single print <single_print> is true, this implies:
-           **   1) print the TLB in any case also if NOT VALID
-           **   2) print out the header
-         */
-
-        pteH = getConfigReg(tlb);
-        valid = GET_VALID(pteH);
-        if (single_print)
-                printk(HOW_TO_READ_TLB_CONTENT);
-        else if (!valid)
-                return;
-
-        pteL = getConfigReg(tlb + 1);
-
-        shared = GET_SHARED(pteH);
-        asid = GET_ASID(pteH);
-        epn = GET_EPN(pteH);
-        cb = GET_CBEHAVIOR(pteL);
-        pSize = GET_PAGE_SIZE(pteL);
-        pProt = GET_PROTECTION(pteL);
-        ppn = GET_PPN(pteL);
-        printk("[%c%2ld]  0x%08x  0x%08x  %03d   %02x    %02x   %4s    %s\n",
-               ((valid) ? ' ' : 'u'), ((tlb & 0x0ffff) / TLB_STEP),
-               ppn, epn, asid, shared, cb, pSize, pProt);
-}
-
-void print_dtlb(void)
-{
-        int count;
-        unsigned long tlb;
-
-        printk(" ================= SH-5 D-TLBs Status ===================\n");
-        printk(HOW_TO_READ_TLB_CONTENT);
-        tlb = DTLB_BASE;
-        for (count = 0; count < MAX_TLBs; count++, tlb += TLB_STEP)
-                print_single_tlb(tlb, 0);
-        printk
-            (" =============================================================\n");
-}
-
-void print_itlb(void)
-{
-        int count;
-        unsigned long tlb;
-
-        printk(" ================= SH-5 I-TLBs Status ===================\n");
-        printk(HOW_TO_READ_TLB_CONTENT);
-        tlb = ITLB_BASE;
-        for (count = 0; count < MAX_TLBs; count++, tlb += TLB_STEP)
-                print_single_tlb(tlb, 0);
-        printk
-            (" =============================================================\n");
-}
-
-void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs)
-{
-
-        unsigned long long ah, al, bh, bl, ch, cl;
-
-        printk("\n");
-        printk("EXCEPTION - %s: task %d; Linux trap # %d; signal = %d\n",
-               ((from) ? from : "???"), current->pid, trapnr, signr);
-
-        asm volatile ("getcon   " __EXPEVT ", %0":"=r"(ah));
-        asm volatile ("getcon   " __EXPEVT ", %0":"=r"(al));
-        ah = (ah) >> 32;
-        al = (al) & 0xffffffff;
-        asm volatile ("getcon   " __KCR1 ", %0":"=r"(bh));
-        asm volatile ("getcon   " __KCR1 ", %0":"=r"(bl));
-        bh = (bh) >> 32;
-        bl = (bl) & 0xffffffff;
-        asm volatile ("getcon   " __INTEVT ", %0":"=r"(ch));
-        asm volatile ("getcon   " __INTEVT ", %0":"=r"(cl));
-        ch = (ch) >> 32;
-        cl = (cl) & 0xffffffff;
-        printk("EXPE: %08Lx%08Lx KCR1: %08Lx%08Lx INTE: %08Lx%08Lx\n",
-               ah, al, bh, bl, ch, cl);
-
-        asm volatile ("getcon   " __PEXPEVT ", %0":"=r"(ah));
-        asm volatile ("getcon   " __PEXPEVT ", %0":"=r"(al));
-        ah = (ah) >> 32;
-        al = (al) & 0xffffffff;
-        asm volatile ("getcon   " __PSPC ", %0":"=r"(bh));
-        asm volatile ("getcon   " __PSPC ", %0":"=r"(bl));
-        bh = (bh) >> 32;
-        bl = (bl) & 0xffffffff;
-        asm volatile ("getcon   " __PSSR ", %0":"=r"(ch));
-        asm volatile ("getcon   " __PSSR ", %0":"=r"(cl));
-        ch = (ch) >> 32;
-        cl = (cl) & 0xffffffff;
-        printk("PEXP: %08Lx%08Lx PSPC: %08Lx%08Lx PSSR: %08Lx%08Lx\n",
-               ah, al, bh, bl, ch, cl);
-
-        ah = (regs->pc) >> 32;
-        al = (regs->pc) & 0xffffffff;
-        bh = (regs->regs[18]) >> 32;
-        bl = (regs->regs[18]) & 0xffffffff;
-        ch = (regs->regs[15]) >> 32;
-        cl = (regs->regs[15]) & 0xffffffff;
-        printk("PC  : %08Lx%08Lx LINK: %08Lx%08Lx SP  : %08Lx%08Lx\n",
-               ah, al, bh, bl, ch, cl);
-
-        ah = (regs->sr) >> 32;
-        al = (regs->sr) & 0xffffffff;
-        asm volatile ("getcon   " __TEA ", %0":"=r"(bh));
-        asm volatile ("getcon   " __TEA ", %0":"=r"(bl));
-        bh = (bh) >> 32;
-        bl = (bl) & 0xffffffff;
-        asm volatile ("getcon   " __KCR0 ", %0":"=r"(ch));
-        asm volatile ("getcon   " __KCR0 ", %0":"=r"(cl));
-        ch = (ch) >> 32;
-        cl = (cl) & 0xffffffff;
-        printk("SR  : %08Lx%08Lx TEA : %08Lx%08Lx KCR0: %08Lx%08Lx\n",
-               ah, al, bh, bl, ch, cl);
-
-        ah = (regs->regs[0]) >> 32;
-        al = (regs->regs[0]) & 0xffffffff;
-        bh = (regs->regs[1]) >> 32;
-        bl = (regs->regs[1]) & 0xffffffff;
-        ch = (regs->regs[2]) >> 32;
-        cl = (regs->regs[2]) & 0xffffffff;
-        printk("R0  : %08Lx%08Lx R1  : %08Lx%08Lx R2  : %08Lx%08Lx\n",
-               ah, al, bh, bl, ch, cl);
-
-        ah = (regs->regs[3]) >> 32;
-        al = (regs->regs[3]) & 0xffffffff;
-        bh = (regs->regs[4]) >> 32;
-        bl = (regs->regs[4]) & 0xffffffff;
-        ch = (regs->regs[5]) >> 32;
-        cl = (regs->regs[5]) & 0xffffffff;
-        printk("R3  : %08Lx%08Lx R4  : %08Lx%08Lx R5  : %08Lx%08Lx\n",
-               ah, al, bh, bl, ch, cl);
-
-        ah = (regs->regs[6]) >> 32;
-        al = (regs->regs[6]) & 0xffffffff;
-        bh = (regs->regs[7]) >> 32;
-        bl = (regs->regs[7]) & 0xffffffff;
-        ch = (regs->regs[8]) >> 32;
-        cl = (regs->regs[8]) & 0xffffffff;
-        printk("R6  : %08Lx%08Lx R7  : %08Lx%08Lx R8  : %08Lx%08Lx\n",
-               ah, al, bh, bl, ch, cl);
-
-        ah = (regs->regs[9]) >> 32;
-        al = (regs->regs[9]) & 0xffffffff;
-        bh = (regs->regs[10]) >> 32;
-        bl = (regs->regs[10]) & 0xffffffff;
-        ch = (regs->regs[11]) >> 32;
-        cl = (regs->regs[11]) & 0xffffffff;
-        printk("R9  : %08Lx%08Lx R10 : %08Lx%08Lx R11 : %08Lx%08Lx\n",
-               ah, al, bh, bl, ch, cl);
-        printk("....\n");
-
-        ah = (regs->tregs[0]) >> 32;
-        al = (regs->tregs[0]) & 0xffffffff;
-        bh = (regs->tregs[1]) >> 32;
-        bl = (regs->tregs[1]) & 0xffffffff;
-        ch = (regs->tregs[2]) >> 32;
-        cl = (regs->tregs[2]) & 0xffffffff;
-        printk("T0  : %08Lx%08Lx T1  : %08Lx%08Lx T2  : %08Lx%08Lx\n",
-               ah, al, bh, bl, ch, cl);
-        printk("....\n");
-
-        print_dtlb();
-        print_itlb();
-}
diff --git a/arch/sh/mm/fault.c b/arch/sh/mm/fault.c
index 1fc25d85e51..3bdc1ad9a34 100644
--- a/arch/sh/mm/fault.c
+++ b/arch/sh/mm/fault.c
@@ -58,11 +58,15 @@ static void show_pte(struct mm_struct *mm, unsigned long addr)
 {
         pgd_t *pgd;
 
-        if (mm)
+        if (mm) {
                 pgd = mm->pgd;
-        else
+        } else {
                 pgd = get_TTB();
 
+                if (unlikely(!pgd))
+                        pgd = swapper_pg_dir;
+        }
+
         printk(KERN_ALERT "pgd = %p\n", pgd);
         pgd += pgd_index(addr);
         printk(KERN_ALERT "[%08lx] *pgd=%0*Lx", addr,
diff --git a/arch/sh/mm/tlb-sh5.c b/arch/sh/mm/tlb-sh5.c
index 3aea25dc431..ff1c40a31cb 100644
--- a/arch/sh/mm/tlb-sh5.c
+++ b/arch/sh/mm/tlb-sh5.c
@@ -17,7 +17,7 @@
 /**
  * sh64_tlb_init - Perform initial setup for the DTLB and ITLB.
  */
-int __init sh64_tlb_init(void)
+int __cpuinit sh64_tlb_init(void)
 {
         /* Assign some sane DTLB defaults */
         cpu_data->dtlb.entries  = 64;
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index e74ff137762..67f1f6f5f4e 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -27,6 +27,7 @@ config SPARC
         select HAVE_ARCH_JUMP_LABEL
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_SHOW
+        select ARCH_WANT_IPC_PARSE_VERSION
         select USE_GENERIC_SMP_HELPERS if SMP
         select GENERIC_PCI_IOMAP
         select HAVE_NMI_WATCHDOG if SPARC64
diff --git a/arch/sparc/include/asm/fixmap.h b/arch/sparc/include/asm/fixmap.h
deleted file mode 100644
index f18fc0755ad..00000000000
--- a/arch/sparc/include/asm/fixmap.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * fixmap.h: compile-time virtual memory allocation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998 Ingo Molnar
- *
- * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
- */
-
-#ifndef _ASM_FIXMAP_H
-#define _ASM_FIXMAP_H
-
-#include <linux/kernel.h>
-#include <asm/page.h>
-#ifdef CONFIG_HIGHMEM
-#include <linux/threads.h>
-#include <asm/kmap_types.h>
-#endif
-
-/*
- * Here we define all the compile-time 'special' virtual
- * addresses. The point is to have a constant address at
- * compile time, but to set the physical address only
- * in the boot process. We allocate these special  addresses
- * from the top of unused virtual memory (0xfd000000 - 1 page) backwards.
- * Also this lets us do fail-safe vmalloc(), we
- * can guarantee that these special addresses and
- * vmalloc()-ed addresses never overlap.
- *
- * these 'compile-time allocated' memory buffers are
- * fixed-size 4k pages. (or larger if used with an increment
- * highger than 1) use fixmap_set(idx,phys) to associate
- * physical memory with fixmap indices.
- *
- * TLB entries of such buffers will not be flushed across
- * task switches.
- */
-
-/*
- * on UP currently we will have no trace of the fixmap mechanism,
- * no page table allocations, etc. This might change in the
- * future, say framebuffers for the console driver(s) could be
- * fix-mapped?
- */
-enum fixed_addresses {
-        FIX_HOLE,
-#ifdef CONFIG_HIGHMEM
-        FIX_KMAP_BEGIN,
-        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
-#endif
-        __end_of_fixed_addresses
-};
-
-extern void __set_fixmap (enum fixed_addresses idx,
-                                        unsigned long phys, pgprot_t flags);
-
-#define set_fixmap(idx, phys) \
-                __set_fixmap(idx, phys, PAGE_KERNEL)
-/*
- * Some hardware wants to get fixmapped without caching.
- */
-#define set_fixmap_nocache(idx, phys) \
-                __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
-/*
- * used by vmalloc.c.
- *
- * Leave one empty page between IO pages at 0xfd000000 and
- * the start of the fixmap.
- */
-#define FIXADDR_TOP     (0xfcfff000UL)
-#define FIXADDR_SIZE    ((__end_of_fixed_addresses) << PAGE_SHIFT)
-#define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
-
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * this branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-        return __virt_to_fix(vaddr);
-}
-
-#endif
diff --git a/arch/sparc/include/asm/highmem.h b/arch/sparc/include/asm/highmem.h
index 3b6e00dd96e..4f9e15c757e 100644
--- a/arch/sparc/include/asm/highmem.h
+++ b/arch/sparc/include/asm/highmem.h
@@ -21,7 +21,6 @@
 #ifdef __KERNEL__
 
 #include <linux/interrupt.h>
-#include <asm/fixmap.h>
 #include <asm/vaddrs.h>
 #include <asm/kmap_types.h>
 #include <asm/pgtable.h>
@@ -29,7 +28,6 @@
 /* declarations for highmem.c */
 extern unsigned long highstart_pfn, highend_pfn;
 
-extern pte_t *kmap_pte;
 extern pgprot_t kmap_prot;
 extern pte_t *pkmap_page_table;
 
@@ -72,7 +70,6 @@ static inline void kunmap(struct page *page)
 
 extern void *kmap_atomic(struct page *page);
 extern void __kunmap_atomic(void *kvaddr);
-extern struct page *kmap_atomic_to_page(void *vaddr);
 
 #define flush_cache_kmaps()     flush_cache_all()
 
diff --git a/arch/sparc/include/asm/leon.h b/arch/sparc/include/asm/leon.h
index 3375c629389..15a716934e4 100644
--- a/arch/sparc/include/asm/leon.h
+++ b/arch/sparc/include/asm/leon.h
@@ -82,7 +82,6 @@ static inline unsigned long leon_load_reg(unsigned long paddr)
 #define LEON_BYPASS_LOAD_PA(x)      leon_load_reg((unsigned long)(x))
 #define LEON_BYPASS_STORE_PA(x, v)  leon_store_reg((unsigned long)(x), (unsigned long)(v))
 
-extern void leon_init(void);
 extern void leon_switch_mm(void);
 extern void leon_init_IRQ(void);
 
diff --git a/arch/sparc/include/asm/mmu_context_32.h b/arch/sparc/include/asm/mmu_context_32.h
index 01456c90072..2df2a9be8f6 100644
--- a/arch/sparc/include/asm/mmu_context_32.h
+++ b/arch/sparc/include/asm/mmu_context_32.h
@@ -9,14 +9,12 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
 }
 
-/*
- * Initialize a new mmu context.  This is invoked when a new
+/* Initialize a new mmu context.  This is invoked when a new
  * address space instance (unique or shared) is instantiated.
  */
-#define init_new_context(tsk, mm) (((mm)->context = NO_CONTEXT), 0)
+int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 
-/*
- * Destroy a dead context.  This occurs when mmput drops the
+/* Destroy a dead context.  This occurs when mmput drops the
  * mm_users count to zero, the mmaps have been released, and
  * all the page tables have been flushed.  Our job is to destroy
  * any remaining processor-specific state.
diff --git a/arch/sparc/include/asm/page_32.h b/arch/sparc/include/asm/page_32.h
index fab78a308eb..f82a1f36b65 100644
--- a/arch/sparc/include/asm/page_32.h
+++ b/arch/sparc/include/asm/page_32.h
@@ -107,8 +107,7 @@ typedef unsigned long iopgprot_t;
 
 typedef struct page *pgtable_t;
 
-extern unsigned long sparc_unmapped_base;
-#define TASK_UNMAPPED_BASE      sparc_unmapped_base
+#define TASK_UNMAPPED_BASE      0x50000000
 
 #else /* !(__ASSEMBLY__) */
 
diff --git a/arch/sparc/include/asm/pgalloc_32.h b/arch/sparc/include/asm/pgalloc_32.h
index e5b169b46d2..9b1c36de0f1 100644
--- a/arch/sparc/include/asm/pgalloc_32.h
+++ b/arch/sparc/include/asm/pgalloc_32.h
@@ -11,28 +11,15 @@
 
 struct page;
 
-extern struct pgtable_cache_struct {
-        unsigned long *pgd_cache;
-        unsigned long *pte_cache;
-        unsigned long pgtable_cache_sz;
-        unsigned long pgd_cache_sz;
-} pgt_quicklists;
-
-unsigned long srmmu_get_nocache(int size, int align);
-void srmmu_free_nocache(unsigned long vaddr, int size);
-
-#define pgd_quicklist           (pgt_quicklists.pgd_cache)
-#define pmd_quicklist           ((unsigned long *)0)
-#define pte_quicklist           (pgt_quicklists.pte_cache)
-#define pgtable_cache_size      (pgt_quicklists.pgtable_cache_sz)
-#define pgd_cache_size          (pgt_quicklists.pgd_cache_sz)
+void *srmmu_get_nocache(int size, int align);
+void srmmu_free_nocache(void *addr, int size);
 
 #define check_pgt_cache()       do { } while (0)
 
 pgd_t *get_pgd_fast(void);
 static inline void free_pgd_fast(pgd_t *pgd)
 {
-        srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
+        srmmu_free_nocache(pgd, SRMMU_PGD_TABLE_SIZE);
 }
 
 #define pgd_free(mm, pgd)       free_pgd_fast(pgd)
@@ -50,13 +37,13 @@ static inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm,
                                    unsigned long address)
 {
-        return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
-                                          SRMMU_PMD_TABLE_SIZE);
+        return srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
+                                 SRMMU_PMD_TABLE_SIZE);
 }
 
 static inline void free_pmd_fast(pmd_t * pmd)
 {
-        srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
+        srmmu_free_nocache(pmd, SRMMU_PMD_TABLE_SIZE);
 }
 
 #define pmd_free(mm, pmd)               free_pmd_fast(pmd)
@@ -73,13 +60,13 @@ pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address);
 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
                                           unsigned long address)
 {
-        return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
+        return srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 }
 
 
 static inline void free_pte_fast(pte_t *pte)
 {
-        srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
+        srmmu_free_nocache(pte, PTE_SIZE);
 }
 
 #define pte_free_kernel(mm, pte)        free_pte_fast(pte)
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h
index cbbbed5cb3a..6fc13483f70 100644
--- a/arch/sparc/include/asm/pgtable_32.h
+++ b/arch/sparc/include/asm/pgtable_32.h
@@ -52,8 +52,9 @@ extern unsigned long calc_highpages(void);
 #define PAGE_READONLY   SRMMU_PAGE_RDONLY
 #define PAGE_KERNEL     SRMMU_PAGE_KERNEL
 
-/* Top-level page directory */
-extern pgd_t swapper_pg_dir[1024];
+/* Top-level page directory - dummy used by init-mm.
+ * srmmu.c will assign the real one (which is dynamically sized) */
+#define swapper_pg_dir NULL
 
 extern void paging_init(void);
 
@@ -78,8 +79,6 @@ extern unsigned long ptr_in_current_pgd;
 #define __S110  PAGE_SHARED
 #define __S111  PAGE_SHARED
 
-extern int num_contexts;
-
 /* First physical page can be anywhere, the following is needed so that
  * va-->pa and vice versa conversions work properly without performance
  * hit for all __pa()/__va() operations.
@@ -88,18 +87,11 @@ extern unsigned long phys_base;
 extern unsigned long pfn_base;
 
 /*
- * BAD_PAGETABLE is used when we need a bogus page-table, while
- * BAD_PAGE is used for a bogus page.
- *
  * ZERO_PAGE is a global shared page that is always zero: used
  * for zero-mapped memory areas etc..
  */
-extern pte_t * __bad_pagetable(void);
-extern pte_t __bad_page(void);
 extern unsigned long empty_zero_page;
 
-#define BAD_PAGETABLE __bad_pagetable()
-#define BAD_PAGE __bad_page()
 #define ZERO_PAGE(vaddr) (virt_to_page(&empty_zero_page))
 
 /*
@@ -398,36 +390,6 @@ static inline pte_t pgoff_to_pte(unsigned long pgoff)
  */
 #define PTE_FILE_MAX_BITS 24
 
-/*
- */
-struct ctx_list {
-        struct ctx_list *next;
-        struct ctx_list *prev;
-        unsigned int ctx_number;
-        struct mm_struct *ctx_mm;
-};
-
-extern struct ctx_list *ctx_list_pool;  /* Dynamically allocated */
-extern struct ctx_list ctx_free;        /* Head of free list */
-extern struct ctx_list ctx_used;        /* Head of used contexts list */
-
-#define NO_CONTEXT     -1
-
-static inline void remove_from_ctx_list(struct ctx_list *entry)
-{
-        entry->next->prev = entry->prev;
-        entry->prev->next = entry->next;
-}
-
-static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
-{
-        entry->next = head;
-        (entry->prev = head->prev)->next = entry;
-        head->prev = entry;
-}
-#define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
-#define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
-
 static inline unsigned long
 __get_phys (unsigned long addr)
 {
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h
index c7cb0af0eb5..fb269346480 100644
--- a/arch/sparc/include/asm/unistd.h
+++ b/arch/sparc/include/asm/unistd.h
@@ -423,7 +423,6 @@
 #endif
 
 #ifdef __KERNEL__
-#define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
 #define __ARCH_WANT_STAT64
 #define __ARCH_WANT_SYS_ALARM
diff --git a/arch/sparc/include/asm/vaddrs.h b/arch/sparc/include/asm/vaddrs.h
index da6535d88a7..c3dbcf90203 100644
--- a/arch/sparc/include/asm/vaddrs.h
+++ b/arch/sparc/include/asm/vaddrs.h
@@ -30,6 +30,28 @@
  */
 #define SRMMU_NOCACHE_ALCRATIO  64      /* 256 pages per 64MB of system RAM */
 
+#ifndef __ASSEMBLY__
+#include <asm/kmap_types.h>
+
+enum fixed_addresses {
+        FIX_HOLE,
+#ifdef CONFIG_HIGHMEM
+        FIX_KMAP_BEGIN,
+        FIX_KMAP_END = (KM_TYPE_NR * NR_CPUS),
+#endif
+        __end_of_fixed_addresses
+};
+#endif
+
+/* Leave one empty page between IO pages at 0xfd000000 and
+ * the top of the fixmap.
+ */
+#define FIXADDR_TOP             (0xfcfff000UL)
+#define FIXADDR_SIZE            ((FIX_KMAP_END + 1) << PAGE_SHIFT)
+#define FIXADDR_START           (FIXADDR_TOP - FIXADDR_SIZE)
+
+#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
+
 #define SUN4M_IOBASE_VADDR      0xfd000000 /* Base for mapping pages */
 #define IOBASE_VADDR            0xfe000000
 #define IOBASE_END              0xfe600000
diff --git a/arch/sparc/kernel/head_32.S b/arch/sparc/kernel/head_32.S
index afeb1d77030..3d92c0a8f6c 100644
--- a/arch/sparc/kernel/head_32.S
+++ b/arch/sparc/kernel/head_32.S
@@ -58,8 +58,6 @@ sun4e_notsup:
 /* This was the only reasonable way I could think of to properly align
  * these page-table data structures.
  */
-        .globl swapper_pg_dir
-swapper_pg_dir:         .skip PAGE_SIZE
         .globl empty_zero_page
 empty_zero_page:        .skip PAGE_SIZE
 
diff --git a/arch/sparc/kernel/ldc.c b/arch/sparc/kernel/ldc.c
index 435e406fdec..81d92fc9983 100644
--- a/arch/sparc/kernel/ldc.c
+++ b/arch/sparc/kernel/ldc.c
@@ -1250,14 +1250,12 @@ int ldc_bind(struct ldc_channel *lp, const char *name)
         snprintf(lp->rx_irq_name, LDC_IRQ_NAME_MAX, "%s RX", name);
         snprintf(lp->tx_irq_name, LDC_IRQ_NAME_MAX, "%s TX", name);
 
-        err = request_irq(lp->cfg.rx_irq, ldc_rx,
-                          IRQF_SAMPLE_RANDOM | IRQF_DISABLED,
+        err = request_irq(lp->cfg.rx_irq, ldc_rx, IRQF_DISABLED,
                           lp->rx_irq_name, lp);
         if (err)
                 return err;
 
-        err = request_irq(lp->cfg.tx_irq, ldc_tx,
-                          IRQF_SAMPLE_RANDOM | IRQF_DISABLED,
+        err = request_irq(lp->cfg.tx_irq, ldc_tx, IRQF_DISABLED,
                           lp->tx_irq_name, lp);
         if (err) {
                 free_irq(lp->cfg.rx_irq, lp);
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index e34e2c40c06..f8b6eee40bd 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -486,17 +486,6 @@ void __init leon_trans_init(struct device_node *dp)
         }
 }
 
-void __initdata (*prom_amba_init)(struct device_node *dp, struct device_node ***nextp) = 0;
-
-void __init leon_node_init(struct device_node *dp, struct device_node ***nextp)
-{
-        if (prom_amba_init &&
-            strcmp(dp->type, "ambapp") == 0 &&
-            strcmp(dp->name, "ambapp0") == 0) {
-                prom_amba_init(dp, nextp);
-        }
-}
-
 #ifdef CONFIG_SMP
 void leon_clear_profile_irq(int cpu)
 {
@@ -522,8 +511,3 @@ void __init leon_init_IRQ(void)
         sparc_config.clear_clock_irq  = leon_clear_clock_irq;
         sparc_config.load_profile_irq = leon_load_profile_irq;
 }
-
-void __init leon_init(void)
-{
-        of_pdt_build_more = &leon_node_init;
-}
diff --git a/arch/sparc/kernel/leon_pci.c b/arch/sparc/kernel/leon_pci.c
index 19f56058742..21dcda75a52 100644
--- a/arch/sparc/kernel/leon_pci.c
+++ b/arch/sparc/kernel/leon_pci.c
@@ -91,14 +91,6 @@ void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
         }
 }
 
-/*
- * Other archs parse arguments here.
- */
-char * __devinit pcibios_setup(char *str)
-{
-        return str;
-}
-
 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
                                 resource_size_t size, resource_size_t align)
 {
diff --git a/arch/sparc/kernel/of_device_64.c b/arch/sparc/kernel/of_device_64.c
index 7a3be6f6737..7bbdc26d951 100644
--- a/arch/sparc/kernel/of_device_64.c
+++ b/arch/sparc/kernel/of_device_64.c
@@ -580,7 +580,7 @@ static unsigned int __init build_one_device_irq(struct platform_device *op,
                                 printk("%s: Apply [%s:%x] imap --> [%s:%x]\n",
                                        op->dev.of_node->full_name,
                                        pp->full_name, this_orig_irq,
-                                       (iret ? iret->full_name : "NULL"), irq);
+                                       of_node_full_name(iret), irq);
 
                         if (!iret)
                                 break;
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index fdaf2181167..065b88c4f86 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -375,93 +375,6 @@ static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
         *last_p = last;
 }
 
-/* For PCI bus devices which lack a 'ranges' property we interrogate
- * the config space values to set the resources, just like the generic
- * Linux PCI probing code does.
- */
-static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
-                                          struct pci_bus *bus,
-                                          struct pci_pbm_info *pbm)
-{
-        struct pci_bus_region region;
-        struct resource *res, res2;
-        u8 io_base_lo, io_limit_lo;
-        u16 mem_base_lo, mem_limit_lo;
-        unsigned long base, limit;
-
-        pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
-        pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
-        base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
-        limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
-
-        if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
-                u16 io_base_hi, io_limit_hi;
-
-                pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
-                pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
-                base |= (io_base_hi << 16);
-                limit |= (io_limit_hi << 16);
-        }
-
-        res = bus->resource[0];
-        if (base <= limit) {
-                res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
-                res2.flags = res->flags;
-                region.start = base;
-                region.end = limit + 0xfff;
-                pcibios_bus_to_resource(dev, &res2, &region);
-                if (!res->start)
-                        res->start = res2.start;
-                if (!res->end)
-                        res->end = res2.end;
-        }
-
-        pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
-        pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
-        base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
-        limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
-
-        res = bus->resource[1];
-        if (base <= limit) {
-                res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
-                              IORESOURCE_MEM);
-                region.start = base;
-                region.end = limit + 0xfffff;
-                pcibios_bus_to_resource(dev, res, &region);
-        }
-
-        pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
-        pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
-        base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
-        limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
-
-        if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
-                u32 mem_base_hi, mem_limit_hi;
-
-                pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
-                pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
-
-                /*
-                 * Some bridges set the base > limit by default, and some
-                 * (broken) BIOSes do not initialize them.  If we find
-                 * this, just assume they are not being used.
-                 */
-                if (mem_base_hi <= mem_limit_hi) {
-                        base |= ((long) mem_base_hi) << 32;
-                        limit |= ((long) mem_limit_hi) << 32;
-                }
-        }
-
-        res = bus->resource[2];
-        if (base <= limit) {
-                res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
-                              IORESOURCE_MEM | IORESOURCE_PREFETCH);
-                region.start = base;
-                region.end = limit + 0xfffff;
-                pcibios_bus_to_resource(dev, res, &region);
-        }
-}
-
 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
  * a proper 'ranges' property.
  */
@@ -535,7 +448,7 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
         }
 
         bus->primary = dev->bus->number;
-        bus->subordinate = busrange[1];
+        pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
         bus->bridge_ctl = 0;
 
         /* parse ranges property, or cook one up by hand for Simba */
@@ -550,7 +463,7 @@ static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
                 apb_fake_ranges(dev, bus, pbm);
                 goto after_ranges;
         } else if (ranges == NULL) {
-                pci_cfg_fake_ranges(dev, bus, pbm);
+                pci_read_bridge_bases(bus);
                 goto after_ranges;
         }
         i = 1;
@@ -685,6 +598,10 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
                                 pbm->io_space.start);
         pci_add_resource_offset(&resources, &pbm->mem_space,
                                 pbm->mem_space.start);
+        pbm->busn.start = pbm->pci_first_busno;
+        pbm->busn.end   = pbm->pci_last_busno;
+        pbm->busn.flags = IORESOURCE_BUS;
+        pci_add_resource(&resources, &pbm->busn);
         bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
                                   pbm, &resources);
         if (!bus) {
@@ -693,8 +610,6 @@ struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
                 pci_free_resource_list(&resources);
                 return NULL;
         }
-        bus->secondary = pbm->pci_first_busno;
-        bus->subordinate = pbm->pci_last_busno;
 
         pci_of_scan_bus(pbm, node, bus);
         pci_bus_add_devices(bus);
@@ -747,11 +662,6 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return 0;
 }
 
-char * __devinit pcibios_setup(char *str)
-{
-        return str;
-}
-
 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
 
 /* If the user uses a host-bridge as the PCI device, he may use
diff --git a/arch/sparc/kernel/pci_impl.h b/arch/sparc/kernel/pci_impl.h
index 6beb60df31d..918a2031c8b 100644
--- a/arch/sparc/kernel/pci_impl.h
+++ b/arch/sparc/kernel/pci_impl.h
@@ -97,6 +97,7 @@ struct pci_pbm_info {
         /* PBM I/O and Memory space resources. */
         struct resource                 io_space;
         struct resource                 mem_space;
+        struct resource                 busn;
 
         /* Base of PCI Config space, can be per-PBM or shared. */
         unsigned long                   config_space;
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
index ded3f6090c3..521fdf1b20e 100644
--- a/arch/sparc/kernel/pcic.c
+++ b/arch/sparc/kernel/pcic.c
@@ -767,14 +767,6 @@ static void watchdog_reset() {
 }
 #endif
 
-/*
- * Other archs parse arguments here.
- */
-char * __devinit pcibios_setup(char *str)
-{
-        return str;
-}
-
 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
                                 resource_size_t size, resource_size_t align)
 {
@@ -884,11 +876,6 @@ void __init sun4m_pci_init_IRQ(void)
         sparc_config.load_profile_irq = pcic_load_profile_irq;
 }
 
-int pcibios_assign_resource(struct pci_dev *pdev, int resource)
-{
-        return -ENXIO;
-}
-
 /*
  * This probably belongs here rather than ioport.c because
  * we do not want this crud linked into SBus kernels.
diff --git a/arch/sparc/kernel/process_32.c b/arch/sparc/kernel/process_32.c
index cb36e82dcd5..14006d8aca2 100644
--- a/arch/sparc/kernel/process_32.c
+++ b/arch/sparc/kernel/process_32.c
@@ -333,9 +333,6 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
                 put_psr(get_psr() | PSR_EF);
                 fpsave(&p->thread.float_regs[0], &p->thread.fsr,
                        &p->thread.fpqueue[0], &p->thread.fpqdepth);
-#ifdef CONFIG_SMP
-                clear_thread_flag(TIF_USEDFPU);
-#endif
         }
 
         /*
@@ -413,6 +410,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
 #ifdef CONFIG_SMP
         /* FPU must be disabled on SMP. */
         childregs->psr &= ~PSR_EF;
+        clear_tsk_thread_flag(p, TIF_USEDFPU);
 #endif
 
         /* Set the return value for the child. */
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index efe3e64bba3..38bf80a22f0 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -371,7 +371,6 @@ void __init setup_arch(char **cmdline_p)
                 (*(linux_dbvec->teach_debugger))();
         }
 
-        init_mm.context = (unsigned long) NO_CONTEXT;
         init_task.thread.kregs = &fake_swapper_regs;
 
         /* Run-time patch instructions to match the cpu model */
diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c
index f591598d92f..781bcb10b8b 100644
--- a/arch/sparc/kernel/smp_64.c
+++ b/arch/sparc/kernel/smp_64.c
@@ -103,8 +103,6 @@ void __cpuinit smp_callin(void)
         if (cheetah_pcache_forced_on)
                 cheetah_enable_pcache();
 
-        local_irq_enable();
-
         callin_flag = 1;
         __asm__ __volatile__("membar #Sync\n\t"
                              "flush  %%g6" : : : "memory");
@@ -124,9 +122,8 @@ void __cpuinit smp_callin(void)
         while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
                 rmb();
 
-        ipi_call_lock_irq();
         set_cpu_online(cpuid, true);
-        ipi_call_unlock_irq();
+        local_irq_enable();
 
         /* idle thread is expected to have preempt disabled */
         preempt_disable();
@@ -1308,9 +1305,7 @@ int __cpu_disable(void)
         mdelay(1);
         local_irq_disable();
 
-        ipi_call_lock();
         set_cpu_online(cpu, false);
-        ipi_call_unlock();
 
         cpu_map_rebuild();
 
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index 275f74fd6f6..11c6c9603e7 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -66,23 +66,6 @@ static inline int invalid_64bit_range(unsigned long addr, unsigned long len)
         return 0;
 }
 
-/* Does start,end straddle the VA-space hole?  */
-static inline int straddles_64bit_va_hole(unsigned long start, unsigned long end)
-{
-        unsigned long va_exclude_start, va_exclude_end;
-
-        va_exclude_start = VA_EXCLUDE_START;
-        va_exclude_end   = VA_EXCLUDE_END;
-
-        if (likely(start < va_exclude_start && end < va_exclude_start))
-                return 0;
-
-        if (likely(start >= va_exclude_end && end >= va_exclude_end))
-                return 0;
-
-        return 1;
-}
-
 /* These functions differ from the default implementations in
  * mm/mmap.c in two ways:
  *
@@ -487,7 +470,7 @@ SYSCALL_DEFINE6(sparc_ipc, unsigned int, call, int, first, unsigned long, second
                 switch (call) {
                 case SHMAT: {
                         ulong raddr;
-                        err = do_shmat(first, ptr, (int)second, &raddr);
+                        err = do_shmat(first, ptr, (int)second, &raddr, SHMLBA);
                         if (!err) {
                                 if (put_user(raddr,
                                              (ulong __user *) third))
@@ -519,12 +502,12 @@ SYSCALL_DEFINE1(sparc64_personality, unsigned long, personality)
 {
         int ret;
 
-        if (current->personality == PER_LINUX32 &&
-            personality == PER_LINUX)
-                personality = PER_LINUX32;
+        if (personality(current->personality) == PER_LINUX32 &&
+            personality(personality) == PER_LINUX)
+                personality |= PER_LINUX32;
         ret = sys_personality(personality);
-        if (ret == PER_LINUX32)
-                ret = PER_LINUX;
+        if (personality(ret) == PER_LINUX32)
+                ret &= ~PER_LINUX32;
 
         return ret;
 }
diff --git a/arch/sparc/lib/NG2memcpy.S b/arch/sparc/lib/NG2memcpy.S
index 0aed75653b5..03eadf66b0d 100644
--- a/arch/sparc/lib/NG2memcpy.S
+++ b/arch/sparc/lib/NG2memcpy.S
@@ -90,49 +90,49 @@
         faligndata      %x7, %x8, %f14;
 
 #define FREG_MOVE_1(x0) \
-        fmovd           %x0, %f0;
+        fsrc2           %x0, %f0;
 #define FREG_MOVE_2(x0, x1) \
-        fmovd           %x0, %f0; \
-        fmovd           %x1, %f2;
+        fsrc2           %x0, %f0; \
+        fsrc2           %x1, %f2;
 #define FREG_MOVE_3(x0, x1, x2) \
-        fmovd           %x0, %f0; \
-        fmovd           %x1, %f2; \
-        fmovd           %x2, %f4;
+        fsrc2           %x0, %f0; \
+        fsrc2           %x1, %f2; \
+        fsrc2           %x2, %f4;
 #define FREG_MOVE_4(x0, x1, x2, x3) \
-        fmovd           %x0, %f0; \
-        fmovd           %x1, %f2; \
-        fmovd           %x2, %f4; \
-        fmovd           %x3, %f6;
+        fsrc2           %x0, %f0; \
+        fsrc2           %x1, %f2; \
+        fsrc2           %x2, %f4; \
+        fsrc2           %x3, %f6;
 #define FREG_MOVE_5(x0, x1, x2, x3, x4) \
-        fmovd           %x0, %f0; \
-        fmovd           %x1, %f2; \
-        fmovd           %x2, %f4; \
-        fmovd           %x3, %f6; \
-        fmovd           %x4, %f8;
+        fsrc2           %x0, %f0; \
+        fsrc2           %x1, %f2; \
+        fsrc2           %x2, %f4; \
+        fsrc2           %x3, %f6; \
+        fsrc2           %x4, %f8;
 #define FREG_MOVE_6(x0, x1, x2, x3, x4, x5) \
-        fmovd           %x0, %f0; \
-        fmovd           %x1, %f2; \
-        fmovd           %x2, %f4; \
-        fmovd           %x3, %f6; \
-        fmovd           %x4, %f8; \
-        fmovd           %x5, %f10;
+        fsrc2           %x0, %f0; \
+        fsrc2           %x1, %f2; \
+        fsrc2           %x2, %f4; \
+        fsrc2           %x3, %f6; \
+        fsrc2           %x4, %f8; \
+        fsrc2           %x5, %f10;
 #define FREG_MOVE_7(x0, x1, x2, x3, x4, x5, x6) \
-        fmovd           %x0, %f0; \
-        fmovd           %x1, %f2; \
-        fmovd           %x2, %f4; \
-        fmovd           %x3, %f6; \
-        fmovd           %x4, %f8; \
-        fmovd           %x5, %f10; \
-        fmovd           %x6, %f12;
+        fsrc2           %x0, %f0; \
+        fsrc2           %x1, %f2; \
+        fsrc2           %x2, %f4; \
+        fsrc2           %x3, %f6; \
+        fsrc2           %x4, %f8; \
+        fsrc2           %x5, %f10; \
+        fsrc2           %x6, %f12;
 #define FREG_MOVE_8(x0, x1, x2, x3, x4, x5, x6, x7) \
-        fmovd           %x0, %f0; \
-        fmovd           %x1, %f2; \
-        fmovd           %x2, %f4; \
-        fmovd           %x3, %f6; \
-        fmovd           %x4, %f8; \
-        fmovd           %x5, %f10; \
-        fmovd           %x6, %f12; \
-        fmovd           %x7, %f14;
+        fsrc2           %x0, %f0; \
+        fsrc2           %x1, %f2; \
+        fsrc2           %x2, %f4; \
+        fsrc2           %x3, %f6; \
+        fsrc2           %x4, %f8; \
+        fsrc2           %x5, %f10; \
+        fsrc2           %x6, %f12; \
+        fsrc2           %x7, %f14;
 #define FREG_LOAD_1(base, x0) \
         EX_LD(LOAD(ldd, base + 0x00, %x0))
 #define FREG_LOAD_2(base, x0, x1) \
diff --git a/arch/sparc/lib/U1memcpy.S b/arch/sparc/lib/U1memcpy.S
index bafd2fc07ac..b67142b7768 100644
--- a/arch/sparc/lib/U1memcpy.S
+++ b/arch/sparc/lib/U1memcpy.S
@@ -109,7 +109,7 @@
 #define UNEVEN_VISCHUNK_LAST(dest, f0, f1, left)        \
         subcc                   %left, 8, %left;        \
         bl,pn                   %xcc, 95f;              \
-         fsrc1                  %f0, %f1;
+         fsrc2                  %f0, %f1;
 
 #define UNEVEN_VISCHUNK(dest, f0, f1, left)             \
         UNEVEN_VISCHUNK_LAST(dest, f0, f1, left)        \
@@ -201,7 +201,7 @@ FUNC_NAME:		/* %o0=dst, %o1=src, %o2=len */
         andn            %o1, (0x40 - 1), %o1
         and             %g2, 7, %g2
         andncc          %g3, 0x7, %g3
-        fmovd           %f0, %f2
+        fsrc2           %f0, %f2
         sub             %g3, 0x8, %g3
         sub             %o2, %GLOBAL_SPARE, %o2
 
diff --git a/arch/sparc/lib/copy_page.S b/arch/sparc/lib/copy_page.S
index b243d3b606b..4d2df328e51 100644
--- a/arch/sparc/lib/copy_page.S
+++ b/arch/sparc/lib/copy_page.S
@@ -34,10 +34,10 @@
 #endif
 
 #define TOUCH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7)   \
-        fmovd   %reg0, %f48;    fmovd   %reg1, %f50;            \
-        fmovd   %reg2, %f52;    fmovd   %reg3, %f54;            \
-        fmovd   %reg4, %f56;    fmovd   %reg5, %f58;            \
-        fmovd   %reg6, %f60;    fmovd   %reg7, %f62;
+        fsrc2   %reg0, %f48;    fsrc2   %reg1, %f50;            \
+        fsrc2   %reg2, %f52;    fsrc2   %reg3, %f54;            \
+        fsrc2   %reg4, %f56;    fsrc2   %reg5, %f58;            \
+        fsrc2   %reg6, %f60;    fsrc2   %reg7, %f62;
 
         .text
 
@@ -104,60 +104,60 @@ cheetah_copy_page_insn:
         prefetch        [%o1 + 0x140], #one_read
         ldd             [%o1 + 0x010], %f4
         prefetch        [%o1 + 0x180], #one_read
-        fmovd           %f0, %f16
+        fsrc2           %f0, %f16
         ldd             [%o1 + 0x018], %f6
-        fmovd           %f2, %f18
+        fsrc2           %f2, %f18
         ldd             [%o1 + 0x020], %f8
-        fmovd           %f4, %f20
+        fsrc2           %f4, %f20
         ldd             [%o1 + 0x028], %f10
-        fmovd           %f6, %f22
+        fsrc2           %f6, %f22
         ldd             [%o1 + 0x030], %f12
-        fmovd           %f8, %f24
+        fsrc2           %f8, %f24
         ldd             [%o1 + 0x038], %f14
-        fmovd           %f10, %f26
+        fsrc2           %f10, %f26
         ldd             [%o1 + 0x040], %f0
 1:      ldd             [%o1 + 0x048], %f2
-        fmovd           %f12, %f28
+        fsrc2           %f12, %f28
         ldd             [%o1 + 0x050], %f4
-        fmovd           %f14, %f30
+        fsrc2           %f14, %f30
         stda            %f16, [%o0] ASI_BLK_P
         ldd             [%o1 + 0x058], %f6
-        fmovd           %f0, %f16
+        fsrc2           %f0, %f16
         ldd             [%o1 + 0x060], %f8
-        fmovd           %f2, %f18
+        fsrc2           %f2, %f18
         ldd             [%o1 + 0x068], %f10
-        fmovd           %f4, %f20
+        fsrc2           %f4, %f20
         ldd             [%o1 + 0x070], %f12
-        fmovd           %f6, %f22
+        fsrc2           %f6, %f22
         ldd             [%o1 + 0x078], %f14
-        fmovd           %f8, %f24
+        fsrc2           %f8, %f24
         ldd             [%o1 + 0x080], %f0
         prefetch        [%o1 + 0x180], #one_read
-        fmovd           %f10, %f26
+        fsrc2           %f10, %f26
         subcc           %o2, 1, %o2
         add             %o0, 0x40, %o0
         bne,pt          %xcc, 1b
          add            %o1, 0x40, %o1
 
         ldd             [%o1 + 0x048], %f2
-        fmovd           %f12, %f28
+        fsrc2           %f12, %f28
         ldd             [%o1 + 0x050], %f4
-        fmovd           %f14, %f30
+        fsrc2           %f14, %f30
         stda            %f16, [%o0] ASI_BLK_P
         ldd             [%o1 + 0x058], %f6
-        fmovd           %f0, %f16
+        fsrc2           %f0, %f16
         ldd             [%o1 + 0x060], %f8
-        fmovd           %f2, %f18
+        fsrc2           %f2, %f18
         ldd             [%o1 + 0x068], %f10
-        fmovd           %f4, %f20
+        fsrc2           %f4, %f20
         ldd             [%o1 + 0x070], %f12
-        fmovd           %f6, %f22
+        fsrc2           %f6, %f22
         add             %o0, 0x40, %o0
         ldd             [%o1 + 0x078], %f14
-        fmovd           %f8, %f24
-        fmovd           %f10, %f26
-        fmovd           %f12, %f28
-        fmovd           %f14, %f30
+        fsrc2           %f8, %f24
+        fsrc2           %f10, %f26
+        fsrc2           %f12, %f28
+        fsrc2           %f14, %f30
         stda            %f16, [%o0] ASI_BLK_P
         membar          #Sync
         VISExitHalf
diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c
index f46cf6be337..77ac917be15 100644
--- a/arch/sparc/mm/fault_32.c
+++ b/arch/sparc/mm/fault_32.c
@@ -32,24 +32,6 @@
 
 int show_unhandled_signals = 1;
 
-/* At boot time we determine these two values necessary for setting
- * up the segment maps and page table entries (pte's).
- */
-
-int num_contexts;
-
-/* Return how much physical memory we have.  */
-unsigned long probe_memory(void)
-{
-        unsigned long total = 0;
-        int i;
-
-        for (i = 0; sp_banks[i].num_bytes; i++)
-                total += sp_banks[i].num_bytes;
-
-        return total;
-}
-
 static void unhandled_fault(unsigned long, struct task_struct *,
                 struct pt_regs *) __attribute__ ((noreturn));
 
diff --git a/arch/sparc/mm/highmem.c b/arch/sparc/mm/highmem.c
index 055c66cf1bf..449f864f0ce 100644
--- a/arch/sparc/mm/highmem.c
+++ b/arch/sparc/mm/highmem.c
@@ -22,13 +22,31 @@
  * shared by CPUs, and so precious, and establishing them requires IPI.
  * Atomic kmaps are lightweight and we may have NCPUS more of them.
  */
-#include <linux/mm.h>
 #include <linux/highmem.h>
 #include <linux/export.h>
-#include <asm/pgalloc.h>
+#include <linux/mm.h>
+
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
-#include <asm/fixmap.h>
+#include <asm/pgalloc.h>
+#include <asm/vaddrs.h>
+
+pgprot_t kmap_prot;
+
+static pte_t *kmap_pte;
+
+void __init kmap_init(void)
+{
+        unsigned long address;
+        pmd_t *dir;
+
+        address = __fix_to_virt(FIX_KMAP_BEGIN);
+        dir = pmd_offset(pgd_offset_k(address), address);
+
+        /* cache the first kmap pte */
+        kmap_pte = pte_offset_kernel(dir, address);
+        kmap_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV | SRMMU_CACHE);
+}
 
 void *kmap_atomic(struct page *page)
 {
@@ -110,21 +128,3 @@ void __kunmap_atomic(void *kvaddr)
         pagefault_enable();
 }
 EXPORT_SYMBOL(__kunmap_atomic);
-
-/* We may be fed a pagetable here by ptep_to_xxx and others. */
-struct page *kmap_atomic_to_page(void *ptr)
-{
-        unsigned long idx, vaddr = (unsigned long)ptr;
-        pte_t *pte;
-
-        if (vaddr < SRMMU_NOCACHE_VADDR)
-                return virt_to_page(ptr);
-        if (vaddr < PKMAP_BASE)
-                return pfn_to_page(__nocache_pa(vaddr) >> PAGE_SHIFT);
-        BUG_ON(vaddr < FIXADDR_START);
-        BUG_ON(vaddr > FIXADDR_TOP);
-
-        idx = virt_to_fix(vaddr);
-        pte = kmap_pte - (idx - FIX_KMAP_BEGIN);
-        return pte_page(*pte);
-}
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index ef5c779ec85..dde85ef1c56 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -45,9 +45,6 @@ unsigned long pfn_base;
 EXPORT_SYMBOL(pfn_base);
 
 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS+1];
-unsigned long sparc_unmapped_base;
-
-struct pgtable_cache_struct pgt_quicklists;
 
 /* Initial ramdisk setup */
 extern unsigned int sparc_ramdisk_image;
@@ -55,19 +52,6 @@ extern unsigned int sparc_ramdisk_size;
 
 unsigned long highstart_pfn, highend_pfn;
 
-pte_t *kmap_pte;
-pgprot_t kmap_prot;
-
-#define kmap_get_fixmap_pte(vaddr) \
-        pte_offset_kernel(pmd_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr))
-
-void __init kmap_init(void)
-{
-        /* cache the first kmap pte */
-        kmap_pte = kmap_get_fixmap_pte(__fix_to_virt(FIX_KMAP_BEGIN));
-        kmap_prot = __pgprot(SRMMU_ET_PTE | SRMMU_PRIV | SRMMU_CACHE);
-}
-
 void show_mem(unsigned int filter)
 {
         printk("Mem-info:\n");
@@ -76,33 +60,8 @@ void show_mem(unsigned int filter)
                nr_swap_pages << (PAGE_SHIFT-10));
         printk("%ld pages of RAM\n", totalram_pages);
         printk("%ld free pages\n", nr_free_pages());
-#if 0 /* undefined pgtable_cache_size, pgd_cache_size */
-        printk("%ld pages in page table cache\n",pgtable_cache_size);
-#ifndef CONFIG_SMP
-        if (sparc_cpu_model == sun4m || sparc_cpu_model == sun4d)
-                printk("%ld entries in page dir cache\n",pgd_cache_size);
-#endif  
-#endif
 }
 
-void __init sparc_context_init(int numctx)
-{
-        int ctx;
-
-        ctx_list_pool = __alloc_bootmem(numctx * sizeof(struct ctx_list), SMP_CACHE_BYTES, 0UL);
-
-        for(ctx = 0; ctx < numctx; ctx++) {
-                struct ctx_list *clist;
-
-                clist = (ctx_list_pool + ctx);
-                clist->ctx_number = ctx;
-                clist->ctx_mm = NULL;
-        }
-        ctx_free.next = ctx_free.prev = &ctx_free;
-        ctx_used.next = ctx_used.prev = &ctx_used;
-        for(ctx = 0; ctx < numctx; ctx++)
-                add_to_free_ctxlist(ctx_list_pool + ctx);
-}
 
 extern unsigned long cmdline_memory_size;
 unsigned long last_valid_pfn;
@@ -292,22 +251,7 @@ extern void device_scan(void);
 
 void __init paging_init(void)
 {
-        switch(sparc_cpu_model) {
-        case sparc_leon:
-                leon_init();
-                /* fall through */
-        case sun4m:
-        case sun4d:
-                srmmu_paging_init();
-                sparc_unmapped_base = 0x50000000;
-                break;
-        default:
-                prom_printf("paging_init: Cannot init paging on this Sparc\n");
-                prom_printf("paging_init: sparc_cpu_model = %d\n", sparc_cpu_model);
-                prom_printf("paging_init: Halting...\n");
-                prom_halt();
-        }
-
+        srmmu_paging_init();
         prom_build_devicetree();
         of_fill_in_cpu_data();
         device_scan();
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index 6026fdd1b2e..d58edf5fefd 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -2020,6 +2020,9 @@ EXPORT_SYMBOL(_PAGE_CACHE);
 #ifdef CONFIG_SPARSEMEM_VMEMMAP
 unsigned long vmemmap_table[VMEMMAP_SIZE];
 
+static long __meminitdata addr_start, addr_end;
+static int __meminitdata node_start;
+
 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
 {
         unsigned long vstart = (unsigned long) start;
@@ -2050,15 +2053,30 @@ int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
 
                         *vmem_pp = pte_base | __pa(block);
 
-                        printk(KERN_INFO "[%p-%p] page_structs=%lu "
-                               "node=%d entry=%lu/%lu\n", start, block, nr,
-                               node,
-                               addr >> VMEMMAP_CHUNK_SHIFT,
-                               VMEMMAP_SIZE);
+                        /* check to see if we have contiguous blocks */
+                        if (addr_end != addr || node_start != node) {
+                                if (addr_start)
+                                        printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
+                                               addr_start, addr_end-1, node_start);
+                                addr_start = addr;
+                                node_start = node;
+                        }
+                        addr_end = addr + VMEMMAP_CHUNK;
                 }
         }
         return 0;
 }
+
+void __meminit vmemmap_populate_print_last(void)
+{
+        if (addr_start) {
+                printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
+                       addr_start, addr_end-1, node_start);
+                addr_start = 0;
+                addr_end = 0;
+                node_start = 0;
+        }
+}
 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
 
 static void prot_init_common(unsigned long page_none,
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 62e3f577330..c38bb72e3e8 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -8,45 +8,45 @@
  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
  */
 
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/vmalloc.h>
-#include <linux/pagemap.h>
-#include <linux/init.h>
+#include <linux/seq_file.h>
 #include <linux/spinlock.h>
 #include <linux/bootmem.h>
-#include <linux/fs.h>
-#include <linux/seq_file.h>
+#include <linux/pagemap.h>
+#include <linux/vmalloc.h>
 #include <linux/kdebug.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
 #include <linux/log2.h>
 #include <linux/gfp.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
 
-#include <asm/bitext.h>
-#include <asm/page.h>
+#include <asm/mmu_context.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/io-unit.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
-#include <asm/io.h>
+#include <asm/bitext.h>
 #include <asm/vaddrs.h>
-#include <asm/traps.h>
-#include <asm/smp.h>
-#include <asm/mbus.h>
 #include <asm/cache.h>
+#include <asm/traps.h>
 #include <asm/oplib.h>
+#include <asm/mbus.h>
+#include <asm/page.h>
 #include <asm/asi.h>
 #include <asm/msi.h>
-#include <asm/mmu_context.h>
-#include <asm/io-unit.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
+#include <asm/smp.h>
+#include <asm/io.h>
 
 /* Now the cpu specific definitions. */
-#include <asm/viking.h>
-#include <asm/mxcc.h>
-#include <asm/ross.h>
+#include <asm/turbosparc.h>
 #include <asm/tsunami.h>
+#include <asm/viking.h>
 #include <asm/swift.h>
-#include <asm/turbosparc.h>
 #include <asm/leon.h>
+#include <asm/mxcc.h>
+#include <asm/ross.h>
 
 #include "srmmu.h"
 
@@ -55,10 +55,6 @@ static unsigned int hwbug_bitmask;
 int vac_cache_size;
 int vac_line_size;
 
-struct ctx_list *ctx_list_pool;
-struct ctx_list ctx_free;
-struct ctx_list ctx_used;
-
 extern struct resource sparc_iomap;
 
 extern unsigned long last_valid_pfn;
@@ -136,8 +132,8 @@ void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
         }
 }
 
-/* Find an entry in the third-level page table.. */ 
-pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address)
+/* Find an entry in the third-level page table.. */
+pte_t *pte_offset_kernel(pmd_t *dir, unsigned long address)
 {
         void *pte;
 
@@ -151,55 +147,61 @@ pte_t *pte_offset_kernel(pmd_t * dir, unsigned long address)
  * align: bytes, number to align at.
  * Returns the virtual address of the allocated area.
  */
-static unsigned long __srmmu_get_nocache(int size, int align)
+static void *__srmmu_get_nocache(int size, int align)
 {
         int offset;
+        unsigned long addr;
 
         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
-                printk("Size 0x%x too small for nocache request\n", size);
+                printk(KERN_ERR "Size 0x%x too small for nocache request\n",
+                       size);
                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
         }
-        if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
-                printk("Size 0x%x unaligned int nocache request\n", size);
-                size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
+        if (size & (SRMMU_NOCACHE_BITMAP_SHIFT - 1)) {
+                printk(KERN_ERR "Size 0x%x unaligned int nocache request\n",
+                       size);
+                size += SRMMU_NOCACHE_BITMAP_SHIFT - 1;
         }
         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 
         offset = bit_map_string_get(&srmmu_nocache_map,
-                                        size >> SRMMU_NOCACHE_BITMAP_SHIFT,
-                                        align >> SRMMU_NOCACHE_BITMAP_SHIFT);
+                                    size >> SRMMU_NOCACHE_BITMAP_SHIFT,
+                                    align >> SRMMU_NOCACHE_BITMAP_SHIFT);
         if (offset == -1) {
-                printk("srmmu: out of nocache %d: %d/%d\n",
-                    size, (int) srmmu_nocache_size,
-                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
+                printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n",
+                       size, (int) srmmu_nocache_size,
+                       srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
                 return 0;
         }
 
-        return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
+        addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT);
+        return (void *)addr;
 }
 
-unsigned long srmmu_get_nocache(int size, int align)
+void *srmmu_get_nocache(int size, int align)
 {
-        unsigned long tmp;
+        void *tmp;
 
         tmp = __srmmu_get_nocache(size, align);
 
         if (tmp)
-                memset((void *)tmp, 0, size);
+                memset(tmp, 0, size);
 
         return tmp;
 }
 
-void srmmu_free_nocache(unsigned long vaddr, int size)
+void srmmu_free_nocache(void *addr, int size)
 {
+        unsigned long vaddr;
         int offset;
 
+        vaddr = (unsigned long)addr;
         if (vaddr < SRMMU_NOCACHE_VADDR) {
                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
                 BUG();
         }
-        if (vaddr+size > srmmu_nocache_end) {
+        if (vaddr + size > srmmu_nocache_end) {
                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
                     vaddr, srmmu_nocache_end);
                 BUG();
@@ -212,7 +214,7 @@ void srmmu_free_nocache(unsigned long vaddr, int size)
                 printk("Size 0x%x is too small\n", size);
                 BUG();
         }
-        if (vaddr & (size-1)) {
+        if (vaddr & (size - 1)) {
                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
                 BUG();
         }
@@ -226,13 +228,23 @@ void srmmu_free_nocache(unsigned long vaddr, int size)
 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
                                                  unsigned long end);
 
-extern unsigned long probe_memory(void);        /* in fault.c */
+/* Return how much physical memory we have.  */
+static unsigned long __init probe_memory(void)
+{
+        unsigned long total = 0;
+        int i;
+
+        for (i = 0; sp_banks[i].num_bytes; i++)
+                total += sp_banks[i].num_bytes;
+
+        return total;
+}
 
 /*
  * Reserve nocache dynamically proportionally to the amount of
  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
  */
-static void srmmu_nocache_calcsize(void)
+static void __init srmmu_nocache_calcsize(void)
 {
         unsigned long sysmemavail = probe_memory() / 1024;
         int srmmu_nocache_npages;
@@ -271,7 +283,7 @@ static void __init srmmu_nocache_init(void)
         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 
-        srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
+        srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
         init_mm.pgd = srmmu_swapper_pg_dir;
 
@@ -304,7 +316,7 @@ pgd_t *get_pgd_fast(void)
 {
         pgd_t *pgd = NULL;
 
-        pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
+        pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
         if (pgd) {
                 pgd_t *init = pgd_offset_k(0);
                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
@@ -330,7 +342,7 @@ pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
 
         if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0)
                 return NULL;
-        page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
+        page = pfn_to_page(__nocache_pa(pte) >> PAGE_SHIFT);
         pgtable_page_ctor(page);
         return page;
 }
@@ -344,18 +356,50 @@ void pte_free(struct mm_struct *mm, pgtable_t pte)
         if (p == 0)
                 BUG();
         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
-        p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
-        srmmu_free_nocache(p, PTE_SIZE);
+
+        /* free non cached virtual address*/
+        srmmu_free_nocache(__nocache_va(p), PTE_SIZE);
 }
 
-/*
- */
+/* context handling - a dynamically sized pool is used */
+#define NO_CONTEXT      -1
+
+struct ctx_list {
+        struct ctx_list *next;
+        struct ctx_list *prev;
+        unsigned int ctx_number;
+        struct mm_struct *ctx_mm;
+};
+
+static struct ctx_list *ctx_list_pool;
+static struct ctx_list ctx_free;
+static struct ctx_list ctx_used;
+
+/* At boot time we determine the number of contexts */
+static int num_contexts;
+
+static inline void remove_from_ctx_list(struct ctx_list *entry)
+{
+        entry->next->prev = entry->prev;
+        entry->prev->next = entry->next;
+}
+
+static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
+{
+        entry->next = head;
+        (entry->prev = head->prev)->next = entry;
+        head->prev = entry;
+}
+#define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
+#define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
+
+
 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 {
         struct ctx_list *ctxp;
 
         ctxp = ctx_free.next;
-        if(ctxp != &ctx_free) {
+        if (ctxp != &ctx_free) {
                 remove_from_ctx_list(ctxp);
                 add_to_used_ctxlist(ctxp);
                 mm->context = ctxp->ctx_number;
@@ -363,9 +407,9 @@ static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
                 return;
         }
         ctxp = ctx_used.next;
-        if(ctxp->ctx_mm == old_mm)
+        if (ctxp->ctx_mm == old_mm)
                 ctxp = ctxp->next;
-        if(ctxp == &ctx_used)
+        if (ctxp == &ctx_used)
                 panic("out of mmu contexts");
         flush_cache_mm(ctxp->ctx_mm);
         flush_tlb_mm(ctxp->ctx_mm);
@@ -385,11 +429,31 @@ static inline void free_context(int context)
         add_to_free_ctxlist(ctx_old);
 }
 
+static void __init sparc_context_init(int numctx)
+{
+        int ctx;
+        unsigned long size;
+
+        size = numctx * sizeof(struct ctx_list);
+        ctx_list_pool = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL);
+
+        for (ctx = 0; ctx < numctx; ctx++) {
+                struct ctx_list *clist;
+
+                clist = (ctx_list_pool + ctx);
+                clist->ctx_number = ctx;
+                clist->ctx_mm = NULL;
+        }
+        ctx_free.next = ctx_free.prev = &ctx_free;
+        ctx_used.next = ctx_used.prev = &ctx_used;
+        for (ctx = 0; ctx < numctx; ctx++)
+                add_to_free_ctxlist(ctx_list_pool + ctx);
+}
 
 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
                struct task_struct *tsk)
 {
-        if(mm->context == NO_CONTEXT) {
+        if (mm->context == NO_CONTEXT) {
                 spin_lock(&srmmu_context_spinlock);
                 alloc_context(old_mm, mm);
                 spin_unlock(&srmmu_context_spinlock);
@@ -407,7 +471,7 @@ void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 
 /* Low level IO area allocation on the SRMMU. */
 static inline void srmmu_mapioaddr(unsigned long physaddr,
-    unsigned long virt_addr, int bus_type)
+                                   unsigned long virt_addr, int bus_type)
 {
         pgd_t *pgdp;
         pmd_t *pmdp;
@@ -420,8 +484,7 @@ static inline void srmmu_mapioaddr(unsigned long physaddr,
         ptep = pte_offset_kernel(pmdp, virt_addr);
         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 
-        /*
-         * I need to test whether this is consistent over all
+        /* I need to test whether this is consistent over all
          * sun4m's.  The bus_type represents the upper 4 bits of
          * 36-bit physical address on the I/O space lines...
          */
@@ -591,10 +654,10 @@ static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
         pmd_t *pmdp;
         pte_t *ptep;
 
-        while(start < end) {
+        while (start < end) {
                 pgdp = pgd_offset_k(start);
                 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
-                        pmdp = (pmd_t *) __srmmu_get_nocache(
+                        pmdp = __srmmu_get_nocache(
                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
                         if (pmdp == NULL)
                                 early_pgtable_allocfail("pmd");
@@ -602,8 +665,8 @@ static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
                         pgd_set(__nocache_fix(pgdp), pmdp);
                 }
                 pmdp = pmd_offset(__nocache_fix(pgdp), start);
-                if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
-                        ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
+                if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
+                        ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
                         if (ptep == NULL)
                                 early_pgtable_allocfail("pte");
                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
@@ -622,18 +685,18 @@ static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
         pmd_t *pmdp;
         pte_t *ptep;
 
-        while(start < end) {
+        while (start < end) {
                 pgdp = pgd_offset_k(start);
                 if (pgd_none(*pgdp)) {
-                        pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
+                        pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
                         if (pmdp == NULL)
                                 early_pgtable_allocfail("pmd");
                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
                         pgd_set(pgdp, pmdp);
                 }
                 pmdp = pmd_offset(pgdp, start);
-                if(srmmu_pmd_none(*pmdp)) {
-                        ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
+                if (srmmu_pmd_none(*pmdp)) {
+                        ptep = __srmmu_get_nocache(PTE_SIZE,
                                                              PTE_SIZE);
                         if (ptep == NULL)
                                 early_pgtable_allocfail("pte");
@@ -671,72 +734,76 @@ static inline unsigned long srmmu_probe(unsigned long vaddr)
 static void __init srmmu_inherit_prom_mappings(unsigned long start,
                                                unsigned long end)
 {
+        unsigned long probed;
+        unsigned long addr;
         pgd_t *pgdp;
         pmd_t *pmdp;
         pte_t *ptep;
-        int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
-        unsigned long prompte;
+        int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
 
-        while(start <= end) {
+        while (start <= end) {
                 if (start == 0)
                         break; /* probably wrap around */
-                if(start == 0xfef00000)
+                if (start == 0xfef00000)
                         start = KADB_DEBUGGER_BEGVM;
-                if(!(prompte = srmmu_probe(start))) {
+                probed = srmmu_probe(start);
+                if (!probed) {
+                        /* continue probing until we find an entry */
                         start += PAGE_SIZE;
                         continue;
                 }
-    
+
                 /* A red snapper, see what it really is. */
                 what = 0;
-    
-                if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
-                        if(srmmu_probe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
+                addr = start - PAGE_SIZE;
+
+                if (!(start & ~(SRMMU_REAL_PMD_MASK))) {
+                        if (srmmu_probe(addr + SRMMU_REAL_PMD_SIZE) == probed)
                                 what = 1;
                 }
-    
-                if(!(start & ~(SRMMU_PGDIR_MASK))) {
-                        if(srmmu_probe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
-                           prompte)
+
+                if (!(start & ~(SRMMU_PGDIR_MASK))) {
+                        if (srmmu_probe(addr + SRMMU_PGDIR_SIZE) == probed)
                                 what = 2;
                 }
-    
+
                 pgdp = pgd_offset_k(start);
-                if(what == 2) {
-                        *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
+                if (what == 2) {
+                        *(pgd_t *)__nocache_fix(pgdp) = __pgd(probed);
                         start += SRMMU_PGDIR_SIZE;
                         continue;
                 }
                 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
-                        pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
+                        pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
+                                                   SRMMU_PMD_TABLE_SIZE);
                         if (pmdp == NULL)
                                 early_pgtable_allocfail("pmd");
                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
                         pgd_set(__nocache_fix(pgdp), pmdp);
                 }
                 pmdp = pmd_offset(__nocache_fix(pgdp), start);
-                if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
-                        ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
-                                                             PTE_SIZE);
+                if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
+                        ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
                         if (ptep == NULL)
                                 early_pgtable_allocfail("pte");
                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
                         pmd_set(__nocache_fix(pmdp), ptep);
                 }
-                if(what == 1) {
-                        /*
-                         * We bend the rule where all 16 PTPs in a pmd_t point
+                if (what == 1) {
+                        /* We bend the rule where all 16 PTPs in a pmd_t point
                          * inside the same PTE page, and we leak a perfectly
                          * good hardware PTE piece. Alternatives seem worse.
                          */
                         unsigned int x; /* Index of HW PMD in soft cluster */
+                        unsigned long *val;
                         x = (start >> PMD_SHIFT) & 15;
-                        *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
+                        val = &pmdp->pmdv[x];
+                        *(unsigned long *)__nocache_fix(val) = probed;
                         start += SRMMU_REAL_PMD_SIZE;
                         continue;
                 }
                 ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
-                *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
+                *(pte_t *)__nocache_fix(ptep) = __pte(probed);
                 start += PAGE_SIZE;
         }
 }
@@ -765,18 +832,18 @@ static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
 
         if (vstart < min_vaddr || vstart >= max_vaddr)
                 return vstart;
-        
+
         if (vend > max_vaddr || vend < min_vaddr)
                 vend = max_vaddr;
 
-        while(vstart < vend) {
+        while (vstart < vend) {
                 do_large_mapping(vstart, pstart);
                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
         }
         return vstart;
 }
 
-static inline void map_kernel(void)
+static void __init map_kernel(void)
 {
         int i;
 
@@ -789,9 +856,6 @@ static inline void map_kernel(void)
         }
 }
 
-/* Paging initialization on the Sparc Reference MMU. */
-extern void sparc_context_init(int);
-
 void (*poke_srmmu)(void) __cpuinitdata = NULL;
 
 extern unsigned long bootmem_init(unsigned long *pages_avail);
@@ -806,6 +870,7 @@ void __init srmmu_paging_init(void)
         pte_t *pte;
         unsigned long pages_avail;
 
+        init_mm.context = (unsigned long) NO_CONTEXT;
         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
 
         if (sparc_cpu_model == sun4d)
@@ -814,9 +879,9 @@ void __init srmmu_paging_init(void)
                 /* Find the number of contexts on the srmmu. */
                 cpunode = prom_getchild(prom_root_node);
                 num_contexts = 0;
-                while(cpunode != 0) {
+                while (cpunode != 0) {
                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
-                        if(!strcmp(node_str, "cpu")) {
+                        if (!strcmp(node_str, "cpu")) {
                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
                                 break;
                         }
@@ -824,7 +889,7 @@ void __init srmmu_paging_init(void)
                 }
         }
 
-        if(!num_contexts) {
+        if (!num_contexts) {
                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
                 prom_halt();
         }
@@ -834,14 +899,14 @@ void __init srmmu_paging_init(void)
 
         srmmu_nocache_calcsize();
         srmmu_nocache_init();
-        srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
+        srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));
         map_kernel();
 
         /* ctx table has to be physically aligned to its size */
-        srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
+        srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t));
         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
 
-        for(i = 0; i < num_contexts; i++)
+        for (i = 0; i < num_contexts; i++)
                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
 
         flush_cache_all();
@@ -897,7 +962,7 @@ void __init srmmu_paging_init(void)
 
 void mmu_info(struct seq_file *m)
 {
-        seq_printf(m, 
+        seq_printf(m,
                    "MMU type\t: %s\n"
                    "contexts\t: %d\n"
                    "nocache total\t: %ld\n"
@@ -908,10 +973,16 @@ void mmu_info(struct seq_file *m)
                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 }
 
+int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+        mm->context = NO_CONTEXT;
+        return 0;
+}
+
 void destroy_context(struct mm_struct *mm)
 {
 
-        if(mm->context != NO_CONTEXT) {
+        if (mm->context != NO_CONTEXT) {
                 flush_cache_mm(mm);
                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
                 flush_tlb_mm(mm);
@@ -941,13 +1012,12 @@ static void __init init_vac_layout(void)
 #endif
 
         nd = prom_getchild(prom_root_node);
-        while((nd = prom_getsibling(nd)) != 0) {
+        while ((nd = prom_getsibling(nd)) != 0) {
                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
-                if(!strcmp(node_str, "cpu")) {
+                if (!strcmp(node_str, "cpu")) {
                         vac_line_size = prom_getint(nd, "cache-line-size");
                         if (vac_line_size == -1) {
-                                prom_printf("can't determine cache-line-size, "
-                                            "halting.\n");
+                                prom_printf("can't determine cache-line-size, halting.\n");
                                 prom_halt();
                         }
                         cache_lines = prom_getint(nd, "cache-nlines");
@@ -958,9 +1028,9 @@ static void __init init_vac_layout(void)
 
                         vac_cache_size = cache_lines * vac_line_size;
 #ifdef CONFIG_SMP
-                        if(vac_cache_size > max_size)
+                        if (vac_cache_size > max_size)
                                 max_size = vac_cache_size;
-                        if(vac_line_size < min_line_size)
+                        if (vac_line_size < min_line_size)
                                 min_line_size = vac_line_size;
                         //FIXME: cpus not contiguous!!
                         cpu++;
@@ -971,7 +1041,7 @@ static void __init init_vac_layout(void)
 #endif
                 }
         }
-        if(nd == 0) {
+        if (nd == 0) {
                 prom_printf("No CPU nodes found, halting.\n");
                 prom_halt();
         }
@@ -1082,7 +1152,7 @@ static void __init init_swift(void)
                              "=r" (swift_rev) :
                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
         srmmu_name = "Fujitsu Swift";
-        switch(swift_rev) {
+        switch (swift_rev) {
         case 0x11:
         case 0x20:
         case 0x23:
@@ -1222,10 +1292,11 @@ static void __cpuinit poke_turbosparc(void)
 
         /* Clear any crap from the cache or else... */
         turbosparc_flush_cache_all();
-        mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
+        /* Temporarily disable I & D caches */
+        mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
         srmmu_set_mmureg(mreg);
-        
+
         ccreg = turbosparc_get_ccreg();
 
 #ifdef TURBOSPARC_WRITEBACK
@@ -1248,7 +1319,7 @@ static void __cpuinit poke_turbosparc(void)
         default:
                 ccreg |= (TURBOSPARC_SCENABLE);
         }
-        turbosparc_set_ccreg (ccreg);
+        turbosparc_set_ccreg(ccreg);
 
         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
@@ -1342,7 +1413,7 @@ static void __cpuinit poke_viking(void)
                 unsigned long bpreg;
 
                 mreg &= ~(VIKING_TCENABLE);
-                if(smp_catch++) {
+                if (smp_catch++) {
                         /* Must disable mixed-cmd mode here for other cpu's. */
                         bpreg = viking_get_bpreg();
                         bpreg &= ~(VIKING_ACTION_MIX);
@@ -1411,7 +1482,7 @@ static void __init init_viking(void)
         unsigned long mreg = srmmu_get_mmureg();
 
         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
-        if(mreg & VIKING_MMODE) {
+        if (mreg & VIKING_MMODE) {
                 srmmu_name = "TI Viking";
                 viking_mxcc_present = 0;
                 msi_set_sync();
@@ -1467,8 +1538,8 @@ static void __init get_srmmu_type(void)
         }
 
         /* Second, check for HyperSparc or Cypress. */
-        if(mod_typ == 1) {
-                switch(mod_rev) {
+        if (mod_typ == 1) {
+                switch (mod_rev) {
                 case 7:
                         /* UP or MP Hypersparc */
                         init_hypersparc();
@@ -1488,9 +1559,8 @@ static void __init get_srmmu_type(void)
                 }
                 return;
         }
-        
-        /*
-         * Now Fujitsu TurboSparc. It might happen that it is
+
+        /* Now Fujitsu TurboSparc. It might happen that it is
          * in Swift emulation mode, so we will check later...
          */
         if (psr_typ == 0 && psr_vers == 5) {
@@ -1499,15 +1569,15 @@ static void __init get_srmmu_type(void)
         }
 
         /* Next check for Fujitsu Swift. */
-        if(psr_typ == 0 && psr_vers == 4) {
+        if (psr_typ == 0 && psr_vers == 4) {
                 phandle cpunode;
                 char node_str[128];
 
                 /* Look if it is not a TurboSparc emulating Swift... */
                 cpunode = prom_getchild(prom_root_node);
-                while((cpunode = prom_getsibling(cpunode)) != 0) {
+                while ((cpunode = prom_getsibling(cpunode)) != 0) {
                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
-                        if(!strcmp(node_str, "cpu")) {
+                        if (!strcmp(node_str, "cpu")) {
                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
                                         init_turbosparc();
@@ -1516,13 +1586,13 @@ static void __init get_srmmu_type(void)
                                 break;
                         }
                 }
-                
+
                 init_swift();
                 return;
         }
 
         /* Now the Viking family of srmmu. */
-        if(psr_typ == 4 &&
+        if (psr_typ == 4 &&
            ((psr_vers == 0) ||
             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
                 init_viking();
@@ -1530,7 +1600,7 @@ static void __init get_srmmu_type(void)
         }
 
         /* Finally the Tsunami. */
-        if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
+        if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
                 init_tsunami();
                 return;
         }
diff --git a/arch/sparc/net/bpf_jit_comp.c b/arch/sparc/net/bpf_jit_comp.c
index 1a69244e785..e9073e9501b 100644
--- a/arch/sparc/net/bpf_jit_comp.c
+++ b/arch/sparc/net/bpf_jit_comp.c
@@ -96,6 +96,7 @@ static void bpf_flush_icache(void *start_, void *end_)
 #define AND             F3(2, 0x01)
 #define ANDCC           F3(2, 0x11)
 #define OR              F3(2, 0x02)
+#define XOR             F3(2, 0x03)
 #define SUB             F3(2, 0x04)
 #define SUBCC           F3(2, 0x14)
 #define MUL             F3(2, 0x0a)     /* umul */
@@ -462,6 +463,9 @@ void bpf_jit_compile(struct sk_filter *fp)
                         case BPF_S_ALU_OR_K:    /* A |= K */
                                 emit_alu_K(OR, K);
                                 break;
+                        case BPF_S_ANC_ALU_XOR_X: /* A ^= X; */
+                                emit_alu_X(XOR);
+                                break;
                         case BPF_S_ALU_LSH_X:   /* A <<= X */
                                 emit_alu_X(SLL);
                                 break;
diff --git a/arch/sparc/prom/init_32.c b/arch/sparc/prom/init_32.c
index 26c64cea3c9..9ac30c2b7db 100644
--- a/arch/sparc/prom/init_32.c
+++ b/arch/sparc/prom/init_32.c
@@ -27,13 +27,10 @@ EXPORT_SYMBOL(prom_root_node);
 struct linux_nodeops *prom_nodeops;
 
 /* You must call prom_init() before you attempt to use any of the
- * routines in the prom library.  It returns 0 on success, 1 on
- * failure.  It gets passed the pointer to the PROM vector.
+ * routines in the prom library.
+ * It gets passed the pointer to the PROM vector.
  */
 
-extern void prom_meminit(void);
-extern void prom_ranges_init(void);
-
 void __init prom_init(struct linux_romvec *rp)
 {
         romvec = rp;
diff --git a/arch/sparc/prom/init_64.c b/arch/sparc/prom/init_64.c
index 5016c5e2057..d95db755828 100644
--- a/arch/sparc/prom/init_64.c
+++ b/arch/sparc/prom/init_64.c
@@ -22,8 +22,8 @@ int prom_stdout;
 phandle prom_chosen_node;
 
 /* You must call prom_init() before you attempt to use any of the
- * routines in the prom library.  It returns 0 on success, 1 on
- * failure.  It gets passed the pointer to the PROM vector.
+ * routines in the prom library.
+ * It gets passed the pointer to the PROM vector.
  */
 
 extern void prom_cif_init(void *, void *);
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index fe128816c44..932e4430f7f 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -3,6 +3,8 @@
 
 config TILE
         def_bool y
+        select HAVE_DMA_ATTRS
+        select HAVE_DMA_API_DEBUG
         select HAVE_KVM if !TILEGX
         select GENERIC_FIND_FIRST_BIT
         select USE_GENERIC_SMP_HELPERS
@@ -79,6 +81,9 @@ config ARCH_DMA_ADDR_T_64BIT
 config NEED_DMA_MAP_STATE
         def_bool y
 
+config ARCH_HAS_DMA_SET_COHERENT_MASK
+        bool
+
 config LOCKDEP_SUPPORT
         def_bool y
 
@@ -212,6 +217,22 @@ config HIGHMEM
 
           If unsure, say "true".
 
+config ZONE_DMA
+        def_bool y
+
+config IOMMU_HELPER
+        bool
+
+config NEED_SG_DMA_LENGTH
+        bool
+
+config SWIOTLB
+        bool
+        default TILEGX
+        select IOMMU_HELPER
+        select NEED_SG_DMA_LENGTH
+        select ARCH_HAS_DMA_SET_COHERENT_MASK
+
 # We do not currently support disabling NUMA.
 config NUMA
         bool # "NUMA Memory Allocation and Scheduler Support"
@@ -345,6 +366,8 @@ config KERNEL_PL
           kernel will be built to run at.  Generally you should use
           the default value here.
 
+source "arch/tile/gxio/Kconfig"
+
 endmenu  # Tilera-specific configuration
 
 menu "Bus options"
@@ -354,6 +377,9 @@ config PCI
         default y
         select PCI_DOMAINS
         select GENERIC_PCI_IOMAP
+        select TILE_GXIO_TRIO if TILEGX
+        select ARCH_SUPPORTS_MSI if TILEGX
+        select PCI_MSI if TILEGX
         ---help---
           Enable PCI root complex support, so PCIe endpoint devices can
           be attached to the Tile chip.  Many, but not all, PCI devices
@@ -370,6 +396,22 @@ config NO_IOPORT
 
 source "drivers/pci/Kconfig"
 
+config TILE_USB
+        tristate "Tilera USB host adapter support"
+        default y
+        depends on USB
+        depends on TILEGX
+        select TILE_GXIO_USB_HOST
+        ---help---
+          Provides USB host adapter support for the built-in EHCI and OHCI
+          interfaces on TILE-Gx chips.
+
+# USB OHCI needs the bounce pool since tilegx will often have more
+# than 4GB of memory, but we don't currently use the IOTLB to present
+# a 32-bit address to OHCI.  So we need to use a bounce pool instead.
+config NEED_BOUNCE_POOL
+        def_bool USB_OHCI_HCD
+
 config HOTPLUG
         bool "Support for hot-pluggable devices"
         ---help---
diff --git a/arch/tile/Makefile b/arch/tile/Makefile
index e20b0a0b64a..55640cf9259 100644
--- a/arch/tile/Makefile
+++ b/arch/tile/Makefile
@@ -59,6 +59,8 @@ libs-y		+= $(LIBGCC_PATH)
 # See arch/tile/Kbuild for content of core part of the kernel
 core-y          += arch/tile/
 
+core-$(CONFIG_TILE_GXIO) += arch/tile/gxio/
+
 ifdef TILERA_ROOT
 INSTALL_PATH ?= $(TILERA_ROOT)/tile/boot
 endif
diff --git a/arch/tile/configs/tilegx_defconfig b/arch/tile/configs/tilegx_defconfig
index b8d99aca543..0270620a169 100644
--- a/arch/tile/configs/tilegx_defconfig
+++ b/arch/tile/configs/tilegx_defconfig
@@ -18,8 +18,8 @@ CONFIG_CGROUP_DEVICE=y
 CONFIG_CPUSETS=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_MEM_RES_CTLR=y
-CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
+CONFIG_CGROUP_MEMCG=y
+CONFIG_CGROUP_MEMCG_SWAP=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_CGROUP=y
diff --git a/arch/tile/configs/tilepro_defconfig b/arch/tile/configs/tilepro_defconfig
index 2b1fd31894f..c11de27a9bc 100644
--- a/arch/tile/configs/tilepro_defconfig
+++ b/arch/tile/configs/tilepro_defconfig
@@ -17,8 +17,8 @@ CONFIG_CGROUP_DEVICE=y
 CONFIG_CPUSETS=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_MEM_RES_CTLR=y
-CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
+CONFIG_CGROUP_MEMCG=y
+CONFIG_CGROUP_MEMCG_SWAP=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_CGROUP=y
diff --git a/arch/tile/gxio/Kconfig b/arch/tile/gxio/Kconfig
new file mode 100644
index 00000000000..d221f8d6de8
--- /dev/null
+++ b/arch/tile/gxio/Kconfig
@@ -0,0 +1,28 @@
+# Support direct access to TILE-Gx hardware from user space, via the
+# gxio library, or from kernel space, via kernel IORPC support.
+config TILE_GXIO
+        bool
+        depends on TILEGX
+
+# Support direct access to the common I/O DMA facility within the
+# TILE-Gx mPIPE and Trio hardware from kernel space.
+config TILE_GXIO_DMA
+        bool
+        select TILE_GXIO
+
+# Support direct access to the TILE-Gx mPIPE hardware from kernel space.
+config TILE_GXIO_MPIPE
+        bool
+        select TILE_GXIO
+        select TILE_GXIO_DMA
+
+# Support direct access to the TILE-Gx TRIO hardware from kernel space.
+config TILE_GXIO_TRIO
+        bool
+        select TILE_GXIO
+        select TILE_GXIO_DMA
+
+# Support direct access to the TILE-Gx USB hardware from kernel space.
+config TILE_GXIO_USB_HOST
+        bool
+        select TILE_GXIO
diff --git a/arch/tile/gxio/Makefile b/arch/tile/gxio/Makefile
new file mode 100644
index 00000000000..8684bcaa74e
--- /dev/null
+++ b/arch/tile/gxio/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the Tile-Gx device access support.
+#
+
+obj-$(CONFIG_TILE_GXIO) += iorpc_globals.o kiorpc.o
+obj-$(CONFIG_TILE_GXIO_DMA) += dma_queue.o
+obj-$(CONFIG_TILE_GXIO_MPIPE) += mpipe.o iorpc_mpipe.o iorpc_mpipe_info.o
+obj-$(CONFIG_TILE_GXIO_TRIO) += trio.o iorpc_trio.o
+obj-$(CONFIG_TILE_GXIO_USB_HOST) += usb_host.o iorpc_usb_host.o
diff --git a/arch/tile/gxio/dma_queue.c b/arch/tile/gxio/dma_queue.c
new file mode 100644
index 00000000000..baa60357f8b
--- /dev/null
+++ b/arch/tile/gxio/dma_queue.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/io.h>
+#include <linux/atomic.h>
+#include <linux/module.h>
+#include <gxio/dma_queue.h>
+
+/* Wait for a memory read to complete. */
+#define wait_for_value(val)                             \
+  __asm__ __volatile__("move %0, %0" :: "r"(val))
+
+/* The index is in the low 16. */
+#define DMA_QUEUE_INDEX_MASK ((1 << 16) - 1)
+
+/*
+ * The hardware descriptor-ring type.
+ * This matches the types used by mpipe (MPIPE_EDMA_POST_REGION_VAL_t)
+ * and trio (TRIO_PUSH_DMA_REGION_VAL_t or TRIO_PULL_DMA_REGION_VAL_t).
+ * See those types for more documentation on the individual fields.
+ */
+typedef union {
+        struct {
+#ifndef __BIG_ENDIAN__
+                uint64_t ring_idx:16;
+                uint64_t count:16;
+                uint64_t gen:1;
+                uint64_t __reserved:31;
+#else
+                uint64_t __reserved:31;
+                uint64_t gen:1;
+                uint64_t count:16;
+                uint64_t ring_idx:16;
+#endif
+        };
+        uint64_t word;
+} __gxio_ring_t;
+
+void __gxio_dma_queue_init(__gxio_dma_queue_t *dma_queue,
+                           void *post_region_addr, unsigned int num_entries)
+{
+        /*
+         * Limit 65536 entry rings to 65535 credits because we only have a
+         * 16 bit completion counter.
+         */
+        int64_t credits = (num_entries < 65536) ? num_entries : 65535;
+
+        memset(dma_queue, 0, sizeof(*dma_queue));
+
+        dma_queue->post_region_addr = post_region_addr;
+        dma_queue->hw_complete_count = 0;
+        dma_queue->credits_and_next_index = credits << DMA_QUEUE_CREDIT_SHIFT;
+}
+
+EXPORT_SYMBOL_GPL(__gxio_dma_queue_init);
+
+void __gxio_dma_queue_update_credits(__gxio_dma_queue_t *dma_queue)
+{
+        __gxio_ring_t val;
+        uint64_t count;
+        uint64_t delta;
+        uint64_t new_count;
+
+        /*
+         * Read the 64-bit completion count without touching the cache, so
+         * we later avoid having to evict any sharers of this cache line
+         * when we update it below.
+         */
+        uint64_t orig_hw_complete_count =
+                cmpxchg(&dma_queue->hw_complete_count,
+                        -1, -1);
+
+        /* Make sure the load completes before we access the hardware. */
+        wait_for_value(orig_hw_complete_count);
+
+        /* Read the 16-bit count of how many packets it has completed. */
+        val.word = __gxio_mmio_read(dma_queue->post_region_addr);
+        count = val.count;
+
+        /*
+         * Calculate the number of completions since we last updated the
+         * 64-bit counter.  It's safe to ignore the high bits because the
+         * maximum credit value is 65535.
+         */
+        delta = (count - orig_hw_complete_count) & 0xffff;
+        if (delta == 0)
+                return;
+
+        /*
+         * Try to write back the count, advanced by delta.  If we race with
+         * another thread, this might fail, in which case we return
+         * immediately on the assumption that some credits are (or at least
+         * were) available.
+         */
+        new_count = orig_hw_complete_count + delta;
+        if (cmpxchg(&dma_queue->hw_complete_count,
+                    orig_hw_complete_count,
+                    new_count) != orig_hw_complete_count)
+                return;
+
+        /*
+         * We succeeded in advancing the completion count; add back the
+         * corresponding number of egress credits.
+         */
+        __insn_fetchadd(&dma_queue->credits_and_next_index,
+                        (delta << DMA_QUEUE_CREDIT_SHIFT));
+}
+
+EXPORT_SYMBOL_GPL(__gxio_dma_queue_update_credits);
+
+/*
+ * A separate 'blocked' method for put() so that backtraces and
+ * profiles will clearly indicate that we're wasting time spinning on
+ * egress availability rather than actually posting commands.
+ */
+int64_t __gxio_dma_queue_wait_for_credits(__gxio_dma_queue_t *dma_queue,
+                                          int64_t modifier)
+{
+        int backoff = 16;
+        int64_t old;
+
+        do {
+                int i;
+                /* Back off to avoid spamming memory networks. */
+                for (i = backoff; i > 0; i--)
+                        __insn_mfspr(SPR_PASS);
+
+                /* Check credits again. */
+                __gxio_dma_queue_update_credits(dma_queue);
+                old = __insn_fetchaddgez(&dma_queue->credits_and_next_index,
+                                         modifier);
+
+                /* Calculate bounded exponential backoff for next iteration. */
+                if (backoff < 256)
+                        backoff *= 2;
+        } while (old + modifier < 0);
+
+        return old;
+}
+
+EXPORT_SYMBOL_GPL(__gxio_dma_queue_wait_for_credits);
+
+int64_t __gxio_dma_queue_reserve_aux(__gxio_dma_queue_t *dma_queue,
+                                     unsigned int num, int wait)
+{
+        return __gxio_dma_queue_reserve(dma_queue, num, wait != 0, true);
+}
+
+EXPORT_SYMBOL_GPL(__gxio_dma_queue_reserve_aux);
+
+int __gxio_dma_queue_is_complete(__gxio_dma_queue_t *dma_queue,
+                                 int64_t completion_slot, int update)
+{
+        if (update) {
+                if (ACCESS_ONCE(dma_queue->hw_complete_count) >
+                    completion_slot)
+                        return 1;
+
+                __gxio_dma_queue_update_credits(dma_queue);
+        }
+
+        return ACCESS_ONCE(dma_queue->hw_complete_count) > completion_slot;
+}
+
+EXPORT_SYMBOL_GPL(__gxio_dma_queue_is_complete);
diff --git a/arch/tile/gxio/iorpc_globals.c b/arch/tile/gxio/iorpc_globals.c
new file mode 100644
index 00000000000..e178e90805a
--- /dev/null
+++ b/arch/tile/gxio/iorpc_globals.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* This file is machine-generated; DO NOT EDIT! */
+#include "gxio/iorpc_globals.h"
+
+struct arm_pollfd_param {
+        union iorpc_pollfd pollfd;
+};
+
+int __iorpc_arm_pollfd(int fd, int pollfd_cookie)
+{
+        struct arm_pollfd_param temp;
+        struct arm_pollfd_param *params = &temp;
+
+        params->pollfd.kernel.cookie = pollfd_cookie;
+
+        return hv_dev_pwrite(fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                             IORPC_OP_ARM_POLLFD);
+}
+
+EXPORT_SYMBOL(__iorpc_arm_pollfd);
+
+struct close_pollfd_param {
+        union iorpc_pollfd pollfd;
+};
+
+int __iorpc_close_pollfd(int fd, int pollfd_cookie)
+{
+        struct close_pollfd_param temp;
+        struct close_pollfd_param *params = &temp;
+
+        params->pollfd.kernel.cookie = pollfd_cookie;
+
+        return hv_dev_pwrite(fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                             IORPC_OP_CLOSE_POLLFD);
+}
+
+EXPORT_SYMBOL(__iorpc_close_pollfd);
+
+struct get_mmio_base_param {
+        HV_PTE base;
+};
+
+int __iorpc_get_mmio_base(int fd, HV_PTE *base)
+{
+        int __result;
+        struct get_mmio_base_param temp;
+        struct get_mmio_base_param *params = &temp;
+
+        __result =
+            hv_dev_pread(fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                         IORPC_OP_GET_MMIO_BASE);
+        *base = params->base;
+
+        return __result;
+}
+
+EXPORT_SYMBOL(__iorpc_get_mmio_base);
+
+struct check_mmio_offset_param {
+        unsigned long offset;
+        unsigned long size;
+};
+
+int __iorpc_check_mmio_offset(int fd, unsigned long offset, unsigned long size)
+{
+        struct check_mmio_offset_param temp;
+        struct check_mmio_offset_param *params = &temp;
+
+        params->offset = offset;
+        params->size = size;
+
+        return hv_dev_pwrite(fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                             IORPC_OP_CHECK_MMIO_OFFSET);
+}
+
+EXPORT_SYMBOL(__iorpc_check_mmio_offset);
diff --git a/arch/tile/gxio/iorpc_mpipe.c b/arch/tile/gxio/iorpc_mpipe.c
new file mode 100644
index 00000000000..31b87bf8c02
--- /dev/null
+++ b/arch/tile/gxio/iorpc_mpipe.c
@@ -0,0 +1,529 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* This file is machine-generated; DO NOT EDIT! */
+#include "gxio/iorpc_mpipe.h"
+
+struct alloc_buffer_stacks_param {
+        unsigned int count;
+        unsigned int first;
+        unsigned int flags;
+};
+
+int gxio_mpipe_alloc_buffer_stacks(gxio_mpipe_context_t * context,
+                                   unsigned int count, unsigned int first,
+                                   unsigned int flags)
+{
+        struct alloc_buffer_stacks_param temp;
+        struct alloc_buffer_stacks_param *params = &temp;
+
+        params->count = count;
+        params->first = first;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_MPIPE_OP_ALLOC_BUFFER_STACKS);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_alloc_buffer_stacks);
+
+struct init_buffer_stack_aux_param {
+        union iorpc_mem_buffer buffer;
+        unsigned int stack;
+        unsigned int buffer_size_enum;
+};
+
+int gxio_mpipe_init_buffer_stack_aux(gxio_mpipe_context_t * context,
+                                     void *mem_va, size_t mem_size,
+                                     unsigned int mem_flags, unsigned int stack,
+                                     unsigned int buffer_size_enum)
+{
+        int __result;
+        unsigned long long __cpa;
+        pte_t __pte;
+        struct init_buffer_stack_aux_param temp;
+        struct init_buffer_stack_aux_param *params = &temp;
+
+        __result = va_to_cpa_and_pte(mem_va, &__cpa, &__pte);
+        if (__result != 0)
+                return __result;
+        params->buffer.kernel.cpa = __cpa;
+        params->buffer.kernel.size = mem_size;
+        params->buffer.kernel.pte = __pte;
+        params->buffer.kernel.flags = mem_flags;
+        params->stack = stack;
+        params->buffer_size_enum = buffer_size_enum;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_MPIPE_OP_INIT_BUFFER_STACK_AUX);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_init_buffer_stack_aux);
+
+
+struct alloc_notif_rings_param {
+        unsigned int count;
+        unsigned int first;
+        unsigned int flags;
+};
+
+int gxio_mpipe_alloc_notif_rings(gxio_mpipe_context_t * context,
+                                 unsigned int count, unsigned int first,
+                                 unsigned int flags)
+{
+        struct alloc_notif_rings_param temp;
+        struct alloc_notif_rings_param *params = &temp;
+
+        params->count = count;
+        params->first = first;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_ALLOC_NOTIF_RINGS);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_alloc_notif_rings);
+
+struct init_notif_ring_aux_param {
+        union iorpc_mem_buffer buffer;
+        unsigned int ring;
+};
+
+int gxio_mpipe_init_notif_ring_aux(gxio_mpipe_context_t * context, void *mem_va,
+                                   size_t mem_size, unsigned int mem_flags,
+                                   unsigned int ring)
+{
+        int __result;
+        unsigned long long __cpa;
+        pte_t __pte;
+        struct init_notif_ring_aux_param temp;
+        struct init_notif_ring_aux_param *params = &temp;
+
+        __result = va_to_cpa_and_pte(mem_va, &__cpa, &__pte);
+        if (__result != 0)
+                return __result;
+        params->buffer.kernel.cpa = __cpa;
+        params->buffer.kernel.size = mem_size;
+        params->buffer.kernel.pte = __pte;
+        params->buffer.kernel.flags = mem_flags;
+        params->ring = ring;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_MPIPE_OP_INIT_NOTIF_RING_AUX);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_init_notif_ring_aux);
+
+struct request_notif_ring_interrupt_param {
+        union iorpc_interrupt interrupt;
+        unsigned int ring;
+};
+
+int gxio_mpipe_request_notif_ring_interrupt(gxio_mpipe_context_t * context,
+                                            int inter_x, int inter_y,
+                                            int inter_ipi, int inter_event,
+                                            unsigned int ring)
+{
+        struct request_notif_ring_interrupt_param temp;
+        struct request_notif_ring_interrupt_param *params = &temp;
+
+        params->interrupt.kernel.x = inter_x;
+        params->interrupt.kernel.y = inter_y;
+        params->interrupt.kernel.ipi = inter_ipi;
+        params->interrupt.kernel.event = inter_event;
+        params->ring = ring;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_MPIPE_OP_REQUEST_NOTIF_RING_INTERRUPT);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_request_notif_ring_interrupt);
+
+struct enable_notif_ring_interrupt_param {
+        unsigned int ring;
+};
+
+int gxio_mpipe_enable_notif_ring_interrupt(gxio_mpipe_context_t * context,
+                                           unsigned int ring)
+{
+        struct enable_notif_ring_interrupt_param temp;
+        struct enable_notif_ring_interrupt_param *params = &temp;
+
+        params->ring = ring;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_MPIPE_OP_ENABLE_NOTIF_RING_INTERRUPT);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_enable_notif_ring_interrupt);
+
+struct alloc_notif_groups_param {
+        unsigned int count;
+        unsigned int first;
+        unsigned int flags;
+};
+
+int gxio_mpipe_alloc_notif_groups(gxio_mpipe_context_t * context,
+                                  unsigned int count, unsigned int first,
+                                  unsigned int flags)
+{
+        struct alloc_notif_groups_param temp;
+        struct alloc_notif_groups_param *params = &temp;
+
+        params->count = count;
+        params->first = first;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_ALLOC_NOTIF_GROUPS);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_alloc_notif_groups);
+
+struct init_notif_group_param {
+        unsigned int group;
+        gxio_mpipe_notif_group_bits_t bits;
+};
+
+int gxio_mpipe_init_notif_group(gxio_mpipe_context_t * context,
+                                unsigned int group,
+                                gxio_mpipe_notif_group_bits_t bits)
+{
+        struct init_notif_group_param temp;
+        struct init_notif_group_param *params = &temp;
+
+        params->group = group;
+        params->bits = bits;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_INIT_NOTIF_GROUP);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_init_notif_group);
+
+struct alloc_buckets_param {
+        unsigned int count;
+        unsigned int first;
+        unsigned int flags;
+};
+
+int gxio_mpipe_alloc_buckets(gxio_mpipe_context_t * context, unsigned int count,
+                             unsigned int first, unsigned int flags)
+{
+        struct alloc_buckets_param temp;
+        struct alloc_buckets_param *params = &temp;
+
+        params->count = count;
+        params->first = first;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_ALLOC_BUCKETS);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_alloc_buckets);
+
+struct init_bucket_param {
+        unsigned int bucket;
+        MPIPE_LBL_INIT_DAT_BSTS_TBL_t bucket_info;
+};
+
+int gxio_mpipe_init_bucket(gxio_mpipe_context_t * context, unsigned int bucket,
+                           MPIPE_LBL_INIT_DAT_BSTS_TBL_t bucket_info)
+{
+        struct init_bucket_param temp;
+        struct init_bucket_param *params = &temp;
+
+        params->bucket = bucket;
+        params->bucket_info = bucket_info;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_INIT_BUCKET);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_init_bucket);
+
+struct alloc_edma_rings_param {
+        unsigned int count;
+        unsigned int first;
+        unsigned int flags;
+};
+
+int gxio_mpipe_alloc_edma_rings(gxio_mpipe_context_t * context,
+                                unsigned int count, unsigned int first,
+                                unsigned int flags)
+{
+        struct alloc_edma_rings_param temp;
+        struct alloc_edma_rings_param *params = &temp;
+
+        params->count = count;
+        params->first = first;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_ALLOC_EDMA_RINGS);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_alloc_edma_rings);
+
+struct init_edma_ring_aux_param {
+        union iorpc_mem_buffer buffer;
+        unsigned int ring;
+        unsigned int channel;
+};
+
+int gxio_mpipe_init_edma_ring_aux(gxio_mpipe_context_t * context, void *mem_va,
+                                  size_t mem_size, unsigned int mem_flags,
+                                  unsigned int ring, unsigned int channel)
+{
+        int __result;
+        unsigned long long __cpa;
+        pte_t __pte;
+        struct init_edma_ring_aux_param temp;
+        struct init_edma_ring_aux_param *params = &temp;
+
+        __result = va_to_cpa_and_pte(mem_va, &__cpa, &__pte);
+        if (__result != 0)
+                return __result;
+        params->buffer.kernel.cpa = __cpa;
+        params->buffer.kernel.size = mem_size;
+        params->buffer.kernel.pte = __pte;
+        params->buffer.kernel.flags = mem_flags;
+        params->ring = ring;
+        params->channel = channel;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_INIT_EDMA_RING_AUX);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_init_edma_ring_aux);
+
+
+int gxio_mpipe_commit_rules(gxio_mpipe_context_t * context, const void *blob,
+                            size_t blob_size)
+{
+        const void *params = blob;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params, blob_size,
+                             GXIO_MPIPE_OP_COMMIT_RULES);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_commit_rules);
+
+struct register_client_memory_param {
+        unsigned int iotlb;
+        HV_PTE pte;
+        unsigned int flags;
+};
+
+int gxio_mpipe_register_client_memory(gxio_mpipe_context_t * context,
+                                      unsigned int iotlb, HV_PTE pte,
+                                      unsigned int flags)
+{
+        struct register_client_memory_param temp;
+        struct register_client_memory_param *params = &temp;
+
+        params->iotlb = iotlb;
+        params->pte = pte;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_MPIPE_OP_REGISTER_CLIENT_MEMORY);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_register_client_memory);
+
+struct link_open_aux_param {
+        _gxio_mpipe_link_name_t name;
+        unsigned int flags;
+};
+
+int gxio_mpipe_link_open_aux(gxio_mpipe_context_t * context,
+                             _gxio_mpipe_link_name_t name, unsigned int flags)
+{
+        struct link_open_aux_param temp;
+        struct link_open_aux_param *params = &temp;
+
+        params->name = name;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_LINK_OPEN_AUX);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_link_open_aux);
+
+struct link_close_aux_param {
+        int mac;
+};
+
+int gxio_mpipe_link_close_aux(gxio_mpipe_context_t * context, int mac)
+{
+        struct link_close_aux_param temp;
+        struct link_close_aux_param *params = &temp;
+
+        params->mac = mac;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_LINK_CLOSE_AUX);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_link_close_aux);
+
+
+struct get_timestamp_aux_param {
+        uint64_t sec;
+        uint64_t nsec;
+        uint64_t cycles;
+};
+
+int gxio_mpipe_get_timestamp_aux(gxio_mpipe_context_t * context, uint64_t * sec,
+                                 uint64_t * nsec, uint64_t * cycles)
+{
+        int __result;
+        struct get_timestamp_aux_param temp;
+        struct get_timestamp_aux_param *params = &temp;
+
+        __result =
+            hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                         GXIO_MPIPE_OP_GET_TIMESTAMP_AUX);
+        *sec = params->sec;
+        *nsec = params->nsec;
+        *cycles = params->cycles;
+
+        return __result;
+}
+
+EXPORT_SYMBOL(gxio_mpipe_get_timestamp_aux);
+
+struct set_timestamp_aux_param {
+        uint64_t sec;
+        uint64_t nsec;
+        uint64_t cycles;
+};
+
+int gxio_mpipe_set_timestamp_aux(gxio_mpipe_context_t * context, uint64_t sec,
+                                 uint64_t nsec, uint64_t cycles)
+{
+        struct set_timestamp_aux_param temp;
+        struct set_timestamp_aux_param *params = &temp;
+
+        params->sec = sec;
+        params->nsec = nsec;
+        params->cycles = cycles;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_SET_TIMESTAMP_AUX);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_set_timestamp_aux);
+
+struct adjust_timestamp_aux_param {
+        int64_t nsec;
+};
+
+int gxio_mpipe_adjust_timestamp_aux(gxio_mpipe_context_t * context,
+                                    int64_t nsec)
+{
+        struct adjust_timestamp_aux_param temp;
+        struct adjust_timestamp_aux_param *params = &temp;
+
+        params->nsec = nsec;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_MPIPE_OP_ADJUST_TIMESTAMP_AUX);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_adjust_timestamp_aux);
+
+struct arm_pollfd_param {
+        union iorpc_pollfd pollfd;
+};
+
+int gxio_mpipe_arm_pollfd(gxio_mpipe_context_t * context, int pollfd_cookie)
+{
+        struct arm_pollfd_param temp;
+        struct arm_pollfd_param *params = &temp;
+
+        params->pollfd.kernel.cookie = pollfd_cookie;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_ARM_POLLFD);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_arm_pollfd);
+
+struct close_pollfd_param {
+        union iorpc_pollfd pollfd;
+};
+
+int gxio_mpipe_close_pollfd(gxio_mpipe_context_t * context, int pollfd_cookie)
+{
+        struct close_pollfd_param temp;
+        struct close_pollfd_param *params = &temp;
+
+        params->pollfd.kernel.cookie = pollfd_cookie;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_CLOSE_POLLFD);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_close_pollfd);
+
+struct get_mmio_base_param {
+        HV_PTE base;
+};
+
+int gxio_mpipe_get_mmio_base(gxio_mpipe_context_t * context, HV_PTE *base)
+{
+        int __result;
+        struct get_mmio_base_param temp;
+        struct get_mmio_base_param *params = &temp;
+
+        __result =
+            hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                         GXIO_MPIPE_OP_GET_MMIO_BASE);
+        *base = params->base;
+
+        return __result;
+}
+
+EXPORT_SYMBOL(gxio_mpipe_get_mmio_base);
+
+struct check_mmio_offset_param {
+        unsigned long offset;
+        unsigned long size;
+};
+
+int gxio_mpipe_check_mmio_offset(gxio_mpipe_context_t * context,
+                                 unsigned long offset, unsigned long size)
+{
+        struct check_mmio_offset_param temp;
+        struct check_mmio_offset_param *params = &temp;
+
+        params->offset = offset;
+        params->size = size;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_MPIPE_OP_CHECK_MMIO_OFFSET);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_check_mmio_offset);
diff --git a/arch/tile/gxio/iorpc_mpipe_info.c b/arch/tile/gxio/iorpc_mpipe_info.c
new file mode 100644
index 00000000000..d0254aa60cb
--- /dev/null
+++ b/arch/tile/gxio/iorpc_mpipe_info.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* This file is machine-generated; DO NOT EDIT! */
+#include "gxio/iorpc_mpipe_info.h"
+
+
+struct enumerate_aux_param {
+        _gxio_mpipe_link_name_t name;
+        _gxio_mpipe_link_mac_t mac;
+};
+
+int gxio_mpipe_info_enumerate_aux(gxio_mpipe_info_context_t * context,
+                                  unsigned int idx,
+                                  _gxio_mpipe_link_name_t * name,
+                                  _gxio_mpipe_link_mac_t * mac)
+{
+        int __result;
+        struct enumerate_aux_param temp;
+        struct enumerate_aux_param *params = &temp;
+
+        __result =
+            hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                         (((uint64_t) idx << 32) |
+                          GXIO_MPIPE_INFO_OP_ENUMERATE_AUX));
+        *name = params->name;
+        *mac = params->mac;
+
+        return __result;
+}
+
+EXPORT_SYMBOL(gxio_mpipe_info_enumerate_aux);
+
+struct get_mmio_base_param {
+        HV_PTE base;
+};
+
+int gxio_mpipe_info_get_mmio_base(gxio_mpipe_info_context_t * context,
+                                  HV_PTE *base)
+{
+        int __result;
+        struct get_mmio_base_param temp;
+        struct get_mmio_base_param *params = &temp;
+
+        __result =
+            hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                         GXIO_MPIPE_INFO_OP_GET_MMIO_BASE);
+        *base = params->base;
+
+        return __result;
+}
+
+EXPORT_SYMBOL(gxio_mpipe_info_get_mmio_base);
+
+struct check_mmio_offset_param {
+        unsigned long offset;
+        unsigned long size;
+};
+
+int gxio_mpipe_info_check_mmio_offset(gxio_mpipe_info_context_t * context,
+                                      unsigned long offset, unsigned long size)
+{
+        struct check_mmio_offset_param temp;
+        struct check_mmio_offset_param *params = &temp;
+
+        params->offset = offset;
+        params->size = size;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_MPIPE_INFO_OP_CHECK_MMIO_OFFSET);
+}
+
+EXPORT_SYMBOL(gxio_mpipe_info_check_mmio_offset);
diff --git a/arch/tile/gxio/iorpc_trio.c b/arch/tile/gxio/iorpc_trio.c
new file mode 100644
index 00000000000..cef4b2209cd
--- /dev/null
+++ b/arch/tile/gxio/iorpc_trio.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* This file is machine-generated; DO NOT EDIT! */
+#include "gxio/iorpc_trio.h"
+
+struct alloc_asids_param {
+        unsigned int count;
+        unsigned int first;
+        unsigned int flags;
+};
+
+int gxio_trio_alloc_asids(gxio_trio_context_t * context, unsigned int count,
+                          unsigned int first, unsigned int flags)
+{
+        struct alloc_asids_param temp;
+        struct alloc_asids_param *params = &temp;
+
+        params->count = count;
+        params->first = first;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_TRIO_OP_ALLOC_ASIDS);
+}
+
+EXPORT_SYMBOL(gxio_trio_alloc_asids);
+
+
+struct alloc_memory_maps_param {
+        unsigned int count;
+        unsigned int first;
+        unsigned int flags;
+};
+
+int gxio_trio_alloc_memory_maps(gxio_trio_context_t * context,
+                                unsigned int count, unsigned int first,
+                                unsigned int flags)
+{
+        struct alloc_memory_maps_param temp;
+        struct alloc_memory_maps_param *params = &temp;
+
+        params->count = count;
+        params->first = first;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_TRIO_OP_ALLOC_MEMORY_MAPS);
+}
+
+EXPORT_SYMBOL(gxio_trio_alloc_memory_maps);
+
+
+struct alloc_pio_regions_param {
+        unsigned int count;
+        unsigned int first;
+        unsigned int flags;
+};
+
+int gxio_trio_alloc_pio_regions(gxio_trio_context_t * context,
+                                unsigned int count, unsigned int first,
+                                unsigned int flags)
+{
+        struct alloc_pio_regions_param temp;
+        struct alloc_pio_regions_param *params = &temp;
+
+        params->count = count;
+        params->first = first;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_TRIO_OP_ALLOC_PIO_REGIONS);
+}
+
+EXPORT_SYMBOL(gxio_trio_alloc_pio_regions);
+
+struct init_pio_region_aux_param {
+        unsigned int pio_region;
+        unsigned int mac;
+        uint32_t bus_address_hi;
+        unsigned int flags;
+};
+
+int gxio_trio_init_pio_region_aux(gxio_trio_context_t * context,
+                                  unsigned int pio_region, unsigned int mac,
+                                  uint32_t bus_address_hi, unsigned int flags)
+{
+        struct init_pio_region_aux_param temp;
+        struct init_pio_region_aux_param *params = &temp;
+
+        params->pio_region = pio_region;
+        params->mac = mac;
+        params->bus_address_hi = bus_address_hi;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_TRIO_OP_INIT_PIO_REGION_AUX);
+}
+
+EXPORT_SYMBOL(gxio_trio_init_pio_region_aux);
+
+
+struct init_memory_map_mmu_aux_param {
+        unsigned int map;
+        unsigned long va;
+        uint64_t size;
+        unsigned int asid;
+        unsigned int mac;
+        uint64_t bus_address;
+        unsigned int node;
+        unsigned int order_mode;
+};
+
+int gxio_trio_init_memory_map_mmu_aux(gxio_trio_context_t * context,
+                                      unsigned int map, unsigned long va,
+                                      uint64_t size, unsigned int asid,
+                                      unsigned int mac, uint64_t bus_address,
+                                      unsigned int node,
+                                      unsigned int order_mode)
+{
+        struct init_memory_map_mmu_aux_param temp;
+        struct init_memory_map_mmu_aux_param *params = &temp;
+
+        params->map = map;
+        params->va = va;
+        params->size = size;
+        params->asid = asid;
+        params->mac = mac;
+        params->bus_address = bus_address;
+        params->node = node;
+        params->order_mode = order_mode;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_TRIO_OP_INIT_MEMORY_MAP_MMU_AUX);
+}
+
+EXPORT_SYMBOL(gxio_trio_init_memory_map_mmu_aux);
+
+struct get_port_property_param {
+        struct pcie_trio_ports_property trio_ports;
+};
+
+int gxio_trio_get_port_property(gxio_trio_context_t * context,
+                                struct pcie_trio_ports_property *trio_ports)
+{
+        int __result;
+        struct get_port_property_param temp;
+        struct get_port_property_param *params = &temp;
+
+        __result =
+            hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                         GXIO_TRIO_OP_GET_PORT_PROPERTY);
+        *trio_ports = params->trio_ports;
+
+        return __result;
+}
+
+EXPORT_SYMBOL(gxio_trio_get_port_property);
+
+struct config_legacy_intr_param {
+        union iorpc_interrupt interrupt;
+        unsigned int mac;
+        unsigned int intx;
+};
+
+int gxio_trio_config_legacy_intr(gxio_trio_context_t * context, int inter_x,
+                                 int inter_y, int inter_ipi, int inter_event,
+                                 unsigned int mac, unsigned int intx)
+{
+        struct config_legacy_intr_param temp;
+        struct config_legacy_intr_param *params = &temp;
+
+        params->interrupt.kernel.x = inter_x;
+        params->interrupt.kernel.y = inter_y;
+        params->interrupt.kernel.ipi = inter_ipi;
+        params->interrupt.kernel.event = inter_event;
+        params->mac = mac;
+        params->intx = intx;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_TRIO_OP_CONFIG_LEGACY_INTR);
+}
+
+EXPORT_SYMBOL(gxio_trio_config_legacy_intr);
+
+struct config_msi_intr_param {
+        union iorpc_interrupt interrupt;
+        unsigned int mac;
+        unsigned int mem_map;
+        uint64_t mem_map_base;
+        uint64_t mem_map_limit;
+        unsigned int asid;
+};
+
+int gxio_trio_config_msi_intr(gxio_trio_context_t * context, int inter_x,
+                              int inter_y, int inter_ipi, int inter_event,
+                              unsigned int mac, unsigned int mem_map,
+                              uint64_t mem_map_base, uint64_t mem_map_limit,
+                              unsigned int asid)
+{
+        struct config_msi_intr_param temp;
+        struct config_msi_intr_param *params = &temp;
+
+        params->interrupt.kernel.x = inter_x;
+        params->interrupt.kernel.y = inter_y;
+        params->interrupt.kernel.ipi = inter_ipi;
+        params->interrupt.kernel.event = inter_event;
+        params->mac = mac;
+        params->mem_map = mem_map;
+        params->mem_map_base = mem_map_base;
+        params->mem_map_limit = mem_map_limit;
+        params->asid = asid;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_TRIO_OP_CONFIG_MSI_INTR);
+}
+
+EXPORT_SYMBOL(gxio_trio_config_msi_intr);
+
+
+struct set_mps_mrs_param {
+        uint16_t mps;
+        uint16_t mrs;
+        unsigned int mac;
+};
+
+int gxio_trio_set_mps_mrs(gxio_trio_context_t * context, uint16_t mps,
+                          uint16_t mrs, unsigned int mac)
+{
+        struct set_mps_mrs_param temp;
+        struct set_mps_mrs_param *params = &temp;
+
+        params->mps = mps;
+        params->mrs = mrs;
+        params->mac = mac;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_TRIO_OP_SET_MPS_MRS);
+}
+
+EXPORT_SYMBOL(gxio_trio_set_mps_mrs);
+
+struct force_rc_link_up_param {
+        unsigned int mac;
+};
+
+int gxio_trio_force_rc_link_up(gxio_trio_context_t * context, unsigned int mac)
+{
+        struct force_rc_link_up_param temp;
+        struct force_rc_link_up_param *params = &temp;
+
+        params->mac = mac;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_TRIO_OP_FORCE_RC_LINK_UP);
+}
+
+EXPORT_SYMBOL(gxio_trio_force_rc_link_up);
+
+struct force_ep_link_up_param {
+        unsigned int mac;
+};
+
+int gxio_trio_force_ep_link_up(gxio_trio_context_t * context, unsigned int mac)
+{
+        struct force_ep_link_up_param temp;
+        struct force_ep_link_up_param *params = &temp;
+
+        params->mac = mac;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_TRIO_OP_FORCE_EP_LINK_UP);
+}
+
+EXPORT_SYMBOL(gxio_trio_force_ep_link_up);
+
+struct get_mmio_base_param {
+        HV_PTE base;
+};
+
+int gxio_trio_get_mmio_base(gxio_trio_context_t * context, HV_PTE *base)
+{
+        int __result;
+        struct get_mmio_base_param temp;
+        struct get_mmio_base_param *params = &temp;
+
+        __result =
+            hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                         GXIO_TRIO_OP_GET_MMIO_BASE);
+        *base = params->base;
+
+        return __result;
+}
+
+EXPORT_SYMBOL(gxio_trio_get_mmio_base);
+
+struct check_mmio_offset_param {
+        unsigned long offset;
+        unsigned long size;
+};
+
+int gxio_trio_check_mmio_offset(gxio_trio_context_t * context,
+                                unsigned long offset, unsigned long size)
+{
+        struct check_mmio_offset_param temp;
+        struct check_mmio_offset_param *params = &temp;
+
+        params->offset = offset;
+        params->size = size;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_TRIO_OP_CHECK_MMIO_OFFSET);
+}
+
+EXPORT_SYMBOL(gxio_trio_check_mmio_offset);
diff --git a/arch/tile/gxio/iorpc_usb_host.c b/arch/tile/gxio/iorpc_usb_host.c
new file mode 100644
index 00000000000..cf3c3cc1220
--- /dev/null
+++ b/arch/tile/gxio/iorpc_usb_host.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* This file is machine-generated; DO NOT EDIT! */
+#include "gxio/iorpc_usb_host.h"
+
+struct cfg_interrupt_param {
+        union iorpc_interrupt interrupt;
+};
+
+int gxio_usb_host_cfg_interrupt(gxio_usb_host_context_t * context, int inter_x,
+                                int inter_y, int inter_ipi, int inter_event)
+{
+        struct cfg_interrupt_param temp;
+        struct cfg_interrupt_param *params = &temp;
+
+        params->interrupt.kernel.x = inter_x;
+        params->interrupt.kernel.y = inter_y;
+        params->interrupt.kernel.ipi = inter_ipi;
+        params->interrupt.kernel.event = inter_event;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params), GXIO_USB_HOST_OP_CFG_INTERRUPT);
+}
+
+EXPORT_SYMBOL(gxio_usb_host_cfg_interrupt);
+
+struct register_client_memory_param {
+        HV_PTE pte;
+        unsigned int flags;
+};
+
+int gxio_usb_host_register_client_memory(gxio_usb_host_context_t * context,
+                                         HV_PTE pte, unsigned int flags)
+{
+        struct register_client_memory_param temp;
+        struct register_client_memory_param *params = &temp;
+
+        params->pte = pte;
+        params->flags = flags;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_USB_HOST_OP_REGISTER_CLIENT_MEMORY);
+}
+
+EXPORT_SYMBOL(gxio_usb_host_register_client_memory);
+
+struct get_mmio_base_param {
+        HV_PTE base;
+};
+
+int gxio_usb_host_get_mmio_base(gxio_usb_host_context_t * context, HV_PTE *base)
+{
+        int __result;
+        struct get_mmio_base_param temp;
+        struct get_mmio_base_param *params = &temp;
+
+        __result =
+            hv_dev_pread(context->fd, 0, (HV_VirtAddr) params, sizeof(*params),
+                         GXIO_USB_HOST_OP_GET_MMIO_BASE);
+        *base = params->base;
+
+        return __result;
+}
+
+EXPORT_SYMBOL(gxio_usb_host_get_mmio_base);
+
+struct check_mmio_offset_param {
+        unsigned long offset;
+        unsigned long size;
+};
+
+int gxio_usb_host_check_mmio_offset(gxio_usb_host_context_t * context,
+                                    unsigned long offset, unsigned long size)
+{
+        struct check_mmio_offset_param temp;
+        struct check_mmio_offset_param *params = &temp;
+
+        params->offset = offset;
+        params->size = size;
+
+        return hv_dev_pwrite(context->fd, 0, (HV_VirtAddr) params,
+                             sizeof(*params),
+                             GXIO_USB_HOST_OP_CHECK_MMIO_OFFSET);
+}
+
+EXPORT_SYMBOL(gxio_usb_host_check_mmio_offset);
diff --git a/arch/tile/gxio/kiorpc.c b/arch/tile/gxio/kiorpc.c
new file mode 100644
index 00000000000..c8096aa5a3f
--- /dev/null
+++ b/arch/tile/gxio/kiorpc.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * TILE-Gx IORPC support for kernel I/O drivers.
+ */
+
+#include <linux/mmzone.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <gxio/iorpc_globals.h>
+#include <gxio/kiorpc.h>
+
+#ifdef DEBUG_IORPC
+#define TRACE(FMT, ...) pr_info(SIMPLE_MSG_LINE FMT, ## __VA_ARGS__)
+#else
+#define TRACE(...)
+#endif
+
+/* Create kernel-VA-space MMIO mapping for an on-chip IO device. */
+void __iomem *iorpc_ioremap(int hv_fd, resource_size_t offset,
+                            unsigned long size)
+{
+        pgprot_t mmio_base, prot = { 0 };
+        unsigned long pfn;
+        int err;
+
+        /* Look up the shim's lotar and base PA. */
+        err = __iorpc_get_mmio_base(hv_fd, &mmio_base);
+        if (err) {
+                TRACE("get_mmio_base() failure: %d\n", err);
+                return NULL;
+        }
+
+        /* Make sure the HV driver approves of our offset and size. */
+        err = __iorpc_check_mmio_offset(hv_fd, offset, size);
+        if (err) {
+                TRACE("check_mmio_offset() failure: %d\n", err);
+                return NULL;
+        }
+
+        /*
+         * mmio_base contains a base pfn and homing coordinates.  Turn
+         * it into an MMIO pgprot and offset pfn.
+         */
+        prot = hv_pte_set_lotar(prot, hv_pte_get_lotar(mmio_base));
+        pfn = pte_pfn(mmio_base) + PFN_DOWN(offset);
+
+        return ioremap_prot(PFN_PHYS(pfn), size, prot);
+}
+
+EXPORT_SYMBOL(iorpc_ioremap);
diff --git a/arch/tile/gxio/mpipe.c b/arch/tile/gxio/mpipe.c
new file mode 100644
index 00000000000..e71c63390ac
--- /dev/null
+++ b/arch/tile/gxio/mpipe.c
@@ -0,0 +1,545 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/*
+ * Implementation of mpipe gxio calls.
+ */
+
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <gxio/iorpc_globals.h>
+#include <gxio/iorpc_mpipe.h>
+#include <gxio/iorpc_mpipe_info.h>
+#include <gxio/kiorpc.h>
+#include <gxio/mpipe.h>
+
+/* HACK: Avoid pointless "shadow" warnings. */
+#define link link_shadow
+
+int gxio_mpipe_init(gxio_mpipe_context_t *context, unsigned int mpipe_index)
+{
+        char file[32];
+
+        int fd;
+        int i;
+
+        snprintf(file, sizeof(file), "mpipe/%d/iorpc", mpipe_index);
+        fd = hv_dev_open((HV_VirtAddr) file, 0);
+        if (fd < 0) {
+                if (fd >= GXIO_ERR_MIN && fd <= GXIO_ERR_MAX)
+                        return fd;
+                else
+                        return -ENODEV;
+        }
+
+        context->fd = fd;
+
+        /* Map in the MMIO space. */
+        context->mmio_cfg_base = (void __force *)
+                iorpc_ioremap(fd, HV_MPIPE_CONFIG_MMIO_OFFSET,
+                              HV_MPIPE_CONFIG_MMIO_SIZE);
+        if (context->mmio_cfg_base == NULL)
+                goto cfg_failed;
+
+        context->mmio_fast_base = (void __force *)
+                iorpc_ioremap(fd, HV_MPIPE_FAST_MMIO_OFFSET,
+                              HV_MPIPE_FAST_MMIO_SIZE);
+        if (context->mmio_fast_base == NULL)
+                goto fast_failed;
+
+        /* Initialize the stacks. */
+        for (i = 0; i < 8; i++)
+                context->__stacks.stacks[i] = 255;
+
+        return 0;
+
+      fast_failed:
+        iounmap((void __force __iomem *)(context->mmio_cfg_base));
+      cfg_failed:
+        hv_dev_close(context->fd);
+        return -ENODEV;
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_init);
+
+int gxio_mpipe_destroy(gxio_mpipe_context_t *context)
+{
+        iounmap((void __force __iomem *)(context->mmio_cfg_base));
+        iounmap((void __force __iomem *)(context->mmio_fast_base));
+        return hv_dev_close(context->fd);
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_destroy);
+
+static int16_t gxio_mpipe_buffer_sizes[8] =
+        { 128, 256, 512, 1024, 1664, 4096, 10368, 16384 };
+
+gxio_mpipe_buffer_size_enum_t gxio_mpipe_buffer_size_to_buffer_size_enum(size_t
+                                                                         size)
+{
+        int i;
+        for (i = 0; i < 7; i++)
+                if (size <= gxio_mpipe_buffer_sizes[i])
+                        break;
+        return i;
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_buffer_size_to_buffer_size_enum);
+
+size_t gxio_mpipe_buffer_size_enum_to_buffer_size(gxio_mpipe_buffer_size_enum_t
+                                                  buffer_size_enum)
+{
+        if (buffer_size_enum > 7)
+                buffer_size_enum = 7;
+
+        return gxio_mpipe_buffer_sizes[buffer_size_enum];
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_buffer_size_enum_to_buffer_size);
+
+size_t gxio_mpipe_calc_buffer_stack_bytes(unsigned long buffers)
+{
+        const int BUFFERS_PER_LINE = 12;
+
+        /* Count the number of cachlines. */
+        unsigned long lines =
+                (buffers + BUFFERS_PER_LINE - 1) / BUFFERS_PER_LINE;
+
+        /* Convert to bytes. */
+        return lines * CHIP_L2_LINE_SIZE();
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_calc_buffer_stack_bytes);
+
+int gxio_mpipe_init_buffer_stack(gxio_mpipe_context_t *context,
+                                 unsigned int stack,
+                                 gxio_mpipe_buffer_size_enum_t
+                                 buffer_size_enum, void *mem, size_t mem_size,
+                                 unsigned int mem_flags)
+{
+        int result;
+
+        memset(mem, 0, mem_size);
+
+        result = gxio_mpipe_init_buffer_stack_aux(context, mem, mem_size,
+                                                  mem_flags, stack,
+                                                  buffer_size_enum);
+        if (result < 0)
+                return result;
+
+        /* Save the stack. */
+        context->__stacks.stacks[buffer_size_enum] = stack;
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_init_buffer_stack);
+
+int gxio_mpipe_init_notif_ring(gxio_mpipe_context_t *context,
+                               unsigned int ring,
+                               void *mem, size_t mem_size,
+                               unsigned int mem_flags)
+{
+        return gxio_mpipe_init_notif_ring_aux(context, mem, mem_size,
+                                              mem_flags, ring);
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_init_notif_ring);
+
+int gxio_mpipe_init_notif_group_and_buckets(gxio_mpipe_context_t *context,
+                                            unsigned int group,
+                                            unsigned int ring,
+                                            unsigned int num_rings,
+                                            unsigned int bucket,
+                                            unsigned int num_buckets,
+                                            gxio_mpipe_bucket_mode_t mode)
+{
+        int i;
+        int result;
+
+        gxio_mpipe_bucket_info_t bucket_info = { {
+                                                  .group = group,
+                                                  .mode = mode,
+                                                  }
+        };
+
+        gxio_mpipe_notif_group_bits_t bits = { {0} };
+
+        for (i = 0; i < num_rings; i++)
+                gxio_mpipe_notif_group_add_ring(&bits, ring + i);
+
+        result = gxio_mpipe_init_notif_group(context, group, bits);
+        if (result != 0)
+                return result;
+
+        for (i = 0; i < num_buckets; i++) {
+                bucket_info.notifring = ring + (i % num_rings);
+
+                result = gxio_mpipe_init_bucket(context, bucket + i,
+                                                bucket_info);
+                if (result != 0)
+                        return result;
+        }
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_init_notif_group_and_buckets);
+
+int gxio_mpipe_init_edma_ring(gxio_mpipe_context_t *context,
+                              unsigned int ring, unsigned int channel,
+                              void *mem, size_t mem_size,
+                              unsigned int mem_flags)
+{
+        memset(mem, 0, mem_size);
+
+        return gxio_mpipe_init_edma_ring_aux(context, mem, mem_size, mem_flags,
+                                             ring, channel);
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_init_edma_ring);
+
+void gxio_mpipe_rules_init(gxio_mpipe_rules_t *rules,
+                           gxio_mpipe_context_t *context)
+{
+        rules->context = context;
+        memset(&rules->list, 0, sizeof(rules->list));
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_rules_init);
+
+int gxio_mpipe_rules_begin(gxio_mpipe_rules_t *rules,
+                           unsigned int bucket, unsigned int num_buckets,
+                           gxio_mpipe_rules_stacks_t *stacks)
+{
+        int i;
+        int stack = 255;
+
+        gxio_mpipe_rules_list_t *list = &rules->list;
+
+        /* Current rule. */
+        gxio_mpipe_rules_rule_t *rule =
+                (gxio_mpipe_rules_rule_t *) (list->rules + list->head);
+
+        unsigned int head = list->tail;
+
+        /*
+         * Align next rule properly.
+         *Note that "dmacs_and_vlans" will also be aligned.
+         */
+        unsigned int pad = 0;
+        while (((head + pad) % __alignof__(gxio_mpipe_rules_rule_t)) != 0)
+                pad++;
+
+        /*
+         * Verify room.
+         * ISSUE: Mark rules as broken on error?
+         */
+        if (head + pad + sizeof(*rule) >= sizeof(list->rules))
+                return GXIO_MPIPE_ERR_RULES_FULL;
+
+        /* Verify num_buckets is a power of 2. */
+        if (__builtin_popcount(num_buckets) != 1)
+                return GXIO_MPIPE_ERR_RULES_INVALID;
+
+        /* Add padding to previous rule. */
+        rule->size += pad;
+
+        /* Start a new rule. */
+        list->head = head + pad;
+
+        rule = (gxio_mpipe_rules_rule_t *) (list->rules + list->head);
+
+        /* Default some values. */
+        rule->headroom = 2;
+        rule->tailroom = 0;
+        rule->capacity = 16384;
+
+        /* Save the bucket info. */
+        rule->bucket_mask = num_buckets - 1;
+        rule->bucket_first = bucket;
+
+        for (i = 8 - 1; i >= 0; i--) {
+                int maybe =
+                        stacks ? stacks->stacks[i] : rules->context->__stacks.
+                        stacks[i];
+                if (maybe != 255)
+                        stack = maybe;
+                rule->stacks.stacks[i] = stack;
+        }
+
+        if (stack == 255)
+                return GXIO_MPIPE_ERR_RULES_INVALID;
+
+        /* NOTE: Only entries at the end of the array can be 255. */
+        for (i = 8 - 1; i > 0; i--) {
+                if (rule->stacks.stacks[i] == 255) {
+                        rule->stacks.stacks[i] = stack;
+                        rule->capacity =
+                                gxio_mpipe_buffer_size_enum_to_buffer_size(i -
+                                                                           1);
+                }
+        }
+
+        rule->size = sizeof(*rule);
+        list->tail = list->head + rule->size;
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_rules_begin);
+
+int gxio_mpipe_rules_add_channel(gxio_mpipe_rules_t *rules,
+                                 unsigned int channel)
+{
+        gxio_mpipe_rules_list_t *list = &rules->list;
+
+        gxio_mpipe_rules_rule_t *rule =
+                (gxio_mpipe_rules_rule_t *) (list->rules + list->head);
+
+        /* Verify channel. */
+        if (channel >= 32)
+                return GXIO_MPIPE_ERR_RULES_INVALID;
+
+        /* Verify begun. */
+        if (list->tail == 0)
+                return GXIO_MPIPE_ERR_RULES_EMPTY;
+
+        rule->channel_bits |= (1UL << channel);
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_rules_add_channel);
+
+int gxio_mpipe_rules_set_headroom(gxio_mpipe_rules_t *rules, uint8_t headroom)
+{
+        gxio_mpipe_rules_list_t *list = &rules->list;
+
+        gxio_mpipe_rules_rule_t *rule =
+                (gxio_mpipe_rules_rule_t *) (list->rules + list->head);
+
+        /* Verify begun. */
+        if (list->tail == 0)
+                return GXIO_MPIPE_ERR_RULES_EMPTY;
+
+        rule->headroom = headroom;
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_rules_set_headroom);
+
+int gxio_mpipe_rules_commit(gxio_mpipe_rules_t *rules)
+{
+        gxio_mpipe_rules_list_t *list = &rules->list;
+        unsigned int size =
+                offsetof(gxio_mpipe_rules_list_t, rules) + list->tail;
+        return gxio_mpipe_commit_rules(rules->context, list, size);
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_rules_commit);
+
+int gxio_mpipe_iqueue_init(gxio_mpipe_iqueue_t *iqueue,
+                           gxio_mpipe_context_t *context,
+                           unsigned int ring,
+                           void *mem, size_t mem_size, unsigned int mem_flags)
+{
+        /* The init call below will verify that "mem_size" is legal. */
+        unsigned int num_entries = mem_size / sizeof(gxio_mpipe_idesc_t);
+
+        iqueue->context = context;
+        iqueue->idescs = (gxio_mpipe_idesc_t *)mem;
+        iqueue->ring = ring;
+        iqueue->num_entries = num_entries;
+        iqueue->mask_num_entries = num_entries - 1;
+        iqueue->log2_num_entries = __builtin_ctz(num_entries);
+        iqueue->head = 1;
+#ifdef __BIG_ENDIAN__
+        iqueue->swapped = 0;
+#endif
+
+        /* Initialize the "tail". */
+        __gxio_mmio_write(mem, iqueue->head);
+
+        return gxio_mpipe_init_notif_ring(context, ring, mem, mem_size,
+                                          mem_flags);
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_iqueue_init);
+
+int gxio_mpipe_equeue_init(gxio_mpipe_equeue_t *equeue,
+                           gxio_mpipe_context_t *context,
+                           unsigned int edma_ring_id,
+                           unsigned int channel,
+                           void *mem, unsigned int mem_size,
+                           unsigned int mem_flags)
+{
+        /* The init call below will verify that "mem_size" is legal. */
+        unsigned int num_entries = mem_size / sizeof(gxio_mpipe_edesc_t);
+
+        /* Offset used to read number of completed commands. */
+        MPIPE_EDMA_POST_REGION_ADDR_t offset;
+
+        int result = gxio_mpipe_init_edma_ring(context, edma_ring_id, channel,
+                                               mem, mem_size, mem_flags);
+        if (result < 0)
+                return result;
+
+        memset(equeue, 0, sizeof(*equeue));
+
+        offset.word = 0;
+        offset.region =
+                MPIPE_MMIO_ADDR__REGION_VAL_EDMA -
+                MPIPE_MMIO_ADDR__REGION_VAL_IDMA;
+        offset.ring = edma_ring_id;
+
+        __gxio_dma_queue_init(&equeue->dma_queue,
+                              context->mmio_fast_base + offset.word,
+                              num_entries);
+        equeue->edescs = mem;
+        equeue->mask_num_entries = num_entries - 1;
+        equeue->log2_num_entries = __builtin_ctz(num_entries);
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_equeue_init);
+
+int gxio_mpipe_set_timestamp(gxio_mpipe_context_t *context,
+                             const struct timespec *ts)
+{
+        cycles_t cycles = get_cycles();
+        return gxio_mpipe_set_timestamp_aux(context, (uint64_t)ts->tv_sec,
+                                            (uint64_t)ts->tv_nsec,
+                                            (uint64_t)cycles);
+}
+
+int gxio_mpipe_get_timestamp(gxio_mpipe_context_t *context,
+                             struct timespec *ts)
+{
+        int ret;
+        cycles_t cycles_prev, cycles_now, clock_rate;
+        cycles_prev = get_cycles();
+        ret = gxio_mpipe_get_timestamp_aux(context, (uint64_t *)&ts->tv_sec,
+                                           (uint64_t *)&ts->tv_nsec,
+                                           (uint64_t *)&cycles_now);
+        if (ret < 0) {
+                return ret;
+        }
+
+        clock_rate = get_clock_rate();
+        ts->tv_nsec -= (cycles_now - cycles_prev) * 1000000000LL / clock_rate;
+        if (ts->tv_nsec < 0) {
+                ts->tv_nsec += 1000000000LL;
+                ts->tv_sec -= 1;
+        }
+        return ret;
+}
+
+int gxio_mpipe_adjust_timestamp(gxio_mpipe_context_t *context, int64_t delta)
+{
+        return gxio_mpipe_adjust_timestamp_aux(context, delta);
+}
+
+/* Get our internal context used for link name access.  This context is
+ *  special in that it is not associated with an mPIPE service domain.
+ */
+static gxio_mpipe_context_t *_gxio_get_link_context(void)
+{
+        static gxio_mpipe_context_t context;
+        static gxio_mpipe_context_t *contextp;
+        static int tried_open = 0;
+        static DEFINE_MUTEX(mutex);
+
+        mutex_lock(&mutex);
+
+        if (!tried_open) {
+                int i = 0;
+                tried_open = 1;
+
+                /*
+                 * "4" here is the maximum possible number of mPIPE shims; it's
+                 * an exaggeration but we shouldn't ever go beyond 2 anyway.
+                 */
+                for (i = 0; i < 4; i++) {
+                        char file[80];
+
+                        snprintf(file, sizeof(file), "mpipe/%d/iorpc_info", i);
+                        context.fd = hv_dev_open((HV_VirtAddr) file, 0);
+                        if (context.fd < 0)
+                                continue;
+
+                        contextp = &context;
+                        break;
+                }
+        }
+
+        mutex_unlock(&mutex);
+
+        return contextp;
+}
+
+int gxio_mpipe_link_enumerate_mac(int idx, char *link_name, uint8_t *link_mac)
+{
+        int rv;
+        _gxio_mpipe_link_name_t name;
+        _gxio_mpipe_link_mac_t mac;
+
+        gxio_mpipe_context_t *context = _gxio_get_link_context();
+        if (!context)
+                return GXIO_ERR_NO_DEVICE;
+
+        rv = gxio_mpipe_info_enumerate_aux(context, idx, &name, &mac);
+        if (rv >= 0) {
+                strncpy(link_name, name.name, sizeof(name.name));
+                memcpy(link_mac, mac.mac, sizeof(mac.mac));
+        }
+
+        return rv;
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_link_enumerate_mac);
+
+int gxio_mpipe_link_open(gxio_mpipe_link_t *link,
+                         gxio_mpipe_context_t *context, const char *link_name,
+                         unsigned int flags)
+{
+        _gxio_mpipe_link_name_t name;
+        int rv;
+
+        strncpy(name.name, link_name, sizeof(name.name));
+        name.name[GXIO_MPIPE_LINK_NAME_LEN - 1] = '\0';
+
+        rv = gxio_mpipe_link_open_aux(context, name, flags);
+        if (rv < 0)
+                return rv;
+
+        link->context = context;
+        link->channel = rv >> 8;
+        link->mac = rv & 0xFF;
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_link_open);
+
+int gxio_mpipe_link_close(gxio_mpipe_link_t *link)
+{
+        return gxio_mpipe_link_close_aux(link->context, link->mac);
+}
+
+EXPORT_SYMBOL_GPL(gxio_mpipe_link_close);
diff --git a/arch/tile/gxio/trio.c b/arch/tile/gxio/trio.c
new file mode 100644
index 00000000000..69f0b8df3ce
--- /dev/null
+++ b/arch/tile/gxio/trio.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/*
+ * Implementation of trio gxio calls.
+ */
+
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/module.h>
+
+#include <gxio/trio.h>
+#include <gxio/iorpc_globals.h>
+#include <gxio/iorpc_trio.h>
+#include <gxio/kiorpc.h>
+
+int gxio_trio_init(gxio_trio_context_t *context, unsigned int trio_index)
+{
+        char file[32];
+        int fd;
+
+        snprintf(file, sizeof(file), "trio/%d/iorpc", trio_index);
+        fd = hv_dev_open((HV_VirtAddr) file, 0);
+        if (fd < 0) {
+                context->fd = -1;
+
+                if (fd >= GXIO_ERR_MIN && fd <= GXIO_ERR_MAX)
+                        return fd;
+                else
+                        return -ENODEV;
+        }
+
+        context->fd = fd;
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(gxio_trio_init);
diff --git a/arch/tile/gxio/usb_host.c b/arch/tile/gxio/usb_host.c
new file mode 100644
index 00000000000..66b002f54ec
--- /dev/null
+++ b/arch/tile/gxio/usb_host.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/*
+ *
+ * Implementation of USB gxio calls.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+
+#include <gxio/iorpc_globals.h>
+#include <gxio/iorpc_usb_host.h>
+#include <gxio/kiorpc.h>
+#include <gxio/usb_host.h>
+
+int gxio_usb_host_init(gxio_usb_host_context_t * context, int usb_index,
+                       int is_ehci)
+{
+        char file[32];
+        int fd;
+
+        if (is_ehci)
+                snprintf(file, sizeof(file), "usb_host/%d/iorpc/ehci",
+                         usb_index);
+        else
+                snprintf(file, sizeof(file), "usb_host/%d/iorpc/ohci",
+                         usb_index);
+
+        fd = hv_dev_open((HV_VirtAddr) file, 0);
+        if (fd < 0) {
+                if (fd >= GXIO_ERR_MIN && fd <= GXIO_ERR_MAX)
+                        return fd;
+                else
+                        return -ENODEV;
+        }
+
+        context->fd = fd;
+
+        // Map in the MMIO space.
+        context->mmio_base =
+                (void __force *)iorpc_ioremap(fd, 0, HV_USB_HOST_MMIO_SIZE);
+
+        if (context->mmio_base == NULL) {
+                hv_dev_close(context->fd);
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(gxio_usb_host_init);
+
+int gxio_usb_host_destroy(gxio_usb_host_context_t * context)
+{
+        iounmap((void __force __iomem *)(context->mmio_base));
+        hv_dev_close(context->fd);
+
+        context->mmio_base = NULL;
+        context->fd = -1;
+
+        return 0;
+}
+
+EXPORT_SYMBOL_GPL(gxio_usb_host_destroy);
+
+void *gxio_usb_host_get_reg_start(gxio_usb_host_context_t * context)
+{
+        return context->mmio_base;
+}
+
+EXPORT_SYMBOL_GPL(gxio_usb_host_get_reg_start);
+
+size_t gxio_usb_host_get_reg_len(gxio_usb_host_context_t * context)
+{
+        return HV_USB_HOST_MMIO_SIZE;
+}
+
+EXPORT_SYMBOL_GPL(gxio_usb_host_get_reg_len);
diff --git a/arch/tile/include/arch/mpipe.h b/arch/tile/include/arch/mpipe.h
new file mode 100644
index 00000000000..8a33912fd6c
--- /dev/null
+++ b/arch/tile/include/arch/mpipe.h
@@ -0,0 +1,359 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_MPIPE_H__
+#define __ARCH_MPIPE_H__
+
+#include <arch/abi.h>
+#include <arch/mpipe_def.h>
+
+#ifndef __ASSEMBLER__
+
+/*
+ * MMIO Ingress DMA Release Region Address.
+ * This is a description of the physical addresses used to manipulate ingress
+ * credit counters.  Accesses to this address space should use an address of
+ * this form and a value like that specified in IDMA_RELEASE_REGION_VAL.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /* Reserved. */
+    uint_reg_t __reserved_0  : 3;
+    /* NotifRing to be released */
+    uint_reg_t ring          : 8;
+    /* Bucket to be released */
+    uint_reg_t bucket        : 13;
+    /* Enable NotifRing release */
+    uint_reg_t ring_enable   : 1;
+    /* Enable Bucket release */
+    uint_reg_t bucket_enable : 1;
+    /*
+     * This field of the address selects the region (address space) to be
+     * accessed.  For the iDMA release region, this field must be 4.
+     */
+    uint_reg_t region        : 3;
+    /* Reserved. */
+    uint_reg_t __reserved_1  : 6;
+    /* This field of the address indexes the 32 entry service domain table. */
+    uint_reg_t svc_dom       : 5;
+    /* Reserved. */
+    uint_reg_t __reserved_2  : 24;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved_2  : 24;
+    uint_reg_t svc_dom       : 5;
+    uint_reg_t __reserved_1  : 6;
+    uint_reg_t region        : 3;
+    uint_reg_t bucket_enable : 1;
+    uint_reg_t ring_enable   : 1;
+    uint_reg_t bucket        : 13;
+    uint_reg_t ring          : 8;
+    uint_reg_t __reserved_0  : 3;
+#endif
+  };
+
+  uint_reg_t word;
+} MPIPE_IDMA_RELEASE_REGION_ADDR_t;
+
+/*
+ * MMIO Ingress DMA Release Region Value - Release NotifRing and/or Bucket.
+ * Provides release of the associated NotifRing.  The address of the MMIO
+ * operation is described in IDMA_RELEASE_REGION_ADDR.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /*
+     * Number of packets being released.  The load balancer's count of
+     * inflight packets will be decremented by this amount for the associated
+     * Bucket and/or NotifRing
+     */
+    uint_reg_t count      : 16;
+    /* Reserved. */
+    uint_reg_t __reserved : 48;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved : 48;
+    uint_reg_t count      : 16;
+#endif
+  };
+
+  uint_reg_t word;
+} MPIPE_IDMA_RELEASE_REGION_VAL_t;
+
+/*
+ * MMIO Buffer Stack Manager Region Address.
+ * This MMIO region is used for posting or fetching buffers to/from the
+ * buffer stack manager.  On an MMIO load, this pops a buffer descriptor from
+ * the top of stack if one is available.  On an MMIO store, this pushes a
+ * buffer to the stack.  The value read or written is described in
+ * BSM_REGION_VAL.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /* Reserved. */
+    uint_reg_t __reserved_0 : 3;
+    /* BufferStack being accessed. */
+    uint_reg_t stack        : 5;
+    /* Reserved. */
+    uint_reg_t __reserved_1 : 18;
+    /*
+     * This field of the address selects the region (address space) to be
+     * accessed.  For the buffer stack manager region, this field must be 6.
+     */
+    uint_reg_t region       : 3;
+    /* Reserved. */
+    uint_reg_t __reserved_2 : 6;
+    /* This field of the address indexes the 32 entry service domain table. */
+    uint_reg_t svc_dom      : 5;
+    /* Reserved. */
+    uint_reg_t __reserved_3 : 24;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved_3 : 24;
+    uint_reg_t svc_dom      : 5;
+    uint_reg_t __reserved_2 : 6;
+    uint_reg_t region       : 3;
+    uint_reg_t __reserved_1 : 18;
+    uint_reg_t stack        : 5;
+    uint_reg_t __reserved_0 : 3;
+#endif
+  };
+
+  uint_reg_t word;
+} MPIPE_BSM_REGION_ADDR_t;
+
+/*
+ * MMIO Buffer Stack Manager Region Value.
+ * This MMIO region is used for posting or fetching buffers to/from the
+ * buffer stack manager.  On an MMIO load, this pops a buffer descriptor from
+ * the top of stack if one is available. On an MMIO store, this pushes a
+ * buffer to the stack.  The address of the MMIO operation is described in
+ * BSM_REGION_ADDR.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /* Reserved. */
+    uint_reg_t __reserved_0 : 7;
+    /*
+     * Base virtual address of the buffer.  Must be sign extended by consumer.
+     */
+    int_reg_t va           : 35;
+    /* Reserved. */
+    uint_reg_t __reserved_1 : 6;
+    /*
+     * Index of the buffer stack to which this buffer belongs.  Ignored on
+     * writes since the offset bits specify the stack being accessed.
+     */
+    uint_reg_t stack_idx    : 5;
+    /* Reserved. */
+    uint_reg_t __reserved_2 : 5;
+    /*
+     * Reads as one to indicate that this is a hardware managed buffer.
+     * Ignored on writes since all buffers on a given stack are the same size.
+     */
+    uint_reg_t hwb          : 1;
+    /*
+     * Encoded size of buffer (ignored on writes):
+     * 0 = 128 bytes
+     * 1 = 256 bytes
+     * 2 = 512 bytes
+     * 3 = 1024 bytes
+     * 4 = 1664 bytes
+     * 5 = 4096 bytes
+     * 6 = 10368 bytes
+     * 7 = 16384 bytes
+     */
+    uint_reg_t size         : 3;
+    /*
+     * Valid indication for the buffer.  Ignored on writes.
+     * 0 : Valid buffer descriptor popped from stack.
+     * 3 : Could not pop a buffer from the stack.  Either the stack is empty,
+     * or the hardware's prefetch buffer is empty for this stack.
+     */
+    uint_reg_t c            : 2;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t c            : 2;
+    uint_reg_t size         : 3;
+    uint_reg_t hwb          : 1;
+    uint_reg_t __reserved_2 : 5;
+    uint_reg_t stack_idx    : 5;
+    uint_reg_t __reserved_1 : 6;
+    int_reg_t va           : 35;
+    uint_reg_t __reserved_0 : 7;
+#endif
+  };
+
+  uint_reg_t word;
+} MPIPE_BSM_REGION_VAL_t;
+
+/*
+ * MMIO Egress DMA Post Region Address.
+ * Used to post descriptor locations to the eDMA descriptor engine.  The
+ * value to be written is described in EDMA_POST_REGION_VAL
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /* Reserved. */
+    uint_reg_t __reserved_0 : 3;
+    /* eDMA ring being accessed */
+    uint_reg_t ring         : 5;
+    /* Reserved. */
+    uint_reg_t __reserved_1 : 18;
+    /*
+     * This field of the address selects the region (address space) to be
+     * accessed.  For the egress DMA post region, this field must be 5.
+     */
+    uint_reg_t region       : 3;
+    /* Reserved. */
+    uint_reg_t __reserved_2 : 6;
+    /* This field of the address indexes the 32 entry service domain table. */
+    uint_reg_t svc_dom      : 5;
+    /* Reserved. */
+    uint_reg_t __reserved_3 : 24;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved_3 : 24;
+    uint_reg_t svc_dom      : 5;
+    uint_reg_t __reserved_2 : 6;
+    uint_reg_t region       : 3;
+    uint_reg_t __reserved_1 : 18;
+    uint_reg_t ring         : 5;
+    uint_reg_t __reserved_0 : 3;
+#endif
+  };
+
+  uint_reg_t word;
+} MPIPE_EDMA_POST_REGION_ADDR_t;
+
+/*
+ * MMIO Egress DMA Post Region Value.
+ * Used to post descriptor locations to the eDMA descriptor engine.  The
+ * address is described in EDMA_POST_REGION_ADDR.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /*
+     * For writes, this specifies the current ring tail pointer prior to any
+     * post.  For example, to post 1 or more descriptors starting at location
+     * 23, this would contain 23 (not 24).  On writes, this index must be
+     * masked based on the ring size.  The new tail pointer after this post
+     * is COUNT+RING_IDX (masked by the ring size).
+     *
+     * For reads, this provides the hardware descriptor fetcher's head
+     * pointer.  The descriptors prior to the head pointer, however, may not
+     * yet have been processed so this indicator is only used to determine
+     * how full the ring is and if software may post more descriptors.
+     */
+    uint_reg_t ring_idx   : 16;
+    /*
+     * For writes, this specifies number of contiguous descriptors that are
+     * being posted.  Software may post up to RingSize descriptors with a
+     * single MMIO store.  A zero in this field on a write will "wake up" an
+     * eDMA ring and cause it fetch descriptors regardless of the hardware's
+     * current view of the state of the tail pointer.
+     *
+     * For reads, this field provides a rolling count of the number of
+     * descriptors that have been completely processed.  This may be used by
+     * software to determine when buffers associated with a descriptor may be
+     * returned or reused.  When the ring's flush bit is cleared by software
+     * (after having been set by HW or SW), the COUNT will be cleared.
+     */
+    uint_reg_t count      : 16;
+    /*
+     * For writes, this specifies the generation number of the tail being
+     * posted. Note that if tail+cnt wraps to the beginning of the ring, the
+     * eDMA hardware assumes that the descriptors posted at the beginning of
+     * the ring are also valid so it is okay to post around the wrap point.
+     *
+     * For reads, this is the current generation number.  Valid descriptors
+     * will have the inverse of this generation number.
+     */
+    uint_reg_t gen        : 1;
+    /* Reserved. */
+    uint_reg_t __reserved : 31;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved : 31;
+    uint_reg_t gen        : 1;
+    uint_reg_t count      : 16;
+    uint_reg_t ring_idx   : 16;
+#endif
+  };
+
+  uint_reg_t word;
+} MPIPE_EDMA_POST_REGION_VAL_t;
+
+/*
+ * Load Balancer Bucket Status Data.
+ * Read/Write data for load balancer Bucket-Status Table. 4160 entries
+ * indexed by LBL_INIT_CTL.IDX when LBL_INIT_CTL.STRUCT_SEL is BSTS_TBL
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /* NotifRing currently assigned to this bucket. */
+    uint_reg_t notifring  : 8;
+    /* Current reference count. */
+    uint_reg_t count      : 16;
+    /* Group associated with this bucket. */
+    uint_reg_t group      : 5;
+    /* Mode select for this bucket. */
+    uint_reg_t mode       : 3;
+    /* Reserved. */
+    uint_reg_t __reserved : 32;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved : 32;
+    uint_reg_t mode       : 3;
+    uint_reg_t group      : 5;
+    uint_reg_t count      : 16;
+    uint_reg_t notifring  : 8;
+#endif
+  };
+
+  uint_reg_t word;
+} MPIPE_LBL_INIT_DAT_BSTS_TBL_t;
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* !defined(__ARCH_MPIPE_H__) */
diff --git a/arch/tile/include/arch/mpipe_constants.h b/arch/tile/include/arch/mpipe_constants.h
new file mode 100644
index 00000000000..410a0400e05
--- /dev/null
+++ b/arch/tile/include/arch/mpipe_constants.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+
+#ifndef __ARCH_MPIPE_CONSTANTS_H__
+#define __ARCH_MPIPE_CONSTANTS_H__
+
+#define MPIPE_NUM_CLASSIFIERS 10
+#define MPIPE_CLS_MHZ 1200
+
+#define MPIPE_NUM_EDMA_RINGS 32
+
+#define MPIPE_NUM_SGMII_MACS 16
+#define MPIPE_NUM_XAUI_MACS 4
+#define MPIPE_NUM_LOOPBACK_CHANNELS 4
+#define MPIPE_NUM_NON_LB_CHANNELS 28
+
+#define MPIPE_NUM_IPKT_BLOCKS 1536
+
+#define MPIPE_NUM_BUCKETS 4160
+
+#define MPIPE_NUM_NOTIF_RINGS 256
+
+#define MPIPE_NUM_NOTIF_GROUPS 32
+
+#define MPIPE_NUM_TLBS_PER_ASID 16
+#define MPIPE_TLB_IDX_WIDTH 4
+
+#define MPIPE_MMIO_NUM_SVC_DOM 32
+
+#endif /* __ARCH_MPIPE_CONSTANTS_H__ */
diff --git a/arch/tile/include/arch/mpipe_def.h b/arch/tile/include/arch/mpipe_def.h
new file mode 100644
index 00000000000..c3d30217fc6
--- /dev/null
+++ b/arch/tile/include/arch/mpipe_def.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_MPIPE_DEF_H__
+#define __ARCH_MPIPE_DEF_H__
+#define MPIPE_MMIO_ADDR__REGION_SHIFT 26
+#define MPIPE_MMIO_ADDR__REGION_VAL_CFG 0x0
+#define MPIPE_MMIO_ADDR__REGION_VAL_IDMA 0x4
+#define MPIPE_MMIO_ADDR__REGION_VAL_EDMA 0x5
+#define MPIPE_MMIO_ADDR__REGION_VAL_BSM 0x6
+#define MPIPE_BSM_REGION_VAL__VA_SHIFT 7
+#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_128 0x0
+#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_256 0x1
+#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_512 0x2
+#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1024 0x3
+#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1664 0x4
+#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_4096 0x5
+#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_10368 0x6
+#define MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_16384 0x7
+#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_DFA 0x0
+#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_FIXED 0x1
+#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_ALWAYS_PICK 0x2
+#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY 0x3
+#define MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY_RAND 0x7
+#define MPIPE_LBL_NR_STATE__FIRST_WORD 0x2138
+#endif /* !defined(__ARCH_MPIPE_DEF_H__) */
diff --git a/arch/tile/include/arch/mpipe_shm.h b/arch/tile/include/arch/mpipe_shm.h
new file mode 100644
index 00000000000..f2e9e122818
--- /dev/null
+++ b/arch/tile/include/arch/mpipe_shm.h
@@ -0,0 +1,509 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+
+#ifndef __ARCH_MPIPE_SHM_H__
+#define __ARCH_MPIPE_SHM_H__
+
+#include <arch/abi.h>
+#include <arch/mpipe_shm_def.h>
+
+#ifndef __ASSEMBLER__
+/**
+ * MPIPE eDMA Descriptor.
+ * The eDMA descriptor is written by software and consumed by hardware.  It
+ * is used to specify the location of egress packet data to be sent out of
+ * the chip via one of the packet interfaces.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+    /* Word 0 */
+
+#ifndef __BIG_ENDIAN__
+    /**
+     * Generation number.  Used to indicate a valid descriptor in ring.  When
+     * a new descriptor is written into the ring, software must toggle this
+     * bit.  The net effect is that the GEN bit being written into new
+     * descriptors toggles each time the ring tail pointer wraps.
+     */
+    uint_reg_t gen        : 1;
+    /** Reserved.  Must be zero. */
+    uint_reg_t r0         : 7;
+    /** Checksum generation enabled for this transfer. */
+    uint_reg_t csum       : 1;
+    /**
+     * Nothing to be sent.  Used, for example, when software has dropped a
+     * packet but still wishes to return all of the associated buffers.
+     */
+    uint_reg_t ns         : 1;
+    /**
+     * Notification interrupt will be delivered when packet has been egressed.
+     */
+    uint_reg_t notif      : 1;
+    /**
+     * Boundary indicator.  When 1, this transfer includes the EOP for this
+     * command.  Must be clear on all but the last descriptor for an egress
+     * packet.
+     */
+    uint_reg_t bound      : 1;
+    /** Reserved.  Must be zero. */
+    uint_reg_t r1         : 4;
+    /**
+     * Number of bytes to be sent for this descriptor.  When zero, no data
+     * will be moved and the buffer descriptor will be ignored.  If the
+     * buffer descriptor indicates that it is chained, the low 7 bits of the
+     * VA indicate the offset within the first buffer (e.g. 127 bytes is the
+     * maximum offset into the first buffer).  If the size exceeds a single
+     * buffer, subsequent buffer descriptors will be fetched prior to
+     * processing the next eDMA descriptor in the ring.
+     */
+    uint_reg_t xfer_size  : 14;
+    /** Reserved.  Must be zero. */
+    uint_reg_t r2         : 2;
+    /**
+     * Destination of checksum relative to CSUM_START relative to the first
+     * byte moved by this descriptor.  Must be zero if CSUM=0 in this
+     * descriptor.  Must be less than XFER_SIZE (e.g. the first byte of the
+     * CSUM_DEST must be within the span of this descriptor).
+     */
+    uint_reg_t csum_dest  : 8;
+    /**
+     * Start byte of checksum relative to the first byte moved by this
+     * descriptor.  If this is not the first descriptor for the egress
+     * packet, CSUM_START is still relative to the first byte in this
+     * descriptor.  Must be zero if CSUM=0 in this descriptor.
+     */
+    uint_reg_t csum_start : 8;
+    /**
+     * Initial value for 16-bit 1's compliment checksum if enabled via CSUM.
+     * Specified in network order.  That is, bits[7:0] will be added to the
+     * byte pointed to by CSUM_START and bits[15:8] will be added to the byte
+     * pointed to by CSUM_START+1 (with appropriate 1's compliment carries).
+     * Must be zero if CSUM=0 in this descriptor.
+     */
+    uint_reg_t csum_seed  : 16;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t csum_seed  : 16;
+    uint_reg_t csum_start : 8;
+    uint_reg_t csum_dest  : 8;
+    uint_reg_t r2         : 2;
+    uint_reg_t xfer_size  : 14;
+    uint_reg_t r1         : 4;
+    uint_reg_t bound      : 1;
+    uint_reg_t notif      : 1;
+    uint_reg_t ns         : 1;
+    uint_reg_t csum       : 1;
+    uint_reg_t r0         : 7;
+    uint_reg_t gen        : 1;
+#endif
+
+    /* Word 1 */
+
+#ifndef __BIG_ENDIAN__
+    /** Virtual address.  Must be sign extended by consumer. */
+    int_reg_t va           : 42;
+    /** Reserved. */
+    uint_reg_t __reserved_0 : 6;
+    /** Index of the buffer stack to which this buffer belongs. */
+    uint_reg_t stack_idx    : 5;
+    /** Reserved. */
+    uint_reg_t __reserved_1 : 3;
+    /**
+     * Instance ID.  For devices that support more than one mPIPE instance,
+     * this field indicates the buffer owner.  If the INST field does not
+     * match the mPIPE's instance number when a packet is egressed, buffers
+     * with HWB set will be returned to the other mPIPE instance.
+     */
+    uint_reg_t inst         : 1;
+    /** Reserved. */
+    uint_reg_t __reserved_2 : 1;
+    /**
+     * Always set to one by hardware in iDMA packet descriptors.  For eDMA,
+     * indicates whether the buffer will be released to the buffer stack
+     * manager.  When 0, software is responsible for releasing the buffer.
+     */
+    uint_reg_t hwb          : 1;
+    /**
+     * Encoded size of buffer.  Set by the ingress hardware for iDMA packet
+     * descriptors.  For eDMA descriptors, indicates the buffer size if .c
+     * indicates a chained packet.  If an eDMA descriptor is not chained and
+     * the .hwb bit is not set, this field is ignored and the size is
+     * specified by the .xfer_size field.
+     * 0 = 128 bytes
+     * 1 = 256 bytes
+     * 2 = 512 bytes
+     * 3 = 1024 bytes
+     * 4 = 1664 bytes
+     * 5 = 4096 bytes
+     * 6 = 10368 bytes
+     * 7 = 16384 bytes
+     */
+    uint_reg_t size         : 3;
+    /**
+     * Chaining configuration for the buffer.  Indicates that an ingress
+     * packet or egress command is chained across multiple buffers, with each
+     * buffer's size indicated by the .size field.
+     */
+    uint_reg_t c            : 2;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t c            : 2;
+    uint_reg_t size         : 3;
+    uint_reg_t hwb          : 1;
+    uint_reg_t __reserved_2 : 1;
+    uint_reg_t inst         : 1;
+    uint_reg_t __reserved_1 : 3;
+    uint_reg_t stack_idx    : 5;
+    uint_reg_t __reserved_0 : 6;
+    int_reg_t va           : 42;
+#endif
+
+  };
+
+  /** Word access */
+  uint_reg_t words[2];
+} MPIPE_EDMA_DESC_t;
+
+/**
+ * MPIPE Packet Descriptor.
+ * The packet descriptor is filled by the mPIPE's classification,
+ * load-balancing, and buffer management services.  Some fields are consumed
+ * by mPIPE hardware, and others are consumed by Tile software.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+    /* Word 0 */
+
+#ifndef __BIG_ENDIAN__
+    /**
+     * Notification ring into which this packet descriptor is written.
+     * Typically written by load balancer, but can be overridden by
+     * classification program if NR is asserted.
+     */
+    uint_reg_t notif_ring   : 8;
+    /** Source channel for this packet.  Written by mPIPE DMA hardware. */
+    uint_reg_t channel      : 5;
+    /** Reserved. */
+    uint_reg_t __reserved_0 : 1;
+    /**
+     * MAC Error.
+     * Generated by the MAC interface.  Asserted if there was an overrun of
+     * the MAC's receive FIFO.  This condition generally only occurs if the
+     * mPIPE clock is running too slowly.
+     */
+    uint_reg_t me           : 1;
+    /**
+     * Truncation Error.
+     * Written by the iDMA hardware.  Asserted if packet was truncated due to
+     * insufficient space in iPkt buffer
+     */
+    uint_reg_t tr           : 1;
+    /**
+     * Written by the iDMA hardware.  Indicates the number of bytes written
+     * to Tile memory.  In general, this is the actual size of the packet as
+     * received from the MAC.  But if the packet is truncated due to running
+     * out of buffers or due to the iPkt buffer filling up, then the L2_SIZE
+     * will be reduced to reflect the actual number of valid bytes written to
+     * Tile memory.
+     */
+    uint_reg_t l2_size      : 14;
+    /**
+     * CRC Error.
+     * Generated by the MAC.  Asserted if MAC indicated an L2 CRC error or
+     * other L2 error (bad length etc.) on the packet.
+     */
+    uint_reg_t ce           : 1;
+    /**
+     * Cut Through.
+     * Written by the iDMA hardware.  Asserted if packet was not completely
+     * received before being sent to classifier.  L2_Size will indicate
+     * number of bytes received so far.
+     */
+    uint_reg_t ct           : 1;
+    /**
+     * Written by the classification program.  Used by the load balancer to
+     * select the ring into which this packet descriptor is written.
+     */
+    uint_reg_t bucket_id    : 13;
+    /** Reserved. */
+    uint_reg_t __reserved_1 : 3;
+    /**
+     * Checksum.
+     * Written by classification program.  When 1, the checksum engine will
+     * perform checksum based on the CSUM_SEED, CSUM_START, and CSUM_BYTES
+     * fields.  The result will be placed in CSUM_VAL.
+     */
+    uint_reg_t cs           : 1;
+    /**
+     * Notification Ring Select.
+     * Written by the classification program.  When 1, the NotifRingIDX is
+     * set by classification program rather than being set by load balancer.
+     */
+    uint_reg_t nr           : 1;
+    /**
+     * Written by classification program.  Indicates whether packet and
+     * descriptor should both be dropped, both be delivered, or only the
+     * descriptor should be delivered.
+     */
+    uint_reg_t dest         : 2;
+    /**
+     * General Purpose Sequence Number Enable.
+     * Written by the classification program.  When 1, the GP_SQN_SEL field
+     * contains the sequence number selector and the GP_SQN field will be
+     * replaced with the associated sequence number.  When clear, the GP_SQN
+     * field is left intact and be used as "Custom" bytes.
+     */
+    uint_reg_t sq           : 1;
+    /**
+     * TimeStamp Enable.
+     * Enable TimeStamp insertion.  When clear, timestamp field may be filled
+     * with custom data by classifier.  When set, hardware inserts the
+     * timestamp when the start of packet is received from the MAC.
+     */
+    uint_reg_t ts           : 1;
+    /**
+     * Packet Sequence Number Enable.
+     * Enable PacketSQN insertion.  When clear, PacketSQN field may be filled
+     * with custom data by classifier.  When set, hardware inserts the packet
+     * sequence number when the packet descriptor is written to a
+     * notification ring.
+     */
+    uint_reg_t ps           : 1;
+    /**
+     * Buffer Error.
+     * Written by the iDMA hardware.  Asserted if iDMA ran out of buffers
+     * while writing the packet. Software must still return any buffer
+     * descriptors whose C field indicates a valid descriptor was consumed.
+     */
+    uint_reg_t be           : 1;
+    /**
+     * Written by  the classification program.  The associated counter is
+     * incremented when the packet is sent.
+     */
+    uint_reg_t ctr0         : 5;
+    /** Reserved. */
+    uint_reg_t __reserved_2 : 3;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved_2 : 3;
+    uint_reg_t ctr0         : 5;
+    uint_reg_t be           : 1;
+    uint_reg_t ps           : 1;
+    uint_reg_t ts           : 1;
+    uint_reg_t sq           : 1;
+    uint_reg_t dest         : 2;
+    uint_reg_t nr           : 1;
+    uint_reg_t cs           : 1;
+    uint_reg_t __reserved_1 : 3;
+    uint_reg_t bucket_id    : 13;
+    uint_reg_t ct           : 1;
+    uint_reg_t ce           : 1;
+    uint_reg_t l2_size      : 14;
+    uint_reg_t tr           : 1;
+    uint_reg_t me           : 1;
+    uint_reg_t __reserved_0 : 1;
+    uint_reg_t channel      : 5;
+    uint_reg_t notif_ring   : 8;
+#endif
+
+    /* Word 1 */
+
+#ifndef __BIG_ENDIAN__
+    /**
+     * Written by  the classification program.  The associated counter is
+     * incremented when the packet is sent.
+     */
+    uint_reg_t ctr1          : 5;
+    /** Reserved. */
+    uint_reg_t __reserved_3  : 3;
+    /**
+     * Written by classification program.  Indicates the start byte for
+     * checksum.  Relative to 1st byte received from MAC.
+     */
+    uint_reg_t csum_start    : 8;
+    /**
+     * Checksum seed written by classification program.  Overwritten with
+     * resultant checksum if CS bit is asserted.  The endianness of the CSUM
+     * value bits when viewed by Tile software match the packet byte order.
+     * That is, bits[7:0] of the resulting checksum value correspond to
+     * earlier (more significant) bytes in the packet.  To avoid classifier
+     * software from having to byte swap the CSUM_SEED, the iDMA checksum
+     * engine byte swaps the classifier's result before seeding the checksum
+     * calculation.  Thus, the CSUM_START byte of packet data is added to
+     * bits[15:8] of the CSUM_SEED field generated by the classifier.  This
+     * byte swap will be visible to Tile software if the CS bit is clear.
+     */
+    uint_reg_t csum_seed_val : 16;
+    /**
+     * Written by  the classification program.  Not interpreted by mPIPE
+     * hardware.
+     */
+    uint_reg_t custom0       : 32;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t custom0       : 32;
+    uint_reg_t csum_seed_val : 16;
+    uint_reg_t csum_start    : 8;
+    uint_reg_t __reserved_3  : 3;
+    uint_reg_t ctr1          : 5;
+#endif
+
+    /* Word 2 */
+
+#ifndef __BIG_ENDIAN__
+    /**
+     * Written by  the classification program.  Not interpreted by mPIPE
+     * hardware.
+     */
+    uint_reg_t custom1 : 64;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t custom1 : 64;
+#endif
+
+    /* Word 3 */
+
+#ifndef __BIG_ENDIAN__
+    /**
+     * Written by  the classification program.  Not interpreted by mPIPE
+     * hardware.
+     */
+    uint_reg_t custom2 : 64;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t custom2 : 64;
+#endif
+
+    /* Word 4 */
+
+#ifndef __BIG_ENDIAN__
+    /**
+     * Written by  the classification program.  Not interpreted by mPIPE
+     * hardware.
+     */
+    uint_reg_t custom3 : 64;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t custom3 : 64;
+#endif
+
+    /* Word 5 */
+
+#ifndef __BIG_ENDIAN__
+    /**
+     * Sequence number applied when packet is distributed.   Classifier
+     * selects which sequence number is to be applied by writing the 13-bit
+     * SQN-selector into this field.
+     */
+    uint_reg_t gp_sqn     : 16;
+    /**
+     * Written by notification hardware.  The packet sequence number is
+     * incremented for each packet that wasn't dropped.
+     */
+    uint_reg_t packet_sqn : 48;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t packet_sqn : 48;
+    uint_reg_t gp_sqn     : 16;
+#endif
+
+    /* Word 6 */
+
+#ifndef __BIG_ENDIAN__
+    /**
+     * Written by hardware when the start-of-packet is received by the mPIPE
+     * from the MAC.  This is the nanoseconds part of the packet timestamp.
+     */
+    uint_reg_t time_stamp_ns  : 32;
+    /**
+     * Written by hardware when the start-of-packet is received by the mPIPE
+     * from the MAC.  This is the seconds part of the packet timestamp.
+     */
+    uint_reg_t time_stamp_sec : 32;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t time_stamp_sec : 32;
+    uint_reg_t time_stamp_ns  : 32;
+#endif
+
+    /* Word 7 */
+
+#ifndef __BIG_ENDIAN__
+    /** Virtual address.  Must be sign extended by consumer. */
+    int_reg_t va           : 42;
+    /** Reserved. */
+    uint_reg_t __reserved_4 : 6;
+    /** Index of the buffer stack to which this buffer belongs. */
+    uint_reg_t stack_idx    : 5;
+    /** Reserved. */
+    uint_reg_t __reserved_5 : 3;
+    /**
+     * Instance ID.  For devices that support more than one mPIPE instance,
+     * this field indicates the buffer owner.  If the INST field does not
+     * match the mPIPE's instance number when a packet is egressed, buffers
+     * with HWB set will be returned to the other mPIPE instance.
+     */
+    uint_reg_t inst         : 1;
+    /** Reserved. */
+    uint_reg_t __reserved_6 : 1;
+    /**
+     * Always set to one by hardware in iDMA packet descriptors.  For eDMA,
+     * indicates whether the buffer will be released to the buffer stack
+     * manager.  When 0, software is responsible for releasing the buffer.
+     */
+    uint_reg_t hwb          : 1;
+    /**
+     * Encoded size of buffer.  Set by the ingress hardware for iDMA packet
+     * descriptors.  For eDMA descriptors, indicates the buffer size if .c
+     * indicates a chained packet.  If an eDMA descriptor is not chained and
+     * the .hwb bit is not set, this field is ignored and the size is
+     * specified by the .xfer_size field.
+     * 0 = 128 bytes
+     * 1 = 256 bytes
+     * 2 = 512 bytes
+     * 3 = 1024 bytes
+     * 4 = 1664 bytes
+     * 5 = 4096 bytes
+     * 6 = 10368 bytes
+     * 7 = 16384 bytes
+     */
+    uint_reg_t size         : 3;
+    /**
+     * Chaining configuration for the buffer.  Indicates that an ingress
+     * packet or egress command is chained across multiple buffers, with each
+     * buffer's size indicated by the .size field.
+     */
+    uint_reg_t c            : 2;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t c            : 2;
+    uint_reg_t size         : 3;
+    uint_reg_t hwb          : 1;
+    uint_reg_t __reserved_6 : 1;
+    uint_reg_t inst         : 1;
+    uint_reg_t __reserved_5 : 3;
+    uint_reg_t stack_idx    : 5;
+    uint_reg_t __reserved_4 : 6;
+    int_reg_t va           : 42;
+#endif
+
+  };
+
+  /** Word access */
+  uint_reg_t words[8];
+} MPIPE_PDESC_t;
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* !defined(__ARCH_MPIPE_SHM_H__) */
diff --git a/arch/tile/include/arch/mpipe_shm_def.h b/arch/tile/include/arch/mpipe_shm_def.h
new file mode 100644
index 00000000000..6124d39c831
--- /dev/null
+++ b/arch/tile/include/arch/mpipe_shm_def.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_MPIPE_SHM_DEF_H__
+#define __ARCH_MPIPE_SHM_DEF_H__
+#define MPIPE_EDMA_DESC_WORD1__C_VAL_UNCHAINED 0x0
+#define MPIPE_EDMA_DESC_WORD1__C_VAL_CHAINED 0x1
+#define MPIPE_EDMA_DESC_WORD1__C_VAL_NOT_RDY 0x2
+#define MPIPE_EDMA_DESC_WORD1__C_VAL_INVALID 0x3
+#endif /* !defined(__ARCH_MPIPE_SHM_DEF_H__) */
diff --git a/arch/tile/include/arch/trio.h b/arch/tile/include/arch/trio.h
new file mode 100644
index 00000000000..d3000a871a2
--- /dev/null
+++ b/arch/tile/include/arch/trio.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_TRIO_H__
+#define __ARCH_TRIO_H__
+
+#include <arch/abi.h>
+#include <arch/trio_def.h>
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Tile PIO Region Configuration - CFG Address Format.
+ * This register describes the address format for PIO accesses when the
+ * associated region is setup with TYPE=CFG.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /* Register Address (full byte address). */
+    uint_reg_t reg_addr     : 12;
+    /* Function Number */
+    uint_reg_t fn           : 3;
+    /* Device Number */
+    uint_reg_t dev          : 5;
+    /* BUS Number */
+    uint_reg_t bus          : 8;
+    /* Config Type: 0 for access to directly-attached device.  1 otherwise. */
+    uint_reg_t type         : 1;
+    /* Reserved. */
+    uint_reg_t __reserved_0 : 1;
+    /*
+     * MAC select.  This must match the configuration in
+     * TILE_PIO_REGION_SETUP.MAC.
+     */
+    uint_reg_t mac          : 2;
+    /* Reserved. */
+    uint_reg_t __reserved_1 : 32;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved_1 : 32;
+    uint_reg_t mac          : 2;
+    uint_reg_t __reserved_0 : 1;
+    uint_reg_t type         : 1;
+    uint_reg_t bus          : 8;
+    uint_reg_t dev          : 5;
+    uint_reg_t fn           : 3;
+    uint_reg_t reg_addr     : 12;
+#endif
+  };
+
+  uint_reg_t word;
+} TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t;
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* !defined(__ARCH_TRIO_H__) */
diff --git a/arch/tile/include/arch/trio_constants.h b/arch/tile/include/arch/trio_constants.h
new file mode 100644
index 00000000000..628b045436b
--- /dev/null
+++ b/arch/tile/include/arch/trio_constants.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+
+#ifndef __ARCH_TRIO_CONSTANTS_H__
+#define __ARCH_TRIO_CONSTANTS_H__
+
+#define TRIO_NUM_ASIDS 16
+#define TRIO_NUM_TLBS_PER_ASID 16
+
+#define TRIO_NUM_TPIO_REGIONS 8
+#define TRIO_LOG2_NUM_TPIO_REGIONS 3
+
+#define TRIO_NUM_MAP_MEM_REGIONS 16
+#define TRIO_LOG2_NUM_MAP_MEM_REGIONS 4
+#define TRIO_NUM_MAP_SQ_REGIONS 8
+#define TRIO_LOG2_NUM_MAP_SQ_REGIONS 3
+
+#define TRIO_LOG2_NUM_SQ_FIFO_ENTRIES 6
+
+#define TRIO_NUM_PUSH_DMA_RINGS 32
+
+#define TRIO_NUM_PULL_DMA_RINGS 32
+
+#endif /* __ARCH_TRIO_CONSTANTS_H__ */
diff --git a/arch/tile/include/arch/trio_def.h b/arch/tile/include/arch/trio_def.h
new file mode 100644
index 00000000000..e80500317dc
--- /dev/null
+++ b/arch/tile/include/arch/trio_def.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_TRIO_DEF_H__
+#define __ARCH_TRIO_DEF_H__
+#define TRIO_CFG_REGION_ADDR__REG_SHIFT 0
+#define TRIO_CFG_REGION_ADDR__INTFC_SHIFT 16
+#define TRIO_CFG_REGION_ADDR__INTFC_VAL_TRIO 0x0
+#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE 0x1
+#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD 0x2
+#define TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED 0x3
+#define TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT 18
+#define TRIO_CFG_REGION_ADDR__PROT_SHIFT 20
+#define TRIO_PIO_REGIONS_ADDR__REGION_SHIFT 32
+#define TRIO_MAP_MEM_REG_INT0 0x1000000000
+#define TRIO_MAP_MEM_REG_INT1 0x1000000008
+#define TRIO_MAP_MEM_REG_INT2 0x1000000010
+#define TRIO_MAP_MEM_REG_INT3 0x1000000018
+#define TRIO_MAP_MEM_REG_INT4 0x1000000020
+#define TRIO_MAP_MEM_REG_INT5 0x1000000028
+#define TRIO_MAP_MEM_REG_INT6 0x1000000030
+#define TRIO_MAP_MEM_REG_INT7 0x1000000038
+#define TRIO_MAP_MEM_LIM__ADDR_SHIFT 12
+#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_UNORDERED 0x0
+#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_STRICT 0x1
+#define TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD 0x2
+#define TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT 30
+#endif /* !defined(__ARCH_TRIO_DEF_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_intfc.h b/arch/tile/include/arch/trio_pcie_intfc.h
new file mode 100644
index 00000000000..0487fdb9d58
--- /dev/null
+++ b/arch/tile/include/arch/trio_pcie_intfc.h
@@ -0,0 +1,229 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_TRIO_PCIE_INTFC_H__
+#define __ARCH_TRIO_PCIE_INTFC_H__
+
+#include <arch/abi.h>
+#include <arch/trio_pcie_intfc_def.h>
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Port Configuration.
+ * Configuration of the PCIe Port
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /* Provides the state of the strapping pins for this port. */
+    uint_reg_t strap_state      : 3;
+    /* Reserved. */
+    uint_reg_t __reserved_0     : 1;
+    /*
+     * When 1, the device type will be overridden using OVD_DEV_TYPE_VAL.
+     * When 0, the device type is determined based on the STRAP_STATE.
+     */
+    uint_reg_t ovd_dev_type     : 1;
+    /* Provides the device type when OVD_DEV_TYPE is 1. */
+    uint_reg_t ovd_dev_type_val : 4;
+    /* Determines how link is trained. */
+    uint_reg_t train_mode       : 2;
+    /* Reserved. */
+    uint_reg_t __reserved_1     : 1;
+    /*
+     * For PCIe, used to flip physical RX lanes that were not properly wired.
+     *  This is not the same as lane reversal which is handled automatically
+     * during link training.  When 0, RX Lane0 must be wired to the link
+     * partner (either to its Lane0 or it's LaneN).  When RX_LANE_FLIP is 1,
+     * the highest numbered lane for this port becomes Lane0 and Lane0 does
+     * NOT have to be wired to the link partner.
+     */
+    uint_reg_t rx_lane_flip     : 1;
+    /*
+     * For PCIe, used to flip physical TX lanes that were not properly wired.
+     *  This is not the same as lane reversal which is handled automatically
+     * during link training.  When 0, TX Lane0 must be wired to the link
+     * partner (either to its Lane0 or it's LaneN).  When TX_LANE_FLIP is 1,
+     * the highest numbered lane for this port becomes Lane0 and Lane0 does
+     * NOT have to be wired to the link partner.
+     */
+    uint_reg_t tx_lane_flip     : 1;
+    /*
+     * For StreamIO port, configures the width of the port when TRAIN_MODE is
+     * not STRAP.
+     */
+    uint_reg_t stream_width     : 2;
+    /*
+     * For StreamIO port, configures the rate of the port when TRAIN_MODE is
+     * not STRAP.
+     */
+    uint_reg_t stream_rate      : 2;
+    /* Reserved. */
+    uint_reg_t __reserved_2     : 46;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved_2     : 46;
+    uint_reg_t stream_rate      : 2;
+    uint_reg_t stream_width     : 2;
+    uint_reg_t tx_lane_flip     : 1;
+    uint_reg_t rx_lane_flip     : 1;
+    uint_reg_t __reserved_1     : 1;
+    uint_reg_t train_mode       : 2;
+    uint_reg_t ovd_dev_type_val : 4;
+    uint_reg_t ovd_dev_type     : 1;
+    uint_reg_t __reserved_0     : 1;
+    uint_reg_t strap_state      : 3;
+#endif
+  };
+
+  uint_reg_t word;
+} TRIO_PCIE_INTFC_PORT_CONFIG_t;
+
+/*
+ * Port Status.
+ * Status of the PCIe Port.  This register applies to the StreamIO port when
+ * StreamIO is enabled.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /*
+     * Indicates the DL state of the port.  When 1, the port is up and ready
+     * to receive traffic.
+     */
+    uint_reg_t dl_up        : 1;
+    /*
+     * Indicates the number of times the link has gone down.  Clears on read.
+     */
+    uint_reg_t dl_down_cnt  : 7;
+    /* Indicates the SERDES PLL has spun up and is providing a valid clock. */
+    uint_reg_t clock_ready  : 1;
+    /* Reserved. */
+    uint_reg_t __reserved_0 : 7;
+    /* Device revision ID. */
+    uint_reg_t device_rev   : 8;
+    /* Link state (PCIe). */
+    uint_reg_t ltssm_state  : 6;
+    /* Link power management state (PCIe). */
+    uint_reg_t pm_state     : 3;
+    /* Reserved. */
+    uint_reg_t __reserved_1 : 31;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved_1 : 31;
+    uint_reg_t pm_state     : 3;
+    uint_reg_t ltssm_state  : 6;
+    uint_reg_t device_rev   : 8;
+    uint_reg_t __reserved_0 : 7;
+    uint_reg_t clock_ready  : 1;
+    uint_reg_t dl_down_cnt  : 7;
+    uint_reg_t dl_up        : 1;
+#endif
+  };
+
+  uint_reg_t word;
+} TRIO_PCIE_INTFC_PORT_STATUS_t;
+
+/*
+ * Transmit FIFO Control.
+ * Contains TX FIFO thresholds.  These registers are for diagnostics purposes
+ * only.  Changing these values causes undefined behavior.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /*
+     * Almost-Empty level for TX0 data.  Typically set to at least
+     * roundup(38.0*M/N) where N=tclk frequency and M=MAC symbol rate in MHz
+     * for a x4 port (250MHz).
+     */
+    uint_reg_t tx0_data_ae_lvl : 7;
+    /* Reserved. */
+    uint_reg_t __reserved_0    : 1;
+    /* Almost-Empty level for TX1 data. */
+    uint_reg_t tx1_data_ae_lvl : 7;
+    /* Reserved. */
+    uint_reg_t __reserved_1    : 1;
+    /* Almost-Full level for TX0 data. */
+    uint_reg_t tx0_data_af_lvl : 7;
+    /* Reserved. */
+    uint_reg_t __reserved_2    : 1;
+    /* Almost-Full level for TX1 data. */
+    uint_reg_t tx1_data_af_lvl : 7;
+    /* Reserved. */
+    uint_reg_t __reserved_3    : 1;
+    /* Almost-Full level for TX0 info. */
+    uint_reg_t tx0_info_af_lvl : 5;
+    /* Reserved. */
+    uint_reg_t __reserved_4    : 3;
+    /* Almost-Full level for TX1 info. */
+    uint_reg_t tx1_info_af_lvl : 5;
+    /* Reserved. */
+    uint_reg_t __reserved_5    : 3;
+    /*
+     * This register provides performance adjustment for high bandwidth
+     * flows.  The MAC will assert almost-full to TRIO if non-posted credits
+     * fall below this level.  Note that setting this larger than the initial
+     * PORT_CREDIT.NPH value will cause READS to never be sent.  If the
+     * initial credit value from the link partner is smaller than this value
+     * when the link comes up, the value will be reset to the initial credit
+     * value to prevent lockup.
+     */
+    uint_reg_t min_np_credits  : 8;
+    /*
+     * This register provides performance adjustment for high bandwidth
+     * flows.  The MAC will assert almost-full to TRIO if posted credits fall
+     * below this level.  Note that setting this larger than the initial
+     * PORT_CREDIT.PH value will cause WRITES to never be sent.  If the
+     * initial credit value from the link partner is smaller than this value
+     * when the link comes up, the value will be reset to the initial credit
+     * value to prevent lockup.
+     */
+    uint_reg_t min_p_credits   : 8;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t min_p_credits   : 8;
+    uint_reg_t min_np_credits  : 8;
+    uint_reg_t __reserved_5    : 3;
+    uint_reg_t tx1_info_af_lvl : 5;
+    uint_reg_t __reserved_4    : 3;
+    uint_reg_t tx0_info_af_lvl : 5;
+    uint_reg_t __reserved_3    : 1;
+    uint_reg_t tx1_data_af_lvl : 7;
+    uint_reg_t __reserved_2    : 1;
+    uint_reg_t tx0_data_af_lvl : 7;
+    uint_reg_t __reserved_1    : 1;
+    uint_reg_t tx1_data_ae_lvl : 7;
+    uint_reg_t __reserved_0    : 1;
+    uint_reg_t tx0_data_ae_lvl : 7;
+#endif
+  };
+
+  uint_reg_t word;
+} TRIO_PCIE_INTFC_TX_FIFO_CTL_t;
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* !defined(__ARCH_TRIO_PCIE_INTFC_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_intfc_def.h b/arch/tile/include/arch/trio_pcie_intfc_def.h
new file mode 100644
index 00000000000..d3fd6781fb2
--- /dev/null
+++ b/arch/tile/include/arch/trio_pcie_intfc_def.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_TRIO_PCIE_INTFC_DEF_H__
+#define __ARCH_TRIO_PCIE_INTFC_DEF_H__
+#define TRIO_PCIE_INTFC_MAC_INT_STS 0x0000
+#define TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK  0xf000
+#define TRIO_PCIE_INTFC_PORT_CONFIG 0x0018
+#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_DISABLED 0x0
+#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT 0x1
+#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC 0x2
+#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1 0x3
+#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1 0x4
+#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_XLINK 0x5
+#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_STREAM_X1 0x6
+#define TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_STREAM_X4 0x7
+#define TRIO_PCIE_INTFC_PORT_STATUS 0x0020
+#define TRIO_PCIE_INTFC_TX_FIFO_CTL 0x0050
+#endif /* !defined(__ARCH_TRIO_PCIE_INTFC_DEF_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_rc.h b/arch/tile/include/arch/trio_pcie_rc.h
new file mode 100644
index 00000000000..6a25d0aca85
--- /dev/null
+++ b/arch/tile/include/arch/trio_pcie_rc.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_TRIO_PCIE_RC_H__
+#define __ARCH_TRIO_PCIE_RC_H__
+
+#include <arch/abi.h>
+#include <arch/trio_pcie_rc_def.h>
+
+#ifndef __ASSEMBLER__
+
+/* Device Capabilities Register. */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /*
+     * Max_Payload_Size Supported, writablethrough the MAC_STANDARD interface
+     */
+    uint_reg_t mps_sup                    : 3;
+    /*
+     * This field is writable through the MAC_STANDARD interface.  However,
+     * Phantom Function is not  supported. Therefore, the application must
+     * not write any value other than 0x0 to this  field.
+     */
+    uint_reg_t phantom_function_supported : 2;
+    /* This bit is writable through the MAC_STANDARD interface. */
+    uint_reg_t ext_tag_field_supported    : 1;
+    /* Reserved. */
+    uint_reg_t __reserved_0               : 3;
+    /* Endpoint L1 Acceptable Latency Must be 0x0 for non-Endpoint devices. */
+    uint_reg_t l1_lat                     : 3;
+    /*
+     * Undefined since PCI Express 1.1 (Was Attention Button Present for PCI
+     * Express 1.0a)
+     */
+    uint_reg_t r1                         : 1;
+    /*
+     * Undefined since PCI Express 1.1 (Was Attention Indicator Present for
+     * PCI  Express 1.0a)
+     */
+    uint_reg_t r2                         : 1;
+    /*
+     * Undefined since PCI Express 1.1 (Was Power Indicator Present for PCI
+     * Express 1.0a)
+     */
+    uint_reg_t r3                         : 1;
+    /*
+     * Role-Based Error Reporting, writable through the MAC_STANDARD
+     * interface.  Required to be set for device compliant to 1.1  spec and
+     * later.
+     */
+    uint_reg_t rer                        : 1;
+    /* Reserved. */
+    uint_reg_t __reserved_1               : 2;
+    /* Captured Slot Power Limit Value Upstream port only. */
+    uint_reg_t slot_pwr_lim               : 8;
+    /* Captured Slot Power Limit Scale Upstream port only. */
+    uint_reg_t slot_pwr_scale             : 2;
+    /* Reserved. */
+    uint_reg_t __reserved_2               : 4;
+    /* Endpoint L0s Acceptable LatencyMust be 0x0 for non-Endpoint devices. */
+    uint_reg_t l0s_lat                    : 1;
+    /* Reserved. */
+    uint_reg_t __reserved_3               : 31;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved_3               : 31;
+    uint_reg_t l0s_lat                    : 1;
+    uint_reg_t __reserved_2               : 4;
+    uint_reg_t slot_pwr_scale             : 2;
+    uint_reg_t slot_pwr_lim               : 8;
+    uint_reg_t __reserved_1               : 2;
+    uint_reg_t rer                        : 1;
+    uint_reg_t r3                         : 1;
+    uint_reg_t r2                         : 1;
+    uint_reg_t r1                         : 1;
+    uint_reg_t l1_lat                     : 3;
+    uint_reg_t __reserved_0               : 3;
+    uint_reg_t ext_tag_field_supported    : 1;
+    uint_reg_t phantom_function_supported : 2;
+    uint_reg_t mps_sup                    : 3;
+#endif
+  };
+
+  uint_reg_t word;
+} TRIO_PCIE_RC_DEVICE_CAP_t;
+
+/* Device Control Register. */
+
+__extension__
+typedef union
+{
+  struct
+  {
+#ifndef __BIG_ENDIAN__
+    /* Correctable Error Reporting Enable */
+    uint_reg_t cor_err_ena      : 1;
+    /* Non-Fatal Error Reporting Enable */
+    uint_reg_t nf_err_ena       : 1;
+    /* Fatal Error Reporting Enable */
+    uint_reg_t fatal_err_ena    : 1;
+    /* Unsupported Request Reporting Enable */
+    uint_reg_t ur_ena           : 1;
+    /* Relaxed orderring enable */
+    uint_reg_t ro_ena           : 1;
+    /* Max Payload Size */
+    uint_reg_t max_payload_size : 3;
+    /* Extended Tag Field Enable */
+    uint_reg_t ext_tag          : 1;
+    /* Phantom Function Enable */
+    uint_reg_t ph_fn_ena        : 1;
+    /* AUX Power PM Enable */
+    uint_reg_t aux_pm_ena       : 1;
+    /* Enable NoSnoop */
+    uint_reg_t no_snoop         : 1;
+    /* Max read request size */
+    uint_reg_t max_read_req_sz  : 3;
+    /* Reserved. */
+    uint_reg_t __reserved       : 49;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t __reserved       : 49;
+    uint_reg_t max_read_req_sz  : 3;
+    uint_reg_t no_snoop         : 1;
+    uint_reg_t aux_pm_ena       : 1;
+    uint_reg_t ph_fn_ena        : 1;
+    uint_reg_t ext_tag          : 1;
+    uint_reg_t max_payload_size : 3;
+    uint_reg_t ro_ena           : 1;
+    uint_reg_t ur_ena           : 1;
+    uint_reg_t fatal_err_ena    : 1;
+    uint_reg_t nf_err_ena       : 1;
+    uint_reg_t cor_err_ena      : 1;
+#endif
+  };
+
+  uint_reg_t word;
+} TRIO_PCIE_RC_DEVICE_CONTROL_t;
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* !defined(__ARCH_TRIO_PCIE_RC_H__) */
diff --git a/arch/tile/include/arch/trio_pcie_rc_def.h b/arch/tile/include/arch/trio_pcie_rc_def.h
new file mode 100644
index 00000000000..74081a65b6f
--- /dev/null
+++ b/arch/tile/include/arch/trio_pcie_rc_def.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_TRIO_PCIE_RC_DEF_H__
+#define __ARCH_TRIO_PCIE_RC_DEF_H__
+#define TRIO_PCIE_RC_DEVICE_CAP 0x0074
+#define TRIO_PCIE_RC_DEVICE_CONTROL 0x0078
+#define TRIO_PCIE_RC_DEVICE_ID_VEN_ID 0x0000
+#define TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT 16
+#define TRIO_PCIE_RC_REVISION_ID 0x0008
+#endif /* !defined(__ARCH_TRIO_PCIE_RC_DEF_H__) */
diff --git a/arch/tile/include/arch/trio_shm.h b/arch/tile/include/arch/trio_shm.h
new file mode 100644
index 00000000000..3382e38245a
--- /dev/null
+++ b/arch/tile/include/arch/trio_shm.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+
+#ifndef __ARCH_TRIO_SHM_H__
+#define __ARCH_TRIO_SHM_H__
+
+#include <arch/abi.h>
+#include <arch/trio_shm_def.h>
+
+#ifndef __ASSEMBLER__
+/**
+ * TRIO DMA Descriptor.
+ * The TRIO DMA descriptor is written by software and consumed by hardware.
+ * It is used to specify the location of transaction data in the IO and Tile
+ * domains.
+ */
+
+__extension__
+typedef union
+{
+  struct
+  {
+    /* Word 0 */
+
+#ifndef __BIG_ENDIAN__
+    /** Tile side virtual address. */
+    int_reg_t va           : 42;
+    /**
+     * Encoded size of buffer used on push DMA when C=1:
+     * 0 = 128 bytes
+     * 1 = 256 bytes
+     * 2 = 512 bytes
+     * 3 = 1024 bytes
+     * 4 = 1664 bytes
+     * 5 = 4096 bytes
+     * 6 = 10368 bytes
+     * 7 = 16384 bytes
+     */
+    uint_reg_t bsz          : 3;
+    /**
+     * Chaining designation.  Always zero for pull DMA
+     * 0 : Unchained buffer pointer
+     * 1 : Chained buffer pointer.  Next buffer descriptor (e.g. VA) stored
+     * in 1st 8-bytes in buffer.  For chained buffers, first 8-bytes of each
+     * buffer contain the next buffer descriptor formatted exactly like a PDE
+     * buffer descriptor.  This allows a chained PDE buffer to be sent using
+     * push DMA.
+     */
+    uint_reg_t c            : 1;
+    /**
+     * Notification interrupt will be delivered when the transaction has
+     * completed (all data has been read from or written to the Tile-side
+     * buffer).
+     */
+    uint_reg_t notif        : 1;
+    /**
+     * When 0, the XSIZE field specifies the total byte count for the
+     * transaction.  When 1, the XSIZE field is encoded as 2^(N+14) for N in
+     * {0..6}:
+     * 0 = 16KB
+     * 1 = 32KB
+     * 2 = 64KB
+     * 3 = 128KB
+     * 4 = 256KB
+     * 5 = 512KB
+     * 6 = 1MB
+     * All other encodings of the XSIZE field are reserved when SMOD=1
+     */
+    uint_reg_t smod         : 1;
+    /**
+     * Total number of bytes to move for this transaction.   When SMOD=1,
+     * this field is encoded - see SMOD description.
+     */
+    uint_reg_t xsize        : 14;
+    /** Reserved. */
+    uint_reg_t __reserved_0 : 1;
+    /**
+     * Generation number.  Used to indicate a valid descriptor in ring.  When
+     * a new descriptor is written into the ring, software must toggle this
+     * bit.  The net effect is that the GEN bit being written into new
+     * descriptors toggles each time the ring tail pointer wraps.
+     */
+    uint_reg_t gen          : 1;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t gen          : 1;
+    uint_reg_t __reserved_0 : 1;
+    uint_reg_t xsize        : 14;
+    uint_reg_t smod         : 1;
+    uint_reg_t notif        : 1;
+    uint_reg_t c            : 1;
+    uint_reg_t bsz          : 3;
+    int_reg_t va           : 42;
+#endif
+
+    /* Word 1 */
+
+#ifndef __BIG_ENDIAN__
+    /** IO-side address */
+    uint_reg_t io_address : 64;
+#else   /* __BIG_ENDIAN__ */
+    uint_reg_t io_address : 64;
+#endif
+
+  };
+
+  /** Word access */
+  uint_reg_t words[2];
+} TRIO_DMA_DESC_t;
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* !defined(__ARCH_TRIO_SHM_H__) */
diff --git a/arch/tile/include/arch/trio_shm_def.h b/arch/tile/include/arch/trio_shm_def.h
new file mode 100644
index 00000000000..72a59c88b06
--- /dev/null
+++ b/arch/tile/include/arch/trio_shm_def.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_TRIO_SHM_DEF_H__
+#define __ARCH_TRIO_SHM_DEF_H__
+#endif /* !defined(__ARCH_TRIO_SHM_DEF_H__) */
diff --git a/arch/tile/include/arch/usb_host.h b/arch/tile/include/arch/usb_host.h
new file mode 100644
index 00000000000..d09f3268396
--- /dev/null
+++ b/arch/tile/include/arch/usb_host.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_USB_HOST_H__
+#define __ARCH_USB_HOST_H__
+
+#include <arch/abi.h>
+#include <arch/usb_host_def.h>
+
+#ifndef __ASSEMBLER__
+#endif /* !defined(__ASSEMBLER__) */
+
+#endif /* !defined(__ARCH_USB_HOST_H__) */
diff --git a/arch/tile/include/arch/usb_host_def.h b/arch/tile/include/arch/usb_host_def.h
new file mode 100644
index 00000000000..aeed7753e8e
--- /dev/null
+++ b/arch/tile/include/arch/usb_host_def.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* Machine-generated file; do not edit. */
+
+#ifndef __ARCH_USB_HOST_DEF_H__
+#define __ARCH_USB_HOST_DEF_H__
+#endif /* !defined(__ARCH_USB_HOST_DEF_H__) */
diff --git a/arch/tile/include/asm/Kbuild b/arch/tile/include/asm/Kbuild
index 143473e3a0b..5bd71994452 100644
--- a/arch/tile/include/asm/Kbuild
+++ b/arch/tile/include/asm/Kbuild
@@ -9,7 +9,6 @@ header-y += hardwall.h
 generic-y += bug.h
 generic-y += bugs.h
 generic-y += cputime.h
-generic-y += device.h
 generic-y += div64.h
 generic-y += emergency-restart.h
 generic-y += errno.h
@@ -17,7 +16,6 @@ generic-y += fb.h
 generic-y += fcntl.h
 generic-y += ioctl.h
 generic-y += ioctls.h
-generic-y += ipc.h
 generic-y += ipcbuf.h
 generic-y += irq_regs.h
 generic-y += kdebug.h
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
index 392e5333dd8..a9a529964e0 100644
--- a/arch/tile/include/asm/cache.h
+++ b/arch/tile/include/asm/cache.h
@@ -27,11 +27,17 @@
 #define L2_CACHE_ALIGN(x)       (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
 
 /*
- * TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN.
+ * TILEPro I/O is not always coherent (networking typically uses coherent
+ * I/O, but PCI traffic does not) and setting ARCH_DMA_MINALIGN to the
+ * L2 cacheline size helps ensure that kernel heap allocations are aligned.
+ * TILE-Gx I/O is always coherent when used on hash-for-home pages.
+ *
+ * However, it's possible at runtime to request not to use hash-for-home
+ * for the kernel heap, in which case the kernel will use flush-and-inval
+ * to manage coherence.  As a result, we use L2_CACHE_BYTES for the
+ * DMA minimum alignment to avoid false sharing in the kernel heap.
  */
-#ifndef __tilegx__
 #define ARCH_DMA_MINALIGN       L2_CACHE_BYTES
-#endif
 
 /* use the cache line size for the L2, which is where it counts */
 #define SMP_CACHE_BYTES_SHIFT   L2_CACHE_SHIFT
diff --git a/arch/tile/include/asm/checksum.h b/arch/tile/include/asm/checksum.h
index a120766c726..b21a2fdec9f 100644
--- a/arch/tile/include/asm/checksum.h
+++ b/arch/tile/include/asm/checksum.h
@@ -21,4 +21,22 @@
 __wsum do_csum(const unsigned char *buff, int len);
 #define do_csum do_csum
 
+/*
+ * Return the sum of all the 16-bit subwords in a long.
+ * This sums two subwords on a 32-bit machine, and four on 64 bits.
+ * The implementation does two vector adds to capture any overflow.
+ */
+static inline unsigned int csum_long(unsigned long x)
+{
+        unsigned long ret;
+#ifdef __tilegx__
+        ret = __insn_v2sadu(x, 0);
+        ret = __insn_v2sadu(ret, 0);
+#else
+        ret = __insn_sadh_u(x, 0);
+        ret = __insn_sadh_u(ret, 0);
+#endif
+        return ret;
+}
+
 #endif /* _ASM_TILE_CHECKSUM_H */
diff --git a/arch/tile/include/asm/device.h b/arch/tile/include/asm/device.h
new file mode 100644
index 00000000000..5182705bd05
--- /dev/null
+++ b/arch/tile/include/asm/device.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2010 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ * Arch specific extensions to struct device
+ */
+
+#ifndef _ASM_TILE_DEVICE_H
+#define _ASM_TILE_DEVICE_H
+
+struct dev_archdata {
+        /* DMA operations on that device */
+        struct dma_map_ops      *dma_ops;
+
+        /* Offset of the DMA address from the PA. */
+        dma_addr_t              dma_offset;
+
+        /* Highest DMA address that can be generated by this device. */
+        dma_addr_t              max_direct_dma_addr;
+};
+
+struct pdev_archdata {
+};
+
+#endif /* _ASM_TILE_DEVICE_H */
diff --git a/arch/tile/include/asm/dma-mapping.h b/arch/tile/include/asm/dma-mapping.h
index eaa06d175b3..4b6247d1a31 100644
--- a/arch/tile/include/asm/dma-mapping.h
+++ b/arch/tile/include/asm/dma-mapping.h
@@ -20,69 +20,80 @@
 #include <linux/cache.h>
 #include <linux/io.h>
 
-/*
- * Note that on x86 and powerpc, there is a "struct dma_mapping_ops"
- * that is used for all the DMA operations.  For now, we don't have an
- * equivalent on tile, because we only have a single way of doing DMA.
- * (Tilera bug 7994 to use dma_mapping_ops.)
- */
+extern struct dma_map_ops *tile_dma_map_ops;
+extern struct dma_map_ops *gx_pci_dma_map_ops;
+extern struct dma_map_ops *gx_legacy_pci_dma_map_ops;
+
+static inline struct dma_map_ops *get_dma_ops(struct device *dev)
+{
+        if (dev && dev->archdata.dma_ops)
+                return dev->archdata.dma_ops;
+        else
+                return tile_dma_map_ops;
+}
+
+static inline dma_addr_t get_dma_offset(struct device *dev)
+{
+        return dev->archdata.dma_offset;
+}
+
+static inline void set_dma_offset(struct device *dev, dma_addr_t off)
+{
+        dev->archdata.dma_offset = off;
+}
 
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-                          enum dma_data_direction);
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
-                             size_t size, enum dma_data_direction);
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-               enum dma_data_direction);
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-                         int nhwentries, enum dma_data_direction);
-extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
-                               unsigned long offset, size_t size,
-                               enum dma_data_direction);
-extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
-                           size_t size, enum dma_data_direction);
-extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
-                                int nelems, enum dma_data_direction);
-extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
-                                   int nelems, enum dma_data_direction);
-
-
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t flag);
-
-void dma_free_coherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle);
-
-extern void dma_sync_single_for_cpu(struct device *, dma_addr_t, size_t,
-                                    enum dma_data_direction);
-extern void dma_sync_single_for_device(struct device *, dma_addr_t,
-                                       size_t, enum dma_data_direction);
-extern void dma_sync_single_range_for_cpu(struct device *, dma_addr_t,
-                                          unsigned long offset, size_t,
-                                          enum dma_data_direction);
-extern void dma_sync_single_range_for_device(struct device *, dma_addr_t,
-                                             unsigned long offset, size_t,
-                                             enum dma_data_direction);
-extern void dma_cache_sync(struct device *dev, void *vaddr, size_t,
-                           enum dma_data_direction);
+static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        return paddr + get_dma_offset(dev);
+}
+
+static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        return daddr - get_dma_offset(dev);
+}
+
+static inline void dma_mark_clean(void *addr, size_t size) {}
+
+#include <asm-generic/dma-mapping-common.h>
+
+static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
+{
+        dev->archdata.dma_ops = ops;
+}
+
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+        if (!dev->dma_mask)
+                return 0;
+
+        return addr + size - 1 <= *dev->dma_mask;
+}
 
 static inline int
 dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
-        return 0;
+        return get_dma_ops(dev)->mapping_error(dev, dma_addr);
 }
 
 static inline int
 dma_supported(struct device *dev, u64 mask)
 {
-        return 1;
+        return get_dma_ops(dev)->dma_supported(dev, mask);
 }
 
 static inline int
 dma_set_mask(struct device *dev, u64 mask)
 {
+        struct dma_map_ops *dma_ops = get_dma_ops(dev);
+
+        /* Handle legacy PCI devices with limited memory addressability. */
+        if ((dma_ops == gx_pci_dma_map_ops) && (mask <= DMA_BIT_MASK(32))) {
+                set_dma_ops(dev, gx_legacy_pci_dma_map_ops);
+                set_dma_offset(dev, 0);
+                if (mask > dev->archdata.max_direct_dma_addr)
+                        mask = dev->archdata.max_direct_dma_addr;
+        }
+
         if (!dev->dma_mask || !dma_supported(dev, mask))
                 return -EIO;
 
@@ -91,4 +102,43 @@ dma_set_mask(struct device *dev, u64 mask)
         return 0;
 }
 
+static inline void *dma_alloc_attrs(struct device *dev, size_t size,
+                                    dma_addr_t *dma_handle, gfp_t flag,
+                                    struct dma_attrs *attrs)
+{
+        struct dma_map_ops *dma_ops = get_dma_ops(dev);
+        void *cpu_addr;
+
+        cpu_addr = dma_ops->alloc(dev, size, dma_handle, flag, attrs);
+
+        debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
+
+        return cpu_addr;
+}
+
+static inline void dma_free_attrs(struct device *dev, size_t size,
+                                  void *cpu_addr, dma_addr_t dma_handle,
+                                  struct dma_attrs *attrs)
+{
+        struct dma_map_ops *dma_ops = get_dma_ops(dev);
+
+        debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
+
+        dma_ops->free(dev, size, cpu_addr, dma_handle, attrs);
+}
+
+#define dma_alloc_coherent(d, s, h, f) dma_alloc_attrs(d, s, h, f, NULL)
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_attrs(d, s, h, f, NULL)
+#define dma_free_coherent(d, s, v, h) dma_free_attrs(d, s, v, h, NULL)
+#define dma_free_noncoherent(d, s, v, h) dma_free_attrs(d, s, v, h, NULL)
+
+/*
+ * dma_alloc_noncoherent() is #defined to return coherent memory,
+ * so there's no need to do any flushing here.
+ */
+static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
+                                  enum dma_data_direction direction)
+{
+}
+
 #endif /* _ASM_TILE_DMA_MAPPING_H */
diff --git a/arch/tile/include/asm/fixmap.h b/arch/tile/include/asm/fixmap.h
index c66f7933bea..e16dbf929cb 100644
--- a/arch/tile/include/asm/fixmap.h
+++ b/arch/tile/include/asm/fixmap.h
@@ -45,15 +45,23 @@
  *
  * TLB entries of such buffers will not be flushed across
  * task switches.
- *
- * We don't bother with a FIX_HOLE since above the fixmaps
- * is unmapped memory in any case.
  */
 enum fixed_addresses {
+#ifdef __tilegx__
+        /*
+         * TILEPro has unmapped memory above so the hole isn't needed,
+         * and in any case the hole pushes us over a single 16MB pmd.
+         */
+        FIX_HOLE,
+#endif
 #ifdef CONFIG_HIGHMEM
         FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
         FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
 #endif
+#ifdef __tilegx__  /* see homecache.c */
+        FIX_HOMECACHE_BEGIN,
+        FIX_HOMECACHE_END = FIX_HOMECACHE_BEGIN+(NR_CPUS)-1,
+#endif
         __end_of_permanent_fixed_addresses,
 
         /*
diff --git a/arch/tile/include/asm/homecache.h b/arch/tile/include/asm/homecache.h
index a8243865d49..7b777132864 100644
--- a/arch/tile/include/asm/homecache.h
+++ b/arch/tile/include/asm/homecache.h
@@ -79,10 +79,17 @@ extern void homecache_change_page_home(struct page *, int order, int home);
 /*
  * Flush a page out of whatever cache(s) it is in.
  * This is more than just finv, since it properly handles waiting
- * for the data to reach memory on tilepro, but it can be quite
- * heavyweight, particularly on hash-for-home memory.
+ * for the data to reach memory, but it can be quite
+ * heavyweight, particularly on incoherent or immutable memory.
  */
-extern void homecache_flush_cache(struct page *, int order);
+extern void homecache_finv_page(struct page *);
+
+/*
+ * Flush a page out of the specified home cache.
+ * Note that the specified home need not be the actual home of the page,
+ * as for example might be the case when coordinating with I/O devices.
+ */
+extern void homecache_finv_map_page(struct page *, int home);
 
 /*
  * Allocate a page with the given GFP flags, home, and optionally
@@ -104,10 +111,10 @@ extern struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
  * routines use homecache_change_page_home() to reset the home
  * back to the default before returning the page to the allocator.
  */
+void __homecache_free_pages(struct page *, unsigned int order);
 void homecache_free_pages(unsigned long addr, unsigned int order);
-#define homecache_free_page(page) \
-  homecache_free_pages((page), 0)
-
+#define __homecache_free_page(page) __homecache_free_pages((page), 0)
+#define homecache_free_page(page) homecache_free_pages((page), 0)
 
 
 /*
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index d2152deb1f3..2a9b293fece 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -62,6 +62,92 @@ extern void iounmap(volatile void __iomem *addr);
 #define mm_ptov(addr)           ((void *)phys_to_virt(addr))
 #define mm_vtop(addr)           ((unsigned long)virt_to_phys(addr))
 
+#if CHIP_HAS_MMIO()
+
+/*
+ * We use inline assembly to guarantee that the compiler does not
+ * split an access into multiple byte-sized accesses as it might
+ * sometimes do if a register data structure is marked "packed".
+ * Obviously on tile we can't tolerate such an access being
+ * actually unaligned, but we want to avoid the case where the
+ * compiler conservatively would generate multiple accesses even
+ * for an aligned read or write.
+ */
+
+static inline u8 __raw_readb(const volatile void __iomem *addr)
+{
+        return *(const volatile u8 __force *)addr;
+}
+
+static inline u16 __raw_readw(const volatile void __iomem *addr)
+{
+        u16 ret;
+        asm volatile("ld2u %0, %1" : "=r" (ret) : "r" (addr));
+        barrier();
+        return le16_to_cpu(ret);
+}
+
+static inline u32 __raw_readl(const volatile void __iomem *addr)
+{
+        u32 ret;
+        /* Sign-extend to conform to u32 ABI sign-extension convention. */
+        asm volatile("ld4s %0, %1" : "=r" (ret) : "r" (addr));
+        barrier();
+        return le32_to_cpu(ret);
+}
+
+static inline u64 __raw_readq(const volatile void __iomem *addr)
+{
+        u64 ret;
+        asm volatile("ld %0, %1" : "=r" (ret) : "r" (addr));
+        barrier();
+        return le64_to_cpu(ret);
+}
+
+static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
+{
+        *(volatile u8 __force *)addr = val;
+}
+
+static inline void __raw_writew(u16 val, volatile void __iomem *addr)
+{
+        asm volatile("st2 %0, %1" :: "r" (addr), "r" (cpu_to_le16(val)));
+}
+
+static inline void __raw_writel(u32 val, volatile void __iomem *addr)
+{
+        asm volatile("st4 %0, %1" :: "r" (addr), "r" (cpu_to_le32(val)));
+}
+
+static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
+{
+        asm volatile("st %0, %1" :: "r" (addr), "r" (cpu_to_le64(val)));
+}
+
+/*
+ * The on-chip I/O hardware on tilegx is configured with VA=PA for the
+ * kernel's PA range.  The low-level APIs and field names use "va" and
+ * "void *" nomenclature, to be consistent with the general notion
+ * that the addresses in question are virtualizable, but in the kernel
+ * context we are actually manipulating PA values.  (In other contexts,
+ * e.g. access from user space, we do in fact use real virtual addresses
+ * in the va fields.)  To allow readers of the code to understand what's
+ * happening, we direct their attention to this comment by using the
+ * following two functions that just duplicate __va() and __pa().
+ */
+typedef unsigned long tile_io_addr_t;
+static inline tile_io_addr_t va_to_tile_io_addr(void *va)
+{
+        BUILD_BUG_ON(sizeof(phys_addr_t) != sizeof(tile_io_addr_t));
+        return __pa(va);
+}
+static inline void *tile_io_addr_to_va(tile_io_addr_t tile_io_addr)
+{
+        return __va(tile_io_addr);
+}
+
+#else /* CHIP_HAS_MMIO() */
+
 #ifdef CONFIG_PCI
 
 extern u8 _tile_readb(unsigned long addr);
@@ -73,10 +159,19 @@ extern void _tile_writew(u16 val, unsigned long addr);
 extern void _tile_writel(u32 val, unsigned long addr);
 extern void _tile_writeq(u64 val, unsigned long addr);
 
-#else
+#define __raw_readb(addr) _tile_readb((unsigned long)addr)
+#define __raw_readw(addr) _tile_readw((unsigned long)addr)
+#define __raw_readl(addr) _tile_readl((unsigned long)addr)
+#define __raw_readq(addr) _tile_readq((unsigned long)addr)
+#define __raw_writeb(val, addr) _tile_writeb(val, (unsigned long)addr)
+#define __raw_writew(val, addr) _tile_writew(val, (unsigned long)addr)
+#define __raw_writel(val, addr) _tile_writel(val, (unsigned long)addr)
+#define __raw_writeq(val, addr) _tile_writeq(val, (unsigned long)addr)
+
+#else /* CONFIG_PCI */
 
 /*
- * The Tile architecture does not support IOMEM unless PCI is enabled.
+ * The tilepro architecture does not support IOMEM unless PCI is enabled.
  * Unfortunately we can't yet simply not declare these methods,
  * since some generic code that compiles into the kernel, but
  * we never run, uses them unconditionally.
@@ -88,65 +183,58 @@ static inline int iomem_panic(void)
         return 0;
 }
 
-static inline u8 _tile_readb(unsigned long addr)
+static inline u8 readb(unsigned long addr)
 {
         return iomem_panic();
 }
 
-static inline u16 _tile_readw(unsigned long addr)
+static inline u16 _readw(unsigned long addr)
 {
         return iomem_panic();
 }
 
-static inline u32 _tile_readl(unsigned long addr)
+static inline u32 readl(unsigned long addr)
 {
         return iomem_panic();
 }
 
-static inline u64 _tile_readq(unsigned long addr)
+static inline u64 readq(unsigned long addr)
 {
         return iomem_panic();
 }
 
-static inline void _tile_writeb(u8  val, unsigned long addr)
+static inline void writeb(u8  val, unsigned long addr)
 {
         iomem_panic();
 }
 
-static inline void _tile_writew(u16 val, unsigned long addr)
+static inline void writew(u16 val, unsigned long addr)
 {
         iomem_panic();
 }
 
-static inline void _tile_writel(u32 val, unsigned long addr)
+static inline void writel(u32 val, unsigned long addr)
 {
         iomem_panic();
 }
 
-static inline void _tile_writeq(u64 val, unsigned long addr)
+static inline void writeq(u64 val, unsigned long addr)
 {
         iomem_panic();
 }
 
-#endif
+#endif /* CONFIG_PCI */
+
+#endif /* CHIP_HAS_MMIO() */
 
-#define readb(addr) _tile_readb((unsigned long)addr)
-#define readw(addr) _tile_readw((unsigned long)addr)
-#define readl(addr) _tile_readl((unsigned long)addr)
-#define readq(addr) _tile_readq((unsigned long)addr)
-#define writeb(val, addr) _tile_writeb(val, (unsigned long)addr)
-#define writew(val, addr) _tile_writew(val, (unsigned long)addr)
-#define writel(val, addr) _tile_writel(val, (unsigned long)addr)
-#define writeq(val, addr) _tile_writeq(val, (unsigned long)addr)
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_readq readq
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define __raw_writeq writeq
+#define readb __raw_readb
+#define readw __raw_readw
+#define readl __raw_readl
+#define readq __raw_readq
+#define writeb __raw_writeb
+#define writew __raw_writew
+#define writel __raw_writel
+#define writeq __raw_writeq
 
 #define readb_relaxed readb
 #define readw_relaxed readw
diff --git a/arch/tile/include/asm/kmap_types.h b/arch/tile/include/asm/kmap_types.h
index 3d0f2024626..92b28e3e997 100644
--- a/arch/tile/include/asm/kmap_types.h
+++ b/arch/tile/include/asm/kmap_types.h
@@ -23,35 +23,6 @@
  * adds 4MB of required address-space.  For now we leave KM_TYPE_NR
  * set to depth 8.
  */
-enum km_type {
-        KM_TYPE_NR = 8
-};
-
-/*
- * We provide dummy definitions of all the stray values that used to be
- * required for kmap_atomic() and no longer are.
- */
-enum {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_SYNC_ICACHE,
-        KM_SYNC_DCACHE,
-        KM_UML_USERCOPY,
-        KM_IRQ_PTE,
-        KM_NMI,
-        KM_NMI_PTE,
-        KM_KDB
-};
+#define KM_TYPE_NR 8
 
 #endif /* _ASM_TILE_KMAP_TYPES_H */
diff --git a/arch/tile/include/asm/memprof.h b/arch/tile/include/asm/memprof.h
deleted file mode 100644
index 359949be28c..00000000000
--- a/arch/tile/include/asm/memprof.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- *   This program is free software; you can redistribute it and/or
- *   modify it under the terms of the GNU General Public License
- *   as published by the Free Software Foundation, version 2.
- *
- *   This program is distributed in the hope that it will be useful, but
- *   WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- *   NON INFRINGEMENT.  See the GNU General Public License for
- *   more details.
- *
- * The hypervisor's memory controller profiling infrastructure allows
- * the programmer to find out what fraction of the available memory
- * bandwidth is being consumed at each memory controller.  The
- * profiler provides start, stop, and clear operations to allows
- * profiling over a specific time window, as well as an interface for
- * reading the most recent profile values.
- *
- * This header declares IOCTL codes necessary to control memprof.
- */
-#ifndef _ASM_TILE_MEMPROF_H
-#define _ASM_TILE_MEMPROF_H
-
-#include <linux/ioctl.h>
-
-#define MEMPROF_IOCTL_TYPE 0xB4
-#define MEMPROF_IOCTL_START _IO(MEMPROF_IOCTL_TYPE, 0)
-#define MEMPROF_IOCTL_STOP _IO(MEMPROF_IOCTL_TYPE, 1)
-#define MEMPROF_IOCTL_CLEAR _IO(MEMPROF_IOCTL_TYPE, 2)
-
-#endif /* _ASM_TILE_MEMPROF_H */
diff --git a/arch/tile/include/asm/page.h b/arch/tile/include/asm/page.h
index 9d9131e5c55..dd033a4fd62 100644
--- a/arch/tile/include/asm/page.h
+++ b/arch/tile/include/asm/page.h
@@ -174,7 +174,9 @@ static inline __attribute_const__ int get_order(unsigned long size)
 #define MEM_LOW_END             (HALF_VA_SPACE - 1)         /* low half */
 #define MEM_HIGH_START          (-HALF_VA_SPACE)            /* high half */
 #define PAGE_OFFSET             MEM_HIGH_START
-#define _VMALLOC_START          _AC(0xfffffff500000000, UL) /* 4 GB */
+#define FIXADDR_BASE            _AC(0xfffffff400000000, UL) /* 4 GB */
+#define FIXADDR_TOP             _AC(0xfffffff500000000, UL) /* 4 GB */
+#define _VMALLOC_START          FIXADDR_TOP
 #define HUGE_VMAP_BASE          _AC(0xfffffff600000000, UL) /* 4 GB */
 #define MEM_SV_START            _AC(0xfffffff700000000, UL) /* 256 MB */
 #define MEM_SV_INTRPT           MEM_SV_START
@@ -185,9 +187,6 @@ static inline __attribute_const__ int get_order(unsigned long size)
 /* Highest DTLB address we will use */
 #define KERNEL_HIGH_VADDR       MEM_SV_START
 
-/* Since we don't currently provide any fixmaps, we use an impossible VA. */
-#define FIXADDR_TOP             MEM_HV_START
-
 #else /* !__tilegx__ */
 
 /*
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index 32e6cbe8dff..302cdf71cee 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -15,9 +15,13 @@
 #ifndef _ASM_TILE_PCI_H
 #define _ASM_TILE_PCI_H
 
+#include <linux/dma-mapping.h>
 #include <linux/pci.h>
+#include <linux/numa.h>
 #include <asm-generic/pci_iomap.h>
 
+#ifndef __tilegx__
+
 /*
  * Structure of a PCI controller (host bridge)
  */
@@ -41,21 +45,151 @@ struct pci_controller {
 };
 
 /*
+ * This flag tells if the platform is TILEmpower that needs
+ * special configuration for the PLX switch chip.
+ */
+extern int tile_plx_gen1;
+
+static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
+
+#define TILE_NUM_PCIE   2
+
+/*
  * The hypervisor maps the entirety of CPA-space as bus addresses, so
  * bus addresses are physical addresses.  The networking and block
  * device layers use this boolean for bounce buffer decisions.
  */
 #define PCI_DMA_BUS_IS_PHYS     1
 
+/* generic pci stuff */
+#include <asm-generic/pci.h>
+
+#else
+
+#include <asm/page.h>
+#include <gxio/trio.h>
+
+/**
+ * We reserve the hugepage-size address range at the top of the 64-bit address
+ * space to serve as the PCI window, emulating the BAR0 space of an endpoint
+ * device. This window is used by the chip-to-chip applications running on
+ * the RC node. The reason for carving out this window is that Mem-Maps that
+ * back up this window will not overlap with those that map the real physical
+ * memory.
+ */
+#define PCIE_HOST_BAR0_SIZE             HPAGE_SIZE
+#define PCIE_HOST_BAR0_START            HPAGE_MASK
+
+/**
+ * The first PAGE_SIZE of the above "BAR" window is mapped to the
+ * gxpci_host_regs structure.
+ */
+#define PCIE_HOST_REGS_SIZE             PAGE_SIZE
+
+/*
+ * This is the PCI address where the Mem-Map interrupt regions start.
+ * We use the 2nd to the last huge page of the 64-bit address space.
+ * The last huge page is used for the rootcomplex "bar", for C2C purpose.
+ */
+#define MEM_MAP_INTR_REGIONS_BASE       (HPAGE_MASK - HPAGE_SIZE)
+
+/*
+ * Each Mem-Map interrupt region occupies 4KB.
+ */
+#define MEM_MAP_INTR_REGION_SIZE        (1 << TRIO_MAP_MEM_LIM__ADDR_SHIFT)
+
+/*
+ * Allocate the PCI BAR window right below 4GB.
+ */
+#define TILE_PCI_BAR_WINDOW_TOP         (1ULL << 32)
+
+/*
+ * Allocate 1GB for the PCI BAR window.
+ */
+#define TILE_PCI_BAR_WINDOW_SIZE        (1 << 30)
+
+/*
+ * This is the highest bus address targeting the host memory that
+ * can be generated by legacy PCI devices with 32-bit or less
+ * DMA capability, dictated by the BAR window size and location.
+ */
+#define TILE_PCI_MAX_DIRECT_DMA_ADDRESS \
+        (TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE - 1)
+
+/*
+ * We shift the PCI bus range for all the physical memory up by the whole PA
+ * range. The corresponding CPA of an incoming PCI request will be the PCI
+ * address minus TILE_PCI_MEM_MAP_BASE_OFFSET. This also implies
+ * that the 64-bit capable devices will be given DMA addresses as
+ * the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit
+ * devices, we create a separate map region that handles the low
+ * 4GB.
+ */
+#define TILE_PCI_MEM_MAP_BASE_OFFSET    (1ULL << CHIP_PA_WIDTH())
+
+/*
+ * Start of the PCI memory resource, which starts at the end of the
+ * maximum system physical RAM address.
+ */
+#define TILE_PCI_MEM_START      (1ULL << CHIP_PA_WIDTH())
+
+/*
+ * Structure of a PCI controller (host bridge) on Gx.
+ */
+struct pci_controller {
+
+        /* Pointer back to the TRIO that this PCIe port is connected to. */
+        gxio_trio_context_t *trio;
+        int mac;                /* PCIe mac index on the TRIO shim */
+        int trio_index;         /* Index of TRIO shim that contains the MAC. */
+
+        int pio_mem_index;      /* PIO region index for memory access */
+
+        /*
+         * Mem-Map regions for all the memory controllers so that Linux can
+         * map all of its physical memory space to the PCI bus.
+         */
+        int mem_maps[MAX_NUMNODES];
+
+        int index;              /* PCI domain number */
+        struct pci_bus *root_bus;
+
+        /* PCI memory space resource for this controller. */
+        struct resource mem_space;
+        char mem_space_name[32];
+
+        uint64_t mem_offset;    /* cpu->bus memory mapping offset. */
+
+        int first_busno;
+
+        struct pci_ops *ops;
+
+        /* Table that maps the INTx numbers to Linux irq numbers. */
+        int irq_intx_table[4];
+
+        /* Address ranges that are routed to this controller/bridge. */
+        struct resource mem_resources[3];
+};
+
+extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
+extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
+
+extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
+
+/*
+ * The PCI address space does not equal the physical memory address
+ * space (we have an IOMMU). The IDE and SCSI device layers use this
+ * boolean for bounce buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS     0
+
+#endif /* __tilegx__ */
+
 int __init tile_pci_init(void);
 int __init pcibios_init(void);
 
-static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
-
 void __devinit pcibios_fixup_bus(struct pci_bus *bus);
 
-#define TILE_NUM_PCIE   2
-
 #define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
 
 /*
@@ -79,19 +213,10 @@ static inline int pcibios_assign_all_busses(void)
 #define PCIBIOS_MIN_MEM         0
 #define PCIBIOS_MIN_IO          0
 
-/*
- * This flag tells if the platform is TILEmpower that needs
- * special configuration for the PLX switch chip.
- */
-extern int tile_plx_gen1;
-
 /* Use any cpu for PCI. */
 #define cpumask_of_pcibus(bus) cpu_online_mask
 
 /* implement the pci_ DMA API in terms of the generic device dma_ one */
 #include <asm-generic/pci-dma-compat.h>
 
-/* generic pci stuff */
-#include <asm-generic/pci.h>
-
 #endif /* _ASM_TILE_PCI_H */
diff --git a/arch/tile/include/gxio/common.h b/arch/tile/include/gxio/common.h
new file mode 100644
index 00000000000..724595a24d0
--- /dev/null
+++ b/arch/tile/include/gxio/common.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#ifndef _GXIO_COMMON_H_
+#define _GXIO_COMMON_H_
+
+/*
+ * Routines shared between the various GXIO device components.
+ */
+
+#include <hv/iorpc.h>
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+#include <linux/io.h>
+
+/* Define the standard gxio MMIO functions using kernel functions. */
+#define __gxio_mmio_read8(addr)         readb(addr)
+#define __gxio_mmio_read16(addr)        readw(addr)
+#define __gxio_mmio_read32(addr)        readl(addr)
+#define __gxio_mmio_read64(addr)        readq(addr)
+#define __gxio_mmio_write8(addr, val)   writeb((val), (addr))
+#define __gxio_mmio_write16(addr, val)  writew((val), (addr))
+#define __gxio_mmio_write32(addr, val)  writel((val), (addr))
+#define __gxio_mmio_write64(addr, val)  writeq((val), (addr))
+#define __gxio_mmio_read(addr)          __gxio_mmio_read64(addr)
+#define __gxio_mmio_write(addr, val)    __gxio_mmio_write64((addr), (val))
+
+#endif /* !_GXIO_COMMON_H_ */
diff --git a/arch/tile/include/gxio/dma_queue.h b/arch/tile/include/gxio/dma_queue.h
new file mode 100644
index 00000000000..00654feb7db
--- /dev/null
+++ b/arch/tile/include/gxio/dma_queue.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#ifndef _GXIO_DMA_QUEUE_H_
+#define _GXIO_DMA_QUEUE_H_
+
+/*
+ * DMA queue management APIs shared between TRIO and mPIPE.
+ */
+
+#include "common.h"
+
+/* The credit counter lives in the high 32 bits. */
+#define DMA_QUEUE_CREDIT_SHIFT 32
+
+/*
+ * State object that tracks a DMA queue's head and tail indices, as
+ * well as the number of commands posted and completed.  The
+ * structure is accessed via a thread-safe, lock-free algorithm.
+ */
+typedef struct {
+        /*
+         * Address of a MPIPE_EDMA_POST_REGION_VAL_t,
+         * TRIO_PUSH_DMA_REGION_VAL_t, or TRIO_PULL_DMA_REGION_VAL_t
+         * register.  These register have identical encodings and provide
+         * information about how many commands have been processed.
+         */
+        void *post_region_addr;
+
+        /*
+         * A lazily-updated count of how many edescs the hardware has
+         * completed.
+         */
+        uint64_t hw_complete_count __attribute__ ((aligned(64)));
+
+        /*
+         * High 32 bits are a count of available egress command credits,
+         * low 24 bits are the next egress "slot".
+         */
+        int64_t credits_and_next_index;
+
+} __gxio_dma_queue_t;
+
+/* Initialize a dma queue. */
+extern void __gxio_dma_queue_init(__gxio_dma_queue_t *dma_queue,
+                                  void *post_region_addr,
+                                  unsigned int num_entries);
+
+/*
+ * Update the "credits_and_next_index" and "hw_complete_count" fields
+ * based on pending hardware completions.  Note that some other thread
+ * may have already done this and, importantly, may still be in the
+ * process of updating "credits_and_next_index".
+ */
+extern void __gxio_dma_queue_update_credits(__gxio_dma_queue_t *dma_queue);
+
+/* Wait for credits to become available. */
+extern int64_t __gxio_dma_queue_wait_for_credits(__gxio_dma_queue_t *dma_queue,
+                                                 int64_t modifier);
+
+/* Reserve slots in the queue, optionally waiting for slots to become
+ * available, and optionally returning a "completion_slot" suitable for
+ * direct comparison to "hw_complete_count".
+ */
+static inline int64_t __gxio_dma_queue_reserve(__gxio_dma_queue_t *dma_queue,
+                                               unsigned int num, bool wait,
+                                               bool completion)
+{
+        uint64_t slot;
+
+        /*
+         * Try to reserve 'num' egress command slots.  We do this by
+         * constructing a constant that subtracts N credits and adds N to
+         * the index, and using fetchaddgez to only apply it if the credits
+         * count doesn't go negative.
+         */
+        int64_t modifier = (((int64_t)(-num)) << DMA_QUEUE_CREDIT_SHIFT) | num;
+        int64_t old =
+                __insn_fetchaddgez(&dma_queue->credits_and_next_index,
+                                   modifier);
+
+        if (unlikely(old + modifier < 0)) {
+                /*
+                 * We're out of credits.  Try once to get more by checking for
+                 * completed egress commands.  If that fails, wait or fail.
+                 */
+                __gxio_dma_queue_update_credits(dma_queue);
+                old = __insn_fetchaddgez(&dma_queue->credits_and_next_index,
+                                         modifier);
+                if (old + modifier < 0) {
+                        if (wait)
+                                old = __gxio_dma_queue_wait_for_credits
+                                        (dma_queue, modifier);
+                        else
+                                return GXIO_ERR_DMA_CREDITS;
+                }
+        }
+
+        /* The bottom 24 bits of old encode the "slot". */
+        slot = (old & 0xffffff);
+
+        if (completion) {
+                /*
+                 * A "completion_slot" is a "slot" which can be compared to
+                 * "hw_complete_count" at any time in the future.  To convert
+                 * "slot" into a "completion_slot", we access "hw_complete_count"
+                 * once (knowing that we have reserved a slot, and thus, it will
+                 * be "basically" accurate), and combine its high 40 bits with
+                 * the 24 bit "slot", and handle "wrapping" by adding "1 << 24"
+                 * if the result is LESS than "hw_complete_count".
+                 */
+                uint64_t complete;
+                complete = ACCESS_ONCE(dma_queue->hw_complete_count);
+                slot |= (complete & 0xffffffffff000000);
+                if (slot < complete)
+                        slot += 0x1000000;
+        }
+
+        /*
+         * If any of our slots mod 256 were equivalent to 0, go ahead and
+         * collect some egress credits, and update "hw_complete_count", and
+         * make sure the index doesn't overflow into the credits.
+         */
+        if (unlikely(((old + num) & 0xff) < num)) {
+                __gxio_dma_queue_update_credits(dma_queue);
+
+                /* Make sure the index doesn't overflow into the credits. */
+#ifdef __BIG_ENDIAN__
+                *(((uint8_t *)&dma_queue->credits_and_next_index) + 4) = 0;
+#else
+                *(((uint8_t *)&dma_queue->credits_and_next_index) + 3) = 0;
+#endif
+        }
+
+        return slot;
+}
+
+/* Non-inlinable "__gxio_dma_queue_reserve(..., true)". */
+extern int64_t __gxio_dma_queue_reserve_aux(__gxio_dma_queue_t *dma_queue,
+                                            unsigned int num, int wait);
+
+/* Check whether a particular "completion slot" has completed.
+ *
+ * Note that this function requires a "completion slot", and thus
+ * cannot be used with the result of any "reserve_fast" function.
+ */
+extern int __gxio_dma_queue_is_complete(__gxio_dma_queue_t *dma_queue,
+                                        int64_t completion_slot, int update);
+
+#endif /* !_GXIO_DMA_QUEUE_H_ */
diff --git a/arch/tile/include/gxio/iorpc_globals.h b/arch/tile/include/gxio/iorpc_globals.h
new file mode 100644
index 00000000000..52c721f8dad
--- /dev/null
+++ b/arch/tile/include/gxio/iorpc_globals.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* This file is machine-generated; DO NOT EDIT! */
+#ifndef __IORPC_LINUX_RPC_H__
+#define __IORPC_LINUX_RPC_H__
+
+#include <hv/iorpc.h>
+
+#include <linux/string.h>
+#include <linux/module.h>
+#include <asm/pgtable.h>
+
+#define IORPC_OP_ARM_POLLFD            IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9000)
+#define IORPC_OP_CLOSE_POLLFD          IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9001)
+#define IORPC_OP_GET_MMIO_BASE         IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
+#define IORPC_OP_CHECK_MMIO_OFFSET     IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
+
+int __iorpc_arm_pollfd(int fd, int pollfd_cookie);
+
+int __iorpc_close_pollfd(int fd, int pollfd_cookie);
+
+int __iorpc_get_mmio_base(int fd, HV_PTE *base);
+
+int __iorpc_check_mmio_offset(int fd, unsigned long offset, unsigned long size);
+
+#endif /* !__IORPC_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/iorpc_mpipe.h b/arch/tile/include/gxio/iorpc_mpipe.h
new file mode 100644
index 00000000000..9d50fce1b1a
--- /dev/null
+++ b/arch/tile/include/gxio/iorpc_mpipe.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* This file is machine-generated; DO NOT EDIT! */
+#ifndef __GXIO_MPIPE_LINUX_RPC_H__
+#define __GXIO_MPIPE_LINUX_RPC_H__
+
+#include <hv/iorpc.h>
+
+#include <hv/drv_mpipe_intf.h>
+#include <asm/page.h>
+#include <gxio/kiorpc.h>
+#include <gxio/mpipe.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <asm/pgtable.h>
+
+#define GXIO_MPIPE_OP_ALLOC_BUFFER_STACKS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1200)
+#define GXIO_MPIPE_OP_INIT_BUFFER_STACK_AUX IORPC_OPCODE(IORPC_FORMAT_KERNEL_MEM, 0x1201)
+
+#define GXIO_MPIPE_OP_ALLOC_NOTIF_RINGS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1203)
+#define GXIO_MPIPE_OP_INIT_NOTIF_RING_AUX IORPC_OPCODE(IORPC_FORMAT_KERNEL_MEM, 0x1204)
+#define GXIO_MPIPE_OP_REQUEST_NOTIF_RING_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1205)
+#define GXIO_MPIPE_OP_ENABLE_NOTIF_RING_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1206)
+#define GXIO_MPIPE_OP_ALLOC_NOTIF_GROUPS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1207)
+#define GXIO_MPIPE_OP_INIT_NOTIF_GROUP IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1208)
+#define GXIO_MPIPE_OP_ALLOC_BUCKETS    IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1209)
+#define GXIO_MPIPE_OP_INIT_BUCKET      IORPC_OPCODE(IORPC_FORMAT_NONE, 0x120a)
+#define GXIO_MPIPE_OP_ALLOC_EDMA_RINGS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x120b)
+#define GXIO_MPIPE_OP_INIT_EDMA_RING_AUX IORPC_OPCODE(IORPC_FORMAT_KERNEL_MEM, 0x120c)
+
+#define GXIO_MPIPE_OP_COMMIT_RULES     IORPC_OPCODE(IORPC_FORMAT_NONE, 0x120f)
+#define GXIO_MPIPE_OP_REGISTER_CLIENT_MEMORY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1210)
+#define GXIO_MPIPE_OP_LINK_OPEN_AUX    IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1211)
+#define GXIO_MPIPE_OP_LINK_CLOSE_AUX   IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1212)
+
+#define GXIO_MPIPE_OP_GET_TIMESTAMP_AUX IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x121e)
+#define GXIO_MPIPE_OP_SET_TIMESTAMP_AUX IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x121f)
+#define GXIO_MPIPE_OP_ADJUST_TIMESTAMP_AUX IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1220)
+#define GXIO_MPIPE_OP_ARM_POLLFD       IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9000)
+#define GXIO_MPIPE_OP_CLOSE_POLLFD     IORPC_OPCODE(IORPC_FORMAT_KERNEL_POLLFD, 0x9001)
+#define GXIO_MPIPE_OP_GET_MMIO_BASE    IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
+#define GXIO_MPIPE_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
+
+int gxio_mpipe_alloc_buffer_stacks(gxio_mpipe_context_t * context,
+                                   unsigned int count, unsigned int first,
+                                   unsigned int flags);
+
+int gxio_mpipe_init_buffer_stack_aux(gxio_mpipe_context_t * context,
+                                     void *mem_va, size_t mem_size,
+                                     unsigned int mem_flags, unsigned int stack,
+                                     unsigned int buffer_size_enum);
+
+
+int gxio_mpipe_alloc_notif_rings(gxio_mpipe_context_t * context,
+                                 unsigned int count, unsigned int first,
+                                 unsigned int flags);
+
+int gxio_mpipe_init_notif_ring_aux(gxio_mpipe_context_t * context, void *mem_va,
+                                   size_t mem_size, unsigned int mem_flags,
+                                   unsigned int ring);
+
+int gxio_mpipe_request_notif_ring_interrupt(gxio_mpipe_context_t * context,
+                                            int inter_x, int inter_y,
+                                            int inter_ipi, int inter_event,
+                                            unsigned int ring);
+
+int gxio_mpipe_enable_notif_ring_interrupt(gxio_mpipe_context_t * context,
+                                           unsigned int ring);
+
+int gxio_mpipe_alloc_notif_groups(gxio_mpipe_context_t * context,
+                                  unsigned int count, unsigned int first,
+                                  unsigned int flags);
+
+int gxio_mpipe_init_notif_group(gxio_mpipe_context_t * context,
+                                unsigned int group,
+                                gxio_mpipe_notif_group_bits_t bits);
+
+int gxio_mpipe_alloc_buckets(gxio_mpipe_context_t * context, unsigned int count,
+                             unsigned int first, unsigned int flags);
+
+int gxio_mpipe_init_bucket(gxio_mpipe_context_t * context, unsigned int bucket,
+                           MPIPE_LBL_INIT_DAT_BSTS_TBL_t bucket_info);
+
+int gxio_mpipe_alloc_edma_rings(gxio_mpipe_context_t * context,
+                                unsigned int count, unsigned int first,
+                                unsigned int flags);
+
+int gxio_mpipe_init_edma_ring_aux(gxio_mpipe_context_t * context, void *mem_va,
+                                  size_t mem_size, unsigned int mem_flags,
+                                  unsigned int ring, unsigned int channel);
+
+
+int gxio_mpipe_commit_rules(gxio_mpipe_context_t * context, const void *blob,
+                            size_t blob_size);
+
+int gxio_mpipe_register_client_memory(gxio_mpipe_context_t * context,
+                                      unsigned int iotlb, HV_PTE pte,
+                                      unsigned int flags);
+
+int gxio_mpipe_link_open_aux(gxio_mpipe_context_t * context,
+                             _gxio_mpipe_link_name_t name, unsigned int flags);
+
+int gxio_mpipe_link_close_aux(gxio_mpipe_context_t * context, int mac);
+
+
+int gxio_mpipe_get_timestamp_aux(gxio_mpipe_context_t * context, uint64_t * sec,
+                                 uint64_t * nsec, uint64_t * cycles);
+
+int gxio_mpipe_set_timestamp_aux(gxio_mpipe_context_t * context, uint64_t sec,
+                                 uint64_t nsec, uint64_t cycles);
+
+int gxio_mpipe_adjust_timestamp_aux(gxio_mpipe_context_t * context,
+                                    int64_t nsec);
+
+int gxio_mpipe_arm_pollfd(gxio_mpipe_context_t * context, int pollfd_cookie);
+
+int gxio_mpipe_close_pollfd(gxio_mpipe_context_t * context, int pollfd_cookie);
+
+int gxio_mpipe_get_mmio_base(gxio_mpipe_context_t * context, HV_PTE *base);
+
+int gxio_mpipe_check_mmio_offset(gxio_mpipe_context_t * context,
+                                 unsigned long offset, unsigned long size);
+
+#endif /* !__GXIO_MPIPE_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/iorpc_mpipe_info.h b/arch/tile/include/gxio/iorpc_mpipe_info.h
new file mode 100644
index 00000000000..0bcf3f71ce8
--- /dev/null
+++ b/arch/tile/include/gxio/iorpc_mpipe_info.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* This file is machine-generated; DO NOT EDIT! */
+#ifndef __GXIO_MPIPE_INFO_LINUX_RPC_H__
+#define __GXIO_MPIPE_INFO_LINUX_RPC_H__
+
+#include <hv/iorpc.h>
+
+#include <hv/drv_mpipe_intf.h>
+#include <asm/page.h>
+#include <gxio/kiorpc.h>
+#include <gxio/mpipe.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <asm/pgtable.h>
+
+
+#define GXIO_MPIPE_INFO_OP_ENUMERATE_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1251)
+#define GXIO_MPIPE_INFO_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
+#define GXIO_MPIPE_INFO_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
+
+
+int gxio_mpipe_info_enumerate_aux(gxio_mpipe_info_context_t * context,
+                                  unsigned int idx,
+                                  _gxio_mpipe_link_name_t * name,
+                                  _gxio_mpipe_link_mac_t * mac);
+
+int gxio_mpipe_info_get_mmio_base(gxio_mpipe_info_context_t * context,
+                                  HV_PTE *base);
+
+int gxio_mpipe_info_check_mmio_offset(gxio_mpipe_info_context_t * context,
+                                      unsigned long offset, unsigned long size);
+
+#endif /* !__GXIO_MPIPE_INFO_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/iorpc_trio.h b/arch/tile/include/gxio/iorpc_trio.h
new file mode 100644
index 00000000000..15fb7799208
--- /dev/null
+++ b/arch/tile/include/gxio/iorpc_trio.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* This file is machine-generated; DO NOT EDIT! */
+#ifndef __GXIO_TRIO_LINUX_RPC_H__
+#define __GXIO_TRIO_LINUX_RPC_H__
+
+#include <hv/iorpc.h>
+
+#include <hv/drv_trio_intf.h>
+#include <gxio/trio.h>
+#include <gxio/kiorpc.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <asm/pgtable.h>
+
+#define GXIO_TRIO_OP_ALLOC_ASIDS       IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1400)
+
+#define GXIO_TRIO_OP_ALLOC_MEMORY_MAPS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x1402)
+
+#define GXIO_TRIO_OP_ALLOC_PIO_REGIONS IORPC_OPCODE(IORPC_FORMAT_NONE, 0x140e)
+#define GXIO_TRIO_OP_INIT_PIO_REGION_AUX IORPC_OPCODE(IORPC_FORMAT_NONE, 0x140f)
+
+#define GXIO_TRIO_OP_INIT_MEMORY_MAP_MMU_AUX IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1417)
+#define GXIO_TRIO_OP_GET_PORT_PROPERTY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1418)
+#define GXIO_TRIO_OP_CONFIG_LEGACY_INTR IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1419)
+#define GXIO_TRIO_OP_CONFIG_MSI_INTR   IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x141a)
+
+#define GXIO_TRIO_OP_SET_MPS_MRS       IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141c)
+#define GXIO_TRIO_OP_FORCE_RC_LINK_UP  IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141d)
+#define GXIO_TRIO_OP_FORCE_EP_LINK_UP  IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x141e)
+#define GXIO_TRIO_OP_GET_MMIO_BASE     IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
+#define GXIO_TRIO_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
+
+int gxio_trio_alloc_asids(gxio_trio_context_t * context, unsigned int count,
+                          unsigned int first, unsigned int flags);
+
+
+int gxio_trio_alloc_memory_maps(gxio_trio_context_t * context,
+                                unsigned int count, unsigned int first,
+                                unsigned int flags);
+
+
+int gxio_trio_alloc_pio_regions(gxio_trio_context_t * context,
+                                unsigned int count, unsigned int first,
+                                unsigned int flags);
+
+int gxio_trio_init_pio_region_aux(gxio_trio_context_t * context,
+                                  unsigned int pio_region, unsigned int mac,
+                                  uint32_t bus_address_hi, unsigned int flags);
+
+
+int gxio_trio_init_memory_map_mmu_aux(gxio_trio_context_t * context,
+                                      unsigned int map, unsigned long va,
+                                      uint64_t size, unsigned int asid,
+                                      unsigned int mac, uint64_t bus_address,
+                                      unsigned int node,
+                                      unsigned int order_mode);
+
+int gxio_trio_get_port_property(gxio_trio_context_t * context,
+                                struct pcie_trio_ports_property *trio_ports);
+
+int gxio_trio_config_legacy_intr(gxio_trio_context_t * context, int inter_x,
+                                 int inter_y, int inter_ipi, int inter_event,
+                                 unsigned int mac, unsigned int intx);
+
+int gxio_trio_config_msi_intr(gxio_trio_context_t * context, int inter_x,
+                              int inter_y, int inter_ipi, int inter_event,
+                              unsigned int mac, unsigned int mem_map,
+                              uint64_t mem_map_base, uint64_t mem_map_limit,
+                              unsigned int asid);
+
+
+int gxio_trio_set_mps_mrs(gxio_trio_context_t * context, uint16_t mps,
+                          uint16_t mrs, unsigned int mac);
+
+int gxio_trio_force_rc_link_up(gxio_trio_context_t * context, unsigned int mac);
+
+int gxio_trio_force_ep_link_up(gxio_trio_context_t * context, unsigned int mac);
+
+int gxio_trio_get_mmio_base(gxio_trio_context_t * context, HV_PTE *base);
+
+int gxio_trio_check_mmio_offset(gxio_trio_context_t * context,
+                                unsigned long offset, unsigned long size);
+
+#endif /* !__GXIO_TRIO_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/iorpc_usb_host.h b/arch/tile/include/gxio/iorpc_usb_host.h
new file mode 100644
index 00000000000..8622e7d126a
--- /dev/null
+++ b/arch/tile/include/gxio/iorpc_usb_host.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/* This file is machine-generated; DO NOT EDIT! */
+#ifndef __GXIO_USB_HOST_LINUX_RPC_H__
+#define __GXIO_USB_HOST_LINUX_RPC_H__
+
+#include <hv/iorpc.h>
+
+#include <hv/drv_usb_host_intf.h>
+#include <asm/page.h>
+#include <gxio/kiorpc.h>
+#include <gxio/usb_host.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <asm/pgtable.h>
+
+#define GXIO_USB_HOST_OP_CFG_INTERRUPT IORPC_OPCODE(IORPC_FORMAT_KERNEL_INTERRUPT, 0x1800)
+#define GXIO_USB_HOST_OP_REGISTER_CLIENT_MEMORY IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x1801)
+#define GXIO_USB_HOST_OP_GET_MMIO_BASE IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8000)
+#define GXIO_USB_HOST_OP_CHECK_MMIO_OFFSET IORPC_OPCODE(IORPC_FORMAT_NONE_NOUSER, 0x8001)
+
+int gxio_usb_host_cfg_interrupt(gxio_usb_host_context_t * context, int inter_x,
+                                int inter_y, int inter_ipi, int inter_event);
+
+int gxio_usb_host_register_client_memory(gxio_usb_host_context_t * context,
+                                         HV_PTE pte, unsigned int flags);
+
+int gxio_usb_host_get_mmio_base(gxio_usb_host_context_t * context,
+                                HV_PTE *base);
+
+int gxio_usb_host_check_mmio_offset(gxio_usb_host_context_t * context,
+                                    unsigned long offset, unsigned long size);
+
+#endif /* !__GXIO_USB_HOST_LINUX_RPC_H__ */
diff --git a/arch/tile/include/gxio/kiorpc.h b/arch/tile/include/gxio/kiorpc.h
new file mode 100644
index 00000000000..ee5820979ff
--- /dev/null
+++ b/arch/tile/include/gxio/kiorpc.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * Support routines for kernel IORPC drivers.
+ */
+
+#ifndef _GXIO_KIORPC_H
+#define _GXIO_KIORPC_H
+
+#include <linux/types.h>
+#include <asm/page.h>
+#include <arch/chip.h>
+
+#if CHIP_HAS_MMIO()
+void __iomem *iorpc_ioremap(int hv_fd, resource_size_t offset,
+                            unsigned long size);
+#endif
+
+#endif /* _GXIO_KIORPC_H */
diff --git a/arch/tile/include/gxio/mpipe.h b/arch/tile/include/gxio/mpipe.h
new file mode 100644
index 00000000000..78c598618c9
--- /dev/null
+++ b/arch/tile/include/gxio/mpipe.h
@@ -0,0 +1,1736 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#ifndef _GXIO_MPIPE_H_
+#define _GXIO_MPIPE_H_
+
+/*
+ *
+ * An API for allocating, configuring, and manipulating mPIPE hardware
+ * resources.
+ */
+
+#include "common.h"
+#include "dma_queue.h"
+
+#include <linux/time.h>
+
+#include <arch/mpipe_def.h>
+#include <arch/mpipe_shm.h>
+
+#include <hv/drv_mpipe_intf.h>
+#include <hv/iorpc.h>
+
+/*
+ *
+ * The TILE-Gx mPIPE&tm; shim provides Ethernet connectivity, packet
+ * classification, and packet load balancing services.  The
+ * gxio_mpipe_ API, declared in <gxio/mpipe.h>, allows applications to
+ * allocate mPIPE IO channels, configure packet distribution
+ * parameters, and send and receive Ethernet packets.  The API is
+ * designed to be a minimal wrapper around the mPIPE hardware, making
+ * system calls only where necessary to preserve inter-process
+ * protection guarantees.
+ *
+ * The APIs described below allow the programmer to allocate and
+ * configure mPIPE resources.  As described below, the mPIPE is a
+ * single shared hardware device that provides partitionable resources
+ * that are shared between all applications in the system.  The
+ * gxio_mpipe_ API allows userspace code to make resource request
+ * calls to the hypervisor, which in turns keeps track of the
+ * resources in use by all applications, maintains protection
+ * guarantees, and resets resources upon application shutdown.
+ *
+ * We strongly recommend reading the mPIPE section of the IO Device
+ * Guide (UG404) before working with this API.  Most functions in the
+ * gxio_mpipe_ API are directly analogous to hardware interfaces and
+ * the documentation assumes that the reader understands those
+ * hardware interfaces.
+ *
+ * @section mpipe__ingress mPIPE Ingress Hardware Resources
+ *
+ * The mPIPE ingress hardware provides extensive hardware offload for
+ * tasks like packet header parsing, load balancing, and memory
+ * management.  This section provides a brief introduction to the
+ * hardware components and the gxio_mpipe_ calls used to manage them;
+ * see the IO Device Guide for a much more detailed description of the
+ * mPIPE's capabilities.
+ *
+ * When a packet arrives at one of the mPIPE's Ethernet MACs, it is
+ * assigned a channel number indicating which MAC received it.  It
+ * then proceeds through the following hardware pipeline:
+ *
+ * @subsection mpipe__classification Classification
+ *
+ * A set of classification processors run header parsing code on each
+ * incoming packet, extracting information including the destination
+ * MAC address, VLAN, Ethernet type, and five-tuple hash.  Some of
+ * this information is then used to choose which buffer stack will be
+ * used to hold the packet, and which bucket will be used by the load
+ * balancer to determine which application will receive the packet.
+ *
+ * The rules by which the buffer stack and bucket are chosen can be
+ * configured via the @ref gxio_mpipe_classifier API.  A given app can
+ * specify multiple rules, each one specifying a bucket range, and a
+ * set of buffer stacks, to be used for packets matching the rule.
+ * Each rule can optionally specify a restricted set of channels,
+ * VLANs, and/or dMACs, in which it is interested.  By default, a
+ * given rule starts out matching all channels associated with the
+ * mPIPE context's set of open links; all VLANs; and all dMACs.
+ * Subsequent restrictions can then be added.
+ *
+ * @subsection mpipe__load_balancing Load Balancing
+ *
+ * The mPIPE load balancer is responsible for choosing the NotifRing
+ * to which the packet will be delivered.  This decision is based on
+ * the bucket number indicated by the classification program.  In
+ * general, the bucket number is based on some number of low bits of
+ * the packet's flow hash (applications that aren't interested in flow
+ * hashing use a single bucket).  Each load balancer bucket keeps a
+ * record of the NotifRing to which packets directed to that bucket
+ * are currently being delivered.  Based on the bucket's load
+ * balancing mode (@ref gxio_mpipe_bucket_mode_t), the load balancer
+ * either forwards the packet to the previously assigned NotifRing or
+ * decides to choose a new NotifRing.  If a new NotifRing is required,
+ * the load balancer chooses the least loaded ring in the NotifGroup
+ * associated with the bucket.
+ *
+ * The load balancer is a shared resource.  Each application needs to
+ * explicitly allocate NotifRings, NotifGroups, and buckets, using
+ * gxio_mpipe_alloc_notif_rings(), gxio_mpipe_alloc_notif_groups(),
+ * and gxio_mpipe_alloc_buckets().  Then the application needs to
+ * configure them using gxio_mpipe_init_notif_ring() and
+ * gxio_mpipe_init_notif_group_and_buckets().
+ *
+ * @subsection mpipe__buffers Buffer Selection and Packet Delivery
+ *
+ * Once the load balancer has chosen the destination NotifRing, the
+ * mPIPE DMA engine pops at least one buffer off of the 'buffer stack'
+ * chosen by the classification program and DMAs the packet data into
+ * that buffer.  Each buffer stack provides a hardware-accelerated
+ * stack of data buffers with the same size.  If the packet data is
+ * larger than the buffers provided by the chosen buffer stack, the
+ * mPIPE hardware pops off multiple buffers and chains the packet data
+ * through a multi-buffer linked list.  Once the packet data is
+ * delivered to the buffer(s), the mPIPE hardware writes the
+ * ::gxio_mpipe_idesc_t metadata object (calculated by the classifier)
+ * into the NotifRing and increments the number of packets delivered
+ * to that ring.
+ *
+ * Applications can push buffers onto a buffer stack by calling
+ * gxio_mpipe_push_buffer() or by egressing a packet with the
+ * ::gxio_mpipe_edesc_t::hwb bit set, indicating that the egressed
+ * buffers should be returned to the stack.
+ *
+ * Applications can allocate and initialize buffer stacks with the
+ * gxio_mpipe_alloc_buffer_stacks() and gxio_mpipe_init_buffer_stack()
+ * APIs.
+ *
+ * The application must also register the memory pages that will hold
+ * packets.  This requires calling gxio_mpipe_register_page() for each
+ * memory page that will hold packets allocated by the application for
+ * a given buffer stack.  Since each buffer stack is limited to 16
+ * registered pages, it may be necessary to use huge pages, or even
+ * extremely huge pages, to hold all the buffers.
+ *
+ * @subsection mpipe__iqueue NotifRings
+ *
+ * Each NotifRing is a region of shared memory, allocated by the
+ * application, to which the mPIPE delivers packet descriptors
+ * (::gxio_mpipe_idesc_t).  The application can allocate them via
+ * gxio_mpipe_alloc_notif_rings().  The application can then either
+ * explicitly initialize them with gxio_mpipe_init_notif_ring() and
+ * then read from them manually, or can make use of the convenience
+ * wrappers provided by @ref gxio_mpipe_wrappers.
+ *
+ * @section mpipe__egress mPIPE Egress Hardware
+ *
+ * Applications use eDMA rings to queue packets for egress.  The
+ * application can allocate them via gxio_mpipe_alloc_edma_rings().
+ * The application can then either explicitly initialize them with
+ * gxio_mpipe_init_edma_ring() and then write to them manually, or
+ * can make use of the convenience wrappers provided by
+ * @ref gxio_mpipe_wrappers.
+ *
+ * @section gxio__shortcomings Plans for Future API Revisions
+ *
+ * The API defined here is only an initial version of the mPIPE API.
+ * Future plans include:
+ *
+ * - Higher level wrapper functions to provide common initialization
+ * patterns.  This should help users start writing mPIPE programs
+ * without having to learn the details of the hardware.
+ *
+ * - Support for reset and deallocation of resources, including
+ * cleanup upon application shutdown.
+ *
+ * - Support for calling these APIs in the BME.
+ *
+ * - Support for IO interrupts.
+ *
+ * - Clearer definitions of thread safety guarantees.
+ *
+ * @section gxio__mpipe_examples Examples
+ *
+ * See the following mPIPE example programs for more information about
+ * allocating mPIPE resources and using them in real applications:
+ *
+ * - @ref mpipe/ingress/app.c : Receiving packets.
+ *
+ * - @ref mpipe/forward/app.c : Forwarding packets.
+ *
+ * Note that there are several more examples.
+ */
+
+/* Flags that can be passed to resource allocation functions. */
+enum gxio_mpipe_alloc_flags_e {
+        /* Require an allocation to start at a specified resource index. */
+        GXIO_MPIPE_ALLOC_FIXED = HV_MPIPE_ALLOC_FIXED,
+};
+
+/* Flags that can be passed to memory registration functions. */
+enum gxio_mpipe_mem_flags_e {
+        /* Do not fill L3 when writing, and invalidate lines upon egress. */
+        GXIO_MPIPE_MEM_FLAG_NT_HINT = IORPC_MEM_BUFFER_FLAG_NT_HINT,
+
+        /* L3 cache fills should only populate IO cache ways. */
+        GXIO_MPIPE_MEM_FLAG_IO_PIN = IORPC_MEM_BUFFER_FLAG_IO_PIN,
+};
+
+/* An ingress packet descriptor.  When a packet arrives, the mPIPE
+ * hardware generates this structure and writes it into a NotifRing.
+ */
+typedef MPIPE_PDESC_t gxio_mpipe_idesc_t;
+
+/* An egress command descriptor.  Applications write this structure
+ * into eDMA rings and the hardware performs the indicated operation
+ * (normally involving egressing some bytes).  Note that egressing a
+ * single packet may involve multiple egress command descriptors.
+ */
+typedef MPIPE_EDMA_DESC_t gxio_mpipe_edesc_t;
+
+/* Get the "va" field from an "idesc".
+ *
+ * This is the address at which the ingress hardware copied the first
+ * byte of the packet.
+ *
+ * If the classifier detected a custom header, then this will point to
+ * the custom header, and gxio_mpipe_idesc_get_l2_start() will point
+ * to the actual L2 header.
+ *
+ * Note that this value may be misleading if "idesc->be" is set.
+ *
+ * @param idesc An ingress packet descriptor.
+ */
+static inline unsigned char *gxio_mpipe_idesc_get_va(gxio_mpipe_idesc_t *idesc)
+{
+        return (unsigned char *)(long)idesc->va;
+}
+
+/* Get the "xfer_size" from an "idesc".
+ *
+ * This is the actual number of packet bytes transferred into memory
+ * by the hardware.
+ *
+ * Note that this value may be misleading if "idesc->be" is set.
+ *
+ * @param idesc An ingress packet descriptor.
+ *
+ * ISSUE: Is this the best name for this?
+ * FIXME: Add more docs about chaining, clipping, etc.
+ */
+static inline unsigned int gxio_mpipe_idesc_get_xfer_size(gxio_mpipe_idesc_t
+                                                          *idesc)
+{
+        return idesc->l2_size;
+}
+
+/* Get the "l2_offset" from an "idesc".
+ *
+ * Extremely customized classifiers might not support this function.
+ *
+ * This is the number of bytes between the "va" and the L2 header.
+ *
+ * The L2 header consists of a destination mac address, a source mac
+ * address, and an initial ethertype.  Various initial ethertypes
+ * allow encoding extra information in the L2 header, often including
+ * a vlan, and/or a new ethertype.
+ *
+ * Note that the "l2_offset" will be non-zero if (and only if) the
+ * classifier processed a custom header for the packet.
+ *
+ * @param idesc An ingress packet descriptor.
+ */
+static inline uint8_t gxio_mpipe_idesc_get_l2_offset(gxio_mpipe_idesc_t *idesc)
+{
+        return (idesc->custom1 >> 32) & 0xFF;
+}
+
+/* Get the "l2_start" from an "idesc".
+ *
+ * This is simply gxio_mpipe_idesc_get_va() plus
+ * gxio_mpipe_idesc_get_l2_offset().
+ *
+ * @param idesc An ingress packet descriptor.
+ */
+static inline unsigned char *gxio_mpipe_idesc_get_l2_start(gxio_mpipe_idesc_t
+                                                           *idesc)
+{
+        unsigned char *va = gxio_mpipe_idesc_get_va(idesc);
+        return va + gxio_mpipe_idesc_get_l2_offset(idesc);
+}
+
+/* Get the "l2_length" from an "idesc".
+ *
+ * This is simply gxio_mpipe_idesc_get_xfer_size() minus
+ * gxio_mpipe_idesc_get_l2_offset().
+ *
+ * @param idesc An ingress packet descriptor.
+ */
+static inline unsigned int gxio_mpipe_idesc_get_l2_length(gxio_mpipe_idesc_t
+                                                          *idesc)
+{
+        unsigned int xfer_size = idesc->l2_size;
+        return xfer_size - gxio_mpipe_idesc_get_l2_offset(idesc);
+}
+
+/* A context object used to manage mPIPE hardware resources. */
+typedef struct {
+
+        /* File descriptor for calling up to Linux (and thus the HV). */
+        int fd;
+
+        /* The VA at which configuration registers are mapped. */
+        char *mmio_cfg_base;
+
+        /* The VA at which IDMA, EDMA, and buffer manager are mapped. */
+        char *mmio_fast_base;
+
+        /* The "initialized" buffer stacks. */
+        gxio_mpipe_rules_stacks_t __stacks;
+
+} gxio_mpipe_context_t;
+
+/* This is only used internally, but it's most easily made visible here. */
+typedef gxio_mpipe_context_t gxio_mpipe_info_context_t;
+
+/* Initialize an mPIPE context.
+ *
+ * This function allocates an mPIPE "service domain" and maps the MMIO
+ * registers into the caller's VA space.
+ *
+ * @param context Context object to be initialized.
+ * @param mpipe_instance Instance number of mPIPE shim to be controlled via
+ *  context.
+ */
+extern int gxio_mpipe_init(gxio_mpipe_context_t *context,
+                           unsigned int mpipe_instance);
+
+/* Destroy an mPIPE context.
+ *
+ * This function frees the mPIPE "service domain" and unmaps the MMIO
+ * registers from the caller's VA space.
+ *
+ * If a user process exits without calling this routine, the kernel
+ * will destroy the mPIPE context as part of process teardown.
+ *
+ * @param context Context object to be destroyed.
+ */
+extern int gxio_mpipe_destroy(gxio_mpipe_context_t *context);
+
+/*****************************************************************
+ *                         Buffer Stacks                          *
+ ******************************************************************/
+
+/* Allocate a set of buffer stacks.
+ *
+ * The return value is NOT interesting if count is zero.
+ *
+ * @param context An initialized mPIPE context.
+ * @param count Number of stacks required.
+ * @param first Index of first stack if ::GXIO_MPIPE_ALLOC_FIXED flag is set,
+ *   otherwise ignored.
+ * @param flags Flag bits from ::gxio_mpipe_alloc_flags_e.
+ * @return Index of first allocated buffer stack, or
+ * ::GXIO_MPIPE_ERR_NO_BUFFER_STACK if allocation failed.
+ */
+extern int gxio_mpipe_alloc_buffer_stacks(gxio_mpipe_context_t *context,
+                                          unsigned int count,
+                                          unsigned int first,
+                                          unsigned int flags);
+
+/* Enum codes for buffer sizes supported by mPIPE. */
+typedef enum {
+        /* 128 byte packet data buffer. */
+        GXIO_MPIPE_BUFFER_SIZE_128 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_128,
+        /* 256 byte packet data buffer. */
+        GXIO_MPIPE_BUFFER_SIZE_256 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_256,
+        /* 512 byte packet data buffer. */
+        GXIO_MPIPE_BUFFER_SIZE_512 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_512,
+        /* 1024 byte packet data buffer. */
+        GXIO_MPIPE_BUFFER_SIZE_1024 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1024,
+        /* 1664 byte packet data buffer. */
+        GXIO_MPIPE_BUFFER_SIZE_1664 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_1664,
+        /* 4096 byte packet data buffer. */
+        GXIO_MPIPE_BUFFER_SIZE_4096 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_4096,
+        /* 10368 byte packet data buffer. */
+        GXIO_MPIPE_BUFFER_SIZE_10368 =
+                MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_10368,
+        /* 16384 byte packet data buffer. */
+        GXIO_MPIPE_BUFFER_SIZE_16384 = MPIPE_BSM_INIT_DAT_1__SIZE_VAL_BSZ_16384
+} gxio_mpipe_buffer_size_enum_t;
+
+/* Convert a buffer size in bytes into a buffer size enum. */
+extern gxio_mpipe_buffer_size_enum_t
+gxio_mpipe_buffer_size_to_buffer_size_enum(size_t size);
+
+/* Convert a buffer size enum into a buffer size in bytes. */
+extern size_t
+gxio_mpipe_buffer_size_enum_to_buffer_size(gxio_mpipe_buffer_size_enum_t
+                                           buffer_size_enum);
+
+/* Calculate the number of bytes required to store a given number of
+ * buffers in the memory registered with a buffer stack via
+ * gxio_mpipe_init_buffer_stack().
+ */
+extern size_t gxio_mpipe_calc_buffer_stack_bytes(unsigned long buffers);
+
+/* Initialize a buffer stack.  This function binds a region of memory
+ * to be used by the hardware for storing buffer addresses pushed via
+ * gxio_mpipe_push_buffer() or as the result of sending a buffer out
+ * the egress with the 'push to stack when done' bit set.  Once this
+ * function returns, the memory region's contents may be arbitrarily
+ * modified by the hardware at any time and software should not access
+ * the memory region again.
+ *
+ * @param context An initialized mPIPE context.
+ * @param stack The buffer stack index.
+ * @param buffer_size_enum The size of each buffer in the buffer stack,
+ * as an enum.
+ * @param mem The address of the buffer stack.  This memory must be
+ * physically contiguous and aligned to a 64kB boundary.
+ * @param mem_size The size of the buffer stack, in bytes.
+ * @param mem_flags ::gxio_mpipe_mem_flags_e memory flags.
+ * @return Zero on success, ::GXIO_MPIPE_ERR_INVAL_BUFFER_SIZE if
+ * buffer_size_enum is invalid, ::GXIO_MPIPE_ERR_BAD_BUFFER_STACK if
+ * stack has not been allocated.
+ */
+extern int gxio_mpipe_init_buffer_stack(gxio_mpipe_context_t *context,
+                                        unsigned int stack,
+                                        gxio_mpipe_buffer_size_enum_t
+                                        buffer_size_enum, void *mem,
+                                        size_t mem_size,
+                                        unsigned int mem_flags);
+
+/* Push a buffer onto a previously initialized buffer stack.
+ *
+ * The size of the buffer being pushed must match the size that was
+ * registered with gxio_mpipe_init_buffer_stack().  All packet buffer
+ * addresses are 128-byte aligned; the low 7 bits of the specified
+ * buffer address will be ignored.
+ *
+ * @param context An initialized mPIPE context.
+ * @param stack The buffer stack index.
+ * @param buffer The buffer (the low seven bits are ignored).
+ */
+static inline void gxio_mpipe_push_buffer(gxio_mpipe_context_t *context,
+                                          unsigned int stack, void *buffer)
+{
+        MPIPE_BSM_REGION_ADDR_t offset = { {0} };
+        MPIPE_BSM_REGION_VAL_t val = { {0} };
+
+        /*
+         * The mmio_fast_base region starts at the IDMA region, so subtract
+         * off that initial offset.
+         */
+        offset.region =
+                MPIPE_MMIO_ADDR__REGION_VAL_BSM -
+                MPIPE_MMIO_ADDR__REGION_VAL_IDMA;
+        offset.stack = stack;
+
+#if __SIZEOF_POINTER__ == 4
+        val.va = ((ulong) buffer) >> MPIPE_BSM_REGION_VAL__VA_SHIFT;
+#else
+        val.va = ((long)buffer) >> MPIPE_BSM_REGION_VAL__VA_SHIFT;
+#endif
+
+        __gxio_mmio_write(context->mmio_fast_base + offset.word, val.word);
+}
+
+/* Pop a buffer off of a previously initialized buffer stack.
+ *
+ * @param context An initialized mPIPE context.
+ * @param stack The buffer stack index.
+ * @return The buffer, or NULL if the stack is empty.
+ */
+static inline void *gxio_mpipe_pop_buffer(gxio_mpipe_context_t *context,
+                                          unsigned int stack)
+{
+        MPIPE_BSM_REGION_ADDR_t offset = { {0} };
+
+        /*
+         * The mmio_fast_base region starts at the IDMA region, so subtract
+         * off that initial offset.
+         */
+        offset.region =
+                MPIPE_MMIO_ADDR__REGION_VAL_BSM -
+                MPIPE_MMIO_ADDR__REGION_VAL_IDMA;
+        offset.stack = stack;
+
+        while (1) {
+                /*
+                 * Case 1: val.c == ..._UNCHAINED, va is non-zero.
+                 * Case 2: val.c == ..._INVALID, va is zero.
+                 * Case 3: val.c == ..._NOT_RDY, va is zero.
+                 */
+                MPIPE_BSM_REGION_VAL_t val;
+                val.word =
+                        __gxio_mmio_read(context->mmio_fast_base +
+                                         offset.word);
+
+                /*
+                 * Handle case 1 and 2 by returning the buffer (or NULL).
+                 * Handle case 3 by waiting for the prefetch buffer to refill.
+                 */
+                if (val.c != MPIPE_EDMA_DESC_WORD1__C_VAL_NOT_RDY)
+                        return (void *)((unsigned long)val.
+                                        va << MPIPE_BSM_REGION_VAL__VA_SHIFT);
+        }
+}
+
+/*****************************************************************
+ *                          NotifRings                            *
+ ******************************************************************/
+
+/* Allocate a set of NotifRings.
+ *
+ * The return value is NOT interesting if count is zero.
+ *
+ * Note that NotifRings are allocated in chunks, so allocating one at
+ * a time is much less efficient than allocating several at once.
+ *
+ * @param context An initialized mPIPE context.
+ * @param count Number of NotifRings required.
+ * @param first Index of first NotifRing if ::GXIO_MPIPE_ALLOC_FIXED flag
+ *   is set, otherwise ignored.
+ * @param flags Flag bits from ::gxio_mpipe_alloc_flags_e.
+ * @return Index of first allocated buffer NotifRing, or
+ * ::GXIO_MPIPE_ERR_NO_NOTIF_RING if allocation failed.
+ */
+extern int gxio_mpipe_alloc_notif_rings(gxio_mpipe_context_t *context,
+                                        unsigned int count, unsigned int first,
+                                        unsigned int flags);
+
+/* Initialize a NotifRing, using the given memory and size.
+ *
+ * @param context An initialized mPIPE context.
+ * @param ring The NotifRing index.
+ * @param mem A physically contiguous region of memory to be filled
+ * with a ring of ::gxio_mpipe_idesc_t structures.
+ * @param mem_size Number of bytes in the ring.  Must be 128, 512,
+ * 2048, or 65536 * sizeof(gxio_mpipe_idesc_t).
+ * @param mem_flags ::gxio_mpipe_mem_flags_e memory flags.
+ *
+ * @return 0 on success, ::GXIO_MPIPE_ERR_BAD_NOTIF_RING or
+ * ::GXIO_ERR_INVAL_MEMORY_SIZE on failure.
+ */
+extern int gxio_mpipe_init_notif_ring(gxio_mpipe_context_t *context,
+                                      unsigned int ring,
+                                      void *mem, size_t mem_size,
+                                      unsigned int mem_flags);
+
+/* Configure an interrupt to be sent to a tile on incoming NotifRing
+ *  traffic.  Once an interrupt is sent for a particular ring, no more
+ *  will be sent until gxio_mica_enable_notif_ring_interrupt() is called.
+ *
+ * @param context An initialized mPIPE context.
+ * @param x X coordinate of interrupt target tile.
+ * @param y Y coordinate of interrupt target tile.
+ * @param i Index of the IPI register which will receive the interrupt.
+ * @param e Specific event which will be set in the target IPI register when
+ * the interrupt occurs.
+ * @param ring The NotifRing index.
+ * @return Zero on success, GXIO_ERR_INVAL if params are out of range.
+ */
+extern int gxio_mpipe_request_notif_ring_interrupt(gxio_mpipe_context_t
+                                                   *context, int x, int y,
+                                                   int i, int e,
+                                                   unsigned int ring);
+
+/* Enable an interrupt on incoming NotifRing traffic.
+ *
+ * @param context An initialized mPIPE context.
+ * @param ring The NotifRing index.
+ * @return Zero on success, GXIO_ERR_INVAL if params are out of range.
+ */
+extern int gxio_mpipe_enable_notif_ring_interrupt(gxio_mpipe_context_t
+                                                  *context, unsigned int ring);
+
+/* Map all of a client's memory via the given IOTLB.
+ * @param context An initialized mPIPE context.
+ * @param iotlb IOTLB index.
+ * @param pte Page table entry.
+ * @param flags Flags.
+ * @return Zero on success, or a negative error code.
+ */
+extern int gxio_mpipe_register_client_memory(gxio_mpipe_context_t *context,
+                                             unsigned int iotlb, HV_PTE pte,
+                                             unsigned int flags);
+
+/*****************************************************************
+ *                        Notif Groups                            *
+ ******************************************************************/
+
+/* Allocate a set of NotifGroups.
+ *
+ * The return value is NOT interesting if count is zero.
+ *
+ * @param context An initialized mPIPE context.
+ * @param count Number of NotifGroups required.
+ * @param first Index of first NotifGroup if ::GXIO_MPIPE_ALLOC_FIXED flag
+ *   is set, otherwise ignored.
+ * @param flags Flag bits from ::gxio_mpipe_alloc_flags_e.
+ * @return Index of first allocated buffer NotifGroup, or
+ * ::GXIO_MPIPE_ERR_NO_NOTIF_GROUP if allocation failed.
+ */
+extern int gxio_mpipe_alloc_notif_groups(gxio_mpipe_context_t *context,
+                                         unsigned int count,
+                                         unsigned int first,
+                                         unsigned int flags);
+
+/* Add a NotifRing to a NotifGroup.  This only sets a bit in the
+ * application's 'group' object; the hardware NotifGroup can be
+ * initialized by passing 'group' to gxio_mpipe_init_notif_group() or
+ * gxio_mpipe_init_notif_group_and_buckets().
+ */
+static inline void
+gxio_mpipe_notif_group_add_ring(gxio_mpipe_notif_group_bits_t *bits, int ring)
+{
+        bits->ring_mask[ring / 64] |= (1ull << (ring % 64));
+}
+
+/* Set a particular NotifGroup bitmask.  Since the load balancer
+ * makes decisions based on both bucket and NotifGroup state, most
+ * applications should use gxio_mpipe_init_notif_group_and_buckets()
+ * rather than using this function to configure just a NotifGroup.
+ */
+extern int gxio_mpipe_init_notif_group(gxio_mpipe_context_t *context,
+                                       unsigned int group,
+                                       gxio_mpipe_notif_group_bits_t bits);
+
+/*****************************************************************
+ *                         Load Balancer                          *
+ ******************************************************************/
+
+/* Allocate a set of load balancer buckets.
+ *
+ * The return value is NOT interesting if count is zero.
+ *
+ * Note that buckets are allocated in chunks, so allocating one at
+ * a time is much less efficient than allocating several at once.
+ *
+ * Note that the buckets are actually divided into two sub-ranges, of
+ * different sizes, and different chunk sizes, and the range you get
+ * by default is determined by the size of the request.  Allocations
+ * cannot span the two sub-ranges.
+ *
+ * @param context An initialized mPIPE context.
+ * @param count Number of buckets required.
+ * @param first Index of first bucket if ::GXIO_MPIPE_ALLOC_FIXED flag is set,
+ *   otherwise ignored.
+ * @param flags Flag bits from ::gxio_mpipe_alloc_flags_e.
+ * @return Index of first allocated buffer bucket, or
+ * ::GXIO_MPIPE_ERR_NO_BUCKET if allocation failed.
+ */
+extern int gxio_mpipe_alloc_buckets(gxio_mpipe_context_t *context,
+                                    unsigned int count, unsigned int first,
+                                    unsigned int flags);
+
+/* The legal modes for gxio_mpipe_bucket_info_t and
+ * gxio_mpipe_init_notif_group_and_buckets().
+ *
+ * All modes except ::GXIO_MPIPE_BUCKET_ROUND_ROBIN expect that the user
+ * will allocate a power-of-two number of buckets and initialize them
+ * to the same mode.  The classifier program then uses the appropriate
+ * number of low bits from the incoming packet's flow hash to choose a
+ * load balancer bucket.  Based on that bucket's load balancing mode,
+ * reference count, and currently active NotifRing, the load balancer
+ * chooses the NotifRing to which the packet will be delivered.
+ */
+typedef enum {
+        /* All packets for a bucket go to the same NotifRing unless the
+         * NotifRing gets full, in which case packets will be dropped.  If
+         * the bucket reference count ever reaches zero, a new NotifRing may
+         * be chosen.
+         */
+        GXIO_MPIPE_BUCKET_DYNAMIC_FLOW_AFFINITY =
+                MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_DFA,
+
+        /* All packets for a bucket always go to the same NotifRing.
+         */
+        GXIO_MPIPE_BUCKET_STATIC_FLOW_AFFINITY =
+                MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_FIXED,
+
+        /* All packets for a bucket go to the least full NotifRing in the
+         * group, providing load balancing round robin behavior.
+         */
+        GXIO_MPIPE_BUCKET_ROUND_ROBIN =
+                MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_ALWAYS_PICK,
+
+        /* All packets for a bucket go to the same NotifRing unless the
+         * NotifRing gets full, at which point the bucket starts using the
+         * least full NotifRing in the group.  If all NotifRings in the
+         * group are full, packets will be dropped.
+         */
+        GXIO_MPIPE_BUCKET_STICKY_FLOW_LOCALITY =
+                MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY,
+
+        /* All packets for a bucket go to the same NotifRing unless the
+         * NotifRing gets full, or a random timer fires, at which point the
+         * bucket starts using the least full NotifRing in the group.  If
+         * all NotifRings in the group are full, packets will be dropped.
+         * WARNING: This mode is BROKEN on chips with fewer than 64 tiles.
+         */
+        GXIO_MPIPE_BUCKET_PREFER_FLOW_LOCALITY =
+                MPIPE_LBL_INIT_DAT_BSTS_TBL__MODE_VAL_STICKY_RAND,
+
+} gxio_mpipe_bucket_mode_t;
+
+/* Copy a set of bucket initialization values into the mPIPE
+ * hardware.  Since the load balancer makes decisions based on both
+ * bucket and NotifGroup state, most applications should use
+ * gxio_mpipe_init_notif_group_and_buckets() rather than using this
+ * function to configure a single bucket.
+ *
+ * @param context An initialized mPIPE context.
+ * @param bucket Bucket index to be initialized.
+ * @param bucket_info Initial reference count, NotifRing index, and mode.
+ * @return 0 on success, ::GXIO_MPIPE_ERR_BAD_BUCKET on failure.
+ */
+extern int gxio_mpipe_init_bucket(gxio_mpipe_context_t *context,
+                                  unsigned int bucket,
+                                  gxio_mpipe_bucket_info_t bucket_info);
+
+/* Initializes a group and range of buckets and range of rings such
+ * that the load balancer runs a particular load balancing function.
+ *
+ * First, the group is initialized with the given rings.
+ *
+ * Second, each bucket is initialized with the mode and group, and a
+ * ring chosen round-robin from the given rings.
+ *
+ * Normally, the classifier picks a bucket, and then the load balancer
+ * picks a ring, based on the bucket's mode, group, and current ring,
+ * possibly updating the bucket's ring.
+ *
+ * @param context An initialized mPIPE context.
+ * @param group The group.
+ * @param ring The first ring.
+ * @param num_rings The number of rings.
+ * @param bucket The first bucket.
+ * @param num_buckets The number of buckets.
+ * @param mode The load balancing mode.
+ *
+ * @return 0 on success, ::GXIO_MPIPE_ERR_BAD_BUCKET,
+ * ::GXIO_MPIPE_ERR_BAD_NOTIF_GROUP, or
+ * ::GXIO_MPIPE_ERR_BAD_NOTIF_RING on failure.
+ */
+extern int gxio_mpipe_init_notif_group_and_buckets(gxio_mpipe_context_t
+                                                   *context,
+                                                   unsigned int group,
+                                                   unsigned int ring,
+                                                   unsigned int num_rings,
+                                                   unsigned int bucket,
+                                                   unsigned int num_buckets,
+                                                   gxio_mpipe_bucket_mode_t
+                                                   mode);
+
+/* Return credits to a NotifRing and/or bucket.
+ *
+ * @param context An initialized mPIPE context.
+ * @param ring The NotifRing index, or -1.
+ * @param bucket The bucket, or -1.
+ * @param count The number of credits to return.
+ */
+static inline void gxio_mpipe_credit(gxio_mpipe_context_t *context,
+                                     int ring, int bucket, unsigned int count)
+{
+        /* NOTE: Fancy struct initialization would break "C89" header test. */
+
+        MPIPE_IDMA_RELEASE_REGION_ADDR_t offset = { {0} };
+        MPIPE_IDMA_RELEASE_REGION_VAL_t val = { {0} };
+
+        /*
+         * The mmio_fast_base region starts at the IDMA region, so subtract
+         * off that initial offset.
+         */
+        offset.region =
+                MPIPE_MMIO_ADDR__REGION_VAL_IDMA -
+                MPIPE_MMIO_ADDR__REGION_VAL_IDMA;
+        offset.ring = ring;
+        offset.bucket = bucket;
+        offset.ring_enable = (ring >= 0);
+        offset.bucket_enable = (bucket >= 0);
+        val.count = count;
+
+        __gxio_mmio_write(context->mmio_fast_base + offset.word, val.word);
+}
+
+/*****************************************************************
+ *                         Egress Rings                           *
+ ******************************************************************/
+
+/* Allocate a set of eDMA rings.
+ *
+ * The return value is NOT interesting if count is zero.
+ *
+ * @param context An initialized mPIPE context.
+ * @param count Number of eDMA rings required.
+ * @param first Index of first eDMA ring if ::GXIO_MPIPE_ALLOC_FIXED flag
+ *   is set, otherwise ignored.
+ * @param flags Flag bits from ::gxio_mpipe_alloc_flags_e.
+ * @return Index of first allocated buffer eDMA ring, or
+ * ::GXIO_MPIPE_ERR_NO_EDMA_RING if allocation failed.
+ */
+extern int gxio_mpipe_alloc_edma_rings(gxio_mpipe_context_t *context,
+                                       unsigned int count, unsigned int first,
+                                       unsigned int flags);
+
+/* Initialize an eDMA ring, using the given memory and size.
+ *
+ * @param context An initialized mPIPE context.
+ * @param ring The eDMA ring index.
+ * @param channel The channel to use.  This must be one of the channels
+ * associated with the context's set of open links.
+ * @param mem A physically contiguous region of memory to be filled
+ * with a ring of ::gxio_mpipe_edesc_t structures.
+ * @param mem_size Number of bytes in the ring.  Must be 512, 2048,
+ * 8192 or 65536, times 16 (i.e. sizeof(gxio_mpipe_edesc_t)).
+ * @param mem_flags ::gxio_mpipe_mem_flags_e memory flags.
+ *
+ * @return 0 on success, ::GXIO_MPIPE_ERR_BAD_EDMA_RING or
+ * ::GXIO_ERR_INVAL_MEMORY_SIZE on failure.
+ */
+extern int gxio_mpipe_init_edma_ring(gxio_mpipe_context_t *context,
+                                     unsigned int ring, unsigned int channel,
+                                     void *mem, size_t mem_size,
+                                     unsigned int mem_flags);
+
+/*****************************************************************
+ *                      Classifier Program                        *
+ ******************************************************************/
+
+/*
+ *
+ * Functions for loading or configuring the mPIPE classifier program.
+ *
+ * The mPIPE classification processors all run a special "classifier"
+ * program which, for each incoming packet, parses the packet headers,
+ * encodes some packet metadata in the "idesc", and either drops the
+ * packet, or picks a notif ring to handle the packet, and a buffer
+ * stack to contain the packet, usually based on the channel, VLAN,
+ * dMAC, flow hash, and packet size, under the guidance of the "rules"
+ * API described below.
+ *
+ * @section gxio_mpipe_classifier_default Default Classifier
+ *
+ * The MDE provides a simple "default" classifier program.  It is
+ * shipped as source in "$TILERA_ROOT/src/sys/mpipe/classifier.c",
+ * which serves as its official documentation.  It is shipped as a
+ * binary program in "$TILERA_ROOT/tile/boot/classifier", which is
+ * automatically included in bootroms created by "tile-monitor", and
+ * is automatically loaded by the hypervisor at boot time.
+ *
+ * The L2 analysis handles LLC packets, SNAP packets, and "VLAN
+ * wrappers" (keeping the outer VLAN).
+ *
+ * The L3 analysis handles IPv4 and IPv6, dropping packets with bad
+ * IPv4 header checksums, requesting computation of a TCP/UDP checksum
+ * if appropriate, and hashing the dest and src IP addresses, plus the
+ * ports for TCP/UDP packets, into the flow hash.  No special analysis
+ * is done for "fragmented" packets or "tunneling" protocols.  Thus,
+ * the first fragment of a fragmented TCP/UDP packet is hashed using
+ * src/dest IP address and ports and all subsequent fragments are only
+ * hashed according to src/dest IP address.
+ *
+ * The L3 analysis handles other packets too, hashing the dMAC
+ * smac into a flow hash.
+ *
+ * The channel, VLAN, and dMAC used to pick a "rule" (see the
+ * "rules" APIs below), which in turn is used to pick a buffer stack
+ * (based on the packet size) and a bucket (based on the flow hash).
+ *
+ * To receive traffic matching a particular (channel/VLAN/dMAC
+ * pattern, an application should allocate its own buffer stacks and
+ * load balancer buckets, and map traffic to those stacks and buckets,
+ * as decribed by the "rules" API below.
+ *
+ * Various packet metadata is encoded in the idesc.  The flow hash is
+ * four bytes at 0x0C.  The VLAN is two bytes at 0x10.  The ethtype is
+ * two bytes at 0x12.  The l3 start is one byte at 0x14.  The l4 start
+ * is one byte at 0x15 for IPv4 and IPv6 packets, and otherwise zero.
+ * The protocol is one byte at 0x16 for IPv4 and IPv6 packets, and
+ * otherwise zero.
+ *
+ * @section gxio_mpipe_classifier_custom Custom Classifiers.
+ *
+ * A custom classifier may be created using "tile-mpipe-cc" with a
+ * customized version of the default classifier sources.
+ *
+ * The custom classifier may be included in bootroms using the
+ * "--classifier" option to "tile-monitor", or loaded dynamically
+ * using gxio_mpipe_classifier_load_from_file().
+ *
+ * Be aware that "extreme" customizations may break the assumptions of
+ * the "rules" APIs described below, but simple customizations, such
+ * as adding new packet metadata, should be fine.
+ */
+
+/* A set of classifier rules, plus a context. */
+typedef struct {
+
+        /* The context. */
+        gxio_mpipe_context_t *context;
+
+        /* The actual rules. */
+        gxio_mpipe_rules_list_t list;
+
+} gxio_mpipe_rules_t;
+
+/* Initialize a classifier program rules list.
+ *
+ * This function can be called on a previously initialized rules list
+ * to discard any previously added rules.
+ *
+ * @param rules Rules list to initialize.
+ * @param context An initialized mPIPE context.
+ */
+extern void gxio_mpipe_rules_init(gxio_mpipe_rules_t *rules,
+                                  gxio_mpipe_context_t *context);
+
+/* Begin a new rule on the indicated rules list.
+ *
+ * Note that an empty rule matches all packets, but an empty rule list
+ * matches no packets.
+ *
+ * @param rules Rules list to which new rule is appended.
+ * @param bucket First load balancer bucket to which packets will be
+ * delivered.
+ * @param num_buckets Number of buckets (must be a power of two) across
+ * which packets will be distributed based on the "flow hash".
+ * @param stacks Either NULL, to assign each packet to the smallest
+ * initialized buffer stack which does not induce chaining (and to
+ * drop packets which exceed the largest initialized buffer stack
+ * buffer size), or an array, with each entry indicating which buffer
+ * stack should be used for packets up to that size (with 255
+ * indicating that those packets should be dropped).
+ * @return 0 on success, or a negative error code on failure.
+ */
+extern int gxio_mpipe_rules_begin(gxio_mpipe_rules_t *rules,
+                                  unsigned int bucket,
+                                  unsigned int num_buckets,
+                                  gxio_mpipe_rules_stacks_t *stacks);
+
+/* Set the headroom of the current rule.
+ *
+ * @param rules Rules list whose current rule will be modified.
+ * @param headroom The headroom.
+ * @return 0 on success, or a negative error code on failure.
+ */
+extern int gxio_mpipe_rules_set_headroom(gxio_mpipe_rules_t *rules,
+                                         uint8_t headroom);
+
+/* Indicate that packets from a particular channel can be delivered
+ * to the buckets and buffer stacks associated with the current rule.
+ *
+ * Channels added must be associated with links opened by the mPIPE context
+ * used in gxio_mpipe_rules_init().  A rule with no channels is equivalent
+ * to a rule naming all such associated channels.
+ *
+ * @param rules Rules list whose current rule will be modified.
+ * @param channel The channel to add.
+ * @return 0 on success, or a negative error code on failure.
+ */
+extern int gxio_mpipe_rules_add_channel(gxio_mpipe_rules_t *rules,
+                                        unsigned int channel);
+
+/* Commit rules.
+ *
+ * The rules are sent to the hypervisor, where they are combined with
+ * the rules from other apps, and used to program the hardware classifier.
+ *
+ * Note that if this function returns an error, then the rules will NOT
+ * have been committed, even if the error is due to interactions with
+ * rules from another app.
+ *
+ * @param rules Rules list to commit.
+ * @return 0 on success, or a negative error code on failure.
+ */
+extern int gxio_mpipe_rules_commit(gxio_mpipe_rules_t *rules);
+
+/*****************************************************************
+ *                     Ingress Queue Wrapper                      *
+ ******************************************************************/
+
+/*
+ *
+ * Convenience functions for receiving packets from a NotifRing and
+ * sending packets via an eDMA ring.
+ *
+ * The mpipe ingress and egress hardware uses shared memory packet
+ * descriptors to describe packets that have arrived on ingress or
+ * are destined for egress.  These descriptors are stored in shared
+ * memory ring buffers and written or read by hardware as necessary.
+ * The gxio library provides wrapper functions that manage the head and
+ * tail pointers for these rings, allowing the user to easily read or
+ * write packet descriptors.
+ *
+ * The initialization interface for ingress and egress rings is quite
+ * similar.  For example, to create an ingress queue, the user passes
+ * a ::gxio_mpipe_iqueue_t state object, a ring number from
+ * gxio_mpipe_alloc_notif_rings(), and the address of memory to hold a
+ * ring buffer to the gxio_mpipe_iqueue_init() function.  The function
+ * returns success when the state object has been initialized and the
+ * hardware configured to deliver packets to the specified ring
+ * buffer.  Similarly, gxio_mpipe_equeue_init() takes a
+ * ::gxio_mpipe_equeue_t state object, a ring number from
+ * gxio_mpipe_alloc_edma_rings(), and a shared memory buffer.
+ *
+ * @section gxio_mpipe_iqueue Working with Ingress Queues
+ *
+ * Once initialized, the gxio_mpipe_iqueue_t API provides two flows
+ * for getting the ::gxio_mpipe_idesc_t packet descriptor associated
+ * with incoming packets.  The simplest is to call
+ * gxio_mpipe_iqueue_get() or gxio_mpipe_iqueue_try_get().  These
+ * functions copy the oldest packet descriptor out of the NotifRing and
+ * into a descriptor provided by the caller.  They also immediately
+ * inform the hardware that a descriptor has been processed.
+ *
+ * For applications with stringent performance requirements, higher
+ * efficiency can be achieved by avoiding the packet descriptor copy
+ * and processing multiple descriptors at once.  The
+ * gxio_mpipe_iqueue_peek() and gxio_mpipe_iqueue_try_peek() functions
+ * allow such optimizations.  These functions provide a pointer to the
+ * next valid ingress descriptor in the NotifRing's shared memory ring
+ * buffer, and a count of how many contiguous descriptors are ready to
+ * be processed.  The application can then process any number of those
+ * descriptors in place, calling gxio_mpipe_iqueue_consume() to inform
+ * the hardware after each one has been processed.
+ *
+ * @section gxio_mpipe_equeue Working with Egress Queues
+ *
+ * Similarly, the egress queue API provides a high-performance
+ * interface plus a simple wrapper for use in posting
+ * ::gxio_mpipe_edesc_t egress packet descriptors.  The simple
+ * version, gxio_mpipe_equeue_put(), allows the programmer to wait for
+ * an eDMA ring slot to become available and write a single descriptor
+ * into the ring.
+ *
+ * Alternatively, you can reserve slots in the eDMA ring using
+ * gxio_mpipe_equeue_reserve() or gxio_mpipe_equeue_try_reserve(), and
+ * then fill in each slot using gxio_mpipe_equeue_put_at().  This
+ * capability can be used to amortize the cost of reserving slots
+ * across several packets.  It also allows gather operations to be
+ * performed on a shared equeue, by ensuring that the edescs for all
+ * the fragments are all contiguous in the eDMA ring.
+ *
+ * The gxio_mpipe_equeue_reserve() and gxio_mpipe_equeue_try_reserve()
+ * functions return a 63-bit "completion slot", which is actually a
+ * sequence number, the low bits of which indicate the ring buffer
+ * index and the high bits the number of times the application has
+ * gone around the egress ring buffer.  The extra bits allow an
+ * application to check for egress completion by calling
+ * gxio_mpipe_equeue_is_complete() to see whether a particular 'slot'
+ * number has finished.  Given the maximum packet rates of the Gx
+ * processor, the 63-bit slot number will never wrap.
+ *
+ * In practice, most applications use the ::gxio_mpipe_edesc_t::hwb
+ * bit to indicate that the buffers containing egress packet data
+ * should be pushed onto a buffer stack when egress is complete.  Such
+ * applications generally do not need to know when an egress operation
+ * completes (since there is no need to free a buffer post-egress),
+ * and thus can use the optimized gxio_mpipe_equeue_reserve_fast() or
+ * gxio_mpipe_equeue_try_reserve_fast() functions, which return a 24
+ * bit "slot", instead of a 63-bit "completion slot".
+ *
+ * Once a slot has been "reserved", it MUST be filled.  If the
+ * application reserves a slot and then decides that it does not
+ * actually need it, it can set the ::gxio_mpipe_edesc_t::ns (no send)
+ * bit on the descriptor passed to gxio_mpipe_equeue_put_at() to
+ * indicate that no data should be sent.  This technique can also be
+ * used to drop an incoming packet, instead of forwarding it, since
+ * any buffer will still be pushed onto the buffer stack when the
+ * egress descriptor is processed.
+ */
+
+/* A convenient interface to a NotifRing, for use by a single thread.
+ */
+typedef struct {
+
+        /* The context. */
+        gxio_mpipe_context_t *context;
+
+        /* The actual NotifRing. */
+        gxio_mpipe_idesc_t *idescs;
+
+        /* The number of entries. */
+        unsigned long num_entries;
+
+        /* The number of entries minus one. */
+        unsigned long mask_num_entries;
+
+        /* The log2() of the number of entries. */
+        unsigned long log2_num_entries;
+
+        /* The next entry. */
+        unsigned int head;
+
+        /* The NotifRing id. */
+        unsigned int ring;
+
+#ifdef __BIG_ENDIAN__
+        /* The number of byteswapped entries. */
+        unsigned int swapped;
+#endif
+
+} gxio_mpipe_iqueue_t;
+
+/* Initialize an "iqueue".
+ *
+ * Takes the iqueue plus the same args as gxio_mpipe_init_notif_ring().
+ */
+extern int gxio_mpipe_iqueue_init(gxio_mpipe_iqueue_t *iqueue,
+                                  gxio_mpipe_context_t *context,
+                                  unsigned int ring,
+                                  void *mem, size_t mem_size,
+                                  unsigned int mem_flags);
+
+/* Advance over some old entries in an iqueue.
+ *
+ * Please see the documentation for gxio_mpipe_iqueue_consume().
+ *
+ * @param iqueue An ingress queue initialized via gxio_mpipe_iqueue_init().
+ * @param count The number of entries to advance over.
+ */
+static inline void gxio_mpipe_iqueue_advance(gxio_mpipe_iqueue_t *iqueue,
+                                             int count)
+{
+        /* Advance with proper wrap. */
+        int head = iqueue->head + count;
+        iqueue->head =
+                (head & iqueue->mask_num_entries) +
+                (head >> iqueue->log2_num_entries);
+
+#ifdef __BIG_ENDIAN__
+        /* HACK: Track swapped entries. */
+        iqueue->swapped -= count;
+#endif
+}
+
+/* Release the ring and bucket for an old entry in an iqueue.
+ *
+ * Releasing the ring allows more packets to be delivered to the ring.
+ *
+ * Releasing the bucket allows flows using the bucket to be moved to a
+ * new ring when using GXIO_MPIPE_BUCKET_DYNAMIC_FLOW_AFFINITY.
+ *
+ * This function is shorthand for "gxio_mpipe_credit(iqueue->context,
+ * iqueue->ring, idesc->bucket_id, 1)", and it may be more convenient
+ * to make that underlying call, using those values, instead of
+ * tracking the entire "idesc".
+ *
+ * If packet processing is deferred, optimal performance requires that
+ * the releasing be deferred as well.
+ *
+ * Please see the documentation for gxio_mpipe_iqueue_consume().
+ *
+ * @param iqueue An ingress queue initialized via gxio_mpipe_iqueue_init().
+ * @param idesc The descriptor which was processed.
+ */
+static inline void gxio_mpipe_iqueue_release(gxio_mpipe_iqueue_t *iqueue,
+                                             gxio_mpipe_idesc_t *idesc)
+{
+        gxio_mpipe_credit(iqueue->context, iqueue->ring, idesc->bucket_id, 1);
+}
+
+/* Consume a packet from an "iqueue".
+ *
+ * After processing packets peeked at via gxio_mpipe_iqueue_peek()
+ * or gxio_mpipe_iqueue_try_peek(), you must call this function, or
+ * gxio_mpipe_iqueue_advance() plus gxio_mpipe_iqueue_release(), to
+ * advance over those entries, and release their rings and buckets.
+ *
+ * You may call this function as each packet is processed, or you can
+ * wait until several packets have been processed.
+ *
+ * Note that if you are using a single bucket, and you are handling
+ * batches of N packets, then you can replace several calls to this
+ * function with calls to "gxio_mpipe_iqueue_advance(iqueue, N)" and
+ * "gxio_mpipe_credit(iqueue->context, iqueue->ring, bucket, N)".
+ *
+ * Note that if your classifier sets "idesc->nr", then you should
+ * explicitly call "gxio_mpipe_iqueue_advance(iqueue, idesc)" plus
+ * "gxio_mpipe_credit(iqueue->context, iqueue->ring, -1, 1)", to
+ * avoid incorrectly crediting the (unused) bucket.
+ *
+ * @param iqueue An ingress queue initialized via gxio_mpipe_iqueue_init().
+ * @param idesc The descriptor which was processed.
+ */
+static inline void gxio_mpipe_iqueue_consume(gxio_mpipe_iqueue_t *iqueue,
+                                             gxio_mpipe_idesc_t *idesc)
+{
+        gxio_mpipe_iqueue_advance(iqueue, 1);
+        gxio_mpipe_iqueue_release(iqueue, idesc);
+}
+
+/* Peek at the next packet(s) in an "iqueue", without waiting.
+ *
+ * If no packets are available, fills idesc_ref with NULL, and then
+ * returns ::GXIO_MPIPE_ERR_IQUEUE_EMPTY.  Otherwise, fills idesc_ref
+ * with the address of the next valid packet descriptor, and returns
+ * the maximum number of valid descriptors which can be processed.
+ * You may process fewer descriptors if desired.
+ *
+ * Call gxio_mpipe_iqueue_consume() on each packet once it has been
+ * processed (or dropped), to allow more packets to be delivered.
+ *
+ * @param iqueue An ingress queue initialized via gxio_mpipe_iqueue_init().
+ * @param idesc_ref A pointer to a packet descriptor pointer.
+ * @return The (positive) number of packets which can be processed,
+ * or ::GXIO_MPIPE_ERR_IQUEUE_EMPTY if no packets are available.
+ */
+static inline int gxio_mpipe_iqueue_try_peek(gxio_mpipe_iqueue_t *iqueue,
+                                             gxio_mpipe_idesc_t **idesc_ref)
+{
+        gxio_mpipe_idesc_t *next;
+
+        uint64_t head = iqueue->head;
+        uint64_t tail = __gxio_mmio_read(iqueue->idescs);
+
+        /* Available entries. */
+        uint64_t avail =
+                (tail >= head) ? (tail - head) : (iqueue->num_entries - head);
+
+        if (avail == 0) {
+                *idesc_ref = NULL;
+                return GXIO_MPIPE_ERR_IQUEUE_EMPTY;
+        }
+
+        next = &iqueue->idescs[head];
+
+        /* ISSUE: Is this helpful? */
+        __insn_prefetch(next);
+
+#ifdef __BIG_ENDIAN__
+        /* HACK: Swap new entries directly in memory. */
+        {
+                int i, j;
+                for (i = iqueue->swapped; i < avail; i++) {
+                        for (j = 0; j < 8; j++)
+                                next[i].words[j] =
+                                        __builtin_bswap64(next[i].words[j]);
+                }
+                iqueue->swapped = avail;
+        }
+#endif
+
+        *idesc_ref = next;
+
+        return avail;
+}
+
+/* Drop a packet by pushing its buffer (if appropriate).
+ *
+ * NOTE: The caller must still call gxio_mpipe_iqueue_consume() if idesc
+ * came from gxio_mpipe_iqueue_try_peek() or gxio_mpipe_iqueue_peek().
+ *
+ * @param iqueue An ingress queue initialized via gxio_mpipe_iqueue_init().
+ * @param idesc A packet descriptor.
+ */
+static inline void gxio_mpipe_iqueue_drop(gxio_mpipe_iqueue_t *iqueue,
+                                          gxio_mpipe_idesc_t *idesc)
+{
+        /* FIXME: Handle "chaining" properly. */
+
+        if (!idesc->be) {
+                unsigned char *va = gxio_mpipe_idesc_get_va(idesc);
+                gxio_mpipe_push_buffer(iqueue->context, idesc->stack_idx, va);
+        }
+}
+
+/*****************************************************************
+ *                      Egress Queue Wrapper                      *
+ ******************************************************************/
+
+/* A convenient, thread-safe interface to an eDMA ring. */
+typedef struct {
+
+        /* State object for tracking head and tail pointers. */
+        __gxio_dma_queue_t dma_queue;
+
+        /* The ring entries. */
+        gxio_mpipe_edesc_t *edescs;
+
+        /* The number of entries minus one. */
+        unsigned long mask_num_entries;
+
+        /* The log2() of the number of entries. */
+        unsigned long log2_num_entries;
+
+} gxio_mpipe_equeue_t;
+
+/* Initialize an "equeue".
+ *
+ * Takes the equeue plus the same args as gxio_mpipe_init_edma_ring().
+ */
+extern int gxio_mpipe_equeue_init(gxio_mpipe_equeue_t *equeue,
+                                  gxio_mpipe_context_t *context,
+                                  unsigned int edma_ring_id,
+                                  unsigned int channel,
+                                  void *mem, unsigned int mem_size,
+                                  unsigned int mem_flags);
+
+/* Reserve completion slots for edescs.
+ *
+ * Use gxio_mpipe_equeue_put_at() to actually populate the slots.
+ *
+ * This function is slower than gxio_mpipe_equeue_reserve_fast(), but
+ * returns a full 64 bit completion slot, which can be used with
+ * gxio_mpipe_equeue_is_complete().
+ *
+ * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
+ * @param num Number of slots to reserve (must be non-zero).
+ * @return The first reserved completion slot, or a negative error code.
+ */
+static inline int64_t gxio_mpipe_equeue_reserve(gxio_mpipe_equeue_t *equeue,
+                                                unsigned int num)
+{
+        return __gxio_dma_queue_reserve_aux(&equeue->dma_queue, num, true);
+}
+
+/* Reserve completion slots for edescs, if possible.
+ *
+ * Use gxio_mpipe_equeue_put_at() to actually populate the slots.
+ *
+ * This function is slower than gxio_mpipe_equeue_try_reserve_fast(),
+ * but returns a full 64 bit completion slot, which can be used with
+ * gxio_mpipe_equeue_is_complete().
+ *
+ * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
+ * @param num Number of slots to reserve (must be non-zero).
+ * @return The first reserved completion slot, or a negative error code.
+ */
+static inline int64_t gxio_mpipe_equeue_try_reserve(gxio_mpipe_equeue_t
+                                                    *equeue, unsigned int num)
+{
+        return __gxio_dma_queue_reserve_aux(&equeue->dma_queue, num, false);
+}
+
+/* Reserve slots for edescs.
+ *
+ * Use gxio_mpipe_equeue_put_at() to actually populate the slots.
+ *
+ * This function is faster than gxio_mpipe_equeue_reserve(), but
+ * returns a 24 bit slot (instead of a 64 bit completion slot), which
+ * thus cannot be used with gxio_mpipe_equeue_is_complete().
+ *
+ * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
+ * @param num Number of slots to reserve (should be non-zero).
+ * @return The first reserved slot, or a negative error code.
+ */
+static inline int64_t gxio_mpipe_equeue_reserve_fast(gxio_mpipe_equeue_t
+                                                     *equeue, unsigned int num)
+{
+        return __gxio_dma_queue_reserve(&equeue->dma_queue, num, true, false);
+}
+
+/* Reserve slots for edescs, if possible.
+ *
+ * Use gxio_mpipe_equeue_put_at() to actually populate the slots.
+ *
+ * This function is faster than gxio_mpipe_equeue_try_reserve(), but
+ * returns a 24 bit slot (instead of a 64 bit completion slot), which
+ * thus cannot be used with gxio_mpipe_equeue_is_complete().
+ *
+ * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
+ * @param num Number of slots to reserve (should be non-zero).
+ * @return The first reserved slot, or a negative error code.
+ */
+static inline int64_t gxio_mpipe_equeue_try_reserve_fast(gxio_mpipe_equeue_t
+                                                         *equeue,
+                                                         unsigned int num)
+{
+        return __gxio_dma_queue_reserve(&equeue->dma_queue, num, false, false);
+}
+
+/*
+ * HACK: This helper function tricks gcc 4.6 into avoiding saving
+ * a copy of "edesc->words[0]" on the stack for no obvious reason.
+ */
+
+static inline void gxio_mpipe_equeue_put_at_aux(gxio_mpipe_equeue_t *equeue,
+                                                uint_reg_t ew[2],
+                                                unsigned long slot)
+{
+        unsigned long edma_slot = slot & equeue->mask_num_entries;
+        gxio_mpipe_edesc_t *edesc_p = &equeue->edescs[edma_slot];
+
+        /*
+         * ISSUE: Could set eDMA ring to be on generation 1 at start, which
+         * would avoid the negation here, perhaps allowing "__insn_bfins()".
+         */
+        ew[0] |= !((slot >> equeue->log2_num_entries) & 1);
+
+        /*
+         * NOTE: We use "__gxio_mpipe_write()", plus the fact that the eDMA
+         * queue alignment restrictions ensure that these two words are on
+         * the same cacheline, to force proper ordering between the stores.
+         */
+        __gxio_mmio_write64(&edesc_p->words[1], ew[1]);
+        __gxio_mmio_write64(&edesc_p->words[0], ew[0]);
+}
+
+/* Post an edesc to a given slot in an equeue.
+ *
+ * This function copies the supplied edesc into entry "slot mod N" in
+ * the underlying ring, setting the "gen" bit to the appropriate value
+ * based on "(slot mod N*2)", where "N" is the size of the ring.  Note
+ * that the higher bits of slot are unused, and thus, this function
+ * can handle "slots" as well as "completion slots".
+ *
+ * Normally this function is used to fill in slots reserved by
+ * gxio_mpipe_equeue_try_reserve(), gxio_mpipe_equeue_reserve(),
+ * gxio_mpipe_equeue_try_reserve_fast(), or
+ * gxio_mpipe_equeue_reserve_fast(),
+ *
+ * This function can also be used without "reserving" slots, if the
+ * application KNOWS that the ring can never overflow, for example, by
+ * pushing fewer buffers into the buffer stacks than there are total
+ * slots in the equeue, but this is NOT recommended.
+ *
+ * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
+ * @param edesc The egress descriptor to be posted.
+ * @param slot An egress slot (only the low bits are actually used).
+ */
+static inline void gxio_mpipe_equeue_put_at(gxio_mpipe_equeue_t *equeue,
+                                            gxio_mpipe_edesc_t edesc,
+                                            unsigned long slot)
+{
+        gxio_mpipe_equeue_put_at_aux(equeue, edesc.words, slot);
+}
+
+/* Post an edesc to the next slot in an equeue.
+ *
+ * This is a convenience wrapper around
+ * gxio_mpipe_equeue_reserve_fast() and gxio_mpipe_equeue_put_at().
+ *
+ * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
+ * @param edesc The egress descriptor to be posted.
+ * @return 0 on success.
+ */
+static inline int gxio_mpipe_equeue_put(gxio_mpipe_equeue_t *equeue,
+                                        gxio_mpipe_edesc_t edesc)
+{
+        int64_t slot = gxio_mpipe_equeue_reserve_fast(equeue, 1);
+        if (slot < 0)
+                return (int)slot;
+
+        gxio_mpipe_equeue_put_at(equeue, edesc, slot);
+
+        return 0;
+}
+
+/* Ask the mPIPE hardware to egress outstanding packets immediately.
+ *
+ * This call is not necessary, but may slightly reduce overall latency.
+ *
+ * Technically, you should flush all gxio_mpipe_equeue_put_at() writes
+ * to memory before calling this function, to ensure the descriptors
+ * are visible in memory before the mPIPE hardware actually looks for
+ * them.  But this should be very rare, and the only side effect would
+ * be increased latency, so it is up to the caller to decide whether
+ * or not to flush memory.
+ *
+ * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
+ */
+static inline void gxio_mpipe_equeue_flush(gxio_mpipe_equeue_t *equeue)
+{
+        /* Use "ring_idx = 0" and "count = 0" to "wake up" the eDMA ring. */
+        MPIPE_EDMA_POST_REGION_VAL_t val = { {0} };
+        /* Flush the write buffers. */
+        __insn_flushwb();
+        __gxio_mmio_write(equeue->dma_queue.post_region_addr, val.word);
+}
+
+/* Determine if a given edesc has been completed.
+ *
+ * Note that this function requires a "completion slot", and thus may
+ * NOT be used with a "slot" from gxio_mpipe_equeue_reserve_fast() or
+ * gxio_mpipe_equeue_try_reserve_fast().
+ *
+ * @param equeue An egress queue initialized via gxio_mpipe_equeue_init().
+ * @param completion_slot The completion slot used by the edesc.
+ * @param update If true, and the desc does not appear to have completed
+ * yet, then update any software cache of the hardware completion counter,
+ * and check again.  This should normally be true.
+ * @return True iff the given edesc has been completed.
+ */
+static inline int gxio_mpipe_equeue_is_complete(gxio_mpipe_equeue_t *equeue,
+                                                int64_t completion_slot,
+                                                int update)
+{
+        return __gxio_dma_queue_is_complete(&equeue->dma_queue,
+                                            completion_slot, update);
+}
+
+/*****************************************************************
+ *                        Link Management                         *
+ ******************************************************************/
+
+/*
+ *
+ * Functions for manipulating and sensing the state and configuration
+ * of physical network links.
+ *
+ * @section gxio_mpipe_link_perm Link Permissions
+ *
+ * Opening a link (with gxio_mpipe_link_open()) requests a set of link
+ * permissions, which control what may be done with the link, and potentially
+ * what permissions may be granted to other processes.
+ *
+ * Data permission allows the process to receive packets from the link by
+ * specifying the link's channel number in mPIPE packet distribution rules,
+ * and to send packets to the link by using the link's channel number as
+ * the target for an eDMA ring.
+ *
+ * Stats permission allows the process to retrieve link attributes (such as
+ * the speeds it is capable of running at, or whether it is currently up), and
+ * to read and write certain statistics-related registers in the link's MAC.
+ *
+ * Control permission allows the process to retrieve and modify link attributes
+ * (so that it may, for example, bring the link up and take it down), and
+ * read and write many registers in the link's MAC and PHY.
+ *
+ * Any permission may be requested as shared, which allows other processes
+ * to also request shared permission, or exclusive, which prevents other
+ * processes from requesting it.  In keeping with GXIO's typical usage in
+ * an embedded environment, the defaults for all permissions are shared.
+ *
+ * Permissions are granted on a first-come, first-served basis, so if two
+ * applications request an exclusive permission on the same link, the one
+ * to run first will win.  Note, however, that some system components, like
+ * the kernel Ethernet driver, may get an opportunity to open links before
+ * any applications run.
+ *
+ * @section gxio_mpipe_link_names Link Names
+ *
+ * Link names are of the form gbe<em>number</em> (for Gigabit Ethernet),
+ * xgbe<em>number</em> (for 10 Gigabit Ethernet), loop<em>number</em> (for
+ * internal mPIPE loopback), or ilk<em>number</em>/<em>channel</em>
+ * (for Interlaken links); for instance, gbe0, xgbe1, loop3, and
+ * ilk0/12 are all possible link names.  The correspondence between
+ * the link name and an mPIPE instance number or mPIPE channel number is
+ * system-dependent; all links will not exist on all systems, and the set
+ * of numbers used for a particular link type may not start at zero and may
+ * not be contiguous.  Use gxio_mpipe_link_enumerate() to retrieve the set of
+ * links which exist on a system, and always use gxio_mpipe_link_instance()
+ * to determine which mPIPE controls a particular link.
+ *
+ * Note that in some cases, links may share hardware, such as PHYs, or
+ * internal mPIPE buffers; in these cases, only one of the links may be
+ * opened at a time.  This is especially common with xgbe and gbe ports,
+ * since each xgbe port uses 4 SERDES lanes, each of which may also be
+ * configured as one gbe port.
+ *
+ * @section gxio_mpipe_link_states Link States
+ *
+ * The mPIPE link management model revolves around three different states,
+ * which are maintained for each link:
+ *
+ * 1. The <em>current</em> link state: is the link up now, and if so, at
+ *    what speed?
+ *
+ * 2. The <em>desired</em> link state: what do we want the link state to be?
+ *    The system is always working to make this state the current state;
+ *    thus, if the desired state is up, and the link is down, we'll be
+ *    constantly trying to bring it up, automatically.
+ *
+ * 3. The <em>possible</em> link state: what speeds are valid for this
+ *    particular link?  Or, in other words, what are the capabilities of
+ *    the link hardware?
+ *
+ * These link states are not, strictly speaking, related to application
+ * state; they may be manipulated at any time, whether or not the link
+ * is currently being used for data transfer.  However, for convenience,
+ * gxio_mpipe_link_open() and gxio_mpipe_link_close() (or application exit)
+ * can affect the link state.  These implicit link management operations
+ * may be modified or disabled by the use of link open flags.
+ *
+ * From an application, you can use gxio_mpipe_link_get_attr()
+ * and gxio_mpipe_link_set_attr() to manipulate the link states.
+ * gxio_mpipe_link_get_attr() with ::GXIO_MPIPE_LINK_POSSIBLE_STATE
+ * gets you the possible link state.  gxio_mpipe_link_get_attr() with
+ * ::GXIO_MPIPE_LINK_CURRENT_STATE gets you the current link state.
+ * Finally, gxio_mpipe_link_set_attr() and gxio_mpipe_link_get_attr()
+ * with ::GXIO_MPIPE_LINK_DESIRED_STATE allow you to modify or retrieve
+ * the desired link state.
+ *
+ * If you want to manage a link from a part of your application which isn't
+ * involved in packet processing, you can use the ::GXIO_MPIPE_LINK_NO_DATA
+ * flags on a gxio_mpipe_link_open() call.  This opens the link, but does
+ * not request data permission, so it does not conflict with any exclusive
+ * permissions which may be held by other processes.  You can then can use
+ * gxio_mpipe_link_get_attr() and gxio_mpipe_link_set_attr() on this link
+ * object to bring up or take down the link.
+ *
+ * Some links support link state bits which support various loopback
+ * modes. ::GXIO_MPIPE_LINK_LOOP_MAC tests datapaths within the Tile
+ * Processor itself; ::GXIO_MPIPE_LINK_LOOP_PHY tests the datapath between
+ * the Tile Processor and the external physical layer interface chip; and
+ * ::GXIO_MPIPE_LINK_LOOP_EXT tests the entire network datapath with the
+ * aid of an external loopback connector.  In addition to enabling hardware
+ * testing, such configuration can be useful for software testing, as well.
+ *
+ * When LOOP_MAC or LOOP_PHY is enabled, packets transmitted on a channel
+ * will be received by that channel, instead of being emitted on the
+ * physical link, and packets received on the physical link will be ignored.
+ * Other than that, all standard GXIO operations work as you might expect.
+ * Note that loopback operation requires that the link be brought up using
+ * one or more of the GXIO_MPIPE_LINK_SPEED_xxx link state bits.
+ *
+ * Those familiar with previous versions of the MDE on TILEPro hardware
+ * will notice significant similarities between the NetIO link management
+ * model and the mPIPE link management model.  However, the NetIO model
+ * was developed in stages, and some of its features -- for instance,
+ * the default setting of certain flags -- were shaped by the need to be
+ * compatible with previous versions of NetIO.  Since the features provided
+ * by the mPIPE hardware and the mPIPE GXIO library are significantly
+ * different than those provided by NetIO, in some cases, we have made
+ * different choices in the mPIPE link management API.  Thus, please read
+ * this documentation carefully before assuming that mPIPE link management
+ * operations are exactly equivalent to their NetIO counterparts.
+ */
+
+/* An object used to manage mPIPE link state and resources. */
+typedef struct {
+        /* The overall mPIPE context. */
+        gxio_mpipe_context_t *context;
+
+        /* The channel number used by this link. */
+        uint8_t channel;
+
+        /* The MAC index used by this link. */
+        uint8_t mac;
+} gxio_mpipe_link_t;
+
+/* Retrieve one of this system's legal link names, and its MAC address.
+ *
+ * @param index Link name index.  If a system supports N legal link names,
+ *  then indices between 0 and N - 1, inclusive, each correspond to one of
+ *  those names.  Thus, to retrieve all of a system's legal link names,
+ *  call this function in a loop, starting with an index of zero, and
+ *  incrementing it once per iteration until -1 is returned.
+ * @param link_name Pointer to the buffer which will receive the retrieved
+ *  link name.  The buffer should contain space for at least
+ *  ::GXIO_MPIPE_LINK_NAME_LEN bytes; the returned name, including the
+ *  terminating null byte, will be no longer than that.
+ * @param link_name Pointer to the buffer which will receive the retrieved
+ *  MAC address.  The buffer should contain space for at least 6 bytes.
+ * @return Zero if a link name was successfully retrieved; -1 if one was
+ *  not.
+ */
+extern int gxio_mpipe_link_enumerate_mac(int index, char *link_name,
+                                         uint8_t *mac_addr);
+
+/* Open an mPIPE link.
+ *
+ *  A link must be opened before it may be used to send or receive packets,
+ *  and before its state may be examined or changed.  Depending up on the
+ *  link's intended use, one or more link permissions may be requested via
+ *  the flags parameter; see @ref gxio_mpipe_link_perm.  In addition, flags
+ *  may request that the link's state be modified at open time.  See @ref
+ *  gxio_mpipe_link_states and @ref gxio_mpipe_link_open_flags for more detail.
+ *
+ * @param link A link state object, which will be initialized if this
+ *  function completes successfully.
+ * @param context An initialized mPIPE context.
+ * @param link_name Name of the link.
+ * @param flags Zero or more @ref gxio_mpipe_link_open_flags, ORed together.
+ * @return 0 if the link was successfully opened, or a negative error code.
+ *
+ */
+extern int gxio_mpipe_link_open(gxio_mpipe_link_t *link,
+                                gxio_mpipe_context_t *context,
+                                const char *link_name, unsigned int flags);
+
+/* Close an mPIPE link.
+ *
+ *  Closing a link makes it available for use by other processes.  Once
+ *  a link has been closed, packets may no longer be sent on or received
+ *  from the link, and its state may not be examined or changed.
+ *
+ * @param link A link state object, which will no longer be initialized
+ *  if this function completes successfully.
+ * @return 0 if the link was successfully closed, or a negative error code.
+ *
+ */
+extern int gxio_mpipe_link_close(gxio_mpipe_link_t *link);
+
+/* Return a link's channel number.
+ *
+ * @param link A properly initialized link state object.
+ * @return The channel number for the link.
+ */
+static inline int gxio_mpipe_link_channel(gxio_mpipe_link_t *link)
+{
+        return link->channel;
+}
+
+///////////////////////////////////////////////////////////////////
+//                             Timestamp                         //
+///////////////////////////////////////////////////////////////////
+
+/* Get the timestamp of mPIPE when this routine is called.
+ *
+ * @param context An initialized mPIPE context.
+ * @param ts A timespec structure to store the current clock.
+ * @return If the call was successful, zero; otherwise, a negative error
+ *  code.
+ */
+extern int gxio_mpipe_get_timestamp(gxio_mpipe_context_t *context,
+                                    struct timespec *ts);
+
+/* Set the timestamp of mPIPE.
+ *
+ * @param context An initialized mPIPE context.
+ * @param ts A timespec structure to store the requested clock.
+ * @return If the call was successful, zero; otherwise, a negative error
+ *  code.
+ */
+extern int gxio_mpipe_set_timestamp(gxio_mpipe_context_t *context,
+                                    const struct timespec *ts);
+
+/* Adjust the timestamp of mPIPE.
+ *
+ * @param context An initialized mPIPE context.
+ * @param delta A signed time offset to adjust, in nanoseconds.
+ * The absolute value of this parameter must be less than or
+ * equal to 1000000000.
+ * @return If the call was successful, zero; otherwise, a negative error
+ *  code.
+ */
+extern int gxio_mpipe_adjust_timestamp(gxio_mpipe_context_t *context,
+                                       int64_t delta);
+
+#endif /* !_GXIO_MPIPE_H_ */
diff --git a/arch/tile/include/gxio/trio.h b/arch/tile/include/gxio/trio.h
new file mode 100644
index 00000000000..77b80cdd46d
--- /dev/null
+++ b/arch/tile/include/gxio/trio.h
@@ -0,0 +1,298 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/*
+ *
+ * An API for allocating, configuring, and manipulating TRIO hardware
+ * resources
+ */
+
+/*
+ *
+ * The TILE-Gx TRIO shim provides connections to external devices via
+ * PCIe or other transaction IO standards.  The gxio_trio_ API,
+ * declared in <gxio/trio.h>, allows applications to allocate and
+ * configure TRIO IO resources like DMA command rings, memory map
+ * windows, and device interrupts.  The following sections introduce
+ * the various components of the API.  We strongly recommend reading
+ * the TRIO section of the IO Device Guide (UG404) before working with
+ * this API.
+ *
+ * @section trio__ingress TRIO Ingress Hardware Resources
+ *
+ * The TRIO ingress hardware is responsible for examining incoming
+ * PCIe or StreamIO packets and choosing a processing mechanism based
+ * on the packets' bus address.  The gxio_trio_ API can be used to
+ * configure different handlers for different ranges of bus address
+ * space.  The user can configure "mapped memory" and "scatter queue"
+ * regions to match incoming packets within 4kB-aligned ranges of bus
+ * addresses.  Each range specifies a different set of mapping
+ * parameters to be applied when handling the ingress packet.  The
+ * following sections describe how to work with MapMem and scatter
+ * queue regions.
+ *
+ * @subsection trio__mapmem TRIO MapMem Regions
+ *
+ * TRIO mapped memory (or MapMem) regions allow the user to map
+ * incoming read and write requests directly to the application's
+ * memory space.  MapMem regions are allocated via
+ * gxio_trio_alloc_memory_maps().  Given an integer MapMem number,
+ * applications can use gxio_trio_init_memory_map() to specify the
+ * range of bus addresses that will match the region and the range of
+ * virtual addresses to which those packets will be applied.
+ *
+ * As with many other gxio APIs, the programmer must be sure to
+ * register memory pages that will be used with MapMem regions.  Pages
+ * can be registered with TRIO by allocating an ASID (address space
+ * identifier) and then using gxio_trio_register_page() to register up to
+ * 16 pages with the hardware.  The initialization functions for
+ * resources that require registered memory (MapMem, scatter queues,
+ * push DMA, and pull DMA) then take an 'asid' parameter in order to
+ * configure which set of registered pages is used by each resource.
+ *
+ * @subsection trio__scatter_queue TRIO Scatter Queues
+ *
+ * The TRIO shim's scatter queue regions allow users to dynamically
+ * map buffers from a large address space into a small range of bus
+ * addresses.  This is particularly helpful for PCIe endpoint devices,
+ * where the host generally limits the size of BARs to tens of
+ * megabytes.
+ *
+ * Each scatter queue consists of a memory map region, a queue of
+ * tile-side buffer VAs to be mapped to that region, and a bus-mapped
+ * "doorbell" register that the remote endpoint can write to trigger a
+ * dequeue of the current buffer VA, thus swapping in a new buffer.
+ * The VAs pushed onto a scatter queue must be 4kB aligned, so
+ * applications may need to use higher-level protocols to inform
+ * remote entities that they should apply some additional, sub-4kB
+ * offset when reading or writing the scatter queue region.  For more
+ * information, see the IO Device Guide (UG404).
+ *
+ * @section trio__egress TRIO Egress Hardware Resources
+ *
+ * The TRIO shim supports two mechanisms for egress packet generation:
+ * programmed IO (PIO) and push/pull DMA.  PIO allows applications to
+ * create MMIO mappings for PCIe or StreamIO address space, such that
+ * the application can generate word-sized read or write transactions
+ * by issuing load or store instructions.  Push and pull DMA are tuned
+ * for larger transactions; they use specialized hardware engines to
+ * transfer large blocks of data at line rate.
+ *
+ * @subsection trio__pio TRIO Programmed IO
+ *
+ * Programmed IO allows applications to create MMIO mappings for PCIe
+ * or StreamIO address space.  The hardware PIO regions support access
+ * to PCIe configuration, IO, and memory space, but the gxio_trio API
+ * only supports memory space accesses.  PIO regions are allocated
+ * with gxio_trio_alloc_pio_regions() and initialized via
+ * gxio_trio_init_pio_region().  Once a region is bound to a range of
+ * bus address via the initialization function, the application can
+ * use gxio_trio_map_pio_region() to create MMIO mappings from its VA
+ * space onto the range of bus addresses supported by the PIO region.
+ *
+ * @subsection trio_dma TRIO Push and Pull DMA
+ *
+ * The TRIO push and pull DMA engines allow users to copy blocks of
+ * data between application memory and the bus.  Push DMA generates
+ * write packets that copy from application memory to the bus and pull
+ * DMA generates read packets that copy from the bus into application
+ * memory.  The DMA engines are managed via an API that is very
+ * similar to the mPIPE eDMA interface.  For a detailed explanation of
+ * the eDMA queue API, see @ref gxio_mpipe_wrappers.
+ *
+ * Push and pull DMA queues are allocated via
+ * gxio_trio_alloc_push_dma_ring() / gxio_trio_alloc_pull_dma_ring().
+ * Once allocated, users generally use a ::gxio_trio_dma_queue_t
+ * object to manage the queue, providing easy wrappers for reserving
+ * command slots in the DMA command ring, filling those slots, and
+ * waiting for commands to complete.  DMA queues can be initialized
+ * via gxio_trio_init_push_dma_queue() or
+ * gxio_trio_init_pull_dma_queue().
+ *
+ * See @ref trio/push_dma/app.c for an example of how to use push DMA.
+ *
+ * @section trio_shortcomings Plans for Future API Revisions
+ *
+ * The simulation framework is incomplete.  Future features include:
+ *
+ * - Support for reset and deallocation of resources.
+ *
+ * - Support for pull DMA.
+ *
+ * - Support for interrupt regions and user-space interrupt delivery.
+ *
+ * - Support for getting BAR mappings and reserving regions of BAR
+ *   address space.
+ */
+#ifndef _GXIO_TRIO_H_
+#define _GXIO_TRIO_H_
+
+#include <linux/types.h>
+
+#include "common.h"
+#include "dma_queue.h"
+
+#include <arch/trio_constants.h>
+#include <arch/trio.h>
+#include <arch/trio_pcie_intfc.h>
+#include <arch/trio_pcie_rc.h>
+#include <arch/trio_shm.h>
+#include <hv/drv_trio_intf.h>
+#include <hv/iorpc.h>
+
+/* A context object used to manage TRIO hardware resources. */
+typedef struct {
+
+        /* File descriptor for calling up to Linux (and thus the HV). */
+        int fd;
+
+        /* The VA at which the MAC MMIO registers are mapped. */
+        char *mmio_base_mac;
+
+        /* The VA at which the PIO config space are mapped for each PCIe MAC.
+           Gx36 has max 3 PCIe MACs per TRIO shim. */
+        char *mmio_base_pio_cfg[TILEGX_TRIO_PCIES];
+
+#ifdef USE_SHARED_PCIE_CONFIG_REGION
+        /* Index of the shared PIO region for PCI config access. */
+        int pio_cfg_index;
+#else
+        /* Index of the PIO region for PCI config access per MAC. */
+        int pio_cfg_index[TILEGX_TRIO_PCIES];
+#endif
+
+        /*  The VA at which the push DMA MMIO registers are mapped. */
+        char *mmio_push_dma[TRIO_NUM_PUSH_DMA_RINGS];
+
+        /*  The VA at which the pull DMA MMIO registers are mapped. */
+        char *mmio_pull_dma[TRIO_NUM_PUSH_DMA_RINGS];
+
+        /* Application space ID. */
+        unsigned int asid;
+
+} gxio_trio_context_t;
+
+/* Command descriptor for push or pull DMA. */
+typedef TRIO_DMA_DESC_t gxio_trio_dma_desc_t;
+
+/* A convenient, thread-safe interface to an eDMA ring. */
+typedef struct {
+
+        /* State object for tracking head and tail pointers. */
+        __gxio_dma_queue_t dma_queue;
+
+        /* The ring entries. */
+        gxio_trio_dma_desc_t *dma_descs;
+
+        /* The number of entries minus one. */
+        unsigned long mask_num_entries;
+
+        /* The log2() of the number of entries. */
+        unsigned int log2_num_entries;
+
+} gxio_trio_dma_queue_t;
+
+/* Initialize a TRIO context.
+ *
+ * This function allocates a TRIO "service domain" and maps the MMIO
+ * registers into the the caller's VA space.
+ *
+ * @param trio_index Which TRIO shim; Gx36 must pass 0.
+ * @param context Context object to be initialized.
+ */
+extern int gxio_trio_init(gxio_trio_context_t *context,
+                          unsigned int trio_index);
+
+/* This indicates that an ASID hasn't been allocated. */
+#define GXIO_ASID_NULL -1
+
+/* Ordering modes for map memory regions and scatter queue regions. */
+typedef enum gxio_trio_order_mode_e {
+        /* Writes are not ordered.  Reads always wait for previous writes. */
+        GXIO_TRIO_ORDER_MODE_UNORDERED =
+                TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_UNORDERED,
+        /* Both writes and reads wait for previous transactions to complete. */
+        GXIO_TRIO_ORDER_MODE_STRICT =
+                TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_STRICT,
+        /* Writes are ordered unless the incoming packet has the
+           relaxed-ordering attributes set. */
+        GXIO_TRIO_ORDER_MODE_OBEY_PACKET =
+                TRIO_MAP_MEM_SETUP__ORDER_MODE_VAL_REL_ORD
+} gxio_trio_order_mode_t;
+
+/* Initialize a memory mapping region.
+ *
+ * @param context An initialized TRIO context.
+ * @param map A Memory map region allocated by gxio_trio_alloc_memory_map().
+ * @param target_mem VA of backing memory, should be registered via
+ *   gxio_trio_register_page() and aligned to 4kB.
+ * @param target_size Length of the memory mapping, must be a multiple
+ * of 4kB.
+ * @param asid ASID to be used for Tile-side address translation.
+ * @param mac MAC number.
+ * @param bus_address Bus address at which the mapping starts.
+ * @param order_mode Memory ordering mode for this mapping.
+ * @return Zero on success, else ::GXIO_TRIO_ERR_BAD_MEMORY_MAP,
+ * GXIO_TRIO_ERR_BAD_ASID, or ::GXIO_TRIO_ERR_BAD_BUS_RANGE.
+ */
+extern int gxio_trio_init_memory_map(gxio_trio_context_t *context,
+                                     unsigned int map, void *target_mem,
+                                     size_t target_size, unsigned int asid,
+                                     unsigned int mac, uint64_t bus_address,
+                                     gxio_trio_order_mode_t order_mode);
+
+/* Flags that can be passed to resource allocation functions. */
+enum gxio_trio_alloc_flags_e {
+        GXIO_TRIO_ALLOC_FIXED = HV_TRIO_ALLOC_FIXED,
+};
+
+/* Flags that can be passed to memory registration functions. */
+enum gxio_trio_mem_flags_e {
+        /* Do not fill L3 when writing, and invalidate lines upon egress. */
+        GXIO_TRIO_MEM_FLAG_NT_HINT = IORPC_MEM_BUFFER_FLAG_NT_HINT,
+
+        /* L3 cache fills should only populate IO cache ways. */
+        GXIO_TRIO_MEM_FLAG_IO_PIN = IORPC_MEM_BUFFER_FLAG_IO_PIN,
+};
+
+/* Flag indicating a request generator uses a special traffic
+    class. */
+#define GXIO_TRIO_FLAG_TRAFFIC_CLASS(N) HV_TRIO_FLAG_TC(N)
+
+/* Flag indicating a request generator uses a virtual function
+    number. */
+#define GXIO_TRIO_FLAG_VFUNC(N) HV_TRIO_FLAG_VFUNC(N)
+
+/*****************************************************************
+ *                       Memory Registration                      *
+ ******************************************************************/
+
+/* Allocate Application Space Identifiers (ASIDs).  Each ASID can
+ * register up to 16 page translations.  ASIDs are used by memory map
+ * regions, scatter queues, and DMA queues to translate application
+ * VAs into memory system PAs.
+ *
+ * @param context An initialized TRIO context.
+ * @param count Number of ASIDs required.
+ * @param first Index of first ASID if ::GXIO_TRIO_ALLOC_FIXED flag
+ *   is set, otherwise ignored.
+ * @param flags Flag bits, including bits from ::gxio_trio_alloc_flags_e.
+ * @return Index of first ASID, or ::GXIO_TRIO_ERR_NO_ASID if allocation
+ *   failed.
+ */
+extern int gxio_trio_alloc_asids(gxio_trio_context_t *context,
+                                 unsigned int count, unsigned int first,
+                                 unsigned int flags);
+
+#endif /* ! _GXIO_TRIO_H_ */
diff --git a/arch/tile/include/gxio/usb_host.h b/arch/tile/include/gxio/usb_host.h
new file mode 100644
index 00000000000..a60a126e456
--- /dev/null
+++ b/arch/tile/include/gxio/usb_host.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+#ifndef _GXIO_USB_H_
+#define _GXIO_USB_H_
+
+#include "common.h"
+
+#include <hv/drv_usb_host_intf.h>
+#include <hv/iorpc.h>
+
+/*
+ *
+ * An API for manipulating general-purpose I/O pins.
+ */
+
+/*
+ *
+ * The USB shim allows access to the processor's Universal Serial Bus
+ * connections.
+ */
+
+/* A context object used to manage USB hardware resources. */
+typedef struct {
+
+        /* File descriptor for calling up to the hypervisor. */
+        int fd;
+
+        /* The VA at which our MMIO registers are mapped. */
+        char *mmio_base;
+} gxio_usb_host_context_t;
+
+/* Initialize a USB context.
+ *
+ *  A properly initialized context must be obtained before any of the other
+ *  gxio_usb_host routines may be used.
+ *
+ * @param context Pointer to a gxio_usb_host_context_t, which will be
+ *  initialized by this routine, if it succeeds.
+ * @param usb_index Index of the USB shim to use.
+ * @param is_ehci Nonzero to use the EHCI interface; zero to use the OHCI
+ *  intereface.
+ * @return Zero if the context was successfully initialized, else a
+ *  GXIO_ERR_xxx error code.
+ */
+extern int gxio_usb_host_init(gxio_usb_host_context_t * context, int usb_index,
+                              int is_ehci);
+
+/* Destroy a USB context.
+ *
+ *  Once destroyed, a context may not be used with any gxio_usb_host routines
+ *  other than gxio_usb_host_init().  After this routine returns, no further
+ *  interrupts or signals requested on this context will be delivered.  The
+ *  state and configuration of the pins which had been attached to this
+ *  context are unchanged by this operation.
+ *
+ * @param context Pointer to a gxio_usb_host_context_t.
+ * @return Zero if the context was successfully destroyed, else a
+ *  GXIO_ERR_xxx error code.
+ */
+extern int gxio_usb_host_destroy(gxio_usb_host_context_t * context);
+
+/* Retrieve the address of the shim's MMIO registers.
+ *
+ * @param context Pointer to a properly initialized gxio_usb_host_context_t.
+ * @return The address of the shim's MMIO registers.
+ */
+extern void *gxio_usb_host_get_reg_start(gxio_usb_host_context_t * context);
+
+/* Retrieve the length of the shim's MMIO registers.
+ *
+ * @param context Pointer to a properly initialized gxio_usb_host_context_t.
+ * @return The length of the shim's MMIO registers.
+ */
+extern size_t gxio_usb_host_get_reg_len(gxio_usb_host_context_t * context);
+
+#endif /* _GXIO_USB_H_ */
diff --git a/arch/tile/include/hv/drv_mpipe_intf.h b/arch/tile/include/hv/drv_mpipe_intf.h
new file mode 100644
index 00000000000..6cdae3bf046
--- /dev/null
+++ b/arch/tile/include/hv/drv_mpipe_intf.h
@@ -0,0 +1,602 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/**
+ * Interface definitions for the mpipe driver.
+ */
+
+#ifndef _SYS_HV_DRV_MPIPE_INTF_H
+#define _SYS_HV_DRV_MPIPE_INTF_H
+
+#include <arch/mpipe.h>
+#include <arch/mpipe_constants.h>
+
+
+/** Number of buffer stacks (32). */
+#define HV_MPIPE_NUM_BUFFER_STACKS \
+  (MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH)
+
+/** Number of NotifRings (256). */
+#define HV_MPIPE_NUM_NOTIF_RINGS (MPIPE_NUM_NOTIF_RINGS)
+
+/** Number of NotifGroups (32). */
+#define HV_MPIPE_NUM_NOTIF_GROUPS (MPIPE_NUM_NOTIF_GROUPS)
+
+/** Number of buckets (4160). */
+#define HV_MPIPE_NUM_BUCKETS (MPIPE_NUM_BUCKETS)
+
+/** Number of "lo" buckets (4096). */
+#define HV_MPIPE_NUM_LO_BUCKETS 4096
+
+/** Number of "hi" buckets (64). */
+#define HV_MPIPE_NUM_HI_BUCKETS \
+  (HV_MPIPE_NUM_BUCKETS - HV_MPIPE_NUM_LO_BUCKETS)
+
+/** Number of edma rings (24). */
+#define HV_MPIPE_NUM_EDMA_RINGS \
+  (MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH)
+
+
+
+
+/** A flag bit indicating a fixed resource allocation. */
+#define HV_MPIPE_ALLOC_FIXED 0x01
+
+/** Offset for the config register MMIO region. */
+#define HV_MPIPE_CONFIG_MMIO_OFFSET \
+  (MPIPE_MMIO_ADDR__REGION_VAL_CFG << MPIPE_MMIO_ADDR__REGION_SHIFT)
+
+/** Size of the config register MMIO region. */
+#define HV_MPIPE_CONFIG_MMIO_SIZE (64 * 1024)
+
+/** Offset for the config register MMIO region. */
+#define HV_MPIPE_FAST_MMIO_OFFSET \
+  (MPIPE_MMIO_ADDR__REGION_VAL_IDMA << MPIPE_MMIO_ADDR__REGION_SHIFT)
+
+/** Size of the fast register MMIO region (IDMA, EDMA, buffer stack). */
+#define HV_MPIPE_FAST_MMIO_SIZE \
+  ((MPIPE_MMIO_ADDR__REGION_VAL_BSM + 1 - MPIPE_MMIO_ADDR__REGION_VAL_IDMA) \
+   << MPIPE_MMIO_ADDR__REGION_SHIFT)
+
+
+/*
+ * Each type of resource allocation comes in quantized chunks, where
+ * XXX_BITS is the number of chunks, and XXX_RES_PER_BIT is the number
+ * of resources in each chunk.
+ */
+
+/** Number of buffer stack chunks available (32). */
+#define HV_MPIPE_ALLOC_BUFFER_STACKS_BITS \
+  MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH
+
+/** Granularity of buffer stack allocation (1). */
+#define HV_MPIPE_ALLOC_BUFFER_STACKS_RES_PER_BIT \
+  (HV_MPIPE_NUM_BUFFER_STACKS / HV_MPIPE_ALLOC_BUFFER_STACKS_BITS)
+
+/** Number of NotifRing chunks available (32). */
+#define HV_MPIPE_ALLOC_NOTIF_RINGS_BITS \
+  MPIPE_MMIO_INIT_DAT_GX36_0__NOTIF_RING_MASK_WIDTH
+
+/** Granularity of NotifRing allocation (8). */
+#define HV_MPIPE_ALLOC_NOTIF_RINGS_RES_PER_BIT \
+  (HV_MPIPE_NUM_NOTIF_RINGS / HV_MPIPE_ALLOC_NOTIF_RINGS_BITS)
+
+/** Number of NotifGroup chunks available (32). */
+#define HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS \
+  HV_MPIPE_NUM_NOTIF_GROUPS
+
+/** Granularity of NotifGroup allocation (1). */
+#define HV_MPIPE_ALLOC_NOTIF_GROUPS_RES_PER_BIT \
+  (HV_MPIPE_NUM_NOTIF_GROUPS / HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS)
+
+/** Number of lo bucket chunks available (16). */
+#define HV_MPIPE_ALLOC_LO_BUCKETS_BITS \
+  MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_LO_WIDTH
+
+/** Granularity of lo bucket allocation (256). */
+#define HV_MPIPE_ALLOC_LO_BUCKETS_RES_PER_BIT \
+  (HV_MPIPE_NUM_LO_BUCKETS / HV_MPIPE_ALLOC_LO_BUCKETS_BITS)
+
+/** Number of hi bucket chunks available (16). */
+#define HV_MPIPE_ALLOC_HI_BUCKETS_BITS \
+  MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_HI_WIDTH
+
+/** Granularity of hi bucket allocation (4). */
+#define HV_MPIPE_ALLOC_HI_BUCKETS_RES_PER_BIT \
+  (HV_MPIPE_NUM_HI_BUCKETS / HV_MPIPE_ALLOC_HI_BUCKETS_BITS)
+
+/** Number of eDMA ring chunks available (24). */
+#define HV_MPIPE_ALLOC_EDMA_RINGS_BITS \
+  MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH
+
+/** Granularity of eDMA ring allocation (1). */
+#define HV_MPIPE_ALLOC_EDMA_RINGS_RES_PER_BIT \
+  (HV_MPIPE_NUM_EDMA_RINGS / HV_MPIPE_ALLOC_EDMA_RINGS_BITS)
+
+
+
+
+/** Bit vector encoding which NotifRings are in a NotifGroup. */
+typedef struct
+{
+  /** The actual bits. */
+  uint64_t ring_mask[4];
+
+} gxio_mpipe_notif_group_bits_t;
+
+
+/** Another name for MPIPE_LBL_INIT_DAT_BSTS_TBL_t. */
+typedef MPIPE_LBL_INIT_DAT_BSTS_TBL_t gxio_mpipe_bucket_info_t;
+
+
+
+/** Eight buffer stack ids. */
+typedef struct
+{
+  /** The stacks. */
+  uint8_t stacks[8];
+
+} gxio_mpipe_rules_stacks_t;
+
+
+/** A destination mac address. */
+typedef struct
+{
+  /** The octets. */
+  uint8_t octets[6];
+
+} gxio_mpipe_rules_dmac_t;
+
+
+/** A vlan. */
+typedef uint16_t gxio_mpipe_rules_vlan_t;
+
+
+
+/** Maximum number of characters in a link name. */
+#define GXIO_MPIPE_LINK_NAME_LEN  32
+
+
+/** Structure holding a link name.  Only needed, and only typedef'ed,
+ *  because the IORPC stub generator only handles types which are single
+ *  words coming before the parameter name. */
+typedef struct
+{
+  /** The name itself. */
+  char name[GXIO_MPIPE_LINK_NAME_LEN];
+}
+_gxio_mpipe_link_name_t;
+
+/** Maximum number of characters in a symbol name. */
+#define GXIO_MPIPE_SYMBOL_NAME_LEN  128
+
+
+/** Structure holding a symbol name.  Only needed, and only typedef'ed,
+ *  because the IORPC stub generator only handles types which are single
+ *  words coming before the parameter name. */
+typedef struct
+{
+  /** The name itself. */
+  char name[GXIO_MPIPE_SYMBOL_NAME_LEN];
+}
+_gxio_mpipe_symbol_name_t;
+
+
+/** Structure holding a MAC address. */
+typedef struct
+{
+  /** The address. */
+  uint8_t mac[6];
+}
+_gxio_mpipe_link_mac_t;
+
+
+
+/** Request shared data permission -- that is, the ability to send and
+ *  receive packets -- on the specified link.  Other processes may also
+ *  request shared data permission on the same link.
+ *
+ *  No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
+ *  or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
+ */
+#define GXIO_MPIPE_LINK_DATA               0x00000001UL
+
+/** Do not request data permission on the specified link.
+ *
+ *  No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
+ *  or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
+ */
+#define GXIO_MPIPE_LINK_NO_DATA            0x00000002UL
+
+/** Request exclusive data permission -- that is, the ability to send and
+ *  receive packets -- on the specified link.  No other processes may
+ *  request data permission on this link, and if any process already has
+ *  data permission on it, this open will fail.
+ *
+ *  No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
+ *  or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
+ */
+#define GXIO_MPIPE_LINK_EXCL_DATA          0x00000004UL
+
+/** Request shared stats permission -- that is, the ability to read and write
+ *  registers which contain link statistics, and to get link attributes --
+ *  on the specified link.  Other processes may also request shared stats
+ *  permission on the same link.
+ *
+ *  No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
+ *  or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
+ */
+#define GXIO_MPIPE_LINK_STATS              0x00000008UL
+
+/** Do not request stats permission on the specified link.
+ *
+ *  No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
+ *  or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
+ */
+#define GXIO_MPIPE_LINK_NO_STATS           0x00000010UL
+
+/** Request exclusive stats permission -- that is, the ability to read and
+ *  write registers which contain link statistics, and to get link
+ *  attributes -- on the specified link.  No other processes may request
+ *  stats permission on this link, and if any process already
+ *  has stats permission on it, this open will fail.
+ *
+ *  Requesting exclusive stats permission is normally a very bad idea, since
+ *  it prevents programs like mpipe-stat from providing information on this
+ *  link.  Applications should only do this if they use MAC statistics
+ *  registers, and cannot tolerate any of the clear-on-read registers being
+ *  reset by other statistics programs.
+ *
+ *  No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
+ *  or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
+ */
+#define GXIO_MPIPE_LINK_EXCL_STATS         0x00000020UL
+
+/** Request shared control permission -- that is, the ability to modify link
+ *  attributes, and read and write MAC and MDIO registers -- on the
+ *  specified link.  Other processes may also request shared control
+ *  permission on the same link.
+ *
+ *  No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
+ *  or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
+ */
+#define GXIO_MPIPE_LINK_CTL                0x00000040UL
+
+/** Do not request control permission on the specified link.
+ *
+ *  No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
+ *  or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
+ */
+#define GXIO_MPIPE_LINK_NO_CTL             0x00000080UL
+
+/** Request exclusive control permission -- that is, the ability to modify
+ *  link attributes, and read and write MAC and MDIO registers -- on the
+ *  specified link.  No other processes may request control permission on
+ *  this link, and if any process already has control permission on it,
+ *  this open will fail.
+ *
+ *  Requesting exclusive control permission is not always a good idea, since
+ *  it prevents programs like mpipe-link from configuring the link.
+ *
+ *  No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
+ *  or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
+ */
+#define GXIO_MPIPE_LINK_EXCL_CTL           0x00000100UL
+
+/** Set the desired state of the link to up, allowing any speeds which are
+ *  supported by the link hardware, as part of this open operation; do not
+ *  change the desired state of the link when it is closed or the process
+ *  exits.  No more than one of ::GXIO_MPIPE_LINK_AUTO_UP,
+ *  ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or
+ *  ::GXIO_MPIPE_LINK_AUTO_NONE may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
+ */
+#define GXIO_MPIPE_LINK_AUTO_UP            0x00000200UL
+
+/** Set the desired state of the link to up, allowing any speeds which are
+ *  supported by the link hardware, as part of this open operation; when the
+ *  link is closed or this process exits, if no other process has the link
+ *  open, set the desired state of the link to down.  No more than one of
+ *  ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN,
+ *  ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be
+ *  specifed in a gxio_mpipe_link_open() call.  If none are specified,
+ *  ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
+ */
+#define GXIO_MPIPE_LINK_AUTO_UPDOWN        0x00000400UL
+
+/** Do not change the desired state of the link as part of the open
+ *  operation; when the link is closed or this process exits, if no other
+ *  process has the link open, set the desired state of the link to down.
+ *  No more than one of ::GXIO_MPIPE_LINK_AUTO_UP,
+ *  ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or
+ *  ::GXIO_MPIPE_LINK_AUTO_NONE may be specifed in a gxio_mpipe_link_open()
+ *  call.  If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
+ */
+#define GXIO_MPIPE_LINK_AUTO_DOWN          0x00000800UL
+
+/** Do not change the desired state of the link as part of the open
+ *  operation; do not change the desired state of the link when it is
+ *  closed or the process exits.  No more than one of
+ *  ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN,
+ *  ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be
+ *  specifed in a gxio_mpipe_link_open() call.  If none are specified,
+ *  ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
+ */
+#define GXIO_MPIPE_LINK_AUTO_NONE          0x00001000UL
+
+/** Request that this open call not complete until the network link is up.
+ *  The process will wait as long as necessary for this to happen;
+ *  applications which wish to abandon waiting for the link after a
+ *  specific time period should not specify this flag when opening a link,
+ *  but should instead call gxio_mpipe_link_wait() afterward.  The link
+ *  must be opened with stats permission.  Note that this flag by itself
+ *  does not change the desired link state; if other open flags or previous
+ *  link state changes have not requested a desired state of up, the open
+ *  call will never complete.  This flag is not available to kernel
+ *  clients.
+ */
+#define GXIO_MPIPE_LINK_WAIT               0x00002000UL
+
+
+/*
+ * Note: link attributes must fit in 24 bits, since we use the top 8 bits
+ * of the IORPC offset word for the channel number.
+ */
+
+/** Determine whether jumbo frames may be received.  If this attribute's
+ *  value value is nonzero, the MAC will accept frames of up to 10240 bytes.
+ *  If the value is zero, the MAC will only accept frames of up to 1544
+ *  bytes.  The default value is zero. */
+#define GXIO_MPIPE_LINK_RECEIVE_JUMBO      0x010000
+
+/** Determine whether to send pause frames on this link if the mPIPE packet
+ *  FIFO is nearly full.  If the value is zero, pause frames are not sent.
+ *  If the value is nonzero, it is the delay value which will be sent in any
+ *  pause frames which are output, in units of 512 bit times.
+ *
+ *  Bear in mind that in almost all circumstances, the mPIPE packet FIFO
+ *  will never fill up, since mPIPE will empty it as fast as or faster than
+ *  the incoming data rate, by either delivering or dropping packets.  The
+ *  only situation in which this is not true is if the memory and cache
+ *  subsystem is extremely heavily loaded, and mPIPE cannot perform DMA of
+ *  packet data to memory in a timely fashion.  In particular, pause frames
+ *  will <em>not</em> be sent if packets cannot be delivered because
+ *  NotifRings are full, buckets are full, or buffers are not available in
+ *  a buffer stack. */
+#define GXIO_MPIPE_LINK_SEND_PAUSE         0x020000
+
+/** Determine whether to suspend output on the receipt of pause frames.
+ *  If the value is nonzero, mPIPE shim will suspend output on the link's
+ *  channel when a pause frame is received.  If the value is zero, pause
+ *  frames will be ignored.  The default value is zero. */
+#define GXIO_MPIPE_LINK_RECEIVE_PAUSE      0x030000
+
+/** Interface MAC address.  The value is a 6-byte MAC address, in the least
+ *  significant 48 bits of the value; in other words, an address which would
+ *  be printed as '12:34:56:78:90:AB' in IEEE 802 canonical format would
+ *  be returned as 0x12345678ab.
+ *
+ *  Depending upon the overall system design, a MAC address may or may not
+ *  be available for each interface.  Note that the interface's MAC address
+ *  does not limit the packets received on its channel, although the
+ *  classifier's rules could be configured to do that.  Similarly, the MAC
+ *  address is not used when transmitting packets, although applications
+ *  could certainly decide to use the assigned address as a source MAC
+ *  address when doing so.  This attribute may only be retrieved with
+ *  gxio_mpipe_link_get_attr(); it may not be modified.
+ */
+#define GXIO_MPIPE_LINK_MAC                0x040000
+
+/** Determine whether to discard egress packets on link down. If this value
+ *  is nonzero, packets sent on this link while the link is down will be
+ *  discarded.  If this value is zero, no packets will be sent on this link
+ *  while it is down.  The default value is one. */
+#define GXIO_MPIPE_LINK_DISCARD_IF_DOWN    0x050000
+
+/** Possible link state.  The value is a combination of link state flags,
+ *  ORed together, that indicate link modes which are actually supported by
+ *  the hardware.  This attribute may only be retrieved with
+ *  gxio_mpipe_link_get_attr(); it may not be modified. */
+#define GXIO_MPIPE_LINK_POSSIBLE_STATE     0x060000
+
+/** Current link state.  The value is a combination of link state flags,
+ *  ORed together, that indicate the current state of the hardware.  If the
+ *  link is down, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will be zero;
+ *  if the link is up, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will
+ *  result in exactly one of the speed values, indicating the current speed.
+ *  This attribute may only be retrieved with gxio_mpipe_link_get_attr(); it
+ *  may not be modified. */
+#define GXIO_MPIPE_LINK_CURRENT_STATE      0x070000
+
+/** Desired link state. The value is a conbination of flags, which specify
+ *  the desired state for the link.  With gxio_mpipe_link_set_attr(), this
+ *  will, in the background, attempt to bring up the link using whichever of
+ *  the requested flags are reasonable, or take down the link if the flags
+ *  are zero.  The actual link up or down operation may happen after this
+ *  call completes.  If the link state changes in the future, the system
+ *  will continue to try to get back to the desired link state; for
+ *  instance, if the link is brought up successfully, and then the network
+ *  cable is disconnected, the link will go down.  However, the desired
+ *  state of the link is still up, so if the cable is reconnected, the link
+ *  will be brought up again.
+ *
+ *  With gxio_mpipe_link_set_attr(), this will indicate the desired state
+ *  for the link, as set with a previous gxio_mpipe_link_set_attr() call,
+ *  or implicitly by a gxio_mpipe_link_open() or link close operation.
+ *  This may not reflect the current state of the link; to get that, use
+ *  ::GXIO_MPIPE_LINK_CURRENT_STATE.
+ */
+#define GXIO_MPIPE_LINK_DESIRED_STATE      0x080000
+
+
+
+/** Link can run, should run, or is running at 10 Mbps. */
+#define GXIO_MPIPE_LINK_10M        0x0000000000000001UL
+
+/** Link can run, should run, or is running at 100 Mbps. */
+#define GXIO_MPIPE_LINK_100M       0x0000000000000002UL
+
+/** Link can run, should run, or is running at 1 Gbps. */
+#define GXIO_MPIPE_LINK_1G         0x0000000000000004UL
+
+/** Link can run, should run, or is running at 10 Gbps. */
+#define GXIO_MPIPE_LINK_10G        0x0000000000000008UL
+
+/** Link can run, should run, or is running at 20 Gbps. */
+#define GXIO_MPIPE_LINK_20G        0x0000000000000010UL
+
+/** Link can run, should run, or is running at 25 Gbps. */
+#define GXIO_MPIPE_LINK_25G        0x0000000000000020UL
+
+/** Link can run, should run, or is running at 50 Gbps. */
+#define GXIO_MPIPE_LINK_50G        0x0000000000000040UL
+
+/** Link should run at the highest speed supported by the link and by
+ *  the device connected to the link.  Only usable as a value for
+ *  the link's desired state; never returned as a value for the current
+ *  or possible states. */
+#define GXIO_MPIPE_LINK_ANYSPEED   0x0000000000000800UL
+
+/** All legal link speeds.  This value is provided for use in extracting
+ *  the speed-related subset of the link state flags; it is not intended
+ *  to be set directly as a value for one of the GXIO_MPIPE_LINK_xxx_STATE
+ *  attributes.  A link is up or is requested to be up if its current or
+ *  desired state, respectively, ANDED with this value, is nonzero. */
+#define GXIO_MPIPE_LINK_SPEED_MASK 0x0000000000000FFFUL
+
+/** Link can run, should run, or is running in MAC loopback mode.  This
+ *  loops transmitted packets back to the receiver, inside the Tile
+ *  Processor. */
+#define GXIO_MPIPE_LINK_LOOP_MAC   0x0000000000001000UL
+
+/** Link can run, should run, or is running in PHY loopback mode.  This
+ *  loops transmitted packets back to the receiver, inside the external
+ *  PHY chip. */
+#define GXIO_MPIPE_LINK_LOOP_PHY   0x0000000000002000UL
+
+/** Link can run, should run, or is running in external loopback mode.
+ *  This requires that an external loopback plug be installed on the
+ *  Ethernet port.  Note that only some links require that this be
+ *  configured via the gxio_mpipe_link routines; other links can do
+ *  external loopack with the plug and no special configuration. */
+#define GXIO_MPIPE_LINK_LOOP_EXT   0x0000000000004000UL
+
+/** All legal loopback types. */
+#define GXIO_MPIPE_LINK_LOOP_MASK  0x000000000000F000UL
+
+/** Link can run, should run, or is running in full-duplex mode.
+ *  If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are
+ *  specified in a set of desired state flags, both are assumed. */
+#define GXIO_MPIPE_LINK_FDX        0x0000000000010000UL
+
+/** Link can run, should run, or is running in half-duplex mode.
+ *  If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are
+ *  specified in a set of desired state flags, both are assumed. */
+#define GXIO_MPIPE_LINK_HDX        0x0000000000020000UL
+
+
+/** An individual rule. */
+typedef struct
+{
+  /** The total size. */
+  uint16_t size;
+
+  /** The priority. */
+  int16_t priority;
+
+  /** The "headroom" in each buffer. */
+  uint8_t headroom;
+
+  /** The "tailroom" in each buffer. */
+  uint8_t tailroom;
+
+  /** The "capacity" of the largest buffer. */
+  uint16_t capacity;
+
+  /** The mask for converting a flow hash into a bucket. */
+  uint16_t bucket_mask;
+
+  /** The offset for converting a flow hash into a bucket. */
+  uint16_t bucket_first;
+
+  /** The buffer stack ids. */
+  gxio_mpipe_rules_stacks_t stacks;
+
+  /** The actual channels. */
+  uint32_t channel_bits;
+
+  /** The number of dmacs. */
+  uint16_t num_dmacs;
+
+  /** The number of vlans. */
+  uint16_t num_vlans;
+
+  /** The actual dmacs and vlans. */
+  uint8_t dmacs_and_vlans[];
+
+} gxio_mpipe_rules_rule_t;
+
+
+/** A list of classifier rules. */
+typedef struct
+{
+  /** The offset to the end of the current rule. */
+  uint16_t tail;
+
+  /** The offset to the start of the current rule. */
+  uint16_t head;
+
+  /** The actual rules. */
+  uint8_t rules[4096 - 4];
+
+} gxio_mpipe_rules_list_t;
+
+
+
+
+/** mPIPE statistics structure. These counters include all relevant
+ *  events occurring on all links within the mPIPE shim. */
+typedef struct
+{
+  /** Number of ingress packets dropped for any reason. */
+  uint64_t ingress_drops;
+  /** Number of ingress packets dropped because a buffer stack was empty. */
+  uint64_t ingress_drops_no_buf;
+  /** Number of ingress packets dropped or truncated due to lack of space in
+   *  the iPkt buffer. */
+  uint64_t ingress_drops_ipkt;
+  /** Number of ingress packets dropped by the classifier or load balancer */
+  uint64_t ingress_drops_cls_lb;
+  /** Total number of ingress packets. */
+  uint64_t ingress_packets;
+  /** Total number of egress packets. */
+  uint64_t egress_packets;
+  /** Total number of ingress bytes. */
+  uint64_t ingress_bytes;
+  /** Total number of egress bytes. */
+  uint64_t egress_bytes;
+}
+gxio_mpipe_stats_t;
+
+
+#endif /* _SYS_HV_DRV_MPIPE_INTF_H */
diff --git a/arch/tile/include/hv/drv_trio_intf.h b/arch/tile/include/hv/drv_trio_intf.h
new file mode 100644
index 00000000000..ef9f3f52ee2
--- /dev/null
+++ b/arch/tile/include/hv/drv_trio_intf.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/**
+ * Interface definitions for the trio driver.
+ */
+
+#ifndef _SYS_HV_DRV_TRIO_INTF_H
+#define _SYS_HV_DRV_TRIO_INTF_H
+
+#include <arch/trio.h>
+
+/** The vendor ID for all Tilera processors. */
+#define TILERA_VENDOR_ID 0x1a41
+
+/** The device ID for the Gx36 processor. */
+#define TILERA_GX36_DEV_ID 0x0200
+
+/** Device ID for our internal bridge when running as RC. */
+#define TILERA_GX36_RC_DEV_ID 0x2000
+
+/** Maximum number of TRIO interfaces. */
+#define TILEGX_NUM_TRIO         2
+
+/** Gx36 has max 3 PCIe MACs per TRIO interface. */
+#define TILEGX_TRIO_PCIES       3
+
+/** Specify port properties for a PCIe MAC. */
+struct pcie_port_property
+{
+  /** If true, the link can be configured in PCIe root complex mode. */
+  uint8_t allow_rc: 1;
+
+  /** If true, the link can be configured in PCIe endpoint mode. */
+  uint8_t allow_ep: 1;
+
+  /** If true, the link can be configured in StreamIO mode. */
+  uint8_t allow_sio: 1;
+
+  /** If true, the link is allowed to support 1-lane operation. Software
+   *  will not consider it an error if the link comes up as a x1 link. */
+  uint8_t allow_x1: 1;
+
+  /** If true, the link is allowed to support 2-lane operation. Software
+   *  will not consider it an error if the link comes up as a x2 link. */
+  uint8_t allow_x2: 1;
+
+  /** If true, the link is allowed to support 4-lane operation. Software
+   *  will not consider it an error if the link comes up as a x4 link. */
+  uint8_t allow_x4: 1;
+
+  /** If true, the link is allowed to support 8-lane operation. Software
+   *  will not consider it an error if the link comes up as a x8 link. */
+  uint8_t allow_x8: 1;
+
+  /** Reserved. */
+  uint8_t reserved: 1;
+
+};
+
+/** Configurations can be issued to configure a char stream interrupt. */
+typedef enum pcie_stream_intr_config_sel_e
+{
+  /** Interrupt configuration for memory map regions. */
+  MEM_MAP_SEL,
+
+  /** Interrupt configuration for push DMAs. */
+  PUSH_DMA_SEL,
+
+  /** Interrupt configuration for pull DMAs. */
+  PULL_DMA_SEL,
+}
+pcie_stream_intr_config_sel_t;
+
+
+/** The mmap file offset (PA) of the TRIO config region. */
+#define HV_TRIO_CONFIG_OFFSET                                        \
+  ((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_CFG <<   \
+    TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT)
+
+/** The maximum size of the TRIO config region. */
+#define HV_TRIO_CONFIG_SIZE                                 \
+  (1ULL << TRIO_CFG_REGION_ADDR__REGION_SHIFT)
+
+/** Size of the config region mapped into client. We can't use
+ *  TRIO_MMIO_ADDRESS_SPACE__OFFSET_WIDTH because it
+ *  will require the kernel to allocate 4GB VA space
+ *  from the VMALLOC region which has a total range
+ *  of 4GB.
+ */
+#define HV_TRIO_CONFIG_IOREMAP_SIZE                            \
+  ((uint64_t) 1 << TRIO_CFG_REGION_ADDR__PROT_SHIFT)
+
+/** The mmap file offset (PA) of a scatter queue region. */
+#define HV_TRIO_SQ_OFFSET(queue)                                        \
+  (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_SQ <<   \
+    TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) |                            \
+   ((queue) << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT))
+
+/** The maximum size of a scatter queue region. */
+#define HV_TRIO_SQ_SIZE                                 \
+  (1ULL << TRIO_MAP_SQ_REGION_ADDR__SQ_SEL_SHIFT)
+
+
+/** The "hardware MMIO region" of the first PIO region. */
+#define HV_TRIO_FIRST_PIO_REGION 8
+
+/** The mmap file offset (PA) of a PIO region. */
+#define HV_TRIO_PIO_OFFSET(region)                           \
+  (((unsigned long long)(region) + HV_TRIO_FIRST_PIO_REGION) \
+   << TRIO_PIO_REGIONS_ADDR__REGION_SHIFT)
+
+/** The maximum size of a PIO region. */
+#define HV_TRIO_PIO_SIZE (1ULL << TRIO_PIO_REGIONS_ADDR__ADDR_WIDTH)
+
+
+/** The mmap file offset (PA) of a push DMA region. */
+#define HV_TRIO_PUSH_DMA_OFFSET(ring)                                   \
+  (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PUSH_DMA << \
+    TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) |                            \
+   ((ring) << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT))
+
+/** The mmap file offset (PA) of a pull DMA region. */
+#define HV_TRIO_PULL_DMA_OFFSET(ring)                                   \
+  (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_PULL_DMA << \
+    TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) |                            \
+   ((ring) << TRIO_PULL_DMA_REGION_ADDR__RING_SEL_SHIFT))
+
+/** The maximum size of a DMA region. */
+#define HV_TRIO_DMA_REGION_SIZE                         \
+  (1ULL << TRIO_PUSH_DMA_REGION_ADDR__RING_SEL_SHIFT)
+
+
+/** The mmap file offset (PA) of a Mem-Map interrupt region. */
+#define HV_TRIO_MEM_MAP_INTR_OFFSET(map)                                 \
+  (((unsigned long long)TRIO_MMIO_ADDRESS_SPACE__REGION_VAL_MAP_MEM <<   \
+    TRIO_MMIO_ADDRESS_SPACE__REGION_SHIFT) |                            \
+   ((map) << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT))
+
+/** The maximum size of a Mem-Map interrupt region. */
+#define HV_TRIO_MEM_MAP_INTR_SIZE                                 \
+  (1ULL << TRIO_MAP_MEM_REGION_ADDR__MAP_SEL_SHIFT)
+
+
+/** A flag bit indicating a fixed resource allocation. */
+#define HV_TRIO_ALLOC_FIXED 0x01
+
+/** TRIO requires that all mappings have 4kB aligned start addresses. */
+#define HV_TRIO_PAGE_SHIFT 12
+
+/** TRIO requires that all mappings have 4kB aligned start addresses. */
+#define HV_TRIO_PAGE_SIZE (1ull << HV_TRIO_PAGE_SHIFT)
+
+
+/* Specify all PCIe port properties for a TRIO. */
+struct pcie_trio_ports_property
+{
+  struct pcie_port_property ports[TILEGX_TRIO_PCIES];
+};
+
+/* Flags indicating traffic class. */
+#define HV_TRIO_FLAG_TC_SHIFT 4
+#define HV_TRIO_FLAG_TC_RMASK 0xf
+#define HV_TRIO_FLAG_TC(N) \
+  ((((N) & HV_TRIO_FLAG_TC_RMASK) + 1) << HV_TRIO_FLAG_TC_SHIFT)
+
+/* Flags indicating virtual functions. */
+#define HV_TRIO_FLAG_VFUNC_SHIFT 8
+#define HV_TRIO_FLAG_VFUNC_RMASK 0xff
+#define HV_TRIO_FLAG_VFUNC(N) \
+  ((((N) & HV_TRIO_FLAG_VFUNC_RMASK) + 1) << HV_TRIO_FLAG_VFUNC_SHIFT)
+
+
+/* Flag indicating an ordered PIO region. */
+#define HV_TRIO_PIO_FLAG_ORDERED (1 << 16)
+
+/* Flags indicating special types of PIO regions. */
+#define HV_TRIO_PIO_FLAG_SPACE_SHIFT 17
+#define HV_TRIO_PIO_FLAG_SPACE_MASK (0x3 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
+#define HV_TRIO_PIO_FLAG_CONFIG_SPACE (0x1 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
+#define HV_TRIO_PIO_FLAG_IO_SPACE (0x2 << HV_TRIO_PIO_FLAG_SPACE_SHIFT)
+
+
+#endif /* _SYS_HV_DRV_TRIO_INTF_H */
diff --git a/arch/tile/include/hv/drv_usb_host_intf.h b/arch/tile/include/hv/drv_usb_host_intf.h
new file mode 100644
index 00000000000..24ce774a3f1
--- /dev/null
+++ b/arch/tile/include/hv/drv_usb_host_intf.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/**
+ * Interface definitions for the USB host driver.
+ */
+
+#ifndef _SYS_HV_DRV_USB_HOST_INTF_H
+#define _SYS_HV_DRV_USB_HOST_INTF_H
+
+#include <arch/usb_host.h>
+
+
+/** Offset for the EHCI register MMIO region. */
+#define HV_USB_HOST_MMIO_OFFSET_EHCI ((uint64_t) USB_HOST_HCCAPBASE_REG)
+
+/** Offset for the OHCI register MMIO region. */
+#define HV_USB_HOST_MMIO_OFFSET_OHCI ((uint64_t) USB_HOST_OHCD_HC_REVISION_REG)
+
+/** Size of the register MMIO region.  This turns out to be the same for
+ *  both EHCI and OHCI. */
+#define HV_USB_HOST_MMIO_SIZE ((uint64_t) 0x1000)
+
+/** The number of service domains supported by the USB host shim. */
+#define HV_USB_HOST_NUM_SVC_DOM 1
+
+
+#endif /* _SYS_HV_DRV_USB_HOST_INTF_H */
diff --git a/arch/tile/include/hv/iorpc.h b/arch/tile/include/hv/iorpc.h
new file mode 100644
index 00000000000..89c72a5d934
--- /dev/null
+++ b/arch/tile/include/hv/iorpc.h
@@ -0,0 +1,714 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+#ifndef _HV_IORPC_H_
+#define _HV_IORPC_H_
+
+/**
+ *
+ * Error codes and struct definitions for the IO RPC library.
+ *
+ * The hypervisor's IO RPC component provides a convenient way for
+ * driver authors to proxy system calls between user space, linux, and
+ * the hypervisor driver.  The core of the system is a set of Python
+ * files that take ".idl" files as input and generates the following
+ * source code:
+ *
+ * - _rpc_call() routines for use in userspace IO libraries.  These
+ * routines take an argument list specified in the .idl file, pack the
+ * arguments in to a buffer, and read or write that buffer via the
+ * Linux iorpc driver.
+ *
+ * - dispatch_read() and dispatch_write() routines that hypervisor
+ * drivers can use to implement most of their dev_pread() and
+ * dev_pwrite() methods.  These routines decode the incoming parameter
+ * blob, permission check and translate parameters where appropriate,
+ * and then invoke a callback routine for whichever RPC call has
+ * arrived.  The driver simply implements the set of callback
+ * routines.
+ *
+ * The IO RPC system also includes the Linux 'iorpc' driver, which
+ * proxies calls between the userspace library and the hypervisor
+ * driver.  The Linux driver is almost entirely device agnostic; it
+ * watches for special flags indicating cases where a memory buffer
+ * address might need to be translated, etc.  As a result, driver
+ * writers can avoid many of the problem cases related to registering
+ * hardware resources like memory pages or interrupts.  However, the
+ * drivers must be careful to obey the conventions documented below in
+ * order to work properly with the generic Linux iorpc driver.
+ *
+ * @section iorpc_domains Service Domains
+ *
+ * All iorpc-based drivers must support a notion of service domains.
+ * A service domain is basically an application context - state
+ * indicating resources that are allocated to that particular app
+ * which it may access and (perhaps) other applications may not
+ * access.  Drivers can support any number of service domains they
+ * choose.  In some cases the design is limited by a number of service
+ * domains supported by the IO hardware; in other cases the service
+ * domains are a purely software concept and the driver chooses a
+ * maximum number of domains based on how much state memory it is
+ * willing to preallocate.
+ *
+ * For example, the mPIPE driver only supports as many service domains
+ * as are supported by the mPIPE hardware.  This limitation is
+ * required because the hardware implements its own MMIO protection
+ * scheme to allow large MMIO mappings while still protecting small
+ * register ranges within the page that should only be accessed by the
+ * hypervisor.
+ *
+ * In contrast, drivers with no hardware service domain limitations
+ * (for instance the TRIO shim) can implement an arbitrary number of
+ * service domains.  In these cases, each service domain is limited to
+ * a carefully restricted set of legal MMIO addresses if necessary to
+ * keep one application from corrupting another application's state.
+ *
+ * @section iorpc_conventions System Call Conventions
+ *
+ * The driver's open routine is responsible for allocating a new
+ * service domain for each hv_dev_open() call.  By convention, the
+ * return value from open() should be the service domain number on
+ * success, or GXIO_ERR_NO_SVC_DOM if no more service domains are
+ * available.
+ *
+ * The implementations of hv_dev_pread() and hv_dev_pwrite() are
+ * responsible for validating the devhdl value passed up by the
+ * client.  Since the device handle returned by hv_dev_open() should
+ * embed the positive service domain number, drivers should make sure
+ * that DRV_HDL2BITS(devhdl) is a legal service domain.  If the client
+ * passes an illegal service domain number, the routine should return
+ * GXIO_ERR_INVAL_SVC_DOM.  Once the service domain number has been
+ * validated, the driver can copy to/from the client buffer and call
+ * the dispatch_read() or dispatch_write() methods created by the RPC
+ * generator.
+ *
+ * The hv_dev_close() implementation should reset all service domain
+ * state and put the service domain back on a free list for
+ * reallocation by a future application.  In most cases, this will
+ * require executing a hardware reset or drain flow and denying any
+ * MMIO regions that were created for the service domain.
+ *
+ * @section iorpc_data Special Data Types
+ *
+ * The .idl file syntax allows the creation of syscalls with special
+ * parameters that require permission checks or translations as part
+ * of the system call path.  Because of limitations in the code
+ * generator, APIs are generally limited to just one of these special
+ * parameters per system call, and they are sometimes required to be
+ * the first or last parameter to the call.  Special parameters
+ * include:
+ *
+ * @subsection iorpc_mem_buffer MEM_BUFFER
+ *
+ * The MEM_BUFFER() datatype allows user space to "register" memory
+ * buffers with a device.  Registering memory accomplishes two tasks:
+ * Linux keeps track of all buffers that might be modified by a
+ * hardware device, and the hardware device drivers bind registered
+ * buffers to particular hardware resources like ingress NotifRings.
+ * The MEM_BUFFER() idl syntax can take extra flags like ALIGN_64KB,
+ * ALIGN_SELF_SIZE, and FLAGS indicating that memory buffers must have
+ * certain alignment or that the user should be able to pass a "memory
+ * flags" word specifying attributes like nt_hint or IO cache pinning.
+ * The parser will accept multiple MEM_BUFFER() flags.
+ *
+ * Implementations must obey the following conventions when
+ * registering memory buffers via the iorpc flow.  These rules are a
+ * result of the Linux driver implementation, which needs to keep
+ * track of how many times a particular page has been registered with
+ * the hardware so that it can release the page when all those
+ * registrations are cleared.
+ *
+ * - Memory registrations that refer to a resource which has already
+ * been bound must return GXIO_ERR_ALREADY_INIT.  Thus, it is an
+ * error to register memory twice without resetting (i.e. closing) the
+ * resource in between.  This convention keeps the Linux driver from
+ * having to track which particular devices a page is bound to.
+ *
+ * - At present, a memory registration is only cleared when the
+ * service domain is reset.  In this case, the Linux driver simply
+ * closes the HV device file handle and then decrements the reference
+ * counts of all pages that were previously registered with the
+ * device.
+ *
+ * - In the future, we may add a mechanism for unregistering memory.
+ * One possible implementation would require that the user specify
+ * which buffer is currently registered.  The HV would then verify
+ * that that page was actually the one currently mapped and return
+ * success or failure to Linux, which would then only decrement the
+ * page reference count if the addresses were mapped.  Another scheme
+ * might allow Linux to pass a token to the HV to be returned when the
+ * resource is unmapped.
+ *
+ * @subsection iorpc_interrupt INTERRUPT
+ *
+ * The INTERRUPT .idl datatype allows the client to bind hardware
+ * interrupts to a particular combination of IPI parameters - CPU, IPI
+ * PL, and event bit number.  This data is passed via a special
+ * datatype so that the Linux driver can validate the CPU and PL and
+ * the HV generic iorpc code can translate client CPUs to real CPUs.
+ *
+ * @subsection iorpc_pollfd_setup POLLFD_SETUP
+ *
+ * The POLLFD_SETUP .idl datatype allows the client to set up hardware
+ * interrupt bindings which are received by Linux but which are made
+ * visible to user processes as state transitions on a file descriptor;
+ * this allows user processes to use Linux primitives, such as poll(), to
+ * await particular hardware events.  This data is passed via a special
+ * datatype so that the Linux driver may recognize the pollable file
+ * descriptor and translate it to a set of interrupt target information,
+ * and so that the HV generic iorpc code can translate client CPUs to real
+ * CPUs.
+ *
+ * @subsection iorpc_pollfd POLLFD
+ *
+ * The POLLFD .idl datatype allows manipulation of hardware interrupt
+ * bindings set up via the POLLFD_SETUP datatype; common operations are
+ * resetting the state of the requested interrupt events, and unbinding any
+ * bound interrupts.  This data is passed via a special datatype so that
+ * the Linux driver may recognize the pollable file descriptor and
+ * translate it to an interrupt identifier previously supplied by the
+ * hypervisor as the result of an earlier pollfd_setup operation.
+ *
+ * @subsection iorpc_blob BLOB
+ *
+ * The BLOB .idl datatype allows the client to write an arbitrary
+ * length string of bytes up to the hypervisor driver.  This can be
+ * useful for passing up large, arbitrarily structured data like
+ * classifier programs.  The iorpc stack takes care of validating the
+ * buffer VA and CPA as the data passes up to the hypervisor.  Unlike
+ * MEM_BUFFER(), the buffer is not registered - Linux does not bump
+ * page refcounts and the HV driver should not reuse the buffer once
+ * the system call is complete.
+ *
+ * @section iorpc_translation Translating User Space Calls
+ *
+ * The ::iorpc_offset structure describes the formatting of the offset
+ * that is passed to pread() or pwrite() as part of the generated RPC code.
+ * When the user calls up to Linux, the rpc code fills in all the fields of
+ * the offset, including a 16-bit opcode, a 16 bit format indicator, and 32
+ * bits of user-specified "sub-offset".  The opcode indicates which syscall
+ * is being requested.  The format indicates whether there is a "prefix
+ * struct" at the start of the memory buffer passed to pwrite(), and if so
+ * what data is in that prefix struct.  These prefix structs are used to
+ * implement special datatypes like MEM_BUFFER() and INTERRUPT - we arrange
+ * to put data that needs translation and permission checks at the start of
+ * the buffer so that the Linux driver and generic portions of the HV iorpc
+ * code can easily access the data.  The 32 bits of user-specified
+ * "sub-offset" are most useful for pread() calls where the user needs to
+ * also pass in a few bits indicating which register to read, etc.
+ *
+ * The Linux iorpc driver watches for system calls that contain prefix
+ * structs so that it can translate parameters and bump reference
+ * counts as appropriate.  It does not (currently) have any knowledge
+ * of the per-device opcodes - it doesn't care what operation you're
+ * doing to mPIPE, so long as it can do all the generic book-keeping.
+ * The hv/iorpc.h header file defines all of the generic encoding bits
+ * needed to translate iorpc calls without knowing which particular
+ * opcode is being issued.
+ *
+ * @section iorpc_globals Global iorpc Calls
+ *
+ * Implementing mmap() required adding some special iorpc syscalls
+ * that are only called by the Linux driver, never by userspace.
+ * These include get_mmio_base() and check_mmio_offset().  These
+ * routines are described in globals.idl and must be included in every
+ * iorpc driver.  By providing these routines in every driver, Linux's
+ * mmap implementation can easily get the PTE bits it needs and
+ * validate the PA offset without needing to know the per-device
+ * opcodes to perform those tasks.
+ *
+ * @section iorpc_kernel Supporting gxio APIs in the Kernel
+ *
+ * The iorpc code generator also supports generation of kernel code
+ * implementing the gxio APIs.  This capability is currently used by
+ * the mPIPE network driver, and will likely be used by the TRIO root
+ * complex and endpoint drivers and perhaps an in-kernel crypto
+ * driver.  Each driver that wants to instantiate iorpc calls in the
+ * kernel needs to generate a kernel version of the generate rpc code
+ * and (probably) copy any related gxio source files into the kernel.
+ * The mPIPE driver provides a good example of this pattern.
+ */
+
+#ifdef __KERNEL__
+#include <linux/stddef.h>
+#else
+#include <stddef.h>
+#endif
+
+#if defined(__HV__)
+#include <hv/hypervisor.h>
+#elif defined(__KERNEL__)
+#include "hypervisor.h"
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
+
+/** Code indicating translation services required within the RPC path.
+ * These indicate whether there is a translatable struct at the start
+ * of the RPC buffer and what information that struct contains.
+ */
+enum iorpc_format_e
+{
+  /** No translation required, no prefix struct. */
+  IORPC_FORMAT_NONE,
+
+  /** No translation required, no prefix struct, no access to this
+   *  operation from user space. */
+  IORPC_FORMAT_NONE_NOUSER,
+
+  /** Prefix struct contains user VA and size. */
+  IORPC_FORMAT_USER_MEM,
+
+  /** Prefix struct contains CPA, size, and homing bits. */
+  IORPC_FORMAT_KERNEL_MEM,
+
+  /** Prefix struct contains interrupt. */
+  IORPC_FORMAT_KERNEL_INTERRUPT,
+
+  /** Prefix struct contains user-level interrupt. */
+  IORPC_FORMAT_USER_INTERRUPT,
+
+  /** Prefix struct contains pollfd_setup (interrupt information). */
+  IORPC_FORMAT_KERNEL_POLLFD_SETUP,
+
+  /** Prefix struct contains user-level pollfd_setup (file descriptor). */
+  IORPC_FORMAT_USER_POLLFD_SETUP,
+
+  /** Prefix struct contains pollfd (interrupt cookie). */
+  IORPC_FORMAT_KERNEL_POLLFD,
+
+  /** Prefix struct contains user-level pollfd (file descriptor). */
+  IORPC_FORMAT_USER_POLLFD,
+};
+
+
+/** Generate an opcode given format and code. */
+#define IORPC_OPCODE(FORMAT, CODE) (((FORMAT) << 16) | (CODE))
+
+/** The offset passed through the read() and write() system calls
+    combines an opcode with 32 bits of user-specified offset. */
+union iorpc_offset
+{
+#ifndef __BIG_ENDIAN__
+  uint64_t offset;              /**< All bits. */
+
+  struct
+  {
+    uint16_t code;              /**< RPC code. */
+    uint16_t format;            /**< iorpc_format_e */
+    uint32_t sub_offset;        /**< caller-specified offset. */
+  };
+
+  uint32_t opcode;              /**< Opcode combines code & format. */
+#else
+  uint64_t offset;              /**< All bits. */
+
+  struct
+  {
+    uint32_t sub_offset;        /**< caller-specified offset. */
+    uint16_t format;            /**< iorpc_format_e */
+    uint16_t code;              /**< RPC code. */
+  };
+
+  struct
+  {
+    uint32_t padding;
+    uint32_t opcode;              /**< Opcode combines code & format. */
+  };
+#endif
+};
+
+
+/** Homing and cache hinting bits that can be used by IO devices. */
+struct iorpc_mem_attr
+{
+  unsigned int lotar_x:4;       /**< lotar X bits (or Gx page_mask). */
+  unsigned int lotar_y:4;       /**< lotar Y bits (or Gx page_offset). */
+  unsigned int hfh:1;           /**< Uses hash-for-home. */
+  unsigned int nt_hint:1;       /**< Non-temporal hint. */
+  unsigned int io_pin:1;        /**< Only fill 'IO' cache ways. */
+};
+
+/** Set the nt_hint bit. */
+#define IORPC_MEM_BUFFER_FLAG_NT_HINT (1 << 0)
+
+/** Set the IO pin bit. */
+#define IORPC_MEM_BUFFER_FLAG_IO_PIN (1 << 1)
+
+
+/** A structure used to describe memory registration.  Different
+    protection levels describe memory differently, so this union
+    contains all the different possible descriptions.  As a request
+    moves up the call chain, each layer translates from one
+    description format to the next.  In particular, the Linux iorpc
+    driver translates user VAs into CPAs and homing parameters. */
+union iorpc_mem_buffer
+{
+  struct
+  {
+    uint64_t va;                /**< User virtual address. */
+    uint64_t size;              /**< Buffer size. */
+    unsigned int flags;         /**< nt_hint, IO pin. */
+  }
+  user;                         /**< Buffer as described by user apps. */
+
+  struct
+  {
+    unsigned long long cpa;     /**< Client physical address. */
+#if defined(__KERNEL__) || defined(__HV__)
+    size_t size;                /**< Buffer size. */
+    HV_PTE pte;                 /**< PTE describing memory homing. */
+#else
+    uint64_t size;
+    uint64_t pte;
+#endif
+    unsigned int flags;         /**< nt_hint, IO pin. */
+  }
+  kernel;                       /**< Buffer as described by kernel. */
+
+  struct
+  {
+    unsigned long long pa;      /**< Physical address. */
+    size_t size;                /**< Buffer size. */
+    struct iorpc_mem_attr attr;      /**< Homing and locality hint bits. */
+  }
+  hv;                           /**< Buffer parameters for HV driver. */
+};
+
+
+/** A structure used to describe interrupts.  The format differs slightly
+ *  for user and kernel interrupts.  As with the mem_buffer_t, translation
+ *  between the formats is done at each level. */
+union iorpc_interrupt
+{
+  struct
+  {
+    int cpu;   /**< CPU. */
+    int event; /**< evt_num */
+  }
+  user;        /**< Interrupt as described by user applications. */
+
+  struct
+  {
+    int x;     /**< X coord. */
+    int y;     /**< Y coord. */
+    int ipi;   /**< int_num */
+    int event; /**< evt_num */
+  }
+  kernel;      /**< Interrupt as described by the kernel. */
+
+};
+
+
+/** A structure used to describe interrupts used with poll().  The format
+ *  differs significantly for requests from user to kernel, and kernel to
+ *  hypervisor.  As with the mem_buffer_t, translation between the formats
+ *  is done at each level. */
+union iorpc_pollfd_setup
+{
+  struct
+  {
+    int fd;    /**< Pollable file descriptor. */
+  }
+  user;        /**< pollfd_setup as described by user applications. */
+
+  struct
+  {
+    int x;     /**< X coord. */
+    int y;     /**< Y coord. */
+    int ipi;   /**< int_num */
+    int event; /**< evt_num */
+  }
+  kernel;      /**< pollfd_setup as described by the kernel. */
+
+};
+
+
+/** A structure used to describe previously set up interrupts used with
+ *  poll().  The format differs significantly for requests from user to
+ *  kernel, and kernel to hypervisor.  As with the mem_buffer_t, translation
+ *  between the formats is done at each level. */
+union iorpc_pollfd
+{
+  struct
+  {
+    int fd;    /**< Pollable file descriptor. */
+  }
+  user;        /**< pollfd as described by user applications. */
+
+  struct
+  {
+    int cookie; /**< hv cookie returned by the pollfd_setup operation. */
+  }
+  kernel;      /**< pollfd as described by the kernel. */
+
+};
+
+
+/** The various iorpc devices use error codes from -1100 to -1299.
+ *
+ * This range is distinct from netio (-700 to -799), the hypervisor
+ * (-800 to -899), tilepci (-900 to -999), ilib (-1000 to -1099),
+ * gxcr (-1300 to -1399) and gxpci (-1400 to -1499).
+ */
+enum gxio_err_e {
+
+  /** Largest iorpc error number. */
+  GXIO_ERR_MAX = -1101,
+
+
+  /********************************************************/
+  /*                   Generic Error Codes                */
+  /********************************************************/
+
+  /** Bad RPC opcode - possible version incompatibility. */
+  GXIO_ERR_OPCODE = -1101,
+
+  /** Invalid parameter. */
+  GXIO_ERR_INVAL = -1102,
+
+  /** Memory buffer did not meet alignment requirements. */
+  GXIO_ERR_ALIGNMENT = -1103,
+
+  /** Memory buffers must be coherent and cacheable. */
+  GXIO_ERR_COHERENCE = -1104,
+
+  /** Resource already initialized. */
+  GXIO_ERR_ALREADY_INIT = -1105,
+
+  /** No service domains available. */
+  GXIO_ERR_NO_SVC_DOM = -1106,
+
+  /** Illegal service domain number. */
+  GXIO_ERR_INVAL_SVC_DOM = -1107,
+
+  /** Illegal MMIO address. */
+  GXIO_ERR_MMIO_ADDRESS = -1108,
+
+  /** Illegal interrupt binding. */
+  GXIO_ERR_INTERRUPT = -1109,
+
+  /** Unreasonable client memory. */
+  GXIO_ERR_CLIENT_MEMORY = -1110,
+
+  /** No more IOTLB entries. */
+  GXIO_ERR_IOTLB_ENTRY = -1111,
+
+  /** Invalid memory size. */
+  GXIO_ERR_INVAL_MEMORY_SIZE = -1112,
+
+  /** Unsupported operation. */
+  GXIO_ERR_UNSUPPORTED_OP = -1113,
+
+  /** Insufficient DMA credits. */
+  GXIO_ERR_DMA_CREDITS = -1114,
+
+  /** Operation timed out. */
+  GXIO_ERR_TIMEOUT = -1115,
+
+  /** No such device or object. */
+  GXIO_ERR_NO_DEVICE = -1116,
+
+  /** Device or resource busy. */
+  GXIO_ERR_BUSY = -1117,
+
+  /** I/O error. */
+  GXIO_ERR_IO = -1118,
+
+  /** Permissions error. */
+  GXIO_ERR_PERM = -1119,
+
+
+
+  /********************************************************/
+  /*                 Test Device Error Codes              */
+  /********************************************************/
+
+  /** Illegal register number. */
+  GXIO_TEST_ERR_REG_NUMBER = -1120,
+
+  /** Illegal buffer slot. */
+  GXIO_TEST_ERR_BUFFER_SLOT = -1121,
+
+
+  /********************************************************/
+  /*                    MPIPE Error Codes                 */
+  /********************************************************/
+
+
+  /** Invalid buffer size. */
+  GXIO_MPIPE_ERR_INVAL_BUFFER_SIZE = -1131,
+
+  /** Cannot allocate buffer stack. */
+  GXIO_MPIPE_ERR_NO_BUFFER_STACK = -1140,
+
+  /** Invalid buffer stack number. */
+  GXIO_MPIPE_ERR_BAD_BUFFER_STACK = -1141,
+
+  /** Cannot allocate NotifRing. */
+  GXIO_MPIPE_ERR_NO_NOTIF_RING = -1142,
+
+  /** Invalid NotifRing number. */
+  GXIO_MPIPE_ERR_BAD_NOTIF_RING = -1143,
+
+  /** Cannot allocate NotifGroup. */
+  GXIO_MPIPE_ERR_NO_NOTIF_GROUP = -1144,
+
+  /** Invalid NotifGroup number. */
+  GXIO_MPIPE_ERR_BAD_NOTIF_GROUP = -1145,
+
+  /** Cannot allocate bucket. */
+  GXIO_MPIPE_ERR_NO_BUCKET = -1146,
+
+  /** Invalid bucket number. */
+  GXIO_MPIPE_ERR_BAD_BUCKET = -1147,
+
+  /** Cannot allocate eDMA ring. */
+  GXIO_MPIPE_ERR_NO_EDMA_RING = -1148,
+
+  /** Invalid eDMA ring number. */
+  GXIO_MPIPE_ERR_BAD_EDMA_RING = -1149,
+
+  /** Invalid channel number. */
+  GXIO_MPIPE_ERR_BAD_CHANNEL = -1150,
+
+  /** Bad configuration. */
+  GXIO_MPIPE_ERR_BAD_CONFIG = -1151,
+
+  /** Empty iqueue. */
+  GXIO_MPIPE_ERR_IQUEUE_EMPTY = -1152,
+
+  /** Empty rules. */
+  GXIO_MPIPE_ERR_RULES_EMPTY = -1160,
+
+  /** Full rules. */
+  GXIO_MPIPE_ERR_RULES_FULL = -1161,
+
+  /** Corrupt rules. */
+  GXIO_MPIPE_ERR_RULES_CORRUPT = -1162,
+
+  /** Invalid rules. */
+  GXIO_MPIPE_ERR_RULES_INVALID = -1163,
+
+  /** Classifier is too big. */
+  GXIO_MPIPE_ERR_CLASSIFIER_TOO_BIG = -1170,
+
+  /** Classifier is too complex. */
+  GXIO_MPIPE_ERR_CLASSIFIER_TOO_COMPLEX = -1171,
+
+  /** Classifier has bad header. */
+  GXIO_MPIPE_ERR_CLASSIFIER_BAD_HEADER = -1172,
+
+  /** Classifier has bad contents. */
+  GXIO_MPIPE_ERR_CLASSIFIER_BAD_CONTENTS = -1173,
+
+  /** Classifier encountered invalid symbol. */
+  GXIO_MPIPE_ERR_CLASSIFIER_INVAL_SYMBOL = -1174,
+
+  /** Classifier encountered invalid bounds. */
+  GXIO_MPIPE_ERR_CLASSIFIER_INVAL_BOUNDS = -1175,
+
+  /** Classifier encountered invalid relocation. */
+  GXIO_MPIPE_ERR_CLASSIFIER_INVAL_RELOCATION = -1176,
+
+  /** Classifier encountered undefined symbol. */
+  GXIO_MPIPE_ERR_CLASSIFIER_UNDEF_SYMBOL = -1177,
+
+
+  /********************************************************/
+  /*                    TRIO  Error Codes                 */
+  /********************************************************/
+
+  /** Cannot allocate memory map region. */
+  GXIO_TRIO_ERR_NO_MEMORY_MAP = -1180,
+
+  /** Invalid memory map region number. */
+  GXIO_TRIO_ERR_BAD_MEMORY_MAP = -1181,
+
+  /** Cannot allocate scatter queue. */
+  GXIO_TRIO_ERR_NO_SCATTER_QUEUE = -1182,
+
+  /** Invalid scatter queue number. */
+  GXIO_TRIO_ERR_BAD_SCATTER_QUEUE = -1183,
+
+  /** Cannot allocate push DMA ring. */
+  GXIO_TRIO_ERR_NO_PUSH_DMA_RING = -1184,
+
+  /** Invalid push DMA ring index. */
+  GXIO_TRIO_ERR_BAD_PUSH_DMA_RING = -1185,
+
+  /** Cannot allocate pull DMA ring. */
+  GXIO_TRIO_ERR_NO_PULL_DMA_RING = -1186,
+
+  /** Invalid pull DMA ring index. */
+  GXIO_TRIO_ERR_BAD_PULL_DMA_RING = -1187,
+
+  /** Cannot allocate PIO region. */
+  GXIO_TRIO_ERR_NO_PIO = -1188,
+
+  /** Invalid PIO region index. */
+  GXIO_TRIO_ERR_BAD_PIO = -1189,
+
+  /** Cannot allocate ASID. */
+  GXIO_TRIO_ERR_NO_ASID = -1190,
+
+  /** Invalid ASID. */
+  GXIO_TRIO_ERR_BAD_ASID = -1191,
+
+
+  /********************************************************/
+  /*                    MICA Error Codes                  */
+  /********************************************************/
+
+  /** No such accelerator type. */
+  GXIO_MICA_ERR_BAD_ACCEL_TYPE = -1220,
+
+  /** Cannot allocate context. */
+  GXIO_MICA_ERR_NO_CONTEXT = -1221,
+
+  /** PKA command queue is full, can't add another command. */
+  GXIO_MICA_ERR_PKA_CMD_QUEUE_FULL = -1222,
+
+  /** PKA result queue is empty, can't get a result from the queue. */
+  GXIO_MICA_ERR_PKA_RESULT_QUEUE_EMPTY = -1223,
+
+  /********************************************************/
+  /*                    GPIO Error Codes                  */
+  /********************************************************/
+
+  /** Pin not available.  Either the physical pin does not exist, or
+   *  it is reserved by the hypervisor for system usage. */
+  GXIO_GPIO_ERR_PIN_UNAVAILABLE = -1240,
+
+  /** Pin busy.  The pin exists, and is available for use via GXIO, but
+   *  it has been attached by some other process or driver. */
+  GXIO_GPIO_ERR_PIN_BUSY = -1241,
+
+  /** Cannot access unattached pin.  One or more of the pins being
+   *  manipulated by this call are not attached to the requesting
+   *  context. */
+  GXIO_GPIO_ERR_PIN_UNATTACHED = -1242,
+
+  /** Invalid I/O mode for pin.  The wiring of the pin in the system
+   *  is such that the I/O mode or electrical control parameters
+   *  requested could cause damage. */
+  GXIO_GPIO_ERR_PIN_INVALID_MODE = -1243,
+
+  /** Smallest iorpc error number. */
+  GXIO_ERR_MIN = -1299
+};
+
+
+#endif /* !_HV_IORPC_H_ */
diff --git a/arch/tile/kernel/Makefile b/arch/tile/kernel/Makefile
index 5de99248d8d..5334be8e253 100644
--- a/arch/tile/kernel/Makefile
+++ b/arch/tile/kernel/Makefile
@@ -14,4 +14,9 @@ obj-$(CONFIG_SMP)		+= smpboot.o smp.o tlb.o
 obj-$(CONFIG_MODULES)           += module.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
 obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel_$(BITS).o
+ifdef CONFIG_TILEGX
+obj-$(CONFIG_PCI)               += pci_gx.o
+else
 obj-$(CONFIG_PCI)               += pci.o
+endif
+obj-$(CONFIG_TILE_USB)          += usb.o
diff --git a/arch/tile/kernel/pci-dma.c b/arch/tile/kernel/pci-dma.c
index b3ed19f8779..b9fe80ec108 100644
--- a/arch/tile/kernel/pci-dma.c
+++ b/arch/tile/kernel/pci-dma.c
@@ -14,6 +14,7 @@
 
 #include <linux/mm.h>
 #include <linux/dma-mapping.h>
+#include <linux/swiotlb.h>
 #include <linux/vmalloc.h>
 #include <linux/export.h>
 #include <asm/tlbflush.h>
@@ -22,13 +23,18 @@
 /* Generic DMA mapping functions: */
 
 /*
- * Allocate what Linux calls "coherent" memory, which for us just
- * means uncached.
+ * Allocate what Linux calls "coherent" memory.  On TILEPro this is
+ * uncached memory; on TILE-Gx it is hash-for-home memory.
  */
-void *dma_alloc_coherent(struct device *dev,
-                         size_t size,
-                         dma_addr_t *dma_handle,
-                         gfp_t gfp)
+#ifdef __tilepro__
+#define PAGE_HOME_DMA PAGE_HOME_UNCACHED
+#else
+#define PAGE_HOME_DMA PAGE_HOME_HASH
+#endif
+
+static void *tile_dma_alloc_coherent(struct device *dev, size_t size,
+                                     dma_addr_t *dma_handle, gfp_t gfp,
+                                     struct dma_attrs *attrs)
 {
         u64 dma_mask = dev->coherent_dma_mask ?: DMA_BIT_MASK(32);
         int node = dev_to_node(dev);
@@ -39,39 +45,42 @@ void *dma_alloc_coherent(struct device *dev,
         gfp |= __GFP_ZERO;
 
         /*
-         * By forcing NUMA node 0 for 32-bit masks we ensure that the
-         * high 32 bits of the resulting PA will be zero.  If the mask
-         * size is, e.g., 24, we may still not be able to guarantee a
-         * suitable memory address, in which case we will return NULL.
-         * But such devices are uncommon.
+         * If the mask specifies that the memory be in the first 4 GB, then
+         * we force the allocation to come from the DMA zone.  We also
+         * force the node to 0 since that's the only node where the DMA
+         * zone isn't empty.  If the mask size is smaller than 32 bits, we
+         * may still not be able to guarantee a suitable memory address, in
+         * which case we will return NULL.  But such devices are uncommon.
          */
-        if (dma_mask <= DMA_BIT_MASK(32))
+        if (dma_mask <= DMA_BIT_MASK(32)) {
+                gfp |= GFP_DMA;
                 node = 0;
+        }
 
-        pg = homecache_alloc_pages_node(node, gfp, order, PAGE_HOME_UNCACHED);
+        pg = homecache_alloc_pages_node(node, gfp, order, PAGE_HOME_DMA);
         if (pg == NULL)
                 return NULL;
 
         addr = page_to_phys(pg);
         if (addr + size > dma_mask) {
-                homecache_free_pages(addr, order);
+                __homecache_free_pages(pg, order);
                 return NULL;
         }
 
         *dma_handle = addr;
+
         return page_address(pg);
 }
-EXPORT_SYMBOL(dma_alloc_coherent);
 
 /*
- * Free memory that was allocated with dma_alloc_coherent.
+ * Free memory that was allocated with tile_dma_alloc_coherent.
  */
-void dma_free_coherent(struct device *dev, size_t size,
-                  void *vaddr, dma_addr_t dma_handle)
+static void tile_dma_free_coherent(struct device *dev, size_t size,
+                                   void *vaddr, dma_addr_t dma_handle,
+                                   struct dma_attrs *attrs)
 {
         homecache_free_pages((unsigned long)vaddr, get_order(size));
 }
-EXPORT_SYMBOL(dma_free_coherent);
 
 /*
  * The map routines "map" the specified address range for DMA
@@ -87,52 +96,285 @@ EXPORT_SYMBOL(dma_free_coherent);
  * can count on nothing having been touched.
  */
 
-/* Flush a PA range from cache page by page. */
-static void __dma_map_pa_range(dma_addr_t dma_addr, size_t size)
+/* Set up a single page for DMA access. */
+static void __dma_prep_page(struct page *page, unsigned long offset,
+                            size_t size, enum dma_data_direction direction)
+{
+        /*
+         * Flush the page from cache if necessary.
+         * On tilegx, data is delivered to hash-for-home L3; on tilepro,
+         * data is delivered direct to memory.
+         *
+         * NOTE: If we were just doing DMA_TO_DEVICE we could optimize
+         * this to be a "flush" not a "finv" and keep some of the
+         * state in cache across the DMA operation, but it doesn't seem
+         * worth creating the necessary flush_buffer_xxx() infrastructure.
+         */
+        int home = page_home(page);
+        switch (home) {
+        case PAGE_HOME_HASH:
+#ifdef __tilegx__
+                return;
+#endif
+                break;
+        case PAGE_HOME_UNCACHED:
+#ifdef __tilepro__
+                return;
+#endif
+                break;
+        case PAGE_HOME_IMMUTABLE:
+                /* Should be going to the device only. */
+                BUG_ON(direction == DMA_FROM_DEVICE ||
+                       direction == DMA_BIDIRECTIONAL);
+                return;
+        case PAGE_HOME_INCOHERENT:
+                /* Incoherent anyway, so no need to work hard here. */
+                return;
+        default:
+                BUG_ON(home < 0 || home >= NR_CPUS);
+                break;
+        }
+        homecache_finv_page(page);
+
+#ifdef DEBUG_ALIGNMENT
+        /* Warn if the region isn't cacheline aligned. */
+        if (offset & (L2_CACHE_BYTES - 1) || (size & (L2_CACHE_BYTES - 1)))
+                pr_warn("Unaligned DMA to non-hfh memory: PA %#llx/%#lx\n",
+                        PFN_PHYS(page_to_pfn(page)) + offset, size);
+#endif
+}
+
+/* Make the page ready to be read by the core. */
+static void __dma_complete_page(struct page *page, unsigned long offset,
+                                size_t size, enum dma_data_direction direction)
+{
+#ifdef __tilegx__
+        switch (page_home(page)) {
+        case PAGE_HOME_HASH:
+                /* I/O device delivered data the way the cpu wanted it. */
+                break;
+        case PAGE_HOME_INCOHERENT:
+                /* Incoherent anyway, so no need to work hard here. */
+                break;
+        case PAGE_HOME_IMMUTABLE:
+                /* Extra read-only copies are not a problem. */
+                break;
+        default:
+                /* Flush the bogus hash-for-home I/O entries to memory. */
+                homecache_finv_map_page(page, PAGE_HOME_HASH);
+                break;
+        }
+#endif
+}
+
+static void __dma_prep_pa_range(dma_addr_t dma_addr, size_t size,
+                                enum dma_data_direction direction)
 {
         struct page *page = pfn_to_page(PFN_DOWN(dma_addr));
-        size_t bytesleft = PAGE_SIZE - (dma_addr & (PAGE_SIZE - 1));
+        unsigned long offset = dma_addr & (PAGE_SIZE - 1);
+        size_t bytes = min(size, (size_t)(PAGE_SIZE - offset));
+
+        while (size != 0) {
+                __dma_prep_page(page, offset, bytes, direction);
+                size -= bytes;
+                ++page;
+                offset = 0;
+                bytes = min((size_t)PAGE_SIZE, size);
+        }
+}
 
-        while ((ssize_t)size > 0) {
-                /* Flush the page. */
-                homecache_flush_cache(page++, 0);
+static void __dma_complete_pa_range(dma_addr_t dma_addr, size_t size,
+                                    enum dma_data_direction direction)
+{
+        struct page *page = pfn_to_page(PFN_DOWN(dma_addr));
+        unsigned long offset = dma_addr & (PAGE_SIZE - 1);
+        size_t bytes = min(size, (size_t)(PAGE_SIZE - offset));
+
+        while (size != 0) {
+                __dma_complete_page(page, offset, bytes, direction);
+                size -= bytes;
+                ++page;
+                offset = 0;
+                bytes = min((size_t)PAGE_SIZE, size);
+        }
+}
+
+static int tile_dma_map_sg(struct device *dev, struct scatterlist *sglist,
+                           int nents, enum dma_data_direction direction,
+                           struct dma_attrs *attrs)
+{
+        struct scatterlist *sg;
+        int i;
+
+        BUG_ON(!valid_dma_direction(direction));
+
+        WARN_ON(nents == 0 || sglist->length == 0);
 
-                /* Figure out if we need to continue on the next page. */
-                size -= bytesleft;
-                bytesleft = PAGE_SIZE;
+        for_each_sg(sglist, sg, nents, i) {
+                sg->dma_address = sg_phys(sg);
+                __dma_prep_pa_range(sg->dma_address, sg->length, direction);
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+                sg->dma_length = sg->length;
+#endif
         }
+
+        return nents;
 }
 
-/*
- * dma_map_single can be passed any memory address, and there appear
- * to be no alignment constraints.
- *
- * There is a chance that the start of the buffer will share a cache
- * line with some other data that has been touched in the meantime.
- */
-dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-               enum dma_data_direction direction)
+static void tile_dma_unmap_sg(struct device *dev, struct scatterlist *sglist,
+                              int nents, enum dma_data_direction direction,
+                              struct dma_attrs *attrs)
+{
+        struct scatterlist *sg;
+        int i;
+
+        BUG_ON(!valid_dma_direction(direction));
+        for_each_sg(sglist, sg, nents, i) {
+                sg->dma_address = sg_phys(sg);
+                __dma_complete_pa_range(sg->dma_address, sg->length,
+                                        direction);
+        }
+}
+
+static dma_addr_t tile_dma_map_page(struct device *dev, struct page *page,
+                                    unsigned long offset, size_t size,
+                                    enum dma_data_direction direction,
+                                    struct dma_attrs *attrs)
 {
-        dma_addr_t dma_addr = __pa(ptr);
+        BUG_ON(!valid_dma_direction(direction));
+
+        BUG_ON(offset + size > PAGE_SIZE);
+        __dma_prep_page(page, offset, size, direction);
 
+        return page_to_pa(page) + offset;
+}
+
+static void tile_dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+                                size_t size, enum dma_data_direction direction,
+                                struct dma_attrs *attrs)
+{
         BUG_ON(!valid_dma_direction(direction));
-        WARN_ON(size == 0);
 
-        __dma_map_pa_range(dma_addr, size);
+        __dma_complete_page(pfn_to_page(PFN_DOWN(dma_address)),
+                            dma_address & PAGE_OFFSET, size, direction);
+}
 
-        return dma_addr;
+static void tile_dma_sync_single_for_cpu(struct device *dev,
+                                         dma_addr_t dma_handle,
+                                         size_t size,
+                                         enum dma_data_direction direction)
+{
+        BUG_ON(!valid_dma_direction(direction));
+
+        __dma_complete_pa_range(dma_handle, size, direction);
+}
+
+static void tile_dma_sync_single_for_device(struct device *dev,
+                                            dma_addr_t dma_handle, size_t size,
+                                            enum dma_data_direction direction)
+{
+        __dma_prep_pa_range(dma_handle, size, direction);
 }
-EXPORT_SYMBOL(dma_map_single);
 
-void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-                 enum dma_data_direction direction)
+static void tile_dma_sync_sg_for_cpu(struct device *dev,
+                                     struct scatterlist *sglist, int nelems,
+                                     enum dma_data_direction direction)
 {
+        struct scatterlist *sg;
+        int i;
+
+        BUG_ON(!valid_dma_direction(direction));
+        WARN_ON(nelems == 0 || sglist->length == 0);
+
+        for_each_sg(sglist, sg, nelems, i) {
+                dma_sync_single_for_cpu(dev, sg->dma_address,
+                                        sg_dma_len(sg), direction);
+        }
+}
+
+static void tile_dma_sync_sg_for_device(struct device *dev,
+                                        struct scatterlist *sglist, int nelems,
+                                        enum dma_data_direction direction)
+{
+        struct scatterlist *sg;
+        int i;
+
         BUG_ON(!valid_dma_direction(direction));
+        WARN_ON(nelems == 0 || sglist->length == 0);
+
+        for_each_sg(sglist, sg, nelems, i) {
+                dma_sync_single_for_device(dev, sg->dma_address,
+                                           sg_dma_len(sg), direction);
+        }
+}
+
+static inline int
+tile_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
+{
+        return 0;
+}
+
+static inline int
+tile_dma_supported(struct device *dev, u64 mask)
+{
+        return 1;
+}
+
+static struct dma_map_ops tile_default_dma_map_ops = {
+        .alloc = tile_dma_alloc_coherent,
+        .free = tile_dma_free_coherent,
+        .map_page = tile_dma_map_page,
+        .unmap_page = tile_dma_unmap_page,
+        .map_sg = tile_dma_map_sg,
+        .unmap_sg = tile_dma_unmap_sg,
+        .sync_single_for_cpu = tile_dma_sync_single_for_cpu,
+        .sync_single_for_device = tile_dma_sync_single_for_device,
+        .sync_sg_for_cpu = tile_dma_sync_sg_for_cpu,
+        .sync_sg_for_device = tile_dma_sync_sg_for_device,
+        .mapping_error = tile_dma_mapping_error,
+        .dma_supported = tile_dma_supported
+};
+
+struct dma_map_ops *tile_dma_map_ops = &tile_default_dma_map_ops;
+EXPORT_SYMBOL(tile_dma_map_ops);
+
+/* Generic PCI DMA mapping functions */
+
+static void *tile_pci_dma_alloc_coherent(struct device *dev, size_t size,
+                                         dma_addr_t *dma_handle, gfp_t gfp,
+                                         struct dma_attrs *attrs)
+{
+        int node = dev_to_node(dev);
+        int order = get_order(size);
+        struct page *pg;
+        dma_addr_t addr;
+
+        gfp |= __GFP_ZERO;
+
+        pg = homecache_alloc_pages_node(node, gfp, order, PAGE_HOME_DMA);
+        if (pg == NULL)
+                return NULL;
+
+        addr = page_to_phys(pg);
+
+        *dma_handle = phys_to_dma(dev, addr);
+
+        return page_address(pg);
+}
+
+/*
+ * Free memory that was allocated with tile_pci_dma_alloc_coherent.
+ */
+static void tile_pci_dma_free_coherent(struct device *dev, size_t size,
+                                       void *vaddr, dma_addr_t dma_handle,
+                                       struct dma_attrs *attrs)
+{
+        homecache_free_pages((unsigned long)vaddr, get_order(size));
 }
-EXPORT_SYMBOL(dma_unmap_single);
 
-int dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
-           enum dma_data_direction direction)
+static int tile_pci_dma_map_sg(struct device *dev, struct scatterlist *sglist,
+                               int nents, enum dma_data_direction direction,
+                               struct dma_attrs *attrs)
 {
         struct scatterlist *sg;
         int i;
@@ -143,73 +385,103 @@ int dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
 
         for_each_sg(sglist, sg, nents, i) {
                 sg->dma_address = sg_phys(sg);
-                __dma_map_pa_range(sg->dma_address, sg->length);
+                __dma_prep_pa_range(sg->dma_address, sg->length, direction);
+
+                sg->dma_address = phys_to_dma(dev, sg->dma_address);
+#ifdef CONFIG_NEED_SG_DMA_LENGTH
+                sg->dma_length = sg->length;
+#endif
         }
 
         return nents;
 }
-EXPORT_SYMBOL(dma_map_sg);
 
-void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
-             enum dma_data_direction direction)
+static void tile_pci_dma_unmap_sg(struct device *dev,
+                                  struct scatterlist *sglist, int nents,
+                                  enum dma_data_direction direction,
+                                  struct dma_attrs *attrs)
 {
+        struct scatterlist *sg;
+        int i;
+
         BUG_ON(!valid_dma_direction(direction));
+        for_each_sg(sglist, sg, nents, i) {
+                sg->dma_address = sg_phys(sg);
+                __dma_complete_pa_range(sg->dma_address, sg->length,
+                                        direction);
+        }
 }
-EXPORT_SYMBOL(dma_unmap_sg);
 
-dma_addr_t dma_map_page(struct device *dev, struct page *page,
-                        unsigned long offset, size_t size,
-                        enum dma_data_direction direction)
+static dma_addr_t tile_pci_dma_map_page(struct device *dev, struct page *page,
+                                        unsigned long offset, size_t size,
+                                        enum dma_data_direction direction,
+                                        struct dma_attrs *attrs)
 {
         BUG_ON(!valid_dma_direction(direction));
 
         BUG_ON(offset + size > PAGE_SIZE);
-        homecache_flush_cache(page, 0);
+        __dma_prep_page(page, offset, size, direction);
 
-        return page_to_pa(page) + offset;
+        return phys_to_dma(dev, page_to_pa(page) + offset);
 }
-EXPORT_SYMBOL(dma_map_page);
 
-void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
-               enum dma_data_direction direction)
+static void tile_pci_dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+                                    size_t size,
+                                    enum dma_data_direction direction,
+                                    struct dma_attrs *attrs)
 {
         BUG_ON(!valid_dma_direction(direction));
+
+        dma_address = dma_to_phys(dev, dma_address);
+
+        __dma_complete_page(pfn_to_page(PFN_DOWN(dma_address)),
+                            dma_address & PAGE_OFFSET, size, direction);
 }
-EXPORT_SYMBOL(dma_unmap_page);
 
-void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
-                             size_t size, enum dma_data_direction direction)
+static void tile_pci_dma_sync_single_for_cpu(struct device *dev,
+                                             dma_addr_t dma_handle,
+                                             size_t size,
+                                             enum dma_data_direction direction)
 {
         BUG_ON(!valid_dma_direction(direction));
+
+        dma_handle = dma_to_phys(dev, dma_handle);
+
+        __dma_complete_pa_range(dma_handle, size, direction);
 }
-EXPORT_SYMBOL(dma_sync_single_for_cpu);
 
-void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
-                                size_t size, enum dma_data_direction direction)
+static void tile_pci_dma_sync_single_for_device(struct device *dev,
+                                                dma_addr_t dma_handle,
+                                                size_t size,
+                                                enum dma_data_direction
+                                                direction)
 {
-        unsigned long start = PFN_DOWN(dma_handle);
-        unsigned long end = PFN_DOWN(dma_handle + size - 1);
-        unsigned long i;
+        dma_handle = dma_to_phys(dev, dma_handle);
 
-        BUG_ON(!valid_dma_direction(direction));
-        for (i = start; i <= end; ++i)
-                homecache_flush_cache(pfn_to_page(i), 0);
+        __dma_prep_pa_range(dma_handle, size, direction);
 }
-EXPORT_SYMBOL(dma_sync_single_for_device);
 
-void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
-                    enum dma_data_direction direction)
+static void tile_pci_dma_sync_sg_for_cpu(struct device *dev,
+                                         struct scatterlist *sglist,
+                                         int nelems,
+                                         enum dma_data_direction direction)
 {
+        struct scatterlist *sg;
+        int i;
+
         BUG_ON(!valid_dma_direction(direction));
-        WARN_ON(nelems == 0 || sg[0].length == 0);
+        WARN_ON(nelems == 0 || sglist->length == 0);
+
+        for_each_sg(sglist, sg, nelems, i) {
+                dma_sync_single_for_cpu(dev, sg->dma_address,
+                                        sg_dma_len(sg), direction);
+        }
 }
-EXPORT_SYMBOL(dma_sync_sg_for_cpu);
 
-/*
- * Flush and invalidate cache for scatterlist.
- */
-void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sglist,
-                            int nelems, enum dma_data_direction direction)
+static void tile_pci_dma_sync_sg_for_device(struct device *dev,
+                                            struct scatterlist *sglist,
+                                            int nelems,
+                                            enum dma_data_direction direction)
 {
         struct scatterlist *sg;
         int i;
@@ -222,31 +494,93 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sglist,
                                            sg_dma_len(sg), direction);
         }
 }
-EXPORT_SYMBOL(dma_sync_sg_for_device);
 
-void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
-                                   unsigned long offset, size_t size,
-                                   enum dma_data_direction direction)
+static inline int
+tile_pci_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
-        dma_sync_single_for_cpu(dev, dma_handle + offset, size, direction);
+        return 0;
 }
-EXPORT_SYMBOL(dma_sync_single_range_for_cpu);
 
-void dma_sync_single_range_for_device(struct device *dev,
-                                      dma_addr_t dma_handle,
-                                      unsigned long offset, size_t size,
-                                      enum dma_data_direction direction)
+static inline int
+tile_pci_dma_supported(struct device *dev, u64 mask)
 {
-        dma_sync_single_for_device(dev, dma_handle + offset, size, direction);
+        return 1;
 }
-EXPORT_SYMBOL(dma_sync_single_range_for_device);
 
-/*
- * dma_alloc_noncoherent() returns non-cacheable memory, so there's no
- * need to do any flushing here.
- */
-void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-                    enum dma_data_direction direction)
+static struct dma_map_ops tile_pci_default_dma_map_ops = {
+        .alloc = tile_pci_dma_alloc_coherent,
+        .free = tile_pci_dma_free_coherent,
+        .map_page = tile_pci_dma_map_page,
+        .unmap_page = tile_pci_dma_unmap_page,
+        .map_sg = tile_pci_dma_map_sg,
+        .unmap_sg = tile_pci_dma_unmap_sg,
+        .sync_single_for_cpu = tile_pci_dma_sync_single_for_cpu,
+        .sync_single_for_device = tile_pci_dma_sync_single_for_device,
+        .sync_sg_for_cpu = tile_pci_dma_sync_sg_for_cpu,
+        .sync_sg_for_device = tile_pci_dma_sync_sg_for_device,
+        .mapping_error = tile_pci_dma_mapping_error,
+        .dma_supported = tile_pci_dma_supported
+};
+
+struct dma_map_ops *gx_pci_dma_map_ops = &tile_pci_default_dma_map_ops;
+EXPORT_SYMBOL(gx_pci_dma_map_ops);
+
+/* PCI DMA mapping functions for legacy PCI devices */
+
+#ifdef CONFIG_SWIOTLB
+static void *tile_swiotlb_alloc_coherent(struct device *dev, size_t size,
+                                         dma_addr_t *dma_handle, gfp_t gfp,
+                                         struct dma_attrs *attrs)
 {
+        gfp |= GFP_DMA;
+        return swiotlb_alloc_coherent(dev, size, dma_handle, gfp);
+}
+
+static void tile_swiotlb_free_coherent(struct device *dev, size_t size,
+                                       void *vaddr, dma_addr_t dma_addr,
+                                       struct dma_attrs *attrs)
+{
+        swiotlb_free_coherent(dev, size, vaddr, dma_addr);
+}
+
+static struct dma_map_ops pci_swiotlb_dma_ops = {
+        .alloc = tile_swiotlb_alloc_coherent,
+        .free = tile_swiotlb_free_coherent,
+        .map_page = swiotlb_map_page,
+        .unmap_page = swiotlb_unmap_page,
+        .map_sg = swiotlb_map_sg_attrs,
+        .unmap_sg = swiotlb_unmap_sg_attrs,
+        .sync_single_for_cpu = swiotlb_sync_single_for_cpu,
+        .sync_single_for_device = swiotlb_sync_single_for_device,
+        .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
+        .sync_sg_for_device = swiotlb_sync_sg_for_device,
+        .dma_supported = swiotlb_dma_supported,
+        .mapping_error = swiotlb_dma_mapping_error,
+};
+
+struct dma_map_ops *gx_legacy_pci_dma_map_ops = &pci_swiotlb_dma_ops;
+#else
+struct dma_map_ops *gx_legacy_pci_dma_map_ops;
+#endif
+EXPORT_SYMBOL(gx_legacy_pci_dma_map_ops);
+
+#ifdef CONFIG_ARCH_HAS_DMA_SET_COHERENT_MASK
+int dma_set_coherent_mask(struct device *dev, u64 mask)
+{
+        struct dma_map_ops *dma_ops = get_dma_ops(dev);
+
+        /* Handle legacy PCI devices with limited memory addressability. */
+        if (((dma_ops == gx_pci_dma_map_ops) ||
+            (dma_ops == gx_legacy_pci_dma_map_ops)) &&
+            (mask <= DMA_BIT_MASK(32))) {
+                if (mask > dev->archdata.max_direct_dma_addr)
+                        mask = dev->archdata.max_direct_dma_addr;
+        }
+
+        if (!dma_supported(dev, mask))
+                return -EIO;
+        dev->coherent_dma_mask = mask;
+        return 0;
 }
-EXPORT_SYMBOL(dma_cache_sync);
+EXPORT_SYMBOL(dma_set_coherent_mask);
+#endif
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index b56d12bf590..33c10864d2f 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -310,6 +310,7 @@ int __init pcibios_init(void)
                 if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
                         struct pci_controller *controller = &controllers[i];
                         struct pci_bus *bus;
+                        LIST_HEAD(resources);
 
                         if (tile_init_irqs(i, controller)) {
                                 pr_err("PCI: Could not initialize IRQs\n");
@@ -327,9 +328,11 @@ int __init pcibios_init(void)
                          * This is inlined in linux/pci.h and calls into
                          * pci_scan_bus_parented() in probe.c.
                          */
-                        bus = pci_scan_bus(0, controller->ops, controller);
+                        pci_add_resource(&resources, &ioport_resource);
+                        pci_add_resource(&resources, &iomem_resource);
+                        bus = pci_scan_root_bus(NULL, 0, controller->ops, controller, &resources);
                         controller->root_bus = bus;
-                        controller->last_busno = bus->subordinate;
+                        controller->last_busno = bus->busn_res.end;
                 }
         }
 
@@ -401,16 +404,6 @@ void pcibios_set_master(struct pci_dev *dev)
 }
 
 /*
- * This can be called from the generic PCI layer, but doesn't need to
- * do anything.
- */
-char __devinit *pcibios_setup(char *str)
-{
-        /* Nothing needs to be done. */
-        return str;
-}
-
-/*
  * This is called from the generic Linux layer.
  */
 void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
diff --git a/arch/tile/kernel/pci_gx.c b/arch/tile/kernel/pci_gx.c
new file mode 100644
index 00000000000..0e213e35ffc
--- /dev/null
+++ b/arch/tile/kernel/pci_gx.c
@@ -0,0 +1,1543 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/mmzone.h>
+#include <linux/pci.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/capability.h>
+#include <linux/sched.h>
+#include <linux/errno.h>
+#include <linux/irq.h>
+#include <linux/msi.h>
+#include <linux/io.h>
+#include <linux/uaccess.h>
+#include <linux/ctype.h>
+
+#include <asm/processor.h>
+#include <asm/sections.h>
+#include <asm/byteorder.h>
+
+#include <gxio/iorpc_globals.h>
+#include <gxio/kiorpc.h>
+#include <gxio/trio.h>
+#include <gxio/iorpc_trio.h>
+#include <hv/drv_trio_intf.h>
+
+#include <arch/sim.h>
+
+/*
+ * This file containes the routines to search for PCI buses,
+ * enumerate the buses, and configure any attached devices.
+ */
+
+#define DEBUG_PCI_CFG   0
+
+#if DEBUG_PCI_CFG
+#define TRACE_CFG_WR(size, val, bus, dev, func, offset) \
+        pr_info("CFG WR %d-byte VAL %#x to bus %d dev %d func %d addr %u\n", \
+                size, val, bus, dev, func, offset & 0xFFF);
+#define TRACE_CFG_RD(size, val, bus, dev, func, offset) \
+        pr_info("CFG RD %d-byte VAL %#x from bus %d dev %d func %d addr %u\n", \
+                size, val, bus, dev, func, offset & 0xFFF);
+#else
+#define TRACE_CFG_WR(...)
+#define TRACE_CFG_RD(...)
+#endif
+
+static int __devinitdata pci_probe = 1;
+
+/* Information on the PCIe RC ports configuration. */
+static int __devinitdata pcie_rc[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
+
+/*
+ * On some platforms with one or more Gx endpoint ports, we need to
+ * delay the PCIe RC port probe for a few seconds to work around
+ * a HW PCIe link-training bug. The exact delay is specified with
+ * a kernel boot argument in the form of "pcie_rc_delay=T,P,S",
+ * where T is the TRIO instance number, P is the port number and S is
+ * the delay in seconds. If the delay is not provided, the value
+ * will be DEFAULT_RC_DELAY.
+ */
+static int __devinitdata rc_delay[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
+
+/* Default number of seconds that the PCIe RC port probe can be delayed. */
+#define DEFAULT_RC_DELAY        10
+
+/* Max number of seconds that the PCIe RC port probe can be delayed. */
+#define MAX_RC_DELAY            20
+
+/* Array of the PCIe ports configuration info obtained from the BIB. */
+struct pcie_port_property pcie_ports[TILEGX_NUM_TRIO][TILEGX_TRIO_PCIES];
+
+/* All drivers share the TRIO contexts defined here. */
+gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
+
+/* Pointer to an array of PCIe RC controllers. */
+struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
+int num_rc_controllers;
+static int num_ep_controllers;
+
+static struct pci_ops tile_cfg_ops;
+
+/* Mask of CPUs that should receive PCIe interrupts. */
+static struct cpumask intr_cpus_map;
+
+/*
+ * We don't need to worry about the alignment of resources.
+ */
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+                                resource_size_t size, resource_size_t align)
+{
+        return res->start;
+}
+EXPORT_SYMBOL(pcibios_align_resource);
+
+
+/*
+ * Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
+ * For now, we simply send interrupts to non-dataplane CPUs.
+ * We may implement methods to allow user to specify the target CPUs,
+ * e.g. via boot arguments.
+ */
+static int tile_irq_cpu(int irq)
+{
+        unsigned int count;
+        int i = 0;
+        int cpu;
+
+        count = cpumask_weight(&intr_cpus_map);
+        if (unlikely(count == 0)) {
+                pr_warning("intr_cpus_map empty, interrupts will be"
+                           " delievered to dataplane tiles\n");
+                return irq % (smp_height * smp_width);
+        }
+
+        count = irq % count;
+        for_each_cpu(cpu, &intr_cpus_map) {
+                if (i++ == count)
+                        break;
+        }
+        return cpu;
+}
+
+/*
+ * Open a file descriptor to the TRIO shim.
+ */
+static int __devinit tile_pcie_open(int trio_index)
+{
+        gxio_trio_context_t *context = &trio_contexts[trio_index];
+        int ret;
+
+        /*
+         * This opens a file descriptor to the TRIO shim.
+         */
+        ret = gxio_trio_init(context, trio_index);
+        if (ret < 0)
+                return ret;
+
+        /*
+         * Allocate an ASID for the kernel.
+         */
+        ret = gxio_trio_alloc_asids(context, 1, 0, 0);
+        if (ret < 0) {
+                pr_err("PCI: ASID alloc failure on TRIO %d, give up\n",
+                        trio_index);
+                goto asid_alloc_failure;
+        }
+
+        context->asid = ret;
+
+#ifdef USE_SHARED_PCIE_CONFIG_REGION
+        /*
+         * Alloc a PIO region for config access, shared by all MACs per TRIO.
+         * This shouldn't fail since the kernel is supposed to the first
+         * client of the TRIO's PIO regions.
+         */
+        ret = gxio_trio_alloc_pio_regions(context, 1, 0, 0);
+        if (ret < 0) {
+                pr_err("PCI: CFG PIO alloc failure on TRIO %d, give up\n",
+                        trio_index);
+                goto pio_alloc_failure;
+        }
+
+        context->pio_cfg_index = ret;
+
+        /*
+         * For PIO CFG, the bus_address_hi parameter is 0. The mac parameter
+         * is also 0 because it is specified in PIO_REGION_SETUP_CFG_ADDR.
+         */
+        ret = gxio_trio_init_pio_region_aux(context, context->pio_cfg_index,
+                0, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
+        if (ret < 0) {
+                pr_err("PCI: CFG PIO init failure on TRIO %d, give up\n",
+                        trio_index);
+                goto pio_alloc_failure;
+        }
+#endif
+
+        return ret;
+
+asid_alloc_failure:
+#ifdef USE_SHARED_PCIE_CONFIG_REGION
+pio_alloc_failure:
+#endif
+        hv_dev_close(context->fd);
+
+        return ret;
+}
+
+static void
+tilegx_legacy_irq_ack(struct irq_data *d)
+{
+        __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
+}
+
+static void
+tilegx_legacy_irq_mask(struct irq_data *d)
+{
+        __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
+}
+
+static void
+tilegx_legacy_irq_unmask(struct irq_data *d)
+{
+        __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
+}
+
+static struct irq_chip tilegx_legacy_irq_chip = {
+        .name                   = "tilegx_legacy_irq",
+        .irq_ack                = tilegx_legacy_irq_ack,
+        .irq_mask               = tilegx_legacy_irq_mask,
+        .irq_unmask             = tilegx_legacy_irq_unmask,
+
+        /* TBD: support set_affinity. */
+};
+
+/*
+ * This is a wrapper function of the kernel level-trigger interrupt
+ * handler handle_level_irq() for PCI legacy interrupts. The TRIO
+ * is configured such that only INTx Assert interrupts are proxied
+ * to Linux which just calls handle_level_irq() after clearing the
+ * MAC INTx Assert status bit associated with this interrupt.
+ */
+static void
+trio_handle_level_irq(unsigned int irq, struct irq_desc *desc)
+{
+        struct pci_controller *controller = irq_desc_get_handler_data(desc);
+        gxio_trio_context_t *trio_context = controller->trio;
+        uint64_t intx = (uint64_t)irq_desc_get_chip_data(desc);
+        int mac = controller->mac;
+        unsigned int reg_offset;
+        uint64_t level_mask;
+
+        handle_level_irq(irq, desc);
+
+        /*
+         * Clear the INTx Level status, otherwise future interrupts are
+         * not sent.
+         */
+        reg_offset = (TRIO_PCIE_INTFC_MAC_INT_STS <<
+                TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
+                TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+
+        level_mask = TRIO_PCIE_INTFC_MAC_INT_STS__INT_LEVEL_MASK << intx;
+
+        __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset, level_mask);
+}
+
+/*
+ * Create kernel irqs and set up the handlers for the legacy interrupts.
+ * Also some minimum initialization for the MSI support.
+ */
+static int __devinit tile_init_irqs(struct pci_controller *controller)
+{
+        int i;
+        int j;
+        int irq;
+        int result;
+
+        cpumask_copy(&intr_cpus_map, cpu_online_mask);
+
+
+        for (i = 0; i < 4; i++) {
+                gxio_trio_context_t *context = controller->trio;
+                int cpu;
+
+                /* Ask the kernel to allocate an IRQ. */
+                irq = create_irq();
+                if (irq < 0) {
+                        pr_err("PCI: no free irq vectors, failed for %d\n", i);
+
+                        goto free_irqs;
+                }
+                controller->irq_intx_table[i] = irq;
+
+                /* Distribute the 4 IRQs to different tiles. */
+                cpu = tile_irq_cpu(irq);
+
+                /* Configure the TRIO intr binding for this IRQ. */
+                result = gxio_trio_config_legacy_intr(context, cpu_x(cpu),
+                                                      cpu_y(cpu), KERNEL_PL,
+                                                      irq, controller->mac, i);
+                if (result < 0) {
+                        pr_err("PCI: MAC intx config failed for %d\n", i);
+
+                        goto free_irqs;
+                }
+
+                /*
+                 * Register the IRQ handler with the kernel.
+                 */
+                irq_set_chip_and_handler(irq, &tilegx_legacy_irq_chip,
+                                        trio_handle_level_irq);
+                irq_set_chip_data(irq, (void *)(uint64_t)i);
+                irq_set_handler_data(irq, controller);
+        }
+
+        return 0;
+
+free_irqs:
+        for (j = 0; j < i; j++)
+                destroy_irq(controller->irq_intx_table[j]);
+
+        return -1;
+}
+
+/*
+ * Find valid controllers and fill in pci_controller structs for each
+ * of them.
+ *
+ * Returns the number of controllers discovered.
+ */
+int __init tile_pci_init(void)
+{
+        int num_trio_shims = 0;
+        int ctl_index = 0;
+        int i, j;
+
+        if (!pci_probe) {
+                pr_info("PCI: disabled by boot argument\n");
+                return 0;
+        }
+
+        pr_info("PCI: Searching for controllers...\n");
+
+        /*
+         * We loop over all the TRIO shims.
+         */
+        for (i = 0; i < TILEGX_NUM_TRIO; i++) {
+                int ret;
+
+                ret = tile_pcie_open(i);
+                if (ret < 0)
+                        continue;
+
+                num_trio_shims++;
+        }
+
+        if (num_trio_shims == 0 || sim_is_simulator())
+                return 0;
+
+        /*
+         * Now determine which PCIe ports are configured to operate in RC mode.
+         * We look at the Board Information Block first and then see if there
+         * are any overriding configuration by the HW strapping pin.
+         */
+        for (i = 0; i < TILEGX_NUM_TRIO; i++) {
+                gxio_trio_context_t *context = &trio_contexts[i];
+                int ret;
+
+                if (context->fd < 0)
+                        continue;
+
+                ret = hv_dev_pread(context->fd, 0,
+                        (HV_VirtAddr)&pcie_ports[i][0],
+                        sizeof(struct pcie_port_property) * TILEGX_TRIO_PCIES,
+                        GXIO_TRIO_OP_GET_PORT_PROPERTY);
+                if (ret < 0) {
+                        pr_err("PCI: PCIE_GET_PORT_PROPERTY failure, error %d,"
+                                " on TRIO %d\n", ret, i);
+                        continue;
+                }
+
+                for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
+                        if (pcie_ports[i][j].allow_rc) {
+                                pcie_rc[i][j] = 1;
+                                num_rc_controllers++;
+                        }
+                        else if (pcie_ports[i][j].allow_ep) {
+                                num_ep_controllers++;
+                        }
+                }
+        }
+
+        /*
+         * Return if no PCIe ports are configured to operate in RC mode.
+         */
+        if (num_rc_controllers == 0)
+                return 0;
+
+        /*
+         * Set the TRIO pointer and MAC index for each PCIe RC port.
+         */
+        for (i = 0; i < TILEGX_NUM_TRIO; i++) {
+                for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
+                        if (pcie_rc[i][j]) {
+                                pci_controllers[ctl_index].trio =
+                                        &trio_contexts[i];
+                                pci_controllers[ctl_index].mac = j;
+                                pci_controllers[ctl_index].trio_index = i;
+                                ctl_index++;
+                                if (ctl_index == num_rc_controllers)
+                                        goto out;
+                        }
+                }
+        }
+
+out:
+        /*
+         * Configure each PCIe RC port.
+         */
+        for (i = 0; i < num_rc_controllers; i++) {
+                /*
+                 * Configure the PCIe MAC to run in RC mode.
+                 */
+
+                struct pci_controller *controller = &pci_controllers[i];
+
+                controller->index = i;
+                controller->ops = &tile_cfg_ops;
+
+                /*
+                 * The PCI memory resource is located above the PA space.
+                 * For every host bridge, the BAR window or the MMIO aperture
+                 * is in range [3GB, 4GB - 1] of a 4GB space beyond the
+                 * PA space.
+                 */
+
+                controller->mem_offset = TILE_PCI_MEM_START +
+                        (i * TILE_PCI_BAR_WINDOW_TOP);
+                controller->mem_space.start = controller->mem_offset +
+                        TILE_PCI_BAR_WINDOW_TOP - TILE_PCI_BAR_WINDOW_SIZE;
+                controller->mem_space.end = controller->mem_offset +
+                        TILE_PCI_BAR_WINDOW_TOP - 1;
+                controller->mem_space.flags = IORESOURCE_MEM;
+                snprintf(controller->mem_space_name,
+                         sizeof(controller->mem_space_name),
+                         "PCI mem domain %d", i);
+                controller->mem_space.name = controller->mem_space_name;
+        }
+
+        return num_rc_controllers;
+}
+
+/*
+ * (pin - 1) converts from the PCI standard's [1:4] convention to
+ * a normal [0:3] range.
+ */
+static int tile_map_irq(const struct pci_dev *dev, u8 device, u8 pin)
+{
+        struct pci_controller *controller =
+                (struct pci_controller *)dev->sysdata;
+        return controller->irq_intx_table[pin - 1];
+}
+
+
+static void __devinit fixup_read_and_payload_sizes(struct pci_controller *
+                                                controller)
+{
+        gxio_trio_context_t *trio_context = controller->trio;
+        struct pci_bus *root_bus = controller->root_bus;
+        TRIO_PCIE_RC_DEVICE_CONTROL_t dev_control;
+        TRIO_PCIE_RC_DEVICE_CAP_t rc_dev_cap;
+        unsigned int reg_offset;
+        struct pci_bus *child;
+        int mac;
+        int err;
+
+        mac = controller->mac;
+
+        /*
+         * Set our max read request size to be 4KB.
+         */
+        reg_offset =
+                (TRIO_PCIE_RC_DEVICE_CONTROL <<
+                        TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
+                        TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+
+        dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
+                                                reg_offset);
+        dev_control.max_read_req_sz = 5;
+        __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
+                                                dev_control.word);
+
+        /*
+         * Set the max payload size supported by this Gx PCIe MAC.
+         * Though Gx PCIe supports Max Payload Size of up to 1024 bytes,
+         * experiments have shown that setting MPS to 256 yields the
+         * best performance.
+         */
+        reg_offset =
+                (TRIO_PCIE_RC_DEVICE_CAP <<
+                        TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
+                        TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+
+        rc_dev_cap.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
+                                                reg_offset);
+        rc_dev_cap.mps_sup = 1;
+        __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
+                                                rc_dev_cap.word);
+
+        /* Configure PCI Express MPS setting. */
+        list_for_each_entry(child, &root_bus->children, node) {
+                struct pci_dev *self = child->self;
+                if (!self)
+                        continue;
+
+                pcie_bus_configure_settings(child, self->pcie_mpss);
+        }
+
+        /*
+         * Set the mac_config register in trio based on the MPS/MRS of the link.
+         */
+        reg_offset =
+                (TRIO_PCIE_RC_DEVICE_CONTROL <<
+                        TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
+                        TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+
+        dev_control.word = __gxio_mmio_read32(trio_context->mmio_base_mac +
+                                                reg_offset);
+
+        err = gxio_trio_set_mps_mrs(trio_context,
+                                    dev_control.max_payload_size,
+                                    dev_control.max_read_req_sz,
+                                    mac);
+        if (err < 0) {
+                pr_err("PCI: PCIE_CONFIGURE_MAC_MPS_MRS failure, "
+                        "MAC %d on TRIO %d\n",
+                        mac, controller->trio_index);
+        }
+}
+
+static int __devinit setup_pcie_rc_delay(char *str)
+{
+        unsigned long delay = 0;
+        unsigned long trio_index;
+        unsigned long mac;
+
+        if (str == NULL || !isdigit(*str))
+                return -EINVAL;
+        trio_index = simple_strtoul(str, (char **)&str, 10);
+        if (trio_index >= TILEGX_NUM_TRIO)
+                return -EINVAL;
+
+        if (*str != ',')
+                return -EINVAL;
+
+        str++;
+        if (!isdigit(*str))
+                return -EINVAL;
+        mac = simple_strtoul(str, (char **)&str, 10);
+        if (mac >= TILEGX_TRIO_PCIES)
+                return -EINVAL;
+
+        if (*str != '\0') {
+                if (*str != ',')
+                        return -EINVAL;
+
+                str++;
+                if (!isdigit(*str))
+                        return -EINVAL;
+                delay = simple_strtoul(str, (char **)&str, 10);
+                if (delay > MAX_RC_DELAY)
+                        return -EINVAL;
+        }
+
+        rc_delay[trio_index][mac] = delay ? : DEFAULT_RC_DELAY;
+        pr_info("Delaying PCIe RC link training for %u sec"
+                " on MAC %lu on TRIO %lu\n", rc_delay[trio_index][mac],
+                mac, trio_index);
+        return 0;
+}
+early_param("pcie_rc_delay", setup_pcie_rc_delay);
+
+/*
+ * PCI initialization entry point, called by subsys_initcall.
+ */
+int __init pcibios_init(void)
+{
+        resource_size_t offset;
+        LIST_HEAD(resources);
+        int next_busno;
+        int i;
+
+        tile_pci_init();
+
+        if (num_rc_controllers == 0 && num_ep_controllers == 0)
+                return 0;
+
+        /*
+         * We loop over all the TRIO shims and set up the MMIO mappings.
+         */
+        for (i = 0; i < TILEGX_NUM_TRIO; i++) {
+                gxio_trio_context_t *context = &trio_contexts[i];
+
+                if (context->fd < 0)
+                        continue;
+
+                /*
+                 * Map in the MMIO space for the MAC.
+                 */
+                offset = 0;
+                context->mmio_base_mac =
+                        iorpc_ioremap(context->fd, offset,
+                                      HV_TRIO_CONFIG_IOREMAP_SIZE);
+                if (context->mmio_base_mac == NULL) {
+                        pr_err("PCI: MAC map failure on TRIO %d\n", i);
+
+                        hv_dev_close(context->fd);
+                        context->fd = -1;
+                        continue;
+                }
+        }
+
+        /*
+         * Delay a bit in case devices aren't ready.  Some devices are
+         * known to require at least 20ms here, but we use a more
+         * conservative value.
+         */
+        msleep(250);
+
+        /* Scan all of the recorded PCI controllers.  */
+        for (next_busno = 0, i = 0; i < num_rc_controllers; i++) {
+                struct pci_controller *controller = &pci_controllers[i];
+                gxio_trio_context_t *trio_context = controller->trio;
+                TRIO_PCIE_INTFC_PORT_CONFIG_t port_config;
+                TRIO_PCIE_INTFC_PORT_STATUS_t port_status;
+                TRIO_PCIE_INTFC_TX_FIFO_CTL_t tx_fifo_ctl;
+                struct pci_bus *bus;
+                unsigned int reg_offset;
+                unsigned int class_code_revision;
+                int trio_index;
+                int mac;
+                int ret;
+
+                if (trio_context->fd < 0)
+                        continue;
+
+                trio_index = controller->trio_index;
+                mac = controller->mac;
+
+                /*
+                 * Check the port strap state which will override the BIB
+                 * setting.
+                 */
+
+                reg_offset =
+                        (TRIO_PCIE_INTFC_PORT_CONFIG <<
+                                TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                        (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
+                                TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                        (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+
+                port_config.word =
+                        __gxio_mmio_read(trio_context->mmio_base_mac +
+                                         reg_offset);
+
+                if ((port_config.strap_state !=
+                        TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC) &&
+                        (port_config.strap_state !=
+                        TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_RC_G1)) {
+                        /*
+                         * If this is really intended to be an EP port,
+                         * record it so that the endpoint driver will know about it.
+                         */
+                        if (port_config.strap_state ==
+                        TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT ||
+                        port_config.strap_state ==
+                        TRIO_PCIE_INTFC_PORT_CONFIG__STRAP_STATE_VAL_AUTO_CONFIG_ENDPOINT_G1)
+                                pcie_ports[trio_index][mac].allow_ep = 1;
+
+                        continue;
+                }
+
+                /*
+                 * Delay the RC link training if needed.
+                 */
+                if (rc_delay[trio_index][mac])
+                        msleep(rc_delay[trio_index][mac] * 1000);
+
+                ret = gxio_trio_force_rc_link_up(trio_context, mac);
+                if (ret < 0)
+                        pr_err("PCI: PCIE_FORCE_LINK_UP failure, "
+                                "MAC %d on TRIO %d\n", mac, trio_index);
+
+                pr_info("PCI: Found PCI controller #%d on TRIO %d MAC %d\n", i,
+                        trio_index, controller->mac);
+
+                /*
+                 * Wait a bit here because some EP devices take longer
+                 * to come up.
+                 */
+                msleep(1000);
+
+                /*
+                 * Check for PCIe link-up status.
+                 */
+
+                reg_offset =
+                        (TRIO_PCIE_INTFC_PORT_STATUS <<
+                                TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                        (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
+                                TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                        (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+
+                port_status.word =
+                        __gxio_mmio_read(trio_context->mmio_base_mac +
+                                         reg_offset);
+                if (!port_status.dl_up) {
+                        pr_err("PCI: link is down, MAC %d on TRIO %d\n",
+                                mac, trio_index);
+                        continue;
+                }
+
+                /*
+                 * Ensure that the link can come out of L1 power down state.
+                 * Strictly speaking, this is needed only in the case of
+                 * heavy RC-initiated DMAs.
+                 */
+                reg_offset =
+                        (TRIO_PCIE_INTFC_TX_FIFO_CTL <<
+                                TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                        (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_INTERFACE <<
+                                TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                        (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+                tx_fifo_ctl.word =
+                        __gxio_mmio_read(trio_context->mmio_base_mac +
+                                         reg_offset);
+                tx_fifo_ctl.min_p_credits = 0;
+                __gxio_mmio_write(trio_context->mmio_base_mac + reg_offset,
+                                  tx_fifo_ctl.word);
+
+                /*
+                 * Change the device ID so that Linux bus crawl doesn't confuse
+                 * the internal bridge with any Tilera endpoints.
+                 */
+
+                reg_offset =
+                        (TRIO_PCIE_RC_DEVICE_ID_VEN_ID <<
+                                TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                        (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
+                                TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                        (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+
+                __gxio_mmio_write32(trio_context->mmio_base_mac + reg_offset,
+                                    (TILERA_GX36_RC_DEV_ID <<
+                                    TRIO_PCIE_RC_DEVICE_ID_VEN_ID__DEV_ID_SHIFT) |
+                                    TILERA_VENDOR_ID);
+
+                /*
+                 * Set the internal P2P bridge class code.
+                 */
+
+                reg_offset =
+                        (TRIO_PCIE_RC_REVISION_ID <<
+                                TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                        (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_STANDARD <<
+                                TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                        (mac << TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+
+                class_code_revision =
+                        __gxio_mmio_read32(trio_context->mmio_base_mac +
+                                           reg_offset);
+                class_code_revision = (class_code_revision & 0xff ) |
+                                        (PCI_CLASS_BRIDGE_PCI << 16);
+
+                __gxio_mmio_write32(trio_context->mmio_base_mac +
+                                    reg_offset, class_code_revision);
+
+#ifdef USE_SHARED_PCIE_CONFIG_REGION
+
+                /*
+                 * Map in the MMIO space for the PIO region.
+                 */
+                offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index) |
+                        (((unsigned long long)mac) <<
+                        TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
+
+#else
+
+                /*
+                 * Alloc a PIO region for PCI config access per MAC.
+                 */
+                ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
+                if (ret < 0) {
+                        pr_err("PCI: PCI CFG PIO alloc failure for mac %d "
+                                "on TRIO %d, give up\n", mac, trio_index);
+
+                        continue;
+                }
+
+                trio_context->pio_cfg_index[mac] = ret;
+
+                /*
+                 * For PIO CFG, the bus_address_hi parameter is 0.
+                 */
+                ret = gxio_trio_init_pio_region_aux(trio_context,
+                        trio_context->pio_cfg_index[mac],
+                        mac, 0, HV_TRIO_PIO_FLAG_CONFIG_SPACE);
+                if (ret < 0) {
+                        pr_err("PCI: PCI CFG PIO init failure for mac %d "
+                                "on TRIO %d, give up\n", mac, trio_index);
+
+                        continue;
+                }
+
+                offset = HV_TRIO_PIO_OFFSET(trio_context->pio_cfg_index[mac]) |
+                        (((unsigned long long)mac) <<
+                        TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT);
+
+#endif
+
+                trio_context->mmio_base_pio_cfg[mac] =
+                        iorpc_ioremap(trio_context->fd, offset,
+                        (1 << TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR__MAC_SHIFT));
+                if (trio_context->mmio_base_pio_cfg[mac] == NULL) {
+                        pr_err("PCI: PIO map failure for mac %d on TRIO %d\n",
+                                mac, trio_index);
+
+                        continue;
+                }
+
+                /*
+                 * Initialize the PCIe interrupts.
+                 */
+                if (tile_init_irqs(controller)) {
+                        pr_err("PCI: IRQs init failure for mac %d on TRIO %d\n",
+                                mac, trio_index);
+
+                        continue;
+                }
+
+                /*
+                 * The PCI memory resource is located above the PA space.
+                 * The memory range for the PCI root bus should not overlap
+                 * with the physical RAM
+                 */
+                pci_add_resource_offset(&resources, &controller->mem_space,
+                                        controller->mem_offset);
+
+                controller->first_busno = next_busno;
+                bus = pci_scan_root_bus(NULL, next_busno, controller->ops,
+                                        controller, &resources);
+                controller->root_bus = bus;
+                next_busno = bus->busn_res.end + 1;
+
+        }
+
+        /* Do machine dependent PCI interrupt routing */
+        pci_fixup_irqs(pci_common_swizzle, tile_map_irq);
+
+        /*
+         * This comes from the generic Linux PCI driver.
+         *
+         * It allocates all of the resources (I/O memory, etc)
+         * associated with the devices read in above.
+         */
+
+        pci_assign_unassigned_resources();
+
+        /* Record the I/O resources in the PCI controller structure. */
+        for (i = 0; i < num_rc_controllers; i++) {
+                struct pci_controller *controller = &pci_controllers[i];
+                gxio_trio_context_t *trio_context = controller->trio;
+                struct pci_bus *root_bus = pci_controllers[i].root_bus;
+                struct pci_bus *next_bus;
+                uint32_t bus_address_hi;
+                struct pci_dev *dev;
+                int ret;
+                int j;
+
+                /*
+                 * Skip controllers that are not properly initialized or
+                 * have down links.
+                 */
+                if (root_bus == NULL)
+                        continue;
+
+                /* Configure the max_payload_size values for this domain. */
+                fixup_read_and_payload_sizes(controller);
+
+                list_for_each_entry(dev, &root_bus->devices, bus_list) {
+                        /* Find the PCI host controller, ie. the 1st bridge. */
+                        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
+                                (PCI_SLOT(dev->devfn) == 0)) {
+                                next_bus = dev->subordinate;
+                                pci_controllers[i].mem_resources[0] =
+                                        *next_bus->resource[0];
+                                pci_controllers[i].mem_resources[1] =
+                                         *next_bus->resource[1];
+                                pci_controllers[i].mem_resources[2] =
+                                         *next_bus->resource[2];
+
+                                break;
+                        }
+                }
+
+                if (pci_controllers[i].mem_resources[1].flags & IORESOURCE_MEM)
+                        bus_address_hi =
+                                pci_controllers[i].mem_resources[1].start >> 32;
+                else if (pci_controllers[i].mem_resources[2].flags & IORESOURCE_PREFETCH)
+                        bus_address_hi =
+                                pci_controllers[i].mem_resources[2].start >> 32;
+                else {
+                        /* This is unlikely. */
+                        pr_err("PCI: no memory resources on TRIO %d mac %d\n",
+                                controller->trio_index, controller->mac);
+                        continue;
+                }
+
+                /*
+                 * Alloc a PIO region for PCI memory access for each RC port.
+                 */
+                ret = gxio_trio_alloc_pio_regions(trio_context, 1, 0, 0);
+                if (ret < 0) {
+                        pr_err("PCI: MEM PIO alloc failure on TRIO %d mac %d, "
+                                "give up\n", controller->trio_index,
+                                controller->mac);
+
+                        continue;
+                }
+
+                controller->pio_mem_index = ret;
+
+                /*
+                 * For PIO MEM, the bus_address_hi parameter is hard-coded 0
+                 * because we always assign 32-bit PCI bus BAR ranges.
+                 */
+                ret = gxio_trio_init_pio_region_aux(trio_context,
+                                                    controller->pio_mem_index,
+                                                    controller->mac,
+                                                    0,
+                                                    0);
+                if (ret < 0) {
+                        pr_err("PCI: MEM PIO init failure on TRIO %d mac %d, "
+                                "give up\n", controller->trio_index,
+                                controller->mac);
+
+                        continue;
+                }
+
+                /*
+                 * Configure a Mem-Map region for each memory controller so
+                 * that Linux can map all of its PA space to the PCI bus.
+                 * Use the IOMMU to handle hash-for-home memory.
+                 */
+                for_each_online_node(j) {
+                        unsigned long start_pfn = node_start_pfn[j];
+                        unsigned long end_pfn = node_end_pfn[j];
+                        unsigned long nr_pages = end_pfn - start_pfn;
+
+                        ret = gxio_trio_alloc_memory_maps(trio_context, 1, 0,
+                                                          0);
+                        if (ret < 0) {
+                                pr_err("PCI: Mem-Map alloc failure on TRIO %d "
+                                        "mac %d for MC %d, give up\n",
+                                        controller->trio_index,
+                                        controller->mac, j);
+
+                                goto alloc_mem_map_failed;
+                        }
+
+                        controller->mem_maps[j] = ret;
+
+                        /*
+                         * Initialize the Mem-Map and the I/O MMU so that all
+                         * the physical memory can be accessed by the endpoint
+                         * devices. The base bus address is set to the base CPA
+                         * of this memory controller plus an offset (see pci.h).
+                         * The region's base VA is set to the base CPA. The
+                         * I/O MMU table essentially translates the CPA to
+                         * the real PA. Implicitly, for node 0, we create
+                         * a separate Mem-Map region that serves as the inbound
+                         * window for legacy 32-bit devices. This is a direct
+                         * map of the low 4GB CPA space.
+                         */
+                        ret = gxio_trio_init_memory_map_mmu_aux(trio_context,
+                                controller->mem_maps[j],
+                                start_pfn << PAGE_SHIFT,
+                                nr_pages << PAGE_SHIFT,
+                                trio_context->asid,
+                                controller->mac,
+                                (start_pfn << PAGE_SHIFT) +
+                                TILE_PCI_MEM_MAP_BASE_OFFSET,
+                                j,
+                                GXIO_TRIO_ORDER_MODE_UNORDERED);
+                        if (ret < 0) {
+                                pr_err("PCI: Mem-Map init failure on TRIO %d "
+                                        "mac %d for MC %d, give up\n",
+                                        controller->trio_index,
+                                        controller->mac, j);
+
+                                goto alloc_mem_map_failed;
+                        }
+                        continue;
+
+alloc_mem_map_failed:
+                        break;
+                }
+
+        }
+
+        return 0;
+}
+subsys_initcall(pcibios_init);
+
+/* Note: to be deleted after Linux 3.6 merge. */
+void __devinit pcibios_fixup_bus(struct pci_bus *bus)
+{
+}
+
+/*
+ * This can be called from the generic PCI layer, but doesn't need to
+ * do anything.
+ */
+char __devinit *pcibios_setup(char *str)
+{
+        if (!strcmp(str, "off")) {
+                pci_probe = 0;
+                return NULL;
+        }
+        return str;
+}
+
+/*
+ * This is called from the generic Linux layer.
+ */
+void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
+{
+        pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
+}
+
+/*
+ * Enable memory address decoding, as appropriate, for the
+ * device described by the 'dev' struct. The I/O decoding
+ * is disabled, though the TILE-Gx supports I/O addressing.
+ *
+ * This is called from the generic PCI layer, and can be called
+ * for bridges or endpoints.
+ */
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+        return pci_enable_resources(dev, mask);
+}
+
+/* Called for each device after PCI setup is done. */
+static void __init
+pcibios_fixup_final(struct pci_dev *pdev)
+{
+        set_dma_ops(&pdev->dev, gx_pci_dma_map_ops);
+        set_dma_offset(&pdev->dev, TILE_PCI_MEM_MAP_BASE_OFFSET);
+        pdev->dev.archdata.max_direct_dma_addr =
+                TILE_PCI_MAX_DIRECT_DMA_ADDRESS;
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
+
+/* Map a PCI MMIO bus address into VA space. */
+void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
+{
+        struct pci_controller *controller = NULL;
+        resource_size_t bar_start;
+        resource_size_t bar_end;
+        resource_size_t offset;
+        resource_size_t start;
+        resource_size_t end;
+        int trio_fd;
+        int i, j;
+
+        start = phys_addr;
+        end = phys_addr + size - 1;
+
+        /*
+         * In the following, each PCI controller's mem_resources[1]
+         * represents its (non-prefetchable) PCI memory resource and
+         * mem_resources[2] refers to its prefetchable PCI memory resource.
+         * By searching phys_addr in each controller's mem_resources[], we can
+         * determine the controller that should accept the PCI memory access.
+         */
+
+        for (i = 0; i < num_rc_controllers; i++) {
+                /*
+                 * Skip controllers that are not properly initialized or
+                 * have down links.
+                 */
+                if (pci_controllers[i].root_bus == NULL)
+                        continue;
+
+                for (j = 1; j < 3; j++) {
+                        bar_start =
+                                pci_controllers[i].mem_resources[j].start;
+                        bar_end =
+                                pci_controllers[i].mem_resources[j].end;
+
+                        if ((start >= bar_start) && (end <= bar_end)) {
+
+                                controller = &pci_controllers[i];
+
+                                goto got_it;
+                        }
+                }
+        }
+
+        if (controller == NULL)
+                return NULL;
+
+got_it:
+        trio_fd = controller->trio->fd;
+
+        /* Convert the resource start to the bus address offset. */
+        start = phys_addr - controller->mem_offset;
+
+        offset = HV_TRIO_PIO_OFFSET(controller->pio_mem_index) + start;
+
+        /*
+         * We need to keep the PCI bus address's in-page offset in the VA.
+         */
+        return iorpc_ioremap(trio_fd, offset, size) +
+                (phys_addr & (PAGE_SIZE - 1));
+}
+EXPORT_SYMBOL(ioremap);
+
+void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
+{
+        iounmap(addr);
+}
+EXPORT_SYMBOL(pci_iounmap);
+
+/****************************************************************
+ *
+ * Tile PCI config space read/write routines
+ *
+ ****************************************************************/
+
+/*
+ * These are the normal read and write ops
+ * These are expanded with macros from  pci_bus_read_config_byte() etc.
+ *
+ * devfn is the combined PCI device & function.
+ *
+ * offset is in bytes, from the start of config space for the
+ * specified bus & device.
+ */
+
+static int __devinit tile_cfg_read(struct pci_bus *bus,
+                                   unsigned int devfn,
+                                   int offset,
+                                   int size,
+                                   u32 *val)
+{
+        struct pci_controller *controller = bus->sysdata;
+        gxio_trio_context_t *trio_context = controller->trio;
+        int busnum = bus->number & 0xff;
+        int device = PCI_SLOT(devfn);
+        int function = PCI_FUNC(devfn);
+        int config_type = 1;
+        TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
+        void *mmio_addr;
+
+        /*
+         * Map all accesses to the local device on root bus into the
+         * MMIO space of the MAC. Accesses to the downstream devices
+         * go to the PIO space.
+         */
+        if (pci_is_root_bus(bus)) {
+                if (device == 0) {
+                        /*
+                         * This is the internal downstream P2P bridge,
+                         * access directly.
+                         */
+                        unsigned int reg_offset;
+
+                        reg_offset = ((offset & 0xFFF) <<
+                                TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                                (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
+                                << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                                (controller->mac <<
+                                        TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+
+                        mmio_addr = trio_context->mmio_base_mac + reg_offset;
+
+                        goto valid_device;
+
+                } else {
+                        /*
+                         * We fake an empty device for (device > 0),
+                         * since there is only one device on bus 0.
+                         */
+                        goto invalid_device;
+                }
+        }
+
+        /*
+         * Accesses to the directly attached device have to be
+         * sent as type-0 configs.
+         */
+
+        if (busnum == (controller->first_busno + 1)) {
+                /*
+                 * There is only one device off of our built-in P2P bridge.
+                 */
+                if (device != 0)
+                        goto invalid_device;
+
+                config_type = 0;
+        }
+
+        cfg_addr.word = 0;
+        cfg_addr.reg_addr = (offset & 0xFFF);
+        cfg_addr.fn = function;
+        cfg_addr.dev = device;
+        cfg_addr.bus = busnum;
+        cfg_addr.type = config_type;
+
+        /*
+         * Note that we don't set the mac field in cfg_addr because the
+         * mapping is per port.
+         */
+
+        mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
+                        cfg_addr.word;
+
+valid_device:
+
+        switch (size) {
+        case 4:
+                *val = __gxio_mmio_read32(mmio_addr);
+                break;
+
+        case 2:
+                *val = __gxio_mmio_read16(mmio_addr);
+                break;
+
+        case 1:
+                *val = __gxio_mmio_read8(mmio_addr);
+                break;
+
+        default:
+                return PCIBIOS_FUNC_NOT_SUPPORTED;
+        }
+
+        TRACE_CFG_RD(size, *val, busnum, device, function, offset);
+
+        return 0;
+
+invalid_device:
+
+        switch (size) {
+        case 4:
+                *val = 0xFFFFFFFF;
+                break;
+
+        case 2:
+                *val = 0xFFFF;
+                break;
+
+        case 1:
+                *val = 0xFF;
+                break;
+
+        default:
+                return PCIBIOS_FUNC_NOT_SUPPORTED;
+        }
+
+        return 0;
+}
+
+
+/*
+ * See tile_cfg_read() for relevent comments.
+ * Note that "val" is the value to write, not a pointer to that value.
+ */
+static int __devinit tile_cfg_write(struct pci_bus *bus,
+                                    unsigned int devfn,
+                                    int offset,
+                                    int size,
+                                    u32 val)
+{
+        struct pci_controller *controller = bus->sysdata;
+        gxio_trio_context_t *trio_context = controller->trio;
+        int busnum = bus->number & 0xff;
+        int device = PCI_SLOT(devfn);
+        int function = PCI_FUNC(devfn);
+        int config_type = 1;
+        TRIO_TILE_PIO_REGION_SETUP_CFG_ADDR_t cfg_addr;
+        void *mmio_addr;
+        u32 val_32 = (u32)val;
+        u16 val_16 = (u16)val;
+        u8 val_8 = (u8)val;
+
+        /*
+         * Map all accesses to the local device on root bus into the
+         * MMIO space of the MAC. Accesses to the downstream devices
+         * go to the PIO space.
+         */
+        if (pci_is_root_bus(bus)) {
+                if (device == 0) {
+                        /*
+                         * This is the internal downstream P2P bridge,
+                         * access directly.
+                         */
+                        unsigned int reg_offset;
+
+                        reg_offset = ((offset & 0xFFF) <<
+                                TRIO_CFG_REGION_ADDR__REG_SHIFT) |
+                                (TRIO_CFG_REGION_ADDR__INTFC_VAL_MAC_PROTECTED
+                                << TRIO_CFG_REGION_ADDR__INTFC_SHIFT ) |
+                                (controller->mac <<
+                                        TRIO_CFG_REGION_ADDR__MAC_SEL_SHIFT);
+
+                        mmio_addr = trio_context->mmio_base_mac + reg_offset;
+
+                        goto valid_device;
+
+                } else {
+                        /*
+                         * We fake an empty device for (device > 0),
+                         * since there is only one device on bus 0.
+                         */
+                        goto invalid_device;
+                }
+        }
+
+        /*
+         * Accesses to the directly attached device have to be
+         * sent as type-0 configs.
+         */
+
+        if (busnum == (controller->first_busno + 1)) {
+                /*
+                 * There is only one device off of our built-in P2P bridge.
+                 */
+                if (device != 0)
+                        goto invalid_device;
+
+                config_type = 0;
+        }
+
+        cfg_addr.word = 0;
+        cfg_addr.reg_addr = (offset & 0xFFF);
+        cfg_addr.fn = function;
+        cfg_addr.dev = device;
+        cfg_addr.bus = busnum;
+        cfg_addr.type = config_type;
+
+        /*
+         * Note that we don't set the mac field in cfg_addr because the
+         * mapping is per port.
+         */
+
+        mmio_addr = trio_context->mmio_base_pio_cfg[controller->mac] +
+                        cfg_addr.word;
+
+valid_device:
+
+        switch (size) {
+        case 4:
+                __gxio_mmio_write32(mmio_addr, val_32);
+                TRACE_CFG_WR(size, val_32, busnum, device, function, offset);
+                break;
+
+        case 2:
+                __gxio_mmio_write16(mmio_addr, val_16);
+                TRACE_CFG_WR(size, val_16, busnum, device, function, offset);
+                break;
+
+        case 1:
+                __gxio_mmio_write8(mmio_addr, val_8);
+                TRACE_CFG_WR(size, val_8, busnum, device, function, offset);
+                break;
+
+        default:
+                return PCIBIOS_FUNC_NOT_SUPPORTED;
+        }
+
+invalid_device:
+
+        return 0;
+}
+
+
+static struct pci_ops tile_cfg_ops = {
+        .read =         tile_cfg_read,
+        .write =        tile_cfg_write,
+};
+
+
+/*
+ * MSI support starts here.
+ */
+static unsigned int
+tilegx_msi_startup(struct irq_data *d)
+{
+        if (d->msi_desc)
+                unmask_msi_irq(d);
+
+        return 0;
+}
+
+static void
+tilegx_msi_ack(struct irq_data *d)
+{
+        __insn_mtspr(SPR_IPI_EVENT_RESET_K, 1UL << d->irq);
+}
+
+static void
+tilegx_msi_mask(struct irq_data *d)
+{
+        mask_msi_irq(d);
+        __insn_mtspr(SPR_IPI_MASK_SET_K, 1UL << d->irq);
+}
+
+static void
+tilegx_msi_unmask(struct irq_data *d)
+{
+        __insn_mtspr(SPR_IPI_MASK_RESET_K, 1UL << d->irq);
+        unmask_msi_irq(d);
+}
+
+static struct irq_chip tilegx_msi_chip = {
+        .name                   = "tilegx_msi",
+        .irq_startup            = tilegx_msi_startup,
+        .irq_ack                = tilegx_msi_ack,
+        .irq_mask               = tilegx_msi_mask,
+        .irq_unmask             = tilegx_msi_unmask,
+
+        /* TBD: support set_affinity. */
+};
+
+int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
+{
+        struct pci_controller *controller;
+        gxio_trio_context_t *trio_context;
+        struct msi_msg msg;
+        int default_irq;
+        uint64_t mem_map_base;
+        uint64_t mem_map_limit;
+        u64 msi_addr;
+        int mem_map;
+        int cpu;
+        int irq;
+        int ret;
+
+        irq = create_irq();
+        if (irq < 0)
+                return irq;
+
+        /*
+         * Since we use a 64-bit Mem-Map to accept the MSI write, we fail
+         * devices that are not capable of generating a 64-bit message address.
+         * These devices will fall back to using the legacy interrupts.
+         * Most PCIe endpoint devices do support 64-bit message addressing.
+         */
+        if (desc->msi_attrib.is_64 == 0) {
+                dev_printk(KERN_INFO, &pdev->dev,
+                        "64-bit MSI message address not supported, "
+                        "falling back to legacy interrupts.\n");
+
+                ret = -ENOMEM;
+                goto is_64_failure;
+        }
+
+        default_irq = desc->msi_attrib.default_irq;
+        controller = irq_get_handler_data(default_irq);
+
+        BUG_ON(!controller);
+
+        trio_context = controller->trio;
+
+        /*
+         * Allocate the Mem-Map that will accept the MSI write and
+         * trigger the TILE-side interrupts.
+         */
+        mem_map = gxio_trio_alloc_memory_maps(trio_context, 1, 0, 0);
+        if (mem_map < 0) {
+                dev_printk(KERN_INFO, &pdev->dev,
+                        "%s Mem-Map alloc failure. "
+                        "Failed to initialize MSI interrupts. "
+                        "Falling back to legacy interrupts.\n",
+                        desc->msi_attrib.is_msix ? "MSI-X" : "MSI");
+
+                ret = -ENOMEM;
+                goto msi_mem_map_alloc_failure;
+        }
+
+        /* We try to distribute different IRQs to different tiles. */
+        cpu = tile_irq_cpu(irq);
+
+        /*
+         * Now call up to the HV to configure the Mem-Map interrupt and
+         * set up the IPI binding.
+         */
+        mem_map_base = MEM_MAP_INTR_REGIONS_BASE +
+                mem_map * MEM_MAP_INTR_REGION_SIZE;
+        mem_map_limit = mem_map_base + MEM_MAP_INTR_REGION_SIZE - 1;
+
+        ret = gxio_trio_config_msi_intr(trio_context, cpu_x(cpu), cpu_y(cpu),
+                                        KERNEL_PL, irq, controller->mac,
+                                        mem_map, mem_map_base, mem_map_limit,
+                                        trio_context->asid);
+        if (ret < 0) {
+                dev_printk(KERN_INFO, &pdev->dev, "HV MSI config failed.\n");
+
+                goto hv_msi_config_failure;
+        }
+
+        irq_set_msi_desc(irq, desc);
+
+        msi_addr = mem_map_base + TRIO_MAP_MEM_REG_INT3 - TRIO_MAP_MEM_REG_INT0;
+
+        msg.address_hi = msi_addr >> 32;
+        msg.address_lo = msi_addr & 0xffffffff;
+
+        msg.data = mem_map;
+
+        write_msi_msg(irq, &msg);
+        irq_set_chip_and_handler(irq, &tilegx_msi_chip, handle_level_irq);
+        irq_set_handler_data(irq, controller);
+
+        return 0;
+
+hv_msi_config_failure:
+        /* Free mem-map */
+msi_mem_map_alloc_failure:
+is_64_failure:
+        destroy_irq(irq);
+        return ret;
+}
+
+void arch_teardown_msi_irq(unsigned int irq)
+{
+        destroy_irq(irq);
+}
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index dd87f342039..6a649a4462d 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -23,6 +23,7 @@
 #include <linux/irq.h>
 #include <linux/kexec.h>
 #include <linux/pci.h>
+#include <linux/swiotlb.h>
 #include <linux/initrd.h>
 #include <linux/io.h>
 #include <linux/highmem.h>
@@ -109,7 +110,7 @@ static unsigned int __initdata maxnodemem_pfn[MAX_NUMNODES] = {
 };
 static nodemask_t __initdata isolnodes;
 
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(__tilegx__)
 enum { DEFAULT_PCI_RESERVE_MB = 64 };
 static unsigned int __initdata pci_reserve_mb = DEFAULT_PCI_RESERVE_MB;
 unsigned long __initdata pci_reserve_start_pfn = -1U;
@@ -160,7 +161,7 @@ static int __init setup_isolnodes(char *str)
 }
 early_param("isolnodes", setup_isolnodes);
 
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(__tilegx__)
 static int __init setup_pci_reserve(char* str)
 {
         unsigned long mb;
@@ -171,7 +172,7 @@ static int __init setup_pci_reserve(char* str)
 
         pci_reserve_mb = mb;
         pr_info("Reserving %dMB for PCIE root complex mappings\n",
-               pci_reserve_mb);
+                pci_reserve_mb);
         return 0;
 }
 early_param("pci_reserve", setup_pci_reserve);
@@ -411,7 +412,7 @@ static void __init setup_memory(void)
                         continue;
                 }
 #endif
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(__tilegx__)
                 /*
                  * Blocks that overlap the pci reserved region must
                  * have enough space to hold the maximum percpu data
@@ -604,11 +605,9 @@ static void __init setup_bootmem_allocator_node(int i)
         /* Free all the space back into the allocator. */
         free_bootmem(PFN_PHYS(start), PFN_PHYS(end - start));
 
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) && !defined(__tilegx__)
         /*
-         * Throw away any memory aliased by the PCI region.  FIXME: this
-         * is a temporary hack to work around bug 10502, and needs to be
-         * fixed properly.
+         * Throw away any memory aliased by the PCI region.
          */
         if (pci_reserve_start_pfn < end && pci_reserve_end_pfn > start)
                 reserve_bootmem(PFN_PHYS(pci_reserve_start_pfn),
@@ -658,6 +657,8 @@ static void __init zone_sizes_init(void)
         unsigned long zones_size[MAX_NR_ZONES] = { 0 };
         int size = percpu_size();
         int num_cpus = smp_height * smp_width;
+        const unsigned long dma_end = (1UL << (32 - PAGE_SHIFT));
+
         int i;
 
         for (i = 0; i < num_cpus; ++i)
@@ -729,6 +730,14 @@ static void __init zone_sizes_init(void)
                 zones_size[ZONE_NORMAL] = end - start;
 #endif
 
+                if (start < dma_end) {
+                        zones_size[ZONE_DMA] = min(zones_size[ZONE_NORMAL],
+                                                   dma_end - start);
+                        zones_size[ZONE_NORMAL] -= zones_size[ZONE_DMA];
+                } else {
+                        zones_size[ZONE_DMA] = 0;
+                }
+
                 /* Take zone metadata from controller 0 if we're isolnode. */
                 if (node_isset(i, isolnodes))
                         NODE_DATA(i)->bdata = &bootmem_node_data[0];
@@ -738,7 +747,7 @@ static void __init zone_sizes_init(void)
                        PFN_UP(node_percpu[i]));
 
                 /* Track the type of memory on each node */
-                if (zones_size[ZONE_NORMAL])
+                if (zones_size[ZONE_NORMAL] || zones_size[ZONE_DMA])
                         node_set_state(i, N_NORMAL_MEMORY);
 #ifdef CONFIG_HIGHMEM
                 if (end != start)
@@ -1343,7 +1352,7 @@ void __init setup_arch(char **cmdline_p)
         setup_cpu_maps();
 
 
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(__tilegx__)
         /*
          * Initialize the PCI structures.  This is done before memory
          * setup so that we know whether or not a pci_reserve region
@@ -1372,6 +1381,10 @@ void __init setup_arch(char **cmdline_p)
          * any memory using the bootmem allocator.
          */
 
+#ifdef CONFIG_SWIOTLB
+        swiotlb_init(0);
+#endif
+
         paging_init();
         setup_numa_mapping();
         zone_sizes_init();
@@ -1522,11 +1535,10 @@ static struct resource code_resource = {
 };
 
 /*
- * We reserve all resources above 4GB so that PCI won't try to put
- * mappings above 4GB; the standard allows that for some devices but
- * the probing code trunates values to 32 bits.
+ * On Pro, we reserve all resources above 4GB so that PCI won't try to put
+ * mappings above 4GB.
  */
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(__tilegx__)
 static struct resource* __init
 insert_non_bus_resource(void)
 {
@@ -1571,8 +1583,7 @@ static int __init request_standard_resources(void)
         int i;
         enum { CODE_DELTA = MEM_SV_INTRPT - PAGE_OFFSET };
 
-        iomem_resource.end = -1LL;
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(__tilegx__)
         insert_non_bus_resource();
 #endif
 
@@ -1580,7 +1591,7 @@ static int __init request_standard_resources(void)
                 u64 start_pfn = node_start_pfn[i];
                 u64 end_pfn = node_end_pfn[i];
 
-#ifdef CONFIG_PCI
+#if defined(CONFIG_PCI) && !defined(__tilegx__)
                 if (start_pfn <= pci_reserve_start_pfn &&
                     end_pfn > pci_reserve_start_pfn) {
                         if (end_pfn > pci_reserve_end_pfn)
diff --git a/arch/tile/kernel/smpboot.c b/arch/tile/kernel/smpboot.c
index 84873fbe8f2..e686c5ac90b 100644
--- a/arch/tile/kernel/smpboot.c
+++ b/arch/tile/kernel/smpboot.c
@@ -198,17 +198,7 @@ void __cpuinit online_secondary(void)
 
         notify_cpu_starting(smp_processor_id());
 
-        /*
-         * We need to hold call_lock, so there is no inconsistency
-         * between the time smp_call_function() determines number of
-         * IPI recipients, and the time when the determination is made
-         * for which cpus receive the IPI. Holding this
-         * lock helps us to not include this cpu in a currently in progress
-         * smp_call_function().
-         */
-        ipi_call_lock();
         set_cpu_online(smp_processor_id(), 1);
-        ipi_call_unlock();
         __get_cpu_var(cpu_state) = CPU_ONLINE;
 
         /* Set up tile-specific state for this cpu. */
diff --git a/arch/tile/kernel/usb.c b/arch/tile/kernel/usb.c
new file mode 100644
index 00000000000..5af8debc6a7
--- /dev/null
+++ b/arch/tile/kernel/usb.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2012 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * Register the Tile-Gx USB interfaces as platform devices.
+ *
+ * The actual USB driver is just some glue (in
+ * drivers/usb/host/[eo]hci-tilegx.c) which makes the registers available
+ * to the standard kernel EHCI and OHCI drivers.
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/usb/tilegx.h>
+#include <linux/types.h>
+
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
+
+#define USB_HOST_DEF(unit, type, dmamask) \
+        static struct \
+            tilegx_usb_platform_data tilegx_usb_platform_data_ ## type ## \
+                hci ## unit = { \
+                .dev_index = unit, \
+        }; \
+        \
+        static struct platform_device tilegx_usb_ ## type ## hci ## unit = { \
+                .name           = "tilegx-" #type "hci", \
+                .id             = unit, \
+                .dev = { \
+                        .dma_mask               = dmamask, \
+                        .coherent_dma_mask      = DMA_BIT_MASK(32), \
+                        .platform_data = \
+                                &tilegx_usb_platform_data_ ## type ## hci ## \
+                                unit, \
+                }, \
+        };
+
+USB_HOST_DEF(0, e, &ehci_dmamask)
+USB_HOST_DEF(0, o, NULL)
+USB_HOST_DEF(1, e, &ehci_dmamask)
+USB_HOST_DEF(1, o, NULL)
+
+#undef USB_HOST_DEF
+
+static struct platform_device *tilegx_usb_devices[] __initdata = {
+        &tilegx_usb_ehci0,
+        &tilegx_usb_ehci1,
+        &tilegx_usb_ohci0,
+        &tilegx_usb_ohci1,
+};
+
+/** Add our set of possible USB devices. */
+static int __init tilegx_usb_init(void)
+{
+        platform_add_devices(tilegx_usb_devices,
+                             ARRAY_SIZE(tilegx_usb_devices));
+
+        return 0;
+}
+arch_initcall(tilegx_usb_init);
diff --git a/arch/tile/lib/checksum.c b/arch/tile/lib/checksum.c
index e4bab5bd3f3..c3ca3e64d9d 100644
--- a/arch/tile/lib/checksum.c
+++ b/arch/tile/lib/checksum.c
@@ -16,19 +16,6 @@
 #include <net/checksum.h>
 #include <linux/module.h>
 
-static inline unsigned int longto16(unsigned long x)
-{
-        unsigned long ret;
-#ifdef __tilegx__
-        ret = __insn_v2sadu(x, 0);
-        ret = __insn_v2sadu(ret, 0);
-#else
-        ret = __insn_sadh_u(x, 0);
-        ret = __insn_sadh_u(ret, 0);
-#endif
-        return ret;
-}
-
 __wsum do_csum(const unsigned char *buff, int len)
 {
         int odd, count;
@@ -94,7 +81,7 @@ __wsum do_csum(const unsigned char *buff, int len)
         }
         if (len & 1)
                 result += *buff;
-        result = longto16(result);
+        result = csum_long(result);
         if (odd)
                 result = swab16(result);
 out:
diff --git a/arch/tile/mm/highmem.c b/arch/tile/mm/highmem.c
index ef8e5a62b6e..347d123b14b 100644
--- a/arch/tile/mm/highmem.c
+++ b/arch/tile/mm/highmem.c
@@ -93,7 +93,7 @@ static DEFINE_PER_CPU(struct kmap_amps, amps);
  * If we examine it earlier we are exposed to a race where it looks
  * writable earlier, but becomes immutable before we write the PTE.
  */
-static void kmap_atomic_register(struct page *page, enum km_type type,
+static void kmap_atomic_register(struct page *page, int type,
                                  unsigned long va, pte_t *ptep, pte_t pteval)
 {
         unsigned long flags;
diff --git a/arch/tile/mm/homecache.c b/arch/tile/mm/homecache.c
index dbcbdf7b8aa..5f7868dcd6d 100644
--- a/arch/tile/mm/homecache.c
+++ b/arch/tile/mm/homecache.c
@@ -64,10 +64,6 @@ early_param("noallocl2", set_noallocl2);
 
 #endif
 
-/* Provide no-op versions of these routines to keep flush_remote() cleaner. */
-#define mark_caches_evicted_start() 0
-#define mark_caches_evicted_finish(mask, timestamp) do {} while (0)
-
 
 /*
  * Update the irq_stat for cpus that we are going to interrupt
@@ -107,7 +103,6 @@ static void hv_flush_update(const struct cpumask *cache_cpumask,
  *    there's never any good reason for hv_flush_remote() to fail.
  *  - Accepts a 32-bit PFN rather than a 64-bit PA, which generally
  *    is the type that Linux wants to pass around anyway.
- *  - Centralizes the mark_caches_evicted() handling.
  *  - Canonicalizes that lengths of zero make cpumasks NULL.
  *  - Handles deferring TLB flushes for dataplane tiles.
  *  - Tracks remote interrupts in the per-cpu irq_cpustat_t.
@@ -126,7 +121,6 @@ void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
                   HV_Remote_ASID *asids, int asidcount)
 {
         int rc;
-        int timestamp = 0;  /* happy compiler */
         struct cpumask cache_cpumask_copy, tlb_cpumask_copy;
         struct cpumask *cache_cpumask, *tlb_cpumask;
         HV_PhysAddr cache_pa;
@@ -157,15 +151,11 @@ void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
         hv_flush_update(cache_cpumask, tlb_cpumask, tlb_va, tlb_length,
                         asids, asidcount);
         cache_pa = (HV_PhysAddr)cache_pfn << PAGE_SHIFT;
-        if (cache_control & HV_FLUSH_EVICT_L2)
-                timestamp = mark_caches_evicted_start();
         rc = hv_flush_remote(cache_pa, cache_control,
                              cpumask_bits(cache_cpumask),
                              tlb_va, tlb_length, tlb_pgsize,
                              cpumask_bits(tlb_cpumask),
                              asids, asidcount);
-        if (cache_control & HV_FLUSH_EVICT_L2)
-                mark_caches_evicted_finish(cache_cpumask, timestamp);
         if (rc == 0)
                 return;
         cpumask_scnprintf(cache_buf, sizeof(cache_buf), &cache_cpumask_copy);
@@ -180,85 +170,86 @@ void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
         panic("Unsafe to continue.");
 }
 
-void flush_remote_page(struct page *page, int order)
+static void homecache_finv_page_va(void* va, int home)
 {
-        int i, pages = (1 << order);
-        for (i = 0; i < pages; ++i, ++page) {
-                void *p = kmap_atomic(page);
-                int hfh = 0;
-                int home = page_home(page);
-#if CHIP_HAS_CBOX_HOME_MAP()
-                if (home == PAGE_HOME_HASH)
-                        hfh = 1;
-                else
-#endif
-                        BUG_ON(home < 0 || home >= NR_CPUS);
-                finv_buffer_remote(p, PAGE_SIZE, hfh);
-                kunmap_atomic(p);
+        if (home == smp_processor_id()) {
+                finv_buffer_local(va, PAGE_SIZE);
+        } else if (home == PAGE_HOME_HASH) {
+                finv_buffer_remote(va, PAGE_SIZE, 1);
+        } else {
+                BUG_ON(home < 0 || home >= NR_CPUS);
+                finv_buffer_remote(va, PAGE_SIZE, 0);
         }
 }
 
-void homecache_evict(const struct cpumask *mask)
+void homecache_finv_map_page(struct page *page, int home)
 {
-        flush_remote(0, HV_FLUSH_EVICT_L2, mask, 0, 0, 0, NULL, NULL, 0);
+        unsigned long flags;
+        unsigned long va;
+        pte_t *ptep;
+        pte_t pte;
+
+        if (home == PAGE_HOME_UNCACHED)
+                return;
+        local_irq_save(flags);
+#ifdef CONFIG_HIGHMEM
+        va = __fix_to_virt(FIX_KMAP_BEGIN + kmap_atomic_idx_push() +
+                           (KM_TYPE_NR * smp_processor_id()));
+#else
+        va = __fix_to_virt(FIX_HOMECACHE_BEGIN + smp_processor_id());
+#endif
+        ptep = virt_to_pte(NULL, (unsigned long)va);
+        pte = pfn_pte(page_to_pfn(page), PAGE_KERNEL);
+        __set_pte(ptep, pte_set_home(pte, home));
+        homecache_finv_page_va((void *)va, home);
+        __pte_clear(ptep);
+        hv_flush_page(va, PAGE_SIZE);
+#ifdef CONFIG_HIGHMEM
+        kmap_atomic_idx_pop();
+#endif
+        local_irq_restore(flags);
 }
 
-/*
- * Return a mask of the cpus whose caches currently own these pages.
- * The return value is whether the pages are all coherently cached
- * (i.e. none are immutable, incoherent, or uncached).
- */
-static int homecache_mask(struct page *page, int pages,
-                          struct cpumask *home_mask)
+static void homecache_finv_page_home(struct page *page, int home)
 {
-        int i;
-        int cached_coherently = 1;
-        cpumask_clear(home_mask);
-        for (i = 0; i < pages; ++i) {
-                int home = page_home(&page[i]);
-                if (home == PAGE_HOME_IMMUTABLE ||
-                    home == PAGE_HOME_INCOHERENT) {
-                        cpumask_copy(home_mask, cpu_possible_mask);
-                        return 0;
-                }
-#if CHIP_HAS_CBOX_HOME_MAP()
-                if (home == PAGE_HOME_HASH) {
-                        cpumask_or(home_mask, home_mask, &hash_for_home_map);
-                        continue;
-                }
-#endif
-                if (home == PAGE_HOME_UNCACHED) {
-                        cached_coherently = 0;
-                        continue;
-                }
-                BUG_ON(home < 0 || home >= NR_CPUS);
-                cpumask_set_cpu(home, home_mask);
-        }
-        return cached_coherently;
+        if (!PageHighMem(page) && home == page_home(page))
+                homecache_finv_page_va(page_address(page), home);
+        else
+                homecache_finv_map_page(page, home);
 }
 
-/*
- * Return the passed length, or zero if it's long enough that we
- * believe we should evict the whole L2 cache.
- */
-static unsigned long cache_flush_length(unsigned long length)
+static inline bool incoherent_home(int home)
 {
-        return (length >= CHIP_L2_CACHE_SIZE()) ? HV_FLUSH_EVICT_L2 : length;
+        return home == PAGE_HOME_IMMUTABLE || home == PAGE_HOME_INCOHERENT;
 }
 
-/* Flush a page out of whatever cache(s) it is in. */
-void homecache_flush_cache(struct page *page, int order)
+static void homecache_finv_page_internal(struct page *page, int force_map)
 {
-        int pages = 1 << order;
-        int length = cache_flush_length(pages * PAGE_SIZE);
-        unsigned long pfn = page_to_pfn(page);
-        struct cpumask home_mask;
-
-        homecache_mask(page, pages, &home_mask);
-        flush_remote(pfn, length, &home_mask, 0, 0, 0, NULL, NULL, 0);
-        sim_validate_lines_evicted(PFN_PHYS(pfn), pages * PAGE_SIZE);
+        int home = page_home(page);
+        if (home == PAGE_HOME_UNCACHED)
+                return;
+        if (incoherent_home(home)) {
+                int cpu;
+                for_each_cpu(cpu, &cpu_cacheable_map)
+                        homecache_finv_map_page(page, cpu);
+        } else if (force_map) {
+                /* Force if, e.g., the normal mapping is migrating. */
+                homecache_finv_map_page(page, home);
+        } else {
+                homecache_finv_page_home(page, home);
+        }
+        sim_validate_lines_evicted(PFN_PHYS(page_to_pfn(page)), PAGE_SIZE);
 }
 
+void homecache_finv_page(struct page *page)
+{
+        homecache_finv_page_internal(page, 0);
+}
+
+void homecache_evict(const struct cpumask *mask)
+{
+        flush_remote(0, HV_FLUSH_EVICT_L2, mask, 0, 0, 0, NULL, NULL, 0);
+}
 
 /* Report the home corresponding to a given PTE. */
 static int pte_to_home(pte_t pte)
@@ -441,15 +432,8 @@ struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
         return page;
 }
 
-void homecache_free_pages(unsigned long addr, unsigned int order)
+void __homecache_free_pages(struct page *page, unsigned int order)
 {
-        struct page *page;
-
-        if (addr == 0)
-                return;
-
-        VM_BUG_ON(!virt_addr_valid((void *)addr));
-        page = virt_to_page((void *)addr);
         if (put_page_testzero(page)) {
                 homecache_change_page_home(page, order, initial_page_home());
                 if (order == 0) {
@@ -460,3 +444,13 @@ void homecache_free_pages(unsigned long addr, unsigned int order)
                 }
         }
 }
+EXPORT_SYMBOL(__homecache_free_pages);
+
+void homecache_free_pages(unsigned long addr, unsigned int order)
+{
+        if (addr != 0) {
+                VM_BUG_ON(!virt_addr_valid((void *)addr));
+                __homecache_free_pages(virt_to_page((void *)addr), order);
+        }
+}
+EXPORT_SYMBOL(homecache_free_pages);
diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c
index 630dd2ce2af..ef29d6c5e10 100644
--- a/arch/tile/mm/init.c
+++ b/arch/tile/mm/init.c
@@ -150,7 +150,21 @@ void __init shatter_pmd(pmd_t *pmd)
         assign_pte(pmd, pte);
 }
 
-#ifdef CONFIG_HIGHMEM
+#ifdef __tilegx__
+static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
+{
+        pud_t *pud = pud_offset(&pgtables[pgd_index(va)], va);
+        if (pud_none(*pud))
+                assign_pmd(pud, alloc_pmd());
+        return pmd_offset(pud, va);
+}
+#else
+static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
+{
+        return pmd_offset(pud_offset(&pgtables[pgd_index(va)], va), va);
+}
+#endif
+
 /*
  * This function initializes a certain range of kernel virtual memory
  * with new bootmem page tables, everywhere page tables are missing in
@@ -163,24 +177,17 @@ void __init shatter_pmd(pmd_t *pmd)
  * checking the pgd every time.
  */
 static void __init page_table_range_init(unsigned long start,
-                                         unsigned long end, pgd_t *pgd_base)
+                                         unsigned long end, pgd_t *pgd)
 {
-        pgd_t *pgd;
-        int pgd_idx;
         unsigned long vaddr;
-
-        vaddr = start;
-        pgd_idx = pgd_index(vaddr);
-        pgd = pgd_base + pgd_idx;
-
-        for ( ; (pgd_idx < PTRS_PER_PGD) && (vaddr != end); pgd++, pgd_idx++) {
-                pmd_t *pmd = pmd_offset(pud_offset(pgd, vaddr), vaddr);
+        start = round_down(start, PMD_SIZE);
+        end = round_up(end, PMD_SIZE);
+        for (vaddr = start; vaddr < end; vaddr += PMD_SIZE) {
+                pmd_t *pmd = get_pmd(pgd, vaddr);
                 if (pmd_none(*pmd))
                         assign_pte(pmd, alloc_pte());
-                vaddr += PMD_SIZE;
         }
 }
-#endif /* CONFIG_HIGHMEM */
 
 
 #if CHIP_HAS_CBOX_HOME_MAP()
@@ -404,21 +411,6 @@ static inline pgprot_t ktext_set_nocache(pgprot_t prot)
         return prot;
 }
 
-#ifndef __tilegx__
-static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
-{
-        return pmd_offset(pud_offset(&pgtables[pgd_index(va)], va), va);
-}
-#else
-static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
-{
-        pud_t *pud = pud_offset(&pgtables[pgd_index(va)], va);
-        if (pud_none(*pud))
-                assign_pmd(pud, alloc_pmd());
-        return pmd_offset(pud, va);
-}
-#endif
-
 /* Temporary page table we use for staging. */
 static pgd_t pgtables[PTRS_PER_PGD]
  __attribute__((aligned(HV_PAGE_TABLE_ALIGN)));
@@ -741,16 +733,15 @@ static void __init set_non_bootmem_pages_init(void)
         for_each_zone(z) {
                 unsigned long start, end;
                 int nid = z->zone_pgdat->node_id;
+#ifdef CONFIG_HIGHMEM
                 int idx = zone_idx(z);
+#endif
 
                 start = z->zone_start_pfn;
-                if (start == 0)
-                        continue;  /* bootmem */
                 end = start + z->spanned_pages;
-                if (idx == ZONE_NORMAL) {
-                        BUG_ON(start != node_start_pfn[nid]);
-                        start = node_free_pfn[nid];
-                }
+                start = max(start, node_free_pfn[nid]);
+                start = max(start, max_low_pfn);
+
 #ifdef CONFIG_HIGHMEM
                 if (idx == ZONE_HIGHMEM)
                         totalhigh_pages += z->spanned_pages;
@@ -779,9 +770,6 @@ static void __init set_non_bootmem_pages_init(void)
  */
 void __init paging_init(void)
 {
-#ifdef CONFIG_HIGHMEM
-        unsigned long vaddr, end;
-#endif
 #ifdef __tilegx__
         pud_t *pud;
 #endif
@@ -789,14 +777,14 @@ void __init paging_init(void)
 
         kernel_physical_mapping_init(pgd_base);
 
-#ifdef CONFIG_HIGHMEM
         /*
          * Fixed mappings, only the page table structure has to be
          * created - mappings will be set by set_fixmap():
          */
-        vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
-        end = (FIXADDR_TOP + PMD_SIZE - 1) & PMD_MASK;
-        page_table_range_init(vaddr, end, pgd_base);
+        page_table_range_init(fix_to_virt(__end_of_fixed_addresses - 1),
+                              FIXADDR_TOP, pgd_base);
+
+#ifdef CONFIG_HIGHMEM
         permanent_kmaps_init(pgd_base);
 #endif
 
diff --git a/arch/tile/mm/pgtable.c b/arch/tile/mm/pgtable.c
index 345edfed9fc..de0de0c0e8a 100644
--- a/arch/tile/mm/pgtable.c
+++ b/arch/tile/mm/pgtable.c
@@ -575,13 +575,6 @@ void __iomem *ioremap_prot(resource_size_t phys_addr, unsigned long size,
 }
 EXPORT_SYMBOL(ioremap_prot);
 
-/* Map a PCI MMIO bus address into VA space. */
-void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
-{
-        panic("ioremap for PCI MMIO is not supported");
-}
-EXPORT_SYMBOL(ioremap);
-
 /* Unmap an MMIO VA mapping. */
 void iounmap(volatile void __iomem *addr_in)
 {
diff --git a/arch/um/defconfig b/arch/um/defconfig
index 7823ab12e6a..08107a79506 100644
--- a/arch/um/defconfig
+++ b/arch/um/defconfig
@@ -155,15 +155,15 @@ CONFIG_CPUSETS=y
 CONFIG_PROC_PID_CPUSET=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
-CONFIG_CGROUP_MEM_RES_CTLR=y
-CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
-# CONFIG_CGROUP_MEM_RES_CTLR_SWAP_ENABLED is not set
-# CONFIG_CGROUP_MEM_RES_CTLR_KMEM is not set
+CONFIG_CGROUP_MEMCG=y
+CONFIG_CGROUP_MEMCG_SWAP=y
+# CONFIG_CGROUP_MEMCG_SWAP_ENABLED is not set
+# CONFIG_CGROUP_MEMCG_KMEM is not set
 CONFIG_CGROUP_SCHED=y
 CONFIG_FAIR_GROUP_SCHED=y
 # CONFIG_CFS_BANDWIDTH is not set
 # CONFIG_RT_GROUP_SCHED is not set
-CONFIG_BLK_CGROUP=m
+CONFIG_BLK_CGROUP=y
 # CONFIG_DEBUG_BLK_CGROUP is not set
 # CONFIG_CHECKPOINT_RESTORE is not set
 CONFIG_NAMESPACES=y
diff --git a/arch/um/drivers/chan_kern.c b/arch/um/drivers/chan_kern.c
index 45e248c2f43..87eebfe03c6 100644
--- a/arch/um/drivers/chan_kern.c
+++ b/arch/um/drivers/chan_kern.c
@@ -150,9 +150,11 @@ void chan_enable_winch(struct chan *chan, struct tty_struct *tty)
 static void line_timer_cb(struct work_struct *work)
 {
         struct line *line = container_of(work, struct line, task.work);
+        struct tty_struct *tty = tty_port_tty_get(&line->port);
 
         if (!line->throttled)
-                chan_interrupt(line, line->tty, line->driver->read_irq);
+                chan_interrupt(line, tty, line->driver->read_irq);
+        tty_kref_put(tty);
 }
 
 int enable_chan(struct line *line)
diff --git a/arch/um/drivers/line.c b/arch/um/drivers/line.c
index acfd0e0fd0c..bbaf2c59830 100644
--- a/arch/um/drivers/line.c
+++ b/arch/um/drivers/line.c
@@ -19,9 +19,11 @@ static irqreturn_t line_interrupt(int irq, void *data)
 {
         struct chan *chan = data;
         struct line *line = chan->line;
+        struct tty_struct *tty = tty_port_tty_get(&line->port);
 
         if (line)
-                chan_interrupt(line, line->tty, irq);
+                chan_interrupt(line, tty, irq);
+        tty_kref_put(tty);
         return IRQ_HANDLED;
 }
 
@@ -219,92 +221,6 @@ void line_set_termios(struct tty_struct *tty, struct ktermios * old)
         /* nothing */
 }
 
-static const struct {
-        int  cmd;
-        char *level;
-        char *name;
-} tty_ioctls[] = {
-        /* don't print these, they flood the log ... */
-        { TCGETS,      NULL,       "TCGETS"      },
-        { TCSETS,      NULL,       "TCSETS"      },
-        { TCSETSW,     NULL,       "TCSETSW"     },
-        { TCFLSH,      NULL,       "TCFLSH"      },
-        { TCSBRK,      NULL,       "TCSBRK"      },
-
-        /* general tty stuff */
-        { TCSETSF,     KERN_DEBUG, "TCSETSF"     },
-        { TCGETA,      KERN_DEBUG, "TCGETA"      },
-        { TIOCMGET,    KERN_DEBUG, "TIOCMGET"    },
-        { TCSBRKP,     KERN_DEBUG, "TCSBRKP"     },
-        { TIOCMSET,    KERN_DEBUG, "TIOCMSET"    },
-
-        /* linux-specific ones */
-        { TIOCLINUX,   KERN_INFO,  "TIOCLINUX"   },
-        { KDGKBMODE,   KERN_INFO,  "KDGKBMODE"   },
-        { KDGKBTYPE,   KERN_INFO,  "KDGKBTYPE"   },
-        { KDSIGACCEPT, KERN_INFO,  "KDSIGACCEPT" },
-};
-
-int line_ioctl(struct tty_struct *tty, unsigned int cmd,
-                                unsigned long arg)
-{
-        int ret;
-        int i;
-
-        ret = 0;
-        switch(cmd) {
-#ifdef TIOCGETP
-        case TIOCGETP:
-        case TIOCSETP:
-        case TIOCSETN:
-#endif
-#ifdef TIOCGETC
-        case TIOCGETC:
-        case TIOCSETC:
-#endif
-#ifdef TIOCGLTC
-        case TIOCGLTC:
-        case TIOCSLTC:
-#endif
-        /* Note: these are out of date as we now have TCGETS2 etc but this
-           whole lot should probably go away */
-        case TCGETS:
-        case TCSETSF:
-        case TCSETSW:
-        case TCSETS:
-        case TCGETA:
-        case TCSETAF:
-        case TCSETAW:
-        case TCSETA:
-        case TCXONC:
-        case TCFLSH:
-        case TIOCOUTQ:
-        case TIOCINQ:
-        case TIOCGLCKTRMIOS:
-        case TIOCSLCKTRMIOS:
-        case TIOCPKT:
-        case TIOCGSOFTCAR:
-        case TIOCSSOFTCAR:
-                return -ENOIOCTLCMD;
-#if 0
-        case TCwhatever:
-                /* do something */
-                break;
-#endif
-        default:
-                for (i = 0; i < ARRAY_SIZE(tty_ioctls); i++)
-                        if (cmd == tty_ioctls[i].cmd)
-                                break;
-                if (i == ARRAY_SIZE(tty_ioctls)) {
-                        printk(KERN_ERR "%s: %s: unknown ioctl: 0x%x\n",
-                               __func__, tty->name, cmd);
-                }
-                ret = -ENOIOCTLCMD;
-                break;
-        }
-        return ret;
-}
-
 void line_throttle(struct tty_struct *tty)
 {
         struct line *line = tty->driver_data;
@@ -333,7 +249,7 @@ static irqreturn_t line_write_interrupt(int irq, void *data)
 {
         struct chan *chan = data;
         struct line *line = chan->line;
-        struct tty_struct *tty = line->tty;
+        struct tty_struct *tty;
         int err;
 
         /*
@@ -352,68 +268,42 @@ static irqreturn_t line_write_interrupt(int irq, void *data)
         }
         spin_unlock(&line->lock);
 
+        tty = tty_port_tty_get(&line->port);
         if (tty == NULL)
                 return IRQ_NONE;
 
         tty_wakeup(tty);
+        tty_kref_put(tty);
+
         return IRQ_HANDLED;
 }
 
 int line_setup_irq(int fd, int input, int output, struct line *line, void *data)
 {
         const struct line_driver *driver = line->driver;
-        int err = 0, flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
+        int err = 0;
 
         if (input)
                 err = um_request_irq(driver->read_irq, fd, IRQ_READ,
-                                       line_interrupt, flags,
-                                       driver->read_irq_name, data);
+                                     line_interrupt, IRQF_SHARED,
+                                     driver->read_irq_name, data);
         if (err)
                 return err;
         if (output)
                 err = um_request_irq(driver->write_irq, fd, IRQ_WRITE,
-                                        line_write_interrupt, flags,
-                                        driver->write_irq_name, data);
+                                     line_write_interrupt, IRQF_SHARED,
+                                     driver->write_irq_name, data);
         return err;
 }
 
-/*
- * Normally, a driver like this can rely mostly on the tty layer
- * locking, particularly when it comes to the driver structure.
- * However, in this case, mconsole requests can come in "from the
- * side", and race with opens and closes.
- *
- * mconsole config requests will want to be sure the device isn't in
- * use, and get_config, open, and close will want a stable
- * configuration.  The checking and modification of the configuration
- * is done under a spinlock.  Checking whether the device is in use is
- * line->tty->count > 1, also under the spinlock.
- *
- * line->count serves to decide whether the device should be enabled or
- * disabled on the host.  If it's equal to 0, then we are doing the
- * first open or last close.  Otherwise, open and close just return.
- */
-
-int line_open(struct line *lines, struct tty_struct *tty)
+static int line_activate(struct tty_port *port, struct tty_struct *tty)
 {
-        struct line *line = &lines[tty->index];
-        int err = -ENODEV;
-
-        mutex_lock(&line->count_lock);
-        if (!line->valid)
-                goto out_unlock;
-
-        err = 0;
-        if (line->count++)
-                goto out_unlock;
-
-        BUG_ON(tty->driver_data);
-        tty->driver_data = line;
-        line->tty = tty;
+        int ret;
+        struct line *line = tty->driver_data;
 
-        err = enable_chan(line);
-        if (err) /* line_close() will be called by our caller */
-                goto out_unlock;
+        ret = enable_chan(line);
+        if (ret)
+                return ret;
 
         if (!line->sigio) {
                 chan_enable_winch(line->chan_out, tty);
@@ -421,44 +311,60 @@ int line_open(struct line *lines, struct tty_struct *tty)
         }
 
         chan_window_size(line, &tty->winsize.ws_row,
-                         &tty->winsize.ws_col);
-out_unlock:
-        mutex_unlock(&line->count_lock);
-        return err;
+                &tty->winsize.ws_col);
+
+        return 0;
 }
 
-static void unregister_winch(struct tty_struct *tty);
+static const struct tty_port_operations line_port_ops = {
+        .activate = line_activate,
+};
 
-void line_close(struct tty_struct *tty, struct file * filp)
+int line_open(struct tty_struct *tty, struct file *filp)
 {
         struct line *line = tty->driver_data;
 
-        /*
-         * If line_open fails (and tty->driver_data is never set),
-         * tty_open will call line_close.  So just return in this case.
-         */
-        if (line == NULL)
-                return;
+        return tty_port_open(&line->port, tty, filp);
+}
 
-        /* We ignore the error anyway! */
-        flush_buffer(line);
+int line_install(struct tty_driver *driver, struct tty_struct *tty,
+                 struct line *line)
+{
+        int ret;
 
-        mutex_lock(&line->count_lock);
-        BUG_ON(!line->valid);
+        ret = tty_standard_install(driver, tty);
+        if (ret)
+                return ret;
 
-        if (--line->count)
-                goto out_unlock;
+        tty->driver_data = line;
 
-        line->tty = NULL;
-        tty->driver_data = NULL;
+        return 0;
+}
+
+static void unregister_winch(struct tty_struct *tty);
+
+void line_cleanup(struct tty_struct *tty)
+{
+        struct line *line = tty->driver_data;
 
         if (line->sigio) {
                 unregister_winch(tty);
                 line->sigio = 0;
         }
+}
+
+void line_close(struct tty_struct *tty, struct file * filp)
+{
+        struct line *line = tty->driver_data;
 
-out_unlock:
-        mutex_unlock(&line->count_lock);
+        tty_port_close(&line->port, tty, filp);
+}
+
+void line_hangup(struct tty_struct *tty)
+{
+        struct line *line = tty->driver_data;
+
+        tty_port_hangup(&line->port);
 }
 
 void close_lines(struct line *lines, int nlines)
@@ -476,9 +382,7 @@ int setup_one_line(struct line *lines, int n, char *init,
         struct tty_driver *driver = line->driver->driver;
         int err = -EINVAL;
 
-        mutex_lock(&line->count_lock);
-
-        if (line->count) {
+        if (line->port.count) {
                 *error_out = "Device is already open";
                 goto out;
         }
@@ -519,7 +423,6 @@ int setup_one_line(struct line *lines, int n, char *init,
                 }
         }
 out:
-        mutex_unlock(&line->count_lock);
         return err;
 }
 
@@ -607,13 +510,17 @@ int line_get_config(char *name, struct line *lines, unsigned int num, char *str,
 
         line = &lines[dev];
 
-        mutex_lock(&line->count_lock);
         if (!line->valid)
                 CONFIG_CHUNK(str, size, n, "none", 1);
-        else if (line->tty == NULL)
-                CONFIG_CHUNK(str, size, n, line->init_str, 1);
-        else n = chan_config_string(line, str, size, error_out);
-        mutex_unlock(&line->count_lock);
+        else {
+                struct tty_struct *tty = tty_port_tty_get(&line->port);
+                if (tty == NULL) {
+                        CONFIG_CHUNK(str, size, n, line->init_str, 1);
+                } else {
+                        n = chan_config_string(line, str, size, error_out);
+                        tty_kref_put(tty);
+                }
+        }
 
         return n;
 }
@@ -663,8 +570,9 @@ int register_lines(struct line_driver *line_driver,
         driver->init_termios = tty_std_termios;
         
         for (i = 0; i < nlines; i++) {
+                tty_port_init(&lines[i].port);
+                lines[i].port.ops = &line_port_ops;
                 spin_lock_init(&lines[i].lock);
-                mutex_init(&lines[i].count_lock);
                 lines[i].driver = line_driver;
                 INIT_LIST_HEAD(&lines[i].chan_list);
         }
@@ -779,8 +687,7 @@ void register_winch_irq(int fd, int tty_fd, int pid, struct tty_struct *tty,
                                    .stack       = stack });
 
         if (um_request_irq(WINCH_IRQ, fd, IRQ_READ, winch_interrupt,
-                           IRQF_SHARED | IRQF_SAMPLE_RANDOM,
-                           "winch", winch) < 0) {
+                           IRQF_SHARED, "winch", winch) < 0) {
                 printk(KERN_ERR "register_winch_irq - failed to register "
                        "IRQ\n");
                 goto out_free;
diff --git a/arch/um/drivers/line.h b/arch/um/drivers/line.h
index 0a1834719db..bae95611e7a 100644
--- a/arch/um/drivers/line.h
+++ b/arch/um/drivers/line.h
@@ -32,9 +32,7 @@ struct line_driver {
 };
 
 struct line {
-        struct tty_struct *tty;
-        struct mutex count_lock;
-        unsigned long count;
+        struct tty_port port;
         int valid;
 
         char *init_str;
@@ -59,7 +57,11 @@ struct line {
 };
 
 extern void line_close(struct tty_struct *tty, struct file * filp);
-extern int line_open(struct line *lines, struct tty_struct *tty);
+extern int line_open(struct tty_struct *tty, struct file *filp);
+extern int line_install(struct tty_driver *driver, struct tty_struct *tty,
+        struct line *line);
+extern void line_cleanup(struct tty_struct *tty);
+extern void line_hangup(struct tty_struct *tty);
 extern int line_setup(char **conf, unsigned nlines, char **def,
                       char *init, char *name);
 extern int line_write(struct tty_struct *tty, const unsigned char *buf,
@@ -70,8 +72,6 @@ extern int line_chars_in_buffer(struct tty_struct *tty);
 extern void line_flush_buffer(struct tty_struct *tty);
 extern void line_flush_chars(struct tty_struct *tty);
 extern int line_write_room(struct tty_struct *tty);
-extern int line_ioctl(struct tty_struct *tty, unsigned int cmd,
-                                unsigned long arg);
 extern void line_throttle(struct tty_struct *tty);
 extern void line_unthrottle(struct tty_struct *tty);
 
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c
index 43b39d61b53..664a60e8dfb 100644
--- a/arch/um/drivers/mconsole_kern.c
+++ b/arch/um/drivers/mconsole_kern.c
@@ -774,8 +774,7 @@ static int __init mconsole_init(void)
         register_reboot_notifier(&reboot_notifier);
 
         err = um_request_irq(MCONSOLE_IRQ, sock, IRQ_READ, mconsole_interrupt,
-                             IRQF_SHARED | IRQF_SAMPLE_RANDOM,
-                             "mconsole", (void *)sock);
+                             IRQF_SHARED, "mconsole", (void *)sock);
         if (err) {
                 printk(KERN_ERR "Failed to get IRQ for management console\n");
                 goto out;
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index 0d60c5685c2..458d324f062 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -339,7 +339,7 @@ static int setup_etheraddr(char *str, unsigned char *addr, char *name)
 random:
         printk(KERN_INFO
                "Choosing a random ethernet address for device %s\n", name);
-        random_ether_addr(addr);
+        eth_random_addr(addr);
         return 1;
 }
 
diff --git a/arch/um/drivers/port_kern.c b/arch/um/drivers/port_kern.c
index 11866ffd45a..1d83d50236e 100644
--- a/arch/um/drivers/port_kern.c
+++ b/arch/um/drivers/port_kern.c
@@ -100,8 +100,7 @@ static int port_accept(struct port_list *port)
                   .port         = port });
 
         if (um_request_irq(TELNETD_IRQ, socket[0], IRQ_READ, pipe_interrupt,
-                          IRQF_SHARED | IRQF_SAMPLE_RANDOM,
-                          "telnetd", conn)) {
+                          IRQF_SHARED, "telnetd", conn)) {
                 printk(KERN_ERR "port_accept : failed to get IRQ for "
                        "telnetd\n");
                 goto out_free;
@@ -184,8 +183,7 @@ void *port_data(int port_num)
         }
 
         if (um_request_irq(ACCEPT_IRQ, fd, IRQ_READ, port_interrupt,
-                          IRQF_SHARED | IRQF_SAMPLE_RANDOM,
-                          "port", port)) {
+                          IRQF_SHARED, "port", port)) {
                 printk(KERN_ERR "Failed to get IRQ for port %d\n", port_num);
                 goto out_close;
         }
diff --git a/arch/um/drivers/random.c b/arch/um/drivers/random.c
index b25296e6218..e32c6aa6396 100644
--- a/arch/um/drivers/random.c
+++ b/arch/um/drivers/random.c
@@ -131,8 +131,7 @@ static int __init rng_init (void)
         random_fd = err;
 
         err = um_request_irq(RANDOM_IRQ, random_fd, IRQ_READ, random_interrupt,
-                             IRQF_SAMPLE_RANDOM, "random",
-                             NULL);
+                             0, "random", NULL);
         if (err)
                 goto err_out_cleanup_hw;
 
diff --git a/arch/um/drivers/ssl.c b/arch/um/drivers/ssl.c
index e09801a1327..7e86f007012 100644
--- a/arch/um/drivers/ssl.c
+++ b/arch/um/drivers/ssl.c
@@ -87,40 +87,13 @@ static int ssl_remove(int n, char **error_out)
                            error_out);
 }
 
-static int ssl_open(struct tty_struct *tty, struct file *filp)
-{
-        int err = line_open(serial_lines, tty);
-
-        if (err)
-                printk(KERN_ERR "Failed to open serial line %d, err = %d\n",
-                       tty->index, err);
-
-        return err;
-}
-
-#if 0
-static void ssl_flush_buffer(struct tty_struct *tty)
-{
-        return;
-}
-
-static void ssl_stop(struct tty_struct *tty)
-{
-        printk(KERN_ERR "Someone should implement ssl_stop\n");
-}
-
-static void ssl_start(struct tty_struct *tty)
-{
-        printk(KERN_ERR "Someone should implement ssl_start\n");
-}
-
-void ssl_hangup(struct tty_struct *tty)
+static int ssl_install(struct tty_driver *driver, struct tty_struct *tty)
 {
+        return line_install(driver, tty, &serial_lines[tty->index]);
 }
-#endif
 
 static const struct tty_operations ssl_ops = {
-        .open                   = ssl_open,
+        .open                   = line_open,
         .close                  = line_close,
         .write                  = line_write,
         .put_char               = line_put_char,
@@ -129,14 +102,11 @@ static const struct tty_operations ssl_ops = {
         .flush_buffer           = line_flush_buffer,
         .flush_chars            = line_flush_chars,
         .set_termios            = line_set_termios,
-        .ioctl                  = line_ioctl,
         .throttle               = line_throttle,
         .unthrottle             = line_unthrottle,
-#if 0
-        .stop                   = ssl_stop,
-        .start                  = ssl_start,
-        .hangup                 = ssl_hangup,
-#endif
+        .install                = ssl_install,
+        .cleanup                = line_cleanup,
+        .hangup                 = line_hangup,
 };
 
 /* Changed by ssl_init and referenced by ssl_exit, which are both serialized
diff --git a/arch/um/drivers/stdio_console.c b/arch/um/drivers/stdio_console.c
index 7663541c372..929b99a261f 100644
--- a/arch/um/drivers/stdio_console.c
+++ b/arch/um/drivers/stdio_console.c
@@ -89,21 +89,17 @@ static int con_remove(int n, char **error_out)
         return line_remove(vts, ARRAY_SIZE(vts), n, error_out);
 }
 
-static int con_open(struct tty_struct *tty, struct file *filp)
-{
-        int err = line_open(vts, tty);
-        if (err)
-                printk(KERN_ERR "Failed to open console %d, err = %d\n",
-                       tty->index, err);
-
-        return err;
-}
-
 /* Set in an initcall, checked in an exitcall */
 static int con_init_done = 0;
 
+static int con_install(struct tty_driver *driver, struct tty_struct *tty)
+{
+        return line_install(driver, tty, &vts[tty->index]);
+}
+
 static const struct tty_operations console_ops = {
-        .open                   = con_open,
+        .open                   = line_open,
+        .install                = con_install,
         .close                  = line_close,
         .write                  = line_write,
         .put_char               = line_put_char,
@@ -112,9 +108,10 @@ static const struct tty_operations console_ops = {
         .flush_buffer           = line_flush_buffer,
         .flush_chars            = line_flush_chars,
         .set_termios            = line_set_termios,
-        .ioctl                  = line_ioctl,
         .throttle               = line_throttle,
         .unthrottle             = line_unthrottle,
+        .cleanup                = line_cleanup,
+        .hangup                 = line_hangup,
 };
 
 static void uml_console_write(struct console *console, const char *string,
diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c
index 20505cafa29..0643e5bc9f4 100644
--- a/arch/um/drivers/ubd_kern.c
+++ b/arch/um/drivers/ubd_kern.c
@@ -514,7 +514,7 @@ static inline int ubd_file_size(struct ubd *ubd_dev, __u64 *size_out)
                 goto out;
         }
 
-        fd = os_open_file(ubd_dev->file, global_openflags, 0);
+        fd = os_open_file(ubd_dev->file, of_read(OPENFLAGS()), 0);
         if (fd < 0)
                 return fd;
 
diff --git a/arch/um/drivers/xterm_kern.c b/arch/um/drivers/xterm_kern.c
index b68bbe269e0..e3031e69445 100644
--- a/arch/um/drivers/xterm_kern.c
+++ b/arch/um/drivers/xterm_kern.c
@@ -50,8 +50,7 @@ int xterm_fd(int socket, int *pid_out)
         init_completion(&data->ready);
 
         err = um_request_irq(XTERM_IRQ, socket, IRQ_READ, xterm_interrupt,
-                             IRQF_SHARED | IRQF_SAMPLE_RANDOM,
-                             "xterm", data);
+                             IRQF_SHARED, "xterm", data);
         if (err) {
                 printk(KERN_ERR "xterm_fd : failed to get IRQ for xterm, "
                        "err = %d\n",  err);
diff --git a/arch/um/include/asm/kmap_types.h b/arch/um/include/asm/kmap_types.h
index 6c03acdb440..2e0a6b1d830 100644
--- a/arch/um/include/asm/kmap_types.h
+++ b/arch/um/include/asm/kmap_types.h
@@ -8,22 +8,6 @@
 
 /* No more #include "asm/arch/kmap_types.h" ! */
 
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_UML_USERCOPY,        /* UML specific, for copy_*_user - used in do_op_one_page */
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
+#define KM_TYPE_NR 14
 
 #endif
diff --git a/arch/um/include/asm/ptrace-generic.h b/arch/um/include/asm/ptrace-generic.h
index e786a6a3ec5..442f1d025dc 100644
--- a/arch/um/include/asm/ptrace-generic.h
+++ b/arch/um/include/asm/ptrace-generic.h
@@ -37,6 +37,8 @@ extern int putreg(struct task_struct *child, int regno, unsigned long value);
 
 extern int arch_copy_tls(struct task_struct *new);
 extern void clear_flushed_tls(struct task_struct *task);
+extern void syscall_trace_enter(struct pt_regs *regs);
+extern void syscall_trace_leave(struct pt_regs *regs);
 
 #endif
 
diff --git a/arch/um/include/shared/as-layout.h b/arch/um/include/shared/as-layout.h
index 896e1660217..86daa546181 100644
--- a/arch/um/include/shared/as-layout.h
+++ b/arch/um/include/shared/as-layout.h
@@ -60,7 +60,8 @@ extern unsigned long host_task_size;
 
 extern int linux_main(int argc, char **argv);
 
-extern void (*sig_info[])(int, struct uml_pt_regs *);
+struct siginfo;
+extern void (*sig_info[])(int, struct siginfo *si, struct uml_pt_regs *);
 
 #endif
 
diff --git a/arch/um/include/shared/irq_user.h b/arch/um/include/shared/irq_user.h
index c6c784df267..2b6d703925b 100644
--- a/arch/um/include/shared/irq_user.h
+++ b/arch/um/include/shared/irq_user.h
@@ -20,7 +20,8 @@ struct irq_fd {
 
 enum { IRQ_READ, IRQ_WRITE };
 
-extern void sigio_handler(int sig, struct uml_pt_regs *regs);
+struct siginfo;
+extern void sigio_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs);
 extern void free_irq_by_fd(int fd);
 extern void reactivate_fd(int fd, int irqnum);
 extern void deactivate_fd(int fd, int irqnum);
diff --git a/arch/um/include/shared/kern_util.h b/arch/um/include/shared/kern_util.h
index 00965d06d2c..af6b6dc868b 100644
--- a/arch/um/include/shared/kern_util.h
+++ b/arch/um/include/shared/kern_util.h
@@ -9,6 +9,8 @@
 #include "sysdep/ptrace.h"
 #include "sysdep/faultinfo.h"
 
+struct siginfo;
+
 extern int uml_exitcode;
 
 extern int ncpus;
@@ -22,7 +24,7 @@ extern void free_stack(unsigned long stack, int order);
 
 extern int do_signal(void);
 extern void interrupt_end(void);
-extern void relay_signal(int sig, struct uml_pt_regs *regs);
+extern void relay_signal(int sig, struct siginfo *si, struct uml_pt_regs *regs);
 
 extern unsigned long segv(struct faultinfo fi, unsigned long ip,
                           int is_user, struct uml_pt_regs *regs);
@@ -33,9 +35,8 @@ extern unsigned int do_IRQ(int irq, struct uml_pt_regs *regs);
 extern int smp_sigio_handler(void);
 extern void initial_thread_cb(void (*proc)(void *), void *arg);
 extern int is_syscall(unsigned long addr);
-extern void timer_handler(int sig, struct uml_pt_regs *regs);
 
-extern void timer_handler(int sig, struct uml_pt_regs *regs);
+extern void timer_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs);
 
 extern int start_uml(void);
 extern void paging_init(void);
@@ -59,9 +60,9 @@ extern unsigned long from_irq_stack(int nested);
 extern void syscall_trace(struct uml_pt_regs *regs, int entryexit);
 extern int singlestepping(void *t);
 
-extern void segv_handler(int sig, struct uml_pt_regs *regs);
-extern void bus_handler(int sig, struct uml_pt_regs *regs);
-extern void winch(int sig, struct uml_pt_regs *regs);
+extern void segv_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs);
+extern void bus_handler(int sig, struct siginfo *si, struct uml_pt_regs *regs);
+extern void winch(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs);
 extern void fatal_sigsegv(void) __attribute__ ((noreturn));
 
 
diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c
index 00506c3d5d6..9883026f073 100644
--- a/arch/um/kernel/irq.c
+++ b/arch/um/kernel/irq.c
@@ -30,7 +30,7 @@ static struct irq_fd **last_irq_ptr = &active_fds;
 
 extern void free_irqs(void);
 
-void sigio_handler(int sig, struct uml_pt_regs *regs)
+void sigio_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs)
 {
         struct irq_fd *irq_fd;
         int n;
diff --git a/arch/um/kernel/process.c b/arch/um/kernel/process.c
index ccb9a9d283f..57fc7028714 100644
--- a/arch/um/kernel/process.c
+++ b/arch/um/kernel/process.c
@@ -151,12 +151,10 @@ void new_thread_handler(void)
          * 0 if it just exits
          */
         n = run_kernel_thread(fn, arg, &current->thread.exec_buf);
-        if (n == 1) {
-                /* Handle any immediate reschedules or signals */
-                interrupt_end();
+        if (n == 1)
                 userspace(&current->thread.regs.regs);
-        }
-        else do_exit(0);
+        else
+                do_exit(0);
 }
 
 /* Called magically, see new_thread_handler above */
@@ -175,9 +173,6 @@ void fork_handler(void)
 
         current->thread.prev_sched = NULL;
 
-        /* Handle any immediate reschedules or signals */
-        interrupt_end();
-
         userspace(&current->thread.regs.regs);
 }
 
@@ -193,7 +188,7 @@ int copy_thread(unsigned long clone_flags, unsigned long sp,
         if (current->thread.forking) {
                 memcpy(&p->thread.regs.regs, &regs->regs,
                        sizeof(p->thread.regs.regs));
-                UPT_SET_SYSCALL_RETURN(&p->thread.regs.regs, 0);
+                PT_REGS_SET_SYSCALL_RETURN(&p->thread.regs, 0);
                 if (sp != 0)
                         REGS_SP(p->thread.regs.regs.gp) = sp;
 
diff --git a/arch/um/kernel/ptrace.c b/arch/um/kernel/ptrace.c
index 06b19039050..694d551c889 100644
--- a/arch/um/kernel/ptrace.c
+++ b/arch/um/kernel/ptrace.c
@@ -3,11 +3,12 @@
  * Licensed under the GPL
  */
 
-#include "linux/audit.h"
-#include "linux/ptrace.h"
-#include "linux/sched.h"
-#include "asm/uaccess.h"
-#include "skas_ptrace.h"
+#include <linux/audit.h>
+#include <linux/ptrace.h>
+#include <linux/sched.h>
+#include <linux/tracehook.h>
+#include <asm/uaccess.h>
+#include <skas_ptrace.h>
 
 
 
@@ -162,48 +163,36 @@ static void send_sigtrap(struct task_struct *tsk, struct uml_pt_regs *regs,
  * XXX Check PT_DTRACE vs TIF_SINGLESTEP for singlestepping check and
  * PT_PTRACED vs TIF_SYSCALL_TRACE for syscall tracing check
  */
-void syscall_trace(struct uml_pt_regs *regs, int entryexit)
+void syscall_trace_enter(struct pt_regs *regs)
 {
-        int is_singlestep = (current->ptrace & PT_DTRACE) && entryexit;
-        int tracesysgood;
-
-        if (!entryexit)
-                audit_syscall_entry(HOST_AUDIT_ARCH,
-                                    UPT_SYSCALL_NR(regs),
-                                    UPT_SYSCALL_ARG1(regs),
-                                    UPT_SYSCALL_ARG2(regs),
-                                    UPT_SYSCALL_ARG3(regs),
-                                    UPT_SYSCALL_ARG4(regs));
-        else
-                audit_syscall_exit(regs);
-
-        /* Fake a debug trap */
-        if (is_singlestep)
-                send_sigtrap(current, regs, 0);
+        audit_syscall_entry(HOST_AUDIT_ARCH,
+                            UPT_SYSCALL_NR(&regs->regs),
+                            UPT_SYSCALL_ARG1(&regs->regs),
+                            UPT_SYSCALL_ARG2(&regs->regs),
+                            UPT_SYSCALL_ARG3(&regs->regs),
+                            UPT_SYSCALL_ARG4(&regs->regs));
 
         if (!test_thread_flag(TIF_SYSCALL_TRACE))
                 return;
 
-        if (!(current->ptrace & PT_PTRACED))
-                return;
+        tracehook_report_syscall_entry(regs);
+}
 
-        /*
-         * the 0x80 provides a way for the tracing parent to distinguish
-         * between a syscall stop and SIGTRAP delivery
-         */
-        tracesysgood = (current->ptrace & PT_TRACESYSGOOD);
-        ptrace_notify(SIGTRAP | (tracesysgood ? 0x80 : 0));
+void syscall_trace_leave(struct pt_regs *regs)
+{
+        int ptraced = current->ptrace;
 
-        if (entryexit) /* force do_signal() --> is_syscall() */
-                set_thread_flag(TIF_SIGPENDING);
+        audit_syscall_exit(regs);
 
-        /*
-         * this isn't the same as continuing with a signal, but it will do
-         * for normal use.  strace only continues with a signal if the
-         * stopping signal is not SIGTRAP.  -brl
-         */
-        if (current->exit_code) {
-                send_sig(current->exit_code, current, 1);
-                current->exit_code = 0;
-        }
+        /* Fake a debug trap */
+        if (ptraced & PT_DTRACE)
+                send_sigtrap(current, &regs->regs, 0);
+
+        if (!test_thread_flag(TIF_SYSCALL_TRACE))
+                return;
+
+        tracehook_report_syscall_exit(regs, 0);
+        /* force do_signal() --> is_syscall() */
+        if (ptraced & PT_PTRACED)
+                set_thread_flag(TIF_SIGPENDING);
 }
diff --git a/arch/um/kernel/sigio.c b/arch/um/kernel/sigio.c
index 2a163925576..c88211139a5 100644
--- a/arch/um/kernel/sigio.c
+++ b/arch/um/kernel/sigio.c
@@ -25,8 +25,7 @@ int write_sigio_irq(int fd)
         int err;
 
         err = um_request_irq(SIGIO_WRITE_IRQ, fd, IRQ_READ, sigio_interrupt,
-                             IRQF_SAMPLE_RANDOM, "write sigio",
-                             NULL);
+                             0, "write sigio", NULL);
         if (err) {
                 printk(KERN_ERR "write_sigio_irq : um_request_irq failed, "
                        "err = %d\n", err);
diff --git a/arch/um/kernel/skas/syscall.c b/arch/um/kernel/skas/syscall.c
index 05fbeb480e0..86368a025a9 100644
--- a/arch/um/kernel/skas/syscall.c
+++ b/arch/um/kernel/skas/syscall.c
@@ -18,7 +18,7 @@ void handle_syscall(struct uml_pt_regs *r)
         long result;
         int syscall;
 
-        syscall_trace(r, 0);
+        syscall_trace_enter(regs);
 
         /*
          * This should go in the declaration of syscall, but when I do that,
@@ -34,7 +34,7 @@ void handle_syscall(struct uml_pt_regs *r)
                 result = -ENOSYS;
         else result = EXECUTE_SYSCALL(syscall, regs);
 
-        UPT_SET_SYSCALL_RETURN(r, result);
+        PT_REGS_SET_SYSCALL_RETURN(regs, result);
 
-        syscall_trace(r, 1);
+        syscall_trace_leave(regs);
 }
diff --git a/arch/um/kernel/time.c b/arch/um/kernel/time.c
index d1a23fb3190..5f76d4ba151 100644
--- a/arch/um/kernel/time.c
+++ b/arch/um/kernel/time.c
@@ -13,7 +13,7 @@
 #include "kern_util.h"
 #include "os.h"
 
-void timer_handler(int sig, struct uml_pt_regs *regs)
+void timer_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs)
 {
         unsigned long flags;
 
diff --git a/arch/um/kernel/trap.c b/arch/um/kernel/trap.c
index 3be60765c0e..0353b98ae35 100644
--- a/arch/um/kernel/trap.c
+++ b/arch/um/kernel/trap.c
@@ -172,7 +172,7 @@ void fatal_sigsegv(void)
         os_dump_core();
 }
 
-void segv_handler(int sig, struct uml_pt_regs *regs)
+void segv_handler(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs)
 {
         struct faultinfo * fi = UPT_FAULTINFO(regs);
 
@@ -258,8 +258,11 @@ unsigned long segv(struct faultinfo fi, unsigned long ip, int is_user,
         return 0;
 }
 
-void relay_signal(int sig, struct uml_pt_regs *regs)
+void relay_signal(int sig, struct siginfo *si, struct uml_pt_regs *regs)
 {
+        struct faultinfo *fi;
+        struct siginfo clean_si;
+
         if (!UPT_IS_USER(regs)) {
                 if (sig == SIGBUS)
                         printk(KERN_ERR "Bus error - the host /dev/shm or /tmp "
@@ -269,18 +272,40 @@ void relay_signal(int sig, struct uml_pt_regs *regs)
 
         arch_examine_signal(sig, regs);
 
-        current->thread.arch.faultinfo = *UPT_FAULTINFO(regs);
-        force_sig(sig, current);
+        memset(&clean_si, 0, sizeof(clean_si));
+        clean_si.si_signo = si->si_signo;
+        clean_si.si_errno = si->si_errno;
+        clean_si.si_code = si->si_code;
+        switch (sig) {
+        case SIGILL:
+        case SIGFPE:
+        case SIGSEGV:
+        case SIGBUS:
+        case SIGTRAP:
+                fi = UPT_FAULTINFO(regs);
+                clean_si.si_addr = (void __user *) FAULT_ADDRESS(*fi);
+                current->thread.arch.faultinfo = *fi;
+#ifdef __ARCH_SI_TRAPNO
+                clean_si.si_trapno = si->si_trapno;
+#endif
+                break;
+        default:
+                printk(KERN_ERR "Attempted to relay unknown signal %d (si_code = %d)\n",
+                        sig, si->si_code);
+        }
+
+        force_sig_info(sig, &clean_si, current);
 }
 
-void bus_handler(int sig, struct uml_pt_regs *regs)
+void bus_handler(int sig, struct siginfo *si, struct uml_pt_regs *regs)
 {
         if (current->thread.fault_catcher != NULL)
                 UML_LONGJMP(current->thread.fault_catcher, 1);
-        else relay_signal(sig, regs);
+        else
+                relay_signal(sig, si, regs);
 }
 
-void winch(int sig, struct uml_pt_regs *regs)
+void winch(int sig, struct siginfo *unused_si, struct uml_pt_regs *regs)
 {
         do_IRQ(WINCH_IRQ, regs);
 }
diff --git a/arch/um/os-Linux/internal.h b/arch/um/os-Linux/internal.h
index 2c3c3ecd8c0..0dc2c9f135f 100644
--- a/arch/um/os-Linux/internal.h
+++ b/arch/um/os-Linux/internal.h
@@ -1 +1 @@
-void alarm_handler(int, mcontext_t *);
+void alarm_handler(int sig, struct siginfo *unused_si, mcontext_t *mc);
diff --git a/arch/um/os-Linux/signal.c b/arch/um/os-Linux/signal.c
index 2d22f1fcd8e..6366ce904b9 100644
--- a/arch/um/os-Linux/signal.c
+++ b/arch/um/os-Linux/signal.c
@@ -13,8 +13,9 @@
 #include "kern_util.h"
 #include "os.h"
 #include "sysdep/mcontext.h"
+#include "internal.h"
 
-void (*sig_info[NSIG])(int, struct uml_pt_regs *) = {
+void (*sig_info[NSIG])(int, siginfo_t *, struct uml_pt_regs *) = {
         [SIGTRAP]       = relay_signal,
         [SIGFPE]        = relay_signal,
         [SIGILL]        = relay_signal,
@@ -24,7 +25,7 @@ void (*sig_info[NSIG])(int, struct uml_pt_regs *) = {
         [SIGIO]         = sigio_handler,
         [SIGVTALRM]     = timer_handler };
 
-static void sig_handler_common(int sig, mcontext_t *mc)
+static void sig_handler_common(int sig, siginfo_t *si, mcontext_t *mc)
 {
         struct uml_pt_regs r;
         int save_errno = errno;
@@ -40,7 +41,7 @@ static void sig_handler_common(int sig, mcontext_t *mc)
         if ((sig != SIGIO) && (sig != SIGWINCH) && (sig != SIGVTALRM))
                 unblock_signals();
 
-        (*sig_info[sig])(sig, &r);
+        (*sig_info[sig])(sig, si, &r);
 
         errno = save_errno;
 }
@@ -60,7 +61,7 @@ static void sig_handler_common(int sig, mcontext_t *mc)
 static int signals_enabled;
 static unsigned int signals_pending;
 
-void sig_handler(int sig, mcontext_t *mc)
+void sig_handler(int sig, siginfo_t *si, mcontext_t *mc)
 {
         int enabled;
 
@@ -72,7 +73,7 @@ void sig_handler(int sig, mcontext_t *mc)
 
         block_signals();
 
-        sig_handler_common(sig, mc);
+        sig_handler_common(sig, si, mc);
 
         set_signals(enabled);
 }
@@ -85,10 +86,10 @@ static void real_alarm_handler(mcontext_t *mc)
                 get_regs_from_mc(&regs, mc);
         regs.is_user = 0;
         unblock_signals();
-        timer_handler(SIGVTALRM, &regs);
+        timer_handler(SIGVTALRM, NULL, &regs);
 }
 
-void alarm_handler(int sig, mcontext_t *mc)
+void alarm_handler(int sig, struct siginfo *unused_si, mcontext_t *mc)
 {
         int enabled;
 
@@ -119,7 +120,7 @@ void set_sigstack(void *sig_stack, int size)
                 panic("enabling signal stack failed, errno = %d\n", errno);
 }
 
-static void (*handlers[_NSIG])(int sig, mcontext_t *mc) = {
+static void (*handlers[_NSIG])(int sig, siginfo_t *si, mcontext_t *mc) = {
         [SIGSEGV] = sig_handler,
         [SIGBUS] = sig_handler,
         [SIGILL] = sig_handler,
@@ -132,7 +133,7 @@ static void (*handlers[_NSIG])(int sig, mcontext_t *mc) = {
 };
 
 
-static void hard_handler(int sig, siginfo_t *info, void *p)
+static void hard_handler(int sig, siginfo_t *si, void *p)
 {
         struct ucontext *uc = p;
         mcontext_t *mc = &uc->uc_mcontext;
@@ -161,7 +162,7 @@ static void hard_handler(int sig, siginfo_t *info, void *p)
                 while ((sig = ffs(pending)) != 0){
                         sig--;
                         pending &= ~(1 << sig);
-                        (*handlers[sig])(sig, mc);
+                        (*handlers[sig])(sig, si, mc);
                 }
 
                 /*
@@ -273,9 +274,12 @@ void unblock_signals(void)
                  * Deal with SIGIO first because the alarm handler might
                  * schedule, leaving the pending SIGIO stranded until we come
                  * back here.
+                 *
+                 * SIGIO's handler doesn't use siginfo or mcontext,
+                 * so they can be NULL.
                  */
                 if (save_pending & SIGIO_MASK)
-                        sig_handler_common(SIGIO, NULL);
+                        sig_handler_common(SIGIO, NULL, NULL);
 
                 if (save_pending & SIGVTALRM_MASK)
                         real_alarm_handler(NULL);
diff --git a/arch/um/os-Linux/skas/process.c b/arch/um/os-Linux/skas/process.c
index cd65727854e..d93bb40499f 100644
--- a/arch/um/os-Linux/skas/process.c
+++ b/arch/um/os-Linux/skas/process.c
@@ -346,6 +346,10 @@ void userspace(struct uml_pt_regs *regs)
         int err, status, op, pid = userspace_pid[0];
         /* To prevent races if using_sysemu changes under us.*/
         int local_using_sysemu;
+        siginfo_t si;
+
+        /* Handle any immediate reschedules or signals */
+        interrupt_end();
 
         if (getitimer(ITIMER_VIRTUAL, &timer))
                 printk(UM_KERN_ERR "Failed to get itimer, errno = %d\n", errno);
@@ -404,13 +408,17 @@ void userspace(struct uml_pt_regs *regs)
 
                 if (WIFSTOPPED(status)) {
                         int sig = WSTOPSIG(status);
+
+                        ptrace(PTRACE_GETSIGINFO, pid, 0, &si);
+
                         switch (sig) {
                         case SIGSEGV:
                                 if (PTRACE_FULL_FAULTINFO ||
                                     !ptrace_faultinfo) {
                                         get_skas_faultinfo(pid,
                                                            &regs->faultinfo);
-                                        (*sig_info[SIGSEGV])(SIGSEGV, regs);
+                                        (*sig_info[SIGSEGV])(SIGSEGV, &si,
+                                                             regs);
                                 }
                                 else handle_segv(pid, regs);
                                 break;
@@ -418,14 +426,14 @@ void userspace(struct uml_pt_regs *regs)
                                 handle_trap(pid, regs, local_using_sysemu);
                                 break;
                         case SIGTRAP:
-                                relay_signal(SIGTRAP, regs);
+                                relay_signal(SIGTRAP, &si, regs);
                                 break;
                         case SIGVTALRM:
                                 now = os_nsecs();
                                 if (now < nsecs)
                                         break;
                                 block_signals();
-                                (*sig_info[sig])(sig, regs);
+                                (*sig_info[sig])(sig, &si, regs);
                                 unblock_signals();
                                 nsecs = timer.it_value.tv_sec *
                                         UM_NSEC_PER_SEC +
@@ -439,7 +447,7 @@ void userspace(struct uml_pt_regs *regs)
                         case SIGFPE:
                         case SIGWINCH:
                                 block_signals();
-                                (*sig_info[sig])(sig, regs);
+                                (*sig_info[sig])(sig, &si, regs);
                                 unblock_signals();
                                 break;
                         default:
diff --git a/arch/um/os-Linux/time.c b/arch/um/os-Linux/time.c
index 910499d76a6..0748fe0c8a7 100644
--- a/arch/um/os-Linux/time.c
+++ b/arch/um/os-Linux/time.c
@@ -87,7 +87,7 @@ static int after_sleep_interval(struct timespec *ts)
 
 static void deliver_alarm(void)
 {
-        alarm_handler(SIGVTALRM, NULL);
+        alarm_handler(SIGVTALRM, NULL, NULL);
 }
 
 static unsigned long long sleep_time(unsigned long long nsecs)
@@ -114,7 +114,7 @@ static void deliver_alarm(void)
         skew += this_tick - last_tick;
 
         while (skew >= one_tick) {
-                alarm_handler(SIGVTALRM, NULL);
+                alarm_handler(SIGVTALRM, NULL, NULL);
                 skew -= one_tick;
         }
 
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index 03c9ff808b5..b0a47433341 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -238,7 +238,6 @@ config I2C_BATTERY_BQ27200
 config I2C_EEPROM_AT24
         tristate "I2C EEPROMs AT24 support"
         select I2C_PUV3
-        select MISC_DEVICES
         select EEPROM_AT24
 
 config LCD_BACKLIGHT
diff --git a/arch/unicore32/kernel/pci.c b/arch/unicore32/kernel/pci.c
index 2fc2b1ba825..46cb6c9de6c 100644
--- a/arch/unicore32/kernel/pci.c
+++ b/arch/unicore32/kernel/pci.c
@@ -296,7 +296,7 @@ static int __init pci_common_init(void)
 }
 subsys_initcall(pci_common_init);
 
-char * __devinit pcibios_setup(char *str)
+char * __init pcibios_setup(char *str)
 {
         if (!strcmp(str, "debug")) {
                 debug_pci = 1;
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c70684f859e..8ec3a1aa4ab 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -70,6 +70,7 @@ config X86
         select HAVE_ARCH_JUMP_LABEL
         select HAVE_TEXT_POKE_SMP
         select HAVE_GENERIC_HARDIRQS
+        select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
         select SPARSE_IRQ
         select GENERIC_FIND_FIRST_BIT
         select GENERIC_IRQ_PROBE
@@ -84,6 +85,7 @@ config X86
         select GENERIC_IOMAP
         select DCACHE_WORD_ACCESS
         select GENERIC_SMP_IDLE_THREAD
+        select ARCH_WANT_IPC_PARSE_VERSION if X86_32
         select HAVE_ARCH_SECCOMP_FILTER
         select BUILDTIME_EXTABLE_SORT
         select GENERIC_CMOS_UPDATE
@@ -1525,7 +1527,7 @@ config SECCOMP
           If unsure, say Y. Only embedded should say N here.
 
 config CC_STACKPROTECTOR
-        bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
+        bool "Enable -fstack-protector buffer overflow detection"
         ---help---
           This option turns on the -fstack-protector GCC feature. This
           feature puts, at the beginning of functions, a canary value on
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index e46c2147397..b322f124ee3 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -129,6 +129,25 @@ config DOUBLEFAULT
           option saves about 4k and might cause you much additional grey
           hair.
 
+config DEBUG_TLBFLUSH
+        bool "Set upper limit of TLB entries to flush one-by-one"
+        depends on DEBUG_KERNEL && (X86_64 || X86_INVLPG)
+        ---help---
+
+        X86-only for now.
+
+        This option allows the user to tune the amount of TLB entries the
+        kernel flushes one-by-one instead of doing a full TLB flush. In
+        certain situations, the former is cheaper. This is controlled by the
+        tlb_flushall_shift knob under /sys/kernel/debug/x86. If you set it
+        to -1, the code flushes the whole TLB unconditionally. Otherwise,
+        for positive values of it, the kernel will use single TLB entry
+        invalidating instructions according to the following formula:
+
+        flush_entries <= active_tlb_entries / 2^tlb_flushall_shift
+
+        If in doubt, say "N".
+
 config IOMMU_DEBUG
         bool "Enable IOMMU debugging"
         depends on GART_IOMMU && DEBUG_KERNEL
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 1f252143455..682e9c210ba 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -27,6 +27,10 @@ ifeq ($(CONFIG_X86_32),y)
 
         KBUILD_CFLAGS += -msoft-float -mregparm=3 -freg-struct-return
 
+        # Never want PIC in a 32-bit kernel, prevent breakage with GCC built
+        # with nonstandard options
+        KBUILD_CFLAGS += -fno-pic
+
         # prevent gcc from keeping the stack 16 byte aligned
         KBUILD_CFLAGS += $(call cc-option,-mpreferred-stack-boundary=2)
 
@@ -49,6 +53,9 @@ else
         KBUILD_AFLAGS += -m64
         KBUILD_CFLAGS += -m64
 
+        # Use -mpreferred-stack-boundary=3 if supported.
+        KBUILD_CFLAGS += $(call cc-option,-mno-sse -mpreferred-stack-boundary=3)
+
         # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
         cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8)
         cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona)
diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile
index 5a747dd884d..f7535bedc33 100644
--- a/arch/x86/boot/Makefile
+++ b/arch/x86/boot/Makefile
@@ -57,7 +57,7 @@ KBUILD_CFLAGS	:= $(LINUXINCLUDE) -g -Os -D_SETUP -D__KERNEL__ \
                    -Wall -Wstrict-prototypes \
                    -march=i386 -mregparm=3 \
                    -include $(srctree)/$(src)/code16gcc.h \
-                   -fno-strict-aliasing -fomit-frame-pointer \
+                   -fno-strict-aliasing -fomit-frame-pointer -fno-pic \
                    $(call cc-option, -ffreestanding) \
                    $(call cc-option, -fno-toplevel-reorder,\
                         $(call cc-option, -fno-unit-at-a-time)) \
diff --git a/arch/x86/boot/compressed/cmdline.c b/arch/x86/boot/compressed/cmdline.c
index cb62f786990..10f6b1178c6 100644
--- a/arch/x86/boot/compressed/cmdline.c
+++ b/arch/x86/boot/compressed/cmdline.c
@@ -1,5 +1,7 @@
 #include "misc.h"
 
+#ifdef CONFIG_EARLY_PRINTK
+
 static unsigned long fs;
 static inline void set_fs(unsigned long seg)
 {
@@ -19,3 +21,5 @@ int cmdline_find_option_bool(const char *option)
 {
         return __cmdline_find_option_bool(real_mode->hdr.cmd_line_ptr, option);
 }
+
+#endif
diff --git a/arch/x86/boot/compressed/early_serial_console.c b/arch/x86/boot/compressed/early_serial_console.c
index 261e81fb958..d3d003cb548 100644
--- a/arch/x86/boot/compressed/early_serial_console.c
+++ b/arch/x86/boot/compressed/early_serial_console.c
@@ -1,5 +1,9 @@
 #include "misc.h"
 
+#ifdef CONFIG_EARLY_PRINTK
+
 int early_serial_base;
 
 #include "../early_serial_console.c"
+
+#endif
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 4e85f5f8583..b3e0227df2c 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -729,32 +729,68 @@ fail:
  * need to create one ourselves (usually the bootloader would create
  * one for us).
  */
-static efi_status_t make_boot_params(struct boot_params *boot_params,
-                                     efi_loaded_image_t *image,
-                                     void *handle)
+struct boot_params *make_boot_params(void *handle, efi_system_table_t *_table)
 {
-        struct efi_info *efi = &boot_params->efi_info;
-        struct apm_bios_info *bi = &boot_params->apm_bios_info;
-        struct sys_desc_table *sdt = &boot_params->sys_desc_table;
-        struct e820entry *e820_map = &boot_params->e820_map[0];
-        struct e820entry *prev = NULL;
-        struct setup_header *hdr = &boot_params->hdr;
-        unsigned long size, key, desc_size, _size;
-        efi_memory_desc_t *mem_map;
-        void *options = image->load_options;
-        u32 load_options_size = image->load_options_size / 2; /* ASCII */
+        struct boot_params *boot_params;
+        struct sys_desc_table *sdt;
+        struct apm_bios_info *bi;
+        struct setup_header *hdr;
+        struct efi_info *efi;
+        efi_loaded_image_t *image;
+        void *options;
+        u32 load_options_size;
+        efi_guid_t proto = LOADED_IMAGE_PROTOCOL_GUID;
         int options_size = 0;
         efi_status_t status;
-        __u32 desc_version;
         unsigned long cmdline;
-        u8 nr_entries;
         u16 *s2;
         u8 *s1;
         int i;
 
+        sys_table = _table;
+
+        /* Check if we were booted by the EFI firmware */
+        if (sys_table->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE)
+                return NULL;
+
+        status = efi_call_phys3(sys_table->boottime->handle_protocol,
+                                handle, &proto, (void *)&image);
+        if (status != EFI_SUCCESS) {
+                efi_printk("Failed to get handle for LOADED_IMAGE_PROTOCOL\n");
+                return NULL;
+        }
+
+        status = low_alloc(0x4000, 1, (unsigned long *)&boot_params);
+        if (status != EFI_SUCCESS) {
+                efi_printk("Failed to alloc lowmem for boot params\n");
+                return NULL;
+        }
+
+        memset(boot_params, 0x0, 0x4000);
+
+        hdr = &boot_params->hdr;
+        efi = &boot_params->efi_info;
+        bi = &boot_params->apm_bios_info;
+        sdt = &boot_params->sys_desc_table;
+
+        /* Copy the second sector to boot_params */
+        memcpy(&hdr->jump, image->image_base + 512, 512);
+
+        /*
+         * Fill out some of the header fields ourselves because the
+         * EFI firmware loader doesn't load the first sector.
+         */
+        hdr->root_flags = 1;
+        hdr->vid_mode = 0xffff;
+        hdr->boot_flag = 0xAA55;
+
+        hdr->code32_start = (__u64)(unsigned long)image->image_base;
+
         hdr->type_of_loader = 0x21;
 
         /* Convert unicode cmdline to ascii */
+        options = image->load_options;
+        load_options_size = image->load_options_size / 2; /* ASCII */
         cmdline = 0;
         s2 = (u16 *)options;
 
@@ -791,18 +827,36 @@ static efi_status_t make_boot_params(struct boot_params *boot_params,
         hdr->ramdisk_image = 0;
         hdr->ramdisk_size = 0;
 
-        status = handle_ramdisks(image, hdr);
-        if (status != EFI_SUCCESS)
-                goto free_cmdline;
-
-        setup_graphics(boot_params);
-
         /* Clear APM BIOS info */
         memset(bi, 0, sizeof(*bi));
 
         memset(sdt, 0, sizeof(*sdt));
 
-        memcpy(&efi->efi_loader_signature, EFI_LOADER_SIGNATURE, sizeof(__u32));
+        status = handle_ramdisks(image, hdr);
+        if (status != EFI_SUCCESS)
+                goto fail2;
+
+        return boot_params;
+fail2:
+        if (options_size)
+                low_free(options_size, hdr->cmd_line_ptr);
+fail:
+        low_free(0x4000, (unsigned long)boot_params);
+        return NULL;
+}
+
+static efi_status_t exit_boot(struct boot_params *boot_params,
+                              void *handle)
+{
+        struct efi_info *efi = &boot_params->efi_info;
+        struct e820entry *e820_map = &boot_params->e820_map[0];
+        struct e820entry *prev = NULL;
+        unsigned long size, key, desc_size, _size;
+        efi_memory_desc_t *mem_map;
+        efi_status_t status;
+        __u32 desc_version;
+        u8 nr_entries;
+        int i;
 
         size = sizeof(*mem_map) * 32;
 
@@ -811,7 +865,7 @@ again:
         _size = size;
         status = low_alloc(size, 1, (unsigned long *)&mem_map);
         if (status != EFI_SUCCESS)
-                goto free_cmdline;
+                return status;
 
         status = efi_call_phys5(sys_table->boottime->get_memory_map, &size,
                                 mem_map, &key, &desc_size, &desc_version);
@@ -823,6 +877,7 @@ again:
         if (status != EFI_SUCCESS)
                 goto free_mem_map;
 
+        memcpy(&efi->efi_loader_signature, EFI_LOADER_SIGNATURE, sizeof(__u32));
         efi->efi_systab = (unsigned long)sys_table;
         efi->efi_memdesc_size = desc_size;
         efi->efi_memdesc_version = desc_version;
@@ -906,61 +961,13 @@ again:
 
 free_mem_map:
         low_free(_size, (unsigned long)mem_map);
-free_cmdline:
-        if (options_size)
-                low_free(options_size, hdr->cmd_line_ptr);
-fail:
         return status;
 }
 
-/*
- * On success we return a pointer to a boot_params structure, and NULL
- * on failure.
- */
-struct boot_params *efi_main(void *handle, efi_system_table_t *_table)
+static efi_status_t relocate_kernel(struct setup_header *hdr)
 {
-        struct boot_params *boot_params;
         unsigned long start, nr_pages;
-        struct desc_ptr *gdt, *idt;
-        efi_loaded_image_t *image;
-        struct setup_header *hdr;
         efi_status_t status;
-        efi_guid_t proto = LOADED_IMAGE_PROTOCOL_GUID;
-        struct desc_struct *desc;
-
-        sys_table = _table;
-
-        /* Check if we were booted by the EFI firmware */
-        if (sys_table->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE)
-                goto fail;
-
-        status = efi_call_phys3(sys_table->boottime->handle_protocol,
-                                handle, &proto, (void *)&image);
-        if (status != EFI_SUCCESS) {
-                efi_printk("Failed to get handle for LOADED_IMAGE_PROTOCOL\n");
-                goto fail;
-        }
-
-        status = low_alloc(0x4000, 1, (unsigned long *)&boot_params);
-        if (status != EFI_SUCCESS) {
-                efi_printk("Failed to alloc lowmem for boot params\n");
-                goto fail;
-        }
-
-        memset(boot_params, 0x0, 0x4000);
-
-        hdr = &boot_params->hdr;
-
-        /* Copy the second sector to boot_params */
-        memcpy(&hdr->jump, image->image_base + 512, 512);
-
-        /*
-         * Fill out some of the header fields ourselves because the
-         * EFI firmware loader doesn't load the first sector.
-         */
-        hdr->root_flags = 1;
-        hdr->vid_mode = 0xffff;
-        hdr->boot_flag = 0xAA55;
 
         /*
          * The EFI firmware loader could have placed the kernel image
@@ -978,16 +985,40 @@ struct boot_params *efi_main(void *handle, efi_system_table_t *_table)
         if (status != EFI_SUCCESS) {
                 status = low_alloc(hdr->init_size, hdr->kernel_alignment,
                                    &start);
-                if (status != EFI_SUCCESS) {
+                if (status != EFI_SUCCESS)
                         efi_printk("Failed to alloc mem for kernel\n");
-                        goto fail;
-                }
         }
 
+        if (status == EFI_SUCCESS)
+                memcpy((void *)start, (void *)(unsigned long)hdr->code32_start,
+                       hdr->init_size);
+
+        hdr->pref_address = hdr->code32_start;
         hdr->code32_start = (__u32)start;
-        hdr->pref_address = (__u64)(unsigned long)image->image_base;
 
-        memcpy((void *)start, image->image_base, image->image_size);
+        return status;
+}
+
+/*
+ * On success we return a pointer to a boot_params structure, and NULL
+ * on failure.
+ */
+struct boot_params *efi_main(void *handle, efi_system_table_t *_table,
+                             struct boot_params *boot_params)
+{
+        struct desc_ptr *gdt, *idt;
+        efi_loaded_image_t *image;
+        struct setup_header *hdr = &boot_params->hdr;
+        efi_status_t status;
+        struct desc_struct *desc;
+
+        sys_table = _table;
+
+        /* Check if we were booted by the EFI firmware */
+        if (sys_table->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE)
+                goto fail;
+
+        setup_graphics(boot_params);
 
         status = efi_call_phys3(sys_table->boottime->allocate_pool,
                                 EFI_LOADER_DATA, sizeof(*gdt),
@@ -1015,7 +1046,18 @@ struct boot_params *efi_main(void *handle, efi_system_table_t *_table)
         idt->size = 0;
         idt->address = 0;
 
-        status = make_boot_params(boot_params, image, handle);
+        /*
+         * If the kernel isn't already loaded at the preferred load
+         * address, relocate it.
+         */
+        if (hdr->pref_address != hdr->code32_start) {
+                status = relocate_kernel(hdr);
+
+                if (status != EFI_SUCCESS)
+                        goto fail;
+        }
+
+        status = exit_boot(boot_params, handle);
         if (status != EFI_SUCCESS)
                 goto fail;
 
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index c85e3ac99bb..aa4aaf1b238 100644
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -42,6 +42,16 @@ ENTRY(startup_32)
          */
         add     $0x4, %esp
 
+        call    make_boot_params
+        cmpl    $0, %eax
+        je      1f
+        movl    0x4(%esp), %esi
+        movl    (%esp), %ecx
+        pushl   %eax
+        pushl   %esi
+        pushl   %ecx
+
+        .org 0x30,0x90
         call    efi_main
         cmpl    $0, %eax
         movl    %eax, %esi
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 87e03a13d8e..2c4b171eec3 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -209,6 +209,16 @@ ENTRY(startup_64)
         .org 0x210
         mov     %rcx, %rdi
         mov     %rdx, %rsi
+        pushq   %rdi
+        pushq   %rsi
+        call    make_boot_params
+        cmpq    $0,%rax
+        je      1f
+        mov     %rax, %rdx
+        popq    %rsi
+        popq    %rdi
+
+        .org 0x230,0x90
         call    efi_main
         movq    %rax,%rsi
         cmpq    $0,%rax
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 7116dcba0c9..88f7ff6da40 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -108,8 +108,6 @@ static void error(char *m);
  * This is set up by the setup-routine at boot-time
  */
 struct boot_params *real_mode;          /* Pointer to real-mode data */
-static int quiet;
-static int debug;
 
 void *memset(void *s, int c, size_t n);
 void *memcpy(void *dest, const void *src, size_t n);
@@ -170,15 +168,11 @@ static void serial_putchar(int ch)
         outb(ch, early_serial_base + TXR);
 }
 
-void __putstr(int error, const char *s)
+void __putstr(const char *s)
 {
         int x, y, pos;
         char c;
 
-#ifndef CONFIG_X86_VERBOSE_BOOTUP
-        if (!error)
-                return;
-#endif
         if (early_serial_base) {
                 const char *str = s;
                 while (*str) {
@@ -265,9 +259,9 @@ void *memcpy(void *dest, const void *src, size_t n)
 
 static void error(char *x)
 {
-        __putstr(1, "\n\n");
-        __putstr(1, x);
-        __putstr(1, "\n\n -- System halted");
+        error_putstr("\n\n");
+        error_putstr(x);
+        error_putstr("\n\n -- System halted");
 
         while (1)
                 asm("hlt");
@@ -294,8 +288,7 @@ static void parse_elf(void *output)
                 return;
         }
 
-        if (!quiet)
-                putstr("Parsing ELF... ");
+        debug_putstr("Parsing ELF... ");
 
         phdrs = malloc(sizeof(*phdrs) * ehdr.e_phnum);
         if (!phdrs)
@@ -332,11 +325,6 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
 {
         real_mode = rmode;
 
-        if (cmdline_find_option_bool("quiet"))
-                quiet = 1;
-        if (cmdline_find_option_bool("debug"))
-                debug = 1;
-
         if (real_mode->screen_info.orig_video_mode == 7) {
                 vidmem = (char *) 0xb0000;
                 vidport = 0x3b4;
@@ -349,8 +337,7 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
         cols = real_mode->screen_info.orig_video_cols;
 
         console_init();
-        if (debug)
-                putstr("early console in decompress_kernel\n");
+        debug_putstr("early console in decompress_kernel\n");
 
         free_mem_ptr     = heap;        /* Heap */
         free_mem_end_ptr = heap + BOOT_HEAP_SIZE;
@@ -369,11 +356,9 @@ asmlinkage void decompress_kernel(void *rmode, memptr heap,
                 error("Wrong destination address");
 #endif
 
-        if (!quiet)
-                putstr("\nDecompressing Linux... ");
+        debug_putstr("\nDecompressing Linux... ");
         decompress(input_data, input_len, NULL, NULL, output, NULL, error);
         parse_elf(output);
-        if (!quiet)
-                putstr("done.\nBooting the kernel.\n");
+        debug_putstr("done.\nBooting the kernel.\n");
         return;
 }
diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h
index 3f19c81a620..0e6dc0ee0ee 100644
--- a/arch/x86/boot/compressed/misc.h
+++ b/arch/x86/boot/compressed/misc.h
@@ -24,9 +24,21 @@
 
 /* misc.c */
 extern struct boot_params *real_mode;           /* Pointer to real-mode data */
-void __putstr(int error, const char *s);
-#define putstr(__x)  __putstr(0, __x)
-#define puts(__x)  __putstr(0, __x)
+void __putstr(const char *s);
+#define error_putstr(__x)  __putstr(__x)
+
+#ifdef CONFIG_X86_VERBOSE_BOOTUP
+
+#define debug_putstr(__x)  __putstr(__x)
+
+#else
+
+static inline void debug_putstr(const char *s)
+{ }
+
+#endif
+
+#ifdef CONFIG_EARLY_PRINTK
 
 /* cmdline.c */
 int cmdline_find_option(const char *option, char *buffer, int bufsize);
@@ -36,4 +48,13 @@ int cmdline_find_option_bool(const char *option);
 extern int early_serial_base;
 void console_init(void);
 
+#else
+
+/* early_serial_console.c */
+static const int early_serial_base;
+static inline void console_init(void)
+{ }
+
+#endif
+
 #endif
diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S
index efe5acfc79c..b4e15dd6786 100644
--- a/arch/x86/boot/header.S
+++ b/arch/x86/boot/header.S
@@ -283,7 +283,7 @@ _start:
         # Part 2 of the header, from the old setup.S
 
                 .ascii  "HdrS"          # header signature
-                .word   0x020a          # header version number (>= 0x0105)
+                .word   0x020b          # header version number (>= 0x0105)
                                         # or else old loadlin-1.5 will fail)
                 .globl realmode_swtch
 realmode_swtch: .word   0, 0            # default_switch, SETUPSEG
@@ -401,18 +401,13 @@ pref_address:		.quad LOAD_PHYSICAL_ADDR	# preferred load addr
 #define INIT_SIZE VO_INIT_SIZE
 #endif
 init_size:              .long INIT_SIZE         # kernel initialization size
+handover_offset:        .long 0x30              # offset to the handover
+                                                # protocol entry point
 
 # End of setup header #####################################################
 
         .section ".entrytext", "ax"
 start_of_setup:
-#ifdef SAFE_RESET_DISK_CONTROLLER
-# Reset the disk controller.
-        movw    $0x0000, %ax            # Reset disk controller
-        movb    $0x80, %dl              # All disks
-        int     $0x13
-#endif
-
 # Force %es = %ds
         movw    %ds, %ax
         movw    %ax, %es
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile
index e191ac048b5..e908e5de82d 100644
--- a/arch/x86/crypto/Makefile
+++ b/arch/x86/crypto/Makefile
@@ -2,6 +2,9 @@
 # Arch-specific CryptoAPI modules.
 #
 
+obj-$(CONFIG_CRYPTO_ABLK_HELPER_X86) += ablk_helper.o
+obj-$(CONFIG_CRYPTO_GLUE_HELPER_X86) += glue_helper.o
+
 obj-$(CONFIG_CRYPTO_AES_586) += aes-i586.o
 obj-$(CONFIG_CRYPTO_TWOFISH_586) += twofish-i586.o
 obj-$(CONFIG_CRYPTO_SALSA20_586) += salsa20-i586.o
@@ -12,8 +15,10 @@ obj-$(CONFIG_CRYPTO_CAMELLIA_X86_64) += camellia-x86_64.o
 obj-$(CONFIG_CRYPTO_BLOWFISH_X86_64) += blowfish-x86_64.o
 obj-$(CONFIG_CRYPTO_TWOFISH_X86_64) += twofish-x86_64.o
 obj-$(CONFIG_CRYPTO_TWOFISH_X86_64_3WAY) += twofish-x86_64-3way.o
+obj-$(CONFIG_CRYPTO_TWOFISH_AVX_X86_64) += twofish-avx-x86_64.o
 obj-$(CONFIG_CRYPTO_SALSA20_X86_64) += salsa20-x86_64.o
 obj-$(CONFIG_CRYPTO_SERPENT_SSE2_X86_64) += serpent-sse2-x86_64.o
+obj-$(CONFIG_CRYPTO_SERPENT_AVX_X86_64) += serpent-avx-x86_64.o
 obj-$(CONFIG_CRYPTO_AES_NI_INTEL) += aesni-intel.o
 obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o
 
@@ -30,16 +35,11 @@ camellia-x86_64-y := camellia-x86_64-asm_64.o camellia_glue.o
 blowfish-x86_64-y := blowfish-x86_64-asm_64.o blowfish_glue.o
 twofish-x86_64-y := twofish-x86_64-asm_64.o twofish_glue.o
 twofish-x86_64-3way-y := twofish-x86_64-asm_64-3way.o twofish_glue_3way.o
+twofish-avx-x86_64-y := twofish-avx-x86_64-asm_64.o twofish_avx_glue.o
 salsa20-x86_64-y := salsa20-x86_64-asm_64.o salsa20_glue.o
 serpent-sse2-x86_64-y := serpent-sse2-x86_64-asm_64.o serpent_sse2_glue.o
+serpent-avx-x86_64-y := serpent-avx-x86_64-asm_64.o serpent_avx_glue.o
 
 aesni-intel-y := aesni-intel_asm.o aesni-intel_glue.o fpu.o
-
 ghash-clmulni-intel-y := ghash-clmulni-intel_asm.o ghash-clmulni-intel_glue.o
-
-# enable AVX support only when $(AS) can actually assemble the instructions
-ifeq ($(call as-instr,vpxor %xmm0$(comma)%xmm1$(comma)%xmm2,yes,no),yes)
-AFLAGS_sha1_ssse3_asm.o += -DSHA1_ENABLE_AVX_SUPPORT
-CFLAGS_sha1_ssse3_glue.o += -DSHA1_ENABLE_AVX_SUPPORT
-endif
 sha1-ssse3-y := sha1_ssse3_asm.o sha1_ssse3_glue.o
diff --git a/arch/x86/crypto/ablk_helper.c b/arch/x86/crypto/ablk_helper.c
new file mode 100644
index 00000000000..43282fe04a8
--- /dev/null
+++ b/arch/x86/crypto/ablk_helper.c
@@ -0,0 +1,149 @@
+/*
+ * Shared async block cipher helpers
+ *
+ * Copyright (c) 2012 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ *
+ * Based on aesni-intel_glue.c by:
+ *  Copyright (C) 2008, Intel Corp.
+ *    Author: Huang Ying <ying.huang@intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
+ * USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/crypto.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <crypto/algapi.h>
+#include <crypto/cryptd.h>
+#include <asm/i387.h>
+#include <asm/crypto/ablk_helper.h>
+
+int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key,
+                 unsigned int key_len)
+{
+        struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm);
+        struct crypto_ablkcipher *child = &ctx->cryptd_tfm->base;
+        int err;
+
+        crypto_ablkcipher_clear_flags(child, CRYPTO_TFM_REQ_MASK);
+        crypto_ablkcipher_set_flags(child, crypto_ablkcipher_get_flags(tfm)
+                                    & CRYPTO_TFM_REQ_MASK);
+        err = crypto_ablkcipher_setkey(child, key, key_len);
+        crypto_ablkcipher_set_flags(tfm, crypto_ablkcipher_get_flags(child)
+                                    & CRYPTO_TFM_RES_MASK);
+        return err;
+}
+EXPORT_SYMBOL_GPL(ablk_set_key);
+
+int __ablk_encrypt(struct ablkcipher_request *req)
+{
+        struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
+        struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm);
+        struct blkcipher_desc desc;
+
+        desc.tfm = cryptd_ablkcipher_child(ctx->cryptd_tfm);
+        desc.info = req->info;
+        desc.flags = 0;
+
+        return crypto_blkcipher_crt(desc.tfm)->encrypt(
+                &desc, req->dst, req->src, req->nbytes);
+}
+EXPORT_SYMBOL_GPL(__ablk_encrypt);
+
+int ablk_encrypt(struct ablkcipher_request *req)
+{
+        struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
+        struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm);
+
+        if (!irq_fpu_usable()) {
+                struct ablkcipher_request *cryptd_req =
+                        ablkcipher_request_ctx(req);
+
+                memcpy(cryptd_req, req, sizeof(*req));
+                ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
+
+                return crypto_ablkcipher_encrypt(cryptd_req);
+        } else {
+                return __ablk_encrypt(req);
+        }
+}
+EXPORT_SYMBOL_GPL(ablk_encrypt);
+
+int ablk_decrypt(struct ablkcipher_request *req)
+{
+        struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
+        struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm);
+
+        if (!irq_fpu_usable()) {
+                struct ablkcipher_request *cryptd_req =
+                        ablkcipher_request_ctx(req);
+
+                memcpy(cryptd_req, req, sizeof(*req));
+                ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
+
+                return crypto_ablkcipher_decrypt(cryptd_req);
+        } else {
+                struct blkcipher_desc desc;
+
+                desc.tfm = cryptd_ablkcipher_child(ctx->cryptd_tfm);
+                desc.info = req->info;
+                desc.flags = 0;
+
+                return crypto_blkcipher_crt(desc.tfm)->decrypt(
+                        &desc, req->dst, req->src, req->nbytes);
+        }
+}
+EXPORT_SYMBOL_GPL(ablk_decrypt);
+
+void ablk_exit(struct crypto_tfm *tfm)
+{
+        struct async_helper_ctx *ctx = crypto_tfm_ctx(tfm);
+
+        cryptd_free_ablkcipher(ctx->cryptd_tfm);
+}
+EXPORT_SYMBOL_GPL(ablk_exit);
+
+int ablk_init_common(struct crypto_tfm *tfm, const char *drv_name)
+{
+        struct async_helper_ctx *ctx = crypto_tfm_ctx(tfm);
+        struct cryptd_ablkcipher *cryptd_tfm;
+
+        cryptd_tfm = cryptd_alloc_ablkcipher(drv_name, 0, 0);
+        if (IS_ERR(cryptd_tfm))
+                return PTR_ERR(cryptd_tfm);
+
+        ctx->cryptd_tfm = cryptd_tfm;
+        tfm->crt_ablkcipher.reqsize = sizeof(struct ablkcipher_request) +
+                crypto_ablkcipher_reqsize(&cryptd_tfm->base);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(ablk_init_common);
+
+int ablk_init(struct crypto_tfm *tfm)
+{
+        char drv_name[CRYPTO_MAX_ALG_NAME];
+
+        snprintf(drv_name, sizeof(drv_name), "__driver-%s",
+                                        crypto_tfm_alg_driver_name(tfm));
+
+        return ablk_init_common(tfm, drv_name);
+}
+EXPORT_SYMBOL_GPL(ablk_init);
+
+MODULE_LICENSE("GPL");
diff --git a/arch/x86/crypto/aes_glue.c b/arch/x86/crypto/aes_glue.c
index 8efcf42a9d7..59b37deb8c8 100644
--- a/arch/x86/crypto/aes_glue.c
+++ b/arch/x86/crypto/aes_glue.c
@@ -5,7 +5,7 @@
 
 #include <linux/module.h>
 #include <crypto/aes.h>
-#include <asm/aes.h>
+#include <asm/crypto/aes.h>
 
 asmlinkage void aes_enc_blk(struct crypto_aes_ctx *ctx, u8 *out, const u8 *in);
 asmlinkage void aes_dec_blk(struct crypto_aes_ctx *ctx, u8 *out, const u8 *in);
diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index ac7f5cd019e..34fdcff4d2c 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -30,7 +30,8 @@
 #include <crypto/ctr.h>
 #include <asm/cpu_device_id.h>
 #include <asm/i387.h>
-#include <asm/aes.h>
+#include <asm/crypto/aes.h>
+#include <asm/crypto/ablk_helper.h>
 #include <crypto/scatterwalk.h>
 #include <crypto/internal/aead.h>
 #include <linux/workqueue.h>
@@ -52,10 +53,6 @@
 #define HAS_XTS
 #endif
 
-struct async_aes_ctx {
-        struct cryptd_ablkcipher *cryptd_tfm;
-};
-
 /* This data is stored at the end of the crypto_tfm struct.
  * It's a type of per "session" data storage location.
  * This needs to be 16 byte aligned.
@@ -377,87 +374,6 @@ static int ctr_crypt(struct blkcipher_desc *desc,
 }
 #endif
 
-static int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key,
-                        unsigned int key_len)
-{
-        struct async_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-        struct crypto_ablkcipher *child = &ctx->cryptd_tfm->base;
-        int err;
-
-        crypto_ablkcipher_clear_flags(child, CRYPTO_TFM_REQ_MASK);
-        crypto_ablkcipher_set_flags(child, crypto_ablkcipher_get_flags(tfm)
-                                    & CRYPTO_TFM_REQ_MASK);
-        err = crypto_ablkcipher_setkey(child, key, key_len);
-        crypto_ablkcipher_set_flags(tfm, crypto_ablkcipher_get_flags(child)
-                                    & CRYPTO_TFM_RES_MASK);
-        return err;
-}
-
-static int ablk_encrypt(struct ablkcipher_request *req)
-{
-        struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
-        struct async_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-
-        if (!irq_fpu_usable()) {
-                struct ablkcipher_request *cryptd_req =
-                        ablkcipher_request_ctx(req);
-                memcpy(cryptd_req, req, sizeof(*req));
-                ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
-                return crypto_ablkcipher_encrypt(cryptd_req);
-        } else {
-                struct blkcipher_desc desc;
-                desc.tfm = cryptd_ablkcipher_child(ctx->cryptd_tfm);
-                desc.info = req->info;
-                desc.flags = 0;
-                return crypto_blkcipher_crt(desc.tfm)->encrypt(
-                        &desc, req->dst, req->src, req->nbytes);
-        }
-}
-
-static int ablk_decrypt(struct ablkcipher_request *req)
-{
-        struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
-        struct async_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-
-        if (!irq_fpu_usable()) {
-                struct ablkcipher_request *cryptd_req =
-                        ablkcipher_request_ctx(req);
-                memcpy(cryptd_req, req, sizeof(*req));
-                ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
-                return crypto_ablkcipher_decrypt(cryptd_req);
-        } else {
-                struct blkcipher_desc desc;
-                desc.tfm = cryptd_ablkcipher_child(ctx->cryptd_tfm);
-                desc.info = req->info;
-                desc.flags = 0;
-                return crypto_blkcipher_crt(desc.tfm)->decrypt(
-                        &desc, req->dst, req->src, req->nbytes);
-        }
-}
-
-static void ablk_exit(struct crypto_tfm *tfm)
-{
-        struct async_aes_ctx *ctx = crypto_tfm_ctx(tfm);
-
-        cryptd_free_ablkcipher(ctx->cryptd_tfm);
-}
-
-static int ablk_init_common(struct crypto_tfm *tfm, const char *drv_name)
-{
-        struct async_aes_ctx *ctx = crypto_tfm_ctx(tfm);
-        struct cryptd_ablkcipher *cryptd_tfm;
-
-        cryptd_tfm = cryptd_alloc_ablkcipher(drv_name, 0, 0);
-        if (IS_ERR(cryptd_tfm))
-                return PTR_ERR(cryptd_tfm);
-
-        ctx->cryptd_tfm = cryptd_tfm;
-        tfm->crt_ablkcipher.reqsize = sizeof(struct ablkcipher_request) +
-                crypto_ablkcipher_reqsize(&cryptd_tfm->base);
-
-        return 0;
-}
-
 static int ablk_ecb_init(struct crypto_tfm *tfm)
 {
         return ablk_init_common(tfm, "__driver-ecb-aes-aesni");
@@ -613,7 +529,7 @@ static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key,
         struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm);
         struct aesni_rfc4106_gcm_ctx *child_ctx =
                                  aesni_rfc4106_gcm_ctx_get(cryptd_child);
-        u8 *new_key_mem = NULL;
+        u8 *new_key_align, *new_key_mem = NULL;
 
         if (key_len < 4) {
                 crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
@@ -637,9 +553,9 @@ static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key,
                 if (!new_key_mem)
                         return -ENOMEM;
 
-                new_key_mem = PTR_ALIGN(new_key_mem, AESNI_ALIGN);
-                memcpy(new_key_mem, key, key_len);
-                key = new_key_mem;
+                new_key_align = PTR_ALIGN(new_key_mem, AESNI_ALIGN);
+                memcpy(new_key_align, key, key_len);
+                key = new_key_align;
         }
 
         if (!irq_fpu_usable())
@@ -968,7 +884,7 @@ static struct crypto_alg aesni_algs[] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = AES_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_aes_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
@@ -989,7 +905,7 @@ static struct crypto_alg aesni_algs[] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = AES_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_aes_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
@@ -1033,7 +949,7 @@ static struct crypto_alg aesni_algs[] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = 1,
-        .cra_ctxsize            = sizeof(struct async_aes_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
@@ -1098,7 +1014,7 @@ static struct crypto_alg aesni_algs[] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = 1,
-        .cra_ctxsize            = sizeof(struct async_aes_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
@@ -1126,7 +1042,7 @@ static struct crypto_alg aesni_algs[] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = AES_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_aes_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
@@ -1150,7 +1066,7 @@ static struct crypto_alg aesni_algs[] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = AES_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_aes_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
@@ -1174,7 +1090,7 @@ static struct crypto_alg aesni_algs[] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = AES_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_aes_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
diff --git a/arch/x86/crypto/camellia_glue.c b/arch/x86/crypto/camellia_glue.c
index 3306dc0b139..eeb2b3b743e 100644
--- a/arch/x86/crypto/camellia_glue.c
+++ b/arch/x86/crypto/camellia_glue.c
@@ -5,10 +5,6 @@
  *
  * Camellia parts based on code by:
  *  Copyright (C) 2006 NTT (Nippon Telegraph and Telephone Corporation)
- * CBC & ECB parts based on code (crypto/cbc.c,ecb.c) by:
- *   Copyright (c) 2006 Herbert Xu <herbert@gondor.apana.org.au>
- * CTR part based on code (crypto/ctr.c) by:
- *   (C) Copyright IBM Corp. 2007 - Joy Latten <latten@us.ibm.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -34,9 +30,9 @@
 #include <linux/module.h>
 #include <linux/types.h>
 #include <crypto/algapi.h>
-#include <crypto/b128ops.h>
 #include <crypto/lrw.h>
 #include <crypto/xts.h>
+#include <asm/crypto/glue_helper.h>
 
 #define CAMELLIA_MIN_KEY_SIZE   16
 #define CAMELLIA_MAX_KEY_SIZE   32
@@ -1312,307 +1308,128 @@ static int camellia_setkey(struct crypto_tfm *tfm, const u8 *in_key,
                                  &tfm->crt_flags);
 }
 
-static int ecb_crypt(struct blkcipher_desc *desc, struct blkcipher_walk *walk,
-                     void (*fn)(struct camellia_ctx *, u8 *, const u8 *),
-                     void (*fn_2way)(struct camellia_ctx *, u8 *, const u8 *))
+static void camellia_decrypt_cbc_2way(void *ctx, u128 *dst, const u128 *src)
 {
-        struct camellia_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        unsigned int bsize = CAMELLIA_BLOCK_SIZE;
-        unsigned int nbytes;
-        int err;
-
-        err = blkcipher_walk_virt(desc, walk);
-
-        while ((nbytes = walk->nbytes)) {
-                u8 *wsrc = walk->src.virt.addr;
-                u8 *wdst = walk->dst.virt.addr;
-
-                /* Process two block batch */
-                if (nbytes >= bsize * 2) {
-                        do {
-                                fn_2way(ctx, wdst, wsrc);
-
-                                wsrc += bsize * 2;
-                                wdst += bsize * 2;
-                                nbytes -= bsize * 2;
-                        } while (nbytes >= bsize * 2);
-
-                        if (nbytes < bsize)
-                                goto done;
-                }
-
-                /* Handle leftovers */
-                do {
-                        fn(ctx, wdst, wsrc);
-
-                        wsrc += bsize;
-                        wdst += bsize;
-                        nbytes -= bsize;
-                } while (nbytes >= bsize);
-
-done:
-                err = blkcipher_walk_done(desc, walk, nbytes);
-        }
-
-        return err;
-}
-
-static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct blkcipher_walk walk;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return ecb_crypt(desc, &walk, camellia_enc_blk, camellia_enc_blk_2way);
-}
+        u128 iv = *src;
 
-static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct blkcipher_walk walk;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return ecb_crypt(desc, &walk, camellia_dec_blk, camellia_dec_blk_2way);
-}
+        camellia_dec_blk_2way(ctx, (u8 *)dst, (u8 *)src);
 
-static unsigned int __cbc_encrypt(struct blkcipher_desc *desc,
-                                  struct blkcipher_walk *walk)
-{
-        struct camellia_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        unsigned int bsize = CAMELLIA_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u128 *src = (u128 *)walk->src.virt.addr;
-        u128 *dst = (u128 *)walk->dst.virt.addr;
-        u128 *iv = (u128 *)walk->iv;
-
-        do {
-                u128_xor(dst, src, iv);
-                camellia_enc_blk(ctx, (u8 *)dst, (u8 *)dst);
-                iv = dst;
-
-                src += 1;
-                dst += 1;
-                nbytes -= bsize;
-        } while (nbytes >= bsize);
-
-        u128_xor((u128 *)walk->iv, (u128 *)walk->iv, iv);
-        return nbytes;
+        u128_xor(&dst[1], &dst[1], &iv);
 }
 
-static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
+static void camellia_crypt_ctr(void *ctx, u128 *dst, const u128 *src, u128 *iv)
 {
-        struct blkcipher_walk walk;
-        int err;
+        be128 ctrblk;
 
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt(desc, &walk);
+        if (dst != src)
+                *dst = *src;
 
-        while ((nbytes = walk.nbytes)) {
-                nbytes = __cbc_encrypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
+        u128_to_be128(&ctrblk, iv);
+        u128_inc(iv);
 
-        return err;
+        camellia_enc_blk_xor(ctx, (u8 *)dst, (u8 *)&ctrblk);
 }
 
-static unsigned int __cbc_decrypt(struct blkcipher_desc *desc,
-                                  struct blkcipher_walk *walk)
+static void camellia_crypt_ctr_2way(void *ctx, u128 *dst, const u128 *src,
+                                    u128 *iv)
 {
-        struct camellia_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        unsigned int bsize = CAMELLIA_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u128 *src = (u128 *)walk->src.virt.addr;
-        u128 *dst = (u128 *)walk->dst.virt.addr;
-        u128 ivs[2 - 1];
-        u128 last_iv;
+        be128 ctrblks[2];
 
-        /* Start of the last block. */
-        src += nbytes / bsize - 1;
-        dst += nbytes / bsize - 1;
-
-        last_iv = *src;
-
-        /* Process two block batch */
-        if (nbytes >= bsize * 2) {
-                do {
-                        nbytes -= bsize * (2 - 1);
-                        src -= 2 - 1;
-                        dst -= 2 - 1;
-
-                        ivs[0] = src[0];
-
-                        camellia_dec_blk_2way(ctx, (u8 *)dst, (u8 *)src);
-
-                        u128_xor(dst + 1, dst + 1, ivs + 0);
-
-                        nbytes -= bsize;
-                        if (nbytes < bsize)
-                                goto done;
-
-                        u128_xor(dst, dst, src - 1);
-                        src -= 1;
-                        dst -= 1;
-                } while (nbytes >= bsize * 2);
-
-                if (nbytes < bsize)
-                        goto done;
+        if (dst != src) {
+                dst[0] = src[0];
+                dst[1] = src[1];
         }
 
-        /* Handle leftovers */
-        for (;;) {
-                camellia_dec_blk(ctx, (u8 *)dst, (u8 *)src);
-
-                nbytes -= bsize;
-                if (nbytes < bsize)
-                        break;
+        u128_to_be128(&ctrblks[0], iv);
+        u128_inc(iv);
+        u128_to_be128(&ctrblks[1], iv);
+        u128_inc(iv);
 
-                u128_xor(dst, dst, src - 1);
-                src -= 1;
-                dst -= 1;
-        }
-
-done:
-        u128_xor(dst, dst, (u128 *)walk->iv);
-        *(u128 *)walk->iv = last_iv;
-
-        return nbytes;
+        camellia_enc_blk_xor_2way(ctx, (u8 *)dst, (u8 *)ctrblks);
 }
 
-static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct blkcipher_walk walk;
-        int err;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt(desc, &walk);
+static const struct common_glue_ctx camellia_enc = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = -1,
+
+        .funcs = { {
+                .num_blocks = 2,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_enc_blk_2way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_enc_blk) }
+        } }
+};
 
-        while ((nbytes = walk.nbytes)) {
-                nbytes = __cbc_decrypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
+static const struct common_glue_ctx camellia_ctr = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = -1,
+
+        .funcs = { {
+                .num_blocks = 2,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_crypt_ctr_2way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(camellia_crypt_ctr) }
+        } }
+};
 
-        return err;
-}
+static const struct common_glue_ctx camellia_dec = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = -1,
+
+        .funcs = { {
+                .num_blocks = 2,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_dec_blk_2way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(camellia_dec_blk) }
+        } }
+};
 
-static inline void u128_to_be128(be128 *dst, const u128 *src)
-{
-        dst->a = cpu_to_be64(src->a);
-        dst->b = cpu_to_be64(src->b);
-}
+static const struct common_glue_ctx camellia_dec_cbc = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = -1,
+
+        .funcs = { {
+                .num_blocks = 2,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(camellia_decrypt_cbc_2way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(camellia_dec_blk) }
+        } }
+};
 
-static inline void be128_to_u128(u128 *dst, const be128 *src)
+static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        dst->a = be64_to_cpu(src->a);
-        dst->b = be64_to_cpu(src->b);
+        return glue_ecb_crypt_128bit(&camellia_enc, desc, dst, src, nbytes);
 }
 
-static inline void u128_inc(u128 *i)
+static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        i->b++;
-        if (!i->b)
-                i->a++;
+        return glue_ecb_crypt_128bit(&camellia_dec, desc, dst, src, nbytes);
 }
 
-static void ctr_crypt_final(struct blkcipher_desc *desc,
-                            struct blkcipher_walk *walk)
+static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        struct camellia_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        u8 keystream[CAMELLIA_BLOCK_SIZE];
-        u8 *src = walk->src.virt.addr;
-        u8 *dst = walk->dst.virt.addr;
-        unsigned int nbytes = walk->nbytes;
-        u128 ctrblk;
-
-        memcpy(keystream, src, nbytes);
-        camellia_enc_blk_xor(ctx, keystream, walk->iv);
-        memcpy(dst, keystream, nbytes);
-
-        be128_to_u128(&ctrblk, (be128 *)walk->iv);
-        u128_inc(&ctrblk);
-        u128_to_be128((be128 *)walk->iv, &ctrblk);
+        return glue_cbc_encrypt_128bit(GLUE_FUNC_CAST(camellia_enc_blk), desc,
+                                       dst, src, nbytes);
 }
 
-static unsigned int __ctr_crypt(struct blkcipher_desc *desc,
-                                struct blkcipher_walk *walk)
+static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        struct camellia_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        unsigned int bsize = CAMELLIA_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u128 *src = (u128 *)walk->src.virt.addr;
-        u128 *dst = (u128 *)walk->dst.virt.addr;
-        u128 ctrblk;
-        be128 ctrblocks[2];
-
-        be128_to_u128(&ctrblk, (be128 *)walk->iv);
-
-        /* Process two block batch */
-        if (nbytes >= bsize * 2) {
-                do {
-                        if (dst != src) {
-                                dst[0] = src[0];
-                                dst[1] = src[1];
-                        }
-
-                        /* create ctrblks for parallel encrypt */
-                        u128_to_be128(&ctrblocks[0], &ctrblk);
-                        u128_inc(&ctrblk);
-                        u128_to_be128(&ctrblocks[1], &ctrblk);
-                        u128_inc(&ctrblk);
-
-                        camellia_enc_blk_xor_2way(ctx, (u8 *)dst,
-                                                 (u8 *)ctrblocks);
-
-                        src += 2;
-                        dst += 2;
-                        nbytes -= bsize * 2;
-                } while (nbytes >= bsize * 2);
-
-                if (nbytes < bsize)
-                        goto done;
-        }
-
-        /* Handle leftovers */
-        do {
-                if (dst != src)
-                        *dst = *src;
-
-                u128_to_be128(&ctrblocks[0], &ctrblk);
-                u128_inc(&ctrblk);
-
-                camellia_enc_blk_xor(ctx, (u8 *)dst, (u8 *)ctrblocks);
-
-                src += 1;
-                dst += 1;
-                nbytes -= bsize;
-        } while (nbytes >= bsize);
-
-done:
-        u128_to_be128((be128 *)walk->iv, &ctrblk);
-        return nbytes;
+        return glue_cbc_decrypt_128bit(&camellia_dec_cbc, desc, dst, src,
+                                       nbytes);
 }
 
 static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                      struct scatterlist *src, unsigned int nbytes)
 {
-        struct blkcipher_walk walk;
-        int err;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt_block(desc, &walk, CAMELLIA_BLOCK_SIZE);
-
-        while ((nbytes = walk.nbytes) >= CAMELLIA_BLOCK_SIZE) {
-                nbytes = __ctr_crypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
-
-        if (walk.nbytes) {
-                ctr_crypt_final(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, 0);
-        }
-
-        return err;
+        return glue_ctr_crypt_128bit(&camellia_ctr, desc, dst, src, nbytes);
 }
 
 static void encrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
diff --git a/arch/x86/crypto/glue_helper.c b/arch/x86/crypto/glue_helper.c
new file mode 100644
index 00000000000..4854f0f31e4
--- /dev/null
+++ b/arch/x86/crypto/glue_helper.c
@@ -0,0 +1,307 @@
+/*
+ * Shared glue code for 128bit block ciphers
+ *
+ * Copyright (c) 2012 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ *
+ * CBC & ECB parts based on code (crypto/cbc.c,ecb.c) by:
+ *   Copyright (c) 2006 Herbert Xu <herbert@gondor.apana.org.au>
+ * CTR part based on code (crypto/ctr.c) by:
+ *   (C) Copyright IBM Corp. 2007 - Joy Latten <latten@us.ibm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
+ * USA
+ *
+ */
+
+#include <linux/module.h>
+#include <crypto/b128ops.h>
+#include <crypto/lrw.h>
+#include <crypto/xts.h>
+#include <asm/crypto/glue_helper.h>
+#include <crypto/scatterwalk.h>
+
+static int __glue_ecb_crypt_128bit(const struct common_glue_ctx *gctx,
+                                   struct blkcipher_desc *desc,
+                                   struct blkcipher_walk *walk)
+{
+        void *ctx = crypto_blkcipher_ctx(desc->tfm);
+        const unsigned int bsize = 128 / 8;
+        unsigned int nbytes, i, func_bytes;
+        bool fpu_enabled = false;
+        int err;
+
+        err = blkcipher_walk_virt(desc, walk);
+
+        while ((nbytes = walk->nbytes)) {
+                u8 *wsrc = walk->src.virt.addr;
+                u8 *wdst = walk->dst.virt.addr;
+
+                fpu_enabled = glue_fpu_begin(bsize, gctx->fpu_blocks_limit,
+                                             desc, fpu_enabled, nbytes);
+
+                for (i = 0; i < gctx->num_funcs; i++) {
+                        func_bytes = bsize * gctx->funcs[i].num_blocks;
+
+                        /* Process multi-block batch */
+                        if (nbytes >= func_bytes) {
+                                do {
+                                        gctx->funcs[i].fn_u.ecb(ctx, wdst,
+                                                                wsrc);
+
+                                        wsrc += func_bytes;
+                                        wdst += func_bytes;
+                                        nbytes -= func_bytes;
+                                } while (nbytes >= func_bytes);
+
+                                if (nbytes < bsize)
+                                        goto done;
+                        }
+                }
+
+done:
+                err = blkcipher_walk_done(desc, walk, nbytes);
+        }
+
+        glue_fpu_end(fpu_enabled);
+        return err;
+}
+
+int glue_ecb_crypt_128bit(const struct common_glue_ctx *gctx,
+                          struct blkcipher_desc *desc, struct scatterlist *dst,
+                          struct scatterlist *src, unsigned int nbytes)
+{
+        struct blkcipher_walk walk;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        return __glue_ecb_crypt_128bit(gctx, desc, &walk);
+}
+EXPORT_SYMBOL_GPL(glue_ecb_crypt_128bit);
+
+static unsigned int __glue_cbc_encrypt_128bit(const common_glue_func_t fn,
+                                              struct blkcipher_desc *desc,
+                                              struct blkcipher_walk *walk)
+{
+        void *ctx = crypto_blkcipher_ctx(desc->tfm);
+        const unsigned int bsize = 128 / 8;
+        unsigned int nbytes = walk->nbytes;
+        u128 *src = (u128 *)walk->src.virt.addr;
+        u128 *dst = (u128 *)walk->dst.virt.addr;
+        u128 *iv = (u128 *)walk->iv;
+
+        do {
+                u128_xor(dst, src, iv);
+                fn(ctx, (u8 *)dst, (u8 *)dst);
+                iv = dst;
+
+                src += 1;
+                dst += 1;
+                nbytes -= bsize;
+        } while (nbytes >= bsize);
+
+        u128_xor((u128 *)walk->iv, (u128 *)walk->iv, iv);
+        return nbytes;
+}
+
+int glue_cbc_encrypt_128bit(const common_glue_func_t fn,
+                            struct blkcipher_desc *desc,
+                            struct scatterlist *dst,
+                            struct scatterlist *src, unsigned int nbytes)
+{
+        struct blkcipher_walk walk;
+        int err;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        err = blkcipher_walk_virt(desc, &walk);
+
+        while ((nbytes = walk.nbytes)) {
+                nbytes = __glue_cbc_encrypt_128bit(fn, desc, &walk);
+                err = blkcipher_walk_done(desc, &walk, nbytes);
+        }
+
+        return err;
+}
+EXPORT_SYMBOL_GPL(glue_cbc_encrypt_128bit);
+
+static unsigned int
+__glue_cbc_decrypt_128bit(const struct common_glue_ctx *gctx,
+                          struct blkcipher_desc *desc,
+                          struct blkcipher_walk *walk)
+{
+        void *ctx = crypto_blkcipher_ctx(desc->tfm);
+        const unsigned int bsize = 128 / 8;
+        unsigned int nbytes = walk->nbytes;
+        u128 *src = (u128 *)walk->src.virt.addr;
+        u128 *dst = (u128 *)walk->dst.virt.addr;
+        u128 last_iv;
+        unsigned int num_blocks, func_bytes;
+        unsigned int i;
+
+        /* Start of the last block. */
+        src += nbytes / bsize - 1;
+        dst += nbytes / bsize - 1;
+
+        last_iv = *src;
+
+        for (i = 0; i < gctx->num_funcs; i++) {
+                num_blocks = gctx->funcs[i].num_blocks;
+                func_bytes = bsize * num_blocks;
+
+                /* Process multi-block batch */
+                if (nbytes >= func_bytes) {
+                        do {
+                                nbytes -= func_bytes - bsize;
+                                src -= num_blocks - 1;
+                                dst -= num_blocks - 1;
+
+                                gctx->funcs[i].fn_u.cbc(ctx, dst, src);
+
+                                nbytes -= bsize;
+                                if (nbytes < bsize)
+                                        goto done;
+
+                                u128_xor(dst, dst, src - 1);
+                                src -= 1;
+                                dst -= 1;
+                        } while (nbytes >= func_bytes);
+
+                        if (nbytes < bsize)
+                                goto done;
+                }
+        }
+
+done:
+        u128_xor(dst, dst, (u128 *)walk->iv);
+        *(u128 *)walk->iv = last_iv;
+
+        return nbytes;
+}
+
+int glue_cbc_decrypt_128bit(const struct common_glue_ctx *gctx,
+                            struct blkcipher_desc *desc,
+                            struct scatterlist *dst,
+                            struct scatterlist *src, unsigned int nbytes)
+{
+        const unsigned int bsize = 128 / 8;
+        bool fpu_enabled = false;
+        struct blkcipher_walk walk;
+        int err;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        err = blkcipher_walk_virt(desc, &walk);
+
+        while ((nbytes = walk.nbytes)) {
+                fpu_enabled = glue_fpu_begin(bsize, gctx->fpu_blocks_limit,
+                                             desc, fpu_enabled, nbytes);
+                nbytes = __glue_cbc_decrypt_128bit(gctx, desc, &walk);
+                err = blkcipher_walk_done(desc, &walk, nbytes);
+        }
+
+        glue_fpu_end(fpu_enabled);
+        return err;
+}
+EXPORT_SYMBOL_GPL(glue_cbc_decrypt_128bit);
+
+static void glue_ctr_crypt_final_128bit(const common_glue_ctr_func_t fn_ctr,
+                                        struct blkcipher_desc *desc,
+                                        struct blkcipher_walk *walk)
+{
+        void *ctx = crypto_blkcipher_ctx(desc->tfm);
+        u8 *src = (u8 *)walk->src.virt.addr;
+        u8 *dst = (u8 *)walk->dst.virt.addr;
+        unsigned int nbytes = walk->nbytes;
+        u128 ctrblk;
+        u128 tmp;
+
+        be128_to_u128(&ctrblk, (be128 *)walk->iv);
+
+        memcpy(&tmp, src, nbytes);
+        fn_ctr(ctx, &tmp, &tmp, &ctrblk);
+        memcpy(dst, &tmp, nbytes);
+
+        u128_to_be128((be128 *)walk->iv, &ctrblk);
+}
+EXPORT_SYMBOL_GPL(glue_ctr_crypt_final_128bit);
+
+static unsigned int __glue_ctr_crypt_128bit(const struct common_glue_ctx *gctx,
+                                            struct blkcipher_desc *desc,
+                                            struct blkcipher_walk *walk)
+{
+        const unsigned int bsize = 128 / 8;
+        void *ctx = crypto_blkcipher_ctx(desc->tfm);
+        unsigned int nbytes = walk->nbytes;
+        u128 *src = (u128 *)walk->src.virt.addr;
+        u128 *dst = (u128 *)walk->dst.virt.addr;
+        u128 ctrblk;
+        unsigned int num_blocks, func_bytes;
+        unsigned int i;
+
+        be128_to_u128(&ctrblk, (be128 *)walk->iv);
+
+        /* Process multi-block batch */
+        for (i = 0; i < gctx->num_funcs; i++) {
+                num_blocks = gctx->funcs[i].num_blocks;
+                func_bytes = bsize * num_blocks;
+
+                if (nbytes >= func_bytes) {
+                        do {
+                                gctx->funcs[i].fn_u.ctr(ctx, dst, src, &ctrblk);
+
+                                src += num_blocks;
+                                dst += num_blocks;
+                                nbytes -= func_bytes;
+                        } while (nbytes >= func_bytes);
+
+                        if (nbytes < bsize)
+                                goto done;
+                }
+        }
+
+done:
+        u128_to_be128((be128 *)walk->iv, &ctrblk);
+        return nbytes;
+}
+
+int glue_ctr_crypt_128bit(const struct common_glue_ctx *gctx,
+                          struct blkcipher_desc *desc, struct scatterlist *dst,
+                          struct scatterlist *src, unsigned int nbytes)
+{
+        const unsigned int bsize = 128 / 8;
+        bool fpu_enabled = false;
+        struct blkcipher_walk walk;
+        int err;
+
+        blkcipher_walk_init(&walk, dst, src, nbytes);
+        err = blkcipher_walk_virt_block(desc, &walk, bsize);
+
+        while ((nbytes = walk.nbytes) >= bsize) {
+                fpu_enabled = glue_fpu_begin(bsize, gctx->fpu_blocks_limit,
+                                             desc, fpu_enabled, nbytes);
+                nbytes = __glue_ctr_crypt_128bit(gctx, desc, &walk);
+                err = blkcipher_walk_done(desc, &walk, nbytes);
+        }
+
+        glue_fpu_end(fpu_enabled);
+
+        if (walk.nbytes) {
+                glue_ctr_crypt_final_128bit(
+                        gctx->funcs[gctx->num_funcs - 1].fn_u.ctr, desc, &walk);
+                err = blkcipher_walk_done(desc, &walk, 0);
+        }
+
+        return err;
+}
+EXPORT_SYMBOL_GPL(glue_ctr_crypt_128bit);
+
+MODULE_LICENSE("GPL");
diff --git a/arch/x86/crypto/serpent-avx-x86_64-asm_64.S b/arch/x86/crypto/serpent-avx-x86_64-asm_64.S
new file mode 100644
index 00000000000..504106bf04a
--- /dev/null
+++ b/arch/x86/crypto/serpent-avx-x86_64-asm_64.S
@@ -0,0 +1,704 @@
+/*
+ * Serpent Cipher 8-way parallel algorithm (x86_64/AVX)
+ *
+ * Copyright (C) 2012 Johannes Goetzfried
+ *     <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
+ *
+ * Based on arch/x86/crypto/serpent-sse2-x86_64-asm_64.S by
+ *  Copyright (C) 2011 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
+ * USA
+ *
+ */
+
+.file "serpent-avx-x86_64-asm_64.S"
+.text
+
+#define CTX %rdi
+
+/**********************************************************************
+  8-way AVX serpent
+ **********************************************************************/
+#define RA1 %xmm0
+#define RB1 %xmm1
+#define RC1 %xmm2
+#define RD1 %xmm3
+#define RE1 %xmm4
+
+#define tp  %xmm5
+
+#define RA2 %xmm6
+#define RB2 %xmm7
+#define RC2 %xmm8
+#define RD2 %xmm9
+#define RE2 %xmm10
+
+#define RNOT %xmm11
+
+#define RK0 %xmm12
+#define RK1 %xmm13
+#define RK2 %xmm14
+#define RK3 %xmm15
+
+
+#define S0_1(x0, x1, x2, x3, x4)      \
+        vpor            x0,   x3, tp; \
+        vpxor           x3,   x0, x0; \
+        vpxor           x2,   x3, x4; \
+        vpxor           RNOT, x4, x4; \
+        vpxor           x1,   tp, x3; \
+        vpand           x0,   x1, x1; \
+        vpxor           x4,   x1, x1; \
+        vpxor           x0,   x2, x2;
+#define S0_2(x0, x1, x2, x3, x4)      \
+        vpxor           x3,   x0, x0; \
+        vpor            x0,   x4, x4; \
+        vpxor           x2,   x0, x0; \
+        vpand           x1,   x2, x2; \
+        vpxor           x2,   x3, x3; \
+        vpxor           RNOT, x1, x1; \
+        vpxor           x4,   x2, x2; \
+        vpxor           x2,   x1, x1;
+
+#define S1_1(x0, x1, x2, x3, x4)      \
+        vpxor           x0,   x1, tp; \
+        vpxor           x3,   x0, x0; \
+        vpxor           RNOT, x3, x3; \
+        vpand           tp,   x1, x4; \
+        vpor            tp,   x0, x0; \
+        vpxor           x2,   x3, x3; \
+        vpxor           x3,   x0, x0; \
+        vpxor           x3,   tp, x1;
+#define S1_2(x0, x1, x2, x3, x4)      \
+        vpxor           x4,   x3, x3; \
+        vpor            x4,   x1, x1; \
+        vpxor           x2,   x4, x4; \
+        vpand           x0,   x2, x2; \
+        vpxor           x1,   x2, x2; \
+        vpor            x0,   x1, x1; \
+        vpxor           RNOT, x0, x0; \
+        vpxor           x2,   x0, x0; \
+        vpxor           x1,   x4, x4;
+
+#define S2_1(x0, x1, x2, x3, x4)      \
+        vpxor           RNOT, x3, x3; \
+        vpxor           x0,   x1, x1; \
+        vpand           x2,   x0, tp; \
+        vpxor           x3,   tp, tp; \
+        vpor            x0,   x3, x3; \
+        vpxor           x1,   x2, x2; \
+        vpxor           x1,   x3, x3; \
+        vpand           tp,   x1, x1;
+#define S2_2(x0, x1, x2, x3, x4)      \
+        vpxor           x2,   tp, tp; \
+        vpand           x3,   x2, x2; \
+        vpor            x1,   x3, x3; \
+        vpxor           RNOT, tp, tp; \
+        vpxor           tp,   x3, x3; \
+        vpxor           tp,   x0, x4; \
+        vpxor           x2,   tp, x0; \
+        vpor            x2,   x1, x1;
+
+#define S3_1(x0, x1, x2, x3, x4)      \
+        vpxor           x3,   x1, tp; \
+        vpor            x0,   x3, x3; \
+        vpand           x0,   x1, x4; \
+        vpxor           x2,   x0, x0; \
+        vpxor           tp,   x2, x2; \
+        vpand           x3,   tp, x1; \
+        vpxor           x3,   x2, x2; \
+        vpor            x4,   x0, x0; \
+        vpxor           x3,   x4, x4;
+#define S3_2(x0, x1, x2, x3, x4)      \
+        vpxor           x0,   x1, x1; \
+        vpand           x3,   x0, x0; \
+        vpand           x4,   x3, x3; \
+        vpxor           x2,   x3, x3; \
+        vpor            x1,   x4, x4; \
+        vpand           x1,   x2, x2; \
+        vpxor           x3,   x4, x4; \
+        vpxor           x3,   x0, x0; \
+        vpxor           x2,   x3, x3;
+
+#define S4_1(x0, x1, x2, x3, x4)      \
+        vpand           x0,   x3, tp; \
+        vpxor           x3,   x0, x0; \
+        vpxor           x2,   tp, tp; \
+        vpor            x3,   x2, x2; \
+        vpxor           x1,   x0, x0; \
+        vpxor           tp,   x3, x4; \
+        vpor            x0,   x2, x2; \
+        vpxor           x1,   x2, x2;
+#define S4_2(x0, x1, x2, x3, x4)      \
+        vpand           x0,   x1, x1; \
+        vpxor           x4,   x1, x1; \
+        vpand           x2,   x4, x4; \
+        vpxor           tp,   x2, x2; \
+        vpxor           x0,   x4, x4; \
+        vpor            x1,   tp, x3; \
+        vpxor           RNOT, x1, x1; \
+        vpxor           x0,   x3, x3;
+
+#define S5_1(x0, x1, x2, x3, x4)      \
+        vpor            x0,   x1, tp; \
+        vpxor           tp,   x2, x2; \
+        vpxor           RNOT, x3, x3; \
+        vpxor           x0,   x1, x4; \
+        vpxor           x2,   x0, x0; \
+        vpand           x4,   tp, x1; \
+        vpor            x3,   x4, x4; \
+        vpxor           x0,   x4, x4;
+#define S5_2(x0, x1, x2, x3, x4)      \
+        vpand           x3,   x0, x0; \
+        vpxor           x3,   x1, x1; \
+        vpxor           x2,   x3, x3; \
+        vpxor           x1,   x0, x0; \
+        vpand           x4,   x2, x2; \
+        vpxor           x2,   x1, x1; \
+        vpand           x0,   x2, x2; \
+        vpxor           x2,   x3, x3;
+
+#define S6_1(x0, x1, x2, x3, x4)      \
+        vpxor           x0,   x3, x3; \
+        vpxor           x2,   x1, tp; \
+        vpxor           x0,   x2, x2; \
+        vpand           x3,   x0, x0; \
+        vpor            x3,   tp, tp; \
+        vpxor           RNOT, x1, x4; \
+        vpxor           tp,   x0, x0; \
+        vpxor           x2,   tp, x1;
+#define S6_2(x0, x1, x2, x3, x4)      \
+        vpxor           x4,   x3, x3; \
+        vpxor           x0,   x4, x4; \
+        vpand           x0,   x2, x2; \
+        vpxor           x1,   x4, x4; \
+        vpxor           x3,   x2, x2; \
+        vpand           x1,   x3, x3; \
+        vpxor           x0,   x3, x3; \
+        vpxor           x2,   x1, x1;
+
+#define S7_1(x0, x1, x2, x3, x4)      \
+        vpxor           RNOT, x1, tp; \
+        vpxor           RNOT, x0, x0; \
+        vpand           x2,   tp, x1; \
+        vpxor           x3,   x1, x1; \
+        vpor            tp,   x3, x3; \
+        vpxor           x2,   tp, x4; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x0,   x3, x3; \
+        vpor            x1,   x0, x0;
+#define S7_2(x0, x1, x2, x3, x4)      \
+        vpand           x0,   x2, x2; \
+        vpxor           x4,   x0, x0; \
+        vpxor           x3,   x4, x4; \
+        vpand           x0,   x3, x3; \
+        vpxor           x1,   x4, x4; \
+        vpxor           x4,   x2, x2; \
+        vpxor           x1,   x3, x3; \
+        vpor            x0,   x4, x4; \
+        vpxor           x1,   x4, x4;
+
+#define SI0_1(x0, x1, x2, x3, x4)     \
+        vpxor           x0,   x1, x1; \
+        vpor            x1,   x3, tp; \
+        vpxor           x1,   x3, x4; \
+        vpxor           RNOT, x0, x0; \
+        vpxor           tp,   x2, x2; \
+        vpxor           x0,   tp, x3; \
+        vpand           x1,   x0, x0; \
+        vpxor           x2,   x0, x0;
+#define SI0_2(x0, x1, x2, x3, x4)     \
+        vpand           x3,   x2, x2; \
+        vpxor           x4,   x3, x3; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x3,   x1, x1; \
+        vpand           x0,   x3, x3; \
+        vpxor           x0,   x1, x1; \
+        vpxor           x2,   x0, x0; \
+        vpxor           x3,   x4, x4;
+
+#define SI1_1(x0, x1, x2, x3, x4)     \
+        vpxor           x3,   x1, x1; \
+        vpxor           x2,   x0, tp; \
+        vpxor           RNOT, x2, x2; \
+        vpor            x1,   x0, x4; \
+        vpxor           x3,   x4, x4; \
+        vpand           x1,   x3, x3; \
+        vpxor           x2,   x1, x1; \
+        vpand           x4,   x2, x2;
+#define SI1_2(x0, x1, x2, x3, x4)     \
+        vpxor           x1,   x4, x4; \
+        vpor            x3,   x1, x1; \
+        vpxor           tp,   x3, x3; \
+        vpxor           tp,   x2, x2; \
+        vpor            x4,   tp, x0; \
+        vpxor           x4,   x2, x2; \
+        vpxor           x0,   x1, x1; \
+        vpxor           x1,   x4, x4;
+
+#define SI2_1(x0, x1, x2, x3, x4)     \
+        vpxor           x1,   x2, x2; \
+        vpxor           RNOT, x3, tp; \
+        vpor            x2,   tp, tp; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x0,   x3, x4; \
+        vpxor           x1,   tp, x3; \
+        vpor            x2,   x1, x1; \
+        vpxor           x0,   x2, x2;
+#define SI2_2(x0, x1, x2, x3, x4)     \
+        vpxor           x4,   x1, x1; \
+        vpor            x3,   x4, x4; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x2,   x4, x4; \
+        vpand           x1,   x2, x2; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x4,   x3, x3; \
+        vpxor           x0,   x4, x4;
+
+#define SI3_1(x0, x1, x2, x3, x4)     \
+        vpxor           x1,   x2, x2; \
+        vpand           x2,   x1, tp; \
+        vpxor           x0,   tp, tp; \
+        vpor            x1,   x0, x0; \
+        vpxor           x3,   x1, x4; \
+        vpxor           x3,   x0, x0; \
+        vpor            tp,   x3, x3; \
+        vpxor           x2,   tp, x1;
+#define SI3_2(x0, x1, x2, x3, x4)     \
+        vpxor           x3,   x1, x1; \
+        vpxor           x2,   x0, x0; \
+        vpxor           x3,   x2, x2; \
+        vpand           x1,   x3, x3; \
+        vpxor           x0,   x1, x1; \
+        vpand           x2,   x0, x0; \
+        vpxor           x3,   x4, x4; \
+        vpxor           x0,   x3, x3; \
+        vpxor           x1,   x0, x0;
+
+#define SI4_1(x0, x1, x2, x3, x4)     \
+        vpxor           x3,   x2, x2; \
+        vpand           x1,   x0, tp; \
+        vpxor           x2,   tp, tp; \
+        vpor            x3,   x2, x2; \
+        vpxor           RNOT, x0, x4; \
+        vpxor           tp,   x1, x1; \
+        vpxor           x2,   tp, x0; \
+        vpand           x4,   x2, x2;
+#define SI4_2(x0, x1, x2, x3, x4)     \
+        vpxor           x0,   x2, x2; \
+        vpor            x4,   x0, x0; \
+        vpxor           x3,   x0, x0; \
+        vpand           x2,   x3, x3; \
+        vpxor           x3,   x4, x4; \
+        vpxor           x1,   x3, x3; \
+        vpand           x0,   x1, x1; \
+        vpxor           x1,   x4, x4; \
+        vpxor           x3,   x0, x0;
+
+#define SI5_1(x0, x1, x2, x3, x4)     \
+        vpor            x2,   x1, tp; \
+        vpxor           x1,   x2, x2; \
+        vpxor           x3,   tp, tp; \
+        vpand           x1,   x3, x3; \
+        vpxor           x3,   x2, x2; \
+        vpor            x0,   x3, x3; \
+        vpxor           RNOT, x0, x0; \
+        vpxor           x2,   x3, x3; \
+        vpor            x0,   x2, x2;
+#define SI5_2(x0, x1, x2, x3, x4)     \
+        vpxor           tp,   x1, x4; \
+        vpxor           x4,   x2, x2; \
+        vpand           x0,   x4, x4; \
+        vpxor           tp,   x0, x0; \
+        vpxor           x3,   tp, x1; \
+        vpand           x2,   x0, x0; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x2,   x0, x0; \
+        vpxor           x4,   x2, x2; \
+        vpxor           x3,   x4, x4;
+
+#define SI6_1(x0, x1, x2, x3, x4)     \
+        vpxor           x2,   x0, x0; \
+        vpand           x3,   x0, tp; \
+        vpxor           x3,   x2, x2; \
+        vpxor           x2,   tp, tp; \
+        vpxor           x1,   x3, x3; \
+        vpor            x0,   x2, x2; \
+        vpxor           x3,   x2, x2; \
+        vpand           tp,   x3, x3;
+#define SI6_2(x0, x1, x2, x3, x4)     \
+        vpxor           RNOT, tp, tp; \
+        vpxor           x1,   x3, x3; \
+        vpand           x2,   x1, x1; \
+        vpxor           tp,   x0, x4; \
+        vpxor           x4,   x3, x3; \
+        vpxor           x2,   x4, x4; \
+        vpxor           x1,   tp, x0; \
+        vpxor           x0,   x2, x2;
+
+#define SI7_1(x0, x1, x2, x3, x4)     \
+        vpand           x0,   x3, tp; \
+        vpxor           x2,   x0, x0; \
+        vpor            x3,   x2, x2; \
+        vpxor           x1,   x3, x4; \
+        vpxor           RNOT, x0, x0; \
+        vpor            tp,   x1, x1; \
+        vpxor           x0,   x4, x4; \
+        vpand           x2,   x0, x0; \
+        vpxor           x1,   x0, x0;
+#define SI7_2(x0, x1, x2, x3, x4)     \
+        vpand           x2,   x1, x1; \
+        vpxor           x2,   tp, x3; \
+        vpxor           x3,   x4, x4; \
+        vpand           x3,   x2, x2; \
+        vpor            x0,   x3, x3; \
+        vpxor           x4,   x1, x1; \
+        vpxor           x4,   x3, x3; \
+        vpand           x0,   x4, x4; \
+        vpxor           x2,   x4, x4;
+
+#define get_key(i, j, t) \
+        vbroadcastss (4*(i)+(j))*4(CTX), t;
+
+#define K2(x0, x1, x2, x3, x4, i) \
+        get_key(i, 0, RK0); \
+        get_key(i, 1, RK1); \
+        get_key(i, 2, RK2); \
+        get_key(i, 3, RK3); \
+        vpxor RK0,      x0 ## 1, x0 ## 1; \
+        vpxor RK1,      x1 ## 1, x1 ## 1; \
+        vpxor RK2,      x2 ## 1, x2 ## 1; \
+        vpxor RK3,      x3 ## 1, x3 ## 1; \
+                vpxor RK0,      x0 ## 2, x0 ## 2; \
+                vpxor RK1,      x1 ## 2, x1 ## 2; \
+                vpxor RK2,      x2 ## 2, x2 ## 2; \
+                vpxor RK3,      x3 ## 2, x3 ## 2;
+
+#define LK2(x0, x1, x2, x3, x4, i) \
+        vpslld $13,             x0 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 13),      x0 ## 1, x0 ## 1;          \
+        vpor                    x4 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   x0 ## 1, x1 ## 1, x1 ## 1; \
+        vpslld $3,              x2 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 3),       x2 ## 1, x2 ## 1;          \
+        vpor                    x4 ## 1, x2 ## 1, x2 ## 1; \
+        vpxor                   x2 ## 1, x1 ## 1, x1 ## 1; \
+                vpslld $13,             x0 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 13),      x0 ## 2, x0 ## 2;          \
+                vpor                    x4 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   x0 ## 2, x1 ## 2, x1 ## 2; \
+                vpslld $3,              x2 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 3),       x2 ## 2, x2 ## 2;          \
+                vpor                    x4 ## 2, x2 ## 2, x2 ## 2; \
+                vpxor                   x2 ## 2, x1 ## 2, x1 ## 2; \
+        vpslld $1,              x1 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 1),       x1 ## 1, x1 ## 1;          \
+        vpor                    x4 ## 1, x1 ## 1, x1 ## 1; \
+        vpslld $3,              x0 ## 1, x4 ## 1;          \
+        vpxor                   x2 ## 1, x3 ## 1, x3 ## 1; \
+        vpxor                   x4 ## 1, x3 ## 1, x3 ## 1; \
+        get_key(i, 1, RK1); \
+                vpslld $1,              x1 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 1),       x1 ## 2, x1 ## 2;          \
+                vpor                    x4 ## 2, x1 ## 2, x1 ## 2; \
+                vpslld $3,              x0 ## 2, x4 ## 2;          \
+                vpxor                   x2 ## 2, x3 ## 2, x3 ## 2; \
+                vpxor                   x4 ## 2, x3 ## 2, x3 ## 2; \
+                get_key(i, 3, RK3); \
+        vpslld $7,              x3 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 7),       x3 ## 1, x3 ## 1;          \
+        vpor                    x4 ## 1, x3 ## 1, x3 ## 1; \
+        vpslld $7,              x1 ## 1, x4 ## 1;          \
+        vpxor                   x1 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   x3 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   x3 ## 1, x2 ## 1, x2 ## 1; \
+        vpxor                   x4 ## 1, x2 ## 1, x2 ## 1; \
+        get_key(i, 0, RK0); \
+                vpslld $7,              x3 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 7),       x3 ## 2, x3 ## 2;          \
+                vpor                    x4 ## 2, x3 ## 2, x3 ## 2; \
+                vpslld $7,              x1 ## 2, x4 ## 2;          \
+                vpxor                   x1 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   x3 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   x3 ## 2, x2 ## 2, x2 ## 2; \
+                vpxor                   x4 ## 2, x2 ## 2, x2 ## 2; \
+                get_key(i, 2, RK2); \
+        vpxor                   RK1, x1 ## 1, x1 ## 1;     \
+        vpxor                   RK3, x3 ## 1, x3 ## 1;     \
+        vpslld $5,              x0 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 5),       x0 ## 1, x0 ## 1;          \
+        vpor                    x4 ## 1, x0 ## 1, x0 ## 1; \
+        vpslld $22,             x2 ## 1, x4 ## 1;          \
+        vpsrld $(32 - 22),      x2 ## 1, x2 ## 1;          \
+        vpor                    x4 ## 1, x2 ## 1, x2 ## 1; \
+        vpxor                   RK0, x0 ## 1, x0 ## 1;     \
+        vpxor                   RK2, x2 ## 1, x2 ## 1;     \
+                vpxor                   RK1, x1 ## 2, x1 ## 2;     \
+                vpxor                   RK3, x3 ## 2, x3 ## 2;     \
+                vpslld $5,              x0 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 5),       x0 ## 2, x0 ## 2;          \
+                vpor                    x4 ## 2, x0 ## 2, x0 ## 2; \
+                vpslld $22,             x2 ## 2, x4 ## 2;          \
+                vpsrld $(32 - 22),      x2 ## 2, x2 ## 2;          \
+                vpor                    x4 ## 2, x2 ## 2, x2 ## 2; \
+                vpxor                   RK0, x0 ## 2, x0 ## 2;     \
+                vpxor                   RK2, x2 ## 2, x2 ## 2;
+
+#define KL2(x0, x1, x2, x3, x4, i) \
+        vpxor                   RK0, x0 ## 1, x0 ## 1;     \
+        vpxor                   RK2, x2 ## 1, x2 ## 1;     \
+        vpsrld $5,              x0 ## 1, x4 ## 1;          \
+        vpslld $(32 - 5),       x0 ## 1, x0 ## 1;          \
+        vpor                    x4 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   RK3, x3 ## 1, x3 ## 1;     \
+        vpxor                   RK1, x1 ## 1, x1 ## 1;     \
+        vpsrld $22,             x2 ## 1, x4 ## 1;          \
+        vpslld $(32 - 22),      x2 ## 1, x2 ## 1;          \
+        vpor                    x4 ## 1, x2 ## 1, x2 ## 1; \
+        vpxor                   x3 ## 1, x2 ## 1, x2 ## 1; \
+                vpxor                   RK0, x0 ## 2, x0 ## 2;     \
+                vpxor                   RK2, x2 ## 2, x2 ## 2;     \
+                vpsrld $5,              x0 ## 2, x4 ## 2;          \
+                vpslld $(32 - 5),       x0 ## 2, x0 ## 2;          \
+                vpor                    x4 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   RK3, x3 ## 2, x3 ## 2;     \
+                vpxor                   RK1, x1 ## 2, x1 ## 2;     \
+                vpsrld $22,             x2 ## 2, x4 ## 2;          \
+                vpslld $(32 - 22),      x2 ## 2, x2 ## 2;          \
+                vpor                    x4 ## 2, x2 ## 2, x2 ## 2; \
+                vpxor                   x3 ## 2, x2 ## 2, x2 ## 2; \
+        vpxor                   x3 ## 1, x0 ## 1, x0 ## 1; \
+        vpslld $7,              x1 ## 1, x4 ## 1;          \
+        vpxor                   x1 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   x4 ## 1, x2 ## 1, x2 ## 1; \
+        vpsrld $1,              x1 ## 1, x4 ## 1;          \
+        vpslld $(32 - 1),       x1 ## 1, x1 ## 1;          \
+        vpor                    x4 ## 1, x1 ## 1, x1 ## 1; \
+                vpxor                   x3 ## 2, x0 ## 2, x0 ## 2; \
+                vpslld $7,              x1 ## 2, x4 ## 2;          \
+                vpxor                   x1 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   x4 ## 2, x2 ## 2, x2 ## 2; \
+                vpsrld $1,              x1 ## 2, x4 ## 2;          \
+                vpslld $(32 - 1),       x1 ## 2, x1 ## 2;          \
+                vpor                    x4 ## 2, x1 ## 2, x1 ## 2; \
+        vpsrld $7,              x3 ## 1, x4 ## 1;          \
+        vpslld $(32 - 7),       x3 ## 1, x3 ## 1;          \
+        vpor                    x4 ## 1, x3 ## 1, x3 ## 1; \
+        vpxor                   x0 ## 1, x1 ## 1, x1 ## 1; \
+        vpslld $3,              x0 ## 1, x4 ## 1;          \
+        vpxor                   x4 ## 1, x3 ## 1, x3 ## 1; \
+                vpsrld $7,              x3 ## 2, x4 ## 2;          \
+                vpslld $(32 - 7),       x3 ## 2, x3 ## 2;          \
+                vpor                    x4 ## 2, x3 ## 2, x3 ## 2; \
+                vpxor                   x0 ## 2, x1 ## 2, x1 ## 2; \
+                vpslld $3,              x0 ## 2, x4 ## 2;          \
+                vpxor                   x4 ## 2, x3 ## 2, x3 ## 2; \
+        vpsrld $13,             x0 ## 1, x4 ## 1;          \
+        vpslld $(32 - 13),      x0 ## 1, x0 ## 1;          \
+        vpor                    x4 ## 1, x0 ## 1, x0 ## 1; \
+        vpxor                   x2 ## 1, x1 ## 1, x1 ## 1; \
+        vpxor                   x2 ## 1, x3 ## 1, x3 ## 1; \
+        vpsrld $3,              x2 ## 1, x4 ## 1;          \
+        vpslld $(32 - 3),       x2 ## 1, x2 ## 1;          \
+        vpor                    x4 ## 1, x2 ## 1, x2 ## 1; \
+                vpsrld $13,             x0 ## 2, x4 ## 2;          \
+                vpslld $(32 - 13),      x0 ## 2, x0 ## 2;          \
+                vpor                    x4 ## 2, x0 ## 2, x0 ## 2; \
+                vpxor                   x2 ## 2, x1 ## 2, x1 ## 2; \
+                vpxor                   x2 ## 2, x3 ## 2, x3 ## 2; \
+                vpsrld $3,              x2 ## 2, x4 ## 2;          \
+                vpslld $(32 - 3),       x2 ## 2, x2 ## 2;          \
+                vpor                    x4 ## 2, x2 ## 2, x2 ## 2;
+
+#define S(SBOX, x0, x1, x2, x3, x4) \
+        SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
+        SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
+        SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
+        SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2);
+
+#define SP(SBOX, x0, x1, x2, x3, x4, i) \
+        get_key(i, 0, RK0); \
+        SBOX ## _1(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
+        get_key(i, 2, RK2); \
+        SBOX ## _2(x0 ## 1, x1 ## 1, x2 ## 1, x3 ## 1, x4 ## 1); \
+        get_key(i, 3, RK3); \
+        SBOX ## _1(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
+        get_key(i, 1, RK1); \
+        SBOX ## _2(x0 ## 2, x1 ## 2, x2 ## 2, x3 ## 2, x4 ## 2); \
+
+#define transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
+        vpunpckldq              x1, x0, t0; \
+        vpunpckhdq              x1, x0, t2; \
+        vpunpckldq              x3, x2, t1; \
+        vpunpckhdq              x3, x2, x3; \
+        \
+        vpunpcklqdq             t1, t0, x0; \
+        vpunpckhqdq             t1, t0, x1; \
+        vpunpcklqdq             x3, t2, x2; \
+        vpunpckhqdq             x3, t2, x3;
+
+#define read_blocks(in, x0, x1, x2, x3, t0, t1, t2) \
+        vmovdqu (0*4*4)(in),    x0; \
+        vmovdqu (1*4*4)(in),    x1; \
+        vmovdqu (2*4*4)(in),    x2; \
+        vmovdqu (3*4*4)(in),    x3; \
+        \
+        transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
+
+#define write_blocks(out, x0, x1, x2, x3, t0, t1, t2) \
+        transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
+        \
+        vmovdqu x0,             (0*4*4)(out); \
+        vmovdqu x1,             (1*4*4)(out); \
+        vmovdqu x2,             (2*4*4)(out); \
+        vmovdqu x3,             (3*4*4)(out);
+
+#define xor_blocks(out, x0, x1, x2, x3, t0, t1, t2) \
+        transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
+        \
+        vpxor (0*4*4)(out),     x0, x0;       \
+        vmovdqu x0,             (0*4*4)(out); \
+        vpxor (1*4*4)(out),     x1, x1;       \
+        vmovdqu x1,             (1*4*4)(out); \
+        vpxor (2*4*4)(out),     x2, x2;       \
+        vmovdqu x2,             (2*4*4)(out); \
+        vpxor (3*4*4)(out),     x3, x3;       \
+        vmovdqu x3,             (3*4*4)(out);
+
+.align 8
+.global __serpent_enc_blk_8way_avx
+.type   __serpent_enc_blk_8way_avx,@function;
+
+__serpent_enc_blk_8way_avx:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         *      %rcx: bool, if true: xor output
+         */
+
+        vpcmpeqd RNOT, RNOT, RNOT;
+
+        leaq (4*4*4)(%rdx), %rax;
+        read_blocks(%rdx, RA1, RB1, RC1, RD1, RK0, RK1, RK2);
+        read_blocks(%rax, RA2, RB2, RC2, RD2, RK0, RK1, RK2);
+
+                                                 K2(RA, RB, RC, RD, RE, 0);
+        S(S0, RA, RB, RC, RD, RE);              LK2(RC, RB, RD, RA, RE, 1);
+        S(S1, RC, RB, RD, RA, RE);              LK2(RE, RD, RA, RC, RB, 2);
+        S(S2, RE, RD, RA, RC, RB);              LK2(RB, RD, RE, RC, RA, 3);
+        S(S3, RB, RD, RE, RC, RA);              LK2(RC, RA, RD, RB, RE, 4);
+        S(S4, RC, RA, RD, RB, RE);              LK2(RA, RD, RB, RE, RC, 5);
+        S(S5, RA, RD, RB, RE, RC);              LK2(RC, RA, RD, RE, RB, 6);
+        S(S6, RC, RA, RD, RE, RB);              LK2(RD, RB, RA, RE, RC, 7);
+        S(S7, RD, RB, RA, RE, RC);              LK2(RC, RA, RE, RD, RB, 8);
+        S(S0, RC, RA, RE, RD, RB);              LK2(RE, RA, RD, RC, RB, 9);
+        S(S1, RE, RA, RD, RC, RB);              LK2(RB, RD, RC, RE, RA, 10);
+        S(S2, RB, RD, RC, RE, RA);              LK2(RA, RD, RB, RE, RC, 11);
+        S(S3, RA, RD, RB, RE, RC);              LK2(RE, RC, RD, RA, RB, 12);
+        S(S4, RE, RC, RD, RA, RB);              LK2(RC, RD, RA, RB, RE, 13);
+        S(S5, RC, RD, RA, RB, RE);              LK2(RE, RC, RD, RB, RA, 14);
+        S(S6, RE, RC, RD, RB, RA);              LK2(RD, RA, RC, RB, RE, 15);
+        S(S7, RD, RA, RC, RB, RE);              LK2(RE, RC, RB, RD, RA, 16);
+        S(S0, RE, RC, RB, RD, RA);              LK2(RB, RC, RD, RE, RA, 17);
+        S(S1, RB, RC, RD, RE, RA);              LK2(RA, RD, RE, RB, RC, 18);
+        S(S2, RA, RD, RE, RB, RC);              LK2(RC, RD, RA, RB, RE, 19);
+        S(S3, RC, RD, RA, RB, RE);              LK2(RB, RE, RD, RC, RA, 20);
+        S(S4, RB, RE, RD, RC, RA);              LK2(RE, RD, RC, RA, RB, 21);
+        S(S5, RE, RD, RC, RA, RB);              LK2(RB, RE, RD, RA, RC, 22);
+        S(S6, RB, RE, RD, RA, RC);              LK2(RD, RC, RE, RA, RB, 23);
+        S(S7, RD, RC, RE, RA, RB);              LK2(RB, RE, RA, RD, RC, 24);
+        S(S0, RB, RE, RA, RD, RC);              LK2(RA, RE, RD, RB, RC, 25);
+        S(S1, RA, RE, RD, RB, RC);              LK2(RC, RD, RB, RA, RE, 26);
+        S(S2, RC, RD, RB, RA, RE);              LK2(RE, RD, RC, RA, RB, 27);
+        S(S3, RE, RD, RC, RA, RB);              LK2(RA, RB, RD, RE, RC, 28);
+        S(S4, RA, RB, RD, RE, RC);              LK2(RB, RD, RE, RC, RA, 29);
+        S(S5, RB, RD, RE, RC, RA);              LK2(RA, RB, RD, RC, RE, 30);
+        S(S6, RA, RB, RD, RC, RE);              LK2(RD, RE, RB, RC, RA, 31);
+        S(S7, RD, RE, RB, RC, RA);               K2(RA, RB, RC, RD, RE, 32);
+
+        leaq (4*4*4)(%rsi), %rax;
+
+        testb %cl, %cl;
+        jnz __enc_xor8;
+
+        write_blocks(%rsi, RA1, RB1, RC1, RD1, RK0, RK1, RK2);
+        write_blocks(%rax, RA2, RB2, RC2, RD2, RK0, RK1, RK2);
+
+        ret;
+
+__enc_xor8:
+        xor_blocks(%rsi, RA1, RB1, RC1, RD1, RK0, RK1, RK2);
+        xor_blocks(%rax, RA2, RB2, RC2, RD2, RK0, RK1, RK2);
+
+        ret;
+
+.align 8
+.global serpent_dec_blk_8way_avx
+.type   serpent_dec_blk_8way_avx,@function;
+
+serpent_dec_blk_8way_avx:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        vpcmpeqd RNOT, RNOT, RNOT;
+
+        leaq (4*4*4)(%rdx), %rax;
+        read_blocks(%rdx, RA1, RB1, RC1, RD1, RK0, RK1, RK2);
+        read_blocks(%rax, RA2, RB2, RC2, RD2, RK0, RK1, RK2);
+
+                                                 K2(RA, RB, RC, RD, RE, 32);
+        SP(SI7, RA, RB, RC, RD, RE, 31);        KL2(RB, RD, RA, RE, RC, 31);
+        SP(SI6, RB, RD, RA, RE, RC, 30);        KL2(RA, RC, RE, RB, RD, 30);
+        SP(SI5, RA, RC, RE, RB, RD, 29);        KL2(RC, RD, RA, RE, RB, 29);
+        SP(SI4, RC, RD, RA, RE, RB, 28);        KL2(RC, RA, RB, RE, RD, 28);
+        SP(SI3, RC, RA, RB, RE, RD, 27);        KL2(RB, RC, RD, RE, RA, 27);
+        SP(SI2, RB, RC, RD, RE, RA, 26);        KL2(RC, RA, RE, RD, RB, 26);
+        SP(SI1, RC, RA, RE, RD, RB, 25);        KL2(RB, RA, RE, RD, RC, 25);
+        SP(SI0, RB, RA, RE, RD, RC, 24);        KL2(RE, RC, RA, RB, RD, 24);
+        SP(SI7, RE, RC, RA, RB, RD, 23);        KL2(RC, RB, RE, RD, RA, 23);
+        SP(SI6, RC, RB, RE, RD, RA, 22);        KL2(RE, RA, RD, RC, RB, 22);
+        SP(SI5, RE, RA, RD, RC, RB, 21);        KL2(RA, RB, RE, RD, RC, 21);
+        SP(SI4, RA, RB, RE, RD, RC, 20);        KL2(RA, RE, RC, RD, RB, 20);
+        SP(SI3, RA, RE, RC, RD, RB, 19);        KL2(RC, RA, RB, RD, RE, 19);
+        SP(SI2, RC, RA, RB, RD, RE, 18);        KL2(RA, RE, RD, RB, RC, 18);
+        SP(SI1, RA, RE, RD, RB, RC, 17);        KL2(RC, RE, RD, RB, RA, 17);
+        SP(SI0, RC, RE, RD, RB, RA, 16);        KL2(RD, RA, RE, RC, RB, 16);
+        SP(SI7, RD, RA, RE, RC, RB, 15);        KL2(RA, RC, RD, RB, RE, 15);
+        SP(SI6, RA, RC, RD, RB, RE, 14);        KL2(RD, RE, RB, RA, RC, 14);
+        SP(SI5, RD, RE, RB, RA, RC, 13);        KL2(RE, RC, RD, RB, RA, 13);
+        SP(SI4, RE, RC, RD, RB, RA, 12);        KL2(RE, RD, RA, RB, RC, 12);
+        SP(SI3, RE, RD, RA, RB, RC, 11);        KL2(RA, RE, RC, RB, RD, 11);
+        SP(SI2, RA, RE, RC, RB, RD, 10);        KL2(RE, RD, RB, RC, RA, 10);
+        SP(SI1, RE, RD, RB, RC, RA, 9);         KL2(RA, RD, RB, RC, RE, 9);
+        SP(SI0, RA, RD, RB, RC, RE, 8);         KL2(RB, RE, RD, RA, RC, 8);
+        SP(SI7, RB, RE, RD, RA, RC, 7);         KL2(RE, RA, RB, RC, RD, 7);
+        SP(SI6, RE, RA, RB, RC, RD, 6);         KL2(RB, RD, RC, RE, RA, 6);
+        SP(SI5, RB, RD, RC, RE, RA, 5);         KL2(RD, RA, RB, RC, RE, 5);
+        SP(SI4, RD, RA, RB, RC, RE, 4);         KL2(RD, RB, RE, RC, RA, 4);
+        SP(SI3, RD, RB, RE, RC, RA, 3);         KL2(RE, RD, RA, RC, RB, 3);
+        SP(SI2, RE, RD, RA, RC, RB, 2);         KL2(RD, RB, RC, RA, RE, 2);
+        SP(SI1, RD, RB, RC, RA, RE, 1);         KL2(RE, RB, RC, RA, RD, 1);
+        S(SI0, RE, RB, RC, RA, RD);              K2(RC, RD, RB, RE, RA, 0);
+
+        leaq (4*4*4)(%rsi), %rax;
+        write_blocks(%rsi, RC1, RD1, RB1, RE1, RK0, RK1, RK2);
+        write_blocks(%rax, RC2, RD2, RB2, RE2, RK0, RK1, RK2);
+
+        ret;
diff --git a/arch/x86/crypto/serpent_avx_glue.c b/arch/x86/crypto/serpent_avx_glue.c
new file mode 100644
index 00000000000..b36bdac237e
--- /dev/null
+++ b/arch/x86/crypto/serpent_avx_glue.c
@@ -0,0 +1,636 @@
+/*
+ * Glue Code for AVX assembler versions of Serpent Cipher
+ *
+ * Copyright (C) 2012 Johannes Goetzfried
+ *     <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
+ *
+ * Glue code based on serpent_sse2_glue.c by:
+ *  Copyright (C) 2011 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
+ * USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/hardirq.h>
+#include <linux/types.h>
+#include <linux/crypto.h>
+#include <linux/err.h>
+#include <crypto/algapi.h>
+#include <crypto/serpent.h>
+#include <crypto/cryptd.h>
+#include <crypto/b128ops.h>
+#include <crypto/ctr.h>
+#include <crypto/lrw.h>
+#include <crypto/xts.h>
+#include <asm/xcr.h>
+#include <asm/xsave.h>
+#include <asm/crypto/serpent-avx.h>
+#include <asm/crypto/ablk_helper.h>
+#include <asm/crypto/glue_helper.h>
+
+static void serpent_decrypt_cbc_xway(void *ctx, u128 *dst, const u128 *src)
+{
+        u128 ivs[SERPENT_PARALLEL_BLOCKS - 1];
+        unsigned int j;
+
+        for (j = 0; j < SERPENT_PARALLEL_BLOCKS - 1; j++)
+                ivs[j] = src[j];
+
+        serpent_dec_blk_xway(ctx, (u8 *)dst, (u8 *)src);
+
+        for (j = 0; j < SERPENT_PARALLEL_BLOCKS - 1; j++)
+                u128_xor(dst + (j + 1), dst + (j + 1), ivs + j);
+}
+
+static void serpent_crypt_ctr(void *ctx, u128 *dst, const u128 *src, u128 *iv)
+{
+        be128 ctrblk;
+
+        u128_to_be128(&ctrblk, iv);
+        u128_inc(iv);
+
+        __serpent_encrypt(ctx, (u8 *)&ctrblk, (u8 *)&ctrblk);
+        u128_xor(dst, src, (u128 *)&ctrblk);
+}
+
+static void serpent_crypt_ctr_xway(void *ctx, u128 *dst, const u128 *src,
+                                   u128 *iv)
+{
+        be128 ctrblks[SERPENT_PARALLEL_BLOCKS];
+        unsigned int i;
+
+        for (i = 0; i < SERPENT_PARALLEL_BLOCKS; i++) {
+                if (dst != src)
+                        dst[i] = src[i];
+
+                u128_to_be128(&ctrblks[i], iv);
+                u128_inc(iv);
+        }
+
+        serpent_enc_blk_xway_xor(ctx, (u8 *)dst, (u8 *)ctrblks);
+}
+
+static const struct common_glue_ctx serpent_enc = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = SERPENT_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = SERPENT_PARALLEL_BLOCKS,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(serpent_enc_blk_xway) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(__serpent_encrypt) }
+        } }
+};
+
+static const struct common_glue_ctx serpent_ctr = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = SERPENT_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = SERPENT_PARALLEL_BLOCKS,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_crypt_ctr_xway) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_crypt_ctr) }
+        } }
+};
+
+static const struct common_glue_ctx serpent_dec = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = SERPENT_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = SERPENT_PARALLEL_BLOCKS,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(serpent_dec_blk_xway) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(__serpent_decrypt) }
+        } }
+};
+
+static const struct common_glue_ctx serpent_dec_cbc = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = SERPENT_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = SERPENT_PARALLEL_BLOCKS,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(serpent_decrypt_cbc_xway) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(__serpent_decrypt) }
+        } }
+};
+
+static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ecb_crypt_128bit(&serpent_enc, desc, dst, src, nbytes);
+}
+
+static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ecb_crypt_128bit(&serpent_dec, desc, dst, src, nbytes);
+}
+
+static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_cbc_encrypt_128bit(GLUE_FUNC_CAST(__serpent_encrypt), desc,
+                                     dst, src, nbytes);
+}
+
+static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_cbc_decrypt_128bit(&serpent_dec_cbc, desc, dst, src,
+                                       nbytes);
+}
+
+static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                     struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ctr_crypt_128bit(&serpent_ctr, desc, dst, src, nbytes);
+}
+
+static inline bool serpent_fpu_begin(bool fpu_enabled, unsigned int nbytes)
+{
+        return glue_fpu_begin(SERPENT_BLOCK_SIZE, SERPENT_PARALLEL_BLOCKS,
+                              NULL, fpu_enabled, nbytes);
+}
+
+static inline void serpent_fpu_end(bool fpu_enabled)
+{
+        glue_fpu_end(fpu_enabled);
+}
+
+struct crypt_priv {
+        struct serpent_ctx *ctx;
+        bool fpu_enabled;
+};
+
+static void encrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
+{
+        const unsigned int bsize = SERPENT_BLOCK_SIZE;
+        struct crypt_priv *ctx = priv;
+        int i;
+
+        ctx->fpu_enabled = serpent_fpu_begin(ctx->fpu_enabled, nbytes);
+
+        if (nbytes == bsize * SERPENT_PARALLEL_BLOCKS) {
+                serpent_enc_blk_xway(ctx->ctx, srcdst, srcdst);
+                return;
+        }
+
+        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
+                __serpent_encrypt(ctx->ctx, srcdst, srcdst);
+}
+
+static void decrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
+{
+        const unsigned int bsize = SERPENT_BLOCK_SIZE;
+        struct crypt_priv *ctx = priv;
+        int i;
+
+        ctx->fpu_enabled = serpent_fpu_begin(ctx->fpu_enabled, nbytes);
+
+        if (nbytes == bsize * SERPENT_PARALLEL_BLOCKS) {
+                serpent_dec_blk_xway(ctx->ctx, srcdst, srcdst);
+                return;
+        }
+
+        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
+                __serpent_decrypt(ctx->ctx, srcdst, srcdst);
+}
+
+struct serpent_lrw_ctx {
+        struct lrw_table_ctx lrw_table;
+        struct serpent_ctx serpent_ctx;
+};
+
+static int lrw_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
+                              unsigned int keylen)
+{
+        struct serpent_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
+        int err;
+
+        err = __serpent_setkey(&ctx->serpent_ctx, key, keylen -
+                                                        SERPENT_BLOCK_SIZE);
+        if (err)
+                return err;
+
+        return lrw_init_table(&ctx->lrw_table, key + keylen -
+                                                SERPENT_BLOCK_SIZE);
+}
+
+static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct serpent_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[SERPENT_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->serpent_ctx,
+                .fpu_enabled = false,
+        };
+        struct lrw_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .table_ctx = &ctx->lrw_table,
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = encrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = lrw_crypt(desc, dst, src, nbytes, &req);
+        serpent_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct serpent_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[SERPENT_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->serpent_ctx,
+                .fpu_enabled = false,
+        };
+        struct lrw_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .table_ctx = &ctx->lrw_table,
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = decrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = lrw_crypt(desc, dst, src, nbytes, &req);
+        serpent_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static void lrw_exit_tfm(struct crypto_tfm *tfm)
+{
+        struct serpent_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
+
+        lrw_free_table(&ctx->lrw_table);
+}
+
+struct serpent_xts_ctx {
+        struct serpent_ctx tweak_ctx;
+        struct serpent_ctx crypt_ctx;
+};
+
+static int xts_serpent_setkey(struct crypto_tfm *tfm, const u8 *key,
+                              unsigned int keylen)
+{
+        struct serpent_xts_ctx *ctx = crypto_tfm_ctx(tfm);
+        u32 *flags = &tfm->crt_flags;
+        int err;
+
+        /* key consists of keys of equal size concatenated, therefore
+         * the length must be even
+         */
+        if (keylen % 2) {
+                *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
+                return -EINVAL;
+        }
+
+        /* first half of xts-key is for crypt */
+        err = __serpent_setkey(&ctx->crypt_ctx, key, keylen / 2);
+        if (err)
+                return err;
+
+        /* second half of xts-key is for tweak */
+        return __serpent_setkey(&ctx->tweak_ctx, key + keylen / 2, keylen / 2);
+}
+
+static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct serpent_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[SERPENT_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->crypt_ctx,
+                .fpu_enabled = false,
+        };
+        struct xts_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .tweak_ctx = &ctx->tweak_ctx,
+                .tweak_fn = XTS_TWEAK_CAST(__serpent_encrypt),
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = encrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = xts_crypt(desc, dst, src, nbytes, &req);
+        serpent_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct serpent_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[SERPENT_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->crypt_ctx,
+                .fpu_enabled = false,
+        };
+        struct xts_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .tweak_ctx = &ctx->tweak_ctx,
+                .tweak_fn = XTS_TWEAK_CAST(__serpent_encrypt),
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = decrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = xts_crypt(desc, dst, src, nbytes, &req);
+        serpent_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static struct crypto_alg serpent_algs[10] = { {
+        .cra_name               = "__ecb-serpent-avx",
+        .cra_driver_name        = "__driver-ecb-serpent-avx",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct serpent_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(serpent_algs[0].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .setkey         = serpent_setkey,
+                        .encrypt        = ecb_encrypt,
+                        .decrypt        = ecb_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__cbc-serpent-avx",
+        .cra_driver_name        = "__driver-cbc-serpent-avx",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct serpent_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(serpent_algs[1].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .setkey         = serpent_setkey,
+                        .encrypt        = cbc_encrypt,
+                        .decrypt        = cbc_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__ctr-serpent-avx",
+        .cra_driver_name        = "__driver-ctr-serpent-avx",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct serpent_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(serpent_algs[2].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = serpent_setkey,
+                        .encrypt        = ctr_crypt,
+                        .decrypt        = ctr_crypt,
+                },
+        },
+}, {
+        .cra_name               = "__lrw-serpent-avx",
+        .cra_driver_name        = "__driver-lrw-serpent-avx",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct serpent_lrw_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(serpent_algs[3].cra_list),
+        .cra_exit               = lrw_exit_tfm,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE +
+                                          SERPENT_BLOCK_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE +
+                                          SERPENT_BLOCK_SIZE,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = lrw_serpent_setkey,
+                        .encrypt        = lrw_encrypt,
+                        .decrypt        = lrw_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__xts-serpent-avx",
+        .cra_driver_name        = "__driver-xts-serpent-avx",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct serpent_xts_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(serpent_algs[4].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE * 2,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE * 2,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = xts_serpent_setkey,
+                        .encrypt        = xts_encrypt,
+                        .decrypt        = xts_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ecb(serpent)",
+        .cra_driver_name        = "ecb-serpent-avx",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(serpent_algs[5].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "cbc(serpent)",
+        .cra_driver_name        = "cbc-serpent-avx",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(serpent_algs[6].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = __ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ctr(serpent)",
+        .cra_driver_name        = "ctr-serpent-avx",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(serpent_algs[7].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_encrypt,
+                        .geniv          = "chainiv",
+                },
+        },
+}, {
+        .cra_name               = "lrw(serpent)",
+        .cra_driver_name        = "lrw-serpent-avx",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(serpent_algs[8].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE +
+                                          SERPENT_BLOCK_SIZE,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE +
+                                          SERPENT_BLOCK_SIZE,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "xts(serpent)",
+        .cra_driver_name        = "xts-serpent-avx",
+        .cra_priority           = 500,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = SERPENT_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(serpent_algs[9].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = SERPENT_MIN_KEY_SIZE * 2,
+                        .max_keysize    = SERPENT_MAX_KEY_SIZE * 2,
+                        .ivsize         = SERPENT_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+} };
+
+static int __init serpent_init(void)
+{
+        u64 xcr0;
+
+        if (!cpu_has_avx || !cpu_has_osxsave) {
+                printk(KERN_INFO "AVX instructions are not detected.\n");
+                return -ENODEV;
+        }
+
+        xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
+        if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
+                printk(KERN_INFO "AVX detected but unusable.\n");
+                return -ENODEV;
+        }
+
+        return crypto_register_algs(serpent_algs, ARRAY_SIZE(serpent_algs));
+}
+
+static void __exit serpent_exit(void)
+{
+        crypto_unregister_algs(serpent_algs, ARRAY_SIZE(serpent_algs));
+}
+
+module_init(serpent_init);
+module_exit(serpent_exit);
+
+MODULE_DESCRIPTION("Serpent Cipher Algorithm, AVX optimized");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("serpent");
diff --git a/arch/x86/crypto/serpent_sse2_glue.c b/arch/x86/crypto/serpent_sse2_glue.c
index 4b21be85e0a..d679c8675f4 100644
--- a/arch/x86/crypto/serpent_sse2_glue.c
+++ b/arch/x86/crypto/serpent_sse2_glue.c
@@ -41,358 +41,145 @@
 #include <crypto/ctr.h>
 #include <crypto/lrw.h>
 #include <crypto/xts.h>
-#include <asm/i387.h>
-#include <asm/serpent.h>
-#include <crypto/scatterwalk.h>
-#include <linux/workqueue.h>
-#include <linux/spinlock.h>
-
-struct async_serpent_ctx {
-        struct cryptd_ablkcipher *cryptd_tfm;
-};
+#include <asm/crypto/serpent-sse2.h>
+#include <asm/crypto/ablk_helper.h>
+#include <asm/crypto/glue_helper.h>
 
-static inline bool serpent_fpu_begin(bool fpu_enabled, unsigned int nbytes)
-{
-        if (fpu_enabled)
-                return true;
-
-        /* SSE2 is only used when chunk to be processed is large enough, so
-         * do not enable FPU until it is necessary.
-         */
-        if (nbytes < SERPENT_BLOCK_SIZE * SERPENT_PARALLEL_BLOCKS)
-                return false;
-
-        kernel_fpu_begin();
-        return true;
-}
-
-static inline void serpent_fpu_end(bool fpu_enabled)
+static void serpent_decrypt_cbc_xway(void *ctx, u128 *dst, const u128 *src)
 {
-        if (fpu_enabled)
-                kernel_fpu_end();
-}
-
-static int ecb_crypt(struct blkcipher_desc *desc, struct blkcipher_walk *walk,
-                     bool enc)
-{
-        bool fpu_enabled = false;
-        struct serpent_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        const unsigned int bsize = SERPENT_BLOCK_SIZE;
-        unsigned int nbytes;
-        int err;
-
-        err = blkcipher_walk_virt(desc, walk);
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-
-        while ((nbytes = walk->nbytes)) {
-                u8 *wsrc = walk->src.virt.addr;
-                u8 *wdst = walk->dst.virt.addr;
-
-                fpu_enabled = serpent_fpu_begin(fpu_enabled, nbytes);
-
-                /* Process multi-block batch */
-                if (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS) {
-                        do {
-                                if (enc)
-                                        serpent_enc_blk_xway(ctx, wdst, wsrc);
-                                else
-                                        serpent_dec_blk_xway(ctx, wdst, wsrc);
-
-                                wsrc += bsize * SERPENT_PARALLEL_BLOCKS;
-                                wdst += bsize * SERPENT_PARALLEL_BLOCKS;
-                                nbytes -= bsize * SERPENT_PARALLEL_BLOCKS;
-                        } while (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS);
-
-                        if (nbytes < bsize)
-                                goto done;
-                }
-
-                /* Handle leftovers */
-                do {
-                        if (enc)
-                                __serpent_encrypt(ctx, wdst, wsrc);
-                        else
-                                __serpent_decrypt(ctx, wdst, wsrc);
-
-                        wsrc += bsize;
-                        wdst += bsize;
-                        nbytes -= bsize;
-                } while (nbytes >= bsize);
-
-done:
-                err = blkcipher_walk_done(desc, walk, nbytes);
-        }
+        u128 ivs[SERPENT_PARALLEL_BLOCKS - 1];
+        unsigned int j;
 
-        serpent_fpu_end(fpu_enabled);
-        return err;
-}
+        for (j = 0; j < SERPENT_PARALLEL_BLOCKS - 1; j++)
+                ivs[j] = src[j];
 
-static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct blkcipher_walk walk;
+        serpent_dec_blk_xway(ctx, (u8 *)dst, (u8 *)src);
 
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return ecb_crypt(desc, &walk, true);
+        for (j = 0; j < SERPENT_PARALLEL_BLOCKS - 1; j++)
+                u128_xor(dst + (j + 1), dst + (j + 1), ivs + j);
 }
 
-static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
+static void serpent_crypt_ctr(void *ctx, u128 *dst, const u128 *src, u128 *iv)
 {
-        struct blkcipher_walk walk;
+        be128 ctrblk;
 
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return ecb_crypt(desc, &walk, false);
-}
+        u128_to_be128(&ctrblk, iv);
+        u128_inc(iv);
 
-static unsigned int __cbc_encrypt(struct blkcipher_desc *desc,
-                                  struct blkcipher_walk *walk)
-{
-        struct serpent_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        const unsigned int bsize = SERPENT_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u128 *src = (u128 *)walk->src.virt.addr;
-        u128 *dst = (u128 *)walk->dst.virt.addr;
-        u128 *iv = (u128 *)walk->iv;
-
-        do {
-                u128_xor(dst, src, iv);
-                __serpent_encrypt(ctx, (u8 *)dst, (u8 *)dst);
-                iv = dst;
-
-                src += 1;
-                dst += 1;
-                nbytes -= bsize;
-        } while (nbytes >= bsize);
-
-        u128_xor((u128 *)walk->iv, (u128 *)walk->iv, iv);
-        return nbytes;
+        __serpent_encrypt(ctx, (u8 *)&ctrblk, (u8 *)&ctrblk);
+        u128_xor(dst, src, (u128 *)&ctrblk);
 }
 
-static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
+static void serpent_crypt_ctr_xway(void *ctx, u128 *dst, const u128 *src,
+                                   u128 *iv)
 {
-        struct blkcipher_walk walk;
-        int err;
+        be128 ctrblks[SERPENT_PARALLEL_BLOCKS];
+        unsigned int i;
 
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt(desc, &walk);
+        for (i = 0; i < SERPENT_PARALLEL_BLOCKS; i++) {
+                if (dst != src)
+                        dst[i] = src[i];
 
-        while ((nbytes = walk.nbytes)) {
-                nbytes = __cbc_encrypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
+                u128_to_be128(&ctrblks[i], iv);
+                u128_inc(iv);
         }
 
-        return err;
+        serpent_enc_blk_xway_xor(ctx, (u8 *)dst, (u8 *)ctrblks);
 }
 
-static unsigned int __cbc_decrypt(struct blkcipher_desc *desc,
-                                  struct blkcipher_walk *walk)
-{
-        struct serpent_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        const unsigned int bsize = SERPENT_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u128 *src = (u128 *)walk->src.virt.addr;
-        u128 *dst = (u128 *)walk->dst.virt.addr;
-        u128 ivs[SERPENT_PARALLEL_BLOCKS - 1];
-        u128 last_iv;
-        int i;
-
-        /* Start of the last block. */
-        src += nbytes / bsize - 1;
-        dst += nbytes / bsize - 1;
-
-        last_iv = *src;
-
-        /* Process multi-block batch */
-        if (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS) {
-                do {
-                        nbytes -= bsize * (SERPENT_PARALLEL_BLOCKS - 1);
-                        src -= SERPENT_PARALLEL_BLOCKS - 1;
-                        dst -= SERPENT_PARALLEL_BLOCKS - 1;
-
-                        for (i = 0; i < SERPENT_PARALLEL_BLOCKS - 1; i++)
-                                ivs[i] = src[i];
-
-                        serpent_dec_blk_xway(ctx, (u8 *)dst, (u8 *)src);
-
-                        for (i = 0; i < SERPENT_PARALLEL_BLOCKS - 1; i++)
-                                u128_xor(dst + (i + 1), dst + (i + 1), ivs + i);
-
-                        nbytes -= bsize;
-                        if (nbytes < bsize)
-                                goto done;
+static const struct common_glue_ctx serpent_enc = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = SERPENT_PARALLEL_BLOCKS,
 
-                        u128_xor(dst, dst, src - 1);
-                        src -= 1;
-                        dst -= 1;
-                } while (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS);
-
-                if (nbytes < bsize)
-                        goto done;
-        }
-
-        /* Handle leftovers */
-        for (;;) {
-                __serpent_decrypt(ctx, (u8 *)dst, (u8 *)src);
-
-                nbytes -= bsize;
-                if (nbytes < bsize)
-                        break;
+        .funcs = { {
+                .num_blocks = SERPENT_PARALLEL_BLOCKS,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(serpent_enc_blk_xway) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(__serpent_encrypt) }
+        } }
+};
 
-                u128_xor(dst, dst, src - 1);
-                src -= 1;
-                dst -= 1;
-        }
+static const struct common_glue_ctx serpent_ctr = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = SERPENT_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = SERPENT_PARALLEL_BLOCKS,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_crypt_ctr_xway) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(serpent_crypt_ctr) }
+        } }
+};
 
-done:
-        u128_xor(dst, dst, (u128 *)walk->iv);
-        *(u128 *)walk->iv = last_iv;
+static const struct common_glue_ctx serpent_dec = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = SERPENT_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = SERPENT_PARALLEL_BLOCKS,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(serpent_dec_blk_xway) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(__serpent_decrypt) }
+        } }
+};
 
-        return nbytes;
-}
+static const struct common_glue_ctx serpent_dec_cbc = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = SERPENT_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = SERPENT_PARALLEL_BLOCKS,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(serpent_decrypt_cbc_xway) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(__serpent_decrypt) }
+        } }
+};
 
-static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
 {
-        bool fpu_enabled = false;
-        struct blkcipher_walk walk;
-        int err;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt(desc, &walk);
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-
-        while ((nbytes = walk.nbytes)) {
-                fpu_enabled = serpent_fpu_begin(fpu_enabled, nbytes);
-                nbytes = __cbc_decrypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
-
-        serpent_fpu_end(fpu_enabled);
-        return err;
+        return glue_ecb_crypt_128bit(&serpent_enc, desc, dst, src, nbytes);
 }
 
-static inline void u128_to_be128(be128 *dst, const u128 *src)
+static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        dst->a = cpu_to_be64(src->a);
-        dst->b = cpu_to_be64(src->b);
+        return glue_ecb_crypt_128bit(&serpent_dec, desc, dst, src, nbytes);
 }
 
-static inline void be128_to_u128(u128 *dst, const be128 *src)
+static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        dst->a = be64_to_cpu(src->a);
-        dst->b = be64_to_cpu(src->b);
+        return glue_cbc_encrypt_128bit(GLUE_FUNC_CAST(__serpent_encrypt), desc,
+                                     dst, src, nbytes);
 }
 
-static inline void u128_inc(u128 *i)
+static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        i->b++;
-        if (!i->b)
-                i->a++;
+        return glue_cbc_decrypt_128bit(&serpent_dec_cbc, desc, dst, src,
+                                       nbytes);
 }
 
-static void ctr_crypt_final(struct blkcipher_desc *desc,
-                            struct blkcipher_walk *walk)
+static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                     struct scatterlist *src, unsigned int nbytes)
 {
-        struct serpent_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        u8 *ctrblk = walk->iv;
-        u8 keystream[SERPENT_BLOCK_SIZE];
-        u8 *src = walk->src.virt.addr;
-        u8 *dst = walk->dst.virt.addr;
-        unsigned int nbytes = walk->nbytes;
-
-        __serpent_encrypt(ctx, keystream, ctrblk);
-        crypto_xor(keystream, src, nbytes);
-        memcpy(dst, keystream, nbytes);
-
-        crypto_inc(ctrblk, SERPENT_BLOCK_SIZE);
+        return glue_ctr_crypt_128bit(&serpent_ctr, desc, dst, src, nbytes);
 }
 
-static unsigned int __ctr_crypt(struct blkcipher_desc *desc,
-                                struct blkcipher_walk *walk)
+static inline bool serpent_fpu_begin(bool fpu_enabled, unsigned int nbytes)
 {
-        struct serpent_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        const unsigned int bsize = SERPENT_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u128 *src = (u128 *)walk->src.virt.addr;
-        u128 *dst = (u128 *)walk->dst.virt.addr;
-        u128 ctrblk;
-        be128 ctrblocks[SERPENT_PARALLEL_BLOCKS];
-        int i;
-
-        be128_to_u128(&ctrblk, (be128 *)walk->iv);
-
-        /* Process multi-block batch */
-        if (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS) {
-                do {
-                        /* create ctrblks for parallel encrypt */
-                        for (i = 0; i < SERPENT_PARALLEL_BLOCKS; i++) {
-                                if (dst != src)
-                                        dst[i] = src[i];
-
-                                u128_to_be128(&ctrblocks[i], &ctrblk);
-                                u128_inc(&ctrblk);
-                        }
-
-                        serpent_enc_blk_xway_xor(ctx, (u8 *)dst,
-                                                 (u8 *)ctrblocks);
-
-                        src += SERPENT_PARALLEL_BLOCKS;
-                        dst += SERPENT_PARALLEL_BLOCKS;
-                        nbytes -= bsize * SERPENT_PARALLEL_BLOCKS;
-                } while (nbytes >= bsize * SERPENT_PARALLEL_BLOCKS);
-
-                if (nbytes < bsize)
-                        goto done;
-        }
-
-        /* Handle leftovers */
-        do {
-                if (dst != src)
-                        *dst = *src;
-
-                u128_to_be128(&ctrblocks[0], &ctrblk);
-                u128_inc(&ctrblk);
-
-                __serpent_encrypt(ctx, (u8 *)ctrblocks, (u8 *)ctrblocks);
-                u128_xor(dst, dst, (u128 *)ctrblocks);
-
-                src += 1;
-                dst += 1;
-                nbytes -= bsize;
-        } while (nbytes >= bsize);
-
-done:
-        u128_to_be128((be128 *)walk->iv, &ctrblk);
-        return nbytes;
+        return glue_fpu_begin(SERPENT_BLOCK_SIZE, SERPENT_PARALLEL_BLOCKS,
+                              NULL, fpu_enabled, nbytes);
 }
 
-static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                     struct scatterlist *src, unsigned int nbytes)
+static inline void serpent_fpu_end(bool fpu_enabled)
 {
-        bool fpu_enabled = false;
-        struct blkcipher_walk walk;
-        int err;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt_block(desc, &walk, SERPENT_BLOCK_SIZE);
-        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
-
-        while ((nbytes = walk.nbytes) >= SERPENT_BLOCK_SIZE) {
-                fpu_enabled = serpent_fpu_begin(fpu_enabled, nbytes);
-                nbytes = __ctr_crypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
-
-        serpent_fpu_end(fpu_enabled);
-
-        if (walk.nbytes) {
-                ctr_crypt_final(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, 0);
-        }
-
-        return err;
+        glue_fpu_end(fpu_enabled);
 }
 
 struct crypt_priv {
@@ -596,106 +383,6 @@ static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
         return ret;
 }
 
-static int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key,
-                        unsigned int key_len)
-{
-        struct async_serpent_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-        struct crypto_ablkcipher *child = &ctx->cryptd_tfm->base;
-        int err;
-
-        crypto_ablkcipher_clear_flags(child, CRYPTO_TFM_REQ_MASK);
-        crypto_ablkcipher_set_flags(child, crypto_ablkcipher_get_flags(tfm)
-                                    & CRYPTO_TFM_REQ_MASK);
-        err = crypto_ablkcipher_setkey(child, key, key_len);
-        crypto_ablkcipher_set_flags(tfm, crypto_ablkcipher_get_flags(child)
-                                    & CRYPTO_TFM_RES_MASK);
-        return err;
-}
-
-static int __ablk_encrypt(struct ablkcipher_request *req)
-{
-        struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
-        struct async_serpent_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-        struct blkcipher_desc desc;
-
-        desc.tfm = cryptd_ablkcipher_child(ctx->cryptd_tfm);
-        desc.info = req->info;
-        desc.flags = 0;
-
-        return crypto_blkcipher_crt(desc.tfm)->encrypt(
-                &desc, req->dst, req->src, req->nbytes);
-}
-
-static int ablk_encrypt(struct ablkcipher_request *req)
-{
-        struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
-        struct async_serpent_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-
-        if (!irq_fpu_usable()) {
-                struct ablkcipher_request *cryptd_req =
-                        ablkcipher_request_ctx(req);
-
-                memcpy(cryptd_req, req, sizeof(*req));
-                ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
-
-                return crypto_ablkcipher_encrypt(cryptd_req);
-        } else {
-                return __ablk_encrypt(req);
-        }
-}
-
-static int ablk_decrypt(struct ablkcipher_request *req)
-{
-        struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
-        struct async_serpent_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-
-        if (!irq_fpu_usable()) {
-                struct ablkcipher_request *cryptd_req =
-                        ablkcipher_request_ctx(req);
-
-                memcpy(cryptd_req, req, sizeof(*req));
-                ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
-
-                return crypto_ablkcipher_decrypt(cryptd_req);
-        } else {
-                struct blkcipher_desc desc;
-
-                desc.tfm = cryptd_ablkcipher_child(ctx->cryptd_tfm);
-                desc.info = req->info;
-                desc.flags = 0;
-
-                return crypto_blkcipher_crt(desc.tfm)->decrypt(
-                        &desc, req->dst, req->src, req->nbytes);
-        }
-}
-
-static void ablk_exit(struct crypto_tfm *tfm)
-{
-        struct async_serpent_ctx *ctx = crypto_tfm_ctx(tfm);
-
-        cryptd_free_ablkcipher(ctx->cryptd_tfm);
-}
-
-static int ablk_init(struct crypto_tfm *tfm)
-{
-        struct async_serpent_ctx *ctx = crypto_tfm_ctx(tfm);
-        struct cryptd_ablkcipher *cryptd_tfm;
-        char drv_name[CRYPTO_MAX_ALG_NAME];
-
-        snprintf(drv_name, sizeof(drv_name), "__driver-%s",
-                                        crypto_tfm_alg_driver_name(tfm));
-
-        cryptd_tfm = cryptd_alloc_ablkcipher(drv_name, 0, 0);
-        if (IS_ERR(cryptd_tfm))
-                return PTR_ERR(cryptd_tfm);
-
-        ctx->cryptd_tfm = cryptd_tfm;
-        tfm->crt_ablkcipher.reqsize = sizeof(struct ablkcipher_request) +
-                crypto_ablkcipher_reqsize(&cryptd_tfm->base);
-
-        return 0;
-}
-
 static struct crypto_alg serpent_algs[10] = { {
         .cra_name               = "__ecb-serpent-sse2",
         .cra_driver_name        = "__driver-ecb-serpent-sse2",
@@ -808,7 +495,7 @@ static struct crypto_alg serpent_algs[10] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = SERPENT_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_serpent_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
@@ -830,7 +517,7 @@ static struct crypto_alg serpent_algs[10] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = SERPENT_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_serpent_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
@@ -853,7 +540,7 @@ static struct crypto_alg serpent_algs[10] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = 1,
-        .cra_ctxsize            = sizeof(struct async_serpent_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
@@ -877,7 +564,7 @@ static struct crypto_alg serpent_algs[10] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = SERPENT_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_serpent_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
@@ -902,7 +589,7 @@ static struct crypto_alg serpent_algs[10] = { {
         .cra_priority           = 400,
         .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
         .cra_blocksize          = SERPENT_BLOCK_SIZE,
-        .cra_ctxsize            = sizeof(struct async_serpent_ctx),
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
         .cra_alignmask          = 0,
         .cra_type               = &crypto_ablkcipher_type,
         .cra_module             = THIS_MODULE,
diff --git a/arch/x86/crypto/sha1_ssse3_asm.S b/arch/x86/crypto/sha1_ssse3_asm.S
index b2c2f57d70e..49d6987a73d 100644
--- a/arch/x86/crypto/sha1_ssse3_asm.S
+++ b/arch/x86/crypto/sha1_ssse3_asm.S
@@ -468,7 +468,7 @@ W_PRECALC_SSSE3
  */
 SHA1_VECTOR_ASM     sha1_transform_ssse3
 
-#ifdef SHA1_ENABLE_AVX_SUPPORT
+#ifdef CONFIG_AS_AVX
 
 .macro W_PRECALC_AVX
 
diff --git a/arch/x86/crypto/sha1_ssse3_glue.c b/arch/x86/crypto/sha1_ssse3_glue.c
index f916499d0ab..4a11a9d7245 100644
--- a/arch/x86/crypto/sha1_ssse3_glue.c
+++ b/arch/x86/crypto/sha1_ssse3_glue.c
@@ -35,7 +35,7 @@
 
 asmlinkage void sha1_transform_ssse3(u32 *digest, const char *data,
                                      unsigned int rounds);
-#ifdef SHA1_ENABLE_AVX_SUPPORT
+#ifdef CONFIG_AS_AVX
 asmlinkage void sha1_transform_avx(u32 *digest, const char *data,
                                    unsigned int rounds);
 #endif
@@ -184,7 +184,7 @@ static struct shash_alg alg = {
         }
 };
 
-#ifdef SHA1_ENABLE_AVX_SUPPORT
+#ifdef CONFIG_AS_AVX
 static bool __init avx_usable(void)
 {
         u64 xcr0;
@@ -209,7 +209,7 @@ static int __init sha1_ssse3_mod_init(void)
         if (cpu_has_ssse3)
                 sha1_transform_asm = sha1_transform_ssse3;
 
-#ifdef SHA1_ENABLE_AVX_SUPPORT
+#ifdef CONFIG_AS_AVX
         /* allow AVX to override SSSE3, it's a little faster */
         if (avx_usable())
                 sha1_transform_asm = sha1_transform_avx;
diff --git a/arch/x86/crypto/twofish-avx-x86_64-asm_64.S b/arch/x86/crypto/twofish-avx-x86_64-asm_64.S
new file mode 100644
index 00000000000..35f45574390
--- /dev/null
+++ b/arch/x86/crypto/twofish-avx-x86_64-asm_64.S
@@ -0,0 +1,300 @@
+/*
+ * Twofish Cipher 8-way parallel algorithm (AVX/x86_64)
+ *
+ * Copyright (C) 2012 Johannes Goetzfried
+ *     <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
+ * USA
+ *
+ */
+
+.file "twofish-avx-x86_64-asm_64.S"
+.text
+
+/* structure of crypto context */
+#define s0      0
+#define s1      1024
+#define s2      2048
+#define s3      3072
+#define w       4096
+#define k       4128
+
+/**********************************************************************
+  8-way AVX twofish
+ **********************************************************************/
+#define CTX %rdi
+
+#define RA1 %xmm0
+#define RB1 %xmm1
+#define RC1 %xmm2
+#define RD1 %xmm3
+
+#define RA2 %xmm4
+#define RB2 %xmm5
+#define RC2 %xmm6
+#define RD2 %xmm7
+
+#define RX %xmm8
+#define RY %xmm9
+
+#define RK1 %xmm10
+#define RK2 %xmm11
+
+#define RID1  %rax
+#define RID1b %al
+#define RID2  %rbx
+#define RID2b %bl
+
+#define RGI1   %rdx
+#define RGI1bl %dl
+#define RGI1bh %dh
+#define RGI2   %rcx
+#define RGI2bl %cl
+#define RGI2bh %ch
+
+#define RGS1  %r8
+#define RGS1d %r8d
+#define RGS2  %r9
+#define RGS2d %r9d
+#define RGS3  %r10
+#define RGS3d %r10d
+
+
+#define lookup_32bit(t0, t1, t2, t3, src, dst) \
+        movb            src ## bl,        RID1b;     \
+        movb            src ## bh,        RID2b;     \
+        movl            t0(CTX, RID1, 4), dst ## d;  \
+        xorl            t1(CTX, RID2, 4), dst ## d;  \
+        shrq $16,       src;                         \
+        movb            src ## bl,        RID1b;     \
+        movb            src ## bh,        RID2b;     \
+        xorl            t2(CTX, RID1, 4), dst ## d;  \
+        xorl            t3(CTX, RID2, 4), dst ## d;
+
+#define G(a, x, t0, t1, t2, t3) \
+        vmovq           a,    RGI1;               \
+        vpsrldq $8,     a,    x;                  \
+        vmovq           x,    RGI2;               \
+        \
+        lookup_32bit(t0, t1, t2, t3, RGI1, RGS1); \
+        shrq $16,       RGI1;                     \
+        lookup_32bit(t0, t1, t2, t3, RGI1, RGS2); \
+        shlq $32,       RGS2;                     \
+        orq             RGS1, RGS2;               \
+        \
+        lookup_32bit(t0, t1, t2, t3, RGI2, RGS1); \
+        shrq $16,       RGI2;                     \
+        lookup_32bit(t0, t1, t2, t3, RGI2, RGS3); \
+        shlq $32,       RGS3;                     \
+        orq             RGS1, RGS3;               \
+        \
+        vmovq           RGS2, x;                  \
+        vpinsrq $1,     RGS3, x, x;
+
+#define encround(a, b, c, d, x, y) \
+        G(a, x, s0, s1, s2, s3);           \
+        G(b, y, s1, s2, s3, s0);           \
+        vpaddd                  x, y,   x; \
+        vpaddd                  y, x,   y; \
+        vpaddd                  x, RK1, x; \
+        vpaddd                  y, RK2, y; \
+        vpxor                   x, c,   c; \
+        vpsrld $1,              c, x;      \
+        vpslld $(32 - 1),       c, c;      \
+        vpor                    c, x,   c; \
+        vpslld $1,              d, x;      \
+        vpsrld $(32 - 1),       d, d;      \
+        vpor                    d, x,   d; \
+        vpxor                   d, y,   d;
+
+#define decround(a, b, c, d, x, y) \
+        G(a, x, s0, s1, s2, s3);           \
+        G(b, y, s1, s2, s3, s0);           \
+        vpaddd                  x, y,   x; \
+        vpaddd                  y, x,   y; \
+        vpaddd                  y, RK2, y; \
+        vpxor                   d, y,   d; \
+        vpsrld $1,              d, y;      \
+        vpslld $(32 - 1),       d, d;      \
+        vpor                    d, y,   d; \
+        vpslld $1,              c, y;      \
+        vpsrld $(32 - 1),       c, c;      \
+        vpor                    c, y,   c; \
+        vpaddd                  x, RK1, x; \
+        vpxor                   x, c,   c;
+
+#define encrypt_round(n, a, b, c, d) \
+        vbroadcastss (k+4*(2*(n)))(CTX),   RK1;           \
+        vbroadcastss (k+4*(2*(n)+1))(CTX), RK2;           \
+        encround(a ## 1, b ## 1, c ## 1, d ## 1, RX, RY); \
+        encround(a ## 2, b ## 2, c ## 2, d ## 2, RX, RY);
+
+#define decrypt_round(n, a, b, c, d) \
+        vbroadcastss (k+4*(2*(n)))(CTX),   RK1;           \
+        vbroadcastss (k+4*(2*(n)+1))(CTX), RK2;           \
+        decround(a ## 1, b ## 1, c ## 1, d ## 1, RX, RY); \
+        decround(a ## 2, b ## 2, c ## 2, d ## 2, RX, RY);
+
+#define encrypt_cycle(n) \
+        encrypt_round((2*n), RA, RB, RC, RD);       \
+        encrypt_round(((2*n) + 1), RC, RD, RA, RB);
+
+#define decrypt_cycle(n) \
+        decrypt_round(((2*n) + 1), RC, RD, RA, RB); \
+        decrypt_round((2*n), RA, RB, RC, RD);
+
+
+#define transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
+        vpunpckldq              x1, x0, t0; \
+        vpunpckhdq              x1, x0, t2; \
+        vpunpckldq              x3, x2, t1; \
+        vpunpckhdq              x3, x2, x3; \
+        \
+        vpunpcklqdq             t1, t0, x0; \
+        vpunpckhqdq             t1, t0, x1; \
+        vpunpcklqdq             x3, t2, x2; \
+        vpunpckhqdq             x3, t2, x3;
+
+#define inpack_blocks(in, x0, x1, x2, x3, wkey, t0, t1, t2) \
+        vpxor (0*4*4)(in),      wkey, x0; \
+        vpxor (1*4*4)(in),      wkey, x1; \
+        vpxor (2*4*4)(in),      wkey, x2; \
+        vpxor (3*4*4)(in),      wkey, x3; \
+        \
+        transpose_4x4(x0, x1, x2, x3, t0, t1, t2)
+
+#define outunpack_blocks(out, x0, x1, x2, x3, wkey, t0, t1, t2) \
+        transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
+        \
+        vpxor           x0, wkey, x0;     \
+        vmovdqu         x0, (0*4*4)(out); \
+        vpxor           x1, wkey, x1;     \
+        vmovdqu         x1, (1*4*4)(out); \
+        vpxor           x2, wkey, x2;     \
+        vmovdqu         x2, (2*4*4)(out); \
+        vpxor           x3, wkey, x3;     \
+        vmovdqu         x3, (3*4*4)(out);
+
+#define outunpack_xor_blocks(out, x0, x1, x2, x3, wkey, t0, t1, t2) \
+        transpose_4x4(x0, x1, x2, x3, t0, t1, t2) \
+        \
+        vpxor           x0, wkey, x0;         \
+        vpxor           (0*4*4)(out), x0, x0; \
+        vmovdqu         x0, (0*4*4)(out);     \
+        vpxor           x1, wkey, x1;         \
+        vpxor           (1*4*4)(out), x1, x1; \
+        vmovdqu         x1, (1*4*4)(out);     \
+        vpxor           x2, wkey, x2;         \
+        vpxor           (2*4*4)(out), x2, x2; \
+        vmovdqu         x2, (2*4*4)(out);     \
+        vpxor           x3, wkey, x3;         \
+        vpxor           (3*4*4)(out), x3, x3; \
+        vmovdqu         x3, (3*4*4)(out);
+
+.align 8
+.global __twofish_enc_blk_8way
+.type   __twofish_enc_blk_8way,@function;
+
+__twofish_enc_blk_8way:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         *      %rcx: bool, if true: xor output
+         */
+
+        pushq %rbx;
+        pushq %rcx;
+
+        vmovdqu w(CTX), RK1;
+
+        leaq (4*4*4)(%rdx), %rax;
+        inpack_blocks(%rdx, RA1, RB1, RC1, RD1, RK1, RX, RY, RK2);
+        inpack_blocks(%rax, RA2, RB2, RC2, RD2, RK1, RX, RY, RK2);
+
+        xorq RID1, RID1;
+        xorq RID2, RID2;
+
+        encrypt_cycle(0);
+        encrypt_cycle(1);
+        encrypt_cycle(2);
+        encrypt_cycle(3);
+        encrypt_cycle(4);
+        encrypt_cycle(5);
+        encrypt_cycle(6);
+        encrypt_cycle(7);
+
+        vmovdqu (w+4*4)(CTX), RK1;
+
+        popq %rcx;
+        popq %rbx;
+
+        leaq (4*4*4)(%rsi), %rax;
+
+        testb %cl, %cl;
+        jnz __enc_xor8;
+
+        outunpack_blocks(%rsi, RC1, RD1, RA1, RB1, RK1, RX, RY, RK2);
+        outunpack_blocks(%rax, RC2, RD2, RA2, RB2, RK1, RX, RY, RK2);
+
+        ret;
+
+__enc_xor8:
+        outunpack_xor_blocks(%rsi, RC1, RD1, RA1, RB1, RK1, RX, RY, RK2);
+        outunpack_xor_blocks(%rax, RC2, RD2, RA2, RB2, RK1, RX, RY, RK2);
+
+        ret;
+
+.align 8
+.global twofish_dec_blk_8way
+.type   twofish_dec_blk_8way,@function;
+
+twofish_dec_blk_8way:
+        /* input:
+         *      %rdi: ctx, CTX
+         *      %rsi: dst
+         *      %rdx: src
+         */
+
+        pushq %rbx;
+
+        vmovdqu (w+4*4)(CTX), RK1;
+
+        leaq (4*4*4)(%rdx), %rax;
+        inpack_blocks(%rdx, RC1, RD1, RA1, RB1, RK1, RX, RY, RK2);
+        inpack_blocks(%rax, RC2, RD2, RA2, RB2, RK1, RX, RY, RK2);
+
+        xorq RID1, RID1;
+        xorq RID2, RID2;
+
+        decrypt_cycle(7);
+        decrypt_cycle(6);
+        decrypt_cycle(5);
+        decrypt_cycle(4);
+        decrypt_cycle(3);
+        decrypt_cycle(2);
+        decrypt_cycle(1);
+        decrypt_cycle(0);
+
+        vmovdqu (w)(CTX), RK1;
+
+        popq %rbx;
+
+        leaq (4*4*4)(%rsi), %rax;
+        outunpack_blocks(%rsi, RA1, RB1, RC1, RD1, RK1, RX, RY, RK2);
+        outunpack_blocks(%rax, RA2, RB2, RC2, RD2, RK1, RX, RY, RK2);
+
+        ret;
diff --git a/arch/x86/crypto/twofish_avx_glue.c b/arch/x86/crypto/twofish_avx_glue.c
new file mode 100644
index 00000000000..782b67ddaf6
--- /dev/null
+++ b/arch/x86/crypto/twofish_avx_glue.c
@@ -0,0 +1,624 @@
+/*
+ * Glue Code for AVX assembler version of Twofish Cipher
+ *
+ * Copyright (C) 2012 Johannes Goetzfried
+ *     <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
+ * USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/hardirq.h>
+#include <linux/types.h>
+#include <linux/crypto.h>
+#include <linux/err.h>
+#include <crypto/algapi.h>
+#include <crypto/twofish.h>
+#include <crypto/cryptd.h>
+#include <crypto/b128ops.h>
+#include <crypto/ctr.h>
+#include <crypto/lrw.h>
+#include <crypto/xts.h>
+#include <asm/i387.h>
+#include <asm/xcr.h>
+#include <asm/xsave.h>
+#include <asm/crypto/twofish.h>
+#include <asm/crypto/ablk_helper.h>
+#include <asm/crypto/glue_helper.h>
+#include <crypto/scatterwalk.h>
+#include <linux/workqueue.h>
+#include <linux/spinlock.h>
+
+#define TWOFISH_PARALLEL_BLOCKS 8
+
+static inline void twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
+                                        const u8 *src)
+{
+        __twofish_enc_blk_3way(ctx, dst, src, false);
+}
+
+/* 8-way parallel cipher functions */
+asmlinkage void __twofish_enc_blk_8way(struct twofish_ctx *ctx, u8 *dst,
+                                       const u8 *src, bool xor);
+asmlinkage void twofish_dec_blk_8way(struct twofish_ctx *ctx, u8 *dst,
+                                     const u8 *src);
+
+static inline void twofish_enc_blk_xway(struct twofish_ctx *ctx, u8 *dst,
+                                        const u8 *src)
+{
+        __twofish_enc_blk_8way(ctx, dst, src, false);
+}
+
+static inline void twofish_enc_blk_xway_xor(struct twofish_ctx *ctx, u8 *dst,
+                                            const u8 *src)
+{
+        __twofish_enc_blk_8way(ctx, dst, src, true);
+}
+
+static inline void twofish_dec_blk_xway(struct twofish_ctx *ctx, u8 *dst,
+                                        const u8 *src)
+{
+        twofish_dec_blk_8way(ctx, dst, src);
+}
+
+static void twofish_dec_blk_cbc_xway(void *ctx, u128 *dst, const u128 *src)
+{
+        u128 ivs[TWOFISH_PARALLEL_BLOCKS - 1];
+        unsigned int j;
+
+        for (j = 0; j < TWOFISH_PARALLEL_BLOCKS - 1; j++)
+                ivs[j] = src[j];
+
+        twofish_dec_blk_xway(ctx, (u8 *)dst, (u8 *)src);
+
+        for (j = 0; j < TWOFISH_PARALLEL_BLOCKS - 1; j++)
+                u128_xor(dst + (j + 1), dst + (j + 1), ivs + j);
+}
+
+static void twofish_enc_blk_ctr_xway(void *ctx, u128 *dst, const u128 *src,
+                                     u128 *iv)
+{
+        be128 ctrblks[TWOFISH_PARALLEL_BLOCKS];
+        unsigned int i;
+
+        for (i = 0; i < TWOFISH_PARALLEL_BLOCKS; i++) {
+                if (dst != src)
+                        dst[i] = src[i];
+
+                u128_to_be128(&ctrblks[i], iv);
+                u128_inc(iv);
+        }
+
+        twofish_enc_blk_xway_xor(ctx, (u8 *)dst, (u8 *)ctrblks);
+}
+
+static const struct common_glue_ctx twofish_enc = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = TWOFISH_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = TWOFISH_PARALLEL_BLOCKS,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk_xway) }
+        }, {
+                .num_blocks = 3,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk) }
+        } }
+};
+
+static const struct common_glue_ctx twofish_ctr = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = TWOFISH_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = TWOFISH_PARALLEL_BLOCKS,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_enc_blk_ctr_xway) }
+        }, {
+                .num_blocks = 3,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_enc_blk_ctr_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ctr = GLUE_CTR_FUNC_CAST(twofish_enc_blk_ctr) }
+        } }
+};
+
+static const struct common_glue_ctx twofish_dec = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = TWOFISH_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = TWOFISH_PARALLEL_BLOCKS,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_dec_blk_xway) }
+        }, {
+                .num_blocks = 3,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_dec_blk_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_dec_blk) }
+        } }
+};
+
+static const struct common_glue_ctx twofish_dec_cbc = {
+        .num_funcs = 3,
+        .fpu_blocks_limit = TWOFISH_PARALLEL_BLOCKS,
+
+        .funcs = { {
+                .num_blocks = TWOFISH_PARALLEL_BLOCKS,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_dec_blk_cbc_xway) }
+        }, {
+                .num_blocks = 3,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_dec_blk_cbc_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_dec_blk) }
+        } }
+};
+
+static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ecb_crypt_128bit(&twofish_enc, desc, dst, src, nbytes);
+}
+
+static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ecb_crypt_128bit(&twofish_dec, desc, dst, src, nbytes);
+}
+
+static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_cbc_encrypt_128bit(GLUE_FUNC_CAST(twofish_enc_blk), desc,
+                                       dst, src, nbytes);
+}
+
+static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_cbc_decrypt_128bit(&twofish_dec_cbc, desc, dst, src,
+                                       nbytes);
+}
+
+static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                     struct scatterlist *src, unsigned int nbytes)
+{
+        return glue_ctr_crypt_128bit(&twofish_ctr, desc, dst, src, nbytes);
+}
+
+static inline bool twofish_fpu_begin(bool fpu_enabled, unsigned int nbytes)
+{
+        return glue_fpu_begin(TF_BLOCK_SIZE, TWOFISH_PARALLEL_BLOCKS, NULL,
+                              fpu_enabled, nbytes);
+}
+
+static inline void twofish_fpu_end(bool fpu_enabled)
+{
+        glue_fpu_end(fpu_enabled);
+}
+
+struct crypt_priv {
+        struct twofish_ctx *ctx;
+        bool fpu_enabled;
+};
+
+static void encrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
+{
+        const unsigned int bsize = TF_BLOCK_SIZE;
+        struct crypt_priv *ctx = priv;
+        int i;
+
+        ctx->fpu_enabled = twofish_fpu_begin(ctx->fpu_enabled, nbytes);
+
+        if (nbytes == bsize * TWOFISH_PARALLEL_BLOCKS) {
+                twofish_enc_blk_xway(ctx->ctx, srcdst, srcdst);
+                return;
+        }
+
+        for (i = 0; i < nbytes / (bsize * 3); i++, srcdst += bsize * 3)
+                twofish_enc_blk_3way(ctx->ctx, srcdst, srcdst);
+
+        nbytes %= bsize * 3;
+
+        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
+                twofish_enc_blk(ctx->ctx, srcdst, srcdst);
+}
+
+static void decrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
+{
+        const unsigned int bsize = TF_BLOCK_SIZE;
+        struct crypt_priv *ctx = priv;
+        int i;
+
+        ctx->fpu_enabled = twofish_fpu_begin(ctx->fpu_enabled, nbytes);
+
+        if (nbytes == bsize * TWOFISH_PARALLEL_BLOCKS) {
+                twofish_dec_blk_xway(ctx->ctx, srcdst, srcdst);
+                return;
+        }
+
+        for (i = 0; i < nbytes / (bsize * 3); i++, srcdst += bsize * 3)
+                twofish_dec_blk_3way(ctx->ctx, srcdst, srcdst);
+
+        nbytes %= bsize * 3;
+
+        for (i = 0; i < nbytes / bsize; i++, srcdst += bsize)
+                twofish_dec_blk(ctx->ctx, srcdst, srcdst);
+}
+
+static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct twofish_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[TWOFISH_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->twofish_ctx,
+                .fpu_enabled = false,
+        };
+        struct lrw_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .table_ctx = &ctx->lrw_table,
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = encrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = lrw_crypt(desc, dst, src, nbytes, &req);
+        twofish_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct twofish_lrw_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[TWOFISH_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->twofish_ctx,
+                .fpu_enabled = false,
+        };
+        struct lrw_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .table_ctx = &ctx->lrw_table,
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = decrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = lrw_crypt(desc, dst, src, nbytes, &req);
+        twofish_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct twofish_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[TWOFISH_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->crypt_ctx,
+                .fpu_enabled = false,
+        };
+        struct xts_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .tweak_ctx = &ctx->tweak_ctx,
+                .tweak_fn = XTS_TWEAK_CAST(twofish_enc_blk),
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = encrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = xts_crypt(desc, dst, src, nbytes, &req);
+        twofish_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static int xts_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
+{
+        struct twofish_xts_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
+        be128 buf[TWOFISH_PARALLEL_BLOCKS];
+        struct crypt_priv crypt_ctx = {
+                .ctx = &ctx->crypt_ctx,
+                .fpu_enabled = false,
+        };
+        struct xts_crypt_req req = {
+                .tbuf = buf,
+                .tbuflen = sizeof(buf),
+
+                .tweak_ctx = &ctx->tweak_ctx,
+                .tweak_fn = XTS_TWEAK_CAST(twofish_enc_blk),
+                .crypt_ctx = &crypt_ctx,
+                .crypt_fn = decrypt_callback,
+        };
+        int ret;
+
+        desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        ret = xts_crypt(desc, dst, src, nbytes, &req);
+        twofish_fpu_end(crypt_ctx.fpu_enabled);
+
+        return ret;
+}
+
+static struct crypto_alg twofish_algs[10] = { {
+        .cra_name               = "__ecb-twofish-avx",
+        .cra_driver_name        = "__driver-ecb-twofish-avx",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct twofish_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(twofish_algs[0].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .setkey         = twofish_setkey,
+                        .encrypt        = ecb_encrypt,
+                        .decrypt        = ecb_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__cbc-twofish-avx",
+        .cra_driver_name        = "__driver-cbc-twofish-avx",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct twofish_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(twofish_algs[1].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .setkey         = twofish_setkey,
+                        .encrypt        = cbc_encrypt,
+                        .decrypt        = cbc_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__ctr-twofish-avx",
+        .cra_driver_name        = "__driver-ctr-twofish-avx",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct twofish_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(twofish_algs[2].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = twofish_setkey,
+                        .encrypt        = ctr_crypt,
+                        .decrypt        = ctr_crypt,
+                },
+        },
+}, {
+        .cra_name               = "__lrw-twofish-avx",
+        .cra_driver_name        = "__driver-lrw-twofish-avx",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct twofish_lrw_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(twofish_algs[3].cra_list),
+        .cra_exit               = lrw_twofish_exit_tfm,
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE +
+                                          TF_BLOCK_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE +
+                                          TF_BLOCK_SIZE,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = lrw_twofish_setkey,
+                        .encrypt        = lrw_encrypt,
+                        .decrypt        = lrw_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "__xts-twofish-avx",
+        .cra_driver_name        = "__driver-xts-twofish-avx",
+        .cra_priority           = 0,
+        .cra_flags              = CRYPTO_ALG_TYPE_BLKCIPHER,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct twofish_xts_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_blkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(twofish_algs[4].cra_list),
+        .cra_u = {
+                .blkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE * 2,
+                        .max_keysize    = TF_MAX_KEY_SIZE * 2,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = xts_twofish_setkey,
+                        .encrypt        = xts_encrypt,
+                        .decrypt        = xts_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ecb(twofish)",
+        .cra_driver_name        = "ecb-twofish-avx",
+        .cra_priority           = 400,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(twofish_algs[5].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "cbc(twofish)",
+        .cra_driver_name        = "cbc-twofish-avx",
+        .cra_priority           = 400,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(twofish_algs[6].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = __ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "ctr(twofish)",
+        .cra_driver_name        = "ctr-twofish-avx",
+        .cra_priority           = 400,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = 1,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(twofish_algs[7].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_encrypt,
+                        .geniv          = "chainiv",
+                },
+        },
+}, {
+        .cra_name               = "lrw(twofish)",
+        .cra_driver_name        = "lrw-twofish-avx",
+        .cra_priority           = 400,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(twofish_algs[8].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE +
+                                          TF_BLOCK_SIZE,
+                        .max_keysize    = TF_MAX_KEY_SIZE +
+                                          TF_BLOCK_SIZE,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+}, {
+        .cra_name               = "xts(twofish)",
+        .cra_driver_name        = "xts-twofish-avx",
+        .cra_priority           = 400,
+        .cra_flags              = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
+        .cra_blocksize          = TF_BLOCK_SIZE,
+        .cra_ctxsize            = sizeof(struct async_helper_ctx),
+        .cra_alignmask          = 0,
+        .cra_type               = &crypto_ablkcipher_type,
+        .cra_module             = THIS_MODULE,
+        .cra_list               = LIST_HEAD_INIT(twofish_algs[9].cra_list),
+        .cra_init               = ablk_init,
+        .cra_exit               = ablk_exit,
+        .cra_u = {
+                .ablkcipher = {
+                        .min_keysize    = TF_MIN_KEY_SIZE * 2,
+                        .max_keysize    = TF_MAX_KEY_SIZE * 2,
+                        .ivsize         = TF_BLOCK_SIZE,
+                        .setkey         = ablk_set_key,
+                        .encrypt        = ablk_encrypt,
+                        .decrypt        = ablk_decrypt,
+                },
+        },
+} };
+
+static int __init twofish_init(void)
+{
+        u64 xcr0;
+
+        if (!cpu_has_avx || !cpu_has_osxsave) {
+                printk(KERN_INFO "AVX instructions are not detected.\n");
+                return -ENODEV;
+        }
+
+        xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
+        if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
+                printk(KERN_INFO "AVX detected but unusable.\n");
+                return -ENODEV;
+        }
+
+        return crypto_register_algs(twofish_algs, ARRAY_SIZE(twofish_algs));
+}
+
+static void __exit twofish_exit(void)
+{
+        crypto_unregister_algs(twofish_algs, ARRAY_SIZE(twofish_algs));
+}
+
+module_init(twofish_init);
+module_exit(twofish_exit);
+
+MODULE_DESCRIPTION("Twofish Cipher Algorithm, AVX optimized");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("twofish");
diff --git a/arch/x86/crypto/twofish_glue_3way.c b/arch/x86/crypto/twofish_glue_3way.c
index 922ab24cce3..15f9347316c 100644
--- a/arch/x86/crypto/twofish_glue_3way.c
+++ b/arch/x86/crypto/twofish_glue_3way.c
@@ -3,11 +3,6 @@
  *
  * Copyright (c) 2011 Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
  *
- * CBC & ECB parts based on code (crypto/cbc.c,ecb.c) by:
- *   Copyright (c) 2006 Herbert Xu <herbert@gondor.apana.org.au>
- * CTR part based on code (crypto/ctr.c) by:
- *   (C) Copyright IBM Corp. 2007 - Joy Latten <latten@us.ibm.com>
- *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -33,20 +28,13 @@
 #include <crypto/algapi.h>
 #include <crypto/twofish.h>
 #include <crypto/b128ops.h>
+#include <asm/crypto/twofish.h>
+#include <asm/crypto/glue_helper.h>
 #include <crypto/lrw.h>
 #include <crypto/xts.h>
 
-/* regular block cipher functions from twofish_x86_64 module */
-asmlinkage void twofish_enc_blk(struct twofish_ctx *ctx, u8 *dst,
-                                const u8 *src);
-asmlinkage void twofish_dec_blk(struct twofish_ctx *ctx, u8 *dst,
-                                const u8 *src);
-
-/* 3-way parallel cipher functions */
-asmlinkage void __twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
-                                       const u8 *src, bool xor);
-asmlinkage void twofish_dec_blk_3way(struct twofish_ctx *ctx, u8 *dst,
-                                     const u8 *src);
+EXPORT_SYMBOL_GPL(__twofish_enc_blk_3way);
+EXPORT_SYMBOL_GPL(twofish_dec_blk_3way);
 
 static inline void twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
                                         const u8 *src)
@@ -60,311 +48,139 @@ static inline void twofish_enc_blk_xor_3way(struct twofish_ctx *ctx, u8 *dst,
         __twofish_enc_blk_3way(ctx, dst, src, true);
 }
 
-static int ecb_crypt(struct blkcipher_desc *desc, struct blkcipher_walk *walk,
-                     void (*fn)(struct twofish_ctx *, u8 *, const u8 *),
-                     void (*fn_3way)(struct twofish_ctx *, u8 *, const u8 *))
-{
-        struct twofish_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        unsigned int bsize = TF_BLOCK_SIZE;
-        unsigned int nbytes;
-        int err;
-
-        err = blkcipher_walk_virt(desc, walk);
-
-        while ((nbytes = walk->nbytes)) {
-                u8 *wsrc = walk->src.virt.addr;
-                u8 *wdst = walk->dst.virt.addr;
-
-                /* Process three block batch */
-                if (nbytes >= bsize * 3) {
-                        do {
-                                fn_3way(ctx, wdst, wsrc);
-
-                                wsrc += bsize * 3;
-                                wdst += bsize * 3;
-                                nbytes -= bsize * 3;
-                        } while (nbytes >= bsize * 3);
-
-                        if (nbytes < bsize)
-                                goto done;
-                }
-
-                /* Handle leftovers */
-                do {
-                        fn(ctx, wdst, wsrc);
-
-                        wsrc += bsize;
-                        wdst += bsize;
-                        nbytes -= bsize;
-                } while (nbytes >= bsize);
-
-done:
-                err = blkcipher_walk_done(desc, walk, nbytes);
-        }
-
-        return err;
-}
-
-static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
+void twofish_dec_blk_cbc_3way(void *ctx, u128 *dst, const u128 *src)
 {
-        struct blkcipher_walk walk;
+        u128 ivs[2];
 
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return ecb_crypt(desc, &walk, twofish_enc_blk, twofish_enc_blk_3way);
-}
+        ivs[0] = src[0];
+        ivs[1] = src[1];
 
-static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct blkcipher_walk walk;
+        twofish_dec_blk_3way(ctx, (u8 *)dst, (u8 *)src);
 
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        return ecb_crypt(desc, &walk, twofish_dec_blk, twofish_dec_blk_3way);
+        u128_xor(&dst[1], &dst[1], &ivs[0]);
+        u128_xor(&dst[2], &dst[2], &ivs[1]);
 }
+EXPORT_SYMBOL_GPL(twofish_dec_blk_cbc_3way);
 
-static unsigned int __cbc_encrypt(struct blkcipher_desc *desc,
-                                  struct blkcipher_walk *walk)
-{
-        struct twofish_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        unsigned int bsize = TF_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u128 *src = (u128 *)walk->src.virt.addr;
-        u128 *dst = (u128 *)walk->dst.virt.addr;
-        u128 *iv = (u128 *)walk->iv;
-
-        do {
-                u128_xor(dst, src, iv);
-                twofish_enc_blk(ctx, (u8 *)dst, (u8 *)dst);
-                iv = dst;
-
-                src += 1;
-                dst += 1;
-                nbytes -= bsize;
-        } while (nbytes >= bsize);
-
-        u128_xor((u128 *)walk->iv, (u128 *)walk->iv, iv);
-        return nbytes;
-}
-
-static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
+void twofish_enc_blk_ctr(void *ctx, u128 *dst, const u128 *src, u128 *iv)
 {
-        struct blkcipher_walk walk;
-        int err;
+        be128 ctrblk;
 
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt(desc, &walk);
+        if (dst != src)
+                *dst = *src;
 
-        while ((nbytes = walk.nbytes)) {
-                nbytes = __cbc_encrypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
+        u128_to_be128(&ctrblk, iv);
+        u128_inc(iv);
 
-        return err;
+        twofish_enc_blk(ctx, (u8 *)&ctrblk, (u8 *)&ctrblk);
+        u128_xor(dst, dst, (u128 *)&ctrblk);
 }
+EXPORT_SYMBOL_GPL(twofish_enc_blk_ctr);
 
-static unsigned int __cbc_decrypt(struct blkcipher_desc *desc,
-                                  struct blkcipher_walk *walk)
+void twofish_enc_blk_ctr_3way(void *ctx, u128 *dst, const u128 *src,
+                                     u128 *iv)
 {
-        struct twofish_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        unsigned int bsize = TF_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u128 *src = (u128 *)walk->src.virt.addr;
-        u128 *dst = (u128 *)walk->dst.virt.addr;
-        u128 ivs[3 - 1];
-        u128 last_iv;
-
-        /* Start of the last block. */
-        src += nbytes / bsize - 1;
-        dst += nbytes / bsize - 1;
-
-        last_iv = *src;
-
-        /* Process three block batch */
-        if (nbytes >= bsize * 3) {
-                do {
-                        nbytes -= bsize * (3 - 1);
-                        src -= 3 - 1;
-                        dst -= 3 - 1;
-
-                        ivs[0] = src[0];
-                        ivs[1] = src[1];
-
-                        twofish_dec_blk_3way(ctx, (u8 *)dst, (u8 *)src);
-
-                        u128_xor(dst + 1, dst + 1, ivs + 0);
-                        u128_xor(dst + 2, dst + 2, ivs + 1);
-
-                        nbytes -= bsize;
-                        if (nbytes < bsize)
-                                goto done;
-
-                        u128_xor(dst, dst, src - 1);
-                        src -= 1;
-                        dst -= 1;
-                } while (nbytes >= bsize * 3);
-
-                if (nbytes < bsize)
-                        goto done;
-        }
-
-        /* Handle leftovers */
-        for (;;) {
-                twofish_dec_blk(ctx, (u8 *)dst, (u8 *)src);
-
-                nbytes -= bsize;
-                if (nbytes < bsize)
-                        break;
+        be128 ctrblks[3];
 
-                u128_xor(dst, dst, src - 1);
-                src -= 1;
-                dst -= 1;
+        if (dst != src) {
+                dst[0] = src[0];
+                dst[1] = src[1];
+                dst[2] = src[2];
         }
 
-done:
-        u128_xor(dst, dst, (u128 *)walk->iv);
-        *(u128 *)walk->iv = last_iv;
+        u128_to_be128(&ctrblks[0], iv);
+        u128_inc(iv);
+        u128_to_be128(&ctrblks[1], iv);
+        u128_inc(iv);
+        u128_to_be128(&ctrblks[2], iv);
+        u128_inc(iv);
 
-        return nbytes;
+        twofish_enc_blk_xor_3way(ctx, (u8 *)dst, (u8 *)ctrblks);
 }
+EXPORT_SYMBOL_GPL(twofish_enc_blk_ctr_3way);
+
+static const struct common_glue_ctx twofish_enc = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = -1,
+
+        .funcs = { {
+                .num_blocks = 3,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk) }
+        } }
+};
 
-static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
-                       struct scatterlist *src, unsigned int nbytes)
-{
-        struct blkcipher_walk walk;
-        int err;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt(desc, &walk);
+static const struct common_glue_ctx twofish_ctr = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = -1,
+
+        .funcs = { {
+                .num_blocks = 3,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk_ctr_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_enc_blk_ctr) }
+        } }
+};
 
-        while ((nbytes = walk.nbytes)) {
-                nbytes = __cbc_decrypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
+static const struct common_glue_ctx twofish_dec = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = -1,
+
+        .funcs = { {
+                .num_blocks = 3,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_dec_blk_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .ecb = GLUE_FUNC_CAST(twofish_dec_blk) }
+        } }
+};
 
-        return err;
-}
+static const struct common_glue_ctx twofish_dec_cbc = {
+        .num_funcs = 2,
+        .fpu_blocks_limit = -1,
+
+        .funcs = { {
+                .num_blocks = 3,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_dec_blk_cbc_3way) }
+        }, {
+                .num_blocks = 1,
+                .fn_u = { .cbc = GLUE_CBC_FUNC_CAST(twofish_dec_blk) }
+        } }
+};
 
-static inline void u128_to_be128(be128 *dst, const u128 *src)
+static int ecb_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        dst->a = cpu_to_be64(src->a);
-        dst->b = cpu_to_be64(src->b);
+        return glue_ecb_crypt_128bit(&twofish_enc, desc, dst, src, nbytes);
 }
 
-static inline void be128_to_u128(u128 *dst, const be128 *src)
+static int ecb_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        dst->a = be64_to_cpu(src->a);
-        dst->b = be64_to_cpu(src->b);
+        return glue_ecb_crypt_128bit(&twofish_dec, desc, dst, src, nbytes);
 }
 
-static inline void u128_inc(u128 *i)
+static int cbc_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        i->b++;
-        if (!i->b)
-                i->a++;
+        return glue_cbc_encrypt_128bit(GLUE_FUNC_CAST(twofish_enc_blk), desc,
+                                       dst, src, nbytes);
 }
 
-static void ctr_crypt_final(struct blkcipher_desc *desc,
-                            struct blkcipher_walk *walk)
+static int cbc_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
+                       struct scatterlist *src, unsigned int nbytes)
 {
-        struct twofish_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        u8 *ctrblk = walk->iv;
-        u8 keystream[TF_BLOCK_SIZE];
-        u8 *src = walk->src.virt.addr;
-        u8 *dst = walk->dst.virt.addr;
-        unsigned int nbytes = walk->nbytes;
-
-        twofish_enc_blk(ctx, keystream, ctrblk);
-        crypto_xor(keystream, src, nbytes);
-        memcpy(dst, keystream, nbytes);
-
-        crypto_inc(ctrblk, TF_BLOCK_SIZE);
-}
-
-static unsigned int __ctr_crypt(struct blkcipher_desc *desc,
-                                struct blkcipher_walk *walk)
-{
-        struct twofish_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
-        unsigned int bsize = TF_BLOCK_SIZE;
-        unsigned int nbytes = walk->nbytes;
-        u128 *src = (u128 *)walk->src.virt.addr;
-        u128 *dst = (u128 *)walk->dst.virt.addr;
-        u128 ctrblk;
-        be128 ctrblocks[3];
-
-        be128_to_u128(&ctrblk, (be128 *)walk->iv);
-
-        /* Process three block batch */
-        if (nbytes >= bsize * 3) {
-                do {
-                        if (dst != src) {
-                                dst[0] = src[0];
-                                dst[1] = src[1];
-                                dst[2] = src[2];
-                        }
-
-                        /* create ctrblks for parallel encrypt */
-                        u128_to_be128(&ctrblocks[0], &ctrblk);
-                        u128_inc(&ctrblk);
-                        u128_to_be128(&ctrblocks[1], &ctrblk);
-                        u128_inc(&ctrblk);
-                        u128_to_be128(&ctrblocks[2], &ctrblk);
-                        u128_inc(&ctrblk);
-
-                        twofish_enc_blk_xor_3way(ctx, (u8 *)dst,
-                                                 (u8 *)ctrblocks);
-
-                        src += 3;
-                        dst += 3;
-                        nbytes -= bsize * 3;
-                } while (nbytes >= bsize * 3);
-
-                if (nbytes < bsize)
-                        goto done;
-        }
-
-        /* Handle leftovers */
-        do {
-                if (dst != src)
-                        *dst = *src;
-
-                u128_to_be128(&ctrblocks[0], &ctrblk);
-                u128_inc(&ctrblk);
-
-                twofish_enc_blk(ctx, (u8 *)ctrblocks, (u8 *)ctrblocks);
-                u128_xor(dst, dst, (u128 *)ctrblocks);
-
-                src += 1;
-                dst += 1;
-                nbytes -= bsize;
-        } while (nbytes >= bsize);
-
-done:
-        u128_to_be128((be128 *)walk->iv, &ctrblk);
-        return nbytes;
+        return glue_cbc_decrypt_128bit(&twofish_dec_cbc, desc, dst, src,
+                                       nbytes);
 }
 
 static int ctr_crypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                      struct scatterlist *src, unsigned int nbytes)
 {
-        struct blkcipher_walk walk;
-        int err;
-
-        blkcipher_walk_init(&walk, dst, src, nbytes);
-        err = blkcipher_walk_virt_block(desc, &walk, TF_BLOCK_SIZE);
-
-        while ((nbytes = walk.nbytes) >= TF_BLOCK_SIZE) {
-                nbytes = __ctr_crypt(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, nbytes);
-        }
-
-        if (walk.nbytes) {
-                ctr_crypt_final(desc, &walk);
-                err = blkcipher_walk_done(desc, &walk, 0);
-        }
-
-        return err;
+        return glue_ctr_crypt_128bit(&twofish_ctr, desc, dst, src, nbytes);
 }
 
 static void encrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
@@ -397,13 +213,8 @@ static void decrypt_callback(void *priv, u8 *srcdst, unsigned int nbytes)
                 twofish_dec_blk(ctx, srcdst, srcdst);
 }
 
-struct twofish_lrw_ctx {
-        struct lrw_table_ctx lrw_table;
-        struct twofish_ctx twofish_ctx;
-};
-
-static int lrw_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
-                              unsigned int keylen)
+int lrw_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
+                       unsigned int keylen)
 {
         struct twofish_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
         int err;
@@ -415,6 +226,7 @@ static int lrw_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
 
         return lrw_init_table(&ctx->lrw_table, key + keylen - TF_BLOCK_SIZE);
 }
+EXPORT_SYMBOL_GPL(lrw_twofish_setkey);
 
 static int lrw_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
@@ -450,20 +262,16 @@ static int lrw_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
         return lrw_crypt(desc, dst, src, nbytes, &req);
 }
 
-static void lrw_exit_tfm(struct crypto_tfm *tfm)
+void lrw_twofish_exit_tfm(struct crypto_tfm *tfm)
 {
         struct twofish_lrw_ctx *ctx = crypto_tfm_ctx(tfm);
 
         lrw_free_table(&ctx->lrw_table);
 }
+EXPORT_SYMBOL_GPL(lrw_twofish_exit_tfm);
 
-struct twofish_xts_ctx {
-        struct twofish_ctx tweak_ctx;
-        struct twofish_ctx crypt_ctx;
-};
-
-static int xts_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
-                              unsigned int keylen)
+int xts_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
+                       unsigned int keylen)
 {
         struct twofish_xts_ctx *ctx = crypto_tfm_ctx(tfm);
         u32 *flags = &tfm->crt_flags;
@@ -486,6 +294,7 @@ static int xts_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
         return __twofish_setkey(&ctx->tweak_ctx, key + keylen / 2, keylen / 2,
                                 flags);
 }
+EXPORT_SYMBOL_GPL(xts_twofish_setkey);
 
 static int xts_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst,
                        struct scatterlist *src, unsigned int nbytes)
@@ -596,7 +405,7 @@ static struct crypto_alg tf_algs[5] = { {
         .cra_type               = &crypto_blkcipher_type,
         .cra_module             = THIS_MODULE,
         .cra_list               = LIST_HEAD_INIT(tf_algs[3].cra_list),
-        .cra_exit               = lrw_exit_tfm,
+        .cra_exit               = lrw_twofish_exit_tfm,
         .cra_u = {
                 .blkcipher = {
                         .min_keysize    = TF_MIN_KEY_SIZE + TF_BLOCK_SIZE,
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index 49331bedc15..70780689599 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -75,23 +75,54 @@ static inline int alternatives_text_reserved(void *start, void *end)
 }
 #endif  /* CONFIG_SMP */
 
+#define OLDINSTR(oldinstr)      "661:\n\t" oldinstr "\n662:\n"
+
+#define b_replacement(number)   "663"#number
+#define e_replacement(number)   "664"#number
+
+#define alt_slen "662b-661b"
+#define alt_rlen(number) e_replacement(number)"f-"b_replacement(number)"f"
+
+#define ALTINSTR_ENTRY(feature, number)                                       \
+        " .long 661b - .\n"                             /* label           */ \
+        " .long " b_replacement(number)"f - .\n"        /* new instruction */ \
+        " .word " __stringify(feature) "\n"             /* feature bit     */ \
+        " .byte " alt_slen "\n"                         /* source len      */ \
+        " .byte " alt_rlen(number) "\n"                 /* replacement len */
+
+#define DISCARD_ENTRY(number)                           /* rlen <= slen */    \
+        " .byte 0xff + (" alt_rlen(number) ") - (" alt_slen ")\n"
+
+#define ALTINSTR_REPLACEMENT(newinstr, feature, number) /* replacement */     \
+        b_replacement(number)":\n\t" newinstr "\n" e_replacement(number) ":\n\t"
+
 /* alternative assembly primitive: */
 #define ALTERNATIVE(oldinstr, newinstr, feature)                        \
-                                                                        \
-      "661:\n\t" oldinstr "\n662:\n"                                    \
-      ".section .altinstructions,\"a\"\n"                               \
-      "  .long 661b - .\n"                      /* label           */   \
-      "  .long 663f - .\n"                      /* new instruction */   \
-      "  .word " __stringify(feature) "\n"      /* feature bit     */   \
-      "  .byte 662b-661b\n"                     /* sourcelen       */   \
-      "  .byte 664f-663f\n"                     /* replacementlen  */   \
-      ".previous\n"                                                     \
-      ".section .discard,\"aw\",@progbits\n"                            \
-      "  .byte 0xff + (664f-663f) - (662b-661b)\n" /* rlen <= slen */   \
-      ".previous\n"                                                     \
-      ".section .altinstr_replacement, \"ax\"\n"                        \
-      "663:\n\t" newinstr "\n664:\n"            /* replacement     */   \
-      ".previous"
+        OLDINSTR(oldinstr)                                              \
+        ".section .altinstructions,\"a\"\n"                             \
+        ALTINSTR_ENTRY(feature, 1)                                      \
+        ".previous\n"                                                   \
+        ".section .discard,\"aw\",@progbits\n"                          \
+        DISCARD_ENTRY(1)                                                \
+        ".previous\n"                                                   \
+        ".section .altinstr_replacement, \"ax\"\n"                      \
+        ALTINSTR_REPLACEMENT(newinstr, feature, 1)                      \
+        ".previous"
+
+#define ALTERNATIVE_2(oldinstr, newinstr1, feature1, newinstr2, feature2)\
+        OLDINSTR(oldinstr)                                              \
+        ".section .altinstructions,\"a\"\n"                             \
+        ALTINSTR_ENTRY(feature1, 1)                                     \
+        ALTINSTR_ENTRY(feature2, 2)                                     \
+        ".previous\n"                                                   \
+        ".section .discard,\"aw\",@progbits\n"                          \
+        DISCARD_ENTRY(1)                                                \
+        DISCARD_ENTRY(2)                                                \
+        ".previous\n"                                                   \
+        ".section .altinstr_replacement, \"ax\"\n"                      \
+        ALTINSTR_REPLACEMENT(newinstr1, feature1, 1)                    \
+        ALTINSTR_REPLACEMENT(newinstr2, feature2, 2)                    \
+        ".previous"
 
 /*
  * This must be included *after* the definition of ALTERNATIVE due to
@@ -140,6 +171,19 @@ static inline int alternatives_text_reserved(void *start, void *end)
                 : output : [old] "i" (oldfunc), [new] "i" (newfunc), ## input)
 
 /*
+ * Like alternative_call, but there are two features and respective functions.
+ * If CPU has feature2, function2 is used.
+ * Otherwise, if CPU has feature1, function1 is used.
+ * Otherwise, old function is used.
+ */
+#define alternative_call_2(oldfunc, newfunc1, feature1, newfunc2, feature2,   \
+                           output, input...)                                  \
+        asm volatile (ALTERNATIVE_2("call %P[old]", "call %P[new1]", feature1,\
+                "call %P[new2]", feature2)                                    \
+                : output : [old] "i" (oldfunc), [new1] "i" (newfunc1),        \
+                [new2] "i" (newfunc2), ## input)
+
+/*
  * use this macro(s) if you need more than one output parameter
  * in alternative_io
  */
diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h
index 49ad773f4b9..b3341e9cd8f 100644
--- a/arch/x86/include/asm/amd_nb.h
+++ b/arch/x86/include/asm/amd_nb.h
@@ -26,10 +26,31 @@ struct amd_l3_cache {
         u8       subcaches[4];
 };
 
+struct threshold_block {
+        unsigned int            block;
+        unsigned int            bank;
+        unsigned int            cpu;
+        u32                     address;
+        u16                     interrupt_enable;
+        bool                    interrupt_capable;
+        u16                     threshold_limit;
+        struct kobject          kobj;
+        struct list_head        miscj;
+};
+
+struct threshold_bank {
+        struct kobject          *kobj;
+        struct threshold_block  *blocks;
+
+        /* initialized to the number of CPUs on the node sharing this bank */
+        atomic_t                cpus;
+};
+
 struct amd_northbridge {
         struct pci_dev *misc;
         struct pci_dev *link;
         struct amd_l3_cache l3_cache;
+        struct threshold_bank *bank4;
 };
 
 struct amd_northbridge_info {
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index eaff4790ed9..f34261296ff 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -306,7 +306,8 @@ struct apic {
         unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
         unsigned long (*check_apicid_present)(int apicid);
 
-        void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
+        void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
+                                         const struct cpumask *mask);
         void (*init_apic_ldr)(void);
 
         void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
@@ -331,9 +332,9 @@ struct apic {
         unsigned long (*set_apic_id)(unsigned int id);
         unsigned long apic_id_mask;
 
-        unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
-        unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
-                                               const struct cpumask *andmask);
+        int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
+                                      const struct cpumask *andmask,
+                                      unsigned int *apicid);
 
         /* ipi */
         void (*send_IPI_mask)(const struct cpumask *mask, int vector);
@@ -464,6 +465,8 @@ static inline u32 safe_apic_wait_icr_idle(void)
         return apic->safe_wait_icr_idle();
 }
 
+extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
+
 #else /* CONFIG_X86_LOCAL_APIC */
 
 static inline u32 apic_read(u32 reg) { return 0; }
@@ -473,6 +476,7 @@ static inline u64 apic_icr_read(void) { return 0; }
 static inline void apic_icr_write(u32 low, u32 high) { }
 static inline void apic_wait_icr_idle(void) { }
 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
+static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
 
 #endif /* CONFIG_X86_LOCAL_APIC */
 
@@ -537,7 +541,12 @@ static inline const struct cpumask *default_target_cpus(void)
 #endif
 }
 
-DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
+static inline const struct cpumask *online_target_cpus(void)
+{
+        return cpu_online_mask;
+}
+
+DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
 
 
 static inline unsigned int read_apic_id(void)
@@ -586,21 +595,50 @@ static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
 
 #endif
 
-static inline unsigned int
-default_cpu_mask_to_apicid(const struct cpumask *cpumask)
+static inline int
+flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
+                            const struct cpumask *andmask,
+                            unsigned int *apicid)
 {
-        return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
+        unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
+                                 cpumask_bits(andmask)[0] &
+                                 cpumask_bits(cpu_online_mask)[0] &
+                                 APIC_ALL_CPUS;
+
+        if (likely(cpu_mask)) {
+                *apicid = (unsigned int)cpu_mask;
+                return 0;
+        } else {
+                return -EINVAL;
+        }
 }
 
-static inline unsigned int
+extern int
 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                               const struct cpumask *andmask)
+                               const struct cpumask *andmask,
+                               unsigned int *apicid);
+
+static inline void
+flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
+                              const struct cpumask *mask)
 {
-        unsigned long mask1 = cpumask_bits(cpumask)[0];
-        unsigned long mask2 = cpumask_bits(andmask)[0];
-        unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
+        /* Careful. Some cpus do not strictly honor the set of cpus
+         * specified in the interrupt destination when using lowest
+         * priority interrupt delivery mode.
+         *
+         * In particular there was a hyperthreading cpu observed to
+         * deliver interrupts to the wrong hyperthread when only one
+         * hyperthread was specified in the interrupt desitination.
+         */
+        cpumask_clear(retmask);
+        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
+}
 
-        return (unsigned int)(mask1 & mask2 & mask3);
+static inline void
+default_vector_allocation_domain(int cpu, struct cpumask *retmask,
+                                 const struct cpumask *mask)
+{
+        cpumask_copy(retmask, cpumask_of(cpu));
 }
 
 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index a6983b27722..72f5009deb5 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -264,6 +264,13 @@ static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
  * This operation is non-atomic and can be reordered.
  * If two examples of this operation race, one can appear to succeed
  * but actually fail.  You must protect multiple accesses with a lock.
+ *
+ * Note: the operation is performed atomically with respect to
+ * the local CPU, but not other CPUs. Portable code should not
+ * rely on this behaviour.
+ * KVM relies on this behaviour on x86 for modifying memory that is also
+ * accessed from a hypervisor on the same CPU if running in a VM: don't change
+ * this without also updating arch/x86/kernel/kvm.c
  */
 static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
 {
diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h
index eb45aa6b1f2..2ad874cb661 100644
--- a/arch/x86/include/asm/bootparam.h
+++ b/arch/x86/include/asm/bootparam.h
@@ -66,6 +66,7 @@ struct setup_header {
         __u64   setup_data;
         __u64   pref_address;
         __u32   init_size;
+        __u32   handover_offset;
 } __attribute__((packed));
 
 struct sys_desc_table {
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index f91e80f4f18..6b7ee5ff682 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -207,6 +207,8 @@
 #define X86_FEATURE_ERMS        (9*32+ 9) /* Enhanced REP MOVSB/STOSB */
 #define X86_FEATURE_INVPCID     (9*32+10) /* Invalidate Processor Context ID */
 #define X86_FEATURE_RTM         (9*32+11) /* Restricted Transactional Memory */
+#define X86_FEATURE_RDSEED      (9*32+18) /* The RDSEED instruction */
+#define X86_FEATURE_ADX         (9*32+19) /* The ADCX and ADOX instructions */
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
diff --git a/arch/x86/include/asm/crypto/ablk_helper.h b/arch/x86/include/asm/crypto/ablk_helper.h
new file mode 100644
index 00000000000..4f93df50c23
--- /dev/null
+++ b/arch/x86/include/asm/crypto/ablk_helper.h
@@ -0,0 +1,31 @@
+/*
+ * Shared async block cipher helpers
+ */
+
+#ifndef _CRYPTO_ABLK_HELPER_H
+#define _CRYPTO_ABLK_HELPER_H
+
+#include <linux/crypto.h>
+#include <linux/kernel.h>
+#include <crypto/cryptd.h>
+
+struct async_helper_ctx {
+        struct cryptd_ablkcipher *cryptd_tfm;
+};
+
+extern int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key,
+                        unsigned int key_len);
+
+extern int __ablk_encrypt(struct ablkcipher_request *req);
+
+extern int ablk_encrypt(struct ablkcipher_request *req);
+
+extern int ablk_decrypt(struct ablkcipher_request *req);
+
+extern void ablk_exit(struct crypto_tfm *tfm);
+
+extern int ablk_init_common(struct crypto_tfm *tfm, const char *drv_name);
+
+extern int ablk_init(struct crypto_tfm *tfm);
+
+#endif /* _CRYPTO_ABLK_HELPER_H */
diff --git a/arch/x86/include/asm/aes.h b/arch/x86/include/asm/crypto/aes.h
index 80545a1cbe3..80545a1cbe3 100644
--- a/arch/x86/include/asm/aes.h
+++ b/arch/x86/include/asm/crypto/aes.h
diff --git a/arch/x86/include/asm/crypto/glue_helper.h b/arch/x86/include/asm/crypto/glue_helper.h
new file mode 100644
index 00000000000..3e408bddc96
--- /dev/null
+++ b/arch/x86/include/asm/crypto/glue_helper.h
@@ -0,0 +1,115 @@
+/*
+ * Shared glue code for 128bit block ciphers
+ */
+
+#ifndef _CRYPTO_GLUE_HELPER_H
+#define _CRYPTO_GLUE_HELPER_H
+
+#include <linux/kernel.h>
+#include <linux/crypto.h>
+#include <asm/i387.h>
+#include <crypto/b128ops.h>
+
+typedef void (*common_glue_func_t)(void *ctx, u8 *dst, const u8 *src);
+typedef void (*common_glue_cbc_func_t)(void *ctx, u128 *dst, const u128 *src);
+typedef void (*common_glue_ctr_func_t)(void *ctx, u128 *dst, const u128 *src,
+                                       u128 *iv);
+
+#define GLUE_FUNC_CAST(fn) ((common_glue_func_t)(fn))
+#define GLUE_CBC_FUNC_CAST(fn) ((common_glue_cbc_func_t)(fn))
+#define GLUE_CTR_FUNC_CAST(fn) ((common_glue_ctr_func_t)(fn))
+
+struct common_glue_func_entry {
+        unsigned int num_blocks; /* number of blocks that @fn will process */
+        union {
+                common_glue_func_t ecb;
+                common_glue_cbc_func_t cbc;
+                common_glue_ctr_func_t ctr;
+        } fn_u;
+};
+
+struct common_glue_ctx {
+        unsigned int num_funcs;
+        int fpu_blocks_limit; /* -1 means fpu not needed at all */
+
+        /*
+         * First funcs entry must have largest num_blocks and last funcs entry
+         * must have num_blocks == 1!
+         */
+        struct common_glue_func_entry funcs[];
+};
+
+static inline bool glue_fpu_begin(unsigned int bsize, int fpu_blocks_limit,
+                                  struct blkcipher_desc *desc,
+                                  bool fpu_enabled, unsigned int nbytes)
+{
+        if (likely(fpu_blocks_limit < 0))
+                return false;
+
+        if (fpu_enabled)
+                return true;
+
+        /*
+         * Vector-registers are only used when chunk to be processed is large
+         * enough, so do not enable FPU until it is necessary.
+         */
+        if (nbytes < bsize * (unsigned int)fpu_blocks_limit)
+                return false;
+
+        if (desc) {
+                /* prevent sleeping if FPU is in use */
+                desc->flags &= ~CRYPTO_TFM_REQ_MAY_SLEEP;
+        }
+
+        kernel_fpu_begin();
+        return true;
+}
+
+static inline void glue_fpu_end(bool fpu_enabled)
+{
+        if (fpu_enabled)
+                kernel_fpu_end();
+}
+
+static inline void u128_to_be128(be128 *dst, const u128 *src)
+{
+        dst->a = cpu_to_be64(src->a);
+        dst->b = cpu_to_be64(src->b);
+}
+
+static inline void be128_to_u128(u128 *dst, const be128 *src)
+{
+        dst->a = be64_to_cpu(src->a);
+        dst->b = be64_to_cpu(src->b);
+}
+
+static inline void u128_inc(u128 *i)
+{
+        i->b++;
+        if (!i->b)
+                i->a++;
+}
+
+extern int glue_ecb_crypt_128bit(const struct common_glue_ctx *gctx,
+                                 struct blkcipher_desc *desc,
+                                 struct scatterlist *dst,
+                                 struct scatterlist *src, unsigned int nbytes);
+
+extern int glue_cbc_encrypt_128bit(const common_glue_func_t fn,
+                                   struct blkcipher_desc *desc,
+                                   struct scatterlist *dst,
+                                   struct scatterlist *src,
+                                   unsigned int nbytes);
+
+extern int glue_cbc_decrypt_128bit(const struct common_glue_ctx *gctx,
+                                   struct blkcipher_desc *desc,
+                                   struct scatterlist *dst,
+                                   struct scatterlist *src,
+                                   unsigned int nbytes);
+
+extern int glue_ctr_crypt_128bit(const struct common_glue_ctx *gctx,
+                                 struct blkcipher_desc *desc,
+                                 struct scatterlist *dst,
+                                 struct scatterlist *src, unsigned int nbytes);
+
+#endif /* _CRYPTO_GLUE_HELPER_H */
diff --git a/arch/x86/include/asm/crypto/serpent-avx.h b/arch/x86/include/asm/crypto/serpent-avx.h
new file mode 100644
index 00000000000..432deedd294
--- /dev/null
+++ b/arch/x86/include/asm/crypto/serpent-avx.h
@@ -0,0 +1,32 @@
+#ifndef ASM_X86_SERPENT_AVX_H
+#define ASM_X86_SERPENT_AVX_H
+
+#include <linux/crypto.h>
+#include <crypto/serpent.h>
+
+#define SERPENT_PARALLEL_BLOCKS 8
+
+asmlinkage void __serpent_enc_blk_8way_avx(struct serpent_ctx *ctx, u8 *dst,
+                                           const u8 *src, bool xor);
+asmlinkage void serpent_dec_blk_8way_avx(struct serpent_ctx *ctx, u8 *dst,
+                                         const u8 *src);
+
+static inline void serpent_enc_blk_xway(struct serpent_ctx *ctx, u8 *dst,
+                                   const u8 *src)
+{
+        __serpent_enc_blk_8way_avx(ctx, dst, src, false);
+}
+
+static inline void serpent_enc_blk_xway_xor(struct serpent_ctx *ctx, u8 *dst,
+                                       const u8 *src)
+{
+        __serpent_enc_blk_8way_avx(ctx, dst, src, true);
+}
+
+static inline void serpent_dec_blk_xway(struct serpent_ctx *ctx, u8 *dst,
+                                   const u8 *src)
+{
+        serpent_dec_blk_8way_avx(ctx, dst, src);
+}
+
+#endif
diff --git a/arch/x86/include/asm/serpent.h b/arch/x86/include/asm/crypto/serpent-sse2.h
index d3ef63fe0c8..e6e77dffbda 100644
--- a/arch/x86/include/asm/serpent.h
+++ b/arch/x86/include/asm/crypto/serpent-sse2.h
@@ -1,5 +1,5 @@
-#ifndef ASM_X86_SERPENT_H
-#define ASM_X86_SERPENT_H
+#ifndef ASM_X86_SERPENT_SSE2_H
+#define ASM_X86_SERPENT_SSE2_H
 
 #include <linux/crypto.h>
 #include <crypto/serpent.h>
diff --git a/arch/x86/include/asm/crypto/twofish.h b/arch/x86/include/asm/crypto/twofish.h
new file mode 100644
index 00000000000..9d2c514bd5f
--- /dev/null
+++ b/arch/x86/include/asm/crypto/twofish.h
@@ -0,0 +1,46 @@
+#ifndef ASM_X86_TWOFISH_H
+#define ASM_X86_TWOFISH_H
+
+#include <linux/crypto.h>
+#include <crypto/twofish.h>
+#include <crypto/lrw.h>
+#include <crypto/b128ops.h>
+
+struct twofish_lrw_ctx {
+        struct lrw_table_ctx lrw_table;
+        struct twofish_ctx twofish_ctx;
+};
+
+struct twofish_xts_ctx {
+        struct twofish_ctx tweak_ctx;
+        struct twofish_ctx crypt_ctx;
+};
+
+/* regular block cipher functions from twofish_x86_64 module */
+asmlinkage void twofish_enc_blk(struct twofish_ctx *ctx, u8 *dst,
+                                const u8 *src);
+asmlinkage void twofish_dec_blk(struct twofish_ctx *ctx, u8 *dst,
+                                const u8 *src);
+
+/* 3-way parallel cipher functions */
+asmlinkage void __twofish_enc_blk_3way(struct twofish_ctx *ctx, u8 *dst,
+                                       const u8 *src, bool xor);
+asmlinkage void twofish_dec_blk_3way(struct twofish_ctx *ctx, u8 *dst,
+                                     const u8 *src);
+
+/* helpers from twofish_x86_64-3way module */
+extern void twofish_dec_blk_cbc_3way(void *ctx, u128 *dst, const u128 *src);
+extern void twofish_enc_blk_ctr(void *ctx, u128 *dst, const u128 *src,
+                                u128 *iv);
+extern void twofish_enc_blk_ctr_3way(void *ctx, u128 *dst, const u128 *src,
+                                     u128 *iv);
+
+extern int lrw_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
+                              unsigned int keylen);
+
+extern void lrw_twofish_exit_tfm(struct crypto_tfm *tfm);
+
+extern int xts_twofish_setkey(struct crypto_tfm *tfm, const u8 *key,
+                              unsigned int keylen);
+
+#endif /* ASM_X86_TWOFISH_H */
diff --git a/arch/x86/include/asm/emergency-restart.h b/arch/x86/include/asm/emergency-restart.h
index cc70c1c78ca..75ce3f47d20 100644
--- a/arch/x86/include/asm/emergency-restart.h
+++ b/arch/x86/include/asm/emergency-restart.h
@@ -4,9 +4,7 @@
 enum reboot_type {
         BOOT_TRIPLE = 't',
         BOOT_KBD = 'k',
-#ifdef CONFIG_X86_32
         BOOT_BIOS = 'b',
-#endif
         BOOT_ACPI = 'a',
         BOOT_EFI = 'e',
         BOOT_CF9 = 'p',
diff --git a/arch/x86/include/asm/entry_arch.h b/arch/x86/include/asm/entry_arch.h
index 0baa628e330..40afa0005c6 100644
--- a/arch/x86/include/asm/entry_arch.h
+++ b/arch/x86/include/asm/entry_arch.h
@@ -15,15 +15,6 @@ BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
 BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR)
 BUILD_INTERRUPT(irq_move_cleanup_interrupt,IRQ_MOVE_CLEANUP_VECTOR)
 BUILD_INTERRUPT(reboot_interrupt,REBOOT_VECTOR)
-
-.irp idx,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, \
-        16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
-.if NUM_INVALIDATE_TLB_VECTORS > \idx
-BUILD_INTERRUPT3(invalidate_interrupt\idx,
-                 (INVALIDATE_TLB_VECTOR_START)+\idx,
-                 smp_invalidate_interrupt)
-.endif
-.endr
 #endif
 
 BUILD_INTERRUPT(x86_platform_ipi, X86_PLATFORM_IPI_VECTOR)
diff --git a/arch/x86/include/asm/floppy.h b/arch/x86/include/asm/floppy.h
index dbe82a5c5ea..d3d74698dce 100644
--- a/arch/x86/include/asm/floppy.h
+++ b/arch/x86/include/asm/floppy.h
@@ -99,7 +99,7 @@ static irqreturn_t floppy_hardint(int irq, void *dev_id)
                 virtual_dma_residue += virtual_dma_count;
                 virtual_dma_count = 0;
 #ifdef TRACE_FLPY_INT
-                printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
+                printk(KERN_DEBUG "count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
                        virtual_dma_count, virtual_dma_residue, calls, bytes,
                        dma_wait);
                 calls = 0;
diff --git a/arch/x86/include/asm/hypervisor.h b/arch/x86/include/asm/hypervisor.h
index 7a15153c675..b518c750993 100644
--- a/arch/x86/include/asm/hypervisor.h
+++ b/arch/x86/include/asm/hypervisor.h
@@ -49,6 +49,7 @@ extern const struct hypervisor_x86 *x86_hyper;
 extern const struct hypervisor_x86 x86_hyper_vmware;
 extern const struct hypervisor_x86 x86_hyper_ms_hyperv;
 extern const struct hypervisor_x86 x86_hyper_xen_hvm;
+extern const struct hypervisor_x86 x86_hyper_kvm;
 
 static inline bool hypervisor_x2apic_available(void)
 {
diff --git a/arch/x86/include/asm/iommu.h b/arch/x86/include/asm/iommu.h
index dffc38ee625..345c99cef15 100644
--- a/arch/x86/include/asm/iommu.h
+++ b/arch/x86/include/asm/iommu.h
@@ -5,7 +5,6 @@ extern struct dma_map_ops nommu_dma_ops;
 extern int force_iommu, no_iommu;
 extern int iommu_detected;
 extern int iommu_pass_through;
-extern int iommu_group_mf;
 
 /* 10 seconds */
 #define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000)
diff --git a/arch/x86/include/asm/irq_vectors.h b/arch/x86/include/asm/irq_vectors.h
index 4b4448761e8..1508e518c7e 100644
--- a/arch/x86/include/asm/irq_vectors.h
+++ b/arch/x86/include/asm/irq_vectors.h
@@ -119,17 +119,6 @@
  */
 #define LOCAL_TIMER_VECTOR              0xef
 
-/* up to 32 vectors used for spreading out TLB flushes: */
-#if NR_CPUS <= 32
-# define NUM_INVALIDATE_TLB_VECTORS     (NR_CPUS)
-#else
-# define NUM_INVALIDATE_TLB_VECTORS     (32)
-#endif
-
-#define INVALIDATE_TLB_VECTOR_END       (0xee)
-#define INVALIDATE_TLB_VECTOR_START     \
-        (INVALIDATE_TLB_VECTOR_END-NUM_INVALIDATE_TLB_VECTORS+1)
-
 #define NR_VECTORS                       256
 
 #define FPU_IRQ                           13
diff --git a/arch/x86/include/asm/kvm.h b/arch/x86/include/asm/kvm.h
index e7d1c194d27..246617efd67 100644
--- a/arch/x86/include/asm/kvm.h
+++ b/arch/x86/include/asm/kvm.h
@@ -12,6 +12,7 @@
 /* Select x86 specific features in <linux/kvm.h> */
 #define __KVM_HAVE_PIT
 #define __KVM_HAVE_IOAPIC
+#define __KVM_HAVE_IRQ_LINE
 #define __KVM_HAVE_DEVICE_ASSIGNMENT
 #define __KVM_HAVE_MSI
 #define __KVM_HAVE_USER_NMI
diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h
index 1ac46c22dd5..c764f43b71c 100644
--- a/arch/x86/include/asm/kvm_emulate.h
+++ b/arch/x86/include/asm/kvm_emulate.h
@@ -192,8 +192,8 @@ struct x86_emulate_ops {
                          struct x86_instruction_info *info,
                          enum x86_intercept_stage stage);
 
-        bool (*get_cpuid)(struct x86_emulate_ctxt *ctxt,
-                         u32 *eax, u32 *ebx, u32 *ecx, u32 *edx);
+        void (*get_cpuid)(struct x86_emulate_ctxt *ctxt,
+                          u32 *eax, u32 *ebx, u32 *ecx, u32 *edx);
 };
 
 typedef u32 __attribute__((vector_size(16))) sse128_t;
@@ -280,9 +280,9 @@ struct x86_emulate_ctxt {
         u8 modrm_seg;
         bool rip_relative;
         unsigned long _eip;
+        struct operand memop;
         /* Fields above regs are cleared together. */
         unsigned long regs[NR_VCPU_REGS];
-        struct operand memop;
         struct operand *memopp;
         struct fetch_cache fetch;
         struct read_cache io_read;
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index db7c1f2709a..09155d64cf7 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -48,12 +48,13 @@
 
 #define CR3_PAE_RESERVED_BITS ((X86_CR3_PWT | X86_CR3_PCD) - 1)
 #define CR3_NONPAE_RESERVED_BITS ((PAGE_SIZE-1) & ~(X86_CR3_PWT | X86_CR3_PCD))
+#define CR3_PCID_ENABLED_RESERVED_BITS 0xFFFFFF0000000000ULL
 #define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS |    \
                                   0xFFFFFF0000000000ULL)
 #define CR4_RESERVED_BITS                                               \
         (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
                           | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE     \
-                          | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR  \
+                          | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \
                           | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_RDWRGSFS \
                           | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
 
@@ -175,6 +176,13 @@ enum {
 
 /* apic attention bits */
 #define KVM_APIC_CHECK_VAPIC    0
+/*
+ * The following bit is set with PV-EOI, unset on EOI.
+ * We detect PV-EOI changes by guest by comparing
+ * this bit with PV-EOI in guest memory.
+ * See the implementation in apic_update_pv_eoi.
+ */
+#define KVM_APIC_PV_EOI_PENDING 1
 
 /*
  * We don't want allocation failures within the mmu code, so we preallocate
@@ -313,8 +321,8 @@ struct kvm_pmu {
         u64 counter_bitmask[2];
         u64 global_ctrl_mask;
         u8 version;
-        struct kvm_pmc gp_counters[X86_PMC_MAX_GENERIC];
-        struct kvm_pmc fixed_counters[X86_PMC_MAX_FIXED];
+        struct kvm_pmc gp_counters[INTEL_PMC_MAX_GENERIC];
+        struct kvm_pmc fixed_counters[INTEL_PMC_MAX_FIXED];
         struct irq_work irq_work;
         u64 reprogram_pmi;
 };
@@ -484,6 +492,11 @@ struct kvm_vcpu_arch {
                 u64 length;
                 u64 status;
         } osvw;
+
+        struct {
+                u64 msr_val;
+                struct gfn_to_hva_cache data;
+        } pv_eoi;
 };
 
 struct kvm_lpage_info {
@@ -661,6 +674,7 @@ struct kvm_x86_ops {
         u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
         int (*get_lpage_level)(void);
         bool (*rdtscp_supported)(void);
+        bool (*invpcid_supported)(void);
         void (*adjust_tsc_offset)(struct kvm_vcpu *vcpu, s64 adjustment, bool host);
 
         void (*set_tdp_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
@@ -802,7 +816,20 @@ int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
 
-int kvm_pic_set_irq(void *opaque, int irq, int level);
+static inline int __kvm_irq_line_state(unsigned long *irq_state,
+                                       int irq_source_id, int level)
+{
+        /* Logical OR for level trig interrupt */
+        if (level)
+                __set_bit(irq_source_id, irq_state);
+        else
+                __clear_bit(irq_source_id, irq_state);
+
+        return !!(*irq_state);
+}
+
+int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level);
+void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id);
 
 void kvm_inject_nmi(struct kvm_vcpu *vcpu);
 
diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h
index 63ab1661d00..2f7712e08b1 100644
--- a/arch/x86/include/asm/kvm_para.h
+++ b/arch/x86/include/asm/kvm_para.h
@@ -22,6 +22,7 @@
 #define KVM_FEATURE_CLOCKSOURCE2        3
 #define KVM_FEATURE_ASYNC_PF            4
 #define KVM_FEATURE_STEAL_TIME          5
+#define KVM_FEATURE_PV_EOI              6
 
 /* The last 8 bits are used to indicate how to interpret the flags field
  * in pvclock structure. If no bits are set, all flags are ignored.
@@ -37,6 +38,7 @@
 #define MSR_KVM_SYSTEM_TIME_NEW 0x4b564d01
 #define MSR_KVM_ASYNC_PF_EN 0x4b564d02
 #define MSR_KVM_STEAL_TIME  0x4b564d03
+#define MSR_KVM_PV_EOI_EN      0x4b564d04
 
 struct kvm_steal_time {
         __u64 steal;
@@ -89,6 +91,11 @@ struct kvm_vcpu_pv_apf_data {
         __u32 enabled;
 };
 
+#define KVM_PV_EOI_BIT 0
+#define KVM_PV_EOI_MASK (0x1 << KVM_PV_EOI_BIT)
+#define KVM_PV_EOI_ENABLED KVM_PV_EOI_MASK
+#define KVM_PV_EOI_DISABLED 0x0
+
 #ifdef __KERNEL__
 #include <asm/processor.h>
 
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 441520e4174..a3ac52b29cb 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -33,6 +33,14 @@
 #define MCI_STATUS_PCC   (1ULL<<57)  /* processor context corrupt */
 #define MCI_STATUS_S     (1ULL<<56)  /* Signaled machine check */
 #define MCI_STATUS_AR    (1ULL<<55)  /* Action required */
+#define MCACOD            0xffff     /* MCA Error Code */
+
+/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
+#define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
+#define MCACOD_SCRUBMSK 0xfff0
+#define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
+#define MCACOD_DATA     0x0134  /* Data Load */
+#define MCACOD_INSTR    0x0150  /* Instruction Fetch */
 
 /* MCi_MISC register defines */
 #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 084ef95274c..813ed103f45 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -115,8 +115,8 @@ notrace static inline int native_write_msr_safe(unsigned int msr,
 
 extern unsigned long long native_read_tsc(void);
 
-extern int native_rdmsr_safe_regs(u32 regs[8]);
-extern int native_wrmsr_safe_regs(u32 regs[8]);
+extern int rdmsr_safe_regs(u32 regs[8]);
+extern int wrmsr_safe_regs(u32 regs[8]);
 
 static __always_inline unsigned long long __native_read_tsc(void)
 {
@@ -187,43 +187,6 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
         return err;
 }
 
-static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
-{
-        u32 gprs[8] = { 0 };
-        int err;
-
-        gprs[1] = msr;
-        gprs[7] = 0x9c5a203a;
-
-        err = native_rdmsr_safe_regs(gprs);
-
-        *p = gprs[0] | ((u64)gprs[2] << 32);
-
-        return err;
-}
-
-static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
-{
-        u32 gprs[8] = { 0 };
-
-        gprs[0] = (u32)val;
-        gprs[1] = msr;
-        gprs[2] = val >> 32;
-        gprs[7] = 0x9c5a203a;
-
-        return native_wrmsr_safe_regs(gprs);
-}
-
-static inline int rdmsr_safe_regs(u32 regs[8])
-{
-        return native_rdmsr_safe_regs(regs);
-}
-
-static inline int wrmsr_safe_regs(u32 regs[8])
-{
-        return native_wrmsr_safe_regs(regs);
-}
-
 #define rdtscl(low)                                             \
         ((low) = (u32)__native_read_tsc())
 
@@ -237,6 +200,8 @@ do {							\
         (high) = (u32)(_l >> 32);                       \
 } while (0)
 
+#define rdpmcl(counter, val) ((val) = native_read_pmc(counter))
+
 #define rdtscp(low, high, aux)                                  \
 do {                                                            \
         unsigned long long _val = native_read_tscp(&(aux));     \
@@ -248,8 +213,7 @@ do {                                                            \
 
 #endif  /* !CONFIG_PARAVIRT */
 
-
-#define checking_wrmsrl(msr, val) wrmsr_safe((msr), (u32)(val),         \
+#define wrmsrl_safe(msr, val) wrmsr_safe((msr), (u32)(val),             \
                                              (u32)((val) >> 32))
 
 #define write_tsc(val1, val2) wrmsr(MSR_IA32_TSC, (val1), (val2))
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index dc580c42851..c0fa356e90d 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -44,28 +44,14 @@ struct nmiaction {
         const char              *name;
 };
 
-#define register_nmi_handler(t, fn, fg, n)              \
+#define register_nmi_handler(t, fn, fg, n, init...)     \
 ({                                                      \
-        static struct nmiaction fn##_na = {             \
+        static struct nmiaction init fn##_na = {        \
                 .handler = (fn),                        \
                 .name = (n),                            \
                 .flags = (fg),                          \
         };                                              \
-        __register_nmi_handler((t), &fn##_na);  \
-})
-
-/*
- * For special handlers that register/unregister in the
- * init section only.  This should be considered rare.
- */
-#define register_nmi_handler_initonly(t, fn, fg, n)             \
-({                                                      \
-        static struct nmiaction fn##_na __initdata = {          \
-                .handler = (fn),                        \
-                .name = (n),                            \
-                .flags = (fg),                          \
-        };                                              \
-        __register_nmi_handler((t), &fn##_na);  \
+        __register_nmi_handler((t), &fn##_na);          \
 })
 
 int __register_nmi_handler(unsigned int, struct nmiaction *);
diff --git a/arch/x86/include/asm/olpc.h b/arch/x86/include/asm/olpc.h
index 87bdbca72f9..72f9adf6eca 100644
--- a/arch/x86/include/asm/olpc.h
+++ b/arch/x86/include/asm/olpc.h
@@ -100,25 +100,6 @@ extern void olpc_xo1_pm_wakeup_clear(u16 value);
 
 extern int pci_olpc_init(void);
 
-/* EC related functions */
-
-extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
-                unsigned char *outbuf, size_t outlen);
-
-/* EC commands */
-
-#define EC_FIRMWARE_REV                 0x08
-#define EC_WRITE_SCI_MASK               0x1b
-#define EC_WAKE_UP_WLAN                 0x24
-#define EC_WLAN_LEAVE_RESET             0x25
-#define EC_READ_EB_MODE                 0x2a
-#define EC_SET_SCI_INHIBIT              0x32
-#define EC_SET_SCI_INHIBIT_RELEASE      0x34
-#define EC_WLAN_ENTER_RESET             0x35
-#define EC_WRITE_EXT_SCI_MASK           0x38
-#define EC_SCI_QUERY                    0x84
-#define EC_EXT_SCI_QUERY                0x85
-
 /* SCI source values */
 
 #define EC_SCI_SRC_EMPTY        0x00
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 6cbbabf5270..a0facf3908d 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -128,21 +128,11 @@ static inline u64 paravirt_read_msr(unsigned msr, int *err)
         return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
 }
 
-static inline int paravirt_rdmsr_regs(u32 *regs)
-{
-        return PVOP_CALL1(int, pv_cpu_ops.rdmsr_regs, regs);
-}
-
 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
 {
         return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
 }
 
-static inline int paravirt_wrmsr_regs(u32 *regs)
-{
-        return PVOP_CALL1(int, pv_cpu_ops.wrmsr_regs, regs);
-}
-
 /* These should all do BUG_ON(_err), but our headers are too tangled. */
 #define rdmsr(msr, val1, val2)                  \
 do {                                            \
@@ -176,9 +166,6 @@ do {						\
         _err;                                   \
 })
 
-#define rdmsr_safe_regs(regs)   paravirt_rdmsr_regs(regs)
-#define wrmsr_safe_regs(regs)   paravirt_wrmsr_regs(regs)
-
 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
 {
         int err;
@@ -186,32 +173,6 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
         *p = paravirt_read_msr(msr, &err);
         return err;
 }
-static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
-{
-        u32 gprs[8] = { 0 };
-        int err;
-
-        gprs[1] = msr;
-        gprs[7] = 0x9c5a203a;
-
-        err = paravirt_rdmsr_regs(gprs);
-
-        *p = gprs[0] | ((u64)gprs[2] << 32);
-
-        return err;
-}
-
-static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
-{
-        u32 gprs[8] = { 0 };
-
-        gprs[0] = (u32)val;
-        gprs[1] = msr;
-        gprs[2] = val >> 32;
-        gprs[7] = 0x9c5a203a;
-
-        return paravirt_wrmsr_regs(gprs);
-}
 
 static inline u64 paravirt_read_tsc(void)
 {
@@ -252,6 +213,8 @@ do {						\
         high = _l >> 32;                        \
 } while (0)
 
+#define rdpmcl(counter, val) ((val) = paravirt_read_pmc(counter))
+
 static inline unsigned long long paravirt_rdtscp(unsigned int *aux)
 {
         return PVOP_CALL1(u64, pv_cpu_ops.read_tscp, aux);
@@ -397,9 +360,10 @@ static inline void __flush_tlb_single(unsigned long addr)
 
 static inline void flush_tlb_others(const struct cpumask *cpumask,
                                     struct mm_struct *mm,
-                                    unsigned long va)
+                                    unsigned long start,
+                                    unsigned long end)
 {
-        PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, cpumask, mm, va);
+        PVOP_VCALL4(pv_mmu_ops.flush_tlb_others, cpumask, mm, start, end);
 }
 
 static inline int paravirt_pgd_alloc(struct mm_struct *mm)
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
index 8e8b9a4987e..142236ed83a 100644
--- a/arch/x86/include/asm/paravirt_types.h
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -153,9 +153,7 @@ struct pv_cpu_ops {
         /* MSR, PMC and TSR operations.
            err = 0/-EFAULT.  wrmsr returns 0/-EFAULT. */
         u64 (*read_msr)(unsigned int msr, int *err);
-        int (*rdmsr_regs)(u32 *regs);
         int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
-        int (*wrmsr_regs)(u32 *regs);
 
         u64 (*read_tsc)(void);
         u64 (*read_pmc)(int counter);
@@ -250,7 +248,8 @@ struct pv_mmu_ops {
         void (*flush_tlb_single)(unsigned long addr);
         void (*flush_tlb_others)(const struct cpumask *cpus,
                                  struct mm_struct *mm,
-                                 unsigned long va);
+                                 unsigned long start,
+                                 unsigned long end);
 
         /* Hooks for allocating and freeing a pagetable top-level */
         int  (*pgd_alloc)(struct mm_struct *mm);
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index b3a53174602..73e8eeff22e 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -7,9 +7,13 @@
 #undef DEBUG
 
 #ifdef DEBUG
-#define DBG(x...) printk(x)
+#define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
 #else
-#define DBG(x...)
+#define DBG(fmt, ...)                           \
+do {                                            \
+        if (0)                                  \
+                printk(fmt, ##__VA_ARGS__);     \
+} while (0)
 #endif
 
 #define PCI_PROBE_BIOS          0x0001
@@ -100,6 +104,7 @@ struct pci_raw_ops {
 extern const struct pci_raw_ops *raw_pci_ops;
 extern const struct pci_raw_ops *raw_pci_ext_ops;
 
+extern const struct pci_raw_ops pci_mmcfg;
 extern const struct pci_raw_ops pci_direct_conf1;
 extern bool port_cf9_safe;
 
@@ -135,6 +140,12 @@ struct pci_mmcfg_region {
 
 extern int __init pci_mmcfg_arch_init(void);
 extern void __init pci_mmcfg_arch_free(void);
+extern int __devinit pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
+extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
+extern int __devinit pci_mmconfig_insert(struct device *dev,
+                                         u16 seg, u8 start,
+                                         u8 end, phys_addr_t addr);
+extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
 extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
 
 extern struct list_head pci_mmcfg_list;
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index d9b8e3f7f42..1104afaba52 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -551,6 +551,12 @@ DECLARE_PER_CPU(unsigned long, this_cpu_off);
                                 { [0 ... NR_CPUS-1] = _initvalue };     \
         __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
 
+#define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue)      \
+        DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue;          \
+        __typeof__(_type) _name##_early_map[NR_CPUS] __initdata =       \
+                                { [0 ... NR_CPUS-1] = _initvalue };     \
+        __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
+
 #define EXPORT_EARLY_PER_CPU_SYMBOL(_name)                      \
         EXPORT_PER_CPU_SYMBOL(_name)
 
@@ -559,6 +565,11 @@ DECLARE_PER_CPU(unsigned long, this_cpu_off);
         extern __typeof__(_type) *_name##_early_ptr;            \
         extern __typeof__(_type)  _name##_early_map[]
 
+#define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name)         \
+        DECLARE_PER_CPU_READ_MOSTLY(_type, _name);              \
+        extern __typeof__(_type) *_name##_early_ptr;            \
+        extern __typeof__(_type)  _name##_early_map[]
+
 #define early_per_cpu_ptr(_name) (_name##_early_ptr)
 #define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx])
 #define early_per_cpu(_name, _cpu)                              \
@@ -570,12 +581,18 @@ DECLARE_PER_CPU(unsigned long, this_cpu_off);
 #define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue)          \
         DEFINE_PER_CPU(_type, _name) = _initvalue
 
+#define DEFINE_EARLY_PER_CPU_READ_MOSTLY(_type, _name, _initvalue)      \
+        DEFINE_PER_CPU_READ_MOSTLY(_type, _name) = _initvalue
+
 #define EXPORT_EARLY_PER_CPU_SYMBOL(_name)                      \
         EXPORT_PER_CPU_SYMBOL(_name)
 
 #define DECLARE_EARLY_PER_CPU(_type, _name)                     \
         DECLARE_PER_CPU(_type, _name)
 
+#define DECLARE_EARLY_PER_CPU_READ_MOSTLY(_type, _name)         \
+        DECLARE_PER_CPU_READ_MOSTLY(_type, _name)
+
 #define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu)
 #define early_per_cpu_ptr(_name) NULL
 /* no early_per_cpu_map() */
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 588f52ea810..cb4e43bce98 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -5,11 +5,10 @@
  * Performance event hw details:
  */
 
-#define X86_PMC_MAX_GENERIC                                    32
-#define X86_PMC_MAX_FIXED                                       3
+#define INTEL_PMC_MAX_GENERIC                                  32
+#define INTEL_PMC_MAX_FIXED                                     3
+#define INTEL_PMC_IDX_FIXED                                    32
 
-#define X86_PMC_IDX_GENERIC                                     0
-#define X86_PMC_IDX_FIXED                                      32
 #define X86_PMC_IDX_MAX                                        64
 
 #define MSR_ARCH_PERFMON_PERFCTR0                             0xc1
@@ -48,8 +47,7 @@
         (X86_RAW_EVENT_MASK          |  \
          AMD64_EVENTSEL_EVENT)
 #define AMD64_NUM_COUNTERS                              4
-#define AMD64_NUM_COUNTERS_F15H                         6
-#define AMD64_NUM_COUNTERS_MAX                          AMD64_NUM_COUNTERS_F15H
+#define AMD64_NUM_COUNTERS_CORE                         6
 
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL           0x3c
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK         (0x00 << 8)
@@ -121,16 +119,16 @@ struct x86_pmu_capability {
 
 /* Instr_Retired.Any: */
 #define MSR_ARCH_PERFMON_FIXED_CTR0     0x309
-#define X86_PMC_IDX_FIXED_INSTRUCTIONS  (X86_PMC_IDX_FIXED + 0)
+#define INTEL_PMC_IDX_FIXED_INSTRUCTIONS        (INTEL_PMC_IDX_FIXED + 0)
 
 /* CPU_CLK_Unhalted.Core: */
 #define MSR_ARCH_PERFMON_FIXED_CTR1     0x30a
-#define X86_PMC_IDX_FIXED_CPU_CYCLES    (X86_PMC_IDX_FIXED + 1)
+#define INTEL_PMC_IDX_FIXED_CPU_CYCLES  (INTEL_PMC_IDX_FIXED + 1)
 
 /* CPU_CLK_Unhalted.Ref: */
 #define MSR_ARCH_PERFMON_FIXED_CTR2     0x30b
-#define X86_PMC_IDX_FIXED_REF_CYCLES    (X86_PMC_IDX_FIXED + 2)
-#define X86_PMC_MSK_FIXED_REF_CYCLES    (1ULL << X86_PMC_IDX_FIXED_REF_CYCLES)
+#define INTEL_PMC_IDX_FIXED_REF_CYCLES  (INTEL_PMC_IDX_FIXED + 2)
+#define INTEL_PMC_MSK_FIXED_REF_CYCLES  (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
 
 /*
  * We model BTS tracing as another fixed-mode PMC.
@@ -139,7 +137,7 @@ struct x86_pmu_capability {
  * values are used by actual fixed events and higher values are used
  * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
  */
-#define X86_PMC_IDX_FIXED_BTS                           (X86_PMC_IDX_FIXED + 16)
+#define INTEL_PMC_IDX_FIXED_BTS                         (INTEL_PMC_IDX_FIXED + 16)
 
 /*
  * IBS cpuid feature detection
@@ -198,11 +196,16 @@ static inline u32 get_ibs_caps(void) { return 0; }
 extern void perf_events_lapic_init(void);
 
 /*
- * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
- * This flag is otherwise unused and ABI specified to be 0, so nobody should
- * care what we do with it.
+ * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
+ * unused and ABI specified to be 0, so nobody should care what we do with
+ * them.
+ *
+ * EXACT - the IP points to the exact instruction that triggered the
+ *         event (HW bugs exempt).
+ * VM    - original X86_VM_MASK; see set_linear_ip().
  */
 #define PERF_EFLAGS_EXACT       (1UL << 3)
+#define PERF_EFLAGS_VM          (1UL << 5)
 
 struct pt_regs;
 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
@@ -234,8 +237,9 @@ struct perf_guest_switch_msr {
 
 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr);
 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
+extern void perf_check_microcode(void);
 #else
-static inline perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
+static inline struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
 {
         *nr = 0;
         return NULL;
@@ -247,6 +251,7 @@ static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
 }
 
 static inline void perf_events_lapic_init(void) { }
+static inline void perf_check_microcode(void) { }
 #endif
 
 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
diff --git a/arch/x86/include/asm/pgtable-2level.h b/arch/x86/include/asm/pgtable-2level.h
index 98391db840c..f2b489cf160 100644
--- a/arch/x86/include/asm/pgtable-2level.h
+++ b/arch/x86/include/asm/pgtable-2level.h
@@ -2,9 +2,9 @@
 #define _ASM_X86_PGTABLE_2LEVEL_H
 
 #define pte_ERROR(e) \
-        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte_low)
+        pr_err("%s:%d: bad pte %08lx\n", __FILE__, __LINE__, (e).pte_low)
 #define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+        pr_err("%s:%d: bad pgd %08lx\n", __FILE__, __LINE__, pgd_val(e))
 
 /*
  * Certain architectures need to do special things when PTEs
diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h
index cb00ccc7d57..4cc9f2b7cdc 100644
--- a/arch/x86/include/asm/pgtable-3level.h
+++ b/arch/x86/include/asm/pgtable-3level.h
@@ -9,13 +9,13 @@
  */
 
 #define pte_ERROR(e)                                                    \
-        printk("%s:%d: bad pte %p(%08lx%08lx).\n",                      \
+        pr_err("%s:%d: bad pte %p(%08lx%08lx)\n",                       \
                __FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
 #define pmd_ERROR(e)                                                    \
-        printk("%s:%d: bad pmd %p(%016Lx).\n",                          \
+        pr_err("%s:%d: bad pmd %p(%016Lx)\n",                           \
                __FILE__, __LINE__, &(e), pmd_val(e))
 #define pgd_ERROR(e)                                                    \
-        printk("%s:%d: bad pgd %p(%016Lx).\n",                          \
+        pr_err("%s:%d: bad pgd %p(%016Lx)\n",                           \
                __FILE__, __LINE__, &(e), pgd_val(e))
 
 /* Rules for using set_pte: the pte being assigned *must* be
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
index 975f709e09a..8251be02301 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -26,16 +26,16 @@ extern pgd_t init_level4_pgt[];
 extern void paging_init(void);
 
 #define pte_ERROR(e)                                    \
-        printk("%s:%d: bad pte %p(%016lx).\n",          \
+        pr_err("%s:%d: bad pte %p(%016lx)\n",           \
                __FILE__, __LINE__, &(e), pte_val(e))
 #define pmd_ERROR(e)                                    \
-        printk("%s:%d: bad pmd %p(%016lx).\n",          \
+        pr_err("%s:%d: bad pmd %p(%016lx)\n",           \
                __FILE__, __LINE__, &(e), pmd_val(e))
 #define pud_ERROR(e)                                    \
-        printk("%s:%d: bad pud %p(%016lx).\n",          \
+        pr_err("%s:%d: bad pud %p(%016lx)\n",           \
                __FILE__, __LINE__, &(e), pud_val(e))
 #define pgd_ERROR(e)                                    \
-        printk("%s:%d: bad pgd %p(%016lx).\n",          \
+        pr_err("%s:%d: bad pgd %p(%016lx)\n",           \
                __FILE__, __LINE__, &(e), pgd_val(e))
 
 struct mm_struct;
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 013286a10c2..db8fec6d295 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -303,11 +303,9 @@ void set_pte_vaddr(unsigned long vaddr, pte_t pte);
 
 extern void native_pagetable_reserve(u64 start, u64 end);
 #ifdef CONFIG_X86_32
-extern void native_pagetable_setup_start(pgd_t *base);
-extern void native_pagetable_setup_done(pgd_t *base);
+extern void native_pagetable_init(void);
 #else
-#define native_pagetable_setup_start x86_init_pgd_noop
-#define native_pagetable_setup_done  x86_init_pgd_noop
+#define native_pagetable_init        paging_init
 #endif
 
 struct seq_file;
diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/processor-flags.h
index f8ab3eaad12..aea1d1d848c 100644
--- a/arch/x86/include/asm/processor-flags.h
+++ b/arch/x86/include/asm/processor-flags.h
@@ -44,6 +44,7 @@
  */
 #define X86_CR3_PWT     0x00000008 /* Page Write Through */
 #define X86_CR3_PCD     0x00000010 /* Page Cache Disable */
+#define X86_CR3_PCID_MASK 0x00000fff /* PCID Mask */
 
 /*
  * Intel CPU features in CR4
@@ -61,6 +62,7 @@
 #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
 #define X86_CR4_VMXE    0x00002000 /* enable VMX virtualization */
 #define X86_CR4_RDWRGSFS 0x00010000 /* enable RDWRGSFS support */
+#define X86_CR4_PCIDE   0x00020000 /* enable PCID support */
 #define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
 #define X86_CR4_SMEP    0x00100000 /* enable SMEP support */
 
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 39bc5777211..d048cad9bca 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -61,6 +61,19 @@ static inline void *current_text_addr(void)
 # define ARCH_MIN_MMSTRUCT_ALIGN        0
 #endif
 
+enum tlb_infos {
+        ENTRIES,
+        NR_INFO
+};
+
+extern u16 __read_mostly tlb_lli_4k[NR_INFO];
+extern u16 __read_mostly tlb_lli_2m[NR_INFO];
+extern u16 __read_mostly tlb_lli_4m[NR_INFO];
+extern u16 __read_mostly tlb_lld_4k[NR_INFO];
+extern u16 __read_mostly tlb_lld_2m[NR_INFO];
+extern u16 __read_mostly tlb_lld_4m[NR_INFO];
+extern s8  __read_mostly tlb_flushall_shift;
+
 /*
  *  CPU type and hardware bug flags. Kept separately for each CPU.
  *  Members of this structure are referenced in head.S, so think twice
diff --git a/arch/x86/include/asm/realmode.h b/arch/x86/include/asm/realmode.h
index fce3f4ae5bd..fe1ec5bcd84 100644
--- a/arch/x86/include/asm/realmode.h
+++ b/arch/x86/include/asm/realmode.h
@@ -21,8 +21,9 @@ struct real_mode_header {
         u32     wakeup_header;
 #endif
         /* APM/BIOS reboot */
-#ifdef CONFIG_X86_32
         u32     machine_real_restart_asm;
+#ifdef CONFIG_X86_64
+        u32     machine_real_restart_seg;
 #endif
 };
 
diff --git a/arch/x86/include/asm/reboot.h b/arch/x86/include/asm/reboot.h
index 92f297069e8..a82c4f1b4d8 100644
--- a/arch/x86/include/asm/reboot.h
+++ b/arch/x86/include/asm/reboot.h
@@ -18,8 +18,8 @@ extern struct machine_ops machine_ops;
 
 void native_machine_crash_shutdown(struct pt_regs *regs);
 void native_machine_shutdown(void);
-void machine_real_restart(unsigned int type);
-/* These must match dispatch_table in reboot_32.S */
+void __noreturn machine_real_restart(unsigned int type);
+/* These must match dispatch in arch/x86/realmore/rm/reboot.S */
 #define MRR_BIOS        0
 #define MRR_APM         1
 
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index f48394513c3..4f19a152603 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -31,12 +31,12 @@ static inline bool cpu_has_ht_siblings(void)
         return has_siblings;
 }
 
-DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map);
-DECLARE_PER_CPU(cpumask_var_t, cpu_core_map);
+DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
+DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
 /* cpus sharing the last level cache: */
-DECLARE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
-DECLARE_PER_CPU(u16, cpu_llc_id);
-DECLARE_PER_CPU(int, cpu_number);
+DECLARE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
+DECLARE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id);
+DECLARE_PER_CPU_READ_MOSTLY(int, cpu_number);
 
 static inline struct cpumask *cpu_sibling_mask(int cpu)
 {
@@ -53,10 +53,10 @@ static inline struct cpumask *cpu_llc_shared_mask(int cpu)
         return per_cpu(cpu_llc_shared_map, cpu);
 }
 
-DECLARE_EARLY_PER_CPU(u16, x86_cpu_to_apicid);
-DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
+DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid);
+DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
-DECLARE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid);
+DECLARE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid);
 #endif
 
 /* Static state in head.S used to set up a CPU */
@@ -169,11 +169,6 @@ void x86_idle_thread_init(unsigned int cpu, struct task_struct *idle);
 void smp_store_cpu_info(int id);
 #define cpu_physical_id(cpu)    per_cpu(x86_cpu_to_apicid, cpu)
 
-/* We don't mark CPUs online until __cpu_up(), so we need another measure */
-static inline int num_booting_cpus(void)
-{
-        return cpumask_weight(cpu_callout_mask);
-}
 #else /* !CONFIG_SMP */
 #define wbinvd_on_cpu(cpu)     wbinvd()
 static inline int wbinvd_on_all_cpus(void)
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index b315a33867f..33692eaabab 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -12,8 +12,7 @@
  * Simple spin lock operations.  There are two variants, one clears IRQ's
  * on the local processor, one does not.
  *
- * These are fair FIFO ticket locks, which are currently limited to 256
- * CPUs.
+ * These are fair FIFO ticket locks, which support up to 2^16 CPUs.
  *
  * (the type definitions are in asm/spinlock_types.h)
  */
diff --git a/arch/x86/include/asm/tlb.h b/arch/x86/include/asm/tlb.h
index 829215fef9e..4fef20773b8 100644
--- a/arch/x86/include/asm/tlb.h
+++ b/arch/x86/include/asm/tlb.h
@@ -4,7 +4,14 @@
 #define tlb_start_vma(tlb, vma) do { } while (0)
 #define tlb_end_vma(tlb, vma) do { } while (0)
 #define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+
+#define tlb_flush(tlb)                                                  \
+{                                                                       \
+        if (tlb->fullmm == 0)                                           \
+                flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end, 0UL); \
+        else                                                            \
+                flush_tlb_mm_range(tlb->mm, 0UL, TLB_FLUSH_ALL, 0UL);   \
+}
 
 #include <asm-generic/tlb.h>
 
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index 36a1a2ab87d..74a44333545 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -73,14 +73,10 @@ static inline void __flush_tlb_one(unsigned long addr)
  *  - flush_tlb_page(vma, vmaddr) flushes one page
  *  - flush_tlb_range(vma, start, end) flushes a range of pages
  *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- *  - flush_tlb_others(cpumask, mm, va) flushes TLBs on other cpus
+ *  - flush_tlb_others(cpumask, mm, start, end) flushes TLBs on other cpus
  *
  * ..but the i386 has somewhat limited tlb flushing capabilities,
  * and page-granular flushes are available only on i486 and up.
- *
- * x86-64 can only flush individual pages or full VMs. For a range flush
- * we always do the full VM. Might be worth trying if for a small
- * range a few INVLPGs in a row are a win.
  */
 
 #ifndef CONFIG_SMP
@@ -109,9 +105,17 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
                 __flush_tlb();
 }
 
+static inline void flush_tlb_mm_range(struct mm_struct *mm,
+           unsigned long start, unsigned long end, unsigned long vmflag)
+{
+        if (mm == current->active_mm)
+                __flush_tlb();
+}
+
 static inline void native_flush_tlb_others(const struct cpumask *cpumask,
                                            struct mm_struct *mm,
-                                           unsigned long va)
+                                           unsigned long start,
+                                           unsigned long end)
 {
 }
 
@@ -119,27 +123,35 @@ static inline void reset_lazy_tlbstate(void)
 {
 }
 
+static inline void flush_tlb_kernel_range(unsigned long start,
+                                          unsigned long end)
+{
+        flush_tlb_all();
+}
+
 #else  /* SMP */
 
 #include <asm/smp.h>
 
 #define local_flush_tlb() __flush_tlb()
 
+#define flush_tlb_mm(mm)        flush_tlb_mm_range(mm, 0UL, TLB_FLUSH_ALL, 0UL)
+
+#define flush_tlb_range(vma, start, end)        \
+                flush_tlb_mm_range(vma->vm_mm, start, end, vma->vm_flags)
+
 extern void flush_tlb_all(void);
 extern void flush_tlb_current_task(void);
-extern void flush_tlb_mm(struct mm_struct *);
 extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
+extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
+                                unsigned long end, unsigned long vmflag);
+extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 
 #define flush_tlb()     flush_tlb_current_task()
 
-static inline void flush_tlb_range(struct vm_area_struct *vma,
-                                   unsigned long start, unsigned long end)
-{
-        flush_tlb_mm(vma->vm_mm);
-}
-
 void native_flush_tlb_others(const struct cpumask *cpumask,
-                             struct mm_struct *mm, unsigned long va);
+                                struct mm_struct *mm,
+                                unsigned long start, unsigned long end);
 
 #define TLBSTATE_OK     1
 #define TLBSTATE_LAZY   2
@@ -159,13 +171,8 @@ static inline void reset_lazy_tlbstate(void)
 #endif  /* SMP */
 
 #ifndef CONFIG_PARAVIRT
-#define flush_tlb_others(mask, mm, va)  native_flush_tlb_others(mask, mm, va)
+#define flush_tlb_others(mask, mm, start, end)  \
+        native_flush_tlb_others(mask, mm, start, end)
 #endif
 
-static inline void flush_tlb_kernel_range(unsigned long start,
-                                          unsigned long end)
-{
-        flush_tlb_all();
-}
-
 #endif /* _ASM_X86_TLBFLUSH_H */
diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h
index 8e796fbbf9c..d8def8b3dba 100644
--- a/arch/x86/include/asm/uaccess_64.h
+++ b/arch/x86/include/asm/uaccess_64.h
@@ -17,6 +17,8 @@
 
 /* Handles exceptions in both to and from, but doesn't do access_ok */
 __must_check unsigned long
+copy_user_enhanced_fast_string(void *to, const void *from, unsigned len);
+__must_check unsigned long
 copy_user_generic_string(void *to, const void *from, unsigned len);
 __must_check unsigned long
 copy_user_generic_unrolled(void *to, const void *from, unsigned len);
@@ -26,9 +28,16 @@ copy_user_generic(void *to, const void *from, unsigned len)
 {
         unsigned ret;
 
-        alternative_call(copy_user_generic_unrolled,
+        /*
+         * If CPU has ERMS feature, use copy_user_enhanced_fast_string.
+         * Otherwise, if CPU has rep_good feature, use copy_user_generic_string.
+         * Otherwise, use copy_user_generic_unrolled.
+         */
+        alternative_call_2(copy_user_generic_unrolled,
                          copy_user_generic_string,
                          X86_FEATURE_REP_GOOD,
+                         copy_user_enhanced_fast_string,
+                         X86_FEATURE_ERMS,
                          ASM_OUTPUT2("=a" (ret), "=D" (to), "=S" (from),
                                      "=d" (len)),
                          "1" (to), "2" (from), "3" (len)
diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h
index 4437001d8e3..0d9776e9e2d 100644
--- a/arch/x86/include/asm/unistd.h
+++ b/arch/x86/include/asm/unistd.h
@@ -15,7 +15,6 @@
 # ifdef CONFIG_X86_32
 
 #  include <asm/unistd_32.h>
-#  define __ARCH_WANT_IPC_PARSE_VERSION
 #  define __ARCH_WANT_STAT64
 #  define __ARCH_WANT_SYS_IPC
 #  define __ARCH_WANT_SYS_OLD_MMAP
diff --git a/arch/x86/include/asm/uprobes.h b/arch/x86/include/asm/uprobes.h
index 1e9bed14f7a..f3971bbcd1d 100644
--- a/arch/x86/include/asm/uprobes.h
+++ b/arch/x86/include/asm/uprobes.h
@@ -48,7 +48,7 @@ struct arch_uprobe_task {
 #endif
 };
 
-extern int  arch_uprobe_analyze_insn(struct arch_uprobe *aup, struct mm_struct *mm);
+extern int  arch_uprobe_analyze_insn(struct arch_uprobe *aup, struct mm_struct *mm, unsigned long addr);
 extern int  arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs);
 extern int  arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs);
 extern bool arch_uprobe_xol_was_trapped(struct task_struct *tsk);
diff --git a/arch/x86/include/asm/uv/uv.h b/arch/x86/include/asm/uv/uv.h
index 3bb9491b765..b47c2a82ff1 100644
--- a/arch/x86/include/asm/uv/uv.h
+++ b/arch/x86/include/asm/uv/uv.h
@@ -15,7 +15,8 @@ extern void uv_nmi_init(void);
 extern void uv_system_init(void);
 extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
                                                  struct mm_struct *mm,
-                                                 unsigned long va,
+                                                 unsigned long start,
+                                                 unsigned end,
                                                  unsigned int cpu);
 
 #else   /* X86_UV */
@@ -26,7 +27,7 @@ static inline void uv_cpu_init(void)	{ }
 static inline void uv_system_init(void) { }
 static inline const struct cpumask *
 uv_flush_tlb_others(const struct cpumask *cpumask, struct mm_struct *mm,
-                    unsigned long va, unsigned int cpu)
+                    unsigned long start, unsigned long end, unsigned int cpu)
 { return cpumask; }
 
 #endif  /* X86_UV */
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index 6149b476d9d..a06983cdc12 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -140,6 +140,9 @@
 #define IPI_RESET_LIMIT                 1
 /* after this # consecutive successes, bump up the throttle if it was lowered */
 #define COMPLETE_THRESHOLD              5
+/* after this # of giveups (fall back to kernel IPI's) disable the use of
+   the BAU for a period of time */
+#define GIVEUP_LIMIT                    100
 
 #define UV_LB_SUBNODEID                 0x10
 
@@ -166,7 +169,6 @@
 #define FLUSH_RETRY_TIMEOUT             2
 #define FLUSH_GIVEUP                    3
 #define FLUSH_COMPLETE                  4
-#define FLUSH_RETRY_BUSYBUG             5
 
 /*
  * tuning the action when the numalink network is extremely delayed
@@ -175,7 +177,7 @@
                                                    microseconds */
 #define CONGESTED_REPS                  10      /* long delays averaged over
                                                    this many broadcasts */
-#define CONGESTED_PERIOD                30      /* time for the bau to be
+#define DISABLED_PERIOD                 10      /* time for the bau to be
                                                    disabled, in seconds */
 /* see msg_type: */
 #define MSG_NOOP                        0
@@ -520,6 +522,12 @@ struct ptc_stats {
         unsigned long   s_uv2_wars;             /* uv2 workaround, perm. busy */
         unsigned long   s_uv2_wars_hw;          /* uv2 workaround, hiwater */
         unsigned long   s_uv2_war_waits;        /* uv2 workaround, long waits */
+        unsigned long   s_overipilimit;         /* over the ipi reset limit */
+        unsigned long   s_giveuplimit;          /* disables, over giveup limit*/
+        unsigned long   s_enters;               /* entries to the driver */
+        unsigned long   s_ipifordisabled;       /* fall back to IPI; disabled */
+        unsigned long   s_plugged;              /* plugged by h/w bug*/
+        unsigned long   s_congested;            /* giveup on long wait */
         /* destination statistics */
         unsigned long   d_alltlb;               /* times all tlb's on this
                                                    cpu were flushed */
@@ -586,8 +594,8 @@ struct bau_control {
         int                     timeout_tries;
         int                     ipi_attempts;
         int                     conseccompletes;
-        int                     baudisabled;
-        int                     set_bau_off;
+        short                   nobau;
+        short                   baudisabled;
         short                   cpu;
         short                   osnode;
         short                   uvhub_cpu;
@@ -596,14 +604,16 @@ struct bau_control {
         short                   cpus_in_socket;
         short                   cpus_in_uvhub;
         short                   partition_base_pnode;
-        short                   using_desc; /* an index, like uvhub_cpu */
-        unsigned int            inuse_map;
+        short                   busy;       /* all were busy (war) */
         unsigned short          message_number;
         unsigned short          uvhub_quiesce;
         short                   socket_acknowledge_count[DEST_Q_SIZE];
         cycles_t                send_message;
+        cycles_t                period_end;
+        cycles_t                period_time;
         spinlock_t              uvhub_lock;
         spinlock_t              queue_lock;
+        spinlock_t              disable_lock;
         /* tunables */
         int                     max_concurr;
         int                     max_concurr_const;
@@ -614,9 +624,9 @@ struct bau_control {
         int                     complete_threshold;
         int                     cong_response_us;
         int                     cong_reps;
-        int                     cong_period;
-        unsigned long           clocks_per_100_usec;
-        cycles_t                period_time;
+        cycles_t                disabled_period;
+        int                     period_giveups;
+        int                     giveup_limit;
         long                    period_requests;
         struct hub_and_pnode    *thp;
 };
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 31f180c21ce..74fcb963595 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -60,6 +60,7 @@
 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
+#define SECONDARY_EXEC_ENABLE_INVPCID           0x00001000
 
 
 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
@@ -281,6 +282,7 @@ enum vmcs_field {
 #define EXIT_REASON_EPT_MISCONFIG       49
 #define EXIT_REASON_WBINVD              54
 #define EXIT_REASON_XSETBV              55
+#define EXIT_REASON_INVPCID             58
 
 /*
  * Interruption-information format
@@ -404,6 +406,7 @@ enum vmcs_field {
 #define VMX_EPTP_WB_BIT                         (1ull << 14)
 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
+#define VMX_EPT_AD_BIT                                  (1ull << 21)
 #define VMX_EPT_EXTENT_INDIVIDUAL_BIT           (1ull << 24)
 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
@@ -415,11 +418,14 @@ enum vmcs_field {
 #define VMX_EPT_MAX_GAW                         0x4
 #define VMX_EPT_MT_EPTE_SHIFT                   3
 #define VMX_EPT_GAW_EPTP_SHIFT                  3
+#define VMX_EPT_AD_ENABLE_BIT                   (1ull << 6)
 #define VMX_EPT_DEFAULT_MT                      0x6ull
 #define VMX_EPT_READABLE_MASK                   0x1ull
 #define VMX_EPT_WRITABLE_MASK                   0x2ull
 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
+#define VMX_EPT_ACCESS_BIT                              (1ull << 8)
+#define VMX_EPT_DIRTY_BIT                               (1ull << 9)
 
 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
 
diff --git a/arch/x86/include/asm/x2apic.h b/arch/x86/include/asm/x2apic.h
index 92e54abf89e..f90f0a587c6 100644
--- a/arch/x86/include/asm/x2apic.h
+++ b/arch/x86/include/asm/x2apic.h
@@ -9,15 +9,6 @@
 #include <asm/ipi.h>
 #include <linux/cpumask.h>
 
-/*
- * Need to use more than cpu 0, because we need more vectors
- * when MSI-X are used.
- */
-static const struct cpumask *x2apic_target_cpus(void)
-{
-        return cpu_online_mask;
-}
-
 static int x2apic_apic_id_valid(int apicid)
 {
         return 1;
@@ -28,15 +19,6 @@ static int x2apic_apic_id_registered(void)
         return 1;
 }
 
-/*
- * For now each logical cpu is in its own vector allocation domain.
- */
-static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
-        cpumask_clear(retmask);
-        cpumask_set_cpu(cpu, retmask);
-}
-
 static void
 __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
 {
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index c090af10ac7..57693498519 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -81,12 +81,13 @@ struct x86_init_mapping {
 
 /**
  * struct x86_init_paging - platform specific paging functions
- * @pagetable_setup_start:      platform specific pre paging_init() call
- * @pagetable_setup_done:       platform specific post paging_init() call
+ * @pagetable_init:     platform specific paging initialization call to setup
+ *                      the kernel pagetables and prepare accessors functions.
+ *                      Callback must call paging_init(). Called once after the
+ *                      direct mapping for phys memory is available.
  */
 struct x86_init_paging {
-        void (*pagetable_setup_start)(pgd_t *base);
-        void (*pagetable_setup_done)(pgd_t *base);
+        void (*pagetable_init)(void);
 };
 
 /**
@@ -156,7 +157,6 @@ struct x86_cpuinit_ops {
 /**
  * struct x86_platform_ops - platform specific runtime functions
  * @calibrate_tsc:              calibrate TSC
- * @wallclock_init:             init the wallclock device
  * @get_wallclock:              get time from HW clock like RTC etc.
  * @set_wallclock:              set time back to HW clock
  * @is_untracked_pat_range      exclude from PAT logic
@@ -164,10 +164,10 @@ struct x86_cpuinit_ops {
  * @i8042_detect                pre-detect if i8042 controller exists
  * @save_sched_clock_state:     save state for sched_clock() on suspend
  * @restore_sched_clock_state:  restore state for sched_clock() on resume
+ * @apic_post_init:             adjust apic if neeeded
  */
 struct x86_platform_ops {
         unsigned long (*calibrate_tsc)(void);
-        void (*wallclock_init)(void);
         unsigned long (*get_wallclock)(void);
         int (*set_wallclock)(unsigned long nowtime);
         void (*iommu_shutdown)(void);
@@ -177,6 +177,7 @@ struct x86_platform_ops {
         int (*i8042_detect)(void);
         void (*save_sched_clock_state)(void);
         void (*restore_sched_clock_state)(void);
+        void (*apic_post_init)(void);
 };
 
 struct pci_dev;
diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h
index 5728852fb90..59c226d120c 100644
--- a/arch/x86/include/asm/xen/hypercall.h
+++ b/arch/x86/include/asm/xen/hypercall.h
@@ -48,6 +48,7 @@
 #include <xen/interface/sched.h>
 #include <xen/interface/physdev.h>
 #include <xen/interface/platform.h>
+#include <xen/interface/xen-mca.h>
 
 /*
  * The hypercall asms have to meet several constraints:
@@ -302,6 +303,13 @@ HYPERVISOR_set_timer_op(u64 timeout)
 }
 
 static inline int
+HYPERVISOR_mca(struct xen_mc *mc_op)
+{
+        mc_op->interface_version = XEN_MCA_INTERFACE_VERSION;
+        return _hypercall1(int, mca, mc_op);
+}
+
+static inline int
 HYPERVISOR_dom0_op(struct xen_platform_op *platform_op)
 {
         platform_op->interface_version = XENPF_INTERFACE_VERSION;
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 95bf99de905..1b8e5a03d94 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -25,10 +25,6 @@ unsigned long acpi_realmode_flags;
 static char temp_stack[4096];
 #endif
 
-asmlinkage void acpi_enter_s3(void)
-{
-        acpi_enter_sleep_state(3, wake_sleep_flags);
-}
 /**
  * acpi_suspend_lowlevel - save kernel state
  *
diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h
index 5653a5791ec..67f59f8c695 100644
--- a/arch/x86/kernel/acpi/sleep.h
+++ b/arch/x86/kernel/acpi/sleep.h
@@ -2,7 +2,6 @@
  *      Variables and functions used by the code in sleep.c
  */
 
-#include <linux/linkage.h>
 #include <asm/realmode.h>
 
 extern unsigned long saved_video_mode;
@@ -11,7 +10,6 @@ extern long saved_magic;
 extern int wakeup_pmode_return;
 
 extern u8 wake_sleep_flags;
-extern asmlinkage void acpi_enter_s3(void);
 
 extern unsigned long acpi_copy_wakeup_routine(unsigned long);
 extern void wakeup_long64(void);
diff --git a/arch/x86/kernel/acpi/wakeup_32.S b/arch/x86/kernel/acpi/wakeup_32.S
index 72610839f03..13ab720573e 100644
--- a/arch/x86/kernel/acpi/wakeup_32.S
+++ b/arch/x86/kernel/acpi/wakeup_32.S
@@ -74,7 +74,9 @@ restore_registers:
 ENTRY(do_suspend_lowlevel)
         call    save_processor_state
         call    save_registers
-        call    acpi_enter_s3
+        pushl   $3
+        call    acpi_enter_sleep_state
+        addl    $4, %esp
 
 #       In case of S3 failure, we'll emerge here.  Jump
 #       to ret_point to recover
diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S
index 014d1d28c39..8ea5164cbd0 100644
--- a/arch/x86/kernel/acpi/wakeup_64.S
+++ b/arch/x86/kernel/acpi/wakeup_64.S
@@ -71,7 +71,9 @@ ENTRY(do_suspend_lowlevel)
         movq    %rsi, saved_rsi
 
         addq    $8, %rsp
-        call    acpi_enter_s3
+        movl    $3, %edi
+        xorl    %eax, %eax
+        call    acpi_enter_sleep_state
         /* in case something went wrong, restore the machine status and go on */
         jmp     resume_point
 
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 1f84794f075..ced4534baed 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -1,3 +1,5 @@
+#define pr_fmt(fmt) "SMP alternatives: " fmt
+
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <linux/mutex.h>
@@ -63,8 +65,11 @@ static int __init setup_noreplace_paravirt(char *str)
 __setup("noreplace-paravirt", setup_noreplace_paravirt);
 #endif
 
-#define DPRINTK(fmt, args...) if (debug_alternative) \
-        printk(KERN_DEBUG fmt, args)
+#define DPRINTK(fmt, ...)                               \
+do {                                                    \
+        if (debug_alternative)                          \
+                printk(KERN_DEBUG fmt, ##__VA_ARGS__);  \
+} while (0)
 
 /*
  * Each GENERIC_NOPX is of X bytes, and defined as an array of bytes
@@ -160,7 +165,7 @@ static const unsigned char * const k7_nops[ASM_NOP_MAX+2] =
 #endif
 
 #ifdef P6_NOP1
-static const unsigned char  __initconst_or_module p6nops[] =
+static const unsigned char p6nops[] =
 {
         P6_NOP1,
         P6_NOP2,
@@ -219,7 +224,7 @@ void __init arch_init_ideal_nops(void)
                         ideal_nops = intel_nops;
 #endif
                 }
-
+                break;
         default:
 #ifdef CONFIG_X86_64
                 ideal_nops = k8_nops;
@@ -428,7 +433,7 @@ void alternatives_smp_switch(int smp)
          * If this still occurs then you should see a hang
          * or crash shortly after this line:
          */
-        printk("lockdep: fixing up alternatives.\n");
+        pr_info("lockdep: fixing up alternatives\n");
 #endif
 
         if (noreplace_smp || smp_alt_once || skip_smp_alternatives)
@@ -444,14 +449,14 @@ void alternatives_smp_switch(int smp)
         if (smp == smp_mode) {
                 /* nothing */
         } else if (smp) {
-                printk(KERN_INFO "SMP alternatives: switching to SMP code\n");
+                pr_info("switching to SMP code\n");
                 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
                 clear_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
                 list_for_each_entry(mod, &smp_alt_modules, next)
                         alternatives_smp_lock(mod->locks, mod->locks_end,
                                               mod->text, mod->text_end);
         } else {
-                printk(KERN_INFO "SMP alternatives: switching to UP code\n");
+                pr_info("switching to UP code\n");
                 set_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
                 set_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
                 list_for_each_entry(mod, &smp_alt_modules, next)
@@ -546,7 +551,7 @@ void __init alternative_instructions(void)
 #ifdef CONFIG_SMP
         if (smp_alt_once) {
                 if (1 == num_possible_cpus()) {
-                        printk(KERN_INFO "SMP alternatives: switching to UP code\n");
+                        pr_info("switching to UP code\n");
                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_UP);
                         set_cpu_cap(&cpu_data(0), X86_FEATURE_UP);
 
@@ -664,7 +669,7 @@ static int __kprobes stop_machine_text_poke(void *data)
         struct text_poke_param *p;
         int i;
 
-        if (atomic_dec_and_test(&stop_machine_first)) {
+        if (atomic_xchg(&stop_machine_first, 0)) {
                 for (i = 0; i < tpp->nparams; i++) {
                         p = &tpp->params[i];
                         text_poke(p->addr, p->opcode, p->len);
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index be16854591c..aadf3359e2a 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -2,6 +2,9 @@
  * Shared support code for AMD K8 northbridges and derivates.
  * Copyright 2006 Andi Kleen, SUSE Labs. Subject to GPLv2.
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/init.h>
@@ -16,6 +19,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
+        { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
         {}
 };
 EXPORT_SYMBOL(amd_nb_misc_ids);
@@ -258,7 +262,7 @@ void amd_flush_garts(void)
         }
         spin_unlock_irqrestore(&gart_lock, flags);
         if (!flushed)
-                printk("nothing to flush?\n");
+                pr_notice("nothing to flush?\n");
 }
 EXPORT_SYMBOL_GPL(amd_flush_garts);
 
@@ -269,11 +273,10 @@ static __init int init_amd_nbs(void)
         err = amd_cache_northbridges();
 
         if (err < 0)
-                printk(KERN_NOTICE "AMD NB: Cannot enumerate AMD northbridges.\n");
+                pr_notice("Cannot enumerate AMD northbridges\n");
 
         if (amd_cache_gart() < 0)
-                printk(KERN_NOTICE "AMD NB: Cannot initialize GART flush words, "
-                       "GART support disabled.\n");
+                pr_notice("Cannot initialize GART flush words, GART support disabled\n");
 
         return err;
 }
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 39a222e094a..24deb308232 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -75,8 +75,8 @@ physid_mask_t phys_cpu_present_map;
 /*
  * Map cpu index to physical APIC ID
  */
-DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID);
-DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID);
+DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
+DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
 
@@ -88,7 +88,7 @@ EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
  * used for the mapping.  This is where the behaviors of x86_64 and 32
  * actually diverge.  Let's keep it ugly for now.
  */
-DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID);
+DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
 
 /*
  * Knob to control our willingness to enable the local APIC.
@@ -2123,6 +2123,42 @@ void default_init_apic_ldr(void)
         apic_write(APIC_LDR, val);
 }
 
+int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
+                                   const struct cpumask *andmask,
+                                   unsigned int *apicid)
+{
+        unsigned int cpu;
+
+        for_each_cpu_and(cpu, cpumask, andmask) {
+                if (cpumask_test_cpu(cpu, cpu_online_mask))
+                        break;
+        }
+
+        if (likely(cpu < nr_cpu_ids)) {
+                *apicid = per_cpu(x86_cpu_to_apicid, cpu);
+                return 0;
+        }
+
+        return -EINVAL;
+}
+
+/*
+ * Override the generic EOI implementation with an optimized version.
+ * Only called during early boot when only one CPU is active and with
+ * interrupts disabled, so we know this does not race with actual APIC driver
+ * use.
+ */
+void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
+{
+        struct apic **drv;
+
+        for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
+                /* Should happen once for each apic */
+                WARN_ON((*drv)->eoi_write == eoi_write);
+                (*drv)->eoi_write = eoi_write;
+        }
+}
+
 /*
  * Power management
  */
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index 0e881c46e8c..00c77cf78e9 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -36,25 +36,6 @@ static int flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
         return 1;
 }
 
-static const struct cpumask *flat_target_cpus(void)
-{
-        return cpu_online_mask;
-}
-
-static void flat_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
-        /* Careful. Some cpus do not strictly honor the set of cpus
-         * specified in the interrupt destination when using lowest
-         * priority interrupt delivery mode.
-         *
-         * In particular there was a hyperthreading cpu observed to
-         * deliver interrupts to the wrong hyperthread when only one
-         * hyperthread was specified in the interrupt desitination.
-         */
-        cpumask_clear(retmask);
-        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
-}
-
 /*
  * Set up the logical destination ID.
  *
@@ -92,7 +73,7 @@ static void flat_send_IPI_mask(const struct cpumask *cpumask, int vector)
 }
 
 static void
- flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector)
+flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector)
 {
         unsigned long mask = cpumask_bits(cpumask)[0];
         int cpu = smp_processor_id();
@@ -186,7 +167,7 @@ static struct apic apic_flat =  {
         .irq_delivery_mode              = dest_LowestPrio,
         .irq_dest_mode                  = 1, /* logical */
 
-        .target_cpus                    = flat_target_cpus,
+        .target_cpus                    = online_target_cpus,
         .disable_esr                    = 0,
         .dest_logical                   = APIC_DEST_LOGICAL,
         .check_apicid_used              = NULL,
@@ -210,8 +191,7 @@ static struct apic apic_flat =  {
         .set_apic_id                    = set_apic_id,
         .apic_id_mask                   = 0xFFu << 24,
 
-        .cpu_mask_to_apicid             = default_cpu_mask_to_apicid,
-        .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
+        .cpu_mask_to_apicid_and         = flat_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = flat_send_IPI_mask,
         .send_IPI_mask_allbutself       = flat_send_IPI_mask_allbutself,
@@ -262,17 +242,6 @@ static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
         return 0;
 }
 
-static const struct cpumask *physflat_target_cpus(void)
-{
-        return cpu_online_mask;
-}
-
-static void physflat_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
-        cpumask_clear(retmask);
-        cpumask_set_cpu(cpu, retmask);
-}
-
 static void physflat_send_IPI_mask(const struct cpumask *cpumask, int vector)
 {
         default_send_IPI_mask_sequence_phys(cpumask, vector);
@@ -294,38 +263,6 @@ static void physflat_send_IPI_all(int vector)
         physflat_send_IPI_mask(cpu_online_mask, vector);
 }
 
-static unsigned int physflat_cpu_mask_to_apicid(const struct cpumask *cpumask)
-{
-        int cpu;
-
-        /*
-         * We're using fixed IRQ delivery, can only return one phys APIC ID.
-         * May as well be the first.
-         */
-        cpu = cpumask_first(cpumask);
-        if ((unsigned)cpu < nr_cpu_ids)
-                return per_cpu(x86_cpu_to_apicid, cpu);
-        else
-                return BAD_APICID;
-}
-
-static unsigned int
-physflat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                                const struct cpumask *andmask)
-{
-        int cpu;
-
-        /*
-         * We're using fixed IRQ delivery, can only return one phys APIC ID.
-         * May as well be the first.
-         */
-        for_each_cpu_and(cpu, cpumask, andmask) {
-                if (cpumask_test_cpu(cpu, cpu_online_mask))
-                        break;
-        }
-        return per_cpu(x86_cpu_to_apicid, cpu);
-}
-
 static int physflat_probe(void)
 {
         if (apic == &apic_physflat || num_possible_cpus() > 8)
@@ -345,13 +282,13 @@ static struct apic apic_physflat =  {
         .irq_delivery_mode              = dest_Fixed,
         .irq_dest_mode                  = 0, /* physical */
 
-        .target_cpus                    = physflat_target_cpus,
+        .target_cpus                    = online_target_cpus,
         .disable_esr                    = 0,
         .dest_logical                   = 0,
         .check_apicid_used              = NULL,
         .check_apicid_present           = NULL,
 
-        .vector_allocation_domain       = physflat_vector_allocation_domain,
+        .vector_allocation_domain       = default_vector_allocation_domain,
         /* not needed, but shouldn't hurt: */
         .init_apic_ldr                  = flat_init_apic_ldr,
 
@@ -370,8 +307,7 @@ static struct apic apic_physflat =  {
         .set_apic_id                    = set_apic_id,
         .apic_id_mask                   = 0xFFu << 24,
 
-        .cpu_mask_to_apicid             = physflat_cpu_mask_to_apicid,
-        .cpu_mask_to_apicid_and         = physflat_cpu_mask_to_apicid_and,
+        .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = physflat_send_IPI_mask,
         .send_IPI_mask_allbutself       = physflat_send_IPI_mask_allbutself,
diff --git a/arch/x86/kernel/apic/apic_noop.c b/arch/x86/kernel/apic/apic_noop.c
index a6e4c6e06c0..e145f28b409 100644
--- a/arch/x86/kernel/apic/apic_noop.c
+++ b/arch/x86/kernel/apic/apic_noop.c
@@ -100,12 +100,12 @@ static unsigned long noop_check_apicid_present(int bit)
         return physid_isset(bit, phys_cpu_present_map);
 }
 
-static void noop_vector_allocation_domain(int cpu, struct cpumask *retmask)
+static void noop_vector_allocation_domain(int cpu, struct cpumask *retmask,
+                                          const struct cpumask *mask)
 {
         if (cpu != 0)
                 pr_warning("APIC: Vector allocated for non-BSP cpu\n");
-        cpumask_clear(retmask);
-        cpumask_set_cpu(cpu, retmask);
+        cpumask_copy(retmask, cpumask_of(cpu));
 }
 
 static u32 noop_apic_read(u32 reg)
@@ -159,8 +159,7 @@ struct apic apic_noop = {
         .set_apic_id                    = NULL,
         .apic_id_mask                   = 0x0F << 24,
 
-        .cpu_mask_to_apicid             = default_cpu_mask_to_apicid,
-        .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
+        .cpu_mask_to_apicid_and         = flat_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = noop_send_IPI_mask,
         .send_IPI_mask_allbutself       = noop_send_IPI_mask_allbutself,
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 6ec6d5d297c..bc552cff257 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -72,17 +72,6 @@ static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
         return initial_apic_id >> index_msb;
 }
 
-static const struct cpumask *numachip_target_cpus(void)
-{
-        return cpu_online_mask;
-}
-
-static void numachip_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
-        cpumask_clear(retmask);
-        cpumask_set_cpu(cpu, retmask);
-}
-
 static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 {
         union numachip_csr_g3_ext_irq_gen int_gen;
@@ -157,38 +146,6 @@ static void numachip_send_IPI_self(int vector)
         __default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
 }
 
-static unsigned int numachip_cpu_mask_to_apicid(const struct cpumask *cpumask)
-{
-        int cpu;
-
-        /*
-         * We're using fixed IRQ delivery, can only return one phys APIC ID.
-         * May as well be the first.
-         */
-        cpu = cpumask_first(cpumask);
-        if (likely((unsigned)cpu < nr_cpu_ids))
-                return per_cpu(x86_cpu_to_apicid, cpu);
-
-        return BAD_APICID;
-}
-
-static unsigned int
-numachip_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                                const struct cpumask *andmask)
-{
-        int cpu;
-
-        /*
-         * We're using fixed IRQ delivery, can only return one phys APIC ID.
-         * May as well be the first.
-         */
-        for_each_cpu_and(cpu, cpumask, andmask) {
-                if (cpumask_test_cpu(cpu, cpu_online_mask))
-                        break;
-        }
-        return per_cpu(x86_cpu_to_apicid, cpu);
-}
-
 static int __init numachip_probe(void)
 {
         return apic == &apic_numachip;
@@ -253,13 +210,13 @@ static struct apic apic_numachip __refconst = {
         .irq_delivery_mode              = dest_Fixed,
         .irq_dest_mode                  = 0, /* physical */
 
-        .target_cpus                    = numachip_target_cpus,
+        .target_cpus                    = online_target_cpus,
         .disable_esr                    = 0,
         .dest_logical                   = 0,
         .check_apicid_used              = NULL,
         .check_apicid_present           = NULL,
 
-        .vector_allocation_domain       = numachip_vector_allocation_domain,
+        .vector_allocation_domain       = default_vector_allocation_domain,
         .init_apic_ldr                  = flat_init_apic_ldr,
 
         .ioapic_phys_id_map             = NULL,
@@ -277,8 +234,7 @@ static struct apic apic_numachip __refconst = {
         .set_apic_id                    = set_apic_id,
         .apic_id_mask                   = 0xffU << 24,
 
-        .cpu_mask_to_apicid             = numachip_cpu_mask_to_apicid,
-        .cpu_mask_to_apicid_and         = numachip_cpu_mask_to_apicid_and,
+        .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = numachip_send_IPI_mask,
         .send_IPI_mask_allbutself       = numachip_send_IPI_mask_allbutself,
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index 31fbdbfbf96..d50e3640d5a 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -26,15 +26,6 @@ static int bigsmp_apic_id_registered(void)
         return 1;
 }
 
-static const struct cpumask *bigsmp_target_cpus(void)
-{
-#ifdef CONFIG_SMP
-        return cpu_online_mask;
-#else
-        return cpumask_of(0);
-#endif
-}
-
 static unsigned long bigsmp_check_apicid_used(physid_mask_t *map, int apicid)
 {
         return 0;
@@ -105,32 +96,6 @@ static int bigsmp_check_phys_apicid_present(int phys_apicid)
         return 1;
 }
 
-/* As we are using single CPU as destination, pick only one CPU here */
-static unsigned int bigsmp_cpu_mask_to_apicid(const struct cpumask *cpumask)
-{
-        int cpu = cpumask_first(cpumask);
-
-        if (cpu < nr_cpu_ids)
-                return cpu_physical_id(cpu);
-        return BAD_APICID;
-}
-
-static unsigned int bigsmp_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                              const struct cpumask *andmask)
-{
-        int cpu;
-
-        /*
-         * We're using fixed IRQ delivery, can only return one phys APIC ID.
-         * May as well be the first.
-         */
-        for_each_cpu_and(cpu, cpumask, andmask) {
-                if (cpumask_test_cpu(cpu, cpu_online_mask))
-                        return cpu_physical_id(cpu);
-        }
-        return BAD_APICID;
-}
-
 static int bigsmp_phys_pkg_id(int cpuid_apic, int index_msb)
 {
         return cpuid_apic >> index_msb;
@@ -177,12 +142,6 @@ static const struct dmi_system_id bigsmp_dmi_table[] = {
         { } /* NULL entry stops DMI scanning */
 };
 
-static void bigsmp_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
-        cpumask_clear(retmask);
-        cpumask_set_cpu(cpu, retmask);
-}
-
 static int probe_bigsmp(void)
 {
         if (def_to_bigsmp)
@@ -205,13 +164,13 @@ static struct apic apic_bigsmp = {
         /* phys delivery to target CPU: */
         .irq_dest_mode                  = 0,
 
-        .target_cpus                    = bigsmp_target_cpus,
+        .target_cpus                    = default_target_cpus,
         .disable_esr                    = 1,
         .dest_logical                   = 0,
         .check_apicid_used              = bigsmp_check_apicid_used,
         .check_apicid_present           = bigsmp_check_apicid_present,
 
-        .vector_allocation_domain       = bigsmp_vector_allocation_domain,
+        .vector_allocation_domain       = default_vector_allocation_domain,
         .init_apic_ldr                  = bigsmp_init_apic_ldr,
 
         .ioapic_phys_id_map             = bigsmp_ioapic_phys_id_map,
@@ -229,8 +188,7 @@ static struct apic apic_bigsmp = {
         .set_apic_id                    = NULL,
         .apic_id_mask                   = 0xFF << 24,
 
-        .cpu_mask_to_apicid             = bigsmp_cpu_mask_to_apicid,
-        .cpu_mask_to_apicid_and         = bigsmp_cpu_mask_to_apicid_and,
+        .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = bigsmp_send_IPI_mask,
         .send_IPI_mask_allbutself       = NULL,
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
index db4ab1be3c7..0874799a98c 100644
--- a/arch/x86/kernel/apic/es7000_32.c
+++ b/arch/x86/kernel/apic/es7000_32.c
@@ -394,21 +394,6 @@ static void es7000_enable_apic_mode(void)
                 WARN(1, "Command failed, status = %x\n", mip_status);
 }
 
-static void es7000_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
-        /* Careful. Some cpus do not strictly honor the set of cpus
-         * specified in the interrupt destination when using lowest
-         * priority interrupt delivery mode.
-         *
-         * In particular there was a hyperthreading cpu observed to
-         * deliver interrupts to the wrong hyperthread when only one
-         * hyperthread was specified in the interrupt desitination.
-         */
-        cpumask_clear(retmask);
-        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
-}
-
-
 static void es7000_wait_for_init_deassert(atomic_t *deassert)
 {
         while (!atomic_read(deassert))
@@ -540,45 +525,49 @@ static int es7000_check_phys_apicid_present(int cpu_physical_apicid)
         return 1;
 }
 
-static unsigned int es7000_cpu_mask_to_apicid(const struct cpumask *cpumask)
+static inline int
+es7000_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *dest_id)
 {
         unsigned int round = 0;
-        int cpu, uninitialized_var(apicid);
+        unsigned int cpu, uninitialized_var(apicid);
 
         /*
          * The cpus in the mask must all be on the apic cluster.
          */
-        for_each_cpu(cpu, cpumask) {
+        for_each_cpu_and(cpu, cpumask, cpu_online_mask) {
                 int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
 
                 if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
                         WARN(1, "Not a valid mask!");
 
-                        return BAD_APICID;
+                        return -EINVAL;
                 }
-                apicid = new_apicid;
+                apicid |= new_apicid;
                 round++;
         }
-        return apicid;
+        if (!round)
+                return -EINVAL;
+        *dest_id = apicid;
+        return 0;
 }
 
-static unsigned int
+static int
 es7000_cpu_mask_to_apicid_and(const struct cpumask *inmask,
-                              const struct cpumask *andmask)
+                              const struct cpumask *andmask,
+                              unsigned int *apicid)
 {
-        int apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
         cpumask_var_t cpumask;
+        *apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
 
         if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
-                return apicid;
+                return 0;
 
         cpumask_and(cpumask, inmask, andmask);
-        cpumask_and(cpumask, cpumask, cpu_online_mask);
-        apicid = es7000_cpu_mask_to_apicid(cpumask);
+        es7000_cpu_mask_to_apicid(cpumask, apicid);
 
         free_cpumask_var(cpumask);
 
-        return apicid;
+        return 0;
 }
 
 static int es7000_phys_pkg_id(int cpuid_apic, int index_msb)
@@ -638,7 +627,7 @@ static struct apic __refdata apic_es7000_cluster = {
         .check_apicid_used              = es7000_check_apicid_used,
         .check_apicid_present           = es7000_check_apicid_present,
 
-        .vector_allocation_domain       = es7000_vector_allocation_domain,
+        .vector_allocation_domain       = flat_vector_allocation_domain,
         .init_apic_ldr                  = es7000_init_apic_ldr_cluster,
 
         .ioapic_phys_id_map             = es7000_ioapic_phys_id_map,
@@ -656,7 +645,6 @@ static struct apic __refdata apic_es7000_cluster = {
         .set_apic_id                    = NULL,
         .apic_id_mask                   = 0xFF << 24,
 
-        .cpu_mask_to_apicid             = es7000_cpu_mask_to_apicid,
         .cpu_mask_to_apicid_and         = es7000_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = es7000_send_IPI_mask,
@@ -705,7 +693,7 @@ static struct apic __refdata apic_es7000 = {
         .check_apicid_used              = es7000_check_apicid_used,
         .check_apicid_present           = es7000_check_apicid_present,
 
-        .vector_allocation_domain       = es7000_vector_allocation_domain,
+        .vector_allocation_domain       = flat_vector_allocation_domain,
         .init_apic_ldr                  = es7000_init_apic_ldr,
 
         .ioapic_phys_id_map             = es7000_ioapic_phys_id_map,
@@ -723,7 +711,6 @@ static struct apic __refdata apic_es7000 = {
         .set_apic_id                    = NULL,
         .apic_id_mask                   = 0xFF << 24,
 
-        .cpu_mask_to_apicid             = es7000_cpu_mask_to_apicid,
         .cpu_mask_to_apicid_and         = es7000_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = es7000_send_IPI_mask,
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 5f0ff597437..c265593ec2c 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -448,8 +448,8 @@ static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pi
 
         entry = alloc_irq_pin_list(node);
         if (!entry) {
-                printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
-                                node, apic, pin);
+                pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
+                       node, apic, pin);
                 return -ENOMEM;
         }
         entry->apic = apic;
@@ -661,7 +661,7 @@ static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
         ioapic_mask_entry(apic, pin);
         entry = ioapic_read_entry(apic, pin);
         if (entry.irr)
-                printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n",
+                pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
                        mpc_ioapic_id(apic), pin);
 }
 
@@ -895,7 +895,7 @@ static int irq_polarity(int idx)
                 }
                 case 2: /* reserved */
                 {
-                        printk(KERN_WARNING "broken BIOS!!\n");
+                        pr_warn("broken BIOS!!\n");
                         polarity = 1;
                         break;
                 }
@@ -906,7 +906,7 @@ static int irq_polarity(int idx)
                 }
                 default: /* invalid */
                 {
-                        printk(KERN_WARNING "broken BIOS!!\n");
+                        pr_warn("broken BIOS!!\n");
                         polarity = 1;
                         break;
                 }
@@ -948,7 +948,7 @@ static int irq_trigger(int idx)
                                 }
                                 default:
                                 {
-                                        printk(KERN_WARNING "broken BIOS!!\n");
+                                        pr_warn("broken BIOS!!\n");
                                         trigger = 1;
                                         break;
                                 }
@@ -962,7 +962,7 @@ static int irq_trigger(int idx)
                 }
                 case 2: /* reserved */
                 {
-                        printk(KERN_WARNING "broken BIOS!!\n");
+                        pr_warn("broken BIOS!!\n");
                         trigger = 1;
                         break;
                 }
@@ -973,7 +973,7 @@ static int irq_trigger(int idx)
                 }
                 default: /* invalid */
                 {
-                        printk(KERN_WARNING "broken BIOS!!\n");
+                        pr_warn("broken BIOS!!\n");
                         trigger = 0;
                         break;
                 }
@@ -991,7 +991,7 @@ static int pin_2_irq(int idx, int apic, int pin)
          * Debugging check, we are in big trouble if this message pops up!
          */
         if (mp_irqs[idx].dstirq != pin)
-                printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
+                pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
 
         if (test_bit(bus, mp_bus_not_pci)) {
                 irq = mp_irqs[idx].srcbusirq;
@@ -1112,8 +1112,7 @@ __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
          * 0x80, because int 0x80 is hm, kind of importantish. ;)
          */
         static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
-        static int current_offset = VECTOR_OFFSET_START % 8;
-        unsigned int old_vector;
+        static int current_offset = VECTOR_OFFSET_START % 16;
         int cpu, err;
         cpumask_var_t tmp_mask;
 
@@ -1123,35 +1122,45 @@ __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
                 return -ENOMEM;
 
-        old_vector = cfg->vector;
-        if (old_vector) {
-                cpumask_and(tmp_mask, mask, cpu_online_mask);
-                cpumask_and(tmp_mask, cfg->domain, tmp_mask);
-                if (!cpumask_empty(tmp_mask)) {
-                        free_cpumask_var(tmp_mask);
-                        return 0;
-                }
-        }
-
         /* Only try and allocate irqs on cpus that are present */
         err = -ENOSPC;
-        for_each_cpu_and(cpu, mask, cpu_online_mask) {
-                int new_cpu;
-                int vector, offset;
+        cpumask_clear(cfg->old_domain);
+        cpu = cpumask_first_and(mask, cpu_online_mask);
+        while (cpu < nr_cpu_ids) {
+                int new_cpu, vector, offset;
 
-                apic->vector_allocation_domain(cpu, tmp_mask);
+                apic->vector_allocation_domain(cpu, tmp_mask, mask);
+
+                if (cpumask_subset(tmp_mask, cfg->domain)) {
+                        err = 0;
+                        if (cpumask_equal(tmp_mask, cfg->domain))
+                                break;
+                        /*
+                         * New cpumask using the vector is a proper subset of
+                         * the current in use mask. So cleanup the vector
+                         * allocation for the members that are not used anymore.
+                         */
+                        cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask);
+                        cfg->move_in_progress = 1;
+                        cpumask_and(cfg->domain, cfg->domain, tmp_mask);
+                        break;
+                }
 
                 vector = current_vector;
                 offset = current_offset;
 next:
-                vector += 8;
+                vector += 16;
                 if (vector >= first_system_vector) {
-                        /* If out of vectors on large boxen, must share them. */
-                        offset = (offset + 1) % 8;
+                        offset = (offset + 1) % 16;
                         vector = FIRST_EXTERNAL_VECTOR + offset;
                 }
-                if (unlikely(current_vector == vector))
+
+                if (unlikely(current_vector == vector)) {
+                        cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask);
+                        cpumask_andnot(tmp_mask, mask, cfg->old_domain);
+                        cpu = cpumask_first_and(tmp_mask, cpu_online_mask);
                         continue;
+                }
 
                 if (test_bit(vector, used_vectors))
                         goto next;
@@ -1162,7 +1171,7 @@ next:
                 /* Found one! */
                 current_vector = vector;
                 current_offset = offset;
-                if (old_vector) {
+                if (cfg->vector) {
                         cfg->move_in_progress = 1;
                         cpumask_copy(cfg->old_domain, cfg->domain);
                 }
@@ -1195,7 +1204,7 @@ static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
         BUG_ON(!cfg->vector);
 
         vector = cfg->vector;
-        for_each_cpu(cpu, cfg->domain)
+        for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
                 per_cpu(vector_irq, cpu)[vector] = -1;
 
         cfg->vector = 0;
@@ -1203,7 +1212,7 @@ static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
 
         if (likely(!cfg->move_in_progress))
                 return;
-        for_each_cpu(cpu, cfg->old_domain) {
+        for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
                                                                 vector++) {
                         if (per_cpu(vector_irq, cpu)[vector] != irq)
@@ -1346,18 +1355,28 @@ static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
 
         if (!IO_APIC_IRQ(irq))
                 return;
+
         /*
-         * For legacy irqs, cfg->domain starts with cpu 0 for legacy
-         * controllers like 8259. Now that IO-APIC can handle this irq, update
-         * the cfg->domain.
+         * For legacy irqs, cfg->domain starts with cpu 0. Now that IO-APIC
+         * can handle this irq and the apic driver is finialized at this point,
+         * update the cfg->domain.
          */
-        if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
-                apic->vector_allocation_domain(0, cfg->domain);
+        if (irq < legacy_pic->nr_legacy_irqs &&
+            cpumask_equal(cfg->domain, cpumask_of(0)))
+                apic->vector_allocation_domain(0, cfg->domain,
+                                               apic->target_cpus());
 
         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
                 return;
 
-        dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
+        if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(),
+                                         &dest)) {
+                pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
+                        mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
+                __clear_irq_vector(irq, cfg);
+
+                return;
+        }
 
         apic_printk(APIC_VERBOSE,KERN_DEBUG
                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
@@ -1366,7 +1385,7 @@ static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
                     cfg->vector, irq, attr->trigger, attr->polarity, dest);
 
         if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
-                pr_warn("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
+                pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
                         mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
                 __clear_irq_vector(irq, cfg);
 
@@ -1469,9 +1488,10 @@ void setup_IO_APIC_irq_extra(u32 gsi)
  * Set up the timer pin, possibly with the 8259A-master behind.
  */
 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
-                                         unsigned int pin, int vector)
+                                        unsigned int pin, int vector)
 {
         struct IO_APIC_route_entry entry;
+        unsigned int dest;
 
         if (irq_remapping_enabled)
                 return;
@@ -1482,9 +1502,13 @@ static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
          * We use logical delivery to get the timer IRQ
          * to the first CPU.
          */
+        if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(),
+                                                  apic->target_cpus(), &dest)))
+                dest = BAD_APICID;
+
         entry.dest_mode = apic->irq_dest_mode;
         entry.mask = 0;                 /* don't mask IRQ for edge */
-        entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
+        entry.dest = dest;
         entry.delivery_mode = apic->irq_delivery_mode;
         entry.polarity = 0;
         entry.trigger = 0;
@@ -1521,7 +1545,6 @@ __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
                 reg_03.raw = io_apic_read(ioapic_idx, 3);
         raw_spin_unlock_irqrestore(&ioapic_lock, flags);
 
-        printk("\n");
         printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
@@ -1578,7 +1601,7 @@ __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
                                 i,
                                 ir_entry->index
                         );
-                        printk("%1d   %1d    %1d    %1d   %1d   "
+                        pr_cont("%1d   %1d    %1d    %1d   %1d   "
                                 "%1d    %1d     %X    %02X\n",
                                 ir_entry->format,
                                 ir_entry->mask,
@@ -1598,7 +1621,7 @@ __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
                                 i,
                                 entry.dest
                         );
-                        printk("%1d    %1d    %1d   %1d   %1d    "
+                        pr_cont("%1d    %1d    %1d   %1d   %1d    "
                                 "%1d    %1d    %02X\n",
                                 entry.mask,
                                 entry.trigger,
@@ -1651,8 +1674,8 @@ __apicdebuginit(void) print_IO_APICs(void)
                         continue;
                 printk(KERN_DEBUG "IRQ%d ", irq);
                 for_each_irq_pin(entry, cfg->irq_2_pin)
-                        printk("-> %d:%d", entry->apic, entry->pin);
-                printk("\n");
+                        pr_cont("-> %d:%d", entry->apic, entry->pin);
+                pr_cont("\n");
         }
 
         printk(KERN_INFO ".................................... done.\n");
@@ -1665,9 +1688,9 @@ __apicdebuginit(void) print_APIC_field(int base)
         printk(KERN_DEBUG);
 
         for (i = 0; i < 8; i++)
-                printk(KERN_CONT "%08x", apic_read(base + i*0x10));
+                pr_cont("%08x", apic_read(base + i*0x10));
 
-        printk(KERN_CONT "\n");
+        pr_cont("\n");
 }
 
 __apicdebuginit(void) print_local_APIC(void *dummy)
@@ -1769,7 +1792,7 @@ __apicdebuginit(void) print_local_APIC(void *dummy)
                         printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
                 }
         }
-        printk("\n");
+        pr_cont("\n");
 }
 
 __apicdebuginit(void) print_local_APICs(int maxcpu)
@@ -2065,7 +2088,7 @@ void __init setup_ioapic_ids_from_mpc_nocheck(void)
                 reg_00.raw = io_apic_read(ioapic_idx, 0);
                 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
                 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
-                        printk("could not set ID!\n");
+                        pr_cont("could not set ID!\n");
                 else
                         apic_printk(APIC_VERBOSE, " ok.\n");
         }
@@ -2210,71 +2233,6 @@ void send_cleanup_vector(struct irq_cfg *cfg)
         cfg->move_in_progress = 0;
 }
 
-static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
-{
-        int apic, pin;
-        struct irq_pin_list *entry;
-        u8 vector = cfg->vector;
-
-        for_each_irq_pin(entry, cfg->irq_2_pin) {
-                unsigned int reg;
-
-                apic = entry->apic;
-                pin = entry->pin;
-                /*
-                 * With interrupt-remapping, destination information comes
-                 * from interrupt-remapping table entry.
-                 */
-                if (!irq_remapped(cfg))
-                        io_apic_write(apic, 0x11 + pin*2, dest);
-                reg = io_apic_read(apic, 0x10 + pin*2);
-                reg &= ~IO_APIC_REDIR_VECTOR_MASK;
-                reg |= vector;
-                io_apic_modify(apic, 0x10 + pin*2, reg);
-        }
-}
-
-/*
- * Either sets data->affinity to a valid value, and returns
- * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
- * leaves data->affinity untouched.
- */
-int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
-                          unsigned int *dest_id)
-{
-        struct irq_cfg *cfg = data->chip_data;
-
-        if (!cpumask_intersects(mask, cpu_online_mask))
-                return -1;
-
-        if (assign_irq_vector(data->irq, data->chip_data, mask))
-                return -1;
-
-        cpumask_copy(data->affinity, mask);
-
-        *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
-        return 0;
-}
-
-static int
-ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
-                    bool force)
-{
-        unsigned int dest, irq = data->irq;
-        unsigned long flags;
-        int ret;
-
-        raw_spin_lock_irqsave(&ioapic_lock, flags);
-        ret = __ioapic_set_affinity(data, mask, &dest);
-        if (!ret) {
-                /* Only the high 8 bits are valid. */
-                dest = SET_APIC_LOGICAL_ID(dest);
-                __target_IO_APIC_irq(irq, dest, data->chip_data);
-        }
-        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
-        return ret;
-}
-
 asmlinkage void smp_irq_move_cleanup_interrupt(void)
 {
         unsigned vector, me;
@@ -2362,6 +2320,87 @@ void irq_force_complete_move(int irq)
 static inline void irq_complete_move(struct irq_cfg *cfg) { }
 #endif
 
+static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
+{
+        int apic, pin;
+        struct irq_pin_list *entry;
+        u8 vector = cfg->vector;
+
+        for_each_irq_pin(entry, cfg->irq_2_pin) {
+                unsigned int reg;
+
+                apic = entry->apic;
+                pin = entry->pin;
+                /*
+                 * With interrupt-remapping, destination information comes
+                 * from interrupt-remapping table entry.
+                 */
+                if (!irq_remapped(cfg))
+                        io_apic_write(apic, 0x11 + pin*2, dest);
+                reg = io_apic_read(apic, 0x10 + pin*2);
+                reg &= ~IO_APIC_REDIR_VECTOR_MASK;
+                reg |= vector;
+                io_apic_modify(apic, 0x10 + pin*2, reg);
+        }
+}
+
+/*
+ * Either sets data->affinity to a valid value, and returns
+ * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
+ * leaves data->affinity untouched.
+ */
+int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
+                          unsigned int *dest_id)
+{
+        struct irq_cfg *cfg = data->chip_data;
+        unsigned int irq = data->irq;
+        int err;
+
+        if (!config_enabled(CONFIG_SMP))
+                return -1;
+
+        if (!cpumask_intersects(mask, cpu_online_mask))
+                return -EINVAL;
+
+        err = assign_irq_vector(irq, cfg, mask);
+        if (err)
+                return err;
+
+        err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id);
+        if (err) {
+                if (assign_irq_vector(irq, cfg, data->affinity))
+                        pr_err("Failed to recover vector for irq %d\n", irq);
+                return err;
+        }
+
+        cpumask_copy(data->affinity, mask);
+
+        return 0;
+}
+
+static int
+ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
+                    bool force)
+{
+        unsigned int dest, irq = data->irq;
+        unsigned long flags;
+        int ret;
+
+        if (!config_enabled(CONFIG_SMP))
+                return -1;
+
+        raw_spin_lock_irqsave(&ioapic_lock, flags);
+        ret = __ioapic_set_affinity(data, mask, &dest);
+        if (!ret) {
+                /* Only the high 8 bits are valid. */
+                dest = SET_APIC_LOGICAL_ID(dest);
+                __target_IO_APIC_irq(irq, dest, data->chip_data);
+                ret = IRQ_SET_MASK_OK_NOCOPY;
+        }
+        raw_spin_unlock_irqrestore(&ioapic_lock, flags);
+        return ret;
+}
+
 static void ack_apic_edge(struct irq_data *data)
 {
         irq_complete_move(data->chip_data);
@@ -2541,9 +2580,7 @@ static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
         chip->irq_ack = ir_ack_apic_edge;
         chip->irq_eoi = ir_ack_apic_level;
 
-#ifdef CONFIG_SMP
         chip->irq_set_affinity = set_remapped_irq_affinity;
-#endif
 }
 #endif /* CONFIG_IRQ_REMAP */
 
@@ -2554,9 +2591,7 @@ static struct irq_chip ioapic_chip __read_mostly = {
         .irq_unmask             = unmask_ioapic_irq,
         .irq_ack                = ack_apic_edge,
         .irq_eoi                = ack_apic_level,
-#ifdef CONFIG_SMP
         .irq_set_affinity       = ioapic_set_affinity,
-#endif
         .irq_retrigger          = ioapic_retrigger_irq,
 };
 
@@ -3038,7 +3073,10 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
         if (err)
                 return err;
 
-        dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
+        err = apic->cpu_mask_to_apicid_and(cfg->domain,
+                                           apic->target_cpus(), &dest);
+        if (err)
+                return err;
 
         if (irq_remapped(cfg)) {
                 compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id);
@@ -3072,7 +3110,6 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
         return err;
 }
 
-#ifdef CONFIG_SMP
 static int
 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
 {
@@ -3092,9 +3129,8 @@ msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
 
         __write_msi_msg(data->msi_desc, &msg);
 
-        return 0;
+        return IRQ_SET_MASK_OK_NOCOPY;
 }
-#endif /* CONFIG_SMP */
 
 /*
  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
@@ -3105,9 +3141,7 @@ static struct irq_chip msi_chip = {
         .irq_unmask             = unmask_msi_irq,
         .irq_mask               = mask_msi_irq,
         .irq_ack                = ack_apic_edge,
-#ifdef CONFIG_SMP
         .irq_set_affinity       = msi_set_affinity,
-#endif
         .irq_retrigger          = ioapic_retrigger_irq,
 };
 
@@ -3192,7 +3226,6 @@ void native_teardown_msi_irq(unsigned int irq)
 }
 
 #ifdef CONFIG_DMAR_TABLE
-#ifdef CONFIG_SMP
 static int
 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
                       bool force)
@@ -3214,19 +3247,15 @@ dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
 
         dmar_msi_write(irq, &msg);
 
-        return 0;
+        return IRQ_SET_MASK_OK_NOCOPY;
 }
 
-#endif /* CONFIG_SMP */
-
 static struct irq_chip dmar_msi_type = {
         .name                   = "DMAR_MSI",
         .irq_unmask             = dmar_msi_unmask,
         .irq_mask               = dmar_msi_mask,
         .irq_ack                = ack_apic_edge,
-#ifdef CONFIG_SMP
         .irq_set_affinity       = dmar_msi_set_affinity,
-#endif
         .irq_retrigger          = ioapic_retrigger_irq,
 };
 
@@ -3247,7 +3276,6 @@ int arch_setup_dmar_msi(unsigned int irq)
 
 #ifdef CONFIG_HPET_TIMER
 
-#ifdef CONFIG_SMP
 static int hpet_msi_set_affinity(struct irq_data *data,
                                  const struct cpumask *mask, bool force)
 {
@@ -3267,19 +3295,15 @@ static int hpet_msi_set_affinity(struct irq_data *data,
 
         hpet_msi_write(data->handler_data, &msg);
 
-        return 0;
+        return IRQ_SET_MASK_OK_NOCOPY;
 }
 
-#endif /* CONFIG_SMP */
-
 static struct irq_chip hpet_msi_type = {
         .name = "HPET_MSI",
         .irq_unmask = hpet_msi_unmask,
         .irq_mask = hpet_msi_mask,
         .irq_ack = ack_apic_edge,
-#ifdef CONFIG_SMP
         .irq_set_affinity = hpet_msi_set_affinity,
-#endif
         .irq_retrigger = ioapic_retrigger_irq,
 };
 
@@ -3314,8 +3338,6 @@ int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
  */
 #ifdef CONFIG_HT_IRQ
 
-#ifdef CONFIG_SMP
-
 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
 {
         struct ht_irq_msg msg;
@@ -3340,25 +3362,23 @@ ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
                 return -1;
 
         target_ht_irq(data->irq, dest, cfg->vector);
-        return 0;
+        return IRQ_SET_MASK_OK_NOCOPY;
 }
 
-#endif
-
 static struct irq_chip ht_irq_chip = {
         .name                   = "PCI-HT",
         .irq_mask               = mask_ht_irq,
         .irq_unmask             = unmask_ht_irq,
         .irq_ack                = ack_apic_edge,
-#ifdef CONFIG_SMP
         .irq_set_affinity       = ht_set_affinity,
-#endif
         .irq_retrigger          = ioapic_retrigger_irq,
 };
 
 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
 {
         struct irq_cfg *cfg;
+        struct ht_irq_msg msg;
+        unsigned dest;
         int err;
 
         if (disable_apic)
@@ -3366,36 +3386,37 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
 
         cfg = irq_cfg(irq);
         err = assign_irq_vector(irq, cfg, apic->target_cpus());
-        if (!err) {
-                struct ht_irq_msg msg;
-                unsigned dest;
+        if (err)
+                return err;
+
+        err = apic->cpu_mask_to_apicid_and(cfg->domain,
+                                           apic->target_cpus(), &dest);
+        if (err)
+                return err;
 
-                dest = apic->cpu_mask_to_apicid_and(cfg->domain,
-                                                    apic->target_cpus());
+        msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
 
-                msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
+        msg.address_lo =
+                HT_IRQ_LOW_BASE |
+                HT_IRQ_LOW_DEST_ID(dest) |
+                HT_IRQ_LOW_VECTOR(cfg->vector) |
+                ((apic->irq_dest_mode == 0) ?
+                        HT_IRQ_LOW_DM_PHYSICAL :
+                        HT_IRQ_LOW_DM_LOGICAL) |
+                HT_IRQ_LOW_RQEOI_EDGE |
+                ((apic->irq_delivery_mode != dest_LowestPrio) ?
+                        HT_IRQ_LOW_MT_FIXED :
+                        HT_IRQ_LOW_MT_ARBITRATED) |
+                HT_IRQ_LOW_IRQ_MASKED;
 
-                msg.address_lo =
-                        HT_IRQ_LOW_BASE |
-                        HT_IRQ_LOW_DEST_ID(dest) |
-                        HT_IRQ_LOW_VECTOR(cfg->vector) |
-                        ((apic->irq_dest_mode == 0) ?
-                                HT_IRQ_LOW_DM_PHYSICAL :
-                                HT_IRQ_LOW_DM_LOGICAL) |
-                        HT_IRQ_LOW_RQEOI_EDGE |
-                        ((apic->irq_delivery_mode != dest_LowestPrio) ?
-                                HT_IRQ_LOW_MT_FIXED :
-                                HT_IRQ_LOW_MT_ARBITRATED) |
-                        HT_IRQ_LOW_IRQ_MASKED;
+        write_ht_irq_msg(irq, &msg);
 
-                write_ht_irq_msg(irq, &msg);
+        irq_set_chip_and_handler_name(irq, &ht_irq_chip,
+                                      handle_edge_irq, "edge");
 
-                irq_set_chip_and_handler_name(irq, &ht_irq_chip,
-                                              handle_edge_irq, "edge");
+        dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
 
-                dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
-        }
-        return err;
+        return 0;
 }
 #endif /* CONFIG_HT_IRQ */
 
@@ -3563,7 +3584,8 @@ static int __init io_apic_get_unique_id(int ioapic, int apic_id)
 
                 /* Sanity check */
                 if (reg_00.bits.ID != apic_id) {
-                        printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
+                        pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
+                               ioapic);
                         return -1;
                 }
         }
diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c
index f00a68cca37..d661ee95cab 100644
--- a/arch/x86/kernel/apic/numaq_32.c
+++ b/arch/x86/kernel/apic/numaq_32.c
@@ -406,16 +406,13 @@ static inline int numaq_check_phys_apicid_present(int phys_apicid)
  * We use physical apicids here, not logical, so just return the default
  * physical broadcast to stop people from breaking us
  */
-static unsigned int numaq_cpu_mask_to_apicid(const struct cpumask *cpumask)
-{
-        return 0x0F;
-}
-
-static inline unsigned int
+static int
 numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                             const struct cpumask *andmask)
+                             const struct cpumask *andmask,
+                             unsigned int *apicid)
 {
-        return 0x0F;
+        *apicid = 0x0F;
+        return 0;
 }
 
 /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
@@ -441,20 +438,6 @@ static int probe_numaq(void)
         return found_numaq;
 }
 
-static void numaq_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
-        /* Careful. Some cpus do not strictly honor the set of cpus
-         * specified in the interrupt destination when using lowest
-         * priority interrupt delivery mode.
-         *
-         * In particular there was a hyperthreading cpu observed to
-         * deliver interrupts to the wrong hyperthread when only one
-         * hyperthread was specified in the interrupt desitination.
-         */
-        cpumask_clear(retmask);
-        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
-}
-
 static void numaq_setup_portio_remap(void)
 {
         int num_quads = num_online_nodes();
@@ -491,7 +474,7 @@ static struct apic __refdata apic_numaq = {
         .check_apicid_used              = numaq_check_apicid_used,
         .check_apicid_present           = numaq_check_apicid_present,
 
-        .vector_allocation_domain       = numaq_vector_allocation_domain,
+        .vector_allocation_domain       = flat_vector_allocation_domain,
         .init_apic_ldr                  = numaq_init_apic_ldr,
 
         .ioapic_phys_id_map             = numaq_ioapic_phys_id_map,
@@ -509,7 +492,6 @@ static struct apic __refdata apic_numaq = {
         .set_apic_id                    = NULL,
         .apic_id_mask                   = 0x0F << 24,
 
-        .cpu_mask_to_apicid             = numaq_cpu_mask_to_apicid,
         .cpu_mask_to_apicid_and         = numaq_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = numaq_send_IPI_mask,
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index 1b291da09e6..eb35ef9ee63 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -66,21 +66,6 @@ static void setup_apic_flat_routing(void)
 #endif
 }
 
-static void default_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
-        /*
-         * Careful. Some cpus do not strictly honor the set of cpus
-         * specified in the interrupt destination when using lowest
-         * priority interrupt delivery mode.
-         *
-         * In particular there was a hyperthreading cpu observed to
-         * deliver interrupts to the wrong hyperthread when only one
-         * hyperthread was specified in the interrupt desitination.
-         */
-        cpumask_clear(retmask);
-        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
-}
-
 /* should be called last. */
 static int probe_default(void)
 {
@@ -105,7 +90,7 @@ static struct apic apic_default = {
         .check_apicid_used              = default_check_apicid_used,
         .check_apicid_present           = default_check_apicid_present,
 
-        .vector_allocation_domain       = default_vector_allocation_domain,
+        .vector_allocation_domain       = flat_vector_allocation_domain,
         .init_apic_ldr                  = default_init_apic_ldr,
 
         .ioapic_phys_id_map             = default_ioapic_phys_id_map,
@@ -123,8 +108,7 @@ static struct apic apic_default = {
         .set_apic_id                    = NULL,
         .apic_id_mask                   = 0x0F << 24,
 
-        .cpu_mask_to_apicid             = default_cpu_mask_to_apicid,
-        .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
+        .cpu_mask_to_apicid_and         = flat_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = default_send_IPI_mask_logical,
         .send_IPI_mask_allbutself       = default_send_IPI_mask_allbutself_logical,
@@ -208,6 +192,9 @@ void __init default_setup_apic_routing(void)
 
         if (apic->setup_apic_routing)
                 apic->setup_apic_routing();
+
+        if (x86_platform.apic_post_init)
+                x86_platform.apic_post_init();
 }
 
 void __init generic_apic_probe(void)
diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c
index 3fe98669892..1793dba7a74 100644
--- a/arch/x86/kernel/apic/probe_64.c
+++ b/arch/x86/kernel/apic/probe_64.c
@@ -23,11 +23,6 @@
 #include <asm/ipi.h>
 #include <asm/setup.h>
 
-static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
-{
-        return hard_smp_processor_id() >> index_msb;
-}
-
 /*
  * Check the APIC IDs in bios_cpu_apicid and choose the APIC mode.
  */
@@ -48,10 +43,8 @@ void __init default_setup_apic_routing(void)
                 }
         }
 
-        if (is_vsmp_box()) {
-                /* need to update phys_pkg_id */
-                apic->phys_pkg_id = apicid_phys_pkg_id;
-        }
+        if (x86_platform.apic_post_init)
+                x86_platform.apic_post_init();
 }
 
 /* Same for both flat and physical. */
diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c
index 659897c0075..77c95c0e1bf 100644
--- a/arch/x86/kernel/apic/summit_32.c
+++ b/arch/x86/kernel/apic/summit_32.c
@@ -26,6 +26,8 @@
  *
  */
 
+#define pr_fmt(fmt) "summit: %s: " fmt, __func__
+
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <asm/io.h>
@@ -235,8 +237,8 @@ static int summit_apic_id_registered(void)
 
 static void summit_setup_apic_routing(void)
 {
-        printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
-                                                nr_ioapics);
+        pr_info("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
+                nr_ioapics);
 }
 
 static int summit_cpu_present_to_apicid(int mps_cpu)
@@ -263,43 +265,48 @@ static int summit_check_phys_apicid_present(int physical_apicid)
         return 1;
 }
 
-static unsigned int summit_cpu_mask_to_apicid(const struct cpumask *cpumask)
+static inline int
+summit_cpu_mask_to_apicid(const struct cpumask *cpumask, unsigned int *dest_id)
 {
         unsigned int round = 0;
-        int cpu, apicid = 0;
+        unsigned int cpu, apicid = 0;
 
         /*
          * The cpus in the mask must all be on the apic cluster.
          */
-        for_each_cpu(cpu, cpumask) {
+        for_each_cpu_and(cpu, cpumask, cpu_online_mask) {
                 int new_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
 
                 if (round && APIC_CLUSTER(apicid) != APIC_CLUSTER(new_apicid)) {
-                        printk("%s: Not a valid mask!\n", __func__);
-                        return BAD_APICID;
+                        pr_err("Not a valid mask!\n");
+                        return -EINVAL;
                 }
                 apicid |= new_apicid;
                 round++;
         }
-        return apicid;
+        if (!round)
+                return -EINVAL;
+        *dest_id = apicid;
+        return 0;
 }
 
-static unsigned int summit_cpu_mask_to_apicid_and(const struct cpumask *inmask,
-                              const struct cpumask *andmask)
+static int
+summit_cpu_mask_to_apicid_and(const struct cpumask *inmask,
+                              const struct cpumask *andmask,
+                              unsigned int *apicid)
 {
-        int apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
         cpumask_var_t cpumask;
+        *apicid = early_per_cpu(x86_cpu_to_logical_apicid, 0);
 
         if (!alloc_cpumask_var(&cpumask, GFP_ATOMIC))
-                return apicid;
+                return 0;
 
         cpumask_and(cpumask, inmask, andmask);
-        cpumask_and(cpumask, cpumask, cpu_online_mask);
-        apicid = summit_cpu_mask_to_apicid(cpumask);
+        summit_cpu_mask_to_apicid(cpumask, apicid);
 
         free_cpumask_var(cpumask);
 
-        return apicid;
+        return 0;
 }
 
 /*
@@ -320,20 +327,6 @@ static int probe_summit(void)
         return 0;
 }
 
-static void summit_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
-        /* Careful. Some cpus do not strictly honor the set of cpus
-         * specified in the interrupt destination when using lowest
-         * priority interrupt delivery mode.
-         *
-         * In particular there was a hyperthreading cpu observed to
-         * deliver interrupts to the wrong hyperthread when only one
-         * hyperthread was specified in the interrupt desitination.
-         */
-        cpumask_clear(retmask);
-        cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
-}
-
 #ifdef CONFIG_X86_SUMMIT_NUMA
 static struct rio_table_hdr *rio_table_hdr;
 static struct scal_detail   *scal_devs[MAX_NUMNODES];
@@ -355,7 +348,7 @@ static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
                 }
         }
         if (i == rio_table_hdr->num_rio_dev) {
-                printk(KERN_ERR "%s: Couldn't find owner Cyclone for Winnipeg!\n", __func__);
+                pr_err("Couldn't find owner Cyclone for Winnipeg!\n");
                 return last_bus;
         }
 
@@ -366,7 +359,7 @@ static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
                 }
         }
         if (i == rio_table_hdr->num_scal_dev) {
-                printk(KERN_ERR "%s: Couldn't find owner Twister for Cyclone!\n", __func__);
+                pr_err("Couldn't find owner Twister for Cyclone!\n");
                 return last_bus;
         }
 
@@ -396,7 +389,7 @@ static int setup_pci_node_map_for_wpeg(int wpeg_num, int last_bus)
                 num_buses = 9;
                 break;
         default:
-                printk(KERN_INFO "%s: Unsupported Winnipeg type!\n", __func__);
+                pr_info("Unsupported Winnipeg type!\n");
                 return last_bus;
         }
 
@@ -411,13 +404,15 @@ static int build_detail_arrays(void)
         int i, scal_detail_size, rio_detail_size;
 
         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES) {
-                printk(KERN_WARNING "%s: MAX_NUMNODES too low!  Defined as %d, but system has %d nodes.\n", __func__, MAX_NUMNODES, rio_table_hdr->num_scal_dev);
+                pr_warn("MAX_NUMNODES too low!  Defined as %d, but system has %d nodes\n",
+                        MAX_NUMNODES, rio_table_hdr->num_scal_dev);
                 return 0;
         }
 
         switch (rio_table_hdr->version) {
         default:
-                printk(KERN_WARNING "%s: Invalid Rio Grande Table Version: %d\n", __func__, rio_table_hdr->version);
+                pr_warn("Invalid Rio Grande Table Version: %d\n",
+                        rio_table_hdr->version);
                 return 0;
         case 2:
                 scal_detail_size = 11;
@@ -462,7 +457,7 @@ void setup_summit(void)
                 offset = *((unsigned short *)(ptr + offset));
         }
         if (!rio_table_hdr) {
-                printk(KERN_ERR "%s: Unable to locate Rio Grande Table in EBDA - bailing!\n", __func__);
+                pr_err("Unable to locate Rio Grande Table in EBDA - bailing!\n");
                 return;
         }
 
@@ -509,7 +504,7 @@ static struct apic apic_summit = {
         .check_apicid_used              = summit_check_apicid_used,
         .check_apicid_present           = summit_check_apicid_present,
 
-        .vector_allocation_domain       = summit_vector_allocation_domain,
+        .vector_allocation_domain       = flat_vector_allocation_domain,
         .init_apic_ldr                  = summit_init_apic_ldr,
 
         .ioapic_phys_id_map             = summit_ioapic_phys_id_map,
@@ -527,7 +522,6 @@ static struct apic apic_summit = {
         .set_apic_id                    = NULL,
         .apic_id_mask                   = 0xFF << 24,
 
-        .cpu_mask_to_apicid             = summit_cpu_mask_to_apicid,
         .cpu_mask_to_apicid_and         = summit_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = summit_send_IPI_mask,
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
index ff35cff0e1a..c88baa4ff0e 100644
--- a/arch/x86/kernel/apic/x2apic_cluster.c
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -81,7 +81,7 @@ static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
 }
 
 static void
- x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
+x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 {
         __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
 }
@@ -96,36 +96,37 @@ static void x2apic_send_IPI_all(int vector)
         __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
 }
 
-static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
+static int
+x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
+                              const struct cpumask *andmask,
+                              unsigned int *apicid)
 {
-        /*
-         * We're using fixed IRQ delivery, can only return one logical APIC ID.
-         * May as well be the first.
-         */
-        int cpu = cpumask_first(cpumask);
+        u32 dest = 0;
+        u16 cluster;
+        int i;
 
-        if ((unsigned)cpu < nr_cpu_ids)
-                return per_cpu(x86_cpu_to_logical_apicid, cpu);
-        else
-                return BAD_APICID;
-}
+        for_each_cpu_and(i, cpumask, andmask) {
+                if (!cpumask_test_cpu(i, cpu_online_mask))
+                        continue;
+                dest = per_cpu(x86_cpu_to_logical_apicid, i);
+                cluster = x2apic_cluster(i);
+                break;
+        }
 
-static unsigned int
-x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                              const struct cpumask *andmask)
-{
-        int cpu;
+        if (!dest)
+                return -EINVAL;
 
-        /*
-         * We're using fixed IRQ delivery, can only return one logical APIC ID.
-         * May as well be the first.
-         */
-        for_each_cpu_and(cpu, cpumask, andmask) {
-                if (cpumask_test_cpu(cpu, cpu_online_mask))
-                        break;
+        for_each_cpu_and(i, cpumask, andmask) {
+                if (!cpumask_test_cpu(i, cpu_online_mask))
+                        continue;
+                if (cluster != x2apic_cluster(i))
+                        continue;
+                dest |= per_cpu(x86_cpu_to_logical_apicid, i);
         }
 
-        return per_cpu(x86_cpu_to_logical_apicid, cpu);
+        *apicid = dest;
+
+        return 0;
 }
 
 static void init_x2apic_ldr(void)
@@ -208,6 +209,32 @@ static int x2apic_cluster_probe(void)
                 return 0;
 }
 
+static const struct cpumask *x2apic_cluster_target_cpus(void)
+{
+        return cpu_all_mask;
+}
+
+/*
+ * Each x2apic cluster is an allocation domain.
+ */
+static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask,
+                                             const struct cpumask *mask)
+{
+        /*
+         * To minimize vector pressure, default case of boot, device bringup
+         * etc will use a single cpu for the interrupt destination.
+         *
+         * On explicit migration requests coming from irqbalance etc,
+         * interrupts will be routed to the x2apic cluster (cluster-id
+         * derived from the first cpu in the mask) members specified
+         * in the mask.
+         */
+        if (mask == x2apic_cluster_target_cpus())
+                cpumask_copy(retmask, cpumask_of(cpu));
+        else
+                cpumask_and(retmask, mask, per_cpu(cpus_in_cluster, cpu));
+}
+
 static struct apic apic_x2apic_cluster = {
 
         .name                           = "cluster x2apic",
@@ -219,13 +246,13 @@ static struct apic apic_x2apic_cluster = {
         .irq_delivery_mode              = dest_LowestPrio,
         .irq_dest_mode                  = 1, /* logical */
 
-        .target_cpus                    = x2apic_target_cpus,
+        .target_cpus                    = x2apic_cluster_target_cpus,
         .disable_esr                    = 0,
         .dest_logical                   = APIC_DEST_LOGICAL,
         .check_apicid_used              = NULL,
         .check_apicid_present           = NULL,
 
-        .vector_allocation_domain       = x2apic_vector_allocation_domain,
+        .vector_allocation_domain       = cluster_vector_allocation_domain,
         .init_apic_ldr                  = init_x2apic_ldr,
 
         .ioapic_phys_id_map             = NULL,
@@ -243,7 +270,6 @@ static struct apic apic_x2apic_cluster = {
         .set_apic_id                    = x2apic_set_apic_id,
         .apic_id_mask                   = 0xFFFFFFFFu,
 
-        .cpu_mask_to_apicid             = x2apic_cpu_mask_to_apicid,
         .cpu_mask_to_apicid_and         = x2apic_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = x2apic_send_IPI_mask,
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index c17e982db27..e03a1e180e8 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -76,38 +76,6 @@ static void x2apic_send_IPI_all(int vector)
         __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
 }
 
-static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
-{
-        /*
-         * We're using fixed IRQ delivery, can only return one phys APIC ID.
-         * May as well be the first.
-         */
-        int cpu = cpumask_first(cpumask);
-
-        if ((unsigned)cpu < nr_cpu_ids)
-                return per_cpu(x86_cpu_to_apicid, cpu);
-        else
-                return BAD_APICID;
-}
-
-static unsigned int
-x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                              const struct cpumask *andmask)
-{
-        int cpu;
-
-        /*
-         * We're using fixed IRQ delivery, can only return one phys APIC ID.
-         * May as well be the first.
-         */
-        for_each_cpu_and(cpu, cpumask, andmask) {
-                if (cpumask_test_cpu(cpu, cpu_online_mask))
-                        break;
-        }
-
-        return per_cpu(x86_cpu_to_apicid, cpu);
-}
-
 static void init_x2apic_ldr(void)
 {
 }
@@ -131,13 +99,13 @@ static struct apic apic_x2apic_phys = {
         .irq_delivery_mode              = dest_Fixed,
         .irq_dest_mode                  = 0, /* physical */
 
-        .target_cpus                    = x2apic_target_cpus,
+        .target_cpus                    = online_target_cpus,
         .disable_esr                    = 0,
         .dest_logical                   = 0,
         .check_apicid_used              = NULL,
         .check_apicid_present           = NULL,
 
-        .vector_allocation_domain       = x2apic_vector_allocation_domain,
+        .vector_allocation_domain       = default_vector_allocation_domain,
         .init_apic_ldr                  = init_x2apic_ldr,
 
         .ioapic_phys_id_map             = NULL,
@@ -155,8 +123,7 @@ static struct apic apic_x2apic_phys = {
         .set_apic_id                    = x2apic_set_apic_id,
         .apic_id_mask                   = 0xFFFFFFFFu,
 
-        .cpu_mask_to_apicid             = x2apic_cpu_mask_to_apicid,
-        .cpu_mask_to_apicid_and         = x2apic_cpu_mask_to_apicid_and,
+        .cpu_mask_to_apicid_and         = default_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = x2apic_send_IPI_mask,
         .send_IPI_mask_allbutself       = x2apic_send_IPI_mask_allbutself,
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index c6d03f7a440..8cfade9510a 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -185,17 +185,6 @@ EXPORT_SYMBOL_GPL(uv_possible_blades);
 unsigned long sn_rtc_cycles_per_second;
 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 
-static const struct cpumask *uv_target_cpus(void)
-{
-        return cpu_online_mask;
-}
-
-static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
-        cpumask_clear(retmask);
-        cpumask_set_cpu(cpu, retmask);
-}
-
 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 {
 #ifdef CONFIG_SMP
@@ -280,25 +269,12 @@ static void uv_init_apic_ldr(void)
 {
 }
 
-static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
-{
-        /*
-         * We're using fixed IRQ delivery, can only return one phys APIC ID.
-         * May as well be the first.
-         */
-        int cpu = cpumask_first(cpumask);
-
-        if ((unsigned)cpu < nr_cpu_ids)
-                return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
-        else
-                return BAD_APICID;
-}
-
-static unsigned int
+static int
 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
-                          const struct cpumask *andmask)
+                          const struct cpumask *andmask,
+                          unsigned int *apicid)
 {
-        int cpu;
+        int unsigned cpu;
 
         /*
          * We're using fixed IRQ delivery, can only return one phys APIC ID.
@@ -308,7 +284,13 @@ uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
                 if (cpumask_test_cpu(cpu, cpu_online_mask))
                         break;
         }
-        return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
+
+        if (likely(cpu < nr_cpu_ids)) {
+                *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
+                return 0;
+        }
+
+        return -EINVAL;
 }
 
 static unsigned int x2apic_get_apic_id(unsigned long x)
@@ -362,13 +344,13 @@ static struct apic __refdata apic_x2apic_uv_x = {
         .irq_delivery_mode              = dest_Fixed,
         .irq_dest_mode                  = 0, /* physical */
 
-        .target_cpus                    = uv_target_cpus,
+        .target_cpus                    = online_target_cpus,
         .disable_esr                    = 0,
         .dest_logical                   = APIC_DEST_LOGICAL,
         .check_apicid_used              = NULL,
         .check_apicid_present           = NULL,
 
-        .vector_allocation_domain       = uv_vector_allocation_domain,
+        .vector_allocation_domain       = default_vector_allocation_domain,
         .init_apic_ldr                  = uv_init_apic_ldr,
 
         .ioapic_phys_id_map             = NULL,
@@ -386,7 +368,6 @@ static struct apic __refdata apic_x2apic_uv_x = {
         .set_apic_id                    = set_apic_id,
         .apic_id_mask                   = 0xFFFFFFFFu,
 
-        .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 
         .send_IPI_mask                  = uv_send_IPI_mask,
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 07b0c0db466..d65464e4350 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -201,6 +201,8 @@
  *    http://www.microsoft.com/whdc/archive/amp_12.mspx]
  */
 
+#define pr_fmt(fmt) "apm: " fmt
+
 #include <linux/module.h>
 
 #include <linux/poll.h>
@@ -485,11 +487,11 @@ static void apm_error(char *str, int err)
                 if (error_table[i].key == err)
                         break;
         if (i < ERROR_COUNT)
-                printk(KERN_NOTICE "apm: %s: %s\n", str, error_table[i].msg);
+                pr_notice("%s: %s\n", str, error_table[i].msg);
         else if (err < 0)
-                printk(KERN_NOTICE "apm: %s: linux error code %i\n", str, err);
+                pr_notice("%s: linux error code %i\n", str, err);
         else
-                printk(KERN_NOTICE "apm: %s: unknown error code %#2.2x\n",
+                pr_notice("%s: unknown error code %#2.2x\n",
                        str, err);
 }
 
@@ -1184,7 +1186,7 @@ static void queue_event(apm_event_t event, struct apm_user *sender)
                         static int notified;
 
                         if (notified++ == 0)
-                            printk(KERN_ERR "apm: an event queue overflowed\n");
+                                pr_err("an event queue overflowed\n");
                         if (++as->event_tail >= APM_MAX_EVENTS)
                                 as->event_tail = 0;
                 }
@@ -1447,7 +1449,7 @@ static void apm_mainloop(void)
 static int check_apm_user(struct apm_user *as, const char *func)
 {
         if (as == NULL || as->magic != APM_BIOS_MAGIC) {
-                printk(KERN_ERR "apm: %s passed bad filp\n", func);
+                pr_err("%s passed bad filp\n", func);
                 return 1;
         }
         return 0;
@@ -1586,7 +1588,7 @@ static int do_release(struct inode *inode, struct file *filp)
                      as1 = as1->next)
                         ;
                 if (as1 == NULL)
-                        printk(KERN_ERR "apm: filp not in user list\n");
+                        pr_err("filp not in user list\n");
                 else
                         as1->next = as->next;
         }
@@ -1600,11 +1602,9 @@ static int do_open(struct inode *inode, struct file *filp)
         struct apm_user *as;
 
         as = kmalloc(sizeof(*as), GFP_KERNEL);
-        if (as == NULL) {
-                printk(KERN_ERR "apm: cannot allocate struct of size %d bytes\n",
-                       sizeof(*as));
+        if (as == NULL)
                 return -ENOMEM;
-        }
+
         as->magic = APM_BIOS_MAGIC;
         as->event_tail = as->event_head = 0;
         as->suspends_pending = as->standbys_pending = 0;
@@ -2313,16 +2313,16 @@ static int __init apm_init(void)
         }
 
         if (apm_info.disabled) {
-                printk(KERN_NOTICE "apm: disabled on user request.\n");
+                pr_notice("disabled on user request.\n");
                 return -ENODEV;
         }
         if ((num_online_cpus() > 1) && !power_off && !smp) {
-                printk(KERN_NOTICE "apm: disabled - APM is not SMP safe.\n");
+                pr_notice("disabled - APM is not SMP safe.\n");
                 apm_info.disabled = 1;
                 return -ENODEV;
         }
         if (!acpi_disabled) {
-                printk(KERN_NOTICE "apm: overridden by ACPI.\n");
+                pr_notice("overridden by ACPI.\n");
                 apm_info.disabled = 1;
                 return -ENODEV;
         }
@@ -2356,8 +2356,7 @@ static int __init apm_init(void)
 
         kapmd_task = kthread_create(apm, NULL, "kapmd");
         if (IS_ERR(kapmd_task)) {
-                printk(KERN_ERR "apm: disabled - Unable to start kernel "
-                                "thread.\n");
+                pr_err("disabled - Unable to start kernel thread\n");
                 err = PTR_ERR(kapmd_task);
                 kapmd_task = NULL;
                 remove_proc_entry("apm", NULL);
diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile
index 6ab6aa2fdfd..d30a6a9a012 100644
--- a/arch/x86/kernel/cpu/Makefile
+++ b/arch/x86/kernel/cpu/Makefile
@@ -14,7 +14,7 @@ CFLAGS_common.o		:= $(nostackp)
 
 obj-y                   := intel_cacheinfo.o scattered.o topology.o
 obj-y                   += proc.o capflags.o powerflags.o common.o
-obj-y                   += vmware.o hypervisor.o sched.o mshyperv.o
+obj-y                   += vmware.o hypervisor.o mshyperv.o
 obj-y                   += rdrand.o
 obj-y                   += match.o
 
@@ -32,7 +32,9 @@ obj-$(CONFIG_PERF_EVENTS)		+= perf_event.o
 
 ifdef CONFIG_PERF_EVENTS
 obj-$(CONFIG_CPU_SUP_AMD)               += perf_event_amd.o
-obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_p6.o perf_event_p4.o perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o
+obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_p6.o perf_event_p4.o
+obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_lbr.o perf_event_intel_ds.o perf_event_intel.o
+obj-$(CONFIG_CPU_SUP_INTEL)             += perf_event_intel_uncore.o
 endif
 
 obj-$(CONFIG_X86_MCE)                   += mcheck/
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 146bb6218ee..9d92e19039f 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -19,6 +19,39 @@
 
 #include "cpu.h"
 
+static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
+{
+        struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
+        u32 gprs[8] = { 0 };
+        int err;
+
+        WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__);
+
+        gprs[1] = msr;
+        gprs[7] = 0x9c5a203a;
+
+        err = rdmsr_safe_regs(gprs);
+
+        *p = gprs[0] | ((u64)gprs[2] << 32);
+
+        return err;
+}
+
+static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
+{
+        struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
+        u32 gprs[8] = { 0 };
+
+        WARN_ONCE((c->x86 != 0xf), "%s should only be used on K8!\n", __func__);
+
+        gprs[0] = (u32)val;
+        gprs[1] = msr;
+        gprs[2] = val >> 32;
+        gprs[7] = 0x9c5a203a;
+
+        return wrmsr_safe_regs(gprs);
+}
+
 #ifdef CONFIG_X86_32
 /*
  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
@@ -586,9 +619,9 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
             !cpu_has(c, X86_FEATURE_TOPOEXT)) {
                 u64 val;
 
-                if (!rdmsrl_amd_safe(0xc0011005, &val)) {
+                if (!rdmsrl_safe(0xc0011005, &val)) {
                         val |= 1ULL << 54;
-                        wrmsrl_amd_safe(0xc0011005, val);
+                        wrmsrl_safe(0xc0011005, val);
                         rdmsrl(0xc0011005, val);
                         if (val & (1ULL << 54)) {
                                 set_cpu_cap(c, X86_FEATURE_TOPOEXT);
@@ -679,7 +712,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 err = rdmsrl_safe(MSR_AMD64_MCx_MASK(4), &mask);
                 if (err == 0) {
                         mask |= (1 << 10);
-                        checking_wrmsrl(MSR_AMD64_MCx_MASK(4), mask);
+                        wrmsrl_safe(MSR_AMD64_MCx_MASK(4), mask);
                 }
         }
 
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 46674fbb62b..c97bb7b5a9f 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -55,8 +55,8 @@ static void __init check_fpu(void)
 
         if (!boot_cpu_data.hard_math) {
 #ifndef CONFIG_MATH_EMULATION
-                printk(KERN_EMERG "No coprocessor found and no math emulation present.\n");
-                printk(KERN_EMERG "Giving up.\n");
+                pr_emerg("No coprocessor found and no math emulation present\n");
+                pr_emerg("Giving up\n");
                 for (;;) ;
 #endif
                 return;
@@ -86,7 +86,7 @@ static void __init check_fpu(void)
 
         boot_cpu_data.fdiv_bug = fdiv_bug;
         if (boot_cpu_data.fdiv_bug)
-                printk(KERN_WARNING "Hmm, FPU with FDIV bug.\n");
+                pr_warn("Hmm, FPU with FDIV bug\n");
 }
 
 static void __init check_hlt(void)
@@ -94,16 +94,16 @@ static void __init check_hlt(void)
         if (boot_cpu_data.x86 >= 5 || paravirt_enabled())
                 return;
 
-        printk(KERN_INFO "Checking 'hlt' instruction... ");
+        pr_info("Checking 'hlt' instruction... ");
         if (!boot_cpu_data.hlt_works_ok) {
-                printk("disabled\n");
+                pr_cont("disabled\n");
                 return;
         }
         halt();
         halt();
         halt();
         halt();
-        printk(KERN_CONT "OK.\n");
+        pr_cont("OK\n");
 }
 
 /*
@@ -116,7 +116,7 @@ static void __init check_popad(void)
 #ifndef CONFIG_X86_POPAD_OK
         int res, inp = (int) &res;
 
-        printk(KERN_INFO "Checking for popad bug... ");
+        pr_info("Checking for popad bug... ");
         __asm__ __volatile__(
           "movl $12345678,%%eax; movl $0,%%edi; pusha; popa; movl (%%edx,%%edi),%%ecx "
           : "=&a" (res)
@@ -127,9 +127,9 @@ static void __init check_popad(void)
          * CPU hard. Too bad.
          */
         if (res != 12345678)
-                printk(KERN_CONT "Buggy.\n");
+                pr_cont("Buggy\n");
         else
-                printk(KERN_CONT "OK.\n");
+                pr_cont("OK\n");
 #endif
 }
 
@@ -161,7 +161,7 @@ void __init check_bugs(void)
 {
         identify_boot_cpu();
 #ifndef CONFIG_SMP
-        printk(KERN_INFO "CPU: ");
+        pr_info("CPU: ");
         print_cpu_info(&boot_cpu_data);
 #endif
         check_config();
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 6b9333b429b..a5fbc3c5fcc 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -144,6 +144,8 @@ static int __init x86_xsave_setup(char *s)
 {
         setup_clear_cpu_cap(X86_FEATURE_XSAVE);
         setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
+        setup_clear_cpu_cap(X86_FEATURE_AVX);
+        setup_clear_cpu_cap(X86_FEATURE_AVX2);
         return 1;
 }
 __setup("noxsave", x86_xsave_setup);
@@ -452,6 +454,35 @@ void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
         c->x86_cache_size = l2size;
 }
 
+u16 __read_mostly tlb_lli_4k[NR_INFO];
+u16 __read_mostly tlb_lli_2m[NR_INFO];
+u16 __read_mostly tlb_lli_4m[NR_INFO];
+u16 __read_mostly tlb_lld_4k[NR_INFO];
+u16 __read_mostly tlb_lld_2m[NR_INFO];
+u16 __read_mostly tlb_lld_4m[NR_INFO];
+
+/*
+ * tlb_flushall_shift shows the balance point in replacing cr3 write
+ * with multiple 'invlpg'. It will do this replacement when
+ *   flush_tlb_lines <= active_lines/2^tlb_flushall_shift.
+ * If tlb_flushall_shift is -1, means the replacement will be disabled.
+ */
+s8  __read_mostly tlb_flushall_shift = -1;
+
+void __cpuinit cpu_detect_tlb(struct cpuinfo_x86 *c)
+{
+        if (this_cpu->c_detect_tlb)
+                this_cpu->c_detect_tlb(c);
+
+        printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \
+                "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n"          \
+                "tlb_flushall_shift is 0x%x\n",
+                tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
+                tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
+                tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
+                tlb_flushall_shift);
+}
+
 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_X86_HT
@@ -911,6 +942,8 @@ void __init identify_boot_cpu(void)
 #else
         vgetcpu_set_mode();
 #endif
+        if (boot_cpu_data.cpuid_level >= 2)
+                cpu_detect_tlb(&boot_cpu_data);
 }
 
 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
@@ -947,7 +980,7 @@ static void __cpuinit __print_cpu_msr(void)
                 index_max = msr_range_array[i].max;
 
                 for (index = index_min; index < index_max; index++) {
-                        if (rdmsrl_amd_safe(index, &val))
+                        if (rdmsrl_safe(index, &val))
                                 continue;
                         printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
                 }
diff --git a/arch/x86/kernel/cpu/cpu.h b/arch/x86/kernel/cpu/cpu.h
index 8bacc7826fb..4041c24ae7d 100644
--- a/arch/x86/kernel/cpu/cpu.h
+++ b/arch/x86/kernel/cpu/cpu.h
@@ -20,10 +20,19 @@ struct cpu_dev {
         void            (*c_bsp_init)(struct cpuinfo_x86 *);
         void            (*c_init)(struct cpuinfo_x86 *);
         void            (*c_identify)(struct cpuinfo_x86 *);
+        void            (*c_detect_tlb)(struct cpuinfo_x86 *);
         unsigned int    (*c_size_cache)(struct cpuinfo_x86 *, unsigned int);
         int             c_x86_vendor;
 };
 
+struct _tlb_table {
+        unsigned char descriptor;
+        char tlb_type;
+        unsigned int entries;
+        /* unsigned int ways; */
+        char info[128];
+};
+
 #define cpu_dev_register(cpu_devX) \
         static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
         __attribute__((__section__(".x86_cpu_dev.init"))) = \
diff --git a/arch/x86/kernel/cpu/hypervisor.c b/arch/x86/kernel/cpu/hypervisor.c
index 755f64fb074..a8f8fa9769d 100644
--- a/arch/x86/kernel/cpu/hypervisor.c
+++ b/arch/x86/kernel/cpu/hypervisor.c
@@ -37,6 +37,9 @@ static const __initconst struct hypervisor_x86 * const hypervisors[] =
 #endif
         &x86_hyper_vmware,
         &x86_hyper_ms_hyperv,
+#ifdef CONFIG_KVM_GUEST
+        &x86_hyper_kvm,
+#endif
 };
 
 const struct hypervisor_x86 *x86_hyper;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 3e6ff6cbf42..0a4ce2980a5 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -491,6 +491,181 @@ static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned i
 }
 #endif
 
+#define TLB_INST_4K     0x01
+#define TLB_INST_4M     0x02
+#define TLB_INST_2M_4M  0x03
+
+#define TLB_INST_ALL    0x05
+#define TLB_INST_1G     0x06
+
+#define TLB_DATA_4K     0x11
+#define TLB_DATA_4M     0x12
+#define TLB_DATA_2M_4M  0x13
+#define TLB_DATA_4K_4M  0x14
+
+#define TLB_DATA_1G     0x16
+
+#define TLB_DATA0_4K    0x21
+#define TLB_DATA0_4M    0x22
+#define TLB_DATA0_2M_4M 0x23
+
+#define STLB_4K         0x41
+
+static const struct _tlb_table intel_tlb_table[] __cpuinitconst = {
+        { 0x01, TLB_INST_4K,            32,     " TLB_INST 4 KByte pages, 4-way set associative" },
+        { 0x02, TLB_INST_4M,            2,      " TLB_INST 4 MByte pages, full associative" },
+        { 0x03, TLB_DATA_4K,            64,     " TLB_DATA 4 KByte pages, 4-way set associative" },
+        { 0x04, TLB_DATA_4M,            8,      " TLB_DATA 4 MByte pages, 4-way set associative" },
+        { 0x05, TLB_DATA_4M,            32,     " TLB_DATA 4 MByte pages, 4-way set associative" },
+        { 0x0b, TLB_INST_4M,            4,      " TLB_INST 4 MByte pages, 4-way set associative" },
+        { 0x4f, TLB_INST_4K,            32,     " TLB_INST 4 KByte pages */" },
+        { 0x50, TLB_INST_ALL,           64,     " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
+        { 0x51, TLB_INST_ALL,           128,    " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
+        { 0x52, TLB_INST_ALL,           256,    " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
+        { 0x55, TLB_INST_2M_4M,         7,      " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
+        { 0x56, TLB_DATA0_4M,           16,     " TLB_DATA0 4 MByte pages, 4-way set associative" },
+        { 0x57, TLB_DATA0_4K,           16,     " TLB_DATA0 4 KByte pages, 4-way associative" },
+        { 0x59, TLB_DATA0_4K,           16,     " TLB_DATA0 4 KByte pages, fully associative" },
+        { 0x5a, TLB_DATA0_2M_4M,        32,     " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
+        { 0x5b, TLB_DATA_4K_4M,         64,     " TLB_DATA 4 KByte and 4 MByte pages" },
+        { 0x5c, TLB_DATA_4K_4M,         128,    " TLB_DATA 4 KByte and 4 MByte pages" },
+        { 0x5d, TLB_DATA_4K_4M,         256,    " TLB_DATA 4 KByte and 4 MByte pages" },
+        { 0xb0, TLB_INST_4K,            128,    " TLB_INST 4 KByte pages, 4-way set associative" },
+        { 0xb1, TLB_INST_2M_4M,         4,      " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
+        { 0xb2, TLB_INST_4K,            64,     " TLB_INST 4KByte pages, 4-way set associative" },
+        { 0xb3, TLB_DATA_4K,            128,    " TLB_DATA 4 KByte pages, 4-way set associative" },
+        { 0xb4, TLB_DATA_4K,            256,    " TLB_DATA 4 KByte pages, 4-way associative" },
+        { 0xba, TLB_DATA_4K,            64,     " TLB_DATA 4 KByte pages, 4-way associative" },
+        { 0xc0, TLB_DATA_4K_4M,         8,      " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
+        { 0xca, STLB_4K,                512,    " STLB 4 KByte pages, 4-way associative" },
+        { 0x00, 0, 0 }
+};
+
+static void __cpuinit intel_tlb_lookup(const unsigned char desc)
+{
+        unsigned char k;
+        if (desc == 0)
+                return;
+
+        /* look up this descriptor in the table */
+        for (k = 0; intel_tlb_table[k].descriptor != desc && \
+                        intel_tlb_table[k].descriptor != 0; k++)
+                ;
+
+        if (intel_tlb_table[k].tlb_type == 0)
+                return;
+
+        switch (intel_tlb_table[k].tlb_type) {
+        case STLB_4K:
+                if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
+                if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
+                break;
+        case TLB_INST_ALL:
+                if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
+                if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
+                if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
+                break;
+        case TLB_INST_4K:
+                if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
+                break;
+        case TLB_INST_4M:
+                if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
+                break;
+        case TLB_INST_2M_4M:
+                if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
+                if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
+                break;
+        case TLB_DATA_4K:
+        case TLB_DATA0_4K:
+                if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
+                break;
+        case TLB_DATA_4M:
+        case TLB_DATA0_4M:
+                if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
+                break;
+        case TLB_DATA_2M_4M:
+        case TLB_DATA0_2M_4M:
+                if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
+                if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
+                break;
+        case TLB_DATA_4K_4M:
+                if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
+                if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
+                        tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
+                break;
+        }
+}
+
+static void __cpuinit intel_tlb_flushall_shift_set(struct cpuinfo_x86 *c)
+{
+        if (!cpu_has_invlpg) {
+                tlb_flushall_shift = -1;
+                return;
+        }
+        switch ((c->x86 << 8) + c->x86_model) {
+        case 0x60f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
+        case 0x616: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
+        case 0x617: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
+        case 0x61d: /* six-core 45 nm xeon "Dunnington" */
+                tlb_flushall_shift = -1;
+                break;
+        case 0x61a: /* 45 nm nehalem, "Bloomfield" */
+        case 0x61e: /* 45 nm nehalem, "Lynnfield" */
+        case 0x625: /* 32 nm nehalem, "Clarkdale" */
+        case 0x62c: /* 32 nm nehalem, "Gulftown" */
+        case 0x62e: /* 45 nm nehalem-ex, "Beckton" */
+        case 0x62f: /* 32 nm Xeon E7 */
+                tlb_flushall_shift = 6;
+                break;
+        case 0x62a: /* SandyBridge */
+        case 0x62d: /* SandyBridge, "Romely-EP" */
+                tlb_flushall_shift = 5;
+                break;
+        case 0x63a: /* Ivybridge */
+                tlb_flushall_shift = 1;
+                break;
+        default:
+                tlb_flushall_shift = 6;
+        }
+}
+
+static void __cpuinit intel_detect_tlb(struct cpuinfo_x86 *c)
+{
+        int i, j, n;
+        unsigned int regs[4];
+        unsigned char *desc = (unsigned char *)regs;
+        /* Number of times to iterate */
+        n = cpuid_eax(2) & 0xFF;
+
+        for (i = 0 ; i < n ; i++) {
+                cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
+
+                /* If bit 31 is set, this is an unknown format */
+                for (j = 0 ; j < 3 ; j++)
+                        if (regs[j] & (1 << 31))
+                                regs[j] = 0;
+
+                /* Byte 0 is level count, not a descriptor */
+                for (j = 1 ; j < 16 ; j++)
+                        intel_tlb_lookup(desc[j]);
+        }
+        intel_tlb_flushall_shift_set(c);
+}
+
 static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
         .c_vendor       = "Intel",
         .c_ident        = { "GenuineIntel" },
@@ -546,6 +721,7 @@ static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
         },
         .c_size_cache   = intel_size_cache,
 #endif
+        .c_detect_tlb   = intel_detect_tlb,
         .c_early_init   = early_init_intel,
         .c_init         = init_intel,
         .c_x86_vendor   = X86_VENDOR_INTEL,
diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index 413c2ced887..13017626f9a 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -55,13 +55,6 @@ static struct severity {
 #define MCI_UC_S (MCI_STATUS_UC|MCI_STATUS_S)
 #define MCI_UC_SAR (MCI_STATUS_UC|MCI_STATUS_S|MCI_STATUS_AR)
 #define MCI_ADDR (MCI_STATUS_ADDRV|MCI_STATUS_MISCV)
-#define MCACOD 0xffff
-/* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
-#define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
-#define MCACOD_SCRUBMSK 0xfff0
-#define MCACOD_L3WB     0x017A  /* L3 Explicit Writeback */
-#define MCACOD_DATA     0x0134  /* Data Load */
-#define MCACOD_INSTR    0x0150  /* Instruction Fetch */
 
         MCESEV(
                 NO, "Invalid",
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index da27c5d2168..292d0258311 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -7,6 +7,9 @@
  * Copyright 2008 Intel Corporation
  * Author: Andi Kleen
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/thread_info.h>
 #include <linux/capability.h>
 #include <linux/miscdevice.h>
@@ -57,8 +60,6 @@ static DEFINE_MUTEX(mce_chrdev_read_mutex);
 
 int mce_disabled __read_mostly;
 
-#define MISC_MCELOG_MINOR       227
-
 #define SPINUNIT 100    /* 100ns */
 
 atomic_t mce_entry;
@@ -102,6 +103,8 @@ DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
 
 static DEFINE_PER_CPU(struct work_struct, mce_work);
 
+static void (*quirk_no_way_out)(int bank, struct mce *m, struct pt_regs *regs);
+
 /*
  * CPU/chipset specific EDAC code can register a notifier call here to print
  * MCE errors in a human-readable form.
@@ -210,7 +213,7 @@ static void drain_mcelog_buffer(void)
                                 cpu_relax();
 
                                 if (!m->finished && retries >= 4) {
-                                        pr_err("MCE: skipping error being logged currently!\n");
+                                        pr_err("skipping error being logged currently!\n");
                                         break;
                                 }
                         }
@@ -649,14 +652,18 @@ EXPORT_SYMBOL_GPL(machine_check_poll);
  * Do a quick check if any of the events requires a panic.
  * This decides if we keep the events around or clear them.
  */
-static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp)
+static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
+                          struct pt_regs *regs)
 {
         int i, ret = 0;
 
         for (i = 0; i < banks; i++) {
                 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
-                if (m->status & MCI_STATUS_VAL)
+                if (m->status & MCI_STATUS_VAL) {
                         __set_bit(i, validp);
+                        if (quirk_no_way_out)
+                                quirk_no_way_out(i, m, regs);
+                }
                 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
                         ret = 1;
         }
@@ -1039,7 +1046,7 @@ void do_machine_check(struct pt_regs *regs, long error_code)
         *final = m;
 
         memset(valid_banks, 0, sizeof(valid_banks));
-        no_way_out = mce_no_way_out(&m, &msg, valid_banks);
+        no_way_out = mce_no_way_out(&m, &msg, valid_banks, regs);
 
         barrier();
 
@@ -1167,8 +1174,9 @@ int memory_failure(unsigned long pfn, int vector, int flags)
 {
         /* mce_severity() should not hand us an ACTION_REQUIRED error */
         BUG_ON(flags & MF_ACTION_REQUIRED);
-        printk(KERN_ERR "Uncorrected memory error in page 0x%lx ignored\n"
-                "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n", pfn);
+        pr_err("Uncorrected memory error in page 0x%lx ignored\n"
+               "Rebuild kernel with CONFIG_MEMORY_FAILURE=y for smarter handling\n",
+               pfn);
 
         return 0;
 }
@@ -1186,6 +1194,7 @@ void mce_notify_process(void)
 {
         unsigned long pfn;
         struct mce_info *mi = mce_find_info();
+        int flags = MF_ACTION_REQUIRED;
 
         if (!mi)
                 mce_panic("Lost physical address for unconsumed uncorrectable error", NULL, NULL);
@@ -1200,8 +1209,9 @@ void mce_notify_process(void)
          * doomed. We still need to mark the page as poisoned and alert any
          * other users of the page.
          */
-        if (memory_failure(pfn, MCE_VECTOR, MF_ACTION_REQUIRED) < 0 ||
-                           mi->restartable == 0) {
+        if (!mi->restartable)
+                flags |= MF_MUST_KILL;
+        if (memory_failure(pfn, MCE_VECTOR, flags) < 0) {
                 pr_err("Memory error not recovered");
                 force_sig(SIGBUS, current);
         }
@@ -1358,11 +1368,10 @@ static int __cpuinit __mcheck_cpu_cap_init(void)
 
         b = cap & MCG_BANKCNT_MASK;
         if (!banks)
-                printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
+                pr_info("CPU supports %d MCE banks\n", b);
 
         if (b > MAX_NR_BANKS) {
-                printk(KERN_WARNING
-                       "MCE: Using only %u machine check banks out of %u\n",
+                pr_warn("Using only %u machine check banks out of %u\n",
                         MAX_NR_BANKS, b);
                 b = MAX_NR_BANKS;
         }
@@ -1415,11 +1424,39 @@ static void __mcheck_cpu_init_generic(void)
         }
 }
 
+/*
+ * During IFU recovery Sandy Bridge -EP4S processors set the RIPV and
+ * EIPV bits in MCG_STATUS to zero on the affected logical processor (SDM
+ * Vol 3B Table 15-20). But this confuses both the code that determines
+ * whether the machine check occurred in kernel or user mode, and also
+ * the severity assessment code. Pretend that EIPV was set, and take the
+ * ip/cs values from the pt_regs that mce_gather_info() ignored earlier.
+ */
+static void quirk_sandybridge_ifu(int bank, struct mce *m, struct pt_regs *regs)
+{
+        if (bank != 0)
+                return;
+        if ((m->mcgstatus & (MCG_STATUS_EIPV|MCG_STATUS_RIPV)) != 0)
+                return;
+        if ((m->status & (MCI_STATUS_OVER|MCI_STATUS_UC|
+                          MCI_STATUS_EN|MCI_STATUS_MISCV|MCI_STATUS_ADDRV|
+                          MCI_STATUS_PCC|MCI_STATUS_S|MCI_STATUS_AR|
+                          MCACOD)) !=
+                         (MCI_STATUS_UC|MCI_STATUS_EN|
+                          MCI_STATUS_MISCV|MCI_STATUS_ADDRV|MCI_STATUS_S|
+                          MCI_STATUS_AR|MCACOD_INSTR))
+                return;
+
+        m->mcgstatus |= MCG_STATUS_EIPV;
+        m->ip = regs->ip;
+        m->cs = regs->cs;
+}
+
 /* Add per CPU specific workarounds here */
 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
 {
         if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
-                pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
+                pr_info("unknown CPU type - not enabling MCE support\n");
                 return -EOPNOTSUPP;
         }
 
@@ -1512,6 +1549,9 @@ static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
                  */
                 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
                         mce_bootlog = 0;
+
+                if (c->x86 == 6 && c->x86_model == 45)
+                        quirk_no_way_out = quirk_sandybridge_ifu;
         }
         if (monarch_timeout < 0)
                 monarch_timeout = 0;
@@ -1574,7 +1614,7 @@ static void __mcheck_cpu_init_timer(void)
 /* Handle unconfigured int18 (should never happen) */
 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
 {
-        printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
+        pr_err("CPU#%d: Unexpected int18 (Machine Check)\n",
                smp_processor_id());
 }
 
@@ -1893,8 +1933,7 @@ static int __init mcheck_enable(char *str)
                         get_option(&str, &monarch_timeout);
                 }
         } else {
-                printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
-                       str);
+                pr_info("mce argument %s ignored. Please use /sys\n", str);
                 return 0;
         }
         return 1;
@@ -2342,7 +2381,7 @@ static __init int mcheck_init_device(void)
 
         return err;
 }
-device_initcall(mcheck_init_device);
+device_initcall_sync(mcheck_init_device);
 
 /*
  * Old style boot options parsing. Only for compatibility.
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index f4873a64f46..c4e916d7737 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -1,15 +1,17 @@
 /*
- *  (c) 2005, 2006 Advanced Micro Devices, Inc.
+ *  (c) 2005-2012 Advanced Micro Devices, Inc.
  *  Your use of this code is subject to the terms and conditions of the
  *  GNU general public license version 2. See "COPYING" or
  *  http://www.gnu.org/licenses/gpl.html
  *
  *  Written by Jacob Shin - AMD, Inc.
  *
- *  Support : jacob.shin@amd.com
+ *  Support: borislav.petkov@amd.com
  *
  *  April 2006
  *     - added support for AMD Family 0x10 processors
+ *  May 2012
+ *     - major scrubbing
  *
  *  All MC4_MISCi registers are shared between multi-cores
  */
@@ -25,6 +27,7 @@
 #include <linux/cpu.h>
 #include <linux/smp.h>
 
+#include <asm/amd_nb.h>
 #include <asm/apic.h>
 #include <asm/idle.h>
 #include <asm/mce.h>
@@ -45,23 +48,15 @@
 #define MASK_BLKPTR_LO    0xFF000000
 #define MCG_XBLK_ADDR     0xC0000400
 
-struct threshold_block {
-        unsigned int            block;
-        unsigned int            bank;
-        unsigned int            cpu;
-        u32                     address;
-        u16                     interrupt_enable;
-        bool                    interrupt_capable;
-        u16                     threshold_limit;
-        struct kobject          kobj;
-        struct list_head        miscj;
+static const char * const th_names[] = {
+        "load_store",
+        "insn_fetch",
+        "combined_unit",
+        "",
+        "northbridge",
+        "execution_unit",
 };
 
-struct threshold_bank {
-        struct kobject          *kobj;
-        struct threshold_block  *blocks;
-        cpumask_var_t           cpus;
-};
 static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
 
 static unsigned char shared_bank[NR_BANKS] = {
@@ -84,6 +79,26 @@ struct thresh_restart {
         u16                     old_limit;
 };
 
+static const char * const bank4_names(struct threshold_block *b)
+{
+        switch (b->address) {
+        /* MSR4_MISC0 */
+        case 0x00000413:
+                return "dram";
+
+        case 0xc0000408:
+                return "ht_links";
+
+        case 0xc0000409:
+                return "l3_cache";
+
+        default:
+                WARN(1, "Funny MSR: 0x%08x\n", b->address);
+                return "";
+        }
+};
+
+
 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
 {
         /*
@@ -224,8 +239,6 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
 
                         if (!block)
                                 per_cpu(bank_map, cpu) |= (1 << bank);
-                        if (shared_bank[bank] && c->cpu_core_id)
-                                break;
 
                         memset(&b, 0, sizeof(b));
                         b.cpu                   = cpu;
@@ -326,7 +339,7 @@ struct threshold_attr {
 #define SHOW_FIELDS(name)                                               \
 static ssize_t show_ ## name(struct threshold_block *b, char *buf)      \
 {                                                                       \
-        return sprintf(buf, "%lx\n", (unsigned long) b->name);          \
+        return sprintf(buf, "%lu\n", (unsigned long) b->name);          \
 }
 SHOW_FIELDS(interrupt_enable)
 SHOW_FIELDS(threshold_limit)
@@ -377,38 +390,21 @@ store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
         return size;
 }
 
-struct threshold_block_cross_cpu {
-        struct threshold_block  *tb;
-        long                    retval;
-};
-
-static void local_error_count_handler(void *_tbcc)
-{
-        struct threshold_block_cross_cpu *tbcc = _tbcc;
-        struct threshold_block *b = tbcc->tb;
-        u32 low, high;
-
-        rdmsr(b->address, low, high);
-        tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
-}
-
 static ssize_t show_error_count(struct threshold_block *b, char *buf)
 {
-        struct threshold_block_cross_cpu tbcc = { .tb = b, };
+        u32 lo, hi;
 
-        smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
-        return sprintf(buf, "%lx\n", tbcc.retval);
-}
-
-static ssize_t store_error_count(struct threshold_block *b,
-                                 const char *buf, size_t count)
-{
-        struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
+        rdmsr_on_cpu(b->cpu, b->address, &lo, &hi);
 
-        smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
-        return 1;
+        return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
+                                     (THRESHOLD_MAX - b->threshold_limit)));
 }
 
+static struct threshold_attr error_count = {
+        .attr = {.name = __stringify(error_count), .mode = 0444 },
+        .show = show_error_count,
+};
+
 #define RW_ATTR(val)                                                    \
 static struct threshold_attr val = {                                    \
         .attr   = {.name = __stringify(val), .mode = 0644 },            \
@@ -418,7 +414,6 @@ static struct threshold_attr val = {					\
 
 RW_ATTR(interrupt_enable);
 RW_ATTR(threshold_limit);
-RW_ATTR(error_count);
 
 static struct attribute *default_attrs[] = {
         &threshold_limit.attr,
@@ -517,7 +512,7 @@ static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
 
         err = kobject_init_and_add(&b->kobj, &threshold_ktype,
                                    per_cpu(threshold_banks, cpu)[bank]->kobj,
-                                   "misc%i", block);
+                                   (bank == 4 ? bank4_names(b) : th_names[bank]));
         if (err)
                 goto out_free;
 recurse:
@@ -548,98 +543,91 @@ out_free:
         return err;
 }
 
-static __cpuinit long
-local_allocate_threshold_blocks(int cpu, unsigned int bank)
+static __cpuinit int __threshold_add_blocks(struct threshold_bank *b)
 {
-        return allocate_threshold_blocks(cpu, bank, 0,
-                                         MSR_IA32_MC0_MISC + bank * 4);
+        struct list_head *head = &b->blocks->miscj;
+        struct threshold_block *pos = NULL;
+        struct threshold_block *tmp = NULL;
+        int err = 0;
+
+        err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
+        if (err)
+                return err;
+
+        list_for_each_entry_safe(pos, tmp, head, miscj) {
+
+                err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
+                if (err) {
+                        list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
+                                kobject_del(&pos->kobj);
+
+                        return err;
+                }
+        }
+        return err;
 }
 
-/* symlinks sibling shared banks to first core.  first core owns dir/files. */
 static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 {
-        int i, err = 0;
-        struct threshold_bank *b = NULL;
         struct device *dev = per_cpu(mce_device, cpu);
-        char name[32];
+        struct amd_northbridge *nb = NULL;
+        struct threshold_bank *b = NULL;
+        const char *name = th_names[bank];
+        int err = 0;
 
-        sprintf(name, "threshold_bank%i", bank);
+        if (shared_bank[bank]) {
 
-#ifdef CONFIG_SMP
-        if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) {   /* symlink */
-                i = cpumask_first(cpu_llc_shared_mask(cpu));
+                nb = node_to_amd_nb(amd_get_nb_id(cpu));
+                WARN_ON(!nb);
 
-                /* first core not up yet */
-                if (cpu_data(i).cpu_core_id)
-                        goto out;
+                /* threshold descriptor already initialized on this node? */
+                if (nb->bank4) {
+                        /* yes, use it */
+                        b = nb->bank4;
+                        err = kobject_add(b->kobj, &dev->kobj, name);
+                        if (err)
+                                goto out;
 
-                /* already linked */
-                if (per_cpu(threshold_banks, cpu)[bank])
-                        goto out;
+                        per_cpu(threshold_banks, cpu)[bank] = b;
+                        atomic_inc(&b->cpus);
 
-                b = per_cpu(threshold_banks, i)[bank];
+                        err = __threshold_add_blocks(b);
 
-                if (!b)
                         goto out;
-
-                err = sysfs_create_link(&dev->kobj, b->kobj, name);
-                if (err)
-                        goto out;
-
-                cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu));
-                per_cpu(threshold_banks, cpu)[bank] = b;
-
-                goto out;
+                }
         }
-#endif
 
         b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
         if (!b) {
                 err = -ENOMEM;
                 goto out;
         }
-        if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
-                kfree(b);
-                err = -ENOMEM;
-                goto out;
-        }
 
         b->kobj = kobject_create_and_add(name, &dev->kobj);
-        if (!b->kobj)
+        if (!b->kobj) {
+                err = -EINVAL;
                 goto out_free;
-
-#ifndef CONFIG_SMP
-        cpumask_setall(b->cpus);
-#else
-        cpumask_set_cpu(cpu, b->cpus);
-#endif
+        }
 
         per_cpu(threshold_banks, cpu)[bank] = b;
 
-        err = local_allocate_threshold_blocks(cpu, bank);
-        if (err)
-                goto out_free;
-
-        for_each_cpu(i, b->cpus) {
-                if (i == cpu)
-                        continue;
-
-                dev = per_cpu(mce_device, i);
-                if (dev)
-                        err = sysfs_create_link(&dev->kobj,b->kobj, name);
-                if (err)
-                        goto out;
+        if (shared_bank[bank]) {
+                atomic_set(&b->cpus, 1);
 
-                per_cpu(threshold_banks, i)[bank] = b;
+                /* nb is already initialized, see above */
+                WARN_ON(nb->bank4);
+                nb->bank4 = b;
         }
 
-        goto out;
+        err = allocate_threshold_blocks(cpu, bank, 0,
+                                        MSR_IA32_MC0_MISC + bank * 4);
+        if (!err)
+                goto out;
 
-out_free:
-        per_cpu(threshold_banks, cpu)[bank] = NULL;
-        free_cpumask_var(b->cpus);
+ out_free:
         kfree(b);
-out:
+
+ out:
         return err;
 }
 
@@ -660,12 +648,6 @@ static __cpuinit int threshold_create_device(unsigned int cpu)
         return err;
 }
 
-/*
- * let's be hotplug friendly.
- * in case of multiple core processors, the first core always takes ownership
- *   of shared sysfs dir/files, and rest of the cores will be symlinked to it.
- */
-
 static void deallocate_threshold_block(unsigned int cpu,
                                                  unsigned int bank)
 {
@@ -686,41 +668,42 @@ static void deallocate_threshold_block(unsigned int cpu,
         per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
 }
 
+static void __threshold_remove_blocks(struct threshold_bank *b)
+{
+        struct threshold_block *pos = NULL;
+        struct threshold_block *tmp = NULL;
+
+        kobject_del(b->kobj);
+
+        list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
+                kobject_del(&pos->kobj);
+}
+
 static void threshold_remove_bank(unsigned int cpu, int bank)
 {
+        struct amd_northbridge *nb;
         struct threshold_bank *b;
-        struct device *dev;
-        char name[32];
-        int i = 0;
 
         b = per_cpu(threshold_banks, cpu)[bank];
         if (!b)
                 return;
+
         if (!b->blocks)
                 goto free_out;
 
-        sprintf(name, "threshold_bank%i", bank);
-
-#ifdef CONFIG_SMP
-        /* sibling symlink */
-        if (shared_bank[bank] && b->blocks->cpu != cpu) {
-                dev = per_cpu(mce_device, cpu);
-                sysfs_remove_link(&dev->kobj, name);
-                per_cpu(threshold_banks, cpu)[bank] = NULL;
-
-                return;
-        }
-#endif
-
-        /* remove all sibling symlinks before unregistering */
-        for_each_cpu(i, b->cpus) {
-                if (i == cpu)
-                        continue;
-
-                dev = per_cpu(mce_device, i);
-                if (dev)
-                        sysfs_remove_link(&dev->kobj, name);
-                per_cpu(threshold_banks, i)[bank] = NULL;
+        if (shared_bank[bank]) {
+                if (!atomic_dec_and_test(&b->cpus)) {
+                        __threshold_remove_blocks(b);
+                        per_cpu(threshold_banks, cpu)[bank] = NULL;
+                        return;
+                } else {
+                        /*
+                         * the last CPU on this node using the shared bank is
+                         * going away, remove that bank now.
+                         */
+                        nb = node_to_amd_nb(amd_get_nb_id(cpu));
+                        nb->bank4 = NULL;
+                }
         }
 
         deallocate_threshold_block(cpu, bank);
@@ -728,7 +711,6 @@ static void threshold_remove_bank(unsigned int cpu, int bank)
 free_out:
         kobject_del(b->kobj);
         kobject_put(b->kobj);
-        free_cpumask_var(b->cpus);
         kfree(b);
         per_cpu(threshold_banks, cpu)[bank] = NULL;
 }
@@ -777,4 +759,24 @@ static __init int threshold_init_device(void)
 
         return 0;
 }
-device_initcall(threshold_init_device);
+/*
+ * there are 3 funcs which need to be _initcalled in a logic sequence:
+ * 1. xen_late_init_mcelog
+ * 2. mcheck_init_device
+ * 3. threshold_init_device
+ *
+ * xen_late_init_mcelog must register xen_mce_chrdev_device before
+ * native mce_chrdev_device registration if running under xen platform;
+ *
+ * mcheck_init_device should be inited before threshold_init_device to
+ * initialize mce_device, otherwise a NULL ptr dereference will cause panic.
+ *
+ * so we use following _initcalls
+ * 1. device_initcall(xen_late_init_mcelog);
+ * 2. device_initcall_sync(mcheck_init_device);
+ * 3. late_initcall(threshold_init_device);
+ *
+ * when running under xen, the initcall order is 1,2,3;
+ * on baremetal, we skip 1 and we do only 2 and 3.
+ */
+late_initcall(threshold_init_device);
diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
index bdda2e6c673..35ffda5d072 100644
--- a/arch/x86/kernel/cpu/mtrr/cleanup.c
+++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
@@ -258,11 +258,11 @@ range_to_mtrr(unsigned int reg, unsigned long range_startk,
 
                 /* Compute the maximum size with which we can make a range: */
                 if (range_startk)
-                        max_align = ffs(range_startk) - 1;
+                        max_align = __ffs(range_startk);
                 else
-                        max_align = 32;
+                        max_align = BITS_PER_LONG - 1;
 
-                align = fls(range_sizek) - 1;
+                align = __fls(range_sizek);
                 if (align > max_align)
                         align = max_align;
 
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 75772ae6c65..e9fe907cd24 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -361,11 +361,7 @@ static void __init print_mtrr_state(void)
         }
         pr_debug("MTRR variable ranges %sabled:\n",
                  mtrr_state.enabled & 2 ? "en" : "dis");
-        if (size_or_mask & 0xffffffffUL)
-                high_width = ffs(size_or_mask & 0xffffffffUL) - 1;
-        else
-                high_width = ffs(size_or_mask>>32) + 32 - 1;
-        high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4;
+        high_width = (__ffs64(size_or_mask) - (32 - PAGE_SHIFT) + 3) / 4;
 
         for (i = 0; i < num_var_ranges; ++i) {
                 if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index c4706cf9c01..915b876edd1 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -32,20 +32,11 @@
 #include <asm/smp.h>
 #include <asm/alternative.h>
 #include <asm/timer.h>
+#include <asm/desc.h>
+#include <asm/ldt.h>
 
 #include "perf_event.h"
 
-#if 0
-#undef wrmsrl
-#define wrmsrl(msr, val)                                        \
-do {                                                            \
-        trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
-                        (unsigned long)(val));                  \
-        native_write_msr((msr), (u32)((u64)(val)),              \
-                        (u32)((u64)(val) >> 32));               \
-} while (0)
-#endif
-
 struct x86_pmu x86_pmu __read_mostly;
 
 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
@@ -74,7 +65,7 @@ u64 x86_perf_event_update(struct perf_event *event)
         int idx = hwc->idx;
         s64 delta;
 
-        if (idx == X86_PMC_IDX_FIXED_BTS)
+        if (idx == INTEL_PMC_IDX_FIXED_BTS)
                 return 0;
 
         /*
@@ -86,7 +77,7 @@ u64 x86_perf_event_update(struct perf_event *event)
          */
 again:
         prev_raw_count = local64_read(&hwc->prev_count);
-        rdmsrl(hwc->event_base, new_raw_count);
+        rdpmcl(hwc->event_base_rdpmc, new_raw_count);
 
         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
                                         new_raw_count) != prev_raw_count)
@@ -189,7 +180,7 @@ static void release_pmc_hardware(void) {}
 
 static bool check_hw_exists(void)
 {
-        u64 val, val_new = 0;
+        u64 val, val_new = ~0;
         int i, reg, ret = 0;
 
         /*
@@ -222,8 +213,9 @@ static bool check_hw_exists(void)
          * that don't trap on the MSR access and always return 0s.
          */
         val = 0xabcdUL;
-        ret = checking_wrmsrl(x86_pmu_event_addr(0), val);
-        ret |= rdmsrl_safe(x86_pmu_event_addr(0), &val_new);
+        reg = x86_pmu_event_addr(0);
+        ret = wrmsrl_safe(reg, val);
+        ret |= rdmsrl_safe(reg, &val_new);
         if (ret || val != val_new)
                 goto msr_fail;
 
@@ -240,6 +232,7 @@ bios_fail:
 
 msr_fail:
         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
+        printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
 
         return false;
 }
@@ -388,7 +381,7 @@ int x86_pmu_hw_config(struct perf_event *event)
                 int precise = 0;
 
                 /* Support for constant skid */
-                if (x86_pmu.pebs_active) {
+                if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
                         precise++;
 
                         /* Support for IP fixup */
@@ -637,8 +630,8 @@ static bool __perf_sched_find_counter(struct perf_sched *sched)
         c = sched->constraints[sched->state.event];
 
         /* Prefer fixed purpose counters */
-        if (x86_pmu.num_counters_fixed) {
-                idx = X86_PMC_IDX_FIXED;
+        if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
+                idx = INTEL_PMC_IDX_FIXED;
                 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
                         if (!__test_and_set_bit(idx, sched->state.used))
                                 goto done;
@@ -646,7 +639,7 @@ static bool __perf_sched_find_counter(struct perf_sched *sched)
         }
         /* Grab the first unused counter starting with idx */
         idx = sched->state.counter;
-        for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_FIXED) {
+        for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
                 if (!__test_and_set_bit(idx, sched->state.used))
                         goto done;
         }
@@ -704,8 +697,8 @@ static bool perf_sched_next_event(struct perf_sched *sched)
 /*
  * Assign a counter for each event.
  */
-static int perf_assign_events(struct event_constraint **constraints, int n,
-                              int wmin, int wmax, int *assign)
+int perf_assign_events(struct event_constraint **constraints, int n,
+                        int wmin, int wmax, int *assign)
 {
         struct perf_sched sched;
 
@@ -824,15 +817,17 @@ static inline void x86_assign_hw_event(struct perf_event *event,
         hwc->last_cpu = smp_processor_id();
         hwc->last_tag = ++cpuc->tags[i];
 
-        if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
+        if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
                 hwc->config_base = 0;
                 hwc->event_base = 0;
-        } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
+        } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
-                hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - X86_PMC_IDX_FIXED);
+                hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
+                hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
         } else {
                 hwc->config_base = x86_pmu_config_addr(hwc->idx);
                 hwc->event_base  = x86_pmu_event_addr(hwc->idx);
+                hwc->event_base_rdpmc = hwc->idx;
         }
 }
 
@@ -930,7 +925,7 @@ int x86_perf_event_set_period(struct perf_event *event)
         s64 period = hwc->sample_period;
         int ret = 0, idx = hwc->idx;
 
-        if (idx == X86_PMC_IDX_FIXED_BTS)
+        if (idx == INTEL_PMC_IDX_FIXED_BTS)
                 return 0;
 
         /*
@@ -1316,7 +1311,6 @@ static struct attribute_group x86_pmu_format_group = {
 static int __init init_hw_perf_events(void)
 {
         struct x86_pmu_quirk *quirk;
-        struct event_constraint *c;
         int err;
 
         pr_info("Performance Events: ");
@@ -1347,21 +1341,8 @@ static int __init init_hw_perf_events(void)
         for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
                 quirk->func();
 
-        if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
-                WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
-                     x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
-                x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
-        }
-        x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
-
-        if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
-                WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
-                     x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
-                x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
-        }
-
-        x86_pmu.intel_ctrl |=
-                ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
+        if (!x86_pmu.intel_ctrl)
+                x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
 
         perf_events_lapic_init();
         register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
@@ -1370,22 +1351,6 @@ static int __init init_hw_perf_events(void)
                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
                                    0, x86_pmu.num_counters, 0);
 
-        if (x86_pmu.event_constraints) {
-                /*
-                 * event on fixed counter2 (REF_CYCLES) only works on this
-                 * counter, so do not extend mask to generic counters
-                 */
-                for_each_event_constraint(c, x86_pmu.event_constraints) {
-                        if (c->cmask != X86_RAW_EVENT_MASK
-                            || c->idxmsk64 == X86_PMC_MSK_FIXED_REF_CYCLES) {
-                                continue;
-                        }
-
-                        c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
-                        c->weight += x86_pmu.num_counters;
-                }
-        }
-
         x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
         x86_pmu_format_group.attrs = x86_pmu.format_attrs;
 
@@ -1620,8 +1585,8 @@ static int x86_pmu_event_idx(struct perf_event *event)
         if (!x86_pmu.attr_rdpmc)
                 return 0;
 
-        if (x86_pmu.num_counters_fixed && idx >= X86_PMC_IDX_FIXED) {
-                idx -= X86_PMC_IDX_FIXED;
+        if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
+                idx -= INTEL_PMC_IDX_FIXED;
                 idx |= 1 << 30;
         }
 
@@ -1649,7 +1614,12 @@ static ssize_t set_attr_rdpmc(struct device *cdev,
                               struct device_attribute *attr,
                               const char *buf, size_t count)
 {
-        unsigned long val = simple_strtoul(buf, NULL, 0);
+        unsigned long val;
+        ssize_t ret;
+
+        ret = kstrtoul(buf, 0, &val);
+        if (ret)
+                return ret;
 
         if (!!val != !!x86_pmu.attr_rdpmc) {
                 x86_pmu.attr_rdpmc = !!val;
@@ -1682,13 +1652,20 @@ static void x86_pmu_flush_branch_stack(void)
                 x86_pmu.flush_branch_stack();
 }
 
+void perf_check_microcode(void)
+{
+        if (x86_pmu.check_microcode)
+                x86_pmu.check_microcode();
+}
+EXPORT_SYMBOL_GPL(perf_check_microcode);
+
 static struct pmu pmu = {
         .pmu_enable             = x86_pmu_enable,
         .pmu_disable            = x86_pmu_disable,
 
-        .attr_groups    = x86_pmu_attr_groups,
+        .attr_groups            = x86_pmu_attr_groups,
 
-        .event_init     = x86_pmu_event_init,
+        .event_init             = x86_pmu_event_init,
 
         .add                    = x86_pmu_add,
         .del                    = x86_pmu_del,
@@ -1696,11 +1673,11 @@ static struct pmu pmu = {
         .stop                   = x86_pmu_stop,
         .read                   = x86_pmu_read,
 
-        .start_txn      = x86_pmu_start_txn,
-        .cancel_txn     = x86_pmu_cancel_txn,
-        .commit_txn     = x86_pmu_commit_txn,
+        .start_txn              = x86_pmu_start_txn,
+        .cancel_txn             = x86_pmu_cancel_txn,
+        .commit_txn             = x86_pmu_commit_txn,
 
-        .event_idx      = x86_pmu_event_idx,
+        .event_idx              = x86_pmu_event_idx,
         .flush_branch_stack     = x86_pmu_flush_branch_stack,
 };
 
@@ -1763,6 +1740,29 @@ valid_user_frame(const void __user *fp, unsigned long size)
         return (__range_not_ok(fp, size, TASK_SIZE) == 0);
 }
 
+static unsigned long get_segment_base(unsigned int segment)
+{
+        struct desc_struct *desc;
+        int idx = segment >> 3;
+
+        if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
+                if (idx > LDT_ENTRIES)
+                        return 0;
+
+                if (idx > current->active_mm->context.size)
+                        return 0;
+
+                desc = current->active_mm->context.ldt;
+        } else {
+                if (idx > GDT_ENTRIES)
+                        return 0;
+
+                desc = __this_cpu_ptr(&gdt_page.gdt[0]);
+        }
+
+        return get_desc_base(desc + idx);
+}
+
 #ifdef CONFIG_COMPAT
 
 #include <asm/compat.h>
@@ -1771,13 +1771,17 @@ static inline int
 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
 {
         /* 32-bit process in 64-bit kernel. */
+        unsigned long ss_base, cs_base;
         struct stack_frame_ia32 frame;
         const void __user *fp;
 
         if (!test_thread_flag(TIF_IA32))
                 return 0;
 
-        fp = compat_ptr(regs->bp);
+        cs_base = get_segment_base(regs->cs);
+        ss_base = get_segment_base(regs->ss);
+
+        fp = compat_ptr(ss_base + regs->bp);
         while (entry->nr < PERF_MAX_STACK_DEPTH) {
                 unsigned long bytes;
                 frame.next_frame     = 0;
@@ -1790,8 +1794,8 @@ perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
                 if (!valid_user_frame(fp, sizeof(frame)))
                         break;
 
-                perf_callchain_store(entry, frame.return_address);
-                fp = compat_ptr(frame.next_frame);
+                perf_callchain_store(entry, cs_base + frame.return_address);
+                fp = compat_ptr(ss_base + frame.next_frame);
         }
         return 1;
 }
@@ -1814,6 +1818,12 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
                 return;
         }
 
+        /*
+         * We don't know what to do with VM86 stacks.. ignore them for now.
+         */
+        if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
+                return;
+
         fp = (void __user *)regs->bp;
 
         perf_callchain_store(entry, regs->ip);
@@ -1841,16 +1851,50 @@ perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
         }
 }
 
-unsigned long perf_instruction_pointer(struct pt_regs *regs)
+/*
+ * Deal with code segment offsets for the various execution modes:
+ *
+ *   VM86 - the good olde 16 bit days, where the linear address is
+ *          20 bits and we use regs->ip + 0x10 * regs->cs.
+ *
+ *   IA32 - Where we need to look at GDT/LDT segment descriptor tables
+ *          to figure out what the 32bit base address is.
+ *
+ *    X32 - has TIF_X32 set, but is running in x86_64
+ *
+ * X86_64 - CS,DS,SS,ES are all zero based.
+ */
+static unsigned long code_segment_base(struct pt_regs *regs)
 {
-        unsigned long ip;
+        /*
+         * If we are in VM86 mode, add the segment offset to convert to a
+         * linear address.
+         */
+        if (regs->flags & X86_VM_MASK)
+                return 0x10 * regs->cs;
+
+        /*
+         * For IA32 we look at the GDT/LDT segment base to convert the
+         * effective IP to a linear address.
+         */
+#ifdef CONFIG_X86_32
+        if (user_mode(regs) && regs->cs != __USER_CS)
+                return get_segment_base(regs->cs);
+#else
+        if (test_thread_flag(TIF_IA32)) {
+                if (user_mode(regs) && regs->cs != __USER32_CS)
+                        return get_segment_base(regs->cs);
+        }
+#endif
+        return 0;
+}
 
+unsigned long perf_instruction_pointer(struct pt_regs *regs)
+{
         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
-                ip = perf_guest_cbs->get_guest_ip();
-        else
-                ip = instruction_pointer(regs);
+                return perf_guest_cbs->get_guest_ip();
 
-        return ip;
+        return regs->ip + code_segment_base(regs);
 }
 
 unsigned long perf_misc_flags(struct pt_regs *regs)
diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index 7241e2fc3c1..6605a81ba33 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -14,6 +14,18 @@
 
 #include <linux/perf_event.h>
 
+#if 0
+#undef wrmsrl
+#define wrmsrl(msr, val)                                                \
+do {                                                                    \
+        unsigned int _msr = (msr);                                      \
+        u64 _val = (val);                                               \
+        trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr),         \
+                        (unsigned long long)(_val));                    \
+        native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32));       \
+} while (0)
+#endif
+
 /*
  *          |   NHM/WSM    |      SNB     |
  * register -------------------------------
@@ -57,7 +69,7 @@ struct amd_nb {
 };
 
 /* The maximal number of PEBS events: */
-#define MAX_PEBS_EVENTS         4
+#define MAX_PEBS_EVENTS         8
 
 /*
  * A debug store configuration.
@@ -349,6 +361,8 @@ struct x86_pmu {
         void            (*cpu_starting)(int cpu);
         void            (*cpu_dying)(int cpu);
         void            (*cpu_dead)(int cpu);
+
+        void            (*check_microcode)(void);
         void            (*flush_branch_stack)(void);
 
         /*
@@ -360,12 +374,16 @@ struct x86_pmu {
         /*
          * Intel DebugStore bits
          */
-        int             bts, pebs;
-        int             bts_active, pebs_active;
+        unsigned int    bts             :1,
+                        bts_active      :1,
+                        pebs            :1,
+                        pebs_active     :1,
+                        pebs_broken     :1;
         int             pebs_record_size;
         void            (*drain_pebs)(struct pt_regs *regs);
         struct event_constraint *pebs_constraints;
         void            (*pebs_aliases)(struct perf_event *event);
+        int             max_pebs_events;
 
         /*
          * Intel LBR
@@ -468,6 +486,8 @@ static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
 
 void x86_pmu_enable_all(int added);
 
+int perf_assign_events(struct event_constraint **constraints, int n,
+                        int wmin, int wmax, int *assign);
 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
 
 void x86_pmu_stop(struct perf_event *event, int flags);
@@ -496,6 +516,26 @@ static inline bool kernel_ip(unsigned long ip)
 #endif
 }
 
+/*
+ * Not all PMUs provide the right context information to place the reported IP
+ * into full context. Specifically segment registers are typically not
+ * supplied.
+ *
+ * Assuming the address is a linear address (it is for IBS), we fake the CS and
+ * vm86 mode using the known zero-based code segment and 'fix up' the registers
+ * to reflect this.
+ *
+ * Intel PEBS/LBR appear to typically provide the effective address, nothing
+ * much we can do about that but pray and treat it like a linear address.
+ */
+static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
+{
+        regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
+        if (regs->flags & X86_VM_MASK)
+                regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
+        regs->ip = ip;
+}
+
 #ifdef CONFIG_CPU_SUP_AMD
 
 int amd_pmu_init(void);
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
index 11a4eb9131d..4528ae7b6ec 100644
--- a/arch/x86/kernel/cpu/perf_event_amd.c
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -366,7 +366,7 @@ static void amd_pmu_cpu_starting(int cpu)
 
         cpuc->perf_ctr_virt_mask = AMD_PERFMON_EVENTSEL_HOSTONLY;
 
-        if (boot_cpu_data.x86_max_cores < 2 || boot_cpu_data.x86 == 0x15)
+        if (boot_cpu_data.x86_max_cores < 2)
                 return;
 
         nb_id = amd_get_nb_id(cpu);
@@ -422,35 +422,6 @@ static struct attribute *amd_format_attr[] = {
         NULL,
 };
 
-static __initconst const struct x86_pmu amd_pmu = {
-        .name                   = "AMD",
-        .handle_irq             = x86_pmu_handle_irq,
-        .disable_all            = x86_pmu_disable_all,
-        .enable_all             = x86_pmu_enable_all,
-        .enable                 = x86_pmu_enable_event,
-        .disable                = x86_pmu_disable_event,
-        .hw_config              = amd_pmu_hw_config,
-        .schedule_events        = x86_schedule_events,
-        .eventsel               = MSR_K7_EVNTSEL0,
-        .perfctr                = MSR_K7_PERFCTR0,
-        .event_map              = amd_pmu_event_map,
-        .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
-        .num_counters           = AMD64_NUM_COUNTERS,
-        .cntval_bits            = 48,
-        .cntval_mask            = (1ULL << 48) - 1,
-        .apic                   = 1,
-        /* use highest bit to detect overflow */
-        .max_period             = (1ULL << 47) - 1,
-        .get_event_constraints  = amd_get_event_constraints,
-        .put_event_constraints  = amd_put_event_constraints,
-
-        .format_attrs           = amd_format_attr,
-
-        .cpu_prepare            = amd_pmu_cpu_prepare,
-        .cpu_starting           = amd_pmu_cpu_starting,
-        .cpu_dead               = amd_pmu_cpu_dead,
-};
-
 /* AMD Family 15h */
 
 #define AMD_EVENT_TYPE_MASK     0x000000F0ULL
@@ -597,8 +568,8 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, struct perf_event *ev
         }
 }
 
-static __initconst const struct x86_pmu amd_pmu_f15h = {
-        .name                   = "AMD Family 15h",
+static __initconst const struct x86_pmu amd_pmu = {
+        .name                   = "AMD",
         .handle_irq             = x86_pmu_handle_irq,
         .disable_all            = x86_pmu_disable_all,
         .enable_all             = x86_pmu_enable_all,
@@ -606,50 +577,68 @@ static __initconst const struct x86_pmu amd_pmu_f15h = {
         .disable                = x86_pmu_disable_event,
         .hw_config              = amd_pmu_hw_config,
         .schedule_events        = x86_schedule_events,
-        .eventsel               = MSR_F15H_PERF_CTL,
-        .perfctr                = MSR_F15H_PERF_CTR,
+        .eventsel               = MSR_K7_EVNTSEL0,
+        .perfctr                = MSR_K7_PERFCTR0,
         .event_map              = amd_pmu_event_map,
         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
-        .num_counters           = AMD64_NUM_COUNTERS_F15H,
+        .num_counters           = AMD64_NUM_COUNTERS,
         .cntval_bits            = 48,
         .cntval_mask            = (1ULL << 48) - 1,
         .apic                   = 1,
         /* use highest bit to detect overflow */
         .max_period             = (1ULL << 47) - 1,
-        .get_event_constraints  = amd_get_event_constraints_f15h,
-        /* nortbridge counters not yet implemented: */
-#if 0
+        .get_event_constraints  = amd_get_event_constraints,
         .put_event_constraints  = amd_put_event_constraints,
 
+        .format_attrs           = amd_format_attr,
+
         .cpu_prepare            = amd_pmu_cpu_prepare,
-        .cpu_dead               = amd_pmu_cpu_dead,
-#endif
         .cpu_starting           = amd_pmu_cpu_starting,
-        .format_attrs           = amd_format_attr,
+        .cpu_dead               = amd_pmu_cpu_dead,
 };
 
+static int setup_event_constraints(void)
+{
+        if (boot_cpu_data.x86 >= 0x15)
+                x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
+        return 0;
+}
+
+static int setup_perfctr_core(void)
+{
+        if (!cpu_has_perfctr_core) {
+                WARN(x86_pmu.get_event_constraints == amd_get_event_constraints_f15h,
+                     KERN_ERR "Odd, counter constraints enabled but no core perfctrs detected!");
+                return -ENODEV;
+        }
+
+        WARN(x86_pmu.get_event_constraints == amd_get_event_constraints,
+             KERN_ERR "hw perf events core counters need constraints handler!");
+
+        /*
+         * If core performance counter extensions exists, we must use
+         * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also
+         * x86_pmu_addr_offset().
+         */
+        x86_pmu.eventsel        = MSR_F15H_PERF_CTL;
+        x86_pmu.perfctr         = MSR_F15H_PERF_CTR;
+        x86_pmu.num_counters    = AMD64_NUM_COUNTERS_CORE;
+
+        printk(KERN_INFO "perf: AMD core performance counters detected\n");
+
+        return 0;
+}
+
 __init int amd_pmu_init(void)
 {
         /* Performance-monitoring supported from K7 and later: */
         if (boot_cpu_data.x86 < 6)
                 return -ENODEV;
 
-        /*
-         * If core performance counter extensions exists, it must be
-         * family 15h, otherwise fail. See x86_pmu_addr_offset().
-         */
-        switch (boot_cpu_data.x86) {
-        case 0x15:
-                if (!cpu_has_perfctr_core)
-                        return -ENODEV;
-                x86_pmu = amd_pmu_f15h;
-                break;
-        default:
-                if (cpu_has_perfctr_core)
-                        return -ENODEV;
-                x86_pmu = amd_pmu;
-                break;
-        }
+        x86_pmu = amd_pmu;
+
+        setup_event_constraints();
+        setup_perfctr_core();
 
         /* Events are common for all AMDs */
         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
index da9bcdcd985..7bfb5bec863 100644
--- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
+++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
@@ -13,6 +13,8 @@
 
 #include <asm/apic.h>
 
+#include "perf_event.h"
+
 static u32 ibs_caps;
 
 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
@@ -536,7 +538,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
         if (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
                 regs.flags &= ~PERF_EFLAGS_EXACT;
         } else {
-                instruction_pointer_set(&regs, ibs_data.regs[1]);
+                set_linear_ip(&regs, ibs_data.regs[1]);
                 regs.flags |= PERF_EFLAGS_EXACT;
         }
 
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 187c294bc65..7f2739e03e7 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -5,6 +5,8 @@
  * among events on a single PMU.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/stddef.h>
 #include <linux/types.h>
 #include <linux/init.h>
@@ -21,14 +23,14 @@
  */
 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
 {
-  [PERF_COUNT_HW_CPU_CYCLES]            = 0x003c,
-  [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
-  [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x4f2e,
-  [PERF_COUNT_HW_CACHE_MISSES]          = 0x412e,
-  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
-  [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
-  [PERF_COUNT_HW_BUS_CYCLES]            = 0x013c,
-  [PERF_COUNT_HW_REF_CPU_CYCLES]        = 0x0300, /* pseudo-encoding */
+        [PERF_COUNT_HW_CPU_CYCLES]              = 0x003c,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = 0x4f2e,
+        [PERF_COUNT_HW_CACHE_MISSES]            = 0x412e,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c4,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c5,
+        [PERF_COUNT_HW_BUS_CYCLES]              = 0x013c,
+        [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x0300, /* pseudo-encoding */
 };
 
 static struct event_constraint intel_core_event_constraints[] __read_mostly =
@@ -136,6 +138,84 @@ static u64 intel_pmu_event_map(int hw_event)
         return intel_perfmon_event_map[hw_event];
 }
 
+#define SNB_DMND_DATA_RD        (1ULL << 0)
+#define SNB_DMND_RFO            (1ULL << 1)
+#define SNB_DMND_IFETCH         (1ULL << 2)
+#define SNB_DMND_WB             (1ULL << 3)
+#define SNB_PF_DATA_RD          (1ULL << 4)
+#define SNB_PF_RFO              (1ULL << 5)
+#define SNB_PF_IFETCH           (1ULL << 6)
+#define SNB_LLC_DATA_RD         (1ULL << 7)
+#define SNB_LLC_RFO             (1ULL << 8)
+#define SNB_LLC_IFETCH          (1ULL << 9)
+#define SNB_BUS_LOCKS           (1ULL << 10)
+#define SNB_STRM_ST             (1ULL << 11)
+#define SNB_OTHER               (1ULL << 15)
+#define SNB_RESP_ANY            (1ULL << 16)
+#define SNB_NO_SUPP             (1ULL << 17)
+#define SNB_LLC_HITM            (1ULL << 18)
+#define SNB_LLC_HITE            (1ULL << 19)
+#define SNB_LLC_HITS            (1ULL << 20)
+#define SNB_LLC_HITF            (1ULL << 21)
+#define SNB_LOCAL               (1ULL << 22)
+#define SNB_REMOTE              (0xffULL << 23)
+#define SNB_SNP_NONE            (1ULL << 31)
+#define SNB_SNP_NOT_NEEDED      (1ULL << 32)
+#define SNB_SNP_MISS            (1ULL << 33)
+#define SNB_NO_FWD              (1ULL << 34)
+#define SNB_SNP_FWD             (1ULL << 35)
+#define SNB_HITM                (1ULL << 36)
+#define SNB_NON_DRAM            (1ULL << 37)
+
+#define SNB_DMND_READ           (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
+#define SNB_DMND_WRITE          (SNB_DMND_RFO|SNB_LLC_RFO)
+#define SNB_DMND_PREFETCH       (SNB_PF_DATA_RD|SNB_PF_RFO)
+
+#define SNB_SNP_ANY             (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
+                                 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
+                                 SNB_HITM)
+
+#define SNB_DRAM_ANY            (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
+#define SNB_DRAM_REMOTE         (SNB_REMOTE|SNB_SNP_ANY)
+
+#define SNB_L3_ACCESS           SNB_RESP_ANY
+#define SNB_L3_MISS             (SNB_DRAM_ANY|SNB_NON_DRAM)
+
+static __initconst const u64 snb_hw_cache_extra_regs
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(LL  ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
+                [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
+                [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
+                [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
+        },
+ },
+ [ C(NODE) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
+                [ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
+                [ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
+                [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
+        },
+ },
+};
+
 static __initconst const u64 snb_hw_cache_event_ids
                                 [PERF_COUNT_HW_CACHE_MAX]
                                 [PERF_COUNT_HW_CACHE_OP_MAX]
@@ -233,16 +313,16 @@ static __initconst const u64 snb_hw_cache_event_ids
  },
  [ C(NODE) ] = {
         [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
+                [ C(RESULT_ACCESS) ] = 0x01b7,
+                [ C(RESULT_MISS)   ] = 0x01b7,
         },
         [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
+                [ C(RESULT_ACCESS) ] = 0x01b7,
+                [ C(RESULT_MISS)   ] = 0x01b7,
         },
         [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
+                [ C(RESULT_ACCESS) ] = 0x01b7,
+                [ C(RESULT_MISS)   ] = 0x01b7,
         },
  },
 
@@ -747,7 +827,7 @@ static void intel_pmu_disable_all(void)
 
         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 
-        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
+        if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
                 intel_pmu_disable_bts();
 
         intel_pmu_pebs_disable_all();
@@ -763,9 +843,9 @@ static void intel_pmu_enable_all(int added)
         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
                         x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
 
-        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
+        if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
                 struct perf_event *event =
-                        cpuc->events[X86_PMC_IDX_FIXED_BTS];
+                        cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
 
                 if (WARN_ON_ONCE(!event))
                         return;
@@ -871,7 +951,7 @@ static inline void intel_pmu_ack_status(u64 ack)
 
 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
 {
-        int idx = hwc->idx - X86_PMC_IDX_FIXED;
+        int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
         u64 ctrl_val, mask;
 
         mask = 0xfULL << (idx * 4);
@@ -886,7 +966,7 @@ static void intel_pmu_disable_event(struct perf_event *event)
         struct hw_perf_event *hwc = &event->hw;
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-        if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
+        if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
                 intel_pmu_disable_bts();
                 intel_pmu_drain_bts_buffer();
                 return;
@@ -915,7 +995,7 @@ static void intel_pmu_disable_event(struct perf_event *event)
 
 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
 {
-        int idx = hwc->idx - X86_PMC_IDX_FIXED;
+        int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
         u64 ctrl_val, bits, mask;
 
         /*
@@ -949,7 +1029,7 @@ static void intel_pmu_enable_event(struct perf_event *event)
         struct hw_perf_event *hwc = &event->hw;
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
-        if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
+        if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
                 if (!__this_cpu_read(cpu_hw_events.enabled))
                         return;
 
@@ -1000,14 +1080,14 @@ static void intel_pmu_reset(void)
 
         local_irq_save(flags);
 
-        printk("clearing PMU state on CPU#%d\n", smp_processor_id());
+        pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
 
         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
-                checking_wrmsrl(x86_pmu_config_addr(idx), 0ull);
-                checking_wrmsrl(x86_pmu_event_addr(idx),  0ull);
+                wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
+                wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
         }
         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
-                checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
+                wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
 
         if (ds)
                 ds->bts_index = ds->bts_buffer_base;
@@ -1442,8 +1522,16 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
         arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
         arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
         arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
+        /*
+         * If PMU counter has PEBS enabled it is not enough to disable counter
+         * on a guest entry since PEBS memory write can overshoot guest entry
+         * and corrupt guest memory. Disabling PEBS solves the problem.
+         */
+        arr[1].msr = MSR_IA32_PEBS_ENABLE;
+        arr[1].host = cpuc->pebs_enabled;
+        arr[1].guest = 0;
 
-        *nr = 1;
+        *nr = 2;
         return arr;
 }
 
@@ -1707,16 +1795,61 @@ static __init void intel_clovertown_quirk(void)
          * But taken together it might just make sense to not enable PEBS on
          * these chips.
          */
-        printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
+        pr_warn("PEBS disabled due to CPU errata\n");
         x86_pmu.pebs = 0;
         x86_pmu.pebs_constraints = NULL;
 }
 
+static int intel_snb_pebs_broken(int cpu)
+{
+        u32 rev = UINT_MAX; /* default to broken for unknown models */
+
+        switch (cpu_data(cpu).x86_model) {
+        case 42: /* SNB */
+                rev = 0x28;
+                break;
+
+        case 45: /* SNB-EP */
+                switch (cpu_data(cpu).x86_mask) {
+                case 6: rev = 0x618; break;
+                case 7: rev = 0x70c; break;
+                }
+        }
+
+        return (cpu_data(cpu).microcode < rev);
+}
+
+static void intel_snb_check_microcode(void)
+{
+        int pebs_broken = 0;
+        int cpu;
+
+        get_online_cpus();
+        for_each_online_cpu(cpu) {
+                if ((pebs_broken = intel_snb_pebs_broken(cpu)))
+                        break;
+        }
+        put_online_cpus();
+
+        if (pebs_broken == x86_pmu.pebs_broken)
+                return;
+
+        /*
+         * Serialized by the microcode lock..
+         */
+        if (x86_pmu.pebs_broken) {
+                pr_info("PEBS enabled due to microcode update\n");
+                x86_pmu.pebs_broken = 0;
+        } else {
+                pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
+                x86_pmu.pebs_broken = 1;
+        }
+}
+
 static __init void intel_sandybridge_quirk(void)
 {
-        printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
-        x86_pmu.pebs = 0;
-        x86_pmu.pebs_constraints = NULL;
+        x86_pmu.check_microcode = intel_snb_check_microcode;
+        intel_snb_check_microcode();
 }
 
 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
@@ -1736,8 +1869,8 @@ static __init void intel_arch_events_quirk(void)
         /* disable event that reported as not presend by cpuid */
         for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
                 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
-                printk(KERN_WARNING "CPUID marked event: \'%s\' unavailable\n",
-                                intel_arch_events_map[bit].name);
+                pr_warn("CPUID marked event: \'%s\' unavailable\n",
+                        intel_arch_events_map[bit].name);
         }
 }
 
@@ -1756,7 +1889,7 @@ static __init void intel_nehalem_quirk(void)
                 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
                 ebx.split.no_branch_misses_retired = 0;
                 x86_pmu.events_maskl = ebx.full;
-                printk(KERN_INFO "CPU erratum AAJ80 worked around\n");
+                pr_info("CPU erratum AAJ80 worked around\n");
         }
 }
 
@@ -1765,6 +1898,7 @@ __init int intel_pmu_init(void)
         union cpuid10_edx edx;
         union cpuid10_eax eax;
         union cpuid10_ebx ebx;
+        struct event_constraint *c;
         unsigned int unused;
         int version;
 
@@ -1800,6 +1934,8 @@ __init int intel_pmu_init(void)
         x86_pmu.events_maskl            = ebx.full;
         x86_pmu.events_mask_len         = eax.split.mask_length;
 
+        x86_pmu.max_pebs_events         = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
+
         /*
          * Quirk: v2 perfmon does not report fixed-purpose events, so
          * assume at least 3 events:
@@ -1914,6 +2050,8 @@ __init int intel_pmu_init(void)
         case 58: /* IvyBridge */
                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
                        sizeof(hw_cache_event_ids));
+                memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
+                       sizeof(hw_cache_extra_regs));
 
                 intel_pmu_lbr_init_snb();
 
@@ -1951,5 +2089,37 @@ __init int intel_pmu_init(void)
                 }
         }
 
+        if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
+                WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
+                     x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
+                x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
+        }
+        x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
+
+        if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
+                WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
+                     x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
+                x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
+        }
+
+        x86_pmu.intel_ctrl |=
+                ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
+
+        if (x86_pmu.event_constraints) {
+                /*
+                 * event on fixed counter2 (REF_CYCLES) only works on this
+                 * counter, so do not extend mask to generic counters
+                 */
+                for_each_event_constraint(c, x86_pmu.event_constraints) {
+                        if (c->cmask != X86_RAW_EVENT_MASK
+                            || c->idxmsk64 == INTEL_PMC_MSK_FIXED_REF_CYCLES) {
+                                continue;
+                        }
+
+                        c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
+                        c->weight += x86_pmu.num_counters;
+                }
+        }
+
         return 0;
 }
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 35e2192df9f..e38d97bf425 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -248,7 +248,7 @@ void reserve_ds_buffers(void)
  */
 
 struct event_constraint bts_constraint =
-        EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
+        EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
 
 void intel_pmu_enable_bts(u64 config)
 {
@@ -295,7 +295,7 @@ int intel_pmu_drain_bts_buffer(void)
                 u64     to;
                 u64     flags;
         };
-        struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
+        struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
         struct bts_record *at, *top;
         struct perf_output_handle handle;
         struct perf_event_header header;
@@ -499,7 +499,7 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
          * We sampled a branch insn, rewind using the LBR stack
          */
         if (ip == to) {
-                regs->ip = from;
+                set_linear_ip(regs, from);
                 return 1;
         }
 
@@ -529,7 +529,7 @@ static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
         } while (to < ip);
 
         if (to == ip) {
-                regs->ip = old_to;
+                set_linear_ip(regs, old_to);
                 return 1;
         }
 
@@ -569,7 +569,8 @@ static void __intel_pmu_pebs_event(struct perf_event *event,
          * A possible PERF_SAMPLE_REGS will have to transfer all regs.
          */
         regs = *iregs;
-        regs.ip = pebs->ip;
+        regs.flags = pebs->flags;
+        set_linear_ip(&regs, pebs->ip);
         regs.bp = pebs->bp;
         regs.sp = pebs->sp;
 
@@ -620,7 +621,7 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
          * Should not happen, we program the threshold at 1 and do not
          * set a reset value.
          */
-        WARN_ON_ONCE(n > 1);
+        WARN_ONCE(n > 1, "bad leftover pebs %d\n", n);
         at += n - 1;
 
         __intel_pmu_pebs_event(event, iregs, at);
@@ -651,10 +652,10 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
          * Should not happen, we program the threshold at 1 and do not
          * set a reset value.
          */
-        WARN_ON_ONCE(n > MAX_PEBS_EVENTS);
+        WARN_ONCE(n > x86_pmu.max_pebs_events, "Unexpected number of pebs records %d\n", n);
 
         for ( ; at < top; at++) {
-                for_each_set_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) {
+                for_each_set_bit(bit, (unsigned long *)&at->status, x86_pmu.max_pebs_events) {
                         event = cpuc->events[bit];
                         if (!test_bit(bit, cpuc->active_mask))
                                 continue;
@@ -670,7 +671,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
                         break;
                 }
 
-                if (!event || bit >= MAX_PEBS_EVENTS)
+                if (!event || bit >= x86_pmu.max_pebs_events)
                         continue;
 
                 __intel_pmu_pebs_event(event, iregs, at);
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
new file mode 100644
index 00000000000..0a5571080e7
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -0,0 +1,2915 @@
+#include "perf_event_intel_uncore.h"
+
+static struct intel_uncore_type *empty_uncore[] = { NULL, };
+static struct intel_uncore_type **msr_uncores = empty_uncore;
+static struct intel_uncore_type **pci_uncores = empty_uncore;
+/* pci bus to socket mapping */
+static int pcibus_to_physid[256] = { [0 ... 255] = -1, };
+
+static DEFINE_RAW_SPINLOCK(uncore_box_lock);
+
+/* mask of cpus that collect uncore events */
+static cpumask_t uncore_cpu_mask;
+
+/* constraint for the fixed counter */
+static struct event_constraint constraint_fixed =
+        EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
+static struct event_constraint constraint_empty =
+        EVENT_CONSTRAINT(0, 0, 0);
+
+DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
+DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
+DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
+DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
+DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
+DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
+DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
+DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
+DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
+DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
+DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
+DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
+DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
+DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
+DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
+DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
+DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
+DEFINE_UNCORE_FORMAT_ATTR(filter_band0, filter_band0, "config1:0-7");
+DEFINE_UNCORE_FORMAT_ATTR(filter_band1, filter_band1, "config1:8-15");
+DEFINE_UNCORE_FORMAT_ATTR(filter_band2, filter_band2, "config1:16-23");
+DEFINE_UNCORE_FORMAT_ATTR(filter_band3, filter_band3, "config1:24-31");
+
+static u64 uncore_msr_read_counter(struct intel_uncore_box *box, struct perf_event *event)
+{
+        u64 count;
+
+        rdmsrl(event->hw.event_base, count);
+
+        return count;
+}
+
+/*
+ * generic get constraint function for shared match/mask registers.
+ */
+static struct event_constraint *
+uncore_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct intel_uncore_extra_reg *er;
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
+        unsigned long flags;
+        bool ok = false;
+
+        /*
+         * reg->alloc can be set due to existing state, so for fake box we
+         * need to ignore this, otherwise we might fail to allocate proper
+         * fake state for this extra reg constraint.
+         */
+        if (reg1->idx == EXTRA_REG_NONE ||
+            (!uncore_box_is_fake(box) && reg1->alloc))
+                return NULL;
+
+        er = &box->shared_regs[reg1->idx];
+        raw_spin_lock_irqsave(&er->lock, flags);
+        if (!atomic_read(&er->ref) ||
+            (er->config1 == reg1->config && er->config2 == reg2->config)) {
+                atomic_inc(&er->ref);
+                er->config1 = reg1->config;
+                er->config2 = reg2->config;
+                ok = true;
+        }
+        raw_spin_unlock_irqrestore(&er->lock, flags);
+
+        if (ok) {
+                if (!uncore_box_is_fake(box))
+                        reg1->alloc = 1;
+                return NULL;
+        }
+
+        return &constraint_empty;
+}
+
+static void uncore_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct intel_uncore_extra_reg *er;
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+
+        /*
+         * Only put constraint if extra reg was actually allocated. Also
+         * takes care of event which do not use an extra shared reg.
+         *
+         * Also, if this is a fake box we shouldn't touch any event state
+         * (reg->alloc) and we don't care about leaving inconsistent box
+         * state either since it will be thrown out.
+         */
+        if (uncore_box_is_fake(box) || !reg1->alloc)
+                return;
+
+        er = &box->shared_regs[reg1->idx];
+        atomic_dec(&er->ref);
+        reg1->alloc = 0;
+}
+
+/* Sandy Bridge-EP uncore support */
+static struct intel_uncore_type snbep_uncore_cbox;
+static struct intel_uncore_type snbep_uncore_pcu;
+
+static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
+{
+        struct pci_dev *pdev = box->pci_dev;
+        int box_ctl = uncore_pci_box_ctl(box);
+        u32 config;
+
+        pci_read_config_dword(pdev, box_ctl, &config);
+        config |= SNBEP_PMON_BOX_CTL_FRZ;
+        pci_write_config_dword(pdev, box_ctl, config);
+}
+
+static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
+{
+        struct pci_dev *pdev = box->pci_dev;
+        int box_ctl = uncore_pci_box_ctl(box);
+        u32 config;
+
+        pci_read_config_dword(pdev, box_ctl, &config);
+        config &= ~SNBEP_PMON_BOX_CTL_FRZ;
+        pci_write_config_dword(pdev, box_ctl, config);
+}
+
+static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct pci_dev *pdev = box->pci_dev;
+        struct hw_perf_event *hwc = &event->hw;
+
+        pci_write_config_dword(pdev, hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
+}
+
+static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct pci_dev *pdev = box->pci_dev;
+        struct hw_perf_event *hwc = &event->hw;
+
+        pci_write_config_dword(pdev, hwc->config_base, hwc->config);
+}
+
+static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct pci_dev *pdev = box->pci_dev;
+        struct hw_perf_event *hwc = &event->hw;
+        u64 count;
+
+        pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
+        pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
+
+        return count;
+}
+
+static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
+{
+        struct pci_dev *pdev = box->pci_dev;
+
+        pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, SNBEP_PMON_BOX_CTL_INT);
+}
+
+static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
+{
+        u64 config;
+        unsigned msr;
+
+        msr = uncore_msr_box_ctl(box);
+        if (msr) {
+                rdmsrl(msr, config);
+                config |= SNBEP_PMON_BOX_CTL_FRZ;
+                wrmsrl(msr, config);
+        }
+}
+
+static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
+{
+        u64 config;
+        unsigned msr;
+
+        msr = uncore_msr_box_ctl(box);
+        if (msr) {
+                rdmsrl(msr, config);
+                config &= ~SNBEP_PMON_BOX_CTL_FRZ;
+                wrmsrl(msr, config);
+        }
+}
+
+static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+
+        if (reg1->idx != EXTRA_REG_NONE)
+                wrmsrl(reg1->reg, reg1->config);
+
+        wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
+}
+
+static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
+                                        struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        wrmsrl(hwc->config_base, hwc->config);
+}
+
+static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
+{
+        unsigned msr = uncore_msr_box_ctl(box);
+
+        if (msr)
+                wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
+}
+
+static int snbep_uncore_hw_config(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+
+        if (box->pmu->type == &snbep_uncore_cbox) {
+                reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
+                        SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
+                reg1->config = event->attr.config1 &
+                        SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK;
+        } else {
+                if (box->pmu->type == &snbep_uncore_pcu) {
+                        reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
+                        reg1->config = event->attr.config1 & SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK;
+                } else {
+                        return 0;
+                }
+        }
+        reg1->idx = 0;
+
+        return 0;
+}
+
+static struct attribute *snbep_uncore_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_thresh8.attr,
+        NULL,
+};
+
+static struct attribute *snbep_uncore_ubox_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_thresh5.attr,
+        NULL,
+};
+
+static struct attribute *snbep_uncore_cbox_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_tid_en.attr,
+        &format_attr_inv.attr,
+        &format_attr_thresh8.attr,
+        &format_attr_filter_tid.attr,
+        &format_attr_filter_nid.attr,
+        &format_attr_filter_state.attr,
+        &format_attr_filter_opc.attr,
+        NULL,
+};
+
+static struct attribute *snbep_uncore_pcu_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_occ_sel.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_thresh5.attr,
+        &format_attr_occ_invert.attr,
+        &format_attr_occ_edge.attr,
+        &format_attr_filter_band0.attr,
+        &format_attr_filter_band1.attr,
+        &format_attr_filter_band2.attr,
+        &format_attr_filter_band3.attr,
+        NULL,
+};
+
+static struct attribute *snbep_uncore_qpi_formats_attr[] = {
+        &format_attr_event_ext.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_thresh8.attr,
+        NULL,
+};
+
+static struct uncore_event_desc snbep_uncore_imc_events[] = {
+        INTEL_UNCORE_EVENT_DESC(clockticks,      "event=0xff,umask=0x00"),
+        INTEL_UNCORE_EVENT_DESC(cas_count_read,  "event=0x04,umask=0x03"),
+        INTEL_UNCORE_EVENT_DESC(cas_count_write, "event=0x04,umask=0x0c"),
+        { /* end: all zeroes */ },
+};
+
+static struct uncore_event_desc snbep_uncore_qpi_events[] = {
+        INTEL_UNCORE_EVENT_DESC(clockticks,       "event=0x14"),
+        INTEL_UNCORE_EVENT_DESC(txl_flits_active, "event=0x00,umask=0x06"),
+        INTEL_UNCORE_EVENT_DESC(drs_data,         "event=0x02,umask=0x08"),
+        INTEL_UNCORE_EVENT_DESC(ncb_data,         "event=0x03,umask=0x04"),
+        { /* end: all zeroes */ },
+};
+
+static struct attribute_group snbep_uncore_format_group = {
+        .name = "format",
+        .attrs = snbep_uncore_formats_attr,
+};
+
+static struct attribute_group snbep_uncore_ubox_format_group = {
+        .name = "format",
+        .attrs = snbep_uncore_ubox_formats_attr,
+};
+
+static struct attribute_group snbep_uncore_cbox_format_group = {
+        .name = "format",
+        .attrs = snbep_uncore_cbox_formats_attr,
+};
+
+static struct attribute_group snbep_uncore_pcu_format_group = {
+        .name = "format",
+        .attrs = snbep_uncore_pcu_formats_attr,
+};
+
+static struct attribute_group snbep_uncore_qpi_format_group = {
+        .name = "format",
+        .attrs = snbep_uncore_qpi_formats_attr,
+};
+
+static struct intel_uncore_ops snbep_uncore_msr_ops = {
+        .init_box       = snbep_uncore_msr_init_box,
+        .disable_box    = snbep_uncore_msr_disable_box,
+        .enable_box     = snbep_uncore_msr_enable_box,
+        .disable_event  = snbep_uncore_msr_disable_event,
+        .enable_event   = snbep_uncore_msr_enable_event,
+        .read_counter   = uncore_msr_read_counter,
+        .get_constraint = uncore_get_constraint,
+        .put_constraint = uncore_put_constraint,
+        .hw_config      = snbep_uncore_hw_config,
+};
+
+static struct intel_uncore_ops snbep_uncore_pci_ops = {
+        .init_box       = snbep_uncore_pci_init_box,
+        .disable_box    = snbep_uncore_pci_disable_box,
+        .enable_box     = snbep_uncore_pci_enable_box,
+        .disable_event  = snbep_uncore_pci_disable_event,
+        .enable_event   = snbep_uncore_pci_enable_event,
+        .read_counter   = snbep_uncore_pci_read_counter,
+};
+
+static struct event_constraint snbep_uncore_cbox_constraints[] = {
+        UNCORE_EVENT_CONSTRAINT(0x01, 0x1),
+        UNCORE_EVENT_CONSTRAINT(0x02, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x04, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x05, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x07, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x11, 0x1),
+        UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x13, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x1b, 0xc),
+        UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
+        UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
+        UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
+        EVENT_CONSTRAINT_OVERLAP(0x1f, 0xe, 0xff),
+        UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x35, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x36, 0x1),
+        UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x38, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x39, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x3b, 0x1),
+        EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint snbep_uncore_r2pcie_constraints[] = {
+        UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x12, 0x1),
+        UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
+        EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint snbep_uncore_r3qpi_constraints[] = {
+        UNCORE_EVENT_CONSTRAINT(0x10, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x11, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x12, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x13, 0x1),
+        UNCORE_EVENT_CONSTRAINT(0x20, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x22, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x24, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x25, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x26, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x30, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x32, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x33, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x34, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x36, 0x3),
+        UNCORE_EVENT_CONSTRAINT(0x37, 0x3),
+        EVENT_CONSTRAINT_END
+};
+
+static struct intel_uncore_type snbep_uncore_ubox = {
+        .name           = "ubox",
+        .num_counters   = 2,
+        .num_boxes      = 1,
+        .perf_ctr_bits  = 44,
+        .fixed_ctr_bits = 48,
+        .perf_ctr       = SNBEP_U_MSR_PMON_CTR0,
+        .event_ctl      = SNBEP_U_MSR_PMON_CTL0,
+        .event_mask     = SNBEP_U_MSR_PMON_RAW_EVENT_MASK,
+        .fixed_ctr      = SNBEP_U_MSR_PMON_UCLK_FIXED_CTR,
+        .fixed_ctl      = SNBEP_U_MSR_PMON_UCLK_FIXED_CTL,
+        .ops            = &snbep_uncore_msr_ops,
+        .format_group   = &snbep_uncore_ubox_format_group,
+};
+
+static struct intel_uncore_type snbep_uncore_cbox = {
+        .name                   = "cbox",
+        .num_counters           = 4,
+        .num_boxes              = 8,
+        .perf_ctr_bits          = 44,
+        .event_ctl              = SNBEP_C0_MSR_PMON_CTL0,
+        .perf_ctr               = SNBEP_C0_MSR_PMON_CTR0,
+        .event_mask             = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
+        .box_ctl                = SNBEP_C0_MSR_PMON_BOX_CTL,
+        .msr_offset             = SNBEP_CBO_MSR_OFFSET,
+        .num_shared_regs        = 1,
+        .constraints            = snbep_uncore_cbox_constraints,
+        .ops                    = &snbep_uncore_msr_ops,
+        .format_group           = &snbep_uncore_cbox_format_group,
+};
+
+static struct intel_uncore_type snbep_uncore_pcu = {
+        .name                   = "pcu",
+        .num_counters           = 4,
+        .num_boxes              = 1,
+        .perf_ctr_bits          = 48,
+        .perf_ctr               = SNBEP_PCU_MSR_PMON_CTR0,
+        .event_ctl              = SNBEP_PCU_MSR_PMON_CTL0,
+        .event_mask             = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
+        .box_ctl                = SNBEP_PCU_MSR_PMON_BOX_CTL,
+        .num_shared_regs        = 1,
+        .ops                    = &snbep_uncore_msr_ops,
+        .format_group           = &snbep_uncore_pcu_format_group,
+};
+
+static struct intel_uncore_type *snbep_msr_uncores[] = {
+        &snbep_uncore_ubox,
+        &snbep_uncore_cbox,
+        &snbep_uncore_pcu,
+        NULL,
+};
+
+#define SNBEP_UNCORE_PCI_COMMON_INIT()                          \
+        .perf_ctr       = SNBEP_PCI_PMON_CTR0,                  \
+        .event_ctl      = SNBEP_PCI_PMON_CTL0,                  \
+        .event_mask     = SNBEP_PMON_RAW_EVENT_MASK,            \
+        .box_ctl        = SNBEP_PCI_PMON_BOX_CTL,               \
+        .ops            = &snbep_uncore_pci_ops,                \
+        .format_group   = &snbep_uncore_format_group
+
+static struct intel_uncore_type snbep_uncore_ha = {
+        .name           = "ha",
+        .num_counters   = 4,
+        .num_boxes      = 1,
+        .perf_ctr_bits  = 48,
+        SNBEP_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type snbep_uncore_imc = {
+        .name           = "imc",
+        .num_counters   = 4,
+        .num_boxes      = 4,
+        .perf_ctr_bits  = 48,
+        .fixed_ctr_bits = 48,
+        .fixed_ctr      = SNBEP_MC_CHy_PCI_PMON_FIXED_CTR,
+        .fixed_ctl      = SNBEP_MC_CHy_PCI_PMON_FIXED_CTL,
+        .event_descs    = snbep_uncore_imc_events,
+        SNBEP_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type snbep_uncore_qpi = {
+        .name           = "qpi",
+        .num_counters   = 4,
+        .num_boxes      = 2,
+        .perf_ctr_bits  = 48,
+        .perf_ctr       = SNBEP_PCI_PMON_CTR0,
+        .event_ctl      = SNBEP_PCI_PMON_CTL0,
+        .event_mask     = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
+        .box_ctl        = SNBEP_PCI_PMON_BOX_CTL,
+        .ops            = &snbep_uncore_pci_ops,
+        .event_descs    = snbep_uncore_qpi_events,
+        .format_group   = &snbep_uncore_qpi_format_group,
+};
+
+
+static struct intel_uncore_type snbep_uncore_r2pcie = {
+        .name           = "r2pcie",
+        .num_counters   = 4,
+        .num_boxes      = 1,
+        .perf_ctr_bits  = 44,
+        .constraints    = snbep_uncore_r2pcie_constraints,
+        SNBEP_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type snbep_uncore_r3qpi = {
+        .name           = "r3qpi",
+        .num_counters   = 3,
+        .num_boxes      = 2,
+        .perf_ctr_bits  = 44,
+        .constraints    = snbep_uncore_r3qpi_constraints,
+        SNBEP_UNCORE_PCI_COMMON_INIT(),
+};
+
+static struct intel_uncore_type *snbep_pci_uncores[] = {
+        &snbep_uncore_ha,
+        &snbep_uncore_imc,
+        &snbep_uncore_qpi,
+        &snbep_uncore_r2pcie,
+        &snbep_uncore_r3qpi,
+        NULL,
+};
+
+static DEFINE_PCI_DEVICE_TABLE(snbep_uncore_pci_ids) = {
+        { /* Home Agent */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_HA),
+                .driver_data = (unsigned long)&snbep_uncore_ha,
+        },
+        { /* MC Channel 0 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC0),
+                .driver_data = (unsigned long)&snbep_uncore_imc,
+        },
+        { /* MC Channel 1 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC1),
+                .driver_data = (unsigned long)&snbep_uncore_imc,
+        },
+        { /* MC Channel 2 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC2),
+                .driver_data = (unsigned long)&snbep_uncore_imc,
+        },
+        { /* MC Channel 3 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_IMC3),
+                .driver_data = (unsigned long)&snbep_uncore_imc,
+        },
+        { /* QPI Port 0 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI0),
+                .driver_data = (unsigned long)&snbep_uncore_qpi,
+        },
+        { /* QPI Port 1 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_QPI1),
+                .driver_data = (unsigned long)&snbep_uncore_qpi,
+        },
+        { /* P2PCIe */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R2PCIE),
+                .driver_data = (unsigned long)&snbep_uncore_r2pcie,
+        },
+        { /* R3QPI Link 0 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI0),
+                .driver_data = (unsigned long)&snbep_uncore_r3qpi,
+        },
+        { /* R3QPI Link 1 */
+                PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_UNC_R3QPI1),
+                .driver_data = (unsigned long)&snbep_uncore_r3qpi,
+        },
+        { /* end: all zeroes */ }
+};
+
+static struct pci_driver snbep_uncore_pci_driver = {
+        .name           = "snbep_uncore",
+        .id_table       = snbep_uncore_pci_ids,
+};
+
+/*
+ * build pci bus to socket mapping
+ */
+static void snbep_pci2phy_map_init(void)
+{
+        struct pci_dev *ubox_dev = NULL;
+        int i, bus, nodeid;
+        u32 config;
+
+        while (1) {
+                /* find the UBOX device */
+                ubox_dev = pci_get_device(PCI_VENDOR_ID_INTEL,
+                                        PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX,
+                                        ubox_dev);
+                if (!ubox_dev)
+                        break;
+                bus = ubox_dev->bus->number;
+                /* get the Node ID of the local register */
+                pci_read_config_dword(ubox_dev, 0x40, &config);
+                nodeid = config;
+                /* get the Node ID mapping */
+                pci_read_config_dword(ubox_dev, 0x54, &config);
+                /*
+                 * every three bits in the Node ID mapping register maps
+                 * to a particular node.
+                 */
+                for (i = 0; i < 8; i++) {
+                        if (nodeid == ((config >> (3 * i)) & 0x7)) {
+                                pcibus_to_physid[bus] = i;
+                                break;
+                        }
+                }
+        };
+        return;
+}
+/* end of Sandy Bridge-EP uncore support */
+
+/* Sandy Bridge uncore support */
+static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        if (hwc->idx < UNCORE_PMC_IDX_FIXED)
+                wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
+        else
+                wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
+}
+
+static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        wrmsrl(event->hw.config_base, 0);
+}
+
+static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
+{
+        if (box->pmu->pmu_idx == 0) {
+                wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
+                        SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
+        }
+}
+
+static struct attribute *snb_uncore_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_cmask5.attr,
+        NULL,
+};
+
+static struct attribute_group snb_uncore_format_group = {
+        .name           = "format",
+        .attrs          = snb_uncore_formats_attr,
+};
+
+static struct intel_uncore_ops snb_uncore_msr_ops = {
+        .init_box       = snb_uncore_msr_init_box,
+        .disable_event  = snb_uncore_msr_disable_event,
+        .enable_event   = snb_uncore_msr_enable_event,
+        .read_counter   = uncore_msr_read_counter,
+};
+
+static struct event_constraint snb_uncore_cbox_constraints[] = {
+        UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
+        UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
+        EVENT_CONSTRAINT_END
+};
+
+static struct intel_uncore_type snb_uncore_cbox = {
+        .name           = "cbox",
+        .num_counters   = 2,
+        .num_boxes      = 4,
+        .perf_ctr_bits  = 44,
+        .fixed_ctr_bits = 48,
+        .perf_ctr       = SNB_UNC_CBO_0_PER_CTR0,
+        .event_ctl      = SNB_UNC_CBO_0_PERFEVTSEL0,
+        .fixed_ctr      = SNB_UNC_FIXED_CTR,
+        .fixed_ctl      = SNB_UNC_FIXED_CTR_CTRL,
+        .single_fixed   = 1,
+        .event_mask     = SNB_UNC_RAW_EVENT_MASK,
+        .msr_offset     = SNB_UNC_CBO_MSR_OFFSET,
+        .constraints    = snb_uncore_cbox_constraints,
+        .ops            = &snb_uncore_msr_ops,
+        .format_group   = &snb_uncore_format_group,
+};
+
+static struct intel_uncore_type *snb_msr_uncores[] = {
+        &snb_uncore_cbox,
+        NULL,
+};
+/* end of Sandy Bridge uncore support */
+
+/* Nehalem uncore support */
+static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
+{
+        wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0);
+}
+
+static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
+{
+        wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
+}
+
+static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        if (hwc->idx < UNCORE_PMC_IDX_FIXED)
+                wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
+        else
+                wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);
+}
+
+static struct attribute *nhm_uncore_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_cmask8.attr,
+        NULL,
+};
+
+static struct attribute_group nhm_uncore_format_group = {
+        .name = "format",
+        .attrs = nhm_uncore_formats_attr,
+};
+
+static struct uncore_event_desc nhm_uncore_events[] = {
+        INTEL_UNCORE_EVENT_DESC(clockticks,                "event=0xff,umask=0x00"),
+        INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any,       "event=0x2f,umask=0x0f"),
+        INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any,      "event=0x2c,umask=0x0f"),
+        INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads,     "event=0x20,umask=0x01"),
+        INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes,    "event=0x20,umask=0x02"),
+        INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads,  "event=0x20,umask=0x04"),
+        INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
+        INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads,   "event=0x20,umask=0x10"),
+        INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes,  "event=0x20,umask=0x20"),
+        { /* end: all zeroes */ },
+};
+
+static struct intel_uncore_ops nhm_uncore_msr_ops = {
+        .disable_box    = nhm_uncore_msr_disable_box,
+        .enable_box     = nhm_uncore_msr_enable_box,
+        .disable_event  = snb_uncore_msr_disable_event,
+        .enable_event   = nhm_uncore_msr_enable_event,
+        .read_counter   = uncore_msr_read_counter,
+};
+
+static struct intel_uncore_type nhm_uncore = {
+        .name           = "",
+        .num_counters   = 8,
+        .num_boxes      = 1,
+        .perf_ctr_bits  = 48,
+        .fixed_ctr_bits = 48,
+        .event_ctl      = NHM_UNC_PERFEVTSEL0,
+        .perf_ctr       = NHM_UNC_UNCORE_PMC0,
+        .fixed_ctr      = NHM_UNC_FIXED_CTR,
+        .fixed_ctl      = NHM_UNC_FIXED_CTR_CTRL,
+        .event_mask     = NHM_UNC_RAW_EVENT_MASK,
+        .event_descs    = nhm_uncore_events,
+        .ops            = &nhm_uncore_msr_ops,
+        .format_group   = &nhm_uncore_format_group,
+};
+
+static struct intel_uncore_type *nhm_msr_uncores[] = {
+        &nhm_uncore,
+        NULL,
+};
+/* end of Nehalem uncore support */
+
+/* Nehalem-EX uncore support */
+#define __BITS_VALUE(x, i, n)  ((typeof(x))(((x) >> ((i) * (n))) & \
+                                ((1ULL << (n)) - 1)))
+
+DEFINE_UNCORE_FORMAT_ATTR(event5, event, "config:1-5");
+DEFINE_UNCORE_FORMAT_ATTR(counter, counter, "config:6-7");
+DEFINE_UNCORE_FORMAT_ATTR(match, match, "config1:0-63");
+DEFINE_UNCORE_FORMAT_ATTR(mask, mask, "config2:0-63");
+
+static void nhmex_uncore_msr_init_box(struct intel_uncore_box *box)
+{
+        wrmsrl(NHMEX_U_MSR_PMON_GLOBAL_CTL, NHMEX_U_PMON_GLOBAL_EN_ALL);
+}
+
+static void nhmex_uncore_msr_disable_box(struct intel_uncore_box *box)
+{
+        unsigned msr = uncore_msr_box_ctl(box);
+        u64 config;
+
+        if (msr) {
+                rdmsrl(msr, config);
+                config &= ~((1ULL << uncore_num_counters(box)) - 1);
+                /* WBox has a fixed counter */
+                if (uncore_msr_fixed_ctl(box))
+                        config &= ~NHMEX_W_PMON_GLOBAL_FIXED_EN;
+                wrmsrl(msr, config);
+        }
+}
+
+static void nhmex_uncore_msr_enable_box(struct intel_uncore_box *box)
+{
+        unsigned msr = uncore_msr_box_ctl(box);
+        u64 config;
+
+        if (msr) {
+                rdmsrl(msr, config);
+                config |= (1ULL << uncore_num_counters(box)) - 1;
+                /* WBox has a fixed counter */
+                if (uncore_msr_fixed_ctl(box))
+                        config |= NHMEX_W_PMON_GLOBAL_FIXED_EN;
+                wrmsrl(msr, config);
+        }
+}
+
+static void nhmex_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        wrmsrl(event->hw.config_base, 0);
+}
+
+static void nhmex_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        if (hwc->idx >= UNCORE_PMC_IDX_FIXED)
+                wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0);
+        else if (box->pmu->type->event_mask & NHMEX_PMON_CTL_EN_BIT0)
+                wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
+        else
+                wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
+}
+
+#define NHMEX_UNCORE_OPS_COMMON_INIT()                          \
+        .init_box       = nhmex_uncore_msr_init_box,            \
+        .disable_box    = nhmex_uncore_msr_disable_box,         \
+        .enable_box     = nhmex_uncore_msr_enable_box,          \
+        .disable_event  = nhmex_uncore_msr_disable_event,       \
+        .read_counter   = uncore_msr_read_counter
+
+static struct intel_uncore_ops nhmex_uncore_ops = {
+        NHMEX_UNCORE_OPS_COMMON_INIT(),
+        .enable_event   = nhmex_uncore_msr_enable_event,
+};
+
+static struct attribute *nhmex_uncore_ubox_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_edge.attr,
+        NULL,
+};
+
+static struct attribute_group nhmex_uncore_ubox_format_group = {
+        .name           = "format",
+        .attrs          = nhmex_uncore_ubox_formats_attr,
+};
+
+static struct intel_uncore_type nhmex_uncore_ubox = {
+        .name           = "ubox",
+        .num_counters   = 1,
+        .num_boxes      = 1,
+        .perf_ctr_bits  = 48,
+        .event_ctl      = NHMEX_U_MSR_PMON_EV_SEL,
+        .perf_ctr       = NHMEX_U_MSR_PMON_CTR,
+        .event_mask     = NHMEX_U_PMON_RAW_EVENT_MASK,
+        .box_ctl        = NHMEX_U_MSR_PMON_GLOBAL_CTL,
+        .ops            = &nhmex_uncore_ops,
+        .format_group   = &nhmex_uncore_ubox_format_group
+};
+
+static struct attribute *nhmex_uncore_cbox_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_thresh8.attr,
+        NULL,
+};
+
+static struct attribute_group nhmex_uncore_cbox_format_group = {
+        .name = "format",
+        .attrs = nhmex_uncore_cbox_formats_attr,
+};
+
+/* msr offset for each instance of cbox */
+static unsigned nhmex_cbox_msr_offsets[] = {
+        0x0, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x240, 0x2c0,
+};
+
+static struct intel_uncore_type nhmex_uncore_cbox = {
+        .name                   = "cbox",
+        .num_counters           = 6,
+        .num_boxes              = 10,
+        .perf_ctr_bits          = 48,
+        .event_ctl              = NHMEX_C0_MSR_PMON_EV_SEL0,
+        .perf_ctr               = NHMEX_C0_MSR_PMON_CTR0,
+        .event_mask             = NHMEX_PMON_RAW_EVENT_MASK,
+        .box_ctl                = NHMEX_C0_MSR_PMON_GLOBAL_CTL,
+        .msr_offsets            = nhmex_cbox_msr_offsets,
+        .pair_ctr_ctl           = 1,
+        .ops                    = &nhmex_uncore_ops,
+        .format_group           = &nhmex_uncore_cbox_format_group
+};
+
+static struct uncore_event_desc nhmex_uncore_wbox_events[] = {
+        INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0"),
+        { /* end: all zeroes */ },
+};
+
+static struct intel_uncore_type nhmex_uncore_wbox = {
+        .name                   = "wbox",
+        .num_counters           = 4,
+        .num_boxes              = 1,
+        .perf_ctr_bits          = 48,
+        .event_ctl              = NHMEX_W_MSR_PMON_CNT0,
+        .perf_ctr               = NHMEX_W_MSR_PMON_EVT_SEL0,
+        .fixed_ctr              = NHMEX_W_MSR_PMON_FIXED_CTR,
+        .fixed_ctl              = NHMEX_W_MSR_PMON_FIXED_CTL,
+        .event_mask             = NHMEX_PMON_RAW_EVENT_MASK,
+        .box_ctl                = NHMEX_W_MSR_GLOBAL_CTL,
+        .pair_ctr_ctl           = 1,
+        .event_descs            = nhmex_uncore_wbox_events,
+        .ops                    = &nhmex_uncore_ops,
+        .format_group           = &nhmex_uncore_cbox_format_group
+};
+
+static int nhmex_bbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
+        int ctr, ev_sel;
+
+        ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >>
+                NHMEX_B_PMON_CTR_SHIFT;
+        ev_sel = (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK) >>
+                  NHMEX_B_PMON_CTL_EV_SEL_SHIFT;
+
+        /* events that do not use the match/mask registers */
+        if ((ctr == 0 && ev_sel > 0x3) || (ctr == 1 && ev_sel > 0x6) ||
+            (ctr == 2 && ev_sel != 0x4) || ctr == 3)
+                return 0;
+
+        if (box->pmu->pmu_idx == 0)
+                reg1->reg = NHMEX_B0_MSR_MATCH;
+        else
+                reg1->reg = NHMEX_B1_MSR_MATCH;
+        reg1->idx = 0;
+        reg1->config = event->attr.config1;
+        reg2->config = event->attr.config2;
+        return 0;
+}
+
+static void nhmex_bbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
+
+        if (reg1->idx != EXTRA_REG_NONE) {
+                wrmsrl(reg1->reg, reg1->config);
+                wrmsrl(reg1->reg + 1, reg2->config);
+        }
+        wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
+                (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK));
+}
+
+/*
+ * The Bbox has 4 counters, but each counter monitors different events.
+ * Use bits 6-7 in the event config to select counter.
+ */
+static struct event_constraint nhmex_uncore_bbox_constraints[] = {
+        EVENT_CONSTRAINT(0 , 1, 0xc0),
+        EVENT_CONSTRAINT(0x40, 2, 0xc0),
+        EVENT_CONSTRAINT(0x80, 4, 0xc0),
+        EVENT_CONSTRAINT(0xc0, 8, 0xc0),
+        EVENT_CONSTRAINT_END,
+};
+
+static struct attribute *nhmex_uncore_bbox_formats_attr[] = {
+        &format_attr_event5.attr,
+        &format_attr_counter.attr,
+        &format_attr_match.attr,
+        &format_attr_mask.attr,
+        NULL,
+};
+
+static struct attribute_group nhmex_uncore_bbox_format_group = {
+        .name = "format",
+        .attrs = nhmex_uncore_bbox_formats_attr,
+};
+
+static struct intel_uncore_ops nhmex_uncore_bbox_ops = {
+        NHMEX_UNCORE_OPS_COMMON_INIT(),
+        .enable_event           = nhmex_bbox_msr_enable_event,
+        .hw_config              = nhmex_bbox_hw_config,
+        .get_constraint         = uncore_get_constraint,
+        .put_constraint         = uncore_put_constraint,
+};
+
+static struct intel_uncore_type nhmex_uncore_bbox = {
+        .name                   = "bbox",
+        .num_counters           = 4,
+        .num_boxes              = 2,
+        .perf_ctr_bits          = 48,
+        .event_ctl              = NHMEX_B0_MSR_PMON_CTL0,
+        .perf_ctr               = NHMEX_B0_MSR_PMON_CTR0,
+        .event_mask             = NHMEX_B_PMON_RAW_EVENT_MASK,
+        .box_ctl                = NHMEX_B0_MSR_PMON_GLOBAL_CTL,
+        .msr_offset             = NHMEX_B_MSR_OFFSET,
+        .pair_ctr_ctl           = 1,
+        .num_shared_regs        = 1,
+        .constraints            = nhmex_uncore_bbox_constraints,
+        .ops                    = &nhmex_uncore_bbox_ops,
+        .format_group           = &nhmex_uncore_bbox_format_group
+};
+
+static int nhmex_sbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
+
+        /* only TO_R_PROG_EV event uses the match/mask register */
+        if ((hwc->config & NHMEX_PMON_CTL_EV_SEL_MASK) !=
+            NHMEX_S_EVENT_TO_R_PROG_EV)
+                return 0;
+
+        if (box->pmu->pmu_idx == 0)
+                reg1->reg = NHMEX_S0_MSR_MM_CFG;
+        else
+                reg1->reg = NHMEX_S1_MSR_MM_CFG;
+        reg1->idx = 0;
+        reg1->config = event->attr.config1;
+        reg2->config = event->attr.config2;
+        return 0;
+}
+
+static void nhmex_sbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
+
+        if (reg1->idx != EXTRA_REG_NONE) {
+                wrmsrl(reg1->reg, 0);
+                wrmsrl(reg1->reg + 1, reg1->config);
+                wrmsrl(reg1->reg + 2, reg2->config);
+                wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN);
+        }
+        wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22);
+}
+
+static struct attribute *nhmex_uncore_sbox_formats_attr[] = {
+        &format_attr_event.attr,
+        &format_attr_umask.attr,
+        &format_attr_edge.attr,
+        &format_attr_inv.attr,
+        &format_attr_thresh8.attr,
+        &format_attr_match.attr,
+        &format_attr_mask.attr,
+        NULL,
+};
+
+static struct attribute_group nhmex_uncore_sbox_format_group = {
+        .name                   = "format",
+        .attrs                  = nhmex_uncore_sbox_formats_attr,
+};
+
+static struct intel_uncore_ops nhmex_uncore_sbox_ops = {
+        NHMEX_UNCORE_OPS_COMMON_INIT(),
+        .enable_event           = nhmex_sbox_msr_enable_event,
+        .hw_config              = nhmex_sbox_hw_config,
+        .get_constraint         = uncore_get_constraint,
+        .put_constraint         = uncore_put_constraint,
+};
+
+static struct intel_uncore_type nhmex_uncore_sbox = {
+        .name                   = "sbox",
+        .num_counters           = 4,
+        .num_boxes              = 2,
+        .perf_ctr_bits          = 48,
+        .event_ctl              = NHMEX_S0_MSR_PMON_CTL0,
+        .perf_ctr               = NHMEX_S0_MSR_PMON_CTR0,
+        .event_mask             = NHMEX_PMON_RAW_EVENT_MASK,
+        .box_ctl                = NHMEX_S0_MSR_PMON_GLOBAL_CTL,
+        .msr_offset             = NHMEX_S_MSR_OFFSET,
+        .pair_ctr_ctl           = 1,
+        .num_shared_regs        = 1,
+        .ops                    = &nhmex_uncore_sbox_ops,
+        .format_group           = &nhmex_uncore_sbox_format_group
+};
+
+enum {
+        EXTRA_REG_NHMEX_M_FILTER,
+        EXTRA_REG_NHMEX_M_DSP,
+        EXTRA_REG_NHMEX_M_ISS,
+        EXTRA_REG_NHMEX_M_MAP,
+        EXTRA_REG_NHMEX_M_MSC_THR,
+        EXTRA_REG_NHMEX_M_PGT,
+        EXTRA_REG_NHMEX_M_PLD,
+        EXTRA_REG_NHMEX_M_ZDP_CTL_FVC,
+};
+
+static struct extra_reg nhmex_uncore_mbox_extra_regs[] = {
+        MBOX_INC_SEL_EXTAR_REG(0x0, DSP),
+        MBOX_INC_SEL_EXTAR_REG(0x4, MSC_THR),
+        MBOX_INC_SEL_EXTAR_REG(0x5, MSC_THR),
+        MBOX_INC_SEL_EXTAR_REG(0x9, ISS),
+        /* event 0xa uses two extra registers */
+        MBOX_INC_SEL_EXTAR_REG(0xa, ISS),
+        MBOX_INC_SEL_EXTAR_REG(0xa, PLD),
+        MBOX_INC_SEL_EXTAR_REG(0xb, PLD),
+        /* events 0xd ~ 0x10 use the same extra register */
+        MBOX_INC_SEL_EXTAR_REG(0xd, ZDP_CTL_FVC),
+        MBOX_INC_SEL_EXTAR_REG(0xe, ZDP_CTL_FVC),
+        MBOX_INC_SEL_EXTAR_REG(0xf, ZDP_CTL_FVC),
+        MBOX_INC_SEL_EXTAR_REG(0x10, ZDP_CTL_FVC),
+        MBOX_INC_SEL_EXTAR_REG(0x16, PGT),
+        MBOX_SET_FLAG_SEL_EXTRA_REG(0x0, DSP),
+        MBOX_SET_FLAG_SEL_EXTRA_REG(0x1, ISS),
+        MBOX_SET_FLAG_SEL_EXTRA_REG(0x5, PGT),
+        MBOX_SET_FLAG_SEL_EXTRA_REG(0x6, MAP),
+        EVENT_EXTRA_END
+};
+
+/* Nehalem-EX or Westmere-EX ? */
+bool uncore_nhmex;
+
+static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config)
+{
+        struct intel_uncore_extra_reg *er;
+        unsigned long flags;
+        bool ret = false;
+        u64 mask;
+
+        if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
+                er = &box->shared_regs[idx];
+                raw_spin_lock_irqsave(&er->lock, flags);
+                if (!atomic_read(&er->ref) || er->config == config) {
+                        atomic_inc(&er->ref);
+                        er->config = config;
+                        ret = true;
+                }
+                raw_spin_unlock_irqrestore(&er->lock, flags);
+
+                return ret;
+        }
+        /*
+         * The ZDP_CTL_FVC MSR has 4 fields which are used to control
+         * events 0xd ~ 0x10. Besides these 4 fields, there are additional
+         * fields which are shared.
+         */
+        idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
+        if (WARN_ON_ONCE(idx >= 4))
+                return false;
+
+        /* mask of the shared fields */
+        if (uncore_nhmex)
+                mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK;
+        else
+                mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK;
+        er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
+
+        raw_spin_lock_irqsave(&er->lock, flags);
+        /* add mask of the non-shared field if it's in use */
+        if (__BITS_VALUE(atomic_read(&er->ref), idx, 8)) {
+                if (uncore_nhmex)
+                        mask |= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
+                else
+                        mask |= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
+        }
+
+        if (!atomic_read(&er->ref) || !((er->config ^ config) & mask)) {
+                atomic_add(1 << (idx * 8), &er->ref);
+                if (uncore_nhmex)
+                        mask = NHMEX_M_PMON_ZDP_CTL_FVC_MASK |
+                                NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
+                else
+                        mask = WSMEX_M_PMON_ZDP_CTL_FVC_MASK |
+                                WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
+                er->config &= ~mask;
+                er->config |= (config & mask);
+                ret = true;
+        }
+        raw_spin_unlock_irqrestore(&er->lock, flags);
+
+        return ret;
+}
+
+static void nhmex_mbox_put_shared_reg(struct intel_uncore_box *box, int idx)
+{
+        struct intel_uncore_extra_reg *er;
+
+        if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
+                er = &box->shared_regs[idx];
+                atomic_dec(&er->ref);
+                return;
+        }
+
+        idx -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
+        er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
+        atomic_sub(1 << (idx * 8), &er->ref);
+}
+
+u64 nhmex_mbox_alter_er(struct perf_event *event, int new_idx, bool modify)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        int idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8);
+        u64 config = reg1->config;
+
+        /* get the non-shared control bits and shift them */
+        idx = orig_idx - EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
+        if (uncore_nhmex)
+                config &= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
+        else
+                config &= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx);
+        if (new_idx > orig_idx) {
+                idx = new_idx - orig_idx;
+                config <<= 3 * idx;
+        } else {
+                idx = orig_idx - new_idx;
+                config >>= 3 * idx;
+        }
+
+        /* add the shared control bits back */
+        if (uncore_nhmex)
+                config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
+        else
+                config |= WSMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
+        config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config;
+        if (modify) {
+                /* adjust the main event selector */
+                if (new_idx > orig_idx)
+                        hwc->config += idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
+                else
+                        hwc->config -= idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT;
+                reg1->config = config;
+                reg1->idx = ~0xff | new_idx;
+        }
+        return config;
+}
+
+static struct event_constraint *
+nhmex_mbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
+        int i, idx[2], alloc = 0;
+        u64 config1 = reg1->config;
+
+        idx[0] = __BITS_VALUE(reg1->idx, 0, 8);
+        idx[1] = __BITS_VALUE(reg1->idx, 1, 8);
+again:
+        for (i = 0; i < 2; i++) {
+                if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i)))
+                        idx[i] = 0xff;
+
+                if (idx[i] == 0xff)
+                        continue;
+
+                if (!nhmex_mbox_get_shared_reg(box, idx[i],
+                                __BITS_VALUE(config1, i, 32)))
+                        goto fail;
+                alloc |= (0x1 << i);
+        }
+
+        /* for the match/mask registers */
+        if (reg2->idx != EXTRA_REG_NONE &&
+            (uncore_box_is_fake(box) || !reg2->alloc) &&
+            !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config))
+                goto fail;
+
+        /*
+         * If it's a fake box -- as per validate_{group,event}() we
+         * shouldn't touch event state and we can avoid doing so
+         * since both will only call get_event_constraints() once
+         * on each event, this avoids the need for reg->alloc.
+         */
+        if (!uncore_box_is_fake(box)) {
+                if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8))
+                        nhmex_mbox_alter_er(event, idx[0], true);
+                reg1->alloc |= alloc;
+                if (reg2->idx != EXTRA_REG_NONE)
+                        reg2->alloc = 1;
+        }
+        return NULL;
+fail:
+        if (idx[0] != 0xff && !(alloc & 0x1) &&
+            idx[0] >= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC) {
+                /*
+                 * events 0xd ~ 0x10 are functional identical, but are
+                 * controlled by different fields in the ZDP_CTL_FVC
+                 * register. If we failed to take one field, try the
+                 * rest 3 choices.
+                 */
+                BUG_ON(__BITS_VALUE(reg1->idx, 1, 8) != 0xff);
+                idx[0] -= EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
+                idx[0] = (idx[0] + 1) % 4;
+                idx[0] += EXTRA_REG_NHMEX_M_ZDP_CTL_FVC;
+                if (idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) {
+                        config1 = nhmex_mbox_alter_er(event, idx[0], false);
+                        goto again;
+                }
+        }
+
+        if (alloc & 0x1)
+                nhmex_mbox_put_shared_reg(box, idx[0]);
+        if (alloc & 0x2)
+                nhmex_mbox_put_shared_reg(box, idx[1]);
+        return &constraint_empty;
+}
+
+static void nhmex_mbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
+
+        if (uncore_box_is_fake(box))
+                return;
+
+        if (reg1->alloc & 0x1)
+                nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8));
+        if (reg1->alloc & 0x2)
+                nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8));
+        reg1->alloc = 0;
+
+        if (reg2->alloc) {
+                nhmex_mbox_put_shared_reg(box, reg2->idx);
+                reg2->alloc = 0;
+        }
+}
+
+static int nhmex_mbox_extra_reg_idx(struct extra_reg *er)
+{
+        if (er->idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
+                return er->idx;
+        return er->idx + (er->event >> NHMEX_M_PMON_CTL_INC_SEL_SHIFT) - 0xd;
+}
+
+static int nhmex_mbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct intel_uncore_type *type = box->pmu->type;
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
+        struct extra_reg *er;
+        unsigned msr;
+        int reg_idx = 0;
+        /*
+         * The mbox events may require 2 extra MSRs at the most. But only
+         * the lower 32 bits in these MSRs are significant, so we can use
+         * config1 to pass two MSRs' config.
+         */
+        for (er = nhmex_uncore_mbox_extra_regs; er->msr; er++) {
+                if (er->event != (event->hw.config & er->config_mask))
+                        continue;
+                if (event->attr.config1 & ~er->valid_mask)
+                        return -EINVAL;
+
+                msr = er->msr + type->msr_offset * box->pmu->pmu_idx;
+                if (WARN_ON_ONCE(msr >= 0xffff || er->idx >= 0xff))
+                        return -EINVAL;
+
+                /* always use the 32~63 bits to pass the PLD config */
+                if (er->idx == EXTRA_REG_NHMEX_M_PLD)
+                        reg_idx = 1;
+                else if (WARN_ON_ONCE(reg_idx > 0))
+                        return -EINVAL;
+
+                reg1->idx &= ~(0xff << (reg_idx * 8));
+                reg1->reg &= ~(0xffff << (reg_idx * 16));
+                reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8);
+                reg1->reg |= msr << (reg_idx * 16);
+                reg1->config = event->attr.config1;
+                reg_idx++;
+        }
+        /*
+         * The mbox only provides ability to perform address matching
+         * for the PLD events.
+         */
+        if (reg_idx == 2) {
+                reg2->idx = EXTRA_REG_NHMEX_M_FILTER;
+                if (event->attr.config2 & NHMEX_M_PMON_MM_CFG_EN)
+                        reg2->config = event->attr.config2;
+                else
+                        reg2->config = ~0ULL;
+                if (box->pmu->pmu_idx == 0)
+                        reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG;
+                else
+                        reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG;
+        }
+        return 0;
+}
+
+static u64 nhmex_mbox_shared_reg_config(struct intel_uncore_box *box, int idx)
+{
+        struct intel_uncore_extra_reg *er;
+        unsigned long flags;
+        u64 config;
+
+        if (idx < EXTRA_REG_NHMEX_M_ZDP_CTL_FVC)
+                return box->shared_regs[idx].config;
+
+        er = &box->shared_regs[EXTRA_REG_NHMEX_M_ZDP_CTL_FVC];
+        raw_spin_lock_irqsave(&er->lock, flags);
+        config = er->config;
+        raw_spin_unlock_irqrestore(&er->lock, flags);
+        return config;
+}
+
+static void nhmex_mbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
+        int idx;
+
+        idx = __BITS_VALUE(reg1->idx, 0, 8);
+        if (idx != 0xff)
+                wrmsrl(__BITS_VALUE(reg1->reg, 0, 16),
+                        nhmex_mbox_shared_reg_config(box, idx));
+        idx = __BITS_VALUE(reg1->idx, 1, 8);
+        if (idx != 0xff)
+                wrmsrl(__BITS_VALUE(reg1->reg, 1, 16),
+                        nhmex_mbox_shared_reg_config(box, idx));
+
+        if (reg2->idx != EXTRA_REG_NONE) {
+                wrmsrl(reg2->reg, 0);
+                if (reg2->config != ~0ULL) {
+                        wrmsrl(reg2->reg + 1,
+                                reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK);
+                        wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK &
+                                (reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT));
+                        wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN);
+                }
+        }
+
+        wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0);
+}
+
+DEFINE_UNCORE_FORMAT_ATTR(count_mode,           count_mode,     "config:2-3");
+DEFINE_UNCORE_FORMAT_ATTR(storage_mode,         storage_mode,   "config:4-5");
+DEFINE_UNCORE_FORMAT_ATTR(wrap_mode,            wrap_mode,      "config:6");
+DEFINE_UNCORE_FORMAT_ATTR(flag_mode,            flag_mode,      "config:7");
+DEFINE_UNCORE_FORMAT_ATTR(inc_sel,              inc_sel,        "config:9-13");
+DEFINE_UNCORE_FORMAT_ATTR(set_flag_sel,         set_flag_sel,   "config:19-21");
+DEFINE_UNCORE_FORMAT_ATTR(filter_cfg_en,        filter_cfg_en,  "config2:63");
+DEFINE_UNCORE_FORMAT_ATTR(filter_match,         filter_match,   "config2:0-33");
+DEFINE_UNCORE_FORMAT_ATTR(filter_mask,          filter_mask,    "config2:34-61");
+DEFINE_UNCORE_FORMAT_ATTR(dsp,                  dsp,            "config1:0-31");
+DEFINE_UNCORE_FORMAT_ATTR(thr,                  thr,            "config1:0-31");
+DEFINE_UNCORE_FORMAT_ATTR(fvc,                  fvc,            "config1:0-31");
+DEFINE_UNCORE_FORMAT_ATTR(pgt,                  pgt,            "config1:0-31");
+DEFINE_UNCORE_FORMAT_ATTR(map,                  map,            "config1:0-31");
+DEFINE_UNCORE_FORMAT_ATTR(iss,                  iss,            "config1:0-31");
+DEFINE_UNCORE_FORMAT_ATTR(pld,                  pld,            "config1:32-63");
+
+static struct attribute *nhmex_uncore_mbox_formats_attr[] = {
+        &format_attr_count_mode.attr,
+        &format_attr_storage_mode.attr,
+        &format_attr_wrap_mode.attr,
+        &format_attr_flag_mode.attr,
+        &format_attr_inc_sel.attr,
+        &format_attr_set_flag_sel.attr,
+        &format_attr_filter_cfg_en.attr,
+        &format_attr_filter_match.attr,
+        &format_attr_filter_mask.attr,
+        &format_attr_dsp.attr,
+        &format_attr_thr.attr,
+        &format_attr_fvc.attr,
+        &format_attr_pgt.attr,
+        &format_attr_map.attr,
+        &format_attr_iss.attr,
+        &format_attr_pld.attr,
+        NULL,
+};
+
+static struct attribute_group nhmex_uncore_mbox_format_group = {
+        .name           = "format",
+        .attrs          = nhmex_uncore_mbox_formats_attr,
+};
+
+static struct uncore_event_desc nhmex_uncore_mbox_events[] = {
+        INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x2800"),
+        INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x2820"),
+        { /* end: all zeroes */ },
+};
+
+static struct uncore_event_desc wsmex_uncore_mbox_events[] = {
+        INTEL_UNCORE_EVENT_DESC(bbox_cmds_read, "inc_sel=0xd,fvc=0x5000"),
+        INTEL_UNCORE_EVENT_DESC(bbox_cmds_write, "inc_sel=0xd,fvc=0x5040"),
+        { /* end: all zeroes */ },
+};
+
+static struct intel_uncore_ops nhmex_uncore_mbox_ops = {
+        NHMEX_UNCORE_OPS_COMMON_INIT(),
+        .enable_event   = nhmex_mbox_msr_enable_event,
+        .hw_config      = nhmex_mbox_hw_config,
+        .get_constraint = nhmex_mbox_get_constraint,
+        .put_constraint = nhmex_mbox_put_constraint,
+};
+
+static struct intel_uncore_type nhmex_uncore_mbox = {
+        .name                   = "mbox",
+        .num_counters           = 6,
+        .num_boxes              = 2,
+        .perf_ctr_bits          = 48,
+        .event_ctl              = NHMEX_M0_MSR_PMU_CTL0,
+        .perf_ctr               = NHMEX_M0_MSR_PMU_CNT0,
+        .event_mask             = NHMEX_M_PMON_RAW_EVENT_MASK,
+        .box_ctl                = NHMEX_M0_MSR_GLOBAL_CTL,
+        .msr_offset             = NHMEX_M_MSR_OFFSET,
+        .pair_ctr_ctl           = 1,
+        .num_shared_regs        = 8,
+        .event_descs            = nhmex_uncore_mbox_events,
+        .ops                    = &nhmex_uncore_mbox_ops,
+        .format_group           = &nhmex_uncore_mbox_format_group,
+};
+
+void nhmex_rbox_alter_er(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        int port;
+
+        /* adjust the main event selector and extra register index */
+        if (reg1->idx % 2) {
+                reg1->idx--;
+                hwc->config -= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
+        } else {
+                reg1->idx++;
+                hwc->config += 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
+        }
+
+        /* adjust extra register config */
+        port = reg1->idx / 6 + box->pmu->pmu_idx * 4;
+        switch (reg1->idx % 6) {
+        case 2:
+                /* shift the 8~15 bits to the 0~7 bits */
+                reg1->config >>= 8;
+                break;
+        case 3:
+                /* shift the 0~7 bits to the 8~15 bits */
+                reg1->config <<= 8;
+                break;
+        };
+}
+
+/*
+ * Each rbox has 4 event set which monitor PQI port 0~3 or 4~7.
+ * An event set consists of 6 events, the 3rd and 4th events in
+ * an event set use the same extra register. So an event set uses
+ * 5 extra registers.
+ */
+static struct event_constraint *
+nhmex_rbox_get_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
+        struct intel_uncore_extra_reg *er;
+        unsigned long flags;
+        int idx, er_idx;
+        u64 config1;
+        bool ok = false;
+
+        if (!uncore_box_is_fake(box) && reg1->alloc)
+                return NULL;
+
+        idx = reg1->idx % 6;
+        config1 = reg1->config;
+again:
+        er_idx = idx;
+        /* the 3rd and 4th events use the same extra register */
+        if (er_idx > 2)
+                er_idx--;
+        er_idx += (reg1->idx / 6) * 5;
+
+        er = &box->shared_regs[er_idx];
+        raw_spin_lock_irqsave(&er->lock, flags);
+        if (idx < 2) {
+                if (!atomic_read(&er->ref) || er->config == reg1->config) {
+                        atomic_inc(&er->ref);
+                        er->config = reg1->config;
+                        ok = true;
+                }
+        } else if (idx == 2 || idx == 3) {
+                /*
+                 * these two events use different fields in a extra register,
+                 * the 0~7 bits and the 8~15 bits respectively.
+                 */
+                u64 mask = 0xff << ((idx - 2) * 8);
+                if (!__BITS_VALUE(atomic_read(&er->ref), idx - 2, 8) ||
+                                !((er->config ^ config1) & mask)) {
+                        atomic_add(1 << ((idx - 2) * 8), &er->ref);
+                        er->config &= ~mask;
+                        er->config |= config1 & mask;
+                        ok = true;
+                }
+        } else {
+                if (!atomic_read(&er->ref) ||
+                                (er->config == (hwc->config >> 32) &&
+                                 er->config1 == reg1->config &&
+                                 er->config2 == reg2->config)) {
+                        atomic_inc(&er->ref);
+                        er->config = (hwc->config >> 32);
+                        er->config1 = reg1->config;
+                        er->config2 = reg2->config;
+                        ok = true;
+                }
+        }
+        raw_spin_unlock_irqrestore(&er->lock, flags);
+
+        if (!ok) {
+                /*
+                 * The Rbox events are always in pairs. The paired
+                 * events are functional identical, but use different
+                 * extra registers. If we failed to take an extra
+                 * register, try the alternative.
+                 */
+                if (idx % 2)
+                        idx--;
+                else
+                        idx++;
+                if (idx != reg1->idx % 6) {
+                        if (idx == 2)
+                                config1 >>= 8;
+                        else if (idx == 3)
+                                config1 <<= 8;
+                        goto again;
+                }
+        } else {
+                if (!uncore_box_is_fake(box)) {
+                        if (idx != reg1->idx % 6)
+                                nhmex_rbox_alter_er(box, event);
+                        reg1->alloc = 1;
+                }
+                return NULL;
+        }
+        return &constraint_empty;
+}
+
+static void nhmex_rbox_put_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct intel_uncore_extra_reg *er;
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        int idx, er_idx;
+
+        if (uncore_box_is_fake(box) || !reg1->alloc)
+                return;
+
+        idx = reg1->idx % 6;
+        er_idx = idx;
+        if (er_idx > 2)
+                er_idx--;
+        er_idx += (reg1->idx / 6) * 5;
+
+        er = &box->shared_regs[er_idx];
+        if (idx == 2 || idx == 3)
+                atomic_sub(1 << ((idx - 2) * 8), &er->ref);
+        else
+                atomic_dec(&er->ref);
+
+        reg1->alloc = 0;
+}
+
+static int nhmex_rbox_hw_config(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
+        struct hw_perf_event_extra *reg2 = &event->hw.branch_reg;
+        int idx;
+
+        idx = (event->hw.config & NHMEX_R_PMON_CTL_EV_SEL_MASK) >>
+                NHMEX_R_PMON_CTL_EV_SEL_SHIFT;
+        if (idx >= 0x18)
+                return -EINVAL;
+
+        reg1->idx = idx;
+        reg1->config = event->attr.config1;
+
+        switch (idx % 6) {
+        case 4:
+        case 5:
+                hwc->config |= event->attr.config & (~0ULL << 32);
+                reg2->config = event->attr.config2;
+                break;
+        };
+        return 0;
+}
+
+static u64 nhmex_rbox_shared_reg_config(struct intel_uncore_box *box, int idx)
+{
+        struct intel_uncore_extra_reg *er;
+        unsigned long flags;
+        u64 config;
+
+        er = &box->shared_regs[idx];
+
+        raw_spin_lock_irqsave(&er->lock, flags);
+        config = er->config;
+        raw_spin_unlock_irqrestore(&er->lock, flags);
+
+        return config;
+}
+
+static void nhmex_rbox_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
+        struct hw_perf_event_extra *reg2 = &hwc->branch_reg;
+        int idx, port;
+
+        idx = reg1->idx;
+        port = idx / 6 + box->pmu->pmu_idx * 4;
+
+        switch (idx % 6) {
+        case 0:
+                wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config);
+                break;
+        case 1:
+                wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config);
+                break;
+        case 2:
+        case 3:
+                wrmsrl(NHMEX_R_MSR_PORTN_QLX_CFG(port),
+                        nhmex_rbox_shared_reg_config(box, 2 + (idx / 6) * 5));
+                break;
+        case 4:
+                wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(port),
+                        hwc->config >> 32);
+                wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config);
+                wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config);
+                break;
+        case 5:
+                wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(port),
+                        hwc->config >> 32);
+                wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config);
+                wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config);
+                break;
+        };
+
+        wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0 |
+                (hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK));
+}
+
+DEFINE_UNCORE_FORMAT_ATTR(xbr_mm_cfg, xbr_mm_cfg, "config:32-63");
+DEFINE_UNCORE_FORMAT_ATTR(xbr_match, xbr_match, "config1:0-63");
+DEFINE_UNCORE_FORMAT_ATTR(xbr_mask, xbr_mask, "config2:0-63");
+DEFINE_UNCORE_FORMAT_ATTR(qlx_cfg, qlx_cfg, "config1:0-15");
+DEFINE_UNCORE_FORMAT_ATTR(iperf_cfg, iperf_cfg, "config1:0-31");
+
+static struct attribute *nhmex_uncore_rbox_formats_attr[] = {
+        &format_attr_event5.attr,
+        &format_attr_xbr_mm_cfg.attr,
+        &format_attr_xbr_match.attr,
+        &format_attr_xbr_mask.attr,
+        &format_attr_qlx_cfg.attr,
+        &format_attr_iperf_cfg.attr,
+        NULL,
+};
+
+static struct attribute_group nhmex_uncore_rbox_format_group = {
+        .name = "format",
+        .attrs = nhmex_uncore_rbox_formats_attr,
+};
+
+static struct uncore_event_desc nhmex_uncore_rbox_events[] = {
+        INTEL_UNCORE_EVENT_DESC(qpi0_flit_send,         "event=0x0,iperf_cfg=0x80000000"),
+        INTEL_UNCORE_EVENT_DESC(qpi1_filt_send,         "event=0x6,iperf_cfg=0x80000000"),
+        INTEL_UNCORE_EVENT_DESC(qpi0_idle_filt,         "event=0x0,iperf_cfg=0x40000000"),
+        INTEL_UNCORE_EVENT_DESC(qpi1_idle_filt,         "event=0x6,iperf_cfg=0x40000000"),
+        INTEL_UNCORE_EVENT_DESC(qpi0_date_response,     "event=0x0,iperf_cfg=0xc4"),
+        INTEL_UNCORE_EVENT_DESC(qpi1_date_response,     "event=0x6,iperf_cfg=0xc4"),
+        { /* end: all zeroes */ },
+};
+
+static struct intel_uncore_ops nhmex_uncore_rbox_ops = {
+        NHMEX_UNCORE_OPS_COMMON_INIT(),
+        .enable_event           = nhmex_rbox_msr_enable_event,
+        .hw_config              = nhmex_rbox_hw_config,
+        .get_constraint         = nhmex_rbox_get_constraint,
+        .put_constraint         = nhmex_rbox_put_constraint,
+};
+
+static struct intel_uncore_type nhmex_uncore_rbox = {
+        .name                   = "rbox",
+        .num_counters           = 8,
+        .num_boxes              = 2,
+        .perf_ctr_bits          = 48,
+        .event_ctl              = NHMEX_R_MSR_PMON_CTL0,
+        .perf_ctr               = NHMEX_R_MSR_PMON_CNT0,
+        .event_mask             = NHMEX_R_PMON_RAW_EVENT_MASK,
+        .box_ctl                = NHMEX_R_MSR_GLOBAL_CTL,
+        .msr_offset             = NHMEX_R_MSR_OFFSET,
+        .pair_ctr_ctl           = 1,
+        .num_shared_regs        = 20,
+        .event_descs            = nhmex_uncore_rbox_events,
+        .ops                    = &nhmex_uncore_rbox_ops,
+        .format_group           = &nhmex_uncore_rbox_format_group
+};
+
+static struct intel_uncore_type *nhmex_msr_uncores[] = {
+        &nhmex_uncore_ubox,
+        &nhmex_uncore_cbox,
+        &nhmex_uncore_bbox,
+        &nhmex_uncore_sbox,
+        &nhmex_uncore_mbox,
+        &nhmex_uncore_rbox,
+        &nhmex_uncore_wbox,
+        NULL,
+};
+/* end of Nehalem-EX uncore support */
+
+static void uncore_assign_hw_event(struct intel_uncore_box *box, struct perf_event *event, int idx)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        hwc->idx = idx;
+        hwc->last_tag = ++box->tags[idx];
+
+        if (hwc->idx == UNCORE_PMC_IDX_FIXED) {
+                hwc->event_base = uncore_fixed_ctr(box);
+                hwc->config_base = uncore_fixed_ctl(box);
+                return;
+        }
+
+        hwc->config_base = uncore_event_ctl(box, hwc->idx);
+        hwc->event_base  = uncore_perf_ctr(box, hwc->idx);
+}
+
+static void uncore_perf_event_update(struct intel_uncore_box *box, struct perf_event *event)
+{
+        u64 prev_count, new_count, delta;
+        int shift;
+
+        if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
+                shift = 64 - uncore_fixed_ctr_bits(box);
+        else
+                shift = 64 - uncore_perf_ctr_bits(box);
+
+        /* the hrtimer might modify the previous event value */
+again:
+        prev_count = local64_read(&event->hw.prev_count);
+        new_count = uncore_read_counter(box, event);
+        if (local64_xchg(&event->hw.prev_count, new_count) != prev_count)
+                goto again;
+
+        delta = (new_count << shift) - (prev_count << shift);
+        delta >>= shift;
+
+        local64_add(delta, &event->count);
+}
+
+/*
+ * The overflow interrupt is unavailable for SandyBridge-EP, is broken
+ * for SandyBridge. So we use hrtimer to periodically poll the counter
+ * to avoid overflow.
+ */
+static enum hrtimer_restart uncore_pmu_hrtimer(struct hrtimer *hrtimer)
+{
+        struct intel_uncore_box *box;
+        unsigned long flags;
+        int bit;
+
+        box = container_of(hrtimer, struct intel_uncore_box, hrtimer);
+        if (!box->n_active || box->cpu != smp_processor_id())
+                return HRTIMER_NORESTART;
+        /*
+         * disable local interrupt to prevent uncore_pmu_event_start/stop
+         * to interrupt the update process
+         */
+        local_irq_save(flags);
+
+        for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX)
+                uncore_perf_event_update(box, box->events[bit]);
+
+        local_irq_restore(flags);
+
+        hrtimer_forward_now(hrtimer, ns_to_ktime(UNCORE_PMU_HRTIMER_INTERVAL));
+        return HRTIMER_RESTART;
+}
+
+static void uncore_pmu_start_hrtimer(struct intel_uncore_box *box)
+{
+        __hrtimer_start_range_ns(&box->hrtimer,
+                        ns_to_ktime(UNCORE_PMU_HRTIMER_INTERVAL), 0,
+                        HRTIMER_MODE_REL_PINNED, 0);
+}
+
+static void uncore_pmu_cancel_hrtimer(struct intel_uncore_box *box)
+{
+        hrtimer_cancel(&box->hrtimer);
+}
+
+static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
+{
+        hrtimer_init(&box->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+        box->hrtimer.function = uncore_pmu_hrtimer;
+}
+
+struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type, int cpu)
+{
+        struct intel_uncore_box *box;
+        int i, size;
+
+        size = sizeof(*box) + type->num_shared_regs * sizeof(struct intel_uncore_extra_reg);
+
+        box = kmalloc_node(size, GFP_KERNEL | __GFP_ZERO, cpu_to_node(cpu));
+        if (!box)
+                return NULL;
+
+        for (i = 0; i < type->num_shared_regs; i++)
+                raw_spin_lock_init(&box->shared_regs[i].lock);
+
+        uncore_pmu_init_hrtimer(box);
+        atomic_set(&box->refcnt, 1);
+        box->cpu = -1;
+        box->phys_id = -1;
+
+        return box;
+}
+
+static struct intel_uncore_box *
+uncore_pmu_to_box(struct intel_uncore_pmu *pmu, int cpu)
+{
+        static struct intel_uncore_box *box;
+
+        box = *per_cpu_ptr(pmu->box, cpu);
+        if (box)
+                return box;
+
+        raw_spin_lock(&uncore_box_lock);
+        list_for_each_entry(box, &pmu->box_list, list) {
+                if (box->phys_id == topology_physical_package_id(cpu)) {
+                        atomic_inc(&box->refcnt);
+                        *per_cpu_ptr(pmu->box, cpu) = box;
+                        break;
+                }
+        }
+        raw_spin_unlock(&uncore_box_lock);
+
+        return *per_cpu_ptr(pmu->box, cpu);
+}
+
+static struct intel_uncore_pmu *uncore_event_to_pmu(struct perf_event *event)
+{
+        return container_of(event->pmu, struct intel_uncore_pmu, pmu);
+}
+
+static struct intel_uncore_box *uncore_event_to_box(struct perf_event *event)
+{
+        /*
+         * perf core schedules event on the basis of cpu, uncore events are
+         * collected by one of the cpus inside a physical package.
+         */
+        return uncore_pmu_to_box(uncore_event_to_pmu(event), smp_processor_id());
+}
+
+static int
+uncore_collect_events(struct intel_uncore_box *box, struct perf_event *leader, bool dogrp)
+{
+        struct perf_event *event;
+        int n, max_count;
+
+        max_count = box->pmu->type->num_counters;
+        if (box->pmu->type->fixed_ctl)
+                max_count++;
+
+        if (box->n_events >= max_count)
+                return -EINVAL;
+
+        n = box->n_events;
+        box->event_list[n] = leader;
+        n++;
+        if (!dogrp)
+                return n;
+
+        list_for_each_entry(event, &leader->sibling_list, group_entry) {
+                if (event->state <= PERF_EVENT_STATE_OFF)
+                        continue;
+
+                if (n >= max_count)
+                        return -EINVAL;
+
+                box->event_list[n] = event;
+                n++;
+        }
+        return n;
+}
+
+static struct event_constraint *
+uncore_get_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        struct intel_uncore_type *type = box->pmu->type;
+        struct event_constraint *c;
+
+        if (type->ops->get_constraint) {
+                c = type->ops->get_constraint(box, event);
+                if (c)
+                        return c;
+        }
+
+        if (event->hw.config == ~0ULL)
+                return &constraint_fixed;
+
+        if (type->constraints) {
+                for_each_event_constraint(c, type->constraints) {
+                        if ((event->hw.config & c->cmask) == c->code)
+                                return c;
+                }
+        }
+
+        return &type->unconstrainted;
+}
+
+static void uncore_put_event_constraint(struct intel_uncore_box *box, struct perf_event *event)
+{
+        if (box->pmu->type->ops->put_constraint)
+                box->pmu->type->ops->put_constraint(box, event);
+}
+
+static int uncore_assign_events(struct intel_uncore_box *box, int assign[], int n)
+{
+        unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
+        struct event_constraint *c, *constraints[UNCORE_PMC_IDX_MAX];
+        int i, wmin, wmax, ret = 0;
+        struct hw_perf_event *hwc;
+
+        bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
+
+        for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
+                c = uncore_get_event_constraint(box, box->event_list[i]);
+                constraints[i] = c;
+                wmin = min(wmin, c->weight);
+                wmax = max(wmax, c->weight);
+        }
+
+        /* fastpath, try to reuse previous register */
+        for (i = 0; i < n; i++) {
+                hwc = &box->event_list[i]->hw;
+                c = constraints[i];
+
+                /* never assigned */
+                if (hwc->idx == -1)
+                        break;
+
+                /* constraint still honored */
+                if (!test_bit(hwc->idx, c->idxmsk))
+                        break;
+
+                /* not already used */
+                if (test_bit(hwc->idx, used_mask))
+                        break;
+
+                __set_bit(hwc->idx, used_mask);
+                if (assign)
+                        assign[i] = hwc->idx;
+        }
+        /* slow path */
+        if (i != n)
+                ret = perf_assign_events(constraints, n, wmin, wmax, assign);
+
+        if (!assign || ret) {
+                for (i = 0; i < n; i++)
+                        uncore_put_event_constraint(box, box->event_list[i]);
+        }
+        return ret ? -EINVAL : 0;
+}
+
+static void uncore_pmu_event_start(struct perf_event *event, int flags)
+{
+        struct intel_uncore_box *box = uncore_event_to_box(event);
+        int idx = event->hw.idx;
+
+        if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
+                return;
+
+        if (WARN_ON_ONCE(idx == -1 || idx >= UNCORE_PMC_IDX_MAX))
+                return;
+
+        event->hw.state = 0;
+        box->events[idx] = event;
+        box->n_active++;
+        __set_bit(idx, box->active_mask);
+
+        local64_set(&event->hw.prev_count, uncore_read_counter(box, event));
+        uncore_enable_event(box, event);
+
+        if (box->n_active == 1) {
+                uncore_enable_box(box);
+                uncore_pmu_start_hrtimer(box);
+        }
+}
+
+static void uncore_pmu_event_stop(struct perf_event *event, int flags)
+{
+        struct intel_uncore_box *box = uncore_event_to_box(event);
+        struct hw_perf_event *hwc = &event->hw;
+
+        if (__test_and_clear_bit(hwc->idx, box->active_mask)) {
+                uncore_disable_event(box, event);
+                box->n_active--;
+                box->events[hwc->idx] = NULL;
+                WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
+                hwc->state |= PERF_HES_STOPPED;
+
+                if (box->n_active == 0) {
+                        uncore_disable_box(box);
+                        uncore_pmu_cancel_hrtimer(box);
+                }
+        }
+
+        if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
+                /*
+                 * Drain the remaining delta count out of a event
+                 * that we are disabling:
+                 */
+                uncore_perf_event_update(box, event);
+                hwc->state |= PERF_HES_UPTODATE;
+        }
+}
+
+static int uncore_pmu_event_add(struct perf_event *event, int flags)
+{
+        struct intel_uncore_box *box = uncore_event_to_box(event);
+        struct hw_perf_event *hwc = &event->hw;
+        int assign[UNCORE_PMC_IDX_MAX];
+        int i, n, ret;
+
+        if (!box)
+                return -ENODEV;
+
+        ret = n = uncore_collect_events(box, event, false);
+        if (ret < 0)
+                return ret;
+
+        hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+        if (!(flags & PERF_EF_START))
+                hwc->state |= PERF_HES_ARCH;
+
+        ret = uncore_assign_events(box, assign, n);
+        if (ret)
+                return ret;
+
+        /* save events moving to new counters */
+        for (i = 0; i < box->n_events; i++) {
+                event = box->event_list[i];
+                hwc = &event->hw;
+
+                if (hwc->idx == assign[i] &&
+                        hwc->last_tag == box->tags[assign[i]])
+                        continue;
+                /*
+                 * Ensure we don't accidentally enable a stopped
+                 * counter simply because we rescheduled.
+                 */
+                if (hwc->state & PERF_HES_STOPPED)
+                        hwc->state |= PERF_HES_ARCH;
+
+                uncore_pmu_event_stop(event, PERF_EF_UPDATE);
+        }
+
+        /* reprogram moved events into new counters */
+        for (i = 0; i < n; i++) {
+                event = box->event_list[i];
+                hwc = &event->hw;
+
+                if (hwc->idx != assign[i] ||
+                        hwc->last_tag != box->tags[assign[i]])
+                        uncore_assign_hw_event(box, event, assign[i]);
+                else if (i < box->n_events)
+                        continue;
+
+                if (hwc->state & PERF_HES_ARCH)
+                        continue;
+
+                uncore_pmu_event_start(event, 0);
+        }
+        box->n_events = n;
+
+        return 0;
+}
+
+static void uncore_pmu_event_del(struct perf_event *event, int flags)
+{
+        struct intel_uncore_box *box = uncore_event_to_box(event);
+        int i;
+
+        uncore_pmu_event_stop(event, PERF_EF_UPDATE);
+
+        for (i = 0; i < box->n_events; i++) {
+                if (event == box->event_list[i]) {
+                        uncore_put_event_constraint(box, event);
+
+                        while (++i < box->n_events)
+                                box->event_list[i - 1] = box->event_list[i];
+
+                        --box->n_events;
+                        break;
+                }
+        }
+
+        event->hw.idx = -1;
+        event->hw.last_tag = ~0ULL;
+}
+
+static void uncore_pmu_event_read(struct perf_event *event)
+{
+        struct intel_uncore_box *box = uncore_event_to_box(event);
+        uncore_perf_event_update(box, event);
+}
+
+/*
+ * validation ensures the group can be loaded onto the
+ * PMU if it was the only group available.
+ */
+static int uncore_validate_group(struct intel_uncore_pmu *pmu,
+                                struct perf_event *event)
+{
+        struct perf_event *leader = event->group_leader;
+        struct intel_uncore_box *fake_box;
+        int ret = -EINVAL, n;
+
+        fake_box = uncore_alloc_box(pmu->type, smp_processor_id());
+        if (!fake_box)
+                return -ENOMEM;
+
+        fake_box->pmu = pmu;
+        /*
+         * the event is not yet connected with its
+         * siblings therefore we must first collect
+         * existing siblings, then add the new event
+         * before we can simulate the scheduling
+         */
+        n = uncore_collect_events(fake_box, leader, true);
+        if (n < 0)
+                goto out;
+
+        fake_box->n_events = n;
+        n = uncore_collect_events(fake_box, event, false);
+        if (n < 0)
+                goto out;
+
+        fake_box->n_events = n;
+
+        ret = uncore_assign_events(fake_box, NULL, n);
+out:
+        kfree(fake_box);
+        return ret;
+}
+
+int uncore_pmu_event_init(struct perf_event *event)
+{
+        struct intel_uncore_pmu *pmu;
+        struct intel_uncore_box *box;
+        struct hw_perf_event *hwc = &event->hw;
+        int ret;
+
+        if (event->attr.type != event->pmu->type)
+                return -ENOENT;
+
+        pmu = uncore_event_to_pmu(event);
+        /* no device found for this pmu */
+        if (pmu->func_id < 0)
+                return -ENOENT;
+
+        /*
+         * Uncore PMU does measure at all privilege level all the time.
+         * So it doesn't make sense to specify any exclude bits.
+         */
+        if (event->attr.exclude_user || event->attr.exclude_kernel ||
+                        event->attr.exclude_hv || event->attr.exclude_idle)
+                return -EINVAL;
+
+        /* Sampling not supported yet */
+        if (hwc->sample_period)
+                return -EINVAL;
+
+        /*
+         * Place all uncore events for a particular physical package
+         * onto a single cpu
+         */
+        if (event->cpu < 0)
+                return -EINVAL;
+        box = uncore_pmu_to_box(pmu, event->cpu);
+        if (!box || box->cpu < 0)
+                return -EINVAL;
+        event->cpu = box->cpu;
+
+        event->hw.idx = -1;
+        event->hw.last_tag = ~0ULL;
+        event->hw.extra_reg.idx = EXTRA_REG_NONE;
+        event->hw.branch_reg.idx = EXTRA_REG_NONE;
+
+        if (event->attr.config == UNCORE_FIXED_EVENT) {
+                /* no fixed counter */
+                if (!pmu->type->fixed_ctl)
+                        return -EINVAL;
+                /*
+                 * if there is only one fixed counter, only the first pmu
+                 * can access the fixed counter
+                 */
+                if (pmu->type->single_fixed && pmu->pmu_idx > 0)
+                        return -EINVAL;
+                hwc->config = ~0ULL;
+        } else {
+                hwc->config = event->attr.config & pmu->type->event_mask;
+                if (pmu->type->ops->hw_config) {
+                        ret = pmu->type->ops->hw_config(box, event);
+                        if (ret)
+                                return ret;
+                }
+        }
+
+        if (event->group_leader != event)
+                ret = uncore_validate_group(pmu, event);
+        else
+                ret = 0;
+
+        return ret;
+}
+
+static int __init uncore_pmu_register(struct intel_uncore_pmu *pmu)
+{
+        int ret;
+
+        pmu->pmu = (struct pmu) {
+                .attr_groups    = pmu->type->attr_groups,
+                .task_ctx_nr    = perf_invalid_context,
+                .event_init     = uncore_pmu_event_init,
+                .add            = uncore_pmu_event_add,
+                .del            = uncore_pmu_event_del,
+                .start          = uncore_pmu_event_start,
+                .stop           = uncore_pmu_event_stop,
+                .read           = uncore_pmu_event_read,
+        };
+
+        if (pmu->type->num_boxes == 1) {
+                if (strlen(pmu->type->name) > 0)
+                        sprintf(pmu->name, "uncore_%s", pmu->type->name);
+                else
+                        sprintf(pmu->name, "uncore");
+        } else {
+                sprintf(pmu->name, "uncore_%s_%d", pmu->type->name,
+                        pmu->pmu_idx);
+        }
+
+        ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
+        return ret;
+}
+
+static void __init uncore_type_exit(struct intel_uncore_type *type)
+{
+        int i;
+
+        for (i = 0; i < type->num_boxes; i++)
+                free_percpu(type->pmus[i].box);
+        kfree(type->pmus);
+        type->pmus = NULL;
+        kfree(type->attr_groups[1]);
+        type->attr_groups[1] = NULL;
+}
+
+static void __init uncore_types_exit(struct intel_uncore_type **types)
+{
+        int i;
+        for (i = 0; types[i]; i++)
+                uncore_type_exit(types[i]);
+}
+
+static int __init uncore_type_init(struct intel_uncore_type *type)
+{
+        struct intel_uncore_pmu *pmus;
+        struct attribute_group *events_group;
+        struct attribute **attrs;
+        int i, j;
+
+        pmus = kzalloc(sizeof(*pmus) * type->num_boxes, GFP_KERNEL);
+        if (!pmus)
+                return -ENOMEM;
+
+        type->unconstrainted = (struct event_constraint)
+                __EVENT_CONSTRAINT(0, (1ULL << type->num_counters) - 1,
+                                0, type->num_counters, 0);
+
+        for (i = 0; i < type->num_boxes; i++) {
+                pmus[i].func_id = -1;
+                pmus[i].pmu_idx = i;
+                pmus[i].type = type;
+                INIT_LIST_HEAD(&pmus[i].box_list);
+                pmus[i].box = alloc_percpu(struct intel_uncore_box *);
+                if (!pmus[i].box)
+                        goto fail;
+        }
+
+        if (type->event_descs) {
+                i = 0;
+                while (type->event_descs[i].attr.attr.name)
+                        i++;
+
+                events_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
+                                        sizeof(*events_group), GFP_KERNEL);
+                if (!events_group)
+                        goto fail;
+
+                attrs = (struct attribute **)(events_group + 1);
+                events_group->name = "events";
+                events_group->attrs = attrs;
+
+                for (j = 0; j < i; j++)
+                        attrs[j] = &type->event_descs[j].attr.attr;
+
+                type->attr_groups[1] = events_group;
+        }
+
+        type->pmus = pmus;
+        return 0;
+fail:
+        uncore_type_exit(type);
+        return -ENOMEM;
+}
+
+static int __init uncore_types_init(struct intel_uncore_type **types)
+{
+        int i, ret;
+
+        for (i = 0; types[i]; i++) {
+                ret = uncore_type_init(types[i]);
+                if (ret)
+                        goto fail;
+        }
+        return 0;
+fail:
+        while (--i >= 0)
+                uncore_type_exit(types[i]);
+        return ret;
+}
+
+static struct pci_driver *uncore_pci_driver;
+static bool pcidrv_registered;
+
+/*
+ * add a pci uncore device
+ */
+static int __devinit uncore_pci_add(struct intel_uncore_type *type, struct pci_dev *pdev)
+{
+        struct intel_uncore_pmu *pmu;
+        struct intel_uncore_box *box;
+        int i, phys_id;
+
+        phys_id = pcibus_to_physid[pdev->bus->number];
+        if (phys_id < 0)
+                return -ENODEV;
+
+        box = uncore_alloc_box(type, 0);
+        if (!box)
+                return -ENOMEM;
+
+        /*
+         * for performance monitoring unit with multiple boxes,
+         * each box has a different function id.
+         */
+        for (i = 0; i < type->num_boxes; i++) {
+                pmu = &type->pmus[i];
+                if (pmu->func_id == pdev->devfn)
+                        break;
+                if (pmu->func_id < 0) {
+                        pmu->func_id = pdev->devfn;
+                        break;
+                }
+                pmu = NULL;
+        }
+
+        if (!pmu) {
+                kfree(box);
+                return -EINVAL;
+        }
+
+        box->phys_id = phys_id;
+        box->pci_dev = pdev;
+        box->pmu = pmu;
+        uncore_box_init(box);
+        pci_set_drvdata(pdev, box);
+
+        raw_spin_lock(&uncore_box_lock);
+        list_add_tail(&box->list, &pmu->box_list);
+        raw_spin_unlock(&uncore_box_lock);
+
+        return 0;
+}
+
+static void uncore_pci_remove(struct pci_dev *pdev)
+{
+        struct intel_uncore_box *box = pci_get_drvdata(pdev);
+        struct intel_uncore_pmu *pmu = box->pmu;
+        int cpu, phys_id = pcibus_to_physid[pdev->bus->number];
+
+        if (WARN_ON_ONCE(phys_id != box->phys_id))
+                return;
+
+        raw_spin_lock(&uncore_box_lock);
+        list_del(&box->list);
+        raw_spin_unlock(&uncore_box_lock);
+
+        for_each_possible_cpu(cpu) {
+                if (*per_cpu_ptr(pmu->box, cpu) == box) {
+                        *per_cpu_ptr(pmu->box, cpu) = NULL;
+                        atomic_dec(&box->refcnt);
+                }
+        }
+
+        WARN_ON_ONCE(atomic_read(&box->refcnt) != 1);
+        kfree(box);
+}
+
+static int __devinit uncore_pci_probe(struct pci_dev *pdev,
+                                const struct pci_device_id *id)
+{
+        struct intel_uncore_type *type;
+
+        type = (struct intel_uncore_type *)id->driver_data;
+
+        return uncore_pci_add(type, pdev);
+}
+
+static int __init uncore_pci_init(void)
+{
+        int ret;
+
+        switch (boot_cpu_data.x86_model) {
+        case 45: /* Sandy Bridge-EP */
+                pci_uncores = snbep_pci_uncores;
+                uncore_pci_driver = &snbep_uncore_pci_driver;
+                snbep_pci2phy_map_init();
+                break;
+        default:
+                return 0;
+        }
+
+        ret = uncore_types_init(pci_uncores);
+        if (ret)
+                return ret;
+
+        uncore_pci_driver->probe = uncore_pci_probe;
+        uncore_pci_driver->remove = uncore_pci_remove;
+
+        ret = pci_register_driver(uncore_pci_driver);
+        if (ret == 0)
+                pcidrv_registered = true;
+        else
+                uncore_types_exit(pci_uncores);
+
+        return ret;
+}
+
+static void __init uncore_pci_exit(void)
+{
+        if (pcidrv_registered) {
+                pcidrv_registered = false;
+                pci_unregister_driver(uncore_pci_driver);
+                uncore_types_exit(pci_uncores);
+        }
+}
+
+static void __cpuinit uncore_cpu_dying(int cpu)
+{
+        struct intel_uncore_type *type;
+        struct intel_uncore_pmu *pmu;
+        struct intel_uncore_box *box;
+        int i, j;
+
+        for (i = 0; msr_uncores[i]; i++) {
+                type = msr_uncores[i];
+                for (j = 0; j < type->num_boxes; j++) {
+                        pmu = &type->pmus[j];
+                        box = *per_cpu_ptr(pmu->box, cpu);
+                        *per_cpu_ptr(pmu->box, cpu) = NULL;
+                        if (box && atomic_dec_and_test(&box->refcnt))
+                                kfree(box);
+                }
+        }
+}
+
+static int __cpuinit uncore_cpu_starting(int cpu)
+{
+        struct intel_uncore_type *type;
+        struct intel_uncore_pmu *pmu;
+        struct intel_uncore_box *box, *exist;
+        int i, j, k, phys_id;
+
+        phys_id = topology_physical_package_id(cpu);
+
+        for (i = 0; msr_uncores[i]; i++) {
+                type = msr_uncores[i];
+                for (j = 0; j < type->num_boxes; j++) {
+                        pmu = &type->pmus[j];
+                        box = *per_cpu_ptr(pmu->box, cpu);
+                        /* called by uncore_cpu_init? */
+                        if (box && box->phys_id >= 0) {
+                                uncore_box_init(box);
+                                continue;
+                        }
+
+                        for_each_online_cpu(k) {
+                                exist = *per_cpu_ptr(pmu->box, k);
+                                if (exist && exist->phys_id == phys_id) {
+                                        atomic_inc(&exist->refcnt);
+                                        *per_cpu_ptr(pmu->box, cpu) = exist;
+                                        kfree(box);
+                                        box = NULL;
+                                        break;
+                                }
+                        }
+
+                        if (box) {
+                                box->phys_id = phys_id;
+                                uncore_box_init(box);
+                        }
+                }
+        }
+        return 0;
+}
+
+static int __cpuinit uncore_cpu_prepare(int cpu, int phys_id)
+{
+        struct intel_uncore_type *type;
+        struct intel_uncore_pmu *pmu;
+        struct intel_uncore_box *box;
+        int i, j;
+
+        for (i = 0; msr_uncores[i]; i++) {
+                type = msr_uncores[i];
+                for (j = 0; j < type->num_boxes; j++) {
+                        pmu = &type->pmus[j];
+                        if (pmu->func_id < 0)
+                                pmu->func_id = j;
+
+                        box = uncore_alloc_box(type, cpu);
+                        if (!box)
+                                return -ENOMEM;
+
+                        box->pmu = pmu;
+                        box->phys_id = phys_id;
+                        *per_cpu_ptr(pmu->box, cpu) = box;
+                }
+        }
+        return 0;
+}
+
+static void __cpuinit
+uncore_change_context(struct intel_uncore_type **uncores, int old_cpu, int new_cpu)
+{
+        struct intel_uncore_type *type;
+        struct intel_uncore_pmu *pmu;
+        struct intel_uncore_box *box;
+        int i, j;
+
+        for (i = 0; uncores[i]; i++) {
+                type = uncores[i];
+                for (j = 0; j < type->num_boxes; j++) {
+                        pmu = &type->pmus[j];
+                        if (old_cpu < 0)
+                                box = uncore_pmu_to_box(pmu, new_cpu);
+                        else
+                                box = uncore_pmu_to_box(pmu, old_cpu);
+                        if (!box)
+                                continue;
+
+                        if (old_cpu < 0) {
+                                WARN_ON_ONCE(box->cpu != -1);
+                                box->cpu = new_cpu;
+                                continue;
+                        }
+
+                        WARN_ON_ONCE(box->cpu != old_cpu);
+                        if (new_cpu >= 0) {
+                                uncore_pmu_cancel_hrtimer(box);
+                                perf_pmu_migrate_context(&pmu->pmu,
+                                                old_cpu, new_cpu);
+                                box->cpu = new_cpu;
+                        } else {
+                                box->cpu = -1;
+                        }
+                }
+        }
+}
+
+static void __cpuinit uncore_event_exit_cpu(int cpu)
+{
+        int i, phys_id, target;
+
+        /* if exiting cpu is used for collecting uncore events */
+        if (!cpumask_test_and_clear_cpu(cpu, &uncore_cpu_mask))
+                return;
+
+        /* find a new cpu to collect uncore events */
+        phys_id = topology_physical_package_id(cpu);
+        target = -1;
+        for_each_online_cpu(i) {
+                if (i == cpu)
+                        continue;
+                if (phys_id == topology_physical_package_id(i)) {
+                        target = i;
+                        break;
+                }
+        }
+
+        /* migrate uncore events to the new cpu */
+        if (target >= 0)
+                cpumask_set_cpu(target, &uncore_cpu_mask);
+
+        uncore_change_context(msr_uncores, cpu, target);
+        uncore_change_context(pci_uncores, cpu, target);
+}
+
+static void __cpuinit uncore_event_init_cpu(int cpu)
+{
+        int i, phys_id;
+
+        phys_id = topology_physical_package_id(cpu);
+        for_each_cpu(i, &uncore_cpu_mask) {
+                if (phys_id == topology_physical_package_id(i))
+                        return;
+        }
+
+        cpumask_set_cpu(cpu, &uncore_cpu_mask);
+
+        uncore_change_context(msr_uncores, -1, cpu);
+        uncore_change_context(pci_uncores, -1, cpu);
+}
+
+static int
+ __cpuinit uncore_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (long)hcpu;
+
+        /* allocate/free data structure for uncore box */
+        switch (action & ~CPU_TASKS_FROZEN) {
+        case CPU_UP_PREPARE:
+                uncore_cpu_prepare(cpu, -1);
+                break;
+        case CPU_STARTING:
+                uncore_cpu_starting(cpu);
+                break;
+        case CPU_UP_CANCELED:
+        case CPU_DYING:
+                uncore_cpu_dying(cpu);
+                break;
+        default:
+                break;
+        }
+
+        /* select the cpu that collects uncore events */
+        switch (action & ~CPU_TASKS_FROZEN) {
+        case CPU_DOWN_FAILED:
+        case CPU_STARTING:
+                uncore_event_init_cpu(cpu);
+                break;
+        case CPU_DOWN_PREPARE:
+                uncore_event_exit_cpu(cpu);
+                break;
+        default:
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block uncore_cpu_nb __cpuinitdata = {
+        .notifier_call  = uncore_cpu_notifier,
+        /*
+         * to migrate uncore events, our notifier should be executed
+         * before perf core's notifier.
+         */
+        .priority       = CPU_PRI_PERF + 1,
+};
+
+static void __init uncore_cpu_setup(void *dummy)
+{
+        uncore_cpu_starting(smp_processor_id());
+}
+
+static int __init uncore_cpu_init(void)
+{
+        int ret, cpu, max_cores;
+
+        max_cores = boot_cpu_data.x86_max_cores;
+        switch (boot_cpu_data.x86_model) {
+        case 26: /* Nehalem */
+        case 30:
+        case 37: /* Westmere */
+        case 44:
+                msr_uncores = nhm_msr_uncores;
+                break;
+        case 42: /* Sandy Bridge */
+                if (snb_uncore_cbox.num_boxes > max_cores)
+                        snb_uncore_cbox.num_boxes = max_cores;
+                msr_uncores = snb_msr_uncores;
+                break;
+        case 45: /* Sandy Birdge-EP */
+                if (snbep_uncore_cbox.num_boxes > max_cores)
+                        snbep_uncore_cbox.num_boxes = max_cores;
+                msr_uncores = snbep_msr_uncores;
+                break;
+        case 46: /* Nehalem-EX */
+                uncore_nhmex = true;
+        case 47: /* Westmere-EX aka. Xeon E7 */
+                if (!uncore_nhmex)
+                        nhmex_uncore_mbox.event_descs = wsmex_uncore_mbox_events;
+                if (nhmex_uncore_cbox.num_boxes > max_cores)
+                        nhmex_uncore_cbox.num_boxes = max_cores;
+                msr_uncores = nhmex_msr_uncores;
+                break;
+        default:
+                return 0;
+        }
+
+        ret = uncore_types_init(msr_uncores);
+        if (ret)
+                return ret;
+
+        get_online_cpus();
+
+        for_each_online_cpu(cpu) {
+                int i, phys_id = topology_physical_package_id(cpu);
+
+                for_each_cpu(i, &uncore_cpu_mask) {
+                        if (phys_id == topology_physical_package_id(i)) {
+                                phys_id = -1;
+                                break;
+                        }
+                }
+                if (phys_id < 0)
+                        continue;
+
+                uncore_cpu_prepare(cpu, phys_id);
+                uncore_event_init_cpu(cpu);
+        }
+        on_each_cpu(uncore_cpu_setup, NULL, 1);
+
+        register_cpu_notifier(&uncore_cpu_nb);
+
+        put_online_cpus();
+
+        return 0;
+}
+
+static int __init uncore_pmus_register(void)
+{
+        struct intel_uncore_pmu *pmu;
+        struct intel_uncore_type *type;
+        int i, j;
+
+        for (i = 0; msr_uncores[i]; i++) {
+                type = msr_uncores[i];
+                for (j = 0; j < type->num_boxes; j++) {
+                        pmu = &type->pmus[j];
+                        uncore_pmu_register(pmu);
+                }
+        }
+
+        for (i = 0; pci_uncores[i]; i++) {
+                type = pci_uncores[i];
+                for (j = 0; j < type->num_boxes; j++) {
+                        pmu = &type->pmus[j];
+                        uncore_pmu_register(pmu);
+                }
+        }
+
+        return 0;
+}
+
+static int __init intel_uncore_init(void)
+{
+        int ret;
+
+        if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
+                return -ENODEV;
+
+        ret = uncore_pci_init();
+        if (ret)
+                goto fail;
+        ret = uncore_cpu_init();
+        if (ret) {
+                uncore_pci_exit();
+                goto fail;
+        }
+
+        uncore_pmus_register();
+        return 0;
+fail:
+        return ret;
+}
+device_initcall(intel_uncore_init);
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.h b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
new file mode 100644
index 00000000000..5b81c1856aa
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.h
@@ -0,0 +1,619 @@
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/perf_event.h>
+#include "perf_event.h"
+
+#define UNCORE_PMU_NAME_LEN             32
+#define UNCORE_PMU_HRTIMER_INTERVAL     (60LL * NSEC_PER_SEC)
+
+#define UNCORE_FIXED_EVENT              0xff
+#define UNCORE_PMC_IDX_MAX_GENERIC      8
+#define UNCORE_PMC_IDX_FIXED            UNCORE_PMC_IDX_MAX_GENERIC
+#define UNCORE_PMC_IDX_MAX              (UNCORE_PMC_IDX_FIXED + 1)
+
+#define UNCORE_EVENT_CONSTRAINT(c, n) EVENT_CONSTRAINT(c, n, 0xff)
+
+/* SNB event control */
+#define SNB_UNC_CTL_EV_SEL_MASK                 0x000000ff
+#define SNB_UNC_CTL_UMASK_MASK                  0x0000ff00
+#define SNB_UNC_CTL_EDGE_DET                    (1 << 18)
+#define SNB_UNC_CTL_EN                          (1 << 22)
+#define SNB_UNC_CTL_INVERT                      (1 << 23)
+#define SNB_UNC_CTL_CMASK_MASK                  0x1f000000
+#define NHM_UNC_CTL_CMASK_MASK                  0xff000000
+#define NHM_UNC_FIXED_CTR_CTL_EN                (1 << 0)
+
+#define SNB_UNC_RAW_EVENT_MASK                  (SNB_UNC_CTL_EV_SEL_MASK | \
+                                                 SNB_UNC_CTL_UMASK_MASK | \
+                                                 SNB_UNC_CTL_EDGE_DET | \
+                                                 SNB_UNC_CTL_INVERT | \
+                                                 SNB_UNC_CTL_CMASK_MASK)
+
+#define NHM_UNC_RAW_EVENT_MASK                  (SNB_UNC_CTL_EV_SEL_MASK | \
+                                                 SNB_UNC_CTL_UMASK_MASK | \
+                                                 SNB_UNC_CTL_EDGE_DET | \
+                                                 SNB_UNC_CTL_INVERT | \
+                                                 NHM_UNC_CTL_CMASK_MASK)
+
+/* SNB global control register */
+#define SNB_UNC_PERF_GLOBAL_CTL                 0x391
+#define SNB_UNC_FIXED_CTR_CTRL                  0x394
+#define SNB_UNC_FIXED_CTR                       0x395
+
+/* SNB uncore global control */
+#define SNB_UNC_GLOBAL_CTL_CORE_ALL             ((1 << 4) - 1)
+#define SNB_UNC_GLOBAL_CTL_EN                   (1 << 29)
+
+/* SNB Cbo register */
+#define SNB_UNC_CBO_0_PERFEVTSEL0               0x700
+#define SNB_UNC_CBO_0_PER_CTR0                  0x706
+#define SNB_UNC_CBO_MSR_OFFSET                  0x10
+
+/* NHM global control register */
+#define NHM_UNC_PERF_GLOBAL_CTL                 0x391
+#define NHM_UNC_FIXED_CTR                       0x394
+#define NHM_UNC_FIXED_CTR_CTRL                  0x395
+
+/* NHM uncore global control */
+#define NHM_UNC_GLOBAL_CTL_EN_PC_ALL            ((1ULL << 8) - 1)
+#define NHM_UNC_GLOBAL_CTL_EN_FC                (1ULL << 32)
+
+/* NHM uncore register */
+#define NHM_UNC_PERFEVTSEL0                     0x3c0
+#define NHM_UNC_UNCORE_PMC0                     0x3b0
+
+/* SNB-EP Box level control */
+#define SNBEP_PMON_BOX_CTL_RST_CTRL     (1 << 0)
+#define SNBEP_PMON_BOX_CTL_RST_CTRS     (1 << 1)
+#define SNBEP_PMON_BOX_CTL_FRZ          (1 << 8)
+#define SNBEP_PMON_BOX_CTL_FRZ_EN       (1 << 16)
+#define SNBEP_PMON_BOX_CTL_INT          (SNBEP_PMON_BOX_CTL_RST_CTRL | \
+                                         SNBEP_PMON_BOX_CTL_RST_CTRS | \
+                                         SNBEP_PMON_BOX_CTL_FRZ_EN)
+/* SNB-EP event control */
+#define SNBEP_PMON_CTL_EV_SEL_MASK      0x000000ff
+#define SNBEP_PMON_CTL_UMASK_MASK       0x0000ff00
+#define SNBEP_PMON_CTL_RST              (1 << 17)
+#define SNBEP_PMON_CTL_EDGE_DET         (1 << 18)
+#define SNBEP_PMON_CTL_EV_SEL_EXT       (1 << 21)       /* only for QPI */
+#define SNBEP_PMON_CTL_EN               (1 << 22)
+#define SNBEP_PMON_CTL_INVERT           (1 << 23)
+#define SNBEP_PMON_CTL_TRESH_MASK       0xff000000
+#define SNBEP_PMON_RAW_EVENT_MASK       (SNBEP_PMON_CTL_EV_SEL_MASK | \
+                                         SNBEP_PMON_CTL_UMASK_MASK | \
+                                         SNBEP_PMON_CTL_EDGE_DET | \
+                                         SNBEP_PMON_CTL_INVERT | \
+                                         SNBEP_PMON_CTL_TRESH_MASK)
+
+/* SNB-EP Ubox event control */
+#define SNBEP_U_MSR_PMON_CTL_TRESH_MASK         0x1f000000
+#define SNBEP_U_MSR_PMON_RAW_EVENT_MASK         \
+                                (SNBEP_PMON_CTL_EV_SEL_MASK | \
+                                 SNBEP_PMON_CTL_UMASK_MASK | \
+                                 SNBEP_PMON_CTL_EDGE_DET | \
+                                 SNBEP_PMON_CTL_INVERT | \
+                                 SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
+
+#define SNBEP_CBO_PMON_CTL_TID_EN               (1 << 19)
+#define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK       (SNBEP_PMON_RAW_EVENT_MASK | \
+                                                 SNBEP_CBO_PMON_CTL_TID_EN)
+
+/* SNB-EP PCU event control */
+#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK     0x0000c000
+#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK       0x1f000000
+#define SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT       (1 << 30)
+#define SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET     (1 << 31)
+#define SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK       \
+                                (SNBEP_PMON_CTL_EV_SEL_MASK | \
+                                 SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK | \
+                                 SNBEP_PMON_CTL_EDGE_DET | \
+                                 SNBEP_PMON_CTL_INVERT | \
+                                 SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK | \
+                                 SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
+                                 SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
+
+#define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK       \
+                                (SNBEP_PMON_RAW_EVENT_MASK | \
+                                 SNBEP_PMON_CTL_EV_SEL_EXT)
+
+/* SNB-EP pci control register */
+#define SNBEP_PCI_PMON_BOX_CTL                  0xf4
+#define SNBEP_PCI_PMON_CTL0                     0xd8
+/* SNB-EP pci counter register */
+#define SNBEP_PCI_PMON_CTR0                     0xa0
+
+/* SNB-EP home agent register */
+#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH0        0x40
+#define SNBEP_HA_PCI_PMON_BOX_ADDRMATCH1        0x44
+#define SNBEP_HA_PCI_PMON_BOX_OPCODEMATCH       0x48
+/* SNB-EP memory controller register */
+#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTL         0xf0
+#define SNBEP_MC_CHy_PCI_PMON_FIXED_CTR         0xd0
+/* SNB-EP QPI register */
+#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH0          0x228
+#define SNBEP_Q_Py_PCI_PMON_PKT_MATCH1          0x22c
+#define SNBEP_Q_Py_PCI_PMON_PKT_MASK0           0x238
+#define SNBEP_Q_Py_PCI_PMON_PKT_MASK1           0x23c
+
+/* SNB-EP Ubox register */
+#define SNBEP_U_MSR_PMON_CTR0                   0xc16
+#define SNBEP_U_MSR_PMON_CTL0                   0xc10
+
+#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTL         0xc08
+#define SNBEP_U_MSR_PMON_UCLK_FIXED_CTR         0xc09
+
+/* SNB-EP Cbo register */
+#define SNBEP_C0_MSR_PMON_CTR0                  0xd16
+#define SNBEP_C0_MSR_PMON_CTL0                  0xd10
+#define SNBEP_C0_MSR_PMON_BOX_CTL               0xd04
+#define SNBEP_C0_MSR_PMON_BOX_FILTER            0xd14
+#define SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK      0xfffffc1f
+#define SNBEP_CBO_MSR_OFFSET                    0x20
+
+/* SNB-EP PCU register */
+#define SNBEP_PCU_MSR_PMON_CTR0                 0xc36
+#define SNBEP_PCU_MSR_PMON_CTL0                 0xc30
+#define SNBEP_PCU_MSR_PMON_BOX_CTL              0xc24
+#define SNBEP_PCU_MSR_PMON_BOX_FILTER           0xc34
+#define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK      0xffffffff
+#define SNBEP_PCU_MSR_CORE_C3_CTR               0x3fc
+#define SNBEP_PCU_MSR_CORE_C6_CTR               0x3fd
+
+/* NHM-EX event control */
+#define NHMEX_PMON_CTL_EV_SEL_MASK      0x000000ff
+#define NHMEX_PMON_CTL_UMASK_MASK       0x0000ff00
+#define NHMEX_PMON_CTL_EN_BIT0          (1 << 0)
+#define NHMEX_PMON_CTL_EDGE_DET         (1 << 18)
+#define NHMEX_PMON_CTL_PMI_EN           (1 << 20)
+#define NHMEX_PMON_CTL_EN_BIT22         (1 << 22)
+#define NHMEX_PMON_CTL_INVERT           (1 << 23)
+#define NHMEX_PMON_CTL_TRESH_MASK       0xff000000
+#define NHMEX_PMON_RAW_EVENT_MASK       (NHMEX_PMON_CTL_EV_SEL_MASK | \
+                                         NHMEX_PMON_CTL_UMASK_MASK | \
+                                         NHMEX_PMON_CTL_EDGE_DET | \
+                                         NHMEX_PMON_CTL_INVERT | \
+                                         NHMEX_PMON_CTL_TRESH_MASK)
+
+/* NHM-EX Ubox */
+#define NHMEX_U_MSR_PMON_GLOBAL_CTL             0xc00
+#define NHMEX_U_MSR_PMON_CTR                    0xc11
+#define NHMEX_U_MSR_PMON_EV_SEL                 0xc10
+
+#define NHMEX_U_PMON_GLOBAL_EN                  (1 << 0)
+#define NHMEX_U_PMON_GLOBAL_PMI_CORE_SEL        0x0000001e
+#define NHMEX_U_PMON_GLOBAL_EN_ALL              (1 << 28)
+#define NHMEX_U_PMON_GLOBAL_RST_ALL             (1 << 29)
+#define NHMEX_U_PMON_GLOBAL_FRZ_ALL             (1 << 31)
+
+#define NHMEX_U_PMON_RAW_EVENT_MASK             \
+                (NHMEX_PMON_CTL_EV_SEL_MASK |   \
+                 NHMEX_PMON_CTL_EDGE_DET)
+
+/* NHM-EX Cbox */
+#define NHMEX_C0_MSR_PMON_GLOBAL_CTL            0xd00
+#define NHMEX_C0_MSR_PMON_CTR0                  0xd11
+#define NHMEX_C0_MSR_PMON_EV_SEL0               0xd10
+#define NHMEX_C_MSR_OFFSET                      0x20
+
+/* NHM-EX Bbox */
+#define NHMEX_B0_MSR_PMON_GLOBAL_CTL            0xc20
+#define NHMEX_B0_MSR_PMON_CTR0                  0xc31
+#define NHMEX_B0_MSR_PMON_CTL0                  0xc30
+#define NHMEX_B_MSR_OFFSET                      0x40
+#define NHMEX_B0_MSR_MATCH                      0xe45
+#define NHMEX_B0_MSR_MASK                       0xe46
+#define NHMEX_B1_MSR_MATCH                      0xe4d
+#define NHMEX_B1_MSR_MASK                       0xe4e
+
+#define NHMEX_B_PMON_CTL_EN                     (1 << 0)
+#define NHMEX_B_PMON_CTL_EV_SEL_SHIFT           1
+#define NHMEX_B_PMON_CTL_EV_SEL_MASK            \
+                (0x1f << NHMEX_B_PMON_CTL_EV_SEL_SHIFT)
+#define NHMEX_B_PMON_CTR_SHIFT          6
+#define NHMEX_B_PMON_CTR_MASK           \
+                (0x3 << NHMEX_B_PMON_CTR_SHIFT)
+#define NHMEX_B_PMON_RAW_EVENT_MASK             \
+                (NHMEX_B_PMON_CTL_EV_SEL_MASK | \
+                 NHMEX_B_PMON_CTR_MASK)
+
+/* NHM-EX Sbox */
+#define NHMEX_S0_MSR_PMON_GLOBAL_CTL            0xc40
+#define NHMEX_S0_MSR_PMON_CTR0                  0xc51
+#define NHMEX_S0_MSR_PMON_CTL0                  0xc50
+#define NHMEX_S_MSR_OFFSET                      0x80
+#define NHMEX_S0_MSR_MM_CFG                     0xe48
+#define NHMEX_S0_MSR_MATCH                      0xe49
+#define NHMEX_S0_MSR_MASK                       0xe4a
+#define NHMEX_S1_MSR_MM_CFG                     0xe58
+#define NHMEX_S1_MSR_MATCH                      0xe59
+#define NHMEX_S1_MSR_MASK                       0xe5a
+
+#define NHMEX_S_PMON_MM_CFG_EN                  (0x1ULL << 63)
+#define NHMEX_S_EVENT_TO_R_PROG_EV              0
+
+/* NHM-EX Mbox */
+#define NHMEX_M0_MSR_GLOBAL_CTL                 0xca0
+#define NHMEX_M0_MSR_PMU_DSP                    0xca5
+#define NHMEX_M0_MSR_PMU_ISS                    0xca6
+#define NHMEX_M0_MSR_PMU_MAP                    0xca7
+#define NHMEX_M0_MSR_PMU_MSC_THR                0xca8
+#define NHMEX_M0_MSR_PMU_PGT                    0xca9
+#define NHMEX_M0_MSR_PMU_PLD                    0xcaa
+#define NHMEX_M0_MSR_PMU_ZDP_CTL_FVC            0xcab
+#define NHMEX_M0_MSR_PMU_CTL0                   0xcb0
+#define NHMEX_M0_MSR_PMU_CNT0                   0xcb1
+#define NHMEX_M_MSR_OFFSET                      0x40
+#define NHMEX_M0_MSR_PMU_MM_CFG                 0xe54
+#define NHMEX_M1_MSR_PMU_MM_CFG                 0xe5c
+
+#define NHMEX_M_PMON_MM_CFG_EN                  (1ULL << 63)
+#define NHMEX_M_PMON_ADDR_MATCH_MASK            0x3ffffffffULL
+#define NHMEX_M_PMON_ADDR_MASK_MASK             0x7ffffffULL
+#define NHMEX_M_PMON_ADDR_MASK_SHIFT            34
+
+#define NHMEX_M_PMON_CTL_EN                     (1 << 0)
+#define NHMEX_M_PMON_CTL_PMI_EN                 (1 << 1)
+#define NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT       2
+#define NHMEX_M_PMON_CTL_COUNT_MODE_MASK        \
+        (0x3 << NHMEX_M_PMON_CTL_COUNT_MODE_SHIFT)
+#define NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT     4
+#define NHMEX_M_PMON_CTL_STORAGE_MODE_MASK      \
+        (0x3 << NHMEX_M_PMON_CTL_STORAGE_MODE_SHIFT)
+#define NHMEX_M_PMON_CTL_WRAP_MODE              (1 << 6)
+#define NHMEX_M_PMON_CTL_FLAG_MODE              (1 << 7)
+#define NHMEX_M_PMON_CTL_INC_SEL_SHIFT          9
+#define NHMEX_M_PMON_CTL_INC_SEL_MASK           \
+        (0x1f << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
+#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT     19
+#define NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK      \
+        (0x7 << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT)
+#define NHMEX_M_PMON_RAW_EVENT_MASK                     \
+                (NHMEX_M_PMON_CTL_COUNT_MODE_MASK |     \
+                 NHMEX_M_PMON_CTL_STORAGE_MODE_MASK |   \
+                 NHMEX_M_PMON_CTL_WRAP_MODE |           \
+                 NHMEX_M_PMON_CTL_FLAG_MODE |           \
+                 NHMEX_M_PMON_CTL_INC_SEL_MASK |        \
+                 NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK)
+
+#define NHMEX_M_PMON_ZDP_CTL_FVC_MASK           (((1 << 11) - 1) | (1 << 23))
+#define NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)  (0x7 << (11 + 3 * (n)))
+
+#define WSMEX_M_PMON_ZDP_CTL_FVC_MASK           (((1 << 12) - 1) | (1 << 24))
+#define WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(n)  (0x7 << (12 + 3 * (n)))
+
+/*
+ * use the 9~13 bits to select event If the 7th bit is not set,
+ * otherwise use the 19~21 bits to select event.
+ */
+#define MBOX_INC_SEL(x) ((x) << NHMEX_M_PMON_CTL_INC_SEL_SHIFT)
+#define MBOX_SET_FLAG_SEL(x) (((x) << NHMEX_M_PMON_CTL_SET_FLAG_SEL_SHIFT) | \
+                                NHMEX_M_PMON_CTL_FLAG_MODE)
+#define MBOX_INC_SEL_MASK (NHMEX_M_PMON_CTL_INC_SEL_MASK | \
+                           NHMEX_M_PMON_CTL_FLAG_MODE)
+#define MBOX_SET_FLAG_SEL_MASK (NHMEX_M_PMON_CTL_SET_FLAG_SEL_MASK | \
+                                NHMEX_M_PMON_CTL_FLAG_MODE)
+#define MBOX_INC_SEL_EXTAR_REG(c, r) \
+                EVENT_EXTRA_REG(MBOX_INC_SEL(c), NHMEX_M0_MSR_PMU_##r, \
+                                MBOX_INC_SEL_MASK, (u64)-1, NHMEX_M_##r)
+#define MBOX_SET_FLAG_SEL_EXTRA_REG(c, r) \
+                EVENT_EXTRA_REG(MBOX_SET_FLAG_SEL(c), NHMEX_M0_MSR_PMU_##r, \
+                                MBOX_SET_FLAG_SEL_MASK, \
+                                (u64)-1, NHMEX_M_##r)
+
+/* NHM-EX Rbox */
+#define NHMEX_R_MSR_GLOBAL_CTL                  0xe00
+#define NHMEX_R_MSR_PMON_CTL0                   0xe10
+#define NHMEX_R_MSR_PMON_CNT0                   0xe11
+#define NHMEX_R_MSR_OFFSET                      0x20
+
+#define NHMEX_R_MSR_PORTN_QLX_CFG(n)            \
+                ((n) < 4 ? (0xe0c + (n)) : (0xe2c + (n) - 4))
+#define NHMEX_R_MSR_PORTN_IPERF_CFG0(n)         (0xe04 + (n))
+#define NHMEX_R_MSR_PORTN_IPERF_CFG1(n)         (0xe24 + (n))
+#define NHMEX_R_MSR_PORTN_XBR_OFFSET(n)         \
+                (((n) < 4 ? 0 : 0x10) + (n) * 4)
+#define NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n)    \
+                (0xe60 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
+#define NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(n)     \
+                (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 1)
+#define NHMEX_R_MSR_PORTN_XBR_SET1_MASK(n)      \
+                (NHMEX_R_MSR_PORTN_XBR_SET1_MM_CFG(n) + 2)
+#define NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n)    \
+                (0xe70 + NHMEX_R_MSR_PORTN_XBR_OFFSET(n))
+#define NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(n)     \
+                (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 1)
+#define NHMEX_R_MSR_PORTN_XBR_SET2_MASK(n)      \
+                (NHMEX_R_MSR_PORTN_XBR_SET2_MM_CFG(n) + 2)
+
+#define NHMEX_R_PMON_CTL_EN                     (1 << 0)
+#define NHMEX_R_PMON_CTL_EV_SEL_SHIFT           1
+#define NHMEX_R_PMON_CTL_EV_SEL_MASK            \
+                (0x1f << NHMEX_R_PMON_CTL_EV_SEL_SHIFT)
+#define NHMEX_R_PMON_CTL_PMI_EN                 (1 << 6)
+#define NHMEX_R_PMON_RAW_EVENT_MASK             NHMEX_R_PMON_CTL_EV_SEL_MASK
+
+/* NHM-EX Wbox */
+#define NHMEX_W_MSR_GLOBAL_CTL                  0xc80
+#define NHMEX_W_MSR_PMON_CNT0                   0xc90
+#define NHMEX_W_MSR_PMON_EVT_SEL0               0xc91
+#define NHMEX_W_MSR_PMON_FIXED_CTR              0x394
+#define NHMEX_W_MSR_PMON_FIXED_CTL              0x395
+
+#define NHMEX_W_PMON_GLOBAL_FIXED_EN            (1ULL << 31)
+
+struct intel_uncore_ops;
+struct intel_uncore_pmu;
+struct intel_uncore_box;
+struct uncore_event_desc;
+
+struct intel_uncore_type {
+        const char *name;
+        int num_counters;
+        int num_boxes;
+        int perf_ctr_bits;
+        int fixed_ctr_bits;
+        unsigned perf_ctr;
+        unsigned event_ctl;
+        unsigned event_mask;
+        unsigned fixed_ctr;
+        unsigned fixed_ctl;
+        unsigned box_ctl;
+        unsigned msr_offset;
+        unsigned num_shared_regs:8;
+        unsigned single_fixed:1;
+        unsigned pair_ctr_ctl:1;
+        unsigned *msr_offsets;
+        struct event_constraint unconstrainted;
+        struct event_constraint *constraints;
+        struct intel_uncore_pmu *pmus;
+        struct intel_uncore_ops *ops;
+        struct uncore_event_desc *event_descs;
+        const struct attribute_group *attr_groups[3];
+};
+
+#define format_group attr_groups[0]
+
+struct intel_uncore_ops {
+        void (*init_box)(struct intel_uncore_box *);
+        void (*disable_box)(struct intel_uncore_box *);
+        void (*enable_box)(struct intel_uncore_box *);
+        void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
+        void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
+        u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
+        int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
+        struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
+                                                   struct perf_event *);
+        void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
+};
+
+struct intel_uncore_pmu {
+        struct pmu pmu;
+        char name[UNCORE_PMU_NAME_LEN];
+        int pmu_idx;
+        int func_id;
+        struct intel_uncore_type *type;
+        struct intel_uncore_box ** __percpu box;
+        struct list_head box_list;
+};
+
+struct intel_uncore_extra_reg {
+        raw_spinlock_t lock;
+        u64 config, config1, config2;
+        atomic_t ref;
+};
+
+struct intel_uncore_box {
+        int phys_id;
+        int n_active;   /* number of active events */
+        int n_events;
+        int cpu;        /* cpu to collect events */
+        unsigned long flags;
+        atomic_t refcnt;
+        struct perf_event *events[UNCORE_PMC_IDX_MAX];
+        struct perf_event *event_list[UNCORE_PMC_IDX_MAX];
+        unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
+        u64 tags[UNCORE_PMC_IDX_MAX];
+        struct pci_dev *pci_dev;
+        struct intel_uncore_pmu *pmu;
+        struct hrtimer hrtimer;
+        struct list_head list;
+        struct intel_uncore_extra_reg shared_regs[0];
+};
+
+#define UNCORE_BOX_FLAG_INITIATED       0
+
+struct uncore_event_desc {
+        struct kobj_attribute attr;
+        const char *config;
+};
+
+#define INTEL_UNCORE_EVENT_DESC(_name, _config)                 \
+{                                                               \
+        .attr   = __ATTR(_name, 0444, uncore_event_show, NULL), \
+        .config = _config,                                      \
+}
+
+#define DEFINE_UNCORE_FORMAT_ATTR(_var, _name, _format)                 \
+static ssize_t __uncore_##_var##_show(struct kobject *kobj,             \
+                                struct kobj_attribute *attr,            \
+                                char *page)                             \
+{                                                                       \
+        BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE);                     \
+        return sprintf(page, _format "\n");                             \
+}                                                                       \
+static struct kobj_attribute format_attr_##_var =                       \
+        __ATTR(_name, 0444, __uncore_##_var##_show, NULL)
+
+
+static ssize_t uncore_event_show(struct kobject *kobj,
+                                struct kobj_attribute *attr, char *buf)
+{
+        struct uncore_event_desc *event =
+                container_of(attr, struct uncore_event_desc, attr);
+        return sprintf(buf, "%s", event->config);
+}
+
+static inline unsigned uncore_pci_box_ctl(struct intel_uncore_box *box)
+{
+        return box->pmu->type->box_ctl;
+}
+
+static inline unsigned uncore_pci_fixed_ctl(struct intel_uncore_box *box)
+{
+        return box->pmu->type->fixed_ctl;
+}
+
+static inline unsigned uncore_pci_fixed_ctr(struct intel_uncore_box *box)
+{
+        return box->pmu->type->fixed_ctr;
+}
+
+static inline
+unsigned uncore_pci_event_ctl(struct intel_uncore_box *box, int idx)
+{
+        return idx * 4 + box->pmu->type->event_ctl;
+}
+
+static inline
+unsigned uncore_pci_perf_ctr(struct intel_uncore_box *box, int idx)
+{
+        return idx * 8 + box->pmu->type->perf_ctr;
+}
+
+static inline unsigned uncore_msr_box_offset(struct intel_uncore_box *box)
+{
+        struct intel_uncore_pmu *pmu = box->pmu;
+        return pmu->type->msr_offsets ?
+                pmu->type->msr_offsets[pmu->pmu_idx] :
+                pmu->type->msr_offset * pmu->pmu_idx;
+}
+
+static inline unsigned uncore_msr_box_ctl(struct intel_uncore_box *box)
+{
+        if (!box->pmu->type->box_ctl)
+                return 0;
+        return box->pmu->type->box_ctl + uncore_msr_box_offset(box);
+}
+
+static inline unsigned uncore_msr_fixed_ctl(struct intel_uncore_box *box)
+{
+        if (!box->pmu->type->fixed_ctl)
+                return 0;
+        return box->pmu->type->fixed_ctl + uncore_msr_box_offset(box);
+}
+
+static inline unsigned uncore_msr_fixed_ctr(struct intel_uncore_box *box)
+{
+        return box->pmu->type->fixed_ctr + uncore_msr_box_offset(box);
+}
+
+static inline
+unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)
+{
+        return box->pmu->type->event_ctl +
+                (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
+                uncore_msr_box_offset(box);
+}
+
+static inline
+unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)
+{
+        return box->pmu->type->perf_ctr +
+                (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +
+                uncore_msr_box_offset(box);
+}
+
+static inline
+unsigned uncore_fixed_ctl(struct intel_uncore_box *box)
+{
+        if (box->pci_dev)
+                return uncore_pci_fixed_ctl(box);
+        else
+                return uncore_msr_fixed_ctl(box);
+}
+
+static inline
+unsigned uncore_fixed_ctr(struct intel_uncore_box *box)
+{
+        if (box->pci_dev)
+                return uncore_pci_fixed_ctr(box);
+        else
+                return uncore_msr_fixed_ctr(box);
+}
+
+static inline
+unsigned uncore_event_ctl(struct intel_uncore_box *box, int idx)
+{
+        if (box->pci_dev)
+                return uncore_pci_event_ctl(box, idx);
+        else
+                return uncore_msr_event_ctl(box, idx);
+}
+
+static inline
+unsigned uncore_perf_ctr(struct intel_uncore_box *box, int idx)
+{
+        if (box->pci_dev)
+                return uncore_pci_perf_ctr(box, idx);
+        else
+                return uncore_msr_perf_ctr(box, idx);
+}
+
+static inline int uncore_perf_ctr_bits(struct intel_uncore_box *box)
+{
+        return box->pmu->type->perf_ctr_bits;
+}
+
+static inline int uncore_fixed_ctr_bits(struct intel_uncore_box *box)
+{
+        return box->pmu->type->fixed_ctr_bits;
+}
+
+static inline int uncore_num_counters(struct intel_uncore_box *box)
+{
+        return box->pmu->type->num_counters;
+}
+
+static inline void uncore_disable_box(struct intel_uncore_box *box)
+{
+        if (box->pmu->type->ops->disable_box)
+                box->pmu->type->ops->disable_box(box);
+}
+
+static inline void uncore_enable_box(struct intel_uncore_box *box)
+{
+        if (box->pmu->type->ops->enable_box)
+                box->pmu->type->ops->enable_box(box);
+}
+
+static inline void uncore_disable_event(struct intel_uncore_box *box,
+                                struct perf_event *event)
+{
+        box->pmu->type->ops->disable_event(box, event);
+}
+
+static inline void uncore_enable_event(struct intel_uncore_box *box,
+                                struct perf_event *event)
+{
+        box->pmu->type->ops->enable_event(box, event);
+}
+
+static inline u64 uncore_read_counter(struct intel_uncore_box *box,
+                                struct perf_event *event)
+{
+        return box->pmu->type->ops->read_counter(box, event);
+}
+
+static inline void uncore_box_init(struct intel_uncore_box *box)
+{
+        if (!test_and_set_bit(UNCORE_BOX_FLAG_INITIATED, &box->flags)) {
+                if (box->pmu->type->ops->init_box)
+                        box->pmu->type->ops->init_box(box);
+        }
+}
+
+static inline bool uncore_box_is_fake(struct intel_uncore_box *box)
+{
+        return (box->phys_id < 0);
+}
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index 47124a73dd7..92c7e39a079 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -895,8 +895,8 @@ static void p4_pmu_disable_pebs(void)
          * So at moment let leave metrics turned on forever -- it's
          * ok for now but need to be revisited!
          *
-         * (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE, (u64)0);
-         * (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT, (u64)0);
+         * (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)0);
+         * (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT, (u64)0);
          */
 }
 
@@ -909,7 +909,7 @@ static inline void p4_pmu_disable_event(struct perf_event *event)
          * state we need to clear P4_CCCR_OVF, otherwise interrupt get
          * asserted again and again
          */
-        (void)checking_wrmsrl(hwc->config_base,
+        (void)wrmsrl_safe(hwc->config_base,
                 (u64)(p4_config_unpack_cccr(hwc->config)) &
                         ~P4_CCCR_ENABLE & ~P4_CCCR_OVF & ~P4_CCCR_RESERVED);
 }
@@ -943,8 +943,8 @@ static void p4_pmu_enable_pebs(u64 config)
 
         bind = &p4_pebs_bind_map[idx];
 
-        (void)checking_wrmsrl(MSR_IA32_PEBS_ENABLE,     (u64)bind->metric_pebs);
-        (void)checking_wrmsrl(MSR_P4_PEBS_MATRIX_VERT,  (u64)bind->metric_vert);
+        (void)wrmsrl_safe(MSR_IA32_PEBS_ENABLE, (u64)bind->metric_pebs);
+        (void)wrmsrl_safe(MSR_P4_PEBS_MATRIX_VERT,      (u64)bind->metric_vert);
 }
 
 static void p4_pmu_enable_event(struct perf_event *event)
@@ -978,8 +978,8 @@ static void p4_pmu_enable_event(struct perf_event *event)
          */
         p4_pmu_enable_pebs(hwc->config);
 
-        (void)checking_wrmsrl(escr_addr, escr_conf);
-        (void)checking_wrmsrl(hwc->config_base,
+        (void)wrmsrl_safe(escr_addr, escr_conf);
+        (void)wrmsrl_safe(hwc->config_base,
                                 (cccr & ~P4_CCCR_RESERVED) | P4_CCCR_ENABLE);
 }
 
@@ -1325,7 +1325,7 @@ __init int p4_pmu_init(void)
         unsigned int low, high;
 
         /* If we get stripped -- indexing fails */
-        BUILD_BUG_ON(ARCH_P4_MAX_CCCR > X86_PMC_MAX_GENERIC);
+        BUILD_BUG_ON(ARCH_P4_MAX_CCCR > INTEL_PMC_MAX_GENERIC);
 
         rdmsr(MSR_IA32_MISC_ENABLE, low, high);
         if (!(low & (1 << 7))) {
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c
index 32bcfc7dd23..e4dd0f7a045 100644
--- a/arch/x86/kernel/cpu/perf_event_p6.c
+++ b/arch/x86/kernel/cpu/perf_event_p6.c
@@ -71,7 +71,7 @@ p6_pmu_disable_event(struct perf_event *event)
         if (cpuc->enabled)
                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 
-        (void)checking_wrmsrl(hwc->config_base, val);
+        (void)wrmsrl_safe(hwc->config_base, val);
 }
 
 static void p6_pmu_enable_event(struct perf_event *event)
@@ -84,7 +84,7 @@ static void p6_pmu_enable_event(struct perf_event *event)
         if (cpuc->enabled)
                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
 
-        (void)checking_wrmsrl(hwc->config_base, val);
+        (void)wrmsrl_safe(hwc->config_base, val);
 }
 
 PMU_FORMAT_ATTR(event,  "config:0-7"    );
diff --git a/arch/x86/kernel/cpu/sched.c b/arch/x86/kernel/cpu/sched.c
deleted file mode 100644
index a640ae5ad20..00000000000
--- a/arch/x86/kernel/cpu/sched.c
+++ /dev/null
@@ -1,55 +0,0 @@
-#include <linux/sched.h>
-#include <linux/math64.h>
-#include <linux/percpu.h>
-#include <linux/irqflags.h>
-
-#include <asm/cpufeature.h>
-#include <asm/processor.h>
-
-#ifdef CONFIG_SMP
-
-static DEFINE_PER_CPU(struct aperfmperf, old_perf_sched);
-
-static unsigned long scale_aperfmperf(void)
-{
-        struct aperfmperf val, *old = &__get_cpu_var(old_perf_sched);
-        unsigned long ratio, flags;
-
-        local_irq_save(flags);
-        get_aperfmperf(&val);
-        local_irq_restore(flags);
-
-        ratio = calc_aperfmperf_ratio(old, &val);
-        *old = val;
-
-        return ratio;
-}
-
-unsigned long arch_scale_freq_power(struct sched_domain *sd, int cpu)
-{
-        /*
-         * do aperf/mperf on the cpu level because it includes things
-         * like turbo mode, which are relevant to full cores.
-         */
-        if (boot_cpu_has(X86_FEATURE_APERFMPERF))
-                return scale_aperfmperf();
-
-        /*
-         * maybe have something cpufreq here
-         */
-
-        return default_scale_freq_power(sd, cpu);
-}
-
-unsigned long arch_scale_smt_power(struct sched_domain *sd, int cpu)
-{
-        /*
-         * aperf/mperf already includes the smt gain
-         */
-        if (boot_cpu_has(X86_FEATURE_APERFMPERF))
-                return SCHED_LOAD_SCALE;
-
-        return default_scale_smt_power(sd, cpu);
-}
-
-#endif
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
index 571246d81ed..ae42418bc50 100644
--- a/arch/x86/kernel/dumpstack.c
+++ b/arch/x86/kernel/dumpstack.c
@@ -27,8 +27,8 @@ static int die_counter;
 
 void printk_address(unsigned long address, int reliable)
 {
-        printk(" [<%p>] %s%pB\n", (void *) address,
-                        reliable ? "" : "? ", (void *) address);
+        pr_cont(" [<%p>] %s%pB\n",
+                (void *)address, reliable ? "" : "? ", (void *)address);
 }
 
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
@@ -271,6 +271,7 @@ int __kprobes __die(const char *str, struct pt_regs *regs, long err)
                         current->thread.trap_nr, SIGSEGV) == NOTIFY_STOP)
                 return 1;
 
+        print_modules();
         show_regs(regs);
 #ifdef CONFIG_X86_32
         if (user_mode_vm(regs)) {
diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c
index e0b1d783daa..1038a417ea5 100644
--- a/arch/x86/kernel/dumpstack_32.c
+++ b/arch/x86/kernel/dumpstack_32.c
@@ -73,11 +73,11 @@ show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
                 if (kstack_end(stack))
                         break;
                 if (i && ((i % STACKSLOTS_PER_LINE) == 0))
-                        printk(KERN_CONT "\n");
-                printk(KERN_CONT " %08lx", *stack++);
+                        pr_cont("\n");
+                pr_cont(" %08lx", *stack++);
                 touch_nmi_watchdog();
         }
-        printk(KERN_CONT "\n");
+        pr_cont("\n");
         show_trace_log_lvl(task, regs, sp, bp, log_lvl);
 }
 
@@ -86,12 +86,11 @@ void show_regs(struct pt_regs *regs)
 {
         int i;
 
-        print_modules();
         __show_regs(regs, !user_mode_vm(regs));
 
-        printk(KERN_EMERG "Process %.*s (pid: %d, ti=%p task=%p task.ti=%p)\n",
-                TASK_COMM_LEN, current->comm, task_pid_nr(current),
-                current_thread_info(), current, task_thread_info(current));
+        pr_emerg("Process %.*s (pid: %d, ti=%p task=%p task.ti=%p)\n",
+                 TASK_COMM_LEN, current->comm, task_pid_nr(current),
+                 current_thread_info(), current, task_thread_info(current));
         /*
          * When in-kernel, we also print out the stack and code at the
          * time of the fault..
@@ -102,10 +101,10 @@ void show_regs(struct pt_regs *regs)
                 unsigned char c;
                 u8 *ip;
 
-                printk(KERN_EMERG "Stack:\n");
+                pr_emerg("Stack:\n");
                 show_stack_log_lvl(NULL, regs, &regs->sp, 0, KERN_EMERG);
 
-                printk(KERN_EMERG "Code: ");
+                pr_emerg("Code:");
 
                 ip = (u8 *)regs->ip - code_prologue;
                 if (ip < (u8 *)PAGE_OFFSET || probe_kernel_address(ip, c)) {
@@ -116,16 +115,16 @@ void show_regs(struct pt_regs *regs)
                 for (i = 0; i < code_len; i++, ip++) {
                         if (ip < (u8 *)PAGE_OFFSET ||
                                         probe_kernel_address(ip, c)) {
-                                printk(KERN_CONT " Bad EIP value.");
+                                pr_cont("  Bad EIP value.");
                                 break;
                         }
                         if (ip == (u8 *)regs->ip)
-                                printk(KERN_CONT "<%02x> ", c);
+                                pr_cont(" <%02x>", c);
                         else
-                                printk(KERN_CONT "%02x ", c);
+                                pr_cont(" %02x", c);
                 }
         }
-        printk(KERN_CONT "\n");
+        pr_cont("\n");
 }
 
 int is_valid_bugaddr(unsigned long ip)
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index 791b76122aa..b653675d528 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -228,20 +228,20 @@ show_stack_log_lvl(struct task_struct *task, struct pt_regs *regs,
                 if (stack >= irq_stack && stack <= irq_stack_end) {
                         if (stack == irq_stack_end) {
                                 stack = (unsigned long *) (irq_stack_end[-1]);
-                                printk(KERN_CONT " <EOI> ");
+                                pr_cont(" <EOI> ");
                         }
                 } else {
                 if (((long) stack & (THREAD_SIZE-1)) == 0)
                         break;
                 }
                 if (i && ((i % STACKSLOTS_PER_LINE) == 0))
-                        printk(KERN_CONT "\n");
-                printk(KERN_CONT " %016lx", *stack++);
+                        pr_cont("\n");
+                pr_cont(" %016lx", *stack++);
                 touch_nmi_watchdog();
         }
         preempt_enable();
 
-        printk(KERN_CONT "\n");
+        pr_cont("\n");
         show_trace_log_lvl(task, regs, sp, bp, log_lvl);
 }
 
@@ -254,10 +254,9 @@ void show_regs(struct pt_regs *regs)
 
         sp = regs->sp;
         printk("CPU %d ", cpu);
-        print_modules();
         __show_regs(regs, 1);
-        printk("Process %s (pid: %d, threadinfo %p, task %p)\n",
-                cur->comm, cur->pid, task_thread_info(cur), cur);
+        printk(KERN_DEFAULT "Process %s (pid: %d, threadinfo %p, task %p)\n",
+               cur->comm, cur->pid, task_thread_info(cur), cur);
 
         /*
          * When in-kernel, we also print out the stack and code at the
@@ -284,16 +283,16 @@ void show_regs(struct pt_regs *regs)
                 for (i = 0; i < code_len; i++, ip++) {
                         if (ip < (u8 *)PAGE_OFFSET ||
                                         probe_kernel_address(ip, c)) {
-                                printk(KERN_CONT " Bad RIP value.");
+                                pr_cont(" Bad RIP value.");
                                 break;
                         }
                         if (ip == (u8 *)regs->ip)
-                                printk(KERN_CONT "<%02x> ", c);
+                                pr_cont("<%02x> ", c);
                         else
-                                printk(KERN_CONT "%02x ", c);
+                                pr_cont("%02x ", c);
                 }
         }
-        printk(KERN_CONT "\n");
+        pr_cont("\n");
 }
 
 int is_valid_bugaddr(unsigned long ip)
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index 41857970517..ed858e9e9a7 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -944,7 +944,7 @@ void __init e820_reserve_resources(void)
         for (i = 0; i < e820_saved.nr_map; i++) {
                 struct e820entry *entry = &e820_saved.map[i];
                 firmware_map_add_early(entry->addr,
-                        entry->addr + entry->size - 1,
+                        entry->addr + entry->size,
                         e820_type_to_string(entry->type));
         }
 }
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index 7d65133b51b..69babd8c834 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1048,24 +1048,6 @@ apicinterrupt LOCAL_TIMER_VECTOR \
 apicinterrupt X86_PLATFORM_IPI_VECTOR \
         x86_platform_ipi smp_x86_platform_ipi
 
-#ifdef CONFIG_SMP
-        ALIGN
-        INTR_FRAME
-.irp idx,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15, \
-        16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
-.if NUM_INVALIDATE_TLB_VECTORS > \idx
-ENTRY(invalidate_interrupt\idx)
-        pushq_cfi $~(INVALIDATE_TLB_VECTOR_START+\idx)
-        jmp .Lcommon_invalidate_interrupt0
-        CFI_ADJUST_CFA_OFFSET -8
-END(invalidate_interrupt\idx)
-.endif
-.endr
-        CFI_ENDPROC
-apicinterrupt INVALIDATE_TLB_VECTOR_START, \
-        invalidate_interrupt0, smp_invalidate_interrupt
-#endif
-
 apicinterrupt THRESHOLD_APIC_VECTOR \
         threshold_interrupt smp_threshold_interrupt
 apicinterrupt THERMAL_APIC_VECTOR \
@@ -1758,10 +1740,30 @@ end_repeat_nmi:
          */
         call save_paranoid
         DEFAULT_FRAME 0
+
+        /*
+         * Save off the CR2 register. If we take a page fault in the NMI then
+         * it could corrupt the CR2 value. If the NMI preempts a page fault
+         * handler before it was able to read the CR2 register, and then the
+         * NMI itself takes a page fault, the page fault that was preempted
+         * will read the information from the NMI page fault and not the
+         * origin fault. Save it off and restore it if it changes.
+         * Use the r12 callee-saved register.
+         */
+        movq %cr2, %r12
+
         /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */
         movq %rsp,%rdi
         movq $-1,%rsi
         call do_nmi
+
+        /* Did the NMI take a page fault? Restore cr2 if it did */
+        movq %cr2, %rcx
+        cmpq %rcx, %r12
+        je 1f
+        movq %r12, %cr2
+1:
+        
         testl %ebx,%ebx                         /* swapgs needed? */
         jnz nmi_restore
 nmi_swapgs:
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 3dafc6003b7..d44f7829968 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -270,7 +270,7 @@ void fixup_irqs(void)
 
                 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
                         break_affinity = 1;
-                        affinity = cpu_all_mask;
+                        affinity = cpu_online_mask;
                 }
 
                 chip = irq_data_get_irq_chip(data);
@@ -294,9 +294,9 @@ void fixup_irqs(void)
                 raw_spin_unlock(&desc->lock);
 
                 if (break_affinity && set_affinity)
-                        printk("Broke affinity for irq %i\n", irq);
+                        pr_notice("Broke affinity for irq %i\n", irq);
                 else if (!set_affinity)
-                        printk("Cannot set affinity for irq %i\n", irq);
+                        pr_notice("Cannot set affinity for irq %i\n", irq);
         }
 
         /*
@@ -328,6 +328,7 @@ void fixup_irqs(void)
                                 chip->irq_retrigger(data);
                         raw_spin_unlock(&desc->lock);
                 }
+                __this_cpu_write(vector_irq[vector], -1);
         }
 }
 #endif
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index 252981afd6c..6e03b0d6913 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -171,79 +171,6 @@ static void __init smp_intr_init(void)
          */
         alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 
-        /* IPIs for invalidation */
-#define ALLOC_INVTLB_VEC(NR) \
-        alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+NR, \
-                invalidate_interrupt##NR)
-
-        switch (NUM_INVALIDATE_TLB_VECTORS) {
-        default:
-                ALLOC_INVTLB_VEC(31);
-        case 31:
-                ALLOC_INVTLB_VEC(30);
-        case 30:
-                ALLOC_INVTLB_VEC(29);
-        case 29:
-                ALLOC_INVTLB_VEC(28);
-        case 28:
-                ALLOC_INVTLB_VEC(27);
-        case 27:
-                ALLOC_INVTLB_VEC(26);
-        case 26:
-                ALLOC_INVTLB_VEC(25);
-        case 25:
-                ALLOC_INVTLB_VEC(24);
-        case 24:
-                ALLOC_INVTLB_VEC(23);
-        case 23:
-                ALLOC_INVTLB_VEC(22);
-        case 22:
-                ALLOC_INVTLB_VEC(21);
-        case 21:
-                ALLOC_INVTLB_VEC(20);
-        case 20:
-                ALLOC_INVTLB_VEC(19);
-        case 19:
-                ALLOC_INVTLB_VEC(18);
-        case 18:
-                ALLOC_INVTLB_VEC(17);
-        case 17:
-                ALLOC_INVTLB_VEC(16);
-        case 16:
-                ALLOC_INVTLB_VEC(15);
-        case 15:
-                ALLOC_INVTLB_VEC(14);
-        case 14:
-                ALLOC_INVTLB_VEC(13);
-        case 13:
-                ALLOC_INVTLB_VEC(12);
-        case 12:
-                ALLOC_INVTLB_VEC(11);
-        case 11:
-                ALLOC_INVTLB_VEC(10);
-        case 10:
-                ALLOC_INVTLB_VEC(9);
-        case 9:
-                ALLOC_INVTLB_VEC(8);
-        case 8:
-                ALLOC_INVTLB_VEC(7);
-        case 7:
-                ALLOC_INVTLB_VEC(6);
-        case 6:
-                ALLOC_INVTLB_VEC(5);
-        case 5:
-                ALLOC_INVTLB_VEC(4);
-        case 4:
-                ALLOC_INVTLB_VEC(3);
-        case 3:
-                ALLOC_INVTLB_VEC(2);
-        case 2:
-                ALLOC_INVTLB_VEC(1);
-        case 1:
-                ALLOC_INVTLB_VEC(0);
-                break;
-        }
-
         /* IPI for generic function call */
         alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 
diff --git a/arch/x86/kernel/kdebugfs.c b/arch/x86/kernel/kdebugfs.c
index 1d5d31ea686..dc1404bf8e4 100644
--- a/arch/x86/kernel/kdebugfs.c
+++ b/arch/x86/kernel/kdebugfs.c
@@ -107,7 +107,7 @@ static int __init create_setup_data_nodes(struct dentry *parent)
 {
         struct setup_data_node *node;
         struct setup_data *data;
-        int error = -ENOMEM;
+        int error;
         struct dentry *d;
         struct page *pg;
         u64 pa_data;
@@ -121,8 +121,10 @@ static int __init create_setup_data_nodes(struct dentry *parent)
 
         while (pa_data) {
                 node = kmalloc(sizeof(*node), GFP_KERNEL);
-                if (!node)
+                if (!node) {
+                        error = -ENOMEM;
                         goto err_dir;
+                }
 
                 pg = pfn_to_page((pa_data+sizeof(*data)-1) >> PAGE_SHIFT);
                 if (PageHighMem(pg)) {
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index e554e5ad2fe..c1d61ee4b4f 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -39,6 +39,9 @@
 #include <asm/desc.h>
 #include <asm/tlbflush.h>
 #include <asm/idle.h>
+#include <asm/apic.h>
+#include <asm/apicdef.h>
+#include <asm/hypervisor.h>
 
 static int kvmapf = 1;
 
@@ -283,6 +286,22 @@ static void kvm_register_steal_time(void)
                 cpu, __pa(st));
 }
 
+static DEFINE_PER_CPU(unsigned long, kvm_apic_eoi) = KVM_PV_EOI_DISABLED;
+
+static void kvm_guest_apic_eoi_write(u32 reg, u32 val)
+{
+        /**
+         * This relies on __test_and_clear_bit to modify the memory
+         * in a way that is atomic with respect to the local CPU.
+         * The hypervisor only accesses this memory from the local CPU so
+         * there's no need for lock or memory barriers.
+         * An optimization barrier is implied in apic write.
+         */
+        if (__test_and_clear_bit(KVM_PV_EOI_BIT, &__get_cpu_var(kvm_apic_eoi)))
+                return;
+        apic_write(APIC_EOI, APIC_EOI_ACK);
+}
+
 void __cpuinit kvm_guest_cpu_init(void)
 {
         if (!kvm_para_available())
@@ -300,11 +319,20 @@ void __cpuinit kvm_guest_cpu_init(void)
                        smp_processor_id());
         }
 
+        if (kvm_para_has_feature(KVM_FEATURE_PV_EOI)) {
+                unsigned long pa;
+                /* Size alignment is implied but just to make it explicit. */
+                BUILD_BUG_ON(__alignof__(kvm_apic_eoi) < 4);
+                __get_cpu_var(kvm_apic_eoi) = 0;
+                pa = __pa(&__get_cpu_var(kvm_apic_eoi)) | KVM_MSR_ENABLED;
+                wrmsrl(MSR_KVM_PV_EOI_EN, pa);
+        }
+
         if (has_steal_clock)
                 kvm_register_steal_time();
 }
 
-static void kvm_pv_disable_apf(void *unused)
+static void kvm_pv_disable_apf(void)
 {
         if (!__get_cpu_var(apf_reason).enabled)
                 return;
@@ -316,11 +344,23 @@ static void kvm_pv_disable_apf(void *unused)
                smp_processor_id());
 }
 
+static void kvm_pv_guest_cpu_reboot(void *unused)
+{
+        /*
+         * We disable PV EOI before we load a new kernel by kexec,
+         * since MSR_KVM_PV_EOI_EN stores a pointer into old kernel's memory.
+         * New kernel can re-enable when it boots.
+         */
+        if (kvm_para_has_feature(KVM_FEATURE_PV_EOI))
+                wrmsrl(MSR_KVM_PV_EOI_EN, 0);
+        kvm_pv_disable_apf();
+}
+
 static int kvm_pv_reboot_notify(struct notifier_block *nb,
                                 unsigned long code, void *unused)
 {
         if (code == SYS_RESTART)
-                on_each_cpu(kvm_pv_disable_apf, NULL, 1);
+                on_each_cpu(kvm_pv_guest_cpu_reboot, NULL, 1);
         return NOTIFY_DONE;
 }
 
@@ -371,7 +411,9 @@ static void __cpuinit kvm_guest_cpu_online(void *dummy)
 static void kvm_guest_cpu_offline(void *dummy)
 {
         kvm_disable_steal_time();
-        kvm_pv_disable_apf(NULL);
+        if (kvm_para_has_feature(KVM_FEATURE_PV_EOI))
+                wrmsrl(MSR_KVM_PV_EOI_EN, 0);
+        kvm_pv_disable_apf();
         apf_task_wake_all();
 }
 
@@ -424,6 +466,9 @@ void __init kvm_guest_init(void)
                 pv_time_ops.steal_clock = kvm_steal_clock;
         }
 
+        if (kvm_para_has_feature(KVM_FEATURE_PV_EOI))
+                apic_set_eoi_write(kvm_guest_apic_eoi_write);
+
 #ifdef CONFIG_SMP
         smp_ops.smp_prepare_boot_cpu = kvm_smp_prepare_boot_cpu;
         register_cpu_notifier(&kvm_cpu_notifier);
@@ -432,6 +477,19 @@ void __init kvm_guest_init(void)
 #endif
 }
 
+static bool __init kvm_detect(void)
+{
+        if (!kvm_para_available())
+                return false;
+        return true;
+}
+
+const struct hypervisor_x86 x86_hyper_kvm __refconst = {
+        .name                   = "KVM",
+        .detect                 = kvm_detect,
+};
+EXPORT_SYMBOL_GPL(x86_hyper_kvm);
+
 static __init int activate_jump_labels(void)
 {
         if (has_steal_clock) {
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 8a2ce8fd41c..82746f942cd 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -143,11 +143,12 @@ static int get_matching_microcode(int cpu, const u8 *ucode_ptr,
                                   unsigned int *current_size)
 {
         struct microcode_header_amd *mc_hdr;
-        unsigned int actual_size;
+        unsigned int actual_size, patch_size;
         u16 equiv_cpu_id;
 
         /* size of the current patch we're staring at */
-        *current_size = *(u32 *)(ucode_ptr + 4) + SECTION_HDR_SIZE;
+        patch_size = *(u32 *)(ucode_ptr + 4);
+        *current_size = patch_size + SECTION_HDR_SIZE;
 
         equiv_cpu_id = find_equiv_id();
         if (!equiv_cpu_id)
@@ -174,7 +175,7 @@ static int get_matching_microcode(int cpu, const u8 *ucode_ptr,
         /*
          * now that the header looks sane, verify its size
          */
-        actual_size = verify_ucode_size(cpu, *current_size, leftover_size);
+        actual_size = verify_ucode_size(cpu, patch_size, leftover_size);
         if (!actual_size)
                 return 0;
 
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index fbdfc691718..4873e62db6a 100644
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -87,6 +87,7 @@
 #include <asm/microcode.h>
 #include <asm/processor.h>
 #include <asm/cpu_device_id.h>
+#include <asm/perf_event.h>
 
 MODULE_DESCRIPTION("Microcode Update Driver");
 MODULE_AUTHOR("Tigran Aivazian <tigran@aivazian.fsnet.co.uk>");
@@ -277,7 +278,6 @@ static int reload_for_cpu(int cpu)
         struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
         int err = 0;
 
-        mutex_lock(&microcode_mutex);
         if (uci->valid) {
                 enum ucode_state ustate;
 
@@ -288,7 +288,6 @@ static int reload_for_cpu(int cpu)
                         if (ustate == UCODE_ERROR)
                                 err = -EINVAL;
         }
-        mutex_unlock(&microcode_mutex);
 
         return err;
 }
@@ -298,19 +297,31 @@ static ssize_t reload_store(struct device *dev,
                             const char *buf, size_t size)
 {
         unsigned long val;
-        int cpu = dev->id;
-        ssize_t ret = 0;
+        int cpu;
+        ssize_t ret = 0, tmp_ret;
 
         ret = kstrtoul(buf, 0, &val);
         if (ret)
                 return ret;
 
-        if (val == 1) {
-                get_online_cpus();
-                if (cpu_online(cpu))
-                        ret = reload_for_cpu(cpu);
-                put_online_cpus();
+        if (val != 1)
+                return size;
+
+        get_online_cpus();
+        mutex_lock(&microcode_mutex);
+        for_each_online_cpu(cpu) {
+                tmp_ret = reload_for_cpu(cpu);
+                if (tmp_ret != 0)
+                        pr_warn("Error reloading microcode on CPU %d\n", cpu);
+
+                /* save retval of the first encountered reload error */
+                if (!ret)
+                        ret = tmp_ret;
         }
+        if (!ret)
+                perf_check_microcode();
+        mutex_unlock(&microcode_mutex);
+        put_online_cpus();
 
         if (!ret)
                 ret = size;
@@ -339,7 +350,6 @@ static DEVICE_ATTR(version, 0400, version_show, NULL);
 static DEVICE_ATTR(processor_flags, 0400, pf_show, NULL);
 
 static struct attribute *mc_default_attrs[] = {
-        &dev_attr_reload.attr,
         &dev_attr_version.attr,
         &dev_attr_processor_flags.attr,
         NULL
@@ -504,7 +514,7 @@ static struct notifier_block __refdata mc_cpu_notifier = {
 
 #ifdef MODULE
 /* Autoload on Intel and AMD systems */
-static const struct x86_cpu_id microcode_id[] = {
+static const struct x86_cpu_id __initconst microcode_id[] = {
 #ifdef CONFIG_MICROCODE_INTEL
         { X86_VENDOR_INTEL, X86_FAMILY_ANY, X86_MODEL_ANY, },
 #endif
@@ -516,6 +526,16 @@ static const struct x86_cpu_id microcode_id[] = {
 MODULE_DEVICE_TABLE(x86cpu, microcode_id);
 #endif
 
+static struct attribute *cpu_root_microcode_attrs[] = {
+        &dev_attr_reload.attr,
+        NULL
+};
+
+static struct attribute_group cpu_root_microcode_group = {
+        .name  = "microcode",
+        .attrs = cpu_root_microcode_attrs,
+};
+
 static int __init microcode_init(void)
 {
         struct cpuinfo_x86 *c = &cpu_data(0);
@@ -540,16 +560,25 @@ static int __init microcode_init(void)
         mutex_lock(&microcode_mutex);
 
         error = subsys_interface_register(&mc_cpu_interface);
-
+        if (!error)
+                perf_check_microcode();
         mutex_unlock(&microcode_mutex);
         put_online_cpus();
 
         if (error)
                 goto out_pdev;
 
+        error = sysfs_create_group(&cpu_subsys.dev_root->kobj,
+                                   &cpu_root_microcode_group);
+
+        if (error) {
+                pr_err("Error creating microcode group!\n");
+                goto out_driver;
+        }
+
         error = microcode_dev_init();
         if (error)
-                goto out_driver;
+                goto out_ucode_group;
 
         register_syscore_ops(&mc_syscore_ops);
         register_hotcpu_notifier(&mc_cpu_notifier);
@@ -559,7 +588,11 @@ static int __init microcode_init(void)
 
         return 0;
 
-out_driver:
+ out_ucode_group:
+        sysfs_remove_group(&cpu_subsys.dev_root->kobj,
+                           &cpu_root_microcode_group);
+
+ out_driver:
         get_online_cpus();
         mutex_lock(&microcode_mutex);
 
@@ -568,7 +601,7 @@ out_driver:
         mutex_unlock(&microcode_mutex);
         put_online_cpus();
 
-out_pdev:
+ out_pdev:
         platform_device_unregister(microcode_pdev);
         return error;
 
@@ -584,6 +617,9 @@ static void __exit microcode_exit(void)
         unregister_hotcpu_notifier(&mc_cpu_notifier);
         unregister_syscore_ops(&mc_syscore_ops);
 
+        sysfs_remove_group(&cpu_subsys.dev_root->kobj,
+                           &cpu_root_microcode_group);
+
         get_online_cpus();
         mutex_lock(&microcode_mutex);
 
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index f21fd94ac89..216a4d754b0 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -15,6 +15,9 @@
     along with this program; if not, write to the Free Software
     Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/moduleloader.h>
 #include <linux/elf.h>
 #include <linux/vmalloc.h>
@@ -30,9 +33,14 @@
 #include <asm/pgtable.h>
 
 #if 0
-#define DEBUGP printk
+#define DEBUGP(fmt, ...)                                \
+        printk(KERN_DEBUG fmt, ##__VA_ARGS__)
 #else
-#define DEBUGP(fmt...)
+#define DEBUGP(fmt, ...)                                \
+do {                                                    \
+        if (0)                                          \
+                printk(KERN_DEBUG fmt, ##__VA_ARGS__);  \
+} while (0)
 #endif
 
 void *module_alloc(unsigned long size)
@@ -56,8 +64,8 @@ int apply_relocate(Elf32_Shdr *sechdrs,
         Elf32_Sym *sym;
         uint32_t *location;
 
-        DEBUGP("Applying relocate section %u to %u\n", relsec,
-               sechdrs[relsec].sh_info);
+        DEBUGP("Applying relocate section %u to %u\n",
+               relsec, sechdrs[relsec].sh_info);
         for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
                 /* This is where to make the change */
                 location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
@@ -73,11 +81,11 @@ int apply_relocate(Elf32_Shdr *sechdrs,
                         *location += sym->st_value;
                         break;
                 case R_386_PC32:
-                        /* Add the value, subtract its postition */
+                        /* Add the value, subtract its position */
                         *location += sym->st_value - (uint32_t)location;
                         break;
                 default:
-                        printk(KERN_ERR "module %s: Unknown relocation: %u\n",
+                        pr_err("%s: Unknown relocation: %u\n",
                                me->name, ELF32_R_TYPE(rel[i].r_info));
                         return -ENOEXEC;
                 }
@@ -97,8 +105,8 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
         void *loc;
         u64 val;
 
-        DEBUGP("Applying relocate section %u to %u\n", relsec,
-               sechdrs[relsec].sh_info);
+        DEBUGP("Applying relocate section %u to %u\n",
+               relsec, sechdrs[relsec].sh_info);
         for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
                 /* This is where to make the change */
                 loc = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
@@ -110,8 +118,8 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
                         + ELF64_R_SYM(rel[i].r_info);
 
                 DEBUGP("type %d st_value %Lx r_addend %Lx loc %Lx\n",
-                        (int)ELF64_R_TYPE(rel[i].r_info),
-                        sym->st_value, rel[i].r_addend, (u64)loc);
+                       (int)ELF64_R_TYPE(rel[i].r_info),
+                       sym->st_value, rel[i].r_addend, (u64)loc);
 
                 val = sym->st_value + rel[i].r_addend;
 
@@ -140,7 +148,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
 #endif
                         break;
                 default:
-                        printk(KERN_ERR "module %s: Unknown rela relocation: %llu\n",
+                        pr_err("%s: Unknown rela relocation: %llu\n",
                                me->name, ELF64_R_TYPE(rel[i].r_info));
                         return -ENOEXEC;
                 }
@@ -148,9 +156,9 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,
         return 0;
 
 overflow:
-        printk(KERN_ERR "overflow in relocation type %d val %Lx\n",
+        pr_err("overflow in relocation type %d val %Lx\n",
                (int)ELF64_R_TYPE(rel[i].r_info), val);
-        printk(KERN_ERR "`%s' likely not compiled with -mcmodel=kernel\n",
+        pr_err("`%s' likely not compiled with -mcmodel=kernel\n",
                me->name);
         return -ENOEXEC;
 }
diff --git a/arch/x86/kernel/nmi.c b/arch/x86/kernel/nmi.c
index a0b2f84457b..f84f5c57de3 100644
--- a/arch/x86/kernel/nmi.c
+++ b/arch/x86/kernel/nmi.c
@@ -365,8 +365,9 @@ static __kprobes void default_do_nmi(struct pt_regs *regs)
 #ifdef CONFIG_X86_32
 /*
  * For i386, NMIs use the same stack as the kernel, and we can
- * add a workaround to the iret problem in C. Simply have 3 states
- * the NMI can be in.
+ * add a workaround to the iret problem in C (preventing nested
+ * NMIs if an NMI takes a trap). Simply have 3 states the NMI
+ * can be in:
  *
  *  1) not running
  *  2) executing
@@ -383,32 +384,50 @@ static __kprobes void default_do_nmi(struct pt_regs *regs)
  * If an NMI hits a breakpoint that executes an iret, another
  * NMI can preempt it. We do not want to allow this new NMI
  * to run, but we want to execute it when the first one finishes.
- * We set the state to "latched", and the first NMI will perform
- * an cmpxchg on the state, and if it doesn't successfully
- * reset the state to "not running" it will restart the next
- * NMI.
+ * We set the state to "latched", and the exit of the first NMI will
+ * perform a dec_return, if the result is zero (NOT_RUNNING), then
+ * it will simply exit the NMI handler. If not, the dec_return
+ * would have set the state to NMI_EXECUTING (what we want it to
+ * be when we are running). In this case, we simply jump back
+ * to rerun the NMI handler again, and restart the 'latched' NMI.
+ *
+ * No trap (breakpoint or page fault) should be hit before nmi_restart,
+ * thus there is no race between the first check of state for NOT_RUNNING
+ * and setting it to NMI_EXECUTING. The HW will prevent nested NMIs
+ * at this point.
+ *
+ * In case the NMI takes a page fault, we need to save off the CR2
+ * because the NMI could have preempted another page fault and corrupt
+ * the CR2 that is about to be read. As nested NMIs must be restarted
+ * and they can not take breakpoints or page faults, the update of the
+ * CR2 must be done before converting the nmi state back to NOT_RUNNING.
+ * Otherwise, there would be a race of another nested NMI coming in
+ * after setting state to NOT_RUNNING but before updating the nmi_cr2.
  */
 enum nmi_states {
-        NMI_NOT_RUNNING,
+        NMI_NOT_RUNNING = 0,
         NMI_EXECUTING,
         NMI_LATCHED,
 };
 static DEFINE_PER_CPU(enum nmi_states, nmi_state);
+static DEFINE_PER_CPU(unsigned long, nmi_cr2);
 
 #define nmi_nesting_preprocess(regs)                                    \
         do {                                                            \
-                if (__get_cpu_var(nmi_state) != NMI_NOT_RUNNING) {      \
-                        __get_cpu_var(nmi_state) = NMI_LATCHED;         \
+                if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) {      \
+                        this_cpu_write(nmi_state, NMI_LATCHED);         \
                         return;                                         \
                 }                                                       \
-        nmi_restart:                                                    \
-                __get_cpu_var(nmi_state) = NMI_EXECUTING;               \
-        } while (0)
+                this_cpu_write(nmi_state, NMI_EXECUTING);               \
+                this_cpu_write(nmi_cr2, read_cr2());                    \
+        } while (0);                                                    \
+        nmi_restart:
 
 #define nmi_nesting_postprocess()                                       \
         do {                                                            \
-                if (cmpxchg(&__get_cpu_var(nmi_state),                  \
-                    NMI_EXECUTING, NMI_NOT_RUNNING) != NMI_EXECUTING)   \
+                if (unlikely(this_cpu_read(nmi_cr2) != read_cr2()))     \
+                        write_cr2(this_cpu_read(nmi_cr2));              \
+                if (this_cpu_dec_return(nmi_state))                     \
                         goto nmi_restart;                               \
         } while (0)
 #else /* x86_64 */
diff --git a/arch/x86/kernel/nmi_selftest.c b/arch/x86/kernel/nmi_selftest.c
index 149b8d9c6ad..6d9582ec032 100644
--- a/arch/x86/kernel/nmi_selftest.c
+++ b/arch/x86/kernel/nmi_selftest.c
@@ -42,7 +42,8 @@ static int __init nmi_unk_cb(unsigned int val, struct pt_regs *regs)
 static void __init init_nmi_testsuite(void)
 {
         /* trap all the unknown NMIs we may generate */
-        register_nmi_handler_initonly(NMI_UNKNOWN, nmi_unk_cb, 0, "nmi_selftest_unk");
+        register_nmi_handler(NMI_UNKNOWN, nmi_unk_cb, 0, "nmi_selftest_unk",
+                        __initdata);
 }
 
 static void __init cleanup_nmi_testsuite(void)
@@ -64,8 +65,8 @@ static void __init test_nmi_ipi(struct cpumask *mask)
 {
         unsigned long timeout;
 
-        if (register_nmi_handler_initonly(NMI_LOCAL, test_nmi_ipi_callback,
-                                 NMI_FLAG_FIRST, "nmi_selftest")) {
+        if (register_nmi_handler(NMI_LOCAL, test_nmi_ipi_callback,
+                                 NMI_FLAG_FIRST, "nmi_selftest", __initdata)) {
                 nmi_fail = FAILURE;
                 return;
         }
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 9ce885996fd..17fff18a103 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -352,9 +352,7 @@ struct pv_cpu_ops pv_cpu_ops = {
 #endif
         .wbinvd = native_wbinvd,
         .read_msr = native_read_msr_safe,
-        .rdmsr_regs = native_rdmsr_safe_regs,
         .write_msr = native_write_msr_safe,
-        .wrmsr_regs = native_wrmsr_safe_regs,
         .read_tsc = native_read_tsc,
         .read_pmc = native_read_pmc,
         .read_tscp = native_read_tscp,
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index b72838bae64..299d49302e7 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -22,6 +22,8 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
 
+#define pr_fmt(fmt) "Calgary: " fmt
+
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/types.h>
@@ -245,7 +247,7 @@ static unsigned long iommu_range_alloc(struct device *dev,
                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
                                           npages, 0, boundary_size, 0);
                 if (offset == ~0UL) {
-                        printk(KERN_WARNING "Calgary: IOMMU full.\n");
+                        pr_warn("IOMMU full\n");
                         spin_unlock_irqrestore(&tbl->it_lock, flags);
                         if (panic_on_overflow)
                                 panic("Calgary: fix the allocator.\n");
@@ -271,8 +273,8 @@ static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
         entry = iommu_range_alloc(dev, tbl, npages);
 
         if (unlikely(entry == DMA_ERROR_CODE)) {
-                printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
-                       "iommu %p\n", npages, tbl);
+                pr_warn("failed to allocate %u pages in iommu %p\n",
+                        npages, tbl);
                 return DMA_ERROR_CODE;
         }
 
@@ -561,8 +563,7 @@ static void calgary_tce_cache_blast(struct iommu_table *tbl)
                 i++;
         } while ((val & 0xff) != 0xff && i < 100);
         if (i == 100)
-                printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
-                       "continuing anyway\n");
+                pr_warn("PCI bus not quiesced, continuing anyway\n");
 
         /* invalidate TCE cache */
         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
@@ -604,8 +605,7 @@ begin:
                 i++;
         } while ((val64 & 0xff) != 0xff && i < 100);
         if (i == 100)
-                printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
-                       "continuing anyway\n");
+                pr_warn("CalIOC2: PCI bus not quiesced, continuing anyway\n");
 
         /* 3. poll Page Migration DEBUG for SoftStopFault */
         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
@@ -617,8 +617,7 @@ begin:
                 if (++count < 100)
                         goto begin;
                 else {
-                        printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
-                               "aborting TCE cache flush sequence!\n");
+                        pr_warn("CalIOC2: too many SoftStopFaults, aborting TCE cache flush sequence!\n");
                         return; /* pray for the best */
                 }
         }
@@ -840,8 +839,8 @@ static void calgary_dump_error_regs(struct iommu_table *tbl)
         plssr = be32_to_cpu(readl(target));
 
         /* If no error, the agent ID in the CSR is not valid */
-        printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
-               "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
+        pr_emerg("DMA error on Calgary PHB 0x%x, 0x%08x@CSR 0x%08x@PLSSR\n",
+                 tbl->it_busno, csr, plssr);
 }
 
 static void calioc2_dump_error_regs(struct iommu_table *tbl)
@@ -867,22 +866,21 @@ static void calioc2_dump_error_regs(struct iommu_table *tbl)
         target = calgary_reg(bbar, phboff | 0x800);
         mck = be32_to_cpu(readl(target));
 
-        printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
-               tbl->it_busno);
+        pr_emerg("DMA error on CalIOC2 PHB 0x%x\n", tbl->it_busno);
 
-        printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
-               csr, plssr, csmr, mck);
+        pr_emerg("0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
+                 csr, plssr, csmr, mck);
 
         /* dump rest of error regs */
-        printk(KERN_EMERG "Calgary: ");
+        pr_emerg("");
         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
                 /* err regs are at 0x810 - 0x870 */
                 erroff = (0x810 + (i * 0x10));
                 target = calgary_reg(bbar, phboff | erroff);
                 errregs[i] = be32_to_cpu(readl(target));
-                printk("0x%08x@0x%lx ", errregs[i], erroff);
+                pr_cont("0x%08x@0x%lx ", errregs[i], erroff);
         }
-        printk("\n");
+        pr_cont("\n");
 
         /* root complex status */
         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index c0f420f76cd..de2b7ad7027 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -45,15 +45,6 @@ int iommu_detected __read_mostly = 0;
  */
 int iommu_pass_through __read_mostly;
 
-/*
- * Group multi-function PCI devices into a single device-group for the
- * iommu_device_group interface.  This tells the iommu driver to pretend
- * it cannot distinguish between functions of a device, exposing only one
- * group for the device.  Useful for disallowing use of individual PCI
- * functions from userspace drivers.
- */
-int iommu_group_mf __read_mostly;
-
 extern struct iommu_table_entry __iommu_table[], __iommu_table_end[];
 
 /* Dummy device used for NULL arguments (normally ISA). */
@@ -194,8 +185,6 @@ static __init int iommu_setup(char *p)
 #endif
                 if (!strncmp(p, "pt", 2))
                         iommu_pass_through = 1;
-                if (!strncmp(p, "group_mf", 8))
-                        iommu_group_mf = 1;
 
                 gart_parse_options(p);
 
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 735279e54e5..ef6a8456f71 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -1,3 +1,5 @@
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/errno.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
@@ -145,16 +147,14 @@ void show_regs_common(void)
         /* Board Name is optional */
         board = dmi_get_system_info(DMI_BOARD_NAME);
 
-        printk(KERN_CONT "\n");
-        printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s",
-                current->pid, current->comm, print_tainted(),
-                init_utsname()->release,
-                (int)strcspn(init_utsname()->version, " "),
-                init_utsname()->version);
-        printk(KERN_CONT " %s %s", vendor, product);
-        if (board)
-                printk(KERN_CONT "/%s", board);
-        printk(KERN_CONT "\n");
+        printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s %s%s%s\n",
+               current->pid, current->comm, print_tainted(),
+               init_utsname()->release,
+               (int)strcspn(init_utsname()->version, " "),
+               init_utsname()->version,
+               vendor, product,
+               board ? "/" : "",
+               board ? board : "");
 }
 
 void flush_thread(void)
@@ -645,7 +645,7 @@ static void amd_e400_idle(void)
                         amd_e400_c1e_detected = true;
                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
                                 mark_tsc_unstable("TSC halt in AMD C1E");
-                        printk(KERN_INFO "System has AMD C1E enabled\n");
+                        pr_info("System has AMD C1E enabled\n");
                 }
         }
 
@@ -659,8 +659,7 @@ static void amd_e400_idle(void)
                          */
                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
                                            &cpu);
-                        printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
-                               cpu);
+                        pr_info("Switch to broadcast mode on CPU%d\n", cpu);
                 }
                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 
@@ -681,8 +680,7 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_SMP
         if (pm_idle == poll_idle && smp_num_siblings > 1) {
-                printk_once(KERN_WARNING "WARNING: polling idle and HT enabled,"
-                        " performance may degrade.\n");
+                pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
         }
 #endif
         if (pm_idle)
@@ -692,11 +690,11 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
                 /*
                  * One CPU supports mwait => All CPUs supports mwait
                  */
-                printk(KERN_INFO "using mwait in idle threads.\n");
+                pr_info("using mwait in idle threads\n");
                 pm_idle = mwait_idle;
         } else if (cpu_has_amd_erratum(amd_erratum_400)) {
                 /* E400: APIC timer interrupt does not wake up CPU from C1e */
-                printk(KERN_INFO "using AMD E400 aware idle routine\n");
+                pr_info("using AMD E400 aware idle routine\n");
                 pm_idle = amd_e400_idle;
         } else
                 pm_idle = default_idle;
@@ -715,7 +713,7 @@ static int __init idle_setup(char *str)
                 return -EINVAL;
 
         if (!strcmp(str, "poll")) {
-                printk("using polling idle threads.\n");
+                pr_info("using polling idle threads\n");
                 pm_idle = poll_idle;
                 boot_option_idle_override = IDLE_POLL;
         } else if (!strcmp(str, "mwait")) {
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 61cdf7fdf09..0a980c9d7cb 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -117,10 +117,10 @@ void release_thread(struct task_struct *dead_task)
 {
         if (dead_task->mm) {
                 if (dead_task->mm->context.size) {
-                        printk("WARNING: dead process %8s still has LDT? <%p/%d>\n",
-                                        dead_task->comm,
-                                        dead_task->mm->context.ldt,
-                                        dead_task->mm->context.size);
+                        pr_warn("WARNING: dead process %8s still has LDT? <%p/%d>\n",
+                                dead_task->comm,
+                                dead_task->mm->context.ldt,
+                                dead_task->mm->context.size);
                         BUG();
                 }
         }
@@ -466,7 +466,7 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
                         task->thread.gs = addr;
                         if (doit) {
                                 load_gs_index(0);
-                                ret = checking_wrmsrl(MSR_KERNEL_GS_BASE, addr);
+                                ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, addr);
                         }
                 }
                 put_cpu();
@@ -494,7 +494,7 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr)
                                 /* set the selector to 0 to not confuse
                                    __switch_to */
                                 loadsegment(fs, 0);
-                                ret = checking_wrmsrl(MSR_FS_BASE, addr);
+                                ret = wrmsrl_safe(MSR_FS_BASE, addr);
                         }
                 }
                 put_cpu();
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c
index 03920a15a63..1b27de56356 100644
--- a/arch/x86/kernel/quirks.c
+++ b/arch/x86/kernel/quirks.c
@@ -512,7 +512,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
 
 #if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
 /* Set correct numa_node information for AMD NB functions */
-static void __init quirk_amd_nb_node(struct pci_dev *dev)
+static void __devinit quirk_amd_nb_node(struct pci_dev *dev)
 {
         struct pci_dev *nb_ht;
         unsigned int devfn;
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 5de92f1abd7..52190a938b4 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -1,3 +1,5 @@
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/module.h>
 #include <linux/reboot.h>
 #include <linux/init.h>
@@ -20,14 +22,12 @@
 #include <asm/virtext.h>
 #include <asm/cpu.h>
 #include <asm/nmi.h>
+#include <asm/smp.h>
 
-#ifdef CONFIG_X86_32
-# include <linux/ctype.h>
-# include <linux/mc146818rtc.h>
-# include <asm/realmode.h>
-#else
-# include <asm/x86_init.h>
-#endif
+#include <linux/ctype.h>
+#include <linux/mc146818rtc.h>
+#include <asm/realmode.h>
+#include <asm/x86_init.h>
 
 /*
  * Power off function, if any
@@ -49,7 +49,7 @@ int reboot_force;
  */
 static int reboot_default = 1;
 
-#if defined(CONFIG_X86_32) && defined(CONFIG_SMP)
+#ifdef CONFIG_SMP
 static int reboot_cpu = -1;
 #endif
 
@@ -67,8 +67,8 @@ bool port_cf9_safe = false;
  * reboot=b[ios] | s[mp] | t[riple] | k[bd] | e[fi] [, [w]arm | [c]old] | p[ci]
  * warm   Don't set the cold reboot flag
  * cold   Set the cold reboot flag
- * bios   Reboot by jumping through the BIOS (only for X86_32)
- * smp    Reboot by executing reset on BSP or other CPU (only for X86_32)
+ * bios   Reboot by jumping through the BIOS
+ * smp    Reboot by executing reset on BSP or other CPU
  * triple Force a triple fault (init)
  * kbd    Use the keyboard controller. cold reset (default)
  * acpi   Use the RESET_REG in the FADT
@@ -95,7 +95,6 @@ static int __init reboot_setup(char *str)
                         reboot_mode = 0;
                         break;
 
-#ifdef CONFIG_X86_32
 #ifdef CONFIG_SMP
                 case 's':
                         if (isdigit(*(str+1))) {
@@ -112,7 +111,6 @@ static int __init reboot_setup(char *str)
 #endif /* CONFIG_SMP */
 
                 case 'b':
-#endif
                 case 'a':
                 case 'k':
                 case 't':
@@ -138,7 +136,6 @@ static int __init reboot_setup(char *str)
 __setup("reboot=", reboot_setup);
 
 
-#ifdef CONFIG_X86_32
 /*
  * Reboot options and system auto-detection code provided by
  * Dell Inc. so their systems "just work". :-)
@@ -152,16 +149,14 @@ static int __init set_bios_reboot(const struct dmi_system_id *d)
 {
         if (reboot_type != BOOT_BIOS) {
                 reboot_type = BOOT_BIOS;
-                printk(KERN_INFO "%s series board detected. Selecting BIOS-method for reboots.\n", d->ident);
+                pr_info("%s series board detected. Selecting %s-method for reboots.\n",
+                        "BIOS", d->ident);
         }
         return 0;
 }
 
-void machine_real_restart(unsigned int type)
+void __noreturn machine_real_restart(unsigned int type)
 {
-        void (*restart_lowmem)(unsigned int) = (void (*)(unsigned int))
-                real_mode_header->machine_real_restart_asm;
-
         local_irq_disable();
 
         /*
@@ -181,25 +176,28 @@ void machine_real_restart(unsigned int type)
         /*
          * Switch back to the initial page table.
          */
+#ifdef CONFIG_X86_32
         load_cr3(initial_page_table);
-
-        /*
-         * Write 0x1234 to absolute memory location 0x472.  The BIOS reads
-         * this on booting to tell it to "Bypass memory test (also warm
-         * boot)".  This seems like a fairly standard thing that gets set by
-         * REBOOT.COM programs, and the previous reset routine did this
-         * too. */
-        *((unsigned short *)0x472) = reboot_mode;
+#else
+        write_cr3(real_mode_header->trampoline_pgd);
+#endif
 
         /* Jump to the identity-mapped low memory code */
-        restart_lowmem(type);
+#ifdef CONFIG_X86_32
+        asm volatile("jmpl *%0" : :
+                     "rm" (real_mode_header->machine_real_restart_asm),
+                     "a" (type));
+#else
+        asm volatile("ljmpl *%0" : :
+                     "m" (real_mode_header->machine_real_restart_asm),
+                     "D" (type));
+#endif
+        unreachable();
 }
 #ifdef CONFIG_APM_MODULE
 EXPORT_SYMBOL(machine_real_restart);
 #endif
 
-#endif /* CONFIG_X86_32 */
-
 /*
  * Some Apple MacBook and MacBookPro's needs reboot=p to be able to reboot
  */
@@ -207,8 +205,8 @@ static int __init set_pci_reboot(const struct dmi_system_id *d)
 {
         if (reboot_type != BOOT_CF9) {
                 reboot_type = BOOT_CF9;
-                printk(KERN_INFO "%s series board detected. "
-                       "Selecting PCI-method for reboots.\n", d->ident);
+                pr_info("%s series board detected. Selecting %s-method for reboots.\n",
+                        "PCI", d->ident);
         }
         return 0;
 }
@@ -217,17 +215,16 @@ static int __init set_kbd_reboot(const struct dmi_system_id *d)
 {
         if (reboot_type != BOOT_KBD) {
                 reboot_type = BOOT_KBD;
-                printk(KERN_INFO "%s series board detected. Selecting KBD-method for reboot.\n", d->ident);
+                pr_info("%s series board detected. Selecting %s-method for reboot.\n",
+                        "KBD", d->ident);
         }
         return 0;
 }
 
 /*
- * This is a single dmi_table handling all reboot quirks.  Note that
- * REBOOT_BIOS is only available for 32bit
+ * This is a single dmi_table handling all reboot quirks.
  */
 static struct dmi_system_id __initdata reboot_dmi_table[] = {
-#ifdef CONFIG_X86_32
         {       /* Handle problems with rebooting on Dell E520's */
                 .callback = set_bios_reboot,
                 .ident = "Dell E520",
@@ -377,7 +374,6 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = {
                         DMI_MATCH(DMI_BOARD_NAME, "P4S800"),
                 },
         },
-#endif /* CONFIG_X86_32 */
 
         {       /* Handle reboot issue on Acer Aspire one */
                 .callback = set_kbd_reboot,
@@ -584,13 +580,11 @@ static void native_machine_emergency_restart(void)
                         reboot_type = BOOT_KBD;
                         break;
 
-#ifdef CONFIG_X86_32
                 case BOOT_BIOS:
                         machine_real_restart(MRR_BIOS);
 
                         reboot_type = BOOT_KBD;
                         break;
-#endif
 
                 case BOOT_ACPI:
                         acpi_reboot();
@@ -632,12 +626,10 @@ void native_machine_shutdown(void)
         /* The boot cpu is always logical cpu 0 */
         int reboot_cpu_id = 0;
 
-#ifdef CONFIG_X86_32
         /* See if there has been given a command line override */
         if ((reboot_cpu != -1) && (reboot_cpu < nr_cpu_ids) &&
                 cpu_online(reboot_cpu))
                 reboot_cpu_id = reboot_cpu;
-#endif
 
         /* Make certain the cpu I'm about to reboot on is online */
         if (!cpu_online(reboot_cpu_id))
@@ -678,7 +670,7 @@ static void __machine_emergency_restart(int emergency)
 
 static void native_machine_restart(char *__unused)
 {
-        printk("machine restart\n");
+        pr_notice("machine restart\n");
 
         if (!reboot_force)
                 machine_shutdown();
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 16be6dc14db..4f165479c45 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -961,9 +961,7 @@ void __init setup_arch(char **cmdline_p)
         kvmclock_init();
 #endif
 
-        x86_init.paging.pagetable_setup_start(swapper_pg_dir);
-        paging_init();
-        x86_init.paging.pagetable_setup_done(swapper_pg_dir);
+        x86_init.paging.pagetable_init();
 
         if (boot_cpu_data.cpuid_level >= 0) {
                 /* A CPU has %cr4 if and only if it has CPUID */
@@ -1031,8 +1029,6 @@ void __init setup_arch(char **cmdline_p)
 
         x86_init.timers.wallclock_init();
 
-        x86_platform.wallclock_init();
-
         mcheck_init();
 
         arch_init_ideal_nops();
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index 5a98aa27218..5cdff035774 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -21,7 +21,7 @@
 #include <asm/cpu.h>
 #include <asm/stackprotector.h>
 
-DEFINE_PER_CPU(int, cpu_number);
+DEFINE_PER_CPU_READ_MOSTLY(int, cpu_number);
 EXPORT_PER_CPU_SYMBOL(cpu_number);
 
 #ifdef CONFIG_X86_64
diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c
index 21af737053a..b280908a376 100644
--- a/arch/x86/kernel/signal.c
+++ b/arch/x86/kernel/signal.c
@@ -6,6 +6,9 @@
  *  2000-06-20  Pentium III FXSR, SSE support by Gareth Hughes
  *  2000-2002   x86-64 support by Andi Kleen
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/sched.h>
 #include <linux/mm.h>
 #include <linux/smp.h>
@@ -814,7 +817,7 @@ void signal_fault(struct pt_regs *regs, void __user *frame, char *where)
                        me->comm, me->pid, where, frame,
                        regs->ip, regs->sp, regs->orig_ax);
                 print_vma_addr(" in ", regs->ip);
-                printk(KERN_CONT "\n");
+                pr_cont("\n");
         }
 
         force_sig(SIGSEGV, me);
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 7bd8a082365..7c5a8c314c0 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -1,4 +1,4 @@
-/*
+ /*
  *      x86 SMP booting functions
  *
  *      (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
@@ -39,6 +39,8 @@
  *      Glauber Costa           :       i386 and x86_64 integration
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/module.h>
@@ -104,17 +106,17 @@ int smp_num_siblings = 1;
 EXPORT_SYMBOL(smp_num_siblings);
 
 /* Last level cache ID of each logical CPU */
-DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
+DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
 
 /* representing HT siblings of each logical CPU */
-DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
+DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
 
 /* representing HT and core siblings of each logical CPU */
-DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
+DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
 
-DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
+DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
 
 /* Per CPU bogomips and other parameters */
 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
@@ -184,7 +186,7 @@ static void __cpuinit smp_callin(void)
          * boards)
          */
 
-        pr_debug("CALLIN, before setup_local_APIC().\n");
+        pr_debug("CALLIN, before setup_local_APIC()\n");
         if (apic->smp_callin_clear_local_apic)
                 apic->smp_callin_clear_local_apic();
         setup_local_APIC();
@@ -255,22 +257,13 @@ notrace static void __cpuinit start_secondary(void *unused)
         check_tsc_sync_target();
 
         /*
-         * We need to hold call_lock, so there is no inconsistency
-         * between the time smp_call_function() determines number of
-         * IPI recipients, and the time when the determination is made
-         * for which cpus receive the IPI. Holding this
-         * lock helps us to not include this cpu in a currently in progress
-         * smp_call_function().
-         *
          * We need to hold vector_lock so there the set of online cpus
          * does not change while we are assigning vectors to cpus.  Holding
          * this lock ensures we don't half assign or remove an irq from a cpu.
          */
-        ipi_call_lock();
         lock_vector_lock();
         set_cpu_online(smp_processor_id(), true);
         unlock_vector_lock();
-        ipi_call_unlock();
         per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
         x86_platform.nmi_init();
 
@@ -432,17 +425,16 @@ static void impress_friends(void)
         /*
          * Allow the user to impress friends.
          */
-        pr_debug("Before bogomips.\n");
+        pr_debug("Before bogomips\n");
         for_each_possible_cpu(cpu)
                 if (cpumask_test_cpu(cpu, cpu_callout_mask))
                         bogosum += cpu_data(cpu).loops_per_jiffy;
-        printk(KERN_INFO
-                "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
+        pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
                 num_online_cpus(),
                 bogosum/(500000/HZ),
                 (bogosum/(5000/HZ))%100);
 
-        pr_debug("Before bogocount - setting activated=1.\n");
+        pr_debug("Before bogocount - setting activated=1\n");
 }
 
 void __inquire_remote_apic(int apicid)
@@ -452,18 +444,17 @@ void __inquire_remote_apic(int apicid)
         int timeout;
         u32 status;
 
-        printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
+        pr_info("Inquiring remote APIC 0x%x...\n", apicid);
 
         for (i = 0; i < ARRAY_SIZE(regs); i++) {
-                printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
+                pr_info("... APIC 0x%x %s: ", apicid, names[i]);
 
                 /*
                  * Wait for idle.
                  */
                 status = safe_apic_wait_icr_idle();
                 if (status)
-                        printk(KERN_CONT
-                               "a previous APIC delivery may have failed\n");
+                        pr_cont("a previous APIC delivery may have failed\n");
 
                 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
 
@@ -476,10 +467,10 @@ void __inquire_remote_apic(int apicid)
                 switch (status) {
                 case APIC_ICR_RR_VALID:
                         status = apic_read(APIC_RRR);
-                        printk(KERN_CONT "%08x\n", status);
+                        pr_cont("%08x\n", status);
                         break;
                 default:
-                        printk(KERN_CONT "failed\n");
+                        pr_cont("failed\n");
                 }
         }
 }
@@ -513,12 +504,12 @@ wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
                         apic_write(APIC_ESR, 0);
                 accept_status = (apic_read(APIC_ESR) & 0xEF);
         }
-        pr_debug("NMI sent.\n");
+        pr_debug("NMI sent\n");
 
         if (send_status)
-                printk(KERN_ERR "APIC never delivered???\n");
+                pr_err("APIC never delivered???\n");
         if (accept_status)
-                printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
+                pr_err("APIC delivery error (%lx)\n", accept_status);
 
         return (send_status | accept_status);
 }
@@ -540,7 +531,7 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
                 apic_read(APIC_ESR);
         }
 
-        pr_debug("Asserting INIT.\n");
+        pr_debug("Asserting INIT\n");
 
         /*
          * Turn INIT on target chip
@@ -556,7 +547,7 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
 
         mdelay(10);
 
-        pr_debug("Deasserting INIT.\n");
+        pr_debug("Deasserting INIT\n");
 
         /* Target chip */
         /* Send IPI */
@@ -589,14 +580,14 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
         /*
          * Run STARTUP IPI loop.
          */
-        pr_debug("#startup loops: %d.\n", num_starts);
+        pr_debug("#startup loops: %d\n", num_starts);
 
         for (j = 1; j <= num_starts; j++) {
-                pr_debug("Sending STARTUP #%d.\n", j);
+                pr_debug("Sending STARTUP #%d\n", j);
                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP.  */
                         apic_write(APIC_ESR, 0);
                 apic_read(APIC_ESR);
-                pr_debug("After apic_write.\n");
+                pr_debug("After apic_write\n");
 
                 /*
                  * STARTUP IPI
@@ -613,7 +604,7 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
                  */
                 udelay(300);
 
-                pr_debug("Startup point 1.\n");
+                pr_debug("Startup point 1\n");
 
                 pr_debug("Waiting for send to finish...\n");
                 send_status = safe_apic_wait_icr_idle();
@@ -628,12 +619,12 @@ wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
                 if (send_status || accept_status)
                         break;
         }
-        pr_debug("After Startup.\n");
+        pr_debug("After Startup\n");
 
         if (send_status)
-                printk(KERN_ERR "APIC never delivered???\n");
+                pr_err("APIC never delivered???\n");
         if (accept_status)
-                printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
+                pr_err("APIC delivery error (%lx)\n", accept_status);
 
         return (send_status | accept_status);
 }
@@ -647,11 +638,11 @@ static void __cpuinit announce_cpu(int cpu, int apicid)
         if (system_state == SYSTEM_BOOTING) {
                 if (node != current_node) {
                         if (current_node > (-1))
-                                pr_cont(" Ok.\n");
+                                pr_cont(" OK\n");
                         current_node = node;
                         pr_info("Booting Node %3d, Processors ", node);
                 }
-                pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
+                pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " OK\n" : "");
                 return;
         } else
                 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
@@ -731,9 +722,9 @@ static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
                 /*
                  * allow APs to start initializing.
                  */
-                pr_debug("Before Callout %d.\n", cpu);
+                pr_debug("Before Callout %d\n", cpu);
                 cpumask_set_cpu(cpu, cpu_callout_mask);
-                pr_debug("After Callout %d.\n", cpu);
+                pr_debug("After Callout %d\n", cpu);
 
                 /*
                  * Wait 5s total for a response
@@ -761,7 +752,7 @@ static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
                                 pr_err("CPU%d: Stuck ??\n", cpu);
                         else
                                 /* trampoline code not run */
-                                pr_err("CPU%d: Not responding.\n", cpu);
+                                pr_err("CPU%d: Not responding\n", cpu);
                         if (apic->inquire_remote_apic)
                                 apic->inquire_remote_apic(apicid);
                 }
@@ -806,7 +797,7 @@ int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle)
         if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
             !physid_isset(apicid, phys_cpu_present_map) ||
             !apic->apic_id_valid(apicid)) {
-                printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
+                pr_err("%s: bad cpu %d\n", __func__, cpu);
                 return -EINVAL;
         }
 
@@ -887,9 +878,8 @@ static int __init smp_sanity_check(unsigned max_cpus)
                 unsigned int cpu;
                 unsigned nr;
 
-                printk(KERN_WARNING
-                       "More than 8 CPUs detected - skipping them.\n"
-                       "Use CONFIG_X86_BIGSMP.\n");
+                pr_warn("More than 8 CPUs detected - skipping them\n"
+                        "Use CONFIG_X86_BIGSMP\n");
 
                 nr = 0;
                 for_each_present_cpu(cpu) {
@@ -910,8 +900,7 @@ static int __init smp_sanity_check(unsigned max_cpus)
 #endif
 
         if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
-                printk(KERN_WARNING
-                        "weird, boot CPU (#%d) not listed by the BIOS.\n",
+                pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
                         hard_smp_processor_id());
 
                 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
@@ -923,11 +912,10 @@ static int __init smp_sanity_check(unsigned max_cpus)
          */
         if (!smp_found_config && !acpi_lapic) {
                 preempt_enable();
-                printk(KERN_NOTICE "SMP motherboard not detected.\n");
+                pr_notice("SMP motherboard not detected\n");
                 disable_smp();
                 if (APIC_init_uniprocessor())
-                        printk(KERN_NOTICE "Local APIC not detected."
-                                           " Using dummy APIC emulation.\n");
+                        pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
                 return -1;
         }
 
@@ -936,9 +924,8 @@ static int __init smp_sanity_check(unsigned max_cpus)
          * CPU too, but we do it for the sake of robustness anyway.
          */
         if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
-                printk(KERN_NOTICE
-                        "weird, boot CPU (#%d) not listed by the BIOS.\n",
-                        boot_cpu_physical_apicid);
+                pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
+                          boot_cpu_physical_apicid);
                 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
         }
         preempt_enable();
@@ -951,8 +938,7 @@ static int __init smp_sanity_check(unsigned max_cpus)
                 if (!disable_apic) {
                         pr_err("BIOS bug, local APIC #%d not detected!...\n",
                                 boot_cpu_physical_apicid);
-                        pr_err("... forcing use of dummy APIC emulation."
-                                "(tell your hw vendor)\n");
+                        pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
                 }
                 smpboot_clear_io_apic();
                 disable_ioapic_support();
@@ -965,7 +951,7 @@ static int __init smp_sanity_check(unsigned max_cpus)
          * If SMP should be disabled, then really disable it!
          */
         if (!max_cpus) {
-                printk(KERN_INFO "SMP mode deactivated.\n");
+                pr_info("SMP mode deactivated\n");
                 smpboot_clear_io_apic();
 
                 connect_bsp_APIC();
@@ -1017,7 +1003,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
 
 
         if (smp_sanity_check(max_cpus) < 0) {
-                printk(KERN_INFO "SMP disabled\n");
+                pr_info("SMP disabled\n");
                 disable_smp();
                 goto out;
         }
@@ -1055,7 +1041,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
          * Set up local APIC timer on boot CPU.
          */
 
-        printk(KERN_INFO "CPU%d: ", 0);
+        pr_info("CPU%d: ", 0);
         print_cpu_info(&cpu_data(0));
         x86_init.timers.setup_percpu_clockev();
 
@@ -1105,7 +1091,7 @@ void __init native_smp_prepare_boot_cpu(void)
 
 void __init native_smp_cpus_done(unsigned int max_cpus)
 {
-        pr_debug("Boot done.\n");
+        pr_debug("Boot done\n");
 
         nmi_selftest();
         impress_friends();
@@ -1166,8 +1152,7 @@ __init void prefill_possible_map(void)
 
         /* nr_cpu_ids could be reduced via nr_cpus= */
         if (possible > nr_cpu_ids) {
-                printk(KERN_WARNING
-                        "%d Processors exceeds NR_CPUS limit of %d\n",
+                pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
                         possible, nr_cpu_ids);
                 possible = nr_cpu_ids;
         }
@@ -1176,13 +1161,12 @@ __init void prefill_possible_map(void)
         if (!setup_max_cpus)
 #endif
         if (possible > i) {
-                printk(KERN_WARNING
-                        "%d Processors exceeds max_cpus limit of %u\n",
+                pr_warn("%d Processors exceeds max_cpus limit of %u\n",
                         possible, setup_max_cpus);
                 possible = i;
         }
 
-        printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
+        pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
                 possible, max_t(int, possible - num_processors, 0));
 
         for (i = 0; i < possible; i++)
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 05b31d92f69..b481341c936 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -9,6 +9,9 @@
 /*
  * Handle hardware traps and faults.
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/interrupt.h>
 #include <linux/kallsyms.h>
 #include <linux/spinlock.h>
@@ -143,12 +146,11 @@ trap_signal:
 #ifdef CONFIG_X86_64
         if (show_unhandled_signals && unhandled_signal(tsk, signr) &&
             printk_ratelimit()) {
-                printk(KERN_INFO
-                       "%s[%d] trap %s ip:%lx sp:%lx error:%lx",
-                       tsk->comm, tsk->pid, str,
-                       regs->ip, regs->sp, error_code);
+                pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx",
+                        tsk->comm, tsk->pid, str,
+                        regs->ip, regs->sp, error_code);
                 print_vma_addr(" in ", regs->ip);
-                printk("\n");
+                pr_cont("\n");
         }
 #endif
 
@@ -269,12 +271,11 @@ do_general_protection(struct pt_regs *regs, long error_code)
 
         if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) &&
                         printk_ratelimit()) {
-                printk(KERN_INFO
-                        "%s[%d] general protection ip:%lx sp:%lx error:%lx",
+                pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx",
                         tsk->comm, task_pid_nr(tsk),
                         regs->ip, regs->sp, error_code);
                 print_vma_addr(" in ", regs->ip);
-                printk("\n");
+                pr_cont("\n");
         }
 
         force_sig(SIGSEGV, tsk);
@@ -570,7 +571,7 @@ do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
         conditional_sti(regs);
 #if 0
         /* No need to warn about this any longer. */
-        printk(KERN_INFO "Ignoring P6 Local APIC Spurious Interrupt Bug...\n");
+        pr_info("Ignoring P6 Local APIC Spurious Interrupt Bug...\n");
 #endif
 }
 
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index fc0a147e372..cfa5d4f7ca5 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1,3 +1,5 @@
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/init.h>
@@ -84,8 +86,7 @@ EXPORT_SYMBOL_GPL(check_tsc_unstable);
 #ifdef CONFIG_X86_TSC
 int __init notsc_setup(char *str)
 {
-        printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
-                        "cannot disable TSC completely.\n");
+        pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
         tsc_disabled = 1;
         return 1;
 }
@@ -373,7 +374,7 @@ static unsigned long quick_pit_calibrate(void)
                         goto success;
                 }
         }
-        printk("Fast TSC calibration failed\n");
+        pr_err("Fast TSC calibration failed\n");
         return 0;
 
 success:
@@ -392,7 +393,7 @@ success:
          */
         delta *= PIT_TICK_RATE;
         do_div(delta, i*256*1000);
-        printk("Fast TSC calibration using PIT\n");
+        pr_info("Fast TSC calibration using PIT\n");
         return delta;
 }
 
@@ -487,9 +488,8 @@ unsigned long native_calibrate_tsc(void)
                  * use the reference value, as it is more precise.
                  */
                 if (delta >= 90 && delta <= 110) {
-                        printk(KERN_INFO
-                               "TSC: PIT calibration matches %s. %d loops\n",
-                               hpet ? "HPET" : "PMTIMER", i + 1);
+                        pr_info("PIT calibration matches %s. %d loops\n",
+                                hpet ? "HPET" : "PMTIMER", i + 1);
                         return tsc_ref_min;
                 }
 
@@ -511,38 +511,36 @@ unsigned long native_calibrate_tsc(void)
          */
         if (tsc_pit_min == ULONG_MAX) {
                 /* PIT gave no useful value */
-                printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
+                pr_warn("Unable to calibrate against PIT\n");
 
                 /* We don't have an alternative source, disable TSC */
                 if (!hpet && !ref1 && !ref2) {
-                        printk("TSC: No reference (HPET/PMTIMER) available\n");
+                        pr_notice("No reference (HPET/PMTIMER) available\n");
                         return 0;
                 }
 
                 /* The alternative source failed as well, disable TSC */
                 if (tsc_ref_min == ULONG_MAX) {
-                        printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
-                               "failed.\n");
+                        pr_warn("HPET/PMTIMER calibration failed\n");
                         return 0;
                 }
 
                 /* Use the alternative source */
-                printk(KERN_INFO "TSC: using %s reference calibration\n",
-                       hpet ? "HPET" : "PMTIMER");
+                pr_info("using %s reference calibration\n",
+                        hpet ? "HPET" : "PMTIMER");
 
                 return tsc_ref_min;
         }
 
         /* We don't have an alternative source, use the PIT calibration value */
         if (!hpet && !ref1 && !ref2) {
-                printk(KERN_INFO "TSC: Using PIT calibration value\n");
+                pr_info("Using PIT calibration value\n");
                 return tsc_pit_min;
         }
 
         /* The alternative source failed, use the PIT calibration value */
         if (tsc_ref_min == ULONG_MAX) {
-                printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
-                       "Using PIT calibration\n");
+                pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
                 return tsc_pit_min;
         }
 
@@ -551,9 +549,9 @@ unsigned long native_calibrate_tsc(void)
          * the PIT value as we know that there are PMTIMERs around
          * running at double speed. At least we let the user know:
          */
-        printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
-               hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
-        printk(KERN_INFO "TSC: Using PIT calibration value\n");
+        pr_warn("PIT calibration deviates from %s: %lu %lu\n",
+                hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
+        pr_info("Using PIT calibration value\n");
         return tsc_pit_min;
 }
 
@@ -785,7 +783,7 @@ void mark_tsc_unstable(char *reason)
                 tsc_unstable = 1;
                 sched_clock_stable = 0;
                 disable_sched_clock_irqtime();
-                printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
+                pr_info("Marking TSC unstable due to %s\n", reason);
                 /* Change only the rating, when not registered */
                 if (clocksource_tsc.mult)
                         clocksource_mark_unstable(&clocksource_tsc);
@@ -912,9 +910,9 @@ static void tsc_refine_calibration_work(struct work_struct *work)
                 goto out;
 
         tsc_khz = freq;
-        printk(KERN_INFO "Refined TSC clocksource calibration: "
-                "%lu.%03lu MHz.\n", (unsigned long)tsc_khz / 1000,
-                                        (unsigned long)tsc_khz % 1000);
+        pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
+                (unsigned long)tsc_khz / 1000,
+                (unsigned long)tsc_khz % 1000);
 
 out:
         clocksource_register_khz(&clocksource_tsc, tsc_khz);
@@ -970,9 +968,9 @@ void __init tsc_init(void)
                 return;
         }
 
-        printk("Detected %lu.%03lu MHz processor.\n",
-                        (unsigned long)cpu_khz / 1000,
-                        (unsigned long)cpu_khz % 1000);
+        pr_info("Detected %lu.%03lu MHz processor\n",
+                (unsigned long)cpu_khz / 1000,
+                (unsigned long)cpu_khz % 1000);
 
         /*
          * Secondary CPUs do not run through tsc_init(), so set up
diff --git a/arch/x86/kernel/uprobes.c b/arch/x86/kernel/uprobes.c
index dc4e910a7d9..36fd42091fa 100644
--- a/arch/x86/kernel/uprobes.c
+++ b/arch/x86/kernel/uprobes.c
@@ -409,9 +409,10 @@ static int validate_insn_bits(struct arch_uprobe *auprobe, struct mm_struct *mm,
  * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
  * @mm: the probed address space.
  * @arch_uprobe: the probepoint information.
+ * @addr: virtual address at which to install the probepoint
  * Return 0 on success or a -ve number on error.
  */
-int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm)
+int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr)
 {
         int ret;
         struct insn insn;
diff --git a/arch/x86/kernel/vm86_32.c b/arch/x86/kernel/vm86_32.c
index 255f58ae71e..54abcc0baf2 100644
--- a/arch/x86/kernel/vm86_32.c
+++ b/arch/x86/kernel/vm86_32.c
@@ -28,6 +28,8 @@
  *
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/capability.h>
 #include <linux/errno.h>
 #include <linux/interrupt.h>
@@ -137,14 +139,14 @@ struct pt_regs *save_v86_state(struct kernel_vm86_regs *regs)
         local_irq_enable();
 
         if (!current->thread.vm86_info) {
-                printk("no vm86_info: BAD\n");
+                pr_alert("no vm86_info: BAD\n");
                 do_exit(SIGSEGV);
         }
         set_flags(regs->pt.flags, VEFLAGS, X86_EFLAGS_VIF | current->thread.v86mask);
         tmp = copy_vm86_regs_to_user(&current->thread.vm86_info->regs, regs);
         tmp += put_user(current->thread.screen_bitmap, &current->thread.vm86_info->screen_bitmap);
         if (tmp) {
-                printk("vm86: could not access userspace vm86_info\n");
+                pr_alert("could not access userspace vm86_info\n");
                 do_exit(SIGSEGV);
         }
 
diff --git a/arch/x86/kernel/vsmp_64.c b/arch/x86/kernel/vsmp_64.c
index 8eeb55a551b..992f890283e 100644
--- a/arch/x86/kernel/vsmp_64.c
+++ b/arch/x86/kernel/vsmp_64.c
@@ -16,6 +16,7 @@
 #include <linux/pci_ids.h>
 #include <linux/pci_regs.h>
 #include <linux/smp.h>
+#include <linux/irq.h>
 
 #include <asm/apic.h>
 #include <asm/pci-direct.h>
@@ -95,6 +96,18 @@ static void __init set_vsmp_pv_ops(void)
         ctl = readl(address + 4);
         printk(KERN_INFO "vSMP CTL: capabilities:0x%08x  control:0x%08x\n",
                cap, ctl);
+
+        /* If possible, let the vSMP foundation route the interrupt optimally */
+#ifdef CONFIG_SMP
+        if (cap & ctl & BIT(8)) {
+                ctl &= ~BIT(8);
+#ifdef CONFIG_PROC_FS
+                /* Don't let users change irq affinity via procfs */
+                no_irq_affinity = 1;
+#endif
+        }
+#endif
+
         if (cap & ctl & (1 << 4)) {
                 /* Setup irq ops and turn on vSMP  IRQ fastpath handling */
                 pv_irq_ops.irq_disable = PV_CALLEE_SAVE(vsmp_irq_disable);
@@ -102,12 +115,11 @@ static void __init set_vsmp_pv_ops(void)
                 pv_irq_ops.save_fl  = PV_CALLEE_SAVE(vsmp_save_fl);
                 pv_irq_ops.restore_fl  = PV_CALLEE_SAVE(vsmp_restore_fl);
                 pv_init_ops.patch = vsmp_patch;
-
                 ctl &= ~(1 << 4);
-                writel(ctl, address + 4);
-                ctl = readl(address + 4);
-                printk(KERN_INFO "vSMP CTL: control set to:0x%08x\n", ctl);
         }
+        writel(ctl, address + 4);
+        ctl = readl(address + 4);
+        pr_info("vSMP CTL: control set to:0x%08x\n", ctl);
 
         early_iounmap(address, 8);
 }
@@ -187,12 +199,36 @@ static void __init vsmp_cap_cpus(void)
 #endif
 }
 
+static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
+{
+        return hard_smp_processor_id() >> index_msb;
+}
+
+/*
+ * In vSMP, all cpus should be capable of handling interrupts, regardless of
+ * the APIC used.
+ */
+static void fill_vector_allocation_domain(int cpu, struct cpumask *retmask,
+                                          const struct cpumask *mask)
+{
+        cpumask_setall(retmask);
+}
+
+static void vsmp_apic_post_init(void)
+{
+        /* need to update phys_pkg_id */
+        apic->phys_pkg_id = apicid_phys_pkg_id;
+        apic->vector_allocation_domain = fill_vector_allocation_domain;
+}
+
 void __init vsmp_init(void)
 {
         detect_vsmp_box();
         if (!is_vsmp_box())
                 return;
 
+        x86_platform.apic_post_init = vsmp_apic_post_init;
+
         vsmp_cap_cpus();
 
         set_vsmp_pv_ops();
diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c
index 5db36caf428..8d141b30904 100644
--- a/arch/x86/kernel/vsyscall_64.c
+++ b/arch/x86/kernel/vsyscall_64.c
@@ -18,6 +18,8 @@
  *  use the vDSO.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/time.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -111,18 +113,13 @@ void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
 static void warn_bad_vsyscall(const char *level, struct pt_regs *regs,
                               const char *message)
 {
-        static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, DEFAULT_RATELIMIT_BURST);
-        struct task_struct *tsk;
-
-        if (!show_unhandled_signals || !__ratelimit(&rs))
+        if (!show_unhandled_signals)
                 return;
 
-        tsk = current;
-
-        printk("%s%s[%d] %s ip:%lx cs:%lx sp:%lx ax:%lx si:%lx di:%lx\n",
-               level, tsk->comm, task_pid_nr(tsk),
-               message, regs->ip, regs->cs,
-               regs->sp, regs->ax, regs->si, regs->di);
+        pr_notice_ratelimited("%s%s[%d] %s ip:%lx cs:%lx sp:%lx ax:%lx si:%lx di:%lx\n",
+                              level, current->comm, task_pid_nr(current),
+                              message, regs->ip, regs->cs,
+                              regs->sp, regs->ax, regs->si, regs->di);
 }
 
 static int addr_to_vsyscall_nr(unsigned long addr)
diff --git a/arch/x86/kernel/x8664_ksyms_64.c b/arch/x86/kernel/x8664_ksyms_64.c
index 9796c2f3d07..6020f6f5927 100644
--- a/arch/x86/kernel/x8664_ksyms_64.c
+++ b/arch/x86/kernel/x8664_ksyms_64.c
@@ -28,6 +28,7 @@ EXPORT_SYMBOL(__put_user_8);
 
 EXPORT_SYMBOL(copy_user_generic_string);
 EXPORT_SYMBOL(copy_user_generic_unrolled);
+EXPORT_SYMBOL(copy_user_enhanced_fast_string);
 EXPORT_SYMBOL(__copy_user_nocache);
 EXPORT_SYMBOL(_copy_from_user);
 EXPORT_SYMBOL(_copy_to_user);
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index 35c5e543f55..7a3d075a814 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -26,10 +26,8 @@
 
 void __cpuinit x86_init_noop(void) { }
 void __init x86_init_uint_noop(unsigned int unused) { }
-void __init x86_init_pgd_noop(pgd_t *unused) { }
 int __init iommu_init_noop(void) { return 0; }
 void iommu_shutdown_noop(void) { }
-void wallclock_init_noop(void) { }
 
 /*
  * The platform setup functions are preset with the default functions
@@ -69,8 +67,7 @@ struct x86_init_ops x86_init __initdata = {
         },
 
         .paging = {
-                .pagetable_setup_start  = native_pagetable_setup_start,
-                .pagetable_setup_done   = native_pagetable_setup_done,
+                .pagetable_init         = native_pagetable_init,
         },
 
         .timers = {
@@ -101,7 +98,6 @@ static int default_i8042_detect(void) { return 1; };
 
 struct x86_platform_ops x86_platform = {
         .calibrate_tsc                  = native_calibrate_tsc,
-        .wallclock_init                 = wallclock_init_noop,
         .get_wallclock                  = mach_get_cmos_time,
         .set_wallclock                  = mach_set_rtc_mmss,
         .iommu_shutdown                 = iommu_shutdown_noop,
diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c
index bd18149b2b0..3d3e2070911 100644
--- a/arch/x86/kernel/xsave.c
+++ b/arch/x86/kernel/xsave.c
@@ -3,6 +3,9 @@
  *
  * Author: Suresh Siddha <suresh.b.siddha@intel.com>
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/bootmem.h>
 #include <linux/compat.h>
 #include <asm/i387.h>
@@ -162,7 +165,7 @@ int save_i387_xstate(void __user *buf)
         BUG_ON(sig_xstate_size < xstate_size);
 
         if ((unsigned long)buf % 64)
-                printk("save_i387_xstate: bad fpstate %p\n", buf);
+                pr_err("%s: bad fpstate %p\n", __func__, buf);
 
         if (!used_math())
                 return 0;
@@ -422,7 +425,7 @@ static void __init xstate_enable_boot_cpu(void)
         pcntxt_mask = eax + ((u64)edx << 32);
 
         if ((pcntxt_mask & XSTATE_FPSSE) != XSTATE_FPSSE) {
-                printk(KERN_ERR "FP/SSE not shown under xsave features 0x%llx\n",
+                pr_err("FP/SSE not shown under xsave features 0x%llx\n",
                        pcntxt_mask);
                 BUG();
         }
@@ -445,9 +448,8 @@ static void __init xstate_enable_boot_cpu(void)
 
         setup_xstate_init();
 
-        printk(KERN_INFO "xsave/xrstor: enabled xstate_bv 0x%llx, "
-               "cntxt size 0x%x\n",
-               pcntxt_mask, xstate_size);
+        pr_info("enabled xstate_bv 0x%llx, cntxt size 0x%x\n",
+                pcntxt_mask, xstate_size);
 }
 
 /*
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 7df1c6d839f..0595f1397b7 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -201,6 +201,7 @@ static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
         unsigned f_lm = 0;
 #endif
         unsigned f_rdtscp = kvm_x86_ops->rdtscp_supported() ? F(RDTSCP) : 0;
+        unsigned f_invpcid = kvm_x86_ops->invpcid_supported() ? F(INVPCID) : 0;
 
         /* cpuid 1.edx */
         const u32 kvm_supported_word0_x86_features =
@@ -228,7 +229,7 @@ static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
                 0 /* DS-CPL, VMX, SMX, EST */ |
                 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
                 F(FMA) | F(CX16) | 0 /* xTPR Update, PDCM */ |
-                0 /* Reserved, DCA */ | F(XMM4_1) |
+                F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
                 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
                 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
                 F(F16C) | F(RDRAND);
@@ -248,7 +249,7 @@ static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
         /* cpuid 7.0.ebx */
         const u32 kvm_supported_word9_x86_features =
                 F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) |
-                F(BMI2) | F(ERMS) | F(RTM);
+                F(BMI2) | F(ERMS) | f_invpcid | F(RTM);
 
         /* all calls to cpuid_count() should be made on the same cpu */
         get_cpu();
@@ -409,6 +410,7 @@ static int do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
                              (1 << KVM_FEATURE_NOP_IO_DELAY) |
                              (1 << KVM_FEATURE_CLOCKSOURCE2) |
                              (1 << KVM_FEATURE_ASYNC_PF) |
+                             (1 << KVM_FEATURE_PV_EOI) |
                              (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
 
                 if (sched_info_on())
@@ -639,33 +641,37 @@ static struct kvm_cpuid_entry2* check_cpuid_limit(struct kvm_vcpu *vcpu,
         return kvm_find_cpuid_entry(vcpu, maxlevel->eax, index);
 }
 
-void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
+void kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
 {
-        u32 function, index;
+        u32 function = *eax, index = *ecx;
         struct kvm_cpuid_entry2 *best;
 
-        function = kvm_register_read(vcpu, VCPU_REGS_RAX);
-        index = kvm_register_read(vcpu, VCPU_REGS_RCX);
-        kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
-        kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
-        kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
-        kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
         best = kvm_find_cpuid_entry(vcpu, function, index);
 
         if (!best)
                 best = check_cpuid_limit(vcpu, function, index);
 
         if (best) {
-                kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
-                kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
-                kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
-                kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
-        }
+                *eax = best->eax;
+                *ebx = best->ebx;
+                *ecx = best->ecx;
+                *edx = best->edx;
+        } else
+                *eax = *ebx = *ecx = *edx = 0;
+}
+
+void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
+{
+        u32 function, eax, ebx, ecx, edx;
+
+        function = eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
+        ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
+        kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx);
+        kvm_register_write(vcpu, VCPU_REGS_RAX, eax);
+        kvm_register_write(vcpu, VCPU_REGS_RBX, ebx);
+        kvm_register_write(vcpu, VCPU_REGS_RCX, ecx);
+        kvm_register_write(vcpu, VCPU_REGS_RDX, edx);
         kvm_x86_ops->skip_emulated_instruction(vcpu);
-        trace_kvm_cpuid(function,
-                        kvm_register_read(vcpu, VCPU_REGS_RAX),
-                        kvm_register_read(vcpu, VCPU_REGS_RBX),
-                        kvm_register_read(vcpu, VCPU_REGS_RCX),
-                        kvm_register_read(vcpu, VCPU_REGS_RDX));
+        trace_kvm_cpuid(function, eax, ebx, ecx, edx);
 }
 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
diff --git a/arch/x86/kvm/cpuid.h b/arch/x86/kvm/cpuid.h
index 26d1fb437eb..a10e4601685 100644
--- a/arch/x86/kvm/cpuid.h
+++ b/arch/x86/kvm/cpuid.h
@@ -17,6 +17,7 @@ int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
                               struct kvm_cpuid2 *cpuid,
                               struct kvm_cpuid_entry2 __user *entries);
+void kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, u32 *ecx, u32 *edx);
 
 
 static inline bool guest_cpuid_has_xsave(struct kvm_vcpu *vcpu)
@@ -51,4 +52,12 @@ static inline bool guest_cpuid_has_osvw(struct kvm_vcpu *vcpu)
         return best && (best->ecx & bit(X86_FEATURE_OSVW));
 }
 
+static inline bool guest_cpuid_has_pcid(struct kvm_vcpu *vcpu)
+{
+        struct kvm_cpuid_entry2 *best;
+
+        best = kvm_find_cpuid_entry(vcpu, 1, 0);
+        return best && (best->ecx & bit(X86_FEATURE_PCID));
+}
+
 #endif
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index f95d242ee9f..a3b57a27be8 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -433,11 +433,32 @@ static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
         return ctxt->ops->intercept(ctxt, &info, stage);
 }
 
+static void assign_masked(ulong *dest, ulong src, ulong mask)
+{
+        *dest = (*dest & ~mask) | (src & mask);
+}
+
 static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
 {
         return (1UL << (ctxt->ad_bytes << 3)) - 1;
 }
 
+static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
+{
+        u16 sel;
+        struct desc_struct ss;
+
+        if (ctxt->mode == X86EMUL_MODE_PROT64)
+                return ~0UL;
+        ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
+        return ~0U >> ((ss.d ^ 1) * 16);  /* d=0: 0xffff; d=1: 0xffffffff */
+}
+
+static int stack_size(struct x86_emulate_ctxt *ctxt)
+{
+        return (__fls(stack_mask(ctxt)) + 1) >> 3;
+}
+
 /* Access/update address held in a register, based on addressing mode. */
 static inline unsigned long
 address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
@@ -454,13 +475,26 @@ register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
         return address_mask(ctxt, reg);
 }
 
+static void masked_increment(ulong *reg, ulong mask, int inc)
+{
+        assign_masked(reg, *reg + inc, mask);
+}
+
 static inline void
 register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
 {
+        ulong mask;
+
         if (ctxt->ad_bytes == sizeof(unsigned long))
-                *reg += inc;
+                mask = ~0UL;
         else
-                *reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
+                mask = ad_mask(ctxt);
+        masked_increment(reg, mask, inc);
+}
+
+static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
+{
+        masked_increment(&ctxt->regs[VCPU_REGS_RSP], stack_mask(ctxt), inc);
 }
 
 static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
@@ -958,6 +992,12 @@ static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
         op->orig_val = op->val;
 }
 
+static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
+{
+        if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
+                ctxt->modrm_seg = VCPU_SREG_SS;
+}
+
 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
                         struct operand *op)
 {
@@ -1061,15 +1101,20 @@ static int decode_modrm(struct x86_emulate_ctxt *ctxt,
 
                         if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
                                 modrm_ea += insn_fetch(s32, ctxt);
-                        else
+                        else {
                                 modrm_ea += ctxt->regs[base_reg];
+                                adjust_modrm_seg(ctxt, base_reg);
+                        }
                         if (index_reg != 4)
                                 modrm_ea += ctxt->regs[index_reg] << scale;
                 } else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
                         if (ctxt->mode == X86EMUL_MODE_PROT64)
                                 ctxt->rip_relative = 1;
-                } else
-                        modrm_ea += ctxt->regs[ctxt->modrm_rm];
+                } else {
+                        base_reg = ctxt->modrm_rm;
+                        modrm_ea += ctxt->regs[base_reg];
+                        adjust_modrm_seg(ctxt, base_reg);
+                }
                 switch (ctxt->modrm_mod) {
                 case 0:
                         if (ctxt->modrm_rm == 5)
@@ -1264,7 +1309,8 @@ static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
 
 /* allowed just for 8 bytes segments */
 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
-                                   u16 selector, struct desc_struct *desc)
+                                   u16 selector, struct desc_struct *desc,
+                                   ulong *desc_addr_p)
 {
         struct desc_ptr dt;
         u16 index = selector >> 3;
@@ -1275,7 +1321,7 @@ static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
         if (dt.size < index * 8 + 7)
                 return emulate_gp(ctxt, selector & 0xfffc);
 
-        addr = dt.address + index * 8;
+        *desc_addr_p = addr = dt.address + index * 8;
         return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
                                    &ctxt->exception);
 }
@@ -1302,11 +1348,12 @@ static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
                                    u16 selector, int seg)
 {
-        struct desc_struct seg_desc;
+        struct desc_struct seg_desc, old_desc;
         u8 dpl, rpl, cpl;
         unsigned err_vec = GP_VECTOR;
         u32 err_code = 0;
         bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
+        ulong desc_addr;
         int ret;
 
         memset(&seg_desc, 0, sizeof seg_desc);
@@ -1324,8 +1371,14 @@ static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
                 goto load;
         }
 
-        /* NULL selector is not valid for TR, CS and SS */
-        if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
+        rpl = selector & 3;
+        cpl = ctxt->ops->cpl(ctxt);
+
+        /* NULL selector is not valid for TR, CS and SS (except for long mode) */
+        if ((seg == VCPU_SREG_CS
+             || (seg == VCPU_SREG_SS
+                 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
+             || seg == VCPU_SREG_TR)
             && null_selector)
                 goto exception;
 
@@ -1336,7 +1389,7 @@ static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
         if (null_selector) /* for NULL selector skip all following checks */
                 goto load;
 
-        ret = read_segment_descriptor(ctxt, selector, &seg_desc);
+        ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
         if (ret != X86EMUL_CONTINUE)
                 return ret;
 
@@ -1352,9 +1405,7 @@ static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
                 goto exception;
         }
 
-        rpl = selector & 3;
         dpl = seg_desc.dpl;
-        cpl = ctxt->ops->cpl(ctxt);
 
         switch (seg) {
         case VCPU_SREG_SS:
@@ -1384,6 +1435,12 @@ static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
         case VCPU_SREG_TR:
                 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
                         goto exception;
+                old_desc = seg_desc;
+                seg_desc.type |= 2; /* busy */
+                ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
+                                                  sizeof(seg_desc), &ctxt->exception);
+                if (ret != X86EMUL_CONTINUE)
+                        return ret;
                 break;
         case VCPU_SREG_LDTR:
                 if (seg_desc.s || seg_desc.type != 2)
@@ -1474,17 +1531,22 @@ static int writeback(struct x86_emulate_ctxt *ctxt)
         return X86EMUL_CONTINUE;
 }
 
-static int em_push(struct x86_emulate_ctxt *ctxt)
+static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
 {
         struct segmented_address addr;
 
-        register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
-        addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
+        rsp_increment(ctxt, -bytes);
+        addr.ea = ctxt->regs[VCPU_REGS_RSP] & stack_mask(ctxt);
         addr.seg = VCPU_SREG_SS;
 
+        return segmented_write(ctxt, addr, data, bytes);
+}
+
+static int em_push(struct x86_emulate_ctxt *ctxt)
+{
         /* Disable writeback. */
         ctxt->dst.type = OP_NONE;
-        return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
+        return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
 }
 
 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
@@ -1493,13 +1555,13 @@ static int emulate_pop(struct x86_emulate_ctxt *ctxt,
         int rc;
         struct segmented_address addr;
 
-        addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
+        addr.ea = ctxt->regs[VCPU_REGS_RSP] & stack_mask(ctxt);
         addr.seg = VCPU_SREG_SS;
         rc = segmented_read(ctxt, addr, dest, len);
         if (rc != X86EMUL_CONTINUE)
                 return rc;
 
-        register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
+        rsp_increment(ctxt, len);
         return rc;
 }
 
@@ -1556,6 +1618,33 @@ static int em_popf(struct x86_emulate_ctxt *ctxt)
         return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
 }
 
+static int em_enter(struct x86_emulate_ctxt *ctxt)
+{
+        int rc;
+        unsigned frame_size = ctxt->src.val;
+        unsigned nesting_level = ctxt->src2.val & 31;
+
+        if (nesting_level)
+                return X86EMUL_UNHANDLEABLE;
+
+        rc = push(ctxt, &ctxt->regs[VCPU_REGS_RBP], stack_size(ctxt));
+        if (rc != X86EMUL_CONTINUE)
+                return rc;
+        assign_masked(&ctxt->regs[VCPU_REGS_RBP], ctxt->regs[VCPU_REGS_RSP],
+                      stack_mask(ctxt));
+        assign_masked(&ctxt->regs[VCPU_REGS_RSP],
+                      ctxt->regs[VCPU_REGS_RSP] - frame_size,
+                      stack_mask(ctxt));
+        return X86EMUL_CONTINUE;
+}
+
+static int em_leave(struct x86_emulate_ctxt *ctxt)
+{
+        assign_masked(&ctxt->regs[VCPU_REGS_RSP], ctxt->regs[VCPU_REGS_RBP],
+                      stack_mask(ctxt));
+        return emulate_pop(ctxt, &ctxt->regs[VCPU_REGS_RBP], ctxt->op_bytes);
+}
+
 static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
 {
         int seg = ctxt->src2.val;
@@ -1612,8 +1701,7 @@ static int em_popa(struct x86_emulate_ctxt *ctxt)
 
         while (reg >= VCPU_REGS_RAX) {
                 if (reg == VCPU_REGS_RSP) {
-                        register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
-                                                        ctxt->op_bytes);
+                        rsp_increment(ctxt, ctxt->op_bytes);
                         --reg;
                 }
 
@@ -1993,8 +2081,8 @@ static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
         u32 eax, ebx, ecx, edx;
 
         eax = ecx = 0;
-        return ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)
-                && ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
+        ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
+        return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
                 && ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
                 && edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
 }
@@ -2013,32 +2101,31 @@ static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
 
         eax = 0x00000000;
         ecx = 0x00000000;
-        if (ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx)) {
-                /*
-                 * Intel ("GenuineIntel")
-                 * remark: Intel CPUs only support "syscall" in 64bit
-                 * longmode. Also an 64bit guest with a
-                 * 32bit compat-app running will #UD !! While this
-                 * behaviour can be fixed (by emulating) into AMD
-                 * response - CPUs of AMD can't behave like Intel.
-                 */
-                if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
-                    ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
-                    edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
-                        return false;
+        ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
+        /*
+         * Intel ("GenuineIntel")
+         * remark: Intel CPUs only support "syscall" in 64bit
+         * longmode. Also an 64bit guest with a
+         * 32bit compat-app running will #UD !! While this
+         * behaviour can be fixed (by emulating) into AMD
+         * response - CPUs of AMD can't behave like Intel.
+         */
+        if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
+            ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
+            edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
+                return false;
 
-                /* AMD ("AuthenticAMD") */
-                if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
-                    ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
-                    edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
-                        return true;
-
-                /* AMD ("AMDisbetter!") */
-                if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
-                    ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
-                    edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
-                        return true;
-        }
+        /* AMD ("AuthenticAMD") */
+        if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
+            ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
+            edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
+                return true;
+
+        /* AMD ("AMDisbetter!") */
+        if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
+            ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
+            edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
+                return true;
 
         /* default: (not Intel, not AMD), apply Intel's stricter rules... */
         return false;
@@ -2547,13 +2634,14 @@ static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
         ulong old_tss_base =
                 ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
         u32 desc_limit;
+        ulong desc_addr;
 
         /* FIXME: old_tss_base == ~0 ? */
 
-        ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
+        ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
         if (ret != X86EMUL_CONTINUE)
                 return ret;
-        ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
+        ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
         if (ret != X86EMUL_CONTINUE)
                 return ret;
 
@@ -2749,7 +2837,7 @@ static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
         rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
         if (rc != X86EMUL_CONTINUE)
                 return rc;
-        register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
+        rsp_increment(ctxt, ctxt->src.val);
         return X86EMUL_CONTINUE;
 }
 
@@ -2948,6 +3036,24 @@ static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
         return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
 }
 
+static int em_lldt(struct x86_emulate_ctxt *ctxt)
+{
+        u16 sel = ctxt->src.val;
+
+        /* Disable writeback. */
+        ctxt->dst.type = OP_NONE;
+        return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
+}
+
+static int em_ltr(struct x86_emulate_ctxt *ctxt)
+{
+        u16 sel = ctxt->src.val;
+
+        /* Disable writeback. */
+        ctxt->dst.type = OP_NONE;
+        return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
+}
+
 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
 {
         int rc;
@@ -2989,11 +3095,42 @@ static int em_vmcall(struct x86_emulate_ctxt *ctxt)
         return X86EMUL_CONTINUE;
 }
 
+static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
+                                  void (*get)(struct x86_emulate_ctxt *ctxt,
+                                              struct desc_ptr *ptr))
+{
+        struct desc_ptr desc_ptr;
+
+        if (ctxt->mode == X86EMUL_MODE_PROT64)
+                ctxt->op_bytes = 8;
+        get(ctxt, &desc_ptr);
+        if (ctxt->op_bytes == 2) {
+                ctxt->op_bytes = 4;
+                desc_ptr.address &= 0x00ffffff;
+        }
+        /* Disable writeback. */
+        ctxt->dst.type = OP_NONE;
+        return segmented_write(ctxt, ctxt->dst.addr.mem,
+                               &desc_ptr, 2 + ctxt->op_bytes);
+}
+
+static int em_sgdt(struct x86_emulate_ctxt *ctxt)
+{
+        return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
+}
+
+static int em_sidt(struct x86_emulate_ctxt *ctxt)
+{
+        return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
+}
+
 static int em_lgdt(struct x86_emulate_ctxt *ctxt)
 {
         struct desc_ptr desc_ptr;
         int rc;
 
+        if (ctxt->mode == X86EMUL_MODE_PROT64)
+                ctxt->op_bytes = 8;
         rc = read_descriptor(ctxt, ctxt->src.addr.mem,
                              &desc_ptr.size, &desc_ptr.address,
                              ctxt->op_bytes);
@@ -3021,6 +3158,8 @@ static int em_lidt(struct x86_emulate_ctxt *ctxt)
         struct desc_ptr desc_ptr;
         int rc;
 
+        if (ctxt->mode == X86EMUL_MODE_PROT64)
+                ctxt->op_bytes = 8;
         rc = read_descriptor(ctxt, ctxt->src.addr.mem,
                              &desc_ptr.size, &desc_ptr.address,
                              ctxt->op_bytes);
@@ -3143,6 +3282,42 @@ static int em_bsr(struct x86_emulate_ctxt *ctxt)
         return X86EMUL_CONTINUE;
 }
 
+static int em_cpuid(struct x86_emulate_ctxt *ctxt)
+{
+        u32 eax, ebx, ecx, edx;
+
+        eax = ctxt->regs[VCPU_REGS_RAX];
+        ecx = ctxt->regs[VCPU_REGS_RCX];
+        ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
+        ctxt->regs[VCPU_REGS_RAX] = eax;
+        ctxt->regs[VCPU_REGS_RBX] = ebx;
+        ctxt->regs[VCPU_REGS_RCX] = ecx;
+        ctxt->regs[VCPU_REGS_RDX] = edx;
+        return X86EMUL_CONTINUE;
+}
+
+static int em_lahf(struct x86_emulate_ctxt *ctxt)
+{
+        ctxt->regs[VCPU_REGS_RAX] &= ~0xff00UL;
+        ctxt->regs[VCPU_REGS_RAX] |= (ctxt->eflags & 0xff) << 8;
+        return X86EMUL_CONTINUE;
+}
+
+static int em_bswap(struct x86_emulate_ctxt *ctxt)
+{
+        switch (ctxt->op_bytes) {
+#ifdef CONFIG_X86_64
+        case 8:
+                asm("bswap %0" : "+r"(ctxt->dst.val));
+                break;
+#endif
+        default:
+                asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
+                break;
+        }
+        return X86EMUL_CONTINUE;
+}
+
 static bool valid_cr(int nr)
 {
         switch (nr) {
@@ -3424,14 +3599,14 @@ static struct opcode group5[] = {
 static struct opcode group6[] = {
         DI(Prot,        sldt),
         DI(Prot,        str),
-        DI(Prot | Priv, lldt),
-        DI(Prot | Priv, ltr),
+        II(Prot | Priv | SrcMem16, em_lldt, lldt),
+        II(Prot | Priv | SrcMem16, em_ltr, ltr),
         N, N, N, N,
 };
 
 static struct group_dual group7 = { {
-        DI(Mov | DstMem | Priv,                 sgdt),
-        DI(Mov | DstMem | Priv,                 sidt),
+        II(Mov | DstMem | Priv,                 em_sgdt, sgdt),
+        II(Mov | DstMem | Priv,                 em_sidt, sidt),
         II(SrcMem | Priv,                       em_lgdt, lgdt),
         II(SrcMem | Priv,                       em_lidt, lidt),
         II(SrcNone | DstMem | Mov,              em_smsw, smsw), N,
@@ -3538,7 +3713,7 @@ static struct opcode opcode_table[256] = {
         D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
         I(SrcImmFAddr | No64, em_call_far), N,
         II(ImplicitOps | Stack, em_pushf, pushf),
-        II(ImplicitOps | Stack, em_popf, popf), N, N,
+        II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
         /* 0xA0 - 0xA7 */
         I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
         I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
@@ -3561,7 +3736,8 @@ static struct opcode opcode_table[256] = {
         I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
         G(ByteOp, group11), G(0, group11),
         /* 0xC8 - 0xCF */
-        N, N, N, I(ImplicitOps | Stack, em_ret_far),
+        I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
+        N, I(ImplicitOps | Stack, em_ret_far),
         D(ImplicitOps), DI(SrcImmByte, intn),
         D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
         /* 0xD0 - 0xD7 */
@@ -3635,7 +3811,7 @@ static struct opcode twobyte_table[256] = {
         X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
         /* 0xA0 - 0xA7 */
         I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
-        DI(ImplicitOps, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
+        II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
         D(DstMem | SrcReg | Src2ImmByte | ModRM),
         D(DstMem | SrcReg | Src2CL | ModRM), N, N,
         /* 0xA8 - 0xAF */
@@ -3658,11 +3834,12 @@ static struct opcode twobyte_table[256] = {
         I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
         I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
         D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
-        /* 0xC0 - 0xCF */
+        /* 0xC0 - 0xC7 */
         D2bv(DstMem | SrcReg | ModRM | Lock),
         N, D(DstMem | SrcReg | ModRM | Mov),
         N, N, N, GD(0, &group9),
-        N, N, N, N, N, N, N, N,
+        /* 0xC8 - 0xCF */
+        X8(I(DstReg, em_bswap)),
         /* 0xD0 - 0xDF */
         N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
         /* 0xE0 - 0xEF */
@@ -4426,12 +4603,12 @@ twobyte_insn:
                 break;
         case 0xb6 ... 0xb7:     /* movzx */
                 ctxt->dst.bytes = ctxt->op_bytes;
-                ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
+                ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
                                                        : (u16) ctxt->src.val;
                 break;
         case 0xbe ... 0xbf:     /* movsx */
                 ctxt->dst.bytes = ctxt->op_bytes;
-                ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
+                ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
                                                         (s16) ctxt->src.val;
                 break;
         case 0xc0 ... 0xc1:     /* xadd */
diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
index 81cf4fa4a2b..e498b18f010 100644
--- a/arch/x86/kvm/i8259.c
+++ b/arch/x86/kvm/i8259.c
@@ -188,14 +188,15 @@ void kvm_pic_update_irq(struct kvm_pic *s)
         pic_unlock(s);
 }
 
-int kvm_pic_set_irq(void *opaque, int irq, int level)
+int kvm_pic_set_irq(struct kvm_pic *s, int irq, int irq_source_id, int level)
 {
-        struct kvm_pic *s = opaque;
         int ret = -1;
 
         pic_lock(s);
         if (irq >= 0 && irq < PIC_NUM_PINS) {
-                ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
+                int irq_level = __kvm_irq_line_state(&s->irq_states[irq],
+                                                     irq_source_id, level);
+                ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);
                 pic_update_irq(s);
                 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
                                       s->pics[irq >> 3].imr, ret == 0);
@@ -205,6 +206,16 @@ int kvm_pic_set_irq(void *opaque, int irq, int level)
         return ret;
 }
 
+void kvm_pic_clear_all(struct kvm_pic *s, int irq_source_id)
+{
+        int i;
+
+        pic_lock(s);
+        for (i = 0; i < PIC_NUM_PINS; i++)
+                __clear_bit(irq_source_id, &s->irq_states[i]);
+        pic_unlock(s);
+}
+
 /*
  * acknowledge interrupt 'irq'
  */
@@ -305,6 +316,11 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)
         addr &= 1;
         if (addr == 0) {
                 if (val & 0x10) {
+                        u8 edge_irr = s->irr & ~s->elcr;
+                        int i;
+                        bool found;
+                        struct kvm_vcpu *vcpu;
+
                         s->init4 = val & 1;
                         s->last_irr = 0;
                         s->irr &= s->elcr;
@@ -322,6 +338,18 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)
                         if (val & 0x08)
                                 pr_pic_unimpl(
                                         "level sensitive irq not supported");
+
+                        kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)
+                                if (kvm_apic_accept_pic_intr(vcpu)) {
+                                        found = true;
+                                        break;
+                                }
+
+
+                        if (found)
+                                for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
+                                        if (edge_irr & (1 << irq))
+                                                pic_clear_isr(s, irq);
                 } else if (val & 0x08) {
                         if (val & 0x04)
                                 s->poll = 1;
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 93c15743f1e..ce878788a39 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -107,6 +107,16 @@ static inline void apic_clear_vector(int vec, void *bitmap)
         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
 }
 
+static inline int __apic_test_and_set_vector(int vec, void *bitmap)
+{
+        return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
+}
+
+static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
+{
+        return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
+}
+
 static inline int apic_hw_enabled(struct kvm_lapic *apic)
 {
         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
@@ -210,6 +220,16 @@ static int find_highest_vector(void *bitmap)
                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 }
 
+static u8 count_vectors(void *bitmap)
+{
+        u32 *word = bitmap;
+        int word_offset;
+        u8 count = 0;
+        for (word_offset = 0; word_offset < MAX_APIC_VECTOR >> 5; ++word_offset)
+                count += hweight32(word[word_offset << 2]);
+        return count;
+}
+
 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 {
         apic->irr_pending = true;
@@ -242,6 +262,27 @@ static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
                 apic->irr_pending = true;
 }
 
+static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
+{
+        if (!__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
+                ++apic->isr_count;
+        BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
+        /*
+         * ISR (in service register) bit is set when injecting an interrupt.
+         * The highest vector is injected. Thus the latest bit set matches
+         * the highest bit in ISR.
+         */
+        apic->highest_isr_cache = vec;
+}
+
+static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
+{
+        if (__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
+                --apic->isr_count;
+        BUG_ON(apic->isr_count < 0);
+        apic->highest_isr_cache = -1;
+}
+
 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 {
         struct kvm_lapic *apic = vcpu->arch.apic;
@@ -270,9 +311,61 @@ int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
                         irq->level, irq->trig_mode);
 }
 
+static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
+{
+
+        return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
+                                      sizeof(val));
+}
+
+static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
+{
+
+        return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
+                                      sizeof(*val));
+}
+
+static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
+}
+
+static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
+{
+        u8 val;
+        if (pv_eoi_get_user(vcpu, &val) < 0)
+                apic_debug("Can't read EOI MSR value: 0x%llx\n",
+                           (unsigned long long)vcpi->arch.pv_eoi.msr_val);
+        return val & 0x1;
+}
+
+static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
+{
+        if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
+                apic_debug("Can't set EOI MSR value: 0x%llx\n",
+                           (unsigned long long)vcpi->arch.pv_eoi.msr_val);
+                return;
+        }
+        __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
+}
+
+static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
+{
+        if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
+                apic_debug("Can't clear EOI MSR value: 0x%llx\n",
+                           (unsigned long long)vcpi->arch.pv_eoi.msr_val);
+                return;
+        }
+        __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
+}
+
 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 {
         int result;
+        if (!apic->isr_count)
+                return -1;
+        if (likely(apic->highest_isr_cache != -1))
+                return apic->highest_isr_cache;
 
         result = find_highest_vector(apic->regs + APIC_ISR);
         ASSERT(result == -1 || result >= 16);
@@ -482,17 +575,20 @@ int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 }
 
-static void apic_set_eoi(struct kvm_lapic *apic)
+static int apic_set_eoi(struct kvm_lapic *apic)
 {
         int vector = apic_find_highest_isr(apic);
+
+        trace_kvm_eoi(apic, vector);
+
         /*
          * Not every write EOI will has corresponding ISR,
          * one example is when Kernel check timer on setup_IO_APIC
          */
         if (vector == -1)
-                return;
+                return vector;
 
-        apic_clear_vector(vector, apic->regs + APIC_ISR);
+        apic_clear_isr(vector, apic);
         apic_update_ppr(apic);
 
         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
@@ -505,6 +601,7 @@ static void apic_set_eoi(struct kvm_lapic *apic)
                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
         }
         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
+        return vector;
 }
 
 static void apic_send_ipi(struct kvm_lapic *apic)
@@ -1081,10 +1178,13 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
         }
         apic->irr_pending = false;
+        apic->isr_count = 0;
+        apic->highest_isr_cache = -1;
         update_divide_count(apic);
         atomic_set(&apic->lapic_timer.pending, 0);
         if (kvm_vcpu_is_bsp(vcpu))
                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
+        vcpu->arch.pv_eoi.msr_val = 0;
         apic_update_ppr(apic);
 
         vcpu->arch.apic_arb_prio = 0;
@@ -1248,7 +1348,7 @@ int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
         if (vector == -1)
                 return -1;
 
-        apic_set_vector(vector, apic->regs + APIC_ISR);
+        apic_set_isr(vector, apic);
         apic_update_ppr(apic);
         apic_clear_irr(vector, apic);
         return vector;
@@ -1267,6 +1367,8 @@ void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
         update_divide_count(apic);
         start_apic_timer(apic);
         apic->irr_pending = true;
+        apic->isr_count = count_vectors(apic->regs + APIC_ISR);
+        apic->highest_isr_cache = -1;
         kvm_make_request(KVM_REQ_EVENT, vcpu);
 }
 
@@ -1283,11 +1385,51 @@ void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
 }
 
+/*
+ * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
+ *
+ * Detect whether guest triggered PV EOI since the
+ * last entry. If yes, set EOI on guests's behalf.
+ * Clear PV EOI in guest memory in any case.
+ */
+static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
+                                        struct kvm_lapic *apic)
+{
+        bool pending;
+        int vector;
+        /*
+         * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
+         * and KVM_PV_EOI_ENABLED in guest memory as follows:
+         *
+         * KVM_APIC_PV_EOI_PENDING is unset:
+         *      -> host disabled PV EOI.
+         * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
+         *      -> host enabled PV EOI, guest did not execute EOI yet.
+         * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
+         *      -> host enabled PV EOI, guest executed EOI.
+         */
+        BUG_ON(!pv_eoi_enabled(vcpu));
+        pending = pv_eoi_get_pending(vcpu);
+        /*
+         * Clear pending bit in any case: it will be set again on vmentry.
+         * While this might not be ideal from performance point of view,
+         * this makes sure pv eoi is only enabled when we know it's safe.
+         */
+        pv_eoi_clr_pending(vcpu);
+        if (pending)
+                return;
+        vector = apic_set_eoi(apic);
+        trace_kvm_pv_eoi(apic, vector);
+}
+
 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
 {
         u32 data;
         void *vapic;
 
+        if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
+                apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
+
         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
                 return;
 
@@ -1298,17 +1440,44 @@ void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
         apic_set_tpr(vcpu->arch.apic, data & 0xff);
 }
 
+/*
+ * apic_sync_pv_eoi_to_guest - called before vmentry
+ *
+ * Detect whether it's safe to enable PV EOI and
+ * if yes do so.
+ */
+static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
+                                        struct kvm_lapic *apic)
+{
+        if (!pv_eoi_enabled(vcpu) ||
+            /* IRR set or many bits in ISR: could be nested. */
+            apic->irr_pending ||
+            /* Cache not set: could be safe but we don't bother. */
+            apic->highest_isr_cache == -1 ||
+            /* Need EOI to update ioapic. */
+            kvm_ioapic_handles_vector(vcpu->kvm, apic->highest_isr_cache)) {
+                /*
+                 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
+                 * so we need not do anything here.
+                 */
+                return;
+        }
+
+        pv_eoi_set_pending(apic->vcpu);
+}
+
 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
 {
         u32 data, tpr;
         int max_irr, max_isr;
-        struct kvm_lapic *apic;
+        struct kvm_lapic *apic = vcpu->arch.apic;
         void *vapic;
 
+        apic_sync_pv_eoi_to_guest(vcpu, apic);
+
         if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
                 return;
 
-        apic = vcpu->arch.apic;
         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
         max_irr = apic_find_highest_irr(apic);
         if (max_irr < 0)
@@ -1394,3 +1563,16 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
 
         return 0;
 }
+
+int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
+{
+        u64 addr = data & ~KVM_MSR_ENABLED;
+        if (!IS_ALIGNED(addr, 4))
+                return 1;
+
+        vcpu->arch.pv_eoi.msr_val = data;
+        if (!pv_eoi_enabled(vcpu))
+                return 0;
+        return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
+                                         addr);
+}
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 6f4ce2575d0..4af5405ae1e 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -13,6 +13,15 @@ struct kvm_lapic {
         u32 divide_count;
         struct kvm_vcpu *vcpu;
         bool irr_pending;
+        /* Number of bits set in ISR. */
+        s16 isr_count;
+        /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
+        int highest_isr_cache;
+        /**
+         * APIC register page.  The layout matches the register layout seen by
+         * the guest 1:1, because it is accessed by the vmx microcode.
+         * Note: Only one register, the TPR, is used by the microcode.
+         */
         void *regs;
         gpa_t vapic_addr;
         struct page *vapic_page;
@@ -60,4 +69,6 @@ static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
 {
         return vcpu->arch.hv_vapic & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE;
 }
+
+int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
 #endif
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 57e168e27b5..7fbd0d273ea 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -90,7 +90,7 @@ module_param(dbg, bool, 0644);
 
 #define PTE_PREFETCH_NUM                8
 
-#define PT_FIRST_AVAIL_BITS_SHIFT 9
+#define PT_FIRST_AVAIL_BITS_SHIFT 10
 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
 
 #define PT64_LEVEL_BITS 9
@@ -145,7 +145,8 @@ module_param(dbg, bool, 0644);
 #define CREATE_TRACE_POINTS
 #include "mmutrace.h"
 
-#define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
+#define SPTE_HOST_WRITEABLE     (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
+#define SPTE_MMU_WRITEABLE      (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
 
 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
 
@@ -188,6 +189,7 @@ static u64 __read_mostly shadow_dirty_mask;
 static u64 __read_mostly shadow_mmio_mask;
 
 static void mmu_spte_set(u64 *sptep, u64 spte);
+static void mmu_free_roots(struct kvm_vcpu *vcpu);
 
 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
 {
@@ -444,8 +446,22 @@ static bool __check_direct_spte_mmio_pf(u64 spte)
 }
 #endif
 
+static bool spte_is_locklessly_modifiable(u64 spte)
+{
+        return !(~spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE));
+}
+
 static bool spte_has_volatile_bits(u64 spte)
 {
+        /*
+         * Always atomicly update spte if it can be updated
+         * out of mmu-lock, it can ensure dirty bit is not lost,
+         * also, it can help us to get a stable is_writable_pte()
+         * to ensure tlb flush is not missed.
+         */
+        if (spte_is_locklessly_modifiable(spte))
+                return true;
+
         if (!shadow_accessed_mask)
                 return false;
 
@@ -478,34 +494,47 @@ static void mmu_spte_set(u64 *sptep, u64 new_spte)
 
 /* Rules for using mmu_spte_update:
  * Update the state bits, it means the mapped pfn is not changged.
+ *
+ * Whenever we overwrite a writable spte with a read-only one we
+ * should flush remote TLBs. Otherwise rmap_write_protect
+ * will find a read-only spte, even though the writable spte
+ * might be cached on a CPU's TLB, the return value indicates this
+ * case.
  */
-static void mmu_spte_update(u64 *sptep, u64 new_spte)
+static bool mmu_spte_update(u64 *sptep, u64 new_spte)
 {
-        u64 mask, old_spte = *sptep;
+        u64 old_spte = *sptep;
+        bool ret = false;
 
         WARN_ON(!is_rmap_spte(new_spte));
 
-        if (!is_shadow_present_pte(old_spte))
-                return mmu_spte_set(sptep, new_spte);
-
-        new_spte |= old_spte & shadow_dirty_mask;
-
-        mask = shadow_accessed_mask;
-        if (is_writable_pte(old_spte))
-                mask |= shadow_dirty_mask;
+        if (!is_shadow_present_pte(old_spte)) {
+                mmu_spte_set(sptep, new_spte);
+                return ret;
+        }
 
-        if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
+        if (!spte_has_volatile_bits(old_spte))
                 __update_clear_spte_fast(sptep, new_spte);
         else
                 old_spte = __update_clear_spte_slow(sptep, new_spte);
 
+        /*
+         * For the spte updated out of mmu-lock is safe, since
+         * we always atomicly update it, see the comments in
+         * spte_has_volatile_bits().
+         */
+        if (is_writable_pte(old_spte) && !is_writable_pte(new_spte))
+                ret = true;
+
         if (!shadow_accessed_mask)
-                return;
+                return ret;
 
         if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
         if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
+
+        return ret;
 }
 
 /*
@@ -652,8 +681,7 @@ static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
                                 mmu_page_header_cache);
 }
 
-static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
-                                    size_t size)
+static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc)
 {
         void *p;
 
@@ -664,8 +692,7 @@ static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
 
 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
 {
-        return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
-                                      sizeof(struct pte_list_desc));
+        return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
 }
 
 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
@@ -1051,35 +1078,82 @@ static void drop_spte(struct kvm *kvm, u64 *sptep)
                 rmap_remove(kvm, sptep);
 }
 
-static int __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp, int level)
+
+static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
+{
+        if (is_large_pte(*sptep)) {
+                WARN_ON(page_header(__pa(sptep))->role.level ==
+                        PT_PAGE_TABLE_LEVEL);
+                drop_spte(kvm, sptep);
+                --kvm->stat.lpages;
+                return true;
+        }
+
+        return false;
+}
+
+static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
+{
+        if (__drop_large_spte(vcpu->kvm, sptep))
+                kvm_flush_remote_tlbs(vcpu->kvm);
+}
+
+/*
+ * Write-protect on the specified @sptep, @pt_protect indicates whether
+ * spte writ-protection is caused by protecting shadow page table.
+ * @flush indicates whether tlb need be flushed.
+ *
+ * Note: write protection is difference between drity logging and spte
+ * protection:
+ * - for dirty logging, the spte can be set to writable at anytime if
+ *   its dirty bitmap is properly set.
+ * - for spte protection, the spte can be writable only after unsync-ing
+ *   shadow page.
+ *
+ * Return true if the spte is dropped.
+ */
+static bool
+spte_write_protect(struct kvm *kvm, u64 *sptep, bool *flush, bool pt_protect)
+{
+        u64 spte = *sptep;
+
+        if (!is_writable_pte(spte) &&
+              !(pt_protect && spte_is_locklessly_modifiable(spte)))
+                return false;
+
+        rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
+
+        if (__drop_large_spte(kvm, sptep)) {
+                *flush |= true;
+                return true;
+        }
+
+        if (pt_protect)
+                spte &= ~SPTE_MMU_WRITEABLE;
+        spte = spte & ~PT_WRITABLE_MASK;
+
+        *flush |= mmu_spte_update(sptep, spte);
+        return false;
+}
+
+static bool __rmap_write_protect(struct kvm *kvm, unsigned long *rmapp,
+                                 int level, bool pt_protect)
 {
         u64 *sptep;
         struct rmap_iterator iter;
-        int write_protected = 0;
+        bool flush = false;
 
         for (sptep = rmap_get_first(*rmapp, &iter); sptep;) {
                 BUG_ON(!(*sptep & PT_PRESENT_MASK));
-                rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep);
-
-                if (!is_writable_pte(*sptep)) {
-                        sptep = rmap_get_next(&iter);
-                        continue;
-                }
-
-                if (level == PT_PAGE_TABLE_LEVEL) {
-                        mmu_spte_update(sptep, *sptep & ~PT_WRITABLE_MASK);
-                        sptep = rmap_get_next(&iter);
-                } else {
-                        BUG_ON(!is_large_pte(*sptep));
-                        drop_spte(kvm, sptep);
-                        --kvm->stat.lpages;
+                if (spte_write_protect(kvm, sptep, &flush, pt_protect)) {
                         sptep = rmap_get_first(*rmapp, &iter);
+                        continue;
                 }
 
-                write_protected = 1;
+                sptep = rmap_get_next(&iter);
         }
 
-        return write_protected;
+        return flush;
 }
 
 /**
@@ -1100,26 +1174,26 @@ void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
 
         while (mask) {
                 rmapp = &slot->rmap[gfn_offset + __ffs(mask)];
-                __rmap_write_protect(kvm, rmapp, PT_PAGE_TABLE_LEVEL);
+                __rmap_write_protect(kvm, rmapp, PT_PAGE_TABLE_LEVEL, false);
 
                 /* clear the first set bit */
                 mask &= mask - 1;
         }
 }
 
-static int rmap_write_protect(struct kvm *kvm, u64 gfn)
+static bool rmap_write_protect(struct kvm *kvm, u64 gfn)
 {
         struct kvm_memory_slot *slot;
         unsigned long *rmapp;
         int i;
-        int write_protected = 0;
+        bool write_protected = false;
 
         slot = gfn_to_memslot(kvm, gfn);
 
         for (i = PT_PAGE_TABLE_LEVEL;
              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
                 rmapp = __gfn_to_rmap(gfn, i, slot);
-                write_protected |= __rmap_write_protect(kvm, rmapp, i);
+                write_protected |= __rmap_write_protect(kvm, rmapp, i, true);
         }
 
         return write_protected;
@@ -1238,11 +1312,12 @@ static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
                          unsigned long data)
 {
         u64 *sptep;
-        struct rmap_iterator iter;
+        struct rmap_iterator uninitialized_var(iter);
         int young = 0;
 
         /*
-         * Emulate the accessed bit for EPT, by checking if this page has
+         * In case of absence of EPT Access and Dirty Bits supports,
+         * emulate the accessed bit for EPT, by checking if this page has
          * an EPT mapping, and clearing it if it does. On the next access,
          * a new EPT mapping will be established.
          * This has some overhead, but not as much as the cost of swapping
@@ -1253,11 +1328,12 @@ static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
 
         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
              sptep = rmap_get_next(&iter)) {
-                BUG_ON(!(*sptep & PT_PRESENT_MASK));
+                BUG_ON(!is_shadow_present_pte(*sptep));
 
-                if (*sptep & PT_ACCESSED_MASK) {
+                if (*sptep & shadow_accessed_mask) {
                         young = 1;
-                        clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)sptep);
+                        clear_bit((ffs(shadow_accessed_mask) - 1),
+                                 (unsigned long *)sptep);
                 }
         }
 
@@ -1281,9 +1357,9 @@ static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
 
         for (sptep = rmap_get_first(*rmapp, &iter); sptep;
              sptep = rmap_get_next(&iter)) {
-                BUG_ON(!(*sptep & PT_PRESENT_MASK));
+                BUG_ON(!is_shadow_present_pte(*sptep));
 
-                if (*sptep & PT_ACCESSED_MASK) {
+                if (*sptep & shadow_accessed_mask) {
                         young = 1;
                         break;
                 }
@@ -1401,12 +1477,10 @@ static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
                                                u64 *parent_pte, int direct)
 {
         struct kvm_mmu_page *sp;
-        sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
-                                        sizeof *sp);
-        sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
+        sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
+        sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
         if (!direct)
-                sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
-                                                  PAGE_SIZE);
+                sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache);
         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
         bitmap_zero(sp->slot_bitmap, KVM_MEM_SLOTS_NUM);
@@ -1701,7 +1775,7 @@ static void mmu_sync_children(struct kvm_vcpu *vcpu,
 
         kvm_mmu_pages_init(parent, &parents, &pages);
         while (mmu_unsync_walk(parent, &pages)) {
-                int protected = 0;
+                bool protected = false;
 
                 for_each_sp(pages, sp, parents, i)
                         protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
@@ -1866,15 +1940,6 @@ static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
         mmu_spte_set(sptep, spte);
 }
 
-static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
-{
-        if (is_large_pte(*sptep)) {
-                drop_spte(vcpu->kvm, sptep);
-                --vcpu->kvm->stat.lpages;
-                kvm_flush_remote_tlbs(vcpu->kvm);
-        }
-}
-
 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                                    unsigned direct_access)
 {
@@ -2243,7 +2308,7 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                     gfn_t gfn, pfn_t pfn, bool speculative,
                     bool can_unsync, bool host_writable)
 {
-        u64 spte, entry = *sptep;
+        u64 spte;
         int ret = 0;
 
         if (set_mmio_spte(sptep, gfn, pfn, pte_access))
@@ -2257,8 +2322,10 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                 spte |= shadow_x_mask;
         else
                 spte |= shadow_nx_mask;
+
         if (pte_access & ACC_USER_MASK)
                 spte |= shadow_user_mask;
+
         if (level > PT_PAGE_TABLE_LEVEL)
                 spte |= PT_PAGE_SIZE_MASK;
         if (tdp_enabled)
@@ -2283,7 +2350,7 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                         goto done;
                 }
 
-                spte |= PT_WRITABLE_MASK;
+                spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE;
 
                 if (!vcpu->arch.mmu.direct_map
                     && !(pte_access & ACC_WRITE_MASK)) {
@@ -2312,8 +2379,7 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                                  __func__, gfn);
                         ret = 1;
                         pte_access &= ~ACC_WRITE_MASK;
-                        if (is_writable_pte(spte))
-                                spte &= ~PT_WRITABLE_MASK;
+                        spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE);
                 }
         }
 
@@ -2321,14 +2387,7 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                 mark_page_dirty(vcpu->kvm, gfn);
 
 set_pte:
-        mmu_spte_update(sptep, spte);
-        /*
-         * If we overwrite a writable spte with a read-only one we
-         * should flush remote TLBs. Otherwise rmap_write_protect
-         * will find a read-only spte, even though the writable spte
-         * might be cached on a CPU's TLB.
-         */
-        if (is_writable_pte(entry) && !is_writable_pte(*sptep))
+        if (mmu_spte_update(sptep, spte))
                 kvm_flush_remote_tlbs(vcpu->kvm);
 done:
         return ret;
@@ -2403,6 +2462,7 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
 
 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
 {
+        mmu_free_roots(vcpu);
 }
 
 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
@@ -2625,18 +2685,116 @@ exit:
         return ret;
 }
 
+static bool page_fault_can_be_fast(struct kvm_vcpu *vcpu, u32 error_code)
+{
+        /*
+         * #PF can be fast only if the shadow page table is present and it
+         * is caused by write-protect, that means we just need change the
+         * W bit of the spte which can be done out of mmu-lock.
+         */
+        if (!(error_code & PFERR_PRESENT_MASK) ||
+              !(error_code & PFERR_WRITE_MASK))
+                return false;
+
+        return true;
+}
+
+static bool
+fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 spte)
+{
+        struct kvm_mmu_page *sp = page_header(__pa(sptep));
+        gfn_t gfn;
+
+        WARN_ON(!sp->role.direct);
+
+        /*
+         * The gfn of direct spte is stable since it is calculated
+         * by sp->gfn.
+         */
+        gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
+
+        if (cmpxchg64(sptep, spte, spte | PT_WRITABLE_MASK) == spte)
+                mark_page_dirty(vcpu->kvm, gfn);
+
+        return true;
+}
+
+/*
+ * Return value:
+ * - true: let the vcpu to access on the same address again.
+ * - false: let the real page fault path to fix it.
+ */
+static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level,
+                            u32 error_code)
+{
+        struct kvm_shadow_walk_iterator iterator;
+        bool ret = false;
+        u64 spte = 0ull;
+
+        if (!page_fault_can_be_fast(vcpu, error_code))
+                return false;
+
+        walk_shadow_page_lockless_begin(vcpu);
+        for_each_shadow_entry_lockless(vcpu, gva, iterator, spte)
+                if (!is_shadow_present_pte(spte) || iterator.level < level)
+                        break;
+
+        /*
+         * If the mapping has been changed, let the vcpu fault on the
+         * same address again.
+         */
+        if (!is_rmap_spte(spte)) {
+                ret = true;
+                goto exit;
+        }
+
+        if (!is_last_spte(spte, level))
+                goto exit;
+
+        /*
+         * Check if it is a spurious fault caused by TLB lazily flushed.
+         *
+         * Need not check the access of upper level table entries since
+         * they are always ACC_ALL.
+         */
+         if (is_writable_pte(spte)) {
+                ret = true;
+                goto exit;
+        }
+
+        /*
+         * Currently, to simplify the code, only the spte write-protected
+         * by dirty-log can be fast fixed.
+         */
+        if (!spte_is_locklessly_modifiable(spte))
+                goto exit;
+
+        /*
+         * Currently, fast page fault only works for direct mapping since
+         * the gfn is not stable for indirect shadow page.
+         * See Documentation/virtual/kvm/locking.txt to get more detail.
+         */
+        ret = fast_pf_fix_direct_spte(vcpu, iterator.sptep, spte);
+exit:
+        trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep,
+                              spte, ret);
+        walk_shadow_page_lockless_end(vcpu);
+
+        return ret;
+}
+
 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
 
-static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
-                         bool prefault)
+static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code,
+                         gfn_t gfn, bool prefault)
 {
         int r;
         int level;
         int force_pt_level;
         pfn_t pfn;
         unsigned long mmu_seq;
-        bool map_writable;
+        bool map_writable, write = error_code & PFERR_WRITE_MASK;
 
         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
         if (likely(!force_pt_level)) {
@@ -2653,6 +2811,9 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
         } else
                 level = PT_PAGE_TABLE_LEVEL;
 
+        if (fast_page_fault(vcpu, v, level, error_code))
+                return 0;
+
         mmu_seq = vcpu->kvm->mmu_notifier_seq;
         smp_rmb();
 
@@ -3041,7 +3202,7 @@ static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
         gfn = gva >> PAGE_SHIFT;
 
         return nonpaging_map(vcpu, gva & PAGE_MASK,
-                             error_code & PFERR_WRITE_MASK, gfn, prefault);
+                             error_code, gfn, prefault);
 }
 
 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
@@ -3121,6 +3282,9 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
         } else
                 level = PT_PAGE_TABLE_LEVEL;
 
+        if (fast_page_fault(vcpu, gpa, level, error_code))
+                return 0;
+
         mmu_seq = vcpu->kvm->mmu_notifier_seq;
         smp_rmb();
 
@@ -3885,6 +4049,7 @@ int kvm_mmu_setup(struct kvm_vcpu *vcpu)
 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
 {
         struct kvm_mmu_page *sp;
+        bool flush = false;
 
         list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
                 int i;
@@ -3899,16 +4064,7 @@ void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
                               !is_last_spte(pt[i], sp->role.level))
                                 continue;
 
-                        if (is_large_pte(pt[i])) {
-                                drop_spte(kvm, &pt[i]);
-                                --kvm->stat.lpages;
-                                continue;
-                        }
-
-                        /* avoid RMW */
-                        if (is_writable_pte(pt[i]))
-                                mmu_spte_update(&pt[i],
-                                                pt[i] & ~PT_WRITABLE_MASK);
+                        spte_write_protect(kvm, &pt[i], &flush, false);
                 }
         }
         kvm_flush_remote_tlbs(kvm);
@@ -3945,7 +4101,6 @@ static void kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
 {
         struct kvm *kvm;
-        struct kvm *kvm_freed = NULL;
         int nr_to_scan = sc->nr_to_scan;
 
         if (nr_to_scan == 0)
@@ -3957,22 +4112,35 @@ static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
                 int idx;
                 LIST_HEAD(invalid_list);
 
+                /*
+                 * Never scan more than sc->nr_to_scan VM instances.
+                 * Will not hit this condition practically since we do not try
+                 * to shrink more than one VM and it is very unlikely to see
+                 * !n_used_mmu_pages so many times.
+                 */
+                if (!nr_to_scan--)
+                        break;
+                /*
+                 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
+                 * here. We may skip a VM instance errorneosly, but we do not
+                 * want to shrink a VM that only started to populate its MMU
+                 * anyway.
+                 */
+                if (!kvm->arch.n_used_mmu_pages)
+                        continue;
+
                 idx = srcu_read_lock(&kvm->srcu);
                 spin_lock(&kvm->mmu_lock);
-                if (!kvm_freed && nr_to_scan > 0 &&
-                    kvm->arch.n_used_mmu_pages > 0) {
-                        kvm_mmu_remove_some_alloc_mmu_pages(kvm,
-                                                            &invalid_list);
-                        kvm_freed = kvm;
-                }
-                nr_to_scan--;
 
+                kvm_mmu_remove_some_alloc_mmu_pages(kvm, &invalid_list);
                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
+
                 spin_unlock(&kvm->mmu_lock);
                 srcu_read_unlock(&kvm->srcu, idx);
+
+                list_move_tail(&kvm->vm_list, &vm_list);
+                break;
         }
-        if (kvm_freed)
-                list_move_tail(&kvm_freed->vm_list, &vm_list);
 
         raw_spin_unlock(&kvm_lock);
 
diff --git a/arch/x86/kvm/mmutrace.h b/arch/x86/kvm/mmutrace.h
index 89fb0e81322..cd6e98333ba 100644
--- a/arch/x86/kvm/mmutrace.h
+++ b/arch/x86/kvm/mmutrace.h
@@ -54,8 +54,8 @@
  */
 TRACE_EVENT(
         kvm_mmu_pagetable_walk,
-        TP_PROTO(u64 addr, int write_fault, int user_fault, int fetch_fault),
-        TP_ARGS(addr, write_fault, user_fault, fetch_fault),
+        TP_PROTO(u64 addr, u32 pferr),
+        TP_ARGS(addr, pferr),
 
         TP_STRUCT__entry(
                 __field(__u64, addr)
@@ -64,8 +64,7 @@ TRACE_EVENT(
 
         TP_fast_assign(
                 __entry->addr = addr;
-                __entry->pferr = (!!write_fault << 1) | (!!user_fault << 2)
-                                 | (!!fetch_fault << 4);
+                __entry->pferr = pferr;
         ),
 
         TP_printk("addr %llx pferr %x %s", __entry->addr, __entry->pferr,
@@ -243,6 +242,44 @@ TRACE_EVENT(
         TP_printk("addr:%llx gfn %llx access %x", __entry->addr, __entry->gfn,
                   __entry->access)
 );
+
+#define __spte_satisfied(__spte)                                \
+        (__entry->retry && is_writable_pte(__entry->__spte))
+
+TRACE_EVENT(
+        fast_page_fault,
+        TP_PROTO(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code,
+                 u64 *sptep, u64 old_spte, bool retry),
+        TP_ARGS(vcpu, gva, error_code, sptep, old_spte, retry),
+
+        TP_STRUCT__entry(
+                __field(int, vcpu_id)
+                __field(gva_t, gva)
+                __field(u32, error_code)
+                __field(u64 *, sptep)
+                __field(u64, old_spte)
+                __field(u64, new_spte)
+                __field(bool, retry)
+        ),
+
+        TP_fast_assign(
+                __entry->vcpu_id = vcpu->vcpu_id;
+                __entry->gva = gva;
+                __entry->error_code = error_code;
+                __entry->sptep = sptep;
+                __entry->old_spte = old_spte;
+                __entry->new_spte = *sptep;
+                __entry->retry = retry;
+        ),
+
+        TP_printk("vcpu %d gva %lx error_code %s sptep %p old %#llx"
+                  " new %llx spurious %d fixed %d", __entry->vcpu_id,
+                  __entry->gva, __print_flags(__entry->error_code, "|",
+                  kvm_mmu_trace_pferr_flags), __entry->sptep,
+                  __entry->old_spte, __entry->new_spte,
+                  __spte_satisfied(old_spte), __spte_satisfied(new_spte)
+        )
+);
 #endif /* _TRACE_KVMMMU_H */
 
 #undef TRACE_INCLUDE_PATH
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 34f970937ef..bb7cf01cae7 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -154,8 +154,7 @@ static int FNAME(walk_addr_generic)(struct guest_walker *walker,
         const int fetch_fault = access & PFERR_FETCH_MASK;
         u16 errcode = 0;
 
-        trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
-                                     fetch_fault);
+        trace_kvm_mmu_pagetable_walk(addr, access);
 retry_walk:
         eperm = false;
         walker->level = mmu->root_level;
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 2e88438ffd8..9b7ec1150ab 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -80,10 +80,10 @@ static inline struct kvm_pmc *get_fixed_pmc_idx(struct kvm_pmu *pmu, int idx)
 
 static struct kvm_pmc *global_idx_to_pmc(struct kvm_pmu *pmu, int idx)
 {
-        if (idx < X86_PMC_IDX_FIXED)
+        if (idx < INTEL_PMC_IDX_FIXED)
                 return get_gp_pmc(pmu, MSR_P6_EVNTSEL0 + idx, MSR_P6_EVNTSEL0);
         else
-                return get_fixed_pmc_idx(pmu, idx - X86_PMC_IDX_FIXED);
+                return get_fixed_pmc_idx(pmu, idx - INTEL_PMC_IDX_FIXED);
 }
 
 void kvm_deliver_pmi(struct kvm_vcpu *vcpu)
@@ -291,7 +291,7 @@ static void reprogram_idx(struct kvm_pmu *pmu, int idx)
         if (pmc_is_gp(pmc))
                 reprogram_gp_counter(pmc, pmc->eventsel);
         else {
-                int fidx = idx - X86_PMC_IDX_FIXED;
+                int fidx = idx - INTEL_PMC_IDX_FIXED;
                 reprogram_fixed_counter(pmc,
                                 fixed_en_pmi(pmu->fixed_ctr_ctrl, fidx), fidx);
         }
@@ -452,7 +452,7 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
                 return;
 
         pmu->nr_arch_gp_counters = min((int)(entry->eax >> 8) & 0xff,
-                        X86_PMC_MAX_GENERIC);
+                        INTEL_PMC_MAX_GENERIC);
         pmu->counter_bitmask[KVM_PMC_GP] =
                 ((u64)1 << ((entry->eax >> 16) & 0xff)) - 1;
         bitmap_len = (entry->eax >> 24) & 0xff;
@@ -462,13 +462,13 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
                 pmu->nr_arch_fixed_counters = 0;
         } else {
                 pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f),
-                                X86_PMC_MAX_FIXED);
+                                INTEL_PMC_MAX_FIXED);
                 pmu->counter_bitmask[KVM_PMC_FIXED] =
                         ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1;
         }
 
         pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) |
-                (((1ull << pmu->nr_arch_fixed_counters) - 1) << X86_PMC_IDX_FIXED);
+                (((1ull << pmu->nr_arch_fixed_counters) - 1) << INTEL_PMC_IDX_FIXED);
         pmu->global_ctrl_mask = ~pmu->global_ctrl;
 }
 
@@ -478,15 +478,15 @@ void kvm_pmu_init(struct kvm_vcpu *vcpu)
         struct kvm_pmu *pmu = &vcpu->arch.pmu;
 
         memset(pmu, 0, sizeof(*pmu));
-        for (i = 0; i < X86_PMC_MAX_GENERIC; i++) {
+        for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
                 pmu->gp_counters[i].type = KVM_PMC_GP;
                 pmu->gp_counters[i].vcpu = vcpu;
                 pmu->gp_counters[i].idx = i;
         }
-        for (i = 0; i < X86_PMC_MAX_FIXED; i++) {
+        for (i = 0; i < INTEL_PMC_MAX_FIXED; i++) {
                 pmu->fixed_counters[i].type = KVM_PMC_FIXED;
                 pmu->fixed_counters[i].vcpu = vcpu;
-                pmu->fixed_counters[i].idx = i + X86_PMC_IDX_FIXED;
+                pmu->fixed_counters[i].idx = i + INTEL_PMC_IDX_FIXED;
         }
         init_irq_work(&pmu->irq_work, trigger_pmi);
         kvm_pmu_cpuid_update(vcpu);
@@ -498,13 +498,13 @@ void kvm_pmu_reset(struct kvm_vcpu *vcpu)
         int i;
 
         irq_work_sync(&pmu->irq_work);
-        for (i = 0; i < X86_PMC_MAX_GENERIC; i++) {
+        for (i = 0; i < INTEL_PMC_MAX_GENERIC; i++) {
                 struct kvm_pmc *pmc = &pmu->gp_counters[i];
                 stop_counter(pmc);
                 pmc->counter = pmc->eventsel = 0;
         }
 
-        for (i = 0; i < X86_PMC_MAX_FIXED; i++)
+        for (i = 0; i < INTEL_PMC_MAX_FIXED; i++)
                 stop_counter(&pmu->fixed_counters[i]);
 
         pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status =
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index f75af406b26..baead950d6c 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -3185,8 +3185,8 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
                 break;
         case MSR_IA32_DEBUGCTLMSR:
                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
-                        pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
-                                        __func__, data);
+                        vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
+                                    __func__, data);
                         break;
                 }
                 if (data & DEBUGCTL_RESERVED_BITS)
@@ -3205,7 +3205,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
         case MSR_VM_CR:
                 return svm_set_vm_cr(vcpu, data);
         case MSR_VM_IGNNE:
-                pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
+                vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
                 break;
         default:
                 return kvm_set_msr_common(vcpu, ecx, data);
@@ -4044,6 +4044,11 @@ static bool svm_rdtscp_supported(void)
         return false;
 }
 
+static bool svm_invpcid_supported(void)
+{
+        return false;
+}
+
 static bool svm_has_wbinvd_exit(void)
 {
         return true;
@@ -4312,6 +4317,7 @@ static struct kvm_x86_ops svm_x86_ops = {
         .cpuid_update = svm_cpuid_update,
 
         .rdtscp_supported = svm_rdtscp_supported,
+        .invpcid_supported = svm_invpcid_supported,
 
         .set_supported_cpuid = svm_set_supported_cpuid,
 
diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h
index 911d2641f14..a71faf727ff 100644
--- a/arch/x86/kvm/trace.h
+++ b/arch/x86/kvm/trace.h
@@ -517,6 +517,40 @@ TRACE_EVENT(kvm_apic_accept_irq,
                   __entry->coalesced ? " (coalesced)" : "")
 );
 
+TRACE_EVENT(kvm_eoi,
+            TP_PROTO(struct kvm_lapic *apic, int vector),
+            TP_ARGS(apic, vector),
+
+        TP_STRUCT__entry(
+                __field(        __u32,          apicid          )
+                __field(        int,            vector          )
+        ),
+
+        TP_fast_assign(
+                __entry->apicid         = apic->vcpu->vcpu_id;
+                __entry->vector         = vector;
+        ),
+
+        TP_printk("apicid %x vector %d", __entry->apicid, __entry->vector)
+);
+
+TRACE_EVENT(kvm_pv_eoi,
+            TP_PROTO(struct kvm_lapic *apic, int vector),
+            TP_ARGS(apic, vector),
+
+        TP_STRUCT__entry(
+                __field(        __u32,          apicid          )
+                __field(        int,            vector          )
+        ),
+
+        TP_fast_assign(
+                __entry->apicid         = apic->vcpu->vcpu_id;
+                __entry->vector         = vector;
+        ),
+
+        TP_printk("apicid %x vector %d", __entry->apicid, __entry->vector)
+);
+
 /*
  * Tracepoint for nested VMRUN
  */
@@ -710,16 +744,6 @@ TRACE_EVENT(kvm_skinit,
                   __entry->rip, __entry->slb)
 );
 
-#define __print_insn(insn, ilen) ({                              \
-        int i;                                                   \
-        const char *ret = p->buffer + p->len;                    \
-                                                                 \
-        for (i = 0; i < ilen; ++i)                               \
-                trace_seq_printf(p, " %02x", insn[i]);           \
-        trace_seq_printf(p, "%c", 0);                            \
-        ret;                                                     \
-        })
-
 #define KVM_EMUL_INSN_F_CR0_PE (1 << 0)
 #define KVM_EMUL_INSN_F_EFL_VM (1 << 1)
 #define KVM_EMUL_INSN_F_CS_D   (1 << 2)
@@ -786,7 +810,7 @@ TRACE_EVENT(kvm_emulate_insn,
 
         TP_printk("%x:%llx:%s (%s)%s",
                   __entry->csbase, __entry->rip,
-                  __print_insn(__entry->insn, __entry->len),
+                  __print_hex(__entry->insn, __entry->len),
                   __print_symbolic(__entry->flags,
                                    kvm_trace_symbol_emul_flags),
                   __entry->failed ? " failed" : ""
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 32eb5886629..c00f03de1b7 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -71,7 +71,10 @@ static bool __read_mostly enable_unrestricted_guest = 1;
 module_param_named(unrestricted_guest,
                         enable_unrestricted_guest, bool, S_IRUGO);
 
-static bool __read_mostly emulate_invalid_guest_state = 0;
+static bool __read_mostly enable_ept_ad_bits = 1;
+module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
+
+static bool __read_mostly emulate_invalid_guest_state = true;
 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
 
 static bool __read_mostly vmm_exclusive = 1;
@@ -615,6 +618,10 @@ static void kvm_cpu_vmxon(u64 addr);
 static void kvm_cpu_vmxoff(void);
 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
+static void vmx_set_segment(struct kvm_vcpu *vcpu,
+                            struct kvm_segment *var, int seg);
+static void vmx_get_segment(struct kvm_vcpu *vcpu,
+                            struct kvm_segment *var, int seg);
 
 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
@@ -789,6 +796,11 @@ static inline bool cpu_has_vmx_ept_4levels(void)
         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 }
 
+static inline bool cpu_has_vmx_ept_ad_bits(void)
+{
+        return vmx_capability.ept & VMX_EPT_AD_BIT;
+}
+
 static inline bool cpu_has_vmx_invept_individual_addr(void)
 {
         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
@@ -849,6 +861,12 @@ static inline bool cpu_has_vmx_rdtscp(void)
                 SECONDARY_EXEC_RDTSCP;
 }
 
+static inline bool cpu_has_vmx_invpcid(void)
+{
+        return vmcs_config.cpu_based_2nd_exec_ctrl &
+                SECONDARY_EXEC_ENABLE_INVPCID;
+}
+
 static inline bool cpu_has_virtual_nmis(void)
 {
         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
@@ -1470,13 +1488,6 @@ static void __vmx_load_host_state(struct vcpu_vmx *vmx)
                 loadsegment(ds, vmx->host_state.ds_sel);
                 loadsegment(es, vmx->host_state.es_sel);
         }
-#else
-        /*
-         * The sysexit path does not restore ds/es, so we must set them to
-         * a reasonable value ourselves.
-         */
-        loadsegment(ds, __USER_DS);
-        loadsegment(es, __USER_DS);
 #endif
         reload_tss();
 #ifdef CONFIG_X86_64
@@ -1739,6 +1750,11 @@ static bool vmx_rdtscp_supported(void)
         return cpu_has_vmx_rdtscp();
 }
 
+static bool vmx_invpcid_supported(void)
+{
+        return cpu_has_vmx_invpcid() && enable_ept;
+}
+
 /*
  * Swap MSR entry in host/guest MSR entry array.
  */
@@ -2458,7 +2474,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
                         SECONDARY_EXEC_ENABLE_EPT |
                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
-                        SECONDARY_EXEC_RDTSCP;
+                        SECONDARY_EXEC_RDTSCP |
+                        SECONDARY_EXEC_ENABLE_INVPCID;
                 if (adjust_vmx_controls(min2, opt2,
                                         MSR_IA32_VMX_PROCBASED_CTLS2,
                                         &_cpu_based_2nd_exec_control) < 0)
@@ -2645,8 +2662,12 @@ static __init int hardware_setup(void)
             !cpu_has_vmx_ept_4levels()) {
                 enable_ept = 0;
                 enable_unrestricted_guest = 0;
+                enable_ept_ad_bits = 0;
         }
 
+        if (!cpu_has_vmx_ept_ad_bits())
+                enable_ept_ad_bits = 0;
+
         if (!cpu_has_vmx_unrestricted_guest())
                 enable_unrestricted_guest = 0;
 
@@ -2770,6 +2791,7 @@ static void enter_rmode(struct kvm_vcpu *vcpu)
 {
         unsigned long flags;
         struct vcpu_vmx *vmx = to_vmx(vcpu);
+        struct kvm_segment var;
 
         if (enable_unrestricted_guest)
                 return;
@@ -2813,20 +2835,23 @@ static void enter_rmode(struct kvm_vcpu *vcpu)
         if (emulate_invalid_guest_state)
                 goto continue_rmode;
 
-        vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
-        vmcs_write32(GUEST_SS_LIMIT, 0xffff);
-        vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
+        vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
+        vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
+
+        vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
+        vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
 
-        vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
-        vmcs_write32(GUEST_CS_LIMIT, 0xffff);
-        if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
-                vmcs_writel(GUEST_CS_BASE, 0xf0000);
-        vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
+        vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
+        vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
 
-        fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
-        fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
-        fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
-        fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
+        vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
+        vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
+
+        vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
+        vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
+
+        vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
+        vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
 
 continue_rmode:
         kvm_mmu_reset_context(vcpu);
@@ -3027,6 +3052,8 @@ static u64 construct_eptp(unsigned long root_hpa)
         /* TODO write the value reading from MSR */
         eptp = VMX_EPT_DEFAULT_MT |
                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
+        if (enable_ept_ad_bits)
+                eptp |= VMX_EPT_AD_ENABLE_BIT;
         eptp |= (root_hpa & PAGE_MASK);
 
         return eptp;
@@ -3153,11 +3180,22 @@ static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
 
 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
 {
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
+
+        /*
+         * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
+         * fail; use the cache instead.
+         */
+        if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
+                return vmx->cpl;
+        }
+
         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
-                to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
+                vmx->cpl = __vmx_get_cpl(vcpu);
         }
-        return to_vmx(vcpu)->cpl;
+
+        return vmx->cpl;
 }
 
 
@@ -3165,7 +3203,7 @@ static u32 vmx_segment_access_rights(struct kvm_segment *var)
 {
         u32 ar;
 
-        if (var->unusable)
+        if (var->unusable || !var->present)
                 ar = 1 << 16;
         else {
                 ar = var->type & 15;
@@ -3177,8 +3215,6 @@ static u32 vmx_segment_access_rights(struct kvm_segment *var)
                 ar |= (var->db & 1) << 14;
                 ar |= (var->g & 1) << 15;
         }
-        if (ar == 0) /* a 0 value means unusable */
-                ar = AR_UNUSABLE_MASK;
 
         return ar;
 }
@@ -3229,6 +3265,44 @@ static void vmx_set_segment(struct kvm_vcpu *vcpu,
 
         vmcs_write32(sf->ar_bytes, ar);
         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
+
+        /*
+         * Fix segments for real mode guest in hosts that don't have
+         * "unrestricted_mode" or it was disabled.
+         * This is done to allow migration of the guests from hosts with
+         * unrestricted guest like Westmere to older host that don't have
+         * unrestricted guest like Nehelem.
+         */
+        if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
+                switch (seg) {
+                case VCPU_SREG_CS:
+                        vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
+                        vmcs_write32(GUEST_CS_LIMIT, 0xffff);
+                        if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
+                                vmcs_writel(GUEST_CS_BASE, 0xf0000);
+                        vmcs_write16(GUEST_CS_SELECTOR,
+                                     vmcs_readl(GUEST_CS_BASE) >> 4);
+                        break;
+                case VCPU_SREG_ES:
+                        fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
+                        break;
+                case VCPU_SREG_DS:
+                        fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
+                        break;
+                case VCPU_SREG_GS:
+                        fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
+                        break;
+                case VCPU_SREG_FS:
+                        fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
+                        break;
+                case VCPU_SREG_SS:
+                        vmcs_write16(GUEST_SS_SELECTOR,
+                                     vmcs_readl(GUEST_SS_BASE) >> 4);
+                        vmcs_write32(GUEST_SS_LIMIT, 0xffff);
+                        vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
+                        break;
+                }
+        }
 }
 
 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
@@ -3731,6 +3805,8 @@ static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
         if (!enable_ept) {
                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
                 enable_unrestricted_guest = 0;
+                /* Enable INVPCID for non-ept guests may cause performance regression. */
+                exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
         }
         if (!enable_unrestricted_guest)
                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
@@ -4489,7 +4565,7 @@ static int handle_cr(struct kvm_vcpu *vcpu)
                 break;
         }
         vcpu->run->exit_reason = 0;
-        pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
+        vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
                (int)(exit_qualification >> 4) & 3, cr);
         return 0;
 }
@@ -4769,6 +4845,7 @@ static int handle_ept_violation(struct kvm_vcpu *vcpu)
 {
         unsigned long exit_qualification;
         gpa_t gpa;
+        u32 error_code;
         int gla_validity;
 
         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
@@ -4793,7 +4870,13 @@ static int handle_ept_violation(struct kvm_vcpu *vcpu)
 
         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
         trace_kvm_page_fault(gpa, exit_qualification);
-        return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
+
+        /* It is a write fault? */
+        error_code = exit_qualification & (1U << 1);
+        /* ept page table is present? */
+        error_code |= (exit_qualification >> 3) & 0x1;
+
+        return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
 }
 
 static u64 ept_rsvd_mask(u64 spte, int level)
@@ -4908,15 +4991,18 @@ static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
         int ret = 1;
         u32 cpu_exec_ctrl;
         bool intr_window_requested;
+        unsigned count = 130;
 
         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
 
-        while (!guest_state_valid(vcpu)) {
-                if (intr_window_requested
-                    && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
+        while (!guest_state_valid(vcpu) && count-- != 0) {
+                if (intr_window_requested && vmx_interrupt_allowed(vcpu))
                         return handle_interrupt_window(&vmx->vcpu);
 
+                if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
+                        return 1;
+
                 err = emulate_instruction(vcpu, 0);
 
                 if (err == EMULATE_DO_MMIO) {
@@ -4924,8 +5010,12 @@ static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
                         goto out;
                 }
 
-                if (err != EMULATE_DONE)
+                if (err != EMULATE_DONE) {
+                        vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+                        vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
+                        vcpu->run->internal.ndata = 0;
                         return 0;
+                }
 
                 if (signal_pending(current))
                         goto out;
@@ -4933,7 +5023,7 @@ static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
                         schedule();
         }
 
-        vmx->emulation_required = 0;
+        vmx->emulation_required = !guest_state_valid(vcpu);
 out:
         return ret;
 }
@@ -6273,6 +6363,19 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
 #endif
               );
 
+#ifndef CONFIG_X86_64
+        /*
+         * The sysexit path does not restore ds/es, so we must set them to
+         * a reasonable value ourselves.
+         *
+         * We can't defer this to vmx_load_host_state() since that function
+         * may be executed in interrupt context, which saves and restore segments
+         * around it, nullifying its effect.
+         */
+        loadsegment(ds, __USER_DS);
+        loadsegment(es, __USER_DS);
+#endif
+
         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
                                   | (1 << VCPU_EXREG_RFLAGS)
                                   | (1 << VCPU_EXREG_CPL)
@@ -6467,6 +6570,23 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
                         }
                 }
         }
+
+        exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
+        /* Exposing INVPCID only when PCID is exposed */
+        best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
+        if (vmx_invpcid_supported() &&
+            best && (best->ecx & bit(X86_FEATURE_INVPCID)) &&
+            guest_cpuid_has_pcid(vcpu)) {
+                exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
+                vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
+                             exec_control);
+        } else {
+                exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
+                vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
+                             exec_control);
+                if (best)
+                        best->ecx &= ~bit(X86_FEATURE_INVPCID);
+        }
 }
 
 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
@@ -7201,6 +7321,7 @@ static struct kvm_x86_ops vmx_x86_ops = {
         .cpuid_update = vmx_cpuid_update,
 
         .rdtscp_supported = vmx_rdtscp_supported,
+        .invpcid_supported = vmx_invpcid_supported,
 
         .set_supported_cpuid = vmx_set_supported_cpuid,
 
@@ -7230,23 +7351,21 @@ static int __init vmx_init(void)
         if (!vmx_io_bitmap_a)
                 return -ENOMEM;
 
+        r = -ENOMEM;
+
         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
-        if (!vmx_io_bitmap_b) {
-                r = -ENOMEM;
+        if (!vmx_io_bitmap_b)
                 goto out;
-        }
 
         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
-        if (!vmx_msr_bitmap_legacy) {
-                r = -ENOMEM;
+        if (!vmx_msr_bitmap_legacy)
                 goto out1;
-        }
+
 
         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
-        if (!vmx_msr_bitmap_longmode) {
-                r = -ENOMEM;
+        if (!vmx_msr_bitmap_longmode)
                 goto out2;
-        }
+
 
         /*
          * Allow direct access to the PC debug port (it is often used for I/O
@@ -7275,8 +7394,10 @@ static int __init vmx_init(void)
         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
 
         if (enable_ept) {
-                kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
-                                VMX_EPT_EXECUTABLE_MASK);
+                kvm_mmu_set_mask_ptes(0ull,
+                        (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
+                        (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
+                        0ull, VMX_EPT_EXECUTABLE_MASK);
                 ept_set_mmio_spte_mask();
                 kvm_enable_tdp();
         } else
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index be6d54929fa..148ed666e31 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -528,6 +528,9 @@ int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
                         return 1;
         }
 
+        if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
+                return 1;
+
         kvm_x86_ops->set_cr0(vcpu, cr0);
 
         if ((cr0 ^ old_cr0) & X86_CR0_PG) {
@@ -604,10 +607,20 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
                                    kvm_read_cr3(vcpu)))
                 return 1;
 
+        if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
+                if (!guest_cpuid_has_pcid(vcpu))
+                        return 1;
+
+                /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
+                if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
+                        return 1;
+        }
+
         if (kvm_x86_ops->set_cr4(vcpu, cr4))
                 return 1;
 
-        if ((cr4 ^ old_cr4) & pdptr_bits)
+        if (((cr4 ^ old_cr4) & pdptr_bits) ||
+            (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
                 kvm_mmu_reset_context(vcpu);
 
         if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
@@ -626,8 +639,12 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
         }
 
         if (is_long_mode(vcpu)) {
-                if (cr3 & CR3_L_MODE_RESERVED_BITS)
-                        return 1;
+                if (kvm_read_cr4(vcpu) & X86_CR4_PCIDE) {
+                        if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
+                                return 1;
+                } else
+                        if (cr3 & CR3_L_MODE_RESERVED_BITS)
+                                return 1;
         } else {
                 if (is_pae(vcpu)) {
                         if (cr3 & CR3_PAE_RESERVED_BITS)
@@ -789,12 +806,13 @@ EXPORT_SYMBOL_GPL(kvm_rdpmc);
  * kvm-specific. Those are put in the beginning of the list.
  */
 
-#define KVM_SAVE_MSRS_BEGIN     9
+#define KVM_SAVE_MSRS_BEGIN     10
 static u32 msrs_to_save[] = {
         MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
         MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
         HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
         HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
+        MSR_KVM_PV_EOI_EN,
         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
         MSR_STAR,
 #ifdef CONFIG_X86_64
@@ -907,6 +925,10 @@ static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
          */
         getboottime(&boot);
 
+        if (kvm->arch.kvmclock_offset) {
+                struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
+                boot = timespec_sub(boot, ts);
+        }
         wc.sec = boot.tv_sec;
         wc.nsec = boot.tv_nsec;
         wc.version = version;
@@ -1437,8 +1459,8 @@ static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                 break;
         }
         default:
-                pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
-                          "data 0x%llx\n", msr, data);
+                vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
+                            "data 0x%llx\n", msr, data);
                 return 1;
         }
         return 0;
@@ -1470,8 +1492,8 @@ static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
         case HV_X64_MSR_TPR:
                 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
         default:
-                pr_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
-                          "data 0x%llx\n", msr, data);
+                vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
+                            "data 0x%llx\n", msr, data);
                 return 1;
         }
 
@@ -1551,15 +1573,15 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                 data &= ~(u64)0x100;    /* ignore ignne emulation enable */
                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
                 if (data != 0) {
-                        pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
-                                data);
+                        vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
+                                    data);
                         return 1;
                 }
                 break;
         case MSR_FAM10H_MMIO_CONF_BASE:
                 if (data != 0) {
-                        pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
-                                "0x%llx\n", data);
+                        vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
+                                    "0x%llx\n", data);
                         return 1;
                 }
                 break;
@@ -1574,8 +1596,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                            thus reserved and should throw a #GP */
                         return 1;
                 }
-                pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
-                        __func__, data);
+                vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
+                            __func__, data);
                 break;
         case MSR_IA32_UCODE_REV:
         case MSR_IA32_UCODE_WRITE:
@@ -1653,6 +1675,10 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
 
                 break;
+        case MSR_KVM_PV_EOI_EN:
+                if (kvm_lapic_enable_pv_eoi(vcpu, data))
+                        return 1;
+                break;
 
         case MSR_IA32_MCG_CTL:
         case MSR_IA32_MCG_STATUS:
@@ -1671,8 +1697,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
         case MSR_K7_EVNTSEL2:
         case MSR_K7_EVNTSEL3:
                 if (data != 0)
-                        pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
-                                "0x%x data 0x%llx\n", msr, data);
+                        vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
+                                    "0x%x data 0x%llx\n", msr, data);
                 break;
         /* at least RHEL 4 unconditionally writes to the perfctr registers,
          * so we ignore writes to make it happy.
@@ -1681,8 +1707,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
         case MSR_K7_PERFCTR1:
         case MSR_K7_PERFCTR2:
         case MSR_K7_PERFCTR3:
-                pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
-                        "0x%x data 0x%llx\n", msr, data);
+                vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
+                            "0x%x data 0x%llx\n", msr, data);
                 break;
         case MSR_P6_PERFCTR0:
         case MSR_P6_PERFCTR1:
@@ -1693,8 +1719,8 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                         return kvm_pmu_set_msr(vcpu, msr, data);
 
                 if (pr || data != 0)
-                        pr_unimpl(vcpu, "disabled perfctr wrmsr: "
-                                "0x%x data 0x%llx\n", msr, data);
+                        vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
+                                    "0x%x data 0x%llx\n", msr, data);
                 break;
         case MSR_K7_CLK_CTL:
                 /*
@@ -1720,7 +1746,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                 /* Drop writes to this legacy MSR -- see rdmsr
                  * counterpart for further detail.
                  */
-                pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
+                vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
                 break;
         case MSR_AMD64_OSVW_ID_LENGTH:
                 if (!guest_cpuid_has_osvw(vcpu))
@@ -1738,12 +1764,12 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                 if (kvm_pmu_msr(vcpu, msr))
                         return kvm_pmu_set_msr(vcpu, msr, data);
                 if (!ignore_msrs) {
-                        pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
-                                msr, data);
+                        vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
+                                    msr, data);
                         return 1;
                 } else {
-                        pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
-                                msr, data);
+                        vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
+                                    msr, data);
                         break;
                 }
         }
@@ -1846,7 +1872,7 @@ static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
                 data = kvm->arch.hv_hypercall;
                 break;
         default:
-                pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
+                vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
                 return 1;
         }
 
@@ -1877,7 +1903,7 @@ static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
                 data = vcpu->arch.hv_vapic;
                 break;
         default:
-                pr_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
+                vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
                 return 1;
         }
         *pdata = data;
@@ -1974,6 +2000,9 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
         case MSR_KVM_STEAL_TIME:
                 data = vcpu->arch.st.msr_val;
                 break;
+        case MSR_KVM_PV_EOI_EN:
+                data = vcpu->arch.pv_eoi.msr_val;
+                break;
         case MSR_IA32_P5_MC_ADDR:
         case MSR_IA32_P5_MC_TYPE:
         case MSR_IA32_MCG_CAP:
@@ -2030,10 +2059,10 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
                 if (kvm_pmu_msr(vcpu, msr))
                         return kvm_pmu_get_msr(vcpu, msr, pdata);
                 if (!ignore_msrs) {
-                        pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
+                        vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
                         return 1;
                 } else {
-                        pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
+                        vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
                         data = 0;
                 }
                 break;
@@ -4116,7 +4145,7 @@ static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
                 value = kvm_get_cr8(vcpu);
                 break;
         default:
-                vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
+                kvm_err("%s: unexpected cr %u\n", __func__, cr);
                 return 0;
         }
 
@@ -4145,7 +4174,7 @@ static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
                 res = kvm_set_cr8(vcpu, val);
                 break;
         default:
-                vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
+                kvm_err("%s: unexpected cr %u\n", __func__, cr);
                 res = -1;
         }
 
@@ -4297,26 +4326,10 @@ static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
         return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
 }
 
-static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
+static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
                                u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
 {
-        struct kvm_cpuid_entry2 *cpuid = NULL;
-
-        if (eax && ecx)
-                cpuid = kvm_find_cpuid_entry(emul_to_vcpu(ctxt),
-                                            *eax, *ecx);
-
-        if (cpuid) {
-                *eax = cpuid->eax;
-                *ecx = cpuid->ecx;
-                if (ebx)
-                        *ebx = cpuid->ebx;
-                if (edx)
-                        *edx = cpuid->edx;
-                return true;
-        }
-
-        return false;
+        kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
 }
 
 static struct x86_emulate_ops emulate_ops = {
@@ -5296,8 +5309,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
 
         r = kvm_mmu_reload(vcpu);
         if (unlikely(r)) {
-                kvm_x86_ops->cancel_injection(vcpu);
-                goto out;
+                goto cancel_injection;
         }
 
         preempt_disable();
@@ -5322,9 +5334,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
                 smp_wmb();
                 local_irq_enable();
                 preempt_enable();
-                kvm_x86_ops->cancel_injection(vcpu);
                 r = 1;
-                goto out;
+                goto cancel_injection;
         }
 
         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
@@ -5388,9 +5399,16 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
         if (unlikely(vcpu->arch.tsc_always_catchup))
                 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
 
-        kvm_lapic_sync_from_vapic(vcpu);
+        if (vcpu->arch.apic_attention)
+                kvm_lapic_sync_from_vapic(vcpu);
 
         r = kvm_x86_ops->handle_exit(vcpu);
+        return r;
+
+cancel_injection:
+        kvm_x86_ops->cancel_injection(vcpu);
+        if (unlikely(vcpu->arch.apic_attention))
+                kvm_lapic_sync_from_vapic(vcpu);
 out:
         return r;
 }
@@ -6304,7 +6322,7 @@ void kvm_arch_free_memslot(struct kvm_memory_slot *free,
 
         for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
                 if (!dont || free->arch.lpage_info[i] != dont->arch.lpage_info[i]) {
-                        vfree(free->arch.lpage_info[i]);
+                        kvm_kvfree(free->arch.lpage_info[i]);
                         free->arch.lpage_info[i] = NULL;
                 }
         }
@@ -6323,7 +6341,7 @@ int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
                                       slot->base_gfn, level) + 1;
 
                 slot->arch.lpage_info[i] =
-                        vzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
+                        kvm_kvzalloc(lpages * sizeof(*slot->arch.lpage_info[i]));
                 if (!slot->arch.lpage_info[i])
                         goto out_free;
 
@@ -6350,7 +6368,7 @@ int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
 
 out_free:
         for (i = 0; i < KVM_NR_PAGE_SIZES - 1; ++i) {
-                vfree(slot->arch.lpage_info[i]);
+                kvm_kvfree(slot->arch.lpage_info[i]);
                 slot->arch.lpage_info[i] = NULL;
         }
         return -ENOMEM;
diff --git a/arch/x86/lib/msr-reg-export.c b/arch/x86/lib/msr-reg-export.c
index a311cc59b65..8d6ef78b5d0 100644
--- a/arch/x86/lib/msr-reg-export.c
+++ b/arch/x86/lib/msr-reg-export.c
@@ -1,5 +1,5 @@
 #include <linux/module.h>
 #include <asm/msr.h>
 
-EXPORT_SYMBOL(native_rdmsr_safe_regs);
-EXPORT_SYMBOL(native_wrmsr_safe_regs);
+EXPORT_SYMBOL(rdmsr_safe_regs);
+EXPORT_SYMBOL(wrmsr_safe_regs);
diff --git a/arch/x86/lib/msr-reg.S b/arch/x86/lib/msr-reg.S
index 69fa10623f2..f6d13eefad1 100644
--- a/arch/x86/lib/msr-reg.S
+++ b/arch/x86/lib/msr-reg.S
@@ -6,13 +6,13 @@
 
 #ifdef CONFIG_X86_64
 /*
- * int native_{rdmsr,wrmsr}_safe_regs(u32 gprs[8]);
+ * int {rdmsr,wrmsr}_safe_regs(u32 gprs[8]);
  *
  * reg layout: u32 gprs[eax, ecx, edx, ebx, esp, ebp, esi, edi]
  *
  */
 .macro op_safe_regs op
-ENTRY(native_\op\()_safe_regs)
+ENTRY(\op\()_safe_regs)
         CFI_STARTPROC
         pushq_cfi %rbx
         pushq_cfi %rbp
@@ -45,13 +45,13 @@ ENTRY(native_\op\()_safe_regs)
 
         _ASM_EXTABLE(1b, 3b)
         CFI_ENDPROC
-ENDPROC(native_\op\()_safe_regs)
+ENDPROC(\op\()_safe_regs)
 .endm
 
 #else /* X86_32 */
 
 .macro op_safe_regs op
-ENTRY(native_\op\()_safe_regs)
+ENTRY(\op\()_safe_regs)
         CFI_STARTPROC
         pushl_cfi %ebx
         pushl_cfi %ebp
@@ -92,7 +92,7 @@ ENTRY(native_\op\()_safe_regs)
 
         _ASM_EXTABLE(1b, 3b)
         CFI_ENDPROC
-ENDPROC(native_\op\()_safe_regs)
+ENDPROC(\op\()_safe_regs)
 .endm
 
 #endif
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index f6679a7fb8c..b91e4851242 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -56,9 +56,16 @@ static int vma_shareable(struct vm_area_struct *vma, unsigned long addr)
 }
 
 /*
- * search for a shareable pmd page for hugetlb.
+ * Search for a shareable pmd page for hugetlb. In any case calls pmd_alloc()
+ * and returns the corresponding pte. While this is not necessary for the
+ * !shared pmd case because we can allocate the pmd later as well, it makes the
+ * code much cleaner. pmd allocation is essential for the shared case because
+ * pud has to be populated inside the same i_mmap_mutex section - otherwise
+ * racing tasks could either miss the sharing (see huge_pte_offset) or select a
+ * bad pmd for sharing.
  */
-static void huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
+static pte_t *
+huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
 {
         struct vm_area_struct *vma = find_vma(mm, addr);
         struct address_space *mapping = vma->vm_file->f_mapping;
@@ -68,9 +75,10 @@ static void huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
         struct vm_area_struct *svma;
         unsigned long saddr;
         pte_t *spte = NULL;
+        pte_t *pte;
 
         if (!vma_shareable(vma, addr))
-                return;
+                return (pte_t *)pmd_alloc(mm, pud, addr);
 
         mutex_lock(&mapping->i_mmap_mutex);
         vma_prio_tree_foreach(svma, &iter, &mapping->i_mmap, idx, idx) {
@@ -97,7 +105,9 @@ static void huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
                 put_page(virt_to_page(spte));
         spin_unlock(&mm->page_table_lock);
 out:
+        pte = (pte_t *)pmd_alloc(mm, pud, addr);
         mutex_unlock(&mapping->i_mmap_mutex);
+        return pte;
 }
 
 /*
@@ -142,8 +152,9 @@ pte_t *huge_pte_alloc(struct mm_struct *mm,
                 } else {
                         BUG_ON(sz != PMD_SIZE);
                         if (pud_none(*pud))
-                                huge_pmd_share(mm, addr, pud);
-                        pte = (pte_t *) pmd_alloc(mm, pud, addr);
+                                pte = huge_pmd_share(mm, addr, pud);
+                        else
+                                pte = (pte_t *)pmd_alloc(mm, pud, addr);
                 }
         }
         BUG_ON(pte && !pte_none(*pte) && !pte_huge(*pte));
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index bc4e9d84157..e0e6990723e 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -385,7 +385,7 @@ void free_initmem(void)
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
-void free_initrd_mem(unsigned long start, unsigned long end)
+void __init free_initrd_mem(unsigned long start, unsigned long end)
 {
         /*
          * end could be not aligned, and We can not align that,
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 575d86f85ce..4f04db15002 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -445,10 +445,10 @@ static inline void permanent_kmaps_init(pgd_t *pgd_base)
 }
 #endif /* CONFIG_HIGHMEM */
 
-void __init native_pagetable_setup_start(pgd_t *base)
+void __init native_pagetable_init(void)
 {
         unsigned long pfn, va;
-        pgd_t *pgd;
+        pgd_t *pgd, *base = swapper_pg_dir;
         pud_t *pud;
         pmd_t *pmd;
         pte_t *pte;
@@ -475,10 +475,7 @@ void __init native_pagetable_setup_start(pgd_t *base)
                 pte_clear(NULL, va, pte);
         }
         paravirt_alloc_pmd(&init_mm, __pa(base) >> PAGE_SHIFT);
-}
-
-void __init native_pagetable_setup_done(pgd_t *base)
-{
+        paging_init();
 }
 
 /*
@@ -493,7 +490,7 @@ void __init native_pagetable_setup_done(pgd_t *base)
  * If we're booting paravirtualized under a hypervisor, then there are
  * more options: we may already be running PAE, and the pagetable may
  * or may not be based in swapper_pg_dir.  In any case,
- * paravirt_pagetable_setup_start() will set up swapper_pg_dir
+ * paravirt_pagetable_init() will set up swapper_pg_dir
  * appropriately for the rest of the initialization to work.
  *
  * In general, pagetable_init() assumes that the pagetable may already
diff --git a/arch/x86/mm/srat.c b/arch/x86/mm/srat.c
index 4599c3e8bcb..4ddf497ca65 100644
--- a/arch/x86/mm/srat.c
+++ b/arch/x86/mm/srat.c
@@ -142,23 +142,23 @@ static inline int save_add_info(void) {return 0;}
 #endif
 
 /* Callback for parsing of the Proximity Domain <-> Memory Area mappings */
-void __init
+int __init
 acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
 {
         u64 start, end;
         int node, pxm;
 
         if (srat_disabled())
-                return;
+                return -1;
         if (ma->header.length != sizeof(struct acpi_srat_mem_affinity)) {
                 bad_srat();
-                return;
+                return -1;
         }
         if ((ma->flags & ACPI_SRAT_MEM_ENABLED) == 0)
-                return;
+                return -1;
 
         if ((ma->flags & ACPI_SRAT_MEM_HOT_PLUGGABLE) && !save_add_info())
-                return;
+                return -1;
         start = ma->base_address;
         end = start + ma->length;
         pxm = ma->proximity_domain;
@@ -168,12 +168,12 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
         if (node < 0) {
                 printk(KERN_ERR "SRAT: Too many proximity domains.\n");
                 bad_srat();
-                return;
+                return -1;
         }
 
         if (numa_add_memblk(node, start, end) < 0) {
                 bad_srat();
-                return;
+                return -1;
         }
 
         node_set(node, numa_nodes_parsed);
@@ -181,6 +181,7 @@ acpi_numa_memory_affinity_init(struct acpi_srat_mem_affinity *ma)
         printk(KERN_INFO "SRAT: Node %u PXM %u [mem %#010Lx-%#010Lx]\n",
                node, pxm,
                (unsigned long long) start, (unsigned long long) end - 1);
+        return 0;
 }
 
 void __init acpi_numa_arch_fixup(void) {}
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 5e57e113b72..613cd83e8c0 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -12,6 +12,7 @@
 #include <asm/cache.h>
 #include <asm/apic.h>
 #include <asm/uv/uv.h>
+#include <linux/debugfs.h>
 
 DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
                         = { &init_mm, 0, };
@@ -27,33 +28,14 @@ DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate)
  *
  *      More scalable flush, from Andi Kleen
  *
- *      To avoid global state use 8 different call vectors.
- *      Each CPU uses a specific vector to trigger flushes on other
- *      CPUs. Depending on the received vector the target CPUs look into
- *      the right array slot for the flush data.
- *
- *      With more than 8 CPUs they are hashed to the 8 available
- *      vectors. The limited global vector space forces us to this right now.
- *      In future when interrupts are split into per CPU domains this could be
- *      fixed, at the cost of triggering multiple IPIs in some cases.
+ *      Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
  */
 
-union smp_flush_state {
-        struct {
-                struct mm_struct *flush_mm;
-                unsigned long flush_va;
-                raw_spinlock_t tlbstate_lock;
-                DECLARE_BITMAP(flush_cpumask, NR_CPUS);
-        };
-        char pad[INTERNODE_CACHE_BYTES];
-} ____cacheline_internodealigned_in_smp;
-
-/* State is put into the per CPU data section, but padded
-   to a full cache line because other CPUs can access it and we don't
-   want false sharing in the per cpu data segment. */
-static union smp_flush_state flush_state[NUM_INVALIDATE_TLB_VECTORS];
-
-static DEFINE_PER_CPU_READ_MOSTLY(int, tlb_vector_offset);
+struct flush_tlb_info {
+        struct mm_struct *flush_mm;
+        unsigned long flush_start;
+        unsigned long flush_end;
+};
 
 /*
  * We cannot call mmdrop() because we are in interrupt context,
@@ -72,28 +54,25 @@ void leave_mm(int cpu)
 EXPORT_SYMBOL_GPL(leave_mm);
 
 /*
- *
  * The flush IPI assumes that a thread switch happens in this order:
  * [cpu0: the cpu that switches]
  * 1) switch_mm() either 1a) or 1b)
  * 1a) thread switch to a different mm
- * 1a1) cpu_clear(cpu, old_mm->cpu_vm_mask);
- *      Stop ipi delivery for the old mm. This is not synchronized with
- *      the other cpus, but smp_invalidate_interrupt ignore flush ipis
- *      for the wrong mm, and in the worst case we perform a superfluous
- *      tlb flush.
- * 1a2) set cpu mmu_state to TLBSTATE_OK
- *      Now the smp_invalidate_interrupt won't call leave_mm if cpu0
- *      was in lazy tlb mode.
- * 1a3) update cpu active_mm
+ * 1a1) set cpu_tlbstate to TLBSTATE_OK
+ *      Now the tlb flush NMI handler flush_tlb_func won't call leave_mm
+ *      if cpu0 was in lazy tlb mode.
+ * 1a2) update cpu active_mm
  *      Now cpu0 accepts tlb flushes for the new mm.
- * 1a4) cpu_set(cpu, new_mm->cpu_vm_mask);
+ * 1a3) cpu_set(cpu, new_mm->cpu_vm_mask);
  *      Now the other cpus will send tlb flush ipis.
  * 1a4) change cr3.
+ * 1a5) cpu_clear(cpu, old_mm->cpu_vm_mask);
+ *      Stop ipi delivery for the old mm. This is not synchronized with
+ *      the other cpus, but flush_tlb_func ignore flush ipis for the wrong
+ *      mm, and in the worst case we perform a superfluous tlb flush.
  * 1b) thread switch without mm change
- *      cpu active_mm is correct, cpu0 already handles
- *      flush ipis.
- * 1b1) set cpu mmu_state to TLBSTATE_OK
+ *      cpu active_mm is correct, cpu0 already handles flush ipis.
+ * 1b1) set cpu_tlbstate to TLBSTATE_OK
  * 1b2) test_and_set the cpu bit in cpu_vm_mask.
  *      Atomically set the bit [other cpus will start sending flush ipis],
  *      and test the bit.
@@ -106,174 +85,62 @@ EXPORT_SYMBOL_GPL(leave_mm);
  *   runs in kernel space, the cpu could load tlb entries for user space
  *   pages.
  *
- * The good news is that cpu mmu_state is local to each cpu, no
+ * The good news is that cpu_tlbstate is local to each cpu, no
  * write/read ordering problems.
  */
 
 /*
- * TLB flush IPI:
- *
+ * TLB flush funcation:
  * 1) Flush the tlb entries if the cpu uses the mm that's being flushed.
  * 2) Leave the mm if we are in the lazy tlb mode.
- *
- * Interrupts are disabled.
- */
-
-/*
- * FIXME: use of asmlinkage is not consistent.  On x86_64 it's noop
- * but still used for documentation purpose but the usage is slightly
- * inconsistent.  On x86_32, asmlinkage is regparm(0) but interrupt
- * entry calls in with the first parameter in %eax.  Maybe define
- * intrlinkage?
  */
-#ifdef CONFIG_X86_64
-asmlinkage
-#endif
-void smp_invalidate_interrupt(struct pt_regs *regs)
+static void flush_tlb_func(void *info)
 {
-        unsigned int cpu;
-        unsigned int sender;
-        union smp_flush_state *f;
-
-        cpu = smp_processor_id();
-        /*
-         * orig_rax contains the negated interrupt vector.
-         * Use that to determine where the sender put the data.
-         */
-        sender = ~regs->orig_ax - INVALIDATE_TLB_VECTOR_START;
-        f = &flush_state[sender];
-
-        if (!cpumask_test_cpu(cpu, to_cpumask(f->flush_cpumask)))
-                goto out;
-                /*
-                 * This was a BUG() but until someone can quote me the
-                 * line from the intel manual that guarantees an IPI to
-                 * multiple CPUs is retried _only_ on the erroring CPUs
-                 * its staying as a return
-                 *
-                 * BUG();
-                 */
-
-        if (f->flush_mm == this_cpu_read(cpu_tlbstate.active_mm)) {
-                if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
-                        if (f->flush_va == TLB_FLUSH_ALL)
-                                local_flush_tlb();
-                        else
-                                __flush_tlb_one(f->flush_va);
-                } else
-                        leave_mm(cpu);
-        }
-out:
-        ack_APIC_irq();
-        smp_mb__before_clear_bit();
-        cpumask_clear_cpu(cpu, to_cpumask(f->flush_cpumask));
-        smp_mb__after_clear_bit();
-        inc_irq_stat(irq_tlb_count);
-}
+        struct flush_tlb_info *f = info;
 
-static void flush_tlb_others_ipi(const struct cpumask *cpumask,
-                                 struct mm_struct *mm, unsigned long va)
-{
-        unsigned int sender;
-        union smp_flush_state *f;
-
-        /* Caller has disabled preemption */
-        sender = this_cpu_read(tlb_vector_offset);
-        f = &flush_state[sender];
-
-        if (nr_cpu_ids > NUM_INVALIDATE_TLB_VECTORS)
-                raw_spin_lock(&f->tlbstate_lock);
-
-        f->flush_mm = mm;
-        f->flush_va = va;
-        if (cpumask_andnot(to_cpumask(f->flush_cpumask), cpumask, cpumask_of(smp_processor_id()))) {
-                /*
-                 * We have to send the IPI only to
-                 * CPUs affected.
-                 */
-                apic->send_IPI_mask(to_cpumask(f->flush_cpumask),
-                              INVALIDATE_TLB_VECTOR_START + sender);
-
-                while (!cpumask_empty(to_cpumask(f->flush_cpumask)))
-                        cpu_relax();
-        }
+        if (f->flush_mm != this_cpu_read(cpu_tlbstate.active_mm))
+                return;
+
+        if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
+                if (f->flush_end == TLB_FLUSH_ALL || !cpu_has_invlpg)
+                        local_flush_tlb();
+                else if (!f->flush_end)
+                        __flush_tlb_single(f->flush_start);
+                else {
+                        unsigned long addr;
+                        addr = f->flush_start;
+                        while (addr < f->flush_end) {
+                                __flush_tlb_single(addr);
+                                addr += PAGE_SIZE;
+                        }
+                }
+        } else
+                leave_mm(smp_processor_id());
 
-        f->flush_mm = NULL;
-        f->flush_va = 0;
-        if (nr_cpu_ids > NUM_INVALIDATE_TLB_VECTORS)
-                raw_spin_unlock(&f->tlbstate_lock);
 }
 
 void native_flush_tlb_others(const struct cpumask *cpumask,
-                             struct mm_struct *mm, unsigned long va)
+                                 struct mm_struct *mm, unsigned long start,
+                                 unsigned long end)
 {
+        struct flush_tlb_info info;
+        info.flush_mm = mm;
+        info.flush_start = start;
+        info.flush_end = end;
+
         if (is_uv_system()) {
                 unsigned int cpu;
 
                 cpu = smp_processor_id();
-                cpumask = uv_flush_tlb_others(cpumask, mm, va, cpu);
+                cpumask = uv_flush_tlb_others(cpumask, mm, start, end, cpu);
                 if (cpumask)
-                        flush_tlb_others_ipi(cpumask, mm, va);
+                        smp_call_function_many(cpumask, flush_tlb_func,
+                                                                &info, 1);
                 return;
         }
-        flush_tlb_others_ipi(cpumask, mm, va);
+        smp_call_function_many(cpumask, flush_tlb_func, &info, 1);
 }
 
-static void __cpuinit calculate_tlb_offset(void)
-{
-        int cpu, node, nr_node_vecs, idx = 0;
-        /*
-         * we are changing tlb_vector_offset for each CPU in runtime, but this
-         * will not cause inconsistency, as the write is atomic under X86. we
-         * might see more lock contentions in a short time, but after all CPU's
-         * tlb_vector_offset are changed, everything should go normal
-         *
-         * Note: if NUM_INVALIDATE_TLB_VECTORS % nr_online_nodes !=0, we might
-         * waste some vectors.
-         **/
-        if (nr_online_nodes > NUM_INVALIDATE_TLB_VECTORS)
-                nr_node_vecs = 1;
-        else
-                nr_node_vecs = NUM_INVALIDATE_TLB_VECTORS/nr_online_nodes;
-
-        for_each_online_node(node) {
-                int node_offset = (idx % NUM_INVALIDATE_TLB_VECTORS) *
-                        nr_node_vecs;
-                int cpu_offset = 0;
-                for_each_cpu(cpu, cpumask_of_node(node)) {
-                        per_cpu(tlb_vector_offset, cpu) = node_offset +
-                                cpu_offset;
-                        cpu_offset++;
-                        cpu_offset = cpu_offset % nr_node_vecs;
-                }
-                idx++;
-        }
-}
-
-static int __cpuinit tlb_cpuhp_notify(struct notifier_block *n,
-                unsigned long action, void *hcpu)
-{
-        switch (action & 0xf) {
-        case CPU_ONLINE:
-        case CPU_DEAD:
-                calculate_tlb_offset();
-        }
-        return NOTIFY_OK;
-}
-
-static int __cpuinit init_smp_flush(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(flush_state); i++)
-                raw_spin_lock_init(&flush_state[i].tlbstate_lock);
-
-        calculate_tlb_offset();
-        hotcpu_notifier(tlb_cpuhp_notify, 0);
-        return 0;
-}
-core_initcall(init_smp_flush);
-
 void flush_tlb_current_task(void)
 {
         struct mm_struct *mm = current->mm;
@@ -282,27 +149,91 @@ void flush_tlb_current_task(void)
 
         local_flush_tlb();
         if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
-                flush_tlb_others(mm_cpumask(mm), mm, TLB_FLUSH_ALL);
+                flush_tlb_others(mm_cpumask(mm), mm, 0UL, TLB_FLUSH_ALL);
         preempt_enable();
 }
 
-void flush_tlb_mm(struct mm_struct *mm)
+/*
+ * It can find out the THP large page, or
+ * HUGETLB page in tlb_flush when THP disabled
+ */
+static inline unsigned long has_large_page(struct mm_struct *mm,
+                                 unsigned long start, unsigned long end)
+{
+        pgd_t *pgd;
+        pud_t *pud;
+        pmd_t *pmd;
+        unsigned long addr = ALIGN(start, HPAGE_SIZE);
+        for (; addr < end; addr += HPAGE_SIZE) {
+                pgd = pgd_offset(mm, addr);
+                if (likely(!pgd_none(*pgd))) {
+                        pud = pud_offset(pgd, addr);
+                        if (likely(!pud_none(*pud))) {
+                                pmd = pmd_offset(pud, addr);
+                                if (likely(!pmd_none(*pmd)))
+                                        if (pmd_large(*pmd))
+                                                return addr;
+                        }
+                }
+        }
+        return 0;
+}
+
+void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
+                                unsigned long end, unsigned long vmflag)
 {
+        unsigned long addr;
+        unsigned act_entries, tlb_entries = 0;
+
         preempt_disable();
+        if (current->active_mm != mm)
+                goto flush_all;
 
-        if (current->active_mm == mm) {
-                if (current->mm)
+        if (!current->mm) {
+                leave_mm(smp_processor_id());
+                goto flush_all;
+        }
+
+        if (end == TLB_FLUSH_ALL || tlb_flushall_shift == -1
+                                        || vmflag == VM_HUGETLB) {
+                local_flush_tlb();
+                goto flush_all;
+        }
+
+        /* In modern CPU, last level tlb used for both data/ins */
+        if (vmflag & VM_EXEC)
+                tlb_entries = tlb_lli_4k[ENTRIES];
+        else
+                tlb_entries = tlb_lld_4k[ENTRIES];
+        /* Assume all of TLB entries was occupied by this task */
+        act_entries = mm->total_vm > tlb_entries ? tlb_entries : mm->total_vm;
+
+        /* tlb_flushall_shift is on balance point, details in commit log */
+        if ((end - start) >> PAGE_SHIFT > act_entries >> tlb_flushall_shift)
+                local_flush_tlb();
+        else {
+                if (has_large_page(mm, start, end)) {
                         local_flush_tlb();
-                else
-                        leave_mm(smp_processor_id());
+                        goto flush_all;
+                }
+                /* flush range by one by one 'invlpg' */
+                for (addr = start; addr < end;  addr += PAGE_SIZE)
+                        __flush_tlb_single(addr);
+
+                if (cpumask_any_but(mm_cpumask(mm),
+                                smp_processor_id()) < nr_cpu_ids)
+                        flush_tlb_others(mm_cpumask(mm), mm, start, end);
+                preempt_enable();
+                return;
         }
-        if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
-                flush_tlb_others(mm_cpumask(mm), mm, TLB_FLUSH_ALL);
 
+flush_all:
+        if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
+                flush_tlb_others(mm_cpumask(mm), mm, 0UL, TLB_FLUSH_ALL);
         preempt_enable();
 }
 
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long start)
 {
         struct mm_struct *mm = vma->vm_mm;
 
@@ -310,13 +241,13 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
 
         if (current->active_mm == mm) {
                 if (current->mm)
-                        __flush_tlb_one(va);
+                        __flush_tlb_one(start);
                 else
                         leave_mm(smp_processor_id());
         }
 
         if (cpumask_any_but(mm_cpumask(mm), smp_processor_id()) < nr_cpu_ids)
-                flush_tlb_others(mm_cpumask(mm), mm, va);
+                flush_tlb_others(mm_cpumask(mm), mm, start, 0UL);
 
         preempt_enable();
 }
@@ -332,3 +263,83 @@ void flush_tlb_all(void)
 {
         on_each_cpu(do_flush_tlb_all, NULL, 1);
 }
+
+static void do_kernel_range_flush(void *info)
+{
+        struct flush_tlb_info *f = info;
+        unsigned long addr;
+
+        /* flush range by one by one 'invlpg' */
+        for (addr = f->flush_start; addr < f->flush_end; addr += PAGE_SIZE)
+                __flush_tlb_single(addr);
+}
+
+void flush_tlb_kernel_range(unsigned long start, unsigned long end)
+{
+        unsigned act_entries;
+        struct flush_tlb_info info;
+
+        /* In modern CPU, last level tlb used for both data/ins */
+        act_entries = tlb_lld_4k[ENTRIES];
+
+        /* Balance as user space task's flush, a bit conservative */
+        if (end == TLB_FLUSH_ALL || tlb_flushall_shift == -1 ||
+                (end - start) >> PAGE_SHIFT > act_entries >> tlb_flushall_shift)
+
+                on_each_cpu(do_flush_tlb_all, NULL, 1);
+        else {
+                info.flush_start = start;
+                info.flush_end = end;
+                on_each_cpu(do_kernel_range_flush, &info, 1);
+        }
+}
+
+#ifdef CONFIG_DEBUG_TLBFLUSH
+static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
+                             size_t count, loff_t *ppos)
+{
+        char buf[32];
+        unsigned int len;
+
+        len = sprintf(buf, "%hd\n", tlb_flushall_shift);
+        return simple_read_from_buffer(user_buf, count, ppos, buf, len);
+}
+
+static ssize_t tlbflush_write_file(struct file *file,
+                 const char __user *user_buf, size_t count, loff_t *ppos)
+{
+        char buf[32];
+        ssize_t len;
+        s8 shift;
+
+        len = min(count, sizeof(buf) - 1);
+        if (copy_from_user(buf, user_buf, len))
+                return -EFAULT;
+
+        buf[len] = '\0';
+        if (kstrtos8(buf, 0, &shift))
+                return -EINVAL;
+
+        if (shift > 64)
+                return -EINVAL;
+
+        tlb_flushall_shift = shift;
+        return count;
+}
+
+static const struct file_operations fops_tlbflush = {
+        .read = tlbflush_read_file,
+        .write = tlbflush_write_file,
+        .llseek = default_llseek,
+};
+
+static int __cpuinit create_tlb_flushall_shift(void)
+{
+        if (cpu_has_invlpg) {
+                debugfs_create_file("tlb_flushall_shift", S_IRUSR | S_IWUSR,
+                        arch_debugfs_dir, NULL, &fops_tlbflush);
+        }
+        return 0;
+}
+late_initcall(create_tlb_flushall_shift);
+#endif
diff --git a/arch/x86/net/bpf_jit_comp.c b/arch/x86/net/bpf_jit_comp.c
index 0597f95b6da..33643a8bcbb 100644
--- a/arch/x86/net/bpf_jit_comp.c
+++ b/arch/x86/net/bpf_jit_comp.c
@@ -309,6 +309,10 @@ void bpf_jit_compile(struct sk_filter *fp)
                                 else
                                         EMIT1_off32(0x0d, K);   /* or imm32,%eax */
                                 break;
+                        case BPF_S_ANC_ALU_XOR_X: /* A ^= X; */
+                                seen |= SEEN_XREG;
+                                EMIT2(0x31, 0xd8);              /* xor %ebx,%eax */
+                                break;
                         case BPF_S_ALU_LSH_X: /* A <<= X; */
                                 seen |= SEEN_XREG;
                                 EMIT4(0x89, 0xd9, 0xd3, 0xe0);  /* mov %ebx,%ecx; shl %cl,%eax */
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 303f0863782..b2b94438ff0 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -312,7 +312,7 @@ static int op_amd_fill_in_addresses(struct op_msrs * const msrs)
                         goto fail;
                 }
                 /* both registers must be reserved */
-                if (num_counters == AMD64_NUM_COUNTERS_F15H) {
+                if (num_counters == AMD64_NUM_COUNTERS_CORE) {
                         msrs->counters[i].addr = MSR_F15H_PERF_CTR + (i << 1);
                         msrs->controls[i].addr = MSR_F15H_PERF_CTL + (i << 1);
                 } else {
@@ -514,7 +514,7 @@ static int op_amd_init(struct oprofile_operations *ops)
         ops->create_files = setup_ibs_files;
 
         if (boot_cpu_data.x86 == 0x15) {
-                num_counters = AMD64_NUM_COUNTERS_F15H;
+                num_counters = AMD64_NUM_COUNTERS_CORE;
         } else {
                 num_counters = AMD64_NUM_COUNTERS;
         }
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index fc09c2754e0..505acdd6d60 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -12,8 +12,13 @@ struct pci_root_info {
         char name[16];
         unsigned int res_num;
         struct resource *res;
-        int busnum;
         struct pci_sysdata sd;
+#ifdef  CONFIG_PCI_MMCONFIG
+        bool mcfg_added;
+        u16 segment;
+        u8 start_bus;
+        u8 end_bus;
+#endif
 };
 
 static bool pci_use_crs = true;
@@ -120,6 +125,81 @@ void __init pci_acpi_crs_quirks(void)
                pci_use_crs ? "nocrs" : "use_crs");
 }
 
+#ifdef  CONFIG_PCI_MMCONFIG
+static int __devinit check_segment(u16 seg, struct device *dev, char *estr)
+{
+        if (seg) {
+                dev_err(dev,
+                        "%s can't access PCI configuration "
+                        "space under this host bridge.\n",
+                        estr);
+                return -EIO;
+        }
+
+        /*
+         * Failure in adding MMCFG information is not fatal,
+         * just can't access extended configuration space of
+         * devices under this host bridge.
+         */
+        dev_warn(dev,
+                 "%s can't access extended PCI configuration "
+                 "space under this bridge.\n",
+                 estr);
+
+        return 0;
+}
+
+static int __devinit setup_mcfg_map(struct pci_root_info *info,
+                                    u16 seg, u8 start, u8 end,
+                                    phys_addr_t addr)
+{
+        int result;
+        struct device *dev = &info->bridge->dev;
+
+        info->start_bus = start;
+        info->end_bus = end;
+        info->mcfg_added = false;
+
+        /* return success if MMCFG is not in use */
+        if (raw_pci_ext_ops && raw_pci_ext_ops != &pci_mmcfg)
+                return 0;
+
+        if (!(pci_probe & PCI_PROBE_MMCONF))
+                return check_segment(seg, dev, "MMCONFIG is disabled,");
+
+        result = pci_mmconfig_insert(dev, seg, start, end, addr);
+        if (result == 0) {
+                /* enable MMCFG if it hasn't been enabled yet */
+                if (raw_pci_ext_ops == NULL)
+                        raw_pci_ext_ops = &pci_mmcfg;
+                info->mcfg_added = true;
+        } else if (result != -EEXIST)
+                return check_segment(seg, dev,
+                         "fail to add MMCONFIG information,");
+
+        return 0;
+}
+
+static void teardown_mcfg_map(struct pci_root_info *info)
+{
+        if (info->mcfg_added) {
+                pci_mmconfig_delete(info->segment, info->start_bus,
+                                    info->end_bus);
+                info->mcfg_added = false;
+        }
+}
+#else
+static int __devinit setup_mcfg_map(struct pci_root_info *info,
+                                    u16 seg, u8 start, u8 end,
+                                    phys_addr_t addr)
+{
+        return 0;
+}
+static void teardown_mcfg_map(struct pci_root_info *info)
+{
+}
+#endif
+
 static acpi_status
 resource_to_addr(struct acpi_resource *resource,
                         struct acpi_resource_address64 *addr)
@@ -234,13 +314,6 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
         }
 
         info->res_num++;
-        if (addr.translation_offset)
-                dev_info(&info->bridge->dev, "host bridge window %pR "
-                         "(PCI address [%#llx-%#llx])\n",
-                         res, res->start - addr.translation_offset,
-                         res->end - addr.translation_offset);
-        else
-                dev_info(&info->bridge->dev, "host bridge window %pR\n", res);
 
         return AE_OK;
 }
@@ -332,8 +405,11 @@ static void __release_pci_root_info(struct pci_root_info *info)
 
         free_pci_root_info_res(info);
 
+        teardown_mcfg_map(info);
+
         kfree(info);
 }
+
 static void release_pci_root_info(struct pci_host_bridge *bridge)
 {
         struct pci_root_info *info = bridge->release_data;
@@ -347,7 +423,9 @@ probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
 {
         size_t size;
 
+        sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
         info->bridge = device;
+
         info->res_num = 0;
         acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource,
                                 info);
@@ -360,8 +438,6 @@ probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
         if (!info->res)
                 return;
 
-        sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
-
         acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource,
                                 info);
 }
@@ -373,7 +449,7 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
         int domain = root->segment;
         int busnum = root->secondary.start;
         LIST_HEAD(resources);
-        struct pci_bus *bus;
+        struct pci_bus *bus = NULL;
         struct pci_sysdata *sd;
         int node;
 #ifdef CONFIG_ACPI_NUMA
@@ -426,6 +502,8 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
         } else {
                 probe_pci_root_info(info, device, busnum, domain);
 
+                /* insert busn res at first */
+                pci_add_resource(&resources,  &root->secondary);
                 /*
                  * _CRS with no apertures is normal, so only fall back to
                  * defaults or native bridge info if we're ignoring _CRS.
@@ -437,10 +515,13 @@ struct pci_bus * __devinit pci_acpi_scan_root(struct acpi_pci_root *root)
                         x86_pci_root_bus_resources(busnum, &resources);
                 }
 
-                bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd,
-                                          &resources);
+                if (!setup_mcfg_map(info, domain, (u8)root->secondary.start,
+                                    (u8)root->secondary.end, root->mcfg_addr))
+                        bus = pci_create_root_bus(NULL, busnum, &pci_root_ops,
+                                                  sd, &resources);
+
                 if (bus) {
-                        bus->subordinate = pci_scan_child_bus(bus);
+                        pci_scan_child_bus(bus);
                         pci_set_host_bridge_release(
                                 to_pci_host_bridge(bus->bridge),
                                 release_pci_root_info, info);
diff --git a/arch/x86/pci/amd_bus.c b/arch/x86/pci/amd_bus.c
index 5aed49bff05..e9e6ed5cdf9 100644
--- a/arch/x86/pci/amd_bus.c
+++ b/arch/x86/pci/amd_bus.c
@@ -121,7 +121,6 @@ static int __init early_fill_mp_bus_info(void)
                 link = (reg >> 8) & 0x03;
 
                 info = alloc_pci_root_info(min_bus, max_bus, node, link);
-                sprintf(info->name, "PCI Bus #%02x", min_bus);
         }
 
         /* get the default node and link for left over res */
@@ -300,9 +299,9 @@ static int __init early_fill_mp_bus_info(void)
                 int busnum;
                 struct pci_root_res *root_res;
 
-                busnum = info->bus_min;
-                printk(KERN_DEBUG "bus: [%02x, %02x] on node %x link %x\n",
-                       info->bus_min, info->bus_max, info->node, info->link);
+                busnum = info->busn.start;
+                printk(KERN_DEBUG "bus: %pR on node %x link %x\n",
+                       &info->busn, info->node, info->link);
                 list_for_each_entry(root_res, &info->resources, list)
                         printk(KERN_DEBUG "bus: %02x %pR\n",
                                        busnum, &root_res->res);
diff --git a/arch/x86/pci/bus_numa.c b/arch/x86/pci/bus_numa.c
index 306579f7d0f..d37e2fec97e 100644
--- a/arch/x86/pci/bus_numa.c
+++ b/arch/x86/pci/bus_numa.c
@@ -14,7 +14,7 @@ static struct pci_root_info *x86_find_pci_root_info(int bus)
                 return NULL;
 
         list_for_each_entry(info, &pci_root_infos, list)
-                if (info->bus_min == bus)
+                if (info->busn.start == bus)
                         return info;
 
         return NULL;
@@ -24,6 +24,8 @@ void x86_pci_root_bus_resources(int bus, struct list_head *resources)
 {
         struct pci_root_info *info = x86_find_pci_root_info(bus);
         struct pci_root_res *root_res;
+        struct pci_host_bridge_window *window;
+        bool found = false;
 
         if (!info)
                 goto default_resources;
@@ -31,6 +33,16 @@ void x86_pci_root_bus_resources(int bus, struct list_head *resources)
         printk(KERN_DEBUG "PCI: root bus %02x: hardware-probed resources\n",
                bus);
 
+        /* already added by acpi ? */
+        list_for_each_entry(window, resources, list)
+                if (window->res->flags & IORESOURCE_BUS) {
+                        found = true;
+                        break;
+                }
+
+        if (!found)
+                pci_add_resource(resources, &info->busn);
+
         list_for_each_entry(root_res, &info->resources, list) {
                 struct resource *res;
                 struct resource *root;
@@ -66,9 +78,13 @@ struct pci_root_info __init *alloc_pci_root_info(int bus_min, int bus_max,
         if (!info)
                 return info;
 
+        sprintf(info->name, "PCI Bus #%02x", bus_min);
+
         INIT_LIST_HEAD(&info->resources);
-        info->bus_min = bus_min;
-        info->bus_max = bus_max;
+        info->busn.name  = info->name;
+        info->busn.start = bus_min;
+        info->busn.end   = bus_max;
+        info->busn.flags = IORESOURCE_BUS;
         info->node = node;
         info->link = link;
 
diff --git a/arch/x86/pci/bus_numa.h b/arch/x86/pci/bus_numa.h
index 226a466b2b2..ff8f65b0457 100644
--- a/arch/x86/pci/bus_numa.h
+++ b/arch/x86/pci/bus_numa.h
@@ -13,8 +13,7 @@ struct pci_root_info {
         struct list_head list;
         char name[12];
         struct list_head resources;
-        int bus_min;
-        int bus_max;
+        struct resource busn;
         int node;
         int link;
 };
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index 0ad990a20d4..720e973fc34 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -494,7 +494,7 @@ int __init pcibios_init(void)
         return 0;
 }
 
-char * __devinit  pcibios_setup(char *str)
+char * __init pcibios_setup(char *str)
 {
         if (!strcmp(str, "off")) {
                 pci_probe = 0;
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 301e325992f..937bcece700 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -17,6 +17,8 @@
 #include <linux/bitmap.h>
 #include <linux/dmi.h>
 #include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/rculist.h>
 #include <asm/e820.h>
 #include <asm/pci_x86.h>
 #include <asm/acpi.h>
@@ -24,7 +26,9 @@
 #define PREFIX "PCI: "
 
 /* Indicate if the mmcfg resources have been placed into the resource table. */
-static int __initdata pci_mmcfg_resources_inserted;
+static bool pci_mmcfg_running_state;
+static bool pci_mmcfg_arch_init_failed;
+static DEFINE_MUTEX(pci_mmcfg_lock);
 
 LIST_HEAD(pci_mmcfg_list);
 
@@ -45,24 +49,25 @@ static __init void free_all_mmcfg(void)
                 pci_mmconfig_remove(cfg);
 }
 
-static __init void list_add_sorted(struct pci_mmcfg_region *new)
+static __devinit void list_add_sorted(struct pci_mmcfg_region *new)
 {
         struct pci_mmcfg_region *cfg;
 
         /* keep list sorted by segment and starting bus number */
-        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
+        list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
                 if (cfg->segment > new->segment ||
                     (cfg->segment == new->segment &&
                      cfg->start_bus >= new->start_bus)) {
-                        list_add_tail(&new->list, &cfg->list);
+                        list_add_tail_rcu(&new->list, &cfg->list);
                         return;
                 }
         }
-        list_add_tail(&new->list, &pci_mmcfg_list);
+        list_add_tail_rcu(&new->list, &pci_mmcfg_list);
 }
 
-static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
-                                                        int end, u64 addr)
+static __devinit struct pci_mmcfg_region *pci_mmconfig_alloc(int segment,
+                                                             int start,
+                                                             int end, u64 addr)
 {
         struct pci_mmcfg_region *new;
         struct resource *res;
@@ -79,8 +84,6 @@ static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
         new->start_bus = start;
         new->end_bus = end;
 
-        list_add_sorted(new);
-
         res = &new->res;
         res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
         res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
@@ -89,9 +92,25 @@ static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
                  "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
         res->name = new->name;
 
-        printk(KERN_INFO PREFIX "MMCONFIG for domain %04x [bus %02x-%02x] at "
-               "%pR (base %#lx)\n", segment, start, end, &new->res,
-               (unsigned long) addr);
+        return new;
+}
+
+static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
+                                                        int end, u64 addr)
+{
+        struct pci_mmcfg_region *new;
+
+        new = pci_mmconfig_alloc(segment, start, end, addr);
+        if (new) {
+                mutex_lock(&pci_mmcfg_lock);
+                list_add_sorted(new);
+                mutex_unlock(&pci_mmcfg_lock);
+
+                pr_info(PREFIX
+                       "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
+                       "(base %#lx)\n",
+                       segment, start, end, &new->res, (unsigned long)addr);
+        }
 
         return new;
 }
@@ -100,7 +119,7 @@ struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
 {
         struct pci_mmcfg_region *cfg;
 
-        list_for_each_entry(cfg, &pci_mmcfg_list, list)
+        list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
                 if (cfg->segment == segment &&
                     cfg->start_bus <= bus && bus <= cfg->end_bus)
                         return cfg;
@@ -343,8 +362,7 @@ static int __init pci_mmcfg_check_hostbridge(void)
                         name = pci_mmcfg_probes[i].probe();
 
                 if (name)
-                        printk(KERN_INFO PREFIX "%s with MMCONFIG support\n",
-                               name);
+                        pr_info(PREFIX "%s with MMCONFIG support\n", name);
         }
 
         /* some end_bus_number is crazy, fix it */
@@ -353,19 +371,8 @@ static int __init pci_mmcfg_check_hostbridge(void)
         return !list_empty(&pci_mmcfg_list);
 }
 
-static void __init pci_mmcfg_insert_resources(void)
-{
-        struct pci_mmcfg_region *cfg;
-
-        list_for_each_entry(cfg, &pci_mmcfg_list, list)
-                insert_resource(&iomem_resource, &cfg->res);
-
-        /* Mark that the resources have been inserted. */
-        pci_mmcfg_resources_inserted = 1;
-}
-
-static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
-                                              void *data)
+static acpi_status __devinit check_mcfg_resource(struct acpi_resource *res,
+                                                 void *data)
 {
         struct resource *mcfg_res = data;
         struct acpi_resource_address64 address;
@@ -401,8 +408,8 @@ static acpi_status __init check_mcfg_resource(struct acpi_resource *res,
         return AE_OK;
 }
 
-static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
-                void *context, void **rv)
+static acpi_status __devinit find_mboard_resource(acpi_handle handle, u32 lvl,
+                                                  void *context, void **rv)
 {
         struct resource *mcfg_res = context;
 
@@ -415,7 +422,7 @@ static acpi_status __init find_mboard_resource(acpi_handle handle, u32 lvl,
         return AE_OK;
 }
 
-static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
+static int __devinit is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 {
         struct resource mcfg_res;
 
@@ -434,13 +441,15 @@ static int __init is_acpi_reserved(u64 start, u64 end, unsigned not_used)
 
 typedef int (*check_reserved_t)(u64 start, u64 end, unsigned type);
 
-static int __init is_mmconf_reserved(check_reserved_t is_reserved,
-                                    struct pci_mmcfg_region *cfg, int with_e820)
+static int __ref is_mmconf_reserved(check_reserved_t is_reserved,
+                                    struct pci_mmcfg_region *cfg,
+                                    struct device *dev, int with_e820)
 {
         u64 addr = cfg->res.start;
         u64 size = resource_size(&cfg->res);
         u64 old_size = size;
-        int valid = 0, num_buses;
+        int num_buses;
+        char *method = with_e820 ? "E820" : "ACPI motherboard resources";
 
         while (!is_reserved(addr, addr + size, E820_RESERVED)) {
                 size >>= 1;
@@ -448,30 +457,76 @@ static int __init is_mmconf_reserved(check_reserved_t is_reserved,
                         break;
         }
 
-        if (size >= (16UL<<20) || size == old_size) {
-                printk(KERN_INFO PREFIX "MMCONFIG at %pR reserved in %s\n",
-                       &cfg->res,
-                       with_e820 ? "E820" : "ACPI motherboard resources");
-                valid = 1;
-
-                if (old_size != size) {
-                        /* update end_bus */
-                        cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
-                        num_buses = cfg->end_bus - cfg->start_bus + 1;
-                        cfg->res.end = cfg->res.start +
-                            PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
-                        snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
-                                 "PCI MMCONFIG %04x [bus %02x-%02x]",
-                                 cfg->segment, cfg->start_bus, cfg->end_bus);
-                        printk(KERN_INFO PREFIX
-                               "MMCONFIG for %04x [bus%02x-%02x] "
-                               "at %pR (base %#lx) (size reduced!)\n",
-                               cfg->segment, cfg->start_bus, cfg->end_bus,
-                               &cfg->res, (unsigned long) cfg->address);
-                }
+        if (size < (16UL<<20) && size != old_size)
+                return 0;
+
+        if (dev)
+                dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
+                         &cfg->res, method);
+        else
+                pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
+                       &cfg->res, method);
+
+        if (old_size != size) {
+                /* update end_bus */
+                cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
+                num_buses = cfg->end_bus - cfg->start_bus + 1;
+                cfg->res.end = cfg->res.start +
+                    PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
+                snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
+                         "PCI MMCONFIG %04x [bus %02x-%02x]",
+                         cfg->segment, cfg->start_bus, cfg->end_bus);
+
+                if (dev)
+                        dev_info(dev,
+                                "MMCONFIG "
+                                "at %pR (base %#lx) (size reduced!)\n",
+                                &cfg->res, (unsigned long) cfg->address);
+                else
+                        pr_info(PREFIX
+                                "MMCONFIG for %04x [bus%02x-%02x] "
+                                "at %pR (base %#lx) (size reduced!)\n",
+                                cfg->segment, cfg->start_bus, cfg->end_bus,
+                                &cfg->res, (unsigned long) cfg->address);
         }
 
-        return valid;
+        return 1;
+}
+
+static int __ref pci_mmcfg_check_reserved(struct device *dev,
+                  struct pci_mmcfg_region *cfg, int early)
+{
+        if (!early && !acpi_disabled) {
+                if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
+                        return 1;
+
+                if (dev)
+                        dev_info(dev, FW_INFO
+                                 "MMCONFIG at %pR not reserved in "
+                                 "ACPI motherboard resources\n",
+                                 &cfg->res);
+                else
+                        pr_info(FW_INFO PREFIX
+                               "MMCONFIG at %pR not reserved in "
+                               "ACPI motherboard resources\n",
+                               &cfg->res);
+        }
+
+        /*
+         * e820_all_mapped() is marked as __init.
+         * All entries from ACPI MCFG table have been checked at boot time.
+         * For MCFG information constructed from hotpluggable host bridge's
+         * _CBA method, just assume it's reserved.
+         */
+        if (pci_mmcfg_running_state)
+                return 1;
+
+        /* Don't try to do this check unless configuration
+           type 1 is available. how about type 2 ?*/
+        if (raw_pci_ops)
+                return is_mmconf_reserved(e820_all_mapped, cfg, dev, 1);
+
+        return 0;
 }
 
 static void __init pci_mmcfg_reject_broken(int early)
@@ -479,38 +534,14 @@ static void __init pci_mmcfg_reject_broken(int early)
         struct pci_mmcfg_region *cfg;
 
         list_for_each_entry(cfg, &pci_mmcfg_list, list) {
-                int valid = 0;
-
-                if (!early && !acpi_disabled) {
-                        valid = is_mmconf_reserved(is_acpi_reserved, cfg, 0);
-
-                        if (valid)
-                                continue;
-                        else
-                                printk(KERN_ERR FW_BUG PREFIX
-                                       "MMCONFIG at %pR not reserved in "
-                                       "ACPI motherboard resources\n",
-                                       &cfg->res);
+                if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
+                        pr_info(PREFIX "not using MMCONFIG\n");
+                        free_all_mmcfg();
+                        return;
                 }
-
-                /* Don't try to do this check unless configuration
-                   type 1 is available. how about type 2 ?*/
-                if (raw_pci_ops)
-                        valid = is_mmconf_reserved(e820_all_mapped, cfg, 1);
-
-                if (!valid)
-                        goto reject;
         }
-
-        return;
-
-reject:
-        printk(KERN_INFO PREFIX "not using MMCONFIG\n");
-        free_all_mmcfg();
 }
 
-static int __initdata known_bridge;
-
 static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
                                         struct acpi_mcfg_allocation *cfg)
 {
@@ -529,7 +560,7 @@ static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
                         return 0;
         }
 
-        printk(KERN_ERR PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
+        pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
                "is above 4GB, ignored\n", cfg->pci_segment,
                cfg->start_bus_number, cfg->end_bus_number, cfg->address);
         return -EINVAL;
@@ -556,7 +587,7 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header)
                 i -= sizeof(struct acpi_mcfg_allocation);
         };
         if (entries == 0) {
-                printk(KERN_ERR PREFIX "MMCONFIG has no entries\n");
+                pr_err(PREFIX "MMCONFIG has no entries\n");
                 return -ENODEV;
         }
 
@@ -570,8 +601,7 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header)
 
                 if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
                                    cfg->end_bus_number, cfg->address) == NULL) {
-                        printk(KERN_WARNING PREFIX
-                               "no memory for MCFG entries\n");
+                        pr_warn(PREFIX "no memory for MCFG entries\n");
                         free_all_mmcfg();
                         return -ENOMEM;
                 }
@@ -582,28 +612,7 @@ static int __init pci_parse_mcfg(struct acpi_table_header *header)
 
 static void __init __pci_mmcfg_init(int early)
 {
-        /* MMCONFIG disabled */
-        if ((pci_probe & PCI_PROBE_MMCONF) == 0)
-                return;
-
-        /* MMCONFIG already enabled */
-        if (!early && !(pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF))
-                return;
-
-        /* for late to exit */
-        if (known_bridge)
-                return;
-
-        if (early) {
-                if (pci_mmcfg_check_hostbridge())
-                        known_bridge = 1;
-        }
-
-        if (!known_bridge)
-                acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
-
         pci_mmcfg_reject_broken(early);
-
         if (list_empty(&pci_mmcfg_list))
                 return;
 
@@ -620,33 +629,48 @@ static void __init __pci_mmcfg_init(int early)
         if (pci_mmcfg_arch_init())
                 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
         else {
-                /*
-                 * Signal not to attempt to insert mmcfg resources because
-                 * the architecture mmcfg setup could not initialize.
-                 */
-                pci_mmcfg_resources_inserted = 1;
+                free_all_mmcfg();
+                pci_mmcfg_arch_init_failed = true;
         }
 }
 
+static int __initdata known_bridge;
+
 void __init pci_mmcfg_early_init(void)
 {
-        __pci_mmcfg_init(1);
+        if (pci_probe & PCI_PROBE_MMCONF) {
+                if (pci_mmcfg_check_hostbridge())
+                        known_bridge = 1;
+                else
+                        acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
+                __pci_mmcfg_init(1);
+        }
 }
 
 void __init pci_mmcfg_late_init(void)
 {
-        __pci_mmcfg_init(0);
+        /* MMCONFIG disabled */
+        if ((pci_probe & PCI_PROBE_MMCONF) == 0)
+                return;
+
+        if (known_bridge)
+                return;
+
+        /* MMCONFIG hasn't been enabled yet, try again */
+        if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
+                acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
+                __pci_mmcfg_init(0);
+        }
 }
 
 static int __init pci_mmcfg_late_insert_resources(void)
 {
-        /*
-         * If resources are already inserted or we are not using MMCONFIG,
-         * don't insert the resources.
-         */
-        if ((pci_mmcfg_resources_inserted == 1) ||
-            (pci_probe & PCI_PROBE_MMCONF) == 0 ||
-            list_empty(&pci_mmcfg_list))
+        struct pci_mmcfg_region *cfg;
+
+        pci_mmcfg_running_state = true;
+
+        /* If we are not using MMCONFIG, don't insert the resources. */
+        if ((pci_probe & PCI_PROBE_MMCONF) == 0)
                 return 1;
 
         /*
@@ -654,7 +678,9 @@ static int __init pci_mmcfg_late_insert_resources(void)
          * marked so it won't cause request errors when __request_region is
          * called.
          */
-        pci_mmcfg_insert_resources();
+        list_for_each_entry(cfg, &pci_mmcfg_list, list)
+                if (!cfg->res.parent)
+                        insert_resource(&iomem_resource, &cfg->res);
 
         return 0;
 }
@@ -665,3 +691,101 @@ static int __init pci_mmcfg_late_insert_resources(void)
  * with other system resources.
  */
 late_initcall(pci_mmcfg_late_insert_resources);
+
+/* Add MMCFG information for host bridges */
+int __devinit pci_mmconfig_insert(struct device *dev,
+                                  u16 seg, u8 start, u8 end,
+                                  phys_addr_t addr)
+{
+        int rc;
+        struct resource *tmp = NULL;
+        struct pci_mmcfg_region *cfg;
+
+        if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
+                return -ENODEV;
+
+        if (start > end)
+                return -EINVAL;
+
+        mutex_lock(&pci_mmcfg_lock);
+        cfg = pci_mmconfig_lookup(seg, start);
+        if (cfg) {
+                if (cfg->end_bus < end)
+                        dev_info(dev, FW_INFO
+                                 "MMCONFIG for "
+                                 "domain %04x [bus %02x-%02x] "
+                                 "only partially covers this bridge\n",
+                                  cfg->segment, cfg->start_bus, cfg->end_bus);
+                mutex_unlock(&pci_mmcfg_lock);
+                return -EEXIST;
+        }
+
+        if (!addr) {
+                mutex_unlock(&pci_mmcfg_lock);
+                return -EINVAL;
+        }
+
+        rc = -EBUSY;
+        cfg = pci_mmconfig_alloc(seg, start, end, addr);
+        if (cfg == NULL) {
+                dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
+                rc = -ENOMEM;
+        } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
+                dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
+                         &cfg->res);
+        } else {
+                /* Insert resource if it's not in boot stage */
+                if (pci_mmcfg_running_state)
+                        tmp = insert_resource_conflict(&iomem_resource,
+                                                       &cfg->res);
+
+                if (tmp) {
+                        dev_warn(dev,
+                                 "MMCONFIG %pR conflicts with "
+                                 "%s %pR\n",
+                                 &cfg->res, tmp->name, tmp);
+                } else if (pci_mmcfg_arch_map(cfg)) {
+                        dev_warn(dev, "fail to map MMCONFIG %pR.\n",
+                                 &cfg->res);
+                } else {
+                        list_add_sorted(cfg);
+                        dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
+                                 &cfg->res, (unsigned long)addr);
+                        cfg = NULL;
+                        rc = 0;
+                }
+        }
+
+        if (cfg) {
+                if (cfg->res.parent)
+                        release_resource(&cfg->res);
+                kfree(cfg);
+        }
+
+        mutex_unlock(&pci_mmcfg_lock);
+
+        return rc;
+}
+
+/* Delete MMCFG information for host bridges */
+int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
+{
+        struct pci_mmcfg_region *cfg;
+
+        mutex_lock(&pci_mmcfg_lock);
+        list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
+                if (cfg->segment == seg && cfg->start_bus == start &&
+                    cfg->end_bus == end) {
+                        list_del_rcu(&cfg->list);
+                        synchronize_rcu();
+                        pci_mmcfg_arch_unmap(cfg);
+                        if (cfg->res.parent)
+                                release_resource(&cfg->res);
+                        mutex_unlock(&pci_mmcfg_lock);
+                        kfree(cfg);
+                        return 0;
+                }
+        mutex_unlock(&pci_mmcfg_lock);
+
+        return -ENOENT;
+}
diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c
index 5372e86834c..db63ac23e3d 100644
--- a/arch/x86/pci/mmconfig_32.c
+++ b/arch/x86/pci/mmconfig_32.c
@@ -11,6 +11,7 @@
 
 #include <linux/pci.h>
 #include <linux/init.h>
+#include <linux/rcupdate.h>
 #include <asm/e820.h>
 #include <asm/pci_x86.h>
 #include <acpi/acpi.h>
@@ -60,9 +61,12 @@ err:		*value = -1;
                 return -EINVAL;
         }
 
+        rcu_read_lock();
         base = get_base_addr(seg, bus, devfn);
-        if (!base)
+        if (!base) {
+                rcu_read_unlock();
                 goto err;
+        }
 
         raw_spin_lock_irqsave(&pci_config_lock, flags);
 
@@ -80,6 +84,7 @@ err:		*value = -1;
                 break;
         }
         raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+        rcu_read_unlock();
 
         return 0;
 }
@@ -93,9 +98,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
         if ((bus > 255) || (devfn > 255) || (reg > 4095))
                 return -EINVAL;
 
+        rcu_read_lock();
         base = get_base_addr(seg, bus, devfn);
-        if (!base)
+        if (!base) {
+                rcu_read_unlock();
                 return -EINVAL;
+        }
 
         raw_spin_lock_irqsave(&pci_config_lock, flags);
 
@@ -113,11 +121,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
                 break;
         }
         raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+        rcu_read_unlock();
 
         return 0;
 }
 
-static const struct pci_raw_ops pci_mmcfg = {
+const struct pci_raw_ops pci_mmcfg = {
         .read =         pci_mmcfg_read,
         .write =        pci_mmcfg_write,
 };
@@ -132,3 +141,18 @@ int __init pci_mmcfg_arch_init(void)
 void __init pci_mmcfg_arch_free(void)
 {
 }
+
+int __devinit pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
+{
+        return 0;
+}
+
+void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
+{
+        unsigned long flags;
+
+        /* Invalidate the cached mmcfg map entry. */
+        raw_spin_lock_irqsave(&pci_config_lock, flags);
+        mmcfg_last_accessed_device = 0;
+        raw_spin_unlock_irqrestore(&pci_config_lock, flags);
+}
diff --git a/arch/x86/pci/mmconfig_64.c b/arch/x86/pci/mmconfig_64.c
index 915a493502c..d4ebd07c306 100644
--- a/arch/x86/pci/mmconfig_64.c
+++ b/arch/x86/pci/mmconfig_64.c
@@ -9,6 +9,7 @@
 #include <linux/init.h>
 #include <linux/acpi.h>
 #include <linux/bitmap.h>
+#include <linux/rcupdate.h>
 #include <asm/e820.h>
 #include <asm/pci_x86.h>
 
@@ -34,9 +35,12 @@ err:		*value = -1;
                 return -EINVAL;
         }
 
+        rcu_read_lock();
         addr = pci_dev_base(seg, bus, devfn);
-        if (!addr)
+        if (!addr) {
+                rcu_read_unlock();
                 goto err;
+        }
 
         switch (len) {
         case 1:
@@ -49,6 +53,7 @@ err:		*value = -1;
                 *value = mmio_config_readl(addr + reg);
                 break;
         }
+        rcu_read_unlock();
 
         return 0;
 }
@@ -62,9 +67,12 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
         if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
                 return -EINVAL;
 
+        rcu_read_lock();
         addr = pci_dev_base(seg, bus, devfn);
-        if (!addr)
+        if (!addr) {
+                rcu_read_unlock();
                 return -EINVAL;
+        }
 
         switch (len) {
         case 1:
@@ -77,16 +85,17 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
                 mmio_config_writel(addr + reg, value);
                 break;
         }
+        rcu_read_unlock();
 
         return 0;
 }
 
-static const struct pci_raw_ops pci_mmcfg = {
+const struct pci_raw_ops pci_mmcfg = {
         .read =         pci_mmcfg_read,
         .write =        pci_mmcfg_write,
 };
 
-static void __iomem * __init mcfg_ioremap(struct pci_mmcfg_region *cfg)
+static void __iomem * __devinit mcfg_ioremap(struct pci_mmcfg_region *cfg)
 {
         void __iomem *addr;
         u64 start, size;
@@ -105,16 +114,14 @@ int __init pci_mmcfg_arch_init(void)
 {
         struct pci_mmcfg_region *cfg;
 
-        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
-                cfg->virt = mcfg_ioremap(cfg);
-                if (!cfg->virt) {
-                        printk(KERN_ERR PREFIX "can't map MMCONFIG at %pR\n",
-                               &cfg->res);
+        list_for_each_entry(cfg, &pci_mmcfg_list, list)
+                if (pci_mmcfg_arch_map(cfg)) {
                         pci_mmcfg_arch_free();
                         return 0;
                 }
-        }
+
         raw_pci_ext_ops = &pci_mmcfg;
+
         return 1;
 }
 
@@ -122,10 +129,25 @@ void __init pci_mmcfg_arch_free(void)
 {
         struct pci_mmcfg_region *cfg;
 
-        list_for_each_entry(cfg, &pci_mmcfg_list, list) {
-                if (cfg->virt) {
-                        iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
-                        cfg->virt = NULL;
-                }
+        list_for_each_entry(cfg, &pci_mmcfg_list, list)
+                pci_mmcfg_arch_unmap(cfg);
+}
+
+int __devinit pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
+{
+        cfg->virt = mcfg_ioremap(cfg);
+        if (!cfg->virt) {
+                pr_err(PREFIX "can't map MMCONFIG at %pR\n", &cfg->res);
+                return -ENOMEM;
+        }
+
+        return 0;
+}
+
+void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
+{
+        if (cfg && cfg->virt) {
+                iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
+                cfg->virt = NULL;
         }
 }
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index 140942f66b3..e14a2ff708b 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -264,7 +264,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
 
 static void __devinit mrst_power_off_unused_dev(struct pci_dev *dev)
 {
-        pci_set_power_state(dev, PCI_D3cold);
+        pci_set_power_state(dev, PCI_D3hot);
 }
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
diff --git a/arch/x86/platform/olpc/olpc-xo1-pm.c b/arch/x86/platform/olpc/olpc-xo1-pm.c
index 0ce8616c88a..d75582d1aa5 100644
--- a/arch/x86/platform/olpc/olpc-xo1-pm.c
+++ b/arch/x86/platform/olpc/olpc-xo1-pm.c
@@ -18,6 +18,7 @@
 #include <linux/pm.h>
 #include <linux/mfd/core.h>
 #include <linux/suspend.h>
+#include <linux/olpc-ec.h>
 
 #include <asm/io.h>
 #include <asm/olpc.h>
@@ -51,16 +52,11 @@ EXPORT_SYMBOL_GPL(olpc_xo1_pm_wakeup_clear);
 static int xo1_power_state_enter(suspend_state_t pm_state)
 {
         unsigned long saved_sci_mask;
-        int r;
 
         /* Only STR is supported */
         if (pm_state != PM_SUSPEND_MEM)
                 return -EINVAL;
 
-        r = olpc_ec_cmd(EC_SET_SCI_INHIBIT, NULL, 0, NULL, 0);
-        if (r)
-                return r;
-
         /*
          * Save SCI mask (this gets lost since PM1_EN is used as a mask for
          * wakeup events, which is not necessarily the same event set)
@@ -76,16 +72,6 @@ static int xo1_power_state_enter(suspend_state_t pm_state)
         /* Restore SCI mask (using dword access to CS5536_PM1_EN) */
         outl(saved_sci_mask, acpi_base + CS5536_PM1_STS);
 
-        /* Tell the EC to stop inhibiting SCIs */
-        olpc_ec_cmd(EC_SET_SCI_INHIBIT_RELEASE, NULL, 0, NULL, 0);
-
-        /*
-         * Tell the wireless module to restart USB communication.
-         * Must be done twice.
-         */
-        olpc_ec_cmd(EC_WAKE_UP_WLAN, NULL, 0, NULL, 0);
-        olpc_ec_cmd(EC_WAKE_UP_WLAN, NULL, 0, NULL, 0);
-
         return 0;
 }
 
diff --git a/arch/x86/platform/olpc/olpc-xo1-sci.c b/arch/x86/platform/olpc/olpc-xo1-sci.c
index 04b8c73659c..63d4aa40956 100644
--- a/arch/x86/platform/olpc/olpc-xo1-sci.c
+++ b/arch/x86/platform/olpc/olpc-xo1-sci.c
@@ -23,6 +23,7 @@
 #include <linux/power_supply.h>
 #include <linux/suspend.h>
 #include <linux/workqueue.h>
+#include <linux/olpc-ec.h>
 
 #include <asm/io.h>
 #include <asm/msr.h>
diff --git a/arch/x86/platform/olpc/olpc-xo15-sci.c b/arch/x86/platform/olpc/olpc-xo15-sci.c
index 23e5b9d7977..2fdca25905a 100644
--- a/arch/x86/platform/olpc/olpc-xo15-sci.c
+++ b/arch/x86/platform/olpc/olpc-xo15-sci.c
@@ -13,6 +13,7 @@
 #include <linux/slab.h>
 #include <linux/workqueue.h>
 #include <linux/power_supply.h>
+#include <linux/olpc-ec.h>
 
 #include <acpi/acpi_bus.h>
 #include <acpi/acpi_drivers.h>
@@ -203,7 +204,7 @@ static int xo15_sci_remove(struct acpi_device *device, int type)
         return 0;
 }
 
-static int xo15_sci_resume(struct acpi_device *device)
+static int xo15_sci_resume(struct device *dev)
 {
         /* Enable all EC events */
         olpc_ec_mask_write(EC_SCI_SRC_ALL);
@@ -215,6 +216,8 @@ static int xo15_sci_resume(struct acpi_device *device)
         return 0;
 }
 
+static SIMPLE_DEV_PM_OPS(xo15_sci_pm, NULL, xo15_sci_resume);
+
 static const struct acpi_device_id xo15_sci_device_ids[] = {
         {"XO15EC", 0},
         {"", 0},
@@ -227,8 +230,8 @@ static struct acpi_driver xo15_sci_drv = {
         .ops = {
                 .add = xo15_sci_add,
                 .remove = xo15_sci_remove,
-                .resume = xo15_sci_resume,
         },
+        .drv.pm = &xo15_sci_pm,
 };
 
 static int __init xo15_sci_init(void)
diff --git a/arch/x86/platform/olpc/olpc.c b/arch/x86/platform/olpc/olpc.c
index a4bee53c2e5..27376081dde 100644
--- a/arch/x86/platform/olpc/olpc.c
+++ b/arch/x86/platform/olpc/olpc.c
@@ -14,14 +14,13 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/delay.h>
-#include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/string.h>
 #include <linux/platform_device.h>
 #include <linux/of.h>
 #include <linux/syscore_ops.h>
-#include <linux/debugfs.h>
 #include <linux/mutex.h>
+#include <linux/olpc-ec.h>
 
 #include <asm/geode.h>
 #include <asm/setup.h>
@@ -31,17 +30,6 @@
 struct olpc_platform_t olpc_platform_info;
 EXPORT_SYMBOL_GPL(olpc_platform_info);
 
-static DEFINE_SPINLOCK(ec_lock);
-
-/* debugfs interface to EC commands */
-#define EC_MAX_CMD_ARGS (5 + 1) /* cmd byte + 5 args */
-#define EC_MAX_CMD_REPLY (8)
-
-static struct dentry *ec_debugfs_dir;
-static DEFINE_MUTEX(ec_debugfs_cmd_lock);
-static unsigned char ec_debugfs_resp[EC_MAX_CMD_REPLY];
-static unsigned int ec_debugfs_resp_bytes;
-
 /* EC event mask to be applied during suspend (defining wakeup sources). */
 static u16 ec_wakeup_mask;
 
@@ -125,16 +113,13 @@ static int __wait_on_obf(unsigned int line, unsigned int port, int desired)
  * <http://wiki.laptop.org/go/Ec_specification>.  Unfortunately, while
  * OpenFirmware's source is available, the EC's is not.
  */
-int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
-                unsigned char *outbuf,  size_t outlen)
+static int olpc_xo1_ec_cmd(u8 cmd, u8 *inbuf, size_t inlen, u8 *outbuf,
+                size_t outlen, void *arg)
 {
-        unsigned long flags;
         int ret = -EIO;
         int i;
         int restarts = 0;
 
-        spin_lock_irqsave(&ec_lock, flags);
-
         /* Clear OBF */
         for (i = 0; i < 10 && (obf_status(0x6c) == 1); i++)
                 inb(0x68);
@@ -198,10 +183,8 @@ restart:
 
         ret = 0;
 err:
-        spin_unlock_irqrestore(&ec_lock, flags);
         return ret;
 }
-EXPORT_SYMBOL_GPL(olpc_ec_cmd);
 
 void olpc_ec_wakeup_set(u16 value)
 {
@@ -280,96 +263,6 @@ int olpc_ec_sci_query(u16 *sci_value)
 }
 EXPORT_SYMBOL_GPL(olpc_ec_sci_query);
 
-static ssize_t ec_debugfs_cmd_write(struct file *file, const char __user *buf,
-                                    size_t size, loff_t *ppos)
-{
-        int i, m;
-        unsigned char ec_cmd[EC_MAX_CMD_ARGS];
-        unsigned int ec_cmd_int[EC_MAX_CMD_ARGS];
-        char cmdbuf[64];
-        int ec_cmd_bytes;
-
-        mutex_lock(&ec_debugfs_cmd_lock);
-
-        size = simple_write_to_buffer(cmdbuf, sizeof(cmdbuf), ppos, buf, size);
-
-        m = sscanf(cmdbuf, "%x:%u %x %x %x %x %x", &ec_cmd_int[0],
-                   &ec_debugfs_resp_bytes,
-                   &ec_cmd_int[1], &ec_cmd_int[2], &ec_cmd_int[3],
-                   &ec_cmd_int[4], &ec_cmd_int[5]);
-        if (m < 2 || ec_debugfs_resp_bytes > EC_MAX_CMD_REPLY) {
-                /* reset to prevent overflow on read */
-                ec_debugfs_resp_bytes = 0;
-
-                printk(KERN_DEBUG "olpc-ec: bad ec cmd:  "
-                       "cmd:response-count [arg1 [arg2 ...]]\n");
-                size = -EINVAL;
-                goto out;
-        }
-
-        /* convert scanf'd ints to char */
-        ec_cmd_bytes = m - 2;
-        for (i = 0; i <= ec_cmd_bytes; i++)
-                ec_cmd[i] = ec_cmd_int[i];
-
-        printk(KERN_DEBUG "olpc-ec: debugfs cmd 0x%02x with %d args "
-               "%02x %02x %02x %02x %02x, want %d returns\n",
-               ec_cmd[0], ec_cmd_bytes, ec_cmd[1], ec_cmd[2], ec_cmd[3],
-               ec_cmd[4], ec_cmd[5], ec_debugfs_resp_bytes);
-
-        olpc_ec_cmd(ec_cmd[0], (ec_cmd_bytes == 0) ? NULL : &ec_cmd[1],
-                    ec_cmd_bytes, ec_debugfs_resp, ec_debugfs_resp_bytes);
-
-        printk(KERN_DEBUG "olpc-ec: response "
-               "%02x %02x %02x %02x %02x %02x %02x %02x (%d bytes expected)\n",
-               ec_debugfs_resp[0], ec_debugfs_resp[1], ec_debugfs_resp[2],
-               ec_debugfs_resp[3], ec_debugfs_resp[4], ec_debugfs_resp[5],
-               ec_debugfs_resp[6], ec_debugfs_resp[7], ec_debugfs_resp_bytes);
-
-out:
-        mutex_unlock(&ec_debugfs_cmd_lock);
-        return size;
-}
-
-static ssize_t ec_debugfs_cmd_read(struct file *file, char __user *buf,
-                                   size_t size, loff_t *ppos)
-{
-        unsigned int i, r;
-        char *rp;
-        char respbuf[64];
-
-        mutex_lock(&ec_debugfs_cmd_lock);
-        rp = respbuf;
-        rp += sprintf(rp, "%02x", ec_debugfs_resp[0]);
-        for (i = 1; i < ec_debugfs_resp_bytes; i++)
-                rp += sprintf(rp, ", %02x", ec_debugfs_resp[i]);
-        mutex_unlock(&ec_debugfs_cmd_lock);
-        rp += sprintf(rp, "\n");
-
-        r = rp - respbuf;
-        return simple_read_from_buffer(buf, size, ppos, respbuf, r);
-}
-
-static const struct file_operations ec_debugfs_genops = {
-        .write   = ec_debugfs_cmd_write,
-        .read    = ec_debugfs_cmd_read,
-};
-
-static void setup_debugfs(void)
-{
-        ec_debugfs_dir = debugfs_create_dir("olpc-ec", 0);
-        if (ec_debugfs_dir == ERR_PTR(-ENODEV))
-                return;
-
-        debugfs_create_file("cmd", 0600, ec_debugfs_dir, NULL,
-                            &ec_debugfs_genops);
-}
-
-static int olpc_ec_suspend(void)
-{
-        return olpc_ec_mask_write(ec_wakeup_mask);
-}
-
 static bool __init check_ofw_architecture(struct device_node *root)
 {
         const char *olpc_arch;
@@ -424,8 +317,59 @@ static int __init add_xo1_platform_devices(void)
         return 0;
 }
 
-static struct syscore_ops olpc_syscore_ops = {
-        .suspend = olpc_ec_suspend,
+static int olpc_xo1_ec_probe(struct platform_device *pdev)
+{
+        /* get the EC revision */
+        olpc_ec_cmd(EC_FIRMWARE_REV, NULL, 0,
+                        (unsigned char *) &olpc_platform_info.ecver, 1);
+
+        /* EC version 0x5f adds support for wide SCI mask */
+        if (olpc_platform_info.ecver >= 0x5f)
+                olpc_platform_info.flags |= OLPC_F_EC_WIDE_SCI;
+
+        pr_info("OLPC board revision %s%X (EC=%x)\n",
+                        ((olpc_platform_info.boardrev & 0xf) < 8) ? "pre" : "",
+                        olpc_platform_info.boardrev >> 4,
+                        olpc_platform_info.ecver);
+
+        return 0;
+}
+static int olpc_xo1_ec_suspend(struct platform_device *pdev)
+{
+        olpc_ec_mask_write(ec_wakeup_mask);
+
+        /*
+         * Squelch SCIs while suspended.  This is a fix for
+         * <http://dev.laptop.org/ticket/1835>.
+         */
+        return olpc_ec_cmd(EC_SET_SCI_INHIBIT, NULL, 0, NULL, 0);
+}
+
+static int olpc_xo1_ec_resume(struct platform_device *pdev)
+{
+        /* Tell the EC to stop inhibiting SCIs */
+        olpc_ec_cmd(EC_SET_SCI_INHIBIT_RELEASE, NULL, 0, NULL, 0);
+
+        /*
+         * Tell the wireless module to restart USB communication.
+         * Must be done twice.
+         */
+        olpc_ec_cmd(EC_WAKE_UP_WLAN, NULL, 0, NULL, 0);
+        olpc_ec_cmd(EC_WAKE_UP_WLAN, NULL, 0, NULL, 0);
+
+        return 0;
+}
+
+static struct olpc_ec_driver ec_xo1_driver = {
+        .probe = olpc_xo1_ec_probe,
+        .suspend = olpc_xo1_ec_suspend,
+        .resume = olpc_xo1_ec_resume,
+        .ec_cmd = olpc_xo1_ec_cmd,
+};
+
+static struct olpc_ec_driver ec_xo1_5_driver = {
+        .probe = olpc_xo1_ec_probe,
+        .ec_cmd = olpc_xo1_ec_cmd,
 };
 
 static int __init olpc_init(void)
@@ -435,16 +379,17 @@ static int __init olpc_init(void)
         if (!olpc_ofw_present() || !platform_detect())
                 return 0;
 
-        spin_lock_init(&ec_lock);
+        /* register the XO-1 and 1.5-specific EC handler */
+        if (olpc_platform_info.boardrev < olpc_board_pre(0xd0)) /* XO-1 */
+                olpc_ec_driver_register(&ec_xo1_driver, NULL);
+        else
+                olpc_ec_driver_register(&ec_xo1_5_driver, NULL);
+        platform_device_register_simple("olpc-ec", -1, NULL, 0);
 
         /* assume B1 and above models always have a DCON */
         if (olpc_board_at_least(olpc_board(0xb1)))
                 olpc_platform_info.flags |= OLPC_F_DCON;
 
-        /* get the EC revision */
-        olpc_ec_cmd(EC_FIRMWARE_REV, NULL, 0,
-                        (unsigned char *) &olpc_platform_info.ecver, 1);
-
 #ifdef CONFIG_PCI_OLPC
         /* If the VSA exists let it emulate PCI, if not emulate in kernel.
          * XO-1 only. */
@@ -452,14 +397,6 @@ static int __init olpc_init(void)
                         !cs5535_has_vsa2())
                 x86_init.pci.arch_init = pci_olpc_init;
 #endif
-        /* EC version 0x5f adds support for wide SCI mask */
-        if (olpc_platform_info.ecver >= 0x5f)
-                olpc_platform_info.flags |= OLPC_F_EC_WIDE_SCI;
-
-        printk(KERN_INFO "OLPC board revision %s%X (EC=%x)\n",
-                        ((olpc_platform_info.boardrev & 0xf) < 8) ? "pre" : "",
-                        olpc_platform_info.boardrev >> 4,
-                        olpc_platform_info.ecver);
 
         if (olpc_platform_info.boardrev < olpc_board_pre(0xd0)) { /* XO-1 */
                 r = add_xo1_platform_devices();
@@ -467,9 +404,6 @@ static int __init olpc_init(void)
                         return r;
         }
 
-        register_syscore_ops(&olpc_syscore_ops);
-        setup_debugfs();
-
         return 0;
 }
 
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index 59880afa851..b8b3a37c80c 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -1,7 +1,7 @@
 /*
  *      SGI UltraViolet TLB flush routines.
  *
- *      (c) 2008-2011 Cliff Wickman <cpw@sgi.com>, SGI.
+ *      (c) 2008-2012 Cliff Wickman <cpw@sgi.com>, SGI.
  *
  *      This code is released under the GNU General Public License version 2 or
  *      later.
@@ -38,8 +38,7 @@ static int timeout_base_ns[] = {
 
 static int timeout_us;
 static int nobau;
-static int baudisabled;
-static spinlock_t disable_lock;
+static int nobau_perm;
 static cycles_t congested_cycles;
 
 /* tunables: */
@@ -47,12 +46,13 @@ static int max_concurr		= MAX_BAU_CONCURRENT;
 static int max_concurr_const    = MAX_BAU_CONCURRENT;
 static int plugged_delay        = PLUGGED_DELAY;
 static int plugsb4reset         = PLUGSB4RESET;
+static int giveup_limit         = GIVEUP_LIMIT;
 static int timeoutsb4reset      = TIMEOUTSB4RESET;
 static int ipi_reset_limit      = IPI_RESET_LIMIT;
 static int complete_threshold   = COMPLETE_THRESHOLD;
 static int congested_respns_us  = CONGESTED_RESPONSE_US;
 static int congested_reps       = CONGESTED_REPS;
-static int congested_period     = CONGESTED_PERIOD;
+static int disabled_period      = DISABLED_PERIOD;
 
 static struct tunables tunables[] = {
         {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */
@@ -63,7 +63,8 @@ static struct tunables tunables[] = {
         {&complete_threshold, COMPLETE_THRESHOLD},
         {&congested_respns_us, CONGESTED_RESPONSE_US},
         {&congested_reps, CONGESTED_REPS},
-        {&congested_period, CONGESTED_PERIOD}
+        {&disabled_period, DISABLED_PERIOD},
+        {&giveup_limit, GIVEUP_LIMIT}
 };
 
 static struct dentry *tunables_dir;
@@ -120,6 +121,40 @@ static DEFINE_PER_CPU(struct ptc_stats, ptcstats);
 static DEFINE_PER_CPU(struct bau_control, bau_control);
 static DEFINE_PER_CPU(cpumask_var_t, uv_flush_tlb_mask);
 
+static void
+set_bau_on(void)
+{
+        int cpu;
+        struct bau_control *bcp;
+
+        if (nobau_perm) {
+                pr_info("BAU not initialized; cannot be turned on\n");
+                return;
+        }
+        nobau = 0;
+        for_each_present_cpu(cpu) {
+                bcp = &per_cpu(bau_control, cpu);
+                bcp->nobau = 0;
+        }
+        pr_info("BAU turned on\n");
+        return;
+}
+
+static void
+set_bau_off(void)
+{
+        int cpu;
+        struct bau_control *bcp;
+
+        nobau = 1;
+        for_each_present_cpu(cpu) {
+                bcp = &per_cpu(bau_control, cpu);
+                bcp->nobau = 1;
+        }
+        pr_info("BAU turned off\n");
+        return;
+}
+
 /*
  * Determine the first node on a uvhub. 'Nodes' are used for kernel
  * memory allocation.
@@ -278,7 +313,7 @@ static void bau_process_message(struct msg_desc *mdp, struct bau_control *bcp,
                  * Both sockets dump their completed count total into
                  * the message's count.
                  */
-                smaster->socket_acknowledge_count[mdp->msg_slot] = 0;
+                *sp = 0;
                 asp = (struct atomic_short *)&msg->acknowledge_count;
                 msg_ack_count = atom_asr(socket_ack_count, asp);
 
@@ -491,16 +526,15 @@ static int uv1_wait_completion(struct bau_desc *bau_desc,
 }
 
 /*
- * UV2 has an extra bit of status in the ACTIVATION_STATUS_2 register.
+ * UV2 could have an extra bit of status in the ACTIVATION_STATUS_2 register.
+ * But not currently used.
  */
 static unsigned long uv2_read_status(unsigned long offset, int rshft, int desc)
 {
         unsigned long descriptor_status;
-        unsigned long descriptor_status2;
 
-        descriptor_status = ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK);
-        descriptor_status2 = (read_mmr_uv2_status() >> desc) & 0x1UL;
-        descriptor_status = (descriptor_status << 1) | descriptor_status2;
+        descriptor_status =
+                ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK) << 1;
         return descriptor_status;
 }
 
@@ -531,87 +565,11 @@ int normal_busy(struct bau_control *bcp)
  */
 int handle_uv2_busy(struct bau_control *bcp)
 {
-        int busy_one = bcp->using_desc;
-        int normal = bcp->uvhub_cpu;
-        int selected = -1;
-        int i;
-        unsigned long descriptor_status;
-        unsigned long status;
-        int mmr_offset;
-        struct bau_desc *bau_desc_old;
-        struct bau_desc *bau_desc_new;
-        struct bau_control *hmaster = bcp->uvhub_master;
         struct ptc_stats *stat = bcp->statp;
-        cycles_t ttm;
 
         stat->s_uv2_wars++;
-        spin_lock(&hmaster->uvhub_lock);
-        /* try for the original first */
-        if (busy_one != normal) {
-                if (!normal_busy(bcp))
-                        selected = normal;
-        }
-        if (selected < 0) {
-                /* can't use the normal, select an alternate */
-                mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
-                descriptor_status = read_lmmr(mmr_offset);
-
-                /* scan available descriptors 32-63 */
-                for (i = 0; i < UV_CPUS_PER_AS; i++) {
-                        if ((hmaster->inuse_map & (1 << i)) == 0) {
-                                status = ((descriptor_status >>
-                                                (i * UV_ACT_STATUS_SIZE)) &
-                                                UV_ACT_STATUS_MASK) << 1;
-                                if (status != UV2H_DESC_BUSY) {
-                                        selected = i + UV_CPUS_PER_AS;
-                                        break;
-                                }
-                        }
-                }
-        }
-
-        if (busy_one != normal)
-                /* mark the busy alternate as not in-use */
-                hmaster->inuse_map &= ~(1 << (busy_one - UV_CPUS_PER_AS));
-
-        if (selected >= 0) {
-                /* switch to the selected descriptor */
-                if (selected != normal) {
-                        /* set the selected alternate as in-use */
-                        hmaster->inuse_map |=
-                                        (1 << (selected - UV_CPUS_PER_AS));
-                        if (selected > stat->s_uv2_wars_hw)
-                                stat->s_uv2_wars_hw = selected;
-                }
-                bau_desc_old = bcp->descriptor_base;
-                bau_desc_old += (ITEMS_PER_DESC * busy_one);
-                bcp->using_desc = selected;
-                bau_desc_new = bcp->descriptor_base;
-                bau_desc_new += (ITEMS_PER_DESC * selected);
-                *bau_desc_new = *bau_desc_old;
-        } else {
-                /*
-                 * All are busy. Wait for the normal one for this cpu to
-                 * free up.
-                 */
-                stat->s_uv2_war_waits++;
-                spin_unlock(&hmaster->uvhub_lock);
-                ttm = get_cycles();
-                do {
-                        cpu_relax();
-                } while (normal_busy(bcp));
-                spin_lock(&hmaster->uvhub_lock);
-                /* switch to the original descriptor */
-                bcp->using_desc = normal;
-                bau_desc_old = bcp->descriptor_base;
-                bau_desc_old += (ITEMS_PER_DESC * bcp->using_desc);
-                bcp->using_desc = (ITEMS_PER_DESC * normal);
-                bau_desc_new = bcp->descriptor_base;
-                bau_desc_new += (ITEMS_PER_DESC * normal);
-                *bau_desc_new = *bau_desc_old; /* copy the entire descriptor */
-        }
-        spin_unlock(&hmaster->uvhub_lock);
-        return FLUSH_RETRY_BUSYBUG;
+        bcp->busy = 1;
+        return FLUSH_GIVEUP;
 }
 
 static int uv2_wait_completion(struct bau_desc *bau_desc,
@@ -620,7 +578,7 @@ static int uv2_wait_completion(struct bau_desc *bau_desc,
 {
         unsigned long descriptor_stat;
         cycles_t ttm;
-        int desc = bcp->using_desc;
+        int desc = bcp->uvhub_cpu;
         long busy_reps = 0;
         struct ptc_stats *stat = bcp->statp;
 
@@ -628,24 +586,38 @@ static int uv2_wait_completion(struct bau_desc *bau_desc,
 
         /* spin on the status MMR, waiting for it to go idle */
         while (descriptor_stat != UV2H_DESC_IDLE) {
-                /*
-                 * Our software ack messages may be blocked because
-                 * there are no swack resources available.  As long
-                 * as none of them has timed out hardware will NACK
-                 * our message and its state will stay IDLE.
-                 */
-                if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) ||
-                    (descriptor_stat == UV2H_DESC_DEST_PUT_ERR)) {
+                if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT)) {
+                        /*
+                         * A h/w bug on the destination side may
+                         * have prevented the message being marked
+                         * pending, thus it doesn't get replied to
+                         * and gets continually nacked until it times
+                         * out with a SOURCE_TIMEOUT.
+                         */
                         stat->s_stimeout++;
                         return FLUSH_GIVEUP;
-                } else if (descriptor_stat == UV2H_DESC_DEST_STRONG_NACK) {
-                        stat->s_strongnacks++;
-                        bcp->conseccompletes = 0;
-                        return FLUSH_GIVEUP;
                 } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
+                        ttm = get_cycles();
+
+                        /*
+                         * Our retries may be blocked by all destination
+                         * swack resources being consumed, and a timeout
+                         * pending.  In that case hardware returns the
+                         * ERROR that looks like a destination timeout.
+                         * Without using the extended status we have to
+                         * deduce from the short time that this was a
+                         * strong nack.
+                         */
+                        if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
+                                bcp->conseccompletes = 0;
+                                stat->s_plugged++;
+                                /* FLUSH_RETRY_PLUGGED causes hang on boot */
+                                return FLUSH_GIVEUP;
+                        }
                         stat->s_dtimeout++;
                         bcp->conseccompletes = 0;
-                        return FLUSH_RETRY_TIMEOUT;
+                        /* FLUSH_RETRY_TIMEOUT causes hang on boot */
+                        return FLUSH_GIVEUP;
                 } else {
                         busy_reps++;
                         if (busy_reps > 1000000) {
@@ -653,9 +625,8 @@ static int uv2_wait_completion(struct bau_desc *bau_desc,
                                 busy_reps = 0;
                                 ttm = get_cycles();
                                 if ((ttm - bcp->send_message) >
-                                        (bcp->clocks_per_100_usec)) {
+                                                bcp->timeout_interval)
                                         return handle_uv2_busy(bcp);
-                                }
                         }
                         /*
                          * descriptor_stat is still BUSY
@@ -679,7 +650,7 @@ static int wait_completion(struct bau_desc *bau_desc,
 {
         int right_shift;
         unsigned long mmr_offset;
-        int desc = bcp->using_desc;
+        int desc = bcp->uvhub_cpu;
 
         if (desc < UV_CPUS_PER_AS) {
                 mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
@@ -758,33 +729,31 @@ static void destination_timeout(struct bau_desc *bau_desc,
 }
 
 /*
- * Completions are taking a very long time due to a congested numalink
- * network.
+ * Stop all cpus on a uvhub from using the BAU for a period of time.
+ * This is reversed by check_enable.
  */
-static void disable_for_congestion(struct bau_control *bcp,
-                                        struct ptc_stats *stat)
+static void disable_for_period(struct bau_control *bcp, struct ptc_stats *stat)
 {
-        /* let only one cpu do this disabling */
-        spin_lock(&disable_lock);
-
-        if (!baudisabled && bcp->period_requests &&
-            ((bcp->period_time / bcp->period_requests) > congested_cycles)) {
-                int tcpu;
-                struct bau_control *tbcp;
-                /* it becomes this cpu's job to turn on the use of the
-                   BAU again */
-                baudisabled = 1;
-                bcp->set_bau_off = 1;
-                bcp->set_bau_on_time = get_cycles();
-                bcp->set_bau_on_time += sec_2_cycles(bcp->cong_period);
+        int tcpu;
+        struct bau_control *tbcp;
+        struct bau_control *hmaster;
+        cycles_t tm1;
+
+        hmaster = bcp->uvhub_master;
+        spin_lock(&hmaster->disable_lock);
+        if (!bcp->baudisabled) {
                 stat->s_bau_disabled++;
+                tm1 = get_cycles();
                 for_each_present_cpu(tcpu) {
                         tbcp = &per_cpu(bau_control, tcpu);
-                        tbcp->baudisabled = 1;
+                        if (tbcp->uvhub_master == hmaster) {
+                                tbcp->baudisabled = 1;
+                                tbcp->set_bau_on_time =
+                                        tm1 + bcp->disabled_period;
+                        }
                 }
         }
-
-        spin_unlock(&disable_lock);
+        spin_unlock(&hmaster->disable_lock);
 }
 
 static void count_max_concurr(int stat, struct bau_control *bcp,
@@ -815,16 +784,30 @@ static void record_send_stats(cycles_t time1, cycles_t time2,
                         bcp->period_requests++;
                         bcp->period_time += elapsed;
                         if ((elapsed > congested_cycles) &&
-                            (bcp->period_requests > bcp->cong_reps))
-                                disable_for_congestion(bcp, stat);
+                            (bcp->period_requests > bcp->cong_reps) &&
+                            ((bcp->period_time / bcp->period_requests) >
+                                                        congested_cycles)) {
+                                stat->s_congested++;
+                                disable_for_period(bcp, stat);
+                        }
                 }
         } else
                 stat->s_requestor--;
 
         if (completion_status == FLUSH_COMPLETE && try > 1)
                 stat->s_retriesok++;
-        else if (completion_status == FLUSH_GIVEUP)
+        else if (completion_status == FLUSH_GIVEUP) {
                 stat->s_giveup++;
+                if (get_cycles() > bcp->period_end)
+                        bcp->period_giveups = 0;
+                bcp->period_giveups++;
+                if (bcp->period_giveups == 1)
+                        bcp->period_end = get_cycles() + bcp->disabled_period;
+                if (bcp->period_giveups > bcp->giveup_limit) {
+                        disable_for_period(bcp, stat);
+                        stat->s_giveuplimit++;
+                }
+        }
 }
 
 /*
@@ -868,7 +851,8 @@ static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
  * Returns 1 if it gives up entirely and the original cpu mask is to be
  * returned to the kernel.
  */
-int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp)
+int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp,
+        struct bau_desc *bau_desc)
 {
         int seq_number = 0;
         int completion_stat = 0;
@@ -881,24 +865,23 @@ int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp)
         struct bau_control *hmaster = bcp->uvhub_master;
         struct uv1_bau_msg_header *uv1_hdr = NULL;
         struct uv2_bau_msg_header *uv2_hdr = NULL;
-        struct bau_desc *bau_desc;
 
-        if (bcp->uvhub_version == 1)
+        if (bcp->uvhub_version == 1) {
+                uv1 = 1;
                 uv1_throttle(hmaster, stat);
+        }
 
         while (hmaster->uvhub_quiesce)
                 cpu_relax();
 
         time1 = get_cycles();
+        if (uv1)
+                uv1_hdr = &bau_desc->header.uv1_hdr;
+        else
+                uv2_hdr = &bau_desc->header.uv2_hdr;
+
         do {
-                bau_desc = bcp->descriptor_base;
-                bau_desc += (ITEMS_PER_DESC * bcp->using_desc);
-                if (bcp->uvhub_version == 1) {
-                        uv1 = 1;
-                        uv1_hdr = &bau_desc->header.uv1_hdr;
-                } else
-                        uv2_hdr = &bau_desc->header.uv2_hdr;
-                if ((try == 0) || (completion_stat == FLUSH_RETRY_BUSYBUG)) {
+                if (try == 0) {
                         if (uv1)
                                 uv1_hdr->msg_type = MSG_REGULAR;
                         else
@@ -916,25 +899,24 @@ int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp)
                         uv1_hdr->sequence = seq_number;
                 else
                         uv2_hdr->sequence = seq_number;
-                index = (1UL << AS_PUSH_SHIFT) | bcp->using_desc;
+                index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu;
                 bcp->send_message = get_cycles();
 
                 write_mmr_activation(index);
 
                 try++;
                 completion_stat = wait_completion(bau_desc, bcp, try);
-                /* UV2: wait_completion() may change the bcp->using_desc */
 
                 handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
 
                 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
                         bcp->ipi_attempts = 0;
+                        stat->s_overipilimit++;
                         completion_stat = FLUSH_GIVEUP;
                         break;
                 }
                 cpu_relax();
         } while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
-                 (completion_stat == FLUSH_RETRY_BUSYBUG) ||
                  (completion_stat == FLUSH_RETRY_TIMEOUT));
 
         time2 = get_cycles();
@@ -955,28 +937,33 @@ int uv_flush_send_and_wait(struct cpumask *flush_mask, struct bau_control *bcp)
 }
 
 /*
- * The BAU is disabled. When the disabled time period has expired, the cpu
- * that disabled it must re-enable it.
- * Return 0 if it is re-enabled for all cpus.
+ * The BAU is disabled for this uvhub. When the disabled time period has
+ * expired re-enable it.
+ * Return 0 if it is re-enabled for all cpus on this uvhub.
  */
 static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
 {
         int tcpu;
         struct bau_control *tbcp;
+        struct bau_control *hmaster;
 
-        if (bcp->set_bau_off) {
-                if (get_cycles() >= bcp->set_bau_on_time) {
-                        stat->s_bau_reenabled++;
-                        baudisabled = 0;
-                        for_each_present_cpu(tcpu) {
-                                tbcp = &per_cpu(bau_control, tcpu);
+        hmaster = bcp->uvhub_master;
+        spin_lock(&hmaster->disable_lock);
+        if (bcp->baudisabled && (get_cycles() >= bcp->set_bau_on_time)) {
+                stat->s_bau_reenabled++;
+                for_each_present_cpu(tcpu) {
+                        tbcp = &per_cpu(bau_control, tcpu);
+                        if (tbcp->uvhub_master == hmaster) {
                                 tbcp->baudisabled = 0;
                                 tbcp->period_requests = 0;
                                 tbcp->period_time = 0;
+                                tbcp->period_giveups = 0;
                         }
-                        return 0;
                 }
+                spin_unlock(&hmaster->disable_lock);
+                return 0;
         }
+        spin_unlock(&hmaster->disable_lock);
         return -1;
 }
 
@@ -1068,8 +1055,8 @@ static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
  * done.  The returned pointer is valid till preemption is re-enabled.
  */
 const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
-                                struct mm_struct *mm, unsigned long va,
-                                unsigned int cpu)
+                                struct mm_struct *mm, unsigned long start,
+                                unsigned end, unsigned int cpu)
 {
         int locals = 0;
         int remotes = 0;
@@ -1078,18 +1065,32 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
         struct cpumask *flush_mask;
         struct ptc_stats *stat;
         struct bau_control *bcp;
-
-        /* kernel was booted 'nobau' */
-        if (nobau)
-                return cpumask;
+        unsigned long descriptor_status;
+        unsigned long status;
 
         bcp = &per_cpu(bau_control, cpu);
         stat = bcp->statp;
+        stat->s_enters++;
+
+        if (bcp->nobau)
+                return cpumask;
+
+        if (bcp->busy) {
+                descriptor_status =
+                        read_lmmr(UVH_LB_BAU_SB_ACTIVATION_STATUS_0);
+                status = ((descriptor_status >> (bcp->uvhub_cpu *
+                        UV_ACT_STATUS_SIZE)) & UV_ACT_STATUS_MASK) << 1;
+                if (status == UV2H_DESC_BUSY)
+                        return cpumask;
+                bcp->busy = 0;
+        }
 
         /* bau was disabled due to slow response */
         if (bcp->baudisabled) {
-                if (check_enable(bcp, stat))
+                if (check_enable(bcp, stat)) {
+                        stat->s_ipifordisabled++;
                         return cpumask;
+                }
         }
 
         /*
@@ -1105,38 +1106,40 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
                 stat->s_ntargself++;
 
         bau_desc = bcp->descriptor_base;
-        bau_desc += (ITEMS_PER_DESC * bcp->using_desc);
+        bau_desc += (ITEMS_PER_DESC * bcp->uvhub_cpu);
         bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
         if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
                 return NULL;
 
         record_send_statistics(stat, locals, hubs, remotes, bau_desc);
 
-        bau_desc->payload.address = va;
+        bau_desc->payload.address = start;
         bau_desc->payload.sending_cpu = cpu;
         /*
          * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
          * or 1 if it gave up and the original cpumask should be returned.
          */
-        if (!uv_flush_send_and_wait(flush_mask, bcp))
+        if (!uv_flush_send_and_wait(flush_mask, bcp, bau_desc))
                 return NULL;
         else
                 return cpumask;
 }
 
 /*
- * Search the message queue for any 'other' message with the same software
- * acknowledge resource bit vector.
+ * Search the message queue for any 'other' unprocessed message with the
+ * same software acknowledge resource bit vector as the 'msg' message.
  */
 struct bau_pq_entry *find_another_by_swack(struct bau_pq_entry *msg,
-                        struct bau_control *bcp, unsigned char swack_vec)
+                                           struct bau_control *bcp)
 {
         struct bau_pq_entry *msg_next = msg + 1;
+        unsigned char swack_vec = msg->swack_vec;
 
         if (msg_next > bcp->queue_last)
                 msg_next = bcp->queue_first;
-        while ((msg_next->swack_vec != 0) && (msg_next != msg)) {
-                if (msg_next->swack_vec == swack_vec)
+        while (msg_next != msg) {
+                if ((msg_next->canceled == 0) && (msg_next->replied_to == 0) &&
+                                (msg_next->swack_vec == swack_vec))
                         return msg_next;
                 msg_next++;
                 if (msg_next > bcp->queue_last)
@@ -1165,32 +1168,30 @@ void process_uv2_message(struct msg_desc *mdp, struct bau_control *bcp)
                  * This message was assigned a swack resource, but no
                  * reserved acknowlegment is pending.
                  * The bug has prevented this message from setting the MMR.
-                 * And no other message has used the same sw_ack resource.
-                 * Do the requested shootdown but do not reply to the msg.
-                 * (the 0 means make no acknowledge)
                  */
-                bau_process_message(mdp, bcp, 0);
-                return;
-        }
-
-        /*
-         * Some message has set the MMR 'pending' bit; it might have been
-         * another message.  Look for that message.
-         */
-        other_msg = find_another_by_swack(msg, bcp, msg->swack_vec);
-        if (other_msg) {
-                /* There is another.  Do not ack the current one. */
-                bau_process_message(mdp, bcp, 0);
                 /*
-                 * Let the natural processing of that message acknowledge
-                 * it. Don't get the processing of sw_ack's out of order.
+                 * Some message has set the MMR 'pending' bit; it might have
+                 * been another message.  Look for that message.
                  */
-                return;
+                other_msg = find_another_by_swack(msg, bcp);
+                if (other_msg) {
+                        /*
+                         * There is another. Process this one but do not
+                         * ack it.
+                         */
+                        bau_process_message(mdp, bcp, 0);
+                        /*
+                         * Let the natural processing of that other message
+                         * acknowledge it. Don't get the processing of sw_ack's
+                         * out of order.
+                         */
+                        return;
+                }
         }
 
         /*
-         * There is no other message using this sw_ack, so it is safe to
-         * acknowledge it.
+         * Either the MMR shows this one pending a reply or there is no
+         * other message using this sw_ack, so it is safe to acknowledge it.
          */
         bau_process_message(mdp, bcp, 1);
 
@@ -1295,7 +1296,8 @@ static void __init enable_timeouts(void)
                  */
                 mmr_image |= (1L << SOFTACK_MSHIFT);
                 if (is_uv2_hub()) {
-                        mmr_image |= (1L << UV2_EXT_SHFT);
+                        /* hw bug workaround; do not use extended status */
+                        mmr_image &= ~(1L << UV2_EXT_SHFT);
                 }
                 write_mmr_misc_control(pnode, mmr_image);
         }
@@ -1338,29 +1340,34 @@ static inline unsigned long long usec_2_cycles(unsigned long microsec)
 static int ptc_seq_show(struct seq_file *file, void *data)
 {
         struct ptc_stats *stat;
+        struct bau_control *bcp;
         int cpu;
 
         cpu = *(loff_t *)data;
         if (!cpu) {
                 seq_printf(file,
-                        "# cpu sent stime self locals remotes ncpus localhub ");
+                 "# cpu bauoff sent stime self locals remotes ncpus localhub ");
                 seq_printf(file,
                         "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
                 seq_printf(file,
-                    "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries rok ");
+                        "numuvhubs4 numuvhubs2 numuvhubs1 dto snacks retries ");
+                seq_printf(file,
+                        "rok resetp resett giveup sto bz throt disable ");
                 seq_printf(file,
-                        "resetp resett giveup sto bz throt swack recv rtime ");
+                        "enable wars warshw warwaits enters ipidis plugged ");
                 seq_printf(file,
-                        "all one mult none retry canc nocan reset rcan ");
+                        "ipiover glim cong swack recv rtime all one mult ");
                 seq_printf(file,
-                        "disable enable wars warshw warwaits\n");
+                        "none retry canc nocan reset rcan\n");
         }
         if (cpu < num_possible_cpus() && cpu_online(cpu)) {
-                stat = &per_cpu(ptcstats, cpu);
+                bcp = &per_cpu(bau_control, cpu);
+                stat = bcp->statp;
                 /* source side statistics */
                 seq_printf(file,
-                        "cpu %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
-                           cpu, stat->s_requestor, cycles_2_us(stat->s_time),
+                        "cpu %d %d %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
+                           cpu, bcp->nobau, stat->s_requestor,
+                           cycles_2_us(stat->s_time),
                            stat->s_ntargself, stat->s_ntarglocals,
                            stat->s_ntargremotes, stat->s_ntargcpu,
                            stat->s_ntarglocaluvhub, stat->s_ntargremoteuvhub,
@@ -1374,20 +1381,23 @@ static int ptc_seq_show(struct seq_file *file, void *data)
                            stat->s_resets_plug, stat->s_resets_timeout,
                            stat->s_giveup, stat->s_stimeout,
                            stat->s_busy, stat->s_throttles);
+                seq_printf(file, "%ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
+                           stat->s_bau_disabled, stat->s_bau_reenabled,
+                           stat->s_uv2_wars, stat->s_uv2_wars_hw,
+                           stat->s_uv2_war_waits, stat->s_enters,
+                           stat->s_ipifordisabled, stat->s_plugged,
+                           stat->s_overipilimit, stat->s_giveuplimit,
+                           stat->s_congested);
 
                 /* destination side statistics */
                 seq_printf(file,
-                           "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
+                        "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld\n",
                            read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)),
                            stat->d_requestee, cycles_2_us(stat->d_time),
                            stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
                            stat->d_nomsg, stat->d_retries, stat->d_canceled,
                            stat->d_nocanceled, stat->d_resets,
                            stat->d_rcanceled);
-                seq_printf(file, "%ld %ld %ld %ld %ld\n",
-                        stat->s_bau_disabled, stat->s_bau_reenabled,
-                        stat->s_uv2_wars, stat->s_uv2_wars_hw,
-                        stat->s_uv2_war_waits);
         }
         return 0;
 }
@@ -1401,13 +1411,14 @@ static ssize_t tunables_read(struct file *file, char __user *userbuf,
         char *buf;
         int ret;
 
-        buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n",
-                "max_concur plugged_delay plugsb4reset",
-                "timeoutsb4reset ipi_reset_limit complete_threshold",
-                "congested_response_us congested_reps congested_period",
+        buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d %d\n",
+                "max_concur plugged_delay plugsb4reset timeoutsb4reset",
+                "ipi_reset_limit complete_threshold congested_response_us",
+                "congested_reps disabled_period giveup_limit",
                 max_concurr, plugged_delay, plugsb4reset,
                 timeoutsb4reset, ipi_reset_limit, complete_threshold,
-                congested_respns_us, congested_reps, congested_period);
+                congested_respns_us, congested_reps, disabled_period,
+                giveup_limit);
 
         if (!buf)
                 return -ENOMEM;
@@ -1438,6 +1449,14 @@ static ssize_t ptc_proc_write(struct file *file, const char __user *user,
                 return -EFAULT;
         optstr[count - 1] = '\0';
 
+        if (!strcmp(optstr, "on")) {
+                set_bau_on();
+                return count;
+        } else if (!strcmp(optstr, "off")) {
+                set_bau_off();
+                return count;
+        }
+
         if (strict_strtol(optstr, 10, &input_arg) < 0) {
                 printk(KERN_DEBUG "%s is invalid\n", optstr);
                 return -EINVAL;
@@ -1570,7 +1589,8 @@ static ssize_t tunables_write(struct file *file, const char __user *user,
                 bcp->complete_threshold =       complete_threshold;
                 bcp->cong_response_us =         congested_respns_us;
                 bcp->cong_reps =                congested_reps;
-                bcp->cong_period =              congested_period;
+                bcp->disabled_period =          sec_2_cycles(disabled_period);
+                bcp->giveup_limit =             giveup_limit;
         }
         return count;
 }
@@ -1699,6 +1719,10 @@ static void activation_descriptor_init(int node, int pnode, int base_pnode)
                          *   fairness chaining multilevel count replied_to
                          */
                 } else {
+                        /*
+                         * BIOS uses legacy mode, but UV2 hardware always
+                         * uses native mode for selective broadcasts.
+                         */
                         uv2_hdr = &bd2->header.uv2_hdr;
                         uv2_hdr->swack_flag =   1;
                         uv2_hdr->base_dest_nasid =
@@ -1811,8 +1835,8 @@ static int calculate_destination_timeout(void)
                 index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
                 mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
                 mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
-                base = timeout_base_ns[index];
-                ts_ns = base * mult1 * mult2;
+                ts_ns = timeout_base_ns[index];
+                ts_ns *= (mult1 * mult2);
                 ret = ts_ns / 1000;
         } else {
                 /* 4 bits  0/1 for 10/80us base, 3 bits of multiplier */
@@ -1836,6 +1860,8 @@ static void __init init_per_cpu_tunables(void)
         for_each_present_cpu(cpu) {
                 bcp = &per_cpu(bau_control, cpu);
                 bcp->baudisabled                = 0;
+                if (nobau)
+                        bcp->nobau              = 1;
                 bcp->statp                      = &per_cpu(ptcstats, cpu);
                 /* time interval to catch a hardware stay-busy bug */
                 bcp->timeout_interval           = usec_2_cycles(2*timeout_us);
@@ -1848,10 +1874,11 @@ static void __init init_per_cpu_tunables(void)
                 bcp->complete_threshold         = complete_threshold;
                 bcp->cong_response_us           = congested_respns_us;
                 bcp->cong_reps                  = congested_reps;
-                bcp->cong_period                = congested_period;
-                bcp->clocks_per_100_usec =      usec_2_cycles(100);
+                bcp->disabled_period =          sec_2_cycles(disabled_period);
+                bcp->giveup_limit =             giveup_limit;
                 spin_lock_init(&bcp->queue_lock);
                 spin_lock_init(&bcp->uvhub_lock);
+                spin_lock_init(&bcp->disable_lock);
         }
 }
 
@@ -1972,7 +1999,6 @@ static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
                 }
                 bcp->uvhub_master = *hmasterp;
                 bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id;
-                bcp->using_desc = bcp->uvhub_cpu;
                 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
                         printk(KERN_EMERG "%d cpus per uvhub invalid\n",
                                 bcp->uvhub_cpu);
@@ -2069,16 +2095,12 @@ static int __init uv_bau_init(void)
         if (!is_uv_system())
                 return 0;
 
-        if (nobau)
-                return 0;
-
         for_each_possible_cpu(cur_cpu) {
                 mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
                 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
         }
 
         nuvhubs = uv_num_possible_blades();
-        spin_lock_init(&disable_lock);
         congested_cycles = usec_2_cycles(congested_respns_us);
 
         uv_base_pnode = 0x7fffffff;
@@ -2091,7 +2113,8 @@ static int __init uv_bau_init(void)
         enable_timeouts();
 
         if (init_per_cpu(nuvhubs, uv_base_pnode)) {
-                nobau = 1;
+                set_bau_off();
+                nobau_perm = 1;
                 return 0;
         }
 
diff --git a/arch/x86/platform/uv/uv_irq.c b/arch/x86/platform/uv/uv_irq.c
index f25c2765a5c..acf7752da95 100644
--- a/arch/x86/platform/uv/uv_irq.c
+++ b/arch/x86/platform/uv/uv_irq.c
@@ -135,6 +135,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
         unsigned long mmr_value;
         struct uv_IO_APIC_route_entry *entry;
         int mmr_pnode, err;
+        unsigned int dest;
 
         BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) !=
                         sizeof(unsigned long));
@@ -143,6 +144,10 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
         if (err != 0)
                 return err;
 
+        err = apic->cpu_mask_to_apicid_and(eligible_cpu, eligible_cpu, &dest);
+        if (err != 0)
+                return err;
+
         if (limit == UV_AFFINITY_CPU)
                 irq_set_status_flags(irq, IRQ_NO_BALANCING);
         else
@@ -159,7 +164,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
         entry->polarity         = 0;
         entry->trigger          = 0;
         entry->mask             = 0;
-        entry->dest             = apic->cpu_mask_to_apicid(eligible_cpu);
+        entry->dest             = dest;
 
         mmr_pnode = uv_blade_to_pnode(mmr_blade);
         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
@@ -222,7 +227,7 @@ uv_set_irq_affinity(struct irq_data *data, const struct cpumask *mask,
         if (cfg->move_in_progress)
                 send_cleanup_vector(cfg);
 
-        return 0;
+        return IRQ_SET_MASK_OK_NOCOPY;
 }
 
 /*
diff --git a/arch/x86/realmode/rm/Makefile b/arch/x86/realmode/rm/Makefile
index 5b84a2d3088..88692871823 100644
--- a/arch/x86/realmode/rm/Makefile
+++ b/arch/x86/realmode/rm/Makefile
@@ -22,7 +22,7 @@ wakeup-objs	+= video-bios.o
 realmode-y                      += header.o
 realmode-y                      += trampoline_$(BITS).o
 realmode-y                      += stack.o
-realmode-$(CONFIG_X86_32)       += reboot_32.o
+realmode-y                      += reboot.o
 realmode-$(CONFIG_ACPI_SLEEP)   += $(wakeup-objs)
 
 targets += $(realmode-y)
@@ -72,7 +72,7 @@ KBUILD_CFLAGS	:= $(LINUXINCLUDE) -m32 -g -Os -D_SETUP -D__KERNEL__ -D_WAKEUP \
                    -Wall -Wstrict-prototypes \
                    -march=i386 -mregparm=3 \
                    -include $(srctree)/$(src)/../../boot/code16gcc.h \
-                   -fno-strict-aliasing -fomit-frame-pointer \
+                   -fno-strict-aliasing -fomit-frame-pointer -fno-pic \
                    $(call cc-option, -ffreestanding) \
                    $(call cc-option, -fno-toplevel-reorder,\
                         $(call cc-option, -fno-unit-at-a-time)) \
diff --git a/arch/x86/realmode/rm/header.S b/arch/x86/realmode/rm/header.S
index fadf48378ad..a28221d94e6 100644
--- a/arch/x86/realmode/rm/header.S
+++ b/arch/x86/realmode/rm/header.S
@@ -6,6 +6,7 @@
 
 #include <linux/linkage.h>
 #include <asm/page_types.h>
+#include <asm/segment.h>
 
 #include "realmode.h"
         
@@ -28,8 +29,9 @@ GLOBAL(real_mode_header)
         .long   pa_wakeup_header
 #endif
         /* APM/BIOS reboot */
-#ifdef CONFIG_X86_32
         .long   pa_machine_real_restart_asm
+#ifdef CONFIG_X86_64
+        .long   __KERNEL32_CS
 #endif
 END(real_mode_header)
 
diff --git a/arch/x86/realmode/rm/reboot_32.S b/arch/x86/realmode/rm/reboot.S
index 114044876b3..f932ea61d1c 100644
--- a/arch/x86/realmode/rm/reboot_32.S
+++ b/arch/x86/realmode/rm/reboot.S
@@ -2,6 +2,8 @@
 #include <linux/init.h>
 #include <asm/segment.h>
 #include <asm/page_types.h>
+#include <asm/processor-flags.h>
+#include <asm/msr-index.h>
 #include "realmode.h"
 
 /*
@@ -12,13 +14,35 @@
  * doesn't work with at least one type of 486 motherboard.  It is easy
  * to stop this code working; hence the copious comments.
  *
- * This code is called with the restart type (0 = BIOS, 1 = APM) in %eax.
+ * This code is called with the restart type (0 = BIOS, 1 = APM) in
+ * the primary argument register (%eax for 32 bit, %edi for 64 bit).
  */
         .section ".text32", "ax"
         .code32
-
-        .balign 16
 ENTRY(machine_real_restart_asm)
+
+#ifdef CONFIG_X86_64
+        /* Switch to trampoline GDT as it is guaranteed < 4 GiB */
+        movl    $__KERNEL_DS, %eax
+        movl    %eax, %ds
+        lgdtl   pa_tr_gdt
+
+        /* Disable paging to drop us out of long mode */
+        movl    %cr0, %eax
+        andl    $~X86_CR0_PG, %eax
+        movl    %eax, %cr0
+        ljmpl   $__KERNEL32_CS, $pa_machine_real_restart_paging_off
+
+GLOBAL(machine_real_restart_paging_off)
+        xorl    %eax, %eax
+        xorl    %edx, %edx
+        movl    $MSR_EFER, %ecx
+        wrmsr
+
+        movl    %edi, %eax
+        
+#endif /* CONFIG_X86_64 */
+        
         /* Set up the IDT for real mode. */
         lidtl   pa_machine_real_restart_idt
 
diff --git a/arch/x86/syscalls/syscall_64.tbl b/arch/x86/syscalls/syscall_64.tbl
index 51171aeff0d..a582bfed95b 100644
--- a/arch/x86/syscalls/syscall_64.tbl
+++ b/arch/x86/syscalls/syscall_64.tbl
@@ -60,8 +60,8 @@
 51      common  getsockname             sys_getsockname
 52      common  getpeername             sys_getpeername
 53      common  socketpair              sys_socketpair
-54      common  setsockopt              sys_setsockopt
-55      common  getsockopt              sys_getsockopt
+54      64      setsockopt              sys_setsockopt
+55      64      getsockopt              sys_getsockopt
 56      common  clone                   stub_clone
 57      common  fork                    stub_fork
 58      common  vfork                   stub_vfork
@@ -318,7 +318,7 @@
 309     common  getcpu                  sys_getcpu
 310     64      process_vm_readv        sys_process_vm_readv
 311     64      process_vm_writev       sys_process_vm_writev
-312     64      kcmp                    sys_kcmp
+312     common  kcmp                    sys_kcmp
 
 #
 # x32-specific system call numbers start at 512 to avoid cache impact
@@ -353,3 +353,5 @@
 538     x32     sendmmsg                compat_sys_sendmmsg
 539     x32     process_vm_readv        compat_sys_process_vm_readv
 540     x32     process_vm_writev       compat_sys_process_vm_writev
+541     x32     setsockopt              compat_sys_setsockopt
+542     x32     getsockopt              compat_sys_getsockopt
diff --git a/arch/x86/um/asm/ptrace.h b/arch/x86/um/asm/ptrace.h
index 950dfb7b841..e72cd0df5ba 100644
--- a/arch/x86/um/asm/ptrace.h
+++ b/arch/x86/um/asm/ptrace.h
@@ -30,10 +30,10 @@
 #define profile_pc(regs) PT_REGS_IP(regs)
 
 #define UPT_RESTART_SYSCALL(r) (UPT_IP(r) -= 2)
-#define UPT_SET_SYSCALL_RETURN(r, res) (UPT_AX(r) = (res))
+#define PT_REGS_SET_SYSCALL_RETURN(r, res) (PT_REGS_AX(r) = (res))
 
-static inline long regs_return_value(struct uml_pt_regs *regs)
+static inline long regs_return_value(struct pt_regs *regs)
 {
-        return UPT_AX(regs);
+        return PT_REGS_AX(regs);
 }
 #endif /* __UM_X86_PTRACE_H */
diff --git a/arch/x86/vdso/vdso32-setup.c b/arch/x86/vdso/vdso32-setup.c
index 66e6d935982..0faad646f5f 100644
--- a/arch/x86/vdso/vdso32-setup.c
+++ b/arch/x86/vdso/vdso32-setup.c
@@ -205,9 +205,9 @@ void syscall32_cpu_init(void)
 {
         /* Load these always in case some future AMD CPU supports
            SYSENTER from compat mode too. */
-        checking_wrmsrl(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
-        checking_wrmsrl(MSR_IA32_SYSENTER_ESP, 0ULL);
-        checking_wrmsrl(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target);
+        wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
+        wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
+        wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)ia32_sysenter_target);
 
         wrmsrl(MSR_CSTAR, ia32_cstar_target);
 }
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index cb1b1914dbd..2766746de27 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -38,6 +38,7 @@
 #include <xen/interface/physdev.h>
 #include <xen/interface/vcpu.h>
 #include <xen/interface/memory.h>
+#include <xen/interface/xen-mca.h>
 #include <xen/features.h>
 #include <xen/page.h>
 #include <xen/hvm.h>
@@ -109,7 +110,7 @@ EXPORT_SYMBOL_GPL(xen_have_vector_callback);
  * Point at some empty memory to start with. We map the real shared_info
  * page as soon as fixmap is up and running.
  */
-struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
+struct shared_info *HYPERVISOR_shared_info = &xen_dummy_shared_info;
 
 /*
  * Flag to determine whether vcpu info placement is available on all
@@ -126,6 +127,19 @@ struct shared_info *HYPERVISOR_shared_info = (void *)&xen_dummy_shared_info;
  */
 static int have_vcpu_info_placement = 1;
 
+struct tls_descs {
+        struct desc_struct desc[3];
+};
+
+/*
+ * Updating the 3 TLS descriptors in the GDT on every task switch is
+ * surprisingly expensive so we avoid updating them if they haven't
+ * changed.  Since Xen writes different descriptors than the one
+ * passed in the update_descriptor hypercall we keep shadow copies to
+ * compare against.
+ */
+static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc);
+
 static void clamp_max_cpus(void)
 {
 #ifdef CONFIG_SMP
@@ -343,9 +357,7 @@ static void __init xen_init_cpuid_mask(void)
         unsigned int xsave_mask;
 
         cpuid_leaf1_edx_mask =
-                ~((1 << X86_FEATURE_MCE)  |  /* disable MCE */
-                  (1 << X86_FEATURE_MCA)  |  /* disable MCA */
-                  (1 << X86_FEATURE_MTRR) |  /* disable MTRR */
+                ~((1 << X86_FEATURE_MTRR) |  /* disable MTRR */
                   (1 << X86_FEATURE_ACC));   /* thermal monitoring */
 
         if (!xen_initial_domain())
@@ -542,12 +554,28 @@ static void __init xen_load_gdt_boot(const struct desc_ptr *dtr)
                 BUG();
 }
 
+static inline bool desc_equal(const struct desc_struct *d1,
+                              const struct desc_struct *d2)
+{
+        return d1->a == d2->a && d1->b == d2->b;
+}
+
 static void load_TLS_descriptor(struct thread_struct *t,
                                 unsigned int cpu, unsigned int i)
 {
-        struct desc_struct *gdt = get_cpu_gdt_table(cpu);
-        xmaddr_t maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]);
-        struct multicall_space mc = __xen_mc_entry(0);
+        struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i];
+        struct desc_struct *gdt;
+        xmaddr_t maddr;
+        struct multicall_space mc;
+
+        if (desc_equal(shadow, &t->tls_array[i]))
+                return;
+
+        *shadow = t->tls_array[i];
+
+        gdt = get_cpu_gdt_table(cpu);
+        maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]);
+        mc = __xen_mc_entry(0);
 
         MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]);
 }
@@ -629,8 +657,8 @@ static int cvt_gate_to_trap(int vector, const gate_desc *val,
         /*
          * Look for known traps using IST, and substitute them
          * appropriately.  The debugger ones are the only ones we care
-         * about.  Xen will handle faults like double_fault and
-         * machine_check, so we should never see them.  Warn if
+         * about.  Xen will handle faults like double_fault,
+         * so we should never see them.  Warn if
          * there's an unexpected IST-using fault handler.
          */
         if (addr == (unsigned long)debug)
@@ -645,7 +673,11 @@ static int cvt_gate_to_trap(int vector, const gate_desc *val,
                 return 0;
 #ifdef CONFIG_X86_MCE
         } else if (addr == (unsigned long)machine_check) {
-                return 0;
+                /*
+                 * when xen hypervisor inject vMCE to guest,
+                 * use native mce handler to handle it
+                 */
+                ;
 #endif
         } else {
                 /* Some other trap using IST? */
@@ -1126,9 +1158,7 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = {
         .wbinvd = native_wbinvd,
 
         .read_msr = native_read_msr_safe,
-        .rdmsr_regs = native_rdmsr_safe_regs,
         .write_msr = xen_write_msr_safe,
-        .wrmsr_regs = native_wrmsr_safe_regs,
 
         .read_tsc = native_read_tsc,
         .read_pmc = native_read_pmc,
@@ -1441,32 +1471,6 @@ asmlinkage void __init xen_start_kernel(void)
 #endif
 }
 
-static int init_hvm_pv_info(int *major, int *minor)
-{
-        uint32_t eax, ebx, ecx, edx, pages, msr, base;
-        u64 pfn;
-
-        base = xen_cpuid_base();
-        cpuid(base + 1, &eax, &ebx, &ecx, &edx);
-
-        *major = eax >> 16;
-        *minor = eax & 0xffff;
-        printk(KERN_INFO "Xen version %d.%d.\n", *major, *minor);
-
-        cpuid(base + 2, &pages, &msr, &ecx, &edx);
-
-        pfn = __pa(hypercall_page);
-        wrmsr_safe(msr, (u32)pfn, (u32)(pfn >> 32));
-
-        xen_setup_features();
-
-        pv_info.name = "Xen HVM";
-
-        xen_domain_type = XEN_HVM_DOMAIN;
-
-        return 0;
-}
-
 void __ref xen_hvm_init_shared_info(void)
 {
         int cpu;
@@ -1499,6 +1503,31 @@ void __ref xen_hvm_init_shared_info(void)
 }
 
 #ifdef CONFIG_XEN_PVHVM
+static void __init init_hvm_pv_info(void)
+{
+        int major, minor;
+        uint32_t eax, ebx, ecx, edx, pages, msr, base;
+        u64 pfn;
+
+        base = xen_cpuid_base();
+        cpuid(base + 1, &eax, &ebx, &ecx, &edx);
+
+        major = eax >> 16;
+        minor = eax & 0xffff;
+        printk(KERN_INFO "Xen version %d.%d.\n", major, minor);
+
+        cpuid(base + 2, &pages, &msr, &ecx, &edx);
+
+        pfn = __pa(hypercall_page);
+        wrmsr_safe(msr, (u32)pfn, (u32)(pfn >> 32));
+
+        xen_setup_features();
+
+        pv_info.name = "Xen HVM";
+
+        xen_domain_type = XEN_HVM_DOMAIN;
+}
+
 static int __cpuinit xen_hvm_cpu_notify(struct notifier_block *self,
                                     unsigned long action, void *hcpu)
 {
@@ -1521,12 +1550,7 @@ static struct notifier_block xen_hvm_cpu_notifier __cpuinitdata = {
 
 static void __init xen_hvm_guest_init(void)
 {
-        int r;
-        int major, minor;
-
-        r = init_hvm_pv_info(&major, &minor);
-        if (r < 0)
-                return;
+        init_hvm_pv_info();
 
         xen_hvm_init_shared_info();
 
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 2d9e7c9c0e7..dfc900471ae 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -308,8 +308,20 @@ static bool xen_batched_set_pte(pte_t *ptep, pte_t pteval)
 
 static inline void __xen_set_pte(pte_t *ptep, pte_t pteval)
 {
-        if (!xen_batched_set_pte(ptep, pteval))
-                native_set_pte(ptep, pteval);
+        if (!xen_batched_set_pte(ptep, pteval)) {
+                /*
+                 * Could call native_set_pte() here and trap and
+                 * emulate the PTE write but with 32-bit guests this
+                 * needs two traps (one for each of the two 32-bit
+                 * words in the PTE) so do one hypercall directly
+                 * instead.
+                 */
+                struct mmu_update u;
+
+                u.ptr = virt_to_machine(ptep).maddr | MMU_NORMAL_PT_UPDATE;
+                u.val = pte_val_ma(pteval);
+                HYPERVISOR_mmu_update(&u, 1, NULL, DOMID_SELF);
+        }
 }
 
 static void xen_set_pte(pte_t *ptep, pte_t pteval)
@@ -1162,8 +1174,13 @@ static void xen_exit_mmap(struct mm_struct *mm)
         spin_unlock(&mm->page_table_lock);
 }
 
-static void __init xen_pagetable_setup_start(pgd_t *base)
+static void xen_post_allocator_init(void);
+
+static void __init xen_pagetable_init(void)
 {
+        paging_init();
+        xen_setup_shared_info();
+        xen_post_allocator_init();
 }
 
 static __init void xen_mapping_pagetable_reserve(u64 start, u64 end)
@@ -1180,14 +1197,6 @@ static __init void xen_mapping_pagetable_reserve(u64 start, u64 end)
         }
 }
 
-static void xen_post_allocator_init(void);
-
-static void __init xen_pagetable_setup_done(pgd_t *base)
-{
-        xen_setup_shared_info();
-        xen_post_allocator_init();
-}
-
 static void xen_write_cr2(unsigned long cr2)
 {
         this_cpu_read(xen_vcpu)->arch.cr2 = cr2;
@@ -1244,7 +1253,8 @@ static void xen_flush_tlb_single(unsigned long addr)
 }
 
 static void xen_flush_tlb_others(const struct cpumask *cpus,
-                                 struct mm_struct *mm, unsigned long va)
+                                 struct mm_struct *mm, unsigned long start,
+                                 unsigned long end)
 {
         struct {
                 struct mmuext_op op;
@@ -1256,7 +1266,7 @@ static void xen_flush_tlb_others(const struct cpumask *cpus,
         } *args;
         struct multicall_space mcs;
 
-        trace_xen_mmu_flush_tlb_others(cpus, mm, va);
+        trace_xen_mmu_flush_tlb_others(cpus, mm, start, end);
 
         if (cpumask_empty(cpus))
                 return;         /* nothing to do */
@@ -1269,11 +1279,10 @@ static void xen_flush_tlb_others(const struct cpumask *cpus,
         cpumask_and(to_cpumask(args->mask), cpus, cpu_online_mask);
         cpumask_clear_cpu(smp_processor_id(), to_cpumask(args->mask));
 
-        if (va == TLB_FLUSH_ALL) {
-                args->op.cmd = MMUEXT_TLB_FLUSH_MULTI;
-        } else {
+        args->op.cmd = MMUEXT_TLB_FLUSH_MULTI;
+        if (end != TLB_FLUSH_ALL && (end - start) <= PAGE_SIZE) {
                 args->op.cmd = MMUEXT_INVLPG_MULTI;
-                args->op.arg1.linear_addr = va;
+                args->op.arg1.linear_addr = start;
         }
 
         MULTI_mmuext_op(mcs.mc, &args->op, 1, NULL, DOMID_SELF);
@@ -1416,13 +1425,28 @@ static pte_t __init mask_rw_pte(pte_t *ptep, pte_t pte)
 }
 #endif /* CONFIG_X86_64 */
 
-/* Init-time set_pte while constructing initial pagetables, which
-   doesn't allow RO pagetable pages to be remapped RW */
+/*
+ * Init-time set_pte while constructing initial pagetables, which
+ * doesn't allow RO page table pages to be remapped RW.
+ *
+ * If there is no MFN for this PFN then this page is initially
+ * ballooned out so clear the PTE (as in decrease_reservation() in
+ * drivers/xen/balloon.c).
+ *
+ * Many of these PTE updates are done on unpinned and writable pages
+ * and doing a hypercall for these is unnecessary and expensive.  At
+ * this point it is not possible to tell if a page is pinned or not,
+ * so always write the PTE directly and rely on Xen trapping and
+ * emulating any updates as necessary.
+ */
 static void __init xen_set_pte_init(pte_t *ptep, pte_t pte)
 {
-        pte = mask_rw_pte(ptep, pte);
+        if (pte_mfn(pte) != INVALID_P2M_ENTRY)
+                pte = mask_rw_pte(ptep, pte);
+        else
+                pte = __pte_ma(0);
 
-        xen_set_pte(ptep, pte);
+        native_set_pte(ptep, pte);
 }
 
 static void pin_pagetable_pfn(unsigned cmd, unsigned long pfn)
@@ -2041,8 +2065,7 @@ static const struct pv_mmu_ops xen_mmu_ops __initconst = {
 void __init xen_init_mmu_ops(void)
 {
         x86_init.mapping.pagetable_reserve = xen_mapping_pagetable_reserve;
-        x86_init.paging.pagetable_setup_start = xen_pagetable_setup_start;
-        x86_init.paging.pagetable_setup_done = xen_pagetable_setup_done;
+        x86_init.paging.pagetable_init = xen_pagetable_init;
         pv_mmu_ops = xen_mmu_ops;
 
         memset(dummy_mapping, 0xff, PAGE_SIZE);
diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c
index 64effdc6da9..76ba0e97e53 100644
--- a/arch/x86/xen/p2m.c
+++ b/arch/x86/xen/p2m.c
@@ -194,6 +194,13 @@ RESERVE_BRK(p2m_mid_mfn, PAGE_SIZE * (MAX_DOMAIN_PAGES / (P2M_PER_PAGE * P2M_MID
  * boundary violation will require three middle nodes. */
 RESERVE_BRK(p2m_mid_identity, PAGE_SIZE * 2 * 3);
 
+/* When we populate back during bootup, the amount of pages can vary. The
+ * max we have is seen is 395979, but that does not mean it can't be more.
+ * Some machines can have 3GB I/O holes even. With early_can_reuse_p2m_middle
+ * it can re-use Xen provided mfn_list array, so we only need to allocate at
+ * most three P2M top nodes. */
+RESERVE_BRK(p2m_populated, PAGE_SIZE * 3);
+
 static inline unsigned p2m_top_index(unsigned long pfn)
 {
         BUG_ON(pfn >= MAX_P2M_PFN);
@@ -570,12 +577,99 @@ static bool __init early_alloc_p2m(unsigned long pfn)
         }
         return true;
 }
+
+/*
+ * Skim over the P2M tree looking at pages that are either filled with
+ * INVALID_P2M_ENTRY or with 1:1 PFNs. If found, re-use that page and
+ * replace the P2M leaf with a p2m_missing or p2m_identity.
+ * Stick the old page in the new P2M tree location.
+ */
+bool __init early_can_reuse_p2m_middle(unsigned long set_pfn, unsigned long set_mfn)
+{
+        unsigned topidx;
+        unsigned mididx;
+        unsigned ident_pfns;
+        unsigned inv_pfns;
+        unsigned long *p2m;
+        unsigned long *mid_mfn_p;
+        unsigned idx;
+        unsigned long pfn;
+
+        /* We only look when this entails a P2M middle layer */
+        if (p2m_index(set_pfn))
+                return false;
+
+        for (pfn = 0; pfn < MAX_DOMAIN_PAGES; pfn += P2M_PER_PAGE) {
+                topidx = p2m_top_index(pfn);
+
+                if (!p2m_top[topidx])
+                        continue;
+
+                if (p2m_top[topidx] == p2m_mid_missing)
+                        continue;
+
+                mididx = p2m_mid_index(pfn);
+                p2m = p2m_top[topidx][mididx];
+                if (!p2m)
+                        continue;
+
+                if ((p2m == p2m_missing) || (p2m == p2m_identity))
+                        continue;
+
+                if ((unsigned long)p2m == INVALID_P2M_ENTRY)
+                        continue;
+
+                ident_pfns = 0;
+                inv_pfns = 0;
+                for (idx = 0; idx < P2M_PER_PAGE; idx++) {
+                        /* IDENTITY_PFNs are 1:1 */
+                        if (p2m[idx] == IDENTITY_FRAME(pfn + idx))
+                                ident_pfns++;
+                        else if (p2m[idx] == INVALID_P2M_ENTRY)
+                                inv_pfns++;
+                        else
+                                break;
+                }
+                if ((ident_pfns == P2M_PER_PAGE) || (inv_pfns == P2M_PER_PAGE))
+                        goto found;
+        }
+        return false;
+found:
+        /* Found one, replace old with p2m_identity or p2m_missing */
+        p2m_top[topidx][mididx] = (ident_pfns ? p2m_identity : p2m_missing);
+        /* And the other for save/restore.. */
+        mid_mfn_p = p2m_top_mfn_p[topidx];
+        /* NOTE: Even if it is a p2m_identity it should still be point to
+         * a page filled with INVALID_P2M_ENTRY entries. */
+        mid_mfn_p[mididx] = virt_to_mfn(p2m_missing);
+
+        /* Reset where we want to stick the old page in. */
+        topidx = p2m_top_index(set_pfn);
+        mididx = p2m_mid_index(set_pfn);
+
+        /* This shouldn't happen */
+        if (WARN_ON(p2m_top[topidx] == p2m_mid_missing))
+                early_alloc_p2m(set_pfn);
+
+        if (WARN_ON(p2m_top[topidx][mididx] != p2m_missing))
+                return false;
+
+        p2m_init(p2m);
+        p2m_top[topidx][mididx] = p2m;
+        mid_mfn_p = p2m_top_mfn_p[topidx];
+        mid_mfn_p[mididx] = virt_to_mfn(p2m);
+
+        return true;
+}
 bool __init early_set_phys_to_machine(unsigned long pfn, unsigned long mfn)
 {
         if (unlikely(!__set_phys_to_machine(pfn, mfn)))  {
                 if (!early_alloc_p2m(pfn))
                         return false;
 
+                if (early_can_reuse_p2m_middle(pfn, mfn))
+                        return __set_phys_to_machine(pfn, mfn);
+
                 if (!early_alloc_p2m_middle(pfn, false /* boundary crossover OK!*/))
                         return false;
 
diff --git a/arch/x86/xen/setup.c b/arch/x86/xen/setup.c
index a4790bf22c5..d11ca11d14f 100644
--- a/arch/x86/xen/setup.c
+++ b/arch/x86/xen/setup.c
@@ -78,9 +78,16 @@ static void __init xen_add_extra_mem(u64 start, u64 size)
         memblock_reserve(start, size);
 
         xen_max_p2m_pfn = PFN_DOWN(start + size);
+        for (pfn = PFN_DOWN(start); pfn < xen_max_p2m_pfn; pfn++) {
+                unsigned long mfn = pfn_to_mfn(pfn);
+
+                if (WARN(mfn == pfn, "Trying to over-write 1-1 mapping (pfn: %lx)\n", pfn))
+                        continue;
+                WARN(mfn != INVALID_P2M_ENTRY, "Trying to remove %lx which has %lx mfn!\n",
+                        pfn, mfn);
 
-        for (pfn = PFN_DOWN(start); pfn <= xen_max_p2m_pfn; pfn++)
                 __set_phys_to_machine(pfn, INVALID_P2M_ENTRY);
+        }
 }
 
 static unsigned long __init xen_do_chunk(unsigned long start,
@@ -157,25 +164,24 @@ static unsigned long __init xen_populate_chunk(
         unsigned long dest_pfn;
 
         for (i = 0, entry = list; i < map_size; i++, entry++) {
-                unsigned long credits = credits_left;
                 unsigned long s_pfn;
                 unsigned long e_pfn;
                 unsigned long pfns;
                 long capacity;
 
-                if (credits <= 0)
+                if (credits_left <= 0)
                         break;
 
                 if (entry->type != E820_RAM)
                         continue;
 
-                e_pfn = PFN_UP(entry->addr + entry->size);
+                e_pfn = PFN_DOWN(entry->addr + entry->size);
 
                 /* We only care about E820 after the xen_start_info->nr_pages */
                 if (e_pfn <= max_pfn)
                         continue;
 
-                s_pfn = PFN_DOWN(entry->addr);
+                s_pfn = PFN_UP(entry->addr);
                 /* If the E820 falls within the nr_pages, we want to start
                  * at the nr_pages PFN.
                  * If that would mean going past the E820 entry, skip it
@@ -184,23 +190,19 @@ static unsigned long __init xen_populate_chunk(
                         capacity = e_pfn - max_pfn;
                         dest_pfn = max_pfn;
                 } else {
-                        /* last_pfn MUST be within E820_RAM regions */
-                        if (*last_pfn && e_pfn >= *last_pfn)
-                                s_pfn = *last_pfn;
                         capacity = e_pfn - s_pfn;
                         dest_pfn = s_pfn;
                 }
-                /* If we had filled this E820_RAM entry, go to the next one. */
-                if (capacity <= 0)
-                        continue;
 
-                if (credits > capacity)
-                        credits = capacity;
+                if (credits_left < capacity)
+                        capacity = credits_left;
 
-                pfns = xen_do_chunk(dest_pfn, dest_pfn + credits, false);
+                pfns = xen_do_chunk(dest_pfn, dest_pfn + capacity, false);
                 done += pfns;
-                credits_left -= pfns;
                 *last_pfn = (dest_pfn + pfns);
+                if (pfns < capacity)
+                        break;
+                credits_left -= pfns;
         }
         return done;
 }
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index afb250d22a6..f58dca7a6e5 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -80,9 +80,7 @@ static void __cpuinit cpu_bringup(void)
 
         notify_cpu_starting(cpu);
 
-        ipi_call_lock();
         set_cpu_online(cpu, true);
-        ipi_call_unlock();
 
         this_cpu_write(cpu_state, CPU_ONLINE);
 
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 8a3f8351f43..8ed64cfae4f 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -7,6 +7,7 @@ config ZONE_DMA
 config XTENSA
         def_bool y
         select HAVE_IDE
+        select GENERIC_ATOMIC64
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_SHOW
         select GENERIC_CPU_DEVICES
diff --git a/arch/xtensa/include/asm/cpumask.h b/arch/xtensa/include/asm/cpumask.h
deleted file mode 100644
index ebeede397db..00000000000
--- a/arch/xtensa/include/asm/cpumask.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * include/asm-xtensa/cpumask.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
- */
-
-#ifndef _XTENSA_CPUMASK_H
-#define _XTENSA_CPUMASK_H
-
-#include <asm-generic/cpumask.h>
-
-#endif /* _XTENSA_CPUMASK_H */
diff --git a/arch/xtensa/include/asm/rmap.h b/arch/xtensa/include/asm/rmap.h
deleted file mode 100644
index 649588b7e9a..00000000000
--- a/arch/xtensa/include/asm/rmap.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * include/asm-xtensa/rmap.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
- */
-
-#ifndef _XTENSA_RMAP_H
-#define _XTENSA_RMAP_H
-
-#include <asm-generic/rmap.h>
-
-#endif
diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c
index eb30e356f5b..69759e9cb3e 100644
--- a/arch/xtensa/kernel/pci.c
+++ b/arch/xtensa/kernel/pci.c
@@ -46,7 +46,6 @@
  * pcibios_fixups
  * pcibios_align_resource
  * pcibios_fixup_bus
- * pcibios_setup
  * pci_bus_add_device
  * pci_mmap_page_range
  */
@@ -187,7 +186,7 @@ static int __init pcibios_init(void)
                 bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
                                         pci_ctrl->ops, pci_ctrl, &resources);
                 pci_ctrl->bus = bus;
-                pci_ctrl->last_busno = bus->subordinate;
+                pci_ctrl->last_busno = bus->busn_res.end;
                 if (next_busno <= pci_ctrl->last_busno)
                         next_busno = pci_ctrl->last_busno+1;
         }
@@ -206,11 +205,6 @@ void __init pcibios_fixup_bus(struct pci_bus *bus)
         }
 }
 
-char __init *pcibios_setup(char *str)
-{
-        return str;
-}
-
 void pcibios_set_master(struct pci_dev *dev)
 {
         /* No special bus mastering setup handling */
diff --git a/arch/xtensa/kernel/syscall.c b/arch/xtensa/kernel/syscall.c
index 816e6d0d686..05b3f093d5d 100644
--- a/arch/xtensa/kernel/syscall.c
+++ b/arch/xtensa/kernel/syscall.c
@@ -44,7 +44,7 @@ asmlinkage long xtensa_shmat(int shmid, char __user *shmaddr, int shmflg)
         unsigned long ret;
         long err;
 
-        err = do_shmat(shmid, shmaddr, shmflg, &ret);
+        err = do_shmat(shmid, shmaddr, shmflg, &ret, SHMLBA);
         if (err)
                 return err;
         return (long)ret;
diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c
index b17885a0b50..5a74c53bc69 100644
--- a/arch/xtensa/mm/fault.c
+++ b/arch/xtensa/mm/fault.c
@@ -44,6 +44,7 @@ void do_page_fault(struct pt_regs *regs)
 
         int is_write, is_exec;
         int fault;
+        unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE;
 
         info.si_code = SEGV_MAPERR;
 
@@ -71,6 +72,7 @@ void do_page_fault(struct pt_regs *regs)
                address, exccause, regs->pc, is_write? "w":"", is_exec? "x":"");
 #endif
 
+retry:
         down_read(&mm->mmap_sem);
         vma = find_vma(mm, address);
 
@@ -93,6 +95,7 @@ good_area:
         if (is_write) {
                 if (!(vma->vm_flags & VM_WRITE))
                         goto bad_area;
+                flags |= FAULT_FLAG_WRITE;
         } else if (is_exec) {
                 if (!(vma->vm_flags & VM_EXEC))
                         goto bad_area;
@@ -104,7 +107,11 @@ good_area:
          * make sure we exit gracefully rather than endlessly redo
          * the fault.
          */
-        fault = handle_mm_fault(mm, vma, address, is_write ? FAULT_FLAG_WRITE : 0);
+        fault = handle_mm_fault(mm, vma, address, flags);
+
+        if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current))
+                return;
+
         if (unlikely(fault & VM_FAULT_ERROR)) {
                 if (fault & VM_FAULT_OOM)
                         goto out_of_memory;
@@ -112,10 +119,22 @@ good_area:
                         goto do_sigbus;
                 BUG();
         }
-        if (fault & VM_FAULT_MAJOR)
-                current->maj_flt++;
-        else
-                current->min_flt++;
+        if (flags & FAULT_FLAG_ALLOW_RETRY) {
+                if (fault & VM_FAULT_MAJOR)
+                        current->maj_flt++;
+                else
+                        current->min_flt++;
+                if (fault & VM_FAULT_RETRY) {
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+
+                         /* No need to up_read(&mm->mmap_sem) as we would
+                         * have already released it in __lock_page_or_retry
+                         * in mm/filemap.c.
+                         */
+
+                        goto retry;
+                }
+        }
 
         up_read(&mm->mmap_sem);
         return;