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diff --git a/arch/x86/kernel/io_apic_32.c b/arch/x86/kernel/io_apic_32.c
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1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
28#include <linux/bootmem.h>
29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
32#include <linux/module.h>
33#include <linux/sysdev.h>
34#include <linux/pci.h>
35#include <linux/msi.h>
36#include <linux/htirq.h>
37#include <linux/freezer.h>
38#include <linux/kthread.h>
39#include <linux/jiffies.h> /* time_after() */
40
41#include <asm/io.h>
42#include <asm/smp.h>
43#include <asm/desc.h>
44#include <asm/timer.h>
45#include <asm/i8259.h>
46#include <asm/nmi.h>
47#include <asm/msidef.h>
48#include <asm/hypertransport.h>
49
50#include <mach_apic.h>
51#include <mach_apicdef.h>
52
53int (*ioapic_renumber_irq)(int ioapic, int irq);
54atomic_t irq_mis_count;
55
56/* Where if anywhere is the i8259 connect in external int mode */
57static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58
59static DEFINE_SPINLOCK(ioapic_lock);
60DEFINE_SPINLOCK(vector_lock);
61
62int timer_through_8259 __initdata;
63
64/*
65 * Is the SiS APIC rmw bug present ?
66 * -1 = don't know, 0 = no, 1 = yes
67 */
68int sis_apic_bug = -1;
69
70/*
71 * # of IRQ routing registers
72 */
73int nr_ioapic_registers[MAX_IO_APICS];
74
75/* I/O APIC entries */
76struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
77int nr_ioapics;
78
79/* MP IRQ source entries */
80struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
81
82/* # of MP IRQ source entries */
83int mp_irq_entries;
84
85#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
86int mp_bus_id_to_type[MAX_MP_BUSSES];
87#endif
88
89DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
90
91static int disable_timer_pin_1 __initdata;
92
93/*
94 * Rough estimation of how many shared IRQs there are, can
95 * be changed anytime.
96 */
97#define MAX_PLUS_SHARED_IRQS NR_IRQS
98#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
99
100/*
101 * This is performance-critical, we want to do it O(1)
102 *
103 * the indexing order of this array favors 1:1 mappings
104 * between pins and IRQs.
105 */
106
107static struct irq_pin_list {
108 int apic, pin, next;
109} irq_2_pin[PIN_MAP_SIZE];
110
111struct io_apic {
112 unsigned int index;
113 unsigned int unused[3];
114 unsigned int data;
115};
116
117static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
118{
119 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
120 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
121}
122
123static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
124{
125 struct io_apic __iomem *io_apic = io_apic_base(apic);
126 writel(reg, &io_apic->index);
127 return readl(&io_apic->data);
128}
129
130static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
131{
132 struct io_apic __iomem *io_apic = io_apic_base(apic);
133 writel(reg, &io_apic->index);
134 writel(value, &io_apic->data);
135}
136
137/*
138 * Re-write a value: to be used for read-modify-write
139 * cycles where the read already set up the index register.
140 *
141 * Older SiS APIC requires we rewrite the index register
142 */
143static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
144{
145 volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
146 if (sis_apic_bug)
147 writel(reg, &io_apic->index);
148 writel(value, &io_apic->data);
149}
150
151union entry_union {
152 struct { u32 w1, w2; };
153 struct IO_APIC_route_entry entry;
154};
155
156static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
157{
158 union entry_union eu;
159 unsigned long flags;
160 spin_lock_irqsave(&ioapic_lock, flags);
161 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
162 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
163 spin_unlock_irqrestore(&ioapic_lock, flags);
164 return eu.entry;
165}
166
167/*
168 * When we write a new IO APIC routing entry, we need to write the high
169 * word first! If the mask bit in the low word is clear, we will enable
170 * the interrupt, and we need to make sure the entry is fully populated
171 * before that happens.
172 */
173static void
174__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
175{
176 union entry_union eu;
177 eu.entry = e;
178 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
179 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
180}
181
182static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
183{
184 unsigned long flags;
185 spin_lock_irqsave(&ioapic_lock, flags);
186 __ioapic_write_entry(apic, pin, e);
187 spin_unlock_irqrestore(&ioapic_lock, flags);
188}
189
190/*
191 * When we mask an IO APIC routing entry, we need to write the low
192 * word first, in order to set the mask bit before we change the
193 * high bits!
194 */
195static void ioapic_mask_entry(int apic, int pin)
196{
197 unsigned long flags;
198 union entry_union eu = { .entry.mask = 1 };
199
200 spin_lock_irqsave(&ioapic_lock, flags);
201 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
202 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
203 spin_unlock_irqrestore(&ioapic_lock, flags);
204}
205
206/*
207 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
208 * shared ISA-space IRQs, so we have to support them. We are super
209 * fast in the common case, and fast for shared ISA-space IRQs.
210 */
211static void add_pin_to_irq(unsigned int irq, int apic, int pin)
212{
213 static int first_free_entry = NR_IRQS;
214 struct irq_pin_list *entry = irq_2_pin + irq;
215
216 while (entry->next)
217 entry = irq_2_pin + entry->next;
218
219 if (entry->pin != -1) {
220 entry->next = first_free_entry;
221 entry = irq_2_pin + entry->next;
222 if (++first_free_entry >= PIN_MAP_SIZE)
223 panic("io_apic.c: whoops");
224 }
225 entry->apic = apic;
226 entry->pin = pin;
227}
228
229/*
230 * Reroute an IRQ to a different pin.
231 */
232static void __init replace_pin_at_irq(unsigned int irq,
233 int oldapic, int oldpin,
234 int newapic, int newpin)
235{
236 struct irq_pin_list *entry = irq_2_pin + irq;
237
238 while (1) {
239 if (entry->apic == oldapic && entry->pin == oldpin) {
240 entry->apic = newapic;
241 entry->pin = newpin;
242 }
243 if (!entry->next)
244 break;
245 entry = irq_2_pin + entry->next;
246 }
247}
248
249static void __modify_IO_APIC_irq(unsigned int irq, unsigned long enable, unsigned long disable)
250{
251 struct irq_pin_list *entry = irq_2_pin + irq;
252 unsigned int pin, reg;
253
254 for (;;) {
255 pin = entry->pin;
256 if (pin == -1)
257 break;
258 reg = io_apic_read(entry->apic, 0x10 + pin*2);
259 reg &= ~disable;
260 reg |= enable;
261 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
262 if (!entry->next)
263 break;
264 entry = irq_2_pin + entry->next;
265 }
266}
267
268/* mask = 1 */
269static void __mask_IO_APIC_irq(unsigned int irq)
270{
271 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED, 0);
272}
273
274/* mask = 0 */
275static void __unmask_IO_APIC_irq(unsigned int irq)
276{
277 __modify_IO_APIC_irq(irq, 0, IO_APIC_REDIR_MASKED);
278}
279
280/* mask = 1, trigger = 0 */
281static void __mask_and_edge_IO_APIC_irq(unsigned int irq)
282{
283 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_MASKED,
284 IO_APIC_REDIR_LEVEL_TRIGGER);
285}
286
287/* mask = 0, trigger = 1 */
288static void __unmask_and_level_IO_APIC_irq(unsigned int irq)
289{
290 __modify_IO_APIC_irq(irq, IO_APIC_REDIR_LEVEL_TRIGGER,
291 IO_APIC_REDIR_MASKED);
292}
293
294static void mask_IO_APIC_irq(unsigned int irq)
295{
296 unsigned long flags;
297
298 spin_lock_irqsave(&ioapic_lock, flags);
299 __mask_IO_APIC_irq(irq);
300 spin_unlock_irqrestore(&ioapic_lock, flags);
301}
302
303static void unmask_IO_APIC_irq(unsigned int irq)
304{
305 unsigned long flags;
306
307 spin_lock_irqsave(&ioapic_lock, flags);
308 __unmask_IO_APIC_irq(irq);
309 spin_unlock_irqrestore(&ioapic_lock, flags);
310}
311
312static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
313{
314 struct IO_APIC_route_entry entry;
315
316 /* Check delivery_mode to be sure we're not clearing an SMI pin */
317 entry = ioapic_read_entry(apic, pin);
318 if (entry.delivery_mode == dest_SMI)
319 return;
320
321 /*
322 * Disable it in the IO-APIC irq-routing table:
323 */
324 ioapic_mask_entry(apic, pin);
325}
326
327static void clear_IO_APIC(void)
328{
329 int apic, pin;
330
331 for (apic = 0; apic < nr_ioapics; apic++)
332 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
333 clear_IO_APIC_pin(apic, pin);
334}
335
336#ifdef CONFIG_SMP
337static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
338{
339 unsigned long flags;
340 int pin;
341 struct irq_pin_list *entry = irq_2_pin + irq;
342 unsigned int apicid_value;
343 cpumask_t tmp;
344
345 cpus_and(tmp, cpumask, cpu_online_map);
346 if (cpus_empty(tmp))
347 tmp = TARGET_CPUS;
348
349 cpus_and(cpumask, tmp, CPU_MASK_ALL);
350
351 apicid_value = cpu_mask_to_apicid(cpumask);
352 /* Prepare to do the io_apic_write */
353 apicid_value = apicid_value << 24;
354 spin_lock_irqsave(&ioapic_lock, flags);
355 for (;;) {
356 pin = entry->pin;
357 if (pin == -1)
358 break;
359 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
360 if (!entry->next)
361 break;
362 entry = irq_2_pin + entry->next;
363 }
364 irq_desc[irq].affinity = cpumask;
365 spin_unlock_irqrestore(&ioapic_lock, flags);
366}
367
368#if defined(CONFIG_IRQBALANCE)
369# include <asm/processor.h> /* kernel_thread() */
370# include <linux/kernel_stat.h> /* kstat */
371# include <linux/slab.h> /* kmalloc() */
372# include <linux/timer.h>
373
374#define IRQBALANCE_CHECK_ARCH -999
375#define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
376#define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
377#define BALANCED_IRQ_MORE_DELTA (HZ/10)
378#define BALANCED_IRQ_LESS_DELTA (HZ)
379
380static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
381static int physical_balance __read_mostly;
382static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
383
384static struct irq_cpu_info {
385 unsigned long *last_irq;
386 unsigned long *irq_delta;
387 unsigned long irq;
388} irq_cpu_data[NR_CPUS];
389
390#define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
391#define LAST_CPU_IRQ(cpu, irq) (irq_cpu_data[cpu].last_irq[irq])
392#define IRQ_DELTA(cpu, irq) (irq_cpu_data[cpu].irq_delta[irq])
393
394#define IDLE_ENOUGH(cpu,now) \
395 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
396
397#define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
398
399#define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
400
401static cpumask_t balance_irq_affinity[NR_IRQS] = {
402 [0 ... NR_IRQS-1] = CPU_MASK_ALL
403};
404
405void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
406{
407 balance_irq_affinity[irq] = mask;
408}
409
410static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
411 unsigned long now, int direction)
412{
413 int search_idle = 1;
414 int cpu = curr_cpu;
415
416 goto inside;
417
418 do {
419 if (unlikely(cpu == curr_cpu))
420 search_idle = 0;
421inside:
422 if (direction == 1) {
423 cpu++;
424 if (cpu >= NR_CPUS)
425 cpu = 0;
426 } else {
427 cpu--;
428 if (cpu == -1)
429 cpu = NR_CPUS-1;
430 }
431 } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu, allowed_mask) ||
432 (search_idle && !IDLE_ENOUGH(cpu, now)));
433
434 return cpu;
435}
436
437static inline void balance_irq(int cpu, int irq)
438{
439 unsigned long now = jiffies;
440 cpumask_t allowed_mask;
441 unsigned int new_cpu;
442
443 if (irqbalance_disabled)
444 return;
445
446 cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
447 new_cpu = move(cpu, allowed_mask, now, 1);
448 if (cpu != new_cpu)
449 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
450}
451
452static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
453{
454 int i, j;
455
456 for_each_online_cpu(i) {
457 for (j = 0; j < NR_IRQS; j++) {
458 if (!irq_desc[j].action)
459 continue;
460 /* Is it a significant load ? */
461 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i), j) <
462 useful_load_threshold)
463 continue;
464 balance_irq(i, j);
465 }
466 }
467 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
468 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
469 return;
470}
471
472static void do_irq_balance(void)
473{
474 int i, j;
475 unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
476 unsigned long move_this_load = 0;
477 int max_loaded = 0, min_loaded = 0;
478 int load;
479 unsigned long useful_load_threshold = balanced_irq_interval + 10;
480 int selected_irq;
481 int tmp_loaded, first_attempt = 1;
482 unsigned long tmp_cpu_irq;
483 unsigned long imbalance = 0;
484 cpumask_t allowed_mask, target_cpu_mask, tmp;
485
486 for_each_possible_cpu(i) {
487 int package_index;
488 CPU_IRQ(i) = 0;
489 if (!cpu_online(i))
490 continue;
491 package_index = CPU_TO_PACKAGEINDEX(i);
492 for (j = 0; j < NR_IRQS; j++) {
493 unsigned long value_now, delta;
494 /* Is this an active IRQ or balancing disabled ? */
495 if (!irq_desc[j].action || irq_balancing_disabled(j))
496 continue;
497 if (package_index == i)
498 IRQ_DELTA(package_index, j) = 0;
499 /* Determine the total count per processor per IRQ */
500 value_now = (unsigned long) kstat_cpu(i).irqs[j];
501
502 /* Determine the activity per processor per IRQ */
503 delta = value_now - LAST_CPU_IRQ(i, j);
504
505 /* Update last_cpu_irq[][] for the next time */
506 LAST_CPU_IRQ(i, j) = value_now;
507
508 /* Ignore IRQs whose rate is less than the clock */
509 if (delta < useful_load_threshold)
510 continue;
511 /* update the load for the processor or package total */
512 IRQ_DELTA(package_index, j) += delta;
513
514 /* Keep track of the higher numbered sibling as well */
515 if (i != package_index)
516 CPU_IRQ(i) += delta;
517 /*
518 * We have sibling A and sibling B in the package
519 *
520 * cpu_irq[A] = load for cpu A + load for cpu B
521 * cpu_irq[B] = load for cpu B
522 */
523 CPU_IRQ(package_index) += delta;
524 }
525 }
526 /* Find the least loaded processor package */
527 for_each_online_cpu(i) {
528 if (i != CPU_TO_PACKAGEINDEX(i))
529 continue;
530 if (min_cpu_irq > CPU_IRQ(i)) {
531 min_cpu_irq = CPU_IRQ(i);
532 min_loaded = i;
533 }
534 }
535 max_cpu_irq = ULONG_MAX;
536
537tryanothercpu:
538 /*
539 * Look for heaviest loaded processor.
540 * We may come back to get the next heaviest loaded processor.
541 * Skip processors with trivial loads.
542 */
543 tmp_cpu_irq = 0;
544 tmp_loaded = -1;
545 for_each_online_cpu(i) {
546 if (i != CPU_TO_PACKAGEINDEX(i))
547 continue;
548 if (max_cpu_irq <= CPU_IRQ(i))
549 continue;
550 if (tmp_cpu_irq < CPU_IRQ(i)) {
551 tmp_cpu_irq = CPU_IRQ(i);
552 tmp_loaded = i;
553 }
554 }
555
556 if (tmp_loaded == -1) {
557 /*
558 * In the case of small number of heavy interrupt sources,
559 * loading some of the cpus too much. We use Ingo's original
560 * approach to rotate them around.
561 */
562 if (!first_attempt && imbalance >= useful_load_threshold) {
563 rotate_irqs_among_cpus(useful_load_threshold);
564 return;
565 }
566 goto not_worth_the_effort;
567 }
568
569 first_attempt = 0; /* heaviest search */
570 max_cpu_irq = tmp_cpu_irq; /* load */
571 max_loaded = tmp_loaded; /* processor */
572 imbalance = (max_cpu_irq - min_cpu_irq) / 2;
573
574 /*
575 * if imbalance is less than approx 10% of max load, then
576 * observe diminishing returns action. - quit
577 */
578 if (imbalance < (max_cpu_irq >> 3))
579 goto not_worth_the_effort;
580
581tryanotherirq:
582 /* if we select an IRQ to move that can't go where we want, then
583 * see if there is another one to try.
584 */
585 move_this_load = 0;
586 selected_irq = -1;
587 for (j = 0; j < NR_IRQS; j++) {
588 /* Is this an active IRQ? */
589 if (!irq_desc[j].action)
590 continue;
591 if (imbalance <= IRQ_DELTA(max_loaded, j))
592 continue;
593 /* Try to find the IRQ that is closest to the imbalance
594 * without going over.
595 */
596 if (move_this_load < IRQ_DELTA(max_loaded, j)) {
597 move_this_load = IRQ_DELTA(max_loaded, j);
598 selected_irq = j;
599 }
600 }
601 if (selected_irq == -1)
602 goto tryanothercpu;
603
604 imbalance = move_this_load;
605
606 /* For physical_balance case, we accumulated both load
607 * values in the one of the siblings cpu_irq[],
608 * to use the same code for physical and logical processors
609 * as much as possible.
610 *
611 * NOTE: the cpu_irq[] array holds the sum of the load for
612 * sibling A and sibling B in the slot for the lowest numbered
613 * sibling (A), _AND_ the load for sibling B in the slot for
614 * the higher numbered sibling.
615 *
616 * We seek the least loaded sibling by making the comparison
617 * (A+B)/2 vs B
618 */
619 load = CPU_IRQ(min_loaded) >> 1;
620 for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
621 if (load > CPU_IRQ(j)) {
622 /* This won't change cpu_sibling_map[min_loaded] */
623 load = CPU_IRQ(j);
624 min_loaded = j;
625 }
626 }
627
628 cpus_and(allowed_mask,
629 cpu_online_map,
630 balance_irq_affinity[selected_irq]);
631 target_cpu_mask = cpumask_of_cpu(min_loaded);
632 cpus_and(tmp, target_cpu_mask, allowed_mask);
633
634 if (!cpus_empty(tmp)) {
635 /* mark for change destination */
636 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
637
638 /* Since we made a change, come back sooner to
639 * check for more variation.
640 */
641 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
642 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
643 return;
644 }
645 goto tryanotherirq;
646
647not_worth_the_effort:
648 /*
649 * if we did not find an IRQ to move, then adjust the time interval
650 * upward
651 */
652 balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
653 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
654 return;
655}
656
657static int balanced_irq(void *unused)
658{
659 int i;
660 unsigned long prev_balance_time = jiffies;
661 long time_remaining = balanced_irq_interval;
662
663 /* push everything to CPU 0 to give us a starting point. */
664 for (i = 0 ; i < NR_IRQS ; i++) {
665 irq_desc[i].pending_mask = cpumask_of_cpu(0);
666 set_pending_irq(i, cpumask_of_cpu(0));
667 }
668
669 set_freezable();
670 for ( ; ; ) {
671 time_remaining = schedule_timeout_interruptible(time_remaining);
672 try_to_freeze();
673 if (time_after(jiffies,
674 prev_balance_time+balanced_irq_interval)) {
675 preempt_disable();
676 do_irq_balance();
677 prev_balance_time = jiffies;
678 time_remaining = balanced_irq_interval;
679 preempt_enable();
680 }
681 }
682 return 0;
683}
684
685static int __init balanced_irq_init(void)
686{
687 int i;
688 struct cpuinfo_x86 *c;
689 cpumask_t tmp;
690
691 cpus_shift_right(tmp, cpu_online_map, 2);
692 c = &boot_cpu_data;
693 /* When not overwritten by the command line ask subarchitecture. */
694 if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
695 irqbalance_disabled = NO_BALANCE_IRQ;
696 if (irqbalance_disabled)
697 return 0;
698
699 /* disable irqbalance completely if there is only one processor online */
700 if (num_online_cpus() < 2) {
701 irqbalance_disabled = 1;
702 return 0;
703 }
704 /*
705 * Enable physical balance only if more than 1 physical processor
706 * is present
707 */
708 if (smp_num_siblings > 1 && !cpus_empty(tmp))
709 physical_balance = 1;
710
711 for_each_online_cpu(i) {
712 irq_cpu_data[i].irq_delta = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
713 irq_cpu_data[i].last_irq = kzalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
714 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
715 printk(KERN_ERR "balanced_irq_init: out of memory");
716 goto failed;
717 }
718 }
719
720 printk(KERN_INFO "Starting balanced_irq\n");
721 if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
722 return 0;
723 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
724failed:
725 for_each_possible_cpu(i) {
726 kfree(irq_cpu_data[i].irq_delta);
727 irq_cpu_data[i].irq_delta = NULL;
728 kfree(irq_cpu_data[i].last_irq);
729 irq_cpu_data[i].last_irq = NULL;
730 }
731 return 0;
732}
733
734int __devinit irqbalance_disable(char *str)
735{
736 irqbalance_disabled = 1;
737 return 1;
738}
739
740__setup("noirqbalance", irqbalance_disable);
741
742late_initcall(balanced_irq_init);
743#endif /* CONFIG_IRQBALANCE */
744#endif /* CONFIG_SMP */
745
746#ifndef CONFIG_SMP
747void send_IPI_self(int vector)
748{
749 unsigned int cfg;
750
751 /*
752 * Wait for idle.
753 */
754 apic_wait_icr_idle();
755 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
756 /*
757 * Send the IPI. The write to APIC_ICR fires this off.
758 */
759 apic_write(APIC_ICR, cfg);
760}
761#endif /* !CONFIG_SMP */
762
763
764/*
765 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
766 * specific CPU-side IRQs.
767 */
768
769#define MAX_PIRQS 8
770static int pirq_entries [MAX_PIRQS];
771static int pirqs_enabled;
772int skip_ioapic_setup;
773
774static int __init ioapic_pirq_setup(char *str)
775{
776 int i, max;
777 int ints[MAX_PIRQS+1];
778
779 get_options(str, ARRAY_SIZE(ints), ints);
780
781 for (i = 0; i < MAX_PIRQS; i++)
782 pirq_entries[i] = -1;
783
784 pirqs_enabled = 1;
785 apic_printk(APIC_VERBOSE, KERN_INFO
786 "PIRQ redirection, working around broken MP-BIOS.\n");
787 max = MAX_PIRQS;
788 if (ints[0] < MAX_PIRQS)
789 max = ints[0];
790
791 for (i = 0; i < max; i++) {
792 apic_printk(APIC_VERBOSE, KERN_DEBUG
793 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
794 /*
795 * PIRQs are mapped upside down, usually.
796 */
797 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
798 }
799 return 1;
800}
801
802__setup("pirq=", ioapic_pirq_setup);
803
804/*
805 * Find the IRQ entry number of a certain pin.
806 */
807static int find_irq_entry(int apic, int pin, int type)
808{
809 int i;
810
811 for (i = 0; i < mp_irq_entries; i++)
812 if (mp_irqs[i].mp_irqtype == type &&
813 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
814 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
815 mp_irqs[i].mp_dstirq == pin)
816 return i;
817
818 return -1;
819}
820
821/*
822 * Find the pin to which IRQ[irq] (ISA) is connected
823 */
824static int __init find_isa_irq_pin(int irq, int type)
825{
826 int i;
827
828 for (i = 0; i < mp_irq_entries; i++) {
829 int lbus = mp_irqs[i].mp_srcbus;
830
831 if (test_bit(lbus, mp_bus_not_pci) &&
832 (mp_irqs[i].mp_irqtype == type) &&
833 (mp_irqs[i].mp_srcbusirq == irq))
834
835 return mp_irqs[i].mp_dstirq;
836 }
837 return -1;
838}
839
840static int __init find_isa_irq_apic(int irq, int type)
841{
842 int i;
843
844 for (i = 0; i < mp_irq_entries; i++) {
845 int lbus = mp_irqs[i].mp_srcbus;
846
847 if (test_bit(lbus, mp_bus_not_pci) &&
848 (mp_irqs[i].mp_irqtype == type) &&
849 (mp_irqs[i].mp_srcbusirq == irq))
850 break;
851 }
852 if (i < mp_irq_entries) {
853 int apic;
854 for (apic = 0; apic < nr_ioapics; apic++) {
855 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
856 return apic;
857 }
858 }
859
860 return -1;
861}
862
863/*
864 * Find a specific PCI IRQ entry.
865 * Not an __init, possibly needed by modules
866 */
867static int pin_2_irq(int idx, int apic, int pin);
868
869int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
870{
871 int apic, i, best_guess = -1;
872
873 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
874 "slot:%d, pin:%d.\n", bus, slot, pin);
875 if (test_bit(bus, mp_bus_not_pci)) {
876 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
877 return -1;
878 }
879 for (i = 0; i < mp_irq_entries; i++) {
880 int lbus = mp_irqs[i].mp_srcbus;
881
882 for (apic = 0; apic < nr_ioapics; apic++)
883 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
884 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
885 break;
886
887 if (!test_bit(lbus, mp_bus_not_pci) &&
888 !mp_irqs[i].mp_irqtype &&
889 (bus == lbus) &&
890 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
891 int irq = pin_2_irq(i, apic, mp_irqs[i].mp_dstirq);
892
893 if (!(apic || IO_APIC_IRQ(irq)))
894 continue;
895
896 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
897 return irq;
898 /*
899 * Use the first all-but-pin matching entry as a
900 * best-guess fuzzy result for broken mptables.
901 */
902 if (best_guess < 0)
903 best_guess = irq;
904 }
905 }
906 return best_guess;
907}
908EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
909
910/*
911 * This function currently is only a helper for the i386 smp boot process where
912 * we need to reprogram the ioredtbls to cater for the cpus which have come online
913 * so mask in all cases should simply be TARGET_CPUS
914 */
915#ifdef CONFIG_SMP
916void __init setup_ioapic_dest(void)
917{
918 int pin, ioapic, irq, irq_entry;
919
920 if (skip_ioapic_setup == 1)
921 return;
922
923 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
924 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
925 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
926 if (irq_entry == -1)
927 continue;
928 irq = pin_2_irq(irq_entry, ioapic, pin);
929 set_ioapic_affinity_irq(irq, TARGET_CPUS);
930 }
931
932 }
933}
934#endif
935
936#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
937/*
938 * EISA Edge/Level control register, ELCR
939 */
940static int EISA_ELCR(unsigned int irq)
941{
942 if (irq < 16) {
943 unsigned int port = 0x4d0 + (irq >> 3);
944 return (inb(port) >> (irq & 7)) & 1;
945 }
946 apic_printk(APIC_VERBOSE, KERN_INFO
947 "Broken MPtable reports ISA irq %d\n", irq);
948 return 0;
949}
950#endif
951
952/* ISA interrupts are always polarity zero edge triggered,
953 * when listed as conforming in the MP table. */
954
955#define default_ISA_trigger(idx) (0)
956#define default_ISA_polarity(idx) (0)
957
958/* EISA interrupts are always polarity zero and can be edge or level
959 * trigger depending on the ELCR value. If an interrupt is listed as
960 * EISA conforming in the MP table, that means its trigger type must
961 * be read in from the ELCR */
962
963#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
964#define default_EISA_polarity(idx) default_ISA_polarity(idx)
965
966/* PCI interrupts are always polarity one level triggered,
967 * when listed as conforming in the MP table. */
968
969#define default_PCI_trigger(idx) (1)
970#define default_PCI_polarity(idx) (1)
971
972/* MCA interrupts are always polarity zero level triggered,
973 * when listed as conforming in the MP table. */
974
975#define default_MCA_trigger(idx) (1)
976#define default_MCA_polarity(idx) default_ISA_polarity(idx)
977
978static int MPBIOS_polarity(int idx)
979{
980 int bus = mp_irqs[idx].mp_srcbus;
981 int polarity;
982
983 /*
984 * Determine IRQ line polarity (high active or low active):
985 */
986 switch (mp_irqs[idx].mp_irqflag & 3) {
987 case 0: /* conforms, ie. bus-type dependent polarity */
988 {
989 polarity = test_bit(bus, mp_bus_not_pci)?
990 default_ISA_polarity(idx):
991 default_PCI_polarity(idx);
992 break;
993 }
994 case 1: /* high active */
995 {
996 polarity = 0;
997 break;
998 }
999 case 2: /* reserved */
1000 {
1001 printk(KERN_WARNING "broken BIOS!!\n");
1002 polarity = 1;
1003 break;
1004 }
1005 case 3: /* low active */
1006 {
1007 polarity = 1;
1008 break;
1009 }
1010 default: /* invalid */
1011 {
1012 printk(KERN_WARNING "broken BIOS!!\n");
1013 polarity = 1;
1014 break;
1015 }
1016 }
1017 return polarity;
1018}
1019
1020static int MPBIOS_trigger(int idx)
1021{
1022 int bus = mp_irqs[idx].mp_srcbus;
1023 int trigger;
1024
1025 /*
1026 * Determine IRQ trigger mode (edge or level sensitive):
1027 */
1028 switch ((mp_irqs[idx].mp_irqflag>>2) & 3) {
1029 case 0: /* conforms, ie. bus-type dependent */
1030 {
1031 trigger = test_bit(bus, mp_bus_not_pci)?
1032 default_ISA_trigger(idx):
1033 default_PCI_trigger(idx);
1034#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1035 switch (mp_bus_id_to_type[bus]) {
1036 case MP_BUS_ISA: /* ISA pin */
1037 {
1038 /* set before the switch */
1039 break;
1040 }
1041 case MP_BUS_EISA: /* EISA pin */
1042 {
1043 trigger = default_EISA_trigger(idx);
1044 break;
1045 }
1046 case MP_BUS_PCI: /* PCI pin */
1047 {
1048 /* set before the switch */
1049 break;
1050 }
1051 case MP_BUS_MCA: /* MCA pin */
1052 {
1053 trigger = default_MCA_trigger(idx);
1054 break;
1055 }
1056 default:
1057 {
1058 printk(KERN_WARNING "broken BIOS!!\n");
1059 trigger = 1;
1060 break;
1061 }
1062 }
1063#endif
1064 break;
1065 }
1066 case 1: /* edge */
1067 {
1068 trigger = 0;
1069 break;
1070 }
1071 case 2: /* reserved */
1072 {
1073 printk(KERN_WARNING "broken BIOS!!\n");
1074 trigger = 1;
1075 break;
1076 }
1077 case 3: /* level */
1078 {
1079 trigger = 1;
1080 break;
1081 }
1082 default: /* invalid */
1083 {
1084 printk(KERN_WARNING "broken BIOS!!\n");
1085 trigger = 0;
1086 break;
1087 }
1088 }
1089 return trigger;
1090}
1091
1092static inline int irq_polarity(int idx)
1093{
1094 return MPBIOS_polarity(idx);
1095}
1096
1097static inline int irq_trigger(int idx)
1098{
1099 return MPBIOS_trigger(idx);
1100}
1101
1102static int pin_2_irq(int idx, int apic, int pin)
1103{
1104 int irq, i;
1105 int bus = mp_irqs[idx].mp_srcbus;
1106
1107 /*
1108 * Debugging check, we are in big trouble if this message pops up!
1109 */
1110 if (mp_irqs[idx].mp_dstirq != pin)
1111 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1112
1113 if (test_bit(bus, mp_bus_not_pci))
1114 irq = mp_irqs[idx].mp_srcbusirq;
1115 else {
1116 /*
1117 * PCI IRQs are mapped in order
1118 */
1119 i = irq = 0;
1120 while (i < apic)
1121 irq += nr_ioapic_registers[i++];
1122 irq += pin;
1123
1124 /*
1125 * For MPS mode, so far only needed by ES7000 platform
1126 */
1127 if (ioapic_renumber_irq)
1128 irq = ioapic_renumber_irq(apic, irq);
1129 }
1130
1131 /*
1132 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1133 */
1134 if ((pin >= 16) && (pin <= 23)) {
1135 if (pirq_entries[pin-16] != -1) {
1136 if (!pirq_entries[pin-16]) {
1137 apic_printk(APIC_VERBOSE, KERN_DEBUG
1138 "disabling PIRQ%d\n", pin-16);
1139 } else {
1140 irq = pirq_entries[pin-16];
1141 apic_printk(APIC_VERBOSE, KERN_DEBUG
1142 "using PIRQ%d -> IRQ %d\n",
1143 pin-16, irq);
1144 }
1145 }
1146 }
1147 return irq;
1148}
1149
1150static inline int IO_APIC_irq_trigger(int irq)
1151{
1152 int apic, idx, pin;
1153
1154 for (apic = 0; apic < nr_ioapics; apic++) {
1155 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1156 idx = find_irq_entry(apic, pin, mp_INT);
1157 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1158 return irq_trigger(idx);
1159 }
1160 }
1161 /*
1162 * nonexistent IRQs are edge default
1163 */
1164 return 0;
1165}
1166
1167/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1168static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1169
1170static int __assign_irq_vector(int irq)
1171{
1172 static int current_vector = FIRST_DEVICE_VECTOR, current_offset;
1173 int vector, offset;
1174
1175 BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1176
1177 if (irq_vector[irq] > 0)
1178 return irq_vector[irq];
1179
1180 vector = current_vector;
1181 offset = current_offset;
1182next:
1183 vector += 8;
1184 if (vector >= first_system_vector) {
1185 offset = (offset + 1) % 8;
1186 vector = FIRST_DEVICE_VECTOR + offset;
1187 }
1188 if (vector == current_vector)
1189 return -ENOSPC;
1190 if (test_and_set_bit(vector, used_vectors))
1191 goto next;
1192
1193 current_vector = vector;
1194 current_offset = offset;
1195 irq_vector[irq] = vector;
1196
1197 return vector;
1198}
1199
1200static int assign_irq_vector(int irq)
1201{
1202 unsigned long flags;
1203 int vector;
1204
1205 spin_lock_irqsave(&vector_lock, flags);
1206 vector = __assign_irq_vector(irq);
1207 spin_unlock_irqrestore(&vector_lock, flags);
1208
1209 return vector;
1210}
1211
1212static struct irq_chip ioapic_chip;
1213
1214#define IOAPIC_AUTO -1
1215#define IOAPIC_EDGE 0
1216#define IOAPIC_LEVEL 1
1217
1218static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1219{
1220 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1221 trigger == IOAPIC_LEVEL) {
1222 irq_desc[irq].status |= IRQ_LEVEL;
1223 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1224 handle_fasteoi_irq, "fasteoi");
1225 } else {
1226 irq_desc[irq].status &= ~IRQ_LEVEL;
1227 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1228 handle_edge_irq, "edge");
1229 }
1230 set_intr_gate(vector, interrupt[irq]);
1231}
1232
1233static void __init setup_IO_APIC_irqs(void)
1234{
1235 struct IO_APIC_route_entry entry;
1236 int apic, pin, idx, irq, first_notcon = 1, vector;
1237
1238 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1239
1240 for (apic = 0; apic < nr_ioapics; apic++) {
1241 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1242
1243 /*
1244 * add it to the IO-APIC irq-routing table:
1245 */
1246 memset(&entry, 0, sizeof(entry));
1247
1248 entry.delivery_mode = INT_DELIVERY_MODE;
1249 entry.dest_mode = INT_DEST_MODE;
1250 entry.mask = 0; /* enable IRQ */
1251 entry.dest.logical.logical_dest =
1252 cpu_mask_to_apicid(TARGET_CPUS);
1253
1254 idx = find_irq_entry(apic, pin, mp_INT);
1255 if (idx == -1) {
1256 if (first_notcon) {
1257 apic_printk(APIC_VERBOSE, KERN_DEBUG
1258 " IO-APIC (apicid-pin) %d-%d",
1259 mp_ioapics[apic].mp_apicid,
1260 pin);
1261 first_notcon = 0;
1262 } else
1263 apic_printk(APIC_VERBOSE, ", %d-%d",
1264 mp_ioapics[apic].mp_apicid, pin);
1265 continue;
1266 }
1267
1268 if (!first_notcon) {
1269 apic_printk(APIC_VERBOSE, " not connected.\n");
1270 first_notcon = 1;
1271 }
1272
1273 entry.trigger = irq_trigger(idx);
1274 entry.polarity = irq_polarity(idx);
1275
1276 if (irq_trigger(idx)) {
1277 entry.trigger = 1;
1278 entry.mask = 1;
1279 }
1280
1281 irq = pin_2_irq(idx, apic, pin);
1282 /*
1283 * skip adding the timer int on secondary nodes, which causes
1284 * a small but painful rift in the time-space continuum
1285 */
1286 if (multi_timer_check(apic, irq))
1287 continue;
1288 else
1289 add_pin_to_irq(irq, apic, pin);
1290
1291 if (!apic && !IO_APIC_IRQ(irq))
1292 continue;
1293
1294 if (IO_APIC_IRQ(irq)) {
1295 vector = assign_irq_vector(irq);
1296 entry.vector = vector;
1297 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1298
1299 if (!apic && (irq < 16))
1300 disable_8259A_irq(irq);
1301 }
1302 ioapic_write_entry(apic, pin, entry);
1303 }
1304 }
1305
1306 if (!first_notcon)
1307 apic_printk(APIC_VERBOSE, " not connected.\n");
1308}
1309
1310/*
1311 * Set up the timer pin, possibly with the 8259A-master behind.
1312 */
1313static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1314 int vector)
1315{
1316 struct IO_APIC_route_entry entry;
1317
1318 memset(&entry, 0, sizeof(entry));
1319
1320 /*
1321 * We use logical delivery to get the timer IRQ
1322 * to the first CPU.
1323 */
1324 entry.dest_mode = INT_DEST_MODE;
1325 entry.mask = 1; /* mask IRQ now */
1326 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1327 entry.delivery_mode = INT_DELIVERY_MODE;
1328 entry.polarity = 0;
1329 entry.trigger = 0;
1330 entry.vector = vector;
1331
1332 /*
1333 * The timer IRQ doesn't have to know that behind the
1334 * scene we may have a 8259A-master in AEOI mode ...
1335 */
1336 ioapic_register_intr(0, vector, IOAPIC_EDGE);
1337
1338 /*
1339 * Add it to the IO-APIC irq-routing table:
1340 */
1341 ioapic_write_entry(apic, pin, entry);
1342}
1343
1344void __init print_IO_APIC(void)
1345{
1346 int apic, i;
1347 union IO_APIC_reg_00 reg_00;
1348 union IO_APIC_reg_01 reg_01;
1349 union IO_APIC_reg_02 reg_02;
1350 union IO_APIC_reg_03 reg_03;
1351 unsigned long flags;
1352
1353 if (apic_verbosity == APIC_QUIET)
1354 return;
1355
1356 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1357 for (i = 0; i < nr_ioapics; i++)
1358 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1359 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1360
1361 /*
1362 * We are a bit conservative about what we expect. We have to
1363 * know about every hardware change ASAP.
1364 */
1365 printk(KERN_INFO "testing the IO APIC.......................\n");
1366
1367 for (apic = 0; apic < nr_ioapics; apic++) {
1368
1369 spin_lock_irqsave(&ioapic_lock, flags);
1370 reg_00.raw = io_apic_read(apic, 0);
1371 reg_01.raw = io_apic_read(apic, 1);
1372 if (reg_01.bits.version >= 0x10)
1373 reg_02.raw = io_apic_read(apic, 2);
1374 if (reg_01.bits.version >= 0x20)
1375 reg_03.raw = io_apic_read(apic, 3);
1376 spin_unlock_irqrestore(&ioapic_lock, flags);
1377
1378 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1379 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1380 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1381 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1382 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1383
1384 printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1385 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1386
1387 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1388 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1389
1390 /*
1391 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1392 * but the value of reg_02 is read as the previous read register
1393 * value, so ignore it if reg_02 == reg_01.
1394 */
1395 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1396 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1397 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1398 }
1399
1400 /*
1401 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1402 * or reg_03, but the value of reg_0[23] is read as the previous read
1403 * register value, so ignore it if reg_03 == reg_0[12].
1404 */
1405 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1406 reg_03.raw != reg_01.raw) {
1407 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1408 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1409 }
1410
1411 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1412
1413 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1414 " Stat Dest Deli Vect: \n");
1415
1416 for (i = 0; i <= reg_01.bits.entries; i++) {
1417 struct IO_APIC_route_entry entry;
1418
1419 entry = ioapic_read_entry(apic, i);
1420
1421 printk(KERN_DEBUG " %02x %03X %02X ",
1422 i,
1423 entry.dest.logical.logical_dest,
1424 entry.dest.physical.physical_dest
1425 );
1426
1427 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1428 entry.mask,
1429 entry.trigger,
1430 entry.irr,
1431 entry.polarity,
1432 entry.delivery_status,
1433 entry.dest_mode,
1434 entry.delivery_mode,
1435 entry.vector
1436 );
1437 }
1438 }
1439 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1440 for (i = 0; i < NR_IRQS; i++) {
1441 struct irq_pin_list *entry = irq_2_pin + i;
1442 if (entry->pin < 0)
1443 continue;
1444 printk(KERN_DEBUG "IRQ%d ", i);
1445 for (;;) {
1446 printk("-> %d:%d", entry->apic, entry->pin);
1447 if (!entry->next)
1448 break;
1449 entry = irq_2_pin + entry->next;
1450 }
1451 printk("\n");
1452 }
1453
1454 printk(KERN_INFO ".................................... done.\n");
1455
1456 return;
1457}
1458
1459#if 0
1460
1461static void print_APIC_bitfield(int base)
1462{
1463 unsigned int v;
1464 int i, j;
1465
1466 if (apic_verbosity == APIC_QUIET)
1467 return;
1468
1469 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1470 for (i = 0; i < 8; i++) {
1471 v = apic_read(base + i*0x10);
1472 for (j = 0; j < 32; j++) {
1473 if (v & (1<<j))
1474 printk("1");
1475 else
1476 printk("0");
1477 }
1478 printk("\n");
1479 }
1480}
1481
1482void /*__init*/ print_local_APIC(void *dummy)
1483{
1484 unsigned int v, ver, maxlvt;
1485
1486 if (apic_verbosity == APIC_QUIET)
1487 return;
1488
1489 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1490 smp_processor_id(), hard_smp_processor_id());
1491 v = apic_read(APIC_ID);
1492 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v,
1493 GET_APIC_ID(read_apic_id()));
1494 v = apic_read(APIC_LVR);
1495 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1496 ver = GET_APIC_VERSION(v);
1497 maxlvt = lapic_get_maxlvt();
1498
1499 v = apic_read(APIC_TASKPRI);
1500 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1501
1502 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1503 v = apic_read(APIC_ARBPRI);
1504 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1505 v & APIC_ARBPRI_MASK);
1506 v = apic_read(APIC_PROCPRI);
1507 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1508 }
1509
1510 v = apic_read(APIC_EOI);
1511 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1512 v = apic_read(APIC_RRR);
1513 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1514 v = apic_read(APIC_LDR);
1515 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1516 v = apic_read(APIC_DFR);
1517 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1518 v = apic_read(APIC_SPIV);
1519 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1520
1521 printk(KERN_DEBUG "... APIC ISR field:\n");
1522 print_APIC_bitfield(APIC_ISR);
1523 printk(KERN_DEBUG "... APIC TMR field:\n");
1524 print_APIC_bitfield(APIC_TMR);
1525 printk(KERN_DEBUG "... APIC IRR field:\n");
1526 print_APIC_bitfield(APIC_IRR);
1527
1528 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1529 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1530 apic_write(APIC_ESR, 0);
1531 v = apic_read(APIC_ESR);
1532 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1533 }
1534
1535 v = apic_read(APIC_ICR);
1536 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1537 v = apic_read(APIC_ICR2);
1538 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1539
1540 v = apic_read(APIC_LVTT);
1541 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1542
1543 if (maxlvt > 3) { /* PC is LVT#4. */
1544 v = apic_read(APIC_LVTPC);
1545 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1546 }
1547 v = apic_read(APIC_LVT0);
1548 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1549 v = apic_read(APIC_LVT1);
1550 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1551
1552 if (maxlvt > 2) { /* ERR is LVT#3. */
1553 v = apic_read(APIC_LVTERR);
1554 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1555 }
1556
1557 v = apic_read(APIC_TMICT);
1558 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1559 v = apic_read(APIC_TMCCT);
1560 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1561 v = apic_read(APIC_TDCR);
1562 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1563 printk("\n");
1564}
1565
1566void print_all_local_APICs(void)
1567{
1568 on_each_cpu(print_local_APIC, NULL, 1);
1569}
1570
1571void /*__init*/ print_PIC(void)
1572{
1573 unsigned int v;
1574 unsigned long flags;
1575
1576 if (apic_verbosity == APIC_QUIET)
1577 return;
1578
1579 printk(KERN_DEBUG "\nprinting PIC contents\n");
1580
1581 spin_lock_irqsave(&i8259A_lock, flags);
1582
1583 v = inb(0xa1) << 8 | inb(0x21);
1584 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1585
1586 v = inb(0xa0) << 8 | inb(0x20);
1587 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1588
1589 outb(0x0b, 0xa0);
1590 outb(0x0b, 0x20);
1591 v = inb(0xa0) << 8 | inb(0x20);
1592 outb(0x0a, 0xa0);
1593 outb(0x0a, 0x20);
1594
1595 spin_unlock_irqrestore(&i8259A_lock, flags);
1596
1597 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1598
1599 v = inb(0x4d1) << 8 | inb(0x4d0);
1600 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1601}
1602
1603#endif /* 0 */
1604
1605static void __init enable_IO_APIC(void)
1606{
1607 union IO_APIC_reg_01 reg_01;
1608 int i8259_apic, i8259_pin;
1609 int i, apic;
1610 unsigned long flags;
1611
1612 for (i = 0; i < PIN_MAP_SIZE; i++) {
1613 irq_2_pin[i].pin = -1;
1614 irq_2_pin[i].next = 0;
1615 }
1616 if (!pirqs_enabled)
1617 for (i = 0; i < MAX_PIRQS; i++)
1618 pirq_entries[i] = -1;
1619
1620 /*
1621 * The number of IO-APIC IRQ registers (== #pins):
1622 */
1623 for (apic = 0; apic < nr_ioapics; apic++) {
1624 spin_lock_irqsave(&ioapic_lock, flags);
1625 reg_01.raw = io_apic_read(apic, 1);
1626 spin_unlock_irqrestore(&ioapic_lock, flags);
1627 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1628 }
1629 for (apic = 0; apic < nr_ioapics; apic++) {
1630 int pin;
1631 /* See if any of the pins is in ExtINT mode */
1632 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1633 struct IO_APIC_route_entry entry;
1634 entry = ioapic_read_entry(apic, pin);
1635
1636
1637 /* If the interrupt line is enabled and in ExtInt mode
1638 * I have found the pin where the i8259 is connected.
1639 */
1640 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1641 ioapic_i8259.apic = apic;
1642 ioapic_i8259.pin = pin;
1643 goto found_i8259;
1644 }
1645 }
1646 }
1647 found_i8259:
1648 /* Look to see what if the MP table has reported the ExtINT */
1649 /* If we could not find the appropriate pin by looking at the ioapic
1650 * the i8259 probably is not connected the ioapic but give the
1651 * mptable a chance anyway.
1652 */
1653 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1654 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1655 /* Trust the MP table if nothing is setup in the hardware */
1656 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1657 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1658 ioapic_i8259.pin = i8259_pin;
1659 ioapic_i8259.apic = i8259_apic;
1660 }
1661 /* Complain if the MP table and the hardware disagree */
1662 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1663 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1664 {
1665 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1666 }
1667
1668 /*
1669 * Do not trust the IO-APIC being empty at bootup
1670 */
1671 clear_IO_APIC();
1672}
1673
1674/*
1675 * Not an __init, needed by the reboot code
1676 */
1677void disable_IO_APIC(void)
1678{
1679 /*
1680 * Clear the IO-APIC before rebooting:
1681 */
1682 clear_IO_APIC();
1683
1684 /*
1685 * If the i8259 is routed through an IOAPIC
1686 * Put that IOAPIC in virtual wire mode
1687 * so legacy interrupts can be delivered.
1688 */
1689 if (ioapic_i8259.pin != -1) {
1690 struct IO_APIC_route_entry entry;
1691
1692 memset(&entry, 0, sizeof(entry));
1693 entry.mask = 0; /* Enabled */
1694 entry.trigger = 0; /* Edge */
1695 entry.irr = 0;
1696 entry.polarity = 0; /* High */
1697 entry.delivery_status = 0;
1698 entry.dest_mode = 0; /* Physical */
1699 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1700 entry.vector = 0;
1701 entry.dest.physical.physical_dest =
1702 GET_APIC_ID(read_apic_id());
1703
1704 /*
1705 * Add it to the IO-APIC irq-routing table:
1706 */
1707 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1708 }
1709 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1710}
1711
1712/*
1713 * function to set the IO-APIC physical IDs based on the
1714 * values stored in the MPC table.
1715 *
1716 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1717 */
1718
1719static void __init setup_ioapic_ids_from_mpc(void)
1720{
1721 union IO_APIC_reg_00 reg_00;
1722 physid_mask_t phys_id_present_map;
1723 int apic;
1724 int i;
1725 unsigned char old_id;
1726 unsigned long flags;
1727
1728#ifdef CONFIG_X86_NUMAQ
1729 if (found_numaq)
1730 return;
1731#endif
1732
1733 /*
1734 * Don't check I/O APIC IDs for xAPIC systems. They have
1735 * no meaning without the serial APIC bus.
1736 */
1737 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1738 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1739 return;
1740 /*
1741 * This is broken; anything with a real cpu count has to
1742 * circumvent this idiocy regardless.
1743 */
1744 phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1745
1746 /*
1747 * Set the IOAPIC ID to the value stored in the MPC table.
1748 */
1749 for (apic = 0; apic < nr_ioapics; apic++) {
1750
1751 /* Read the register 0 value */
1752 spin_lock_irqsave(&ioapic_lock, flags);
1753 reg_00.raw = io_apic_read(apic, 0);
1754 spin_unlock_irqrestore(&ioapic_lock, flags);
1755
1756 old_id = mp_ioapics[apic].mp_apicid;
1757
1758 if (mp_ioapics[apic].mp_apicid >= get_physical_broadcast()) {
1759 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1760 apic, mp_ioapics[apic].mp_apicid);
1761 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1762 reg_00.bits.ID);
1763 mp_ioapics[apic].mp_apicid = reg_00.bits.ID;
1764 }
1765
1766 /*
1767 * Sanity check, is the ID really free? Every APIC in a
1768 * system must have a unique ID or we get lots of nice
1769 * 'stuck on smp_invalidate_needed IPI wait' messages.
1770 */
1771 if (check_apicid_used(phys_id_present_map,
1772 mp_ioapics[apic].mp_apicid)) {
1773 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1774 apic, mp_ioapics[apic].mp_apicid);
1775 for (i = 0; i < get_physical_broadcast(); i++)
1776 if (!physid_isset(i, phys_id_present_map))
1777 break;
1778 if (i >= get_physical_broadcast())
1779 panic("Max APIC ID exceeded!\n");
1780 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1781 i);
1782 physid_set(i, phys_id_present_map);
1783 mp_ioapics[apic].mp_apicid = i;
1784 } else {
1785 physid_mask_t tmp;
1786 tmp = apicid_to_cpu_present(mp_ioapics[apic].mp_apicid);
1787 apic_printk(APIC_VERBOSE, "Setting %d in the "
1788 "phys_id_present_map\n",
1789 mp_ioapics[apic].mp_apicid);
1790 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1791 }
1792
1793
1794 /*
1795 * We need to adjust the IRQ routing table
1796 * if the ID changed.
1797 */
1798 if (old_id != mp_ioapics[apic].mp_apicid)
1799 for (i = 0; i < mp_irq_entries; i++)
1800 if (mp_irqs[i].mp_dstapic == old_id)
1801 mp_irqs[i].mp_dstapic
1802 = mp_ioapics[apic].mp_apicid;
1803
1804 /*
1805 * Read the right value from the MPC table and
1806 * write it into the ID register.
1807 */
1808 apic_printk(APIC_VERBOSE, KERN_INFO
1809 "...changing IO-APIC physical APIC ID to %d ...",
1810 mp_ioapics[apic].mp_apicid);
1811
1812 reg_00.bits.ID = mp_ioapics[apic].mp_apicid;
1813 spin_lock_irqsave(&ioapic_lock, flags);
1814 io_apic_write(apic, 0, reg_00.raw);
1815 spin_unlock_irqrestore(&ioapic_lock, flags);
1816
1817 /*
1818 * Sanity check
1819 */
1820 spin_lock_irqsave(&ioapic_lock, flags);
1821 reg_00.raw = io_apic_read(apic, 0);
1822 spin_unlock_irqrestore(&ioapic_lock, flags);
1823 if (reg_00.bits.ID != mp_ioapics[apic].mp_apicid)
1824 printk("could not set ID!\n");
1825 else
1826 apic_printk(APIC_VERBOSE, " ok.\n");
1827 }
1828}
1829
1830int no_timer_check __initdata;
1831
1832static int __init notimercheck(char *s)
1833{
1834 no_timer_check = 1;
1835 return 1;
1836}
1837__setup("no_timer_check", notimercheck);
1838
1839/*
1840 * There is a nasty bug in some older SMP boards, their mptable lies
1841 * about the timer IRQ. We do the following to work around the situation:
1842 *
1843 * - timer IRQ defaults to IO-APIC IRQ
1844 * - if this function detects that timer IRQs are defunct, then we fall
1845 * back to ISA timer IRQs
1846 */
1847static int __init timer_irq_works(void)
1848{
1849 unsigned long t1 = jiffies;
1850 unsigned long flags;
1851
1852 if (no_timer_check)
1853 return 1;
1854
1855 local_save_flags(flags);
1856 local_irq_enable();
1857 /* Let ten ticks pass... */
1858 mdelay((10 * 1000) / HZ);
1859 local_irq_restore(flags);
1860
1861 /*
1862 * Expect a few ticks at least, to be sure some possible
1863 * glue logic does not lock up after one or two first
1864 * ticks in a non-ExtINT mode. Also the local APIC
1865 * might have cached one ExtINT interrupt. Finally, at
1866 * least one tick may be lost due to delays.
1867 */
1868 if (time_after(jiffies, t1 + 4))
1869 return 1;
1870
1871 return 0;
1872}
1873
1874/*
1875 * In the SMP+IOAPIC case it might happen that there are an unspecified
1876 * number of pending IRQ events unhandled. These cases are very rare,
1877 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1878 * better to do it this way as thus we do not have to be aware of
1879 * 'pending' interrupts in the IRQ path, except at this point.
1880 */
1881/*
1882 * Edge triggered needs to resend any interrupt
1883 * that was delayed but this is now handled in the device
1884 * independent code.
1885 */
1886
1887/*
1888 * Startup quirk:
1889 *
1890 * Starting up a edge-triggered IO-APIC interrupt is
1891 * nasty - we need to make sure that we get the edge.
1892 * If it is already asserted for some reason, we need
1893 * return 1 to indicate that is was pending.
1894 *
1895 * This is not complete - we should be able to fake
1896 * an edge even if it isn't on the 8259A...
1897 *
1898 * (We do this for level-triggered IRQs too - it cannot hurt.)
1899 */
1900static unsigned int startup_ioapic_irq(unsigned int irq)
1901{
1902 int was_pending = 0;
1903 unsigned long flags;
1904
1905 spin_lock_irqsave(&ioapic_lock, flags);
1906 if (irq < 16) {
1907 disable_8259A_irq(irq);
1908 if (i8259A_irq_pending(irq))
1909 was_pending = 1;
1910 }
1911 __unmask_IO_APIC_irq(irq);
1912 spin_unlock_irqrestore(&ioapic_lock, flags);
1913
1914 return was_pending;
1915}
1916
1917static void ack_ioapic_irq(unsigned int irq)
1918{
1919 move_native_irq(irq);
1920 ack_APIC_irq();
1921}
1922
1923static void ack_ioapic_quirk_irq(unsigned int irq)
1924{
1925 unsigned long v;
1926 int i;
1927
1928 move_native_irq(irq);
1929/*
1930 * It appears there is an erratum which affects at least version 0x11
1931 * of I/O APIC (that's the 82093AA and cores integrated into various
1932 * chipsets). Under certain conditions a level-triggered interrupt is
1933 * erroneously delivered as edge-triggered one but the respective IRR
1934 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1935 * message but it will never arrive and further interrupts are blocked
1936 * from the source. The exact reason is so far unknown, but the
1937 * phenomenon was observed when two consecutive interrupt requests
1938 * from a given source get delivered to the same CPU and the source is
1939 * temporarily disabled in between.
1940 *
1941 * A workaround is to simulate an EOI message manually. We achieve it
1942 * by setting the trigger mode to edge and then to level when the edge
1943 * trigger mode gets detected in the TMR of a local APIC for a
1944 * level-triggered interrupt. We mask the source for the time of the
1945 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1946 * The idea is from Manfred Spraul. --macro
1947 */
1948 i = irq_vector[irq];
1949
1950 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1951
1952 ack_APIC_irq();
1953
1954 if (!(v & (1 << (i & 0x1f)))) {
1955 atomic_inc(&irq_mis_count);
1956 spin_lock(&ioapic_lock);
1957 __mask_and_edge_IO_APIC_irq(irq);
1958 __unmask_and_level_IO_APIC_irq(irq);
1959 spin_unlock(&ioapic_lock);
1960 }
1961}
1962
1963static int ioapic_retrigger_irq(unsigned int irq)
1964{
1965 send_IPI_self(irq_vector[irq]);
1966
1967 return 1;
1968}
1969
1970static struct irq_chip ioapic_chip __read_mostly = {
1971 .name = "IO-APIC",
1972 .startup = startup_ioapic_irq,
1973 .mask = mask_IO_APIC_irq,
1974 .unmask = unmask_IO_APIC_irq,
1975 .ack = ack_ioapic_irq,
1976 .eoi = ack_ioapic_quirk_irq,
1977#ifdef CONFIG_SMP
1978 .set_affinity = set_ioapic_affinity_irq,
1979#endif
1980 .retrigger = ioapic_retrigger_irq,
1981};
1982
1983
1984static inline void init_IO_APIC_traps(void)
1985{
1986 int irq;
1987
1988 /*
1989 * NOTE! The local APIC isn't very good at handling
1990 * multiple interrupts at the same interrupt level.
1991 * As the interrupt level is determined by taking the
1992 * vector number and shifting that right by 4, we
1993 * want to spread these out a bit so that they don't
1994 * all fall in the same interrupt level.
1995 *
1996 * Also, we've got to be careful not to trash gate
1997 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1998 */
1999 for (irq = 0; irq < NR_IRQS ; irq++) {
2000 if (IO_APIC_IRQ(irq) && !irq_vector[irq]) {
2001 /*
2002 * Hmm.. We don't have an entry for this,
2003 * so default to an old-fashioned 8259
2004 * interrupt if we can..
2005 */
2006 if (irq < 16)
2007 make_8259A_irq(irq);
2008 else
2009 /* Strange. Oh, well.. */
2010 irq_desc[irq].chip = &no_irq_chip;
2011 }
2012 }
2013}
2014
2015/*
2016 * The local APIC irq-chip implementation:
2017 */
2018
2019static void ack_lapic_irq(unsigned int irq)
2020{
2021 ack_APIC_irq();
2022}
2023
2024static void mask_lapic_irq(unsigned int irq)
2025{
2026 unsigned long v;
2027
2028 v = apic_read(APIC_LVT0);
2029 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2030}
2031
2032static void unmask_lapic_irq(unsigned int irq)
2033{
2034 unsigned long v;
2035
2036 v = apic_read(APIC_LVT0);
2037 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2038}
2039
2040static struct irq_chip lapic_chip __read_mostly = {
2041 .name = "local-APIC",
2042 .mask = mask_lapic_irq,
2043 .unmask = unmask_lapic_irq,
2044 .ack = ack_lapic_irq,
2045};
2046
2047static void lapic_register_intr(int irq, int vector)
2048{
2049 irq_desc[irq].status &= ~IRQ_LEVEL;
2050 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2051 "edge");
2052 set_intr_gate(vector, interrupt[irq]);
2053}
2054
2055static void __init setup_nmi(void)
2056{
2057 /*
2058 * Dirty trick to enable the NMI watchdog ...
2059 * We put the 8259A master into AEOI mode and
2060 * unmask on all local APICs LVT0 as NMI.
2061 *
2062 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2063 * is from Maciej W. Rozycki - so we do not have to EOI from
2064 * the NMI handler or the timer interrupt.
2065 */
2066 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2067
2068 enable_NMI_through_LVT0();
2069
2070 apic_printk(APIC_VERBOSE, " done.\n");
2071}
2072
2073/*
2074 * This looks a bit hackish but it's about the only one way of sending
2075 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2076 * not support the ExtINT mode, unfortunately. We need to send these
2077 * cycles as some i82489DX-based boards have glue logic that keeps the
2078 * 8259A interrupt line asserted until INTA. --macro
2079 */
2080static inline void __init unlock_ExtINT_logic(void)
2081{
2082 int apic, pin, i;
2083 struct IO_APIC_route_entry entry0, entry1;
2084 unsigned char save_control, save_freq_select;
2085
2086 pin = find_isa_irq_pin(8, mp_INT);
2087 if (pin == -1) {
2088 WARN_ON_ONCE(1);
2089 return;
2090 }
2091 apic = find_isa_irq_apic(8, mp_INT);
2092 if (apic == -1) {
2093 WARN_ON_ONCE(1);
2094 return;
2095 }
2096
2097 entry0 = ioapic_read_entry(apic, pin);
2098 clear_IO_APIC_pin(apic, pin);
2099
2100 memset(&entry1, 0, sizeof(entry1));
2101
2102 entry1.dest_mode = 0; /* physical delivery */
2103 entry1.mask = 0; /* unmask IRQ now */
2104 entry1.dest.physical.physical_dest = hard_smp_processor_id();
2105 entry1.delivery_mode = dest_ExtINT;
2106 entry1.polarity = entry0.polarity;
2107 entry1.trigger = 0;
2108 entry1.vector = 0;
2109
2110 ioapic_write_entry(apic, pin, entry1);
2111
2112 save_control = CMOS_READ(RTC_CONTROL);
2113 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2114 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2115 RTC_FREQ_SELECT);
2116 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2117
2118 i = 100;
2119 while (i-- > 0) {
2120 mdelay(10);
2121 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2122 i -= 10;
2123 }
2124
2125 CMOS_WRITE(save_control, RTC_CONTROL);
2126 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2127 clear_IO_APIC_pin(apic, pin);
2128
2129 ioapic_write_entry(apic, pin, entry0);
2130}
2131
2132/*
2133 * This code may look a bit paranoid, but it's supposed to cooperate with
2134 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2135 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2136 * fanatically on his truly buggy board.
2137 */
2138static inline void __init check_timer(void)
2139{
2140 int apic1, pin1, apic2, pin2;
2141 int no_pin1 = 0;
2142 int vector;
2143 unsigned int ver;
2144 unsigned long flags;
2145
2146 local_irq_save(flags);
2147
2148 ver = apic_read(APIC_LVR);
2149 ver = GET_APIC_VERSION(ver);
2150
2151 /*
2152 * get/set the timer IRQ vector:
2153 */
2154 disable_8259A_irq(0);
2155 vector = assign_irq_vector(0);
2156 set_intr_gate(vector, interrupt[0]);
2157
2158 /*
2159 * As IRQ0 is to be enabled in the 8259A, the virtual
2160 * wire has to be disabled in the local APIC. Also
2161 * timer interrupts need to be acknowledged manually in
2162 * the 8259A for the i82489DX when using the NMI
2163 * watchdog as that APIC treats NMIs as level-triggered.
2164 * The AEOI mode will finish them in the 8259A
2165 * automatically.
2166 */
2167 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2168 init_8259A(1);
2169 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2170
2171 pin1 = find_isa_irq_pin(0, mp_INT);
2172 apic1 = find_isa_irq_apic(0, mp_INT);
2173 pin2 = ioapic_i8259.pin;
2174 apic2 = ioapic_i8259.apic;
2175
2176 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2177 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2178 vector, apic1, pin1, apic2, pin2);
2179
2180 /*
2181 * Some BIOS writers are clueless and report the ExtINTA
2182 * I/O APIC input from the cascaded 8259A as the timer
2183 * interrupt input. So just in case, if only one pin
2184 * was found above, try it both directly and through the
2185 * 8259A.
2186 */
2187 if (pin1 == -1) {
2188 pin1 = pin2;
2189 apic1 = apic2;
2190 no_pin1 = 1;
2191 } else if (pin2 == -1) {
2192 pin2 = pin1;
2193 apic2 = apic1;
2194 }
2195
2196 if (pin1 != -1) {
2197 /*
2198 * Ok, does IRQ0 through the IOAPIC work?
2199 */
2200 if (no_pin1) {
2201 add_pin_to_irq(0, apic1, pin1);
2202 setup_timer_IRQ0_pin(apic1, pin1, vector);
2203 }
2204 unmask_IO_APIC_irq(0);
2205 if (timer_irq_works()) {
2206 if (nmi_watchdog == NMI_IO_APIC) {
2207 setup_nmi();
2208 enable_8259A_irq(0);
2209 }
2210 if (disable_timer_pin_1 > 0)
2211 clear_IO_APIC_pin(0, pin1);
2212 goto out;
2213 }
2214 clear_IO_APIC_pin(apic1, pin1);
2215 if (!no_pin1)
2216 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2217 "8254 timer not connected to IO-APIC\n");
2218
2219 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2220 "(IRQ0) through the 8259A ...\n");
2221 apic_printk(APIC_QUIET, KERN_INFO
2222 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2223 /*
2224 * legacy devices should be connected to IO APIC #0
2225 */
2226 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2227 setup_timer_IRQ0_pin(apic2, pin2, vector);
2228 unmask_IO_APIC_irq(0);
2229 enable_8259A_irq(0);
2230 if (timer_irq_works()) {
2231 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2232 timer_through_8259 = 1;
2233 if (nmi_watchdog == NMI_IO_APIC) {
2234 disable_8259A_irq(0);
2235 setup_nmi();
2236 enable_8259A_irq(0);
2237 }
2238 goto out;
2239 }
2240 /*
2241 * Cleanup, just in case ...
2242 */
2243 disable_8259A_irq(0);
2244 clear_IO_APIC_pin(apic2, pin2);
2245 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2246 }
2247
2248 if (nmi_watchdog == NMI_IO_APIC) {
2249 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2250 "through the IO-APIC - disabling NMI Watchdog!\n");
2251 nmi_watchdog = NMI_NONE;
2252 }
2253 timer_ack = 0;
2254
2255 apic_printk(APIC_QUIET, KERN_INFO
2256 "...trying to set up timer as Virtual Wire IRQ...\n");
2257
2258 lapic_register_intr(0, vector);
2259 apic_write(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
2260 enable_8259A_irq(0);
2261
2262 if (timer_irq_works()) {
2263 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2264 goto out;
2265 }
2266 disable_8259A_irq(0);
2267 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2268 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2269
2270 apic_printk(APIC_QUIET, KERN_INFO
2271 "...trying to set up timer as ExtINT IRQ...\n");
2272
2273 init_8259A(0);
2274 make_8259A_irq(0);
2275 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2276
2277 unlock_ExtINT_logic();
2278
2279 if (timer_irq_works()) {
2280 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2281 goto out;
2282 }
2283 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2284 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2285 "report. Then try booting with the 'noapic' option.\n");
2286out:
2287 local_irq_restore(flags);
2288}
2289
2290/*
2291 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2292 * to devices. However there may be an I/O APIC pin available for
2293 * this interrupt regardless. The pin may be left unconnected, but
2294 * typically it will be reused as an ExtINT cascade interrupt for
2295 * the master 8259A. In the MPS case such a pin will normally be
2296 * reported as an ExtINT interrupt in the MP table. With ACPI
2297 * there is no provision for ExtINT interrupts, and in the absence
2298 * of an override it would be treated as an ordinary ISA I/O APIC
2299 * interrupt, that is edge-triggered and unmasked by default. We
2300 * used to do this, but it caused problems on some systems because
2301 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2302 * the same ExtINT cascade interrupt to drive the local APIC of the
2303 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2304 * the I/O APIC in all cases now. No actual device should request
2305 * it anyway. --macro
2306 */
2307#define PIC_IRQS (1 << PIC_CASCADE_IR)
2308
2309void __init setup_IO_APIC(void)
2310{
2311 int i;
2312
2313 /* Reserve all the system vectors. */
2314 for (i = first_system_vector; i < NR_VECTORS; i++)
2315 set_bit(i, used_vectors);
2316
2317 enable_IO_APIC();
2318
2319 io_apic_irqs = ~PIC_IRQS;
2320
2321 printk("ENABLING IO-APIC IRQs\n");
2322
2323 /*
2324 * Set up IO-APIC IRQ routing.
2325 */
2326 if (!acpi_ioapic)
2327 setup_ioapic_ids_from_mpc();
2328 sync_Arb_IDs();
2329 setup_IO_APIC_irqs();
2330 init_IO_APIC_traps();
2331 check_timer();
2332 if (!acpi_ioapic)
2333 print_IO_APIC();
2334}
2335
2336/*
2337 * Called after all the initialization is done. If we didnt find any
2338 * APIC bugs then we can allow the modify fast path
2339 */
2340
2341static int __init io_apic_bug_finalize(void)
2342{
2343 if (sis_apic_bug == -1)
2344 sis_apic_bug = 0;
2345 return 0;
2346}
2347
2348late_initcall(io_apic_bug_finalize);
2349
2350struct sysfs_ioapic_data {
2351 struct sys_device dev;
2352 struct IO_APIC_route_entry entry[0];
2353};
2354static struct sysfs_ioapic_data *mp_ioapic_data[MAX_IO_APICS];
2355
2356static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2357{
2358 struct IO_APIC_route_entry *entry;
2359 struct sysfs_ioapic_data *data;
2360 int i;
2361
2362 data = container_of(dev, struct sysfs_ioapic_data, dev);
2363 entry = data->entry;
2364 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2365 entry[i] = ioapic_read_entry(dev->id, i);
2366
2367 return 0;
2368}
2369
2370static int ioapic_resume(struct sys_device *dev)
2371{
2372 struct IO_APIC_route_entry *entry;
2373 struct sysfs_ioapic_data *data;
2374 unsigned long flags;
2375 union IO_APIC_reg_00 reg_00;
2376 int i;
2377
2378 data = container_of(dev, struct sysfs_ioapic_data, dev);
2379 entry = data->entry;
2380
2381 spin_lock_irqsave(&ioapic_lock, flags);
2382 reg_00.raw = io_apic_read(dev->id, 0);
2383 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2384 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2385 io_apic_write(dev->id, 0, reg_00.raw);
2386 }
2387 spin_unlock_irqrestore(&ioapic_lock, flags);
2388 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2389 ioapic_write_entry(dev->id, i, entry[i]);
2390
2391 return 0;
2392}
2393
2394static struct sysdev_class ioapic_sysdev_class = {
2395 .name = "ioapic",
2396 .suspend = ioapic_suspend,
2397 .resume = ioapic_resume,
2398};
2399
2400static int __init ioapic_init_sysfs(void)
2401{
2402 struct sys_device *dev;
2403 int i, size, error = 0;
2404
2405 error = sysdev_class_register(&ioapic_sysdev_class);
2406 if (error)
2407 return error;
2408
2409 for (i = 0; i < nr_ioapics; i++) {
2410 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2411 * sizeof(struct IO_APIC_route_entry);
2412 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2413 if (!mp_ioapic_data[i]) {
2414 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2415 continue;
2416 }
2417 dev = &mp_ioapic_data[i]->dev;
2418 dev->id = i;
2419 dev->cls = &ioapic_sysdev_class;
2420 error = sysdev_register(dev);
2421 if (error) {
2422 kfree(mp_ioapic_data[i]);
2423 mp_ioapic_data[i] = NULL;
2424 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2425 continue;
2426 }
2427 }
2428
2429 return 0;
2430}
2431
2432device_initcall(ioapic_init_sysfs);
2433
2434/*
2435 * Dynamic irq allocate and deallocation
2436 */
2437int create_irq(void)
2438{
2439 /* Allocate an unused irq */
2440 int irq, new, vector = 0;
2441 unsigned long flags;
2442
2443 irq = -ENOSPC;
2444 spin_lock_irqsave(&vector_lock, flags);
2445 for (new = (NR_IRQS - 1); new >= 0; new--) {
2446 if (platform_legacy_irq(new))
2447 continue;
2448 if (irq_vector[new] != 0)
2449 continue;
2450 vector = __assign_irq_vector(new);
2451 if (likely(vector > 0))
2452 irq = new;
2453 break;
2454 }
2455 spin_unlock_irqrestore(&vector_lock, flags);
2456
2457 if (irq >= 0) {
2458 set_intr_gate(vector, interrupt[irq]);
2459 dynamic_irq_init(irq);
2460 }
2461 return irq;
2462}
2463
2464void destroy_irq(unsigned int irq)
2465{
2466 unsigned long flags;
2467
2468 dynamic_irq_cleanup(irq);
2469
2470 spin_lock_irqsave(&vector_lock, flags);
2471 clear_bit(irq_vector[irq], used_vectors);
2472 irq_vector[irq] = 0;
2473 spin_unlock_irqrestore(&vector_lock, flags);
2474}
2475
2476/*
2477 * MSI message composition
2478 */
2479#ifdef CONFIG_PCI_MSI
2480static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2481{
2482 int vector;
2483 unsigned dest;
2484
2485 vector = assign_irq_vector(irq);
2486 if (vector >= 0) {
2487 dest = cpu_mask_to_apicid(TARGET_CPUS);
2488
2489 msg->address_hi = MSI_ADDR_BASE_HI;
2490 msg->address_lo =
2491 MSI_ADDR_BASE_LO |
2492 ((INT_DEST_MODE == 0) ?
2493MSI_ADDR_DEST_MODE_PHYSICAL:
2494 MSI_ADDR_DEST_MODE_LOGICAL) |
2495 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2496 MSI_ADDR_REDIRECTION_CPU:
2497 MSI_ADDR_REDIRECTION_LOWPRI) |
2498 MSI_ADDR_DEST_ID(dest);
2499
2500 msg->data =
2501 MSI_DATA_TRIGGER_EDGE |
2502 MSI_DATA_LEVEL_ASSERT |
2503 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2504MSI_DATA_DELIVERY_FIXED:
2505 MSI_DATA_DELIVERY_LOWPRI) |
2506 MSI_DATA_VECTOR(vector);
2507 }
2508 return vector;
2509}
2510
2511#ifdef CONFIG_SMP
2512static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2513{
2514 struct msi_msg msg;
2515 unsigned int dest;
2516 cpumask_t tmp;
2517 int vector;
2518
2519 cpus_and(tmp, mask, cpu_online_map);
2520 if (cpus_empty(tmp))
2521 tmp = TARGET_CPUS;
2522
2523 vector = assign_irq_vector(irq);
2524 if (vector < 0)
2525 return;
2526
2527 dest = cpu_mask_to_apicid(mask);
2528
2529 read_msi_msg(irq, &msg);
2530
2531 msg.data &= ~MSI_DATA_VECTOR_MASK;
2532 msg.data |= MSI_DATA_VECTOR(vector);
2533 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2534 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2535
2536 write_msi_msg(irq, &msg);
2537 irq_desc[irq].affinity = mask;
2538}
2539#endif /* CONFIG_SMP */
2540
2541/*
2542 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2543 * which implement the MSI or MSI-X Capability Structure.
2544 */
2545static struct irq_chip msi_chip = {
2546 .name = "PCI-MSI",
2547 .unmask = unmask_msi_irq,
2548 .mask = mask_msi_irq,
2549 .ack = ack_ioapic_irq,
2550#ifdef CONFIG_SMP
2551 .set_affinity = set_msi_irq_affinity,
2552#endif
2553 .retrigger = ioapic_retrigger_irq,
2554};
2555
2556int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2557{
2558 struct msi_msg msg;
2559 int irq, ret;
2560 irq = create_irq();
2561 if (irq < 0)
2562 return irq;
2563
2564 ret = msi_compose_msg(dev, irq, &msg);
2565 if (ret < 0) {
2566 destroy_irq(irq);
2567 return ret;
2568 }
2569
2570 set_irq_msi(irq, desc);
2571 write_msi_msg(irq, &msg);
2572
2573 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2574 "edge");
2575
2576 return 0;
2577}
2578
2579void arch_teardown_msi_irq(unsigned int irq)
2580{
2581 destroy_irq(irq);
2582}
2583
2584#endif /* CONFIG_PCI_MSI */
2585
2586/*
2587 * Hypertransport interrupt support
2588 */
2589#ifdef CONFIG_HT_IRQ
2590
2591#ifdef CONFIG_SMP
2592
2593static void target_ht_irq(unsigned int irq, unsigned int dest)
2594{
2595 struct ht_irq_msg msg;
2596 fetch_ht_irq_msg(irq, &msg);
2597
2598 msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2599 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2600
2601 msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2602 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2603
2604 write_ht_irq_msg(irq, &msg);
2605}
2606
2607static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2608{
2609 unsigned int dest;
2610 cpumask_t tmp;
2611
2612 cpus_and(tmp, mask, cpu_online_map);
2613 if (cpus_empty(tmp))
2614 tmp = TARGET_CPUS;
2615
2616 cpus_and(mask, tmp, CPU_MASK_ALL);
2617
2618 dest = cpu_mask_to_apicid(mask);
2619
2620 target_ht_irq(irq, dest);
2621 irq_desc[irq].affinity = mask;
2622}
2623#endif
2624
2625static struct irq_chip ht_irq_chip = {
2626 .name = "PCI-HT",
2627 .mask = mask_ht_irq,
2628 .unmask = unmask_ht_irq,
2629 .ack = ack_ioapic_irq,
2630#ifdef CONFIG_SMP
2631 .set_affinity = set_ht_irq_affinity,
2632#endif
2633 .retrigger = ioapic_retrigger_irq,
2634};
2635
2636int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2637{
2638 int vector;
2639
2640 vector = assign_irq_vector(irq);
2641 if (vector >= 0) {
2642 struct ht_irq_msg msg;
2643 unsigned dest;
2644 cpumask_t tmp;
2645
2646 cpus_clear(tmp);
2647 cpu_set(vector >> 8, tmp);
2648 dest = cpu_mask_to_apicid(tmp);
2649
2650 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2651
2652 msg.address_lo =
2653 HT_IRQ_LOW_BASE |
2654 HT_IRQ_LOW_DEST_ID(dest) |
2655 HT_IRQ_LOW_VECTOR(vector) |
2656 ((INT_DEST_MODE == 0) ?
2657 HT_IRQ_LOW_DM_PHYSICAL :
2658 HT_IRQ_LOW_DM_LOGICAL) |
2659 HT_IRQ_LOW_RQEOI_EDGE |
2660 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2661 HT_IRQ_LOW_MT_FIXED :
2662 HT_IRQ_LOW_MT_ARBITRATED) |
2663 HT_IRQ_LOW_IRQ_MASKED;
2664
2665 write_ht_irq_msg(irq, &msg);
2666
2667 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2668 handle_edge_irq, "edge");
2669 }
2670 return vector;
2671}
2672#endif /* CONFIG_HT_IRQ */
2673
2674/* --------------------------------------------------------------------------
2675 ACPI-based IOAPIC Configuration
2676 -------------------------------------------------------------------------- */
2677
2678#ifdef CONFIG_ACPI
2679
2680int __init io_apic_get_unique_id(int ioapic, int apic_id)
2681{
2682 union IO_APIC_reg_00 reg_00;
2683 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2684 physid_mask_t tmp;
2685 unsigned long flags;
2686 int i = 0;
2687
2688 /*
2689 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2690 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2691 * supports up to 16 on one shared APIC bus.
2692 *
2693 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2694 * advantage of new APIC bus architecture.
2695 */
2696
2697 if (physids_empty(apic_id_map))
2698 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2699
2700 spin_lock_irqsave(&ioapic_lock, flags);
2701 reg_00.raw = io_apic_read(ioapic, 0);
2702 spin_unlock_irqrestore(&ioapic_lock, flags);
2703
2704 if (apic_id >= get_physical_broadcast()) {
2705 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2706 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2707 apic_id = reg_00.bits.ID;
2708 }
2709
2710 /*
2711 * Every APIC in a system must have a unique ID or we get lots of nice
2712 * 'stuck on smp_invalidate_needed IPI wait' messages.
2713 */
2714 if (check_apicid_used(apic_id_map, apic_id)) {
2715
2716 for (i = 0; i < get_physical_broadcast(); i++) {
2717 if (!check_apicid_used(apic_id_map, i))
2718 break;
2719 }
2720
2721 if (i == get_physical_broadcast())
2722 panic("Max apic_id exceeded!\n");
2723
2724 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2725 "trying %d\n", ioapic, apic_id, i);
2726
2727 apic_id = i;
2728 }
2729
2730 tmp = apicid_to_cpu_present(apic_id);
2731 physids_or(apic_id_map, apic_id_map, tmp);
2732
2733 if (reg_00.bits.ID != apic_id) {
2734 reg_00.bits.ID = apic_id;
2735
2736 spin_lock_irqsave(&ioapic_lock, flags);
2737 io_apic_write(ioapic, 0, reg_00.raw);
2738 reg_00.raw = io_apic_read(ioapic, 0);
2739 spin_unlock_irqrestore(&ioapic_lock, flags);
2740
2741 /* Sanity check */
2742 if (reg_00.bits.ID != apic_id) {
2743 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2744 return -1;
2745 }
2746 }
2747
2748 apic_printk(APIC_VERBOSE, KERN_INFO
2749 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2750
2751 return apic_id;
2752}
2753
2754
2755int __init io_apic_get_version(int ioapic)
2756{
2757 union IO_APIC_reg_01 reg_01;
2758 unsigned long flags;
2759
2760 spin_lock_irqsave(&ioapic_lock, flags);
2761 reg_01.raw = io_apic_read(ioapic, 1);
2762 spin_unlock_irqrestore(&ioapic_lock, flags);
2763
2764 return reg_01.bits.version;
2765}
2766
2767
2768int __init io_apic_get_redir_entries(int ioapic)
2769{
2770 union IO_APIC_reg_01 reg_01;
2771 unsigned long flags;
2772
2773 spin_lock_irqsave(&ioapic_lock, flags);
2774 reg_01.raw = io_apic_read(ioapic, 1);
2775 spin_unlock_irqrestore(&ioapic_lock, flags);
2776
2777 return reg_01.bits.entries;
2778}
2779
2780
2781int io_apic_set_pci_routing(int ioapic, int pin, int irq, int edge_level, int active_high_low)
2782{
2783 struct IO_APIC_route_entry entry;
2784
2785 if (!IO_APIC_IRQ(irq)) {
2786 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2787 ioapic);
2788 return -EINVAL;
2789 }
2790
2791 /*
2792 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2793 * Note that we mask (disable) IRQs now -- these get enabled when the
2794 * corresponding device driver registers for this IRQ.
2795 */
2796
2797 memset(&entry, 0, sizeof(entry));
2798
2799 entry.delivery_mode = INT_DELIVERY_MODE;
2800 entry.dest_mode = INT_DEST_MODE;
2801 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2802 entry.trigger = edge_level;
2803 entry.polarity = active_high_low;
2804 entry.mask = 1;
2805
2806 /*
2807 * IRQs < 16 are already in the irq_2_pin[] map
2808 */
2809 if (irq >= 16)
2810 add_pin_to_irq(irq, ioapic, pin);
2811
2812 entry.vector = assign_irq_vector(irq);
2813
2814 apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2815 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2816 mp_ioapics[ioapic].mp_apicid, pin, entry.vector, irq,
2817 edge_level, active_high_low);
2818
2819 ioapic_register_intr(irq, entry.vector, edge_level);
2820
2821 if (!ioapic && (irq < 16))
2822 disable_8259A_irq(irq);
2823
2824 ioapic_write_entry(ioapic, pin, entry);
2825
2826 return 0;
2827}
2828
2829int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2830{
2831 int i;
2832
2833 if (skip_ioapic_setup)
2834 return -1;
2835
2836 for (i = 0; i < mp_irq_entries; i++)
2837 if (mp_irqs[i].mp_irqtype == mp_INT &&
2838 mp_irqs[i].mp_srcbusirq == bus_irq)
2839 break;
2840 if (i >= mp_irq_entries)
2841 return -1;
2842
2843 *trigger = irq_trigger(i);
2844 *polarity = irq_polarity(i);
2845 return 0;
2846}
2847
2848#endif /* CONFIG_ACPI */
2849
2850static int __init parse_disable_timer_pin_1(char *arg)
2851{
2852 disable_timer_pin_1 = 1;
2853 return 0;
2854}
2855early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2856
2857static int __init parse_enable_timer_pin_1(char *arg)
2858{
2859 disable_timer_pin_1 = -1;
2860 return 0;
2861}
2862early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2863
2864static int __init parse_noapic(char *arg)
2865{
2866 /* disable IO-APIC */
2867 disable_ioapic_setup();
2868 return 0;
2869}
2870early_param("noapic", parse_noapic);
2871
2872void __init ioapic_init_mappings(void)
2873{
2874 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2875 int i;
2876
2877 for (i = 0; i < nr_ioapics; i++) {
2878 if (smp_found_config) {
2879 ioapic_phys = mp_ioapics[i].mp_apicaddr;
2880 if (!ioapic_phys) {
2881 printk(KERN_ERR
2882 "WARNING: bogus zero IO-APIC "
2883 "address found in MPTABLE, "
2884 "disabling IO/APIC support!\n");
2885 smp_found_config = 0;
2886 skip_ioapic_setup = 1;
2887 goto fake_ioapic_page;
2888 }
2889 } else {
2890fake_ioapic_page:
2891 ioapic_phys = (unsigned long)
2892 alloc_bootmem_pages(PAGE_SIZE);
2893 ioapic_phys = __pa(ioapic_phys);
2894 }
2895 set_fixmap_nocache(idx, ioapic_phys);
2896 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
2897 __fix_to_virt(idx), ioapic_phys);
2898 idx++;
2899 }
2900}
2901
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 12:24:44 -0500