diff options
Diffstat (limited to 'arch/x86/kernel/cpu/mcheck/mce.c')
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index a04806e01a8..07139a0578e 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c | |||
@@ -267,11 +267,11 @@ static int msr_to_offset(u32 msr) | |||
267 | unsigned bank = __get_cpu_var(injectm.bank); | 267 | unsigned bank = __get_cpu_var(injectm.bank); |
268 | if (msr == rip_msr) | 268 | if (msr == rip_msr) |
269 | return offsetof(struct mce, ip); | 269 | return offsetof(struct mce, ip); |
270 | if (msr == MSR_IA32_MC0_STATUS + bank*4) | 270 | if (msr == MSR_IA32_MCx_STATUS(bank)) |
271 | return offsetof(struct mce, status); | 271 | return offsetof(struct mce, status); |
272 | if (msr == MSR_IA32_MC0_ADDR + bank*4) | 272 | if (msr == MSR_IA32_MCx_ADDR(bank)) |
273 | return offsetof(struct mce, addr); | 273 | return offsetof(struct mce, addr); |
274 | if (msr == MSR_IA32_MC0_MISC + bank*4) | 274 | if (msr == MSR_IA32_MCx_MISC(bank)) |
275 | return offsetof(struct mce, misc); | 275 | return offsetof(struct mce, misc); |
276 | if (msr == MSR_IA32_MCG_STATUS) | 276 | if (msr == MSR_IA32_MCG_STATUS) |
277 | return offsetof(struct mce, mcgstatus); | 277 | return offsetof(struct mce, mcgstatus); |
@@ -485,7 +485,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) | |||
485 | m.tsc = 0; | 485 | m.tsc = 0; |
486 | 486 | ||
487 | barrier(); | 487 | barrier(); |
488 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); | 488 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
489 | if (!(m.status & MCI_STATUS_VAL)) | 489 | if (!(m.status & MCI_STATUS_VAL)) |
490 | continue; | 490 | continue; |
491 | 491 | ||
@@ -500,9 +500,9 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) | |||
500 | continue; | 500 | continue; |
501 | 501 | ||
502 | if (m.status & MCI_STATUS_MISCV) | 502 | if (m.status & MCI_STATUS_MISCV) |
503 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); | 503 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
504 | if (m.status & MCI_STATUS_ADDRV) | 504 | if (m.status & MCI_STATUS_ADDRV) |
505 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); | 505 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
506 | 506 | ||
507 | if (!(flags & MCP_TIMESTAMP)) | 507 | if (!(flags & MCP_TIMESTAMP)) |
508 | m.tsc = 0; | 508 | m.tsc = 0; |
@@ -518,7 +518,7 @@ void machine_check_poll(enum mcp_flags flags, mce_banks_t *b) | |||
518 | /* | 518 | /* |
519 | * Clear state for this bank. | 519 | * Clear state for this bank. |
520 | */ | 520 | */ |
521 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | 521 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
522 | } | 522 | } |
523 | 523 | ||
524 | /* | 524 | /* |
@@ -539,7 +539,7 @@ static int mce_no_way_out(struct mce *m, char **msg) | |||
539 | int i; | 539 | int i; |
540 | 540 | ||
541 | for (i = 0; i < banks; i++) { | 541 | for (i = 0; i < banks; i++) { |
542 | m->status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); | 542 | m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
543 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) | 543 | if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY) |
544 | return 1; | 544 | return 1; |
545 | } | 545 | } |
@@ -823,7 +823,7 @@ static void mce_clear_state(unsigned long *toclear) | |||
823 | 823 | ||
824 | for (i = 0; i < banks; i++) { | 824 | for (i = 0; i < banks; i++) { |
825 | if (test_bit(i, toclear)) | 825 | if (test_bit(i, toclear)) |
826 | mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | 826 | mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
827 | } | 827 | } |
828 | } | 828 | } |
829 | 829 | ||
@@ -904,7 +904,7 @@ void do_machine_check(struct pt_regs *regs, long error_code) | |||
904 | m.addr = 0; | 904 | m.addr = 0; |
905 | m.bank = i; | 905 | m.bank = i; |
906 | 906 | ||
907 | m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4); | 907 | m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i)); |
908 | if ((m.status & MCI_STATUS_VAL) == 0) | 908 | if ((m.status & MCI_STATUS_VAL) == 0) |
909 | continue; | 909 | continue; |
910 | 910 | ||
@@ -945,9 +945,9 @@ void do_machine_check(struct pt_regs *regs, long error_code) | |||
945 | kill_it = 1; | 945 | kill_it = 1; |
946 | 946 | ||
947 | if (m.status & MCI_STATUS_MISCV) | 947 | if (m.status & MCI_STATUS_MISCV) |
948 | m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4); | 948 | m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i)); |
949 | if (m.status & MCI_STATUS_ADDRV) | 949 | if (m.status & MCI_STATUS_ADDRV) |
950 | m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4); | 950 | m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i)); |
951 | 951 | ||
952 | /* | 952 | /* |
953 | * Action optional error. Queue address for later processing. | 953 | * Action optional error. Queue address for later processing. |
@@ -1216,8 +1216,8 @@ static void mce_init(void) | |||
1216 | struct mce_bank *b = &mce_banks[i]; | 1216 | struct mce_bank *b = &mce_banks[i]; |
1217 | if (!b->init) | 1217 | if (!b->init) |
1218 | continue; | 1218 | continue; |
1219 | wrmsrl(MSR_IA32_MC0_CTL+4*i, b->ctl); | 1219 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1220 | wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0); | 1220 | wrmsrl(MSR_IA32_MCx_STATUS(i), 0); |
1221 | } | 1221 | } |
1222 | } | 1222 | } |
1223 | 1223 | ||
@@ -1589,7 +1589,7 @@ static int mce_disable(void) | |||
1589 | for (i = 0; i < banks; i++) { | 1589 | for (i = 0; i < banks; i++) { |
1590 | struct mce_bank *b = &mce_banks[i]; | 1590 | struct mce_bank *b = &mce_banks[i]; |
1591 | if (b->init) | 1591 | if (b->init) |
1592 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | 1592 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
1593 | } | 1593 | } |
1594 | return 0; | 1594 | return 0; |
1595 | } | 1595 | } |
@@ -1876,7 +1876,7 @@ static void mce_disable_cpu(void *h) | |||
1876 | for (i = 0; i < banks; i++) { | 1876 | for (i = 0; i < banks; i++) { |
1877 | struct mce_bank *b = &mce_banks[i]; | 1877 | struct mce_bank *b = &mce_banks[i]; |
1878 | if (b->init) | 1878 | if (b->init) |
1879 | wrmsrl(MSR_IA32_MC0_CTL + i*4, 0); | 1879 | wrmsrl(MSR_IA32_MCx_CTL(i), 0); |
1880 | } | 1880 | } |
1881 | } | 1881 | } |
1882 | 1882 | ||
@@ -1893,7 +1893,7 @@ static void mce_reenable_cpu(void *h) | |||
1893 | for (i = 0; i < banks; i++) { | 1893 | for (i = 0; i < banks; i++) { |
1894 | struct mce_bank *b = &mce_banks[i]; | 1894 | struct mce_bank *b = &mce_banks[i]; |
1895 | if (b->init) | 1895 | if (b->init) |
1896 | wrmsrl(MSR_IA32_MC0_CTL + i*4, b->ctl); | 1896 | wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl); |
1897 | } | 1897 | } |
1898 | } | 1898 | } |
1899 | 1899 | ||