1 files changed, 359 insertions, 189 deletions
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 18514ed2610..8f1e31db2ad 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1,13 +1,22 @@
 #include <linux/init.h>
 #include <linux/bitops.h>
 #include <linux/mm.h>
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/apic.h>
+#ifdef CONFIG_X86_64
+# include <asm/numa_64.h>
+# include <asm/mmconfig.h>
+# include <asm/cacheflush.h>
+#endif
 #include <mach_apic.h>
 #include "cpu.h"
+#ifdef CONFIG_X86_32
 /*
 *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
 *      misexecution of code under Linux. Owners of such processors should
@@ -24,26 +33,273 @@
 extern void vide(void);
 __asm__(".align 4\nvide: ret");
-static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
+static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
 {
-        if (cpuid_eax(0x80000000) >= 0x80000007) {
+/*
-                c->x86_power = cpuid_edx(0x80000007);
+ * General Systems BIOSen alias the cpu frequency registers
-                if (c->x86_power & (1<<8))
+ * of the Elan at 0x000df000. Unfortuantly, one of the Linux
-                        set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+ * drivers subsequently pokes it, and changes the CPU speed.
+ * Workaround : Remove the unneeded alias.
+ */
+#define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
+#define CBAR_ENB        (0x80000000)
+#define CBAR_KEY        (0X000000CB)
+        if (c->x86_model == 9 || c->x86_model == 10) {
+                if (inl (CBAR) & CBAR_ENB)
+                        outl (0 | CBAR_KEY, CBAR);
        }
-        /*  Set MTRR capability flag if appropriate */
-        if (c->x86_model == 13 || c->x86_model == 9 ||
-           (c->x86_model == 8 && c->x86_mask >= 8))
-                set_cpu_cap(c, X86_FEATURE_K6_MTRR);
 }
-static void __cpuinit init_amd(struct cpuinfo_x86 *c)
+static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
 {
        u32 l, h;
        int mbytes = num_physpages >> (20-PAGE_SHIFT);
-        int r;
+        if (c->x86_model < 6) {
+                /* Based on AMD doc 20734R - June 2000 */
+                if (c->x86_model == 0) {
+                        clear_cpu_cap(c, X86_FEATURE_APIC);
+                        set_cpu_cap(c, X86_FEATURE_PGE);
+                }
+                return;
+        }
+        if (c->x86_model == 6 && c->x86_mask == 1) {
+                const int K6_BUG_LOOP = 1000000;
+                int n;
+                void (*f_vide)(void);
+                unsigned long d, d2;
+                printk(KERN_INFO "AMD K6 stepping B detected - ");
+                /*
+                 * It looks like AMD fixed the 2.6.2 bug and improved indirect
+                 * calls at the same time.
+                 */
+                n = K6_BUG_LOOP;
+                f_vide = vide;
+                rdtscl(d);
+                while (n--)
+                        f_vide();
+                rdtscl(d2);
+                d = d2-d;
+                if (d > 20*K6_BUG_LOOP)
+                        printk("system stability may be impaired when more than 32 MB are used.\n");
+                else
+                        printk("probably OK (after B9730xxxx).\n");
+                printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
+        }
+        /* K6 with old style WHCR */
+        if (c->x86_model < 8 ||
+           (c->x86_model == 8 && c->x86_mask < 8)) {
+                /* We can only write allocate on the low 508Mb */
+                if (mbytes > 508)
+                        mbytes = 508;
+                rdmsr(MSR_K6_WHCR, l, h);
+                if ((l&0x0000FFFF) == 0) {
+                        unsigned long flags;
+                        l = (1<<0)|((mbytes/4)<<1);
+                        local_irq_save(flags);
+                        wbinvd();
+                        wrmsr(MSR_K6_WHCR, l, h);
+                        local_irq_restore(flags);
+                        printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
+                                mbytes);
+                }
+                return;
+        }
+        if ((c->x86_model == 8 && c->x86_mask > 7) ||
+             c->x86_model == 9 || c->x86_model == 13) {
+                /* The more serious chips .. */
+                if (mbytes > 4092)
+                        mbytes = 4092;
+                rdmsr(MSR_K6_WHCR, l, h);
+                if ((l&0xFFFF0000) == 0) {
+                        unsigned long flags;
+                        l = ((mbytes>>2)<<22)|(1<<16);
+                        local_irq_save(flags);
+                        wbinvd();
+                        wrmsr(MSR_K6_WHCR, l, h);
+                        local_irq_restore(flags);
+                        printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
+                                mbytes);
+                }
+                return;
+        }
+        if (c->x86_model == 10) {
+                /* AMD Geode LX is model 10 */
+                /* placeholder for any needed mods */
+                return;
+        }
+}
+static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
+{
+        u32 l, h;
+        /*
+         * Bit 15 of Athlon specific MSR 15, needs to be 0
+         * to enable SSE on Palomino/Morgan/Barton CPU's.
+         * If the BIOS didn't enable it already, enable it here.
+         */
+        if (c->x86_model >= 6 && c->x86_model <= 10) {
+                if (!cpu_has(c, X86_FEATURE_XMM)) {
+                        printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
+                        rdmsr(MSR_K7_HWCR, l, h);
+                        l &= ~0x00008000;
+                        wrmsr(MSR_K7_HWCR, l, h);
+                        set_cpu_cap(c, X86_FEATURE_XMM);
+                }
+        }
+        /*
+         * It's been determined by AMD that Athlons since model 8 stepping 1
+         * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
+         * As per AMD technical note 27212 0.2
+         */
+        if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
+                rdmsr(MSR_K7_CLK_CTL, l, h);
+                if ((l & 0xfff00000) != 0x20000000) {
+                        printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
+                                ((l & 0x000fffff)|0x20000000));
+                        wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
+                }
+        }
+        set_cpu_cap(c, X86_FEATURE_K7);
+}
+#endif
+#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
+static int __cpuinit nearby_node(int apicid)
+{
+        int i, node;
+        for (i = apicid - 1; i >= 0; i--) {
+                node = apicid_to_node[i];
+                if (node != NUMA_NO_NODE && node_online(node))
+                        return node;
+        }
+        for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
+                node = apicid_to_node[i];
+                if (node != NUMA_NO_NODE && node_online(node))
+                        return node;
+        }
+        return first_node(node_online_map); /* Shouldn't happen */
+}
+#endif
+/*
+ * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
+ * Assumes number of cores is a power of two.
+ */
+static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_X86_HT
+        unsigned bits;
+        bits = c->x86_coreid_bits;
+        /* Low order bits define the core id (index of core in socket) */
+        c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
+        /* Convert the initial APIC ID into the socket ID */
+        c->phys_proc_id = c->initial_apicid >> bits;
+#endif
+}
+static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
+{
+#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
+        int cpu = smp_processor_id();
+        int node;
+        unsigned apicid = hard_smp_processor_id();
+        node = c->phys_proc_id;
+        if (apicid_to_node[apicid] != NUMA_NO_NODE)
+                node = apicid_to_node[apicid];
+        if (!node_online(node)) {
+                /* Two possibilities here:
+                   - The CPU is missing memory and no node was created.
+                   In that case try picking one from a nearby CPU
+                   - The APIC IDs differ from the HyperTransport node IDs
+                   which the K8 northbridge parsing fills in.
+                   Assume they are all increased by a constant offset,
+                   but in the same order as the HT nodeids.
+                   If that doesn't result in a usable node fall back to the
+                   path for the previous case.  */
+                int ht_nodeid = c->initial_apicid;
+                if (ht_nodeid >= 0 &&
+                    apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
+                        node = apicid_to_node[ht_nodeid];
+                /* Pick a nearby node */
+                if (!node_online(node))
+                        node = nearby_node(apicid);
+        }
+        numa_set_node(cpu, node);
+        printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
+#endif
+}
+static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_X86_HT
+        unsigned bits, ecx;
+        /* Multi core CPU? */
+        if (c->extended_cpuid_level < 0x80000008)
+                return;
+        ecx = cpuid_ecx(0x80000008);
+        c->x86_max_cores = (ecx & 0xff) + 1;
+        /* CPU telling us the core id bits shift? */
+        bits = (ecx >> 12) & 0xF;
+        /* Otherwise recompute */
+        if (bits == 0) {
+                while ((1 << bits) < c->x86_max_cores)
+                        bits++;
+        }
+        c->x86_coreid_bits = bits;
+#endif
+}
+static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
+{
+        early_init_amd_mc(c);
+        /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
+        if (c->x86_power & (1<<8))
+                set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
+#ifdef CONFIG_X86_64
+        set_cpu_cap(c, X86_FEATURE_SYSCALL32);
+#else
+        /*  Set MTRR capability flag if appropriate */
+        if (c->x86 == 5)
+                if (c->x86_model == 13 || c->x86_model == 9 ||
+                    (c->x86_model == 8 && c->x86_mask >= 8))
+                        set_cpu_cap(c, X86_FEATURE_K6_MTRR);
+#endif
+}
+static void __cpuinit init_amd(struct cpuinfo_x86 *c)
+{
 #ifdef CONFIG_SMP
        unsigned long long value;
@@ -54,7 +310,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         * Errata 63 for SH-B3 steppings
         * Errata 122 for all steppings (F+ have it disabled by default)
         */
-        if (c->x86 == 15) {
+        if (c->x86 == 0xf) {
                rdmsrl(MSR_K7_HWCR, value);
                value |= 1 << 6;
                wrmsrl(MSR_K7_HWCR, value);
@@ -64,209 +320,119 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
        early_init_amd(c);
        /*
-         *      FIXME: We should handle the K5 here. Set up the write
-         *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
-         *      no bus pipeline)
-         */
-        /*
         * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
         * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
         */
        clear_cpu_cap(c, 0*32+31);
-        r = get_model_name(c);
+#ifdef CONFIG_X86_64
+        /* On C+ stepping K8 rep microcode works well for copy/memset */
+        if (c->x86 == 0xf) {
+                u32 level;
-        switch (c->x86) {
+                level = cpuid_eax(1);
-        case 4:
+                if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
-                /*
+                        set_cpu_cap(c, X86_FEATURE_REP_GOOD);
-                 * General Systems BIOSen alias the cpu frequency registers
-                 * of the Elan at 0x000df000. Unfortuantly, one of the Linux
-                 * drivers subsequently pokes it, and changes the CPU speed.
-                 * Workaround : Remove the unneeded alias.
-                 */
-#define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
-#define CBAR_ENB        (0x80000000)
-#define CBAR_KEY        (0X000000CB)
-                        if (c->x86_model == 9 || c->x86_model == 10) {
-                                if (inl (CBAR) & CBAR_ENB)
-                                        outl (0 | CBAR_KEY, CBAR);
-                        }
-                        break;
-        case 5:
-                        if (c->x86_model < 6) {
-                                /* Based on AMD doc 20734R - June 2000 */
-                                if (c->x86_model == 0) {
-                                        clear_cpu_cap(c, X86_FEATURE_APIC);
-                                        set_cpu_cap(c, X86_FEATURE_PGE);
-                                }
-                                break;
-                        }
-                        if (c->x86_model == 6 && c->x86_mask == 1) {
-                                const int K6_BUG_LOOP = 1000000;
-                                int n;
-                                void (*f_vide)(void);
-                                unsigned long d, d2;
-                                printk(KERN_INFO "AMD K6 stepping B detected - ");
-                                /*
-                                 * It looks like AMD fixed the 2.6.2 bug and improved indirect
-                                 * calls at the same time.
-                                 */
-                                n = K6_BUG_LOOP;
-                                f_vide = vide;
-                                rdtscl(d);
-                                while (n--)
-                                        f_vide();
-                                rdtscl(d2);
-                                d = d2-d;
-                                if (d > 20*K6_BUG_LOOP)
-                                        printk("system stability may be impaired when more than 32 MB are used.\n");
-                                else
-                                        printk("probably OK (after B9730xxxx).\n");
-                                printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
-                        }
-                        /* K6 with old style WHCR */
-                        if (c->x86_model < 8 ||
-                           (c->x86_model == 8 && c->x86_mask < 8)) {
-                                /* We can only write allocate on the low 508Mb */
-                                if (mbytes > 508)
-                                        mbytes = 508;
-                                rdmsr(MSR_K6_WHCR, l, h);
-                                if ((l&0x0000FFFF) == 0) {
-                                        unsigned long flags;
-                                        l = (1<<0)|((mbytes/4)<<1);
-                                        local_irq_save(flags);
-                                        wbinvd();
-                                        wrmsr(MSR_K6_WHCR, l, h);
-                                        local_irq_restore(flags);
-                                        printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
-                                                mbytes);
-                                }
-                                break;
-                        }
-                        if ((c->x86_model == 8 && c->x86_mask > 7) ||
-                             c->x86_model == 9 || c->x86_model == 13) {
-                                /* The more serious chips .. */
-                                if (mbytes > 4092)
-                                        mbytes = 4092;
-                                rdmsr(MSR_K6_WHCR, l, h);
-                                if ((l&0xFFFF0000) == 0) {
-                                        unsigned long flags;
-                                        l = ((mbytes>>2)<<22)|(1<<16);
-                                        local_irq_save(flags);
-                                        wbinvd();
-                                        wrmsr(MSR_K6_WHCR, l, h);
-                                        local_irq_restore(flags);
-                                        printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
-                                                mbytes);
-                                }
-                                break;
-                        }
-                        if (c->x86_model == 10) {
-                                /* AMD Geode LX is model 10 */
-                                /* placeholder for any needed mods */
-                                break;
-                        }
-                        break;
-        case 6: /* An Athlon/Duron */
-                        /*
-                         * Bit 15 of Athlon specific MSR 15, needs to be 0
-                         * to enable SSE on Palomino/Morgan/Barton CPU's.
-                         * If the BIOS didn't enable it already, enable it here.
-                         */
-                        if (c->x86_model >= 6 && c->x86_model <= 10) {
-                                if (!cpu_has(c, X86_FEATURE_XMM)) {
-                                        printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
-                                        rdmsr(MSR_K7_HWCR, l, h);
-                                        l &= ~0x00008000;
-                                        wrmsr(MSR_K7_HWCR, l, h);
-                                        set_cpu_cap(c, X86_FEATURE_XMM);
-                                }
-                        }
-                        /*
-                         * It's been determined by AMD that Athlons since model 8 stepping 1
-                         * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
-                         * As per AMD technical note 27212 0.2
-                         */
-                        if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
-                                rdmsr(MSR_K7_CLK_CTL, l, h);
-                                if ((l & 0xfff00000) != 0x20000000) {
-                                        printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
-                                                ((l & 0x000fffff)|0x20000000));
-                                        wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
-                                }
-                        }
-                        break;
        }
+        if (c->x86 == 0x10 || c->x86 == 0x11)
+                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+#else
+        /*
+         *      FIXME: We should handle the K5 here. Set up the write
+         *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
+         *      no bus pipeline)
+         */
        switch (c->x86) {
-        case 15:
+        case 4:
-        /* Use K8 tuning for Fam10h and Fam11h */
+                init_amd_k5(c);
-        case 0x10:
-        case 0x11:
-                set_cpu_cap(c, X86_FEATURE_K8);
                break;
-        case 6:
+        case 5:
-                set_cpu_cap(c, X86_FEATURE_K7);
+                init_amd_k6(c);
+                break;
+        case 6: /* An Athlon/Duron */
+                init_amd_k7(c);
                break;
        }
+        /* K6s reports MCEs but don't actually have all the MSRs */
+        if (c->x86 < 6)
+                clear_cpu_cap(c, X86_FEATURE_MCE);
+#endif
+        /* Enable workaround for FXSAVE leak */
        if (c->x86 >= 6)
                set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
-        display_cacheinfo(c);
+        if (!c->x86_model_id[0]) {
+                switch (c->x86) {
-        if (cpuid_eax(0x80000000) >= 0x80000008)
+                case 0xf:
-                c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
+                        /* Should distinguish Models here, but this is only
+                           a fallback anyways. */
+                        strcpy(c->x86_model_id, "Hammer");
+                        break;
+                }
+        }
-#ifdef CONFIG_X86_HT
+        display_cacheinfo(c);
-        /*
-         * On a AMD multi core setup the lower bits of the APIC id
-         * distinguish the cores.
-         */
-        if (c->x86_max_cores > 1) {
-                int cpu = smp_processor_id();
-                unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
-                if (bits == 0) {
+        /* Multi core CPU? */
-                        while ((1 << bits) < c->x86_max_cores)
+        if (c->extended_cpuid_level >= 0x80000008) {
-                                bits++;
+                amd_detect_cmp(c);
-                }
+                srat_detect_node(c);
-                c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
-                c->phys_proc_id >>= bits;
-                printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
-                       cpu, c->x86_max_cores, c->cpu_core_id);
        }
+#ifdef CONFIG_X86_32
+        detect_ht(c);
 #endif
-        if (cpuid_eax(0x80000000) >= 0x80000006) {
+        if (c->extended_cpuid_level >= 0x80000006) {
-                if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
+                if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
                        num_cache_leaves = 4;
                else
                        num_cache_leaves = 3;
        }
-        /* K6s reports MCEs but don't actually have all the MSRs */
+        if (c->x86 >= 0xf && c->x86 <= 0x11)
-        if (c->x86 < 6)
+                set_cpu_cap(c, X86_FEATURE_K8);
-                clear_cpu_cap(c, X86_FEATURE_MCE);
-        if (cpu_has_xmm2)
+        if (cpu_has_xmm2) {
+                /* MFENCE stops RDTSC speculation */
                set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
+        }
+#ifdef CONFIG_X86_64
+        if (c->x86 == 0x10) {
+                /* do this for boot cpu */
+                if (c == &boot_cpu_data)
+                        check_enable_amd_mmconf_dmi();
+                fam10h_check_enable_mmcfg();
+        }
+        if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
+                unsigned long long tseg;
+                /*
+                 * Split up direct mapping around the TSEG SMM area.
+                 * Don't do it for gbpages because there seems very little
+                 * benefit in doing so.
+                 */
+                if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
+                    printk(KERN_DEBUG "tseg: %010llx\n", tseg);
+                    if ((tseg>>PMD_SHIFT) <
+                                (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
+                        ((tseg>>PMD_SHIFT) <
+                                (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
+                         (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
+                        set_memory_4k((unsigned long)__va(tseg), 1);
+                }
+        }
+#endif
 }
+#ifdef CONFIG_X86_32
 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 {
        /* AMD errata T13 (order #21922) */
@@ -279,10 +445,12 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int
        }
        return size;
 }
+#endif
 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
        .c_vendor       = "AMD",
        .c_ident        = { "AuthenticAMD" },
+#ifdef CONFIG_X86_32
        .c_models = {
                { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
                  {
@@ -295,9 +463,11 @@ static struct cpu_dev amd_cpu_dev __cpuinitdata = {
                  }
                },
        },
+        .c_size_cache   = amd_size_cache,
+#endif
        .c_early_init   = early_init_amd,
        .c_init         = init_amd,
-        .c_size_cache   = amd_size_cache,
+        .c_x86_vendor   = X86_VENDOR_AMD,
 };
-cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);
+cpu_dev_register(amd_cpu_dev);

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 18514ed2610..8f1e31db2ad 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c
@@ -1,13 +1,22 @@
1	#include <linux/init.h>	1	#include <linux/init.h>
2	#include <linux/bitops.h>	2	#include <linux/bitops.h>
3	#include <linux/mm.h>	3	#include <linux/mm.h>
		4
4	#include <asm/io.h>	5	#include <asm/io.h>
5	#include <asm/processor.h>	6	#include <asm/processor.h>
6	#include <asm/apic.h>	7	#include <asm/apic.h>
7		8
		9	#ifdef CONFIG_X86_64
		10	# include <asm/numa_64.h>
		11	# include <asm/mmconfig.h>
		12	# include <asm/cacheflush.h>
		13	#endif
		14
8	#include <mach_apic.h>	15	#include <mach_apic.h>
		16
9	#include "cpu.h"	17	#include "cpu.h"
10		18
		19	#ifdef CONFIG_X86_32
11	/*	20	/*
12	* B step AMD K6 before B 9730xxxx have hardware bugs that can cause	21	* B step AMD K6 before B 9730xxxx have hardware bugs that can cause
13	* misexecution of code under Linux. Owners of such processors should	22	* misexecution of code under Linux. Owners of such processors should
@@ -24,26 +33,273 @@
24	extern void vide(void);	33	extern void vide(void);
25	__asm__(".align 4\nvide: ret");	34	__asm__(".align 4\nvide: ret");
26		35
27	static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)	36	static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
28	{	37	{
29	if (cpuid_eax(0x80000000) >= 0x80000007) {	38	/*
30	c->x86_power = cpuid_edx(0x80000007);	39	* General Systems BIOSen alias the cpu frequency registers
31	if (c->x86_power & (1<<8))	40	* of the Elan at 0x000df000. Unfortuantly, one of the Linux
32	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);	41	* drivers subsequently pokes it, and changes the CPU speed.
		42	* Workaround : Remove the unneeded alias.
		43	*/
		44	#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
		45	#define CBAR_ENB (0x80000000)
		46	#define CBAR_KEY (0X000000CB)
		47	if (c->x86_model == 9 \|\| c->x86_model == 10) {
		48	if (inl (CBAR) & CBAR_ENB)
		49	outl (0 \| CBAR_KEY, CBAR);
33	}	50	}
34
35	/* Set MTRR capability flag if appropriate */
36	if (c->x86_model == 13 \|\| c->x86_model == 9 \|\|
37	(c->x86_model == 8 && c->x86_mask >= 8))
38	set_cpu_cap(c, X86_FEATURE_K6_MTRR);
39	}	51	}
40		52
41	static void __cpuinit init_amd(struct cpuinfo_x86 *c)	53
		54	static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
42	{	55	{
43	u32 l, h;	56	u32 l, h;
44	int mbytes = num_physpages >> (20-PAGE_SHIFT);	57	int mbytes = num_physpages >> (20-PAGE_SHIFT);
45	int r;
46		58
		59	if (c->x86_model < 6) {
		60	/* Based on AMD doc 20734R - June 2000 */
		61	if (c->x86_model == 0) {
		62	clear_cpu_cap(c, X86_FEATURE_APIC);
		63	set_cpu_cap(c, X86_FEATURE_PGE);
		64	}
		65	return;
		66	}
		67
		68	if (c->x86_model == 6 && c->x86_mask == 1) {
		69	const int K6_BUG_LOOP = 1000000;
		70	int n;
		71	void (*f_vide)(void);
		72	unsigned long d, d2;
		73
		74	printk(KERN_INFO "AMD K6 stepping B detected - ");
		75
		76	/*
		77	* It looks like AMD fixed the 2.6.2 bug and improved indirect
		78	* calls at the same time.
		79	*/
		80
		81	n = K6_BUG_LOOP;
		82	f_vide = vide;
		83	rdtscl(d);
		84	while (n--)
		85	f_vide();
		86	rdtscl(d2);
		87	d = d2-d;
		88
		89	if (d > 20*K6_BUG_LOOP)
		90	printk("system stability may be impaired when more than 32 MB are used.\n");
		91	else
		92	printk("probably OK (after B9730xxxx).\n");
		93	printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
		94	}
		95
		96	/* K6 with old style WHCR */
		97	if (c->x86_model < 8 \|\|
		98	(c->x86_model == 8 && c->x86_mask < 8)) {
		99	/* We can only write allocate on the low 508Mb */
		100	if (mbytes > 508)
		101	mbytes = 508;
		102
		103	rdmsr(MSR_K6_WHCR, l, h);
		104	if ((l&0x0000FFFF) == 0) {
		105	unsigned long flags;
		106	l = (1<<0)\|((mbytes/4)<<1);
		107	local_irq_save(flags);
		108	wbinvd();
		109	wrmsr(MSR_K6_WHCR, l, h);
		110	local_irq_restore(flags);
		111	printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
		112	mbytes);
		113	}
		114	return;
		115	}
		116
		117	if ((c->x86_model == 8 && c->x86_mask > 7) \|\|
		118	c->x86_model == 9 \|\| c->x86_model == 13) {
		119	/* The more serious chips .. */
		120
		121	if (mbytes > 4092)
		122	mbytes = 4092;
		123
		124	rdmsr(MSR_K6_WHCR, l, h);
		125	if ((l&0xFFFF0000) == 0) {
		126	unsigned long flags;
		127	l = ((mbytes>>2)<<22)\|(1<<16);
		128	local_irq_save(flags);
		129	wbinvd();
		130	wrmsr(MSR_K6_WHCR, l, h);
		131	local_irq_restore(flags);
		132	printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
		133	mbytes);
		134	}
		135
		136	return;
		137	}
		138
		139	if (c->x86_model == 10) {
		140	/* AMD Geode LX is model 10 */
		141	/* placeholder for any needed mods */
		142	return;
		143	}
		144	}
		145
		146	static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
		147	{
		148	u32 l, h;
		149
		150	/*
		151	* Bit 15 of Athlon specific MSR 15, needs to be 0
		152	* to enable SSE on Palomino/Morgan/Barton CPU's.
		153	* If the BIOS didn't enable it already, enable it here.
		154	*/
		155	if (c->x86_model >= 6 && c->x86_model <= 10) {
		156	if (!cpu_has(c, X86_FEATURE_XMM)) {
		157	printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
		158	rdmsr(MSR_K7_HWCR, l, h);
		159	l &= ~0x00008000;
		160	wrmsr(MSR_K7_HWCR, l, h);
		161	set_cpu_cap(c, X86_FEATURE_XMM);
		162	}
		163	}
		164
		165	/*
		166	* It's been determined by AMD that Athlons since model 8 stepping 1
		167	* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
		168	* As per AMD technical note 27212 0.2
		169	*/
		170	if ((c->x86_model == 8 && c->x86_mask >= 1) \|\| (c->x86_model > 8)) {
		171	rdmsr(MSR_K7_CLK_CTL, l, h);
		172	if ((l & 0xfff00000) != 0x20000000) {
		173	printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
		174	((l & 0x000fffff)\|0x20000000));
		175	wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)\|0x20000000, h);
		176	}
		177	}
		178
		179	set_cpu_cap(c, X86_FEATURE_K7);
		180	}
		181	#endif
		182
		183	#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
		184	static int __cpuinit nearby_node(int apicid)
		185	{
		186	int i, node;
		187
		188	for (i = apicid - 1; i >= 0; i--) {
		189	node = apicid_to_node[i];
		190	if (node != NUMA_NO_NODE && node_online(node))
		191	return node;
		192	}
		193	for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
		194	node = apicid_to_node[i];
		195	if (node != NUMA_NO_NODE && node_online(node))
		196	return node;
		197	}
		198	return first_node(node_online_map); /* Shouldn't happen */
		199	}
		200	#endif
		201
		202	/*
		203	* On a AMD dual core setup the lower bits of the APIC id distingush the cores.
		204	* Assumes number of cores is a power of two.
		205	*/
		206	static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
		207	{
		208	#ifdef CONFIG_X86_HT
		209	unsigned bits;
		210
		211	bits = c->x86_coreid_bits;
		212
		213	/* Low order bits define the core id (index of core in socket) */
		214	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
		215	/* Convert the initial APIC ID into the socket ID */
		216	c->phys_proc_id = c->initial_apicid >> bits;
		217	#endif
		218	}
		219
		220	static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
		221	{
		222	#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
		223	int cpu = smp_processor_id();
		224	int node;
		225	unsigned apicid = hard_smp_processor_id();
		226
		227	node = c->phys_proc_id;
		228	if (apicid_to_node[apicid] != NUMA_NO_NODE)
		229	node = apicid_to_node[apicid];
		230	if (!node_online(node)) {
		231	/* Two possibilities here:
		232	- The CPU is missing memory and no node was created.
		233	In that case try picking one from a nearby CPU
		234	- The APIC IDs differ from the HyperTransport node IDs
		235	which the K8 northbridge parsing fills in.
		236	Assume they are all increased by a constant offset,
		237	but in the same order as the HT nodeids.
		238	If that doesn't result in a usable node fall back to the
		239	path for the previous case. */
		240
		241	int ht_nodeid = c->initial_apicid;
		242
		243	if (ht_nodeid >= 0 &&
		244	apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
		245	node = apicid_to_node[ht_nodeid];
		246	/* Pick a nearby node */
		247	if (!node_online(node))
		248	node = nearby_node(apicid);
		249	}
		250	numa_set_node(cpu, node);
		251
		252	printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
		253	#endif
		254	}
		255
		256	static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
		257	{
		258	#ifdef CONFIG_X86_HT
		259	unsigned bits, ecx;
		260
		261	/* Multi core CPU? */
		262	if (c->extended_cpuid_level < 0x80000008)
		263	return;
		264
		265	ecx = cpuid_ecx(0x80000008);
		266
		267	c->x86_max_cores = (ecx & 0xff) + 1;
		268
		269	/* CPU telling us the core id bits shift? */
		270	bits = (ecx >> 12) & 0xF;
		271
		272	/* Otherwise recompute */
		273	if (bits == 0) {
		274	while ((1 << bits) < c->x86_max_cores)
		275	bits++;
		276	}
		277
		278	c->x86_coreid_bits = bits;
		279	#endif
		280	}
		281
		282	static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
		283	{
		284	early_init_amd_mc(c);
		285
		286	/* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
		287	if (c->x86_power & (1<<8))
		288	set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
		289
		290	#ifdef CONFIG_X86_64
		291	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
		292	#else
		293	/* Set MTRR capability flag if appropriate */
		294	if (c->x86 == 5)
		295	if (c->x86_model == 13 \|\| c->x86_model == 9 \|\|
		296	(c->x86_model == 8 && c->x86_mask >= 8))
		297	set_cpu_cap(c, X86_FEATURE_K6_MTRR);
		298	#endif
		299	}
		300
		301	static void __cpuinit init_amd(struct cpuinfo_x86 *c)
		302	{
47	#ifdef CONFIG_SMP	303	#ifdef CONFIG_SMP
48	unsigned long long value;	304	unsigned long long value;
49		305
@@ -54,7 +310,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
54	* Errata 63 for SH-B3 steppings	310	* Errata 63 for SH-B3 steppings
55	* Errata 122 for all steppings (F+ have it disabled by default)	311	* Errata 122 for all steppings (F+ have it disabled by default)
56	*/	312	*/
57	if (c->x86 == 15) {	313	if (c->x86 == 0xf) {
58	rdmsrl(MSR_K7_HWCR, value);	314	rdmsrl(MSR_K7_HWCR, value);
59	value \|= 1 << 6;	315	value \|= 1 << 6;
60	wrmsrl(MSR_K7_HWCR, value);	316	wrmsrl(MSR_K7_HWCR, value);
@@ -64,209 +320,119 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
64	early_init_amd(c);	320	early_init_amd(c);
65		321
66	/*	322	/*
67	* FIXME: We should handle the K5 here. Set up the write
68	* range and also turn on MSR 83 bits 4 and 31 (write alloc,
69	* no bus pipeline)
70	*/
71
72	/*
73	* Bit 31 in normal CPUID used for nonstandard 3DNow ID;	323	* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
74	* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway	324	* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
75	*/	325	*/
76	clear_cpu_cap(c, 0*32+31);	326	clear_cpu_cap(c, 0*32+31);
77		327
78	r = get_model_name(c);	328	#ifdef CONFIG_X86_64
		329	/* On C+ stepping K8 rep microcode works well for copy/memset */
		330	if (c->x86 == 0xf) {
		331	u32 level;
79		332
80	switch (c->x86) {	333	level = cpuid_eax(1);
81	case 4:	334	if((level >= 0x0f48 && level < 0x0f50) \|\| level >= 0x0f58)
82	/*	335	set_cpu_cap(c, X86_FEATURE_REP_GOOD);
83	* General Systems BIOSen alias the cpu frequency registers
84	* of the Elan at 0x000df000. Unfortuantly, one of the Linux
85	* drivers subsequently pokes it, and changes the CPU speed.
86	* Workaround : Remove the unneeded alias.
87	*/
88	#define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
89	#define CBAR_ENB (0x80000000)
90	#define CBAR_KEY (0X000000CB)
91	if (c->x86_model == 9 \|\| c->x86_model == 10) {
92	if (inl (CBAR) & CBAR_ENB)
93	outl (0 \| CBAR_KEY, CBAR);
94	}
95	break;
96	case 5:
97	if (c->x86_model < 6) {
98	/* Based on AMD doc 20734R - June 2000 */
99	if (c->x86_model == 0) {
100	clear_cpu_cap(c, X86_FEATURE_APIC);
101	set_cpu_cap(c, X86_FEATURE_PGE);
102	}
103	break;
104	}
105
106	if (c->x86_model == 6 && c->x86_mask == 1) {
107	const int K6_BUG_LOOP = 1000000;
108	int n;
109	void (*f_vide)(void);
110	unsigned long d, d2;
111
112	printk(KERN_INFO "AMD K6 stepping B detected - ");
113
114	/*
115	* It looks like AMD fixed the 2.6.2 bug and improved indirect
116	* calls at the same time.
117	*/
118
119	n = K6_BUG_LOOP;
120	f_vide = vide;
121	rdtscl(d);
122	while (n--)
123	f_vide();
124	rdtscl(d2);
125	d = d2-d;
126
127	if (d > 20*K6_BUG_LOOP)
128	printk("system stability may be impaired when more than 32 MB are used.\n");
129	else
130	printk("probably OK (after B9730xxxx).\n");
131	printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
132	}
133
134	/* K6 with old style WHCR */
135	if (c->x86_model < 8 \|\|
136	(c->x86_model == 8 && c->x86_mask < 8)) {
137	/* We can only write allocate on the low 508Mb */
138	if (mbytes > 508)
139	mbytes = 508;
140
141	rdmsr(MSR_K6_WHCR, l, h);
142	if ((l&0x0000FFFF) == 0) {
143	unsigned long flags;
144	l = (1<<0)\|((mbytes/4)<<1);
145	local_irq_save(flags);
146	wbinvd();
147	wrmsr(MSR_K6_WHCR, l, h);
148	local_irq_restore(flags);
149	printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
150	mbytes);
151	}
152	break;
153	}
154
155	if ((c->x86_model == 8 && c->x86_mask > 7) \|\|
156	c->x86_model == 9 \|\| c->x86_model == 13) {
157	/* The more serious chips .. */
158
159	if (mbytes > 4092)
160	mbytes = 4092;
161
162	rdmsr(MSR_K6_WHCR, l, h);
163	if ((l&0xFFFF0000) == 0) {
164	unsigned long flags;
165	l = ((mbytes>>2)<<22)\|(1<<16);
166	local_irq_save(flags);
167	wbinvd();
168	wrmsr(MSR_K6_WHCR, l, h);
169	local_irq_restore(flags);
170	printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
171	mbytes);
172	}
173
174	break;
175	}
176
177	if (c->x86_model == 10) {
178	/* AMD Geode LX is model 10 */
179	/* placeholder for any needed mods */
180	break;
181	}
182	break;
183	case 6: /* An Athlon/Duron */
184
185	/*
186	* Bit 15 of Athlon specific MSR 15, needs to be 0
187	* to enable SSE on Palomino/Morgan/Barton CPU's.
188	* If the BIOS didn't enable it already, enable it here.
189	*/
190	if (c->x86_model >= 6 && c->x86_model <= 10) {
191	if (!cpu_has(c, X86_FEATURE_XMM)) {
192	printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
193	rdmsr(MSR_K7_HWCR, l, h);
194	l &= ~0x00008000;
195	wrmsr(MSR_K7_HWCR, l, h);
196	set_cpu_cap(c, X86_FEATURE_XMM);
197	}
198	}
199
200	/*
201	* It's been determined by AMD that Athlons since model 8 stepping 1
202	* are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
203	* As per AMD technical note 27212 0.2
204	*/
205	if ((c->x86_model == 8 && c->x86_mask >= 1) \|\| (c->x86_model > 8)) {
206	rdmsr(MSR_K7_CLK_CTL, l, h);
207	if ((l & 0xfff00000) != 0x20000000) {
208	printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
209	((l & 0x000fffff)\|0x20000000));
210	wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)\|0x20000000, h);
211	}
212	}
213	break;
214	}	336	}
		337	if (c->x86 == 0x10 \|\| c->x86 == 0x11)
		338	set_cpu_cap(c, X86_FEATURE_REP_GOOD);
		339	#else
		340
		341	/*
		342	* FIXME: We should handle the K5 here. Set up the write
		343	* range and also turn on MSR 83 bits 4 and 31 (write alloc,
		344	* no bus pipeline)
		345	*/
215		346
216	switch (c->x86) {	347	switch (c->x86) {
217	case 15:	348	case 4:
218	/* Use K8 tuning for Fam10h and Fam11h */	349	init_amd_k5(c);
219	case 0x10:
220	case 0x11:
221	set_cpu_cap(c, X86_FEATURE_K8);
222	break;	350	break;
223	case 6:	351	case 5:
224	set_cpu_cap(c, X86_FEATURE_K7);	352	init_amd_k6(c);
		353	break;
		354	case 6: /* An Athlon/Duron */
		355	init_amd_k7(c);
225	break;	356	break;
226	}	357	}
		358
		359	/* K6s reports MCEs but don't actually have all the MSRs */
		360	if (c->x86 < 6)
		361	clear_cpu_cap(c, X86_FEATURE_MCE);
		362	#endif
		363
		364	/* Enable workaround for FXSAVE leak */
227	if (c->x86 >= 6)	365	if (c->x86 >= 6)
228	set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);	366	set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
229		367
230	display_cacheinfo(c);	368	if (!c->x86_model_id[0]) {
231		369	switch (c->x86) {
232	if (cpuid_eax(0x80000000) >= 0x80000008)	370	case 0xf:
233	c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;	371	/* Should distinguish Models here, but this is only
		372	a fallback anyways. */
		373	strcpy(c->x86_model_id, "Hammer");
		374	break;
		375	}
		376	}
234		377
235	#ifdef CONFIG_X86_HT	378	display_cacheinfo(c);
236	/*
237	* On a AMD multi core setup the lower bits of the APIC id
238	* distinguish the cores.
239	*/
240	if (c->x86_max_cores > 1) {
241	int cpu = smp_processor_id();
242	unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
243		379
244	if (bits == 0) {	380	/* Multi core CPU? */
245	while ((1 << bits) < c->x86_max_cores)	381	if (c->extended_cpuid_level >= 0x80000008) {
246	bits++;	382	amd_detect_cmp(c);
247	}	383	srat_detect_node(c);
248	c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
249	c->phys_proc_id >>= bits;
250	printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
251	cpu, c->x86_max_cores, c->cpu_core_id);
252	}	384	}
		385
		386	#ifdef CONFIG_X86_32
		387	detect_ht(c);
253	#endif	388	#endif
254		389
255	if (cpuid_eax(0x80000000) >= 0x80000006) {	390	if (c->extended_cpuid_level >= 0x80000006) {
256	if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))	391	if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
257	num_cache_leaves = 4;	392	num_cache_leaves = 4;
258	else	393	else
259	num_cache_leaves = 3;	394	num_cache_leaves = 3;
260	}	395	}
261		396
262	/* K6s reports MCEs but don't actually have all the MSRs */	397	if (c->x86 >= 0xf && c->x86 <= 0x11)
263	if (c->x86 < 6)	398	set_cpu_cap(c, X86_FEATURE_K8);
264	clear_cpu_cap(c, X86_FEATURE_MCE);
265		399
266	if (cpu_has_xmm2)	400	if (cpu_has_xmm2) {
		401	/* MFENCE stops RDTSC speculation */
267	set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);	402	set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
		403	}
		404
		405	#ifdef CONFIG_X86_64
		406	if (c->x86 == 0x10) {
		407	/* do this for boot cpu */
		408	if (c == &boot_cpu_data)
		409	check_enable_amd_mmconf_dmi();
		410
		411	fam10h_check_enable_mmcfg();
		412	}
		413
		414	if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
		415	unsigned long long tseg;
		416
		417	/*
		418	* Split up direct mapping around the TSEG SMM area.
		419	* Don't do it for gbpages because there seems very little
		420	* benefit in doing so.
		421	*/
		422	if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
		423	printk(KERN_DEBUG "tseg: %010llx\n", tseg);
		424	if ((tseg>>PMD_SHIFT) <
		425	(max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) \|\|
		426	((tseg>>PMD_SHIFT) <
		427	(max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
		428	(tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
		429	set_memory_4k((unsigned long)__va(tseg), 1);
		430	}
		431	}
		432	#endif
268	}	433	}
269		434
		435	#ifdef CONFIG_X86_32
270	static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)	436	static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
271	{	437	{
272	/* AMD errata T13 (order #21922) */	438	/* AMD errata T13 (order #21922) */
@@ -279,10 +445,12 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int
279	}	445	}
280	return size;	446	return size;
281	}	447	}
		448	#endif
282		449
283	static struct cpu_dev amd_cpu_dev __cpuinitdata = {	450	static struct cpu_dev amd_cpu_dev __cpuinitdata = {
284	.c_vendor = "AMD",	451	.c_vendor = "AMD",
285	.c_ident = { "AuthenticAMD" },	452	.c_ident = { "AuthenticAMD" },
		453	#ifdef CONFIG_X86_32
286	.c_models = {	454	.c_models = {
287	{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =	455	{ .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
288	{	456	{
@@ -295,9 +463,11 @@ static struct cpu_dev amd_cpu_dev __cpuinitdata = {
295	}	463	}
296	},	464	},
297	},	465	},
		466	.c_size_cache = amd_size_cache,
		467	#endif
298	.c_early_init = early_init_amd,	468	.c_early_init = early_init_amd,
299	.c_init = init_amd,	469	.c_init = init_amd,
300	.c_size_cache = amd_size_cache,	470	.c_x86_vendor = X86_VENDOR_AMD,
301	};	471	};
302		472
303	cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);	473	cpu_dev_register(amd_cpu_dev);