diff options
Diffstat (limited to 'arch/unicore32/include/mach/regs-sdc.h')
-rw-r--r-- | arch/unicore32/include/mach/regs-sdc.h | 156 |
1 files changed, 156 insertions, 0 deletions
diff --git a/arch/unicore32/include/mach/regs-sdc.h b/arch/unicore32/include/mach/regs-sdc.h new file mode 100644 index 00000000000..1303ecf660b --- /dev/null +++ b/arch/unicore32/include/mach/regs-sdc.h | |||
@@ -0,0 +1,156 @@ | |||
1 | /* | ||
2 | * PKUnity Multi-Media Card and Security Digital Card (MMC/SD) Registers | ||
3 | */ | ||
4 | /* | ||
5 | * Clock Control Reg SDC_CCR | ||
6 | */ | ||
7 | #define SDC_CCR (PKUNITY_SDC_BASE + 0x0000) | ||
8 | /* | ||
9 | * Software Reset Reg SDC_SRR | ||
10 | */ | ||
11 | #define SDC_SRR (PKUNITY_SDC_BASE + 0x0004) | ||
12 | /* | ||
13 | * Argument Reg SDC_ARGUMENT | ||
14 | */ | ||
15 | #define SDC_ARGUMENT (PKUNITY_SDC_BASE + 0x0008) | ||
16 | /* | ||
17 | * Command Reg SDC_COMMAND | ||
18 | */ | ||
19 | #define SDC_COMMAND (PKUNITY_SDC_BASE + 0x000C) | ||
20 | /* | ||
21 | * Block Size Reg SDC_BLOCKSIZE | ||
22 | */ | ||
23 | #define SDC_BLOCKSIZE (PKUNITY_SDC_BASE + 0x0010) | ||
24 | /* | ||
25 | * Block Cound Reg SDC_BLOCKCOUNT | ||
26 | */ | ||
27 | #define SDC_BLOCKCOUNT (PKUNITY_SDC_BASE + 0x0014) | ||
28 | /* | ||
29 | * Transfer Mode Reg SDC_TMR | ||
30 | */ | ||
31 | #define SDC_TMR (PKUNITY_SDC_BASE + 0x0018) | ||
32 | /* | ||
33 | * Response Reg. 0 SDC_RES0 | ||
34 | */ | ||
35 | #define SDC_RES0 (PKUNITY_SDC_BASE + 0x001C) | ||
36 | /* | ||
37 | * Response Reg. 1 SDC_RES1 | ||
38 | */ | ||
39 | #define SDC_RES1 (PKUNITY_SDC_BASE + 0x0020) | ||
40 | /* | ||
41 | * Response Reg. 2 SDC_RES2 | ||
42 | */ | ||
43 | #define SDC_RES2 (PKUNITY_SDC_BASE + 0x0024) | ||
44 | /* | ||
45 | * Response Reg. 3 SDC_RES3 | ||
46 | */ | ||
47 | #define SDC_RES3 (PKUNITY_SDC_BASE + 0x0028) | ||
48 | /* | ||
49 | * Read Timeout Control Reg SDC_RTCR | ||
50 | */ | ||
51 | #define SDC_RTCR (PKUNITY_SDC_BASE + 0x002C) | ||
52 | /* | ||
53 | * Interrupt Status Reg SDC_ISR | ||
54 | */ | ||
55 | #define SDC_ISR (PKUNITY_SDC_BASE + 0x0030) | ||
56 | /* | ||
57 | * Interrupt Status Mask Reg SDC_ISMR | ||
58 | */ | ||
59 | #define SDC_ISMR (PKUNITY_SDC_BASE + 0x0034) | ||
60 | /* | ||
61 | * RX FIFO SDC_RXFIFO | ||
62 | */ | ||
63 | #define SDC_RXFIFO (PKUNITY_SDC_BASE + 0x0038) | ||
64 | /* | ||
65 | * TX FIFO SDC_TXFIFO | ||
66 | */ | ||
67 | #define SDC_TXFIFO (PKUNITY_SDC_BASE + 0x003C) | ||
68 | |||
69 | /* | ||
70 | * SD Clock Enable SDC_CCR_CLKEN | ||
71 | */ | ||
72 | #define SDC_CCR_CLKEN FIELD(1, 1, 2) | ||
73 | /* | ||
74 | * [15:8] SDC_CCR_PDIV(v) | ||
75 | */ | ||
76 | #define SDC_CCR_PDIV(v) FIELD((v), 8, 8) | ||
77 | |||
78 | /* | ||
79 | * Software reset enable SDC_SRR_ENABLE | ||
80 | */ | ||
81 | #define SDC_SRR_ENABLE FIELD(0, 1, 0) | ||
82 | /* | ||
83 | * Software reset disable SDC_SRR_DISABLE | ||
84 | */ | ||
85 | #define SDC_SRR_DISABLE FIELD(1, 1, 0) | ||
86 | |||
87 | /* | ||
88 | * Response type SDC_COMMAND_RESTYPE_MASK | ||
89 | */ | ||
90 | #define SDC_COMMAND_RESTYPE_MASK FMASK(2, 0) | ||
91 | /* | ||
92 | * No response SDC_COMMAND_RESTYPE_NONE | ||
93 | */ | ||
94 | #define SDC_COMMAND_RESTYPE_NONE FIELD(0, 2, 0) | ||
95 | /* | ||
96 | * 136-bit long response SDC_COMMAND_RESTYPE_LONG | ||
97 | */ | ||
98 | #define SDC_COMMAND_RESTYPE_LONG FIELD(1, 2, 0) | ||
99 | /* | ||
100 | * 48-bit short response SDC_COMMAND_RESTYPE_SHORT | ||
101 | */ | ||
102 | #define SDC_COMMAND_RESTYPE_SHORT FIELD(2, 2, 0) | ||
103 | /* | ||
104 | * 48-bit short and test if busy response SDC_COMMAND_RESTYPE_SHORTBUSY | ||
105 | */ | ||
106 | #define SDC_COMMAND_RESTYPE_SHORTBUSY FIELD(3, 2, 0) | ||
107 | /* | ||
108 | * data ready SDC_COMMAND_DATAREADY | ||
109 | */ | ||
110 | #define SDC_COMMAND_DATAREADY FIELD(1, 1, 2) | ||
111 | #define SDC_COMMAND_CMDEN FIELD(1, 1, 3) | ||
112 | /* | ||
113 | * [10:5] SDC_COMMAND_CMDINDEX(v) | ||
114 | */ | ||
115 | #define SDC_COMMAND_CMDINDEX(v) FIELD((v), 6, 5) | ||
116 | |||
117 | /* | ||
118 | * [10:0] SDC_BLOCKSIZE_BSMASK(v) | ||
119 | */ | ||
120 | #define SDC_BLOCKSIZE_BSMASK(v) FIELD((v), 11, 0) | ||
121 | /* | ||
122 | * [11:0] SDC_BLOCKCOUNT_BCMASK(v) | ||
123 | */ | ||
124 | #define SDC_BLOCKCOUNT_BCMASK(v) FIELD((v), 12, 0) | ||
125 | |||
126 | /* | ||
127 | * Data Width 1bit SDC_TMR_WTH_1BIT | ||
128 | */ | ||
129 | #define SDC_TMR_WTH_1BIT FIELD(0, 1, 0) | ||
130 | /* | ||
131 | * Data Width 4bit SDC_TMR_WTH_4BIT | ||
132 | */ | ||
133 | #define SDC_TMR_WTH_4BIT FIELD(1, 1, 0) | ||
134 | /* | ||
135 | * Read SDC_TMR_DIR_READ | ||
136 | */ | ||
137 | #define SDC_TMR_DIR_READ FIELD(0, 1, 1) | ||
138 | /* | ||
139 | * Write SDC_TMR_DIR_WRITE | ||
140 | */ | ||
141 | #define SDC_TMR_DIR_WRITE FIELD(1, 1, 1) | ||
142 | |||
143 | #define SDC_IR_MASK FMASK(13, 0) | ||
144 | #define SDC_IR_RESTIMEOUT FIELD(1, 1, 0) | ||
145 | #define SDC_IR_WRITECRC FIELD(1, 1, 1) | ||
146 | #define SDC_IR_READCRC FIELD(1, 1, 2) | ||
147 | #define SDC_IR_TXFIFOREAD FIELD(1, 1, 3) | ||
148 | #define SDC_IR_RXFIFOWRITE FIELD(1, 1, 4) | ||
149 | #define SDC_IR_READTIMEOUT FIELD(1, 1, 5) | ||
150 | #define SDC_IR_DATACOMPLETE FIELD(1, 1, 6) | ||
151 | #define SDC_IR_CMDCOMPLETE FIELD(1, 1, 7) | ||
152 | #define SDC_IR_RXFIFOFULL FIELD(1, 1, 8) | ||
153 | #define SDC_IR_RXFIFOEMPTY FIELD(1, 1, 9) | ||
154 | #define SDC_IR_TXFIFOFULL FIELD(1, 1, 10) | ||
155 | #define SDC_IR_TXFIFOEMPTY FIELD(1, 1, 11) | ||
156 | #define SDC_IR_ENDCMDWITHRES FIELD(1, 1, 12) | ||