7 files changed, 50 insertions, 4 deletions

diff --git a/arch/sparc/include/asm/elf_64.h b/arch/sparc/include/asm/elf_64.h
index cfa9cd2e551..64f7a00b374 100644
--- a/arch/sparc/include/asm/elf_64.h
+++ b/arch/sparc/include/asm/elf_64.h
@@ -177,9 +177,11 @@ static inline unsigned int sparc64_elf_hwcap(void)
                 cap |= HWCAP_SPARC_ULTRA3;
         else if (tlb_type == hypervisor) {
                 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
-                    sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
                         cap |= HWCAP_SPARC_BLKINIT;
-                if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
+                if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
+                    sun4v_chip_type == SUN4V_CHIP_NIAGARA3)
                         cap |= HWCAP_SPARC_N2;
         }
 
diff --git a/arch/sparc/include/asm/xor_64.h b/arch/sparc/include/asm/xor_64.h
index bee4bf4be3a..9ed6ff679ab 100644
--- a/arch/sparc/include/asm/xor_64.h
+++ b/arch/sparc/include/asm/xor_64.h
@@ -65,6 +65,7 @@ static struct xor_block_template xor_block_niagara = {
 #define XOR_SELECT_TEMPLATE(FASTEST) \
         ((tlb_type == hypervisor && \
           (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \
-           sun4v_chip_type == SUN4V_CHIP_NIAGARA2)) ? \
+           sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \
+           sun4v_chip_type == SUN4V_CHIP_NIAGARA3)) ? \
          &xor_block_niagara : \
          &xor_block_VIS)
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index 70f035c86c0..17cf290dc2b 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -474,6 +474,12 @@ static void __init sun4v_cpu_probe(void)
                 sparc_pmu_type = "niagara2";
                 break;
 
+        case SUN4V_CHIP_NIAGARA3:
+                sparc_cpu_type = "UltraSparc T3 (Niagara3)";
+                sparc_fpu_type = "UltraSparc T3 integrated FPU";
+                sparc_pmu_type = "niagara3";
+                break;
+
         default:
                 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
                        prom_cpu_compatible);
diff --git a/arch/sparc/kernel/cpumap.c b/arch/sparc/kernel/cpumap.c
index d91fd782743..4197e8d62d4 100644
--- a/arch/sparc/kernel/cpumap.c
+++ b/arch/sparc/kernel/cpumap.c
@@ -324,6 +324,7 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
         switch (sun4v_chip_type) {
         case SUN4V_CHIP_NIAGARA1:
         case SUN4V_CHIP_NIAGARA2:
+        case SUN4V_CHIP_NIAGARA3:
                 rover_inc_table = niagara_iterate_method;
                 break;
         default:
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index aa594c792d1..c752603a7c0 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -132,6 +132,8 @@ prom_sun4v_name:
         .asciz  "sun4v"
 prom_niagara_prefix:
         .asciz  "SUNW,UltraSPARC-T"
+prom_sparc_prefix:
+        .asciz  "SPARC-T"
         .align  4
 prom_root_compatible:
         .skip   64
@@ -382,6 +384,22 @@ sun4v_chip_type:
 90:     ldub    [%g7], %g2
         ldub    [%g1], %g4
         cmp     %g2, %g4
+        bne,pn  %icc, 89f
+         add    %g7, 1, %g7
+        subcc   %g3, 1, %g3
+        bne,pt  %xcc, 90b
+         add    %g1, 1, %g1
+        ba,pt   %xcc, 91f
+         nop
+
+89:     sethi   %hi(prom_cpu_compatible), %g1
+        or      %g1, %lo(prom_cpu_compatible), %g1
+        sethi   %hi(prom_sparc_prefix), %g7
+        or      %g7, %lo(prom_sparc_prefix), %g7
+        mov     7, %g3
+90:     ldub    [%g7], %g2
+        ldub    [%g1], %g4
+        cmp     %g2, %g4
         bne,pn  %icc, 4f
          add    %g7, 1, %g7
         subcc   %g3, 1, %g3
@@ -390,6 +408,15 @@ sun4v_chip_type:
 
         sethi   %hi(prom_cpu_compatible), %g1
         or      %g1, %lo(prom_cpu_compatible), %g1
+        ldub    [%g1 + 7], %g2
+        cmp     %g2, '3'
+        be,pt   %xcc, 5f
+         mov    SUN4V_CHIP_NIAGARA3, %g4
+        ba,pt   %xcc, 4f
+         nop
+
+91:     sethi   %hi(prom_cpu_compatible), %g1
+        or      %g1, %lo(prom_cpu_compatible), %g1
         ldub    [%g1 + 17], %g2
         cmp     %g2, '1'
         be,pt   %xcc, 5f
@@ -397,6 +424,7 @@ sun4v_chip_type:
         cmp     %g2, '2'
         be,pt   %xcc, 5f
          mov    SUN4V_CHIP_NIAGARA2, %g4
+        
 4:
         mov     SUN4V_CHIP_UNKNOWN, %g4
 5:      sethi   %hi(sun4v_chip_type), %g2
@@ -514,6 +542,9 @@ niagara_tlb_fixup:
          cmp    %g1, SUN4V_CHIP_NIAGARA2
         be,pt   %xcc, niagara2_patch
          nop
+        cmp     %g1, SUN4V_CHIP_NIAGARA3
+        be,pt   %xcc, niagara2_patch
+         nop
 
         call    generic_patch_copyops
          nop
diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c
index 878c6824c73..343b0f9e2e7 100644
--- a/arch/sparc/kernel/pcr.c
+++ b/arch/sparc/kernel/pcr.c
@@ -109,6 +109,10 @@ static int __init register_perf_hsvc(void)
                         perf_hsvc_group = HV_GRP_N2_CPU;
                         break;
 
+                case SUN4V_CHIP_NIAGARA3:
+                        perf_hsvc_group = HV_GRP_KT_CPU;
+                        break;
+
                 default:
                         return -ENODEV;
                 }
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index 171e8d84dc3..614da624330 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -1343,7 +1343,8 @@ static bool __init supported_pmu(void)
                 sparc_pmu = &niagara1_pmu;
                 return true;
         }
-        if (!strcmp(sparc_pmu_type, "niagara2")) {
+        if (!strcmp(sparc_pmu_type, "niagara2") ||
+            !strcmp(sparc_pmu_type, "niagara3")) {
                 sparc_pmu = &niagara2_pmu;
                 return true;
         }