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-rw-r--r--arch/sparc64/mm/Makefile9
-rw-r--r--arch/sparc64/mm/fault.c440
-rw-r--r--arch/sparc64/mm/generic.c163
-rw-r--r--arch/sparc64/mm/hugetlbpage.c357
-rw-r--r--arch/sparc64/mm/init.c2362
-rw-r--r--arch/sparc64/mm/init.h49
-rw-r--r--arch/sparc64/mm/tlb.c97
-rw-r--r--arch/sparc64/mm/tsb.c498
-rw-r--r--arch/sparc64/mm/ultra.S769
9 files changed, 0 insertions, 4744 deletions
diff --git a/arch/sparc64/mm/Makefile b/arch/sparc64/mm/Makefile
deleted file mode 100644
index 68d04c0370f..00000000000
--- a/arch/sparc64/mm/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
1# Makefile for the linux Sparc64-specific parts of the memory manager.
2#
3
4EXTRA_AFLAGS := -ansi
5EXTRA_CFLAGS := -Werror
6
7obj-y := ultra.o tlb.o tsb.o fault.o init.o generic.o
8
9obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
diff --git a/arch/sparc64/mm/fault.c b/arch/sparc64/mm/fault.c
deleted file mode 100644
index a9e474bf638..00000000000
--- a/arch/sparc64/mm/fault.c
+++ /dev/null
@@ -1,440 +0,0 @@
1/*
2 * arch/sparc64/mm/fault.c: Page fault handlers for the 64-bit Sparc.
3 *
4 * Copyright (C) 1996, 2008 David S. Miller (davem@davemloft.net)
5 * Copyright (C) 1997, 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 */
7
8#include <asm/head.h>
9
10#include <linux/string.h>
11#include <linux/types.h>
12#include <linux/sched.h>
13#include <linux/ptrace.h>
14#include <linux/mman.h>
15#include <linux/signal.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/kprobes.h>
21#include <linux/kdebug.h>
22
23#include <asm/page.h>
24#include <asm/pgtable.h>
25#include <asm/openprom.h>
26#include <asm/oplib.h>
27#include <asm/uaccess.h>
28#include <asm/asi.h>
29#include <asm/lsu.h>
30#include <asm/sections.h>
31#include <asm/mmu_context.h>
32
33#ifdef CONFIG_KPROBES
34static inline int notify_page_fault(struct pt_regs *regs)
35{
36 int ret = 0;
37
38 /* kprobe_running() needs smp_processor_id() */
39 if (!user_mode(regs)) {
40 preempt_disable();
41 if (kprobe_running() && kprobe_fault_handler(regs, 0))
42 ret = 1;
43 preempt_enable();
44 }
45 return ret;
46}
47#else
48static inline int notify_page_fault(struct pt_regs *regs)
49{
50 return 0;
51}
52#endif
53
54static void __kprobes unhandled_fault(unsigned long address,
55 struct task_struct *tsk,
56 struct pt_regs *regs)
57{
58 if ((unsigned long) address < PAGE_SIZE) {
59 printk(KERN_ALERT "Unable to handle kernel NULL "
60 "pointer dereference\n");
61 } else {
62 printk(KERN_ALERT "Unable to handle kernel paging request "
63 "at virtual address %016lx\n", (unsigned long)address);
64 }
65 printk(KERN_ALERT "tsk->{mm,active_mm}->context = %016lx\n",
66 (tsk->mm ?
67 CTX_HWBITS(tsk->mm->context) :
68 CTX_HWBITS(tsk->active_mm->context)));
69 printk(KERN_ALERT "tsk->{mm,active_mm}->pgd = %016lx\n",
70 (tsk->mm ? (unsigned long) tsk->mm->pgd :
71 (unsigned long) tsk->active_mm->pgd));
72 die_if_kernel("Oops", regs);
73}
74
75static void bad_kernel_pc(struct pt_regs *regs, unsigned long vaddr)
76{
77 printk(KERN_CRIT "OOPS: Bogus kernel PC [%016lx] in fault handler\n",
78 regs->tpc);
79 printk(KERN_CRIT "OOPS: RPC [%016lx]\n", regs->u_regs[15]);
80 printk("OOPS: RPC <%pS>\n", (void *) regs->u_regs[15]);
81 printk(KERN_CRIT "OOPS: Fault was to vaddr[%lx]\n", vaddr);
82 dump_stack();
83 unhandled_fault(regs->tpc, current, regs);
84}
85
86/*
87 * We now make sure that mmap_sem is held in all paths that call
88 * this. Additionally, to prevent kswapd from ripping ptes from
89 * under us, raise interrupts around the time that we look at the
90 * pte, kswapd will have to wait to get his smp ipi response from
91 * us. vmtruncate likewise. This saves us having to get pte lock.
92 */
93static unsigned int get_user_insn(unsigned long tpc)
94{
95 pgd_t *pgdp = pgd_offset(current->mm, tpc);
96 pud_t *pudp;
97 pmd_t *pmdp;
98 pte_t *ptep, pte;
99 unsigned long pa;
100 u32 insn = 0;
101 unsigned long pstate;
102
103 if (pgd_none(*pgdp))
104 goto outret;
105 pudp = pud_offset(pgdp, tpc);
106 if (pud_none(*pudp))
107 goto outret;
108 pmdp = pmd_offset(pudp, tpc);
109 if (pmd_none(*pmdp))
110 goto outret;
111
112 /* This disables preemption for us as well. */
113 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
114 __asm__ __volatile__("wrpr %0, %1, %%pstate"
115 : : "r" (pstate), "i" (PSTATE_IE));
116 ptep = pte_offset_map(pmdp, tpc);
117 pte = *ptep;
118 if (!pte_present(pte))
119 goto out;
120
121 pa = (pte_pfn(pte) << PAGE_SHIFT);
122 pa += (tpc & ~PAGE_MASK);
123
124 /* Use phys bypass so we don't pollute dtlb/dcache. */
125 __asm__ __volatile__("lduwa [%1] %2, %0"
126 : "=r" (insn)
127 : "r" (pa), "i" (ASI_PHYS_USE_EC));
128
129out:
130 pte_unmap(ptep);
131 __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
132outret:
133 return insn;
134}
135
136extern unsigned long compute_effective_address(struct pt_regs *, unsigned int, unsigned int);
137
138static void do_fault_siginfo(int code, int sig, struct pt_regs *regs,
139 unsigned int insn, int fault_code)
140{
141 siginfo_t info;
142
143 info.si_code = code;
144 info.si_signo = sig;
145 info.si_errno = 0;
146 if (fault_code & FAULT_CODE_ITLB)
147 info.si_addr = (void __user *) regs->tpc;
148 else
149 info.si_addr = (void __user *)
150 compute_effective_address(regs, insn, 0);
151 info.si_trapno = 0;
152 force_sig_info(sig, &info, current);
153}
154
155extern int handle_ldf_stq(u32, struct pt_regs *);
156extern int handle_ld_nf(u32, struct pt_regs *);
157
158static unsigned int get_fault_insn(struct pt_regs *regs, unsigned int insn)
159{
160 if (!insn) {
161 if (!regs->tpc || (regs->tpc & 0x3))
162 return 0;
163 if (regs->tstate & TSTATE_PRIV) {
164 insn = *(unsigned int *) regs->tpc;
165 } else {
166 insn = get_user_insn(regs->tpc);
167 }
168 }
169 return insn;
170}
171
172static void do_kernel_fault(struct pt_regs *regs, int si_code, int fault_code,
173 unsigned int insn, unsigned long address)
174{
175 unsigned char asi = ASI_P;
176
177 if ((!insn) && (regs->tstate & TSTATE_PRIV))
178 goto cannot_handle;
179
180 /* If user insn could be read (thus insn is zero), that
181 * is fine. We will just gun down the process with a signal
182 * in that case.
183 */
184
185 if (!(fault_code & (FAULT_CODE_WRITE|FAULT_CODE_ITLB)) &&
186 (insn & 0xc0800000) == 0xc0800000) {
187 if (insn & 0x2000)
188 asi = (regs->tstate >> 24);
189 else
190 asi = (insn >> 5);
191 if ((asi & 0xf2) == 0x82) {
192 if (insn & 0x1000000) {
193 handle_ldf_stq(insn, regs);
194 } else {
195 /* This was a non-faulting load. Just clear the
196 * destination register(s) and continue with the next
197 * instruction. -jj
198 */
199 handle_ld_nf(insn, regs);
200 }
201 return;
202 }
203 }
204
205 /* Is this in ex_table? */
206 if (regs->tstate & TSTATE_PRIV) {
207 const struct exception_table_entry *entry;
208
209 entry = search_exception_tables(regs->tpc);
210 if (entry) {
211 regs->tpc = entry->fixup;
212 regs->tnpc = regs->tpc + 4;
213 return;
214 }
215 } else {
216 /* The si_code was set to make clear whether
217 * this was a SEGV_MAPERR or SEGV_ACCERR fault.
218 */
219 do_fault_siginfo(si_code, SIGSEGV, regs, insn, fault_code);
220 return;
221 }
222
223cannot_handle:
224 unhandled_fault (address, current, regs);
225}
226
227asmlinkage void __kprobes do_sparc64_fault(struct pt_regs *regs)
228{
229 struct mm_struct *mm = current->mm;
230 struct vm_area_struct *vma;
231 unsigned int insn = 0;
232 int si_code, fault_code, fault;
233 unsigned long address, mm_rss;
234
235 fault_code = get_thread_fault_code();
236
237 if (notify_page_fault(regs))
238 return;
239
240 si_code = SEGV_MAPERR;
241 address = current_thread_info()->fault_address;
242
243 if ((fault_code & FAULT_CODE_ITLB) &&
244 (fault_code & FAULT_CODE_DTLB))
245 BUG();
246
247 if (regs->tstate & TSTATE_PRIV) {
248 unsigned long tpc = regs->tpc;
249
250 /* Sanity check the PC. */
251 if ((tpc >= KERNBASE && tpc < (unsigned long) __init_end) ||
252 (tpc >= MODULES_VADDR && tpc < MODULES_END)) {
253 /* Valid, no problems... */
254 } else {
255 bad_kernel_pc(regs, address);
256 return;
257 }
258 }
259
260 /*
261 * If we're in an interrupt or have no user
262 * context, we must not take the fault..
263 */
264 if (in_atomic() || !mm)
265 goto intr_or_no_mm;
266
267 if (test_thread_flag(TIF_32BIT)) {
268 if (!(regs->tstate & TSTATE_PRIV))
269 regs->tpc &= 0xffffffff;
270 address &= 0xffffffff;
271 }
272
273 if (!down_read_trylock(&mm->mmap_sem)) {
274 if ((regs->tstate & TSTATE_PRIV) &&
275 !search_exception_tables(regs->tpc)) {
276 insn = get_fault_insn(regs, insn);
277 goto handle_kernel_fault;
278 }
279 down_read(&mm->mmap_sem);
280 }
281
282 vma = find_vma(mm, address);
283 if (!vma)
284 goto bad_area;
285
286 /* Pure DTLB misses do not tell us whether the fault causing
287 * load/store/atomic was a write or not, it only says that there
288 * was no match. So in such a case we (carefully) read the
289 * instruction to try and figure this out. It's an optimization
290 * so it's ok if we can't do this.
291 *
292 * Special hack, window spill/fill knows the exact fault type.
293 */
294 if (((fault_code &
295 (FAULT_CODE_DTLB | FAULT_CODE_WRITE | FAULT_CODE_WINFIXUP)) == FAULT_CODE_DTLB) &&
296 (vma->vm_flags & VM_WRITE) != 0) {
297 insn = get_fault_insn(regs, 0);
298 if (!insn)
299 goto continue_fault;
300 /* All loads, stores and atomics have bits 30 and 31 both set
301 * in the instruction. Bit 21 is set in all stores, but we
302 * have to avoid prefetches which also have bit 21 set.
303 */
304 if ((insn & 0xc0200000) == 0xc0200000 &&
305 (insn & 0x01780000) != 0x01680000) {
306 /* Don't bother updating thread struct value,
307 * because update_mmu_cache only cares which tlb
308 * the access came from.
309 */
310 fault_code |= FAULT_CODE_WRITE;
311 }
312 }
313continue_fault:
314
315 if (vma->vm_start <= address)
316 goto good_area;
317 if (!(vma->vm_flags & VM_GROWSDOWN))
318 goto bad_area;
319 if (!(fault_code & FAULT_CODE_WRITE)) {
320 /* Non-faulting loads shouldn't expand stack. */
321 insn = get_fault_insn(regs, insn);
322 if ((insn & 0xc0800000) == 0xc0800000) {
323 unsigned char asi;
324
325 if (insn & 0x2000)
326 asi = (regs->tstate >> 24);
327 else
328 asi = (insn >> 5);
329 if ((asi & 0xf2) == 0x82)
330 goto bad_area;
331 }
332 }
333 if (expand_stack(vma, address))
334 goto bad_area;
335 /*
336 * Ok, we have a good vm_area for this memory access, so
337 * we can handle it..
338 */
339good_area:
340 si_code = SEGV_ACCERR;
341
342 /* If we took a ITLB miss on a non-executable page, catch
343 * that here.
344 */
345 if ((fault_code & FAULT_CODE_ITLB) && !(vma->vm_flags & VM_EXEC)) {
346 BUG_ON(address != regs->tpc);
347 BUG_ON(regs->tstate & TSTATE_PRIV);
348 goto bad_area;
349 }
350
351 if (fault_code & FAULT_CODE_WRITE) {
352 if (!(vma->vm_flags & VM_WRITE))
353 goto bad_area;
354
355 /* Spitfire has an icache which does not snoop
356 * processor stores. Later processors do...
357 */
358 if (tlb_type == spitfire &&
359 (vma->vm_flags & VM_EXEC) != 0 &&
360 vma->vm_file != NULL)
361 set_thread_fault_code(fault_code |
362 FAULT_CODE_BLKCOMMIT);
363 } else {
364 /* Allow reads even for write-only mappings */
365 if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
366 goto bad_area;
367 }
368
369 fault = handle_mm_fault(mm, vma, address, (fault_code & FAULT_CODE_WRITE));
370 if (unlikely(fault & VM_FAULT_ERROR)) {
371 if (fault & VM_FAULT_OOM)
372 goto out_of_memory;
373 else if (fault & VM_FAULT_SIGBUS)
374 goto do_sigbus;
375 BUG();
376 }
377 if (fault & VM_FAULT_MAJOR)
378 current->maj_flt++;
379 else
380 current->min_flt++;
381
382 up_read(&mm->mmap_sem);
383
384 mm_rss = get_mm_rss(mm);
385#ifdef CONFIG_HUGETLB_PAGE
386 mm_rss -= (mm->context.huge_pte_count * (HPAGE_SIZE / PAGE_SIZE));
387#endif
388 if (unlikely(mm_rss >
389 mm->context.tsb_block[MM_TSB_BASE].tsb_rss_limit))
390 tsb_grow(mm, MM_TSB_BASE, mm_rss);
391#ifdef CONFIG_HUGETLB_PAGE
392 mm_rss = mm->context.huge_pte_count;
393 if (unlikely(mm_rss >
394 mm->context.tsb_block[MM_TSB_HUGE].tsb_rss_limit))
395 tsb_grow(mm, MM_TSB_HUGE, mm_rss);
396#endif
397 return;
398
399 /*
400 * Something tried to access memory that isn't in our memory map..
401 * Fix it, but check if it's kernel or user first..
402 */
403bad_area:
404 insn = get_fault_insn(regs, insn);
405 up_read(&mm->mmap_sem);
406
407handle_kernel_fault:
408 do_kernel_fault(regs, si_code, fault_code, insn, address);
409 return;
410
411/*
412 * We ran out of memory, or some other thing happened to us that made
413 * us unable to handle the page fault gracefully.
414 */
415out_of_memory:
416 insn = get_fault_insn(regs, insn);
417 up_read(&mm->mmap_sem);
418 printk("VM: killing process %s\n", current->comm);
419 if (!(regs->tstate & TSTATE_PRIV))
420 do_group_exit(SIGKILL);
421 goto handle_kernel_fault;
422
423intr_or_no_mm:
424 insn = get_fault_insn(regs, 0);
425 goto handle_kernel_fault;
426
427do_sigbus:
428 insn = get_fault_insn(regs, insn);
429 up_read(&mm->mmap_sem);
430
431 /*
432 * Send a sigbus, regardless of whether we were in kernel
433 * or user mode.
434 */
435 do_fault_siginfo(BUS_ADRERR, SIGBUS, regs, insn, fault_code);
436
437 /* Kernel mode? Handle exceptions or die */
438 if (regs->tstate & TSTATE_PRIV)
439 goto handle_kernel_fault;
440}
diff --git a/arch/sparc64/mm/generic.c b/arch/sparc64/mm/generic.c
deleted file mode 100644
index f362c203701..00000000000
--- a/arch/sparc64/mm/generic.c
+++ /dev/null
@@ -1,163 +0,0 @@
1/*
2 * generic.c: Generic Sparc mm routines that are not dependent upon
3 * MMU type but are Sparc specific.
4 *
5 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8#include <linux/kernel.h>
9#include <linux/mm.h>
10#include <linux/swap.h>
11#include <linux/pagemap.h>
12
13#include <asm/pgalloc.h>
14#include <asm/pgtable.h>
15#include <asm/page.h>
16#include <asm/tlbflush.h>
17
18/* Remap IO memory, the same way as remap_pfn_range(), but use
19 * the obio memory space.
20 *
21 * They use a pgprot that sets PAGE_IO and does not check the
22 * mem_map table as this is independent of normal memory.
23 */
24static inline void io_remap_pte_range(struct mm_struct *mm, pte_t * pte,
25 unsigned long address,
26 unsigned long size,
27 unsigned long offset, pgprot_t prot,
28 int space)
29{
30 unsigned long end;
31
32 /* clear hack bit that was used as a write_combine side-effect flag */
33 offset &= ~0x1UL;
34 address &= ~PMD_MASK;
35 end = address + size;
36 if (end > PMD_SIZE)
37 end = PMD_SIZE;
38 do {
39 pte_t entry;
40 unsigned long curend = address + PAGE_SIZE;
41
42 entry = mk_pte_io(offset, prot, space, PAGE_SIZE);
43 if (!(address & 0xffff)) {
44 if (PAGE_SIZE < (4 * 1024 * 1024) &&
45 !(address & 0x3fffff) &&
46 !(offset & 0x3ffffe) &&
47 end >= address + 0x400000) {
48 entry = mk_pte_io(offset, prot, space,
49 4 * 1024 * 1024);
50 curend = address + 0x400000;
51 offset += 0x400000;
52 } else if (PAGE_SIZE < (512 * 1024) &&
53 !(address & 0x7ffff) &&
54 !(offset & 0x7fffe) &&
55 end >= address + 0x80000) {
56 entry = mk_pte_io(offset, prot, space,
57 512 * 1024 * 1024);
58 curend = address + 0x80000;
59 offset += 0x80000;
60 } else if (PAGE_SIZE < (64 * 1024) &&
61 !(offset & 0xfffe) &&
62 end >= address + 0x10000) {
63 entry = mk_pte_io(offset, prot, space,
64 64 * 1024);
65 curend = address + 0x10000;
66 offset += 0x10000;
67 } else
68 offset += PAGE_SIZE;
69 } else
70 offset += PAGE_SIZE;
71
72 if (pte_write(entry))
73 entry = pte_mkdirty(entry);
74 do {
75 BUG_ON(!pte_none(*pte));
76 set_pte_at(mm, address, pte, entry);
77 address += PAGE_SIZE;
78 pte_val(entry) += PAGE_SIZE;
79 pte++;
80 } while (address < curend);
81 } while (address < end);
82}
83
84static inline int io_remap_pmd_range(struct mm_struct *mm, pmd_t * pmd, unsigned long address, unsigned long size,
85 unsigned long offset, pgprot_t prot, int space)
86{
87 unsigned long end;
88
89 address &= ~PGDIR_MASK;
90 end = address + size;
91 if (end > PGDIR_SIZE)
92 end = PGDIR_SIZE;
93 offset -= address;
94 do {
95 pte_t * pte = pte_alloc_map(mm, pmd, address);
96 if (!pte)
97 return -ENOMEM;
98 io_remap_pte_range(mm, pte, address, end - address, address + offset, prot, space);
99 pte_unmap(pte);
100 address = (address + PMD_SIZE) & PMD_MASK;
101 pmd++;
102 } while (address < end);
103 return 0;
104}
105
106static inline int io_remap_pud_range(struct mm_struct *mm, pud_t * pud, unsigned long address, unsigned long size,
107 unsigned long offset, pgprot_t prot, int space)
108{
109 unsigned long end;
110
111 address &= ~PUD_MASK;
112 end = address + size;
113 if (end > PUD_SIZE)
114 end = PUD_SIZE;
115 offset -= address;
116 do {
117 pmd_t *pmd = pmd_alloc(mm, pud, address);
118 if (!pud)
119 return -ENOMEM;
120 io_remap_pmd_range(mm, pmd, address, end - address, address + offset, prot, space);
121 address = (address + PUD_SIZE) & PUD_MASK;
122 pud++;
123 } while (address < end);
124 return 0;
125}
126
127int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
128 unsigned long pfn, unsigned long size, pgprot_t prot)
129{
130 int error = 0;
131 pgd_t * dir;
132 unsigned long beg = from;
133 unsigned long end = from + size;
134 struct mm_struct *mm = vma->vm_mm;
135 int space = GET_IOSPACE(pfn);
136 unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT;
137 unsigned long phys_base;
138
139 phys_base = offset | (((unsigned long) space) << 32UL);
140
141 /* See comment in mm/memory.c remap_pfn_range */
142 vma->vm_flags |= VM_IO | VM_RESERVED | VM_PFNMAP;
143 vma->vm_pgoff = phys_base >> PAGE_SHIFT;
144
145 offset -= from;
146 dir = pgd_offset(mm, from);
147 flush_cache_range(vma, beg, end);
148
149 while (from < end) {
150 pud_t *pud = pud_alloc(mm, dir, from);
151 error = -ENOMEM;
152 if (!pud)
153 break;
154 error = io_remap_pud_range(mm, pud, from, end - from, offset + from, prot, space);
155 if (error)
156 break;
157 from = (from + PGDIR_SIZE) & PGDIR_MASK;
158 dir++;
159 }
160
161 flush_tlb_range(vma, beg, end);
162 return error;
163}
diff --git a/arch/sparc64/mm/hugetlbpage.c b/arch/sparc64/mm/hugetlbpage.c
deleted file mode 100644
index f27d10369e0..00000000000
--- a/arch/sparc64/mm/hugetlbpage.c
+++ /dev/null
@@ -1,357 +0,0 @@
1/*
2 * SPARC64 Huge TLB page support.
3 *
4 * Copyright (C) 2002, 2003, 2006 David S. Miller (davem@davemloft.net)
5 */
6
7#include <linux/init.h>
8#include <linux/module.h>
9#include <linux/fs.h>
10#include <linux/mm.h>
11#include <linux/hugetlb.h>
12#include <linux/pagemap.h>
13#include <linux/slab.h>
14#include <linux/sysctl.h>
15
16#include <asm/mman.h>
17#include <asm/pgalloc.h>
18#include <asm/tlb.h>
19#include <asm/tlbflush.h>
20#include <asm/cacheflush.h>
21#include <asm/mmu_context.h>
22
23/* Slightly simplified from the non-hugepage variant because by
24 * definition we don't have to worry about any page coloring stuff
25 */
26#define VA_EXCLUDE_START (0x0000080000000000UL - (1UL << 32UL))
27#define VA_EXCLUDE_END (0xfffff80000000000UL + (1UL << 32UL))
28
29static unsigned long hugetlb_get_unmapped_area_bottomup(struct file *filp,
30 unsigned long addr,
31 unsigned long len,
32 unsigned long pgoff,
33 unsigned long flags)
34{
35 struct mm_struct *mm = current->mm;
36 struct vm_area_struct * vma;
37 unsigned long task_size = TASK_SIZE;
38 unsigned long start_addr;
39
40 if (test_thread_flag(TIF_32BIT))
41 task_size = STACK_TOP32;
42 if (unlikely(len >= VA_EXCLUDE_START))
43 return -ENOMEM;
44
45 if (len > mm->cached_hole_size) {
46 start_addr = addr = mm->free_area_cache;
47 } else {
48 start_addr = addr = TASK_UNMAPPED_BASE;
49 mm->cached_hole_size = 0;
50 }
51
52 task_size -= len;
53
54full_search:
55 addr = ALIGN(addr, HPAGE_SIZE);
56
57 for (vma = find_vma(mm, addr); ; vma = vma->vm_next) {
58 /* At this point: (!vma || addr < vma->vm_end). */
59 if (addr < VA_EXCLUDE_START &&
60 (addr + len) >= VA_EXCLUDE_START) {
61 addr = VA_EXCLUDE_END;
62 vma = find_vma(mm, VA_EXCLUDE_END);
63 }
64 if (unlikely(task_size < addr)) {
65 if (start_addr != TASK_UNMAPPED_BASE) {
66 start_addr = addr = TASK_UNMAPPED_BASE;
67 mm->cached_hole_size = 0;
68 goto full_search;
69 }
70 return -ENOMEM;
71 }
72 if (likely(!vma || addr + len <= vma->vm_start)) {
73 /*
74 * Remember the place where we stopped the search:
75 */
76 mm->free_area_cache = addr + len;
77 return addr;
78 }
79 if (addr + mm->cached_hole_size < vma->vm_start)
80 mm->cached_hole_size = vma->vm_start - addr;
81
82 addr = ALIGN(vma->vm_end, HPAGE_SIZE);
83 }
84}
85
86static unsigned long
87hugetlb_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
88 const unsigned long len,
89 const unsigned long pgoff,
90 const unsigned long flags)
91{
92 struct vm_area_struct *vma;
93 struct mm_struct *mm = current->mm;
94 unsigned long addr = addr0;
95
96 /* This should only ever run for 32-bit processes. */
97 BUG_ON(!test_thread_flag(TIF_32BIT));
98
99 /* check if free_area_cache is useful for us */
100 if (len <= mm->cached_hole_size) {
101 mm->cached_hole_size = 0;
102 mm->free_area_cache = mm->mmap_base;
103 }
104
105 /* either no address requested or can't fit in requested address hole */
106 addr = mm->free_area_cache & HPAGE_MASK;
107
108 /* make sure it can fit in the remaining address space */
109 if (likely(addr > len)) {
110 vma = find_vma(mm, addr-len);
111 if (!vma || addr <= vma->vm_start) {
112 /* remember the address as a hint for next time */
113 return (mm->free_area_cache = addr-len);
114 }
115 }
116
117 if (unlikely(mm->mmap_base < len))
118 goto bottomup;
119
120 addr = (mm->mmap_base-len) & HPAGE_MASK;
121
122 do {
123 /*
124 * Lookup failure means no vma is above this address,
125 * else if new region fits below vma->vm_start,
126 * return with success:
127 */
128 vma = find_vma(mm, addr);
129 if (likely(!vma || addr+len <= vma->vm_start)) {
130 /* remember the address as a hint for next time */
131 return (mm->free_area_cache = addr);
132 }
133
134 /* remember the largest hole we saw so far */
135 if (addr + mm->cached_hole_size < vma->vm_start)
136 mm->cached_hole_size = vma->vm_start - addr;
137
138 /* try just below the current vma->vm_start */
139 addr = (vma->vm_start-len) & HPAGE_MASK;
140 } while (likely(len < vma->vm_start));
141
142bottomup:
143 /*
144 * A failed mmap() very likely causes application failure,
145 * so fall back to the bottom-up function here. This scenario
146 * can happen with large stack limits and large mmap()
147 * allocations.
148 */
149 mm->cached_hole_size = ~0UL;
150 mm->free_area_cache = TASK_UNMAPPED_BASE;
151 addr = arch_get_unmapped_area(filp, addr0, len, pgoff, flags);
152 /*
153 * Restore the topdown base:
154 */
155 mm->free_area_cache = mm->mmap_base;
156 mm->cached_hole_size = ~0UL;
157
158 return addr;
159}
160
161unsigned long
162hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
163 unsigned long len, unsigned long pgoff, unsigned long flags)
164{
165 struct mm_struct *mm = current->mm;
166 struct vm_area_struct *vma;
167 unsigned long task_size = TASK_SIZE;
168
169 if (test_thread_flag(TIF_32BIT))
170 task_size = STACK_TOP32;
171
172 if (len & ~HPAGE_MASK)
173 return -EINVAL;
174 if (len > task_size)
175 return -ENOMEM;
176
177 if (flags & MAP_FIXED) {
178 if (prepare_hugepage_range(file, addr, len))
179 return -EINVAL;
180 return addr;
181 }
182
183 if (addr) {
184 addr = ALIGN(addr, HPAGE_SIZE);
185 vma = find_vma(mm, addr);
186 if (task_size - len >= addr &&
187 (!vma || addr + len <= vma->vm_start))
188 return addr;
189 }
190 if (mm->get_unmapped_area == arch_get_unmapped_area)
191 return hugetlb_get_unmapped_area_bottomup(file, addr, len,
192 pgoff, flags);
193 else
194 return hugetlb_get_unmapped_area_topdown(file, addr, len,
195 pgoff, flags);
196}
197
198pte_t *huge_pte_alloc(struct mm_struct *mm,
199 unsigned long addr, unsigned long sz)
200{
201 pgd_t *pgd;
202 pud_t *pud;
203 pmd_t *pmd;
204 pte_t *pte = NULL;
205
206 /* We must align the address, because our caller will run
207 * set_huge_pte_at() on whatever we return, which writes out
208 * all of the sub-ptes for the hugepage range. So we have
209 * to give it the first such sub-pte.
210 */
211 addr &= HPAGE_MASK;
212
213 pgd = pgd_offset(mm, addr);
214 pud = pud_alloc(mm, pgd, addr);
215 if (pud) {
216 pmd = pmd_alloc(mm, pud, addr);
217 if (pmd)
218 pte = pte_alloc_map(mm, pmd, addr);
219 }
220 return pte;
221}
222
223pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
224{
225 pgd_t *pgd;
226 pud_t *pud;
227 pmd_t *pmd;
228 pte_t *pte = NULL;
229
230 addr &= HPAGE_MASK;
231
232 pgd = pgd_offset(mm, addr);
233 if (!pgd_none(*pgd)) {
234 pud = pud_offset(pgd, addr);
235 if (!pud_none(*pud)) {
236 pmd = pmd_offset(pud, addr);
237 if (!pmd_none(*pmd))
238 pte = pte_offset_map(pmd, addr);
239 }
240 }
241 return pte;
242}
243
244int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
245{
246 return 0;
247}
248
249void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
250 pte_t *ptep, pte_t entry)
251{
252 int i;
253
254 if (!pte_present(*ptep) && pte_present(entry))
255 mm->context.huge_pte_count++;
256
257 addr &= HPAGE_MASK;
258 for (i = 0; i < (1 << HUGETLB_PAGE_ORDER); i++) {
259 set_pte_at(mm, addr, ptep, entry);
260 ptep++;
261 addr += PAGE_SIZE;
262 pte_val(entry) += PAGE_SIZE;
263 }
264}
265
266pte_t huge_ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
267 pte_t *ptep)
268{
269 pte_t entry;
270 int i;
271
272 entry = *ptep;
273 if (pte_present(entry))
274 mm->context.huge_pte_count--;
275
276 addr &= HPAGE_MASK;
277
278 for (i = 0; i < (1 << HUGETLB_PAGE_ORDER); i++) {
279 pte_clear(mm, addr, ptep);
280 addr += PAGE_SIZE;
281 ptep++;
282 }
283
284 return entry;
285}
286
287struct page *follow_huge_addr(struct mm_struct *mm,
288 unsigned long address, int write)
289{
290 return ERR_PTR(-EINVAL);
291}
292
293int pmd_huge(pmd_t pmd)
294{
295 return 0;
296}
297
298int pud_huge(pud_t pud)
299{
300 return 0;
301}
302
303struct page *follow_huge_pmd(struct mm_struct *mm, unsigned long address,
304 pmd_t *pmd, int write)
305{
306 return NULL;
307}
308
309static void context_reload(void *__data)
310{
311 struct mm_struct *mm = __data;
312
313 if (mm == current->mm)
314 load_secondary_context(mm);
315}
316
317void hugetlb_prefault_arch_hook(struct mm_struct *mm)
318{
319 struct tsb_config *tp = &mm->context.tsb_block[MM_TSB_HUGE];
320
321 if (likely(tp->tsb != NULL))
322 return;
323
324 tsb_grow(mm, MM_TSB_HUGE, 0);
325 tsb_context_switch(mm);
326 smp_tsb_sync(mm);
327
328 /* On UltraSPARC-III+ and later, configure the second half of
329 * the Data-TLB for huge pages.
330 */
331 if (tlb_type == cheetah_plus) {
332 unsigned long ctx;
333
334 spin_lock(&ctx_alloc_lock);
335 ctx = mm->context.sparc64_ctx_val;
336 ctx &= ~CTX_PGSZ_MASK;
337 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
338 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
339
340 if (ctx != mm->context.sparc64_ctx_val) {
341 /* When changing the page size fields, we
342 * must perform a context flush so that no
343 * stale entries match. This flush must
344 * occur with the original context register
345 * settings.
346 */
347 do_flush_tlb_mm(mm);
348
349 /* Reload the context register of all processors
350 * also executing in this address space.
351 */
352 mm->context.sparc64_ctx_val = ctx;
353 on_each_cpu(context_reload, mm, 0);
354 }
355 spin_unlock(&ctx_alloc_lock);
356 }
357}
diff --git a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
deleted file mode 100644
index 185f3467911..00000000000
--- a/arch/sparc64/mm/init.c
+++ /dev/null
@@ -1,2362 +0,0 @@
1/*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/poison.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
23#include <linux/kprobes.h>
24#include <linux/cache.h>
25#include <linux/sort.h>
26#include <linux/percpu.h>
27#include <linux/lmb.h>
28#include <linux/mmzone.h>
29
30#include <asm/head.h>
31#include <asm/system.h>
32#include <asm/page.h>
33#include <asm/pgalloc.h>
34#include <asm/pgtable.h>
35#include <asm/oplib.h>
36#include <asm/iommu.h>
37#include <asm/io.h>
38#include <asm/uaccess.h>
39#include <asm/mmu_context.h>
40#include <asm/tlbflush.h>
41#include <asm/dma.h>
42#include <asm/starfire.h>
43#include <asm/tlb.h>
44#include <asm/spitfire.h>
45#include <asm/sections.h>
46#include <asm/tsb.h>
47#include <asm/hypervisor.h>
48#include <asm/prom.h>
49#include <asm/mdesc.h>
50#include <asm/cpudata.h>
51#include <asm/irq.h>
52
53#include "init.h"
54
55unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57/* A bitmap, one bit for every 256MB of physical memory. If the bit
58 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 */
61unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
63#ifndef CONFIG_DEBUG_PAGEALLOC
64/* A special kernel TSB for 4MB and 256MB linear mappings.
65 * Space is allocated for this right after the trap table
66 * in arch/sparc64/kernel/head.S
67 */
68extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69#endif
70
71#define MAX_BANKS 32
72
73static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
74static int pavail_ents __initdata;
75
76static int cmp_p64(const void *a, const void *b)
77{
78 const struct linux_prom64_registers *x = a, *y = b;
79
80 if (x->phys_addr > y->phys_addr)
81 return 1;
82 if (x->phys_addr < y->phys_addr)
83 return -1;
84 return 0;
85}
86
87static void __init read_obp_memory(const char *property,
88 struct linux_prom64_registers *regs,
89 int *num_ents)
90{
91 int node = prom_finddevice("/memory");
92 int prop_size = prom_getproplen(node, property);
93 int ents, ret, i;
94
95 ents = prop_size / sizeof(struct linux_prom64_registers);
96 if (ents > MAX_BANKS) {
97 prom_printf("The machine has more %s property entries than "
98 "this kernel can support (%d).\n",
99 property, MAX_BANKS);
100 prom_halt();
101 }
102
103 ret = prom_getproperty(node, property, (char *) regs, prop_size);
104 if (ret == -1) {
105 prom_printf("Couldn't get %s property from /memory.\n");
106 prom_halt();
107 }
108
109 /* Sanitize what we got from the firmware, by page aligning
110 * everything.
111 */
112 for (i = 0; i < ents; i++) {
113 unsigned long base, size;
114
115 base = regs[i].phys_addr;
116 size = regs[i].reg_size;
117
118 size &= PAGE_MASK;
119 if (base & ~PAGE_MASK) {
120 unsigned long new_base = PAGE_ALIGN(base);
121
122 size -= new_base - base;
123 if ((long) size < 0L)
124 size = 0UL;
125 base = new_base;
126 }
127 if (size == 0UL) {
128 /* If it is empty, simply get rid of it.
129 * This simplifies the logic of the other
130 * functions that process these arrays.
131 */
132 memmove(&regs[i], &regs[i + 1],
133 (ents - i - 1) * sizeof(regs[0]));
134 i--;
135 ents--;
136 continue;
137 }
138 regs[i].phys_addr = base;
139 regs[i].reg_size = size;
140 }
141
142 *num_ents = ents;
143
144 sort(regs, ents, sizeof(struct linux_prom64_registers),
145 cmp_p64, NULL);
146}
147
148unsigned long *sparc64_valid_addr_bitmap __read_mostly;
149
150/* Kernel physical address base and size in bytes. */
151unsigned long kern_base __read_mostly;
152unsigned long kern_size __read_mostly;
153
154/* Initial ramdisk setup */
155extern unsigned long sparc_ramdisk_image64;
156extern unsigned int sparc_ramdisk_image;
157extern unsigned int sparc_ramdisk_size;
158
159struct page *mem_map_zero __read_mostly;
160EXPORT_SYMBOL(mem_map_zero);
161
162unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
163
164unsigned long sparc64_kern_pri_context __read_mostly;
165unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
166unsigned long sparc64_kern_sec_context __read_mostly;
167
168int num_kernel_image_mappings;
169
170#ifdef CONFIG_DEBUG_DCFLUSH
171atomic_t dcpage_flushes = ATOMIC_INIT(0);
172#ifdef CONFIG_SMP
173atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
174#endif
175#endif
176
177inline void flush_dcache_page_impl(struct page *page)
178{
179 BUG_ON(tlb_type == hypervisor);
180#ifdef CONFIG_DEBUG_DCFLUSH
181 atomic_inc(&dcpage_flushes);
182#endif
183
184#ifdef DCACHE_ALIASING_POSSIBLE
185 __flush_dcache_page(page_address(page),
186 ((tlb_type == spitfire) &&
187 page_mapping(page) != NULL));
188#else
189 if (page_mapping(page) != NULL &&
190 tlb_type == spitfire)
191 __flush_icache_page(__pa(page_address(page)));
192#endif
193}
194
195#define PG_dcache_dirty PG_arch_1
196#define PG_dcache_cpu_shift 32UL
197#define PG_dcache_cpu_mask \
198 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
199
200#define dcache_dirty_cpu(page) \
201 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
202
203static inline void set_dcache_dirty(struct page *page, int this_cpu)
204{
205 unsigned long mask = this_cpu;
206 unsigned long non_cpu_bits;
207
208 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
209 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
210
211 __asm__ __volatile__("1:\n\t"
212 "ldx [%2], %%g7\n\t"
213 "and %%g7, %1, %%g1\n\t"
214 "or %%g1, %0, %%g1\n\t"
215 "casx [%2], %%g7, %%g1\n\t"
216 "cmp %%g7, %%g1\n\t"
217 "membar #StoreLoad | #StoreStore\n\t"
218 "bne,pn %%xcc, 1b\n\t"
219 " nop"
220 : /* no outputs */
221 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
222 : "g1", "g7");
223}
224
225static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
226{
227 unsigned long mask = (1UL << PG_dcache_dirty);
228
229 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
230 "1:\n\t"
231 "ldx [%2], %%g7\n\t"
232 "srlx %%g7, %4, %%g1\n\t"
233 "and %%g1, %3, %%g1\n\t"
234 "cmp %%g1, %0\n\t"
235 "bne,pn %%icc, 2f\n\t"
236 " andn %%g7, %1, %%g1\n\t"
237 "casx [%2], %%g7, %%g1\n\t"
238 "cmp %%g7, %%g1\n\t"
239 "membar #StoreLoad | #StoreStore\n\t"
240 "bne,pn %%xcc, 1b\n\t"
241 " nop\n"
242 "2:"
243 : /* no outputs */
244 : "r" (cpu), "r" (mask), "r" (&page->flags),
245 "i" (PG_dcache_cpu_mask),
246 "i" (PG_dcache_cpu_shift)
247 : "g1", "g7");
248}
249
250static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
251{
252 unsigned long tsb_addr = (unsigned long) ent;
253
254 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
255 tsb_addr = __pa(tsb_addr);
256
257 __tsb_insert(tsb_addr, tag, pte);
258}
259
260unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
261unsigned long _PAGE_SZBITS __read_mostly;
262
263void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
264{
265 struct mm_struct *mm;
266 struct tsb *tsb;
267 unsigned long tag, flags;
268 unsigned long tsb_index, tsb_hash_shift;
269
270 if (tlb_type != hypervisor) {
271 unsigned long pfn = pte_pfn(pte);
272 unsigned long pg_flags;
273 struct page *page;
274
275 if (pfn_valid(pfn) &&
276 (page = pfn_to_page(pfn), page_mapping(page)) &&
277 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
278 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
279 PG_dcache_cpu_mask);
280 int this_cpu = get_cpu();
281
282 /* This is just to optimize away some function calls
283 * in the SMP case.
284 */
285 if (cpu == this_cpu)
286 flush_dcache_page_impl(page);
287 else
288 smp_flush_dcache_page_impl(page, cpu);
289
290 clear_dcache_dirty_cpu(page, cpu);
291
292 put_cpu();
293 }
294 }
295
296 mm = vma->vm_mm;
297
298 tsb_index = MM_TSB_BASE;
299 tsb_hash_shift = PAGE_SHIFT;
300
301 spin_lock_irqsave(&mm->context.lock, flags);
302
303#ifdef CONFIG_HUGETLB_PAGE
304 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
305 if ((tlb_type == hypervisor &&
306 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
307 (tlb_type != hypervisor &&
308 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
309 tsb_index = MM_TSB_HUGE;
310 tsb_hash_shift = HPAGE_SHIFT;
311 }
312 }
313#endif
314
315 tsb = mm->context.tsb_block[tsb_index].tsb;
316 tsb += ((address >> tsb_hash_shift) &
317 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
318 tag = (address >> 22UL);
319 tsb_insert(tsb, tag, pte_val(pte));
320
321 spin_unlock_irqrestore(&mm->context.lock, flags);
322}
323
324void flush_dcache_page(struct page *page)
325{
326 struct address_space *mapping;
327 int this_cpu;
328
329 if (tlb_type == hypervisor)
330 return;
331
332 /* Do not bother with the expensive D-cache flush if it
333 * is merely the zero page. The 'bigcore' testcase in GDB
334 * causes this case to run millions of times.
335 */
336 if (page == ZERO_PAGE(0))
337 return;
338
339 this_cpu = get_cpu();
340
341 mapping = page_mapping(page);
342 if (mapping && !mapping_mapped(mapping)) {
343 int dirty = test_bit(PG_dcache_dirty, &page->flags);
344 if (dirty) {
345 int dirty_cpu = dcache_dirty_cpu(page);
346
347 if (dirty_cpu == this_cpu)
348 goto out;
349 smp_flush_dcache_page_impl(page, dirty_cpu);
350 }
351 set_dcache_dirty(page, this_cpu);
352 } else {
353 /* We could delay the flush for the !page_mapping
354 * case too. But that case is for exec env/arg
355 * pages and those are %99 certainly going to get
356 * faulted into the tlb (and thus flushed) anyways.
357 */
358 flush_dcache_page_impl(page);
359 }
360
361out:
362 put_cpu();
363}
364
365void __kprobes flush_icache_range(unsigned long start, unsigned long end)
366{
367 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
368 if (tlb_type == spitfire) {
369 unsigned long kaddr;
370
371 /* This code only runs on Spitfire cpus so this is
372 * why we can assume _PAGE_PADDR_4U.
373 */
374 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
375 unsigned long paddr, mask = _PAGE_PADDR_4U;
376
377 if (kaddr >= PAGE_OFFSET)
378 paddr = kaddr & mask;
379 else {
380 pgd_t *pgdp = pgd_offset_k(kaddr);
381 pud_t *pudp = pud_offset(pgdp, kaddr);
382 pmd_t *pmdp = pmd_offset(pudp, kaddr);
383 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
384
385 paddr = pte_val(*ptep) & mask;
386 }
387 __flush_icache_page(paddr);
388 }
389 }
390}
391
392void mmu_info(struct seq_file *m)
393{
394 if (tlb_type == cheetah)
395 seq_printf(m, "MMU Type\t: Cheetah\n");
396 else if (tlb_type == cheetah_plus)
397 seq_printf(m, "MMU Type\t: Cheetah+\n");
398 else if (tlb_type == spitfire)
399 seq_printf(m, "MMU Type\t: Spitfire\n");
400 else if (tlb_type == hypervisor)
401 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
402 else
403 seq_printf(m, "MMU Type\t: ???\n");
404
405#ifdef CONFIG_DEBUG_DCFLUSH
406 seq_printf(m, "DCPageFlushes\t: %d\n",
407 atomic_read(&dcpage_flushes));
408#ifdef CONFIG_SMP
409 seq_printf(m, "DCPageFlushesXC\t: %d\n",
410 atomic_read(&dcpage_flushes_xcall));
411#endif /* CONFIG_SMP */
412#endif /* CONFIG_DEBUG_DCFLUSH */
413}
414
415struct linux_prom_translation prom_trans[512] __read_mostly;
416unsigned int prom_trans_ents __read_mostly;
417
418unsigned long kern_locked_tte_data;
419
420/* The obp translations are saved based on 8k pagesize, since obp can
421 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
422 * HI_OBP_ADDRESS range are handled in ktlb.S.
423 */
424static inline int in_obp_range(unsigned long vaddr)
425{
426 return (vaddr >= LOW_OBP_ADDRESS &&
427 vaddr < HI_OBP_ADDRESS);
428}
429
430static int cmp_ptrans(const void *a, const void *b)
431{
432 const struct linux_prom_translation *x = a, *y = b;
433
434 if (x->virt > y->virt)
435 return 1;
436 if (x->virt < y->virt)
437 return -1;
438 return 0;
439}
440
441/* Read OBP translations property into 'prom_trans[]'. */
442static void __init read_obp_translations(void)
443{
444 int n, node, ents, first, last, i;
445
446 node = prom_finddevice("/virtual-memory");
447 n = prom_getproplen(node, "translations");
448 if (unlikely(n == 0 || n == -1)) {
449 prom_printf("prom_mappings: Couldn't get size.\n");
450 prom_halt();
451 }
452 if (unlikely(n > sizeof(prom_trans))) {
453 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
454 prom_halt();
455 }
456
457 if ((n = prom_getproperty(node, "translations",
458 (char *)&prom_trans[0],
459 sizeof(prom_trans))) == -1) {
460 prom_printf("prom_mappings: Couldn't get property.\n");
461 prom_halt();
462 }
463
464 n = n / sizeof(struct linux_prom_translation);
465
466 ents = n;
467
468 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
469 cmp_ptrans, NULL);
470
471 /* Now kick out all the non-OBP entries. */
472 for (i = 0; i < ents; i++) {
473 if (in_obp_range(prom_trans[i].virt))
474 break;
475 }
476 first = i;
477 for (; i < ents; i++) {
478 if (!in_obp_range(prom_trans[i].virt))
479 break;
480 }
481 last = i;
482
483 for (i = 0; i < (last - first); i++) {
484 struct linux_prom_translation *src = &prom_trans[i + first];
485 struct linux_prom_translation *dest = &prom_trans[i];
486
487 *dest = *src;
488 }
489 for (; i < ents; i++) {
490 struct linux_prom_translation *dest = &prom_trans[i];
491 dest->virt = dest->size = dest->data = 0x0UL;
492 }
493
494 prom_trans_ents = last - first;
495
496 if (tlb_type == spitfire) {
497 /* Clear diag TTE bits. */
498 for (i = 0; i < prom_trans_ents; i++)
499 prom_trans[i].data &= ~0x0003fe0000000000UL;
500 }
501}
502
503static void __init hypervisor_tlb_lock(unsigned long vaddr,
504 unsigned long pte,
505 unsigned long mmu)
506{
507 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
508
509 if (ret != 0) {
510 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
511 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
512 prom_halt();
513 }
514}
515
516static unsigned long kern_large_tte(unsigned long paddr);
517
518static void __init remap_kernel(void)
519{
520 unsigned long phys_page, tte_vaddr, tte_data;
521 int i, tlb_ent = sparc64_highest_locked_tlbent();
522
523 tte_vaddr = (unsigned long) KERNBASE;
524 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
525 tte_data = kern_large_tte(phys_page);
526
527 kern_locked_tte_data = tte_data;
528
529 /* Now lock us into the TLBs via Hypervisor or OBP. */
530 if (tlb_type == hypervisor) {
531 for (i = 0; i < num_kernel_image_mappings; i++) {
532 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
533 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
534 tte_vaddr += 0x400000;
535 tte_data += 0x400000;
536 }
537 } else {
538 for (i = 0; i < num_kernel_image_mappings; i++) {
539 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
540 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
541 tte_vaddr += 0x400000;
542 tte_data += 0x400000;
543 }
544 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
545 }
546 if (tlb_type == cheetah_plus) {
547 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
548 CTX_CHEETAH_PLUS_NUC);
549 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
550 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
551 }
552}
553
554
555static void __init inherit_prom_mappings(void)
556{
557 /* Now fixup OBP's idea about where we really are mapped. */
558 printk("Remapping the kernel... ");
559 remap_kernel();
560 printk("done.\n");
561}
562
563void prom_world(int enter)
564{
565 if (!enter)
566 set_fs((mm_segment_t) { get_thread_current_ds() });
567
568 __asm__ __volatile__("flushw");
569}
570
571void __flush_dcache_range(unsigned long start, unsigned long end)
572{
573 unsigned long va;
574
575 if (tlb_type == spitfire) {
576 int n = 0;
577
578 for (va = start; va < end; va += 32) {
579 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
580 if (++n >= 512)
581 break;
582 }
583 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
584 start = __pa(start);
585 end = __pa(end);
586 for (va = start; va < end; va += 32)
587 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
588 "membar #Sync"
589 : /* no outputs */
590 : "r" (va),
591 "i" (ASI_DCACHE_INVALIDATE));
592 }
593}
594
595/* get_new_mmu_context() uses "cache + 1". */
596DEFINE_SPINLOCK(ctx_alloc_lock);
597unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
598#define MAX_CTX_NR (1UL << CTX_NR_BITS)
599#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
600DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
601
602/* Caller does TLB context flushing on local CPU if necessary.
603 * The caller also ensures that CTX_VALID(mm->context) is false.
604 *
605 * We must be careful about boundary cases so that we never
606 * let the user have CTX 0 (nucleus) or we ever use a CTX
607 * version of zero (and thus NO_CONTEXT would not be caught
608 * by version mis-match tests in mmu_context.h).
609 *
610 * Always invoked with interrupts disabled.
611 */
612void get_new_mmu_context(struct mm_struct *mm)
613{
614 unsigned long ctx, new_ctx;
615 unsigned long orig_pgsz_bits;
616 unsigned long flags;
617 int new_version;
618
619 spin_lock_irqsave(&ctx_alloc_lock, flags);
620 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
621 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
622 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
623 new_version = 0;
624 if (new_ctx >= (1 << CTX_NR_BITS)) {
625 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
626 if (new_ctx >= ctx) {
627 int i;
628 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
629 CTX_FIRST_VERSION;
630 if (new_ctx == 1)
631 new_ctx = CTX_FIRST_VERSION;
632
633 /* Don't call memset, for 16 entries that's just
634 * plain silly...
635 */
636 mmu_context_bmap[0] = 3;
637 mmu_context_bmap[1] = 0;
638 mmu_context_bmap[2] = 0;
639 mmu_context_bmap[3] = 0;
640 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
641 mmu_context_bmap[i + 0] = 0;
642 mmu_context_bmap[i + 1] = 0;
643 mmu_context_bmap[i + 2] = 0;
644 mmu_context_bmap[i + 3] = 0;
645 }
646 new_version = 1;
647 goto out;
648 }
649 }
650 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
651 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
652out:
653 tlb_context_cache = new_ctx;
654 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
655 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
656
657 if (unlikely(new_version))
658 smp_new_mmu_context_version();
659}
660
661static int numa_enabled = 1;
662static int numa_debug;
663
664static int __init early_numa(char *p)
665{
666 if (!p)
667 return 0;
668
669 if (strstr(p, "off"))
670 numa_enabled = 0;
671
672 if (strstr(p, "debug"))
673 numa_debug = 1;
674
675 return 0;
676}
677early_param("numa", early_numa);
678
679#define numadbg(f, a...) \
680do { if (numa_debug) \
681 printk(KERN_INFO f, ## a); \
682} while (0)
683
684static void __init find_ramdisk(unsigned long phys_base)
685{
686#ifdef CONFIG_BLK_DEV_INITRD
687 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
688 unsigned long ramdisk_image;
689
690 /* Older versions of the bootloader only supported a
691 * 32-bit physical address for the ramdisk image
692 * location, stored at sparc_ramdisk_image. Newer
693 * SILO versions set sparc_ramdisk_image to zero and
694 * provide a full 64-bit physical address at
695 * sparc_ramdisk_image64.
696 */
697 ramdisk_image = sparc_ramdisk_image;
698 if (!ramdisk_image)
699 ramdisk_image = sparc_ramdisk_image64;
700
701 /* Another bootloader quirk. The bootloader normalizes
702 * the physical address to KERNBASE, so we have to
703 * factor that back out and add in the lowest valid
704 * physical page address to get the true physical address.
705 */
706 ramdisk_image -= KERNBASE;
707 ramdisk_image += phys_base;
708
709 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
710 ramdisk_image, sparc_ramdisk_size);
711
712 initrd_start = ramdisk_image;
713 initrd_end = ramdisk_image + sparc_ramdisk_size;
714
715 lmb_reserve(initrd_start, sparc_ramdisk_size);
716
717 initrd_start += PAGE_OFFSET;
718 initrd_end += PAGE_OFFSET;
719 }
720#endif
721}
722
723struct node_mem_mask {
724 unsigned long mask;
725 unsigned long val;
726 unsigned long bootmem_paddr;
727};
728static struct node_mem_mask node_masks[MAX_NUMNODES];
729static int num_node_masks;
730
731int numa_cpu_lookup_table[NR_CPUS];
732cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
733
734#ifdef CONFIG_NEED_MULTIPLE_NODES
735
736struct mdesc_mblock {
737 u64 base;
738 u64 size;
739 u64 offset; /* RA-to-PA */
740};
741static struct mdesc_mblock *mblocks;
742static int num_mblocks;
743
744static unsigned long ra_to_pa(unsigned long addr)
745{
746 int i;
747
748 for (i = 0; i < num_mblocks; i++) {
749 struct mdesc_mblock *m = &mblocks[i];
750
751 if (addr >= m->base &&
752 addr < (m->base + m->size)) {
753 addr += m->offset;
754 break;
755 }
756 }
757 return addr;
758}
759
760static int find_node(unsigned long addr)
761{
762 int i;
763
764 addr = ra_to_pa(addr);
765 for (i = 0; i < num_node_masks; i++) {
766 struct node_mem_mask *p = &node_masks[i];
767
768 if ((addr & p->mask) == p->val)
769 return i;
770 }
771 return -1;
772}
773
774static unsigned long nid_range(unsigned long start, unsigned long end,
775 int *nid)
776{
777 *nid = find_node(start);
778 start += PAGE_SIZE;
779 while (start < end) {
780 int n = find_node(start);
781
782 if (n != *nid)
783 break;
784 start += PAGE_SIZE;
785 }
786
787 if (start > end)
788 start = end;
789
790 return start;
791}
792#else
793static unsigned long nid_range(unsigned long start, unsigned long end,
794 int *nid)
795{
796 *nid = 0;
797 return end;
798}
799#endif
800
801/* This must be invoked after performing all of the necessary
802 * add_active_range() calls for 'nid'. We need to be able to get
803 * correct data from get_pfn_range_for_nid().
804 */
805static void __init allocate_node_data(int nid)
806{
807 unsigned long paddr, num_pages, start_pfn, end_pfn;
808 struct pglist_data *p;
809
810#ifdef CONFIG_NEED_MULTIPLE_NODES
811 paddr = lmb_alloc_nid(sizeof(struct pglist_data),
812 SMP_CACHE_BYTES, nid, nid_range);
813 if (!paddr) {
814 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
815 prom_halt();
816 }
817 NODE_DATA(nid) = __va(paddr);
818 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
819
820 NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
821#endif
822
823 p = NODE_DATA(nid);
824
825 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
826 p->node_start_pfn = start_pfn;
827 p->node_spanned_pages = end_pfn - start_pfn;
828
829 if (p->node_spanned_pages) {
830 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
831
832 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
833 nid_range);
834 if (!paddr) {
835 prom_printf("Cannot allocate bootmap for nid[%d]\n",
836 nid);
837 prom_halt();
838 }
839 node_masks[nid].bootmem_paddr = paddr;
840 }
841}
842
843static void init_node_masks_nonnuma(void)
844{
845 int i;
846
847 numadbg("Initializing tables for non-numa.\n");
848
849 node_masks[0].mask = node_masks[0].val = 0;
850 num_node_masks = 1;
851
852 for (i = 0; i < NR_CPUS; i++)
853 numa_cpu_lookup_table[i] = 0;
854
855 numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
856}
857
858#ifdef CONFIG_NEED_MULTIPLE_NODES
859struct pglist_data *node_data[MAX_NUMNODES];
860
861EXPORT_SYMBOL(numa_cpu_lookup_table);
862EXPORT_SYMBOL(numa_cpumask_lookup_table);
863EXPORT_SYMBOL(node_data);
864
865struct mdesc_mlgroup {
866 u64 node;
867 u64 latency;
868 u64 match;
869 u64 mask;
870};
871static struct mdesc_mlgroup *mlgroups;
872static int num_mlgroups;
873
874static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
875 u32 cfg_handle)
876{
877 u64 arc;
878
879 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
880 u64 target = mdesc_arc_target(md, arc);
881 const u64 *val;
882
883 val = mdesc_get_property(md, target,
884 "cfg-handle", NULL);
885 if (val && *val == cfg_handle)
886 return 0;
887 }
888 return -ENODEV;
889}
890
891static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
892 u32 cfg_handle)
893{
894 u64 arc, candidate, best_latency = ~(u64)0;
895
896 candidate = MDESC_NODE_NULL;
897 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
898 u64 target = mdesc_arc_target(md, arc);
899 const char *name = mdesc_node_name(md, target);
900 const u64 *val;
901
902 if (strcmp(name, "pio-latency-group"))
903 continue;
904
905 val = mdesc_get_property(md, target, "latency", NULL);
906 if (!val)
907 continue;
908
909 if (*val < best_latency) {
910 candidate = target;
911 best_latency = *val;
912 }
913 }
914
915 if (candidate == MDESC_NODE_NULL)
916 return -ENODEV;
917
918 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
919}
920
921int of_node_to_nid(struct device_node *dp)
922{
923 const struct linux_prom64_registers *regs;
924 struct mdesc_handle *md;
925 u32 cfg_handle;
926 int count, nid;
927 u64 grp;
928
929 /* This is the right thing to do on currently supported
930 * SUN4U NUMA platforms as well, as the PCI controller does
931 * not sit behind any particular memory controller.
932 */
933 if (!mlgroups)
934 return -1;
935
936 regs = of_get_property(dp, "reg", NULL);
937 if (!regs)
938 return -1;
939
940 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
941
942 md = mdesc_grab();
943
944 count = 0;
945 nid = -1;
946 mdesc_for_each_node_by_name(md, grp, "group") {
947 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
948 nid = count;
949 break;
950 }
951 count++;
952 }
953
954 mdesc_release(md);
955
956 return nid;
957}
958
959static void __init add_node_ranges(void)
960{
961 int i;
962
963 for (i = 0; i < lmb.memory.cnt; i++) {
964 unsigned long size = lmb_size_bytes(&lmb.memory, i);
965 unsigned long start, end;
966
967 start = lmb.memory.region[i].base;
968 end = start + size;
969 while (start < end) {
970 unsigned long this_end;
971 int nid;
972
973 this_end = nid_range(start, end, &nid);
974
975 numadbg("Adding active range nid[%d] "
976 "start[%lx] end[%lx]\n",
977 nid, start, this_end);
978
979 add_active_range(nid,
980 start >> PAGE_SHIFT,
981 this_end >> PAGE_SHIFT);
982
983 start = this_end;
984 }
985 }
986}
987
988static int __init grab_mlgroups(struct mdesc_handle *md)
989{
990 unsigned long paddr;
991 int count = 0;
992 u64 node;
993
994 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
995 count++;
996 if (!count)
997 return -ENOENT;
998
999 paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup),
1000 SMP_CACHE_BYTES);
1001 if (!paddr)
1002 return -ENOMEM;
1003
1004 mlgroups = __va(paddr);
1005 num_mlgroups = count;
1006
1007 count = 0;
1008 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1009 struct mdesc_mlgroup *m = &mlgroups[count++];
1010 const u64 *val;
1011
1012 m->node = node;
1013
1014 val = mdesc_get_property(md, node, "latency", NULL);
1015 m->latency = *val;
1016 val = mdesc_get_property(md, node, "address-match", NULL);
1017 m->match = *val;
1018 val = mdesc_get_property(md, node, "address-mask", NULL);
1019 m->mask = *val;
1020
1021 numadbg("MLGROUP[%d]: node[%lx] latency[%lx] "
1022 "match[%lx] mask[%lx]\n",
1023 count - 1, m->node, m->latency, m->match, m->mask);
1024 }
1025
1026 return 0;
1027}
1028
1029static int __init grab_mblocks(struct mdesc_handle *md)
1030{
1031 unsigned long paddr;
1032 int count = 0;
1033 u64 node;
1034
1035 mdesc_for_each_node_by_name(md, node, "mblock")
1036 count++;
1037 if (!count)
1038 return -ENOENT;
1039
1040 paddr = lmb_alloc(count * sizeof(struct mdesc_mblock),
1041 SMP_CACHE_BYTES);
1042 if (!paddr)
1043 return -ENOMEM;
1044
1045 mblocks = __va(paddr);
1046 num_mblocks = count;
1047
1048 count = 0;
1049 mdesc_for_each_node_by_name(md, node, "mblock") {
1050 struct mdesc_mblock *m = &mblocks[count++];
1051 const u64 *val;
1052
1053 val = mdesc_get_property(md, node, "base", NULL);
1054 m->base = *val;
1055 val = mdesc_get_property(md, node, "size", NULL);
1056 m->size = *val;
1057 val = mdesc_get_property(md, node,
1058 "address-congruence-offset", NULL);
1059 m->offset = *val;
1060
1061 numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n",
1062 count - 1, m->base, m->size, m->offset);
1063 }
1064
1065 return 0;
1066}
1067
1068static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1069 u64 grp, cpumask_t *mask)
1070{
1071 u64 arc;
1072
1073 cpus_clear(*mask);
1074
1075 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1076 u64 target = mdesc_arc_target(md, arc);
1077 const char *name = mdesc_node_name(md, target);
1078 const u64 *id;
1079
1080 if (strcmp(name, "cpu"))
1081 continue;
1082 id = mdesc_get_property(md, target, "id", NULL);
1083 if (*id < NR_CPUS)
1084 cpu_set(*id, *mask);
1085 }
1086}
1087
1088static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1089{
1090 int i;
1091
1092 for (i = 0; i < num_mlgroups; i++) {
1093 struct mdesc_mlgroup *m = &mlgroups[i];
1094 if (m->node == node)
1095 return m;
1096 }
1097 return NULL;
1098}
1099
1100static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1101 int index)
1102{
1103 struct mdesc_mlgroup *candidate = NULL;
1104 u64 arc, best_latency = ~(u64)0;
1105 struct node_mem_mask *n;
1106
1107 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1108 u64 target = mdesc_arc_target(md, arc);
1109 struct mdesc_mlgroup *m = find_mlgroup(target);
1110 if (!m)
1111 continue;
1112 if (m->latency < best_latency) {
1113 candidate = m;
1114 best_latency = m->latency;
1115 }
1116 }
1117 if (!candidate)
1118 return -ENOENT;
1119
1120 if (num_node_masks != index) {
1121 printk(KERN_ERR "Inconsistent NUMA state, "
1122 "index[%d] != num_node_masks[%d]\n",
1123 index, num_node_masks);
1124 return -EINVAL;
1125 }
1126
1127 n = &node_masks[num_node_masks++];
1128
1129 n->mask = candidate->mask;
1130 n->val = candidate->match;
1131
1132 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n",
1133 index, n->mask, n->val, candidate->latency);
1134
1135 return 0;
1136}
1137
1138static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1139 int index)
1140{
1141 cpumask_t mask;
1142 int cpu;
1143
1144 numa_parse_mdesc_group_cpus(md, grp, &mask);
1145
1146 for_each_cpu_mask(cpu, mask)
1147 numa_cpu_lookup_table[cpu] = index;
1148 numa_cpumask_lookup_table[index] = mask;
1149
1150 if (numa_debug) {
1151 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1152 for_each_cpu_mask(cpu, mask)
1153 printk("%d ", cpu);
1154 printk("]\n");
1155 }
1156
1157 return numa_attach_mlgroup(md, grp, index);
1158}
1159
1160static int __init numa_parse_mdesc(void)
1161{
1162 struct mdesc_handle *md = mdesc_grab();
1163 int i, err, count;
1164 u64 node;
1165
1166 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1167 if (node == MDESC_NODE_NULL) {
1168 mdesc_release(md);
1169 return -ENOENT;
1170 }
1171
1172 err = grab_mblocks(md);
1173 if (err < 0)
1174 goto out;
1175
1176 err = grab_mlgroups(md);
1177 if (err < 0)
1178 goto out;
1179
1180 count = 0;
1181 mdesc_for_each_node_by_name(md, node, "group") {
1182 err = numa_parse_mdesc_group(md, node, count);
1183 if (err < 0)
1184 break;
1185 count++;
1186 }
1187
1188 add_node_ranges();
1189
1190 for (i = 0; i < num_node_masks; i++) {
1191 allocate_node_data(i);
1192 node_set_online(i);
1193 }
1194
1195 err = 0;
1196out:
1197 mdesc_release(md);
1198 return err;
1199}
1200
1201static int __init numa_parse_jbus(void)
1202{
1203 unsigned long cpu, index;
1204
1205 /* NUMA node id is encoded in bits 36 and higher, and there is
1206 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1207 */
1208 index = 0;
1209 for_each_present_cpu(cpu) {
1210 numa_cpu_lookup_table[cpu] = index;
1211 numa_cpumask_lookup_table[index] = cpumask_of_cpu(cpu);
1212 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1213 node_masks[index].val = cpu << 36UL;
1214
1215 index++;
1216 }
1217 num_node_masks = index;
1218
1219 add_node_ranges();
1220
1221 for (index = 0; index < num_node_masks; index++) {
1222 allocate_node_data(index);
1223 node_set_online(index);
1224 }
1225
1226 return 0;
1227}
1228
1229static int __init numa_parse_sun4u(void)
1230{
1231 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1232 unsigned long ver;
1233
1234 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1235 if ((ver >> 32UL) == __JALAPENO_ID ||
1236 (ver >> 32UL) == __SERRANO_ID)
1237 return numa_parse_jbus();
1238 }
1239 return -1;
1240}
1241
1242static int __init bootmem_init_numa(void)
1243{
1244 int err = -1;
1245
1246 numadbg("bootmem_init_numa()\n");
1247
1248 if (numa_enabled) {
1249 if (tlb_type == hypervisor)
1250 err = numa_parse_mdesc();
1251 else
1252 err = numa_parse_sun4u();
1253 }
1254 return err;
1255}
1256
1257#else
1258
1259static int bootmem_init_numa(void)
1260{
1261 return -1;
1262}
1263
1264#endif
1265
1266static void __init bootmem_init_nonnuma(void)
1267{
1268 unsigned long top_of_ram = lmb_end_of_DRAM();
1269 unsigned long total_ram = lmb_phys_mem_size();
1270 unsigned int i;
1271
1272 numadbg("bootmem_init_nonnuma()\n");
1273
1274 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1275 top_of_ram, total_ram);
1276 printk(KERN_INFO "Memory hole size: %ldMB\n",
1277 (top_of_ram - total_ram) >> 20);
1278
1279 init_node_masks_nonnuma();
1280
1281 for (i = 0; i < lmb.memory.cnt; i++) {
1282 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1283 unsigned long start_pfn, end_pfn;
1284
1285 if (!size)
1286 continue;
1287
1288 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
1289 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
1290 add_active_range(0, start_pfn, end_pfn);
1291 }
1292
1293 allocate_node_data(0);
1294
1295 node_set_online(0);
1296}
1297
1298static void __init reserve_range_in_node(int nid, unsigned long start,
1299 unsigned long end)
1300{
1301 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1302 nid, start, end);
1303 while (start < end) {
1304 unsigned long this_end;
1305 int n;
1306
1307 this_end = nid_range(start, end, &n);
1308 if (n == nid) {
1309 numadbg(" MATCH reserving range [%lx:%lx]\n",
1310 start, this_end);
1311 reserve_bootmem_node(NODE_DATA(nid), start,
1312 (this_end - start), BOOTMEM_DEFAULT);
1313 } else
1314 numadbg(" NO MATCH, advancing start to %lx\n",
1315 this_end);
1316
1317 start = this_end;
1318 }
1319}
1320
1321static void __init trim_reserved_in_node(int nid)
1322{
1323 int i;
1324
1325 numadbg(" trim_reserved_in_node(%d)\n", nid);
1326
1327 for (i = 0; i < lmb.reserved.cnt; i++) {
1328 unsigned long start = lmb.reserved.region[i].base;
1329 unsigned long size = lmb_size_bytes(&lmb.reserved, i);
1330 unsigned long end = start + size;
1331
1332 reserve_range_in_node(nid, start, end);
1333 }
1334}
1335
1336static void __init bootmem_init_one_node(int nid)
1337{
1338 struct pglist_data *p;
1339
1340 numadbg("bootmem_init_one_node(%d)\n", nid);
1341
1342 p = NODE_DATA(nid);
1343
1344 if (p->node_spanned_pages) {
1345 unsigned long paddr = node_masks[nid].bootmem_paddr;
1346 unsigned long end_pfn;
1347
1348 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1349
1350 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1351 nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1352
1353 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1354 p->node_start_pfn, end_pfn);
1355
1356 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1357 nid, end_pfn);
1358 free_bootmem_with_active_regions(nid, end_pfn);
1359
1360 trim_reserved_in_node(nid);
1361
1362 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1363 nid);
1364 sparse_memory_present_with_active_regions(nid);
1365 }
1366}
1367
1368static unsigned long __init bootmem_init(unsigned long phys_base)
1369{
1370 unsigned long end_pfn;
1371 int nid;
1372
1373 end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
1374 max_pfn = max_low_pfn = end_pfn;
1375 min_low_pfn = (phys_base >> PAGE_SHIFT);
1376
1377 if (bootmem_init_numa() < 0)
1378 bootmem_init_nonnuma();
1379
1380 /* XXX cpu notifier XXX */
1381
1382 for_each_online_node(nid)
1383 bootmem_init_one_node(nid);
1384
1385 sparse_init();
1386
1387 return end_pfn;
1388}
1389
1390static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1391static int pall_ents __initdata;
1392
1393#ifdef CONFIG_DEBUG_PAGEALLOC
1394static unsigned long __ref kernel_map_range(unsigned long pstart,
1395 unsigned long pend, pgprot_t prot)
1396{
1397 unsigned long vstart = PAGE_OFFSET + pstart;
1398 unsigned long vend = PAGE_OFFSET + pend;
1399 unsigned long alloc_bytes = 0UL;
1400
1401 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1402 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1403 vstart, vend);
1404 prom_halt();
1405 }
1406
1407 while (vstart < vend) {
1408 unsigned long this_end, paddr = __pa(vstart);
1409 pgd_t *pgd = pgd_offset_k(vstart);
1410 pud_t *pud;
1411 pmd_t *pmd;
1412 pte_t *pte;
1413
1414 pud = pud_offset(pgd, vstart);
1415 if (pud_none(*pud)) {
1416 pmd_t *new;
1417
1418 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1419 alloc_bytes += PAGE_SIZE;
1420 pud_populate(&init_mm, pud, new);
1421 }
1422
1423 pmd = pmd_offset(pud, vstart);
1424 if (!pmd_present(*pmd)) {
1425 pte_t *new;
1426
1427 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1428 alloc_bytes += PAGE_SIZE;
1429 pmd_populate_kernel(&init_mm, pmd, new);
1430 }
1431
1432 pte = pte_offset_kernel(pmd, vstart);
1433 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1434 if (this_end > vend)
1435 this_end = vend;
1436
1437 while (vstart < this_end) {
1438 pte_val(*pte) = (paddr | pgprot_val(prot));
1439
1440 vstart += PAGE_SIZE;
1441 paddr += PAGE_SIZE;
1442 pte++;
1443 }
1444 }
1445
1446 return alloc_bytes;
1447}
1448
1449extern unsigned int kvmap_linear_patch[1];
1450#endif /* CONFIG_DEBUG_PAGEALLOC */
1451
1452static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1453{
1454 const unsigned long shift_256MB = 28;
1455 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1456 const unsigned long size_256MB = (1UL << shift_256MB);
1457
1458 while (start < end) {
1459 long remains;
1460
1461 remains = end - start;
1462 if (remains < size_256MB)
1463 break;
1464
1465 if (start & mask_256MB) {
1466 start = (start + size_256MB) & ~mask_256MB;
1467 continue;
1468 }
1469
1470 while (remains >= size_256MB) {
1471 unsigned long index = start >> shift_256MB;
1472
1473 __set_bit(index, kpte_linear_bitmap);
1474
1475 start += size_256MB;
1476 remains -= size_256MB;
1477 }
1478 }
1479}
1480
1481static void __init init_kpte_bitmap(void)
1482{
1483 unsigned long i;
1484
1485 for (i = 0; i < pall_ents; i++) {
1486 unsigned long phys_start, phys_end;
1487
1488 phys_start = pall[i].phys_addr;
1489 phys_end = phys_start + pall[i].reg_size;
1490
1491 mark_kpte_bitmap(phys_start, phys_end);
1492 }
1493}
1494
1495static void __init kernel_physical_mapping_init(void)
1496{
1497#ifdef CONFIG_DEBUG_PAGEALLOC
1498 unsigned long i, mem_alloced = 0UL;
1499
1500 for (i = 0; i < pall_ents; i++) {
1501 unsigned long phys_start, phys_end;
1502
1503 phys_start = pall[i].phys_addr;
1504 phys_end = phys_start + pall[i].reg_size;
1505
1506 mem_alloced += kernel_map_range(phys_start, phys_end,
1507 PAGE_KERNEL);
1508 }
1509
1510 printk("Allocated %ld bytes for kernel page tables.\n",
1511 mem_alloced);
1512
1513 kvmap_linear_patch[0] = 0x01000000; /* nop */
1514 flushi(&kvmap_linear_patch[0]);
1515
1516 __flush_tlb_all();
1517#endif
1518}
1519
1520#ifdef CONFIG_DEBUG_PAGEALLOC
1521void kernel_map_pages(struct page *page, int numpages, int enable)
1522{
1523 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1524 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1525
1526 kernel_map_range(phys_start, phys_end,
1527 (enable ? PAGE_KERNEL : __pgprot(0)));
1528
1529 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1530 PAGE_OFFSET + phys_end);
1531
1532 /* we should perform an IPI and flush all tlbs,
1533 * but that can deadlock->flush only current cpu.
1534 */
1535 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1536 PAGE_OFFSET + phys_end);
1537}
1538#endif
1539
1540unsigned long __init find_ecache_flush_span(unsigned long size)
1541{
1542 int i;
1543
1544 for (i = 0; i < pavail_ents; i++) {
1545 if (pavail[i].reg_size >= size)
1546 return pavail[i].phys_addr;
1547 }
1548
1549 return ~0UL;
1550}
1551
1552static void __init tsb_phys_patch(void)
1553{
1554 struct tsb_ldquad_phys_patch_entry *pquad;
1555 struct tsb_phys_patch_entry *p;
1556
1557 pquad = &__tsb_ldquad_phys_patch;
1558 while (pquad < &__tsb_ldquad_phys_patch_end) {
1559 unsigned long addr = pquad->addr;
1560
1561 if (tlb_type == hypervisor)
1562 *(unsigned int *) addr = pquad->sun4v_insn;
1563 else
1564 *(unsigned int *) addr = pquad->sun4u_insn;
1565 wmb();
1566 __asm__ __volatile__("flush %0"
1567 : /* no outputs */
1568 : "r" (addr));
1569
1570 pquad++;
1571 }
1572
1573 p = &__tsb_phys_patch;
1574 while (p < &__tsb_phys_patch_end) {
1575 unsigned long addr = p->addr;
1576
1577 *(unsigned int *) addr = p->insn;
1578 wmb();
1579 __asm__ __volatile__("flush %0"
1580 : /* no outputs */
1581 : "r" (addr));
1582
1583 p++;
1584 }
1585}
1586
1587/* Don't mark as init, we give this to the Hypervisor. */
1588#ifndef CONFIG_DEBUG_PAGEALLOC
1589#define NUM_KTSB_DESCR 2
1590#else
1591#define NUM_KTSB_DESCR 1
1592#endif
1593static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1594extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1595
1596static void __init sun4v_ktsb_init(void)
1597{
1598 unsigned long ktsb_pa;
1599
1600 /* First KTSB for PAGE_SIZE mappings. */
1601 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1602
1603 switch (PAGE_SIZE) {
1604 case 8 * 1024:
1605 default:
1606 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1607 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1608 break;
1609
1610 case 64 * 1024:
1611 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1612 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1613 break;
1614
1615 case 512 * 1024:
1616 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1617 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1618 break;
1619
1620 case 4 * 1024 * 1024:
1621 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1622 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1623 break;
1624 };
1625
1626 ktsb_descr[0].assoc = 1;
1627 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1628 ktsb_descr[0].ctx_idx = 0;
1629 ktsb_descr[0].tsb_base = ktsb_pa;
1630 ktsb_descr[0].resv = 0;
1631
1632#ifndef CONFIG_DEBUG_PAGEALLOC
1633 /* Second KTSB for 4MB/256MB mappings. */
1634 ktsb_pa = (kern_base +
1635 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1636
1637 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1638 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1639 HV_PGSZ_MASK_256MB);
1640 ktsb_descr[1].assoc = 1;
1641 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1642 ktsb_descr[1].ctx_idx = 0;
1643 ktsb_descr[1].tsb_base = ktsb_pa;
1644 ktsb_descr[1].resv = 0;
1645#endif
1646}
1647
1648void __cpuinit sun4v_ktsb_register(void)
1649{
1650 unsigned long pa, ret;
1651
1652 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1653
1654 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1655 if (ret != 0) {
1656 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1657 "errors with %lx\n", pa, ret);
1658 prom_halt();
1659 }
1660}
1661
1662/* paging_init() sets up the page tables */
1663
1664static unsigned long last_valid_pfn;
1665pgd_t swapper_pg_dir[2048];
1666
1667static void sun4u_pgprot_init(void);
1668static void sun4v_pgprot_init(void);
1669
1670/* Dummy function */
1671void __init setup_per_cpu_areas(void)
1672{
1673}
1674
1675void __init paging_init(void)
1676{
1677 unsigned long end_pfn, shift, phys_base;
1678 unsigned long real_end, i;
1679
1680 /* These build time checkes make sure that the dcache_dirty_cpu()
1681 * page->flags usage will work.
1682 *
1683 * When a page gets marked as dcache-dirty, we store the
1684 * cpu number starting at bit 32 in the page->flags. Also,
1685 * functions like clear_dcache_dirty_cpu use the cpu mask
1686 * in 13-bit signed-immediate instruction fields.
1687 */
1688
1689 /*
1690 * Page flags must not reach into upper 32 bits that are used
1691 * for the cpu number
1692 */
1693 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1694
1695 /*
1696 * The bit fields placed in the high range must not reach below
1697 * the 32 bit boundary. Otherwise we cannot place the cpu field
1698 * at the 32 bit boundary.
1699 */
1700 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1701 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1702
1703 BUILD_BUG_ON(NR_CPUS > 4096);
1704
1705 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1706 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1707
1708 /* Invalidate both kernel TSBs. */
1709 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1710#ifndef CONFIG_DEBUG_PAGEALLOC
1711 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1712#endif
1713
1714 if (tlb_type == hypervisor)
1715 sun4v_pgprot_init();
1716 else
1717 sun4u_pgprot_init();
1718
1719 if (tlb_type == cheetah_plus ||
1720 tlb_type == hypervisor)
1721 tsb_phys_patch();
1722
1723 if (tlb_type == hypervisor) {
1724 sun4v_patch_tlb_handlers();
1725 sun4v_ktsb_init();
1726 }
1727
1728 lmb_init();
1729
1730 /* Find available physical memory...
1731 *
1732 * Read it twice in order to work around a bug in openfirmware.
1733 * The call to grab this table itself can cause openfirmware to
1734 * allocate memory, which in turn can take away some space from
1735 * the list of available memory. Reading it twice makes sure
1736 * we really do get the final value.
1737 */
1738 read_obp_translations();
1739 read_obp_memory("reg", &pall[0], &pall_ents);
1740 read_obp_memory("available", &pavail[0], &pavail_ents);
1741 read_obp_memory("available", &pavail[0], &pavail_ents);
1742
1743 phys_base = 0xffffffffffffffffUL;
1744 for (i = 0; i < pavail_ents; i++) {
1745 phys_base = min(phys_base, pavail[i].phys_addr);
1746 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1747 }
1748
1749 lmb_reserve(kern_base, kern_size);
1750
1751 find_ramdisk(phys_base);
1752
1753 lmb_enforce_memory_limit(cmdline_memory_size);
1754
1755 lmb_analyze();
1756 lmb_dump_all();
1757
1758 set_bit(0, mmu_context_bmap);
1759
1760 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1761
1762 real_end = (unsigned long)_end;
1763 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1764 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1765 num_kernel_image_mappings);
1766
1767 /* Set kernel pgd to upper alias so physical page computations
1768 * work.
1769 */
1770 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1771
1772 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1773
1774 /* Now can init the kernel/bad page tables. */
1775 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1776 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1777
1778 inherit_prom_mappings();
1779
1780 init_kpte_bitmap();
1781
1782 /* Ok, we can use our TLB miss and window trap handlers safely. */
1783 setup_tba();
1784
1785 __flush_tlb_all();
1786
1787 if (tlb_type == hypervisor)
1788 sun4v_ktsb_register();
1789
1790 /* We must setup the per-cpu areas before we pull in the
1791 * PROM and the MDESC. The code there fills in cpu and
1792 * other information into per-cpu data structures.
1793 */
1794 real_setup_per_cpu_areas();
1795
1796 prom_build_devicetree();
1797
1798 if (tlb_type == hypervisor)
1799 sun4v_mdesc_init();
1800
1801 /* Once the OF device tree and MDESC have been setup, we know
1802 * the list of possible cpus. Therefore we can allocate the
1803 * IRQ stacks.
1804 */
1805 for_each_possible_cpu(i) {
1806 /* XXX Use node local allocations... XXX */
1807 softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1808 hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1809 }
1810
1811 /* Setup bootmem... */
1812 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1813
1814#ifndef CONFIG_NEED_MULTIPLE_NODES
1815 max_mapnr = last_valid_pfn;
1816#endif
1817 kernel_physical_mapping_init();
1818
1819 {
1820 unsigned long max_zone_pfns[MAX_NR_ZONES];
1821
1822 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1823
1824 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1825
1826 free_area_init_nodes(max_zone_pfns);
1827 }
1828
1829 printk("Booting Linux...\n");
1830}
1831
1832int __init page_in_phys_avail(unsigned long paddr)
1833{
1834 int i;
1835
1836 paddr &= PAGE_MASK;
1837
1838 for (i = 0; i < pavail_ents; i++) {
1839 unsigned long start, end;
1840
1841 start = pavail[i].phys_addr;
1842 end = start + pavail[i].reg_size;
1843
1844 if (paddr >= start && paddr < end)
1845 return 1;
1846 }
1847 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1848 return 1;
1849#ifdef CONFIG_BLK_DEV_INITRD
1850 if (paddr >= __pa(initrd_start) &&
1851 paddr < __pa(PAGE_ALIGN(initrd_end)))
1852 return 1;
1853#endif
1854
1855 return 0;
1856}
1857
1858static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1859static int pavail_rescan_ents __initdata;
1860
1861/* Certain OBP calls, such as fetching "available" properties, can
1862 * claim physical memory. So, along with initializing the valid
1863 * address bitmap, what we do here is refetch the physical available
1864 * memory list again, and make sure it provides at least as much
1865 * memory as 'pavail' does.
1866 */
1867static void __init setup_valid_addr_bitmap_from_pavail(void)
1868{
1869 int i;
1870
1871 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1872
1873 for (i = 0; i < pavail_ents; i++) {
1874 unsigned long old_start, old_end;
1875
1876 old_start = pavail[i].phys_addr;
1877 old_end = old_start + pavail[i].reg_size;
1878 while (old_start < old_end) {
1879 int n;
1880
1881 for (n = 0; n < pavail_rescan_ents; n++) {
1882 unsigned long new_start, new_end;
1883
1884 new_start = pavail_rescan[n].phys_addr;
1885 new_end = new_start +
1886 pavail_rescan[n].reg_size;
1887
1888 if (new_start <= old_start &&
1889 new_end >= (old_start + PAGE_SIZE)) {
1890 set_bit(old_start >> 22,
1891 sparc64_valid_addr_bitmap);
1892 goto do_next_page;
1893 }
1894 }
1895
1896 prom_printf("mem_init: Lost memory in pavail\n");
1897 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1898 pavail[i].phys_addr,
1899 pavail[i].reg_size);
1900 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1901 pavail_rescan[i].phys_addr,
1902 pavail_rescan[i].reg_size);
1903 prom_printf("mem_init: Cannot continue, aborting.\n");
1904 prom_halt();
1905
1906 do_next_page:
1907 old_start += PAGE_SIZE;
1908 }
1909 }
1910}
1911
1912void __init mem_init(void)
1913{
1914 unsigned long codepages, datapages, initpages;
1915 unsigned long addr, last;
1916 int i;
1917
1918 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1919 i += 1;
1920 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1921 if (sparc64_valid_addr_bitmap == NULL) {
1922 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1923 prom_halt();
1924 }
1925 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1926
1927 addr = PAGE_OFFSET + kern_base;
1928 last = PAGE_ALIGN(kern_size) + addr;
1929 while (addr < last) {
1930 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1931 addr += PAGE_SIZE;
1932 }
1933
1934 setup_valid_addr_bitmap_from_pavail();
1935
1936 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1937
1938#ifdef CONFIG_NEED_MULTIPLE_NODES
1939 for_each_online_node(i) {
1940 if (NODE_DATA(i)->node_spanned_pages != 0) {
1941 totalram_pages +=
1942 free_all_bootmem_node(NODE_DATA(i));
1943 }
1944 }
1945#else
1946 totalram_pages = free_all_bootmem();
1947#endif
1948
1949 /* We subtract one to account for the mem_map_zero page
1950 * allocated below.
1951 */
1952 totalram_pages -= 1;
1953 num_physpages = totalram_pages;
1954
1955 /*
1956 * Set up the zero page, mark it reserved, so that page count
1957 * is not manipulated when freeing the page from user ptes.
1958 */
1959 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1960 if (mem_map_zero == NULL) {
1961 prom_printf("paging_init: Cannot alloc zero page.\n");
1962 prom_halt();
1963 }
1964 SetPageReserved(mem_map_zero);
1965
1966 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1967 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1968 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1969 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1970 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1971 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1972
1973 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1974 nr_free_pages() << (PAGE_SHIFT-10),
1975 codepages << (PAGE_SHIFT-10),
1976 datapages << (PAGE_SHIFT-10),
1977 initpages << (PAGE_SHIFT-10),
1978 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1979
1980 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1981 cheetah_ecache_flush_init();
1982}
1983
1984void free_initmem(void)
1985{
1986 unsigned long addr, initend;
1987 int do_free = 1;
1988
1989 /* If the physical memory maps were trimmed by kernel command
1990 * line options, don't even try freeing this initmem stuff up.
1991 * The kernel image could have been in the trimmed out region
1992 * and if so the freeing below will free invalid page structs.
1993 */
1994 if (cmdline_memory_size)
1995 do_free = 0;
1996
1997 /*
1998 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1999 */
2000 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2001 initend = (unsigned long)(__init_end) & PAGE_MASK;
2002 for (; addr < initend; addr += PAGE_SIZE) {
2003 unsigned long page;
2004 struct page *p;
2005
2006 page = (addr +
2007 ((unsigned long) __va(kern_base)) -
2008 ((unsigned long) KERNBASE));
2009 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2010
2011 if (do_free) {
2012 p = virt_to_page(page);
2013
2014 ClearPageReserved(p);
2015 init_page_count(p);
2016 __free_page(p);
2017 num_physpages++;
2018 totalram_pages++;
2019 }
2020 }
2021}
2022
2023#ifdef CONFIG_BLK_DEV_INITRD
2024void free_initrd_mem(unsigned long start, unsigned long end)
2025{
2026 if (start < end)
2027 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2028 for (; start < end; start += PAGE_SIZE) {
2029 struct page *p = virt_to_page(start);
2030
2031 ClearPageReserved(p);
2032 init_page_count(p);
2033 __free_page(p);
2034 num_physpages++;
2035 totalram_pages++;
2036 }
2037}
2038#endif
2039
2040#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2041#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2042#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2043#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2044#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2045#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2046
2047pgprot_t PAGE_KERNEL __read_mostly;
2048EXPORT_SYMBOL(PAGE_KERNEL);
2049
2050pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2051pgprot_t PAGE_COPY __read_mostly;
2052
2053pgprot_t PAGE_SHARED __read_mostly;
2054EXPORT_SYMBOL(PAGE_SHARED);
2055
2056unsigned long pg_iobits __read_mostly;
2057
2058unsigned long _PAGE_IE __read_mostly;
2059EXPORT_SYMBOL(_PAGE_IE);
2060
2061unsigned long _PAGE_E __read_mostly;
2062EXPORT_SYMBOL(_PAGE_E);
2063
2064unsigned long _PAGE_CACHE __read_mostly;
2065EXPORT_SYMBOL(_PAGE_CACHE);
2066
2067#ifdef CONFIG_SPARSEMEM_VMEMMAP
2068unsigned long vmemmap_table[VMEMMAP_SIZE];
2069
2070int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2071{
2072 unsigned long vstart = (unsigned long) start;
2073 unsigned long vend = (unsigned long) (start + nr);
2074 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2075 unsigned long phys_end = (vend - VMEMMAP_BASE);
2076 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2077 unsigned long end = VMEMMAP_ALIGN(phys_end);
2078 unsigned long pte_base;
2079
2080 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2081 _PAGE_CP_4U | _PAGE_CV_4U |
2082 _PAGE_P_4U | _PAGE_W_4U);
2083 if (tlb_type == hypervisor)
2084 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2085 _PAGE_CP_4V | _PAGE_CV_4V |
2086 _PAGE_P_4V | _PAGE_W_4V);
2087
2088 for (; addr < end; addr += VMEMMAP_CHUNK) {
2089 unsigned long *vmem_pp =
2090 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2091 void *block;
2092
2093 if (!(*vmem_pp & _PAGE_VALID)) {
2094 block = vmemmap_alloc_block(1UL << 22, node);
2095 if (!block)
2096 return -ENOMEM;
2097
2098 *vmem_pp = pte_base | __pa(block);
2099
2100 printk(KERN_INFO "[%p-%p] page_structs=%lu "
2101 "node=%d entry=%lu/%lu\n", start, block, nr,
2102 node,
2103 addr >> VMEMMAP_CHUNK_SHIFT,
2104 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
2105 }
2106 }
2107 return 0;
2108}
2109#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2110
2111static void prot_init_common(unsigned long page_none,
2112 unsigned long page_shared,
2113 unsigned long page_copy,
2114 unsigned long page_readonly,
2115 unsigned long page_exec_bit)
2116{
2117 PAGE_COPY = __pgprot(page_copy);
2118 PAGE_SHARED = __pgprot(page_shared);
2119
2120 protection_map[0x0] = __pgprot(page_none);
2121 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2122 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2123 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2124 protection_map[0x4] = __pgprot(page_readonly);
2125 protection_map[0x5] = __pgprot(page_readonly);
2126 protection_map[0x6] = __pgprot(page_copy);
2127 protection_map[0x7] = __pgprot(page_copy);
2128 protection_map[0x8] = __pgprot(page_none);
2129 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2130 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2131 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2132 protection_map[0xc] = __pgprot(page_readonly);
2133 protection_map[0xd] = __pgprot(page_readonly);
2134 protection_map[0xe] = __pgprot(page_shared);
2135 protection_map[0xf] = __pgprot(page_shared);
2136}
2137
2138static void __init sun4u_pgprot_init(void)
2139{
2140 unsigned long page_none, page_shared, page_copy, page_readonly;
2141 unsigned long page_exec_bit;
2142
2143 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2144 _PAGE_CACHE_4U | _PAGE_P_4U |
2145 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2146 _PAGE_EXEC_4U);
2147 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2148 _PAGE_CACHE_4U | _PAGE_P_4U |
2149 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2150 _PAGE_EXEC_4U | _PAGE_L_4U);
2151
2152 _PAGE_IE = _PAGE_IE_4U;
2153 _PAGE_E = _PAGE_E_4U;
2154 _PAGE_CACHE = _PAGE_CACHE_4U;
2155
2156 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2157 __ACCESS_BITS_4U | _PAGE_E_4U);
2158
2159#ifdef CONFIG_DEBUG_PAGEALLOC
2160 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2161 0xfffff80000000000UL;
2162#else
2163 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2164 0xfffff80000000000UL;
2165#endif
2166 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2167 _PAGE_P_4U | _PAGE_W_4U);
2168
2169 /* XXX Should use 256MB on Panther. XXX */
2170 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2171
2172 _PAGE_SZBITS = _PAGE_SZBITS_4U;
2173 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2174 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2175 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2176
2177
2178 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2179 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2180 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2181 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2182 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2183 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2184 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2185
2186 page_exec_bit = _PAGE_EXEC_4U;
2187
2188 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2189 page_exec_bit);
2190}
2191
2192static void __init sun4v_pgprot_init(void)
2193{
2194 unsigned long page_none, page_shared, page_copy, page_readonly;
2195 unsigned long page_exec_bit;
2196
2197 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2198 _PAGE_CACHE_4V | _PAGE_P_4V |
2199 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2200 _PAGE_EXEC_4V);
2201 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2202
2203 _PAGE_IE = _PAGE_IE_4V;
2204 _PAGE_E = _PAGE_E_4V;
2205 _PAGE_CACHE = _PAGE_CACHE_4V;
2206
2207#ifdef CONFIG_DEBUG_PAGEALLOC
2208 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2209 0xfffff80000000000UL;
2210#else
2211 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2212 0xfffff80000000000UL;
2213#endif
2214 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2215 _PAGE_P_4V | _PAGE_W_4V);
2216
2217#ifdef CONFIG_DEBUG_PAGEALLOC
2218 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2219 0xfffff80000000000UL;
2220#else
2221 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2222 0xfffff80000000000UL;
2223#endif
2224 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2225 _PAGE_P_4V | _PAGE_W_4V);
2226
2227 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2228 __ACCESS_BITS_4V | _PAGE_E_4V);
2229
2230 _PAGE_SZBITS = _PAGE_SZBITS_4V;
2231 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2232 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2233 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2234 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2235
2236 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2237 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2238 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2239 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2240 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2241 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2242 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2243
2244 page_exec_bit = _PAGE_EXEC_4V;
2245
2246 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2247 page_exec_bit);
2248}
2249
2250unsigned long pte_sz_bits(unsigned long sz)
2251{
2252 if (tlb_type == hypervisor) {
2253 switch (sz) {
2254 case 8 * 1024:
2255 default:
2256 return _PAGE_SZ8K_4V;
2257 case 64 * 1024:
2258 return _PAGE_SZ64K_4V;
2259 case 512 * 1024:
2260 return _PAGE_SZ512K_4V;
2261 case 4 * 1024 * 1024:
2262 return _PAGE_SZ4MB_4V;
2263 };
2264 } else {
2265 switch (sz) {
2266 case 8 * 1024:
2267 default:
2268 return _PAGE_SZ8K_4U;
2269 case 64 * 1024:
2270 return _PAGE_SZ64K_4U;
2271 case 512 * 1024:
2272 return _PAGE_SZ512K_4U;
2273 case 4 * 1024 * 1024:
2274 return _PAGE_SZ4MB_4U;
2275 };
2276 }
2277}
2278
2279pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2280{
2281 pte_t pte;
2282
2283 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2284 pte_val(pte) |= (((unsigned long)space) << 32);
2285 pte_val(pte) |= pte_sz_bits(page_size);
2286
2287 return pte;
2288}
2289
2290static unsigned long kern_large_tte(unsigned long paddr)
2291{
2292 unsigned long val;
2293
2294 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2295 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2296 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2297 if (tlb_type == hypervisor)
2298 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2299 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2300 _PAGE_EXEC_4V | _PAGE_W_4V);
2301
2302 return val | paddr;
2303}
2304
2305/* If not locked, zap it. */
2306void __flush_tlb_all(void)
2307{
2308 unsigned long pstate;
2309 int i;
2310
2311 __asm__ __volatile__("flushw\n\t"
2312 "rdpr %%pstate, %0\n\t"
2313 "wrpr %0, %1, %%pstate"
2314 : "=r" (pstate)
2315 : "i" (PSTATE_IE));
2316 if (tlb_type == hypervisor) {
2317 sun4v_mmu_demap_all();
2318 } else if (tlb_type == spitfire) {
2319 for (i = 0; i < 64; i++) {
2320 /* Spitfire Errata #32 workaround */
2321 /* NOTE: Always runs on spitfire, so no
2322 * cheetah+ page size encodings.
2323 */
2324 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2325 "flush %%g6"
2326 : /* No outputs */
2327 : "r" (0),
2328 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2329
2330 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2331 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2332 "membar #Sync"
2333 : /* no outputs */
2334 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2335 spitfire_put_dtlb_data(i, 0x0UL);
2336 }
2337
2338 /* Spitfire Errata #32 workaround */
2339 /* NOTE: Always runs on spitfire, so no
2340 * cheetah+ page size encodings.
2341 */
2342 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2343 "flush %%g6"
2344 : /* No outputs */
2345 : "r" (0),
2346 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2347
2348 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2349 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2350 "membar #Sync"
2351 : /* no outputs */
2352 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2353 spitfire_put_itlb_data(i, 0x0UL);
2354 }
2355 }
2356 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2357 cheetah_flush_dtlb_all();
2358 cheetah_flush_itlb_all();
2359 }
2360 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2361 : : "r" (pstate));
2362}
diff --git a/arch/sparc64/mm/init.h b/arch/sparc64/mm/init.h
deleted file mode 100644
index 16063870a48..00000000000
--- a/arch/sparc64/mm/init.h
+++ /dev/null
@@ -1,49 +0,0 @@
1#ifndef _SPARC64_MM_INIT_H
2#define _SPARC64_MM_INIT_H
3
4/* Most of the symbols in this file are defined in init.c and
5 * marked non-static so that assembler code can get at them.
6 */
7
8#define MAX_PHYS_ADDRESS (1UL << 42UL)
9#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
10#define KPTE_BITMAP_BYTES \
11 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
12
13extern unsigned long kern_linear_pte_xor[2];
14extern unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
15extern unsigned int sparc64_highest_unlocked_tlb_ent;
16extern unsigned long sparc64_kern_pri_context;
17extern unsigned long sparc64_kern_pri_nuc_bits;
18extern unsigned long sparc64_kern_sec_context;
19extern void mmu_info(struct seq_file *m);
20
21struct linux_prom_translation {
22 unsigned long virt;
23 unsigned long size;
24 unsigned long data;
25};
26
27/* Exported for kernel TLB miss handling in ktlb.S */
28extern struct linux_prom_translation prom_trans[512];
29extern unsigned int prom_trans_ents;
30
31/* Exported for SMP bootup purposes. */
32extern unsigned long kern_locked_tte_data;
33
34extern void prom_world(int enter);
35
36extern void free_initmem(void);
37
38#ifdef CONFIG_SPARSEMEM_VMEMMAP
39#define VMEMMAP_CHUNK_SHIFT 22
40#define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
41#define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
42#define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
43
44#define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
45 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
46extern unsigned long vmemmap_table[VMEMMAP_SIZE];
47#endif
48
49#endif /* _SPARC64_MM_INIT_H */
diff --git a/arch/sparc64/mm/tlb.c b/arch/sparc64/mm/tlb.c
deleted file mode 100644
index d8f21e24a82..00000000000
--- a/arch/sparc64/mm/tlb.c
+++ /dev/null
@@ -1,97 +0,0 @@
1/* arch/sparc64/mm/tlb.c
2 *
3 * Copyright (C) 2004 David S. Miller <davem@redhat.com>
4 */
5
6#include <linux/kernel.h>
7#include <linux/init.h>
8#include <linux/percpu.h>
9#include <linux/mm.h>
10#include <linux/swap.h>
11#include <linux/preempt.h>
12
13#include <asm/pgtable.h>
14#include <asm/pgalloc.h>
15#include <asm/tlbflush.h>
16#include <asm/cacheflush.h>
17#include <asm/mmu_context.h>
18#include <asm/tlb.h>
19
20/* Heavily inspired by the ppc64 code. */
21
22DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
23
24void flush_tlb_pending(void)
25{
26 struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
27
28 if (mp->tlb_nr) {
29 flush_tsb_user(mp);
30
31 if (CTX_VALID(mp->mm->context)) {
32#ifdef CONFIG_SMP
33 smp_flush_tlb_pending(mp->mm, mp->tlb_nr,
34 &mp->vaddrs[0]);
35#else
36 __flush_tlb_pending(CTX_HWBITS(mp->mm->context),
37 mp->tlb_nr, &mp->vaddrs[0]);
38#endif
39 }
40 mp->tlb_nr = 0;
41 }
42
43 put_cpu_var(mmu_gathers);
44}
45
46void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig)
47{
48 struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
49 unsigned long nr;
50
51 vaddr &= PAGE_MASK;
52 if (pte_exec(orig))
53 vaddr |= 0x1UL;
54
55 if (tlb_type != hypervisor &&
56 pte_dirty(orig)) {
57 unsigned long paddr, pfn = pte_pfn(orig);
58 struct address_space *mapping;
59 struct page *page;
60
61 if (!pfn_valid(pfn))
62 goto no_cache_flush;
63
64 page = pfn_to_page(pfn);
65 if (PageReserved(page))
66 goto no_cache_flush;
67
68 /* A real file page? */
69 mapping = page_mapping(page);
70 if (!mapping)
71 goto no_cache_flush;
72
73 paddr = (unsigned long) page_address(page);
74 if ((paddr ^ vaddr) & (1 << 13))
75 flush_dcache_page_all(mm, page);
76 }
77
78no_cache_flush:
79
80 if (mp->fullmm)
81 return;
82
83 nr = mp->tlb_nr;
84
85 if (unlikely(nr != 0 && mm != mp->mm)) {
86 flush_tlb_pending();
87 nr = 0;
88 }
89
90 if (nr == 0)
91 mp->mm = mm;
92
93 mp->vaddrs[nr] = vaddr;
94 mp->tlb_nr = ++nr;
95 if (nr >= TLB_BATCH_NR)
96 flush_tlb_pending();
97}
diff --git a/arch/sparc64/mm/tsb.c b/arch/sparc64/mm/tsb.c
deleted file mode 100644
index 587f8efb2e0..00000000000
--- a/arch/sparc64/mm/tsb.c
+++ /dev/null
@@ -1,498 +0,0 @@
1/* arch/sparc64/mm/tsb.c
2 *
3 * Copyright (C) 2006, 2008 David S. Miller <davem@davemloft.net>
4 */
5
6#include <linux/kernel.h>
7#include <linux/preempt.h>
8#include <asm/system.h>
9#include <asm/page.h>
10#include <asm/tlbflush.h>
11#include <asm/tlb.h>
12#include <asm/mmu_context.h>
13#include <asm/pgtable.h>
14#include <asm/tsb.h>
15#include <asm/oplib.h>
16
17extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
18
19static inline unsigned long tsb_hash(unsigned long vaddr, unsigned long hash_shift, unsigned long nentries)
20{
21 vaddr >>= hash_shift;
22 return vaddr & (nentries - 1);
23}
24
25static inline int tag_compare(unsigned long tag, unsigned long vaddr)
26{
27 return (tag == (vaddr >> 22));
28}
29
30/* TSB flushes need only occur on the processor initiating the address
31 * space modification, not on each cpu the address space has run on.
32 * Only the TLB flush needs that treatment.
33 */
34
35void flush_tsb_kernel_range(unsigned long start, unsigned long end)
36{
37 unsigned long v;
38
39 for (v = start; v < end; v += PAGE_SIZE) {
40 unsigned long hash = tsb_hash(v, PAGE_SHIFT,
41 KERNEL_TSB_NENTRIES);
42 struct tsb *ent = &swapper_tsb[hash];
43
44 if (tag_compare(ent->tag, v)) {
45 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
46 membar_storeload_storestore();
47 }
48 }
49}
50
51static void __flush_tsb_one(struct mmu_gather *mp, unsigned long hash_shift, unsigned long tsb, unsigned long nentries)
52{
53 unsigned long i;
54
55 for (i = 0; i < mp->tlb_nr; i++) {
56 unsigned long v = mp->vaddrs[i];
57 unsigned long tag, ent, hash;
58
59 v &= ~0x1UL;
60
61 hash = tsb_hash(v, hash_shift, nentries);
62 ent = tsb + (hash * sizeof(struct tsb));
63 tag = (v >> 22UL);
64
65 tsb_flush(ent, tag);
66 }
67}
68
69void flush_tsb_user(struct mmu_gather *mp)
70{
71 struct mm_struct *mm = mp->mm;
72 unsigned long nentries, base, flags;
73
74 spin_lock_irqsave(&mm->context.lock, flags);
75
76 base = (unsigned long) mm->context.tsb_block[MM_TSB_BASE].tsb;
77 nentries = mm->context.tsb_block[MM_TSB_BASE].tsb_nentries;
78 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
79 base = __pa(base);
80 __flush_tsb_one(mp, PAGE_SHIFT, base, nentries);
81
82#ifdef CONFIG_HUGETLB_PAGE
83 if (mm->context.tsb_block[MM_TSB_HUGE].tsb) {
84 base = (unsigned long) mm->context.tsb_block[MM_TSB_HUGE].tsb;
85 nentries = mm->context.tsb_block[MM_TSB_HUGE].tsb_nentries;
86 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
87 base = __pa(base);
88 __flush_tsb_one(mp, HPAGE_SHIFT, base, nentries);
89 }
90#endif
91 spin_unlock_irqrestore(&mm->context.lock, flags);
92}
93
94#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
95#define HV_PGSZ_IDX_BASE HV_PGSZ_IDX_8K
96#define HV_PGSZ_MASK_BASE HV_PGSZ_MASK_8K
97#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
98#define HV_PGSZ_IDX_BASE HV_PGSZ_IDX_64K
99#define HV_PGSZ_MASK_BASE HV_PGSZ_MASK_64K
100#else
101#error Broken base page size setting...
102#endif
103
104#ifdef CONFIG_HUGETLB_PAGE
105#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
106#define HV_PGSZ_IDX_HUGE HV_PGSZ_IDX_64K
107#define HV_PGSZ_MASK_HUGE HV_PGSZ_MASK_64K
108#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
109#define HV_PGSZ_IDX_HUGE HV_PGSZ_IDX_512K
110#define HV_PGSZ_MASK_HUGE HV_PGSZ_MASK_512K
111#elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
112#define HV_PGSZ_IDX_HUGE HV_PGSZ_IDX_4MB
113#define HV_PGSZ_MASK_HUGE HV_PGSZ_MASK_4MB
114#else
115#error Broken huge page size setting...
116#endif
117#endif
118
119static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_idx, unsigned long tsb_bytes)
120{
121 unsigned long tsb_reg, base, tsb_paddr;
122 unsigned long page_sz, tte;
123
124 mm->context.tsb_block[tsb_idx].tsb_nentries =
125 tsb_bytes / sizeof(struct tsb);
126
127 base = TSBMAP_BASE;
128 tte = pgprot_val(PAGE_KERNEL_LOCKED);
129 tsb_paddr = __pa(mm->context.tsb_block[tsb_idx].tsb);
130 BUG_ON(tsb_paddr & (tsb_bytes - 1UL));
131
132 /* Use the smallest page size that can map the whole TSB
133 * in one TLB entry.
134 */
135 switch (tsb_bytes) {
136 case 8192 << 0:
137 tsb_reg = 0x0UL;
138#ifdef DCACHE_ALIASING_POSSIBLE
139 base += (tsb_paddr & 8192);
140#endif
141 page_sz = 8192;
142 break;
143
144 case 8192 << 1:
145 tsb_reg = 0x1UL;
146 page_sz = 64 * 1024;
147 break;
148
149 case 8192 << 2:
150 tsb_reg = 0x2UL;
151 page_sz = 64 * 1024;
152 break;
153
154 case 8192 << 3:
155 tsb_reg = 0x3UL;
156 page_sz = 64 * 1024;
157 break;
158
159 case 8192 << 4:
160 tsb_reg = 0x4UL;
161 page_sz = 512 * 1024;
162 break;
163
164 case 8192 << 5:
165 tsb_reg = 0x5UL;
166 page_sz = 512 * 1024;
167 break;
168
169 case 8192 << 6:
170 tsb_reg = 0x6UL;
171 page_sz = 512 * 1024;
172 break;
173
174 case 8192 << 7:
175 tsb_reg = 0x7UL;
176 page_sz = 4 * 1024 * 1024;
177 break;
178
179 default:
180 printk(KERN_ERR "TSB[%s:%d]: Impossible TSB size %lu, killing process.\n",
181 current->comm, current->pid, tsb_bytes);
182 do_exit(SIGSEGV);
183 };
184 tte |= pte_sz_bits(page_sz);
185
186 if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
187 /* Physical mapping, no locked TLB entry for TSB. */
188 tsb_reg |= tsb_paddr;
189
190 mm->context.tsb_block[tsb_idx].tsb_reg_val = tsb_reg;
191 mm->context.tsb_block[tsb_idx].tsb_map_vaddr = 0;
192 mm->context.tsb_block[tsb_idx].tsb_map_pte = 0;
193 } else {
194 tsb_reg |= base;
195 tsb_reg |= (tsb_paddr & (page_sz - 1UL));
196 tte |= (tsb_paddr & ~(page_sz - 1UL));
197
198 mm->context.tsb_block[tsb_idx].tsb_reg_val = tsb_reg;
199 mm->context.tsb_block[tsb_idx].tsb_map_vaddr = base;
200 mm->context.tsb_block[tsb_idx].tsb_map_pte = tte;
201 }
202
203 /* Setup the Hypervisor TSB descriptor. */
204 if (tlb_type == hypervisor) {
205 struct hv_tsb_descr *hp = &mm->context.tsb_descr[tsb_idx];
206
207 switch (tsb_idx) {
208 case MM_TSB_BASE:
209 hp->pgsz_idx = HV_PGSZ_IDX_BASE;
210 break;
211#ifdef CONFIG_HUGETLB_PAGE
212 case MM_TSB_HUGE:
213 hp->pgsz_idx = HV_PGSZ_IDX_HUGE;
214 break;
215#endif
216 default:
217 BUG();
218 };
219 hp->assoc = 1;
220 hp->num_ttes = tsb_bytes / 16;
221 hp->ctx_idx = 0;
222 switch (tsb_idx) {
223 case MM_TSB_BASE:
224 hp->pgsz_mask = HV_PGSZ_MASK_BASE;
225 break;
226#ifdef CONFIG_HUGETLB_PAGE
227 case MM_TSB_HUGE:
228 hp->pgsz_mask = HV_PGSZ_MASK_HUGE;
229 break;
230#endif
231 default:
232 BUG();
233 };
234 hp->tsb_base = tsb_paddr;
235 hp->resv = 0;
236 }
237}
238
239static struct kmem_cache *tsb_caches[8] __read_mostly;
240
241static const char *tsb_cache_names[8] = {
242 "tsb_8KB",
243 "tsb_16KB",
244 "tsb_32KB",
245 "tsb_64KB",
246 "tsb_128KB",
247 "tsb_256KB",
248 "tsb_512KB",
249 "tsb_1MB",
250};
251
252void __init pgtable_cache_init(void)
253{
254 unsigned long i;
255
256 for (i = 0; i < 8; i++) {
257 unsigned long size = 8192 << i;
258 const char *name = tsb_cache_names[i];
259
260 tsb_caches[i] = kmem_cache_create(name,
261 size, size,
262 0, NULL);
263 if (!tsb_caches[i]) {
264 prom_printf("Could not create %s cache\n", name);
265 prom_halt();
266 }
267 }
268}
269
270/* When the RSS of an address space exceeds tsb_rss_limit for a TSB,
271 * do_sparc64_fault() invokes this routine to try and grow it.
272 *
273 * When we reach the maximum TSB size supported, we stick ~0UL into
274 * tsb_rss_limit for that TSB so the grow checks in do_sparc64_fault()
275 * will not trigger any longer.
276 *
277 * The TSB can be anywhere from 8K to 1MB in size, in increasing powers
278 * of two. The TSB must be aligned to it's size, so f.e. a 512K TSB
279 * must be 512K aligned. It also must be physically contiguous, so we
280 * cannot use vmalloc().
281 *
282 * The idea here is to grow the TSB when the RSS of the process approaches
283 * the number of entries that the current TSB can hold at once. Currently,
284 * we trigger when the RSS hits 3/4 of the TSB capacity.
285 */
286void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long rss)
287{
288 unsigned long max_tsb_size = 1 * 1024 * 1024;
289 unsigned long new_size, old_size, flags;
290 struct tsb *old_tsb, *new_tsb;
291 unsigned long new_cache_index, old_cache_index;
292 unsigned long new_rss_limit;
293 gfp_t gfp_flags;
294
295 if (max_tsb_size > (PAGE_SIZE << MAX_ORDER))
296 max_tsb_size = (PAGE_SIZE << MAX_ORDER);
297
298 new_cache_index = 0;
299 for (new_size = 8192; new_size < max_tsb_size; new_size <<= 1UL) {
300 unsigned long n_entries = new_size / sizeof(struct tsb);
301
302 n_entries = (n_entries * 3) / 4;
303 if (n_entries > rss)
304 break;
305
306 new_cache_index++;
307 }
308
309 if (new_size == max_tsb_size)
310 new_rss_limit = ~0UL;
311 else
312 new_rss_limit = ((new_size / sizeof(struct tsb)) * 3) / 4;
313
314retry_tsb_alloc:
315 gfp_flags = GFP_KERNEL;
316 if (new_size > (PAGE_SIZE * 2))
317 gfp_flags = __GFP_NOWARN | __GFP_NORETRY;
318
319 new_tsb = kmem_cache_alloc_node(tsb_caches[new_cache_index],
320 gfp_flags, numa_node_id());
321 if (unlikely(!new_tsb)) {
322 /* Not being able to fork due to a high-order TSB
323 * allocation failure is very bad behavior. Just back
324 * down to a 0-order allocation and force no TSB
325 * growing for this address space.
326 */
327 if (mm->context.tsb_block[tsb_index].tsb == NULL &&
328 new_cache_index > 0) {
329 new_cache_index = 0;
330 new_size = 8192;
331 new_rss_limit = ~0UL;
332 goto retry_tsb_alloc;
333 }
334
335 /* If we failed on a TSB grow, we are under serious
336 * memory pressure so don't try to grow any more.
337 */
338 if (mm->context.tsb_block[tsb_index].tsb != NULL)
339 mm->context.tsb_block[tsb_index].tsb_rss_limit = ~0UL;
340 return;
341 }
342
343 /* Mark all tags as invalid. */
344 tsb_init(new_tsb, new_size);
345
346 /* Ok, we are about to commit the changes. If we are
347 * growing an existing TSB the locking is very tricky,
348 * so WATCH OUT!
349 *
350 * We have to hold mm->context.lock while committing to the
351 * new TSB, this synchronizes us with processors in
352 * flush_tsb_user() and switch_mm() for this address space.
353 *
354 * But even with that lock held, processors run asynchronously
355 * accessing the old TSB via TLB miss handling. This is OK
356 * because those actions are just propagating state from the
357 * Linux page tables into the TSB, page table mappings are not
358 * being changed. If a real fault occurs, the processor will
359 * synchronize with us when it hits flush_tsb_user(), this is
360 * also true for the case where vmscan is modifying the page
361 * tables. The only thing we need to be careful with is to
362 * skip any locked TSB entries during copy_tsb().
363 *
364 * When we finish committing to the new TSB, we have to drop
365 * the lock and ask all other cpus running this address space
366 * to run tsb_context_switch() to see the new TSB table.
367 */
368 spin_lock_irqsave(&mm->context.lock, flags);
369
370 old_tsb = mm->context.tsb_block[tsb_index].tsb;
371 old_cache_index =
372 (mm->context.tsb_block[tsb_index].tsb_reg_val & 0x7UL);
373 old_size = (mm->context.tsb_block[tsb_index].tsb_nentries *
374 sizeof(struct tsb));
375
376
377 /* Handle multiple threads trying to grow the TSB at the same time.
378 * One will get in here first, and bump the size and the RSS limit.
379 * The others will get in here next and hit this check.
380 */
381 if (unlikely(old_tsb &&
382 (rss < mm->context.tsb_block[tsb_index].tsb_rss_limit))) {
383 spin_unlock_irqrestore(&mm->context.lock, flags);
384
385 kmem_cache_free(tsb_caches[new_cache_index], new_tsb);
386 return;
387 }
388
389 mm->context.tsb_block[tsb_index].tsb_rss_limit = new_rss_limit;
390
391 if (old_tsb) {
392 extern void copy_tsb(unsigned long old_tsb_base,
393 unsigned long old_tsb_size,
394 unsigned long new_tsb_base,
395 unsigned long new_tsb_size);
396 unsigned long old_tsb_base = (unsigned long) old_tsb;
397 unsigned long new_tsb_base = (unsigned long) new_tsb;
398
399 if (tlb_type == cheetah_plus || tlb_type == hypervisor) {
400 old_tsb_base = __pa(old_tsb_base);
401 new_tsb_base = __pa(new_tsb_base);
402 }
403 copy_tsb(old_tsb_base, old_size, new_tsb_base, new_size);
404 }
405
406 mm->context.tsb_block[tsb_index].tsb = new_tsb;
407 setup_tsb_params(mm, tsb_index, new_size);
408
409 spin_unlock_irqrestore(&mm->context.lock, flags);
410
411 /* If old_tsb is NULL, we're being invoked for the first time
412 * from init_new_context().
413 */
414 if (old_tsb) {
415 /* Reload it on the local cpu. */
416 tsb_context_switch(mm);
417
418 /* Now force other processors to do the same. */
419 preempt_disable();
420 smp_tsb_sync(mm);
421 preempt_enable();
422
423 /* Now it is safe to free the old tsb. */
424 kmem_cache_free(tsb_caches[old_cache_index], old_tsb);
425 }
426}
427
428int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
429{
430#ifdef CONFIG_HUGETLB_PAGE
431 unsigned long huge_pte_count;
432#endif
433 unsigned int i;
434
435 spin_lock_init(&mm->context.lock);
436
437 mm->context.sparc64_ctx_val = 0UL;
438
439#ifdef CONFIG_HUGETLB_PAGE
440 /* We reset it to zero because the fork() page copying
441 * will re-increment the counters as the parent PTEs are
442 * copied into the child address space.
443 */
444 huge_pte_count = mm->context.huge_pte_count;
445 mm->context.huge_pte_count = 0;
446#endif
447
448 /* copy_mm() copies over the parent's mm_struct before calling
449 * us, so we need to zero out the TSB pointer or else tsb_grow()
450 * will be confused and think there is an older TSB to free up.
451 */
452 for (i = 0; i < MM_NUM_TSBS; i++)
453 mm->context.tsb_block[i].tsb = NULL;
454
455 /* If this is fork, inherit the parent's TSB size. We would
456 * grow it to that size on the first page fault anyways.
457 */
458 tsb_grow(mm, MM_TSB_BASE, get_mm_rss(mm));
459
460#ifdef CONFIG_HUGETLB_PAGE
461 if (unlikely(huge_pte_count))
462 tsb_grow(mm, MM_TSB_HUGE, huge_pte_count);
463#endif
464
465 if (unlikely(!mm->context.tsb_block[MM_TSB_BASE].tsb))
466 return -ENOMEM;
467
468 return 0;
469}
470
471static void tsb_destroy_one(struct tsb_config *tp)
472{
473 unsigned long cache_index;
474
475 if (!tp->tsb)
476 return;
477 cache_index = tp->tsb_reg_val & 0x7UL;
478 kmem_cache_free(tsb_caches[cache_index], tp->tsb);
479 tp->tsb = NULL;
480 tp->tsb_reg_val = 0UL;
481}
482
483void destroy_context(struct mm_struct *mm)
484{
485 unsigned long flags, i;
486
487 for (i = 0; i < MM_NUM_TSBS; i++)
488 tsb_destroy_one(&mm->context.tsb_block[i]);
489
490 spin_lock_irqsave(&ctx_alloc_lock, flags);
491
492 if (CTX_VALID(mm->context)) {
493 unsigned long nr = CTX_NRBITS(mm->context);
494 mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63));
495 }
496
497 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
498}
diff --git a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
deleted file mode 100644
index 86773e89dc1..00000000000
--- a/arch/sparc64/mm/ultra.S
+++ /dev/null
@@ -1,769 +0,0 @@
1/*
2 * ultra.S: Don't expand these all over the place...
3 *
4 * Copyright (C) 1997, 2000, 2008 David S. Miller (davem@davemloft.net)
5 */
6
7#include <asm/asi.h>
8#include <asm/pgtable.h>
9#include <asm/page.h>
10#include <asm/spitfire.h>
11#include <asm/mmu_context.h>
12#include <asm/mmu.h>
13#include <asm/pil.h>
14#include <asm/head.h>
15#include <asm/thread_info.h>
16#include <asm/cacheflush.h>
17#include <asm/hypervisor.h>
18#include <asm/cpudata.h>
19
20 /* Basically, most of the Spitfire vs. Cheetah madness
21 * has to do with the fact that Cheetah does not support
22 * IMMU flushes out of the secondary context. Someone needs
23 * to throw a south lake birthday party for the folks
24 * in Microelectronics who refused to fix this shit.
25 */
26
27 /* This file is meant to be read efficiently by the CPU, not humans.
28 * Staraj sie tego nikomu nie pierdolnac...
29 */
30 .text
31 .align 32
32 .globl __flush_tlb_mm
33__flush_tlb_mm: /* 18 insns */
34 /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */
35 ldxa [%o1] ASI_DMMU, %g2
36 cmp %g2, %o0
37 bne,pn %icc, __spitfire_flush_tlb_mm_slow
38 mov 0x50, %g3
39 stxa %g0, [%g3] ASI_DMMU_DEMAP
40 stxa %g0, [%g3] ASI_IMMU_DEMAP
41 sethi %hi(KERNBASE), %g3
42 flush %g3
43 retl
44 nop
45 nop
46 nop
47 nop
48 nop
49 nop
50 nop
51 nop
52 nop
53 nop
54
55 .align 32
56 .globl __flush_tlb_pending
57__flush_tlb_pending: /* 26 insns */
58 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
59 rdpr %pstate, %g7
60 sllx %o1, 3, %o1
61 andn %g7, PSTATE_IE, %g2
62 wrpr %g2, %pstate
63 mov SECONDARY_CONTEXT, %o4
64 ldxa [%o4] ASI_DMMU, %g2
65 stxa %o0, [%o4] ASI_DMMU
661: sub %o1, (1 << 3), %o1
67 ldx [%o2 + %o1], %o3
68 andcc %o3, 1, %g0
69 andn %o3, 1, %o3
70 be,pn %icc, 2f
71 or %o3, 0x10, %o3
72 stxa %g0, [%o3] ASI_IMMU_DEMAP
732: stxa %g0, [%o3] ASI_DMMU_DEMAP
74 membar #Sync
75 brnz,pt %o1, 1b
76 nop
77 stxa %g2, [%o4] ASI_DMMU
78 sethi %hi(KERNBASE), %o4
79 flush %o4
80 retl
81 wrpr %g7, 0x0, %pstate
82 nop
83 nop
84 nop
85 nop
86
87 .align 32
88 .globl __flush_tlb_kernel_range
89__flush_tlb_kernel_range: /* 16 insns */
90 /* %o0=start, %o1=end */
91 cmp %o0, %o1
92 be,pn %xcc, 2f
93 sethi %hi(PAGE_SIZE), %o4
94 sub %o1, %o0, %o3
95 sub %o3, %o4, %o3
96 or %o0, 0x20, %o0 ! Nucleus
971: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP
98 stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP
99 membar #Sync
100 brnz,pt %o3, 1b
101 sub %o3, %o4, %o3
1022: sethi %hi(KERNBASE), %o3
103 flush %o3
104 retl
105 nop
106 nop
107
108__spitfire_flush_tlb_mm_slow:
109 rdpr %pstate, %g1
110 wrpr %g1, PSTATE_IE, %pstate
111 stxa %o0, [%o1] ASI_DMMU
112 stxa %g0, [%g3] ASI_DMMU_DEMAP
113 stxa %g0, [%g3] ASI_IMMU_DEMAP
114 flush %g6
115 stxa %g2, [%o1] ASI_DMMU
116 sethi %hi(KERNBASE), %o1
117 flush %o1
118 retl
119 wrpr %g1, 0, %pstate
120
121/*
122 * The following code flushes one page_size worth.
123 */
124 .section .kprobes.text, "ax"
125 .align 32
126 .globl __flush_icache_page
127__flush_icache_page: /* %o0 = phys_page */
128 membar #StoreStore
129 srlx %o0, PAGE_SHIFT, %o0
130 sethi %uhi(PAGE_OFFSET), %g1
131 sllx %o0, PAGE_SHIFT, %o0
132 sethi %hi(PAGE_SIZE), %g2
133 sllx %g1, 32, %g1
134 add %o0, %g1, %o0
1351: subcc %g2, 32, %g2
136 bne,pt %icc, 1b
137 flush %o0 + %g2
138 retl
139 nop
140
141#ifdef DCACHE_ALIASING_POSSIBLE
142
143#if (PAGE_SHIFT != 13)
144#error only page shift of 13 is supported by dcache flush
145#endif
146
147#define DTAG_MASK 0x3
148
149 /* This routine is Spitfire specific so the hardcoded
150 * D-cache size and line-size are OK.
151 */
152 .align 64
153 .globl __flush_dcache_page
154__flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
155 sethi %uhi(PAGE_OFFSET), %g1
156 sllx %g1, 32, %g1
157 sub %o0, %g1, %o0 ! physical address
158 srlx %o0, 11, %o0 ! make D-cache TAG
159 sethi %hi(1 << 14), %o2 ! D-cache size
160 sub %o2, (1 << 5), %o2 ! D-cache line size
1611: ldxa [%o2] ASI_DCACHE_TAG, %o3 ! load D-cache TAG
162 andcc %o3, DTAG_MASK, %g0 ! Valid?
163 be,pn %xcc, 2f ! Nope, branch
164 andn %o3, DTAG_MASK, %o3 ! Clear valid bits
165 cmp %o3, %o0 ! TAG match?
166 bne,pt %xcc, 2f ! Nope, branch
167 nop
168 stxa %g0, [%o2] ASI_DCACHE_TAG ! Invalidate TAG
169 membar #Sync
1702: brnz,pt %o2, 1b
171 sub %o2, (1 << 5), %o2 ! D-cache line size
172
173 /* The I-cache does not snoop local stores so we
174 * better flush that too when necessary.
175 */
176 brnz,pt %o1, __flush_icache_page
177 sllx %o0, 11, %o0
178 retl
179 nop
180
181#endif /* DCACHE_ALIASING_POSSIBLE */
182
183 .previous
184
185 /* Cheetah specific versions, patched at boot time. */
186__cheetah_flush_tlb_mm: /* 19 insns */
187 rdpr %pstate, %g7
188 andn %g7, PSTATE_IE, %g2
189 wrpr %g2, 0x0, %pstate
190 wrpr %g0, 1, %tl
191 mov PRIMARY_CONTEXT, %o2
192 mov 0x40, %g3
193 ldxa [%o2] ASI_DMMU, %g2
194 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o1
195 sllx %o1, CTX_PGSZ1_NUC_SHIFT, %o1
196 or %o0, %o1, %o0 /* Preserve nucleus page size fields */
197 stxa %o0, [%o2] ASI_DMMU
198 stxa %g0, [%g3] ASI_DMMU_DEMAP
199 stxa %g0, [%g3] ASI_IMMU_DEMAP
200 stxa %g2, [%o2] ASI_DMMU
201 sethi %hi(KERNBASE), %o2
202 flush %o2
203 wrpr %g0, 0, %tl
204 retl
205 wrpr %g7, 0x0, %pstate
206
207__cheetah_flush_tlb_pending: /* 27 insns */
208 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
209 rdpr %pstate, %g7
210 sllx %o1, 3, %o1
211 andn %g7, PSTATE_IE, %g2
212 wrpr %g2, 0x0, %pstate
213 wrpr %g0, 1, %tl
214 mov PRIMARY_CONTEXT, %o4
215 ldxa [%o4] ASI_DMMU, %g2
216 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3
217 sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3
218 or %o0, %o3, %o0 /* Preserve nucleus page size fields */
219 stxa %o0, [%o4] ASI_DMMU
2201: sub %o1, (1 << 3), %o1
221 ldx [%o2 + %o1], %o3
222 andcc %o3, 1, %g0
223 be,pn %icc, 2f
224 andn %o3, 1, %o3
225 stxa %g0, [%o3] ASI_IMMU_DEMAP
2262: stxa %g0, [%o3] ASI_DMMU_DEMAP
227 membar #Sync
228 brnz,pt %o1, 1b
229 nop
230 stxa %g2, [%o4] ASI_DMMU
231 sethi %hi(KERNBASE), %o4
232 flush %o4
233 wrpr %g0, 0, %tl
234 retl
235 wrpr %g7, 0x0, %pstate
236
237#ifdef DCACHE_ALIASING_POSSIBLE
238__cheetah_flush_dcache_page: /* 11 insns */
239 sethi %uhi(PAGE_OFFSET), %g1
240 sllx %g1, 32, %g1
241 sub %o0, %g1, %o0
242 sethi %hi(PAGE_SIZE), %o4
2431: subcc %o4, (1 << 5), %o4
244 stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE
245 membar #Sync
246 bne,pt %icc, 1b
247 nop
248 retl /* I-cache flush never needed on Cheetah, see callers. */
249 nop
250#endif /* DCACHE_ALIASING_POSSIBLE */
251
252 /* Hypervisor specific versions, patched at boot time. */
253__hypervisor_tlb_tl0_error:
254 save %sp, -192, %sp
255 mov %i0, %o0
256 call hypervisor_tlbop_error
257 mov %i1, %o1
258 ret
259 restore
260
261__hypervisor_flush_tlb_mm: /* 10 insns */
262 mov %o0, %o2 /* ARG2: mmu context */
263 mov 0, %o0 /* ARG0: CPU lists unimplemented */
264 mov 0, %o1 /* ARG1: CPU lists unimplemented */
265 mov HV_MMU_ALL, %o3 /* ARG3: flags */
266 mov HV_FAST_MMU_DEMAP_CTX, %o5
267 ta HV_FAST_TRAP
268 brnz,pn %o0, __hypervisor_tlb_tl0_error
269 mov HV_FAST_MMU_DEMAP_CTX, %o1
270 retl
271 nop
272
273__hypervisor_flush_tlb_pending: /* 16 insns */
274 /* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
275 sllx %o1, 3, %g1
276 mov %o2, %g2
277 mov %o0, %g3
2781: sub %g1, (1 << 3), %g1
279 ldx [%g2 + %g1], %o0 /* ARG0: vaddr + IMMU-bit */
280 mov %g3, %o1 /* ARG1: mmu context */
281 mov HV_MMU_ALL, %o2 /* ARG2: flags */
282 srlx %o0, PAGE_SHIFT, %o0
283 sllx %o0, PAGE_SHIFT, %o0
284 ta HV_MMU_UNMAP_ADDR_TRAP
285 brnz,pn %o0, __hypervisor_tlb_tl0_error
286 mov HV_MMU_UNMAP_ADDR_TRAP, %o1
287 brnz,pt %g1, 1b
288 nop
289 retl
290 nop
291
292__hypervisor_flush_tlb_kernel_range: /* 16 insns */
293 /* %o0=start, %o1=end */
294 cmp %o0, %o1
295 be,pn %xcc, 2f
296 sethi %hi(PAGE_SIZE), %g3
297 mov %o0, %g1
298 sub %o1, %g1, %g2
299 sub %g2, %g3, %g2
3001: add %g1, %g2, %o0 /* ARG0: virtual address */
301 mov 0, %o1 /* ARG1: mmu context */
302 mov HV_MMU_ALL, %o2 /* ARG2: flags */
303 ta HV_MMU_UNMAP_ADDR_TRAP
304 brnz,pn %o0, __hypervisor_tlb_tl0_error
305 mov HV_MMU_UNMAP_ADDR_TRAP, %o1
306 brnz,pt %g2, 1b
307 sub %g2, %g3, %g2
3082: retl
309 nop
310
311#ifdef DCACHE_ALIASING_POSSIBLE
312 /* XXX Niagara and friends have an 8K cache, so no aliasing is
313 * XXX possible, but nothing explicit in the Hypervisor API
314 * XXX guarantees this.
315 */
316__hypervisor_flush_dcache_page: /* 2 insns */
317 retl
318 nop
319#endif
320
321tlb_patch_one:
3221: lduw [%o1], %g1
323 stw %g1, [%o0]
324 flush %o0
325 subcc %o2, 1, %o2
326 add %o1, 4, %o1
327 bne,pt %icc, 1b
328 add %o0, 4, %o0
329 retl
330 nop
331
332 .globl cheetah_patch_cachetlbops
333cheetah_patch_cachetlbops:
334 save %sp, -128, %sp
335
336 sethi %hi(__flush_tlb_mm), %o0
337 or %o0, %lo(__flush_tlb_mm), %o0
338 sethi %hi(__cheetah_flush_tlb_mm), %o1
339 or %o1, %lo(__cheetah_flush_tlb_mm), %o1
340 call tlb_patch_one
341 mov 19, %o2
342
343 sethi %hi(__flush_tlb_pending), %o0
344 or %o0, %lo(__flush_tlb_pending), %o0
345 sethi %hi(__cheetah_flush_tlb_pending), %o1
346 or %o1, %lo(__cheetah_flush_tlb_pending), %o1
347 call tlb_patch_one
348 mov 27, %o2
349
350#ifdef DCACHE_ALIASING_POSSIBLE
351 sethi %hi(__flush_dcache_page), %o0
352 or %o0, %lo(__flush_dcache_page), %o0
353 sethi %hi(__cheetah_flush_dcache_page), %o1
354 or %o1, %lo(__cheetah_flush_dcache_page), %o1
355 call tlb_patch_one
356 mov 11, %o2
357#endif /* DCACHE_ALIASING_POSSIBLE */
358
359 ret
360 restore
361
362#ifdef CONFIG_SMP
363 /* These are all called by the slaves of a cross call, at
364 * trap level 1, with interrupts fully disabled.
365 *
366 * Register usage:
367 * %g5 mm->context (all tlb flushes)
368 * %g1 address arg 1 (tlb page and range flushes)
369 * %g7 address arg 2 (tlb range flush only)
370 *
371 * %g6 scratch 1
372 * %g2 scratch 2
373 * %g3 scratch 3
374 * %g4 scratch 4
375 */
376 .align 32
377 .globl xcall_flush_tlb_mm
378xcall_flush_tlb_mm: /* 21 insns */
379 mov PRIMARY_CONTEXT, %g2
380 ldxa [%g2] ASI_DMMU, %g3
381 srlx %g3, CTX_PGSZ1_NUC_SHIFT, %g4
382 sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
383 or %g5, %g4, %g5 /* Preserve nucleus page size fields */
384 stxa %g5, [%g2] ASI_DMMU
385 mov 0x40, %g4
386 stxa %g0, [%g4] ASI_DMMU_DEMAP
387 stxa %g0, [%g4] ASI_IMMU_DEMAP
388 stxa %g3, [%g2] ASI_DMMU
389 retry
390 nop
391 nop
392 nop
393 nop
394 nop
395 nop
396 nop
397 nop
398 nop
399 nop
400
401 .globl xcall_flush_tlb_pending
402xcall_flush_tlb_pending: /* 21 insns */
403 /* %g5=context, %g1=nr, %g7=vaddrs[] */
404 sllx %g1, 3, %g1
405 mov PRIMARY_CONTEXT, %g4
406 ldxa [%g4] ASI_DMMU, %g2
407 srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4
408 sllx %g4, CTX_PGSZ1_NUC_SHIFT, %g4
409 or %g5, %g4, %g5
410 mov PRIMARY_CONTEXT, %g4
411 stxa %g5, [%g4] ASI_DMMU
4121: sub %g1, (1 << 3), %g1
413 ldx [%g7 + %g1], %g5
414 andcc %g5, 0x1, %g0
415 be,pn %icc, 2f
416
417 andn %g5, 0x1, %g5
418 stxa %g0, [%g5] ASI_IMMU_DEMAP
4192: stxa %g0, [%g5] ASI_DMMU_DEMAP
420 membar #Sync
421 brnz,pt %g1, 1b
422 nop
423 stxa %g2, [%g4] ASI_DMMU
424 retry
425 nop
426
427 .globl xcall_flush_tlb_kernel_range
428xcall_flush_tlb_kernel_range: /* 25 insns */
429 sethi %hi(PAGE_SIZE - 1), %g2
430 or %g2, %lo(PAGE_SIZE - 1), %g2
431 andn %g1, %g2, %g1
432 andn %g7, %g2, %g7
433 sub %g7, %g1, %g3
434 add %g2, 1, %g2
435 sub %g3, %g2, %g3
436 or %g1, 0x20, %g1 ! Nucleus
4371: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
438 stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
439 membar #Sync
440 brnz,pt %g3, 1b
441 sub %g3, %g2, %g3
442 retry
443 nop
444 nop
445 nop
446 nop
447 nop
448 nop
449 nop
450 nop
451 nop
452 nop
453 nop
454
455 /* This runs in a very controlled environment, so we do
456 * not need to worry about BH races etc.
457 */
458 .globl xcall_sync_tick
459xcall_sync_tick:
460
461661: rdpr %pstate, %g2
462 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
463 .section .sun4v_2insn_patch, "ax"
464 .word 661b
465 nop
466 nop
467 .previous
468
469 rdpr %pil, %g2
470 wrpr %g0, 15, %pil
471 sethi %hi(109f), %g7
472 b,pt %xcc, etrap_irq
473109: or %g7, %lo(109b), %g7
474#ifdef CONFIG_TRACE_IRQFLAGS
475 call trace_hardirqs_off
476 nop
477#endif
478 call smp_synchronize_tick_client
479 nop
480 b rtrap_xcall
481 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
482
483 .globl xcall_fetch_glob_regs
484xcall_fetch_glob_regs:
485 sethi %hi(global_reg_snapshot), %g1
486 or %g1, %lo(global_reg_snapshot), %g1
487 __GET_CPUID(%g2)
488 sllx %g2, 6, %g3
489 add %g1, %g3, %g1
490 rdpr %tstate, %g7
491 stx %g7, [%g1 + GR_SNAP_TSTATE]
492 rdpr %tpc, %g7
493 stx %g7, [%g1 + GR_SNAP_TPC]
494 rdpr %tnpc, %g7
495 stx %g7, [%g1 + GR_SNAP_TNPC]
496 stx %o7, [%g1 + GR_SNAP_O7]
497 stx %i7, [%g1 + GR_SNAP_I7]
498 /* Don't try this at home kids... */
499 rdpr %cwp, %g2
500 sub %g2, 1, %g7
501 wrpr %g7, %cwp
502 mov %i7, %g7
503 wrpr %g2, %cwp
504 stx %g7, [%g1 + GR_SNAP_RPC]
505 sethi %hi(trap_block), %g7
506 or %g7, %lo(trap_block), %g7
507 sllx %g2, TRAP_BLOCK_SZ_SHIFT, %g2
508 add %g7, %g2, %g7
509 ldx [%g7 + TRAP_PER_CPU_THREAD], %g3
510 membar #StoreStore
511 stx %g3, [%g1 + GR_SNAP_THREAD]
512 retry
513
514#ifdef DCACHE_ALIASING_POSSIBLE
515 .align 32
516 .globl xcall_flush_dcache_page_cheetah
517xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */
518 sethi %hi(PAGE_SIZE), %g3
5191: subcc %g3, (1 << 5), %g3
520 stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE
521 membar #Sync
522 bne,pt %icc, 1b
523 nop
524 retry
525 nop
526#endif /* DCACHE_ALIASING_POSSIBLE */
527
528 .globl xcall_flush_dcache_page_spitfire
529xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
530 %g7 == kernel page virtual address
531 %g5 == (page->mapping != NULL) */
532#ifdef DCACHE_ALIASING_POSSIBLE
533 srlx %g1, (13 - 2), %g1 ! Form tag comparitor
534 sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K
535 sub %g3, (1 << 5), %g3 ! D$ linesize == 32
5361: ldxa [%g3] ASI_DCACHE_TAG, %g2
537 andcc %g2, 0x3, %g0
538 be,pn %xcc, 2f
539 andn %g2, 0x3, %g2
540 cmp %g2, %g1
541
542 bne,pt %xcc, 2f
543 nop
544 stxa %g0, [%g3] ASI_DCACHE_TAG
545 membar #Sync
5462: cmp %g3, 0
547 bne,pt %xcc, 1b
548 sub %g3, (1 << 5), %g3
549
550 brz,pn %g5, 2f
551#endif /* DCACHE_ALIASING_POSSIBLE */
552 sethi %hi(PAGE_SIZE), %g3
553
5541: flush %g7
555 subcc %g3, (1 << 5), %g3
556 bne,pt %icc, 1b
557 add %g7, (1 << 5), %g7
558
5592: retry
560 nop
561 nop
562
563 /* %g5: error
564 * %g6: tlb op
565 */
566__hypervisor_tlb_xcall_error:
567 mov %g5, %g4
568 mov %g6, %g5
569 ba,pt %xcc, etrap
570 rd %pc, %g7
571 mov %l4, %o0
572 call hypervisor_tlbop_error_xcall
573 mov %l5, %o1
574 ba,a,pt %xcc, rtrap
575
576 .globl __hypervisor_xcall_flush_tlb_mm
577__hypervisor_xcall_flush_tlb_mm: /* 21 insns */
578 /* %g5=ctx, g1,g2,g3,g4,g7=scratch, %g6=unusable */
579 mov %o0, %g2
580 mov %o1, %g3
581 mov %o2, %g4
582 mov %o3, %g1
583 mov %o5, %g7
584 clr %o0 /* ARG0: CPU lists unimplemented */
585 clr %o1 /* ARG1: CPU lists unimplemented */
586 mov %g5, %o2 /* ARG2: mmu context */
587 mov HV_MMU_ALL, %o3 /* ARG3: flags */
588 mov HV_FAST_MMU_DEMAP_CTX, %o5
589 ta HV_FAST_TRAP
590 mov HV_FAST_MMU_DEMAP_CTX, %g6
591 brnz,pn %o0, __hypervisor_tlb_xcall_error
592 mov %o0, %g5
593 mov %g2, %o0
594 mov %g3, %o1
595 mov %g4, %o2
596 mov %g1, %o3
597 mov %g7, %o5
598 membar #Sync
599 retry
600
601 .globl __hypervisor_xcall_flush_tlb_pending
602__hypervisor_xcall_flush_tlb_pending: /* 21 insns */
603 /* %g5=ctx, %g1=nr, %g7=vaddrs[], %g2,%g3,%g4,g6=scratch */
604 sllx %g1, 3, %g1
605 mov %o0, %g2
606 mov %o1, %g3
607 mov %o2, %g4
6081: sub %g1, (1 << 3), %g1
609 ldx [%g7 + %g1], %o0 /* ARG0: virtual address */
610 mov %g5, %o1 /* ARG1: mmu context */
611 mov HV_MMU_ALL, %o2 /* ARG2: flags */
612 srlx %o0, PAGE_SHIFT, %o0
613 sllx %o0, PAGE_SHIFT, %o0
614 ta HV_MMU_UNMAP_ADDR_TRAP
615 mov HV_MMU_UNMAP_ADDR_TRAP, %g6
616 brnz,a,pn %o0, __hypervisor_tlb_xcall_error
617 mov %o0, %g5
618 brnz,pt %g1, 1b
619 nop
620 mov %g2, %o0
621 mov %g3, %o1
622 mov %g4, %o2
623 membar #Sync
624 retry
625
626 .globl __hypervisor_xcall_flush_tlb_kernel_range
627__hypervisor_xcall_flush_tlb_kernel_range: /* 25 insns */
628 /* %g1=start, %g7=end, g2,g3,g4,g5,g6=scratch */
629 sethi %hi(PAGE_SIZE - 1), %g2
630 or %g2, %lo(PAGE_SIZE - 1), %g2
631 andn %g1, %g2, %g1
632 andn %g7, %g2, %g7
633 sub %g7, %g1, %g3
634 add %g2, 1, %g2
635 sub %g3, %g2, %g3
636 mov %o0, %g2
637 mov %o1, %g4
638 mov %o2, %g7
6391: add %g1, %g3, %o0 /* ARG0: virtual address */
640 mov 0, %o1 /* ARG1: mmu context */
641 mov HV_MMU_ALL, %o2 /* ARG2: flags */
642 ta HV_MMU_UNMAP_ADDR_TRAP
643 mov HV_MMU_UNMAP_ADDR_TRAP, %g6
644 brnz,pn %o0, __hypervisor_tlb_xcall_error
645 mov %o0, %g5
646 sethi %hi(PAGE_SIZE), %o2
647 brnz,pt %g3, 1b
648 sub %g3, %o2, %g3
649 mov %g2, %o0
650 mov %g4, %o1
651 mov %g7, %o2
652 membar #Sync
653 retry
654
655 /* These just get rescheduled to PIL vectors. */
656 .globl xcall_call_function
657xcall_call_function:
658 wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
659 retry
660
661 .globl xcall_call_function_single
662xcall_call_function_single:
663 wr %g0, (1 << PIL_SMP_CALL_FUNC_SNGL), %set_softint
664 retry
665
666 .globl xcall_receive_signal
667xcall_receive_signal:
668 wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint
669 retry
670
671 .globl xcall_capture
672xcall_capture:
673 wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint
674 retry
675
676 .globl xcall_new_mmu_context_version
677xcall_new_mmu_context_version:
678 wr %g0, (1 << PIL_SMP_CTX_NEW_VERSION), %set_softint
679 retry
680
681#ifdef CONFIG_KGDB
682 .globl xcall_kgdb_capture
683xcall_kgdb_capture:
684661: rdpr %pstate, %g2
685 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
686 .section .sun4v_2insn_patch, "ax"
687 .word 661b
688 nop
689 nop
690 .previous
691
692 rdpr %pil, %g2
693 wrpr %g0, 15, %pil
694 sethi %hi(109f), %g7
695 ba,pt %xcc, etrap_irq
696109: or %g7, %lo(109b), %g7
697#ifdef CONFIG_TRACE_IRQFLAGS
698 call trace_hardirqs_off
699 nop
700#endif
701 call smp_kgdb_capture_client
702 add %sp, PTREGS_OFF, %o0
703 /* Has to be a non-v9 branch due to the large distance. */
704 ba rtrap_xcall
705 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
706#endif
707
708#endif /* CONFIG_SMP */
709
710
711 .globl hypervisor_patch_cachetlbops
712hypervisor_patch_cachetlbops:
713 save %sp, -128, %sp
714
715 sethi %hi(__flush_tlb_mm), %o0
716 or %o0, %lo(__flush_tlb_mm), %o0
717 sethi %hi(__hypervisor_flush_tlb_mm), %o1
718 or %o1, %lo(__hypervisor_flush_tlb_mm), %o1
719 call tlb_patch_one
720 mov 10, %o2
721
722 sethi %hi(__flush_tlb_pending), %o0
723 or %o0, %lo(__flush_tlb_pending), %o0
724 sethi %hi(__hypervisor_flush_tlb_pending), %o1
725 or %o1, %lo(__hypervisor_flush_tlb_pending), %o1
726 call tlb_patch_one
727 mov 16, %o2
728
729 sethi %hi(__flush_tlb_kernel_range), %o0
730 or %o0, %lo(__flush_tlb_kernel_range), %o0
731 sethi %hi(__hypervisor_flush_tlb_kernel_range), %o1
732 or %o1, %lo(__hypervisor_flush_tlb_kernel_range), %o1
733 call tlb_patch_one
734 mov 16, %o2
735
736#ifdef DCACHE_ALIASING_POSSIBLE
737 sethi %hi(__flush_dcache_page), %o0
738 or %o0, %lo(__flush_dcache_page), %o0
739 sethi %hi(__hypervisor_flush_dcache_page), %o1
740 or %o1, %lo(__hypervisor_flush_dcache_page), %o1
741 call tlb_patch_one
742 mov 2, %o2
743#endif /* DCACHE_ALIASING_POSSIBLE */
744
745#ifdef CONFIG_SMP
746 sethi %hi(xcall_flush_tlb_mm), %o0
747 or %o0, %lo(xcall_flush_tlb_mm), %o0
748 sethi %hi(__hypervisor_xcall_flush_tlb_mm), %o1
749 or %o1, %lo(__hypervisor_xcall_flush_tlb_mm), %o1
750 call tlb_patch_one
751 mov 21, %o2
752
753 sethi %hi(xcall_flush_tlb_pending), %o0
754 or %o0, %lo(xcall_flush_tlb_pending), %o0
755 sethi %hi(__hypervisor_xcall_flush_tlb_pending), %o1
756 or %o1, %lo(__hypervisor_xcall_flush_tlb_pending), %o1
757 call tlb_patch_one
758 mov 21, %o2
759
760 sethi %hi(xcall_flush_tlb_kernel_range), %o0
761 or %o0, %lo(xcall_flush_tlb_kernel_range), %o0
762 sethi %hi(__hypervisor_xcall_flush_tlb_kernel_range), %o1
763 or %o1, %lo(__hypervisor_xcall_flush_tlb_kernel_range), %o1
764 call tlb_patch_one
765 mov 25, %o2
766#endif /* CONFIG_SMP */
767
768 ret
769 restore
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 15:32:53 -0500