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-rw-r--r--arch/sparc/kernel/init_task.c22
-rw-r--r--arch/sparc/kernel/muldiv.c239
-rw-r--r--arch/sparc/kernel/sun4c_irq.c264
-rw-r--r--arch/sparc/kernel/ttable.S272
4 files changed, 797 insertions, 0 deletions
diff --git a/arch/sparc/kernel/init_task.c b/arch/sparc/kernel/init_task.c
new file mode 100644
index 00000000000..35f141a9f50
--- /dev/null
+++ b/arch/sparc/kernel/init_task.c
@@ -0,0 +1,22 @@
1#include <linux/mm.h>
2#include <linux/fs.h>
3#include <linux/module.h>
4#include <linux/sched.h>
5#include <linux/init_task.h>
6#include <linux/mqueue.h>
7
8#include <asm/pgtable.h>
9#include <asm/uaccess.h>
10
11static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
12static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
13struct task_struct init_task = INIT_TASK(init_task);
14EXPORT_SYMBOL(init_task);
15
16/* .text section in head.S is aligned at 8k boundary and this gets linked
17 * right after that so that the init_thread_union is aligned properly as well.
18 * If this is not aligned on a 8k boundary, then you should change code
19 * in etrap.S which assumes it.
20 */
21union thread_union init_thread_union __init_task_data =
22 { INIT_THREAD_INFO(init_task) };
diff --git a/arch/sparc/kernel/muldiv.c b/arch/sparc/kernel/muldiv.c
new file mode 100644
index 00000000000..6ce1021d487
--- /dev/null
+++ b/arch/sparc/kernel/muldiv.c
@@ -0,0 +1,239 @@
1/*
2 * muldiv.c: Hardware multiply/division illegal instruction trap
3 * for sun4c/sun4 (which do not have those instructions)
4 *
5 * Copyright (C) 1996 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
7 *
8 * 2004-12-25 Krzysztof Helt (krzysztof.h1@wp.pl)
9 * - fixed registers constrains in inline assembly declarations
10 */
11
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/mm.h>
15#include <asm/ptrace.h>
16#include <asm/processor.h>
17#include <asm/system.h>
18#include <asm/uaccess.h>
19
20#include "kernel.h"
21
22/* #define DEBUG_MULDIV */
23
24static inline int has_imm13(int insn)
25{
26 return (insn & 0x2000);
27}
28
29static inline int is_foocc(int insn)
30{
31 return (insn & 0x800000);
32}
33
34static inline int sign_extend_imm13(int imm)
35{
36 return imm << 19 >> 19;
37}
38
39static inline void advance(struct pt_regs *regs)
40{
41 regs->pc = regs->npc;
42 regs->npc += 4;
43}
44
45static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
46 unsigned int rd)
47{
48 if(rs2 >= 16 || rs1 >= 16 || rd >= 16) {
49 /* Wheee... */
50 __asm__ __volatile__("save %sp, -0x40, %sp\n\t"
51 "save %sp, -0x40, %sp\n\t"
52 "save %sp, -0x40, %sp\n\t"
53 "save %sp, -0x40, %sp\n\t"
54 "save %sp, -0x40, %sp\n\t"
55 "save %sp, -0x40, %sp\n\t"
56 "save %sp, -0x40, %sp\n\t"
57 "restore; restore; restore; restore;\n\t"
58 "restore; restore; restore;\n\t");
59 }
60}
61
62#define fetch_reg(reg, regs) ({ \
63 struct reg_window32 __user *win; \
64 register unsigned long ret; \
65 \
66 if (!(reg)) ret = 0; \
67 else if ((reg) < 16) { \
68 ret = regs->u_regs[(reg)]; \
69 } else { \
70 /* Ho hum, the slightly complicated case. */ \
71 win = (struct reg_window32 __user *)regs->u_regs[UREG_FP];\
72 if (get_user (ret, &win->locals[(reg) - 16])) return -1;\
73 } \
74 ret; \
75})
76
77static inline int
78store_reg(unsigned int result, unsigned int reg, struct pt_regs *regs)
79{
80 struct reg_window32 __user *win;
81
82 if (!reg)
83 return 0;
84 if (reg < 16) {
85 regs->u_regs[reg] = result;
86 return 0;
87 } else {
88 /* need to use put_user() in this case: */
89 win = (struct reg_window32 __user *) regs->u_regs[UREG_FP];
90 return (put_user(result, &win->locals[reg - 16]));
91 }
92}
93
94/* Should return 0 if mul/div emulation succeeded and SIGILL should
95 * not be issued.
96 */
97int do_user_muldiv(struct pt_regs *regs, unsigned long pc)
98{
99 unsigned int insn;
100 int inst;
101 unsigned int rs1, rs2, rdv;
102
103 if (!pc)
104 return -1; /* This happens to often, I think */
105 if (get_user (insn, (unsigned int __user *)pc))
106 return -1;
107 if ((insn & 0xc1400000) != 0x80400000)
108 return -1;
109 inst = ((insn >> 19) & 0xf);
110 if ((inst & 0xe) != 10 && (inst & 0xe) != 14)
111 return -1;
112
113 /* Now we know we have to do something with umul, smul, udiv or sdiv */
114 rs1 = (insn >> 14) & 0x1f;
115 rs2 = insn & 0x1f;
116 rdv = (insn >> 25) & 0x1f;
117 if (has_imm13(insn)) {
118 maybe_flush_windows(rs1, 0, rdv);
119 rs2 = sign_extend_imm13(insn);
120 } else {
121 maybe_flush_windows(rs1, rs2, rdv);
122 rs2 = fetch_reg(rs2, regs);
123 }
124 rs1 = fetch_reg(rs1, regs);
125 switch (inst) {
126 case 10: /* umul */
127#ifdef DEBUG_MULDIV
128 printk ("unsigned muldiv: 0x%x * 0x%x = ", rs1, rs2);
129#endif
130 __asm__ __volatile__ ("\n\t"
131 "mov %0, %%o0\n\t"
132 "call .umul\n\t"
133 " mov %1, %%o1\n\t"
134 "mov %%o0, %0\n\t"
135 "mov %%o1, %1\n\t"
136 : "=r" (rs1), "=r" (rs2)
137 : "0" (rs1), "1" (rs2)
138 : "o0", "o1", "o2", "o3", "o4", "o5", "o7", "cc");
139#ifdef DEBUG_MULDIV
140 printk ("0x%x%08x\n", rs2, rs1);
141#endif
142 if (store_reg(rs1, rdv, regs))
143 return -1;
144 regs->y = rs2;
145 break;
146 case 11: /* smul */
147#ifdef DEBUG_MULDIV
148 printk ("signed muldiv: 0x%x * 0x%x = ", rs1, rs2);
149#endif
150 __asm__ __volatile__ ("\n\t"
151 "mov %0, %%o0\n\t"
152 "call .mul\n\t"
153 " mov %1, %%o1\n\t"
154 "mov %%o0, %0\n\t"
155 "mov %%o1, %1\n\t"
156 : "=r" (rs1), "=r" (rs2)
157 : "0" (rs1), "1" (rs2)
158 : "o0", "o1", "o2", "o3", "o4", "o5", "o7", "cc");
159#ifdef DEBUG_MULDIV
160 printk ("0x%x%08x\n", rs2, rs1);
161#endif
162 if (store_reg(rs1, rdv, regs))
163 return -1;
164 regs->y = rs2;
165 break;
166 case 14: /* udiv */
167#ifdef DEBUG_MULDIV
168 printk ("unsigned muldiv: 0x%x%08x / 0x%x = ", regs->y, rs1, rs2);
169#endif
170 if (!rs2) {
171#ifdef DEBUG_MULDIV
172 printk ("DIVISION BY ZERO\n");
173#endif
174 handle_hw_divzero (regs, pc, regs->npc, regs->psr);
175 return 0;
176 }
177 __asm__ __volatile__ ("\n\t"
178 "mov %2, %%o0\n\t"
179 "mov %0, %%o1\n\t"
180 "mov %%g0, %%o2\n\t"
181 "call __udivdi3\n\t"
182 " mov %1, %%o3\n\t"
183 "mov %%o1, %0\n\t"
184 "mov %%o0, %1\n\t"
185 : "=r" (rs1), "=r" (rs2)
186 : "r" (regs->y), "0" (rs1), "1" (rs2)
187 : "o0", "o1", "o2", "o3", "o4", "o5", "o7",
188 "g1", "g2", "g3", "cc");
189#ifdef DEBUG_MULDIV
190 printk ("0x%x\n", rs1);
191#endif
192 if (store_reg(rs1, rdv, regs))
193 return -1;
194 break;
195 case 15: /* sdiv */
196#ifdef DEBUG_MULDIV
197 printk ("signed muldiv: 0x%x%08x / 0x%x = ", regs->y, rs1, rs2);
198#endif
199 if (!rs2) {
200#ifdef DEBUG_MULDIV
201 printk ("DIVISION BY ZERO\n");
202#endif
203 handle_hw_divzero (regs, pc, regs->npc, regs->psr);
204 return 0;
205 }
206 __asm__ __volatile__ ("\n\t"
207 "mov %2, %%o0\n\t"
208 "mov %0, %%o1\n\t"
209 "mov %%g0, %%o2\n\t"
210 "call __divdi3\n\t"
211 " mov %1, %%o3\n\t"
212 "mov %%o1, %0\n\t"
213 "mov %%o0, %1\n\t"
214 : "=r" (rs1), "=r" (rs2)
215 : "r" (regs->y), "0" (rs1), "1" (rs2)
216 : "o0", "o1", "o2", "o3", "o4", "o5", "o7",
217 "g1", "g2", "g3", "cc");
218#ifdef DEBUG_MULDIV
219 printk ("0x%x\n", rs1);
220#endif
221 if (store_reg(rs1, rdv, regs))
222 return -1;
223 break;
224 }
225 if (is_foocc (insn)) {
226 regs->psr &= ~PSR_ICC;
227 if ((inst & 0xe) == 14) {
228 /* ?div */
229 if (rs2) regs->psr |= PSR_V;
230 }
231 if (!rs1) regs->psr |= PSR_Z;
232 if (((int)rs1) < 0) regs->psr |= PSR_N;
233#ifdef DEBUG_MULDIV
234 printk ("psr muldiv: %08x\n", regs->psr);
235#endif
236 }
237 advance(regs);
238 return 0;
239}
diff --git a/arch/sparc/kernel/sun4c_irq.c b/arch/sparc/kernel/sun4c_irq.c
new file mode 100644
index 00000000000..f6bf25a2ff8
--- /dev/null
+++ b/arch/sparc/kernel/sun4c_irq.c
@@ -0,0 +1,264 @@
1/*
2 * sun4c irq support
3 *
4 * djhr: Hacked out of irq.c into a CPU dependent version.
5 *
6 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
7 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
8 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
9 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
10 */
11
12#include <linux/init.h>
13
14#include <asm/oplib.h>
15#include <asm/timer.h>
16#include <asm/irq.h>
17#include <asm/io.h>
18
19#include "irq.h"
20
21/* Sun4c interrupts are typically laid out as follows:
22 *
23 * 1 - Software interrupt, SBUS level 1
24 * 2 - SBUS level 2
25 * 3 - ESP SCSI, SBUS level 3
26 * 4 - Software interrupt
27 * 5 - Lance ethernet, SBUS level 4
28 * 6 - Software interrupt
29 * 7 - Graphics card, SBUS level 5
30 * 8 - SBUS level 6
31 * 9 - SBUS level 7
32 * 10 - Counter timer
33 * 11 - Floppy
34 * 12 - Zilog uart
35 * 13 - CS4231 audio
36 * 14 - Profiling timer
37 * 15 - NMI
38 *
39 * The interrupt enable bits in the interrupt mask register are
40 * really only used to enable/disable the timer interrupts, and
41 * for signalling software interrupts. There is also a master
42 * interrupt enable bit in this register.
43 *
44 * Interrupts are enabled by setting the SUN4C_INT_* bits, they
45 * are disabled by clearing those bits.
46 */
47
48/*
49 * Bit field defines for the interrupt registers on various
50 * Sparc machines.
51 */
52
53/* The sun4c interrupt register. */
54#define SUN4C_INT_ENABLE 0x01 /* Allow interrupts. */
55#define SUN4C_INT_E14 0x80 /* Enable level 14 IRQ. */
56#define SUN4C_INT_E10 0x20 /* Enable level 10 IRQ. */
57#define SUN4C_INT_E8 0x10 /* Enable level 8 IRQ. */
58#define SUN4C_INT_E6 0x08 /* Enable level 6 IRQ. */
59#define SUN4C_INT_E4 0x04 /* Enable level 4 IRQ. */
60#define SUN4C_INT_E1 0x02 /* Enable level 1 IRQ. */
61
62/*
63 * Pointer to the interrupt enable byte
64 * Used by entry.S
65 */
66unsigned char __iomem *interrupt_enable;
67
68static void sun4c_mask_irq(struct irq_data *data)
69{
70 unsigned long mask = (unsigned long)data->chip_data;
71
72 if (mask) {
73 unsigned long flags;
74
75 local_irq_save(flags);
76 mask = sbus_readb(interrupt_enable) & ~mask;
77 sbus_writeb(mask, interrupt_enable);
78 local_irq_restore(flags);
79 }
80}
81
82static void sun4c_unmask_irq(struct irq_data *data)
83{
84 unsigned long mask = (unsigned long)data->chip_data;
85
86 if (mask) {
87 unsigned long flags;
88
89 local_irq_save(flags);
90 mask = sbus_readb(interrupt_enable) | mask;
91 sbus_writeb(mask, interrupt_enable);
92 local_irq_restore(flags);
93 }
94}
95
96static unsigned int sun4c_startup_irq(struct irq_data *data)
97{
98 irq_link(data->irq);
99 sun4c_unmask_irq(data);
100
101 return 0;
102}
103
104static void sun4c_shutdown_irq(struct irq_data *data)
105{
106 sun4c_mask_irq(data);
107 irq_unlink(data->irq);
108}
109
110static struct irq_chip sun4c_irq = {
111 .name = "sun4c",
112 .irq_startup = sun4c_startup_irq,
113 .irq_shutdown = sun4c_shutdown_irq,
114 .irq_mask = sun4c_mask_irq,
115 .irq_unmask = sun4c_unmask_irq,
116};
117
118static unsigned int sun4c_build_device_irq(struct platform_device *op,
119 unsigned int real_irq)
120{
121 unsigned int irq;
122
123 if (real_irq >= 16) {
124 prom_printf("Bogus sun4c IRQ %u\n", real_irq);
125 prom_halt();
126 }
127
128 irq = irq_alloc(real_irq, real_irq);
129 if (irq) {
130 unsigned long mask = 0UL;
131
132 switch (real_irq) {
133 case 1:
134 mask = SUN4C_INT_E1;
135 break;
136 case 8:
137 mask = SUN4C_INT_E8;
138 break;
139 case 10:
140 mask = SUN4C_INT_E10;
141 break;
142 case 14:
143 mask = SUN4C_INT_E14;
144 break;
145 default:
146 /* All the rest are either always enabled,
147 * or are for signalling software interrupts.
148 */
149 break;
150 }
151 irq_set_chip_and_handler_name(irq, &sun4c_irq,
152 handle_level_irq, "level");
153 irq_set_chip_data(irq, (void *)mask);
154 }
155 return irq;
156}
157
158struct sun4c_timer_info {
159 u32 l10_count;
160 u32 l10_limit;
161 u32 l14_count;
162 u32 l14_limit;
163};
164
165static struct sun4c_timer_info __iomem *sun4c_timers;
166
167static void sun4c_clear_clock_irq(void)
168{
169 sbus_readl(&sun4c_timers->l10_limit);
170}
171
172static void sun4c_load_profile_irq(int cpu, unsigned int limit)
173{
174 /* Errm.. not sure how to do this.. */
175}
176
177static void __init sun4c_init_timers(irq_handler_t counter_fn)
178{
179 const struct linux_prom_irqs *prom_irqs;
180 struct device_node *dp;
181 unsigned int irq;
182 const u32 *addr;
183 int err;
184
185 dp = of_find_node_by_name(NULL, "counter-timer");
186 if (!dp) {
187 prom_printf("sun4c_init_timers: Unable to find counter-timer\n");
188 prom_halt();
189 }
190
191 addr = of_get_property(dp, "address", NULL);
192 if (!addr) {
193 prom_printf("sun4c_init_timers: No address property\n");
194 prom_halt();
195 }
196
197 sun4c_timers = (void __iomem *) (unsigned long) addr[0];
198
199 prom_irqs = of_get_property(dp, "intr", NULL);
200 of_node_put(dp);
201 if (!prom_irqs) {
202 prom_printf("sun4c_init_timers: No intr property\n");
203 prom_halt();
204 }
205
206 /* Have the level 10 timer tick at 100HZ. We don't touch the
207 * level 14 timer limit since we are letting the prom handle
208 * them until we have a real console driver so L1-A works.
209 */
210 sbus_writel((((1000000/HZ) + 1) << 10), &sun4c_timers->l10_limit);
211
212 master_l10_counter = &sun4c_timers->l10_count;
213
214 irq = sun4c_build_device_irq(NULL, prom_irqs[0].pri);
215 err = request_irq(irq, counter_fn, IRQF_TIMER, "timer", NULL);
216 if (err) {
217 prom_printf("sun4c_init_timers: request_irq() fails with %d\n", err);
218 prom_halt();
219 }
220
221 /* disable timer interrupt */
222 sun4c_mask_irq(irq_get_irq_data(irq));
223}
224
225#ifdef CONFIG_SMP
226static void sun4c_nop(void)
227{
228}
229#endif
230
231void __init sun4c_init_IRQ(void)
232{
233 struct device_node *dp;
234 const u32 *addr;
235
236 dp = of_find_node_by_name(NULL, "interrupt-enable");
237 if (!dp) {
238 prom_printf("sun4c_init_IRQ: Unable to find interrupt-enable\n");
239 prom_halt();
240 }
241
242 addr = of_get_property(dp, "address", NULL);
243 of_node_put(dp);
244 if (!addr) {
245 prom_printf("sun4c_init_IRQ: No address property\n");
246 prom_halt();
247 }
248
249 interrupt_enable = (void __iomem *) (unsigned long) addr[0];
250
251 BTFIXUPSET_CALL(clear_clock_irq, sun4c_clear_clock_irq, BTFIXUPCALL_NORM);
252 BTFIXUPSET_CALL(load_profile_irq, sun4c_load_profile_irq, BTFIXUPCALL_NOP);
253
254 sparc_irq_config.init_timers = sun4c_init_timers;
255 sparc_irq_config.build_device_irq = sun4c_build_device_irq;
256
257#ifdef CONFIG_SMP
258 BTFIXUPSET_CALL(set_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
259 BTFIXUPSET_CALL(clear_cpu_int, sun4c_nop, BTFIXUPCALL_NOP);
260 BTFIXUPSET_CALL(set_irq_udt, sun4c_nop, BTFIXUPCALL_NOP);
261#endif
262 sbus_writeb(SUN4C_INT_ENABLE, interrupt_enable);
263 /* Cannot enable interrupts until OBP ticker is disabled. */
264}
diff --git a/arch/sparc/kernel/ttable.S b/arch/sparc/kernel/ttable.S
new file mode 100644
index 00000000000..c6dfdaa29e2
--- /dev/null
+++ b/arch/sparc/kernel/ttable.S
@@ -0,0 +1,272 @@
1/* ttable.S: Sparc V9 Trap Table(s) with SpitFire/Cheetah/SUN4V extensions.
2 *
3 * Copyright (C) 1996, 2001, 2006 David S. Miller (davem@davemloft.net)
4 */
5
6
7 .globl sparc64_ttable_tl0, sparc64_ttable_tl1
8 .globl tl0_icpe, tl1_icpe
9 .globl tl0_dcpe, tl1_dcpe
10 .globl tl0_fecc, tl1_fecc
11 .globl tl0_cee, tl1_cee
12 .globl tl0_iae, tl1_iae
13 .globl tl0_dae, tl1_dae
14
15sparc64_ttable_tl0:
16tl0_resv000: BOOT_KERNEL BTRAP(0x1) BTRAP(0x2) BTRAP(0x3)
17tl0_resv004: BTRAP(0x4) BTRAP(0x5) BTRAP(0x6) BTRAP(0x7)
18tl0_iax: membar #Sync
19 TRAP_NOSAVE_7INSNS(__spitfire_insn_access_exception)
20tl0_itsb_4v: SUN4V_ITSB_MISS
21tl0_iae: membar #Sync
22 TRAP_NOSAVE_7INSNS(__spitfire_access_error)
23tl0_resv00b: BTRAP(0xb) BTRAP(0xc) BTRAP(0xd) BTRAP(0xe) BTRAP(0xf)
24tl0_ill: membar #Sync
25 TRAP_7INSNS(do_illegal_instruction)
26tl0_privop: TRAP(do_privop)
27tl0_resv012: BTRAP(0x12) BTRAP(0x13) BTRAP(0x14) BTRAP(0x15) BTRAP(0x16) BTRAP(0x17)
28tl0_resv018: BTRAP(0x18) BTRAP(0x19) BTRAP(0x1a) BTRAP(0x1b) BTRAP(0x1c) BTRAP(0x1d)
29tl0_resv01e: BTRAP(0x1e) BTRAP(0x1f)
30tl0_fpdis: TRAP_NOSAVE(do_fpdis)
31tl0_fpieee: TRAP_SAVEFPU(do_fpieee)
32tl0_fpother: TRAP_NOSAVE(do_fpother_check_fitos)
33tl0_tof: TRAP(do_tof)
34tl0_cwin: CLEAN_WINDOW
35tl0_div0: TRAP(do_div0)
36tl0_resv029: BTRAP(0x29) BTRAP(0x2a) BTRAP(0x2b) BTRAP(0x2c) BTRAP(0x2d) BTRAP(0x2e)
37tl0_resv02f: BTRAP(0x2f)
38tl0_dax: TRAP_NOSAVE(__spitfire_data_access_exception)
39tl0_dtsb_4v: SUN4V_DTSB_MISS
40tl0_dae: membar #Sync
41 TRAP_NOSAVE_7INSNS(__spitfire_access_error)
42tl0_resv033: BTRAP(0x33)
43tl0_mna: TRAP_NOSAVE(do_mna)
44tl0_lddfmna: TRAP_NOSAVE(do_lddfmna)
45tl0_stdfmna: TRAP_NOSAVE(do_stdfmna)
46tl0_privact: TRAP_NOSAVE(__do_privact)
47tl0_resv038: BTRAP(0x38) BTRAP(0x39) BTRAP(0x3a) BTRAP(0x3b) BTRAP(0x3c) BTRAP(0x3d)
48tl0_resv03e: BTRAP(0x3e) BTRAP(0x3f) BTRAP(0x40)
49#ifdef CONFIG_SMP
50tl0_irq1: TRAP_IRQ(smp_call_function_client, 1)
51tl0_irq2: TRAP_IRQ(smp_receive_signal_client, 2)
52tl0_irq3: TRAP_IRQ(smp_penguin_jailcell, 3)
53tl0_irq4: TRAP_IRQ(smp_new_mmu_context_version_client, 4)
54#else
55tl0_irq1: BTRAP(0x41)
56tl0_irq2: BTRAP(0x42)
57tl0_irq3: BTRAP(0x43)
58tl0_irq4: BTRAP(0x44)
59#endif
60tl0_irq5: TRAP_IRQ(handler_irq, 5)
61#ifdef CONFIG_SMP
62tl0_irq6: TRAP_IRQ(smp_call_function_single_client, 6)
63#else
64tl0_irq6: BTRAP(0x46)
65#endif
66tl0_irq7: TRAP_IRQ(deferred_pcr_work_irq, 7)
67#if defined(CONFIG_KGDB) && defined(CONFIG_SMP)
68tl0_irq8: TRAP_IRQ(smp_kgdb_capture_client, 8)
69#else
70tl0_irq8: BTRAP(0x48)
71#endif
72tl0_irq9: BTRAP(0x49)
73tl0_irq10: BTRAP(0x4a) BTRAP(0x4b) BTRAP(0x4c) BTRAP(0x4d)
74tl0_irq14: TRAP_IRQ(timer_interrupt, 14)
75tl0_irq15: TRAP_NMI_IRQ(perfctr_irq, 15)
76tl0_resv050: BTRAP(0x50) BTRAP(0x51) BTRAP(0x52) BTRAP(0x53) BTRAP(0x54) BTRAP(0x55)
77tl0_resv056: BTRAP(0x56) BTRAP(0x57) BTRAP(0x58) BTRAP(0x59) BTRAP(0x5a) BTRAP(0x5b)
78tl0_resv05c: BTRAP(0x5c) BTRAP(0x5d) BTRAP(0x5e) BTRAP(0x5f)
79tl0_ivec: TRAP_IVEC
80tl0_paw: TRAP(do_paw)
81tl0_vaw: TRAP(do_vaw)
82tl0_cee: membar #Sync
83 TRAP_NOSAVE_7INSNS(__spitfire_cee_trap)
84tl0_iamiss:
85#include "itlb_miss.S"
86tl0_damiss:
87#include "dtlb_miss.S"
88tl0_daprot:
89#include "dtlb_prot.S"
90tl0_fecc: BTRAP(0x70) /* Fast-ECC on Cheetah */
91tl0_dcpe: BTRAP(0x71) /* D-cache Parity Error on Cheetah+ */
92tl0_icpe: BTRAP(0x72) /* I-cache Parity Error on Cheetah+ */
93tl0_resv073: BTRAP(0x73) BTRAP(0x74) BTRAP(0x75)
94tl0_resv076: BTRAP(0x76) BTRAP(0x77) BTRAP(0x78) BTRAP(0x79) BTRAP(0x7a) BTRAP(0x7b)
95tl0_cpu_mondo: TRAP_NOSAVE(sun4v_cpu_mondo)
96tl0_dev_mondo: TRAP_NOSAVE(sun4v_dev_mondo)
97tl0_res_mondo: TRAP_NOSAVE(sun4v_res_mondo)
98tl0_nres_mondo: TRAP_NOSAVE(sun4v_nonres_mondo)
99tl0_s0n: SPILL_0_NORMAL
100tl0_s1n: SPILL_1_NORMAL
101tl0_s2n: SPILL_2_NORMAL
102tl0_s3n: SPILL_0_NORMAL_ETRAP
103tl0_s4n: SPILL_1_GENERIC_ETRAP
104tl0_s5n: SPILL_1_GENERIC_ETRAP_FIXUP
105tl0_s6n: SPILL_2_GENERIC_ETRAP
106tl0_s7n: SPILL_2_GENERIC_ETRAP_FIXUP
107tl0_s0o: SPILL_0_OTHER
108tl0_s1o: SPILL_1_OTHER
109tl0_s2o: SPILL_2_OTHER
110tl0_s3o: SPILL_3_OTHER
111tl0_s4o: SPILL_4_OTHER
112tl0_s5o: SPILL_5_OTHER
113tl0_s6o: SPILL_6_OTHER
114tl0_s7o: SPILL_7_OTHER
115tl0_f0n: FILL_0_NORMAL
116tl0_f1n: FILL_1_NORMAL
117tl0_f2n: FILL_2_NORMAL
118tl0_f3n: FILL_3_NORMAL
119tl0_f4n: FILL_4_NORMAL
120tl0_f5n: FILL_0_NORMAL_RTRAP
121tl0_f6n: FILL_1_GENERIC_RTRAP
122tl0_f7n: FILL_2_GENERIC_RTRAP
123tl0_f0o: FILL_0_OTHER
124tl0_f1o: FILL_1_OTHER
125tl0_f2o: FILL_2_OTHER
126tl0_f3o: FILL_3_OTHER
127tl0_f4o: FILL_4_OTHER
128tl0_f5o: FILL_5_OTHER
129tl0_f6o: FILL_6_OTHER
130tl0_f7o: FILL_7_OTHER
131tl0_resv100: BTRAP(0x100)
132tl0_bkpt: BREAKPOINT_TRAP
133tl0_divz: TRAP(do_div0)
134tl0_flushw: FLUSH_WINDOW_TRAP
135tl0_resv104: BTRAP(0x104) BTRAP(0x105) BTRAP(0x106) BTRAP(0x107) BTRAP(0x108)
136tl0_resv109: BTRAP(0x109) BTRAP(0x10a) BTRAP(0x10b) BTRAP(0x10c) BTRAP(0x10d)
137tl0_resv10e: BTRAP(0x10e) BTRAP(0x10f)
138tl0_linux32: LINUX_32BIT_SYSCALL_TRAP
139tl0_oldlinux64: LINUX_64BIT_SYSCALL_TRAP
140tl0_resv112: TRAP_UTRAP(UT_TRAP_INSTRUCTION_18,0x112) TRAP_UTRAP(UT_TRAP_INSTRUCTION_19,0x113)
141tl0_resv114: TRAP_UTRAP(UT_TRAP_INSTRUCTION_20,0x114) TRAP_UTRAP(UT_TRAP_INSTRUCTION_21,0x115)
142tl0_resv116: TRAP_UTRAP(UT_TRAP_INSTRUCTION_22,0x116) TRAP_UTRAP(UT_TRAP_INSTRUCTION_23,0x117)
143tl0_resv118: TRAP_UTRAP(UT_TRAP_INSTRUCTION_24,0x118) TRAP_UTRAP(UT_TRAP_INSTRUCTION_25,0x119)
144tl0_resv11a: TRAP_UTRAP(UT_TRAP_INSTRUCTION_26,0x11a) TRAP_UTRAP(UT_TRAP_INSTRUCTION_27,0x11b)
145tl0_resv11c: TRAP_UTRAP(UT_TRAP_INSTRUCTION_28,0x11c) TRAP_UTRAP(UT_TRAP_INSTRUCTION_29,0x11d)
146tl0_resv11e: TRAP_UTRAP(UT_TRAP_INSTRUCTION_30,0x11e) TRAP_UTRAP(UT_TRAP_INSTRUCTION_31,0x11f)
147tl0_getcc: GETCC_TRAP
148tl0_setcc: SETCC_TRAP
149tl0_getpsr: TRAP(do_getpsr)
150tl0_resv123: BTRAP(0x123) BTRAP(0x124) BTRAP(0x125) BTRAP(0x126) BTRAP(0x127)
151tl0_resv128: BTRAP(0x128) BTRAP(0x129) BTRAP(0x12a) BTRAP(0x12b) BTRAP(0x12c)
152tl0_resv12d: BTRAP(0x12d) BTRAP(0x12e) BTRAP(0x12f) BTRAP(0x130) BTRAP(0x131)
153tl0_resv132: BTRAP(0x132) BTRAP(0x133) BTRAP(0x134) BTRAP(0x135) BTRAP(0x136)
154tl0_resv137: BTRAP(0x137) BTRAP(0x138) BTRAP(0x139) BTRAP(0x13a) BTRAP(0x13b)
155tl0_resv13c: BTRAP(0x13c) BTRAP(0x13d) BTRAP(0x13e) BTRAP(0x13f) BTRAP(0x140)
156tl0_resv141: BTRAP(0x141) BTRAP(0x142) BTRAP(0x143) BTRAP(0x144) BTRAP(0x145)
157tl0_resv146: BTRAP(0x146) BTRAP(0x147) BTRAP(0x148) BTRAP(0x149) BTRAP(0x14a)
158tl0_resv14b: BTRAP(0x14b) BTRAP(0x14c) BTRAP(0x14d) BTRAP(0x14e) BTRAP(0x14f)
159tl0_resv150: BTRAP(0x150) BTRAP(0x151) BTRAP(0x152) BTRAP(0x153) BTRAP(0x154)
160tl0_resv155: BTRAP(0x155) BTRAP(0x156) BTRAP(0x157) BTRAP(0x158) BTRAP(0x159)
161tl0_resv15a: BTRAP(0x15a) BTRAP(0x15b) BTRAP(0x15c) BTRAP(0x15d) BTRAP(0x15e)
162tl0_resv15f: BTRAP(0x15f) BTRAP(0x160) BTRAP(0x161) BTRAP(0x162) BTRAP(0x163)
163tl0_resv164: BTRAP(0x164) BTRAP(0x165) BTRAP(0x166) BTRAP(0x167) BTRAP(0x168)
164tl0_resv169: BTRAP(0x169) BTRAP(0x16a) BTRAP(0x16b) BTRAP(0x16c)
165tl0_linux64: LINUX_64BIT_SYSCALL_TRAP
166tl0_gsctx: TRAP(sparc64_get_context) TRAP(sparc64_set_context)
167tl0_resv170: KPROBES_TRAP(0x170) KPROBES_TRAP(0x171) KGDB_TRAP(0x172)
168tl0_resv173: BTRAP(0x173) BTRAP(0x174) BTRAP(0x175) BTRAP(0x176) BTRAP(0x177)
169tl0_resv178: BTRAP(0x178) BTRAP(0x179) BTRAP(0x17a) BTRAP(0x17b) BTRAP(0x17c)
170tl0_resv17d: BTRAP(0x17d) BTRAP(0x17e) BTRAP(0x17f)
171#define BTRAPS(x) BTRAP(x) BTRAP(x+1) BTRAP(x+2) BTRAP(x+3) BTRAP(x+4) BTRAP(x+5) BTRAP(x+6) BTRAP(x+7)
172tl0_resv180: BTRAPS(0x180) BTRAPS(0x188)
173tl0_resv190: BTRAPS(0x190) BTRAPS(0x198)
174tl0_resv1a0: BTRAPS(0x1a0) BTRAPS(0x1a8)
175tl0_resv1b0: BTRAPS(0x1b0) BTRAPS(0x1b8)
176tl0_resv1c0: BTRAPS(0x1c0) BTRAPS(0x1c8)
177tl0_resv1d0: BTRAPS(0x1d0) BTRAPS(0x1d8)
178tl0_resv1e0: BTRAPS(0x1e0) BTRAPS(0x1e8)
179tl0_resv1f0: BTRAPS(0x1f0) BTRAPS(0x1f8)
180
181sparc64_ttable_tl1:
182tl1_resv000: BOOT_KERNEL BTRAPTL1(0x1) BTRAPTL1(0x2) BTRAPTL1(0x3)
183tl1_resv004: BTRAPTL1(0x4) BTRAPTL1(0x5) BTRAPTL1(0x6) BTRAPTL1(0x7)
184tl1_iax: TRAP_NOSAVE(__spitfire_insn_access_exception_tl1)
185tl1_itsb_4v: SUN4V_ITSB_MISS
186tl1_iae: membar #Sync
187 TRAP_NOSAVE_7INSNS(__spitfire_access_error)
188tl1_resv00b: BTRAPTL1(0xb) BTRAPTL1(0xc) BTRAPTL1(0xd) BTRAPTL1(0xe) BTRAPTL1(0xf)
189tl1_ill: TRAPTL1(do_ill_tl1)
190tl1_privop: BTRAPTL1(0x11)
191tl1_resv012: BTRAPTL1(0x12) BTRAPTL1(0x13) BTRAPTL1(0x14) BTRAPTL1(0x15)
192tl1_resv016: BTRAPTL1(0x16) BTRAPTL1(0x17) BTRAPTL1(0x18) BTRAPTL1(0x19)
193tl1_resv01a: BTRAPTL1(0x1a) BTRAPTL1(0x1b) BTRAPTL1(0x1c) BTRAPTL1(0x1d)
194tl1_resv01e: BTRAPTL1(0x1e) BTRAPTL1(0x1f)
195tl1_fpdis: TRAP_NOSAVE(do_fpdis)
196tl1_fpieee: TRAPTL1(do_fpieee_tl1)
197tl1_fpother: TRAPTL1(do_fpother_tl1)
198tl1_tof: TRAPTL1(do_tof_tl1)
199tl1_cwin: CLEAN_WINDOW
200tl1_div0: TRAPTL1(do_div0_tl1)
201tl1_resv029: BTRAPTL1(0x29) BTRAPTL1(0x2a) BTRAPTL1(0x2b) BTRAPTL1(0x2c)
202tl1_resv02d: BTRAPTL1(0x2d) BTRAPTL1(0x2e) BTRAPTL1(0x2f)
203tl1_dax: TRAP_NOSAVE(__spitfire_data_access_exception_tl1)
204tl1_dtsb_4v: SUN4V_DTSB_MISS
205tl1_dae: membar #Sync
206 TRAP_NOSAVE_7INSNS(__spitfire_access_error)
207tl1_resv033: BTRAPTL1(0x33)
208tl1_mna: TRAP_NOSAVE(do_mna)
209tl1_lddfmna: TRAPTL1(do_lddfmna_tl1)
210tl1_stdfmna: TRAPTL1(do_stdfmna_tl1)
211tl1_privact: BTRAPTL1(0x37)
212tl1_resv038: BTRAPTL1(0x38) BTRAPTL1(0x39) BTRAPTL1(0x3a) BTRAPTL1(0x3b)
213tl1_resv03c: BTRAPTL1(0x3c) BTRAPTL1(0x3d) BTRAPTL1(0x3e) BTRAPTL1(0x3f)
214tl1_resv040: BTRAPTL1(0x40)
215tl1_irq1: TRAP_IRQ(do_irq_tl1, 1) TRAP_IRQ(do_irq_tl1, 2) TRAP_IRQ(do_irq_tl1, 3)
216tl1_irq4: TRAP_IRQ(do_irq_tl1, 4) TRAP_IRQ(do_irq_tl1, 5) TRAP_IRQ(do_irq_tl1, 6)
217tl1_irq7: TRAP_IRQ(do_irq_tl1, 7) TRAP_IRQ(do_irq_tl1, 8) TRAP_IRQ(do_irq_tl1, 9)
218tl1_irq10: TRAP_IRQ(do_irq_tl1, 10) TRAP_IRQ(do_irq_tl1, 11)
219tl1_irq12: TRAP_IRQ(do_irq_tl1, 12) TRAP_IRQ(do_irq_tl1, 13)
220tl1_irq14: TRAP_IRQ(do_irq_tl1, 14) TRAP_IRQ(do_irq_tl1, 15)
221tl1_resv050: BTRAPTL1(0x50) BTRAPTL1(0x51) BTRAPTL1(0x52) BTRAPTL1(0x53)
222tl1_resv054: BTRAPTL1(0x54) BTRAPTL1(0x55) BTRAPTL1(0x56) BTRAPTL1(0x57)
223tl1_resv058: BTRAPTL1(0x58) BTRAPTL1(0x59) BTRAPTL1(0x5a) BTRAPTL1(0x5b)
224tl1_resv05c: BTRAPTL1(0x5c) BTRAPTL1(0x5d) BTRAPTL1(0x5e) BTRAPTL1(0x5f)
225tl1_ivec: TRAP_IVEC
226tl1_paw: TRAPTL1(do_paw_tl1)
227tl1_vaw: TRAPTL1(do_vaw_tl1)
228tl1_cee: BTRAPTL1(0x63)
229tl1_iamiss: BTRAPTL1(0x64) BTRAPTL1(0x65) BTRAPTL1(0x66) BTRAPTL1(0x67)
230tl1_damiss:
231#include "dtlb_miss.S"
232tl1_daprot:
233#include "dtlb_prot.S"
234tl1_fecc: BTRAPTL1(0x70) /* Fast-ECC on Cheetah */
235tl1_dcpe: BTRAPTL1(0x71) /* D-cache Parity Error on Cheetah+ */
236tl1_icpe: BTRAPTL1(0x72) /* I-cache Parity Error on Cheetah+ */
237tl1_resv073: BTRAPTL1(0x73)
238tl1_resv074: BTRAPTL1(0x74) BTRAPTL1(0x75) BTRAPTL1(0x76) BTRAPTL1(0x77)
239tl1_resv078: BTRAPTL1(0x78) BTRAPTL1(0x79) BTRAPTL1(0x7a) BTRAPTL1(0x7b)
240tl1_resv07c: BTRAPTL1(0x7c) BTRAPTL1(0x7d) BTRAPTL1(0x7e) BTRAPTL1(0x7f)
241tl1_s0n: SPILL_0_NORMAL
242tl1_s1n: SPILL_1_NORMAL
243tl1_s2n: SPILL_2_NORMAL
244tl1_s3n: SPILL_3_NORMAL
245tl1_s4n: SPILL_4_NORMAL
246tl1_s5n: SPILL_5_NORMAL
247tl1_s6n: SPILL_6_NORMAL
248tl1_s7n: SPILL_7_NORMAL
249tl1_s0o: SPILL_0_OTHER
250tl1_s1o: SPILL_1_OTHER
251tl1_s2o: SPILL_2_OTHER
252tl1_s3o: SPILL_3_OTHER
253tl1_s4o: SPILL_4_OTHER
254tl1_s5o: SPILL_5_OTHER
255tl1_s6o: SPILL_6_OTHER
256tl1_s7o: SPILL_7_OTHER
257tl1_f0n: FILL_0_NORMAL
258tl1_f1n: FILL_1_NORMAL
259tl1_f2n: FILL_2_NORMAL
260tl1_f3n: FILL_3_NORMAL
261tl1_f4n: FILL_4_NORMAL
262tl1_f5n: FILL_5_NORMAL
263tl1_f6n: FILL_6_NORMAL
264tl1_f7n: FILL_7_NORMAL
265tl1_f0o: FILL_0_OTHER
266tl1_f1o: FILL_1_OTHER
267tl1_f2o: FILL_2_OTHER
268tl1_f3o: FILL_3_OTHER
269tl1_f4o: FILL_4_OTHER
270tl1_f5o: FILL_5_OTHER
271tl1_f6o: FILL_6_OTHER
272tl1_f7o: FILL_7_OTHER
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 07:46:51 -0400