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-rw-r--r--arch/sparc/include/asm/atomic_64.h10
-rw-r--r--arch/sparc/include/asm/backoff.h11
-rw-r--r--arch/sparc/include/asm/fb.h4
-rw-r--r--arch/sparc/include/asm/oplib_64.h27
-rw-r--r--arch/sparc/include/asm/rwsem-const.h12
-rw-r--r--arch/sparc/include/asm/rwsem.h120
-rw-r--r--arch/sparc/include/asm/system_64.h1
-rw-r--r--arch/sparc/include/asm/unistd.h5
8 files changed, 128 insertions, 62 deletions
diff --git a/arch/sparc/include/asm/atomic_64.h b/arch/sparc/include/asm/atomic_64.h
index 2050ca02c42..bdb2ff880bd 100644
--- a/arch/sparc/include/asm/atomic_64.h
+++ b/arch/sparc/include/asm/atomic_64.h
@@ -20,14 +20,14 @@
20#define atomic64_set(v, i) (((v)->counter) = i) 20#define atomic64_set(v, i) (((v)->counter) = i)
21 21
22extern void atomic_add(int, atomic_t *); 22extern void atomic_add(int, atomic_t *);
23extern void atomic64_add(int, atomic64_t *); 23extern void atomic64_add(long, atomic64_t *);
24extern void atomic_sub(int, atomic_t *); 24extern void atomic_sub(int, atomic_t *);
25extern void atomic64_sub(int, atomic64_t *); 25extern void atomic64_sub(long, atomic64_t *);
26 26
27extern int atomic_add_ret(int, atomic_t *); 27extern int atomic_add_ret(int, atomic_t *);
28extern int atomic64_add_ret(int, atomic64_t *); 28extern long atomic64_add_ret(long, atomic64_t *);
29extern int atomic_sub_ret(int, atomic_t *); 29extern int atomic_sub_ret(int, atomic_t *);
30extern int atomic64_sub_ret(int, atomic64_t *); 30extern long atomic64_sub_ret(long, atomic64_t *);
31 31
32#define atomic_dec_return(v) atomic_sub_ret(1, v) 32#define atomic_dec_return(v) atomic_sub_ret(1, v)
33#define atomic64_dec_return(v) atomic64_sub_ret(1, v) 33#define atomic64_dec_return(v) atomic64_sub_ret(1, v)
@@ -91,7 +91,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
91 ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n))) 91 ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
92#define atomic64_xchg(v, new) (xchg(&((v)->counter), new)) 92#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
93 93
94static inline int atomic64_add_unless(atomic64_t *v, long a, long u) 94static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
95{ 95{
96 long c, old; 96 long c, old;
97 c = atomic64_read(v); 97 c = atomic64_read(v);
diff --git a/arch/sparc/include/asm/backoff.h b/arch/sparc/include/asm/backoff.h
index fa1fdf67e35..db3af0d30fb 100644
--- a/arch/sparc/include/asm/backoff.h
+++ b/arch/sparc/include/asm/backoff.h
@@ -8,6 +8,9 @@
8#define BACKOFF_SETUP(reg) \ 8#define BACKOFF_SETUP(reg) \
9 mov 1, reg 9 mov 1, reg
10 10
11#define BACKOFF_LABEL(spin_label, continue_label) \
12 spin_label
13
11#define BACKOFF_SPIN(reg, tmp, label) \ 14#define BACKOFF_SPIN(reg, tmp, label) \
12 mov reg, tmp; \ 15 mov reg, tmp; \
1388: brnz,pt tmp, 88b; \ 1688: brnz,pt tmp, 88b; \
@@ -22,9 +25,11 @@
22#else 25#else
23 26
24#define BACKOFF_SETUP(reg) 27#define BACKOFF_SETUP(reg)
25#define BACKOFF_SPIN(reg, tmp, label) \ 28
26 ba,pt %xcc, label; \ 29#define BACKOFF_LABEL(spin_label, continue_label) \
27 nop; 30 continue_label
31
32#define BACKOFF_SPIN(reg, tmp, label)
28 33
29#endif 34#endif
30 35
diff --git a/arch/sparc/include/asm/fb.h b/arch/sparc/include/asm/fb.h
index e834880be20..2173432ad7f 100644
--- a/arch/sparc/include/asm/fb.h
+++ b/arch/sparc/include/asm/fb.h
@@ -1,5 +1,6 @@
1#ifndef _SPARC_FB_H_ 1#ifndef _SPARC_FB_H_
2#define _SPARC_FB_H_ 2#define _SPARC_FB_H_
3#include <linux/console.h>
3#include <linux/fb.h> 4#include <linux/fb.h>
4#include <linux/fs.h> 5#include <linux/fs.h>
5#include <asm/page.h> 6#include <asm/page.h>
@@ -18,6 +19,9 @@ static inline int fb_is_primary_device(struct fb_info *info)
18 struct device *dev = info->device; 19 struct device *dev = info->device;
19 struct device_node *node; 20 struct device_node *node;
20 21
22 if (console_set_on_cmdline)
23 return 0;
24
21 node = dev->of_node; 25 node = dev->of_node;
22 if (node && 26 if (node &&
23 node == of_console_device) 27 node == of_console_device)
diff --git a/arch/sparc/include/asm/oplib_64.h b/arch/sparc/include/asm/oplib_64.h
index a5db0317b5f..3e0b2d62303 100644
--- a/arch/sparc/include/asm/oplib_64.h
+++ b/arch/sparc/include/asm/oplib_64.h
@@ -185,9 +185,8 @@ extern int prom_getunumber(int syndrome_code,
185 char *buf, int buflen); 185 char *buf, int buflen);
186 186
187/* Retain physical memory to the caller across soft resets. */ 187/* Retain physical memory to the caller across soft resets. */
188extern unsigned long prom_retain(const char *name, 188extern int prom_retain(const char *name, unsigned long size,
189 unsigned long pa_low, unsigned long pa_high, 189 unsigned long align, unsigned long *paddr);
190 long size, long align);
191 190
192/* Load explicit I/D TLB entries into the calling processor. */ 191/* Load explicit I/D TLB entries into the calling processor. */
193extern long prom_itlb_load(unsigned long index, 192extern long prom_itlb_load(unsigned long index,
@@ -287,26 +286,6 @@ extern void prom_sun4v_guest_soft_state(void);
287extern int prom_ihandle2path(int handle, char *buffer, int bufsize); 286extern int prom_ihandle2path(int handle, char *buffer, int bufsize);
288 287
289/* Client interface level routines. */ 288/* Client interface level routines. */
290extern long p1275_cmd(const char *, long, ...); 289extern void p1275_cmd_direct(unsigned long *);
291
292#if 0
293#define P1275_SIZE(x) ((((long)((x) / 32)) << 32) | (x))
294#else
295#define P1275_SIZE(x) x
296#endif
297
298/* We support at most 16 input and 1 output argument */
299#define P1275_ARG_NUMBER 0
300#define P1275_ARG_IN_STRING 1
301#define P1275_ARG_OUT_BUF 2
302#define P1275_ARG_OUT_32B 3
303#define P1275_ARG_IN_FUNCTION 4
304#define P1275_ARG_IN_BUF 5
305#define P1275_ARG_IN_64B 6
306
307#define P1275_IN(x) ((x) & 0xf)
308#define P1275_OUT(x) (((x) << 4) & 0xf0)
309#define P1275_INOUT(i,o) (P1275_IN(i)|P1275_OUT(o))
310#define P1275_ARG(n,x) ((x) << ((n)*3 + 8))
311 290
312#endif /* !(__SPARC64_OPLIB_H) */ 291#endif /* !(__SPARC64_OPLIB_H) */
diff --git a/arch/sparc/include/asm/rwsem-const.h b/arch/sparc/include/asm/rwsem-const.h
deleted file mode 100644
index a303c9d64d8..00000000000
--- a/arch/sparc/include/asm/rwsem-const.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/* rwsem-const.h: RW semaphore counter constants. */
2#ifndef _SPARC64_RWSEM_CONST_H
3#define _SPARC64_RWSEM_CONST_H
4
5#define RWSEM_UNLOCKED_VALUE 0x00000000
6#define RWSEM_ACTIVE_BIAS 0x00000001
7#define RWSEM_ACTIVE_MASK 0x0000ffff
8#define RWSEM_WAITING_BIAS 0xffff0000
9#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
10#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
11
12#endif /* _SPARC64_RWSEM_CONST_H */
diff --git a/arch/sparc/include/asm/rwsem.h b/arch/sparc/include/asm/rwsem.h
index 6e5621006f8..a2b4302869b 100644
--- a/arch/sparc/include/asm/rwsem.h
+++ b/arch/sparc/include/asm/rwsem.h
@@ -15,16 +15,21 @@
15 15
16#include <linux/list.h> 16#include <linux/list.h>
17#include <linux/spinlock.h> 17#include <linux/spinlock.h>
18#include <asm/rwsem-const.h>
19 18
20struct rwsem_waiter; 19struct rwsem_waiter;
21 20
22struct rw_semaphore { 21struct rw_semaphore {
23 signed int count; 22 signed long count;
24 spinlock_t wait_lock; 23#define RWSEM_UNLOCKED_VALUE 0x00000000L
25 struct list_head wait_list; 24#define RWSEM_ACTIVE_BIAS 0x00000001L
25#define RWSEM_ACTIVE_MASK 0xffffffffL
26#define RWSEM_WAITING_BIAS (-RWSEM_ACTIVE_MASK-1)
27#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
28#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
29 spinlock_t wait_lock;
30 struct list_head wait_list;
26#ifdef CONFIG_DEBUG_LOCK_ALLOC 31#ifdef CONFIG_DEBUG_LOCK_ALLOC
27 struct lockdep_map dep_map; 32 struct lockdep_map dep_map;
28#endif 33#endif
29}; 34};
30 35
@@ -41,6 +46,11 @@ struct rw_semaphore {
41#define DECLARE_RWSEM(name) \ 46#define DECLARE_RWSEM(name) \
42 struct rw_semaphore name = __RWSEM_INITIALIZER(name) 47 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
43 48
49extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
50extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
51extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
52extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
53
44extern void __init_rwsem(struct rw_semaphore *sem, const char *name, 54extern void __init_rwsem(struct rw_semaphore *sem, const char *name,
45 struct lock_class_key *key); 55 struct lock_class_key *key);
46 56
@@ -51,27 +61,103 @@ do { \
51 __init_rwsem((sem), #sem, &__key); \ 61 __init_rwsem((sem), #sem, &__key); \
52} while (0) 62} while (0)
53 63
54extern void __down_read(struct rw_semaphore *sem); 64/*
55extern int __down_read_trylock(struct rw_semaphore *sem); 65 * lock for reading
56extern void __down_write(struct rw_semaphore *sem); 66 */
57extern int __down_write_trylock(struct rw_semaphore *sem); 67static inline void __down_read(struct rw_semaphore *sem)
58extern void __up_read(struct rw_semaphore *sem); 68{
59extern void __up_write(struct rw_semaphore *sem); 69 if (unlikely(atomic64_inc_return((atomic64_t *)(&sem->count)) <= 0L))
60extern void __downgrade_write(struct rw_semaphore *sem); 70 rwsem_down_read_failed(sem);
71}
72
73static inline int __down_read_trylock(struct rw_semaphore *sem)
74{
75 long tmp;
76
77 while ((tmp = sem->count) >= 0L) {
78 if (tmp == cmpxchg(&sem->count, tmp,
79 tmp + RWSEM_ACTIVE_READ_BIAS)) {
80 return 1;
81 }
82 }
83 return 0;
84}
61 85
86/*
87 * lock for writing
88 */
62static inline void __down_write_nested(struct rw_semaphore *sem, int subclass) 89static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
63{ 90{
64 __down_write(sem); 91 long tmp;
92
93 tmp = atomic64_add_return(RWSEM_ACTIVE_WRITE_BIAS,
94 (atomic64_t *)(&sem->count));
95 if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
96 rwsem_down_write_failed(sem);
65} 97}
66 98
67static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem) 99static inline void __down_write(struct rw_semaphore *sem)
68{ 100{
69 return atomic_add_return(delta, (atomic_t *)(&sem->count)); 101 __down_write_nested(sem, 0);
102}
103
104static inline int __down_write_trylock(struct rw_semaphore *sem)
105{
106 long tmp;
107
108 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
109 RWSEM_ACTIVE_WRITE_BIAS);
110 return tmp == RWSEM_UNLOCKED_VALUE;
70} 111}
71 112
72static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem) 113/*
114 * unlock after reading
115 */
116static inline void __up_read(struct rw_semaphore *sem)
117{
118 long tmp;
119
120 tmp = atomic64_dec_return((atomic64_t *)(&sem->count));
121 if (unlikely(tmp < -1L && (tmp & RWSEM_ACTIVE_MASK) == 0L))
122 rwsem_wake(sem);
123}
124
125/*
126 * unlock after writing
127 */
128static inline void __up_write(struct rw_semaphore *sem)
129{
130 if (unlikely(atomic64_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
131 (atomic64_t *)(&sem->count)) < 0L))
132 rwsem_wake(sem);
133}
134
135/*
136 * implement atomic add functionality
137 */
138static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
139{
140 atomic64_add(delta, (atomic64_t *)(&sem->count));
141}
142
143/*
144 * downgrade write lock to read lock
145 */
146static inline void __downgrade_write(struct rw_semaphore *sem)
147{
148 long tmp;
149
150 tmp = atomic64_add_return(-RWSEM_WAITING_BIAS, (atomic64_t *)(&sem->count));
151 if (tmp < 0L)
152 rwsem_downgrade_wake(sem);
153}
154
155/*
156 * implement exchange and add functionality
157 */
158static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
73{ 159{
74 atomic_add(delta, (atomic_t *)(&sem->count)); 160 return atomic64_add_return(delta, (atomic64_t *)(&sem->count));
75} 161}
76 162
77static inline int rwsem_is_locked(struct rw_semaphore *sem) 163static inline int rwsem_is_locked(struct rw_semaphore *sem)
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h
index d24cfe16afc..e3b65d8cf41 100644
--- a/arch/sparc/include/asm/system_64.h
+++ b/arch/sparc/include/asm/system_64.h
@@ -106,6 +106,7 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \
106 */ 106 */
107#define write_pic(__p) \ 107#define write_pic(__p) \
108 __asm__ __volatile__("ba,pt %%xcc, 99f\n\t" \ 108 __asm__ __volatile__("ba,pt %%xcc, 99f\n\t" \
109 " nop\n\t" \
109 ".align 64\n" \ 110 ".align 64\n" \
110 "99:wr %0, 0x0, %%pic\n\t" \ 111 "99:wr %0, 0x0, %%pic\n\t" \
111 "rd %%pic, %%g0" : : "r" (__p)) 112 "rd %%pic, %%g0" : : "r" (__p))
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h
index d0b3b01ac9d..03eb5a8f6f9 100644
--- a/arch/sparc/include/asm/unistd.h
+++ b/arch/sparc/include/asm/unistd.h
@@ -397,8 +397,11 @@
397#define __NR_rt_tgsigqueueinfo 326 397#define __NR_rt_tgsigqueueinfo 326
398#define __NR_perf_event_open 327 398#define __NR_perf_event_open 327
399#define __NR_recvmmsg 328 399#define __NR_recvmmsg 328
400#define __NR_fanotify_init 329
401#define __NR_fanotify_mark 330
402#define __NR_prlimit64 331
400 403
401#define NR_syscalls 329 404#define NR_syscalls 332
402 405
403#ifdef __32bit_syscall_numbers__ 406#ifdef __32bit_syscall_numbers__
404/* Sparc 32-bit only has the "setresuid32", "getresuid32" variants, 407/* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,