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-rw-r--r--arch/sparc/include/asm/atomic_32.h104
-rw-r--r--arch/sparc/include/asm/io_32.h2
-rw-r--r--arch/sparc/include/asm/io_64.h2
-rw-r--r--arch/sparc/include/asm/page_32.h10
-rw-r--r--arch/sparc/include/asm/pgtsun4.h171
-rw-r--r--arch/sparc/include/asm/signal.h3
-rw-r--r--arch/sparc/include/asm/thread_info_32.h2
7 files changed, 9 insertions, 285 deletions
diff --git a/arch/sparc/include/asm/atomic_32.h b/arch/sparc/include/asm/atomic_32.h
index 5c3c8b69884..9dd0a769fa1 100644
--- a/arch/sparc/include/asm/atomic_32.h
+++ b/arch/sparc/include/asm/atomic_32.h
@@ -13,7 +13,7 @@
13 13
14#include <linux/types.h> 14#include <linux/types.h>
15 15
16#ifdef __KERNEL__ 16#include <asm-generic/atomic64.h>
17 17
18#include <asm/system.h> 18#include <asm/system.h>
19 19
@@ -52,112 +52,10 @@ extern void atomic_set(atomic_t *, int);
52#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0) 52#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
53#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0) 53#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
54 54
55
56/* This is the old 24-bit implementation. It's still used internally
57 * by some sparc-specific code, notably the semaphore implementation.
58 */
59typedef struct { volatile int counter; } atomic24_t;
60
61#ifndef CONFIG_SMP
62
63#define ATOMIC24_INIT(i) { (i) }
64#define atomic24_read(v) ((v)->counter)
65#define atomic24_set(v, i) (((v)->counter) = i)
66
67#else
68/* We do the bulk of the actual work out of line in two common
69 * routines in assembler, see arch/sparc/lib/atomic.S for the
70 * "fun" details.
71 *
72 * For SMP the trick is you embed the spin lock byte within
73 * the word, use the low byte so signedness is easily retained
74 * via a quick arithmetic shift. It looks like this:
75 *
76 * ----------------------------------------
77 * | signed 24-bit counter value | lock | atomic_t
78 * ----------------------------------------
79 * 31 8 7 0
80 */
81
82#define ATOMIC24_INIT(i) { ((i) << 8) }
83
84static inline int atomic24_read(const atomic24_t *v)
85{
86 int ret = v->counter;
87
88 while(ret & 0xff)
89 ret = v->counter;
90
91 return ret >> 8;
92}
93
94#define atomic24_set(v, i) (((v)->counter) = ((i) << 8))
95#endif
96
97static inline int __atomic24_add(int i, atomic24_t *v)
98{
99 register volatile int *ptr asm("g1");
100 register int increment asm("g2");
101 register int tmp1 asm("g3");
102 register int tmp2 asm("g4");
103 register int tmp3 asm("g7");
104
105 ptr = &v->counter;
106 increment = i;
107
108 __asm__ __volatile__(
109 "mov %%o7, %%g4\n\t"
110 "call ___atomic24_add\n\t"
111 " add %%o7, 8, %%o7\n"
112 : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
113 : "0" (increment), "r" (ptr)
114 : "memory", "cc");
115
116 return increment;
117}
118
119static inline int __atomic24_sub(int i, atomic24_t *v)
120{
121 register volatile int *ptr asm("g1");
122 register int increment asm("g2");
123 register int tmp1 asm("g3");
124 register int tmp2 asm("g4");
125 register int tmp3 asm("g7");
126
127 ptr = &v->counter;
128 increment = i;
129
130 __asm__ __volatile__(
131 "mov %%o7, %%g4\n\t"
132 "call ___atomic24_sub\n\t"
133 " add %%o7, 8, %%o7\n"
134 : "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)
135 : "0" (increment), "r" (ptr)
136 : "memory", "cc");
137
138 return increment;
139}
140
141#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))
142#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))
143
144#define atomic24_dec_return(v) __atomic24_sub(1, (v))
145#define atomic24_inc_return(v) __atomic24_add(1, (v))
146
147#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)
148#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)
149
150#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))
151#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))
152
153#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)
154
155/* Atomic operations are already serializing */ 55/* Atomic operations are already serializing */
156#define smp_mb__before_atomic_dec() barrier() 56#define smp_mb__before_atomic_dec() barrier()
157#define smp_mb__after_atomic_dec() barrier() 57#define smp_mb__after_atomic_dec() barrier()
158#define smp_mb__before_atomic_inc() barrier() 58#define smp_mb__before_atomic_inc() barrier()
159#define smp_mb__after_atomic_inc() barrier() 59#define smp_mb__after_atomic_inc() barrier()
160 60
161#endif /* !(__KERNEL__) */
162
163#endif /* !(__ARCH_SPARC_ATOMIC__) */ 61#endif /* !(__ARCH_SPARC_ATOMIC__) */
diff --git a/arch/sparc/include/asm/io_32.h b/arch/sparc/include/asm/io_32.h
index c2ced21c9dc..2006e5d359d 100644
--- a/arch/sparc/include/asm/io_32.h
+++ b/arch/sparc/include/asm/io_32.h
@@ -7,6 +7,7 @@
7 7
8#include <asm/page.h> /* IO address mapping routines need this */ 8#include <asm/page.h> /* IO address mapping routines need this */
9#include <asm/system.h> 9#include <asm/system.h>
10#include <asm-generic/pci_iomap.h>
10 11
11#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) 12#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
12 13
@@ -324,7 +325,6 @@ extern void ioport_unmap(void __iomem *);
324 325
325/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ 326/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
326struct pci_dev; 327struct pci_dev;
327extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
328extern void pci_iounmap(struct pci_dev *dev, void __iomem *); 328extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
329 329
330/* 330/*
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
index 9c8965415f0..9481e5a6fa9 100644
--- a/arch/sparc/include/asm/io_64.h
+++ b/arch/sparc/include/asm/io_64.h
@@ -8,6 +8,7 @@
8#include <asm/page.h> /* IO address mapping routines need this */ 8#include <asm/page.h> /* IO address mapping routines need this */
9#include <asm/system.h> 9#include <asm/system.h>
10#include <asm/asi.h> 10#include <asm/asi.h>
11#include <asm-generic/pci_iomap.h>
11 12
12/* PC crapola... */ 13/* PC crapola... */
13#define __SLOW_DOWN_IO do { } while (0) 14#define __SLOW_DOWN_IO do { } while (0)
@@ -514,7 +515,6 @@ extern void ioport_unmap(void __iomem *);
514 515
515/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ 516/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
516struct pci_dev; 517struct pci_dev;
517extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
518extern void pci_iounmap(struct pci_dev *dev, void __iomem *); 518extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
519 519
520static inline int sbus_can_dma_64bit(void) 520static inline int sbus_can_dma_64bit(void)
diff --git a/arch/sparc/include/asm/page_32.h b/arch/sparc/include/asm/page_32.h
index 156707b0f18..bb5c2ac4055 100644
--- a/arch/sparc/include/asm/page_32.h
+++ b/arch/sparc/include/asm/page_32.h
@@ -8,14 +8,10 @@
8#ifndef _SPARC_PAGE_H 8#ifndef _SPARC_PAGE_H
9#define _SPARC_PAGE_H 9#define _SPARC_PAGE_H
10 10
11#define PAGE_SHIFT 12 11#include <linux/const.h>
12 12
13#ifndef __ASSEMBLY__ 13#define PAGE_SHIFT 12
14/* I have my suspicions... -DaveM */ 14#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
15#define PAGE_SIZE (1UL << PAGE_SHIFT)
16#else
17#define PAGE_SIZE (1 << PAGE_SHIFT)
18#endif
19#define PAGE_MASK (~(PAGE_SIZE-1)) 15#define PAGE_MASK (~(PAGE_SIZE-1))
20 16
21#include <asm/btfixup.h> 17#include <asm/btfixup.h>
diff --git a/arch/sparc/include/asm/pgtsun4.h b/arch/sparc/include/asm/pgtsun4.h
deleted file mode 100644
index 5a0d661fb82..00000000000
--- a/arch/sparc/include/asm/pgtsun4.h
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * pgtsun4.h: Sun4 specific pgtable.h defines and code.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7#ifndef _SPARC_PGTSUN4C_H
8#define _SPARC_PGTSUN4C_H
9
10#include <asm/contregs.h>
11
12/* PMD_SHIFT determines the size of the area a second-level page table can map */
13#define SUN4C_PMD_SHIFT 23
14
15/* PGDIR_SHIFT determines what a third-level page table entry can map */
16#define SUN4C_PGDIR_SHIFT 23
17#define SUN4C_PGDIR_SIZE (1UL << SUN4C_PGDIR_SHIFT)
18#define SUN4C_PGDIR_MASK (~(SUN4C_PGDIR_SIZE-1))
19#define SUN4C_PGDIR_ALIGN(addr) (((addr)+SUN4C_PGDIR_SIZE-1)&SUN4C_PGDIR_MASK)
20
21/* To represent how the sun4c mmu really lays things out. */
22#define SUN4C_REAL_PGDIR_SHIFT 18
23#define SUN4C_REAL_PGDIR_SIZE (1UL << SUN4C_REAL_PGDIR_SHIFT)
24#define SUN4C_REAL_PGDIR_MASK (~(SUN4C_REAL_PGDIR_SIZE-1))
25#define SUN4C_REAL_PGDIR_ALIGN(addr) (((addr)+SUN4C_REAL_PGDIR_SIZE-1)&SUN4C_REAL_PGDIR_MASK)
26
27/* 19 bit PFN on sun4 */
28#define SUN4C_PFN_MASK 0x7ffff
29
30/* Don't increase these unless the structures in sun4c.c are fixed */
31#define SUN4C_MAX_SEGMAPS 256
32#define SUN4C_MAX_CONTEXTS 16
33
34/*
35 * To be efficient, and not have to worry about allocating such
36 * a huge pgd, we make the kernel sun4c tables each hold 1024
37 * entries and the pgd similarly just like the i386 tables.
38 */
39#define SUN4C_PTRS_PER_PTE 1024
40#define SUN4C_PTRS_PER_PMD 1
41#define SUN4C_PTRS_PER_PGD 1024
42
43/*
44 * Sparc SUN4C pte fields.
45 */
46#define _SUN4C_PAGE_VALID 0x80000000
47#define _SUN4C_PAGE_SILENT_READ 0x80000000 /* synonym */
48#define _SUN4C_PAGE_DIRTY 0x40000000
49#define _SUN4C_PAGE_SILENT_WRITE 0x40000000 /* synonym */
50#define _SUN4C_PAGE_PRIV 0x20000000 /* privileged page */
51#define _SUN4C_PAGE_NOCACHE 0x10000000 /* non-cacheable page */
52#define _SUN4C_PAGE_PRESENT 0x08000000 /* implemented in software */
53#define _SUN4C_PAGE_IO 0x04000000 /* I/O page */
54#define _SUN4C_PAGE_FILE 0x02000000 /* implemented in software */
55#define _SUN4C_PAGE_READ 0x00800000 /* implemented in software */
56#define _SUN4C_PAGE_WRITE 0x00400000 /* implemented in software */
57#define _SUN4C_PAGE_ACCESSED 0x00200000 /* implemented in software */
58#define _SUN4C_PAGE_MODIFIED 0x00100000 /* implemented in software */
59
60#define _SUN4C_READABLE (_SUN4C_PAGE_READ|_SUN4C_PAGE_SILENT_READ|\
61 _SUN4C_PAGE_ACCESSED)
62#define _SUN4C_WRITEABLE (_SUN4C_PAGE_WRITE|_SUN4C_PAGE_SILENT_WRITE|\
63 _SUN4C_PAGE_MODIFIED)
64
65#define _SUN4C_PAGE_CHG_MASK (0xffff|_SUN4C_PAGE_ACCESSED|_SUN4C_PAGE_MODIFIED)
66
67#define SUN4C_PAGE_NONE __pgprot(_SUN4C_PAGE_PRESENT)
68#define SUN4C_PAGE_SHARED __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE|\
69 _SUN4C_PAGE_WRITE)
70#define SUN4C_PAGE_COPY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
71#define SUN4C_PAGE_READONLY __pgprot(_SUN4C_PAGE_PRESENT|_SUN4C_READABLE)
72#define SUN4C_PAGE_KERNEL __pgprot(_SUN4C_READABLE|_SUN4C_WRITEABLE|\
73 _SUN4C_PAGE_DIRTY|_SUN4C_PAGE_PRIV)
74
75/* SUN4C swap entry encoding
76 *
77 * We use 5 bits for the type and 19 for the offset. This gives us
78 * 32 swapfiles of 4GB each. Encoding looks like:
79 *
80 * RRRRRRRRooooooooooooooooooottttt
81 * fedcba9876543210fedcba9876543210
82 *
83 * The top 8 bits are reserved for protection and status bits, especially
84 * FILE and PRESENT.
85 */
86#define SUN4C_SWP_TYPE_MASK 0x1f
87#define SUN4C_SWP_OFF_MASK 0x7ffff
88#define SUN4C_SWP_OFF_SHIFT 5
89
90#ifndef __ASSEMBLY__
91
92static inline unsigned long sun4c_get_synchronous_error(void)
93{
94 unsigned long sync_err;
95
96 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
97 "=r" (sync_err) :
98 "r" (AC_SYNC_ERR), "i" (ASI_CONTROL));
99 return sync_err;
100}
101
102static inline unsigned long sun4c_get_synchronous_address(void)
103{
104 unsigned long sync_addr;
105
106 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
107 "=r" (sync_addr) :
108 "r" (AC_SYNC_VA), "i" (ASI_CONTROL));
109 return sync_addr;
110}
111
112/* SUN4 pte, segmap, and context manipulation */
113static inline unsigned long sun4c_get_segmap(unsigned long addr)
114{
115 register unsigned long entry;
116
117 __asm__ __volatile__("\n\tlduha [%1] %2, %0\n\t" :
118 "=r" (entry) :
119 "r" (addr), "i" (ASI_SEGMAP));
120 return entry;
121}
122
123static inline void sun4c_put_segmap(unsigned long addr, unsigned long entry)
124{
125 __asm__ __volatile__("\n\tstha %1, [%0] %2; nop; nop; nop;\n\t" : :
126 "r" (addr), "r" (entry),
127 "i" (ASI_SEGMAP)
128 : "memory");
129}
130
131static inline unsigned long sun4c_get_pte(unsigned long addr)
132{
133 register unsigned long entry;
134
135 __asm__ __volatile__("\n\tlda [%1] %2, %0\n\t" :
136 "=r" (entry) :
137 "r" (addr), "i" (ASI_PTE));
138 return entry;
139}
140
141static inline void sun4c_put_pte(unsigned long addr, unsigned long entry)
142{
143 __asm__ __volatile__("\n\tsta %1, [%0] %2; nop; nop; nop;\n\t" : :
144 "r" (addr),
145 "r" ((entry & ~(_SUN4C_PAGE_PRESENT))), "i" (ASI_PTE)
146 : "memory");
147}
148
149static inline int sun4c_get_context(void)
150{
151 register int ctx;
152
153 __asm__ __volatile__("\n\tlduba [%1] %2, %0\n\t" :
154 "=r" (ctx) :
155 "r" (AC_CONTEXT), "i" (ASI_CONTROL));
156
157 return ctx;
158}
159
160static inline int sun4c_set_context(int ctx)
161{
162 __asm__ __volatile__("\n\tstba %0, [%1] %2; nop; nop; nop;\n\t" : :
163 "r" (ctx), "r" (AC_CONTEXT), "i" (ASI_CONTROL)
164 : "memory");
165
166 return ctx;
167}
168
169#endif /* !(__ASSEMBLY__) */
170
171#endif /* !(_SPARC_PGTSUN4_H) */
diff --git a/arch/sparc/include/asm/signal.h b/arch/sparc/include/asm/signal.h
index e49b828a247..aa42fe30d5b 100644
--- a/arch/sparc/include/asm/signal.h
+++ b/arch/sparc/include/asm/signal.h
@@ -143,10 +143,11 @@ struct sigstack {
143#define SA_ONSTACK _SV_SSTACK 143#define SA_ONSTACK _SV_SSTACK
144#define SA_RESTART _SV_INTR 144#define SA_RESTART _SV_INTR
145#define SA_ONESHOT _SV_RESET 145#define SA_ONESHOT _SV_RESET
146#define SA_NOMASK 0x20u 146#define SA_NODEFER 0x20u
147#define SA_NOCLDWAIT 0x100u 147#define SA_NOCLDWAIT 0x100u
148#define SA_SIGINFO 0x200u 148#define SA_SIGINFO 0x200u
149 149
150#define SA_NOMASK SA_NODEFER
150 151
151#define SIG_BLOCK 0x01 /* for blocking signals */ 152#define SIG_BLOCK 0x01 /* for blocking signals */
152#define SIG_UNBLOCK 0x02 /* for unblocking signals */ 153#define SIG_UNBLOCK 0x02 /* for unblocking signals */
diff --git a/arch/sparc/include/asm/thread_info_32.h b/arch/sparc/include/asm/thread_info_32.h
index 5cc5888ad5a..c2a1080cdd3 100644
--- a/arch/sparc/include/asm/thread_info_32.h
+++ b/arch/sparc/include/asm/thread_info_32.h
@@ -95,7 +95,7 @@ BTFIXUPDEF_CALL(void, free_thread_info, struct thread_info *)
95 * Observe the order of get_free_pages() in alloc_thread_info_node(). 95 * Observe the order of get_free_pages() in alloc_thread_info_node().
96 * The sun4 has 8K stack too, because it's short on memory, and 16K is a waste. 96 * The sun4 has 8K stack too, because it's short on memory, and 16K is a waste.
97 */ 97 */
98#define THREAD_SIZE 8192 98#define THREAD_SIZE (2 * PAGE_SIZE)
99 99
100/* 100/*
101 * Offsets in thread_info structure, used in assembly code 101 * Offsets in thread_info structure, used in assembly code
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 07:19:33 -0400