0 files changed, 0 insertions, 0 deletions
diff --git a/CREDITS b/CREDITS
index 44fce988eaa..370b4c7da39 100644
--- a/CREDITS
+++ b/CREDITS
@@ -514,6 +514,11 @@ S: Bessemerstraat 21
 S: Amsterdam
 S: The Netherlands
+N: NeilBrown
+E: neil@brown.name
+P: 4096R/566281B9 1BC6 29EB D390 D870 7B5F  497A 39EC 9EDD 5662 81B9
+D: NFSD Maintainer 2000-2007
 N: Zach Brown
 E: zab@zabbo.net
 D: maestro pci sound
diff --git a/Documentation/ABI/stable/sysfs-bus-xen-backend b/Documentation/ABI/stable/sysfs-bus-xen-backend
new file mode 100644
index 00000000000..3d5951c8bf5
--- /dev/null
+++ b/Documentation/ABI/stable/sysfs-bus-xen-backend
@@ -0,0 +1,75 @@
+What:           /sys/bus/xen-backend/devices/*/devtype
+Date:           Feb 2009
+KernelVersion:  2.6.38
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                The type of the device.  e.g., one of: 'vbd' (block),
+                'vif' (network), or 'vfb' (framebuffer).
+What:           /sys/bus/xen-backend/devices/*/nodename
+Date:           Feb 2009
+KernelVersion:  2.6.38
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                XenStore node (under /local/domain/NNN/) for this
+                backend device.
+What:           /sys/bus/xen-backend/devices/vbd-*/physical_device
+Date:           April 2011
+KernelVersion:  3.0
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                The major:minor number (in hexidecimal) of the
+                physical device providing the storage for this backend
+                block device.
+What:           /sys/bus/xen-backend/devices/vbd-*/mode
+Date:           April 2011
+KernelVersion:  3.0
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                Whether the block device is read-only ('r') or
+                read-write ('w').
+What:           /sys/bus/xen-backend/devices/vbd-*/statistics/f_req
+Date:           April 2011
+KernelVersion:  3.0
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                Number of flush requests from the frontend.
+What:           /sys/bus/xen-backend/devices/vbd-*/statistics/oo_req
+Date:           April 2011
+KernelVersion:  3.0
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                Number of requests delayed because the backend was too
+                busy processing previous requests.
+What:           /sys/bus/xen-backend/devices/vbd-*/statistics/rd_req
+Date:           April 2011
+KernelVersion:  3.0
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                Number of read requests from the frontend.
+What:           /sys/bus/xen-backend/devices/vbd-*/statistics/rd_sect
+Date:           April 2011
+KernelVersion:  3.0
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                Number of sectors read by the frontend.
+What:           /sys/bus/xen-backend/devices/vbd-*/statistics/wr_req
+Date:           April 2011
+KernelVersion:  3.0
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                Number of write requests from the frontend.
+What:           /sys/bus/xen-backend/devices/vbd-*/statistics/wr_sect
+Date:           April 2011
+KernelVersion:  3.0
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                Number of sectors written by the frontend.
diff --git a/Documentation/ABI/stable/sysfs-devices-system-xen_memory b/Documentation/ABI/stable/sysfs-devices-system-xen_memory
new file mode 100644
index 00000000000..caa311d59ac
--- /dev/null
+++ b/Documentation/ABI/stable/sysfs-devices-system-xen_memory
@@ -0,0 +1,77 @@
+What:           /sys/devices/system/xen_memory/xen_memory0/max_retry_count
+Date:           May 2011
+KernelVersion:  2.6.39
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                The maximum number of times the balloon driver will
+                attempt to increase the balloon before giving up.  See
+                also 'retry_count' below.
+                A value of zero means retry forever and is the default one.
+What:           /sys/devices/system/xen_memory/xen_memory0/max_schedule_delay
+Date:           May 2011
+KernelVersion:  2.6.39
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                The limit that 'schedule_delay' (see below) will be
+                increased to. The default value is 32 seconds.
+What:           /sys/devices/system/xen_memory/xen_memory0/retry_count
+Date:           May 2011
+KernelVersion:  2.6.39
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                The current number of times that the balloon driver
+                has attempted to increase the size of the balloon.
+                The default value is one. With max_retry_count being
+                zero (unlimited), this means that the driver will attempt
+                to retry with a 'schedule_delay' delay.
+What:           /sys/devices/system/xen_memory/xen_memory0/schedule_delay
+Date:           May 2011
+KernelVersion:  2.6.39
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                The time (in seconds) to wait between attempts to
+                increase the balloon.  Each time the balloon cannot be
+                increased, 'schedule_delay' is increased (until
+                'max_schedule_delay' is reached at which point it
+                will use the max value).
+What:           /sys/devices/system/xen_memory/xen_memory0/target
+Date:           April 2008
+KernelVersion:  2.6.26
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                The target number of pages to adjust this domain's
+                memory reservation to.
+What:           /sys/devices/system/xen_memory/xen_memory0/target_kb
+Date:           April 2008
+KernelVersion:  2.6.26
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                As target above, except the value is in KiB.
+What:           /sys/devices/system/xen_memory/xen_memory0/info/current_kb
+Date:           April 2008
+KernelVersion:  2.6.26
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                Current size (in KiB) of this domain's memory
+                reservation.
+What:           /sys/devices/system/xen_memory/xen_memory0/info/high_kb
+Date:           April 2008
+KernelVersion:  2.6.26
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                Amount (in KiB) of high memory in the balloon.
+What:           /sys/devices/system/xen_memory/xen_memory0/info/low_kb
+Date:           April 2008
+KernelVersion:  2.6.26
+Contact:        Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
+Description:
+                Amount (in KiB) of low (or normal) memory in the
+                balloon.
diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci
index 349ecf26ce1..34f51100f02 100644
--- a/Documentation/ABI/testing/sysfs-bus-pci
+++ b/Documentation/ABI/testing/sysfs-bus-pci
@@ -66,6 +66,24 @@ Description:
                re-discover previously removed devices.
                Depends on CONFIG_HOTPLUG.
+What:           /sys/bus/pci/devices/.../msi_irqs/
+Date:           September, 2011
+Contact:        Neil Horman <nhorman@tuxdriver.com>
+Description:
+                The /sys/devices/.../msi_irqs directory contains a variable set
+                of sub-directories, with each sub-directory being named after a
+                corresponding msi irq vector allocated to that device.  Each
+                numbered sub-directory N contains attributes of that irq.
+                Note that this directory is not created for device drivers which
+                do not support msi irqs
+What:           /sys/bus/pci/devices/.../msi_irqs/<N>/mode
+Date:           September 2011
+Contact:        Neil Horman <nhorman@tuxdriver.com>
+Description:
+                This attribute indicates the mode that the irq vector named by
+                the parent directory is in (msi vs. msix)
 What:           /sys/bus/pci/devices/.../remove
 Date:           January 2009
 Contact:        Linux PCI developers <linux-pci@vger.kernel.org>
diff --git a/Documentation/ABI/testing/sysfs-bus-usb b/Documentation/ABI/testing/sysfs-bus-usb
index e647378e9e8..b4f548792e3 100644
--- a/Documentation/ABI/testing/sysfs-bus-usb
+++ b/Documentation/ABI/testing/sysfs-bus-usb
@@ -119,6 +119,31 @@ Description:
                Write a 1 to force the device to disconnect
                (equivalent to unplugging a wired USB device).
+What:           /sys/bus/usb/drivers/.../new_id
+Date:           October 2011
+Contact:        linux-usb@vger.kernel.org
+Description:
+                Writing a device ID to this file will attempt to
+                dynamically add a new device ID to a USB device driver.
+                This may allow the driver to support more hardware than
+                was included in the driver's static device ID support
+                table at compile time. The format for the device ID is:
+                idVendor idProduct bInterfaceClass.
+                The vendor ID and device ID fields are required, the
+                interface class is optional.
+                Upon successfully adding an ID, the driver will probe
+                for the device and attempt to bind to it.  For example:
+                # echo "8086 10f5" > /sys/bus/usb/drivers/foo/new_id
+What:           /sys/bus/usb-serial/drivers/.../new_id
+Date:           October 2011
+Contact:        linux-usb@vger.kernel.org
+Description:
+                For serial USB drivers, this attribute appears under the
+                extra bus folder "usb-serial" in sysfs; apart from that
+                difference, all descriptions from the entry
+                "/sys/bus/usb/drivers/.../new_id" apply.
 What:           /sys/bus/usb/drivers/.../remove_id
 Date:           November 2009
 Contact:        CHENG Renquan <rqcheng@smu.edu.sg>
diff --git a/Documentation/ABI/testing/sysfs-class-rtc-rtc0-device-rtc_calibration b/Documentation/ABI/testing/sysfs-class-rtc-rtc0-device-rtc_calibration
new file mode 100644
index 00000000000..4cf1e72222d
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-class-rtc-rtc0-device-rtc_calibration
@@ -0,0 +1,12 @@
+What:           Attribute for calibrating ST-Ericsson AB8500 Real Time Clock
+Date:           Oct 2011
+KernelVersion:  3.0
+Contact:        Mark Godfrey <mark.godfrey@stericsson.com>
+Description:    The rtc_calibration attribute allows the userspace to
+                calibrate the AB8500.s 32KHz Real Time Clock.
+                Every 60 seconds the AB8500 will correct the RTC's value
+                by adding to it the value of this attribute.
+                The range of the attribute is -127 to +127 in units of
+                30.5 micro-seconds (half-parts-per-million of the 32KHz clock)
+Users:          The /vendor/st-ericsson/base_utilities/core/rtc_calibration
+                daemon uses this interface.
diff --git a/Documentation/ABI/testing/sysfs-devices-platform-docg3 b/Documentation/ABI/testing/sysfs-devices-platform-docg3
new file mode 100644
index 00000000000..8aa36716882
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-platform-docg3
@@ -0,0 +1,34 @@
+What:           /sys/devices/platform/docg3/f[0-3]_dps[01]_is_keylocked
+Date:           November 2011
+KernelVersion:  3.3
+Contact:        Robert Jarzmik <robert.jarzmik@free.fr>
+Description:
+                Show whether the floor (0 to 4), protection area (0 or 1) is
+                keylocked. Each docg3 chip (or floor) has 2 protection areas,
+                which can cover any part of it, block aligned, called DPS.
+                The protection has information embedded whether it blocks reads,
+                writes or both.
+                The result is:
+                0 -> the DPS is not keylocked
+                1 -> the DPS is keylocked
+Users:          None identified so far.
+What:           /sys/devices/platform/docg3/f[0-3]_dps[01]_protection_key
+Date:           November 2011
+KernelVersion:  3.3
+Contact:        Robert Jarzmik <robert.jarzmik@free.fr>
+Description:
+                Enter the protection key for the floor (0 to 4), protection area
+                (0 or 1). Each docg3 chip (or floor) has 2 protection areas,
+                which can cover any part of it, block aligned, called DPS.
+                The protection has information embedded whether it blocks reads,
+                writes or both.
+                The protection key is a string of 8 bytes (value 0-255).
+                Entering the correct value toggle the lock, and can be observed
+                through f[0-3]_dps[01]_is_keylocked.
+                Possible values are:
+                        - 8 bytes
+                Typical values are:
+                        - "00000000"
+                        - "12345678"
+Users:          None identified so far.
diff --git a/Documentation/ABI/testing/sysfs-driver-hid-logitech-lg4ff b/Documentation/ABI/testing/sysfs-driver-hid-logitech-lg4ff
index 9aec8ef228b..167d9032b97 100644
--- a/Documentation/ABI/testing/sysfs-driver-hid-logitech-lg4ff
+++ b/Documentation/ABI/testing/sysfs-driver-hid-logitech-lg4ff
@@ -1,7 +1,7 @@
 What:           /sys/module/hid_logitech/drivers/hid:logitech/<dev>/range.
 Date:           July 2011
 KernelVersion:  3.2
-Contact:        Michal Mal� <madcatxster@gmail.com>
+Contact:        Michal Malý <madcatxster@gmail.com>
 Description:    Display minimum, maximum and current range of the steering
                wheel. Writing a value within min and max boundaries sets the
                range of the wheel.
diff --git a/Documentation/ABI/testing/sysfs-driver-hid-multitouch b/Documentation/ABI/testing/sysfs-driver-hid-multitouch
new file mode 100644
index 00000000000..f79839d1af3
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-hid-multitouch
@@ -0,0 +1,9 @@
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/quirks
+Date:           November 2011
+Contact:        Benjamin Tissoires <benjamin.tissoires@gmail.com>
+Description:    The integer value of this attribute corresponds to the
+                quirks actually in place to handle the device's protocol.
+                When read, this attribute returns the current settings (see
+                MT_QUIRKS_* in hid-multitouch.c).
+                When written this attribute change on the fly the quirks, then
+                the protocol to handle the device.
diff --git a/Documentation/ABI/testing/sysfs-driver-hid-roccat-isku b/Documentation/ABI/testing/sysfs-driver-hid-roccat-isku
new file mode 100644
index 00000000000..189dc43891b
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-hid-roccat-isku
@@ -0,0 +1,135 @@
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/actual_profile
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    The integer value of this attribute ranges from 0-4.
+                When read, this attribute returns the number of the actual
+                profile. This value is persistent, so its equivalent to the
+                profile that's active when the device is powered on next time.
+                When written, this file sets the number of the startup profile
+                and the device activates this profile immediately.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/info
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When read, this file returns general data like firmware version.
+                The data is 6 bytes long.
+                This file is readonly.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/key_mask
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one deactivate certain keys like
+                windows and application keys, to prevent accidental presses.
+                Profile number for which this settings occur is included in
+                written data. The data has to be 6 bytes long.
+                Before reading this file, control has to be written to select
+                which profile to read.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/keys_capslock
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one set the function of the
+                capslock key for a specific profile. Profile number is included
+                in written data. The data has to be 6 bytes long.
+                Before reading this file, control has to be written to select
+                which profile to read.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/keys_easyzone
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one set the function of the
+                easyzone keys for a specific profile. Profile number is included
+                in written data. The data has to be 65 bytes long.
+                Before reading this file, control has to be written to select
+                which profile to read.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/keys_function
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one set the function of the
+                function keys for a specific profile. Profile number is included
+                in written data. The data has to be 41 bytes long.
+                Before reading this file, control has to be written to select
+                which profile to read.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/keys_macro
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one set the function of the macro
+                keys for a specific profile. Profile number is included in
+                written data. The data has to be 35 bytes long.
+                Before reading this file, control has to be written to select
+                which profile to read.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/keys_media
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one set the function of the media
+                keys for a specific profile. Profile number is included in
+                written data. The data has to be 29 bytes long.
+                Before reading this file, control has to be written to select
+                which profile to read.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/keys_thumbster
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one set the function of the
+                thumbster keys for a specific profile. Profile number is included
+                in written data. The data has to be 23 bytes long.
+                Before reading this file, control has to be written to select
+                which profile to read.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/last_set
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one set the time in secs since
+                epoch in which the last configuration took place.
+                The data has to be 20 bytes long.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/light
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one set the backlight intensity for
+                a specific profile. Profile number is included in written data.
+                The data has to be 10 bytes long.
+                Before reading this file, control has to be written to select
+                which profile to read.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/macro
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one store macros with max 500
+                keystrokes for a specific button for a specific profile.
+                Button and profile numbers are included in written data.
+                The data has to be 2083 bytes long.
+                Before reading this file, control has to be written to select
+                which profile and key to read.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/control
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one select which data from which
+                profile will be read next. The data has to be 3 bytes long.
+                This file is writeonly.
+Users:          http://roccat.sourceforge.net
+What:           /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<product-id>.<num>/isku/roccatisku<minor>/talk
+Date:           June 2011
+Contact:        Stefan Achatz <erazor_de@users.sourceforge.net>
+Description:    When written, this file lets one trigger easyshift functionality
+                from the host.
+                The data has to be 16 bytes long.
+                This file is writeonly.
+Users:          http://roccat.sourceforge.net
diff --git a/Documentation/ABI/testing/sysfs-driver-hid-wiimote b/Documentation/ABI/testing/sysfs-driver-hid-wiimote
index 5d5a16ea57c..3d98009f447 100644
--- a/Documentation/ABI/testing/sysfs-driver-hid-wiimote
+++ b/Documentation/ABI/testing/sysfs-driver-hid-wiimote
@@ -8,3 +8,15 @@ Contact:	David Herrmann <dh.herrmann@googlemail.com>
 Description:    Make it possible to set/get current led state. Reading from it
                returns 0 if led is off and 1 if it is on. Writing 0 to it
                disables the led, writing 1 enables it.
+What:           /sys/bus/hid/drivers/wiimote/<dev>/extension
+Date:           August 2011
+KernelVersion:  3.2
+Contact:        David Herrmann <dh.herrmann@googlemail.com>
+Description:    This file contains the currently connected and initialized
+                extensions. It can be one of: none, motionp, nunchuck, classic,
+                motionp+nunchuck, motionp+classic
+                motionp is the official Nintendo Motion+ extension, nunchuck is
+                the official Nintendo Nunchuck extension and classic is the
+                Nintendo Classic Controller extension. The motionp extension can
+                be combined with the other two.
diff --git a/Documentation/ABI/testing/sysfs-driver-wacom b/Documentation/ABI/testing/sysfs-driver-wacom
index 82d4df13644..0130d6683c1 100644
--- a/Documentation/ABI/testing/sysfs-driver-wacom
+++ b/Documentation/ABI/testing/sysfs-driver-wacom
@@ -15,9 +15,9 @@ Contact:	linux-input@vger.kernel.org
 Description:
                Attribute group for control of the status LEDs and the OLEDs.
                This attribute group is only available for Intuos 4 M, L,
-                and XL (with LEDs and OLEDs) and Cintiq 21UX2 (LEDs only).
+                and XL (with LEDs and OLEDs) and Cintiq 21UX2 and Cintiq 24HD
-                Therefore its presence implicitly signifies the presence of
+                (LEDs only). Therefore its presence implicitly signifies the
-                said LEDs and OLEDs on the tablet device.
+                presence of said LEDs and OLEDs on the tablet device.
 What:           /sys/bus/usb/devices/<busnum>-<devnum>:<cfg>.<intf>/wacom_led/status0_luminance
 Date:           August 2011
@@ -41,16 +41,17 @@ Date:		August 2011
 Contact:        linux-input@vger.kernel.org
 Description:
                Writing to this file sets which one of the four (for Intuos 4)
-                or of the right four (for Cintiq 21UX2) status LEDs is active (0..3).
+                or of the right four (for Cintiq 21UX2 and Cintiq 24HD) status
-                The other three LEDs on the same side are always inactive.
+                LEDs is active (0..3). The other three LEDs on the same side are
+                always inactive.
 What:           /sys/bus/usb/devices/<busnum>-<devnum>:<cfg>.<intf>/wacom_led/status_led1_select
 Date:           September 2011
 Contact:        linux-input@vger.kernel.org
 Description:
-                Writing to this file sets which one of the left four (for Cintiq 21UX2)
+                Writing to this file sets which one of the left four (for Cintiq 21UX2
-                status LEDs is active (0..3). The other three LEDs on the left are always
+                and Cintiq 24HD) status LEDs is active (0..3). The other three LEDs on
-                inactive.
+                the left are always inactive.
 What:           /sys/bus/usb/devices/<busnum>-<devnum>:<cfg>.<intf>/wacom_led/buttons_luminance
 Date:           August 2011
diff --git a/Documentation/ABI/testing/sysfs-kernel-slab b/Documentation/ABI/testing/sysfs-kernel-slab
index 8b093f8222d..91bd6ca5440 100644
--- a/Documentation/ABI/testing/sysfs-kernel-slab
+++ b/Documentation/ABI/testing/sysfs-kernel-slab
@@ -346,6 +346,10 @@ Description:
                number of objects per slab.  If a slab cannot be allocated
                because of fragmentation, SLUB will retry with the minimum order
                possible depending on its characteristics.
+                When debug_guardpage_minorder=N (N > 0) parameter is specified
+                (see Documentation/kernel-parameters.txt), the minimum possible
+                order is used and this sysfs entry can not be used to change
+                the order at run time.
 What:           /sys/kernel/slab/cache/order_fallback
 Date:           April 2008
diff --git a/Documentation/ABI/testing/sysfs-module b/Documentation/ABI/testing/sysfs-module
index 9489ea8e294..47064c2b1f7 100644
--- a/Documentation/ABI/testing/sysfs-module
+++ b/Documentation/ABI/testing/sysfs-module
@@ -33,3 +33,19 @@ Description:	Maximum time allowed for periodic transfers per microframe (μs)
                Beware, non-standard modes are usually not thoroughly tested by
                hardware designers, and the hardware can malfunction when this
                setting differ from default 100.
+What:           /sys/module/*/{coresize,initsize}
+Date:           Jan 2012
+KernelVersion:»·3.3
+Contact:        Kay Sievers <kay.sievers@vrfy.org>
+Description:    Module size in bytes.
+What:           /sys/module/*/taint
+Date:           Jan 2012
+KernelVersion:»·3.3
+Contact:        Kay Sievers <kay.sievers@vrfy.org>
+Description:    Module taint flags:
+                        P - proprietary module
+                        O - out-of-tree module
+                        F - force-loaded module
+                        C - staging driver module
diff --git a/Documentation/DocBook/debugobjects.tmpl b/Documentation/DocBook/debugobjects.tmpl
index 08ff908aa7a..24979f691e3 100644
--- a/Documentation/DocBook/debugobjects.tmpl
+++ b/Documentation/DocBook/debugobjects.tmpl
@@ -96,6 +96,7 @@
        <listitem><para>debug_object_deactivate</para></listitem>
        <listitem><para>debug_object_destroy</para></listitem>
        <listitem><para>debug_object_free</para></listitem>
+        <listitem><para>debug_object_assert_init</para></listitem>
      </itemizedlist>
      Each of these functions takes the address of the real object and
      a pointer to the object type specific debug description
@@ -273,6 +274,26 @@
        debug checks.
      </para>
    </sect1>
+    <sect1 id="debug_object_assert_init">
+      <title>debug_object_assert_init</title>
+      <para>
+        This function is called to assert that an object has been
+        initialized.
+      </para>
+      <para>
+        When the real object is not tracked by debugobjects, it calls
+        fixup_assert_init of the object type description structure
+        provided by the caller, with the hardcoded object state
+        ODEBUG_NOT_AVAILABLE. The fixup function can correct the problem
+        by calling debug_object_init and other specific initializing
+        functions.
+      </para>
+      <para>
+        When the real object is already tracked by debugobjects it is
+        ignored.
+      </para>
+    </sect1>
  </chapter>
  <chapter id="fixupfunctions">
    <title>Fixup functions</title>
@@ -381,6 +402,35 @@
        statistics.
      </para>
    </sect1>
+    <sect1 id="fixup_assert_init">
+      <title>fixup_assert_init</title>
+      <para>
+        This function is called from the debug code whenever a problem
+        in debug_object_assert_init is detected.
+      </para>
+      <para>
+        Called from debug_object_assert_init() with a hardcoded state
+        ODEBUG_STATE_NOTAVAILABLE when the object is not found in the
+        debug bucket.
+      </para>
+      <para>
+        The function returns 1 when the fixup was successful,
+        otherwise 0. The return value is used to update the
+        statistics.
+      </para>
+      <para>
+        Note, this function should make sure debug_object_init() is
+        called before returning.
+      </para>
+      <para>
+        The handling of statically initialized objects is a special
+        case. The fixup function should check if this is a legitimate
+        case of a statically initialized object or not. In this case only
+        debug_object_init() should be called to make the object known to
+        the tracker. Then the function should return 0 because this is not
+        a real fixup.
+      </para>
+    </sect1>
  </chapter>
  <chapter id="bugs">
    <title>Known Bugs And Assumptions</title>
diff --git a/Documentation/DocBook/media/v4l/pixfmt-nv24.xml b/Documentation/DocBook/media/v4l/pixfmt-nv24.xml
new file mode 100644
index 00000000000..fb255f2ca9d
--- /dev/null
+++ b/Documentation/DocBook/media/v4l/pixfmt-nv24.xml
@@ -0,0 +1,121 @@
+    <refentry>
+      <refmeta>
+        <refentrytitle>V4L2_PIX_FMT_NV24 ('NV24'), V4L2_PIX_FMT_NV42 ('NV42')</refentrytitle>
+        &manvol;
+      </refmeta>
+      <refnamediv>
+        <refname id="V4L2-PIX-FMT-NV24"><constant>V4L2_PIX_FMT_NV24</constant></refname>
+        <refname id="V4L2-PIX-FMT-NV42"><constant>V4L2_PIX_FMT_NV42</constant></refname>
+        <refpurpose>Formats with full horizontal and vertical
+chroma resolutions, also known as YUV 4:4:4. One luminance and one
+chrominance plane with alternating chroma samples as opposed to
+<constant>V4L2_PIX_FMT_YVU420</constant></refpurpose>
+      </refnamediv>
+      <refsect1>
+        <title>Description</title>
+        <para>These are two-plane versions of the YUV 4:4:4 format. The three
+        components are separated into two sub-images or planes. The Y plane is
+        first, with each Y sample stored in one byte per pixel. For
+        <constant>V4L2_PIX_FMT_NV24</constant>, a combined CbCr plane
+        immediately follows the Y plane in memory. The CbCr plane has the same
+        width and height, in pixels, as the Y plane (and the image). Each line
+        contains one CbCr pair per pixel, with each Cb and Cr sample stored in
+        one byte. <constant>V4L2_PIX_FMT_NV42</constant> is the same except that
+        the Cb and Cr samples are swapped, the CrCb plane starts with a Cr
+        sample.</para>
+        <para>If the Y plane has pad bytes after each row, then the CbCr plane
+        has twice as many pad bytes after its rows.</para>
+        <example>
+          <title><constant>V4L2_PIX_FMT_NV24</constant> 4 &times; 4
+pixel image</title>
+          <formalpara>
+            <title>Byte Order.</title>
+            <para>Each cell is one byte.
+                <informaltable frame="none">
+                <tgroup cols="9" align="center">
+                  <colspec align="left" colwidth="2*" />
+                  <tbody valign="top">
+                    <row>
+                      <entry>start&nbsp;+&nbsp;0:</entry>
+                      <entry>Y'<subscript>00</subscript></entry>
+                      <entry>Y'<subscript>01</subscript></entry>
+                      <entry>Y'<subscript>02</subscript></entry>
+                      <entry>Y'<subscript>03</subscript></entry>
+                    </row>
+                    <row>
+                      <entry>start&nbsp;+&nbsp;4:</entry>
+                      <entry>Y'<subscript>10</subscript></entry>
+                      <entry>Y'<subscript>11</subscript></entry>
+                      <entry>Y'<subscript>12</subscript></entry>
+                      <entry>Y'<subscript>13</subscript></entry>
+                    </row>
+                    <row>
+                      <entry>start&nbsp;+&nbsp;8:</entry>
+                      <entry>Y'<subscript>20</subscript></entry>
+                      <entry>Y'<subscript>21</subscript></entry>
+                      <entry>Y'<subscript>22</subscript></entry>
+                      <entry>Y'<subscript>23</subscript></entry>
+                    </row>
+                    <row>
+                      <entry>start&nbsp;+&nbsp;12:</entry>
+                      <entry>Y'<subscript>30</subscript></entry>
+                      <entry>Y'<subscript>31</subscript></entry>
+                      <entry>Y'<subscript>32</subscript></entry>
+                      <entry>Y'<subscript>33</subscript></entry>
+                    </row>
+                    <row>
+                      <entry>start&nbsp;+&nbsp;16:</entry>
+                      <entry>Cb<subscript>00</subscript></entry>
+                      <entry>Cr<subscript>00</subscript></entry>
+                      <entry>Cb<subscript>01</subscript></entry>
+                      <entry>Cr<subscript>01</subscript></entry>
+                      <entry>Cb<subscript>02</subscript></entry>
+                      <entry>Cr<subscript>02</subscript></entry>
+                      <entry>Cb<subscript>03</subscript></entry>
+                      <entry>Cr<subscript>03</subscript></entry>
+                    </row>
+                    <row>
+                      <entry>start&nbsp;+&nbsp;24:</entry>
+                      <entry>Cb<subscript>10</subscript></entry>
+                      <entry>Cr<subscript>10</subscript></entry>
+                      <entry>Cb<subscript>11</subscript></entry>
+                      <entry>Cr<subscript>11</subscript></entry>
+                      <entry>Cb<subscript>12</subscript></entry>
+                      <entry>Cr<subscript>12</subscript></entry>
+                      <entry>Cb<subscript>13</subscript></entry>
+                      <entry>Cr<subscript>13</subscript></entry>
+                    </row>
+                    <row>
+                      <entry>start&nbsp;+&nbsp;32:</entry>
+                      <entry>Cb<subscript>20</subscript></entry>
+                      <entry>Cr<subscript>20</subscript></entry>
+                      <entry>Cb<subscript>21</subscript></entry>
+                      <entry>Cr<subscript>21</subscript></entry>
+                      <entry>Cb<subscript>22</subscript></entry>
+                      <entry>Cr<subscript>22</subscript></entry>
+                      <entry>Cb<subscript>23</subscript></entry>
+                      <entry>Cr<subscript>23</subscript></entry>
+                    </row>
+                    <row>
+                      <entry>start&nbsp;+&nbsp;40:</entry>
+                      <entry>Cb<subscript>30</subscript></entry>
+                      <entry>Cr<subscript>30</subscript></entry>
+                      <entry>Cb<subscript>31</subscript></entry>
+                      <entry>Cr<subscript>31</subscript></entry>
+                      <entry>Cb<subscript>32</subscript></entry>
+                      <entry>Cr<subscript>32</subscript></entry>
+                      <entry>Cb<subscript>33</subscript></entry>
+                      <entry>Cr<subscript>33</subscript></entry>
+                    </row>
+                  </tbody>
+                </tgroup>
+                </informaltable>
+              </para>
+          </formalpara>
+        </example>
+      </refsect1>
+    </refentry>
diff --git a/Documentation/DocBook/media/v4l/pixfmt.xml b/Documentation/DocBook/media/v4l/pixfmt.xml
index 9ddc57cb2ef..31eaae2469f 100644
--- a/Documentation/DocBook/media/v4l/pixfmt.xml
+++ b/Documentation/DocBook/media/v4l/pixfmt.xml
@@ -714,6 +714,7 @@ information.</para>
    &sub-nv12m;
    &sub-nv12mt;
    &sub-nv16;
+    &sub-nv24;
    &sub-m420;
  </section>
diff --git a/Documentation/DocBook/writing-an-alsa-driver.tmpl b/Documentation/DocBook/writing-an-alsa-driver.tmpl
index 5de23c00707..cab4ec58e46 100644
--- a/Documentation/DocBook/writing-an-alsa-driver.tmpl
+++ b/Documentation/DocBook/writing-an-alsa-driver.tmpl
@@ -404,7 +404,7 @@
  /* SNDRV_CARDS: maximum number of cards supported by this module */
  static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
-  static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
+  static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  /* definition of the chip-specific record */
  struct mychip {
diff --git a/Documentation/HOWTO b/Documentation/HOWTO
index 81bc1a9ab9d..f7ade3b3b40 100644
--- a/Documentation/HOWTO
+++ b/Documentation/HOWTO
@@ -275,8 +275,8 @@ versions.
 If no 2.6.x.y kernel is available, then the highest numbered 2.6.x
 kernel is the current stable kernel.
-2.6.x.y are maintained by the "stable" team <stable@kernel.org>, and are
+2.6.x.y are maintained by the "stable" team <stable@vger.kernel.org>, and
-released as needs dictate.  The normal release period is approximately 
+are released as needs dictate.  The normal release period is approximately
 two weeks, but it can be longer if there are no pressing problems.  A
 security-related problem, instead, can cause a release to happen almost
 instantly.
diff --git a/Documentation/RCU/checklist.txt b/Documentation/RCU/checklist.txt
index 0c134f8afc6..bff2d8be1e1 100644
--- a/Documentation/RCU/checklist.txt
+++ b/Documentation/RCU/checklist.txt
@@ -328,6 +328,12 @@ over a rather long period of time, but improvements are always welcome!
        RCU rather than SRCU, because RCU is almost always faster and
        easier to use than is SRCU.
+        If you need to enter your read-side critical section in a
+        hardirq or exception handler, and then exit that same read-side
+        critical section in the task that was interrupted, then you need
+        to srcu_read_lock_raw() and srcu_read_unlock_raw(), which avoid
+        the lockdep checking that would otherwise this practice illegal.
        Also unlike other forms of RCU, explicit initialization
        and cleanup is required via init_srcu_struct() and
        cleanup_srcu_struct().  These are passed a "struct srcu_struct"
diff --git a/Documentation/RCU/rcu.txt b/Documentation/RCU/rcu.txt
index 31852705b58..bf778332a28 100644
--- a/Documentation/RCU/rcu.txt
+++ b/Documentation/RCU/rcu.txt
@@ -38,11 +38,11 @@ o	How can the updater tell when a grace period has completed
        Preemptible variants of RCU (CONFIG_TREE_PREEMPT_RCU) get the
        same effect, but require that the readers manipulate CPU-local
-        counters.  These counters allow limited types of blocking
+        counters.  These counters allow limited types of blocking within
-        within RCU read-side critical sections.  SRCU also uses
+        RCU read-side critical sections.  SRCU also uses CPU-local
-        CPU-local counters, and permits general blocking within
+        counters, and permits general blocking within RCU read-side
-        RCU read-side critical sections.  These two variants of
+        critical sections.  These variants of RCU detect grace periods
-        RCU detect grace periods by sampling these counters.
+        by sampling these counters.
 o       If I am running on a uniprocessor kernel, which can only do one
        thing at a time, why should I wait for a grace period?
diff --git a/Documentation/RCU/stallwarn.txt b/Documentation/RCU/stallwarn.txt
index 4e959208f73..083d88cbc08 100644
--- a/Documentation/RCU/stallwarn.txt
+++ b/Documentation/RCU/stallwarn.txt
@@ -101,6 +101,11 @@ o	A CPU-bound real-time task in a CONFIG_PREEMPT_RT kernel that
        CONFIG_TREE_PREEMPT_RCU case, you might see stall-warning
        messages.
+o       A hardware or software issue shuts off the scheduler-clock
+        interrupt on a CPU that is not in dyntick-idle mode.  This
+        problem really has happened, and seems to be most likely to
+        result in RCU CPU stall warnings for CONFIG_NO_HZ=n kernels.
 o       A bug in the RCU implementation.
 o       A hardware failure.  This is quite unlikely, but has occurred
@@ -109,12 +114,11 @@ o	A hardware failure.  This is quite unlikely, but has occurred
        This resulted in a series of RCU CPU stall warnings, eventually
        leading the realization that the CPU had failed.
-The RCU, RCU-sched, and RCU-bh implementations have CPU stall
+The RCU, RCU-sched, and RCU-bh implementations have CPU stall warning.
-warning.  SRCU does not have its own CPU stall warnings, but its
+SRCU does not have its own CPU stall warnings, but its calls to
-calls to synchronize_sched() will result in RCU-sched detecting
+synchronize_sched() will result in RCU-sched detecting RCU-sched-related
-RCU-sched-related CPU stalls.  Please note that RCU only detects
+CPU stalls.  Please note that RCU only detects CPU stalls when there is
-CPU stalls when there is a grace period in progress.  No grace period,
+a grace period in progress.  No grace period, no CPU stall warnings.
-no CPU stall warnings.
 To diagnose the cause of the stall, inspect the stack traces.
 The offending function will usually be near the top of the stack.
diff --git a/Documentation/RCU/torture.txt b/Documentation/RCU/torture.txt
index 783d6c134d3..d67068d0d2b 100644
--- a/Documentation/RCU/torture.txt
+++ b/Documentation/RCU/torture.txt
@@ -61,11 +61,24 @@ nreaders	This is the number of RCU reading threads supported.
                To properly exercise RCU implementations with preemptible
                read-side critical sections.
+onoff_interval
+                The number of seconds between each attempt to execute a
+                randomly selected CPU-hotplug operation.  Defaults to
+                zero, which disables CPU hotplugging.  In HOTPLUG_CPU=n
+                kernels, rcutorture will silently refuse to do any
+                CPU-hotplug operations regardless of what value is
+                specified for onoff_interval.
 shuffle_interval
                The number of seconds to keep the test threads affinitied
                to a particular subset of the CPUs, defaults to 3 seconds.
                Used in conjunction with test_no_idle_hz.
+shutdown_secs   The number of seconds to run the test before terminating
+                the test and powering off the system.  The default is
+                zero, which disables test termination and system shutdown.
+                This capability is useful for automated testing.
 stat_interval   The number of seconds between output of torture
                statistics (via printk()).  Regardless of the interval,
                statistics are printed when the module is unloaded.
diff --git a/Documentation/RCU/trace.txt b/Documentation/RCU/trace.txt
index aaf65f6c6cd..49587abfc2f 100644
--- a/Documentation/RCU/trace.txt
+++ b/Documentation/RCU/trace.txt
@@ -105,14 +105,10 @@ o	"dt" is the current value of the dyntick counter that is incremented
        or one greater than the interrupt-nesting depth otherwise.
        The number after the second "/" is the NMI nesting depth.
-        This field is displayed only for CONFIG_NO_HZ kernels.
 o       "df" is the number of times that some other CPU has forced a
        quiescent state on behalf of this CPU due to this CPU being in
        dynticks-idle state.
-        This field is displayed only for CONFIG_NO_HZ kernels.
 o       "of" is the number of times that some other CPU has forced a
        quiescent state on behalf of this CPU due to this CPU being
        offline.  In a perfect world, this might never happen, but it
diff --git a/Documentation/RCU/whatisRCU.txt b/Documentation/RCU/whatisRCU.txt
index 6ef692667e2..6bbe8dcdc3d 100644
--- a/Documentation/RCU/whatisRCU.txt
+++ b/Documentation/RCU/whatisRCU.txt
@@ -4,6 +4,7 @@ to start learning about RCU:
 1.      What is RCU, Fundamentally?  http://lwn.net/Articles/262464/
 2.      What is RCU? Part 2: Usage   http://lwn.net/Articles/263130/
 3.      RCU part 3: the RCU API      http://lwn.net/Articles/264090/
+4.      The RCU API, 2010 Edition    http://lwn.net/Articles/418853/
 What is RCU?
@@ -834,6 +835,8 @@ SRCU:	Critical sections	Grace period		Barrier
        srcu_read_lock          synchronize_srcu        N/A
        srcu_read_unlock        synchronize_srcu_expedited
+        srcu_read_lock_raw
+        srcu_read_unlock_raw
        srcu_dereference
 SRCU:   Initialization/cleanup
@@ -855,27 +858,33 @@ list can be helpful:
 a.      Will readers need to block?  If so, you need SRCU.
-b.      What about the -rt patchset?  If readers would need to block
+b.      Is it necessary to start a read-side critical section in a
+        hardirq handler or exception handler, and then to complete
+        this read-side critical section in the task that was
+        interrupted?  If so, you need SRCU's srcu_read_lock_raw() and
+        srcu_read_unlock_raw() primitives.
+c.      What about the -rt patchset?  If readers would need to block
        in an non-rt kernel, you need SRCU.  If readers would block
        in a -rt kernel, but not in a non-rt kernel, SRCU is not
        necessary.
-c.      Do you need to treat NMI handlers, hardirq handlers,
+d.      Do you need to treat NMI handlers, hardirq handlers,
        and code segments with preemption disabled (whether
        via preempt_disable(), local_irq_save(), local_bh_disable(),
        or some other mechanism) as if they were explicit RCU readers?
        If so, you need RCU-sched.
-d.      Do you need RCU grace periods to complete even in the face
+e.      Do you need RCU grace periods to complete even in the face
        of softirq monopolization of one or more of the CPUs?  For
        example, is your code subject to network-based denial-of-service
        attacks?  If so, you need RCU-bh.
-e.      Is your workload too update-intensive for normal use of
+f.      Is your workload too update-intensive for normal use of
        RCU, but inappropriate for other synchronization mechanisms?
        If so, consider SLAB_DESTROY_BY_RCU.  But please be careful!
-f.      Otherwise, use RCU.
+g.      Otherwise, use RCU.
 Of course, this all assumes that you have determined that RCU is in fact
 the right tool for your job.
diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt
index 771d48d3b33..208a2d465b9 100644
--- a/Documentation/arm/memory.txt
+++ b/Documentation/arm/memory.txt
@@ -51,15 +51,14 @@ ffc00000	ffefffff	DMA memory mapping region.  Memory returned
 ff000000        ffbfffff        Reserved for future expansion of DMA
                                mapping region.
-VMALLOC_END     feffffff        Free for platform use, recommended.
-                                VMALLOC_END must be aligned to a 2MB
-                                boundary.
 VMALLOC_START   VMALLOC_END-1   vmalloc() / ioremap() space.
                                Memory returned by vmalloc/ioremap will
                                be dynamically placed in this region.
-                                VMALLOC_START may be based upon the value
+                                Machine specific static mappings are also
-                                of the high_memory variable.
+                                located here through iotable_init().
+                                VMALLOC_START is based upon the value
+                                of the high_memory variable, and VMALLOC_END
+                                is equal to 0xff000000.
 PAGE_OFFSET     high_memory-1   Kernel direct-mapped RAM region.
                                This maps the platforms RAM, and typically
diff --git a/Documentation/atomic_ops.txt b/Documentation/atomic_ops.txt
index 3bd585b4492..27f2b21a9d5 100644
--- a/Documentation/atomic_ops.txt
+++ b/Documentation/atomic_ops.txt
@@ -84,6 +84,93 @@ compiler optimizes the section accessing atomic_t variables.
 *** YOU HAVE BEEN WARNED! ***
+Properly aligned pointers, longs, ints, and chars (and unsigned
+equivalents) may be atomically loaded from and stored to in the same
+sense as described for atomic_read() and atomic_set().  The ACCESS_ONCE()
+macro should be used to prevent the compiler from using optimizations
+that might otherwise optimize accesses out of existence on the one hand,
+or that might create unsolicited accesses on the other.
+For example consider the following code:
+        while (a > 0)
+                do_something();
+If the compiler can prove that do_something() does not store to the
+variable a, then the compiler is within its rights transforming this to
+the following:
+        tmp = a;
+        if (a > 0)
+                for (;;)
+                        do_something();
+If you don't want the compiler to do this (and you probably don't), then
+you should use something like the following:
+        while (ACCESS_ONCE(a) < 0)
+                do_something();
+Alternatively, you could place a barrier() call in the loop.
+For another example, consider the following code:
+        tmp_a = a;
+        do_something_with(tmp_a);
+        do_something_else_with(tmp_a);
+If the compiler can prove that do_something_with() does not store to the
+variable a, then the compiler is within its rights to manufacture an
+additional load as follows:
+        tmp_a = a;
+        do_something_with(tmp_a);
+        tmp_a = a;
+        do_something_else_with(tmp_a);
+This could fatally confuse your code if it expected the same value
+to be passed to do_something_with() and do_something_else_with().
+The compiler would be likely to manufacture this additional load if
+do_something_with() was an inline function that made very heavy use
+of registers: reloading from variable a could save a flush to the
+stack and later reload.  To prevent the compiler from attacking your
+code in this manner, write the following:
+        tmp_a = ACCESS_ONCE(a);
+        do_something_with(tmp_a);
+        do_something_else_with(tmp_a);
+For a final example, consider the following code, assuming that the
+variable a is set at boot time before the second CPU is brought online
+and never changed later, so that memory barriers are not needed:
+        if (a)
+                b = 9;
+        else
+                b = 42;
+The compiler is within its rights to manufacture an additional store
+by transforming the above code into the following:
+        b = 42;
+        if (a)
+                b = 9;
+This could come as a fatal surprise to other code running concurrently
+that expected b to never have the value 42 if a was zero.  To prevent
+the compiler from doing this, write something like:
+        if (a)
+                ACCESS_ONCE(b) = 9;
+        else
+                ACCESS_ONCE(b) = 42;
+Don't even -think- about doing this without proper use of memory barriers,
+locks, or atomic operations if variable a can change at runtime!
+*** WARNING: ACCESS_ONCE() DOES NOT IMPLY A BARRIER! ***
 Now, we move onto the atomic operation interfaces typically implemented with
 the help of assembly code.
diff --git a/Documentation/cgroups/cgroups.txt b/Documentation/cgroups/cgroups.txt
index 9c452ef2328..a7c96ae5557 100644
--- a/Documentation/cgroups/cgroups.txt
+++ b/Documentation/cgroups/cgroups.txt
@@ -594,53 +594,44 @@ rmdir() will fail with it. From this behavior, pre_destroy() can be
 called multiple times against a cgroup.
 int can_attach(struct cgroup_subsys *ss, struct cgroup *cgrp,
-               struct task_struct *task)
+               struct cgroup_taskset *tset)
 (cgroup_mutex held by caller)
-Called prior to moving a task into a cgroup; if the subsystem
+Called prior to moving one or more tasks into a cgroup; if the
-returns an error, this will abort the attach operation.  If a NULL
+subsystem returns an error, this will abort the attach operation.
-task is passed, then a successful result indicates that *any*
+@tset contains the tasks to be attached and is guaranteed to have at
-unspecified task can be moved into the cgroup. Note that this isn't
+least one task in it.
-called on a fork. If this method returns 0 (success) then this should
-remain valid while the caller holds cgroup_mutex and it is ensured that either
+If there are multiple tasks in the taskset, then:
+  - it's guaranteed that all are from the same thread group
+  - @tset contains all tasks from the thread group whether or not
+    they're switching cgroups
+  - the first task is the leader
+Each @tset entry also contains the task's old cgroup and tasks which
+aren't switching cgroup can be skipped easily using the
+cgroup_taskset_for_each() iterator. Note that this isn't called on a
+fork. If this method returns 0 (success) then this should remain valid
+while the caller holds cgroup_mutex and it is ensured that either
 attach() or cancel_attach() will be called in future.
-int can_attach_task(struct cgroup *cgrp, struct task_struct *tsk);
-(cgroup_mutex held by caller)
-As can_attach, but for operations that must be run once per task to be
-attached (possibly many when using cgroup_attach_proc). Called after
-can_attach.
 void cancel_attach(struct cgroup_subsys *ss, struct cgroup *cgrp,
-               struct task_struct *task, bool threadgroup)
+                   struct cgroup_taskset *tset)
 (cgroup_mutex held by caller)
 Called when a task attach operation has failed after can_attach() has succeeded.
 A subsystem whose can_attach() has some side-effects should provide this
 function, so that the subsystem can implement a rollback. If not, not necessary.
 This will be called only about subsystems whose can_attach() operation have
-succeeded.
+succeeded. The parameters are identical to can_attach().
-void pre_attach(struct cgroup *cgrp);
-(cgroup_mutex held by caller)
-For any non-per-thread attachment work that needs to happen before
-attach_task. Needed by cpuset.
 void attach(struct cgroup_subsys *ss, struct cgroup *cgrp,
-            struct cgroup *old_cgrp, struct task_struct *task)
+            struct cgroup_taskset *tset)
 (cgroup_mutex held by caller)
 Called after the task has been attached to the cgroup, to allow any
 post-attachment activity that requires memory allocations or blocking.
+The parameters are identical to can_attach().
-void attach_task(struct cgroup *cgrp, struct task_struct *tsk);
-(cgroup_mutex held by caller)
-As attach, but for operations that must be run once per task to be attached,
-like can_attach_task. Called before attach. Currently does not support any
-subsystem that might need the old_cgrp for every thread in the group.
 void fork(struct cgroup_subsy *ss, struct task_struct *task)
diff --git a/Documentation/cgroups/memory.txt b/Documentation/cgroups/memory.txt
index cc0ebc5241b..4c95c0034a4 100644
--- a/Documentation/cgroups/memory.txt
+++ b/Documentation/cgroups/memory.txt
@@ -44,8 +44,8 @@ Features:
 - oom-killer disable knob and oom-notifier
 - Root cgroup has no limit controls.
- Kernel memory and Hugepages are not under control yet. We just manage
+ Kernel memory support is work in progress, and the current version provides
- pages on LRU. To add more controls, we have to take care of performance.
+ basically functionality. (See Section 2.7)
 Brief summary of control files.
@@ -61,7 +61,7 @@ Brief summary of control files.
 memory.failcnt                  # show the number of memory usage hits limits
 memory.memsw.failcnt            # show the number of memory+Swap hits limits
 memory.max_usage_in_bytes       # show max memory usage recorded
- memory.memsw.usage_in_bytes     # show max memory+Swap usage recorded
+ memory.memsw.max_usage_in_bytes # show max memory+Swap usage recorded
 memory.soft_limit_in_bytes      # set/show soft limit of memory usage
 memory.stat                     # show various statistics
 memory.use_hierarchy            # set/show hierarchical account enabled
@@ -72,6 +72,9 @@ Brief summary of control files.
 memory.oom_control              # set/show oom controls.
 memory.numa_stat                # show the number of memory usage per numa node
+ memory.kmem.tcp.limit_in_bytes  # set/show hard limit for tcp buf memory
+ memory.kmem.tcp.usage_in_bytes  # show current tcp buf memory allocation
 1. History
 The memory controller has a long history. A request for comments for the memory
@@ -255,6 +258,27 @@ When oom event notifier is registered, event will be delivered.
  per-zone-per-cgroup LRU (cgroup's private LRU) is just guarded by
  zone->lru_lock, it has no lock of its own.
+2.7 Kernel Memory Extension (CONFIG_CGROUP_MEM_RES_CTLR_KMEM)
+With the Kernel memory extension, the Memory Controller is able to limit
+the amount of kernel memory used by the system. Kernel memory is fundamentally
+different than user memory, since it can't be swapped out, which makes it
+possible to DoS the system by consuming too much of this precious resource.
+Kernel memory limits are not imposed for the root cgroup. Usage for the root
+cgroup may or may not be accounted.
+Currently no soft limit is implemented for kernel memory. It is future work
+to trigger slab reclaim when those limits are reached.
+2.7.1 Current Kernel Memory resources accounted
+* sockets memory pressure: some sockets protocols have memory pressure
+thresholds. The Memory Controller allows them to be controlled individually
+per cgroup, instead of globally.
+* tcp memory pressure: sockets memory pressure for the tcp protocol.
 3. User Interface
 0. Configuration
@@ -386,8 +410,11 @@ memory.stat file includes following statistics
 cache           - # of bytes of page cache memory.
 rss             - # of bytes of anonymous and swap cache memory.
 mapped_file     - # of bytes of mapped file (includes tmpfs/shmem)
-pgpgin          - # of pages paged in (equivalent to # of charging events).
+pgpgin          - # of charging events to the memory cgroup. The charging
-pgpgout         - # of pages paged out (equivalent to # of uncharging events).
+                event happens each time a page is accounted as either mapped
+                anon page(RSS) or cache page(Page Cache) to the cgroup.
+pgpgout         - # of uncharging events to the memory cgroup. The uncharging
+                event happens each time a page is unaccounted from the cgroup.
 swap            - # of bytes of swap usage
 inactive_anon   - # of bytes of anonymous memory and swap cache memory on
                LRU list.
diff --git a/Documentation/cgroups/net_prio.txt b/Documentation/cgroups/net_prio.txt
new file mode 100644
index 00000000000..01b32263559
--- /dev/null
+++ b/Documentation/cgroups/net_prio.txt
@@ -0,0 +1,53 @@
+Network priority cgroup
+-------------------------
+The Network priority cgroup provides an interface to allow an administrator to
+dynamically set the priority of network traffic generated by various
+applications
+Nominally, an application would set the priority of its traffic via the
+SO_PRIORITY socket option.  This however, is not always possible because:
+1) The application may not have been coded to set this value
+2) The priority of application traffic is often a site-specific administrative
+   decision rather than an application defined one.
+This cgroup allows an administrator to assign a process to a group which defines
+the priority of egress traffic on a given interface. Network priority groups can
+be created by first mounting the cgroup filesystem.
+# mount -t cgroup -onet_prio none /sys/fs/cgroup/net_prio
+With the above step, the initial group acting as the parent accounting group
+becomes visible at '/sys/fs/cgroup/net_prio'.  This group includes all tasks in
+the system. '/sys/fs/cgroup/net_prio/tasks' lists the tasks in this cgroup.
+Each net_prio cgroup contains two files that are subsystem specific
+net_prio.prioidx
+This file is read-only, and is simply informative.  It contains a unique integer
+value that the kernel uses as an internal representation of this cgroup.
+net_prio.ifpriomap
+This file contains a map of the priorities assigned to traffic originating from
+processes in this group and egressing the system on various interfaces. It
+contains a list of tuples in the form <ifname priority>.  Contents of this file
+can be modified by echoing a string into the file using the same tuple format.
+for example:
+echo "eth0 5" > /sys/fs/cgroups/net_prio/iscsi/net_prio.ifpriomap
+This command would force any traffic originating from processes belonging to the
+iscsi net_prio cgroup and egressing on interface eth0 to have the priority of
+said traffic set to the value 5. The parent accounting group also has a
+writeable 'net_prio.ifpriomap' file that can be used to set a system default
+priority.
+Priorities are set immediately prior to queueing a frame to the device
+queueing discipline (qdisc) so priorities will be assigned prior to the hardware
+queue selection being made.
+One usage for the net_prio cgroup is with mqprio qdisc allowing application
+traffic to be steered to hardware/driver based traffic classes. These mappings
+can then be managed by administrators or other networking protocols such as
+DCBX.
diff --git a/Documentation/coccinelle.txt b/Documentation/coccinelle.txt
index 96b690348ba..cf44eb6499b 100644
--- a/Documentation/coccinelle.txt
+++ b/Documentation/coccinelle.txt
@@ -102,9 +102,15 @@ or
        make coccicheck COCCI=<my_SP.cocci> MODE=report
- Using Coccinelle on (modified) files
+ Controlling Which Files are Processed by Coccinelle
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+By default the entire kernel source tree is checked.
+To apply Coccinelle to a specific directory, M= can be used.
+For example, to check drivers/net/wireless/ one may write:
+    make coccicheck M=drivers/net/wireless/
+    
 To apply Coccinelle on a file basis, instead of a directory basis, the
 following command may be used:
diff --git a/Documentation/cpu-freq/governors.txt b/Documentation/cpu-freq/governors.txt
index d221781daba..c7a2eb8450c 100644
--- a/Documentation/cpu-freq/governors.txt
+++ b/Documentation/cpu-freq/governors.txt
@@ -127,7 +127,7 @@ in the bash (as said, 1000 is default), do:
 echo `$(($(cat cpuinfo_transition_latency) * 750 / 1000)) \
    >ondemand/sampling_rate
-show_sampling_rate_min:
+sampling_rate_min:
 The sampling rate is limited by the HW transition latency:
 transition_latency * 100
 Or by kernel restrictions:
@@ -140,8 +140,6 @@ HZ=100:  min=200000us (200ms)
 The highest value of kernel and HW latency restrictions is shown and
 used as the minimum sampling rate.
-show_sampling_rate_max: THIS INTERFACE IS DEPRECATED, DON'T USE IT.
 up_threshold: defines what the average CPU usage between the samplings
 of 'sampling_rate' needs to be for the kernel to make a decision on
 whether it should increase the frequency.  For example when it is set
diff --git a/Documentation/development-process/5.Posting b/Documentation/development-process/5.Posting
index 903a2546f13..8a48c9b6286 100644
--- a/Documentation/development-process/5.Posting
+++ b/Documentation/development-process/5.Posting
@@ -271,10 +271,10 @@ copies should go to:
   the linux-kernel list.
 - If you are fixing a bug, think about whether the fix should go into the
-   next stable update.  If so, stable@kernel.org should get a copy of the
+   next stable update.  If so, stable@vger.kernel.org should get a copy of
-   patch.  Also add a "Cc: stable@kernel.org" to the tags within the patch
+   the patch.  Also add a "Cc: stable@vger.kernel.org" to the tags within
-   itself; that will cause the stable team to get a notification when your
+   the patch itself; that will cause the stable team to get a notification
-   fix goes into the mainline.
+   when your fix goes into the mainline.
 When selecting recipients for a patch, it is good to have an idea of who
 you think will eventually accept the patch and get it merged.  While it
diff --git a/Documentation/devices.txt b/Documentation/devices.txt
index eccffe71522..00383186d8f 100644
--- a/Documentation/devices.txt
+++ b/Documentation/devices.txt
@@ -379,7 +379,7 @@ Your cooperation is appreciated.
                162 = /dev/smbus        System Management Bus
                163 = /dev/lik          Logitech Internet Keyboard
                164 = /dev/ipmo         Intel Intelligent Platform Management
-                165 = /dev/vmmon        VMWare virtual machine monitor
+                165 = /dev/vmmon        VMware virtual machine monitor
                166 = /dev/i2o/ctl      I2O configuration manager
                167 = /dev/specialix_sxctl Specialix serial control
                168 = /dev/tcldrv       Technology Concepts serial control
@@ -447,6 +447,9 @@ Your cooperation is appreciated.
                234 = /dev/btrfs-control        Btrfs control device
                235 = /dev/autofs       Autofs control device
                236 = /dev/mapper/control       Device-Mapper control device
+                237 = /dev/loop-control Loopback control device
+                238 = /dev/vhost-net    Host kernel accelerator for virtio net
                240-254                 Reserved for local use
                255                     Reserved for MISC_DYNAMIC_MINOR
diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index c9848ad0e2e..54bdddadf1c 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -21,6 +21,10 @@ i.MX53 Smart Mobile Reference Design Board
 Required root node properties:
    - compatible = "fsl,imx53-smd", "fsl,imx53";
-i.MX6 Quad SABRE Automotive Board
+i.MX6 Quad Armadillo2 Board
 Required root node properties:
-    - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
+    - compatible = "fsl,imx6q-arm2", "fsl,imx6q";
+i.MX6 Quad SABRE Lite Board
+Required root node properties:
+    - compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index 52916b4aa1f..9b4b82a721b 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -42,6 +42,10 @@ Optional
 - interrupts    : Interrupt source of the parent interrupt controller. Only
  present on secondary GICs.
+- cpu-offset    : per-cpu offset within the distributor and cpu interface
+  regions, used when the GIC doesn't have banked registers. The offset is
+  cpu-offset * cpu-nr.
 Example:
        intc: interrupt-controller@fff11000 {
diff --git a/Documentation/devicetree/bindings/arm/insignal-boards.txt b/Documentation/devicetree/bindings/arm/insignal-boards.txt
new file mode 100644
index 00000000000..524c3dc5d80
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/insignal-boards.txt
@@ -0,0 +1,8 @@
+* Insignal's Exynos4210 based Origen evaluation board
+Origen low-cost evaluation board is based on Samsung's Exynos4210 SoC.
+Required root node properties:
+    - compatible = should be one or more of the following.
+        (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
+        (b) "samsung,exynos4210"  - for boards based on Exynos4210 SoC.
diff --git a/Documentation/devicetree/bindings/arm/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung-boards.txt
new file mode 100644
index 00000000000..0bf68be56fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/samsung-boards.txt
@@ -0,0 +1,8 @@
+* Samsung's Exynos4210 based SMDKV310 evaluation board
+SMDKV310 evaluation board is based on Samsung's Exynos4210 SoC.
+Required root node properties:
+    - compatible = should be one or more of the following.
+        (a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
+        (b) "samsung,exynos4210"  - for boards based on Exynos4210 SoC.
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
new file mode 100644
index 00000000000..6e69d2e5e76
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -0,0 +1,14 @@
+NVIDIA Tegra device tree bindings
+-------------------------------------------
+Boards with the tegra20 SoC shall have the following properties:
+Required root node property:
+compatible = "nvidia,tegra20";
+Boards with the tegra30 SoC shall have the following properties:
+Required root node property:
+compatible = "nvidia,tegra30";
diff --git a/Documentation/devicetree/bindings/arm/vic.txt b/Documentation/devicetree/bindings/arm/vic.txt
new file mode 100644
index 00000000000..266716b2343
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vic.txt
@@ -0,0 +1,29 @@
+* ARM Vectored Interrupt Controller
+One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
+system for interrupt routing.  For multiple controllers they can either be
+nested or have the outputs wire-OR'd together.
+Required properties:
+- compatible : should be one of
+        "arm,pl190-vic"
+        "arm,pl192-vic"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : The number of cells to define the interrupts.  Must be 1 as
+  the VIC has no configuration options for interrupt sources.  The cell is a u32
+  and defines the interrupt number.
+- reg : The register bank for the VIC.
+Optional properties:
+- interrupts : Interrupt source for parent controllers if the VIC is nested.
+Example:
+        vic0: interrupt-controller@60000 {
+                compatible = "arm,pl192-vic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x60000 0x1000>;
+        };
diff --git a/Documentation/devicetree/bindings/c6x/clocks.txt b/Documentation/devicetree/bindings/c6x/clocks.txt
new file mode 100644
index 00000000000..a04f5fd3012
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/clocks.txt
@@ -0,0 +1,40 @@
+C6X PLL Clock Controllers
+-------------------------
+This is a first-cut support for the SoC clock controllers. This is still
+under development and will probably change as the common device tree
+clock support is added to the kernel.
+Required properties:
+- compatible: "ti,c64x+pll"
+    May also have SoC-specific value to support SoC-specific initialization
+    in the driver. One of:
+        "ti,c6455-pll"
+        "ti,c6457-pll"
+        "ti,c6472-pll"
+        "ti,c6474-pll"
+- reg: base address and size of register area
+- clock-frequency: input clock frequency in hz
+Optional properties:
+- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
+- ti,c64x+pll-reset-delay:  CPU cycles to delay after PLL reset
+- ti,c64x+pll-lock-delay:   CPU cycles to delay after PLL frequency change
+Example:
+        clock-controller@29a0000 {
+                compatible = "ti,c6472-pll", "ti,c64x+pll";
+                reg = <0x029a0000 0x200>;
+                clock-frequency = <25000000>;
+                ti,c64x+pll-bypass-delay = <200>;
+                ti,c64x+pll-reset-delay = <12000>;
+                ti,c64x+pll-lock-delay = <80000>;
+        };
diff --git a/Documentation/devicetree/bindings/c6x/dscr.txt b/Documentation/devicetree/bindings/c6x/dscr.txt
new file mode 100644
index 00000000000..d847758f2b2
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/dscr.txt
@@ -0,0 +1,127 @@
+Device State Configuration Registers
+------------------------------------
+TI C6X SoCs contain a region of miscellaneous registers which provide various
+function for SoC control or status. Details vary considerably among from SoC
+to SoC with no two being alike.
+In general, the Device State Configuraion Registers (DSCR) will provide one or
+more configuration registers often protected by a lock register where one or
+more key values must be written to a lock register in order to unlock the
+configuration register for writes. These configuration register may be used to
+enable (and disable in some cases) SoC pin drivers, select peripheral clock
+sources (internal or pin), etc. In some cases, a configuration register is
+write once or the individual bits are write once. In addition to device config,
+the DSCR block may provide registers which which are used to reset peripherals,
+provide device ID information, provide ethernet MAC addresses, as well as other
+miscellaneous functions.
+For device state control (enable/disable), each device control is assigned an
+id which is used by individual device drivers to control the state as needed.
+Required properties:
+- compatible: must be "ti,c64x+dscr"
+- reg: register area base and size
+Optional properties:
+  NOTE: These are optional in that not all SoCs will have all properties. For
+        SoCs which do support a given property, leaving the property out of the
+        device tree will result in reduced functionality or possibly driver
+        failure.
+- ti,dscr-devstat
+    offset of the devstat register
+- ti,dscr-silicon-rev
+    offset, start bit, and bitsize of silicon revision field
+- ti,dscr-rmii-resets
+    offset and bitmask of RMII reset field. May have multiple tuples if more
+    than one ethernet port is available.
+- ti,dscr-locked-regs
+    possibly multiple tuples describing registers which are write protected by
+    a lock register. Each tuple consists of the register offset, lock register
+    offsset, and the key value used to unlock the register.
+- ti,dscr-kick-regs
+    offset and key values of two "kick" registers used to write protect other
+    registers in DSCR. On SoCs using kick registers, the first key must be
+    written to the first kick register and the second key must be written to
+    the second register before other registers in the area are write-enabled.
+- ti,dscr-mac-fuse-regs
+    MAC addresses are contained in two registers. Each element of a MAC address
+    is contained in a single byte. This property has two tuples. Each tuple has
+    a register offset and four cells representing bytes in the register from
+    most significant to least. The value of these four cells is the MAC byte
+    index (1-6) of the byte within the register. A value of 0 means the byte
+    is unused in the MAC address.
+- ti,dscr-devstate-ctl-regs
+    This property describes the bitfields used to control the state of devices.
+    Each tuple describes a range of identical bitfields used to control one or
+    more devices (one bitfield per device). The layout of each tuple is:
+        start_id num_ids reg enable disable start_bit nbits
+    Where:
+        start_id is device id for the first device control in the range
+        num_ids is the number of device controls in the range
+        reg is the offset of the register holding the control bits
+        enable is the value to enable a device
+        disable is the value to disable a device (0xffffffff if cannot disable)
+        start_bit is the bit number of the first bit in the range
+        nbits is the number of bits per device control
+- ti,dscr-devstate-stat-regs
+    This property describes the bitfields used to provide device state status
+    for device states controlled by the DSCR. Each tuple describes a range of
+    identical bitfields used to provide status for one or more devices (one
+    bitfield per device). The layout of each tuple is:
+        start_id num_ids reg enable disable start_bit nbits
+    Where:
+        start_id is device id for the first device status in the range
+        num_ids is the number of devices covered by the range
+        reg is the offset of the register holding the status bits
+        enable is the value indicating device is enabled
+        disable is the value indicating device is disabled
+        start_bit is the bit number of the first bit in the range
+        nbits is the number of bits per device status
+- ti,dscr-privperm
+    Offset and default value for register used to set access privilege for
+    some SoC devices.
+Example:
+        device-state-config-regs@2a80000 {
+                compatible = "ti,c64x+dscr";
+                reg = <0x02a80000 0x41000>;
+                ti,dscr-devstat = <0>;
+                ti,dscr-silicon-rev = <8 28 0xf>;
+                ti,dscr-rmii-resets = <0x40020 0x00040000>;
+                ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
+                ti,dscr-devstate-ctl-regs =
+                         <0 12 0x40008 1 0  0  2
+                          12 1 0x40008 3 0 30  2
+                          13 2 0x4002c 1 0xffffffff 0 1>;
+                ti,dscr-devstate-stat-regs =
+                        <0 10 0x40014 1 0  0  3
+                         10 2 0x40018 1 0  0  3>;
+                ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
+                                         0x704 5 6 0 0>;
+                ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
+                ti,dscr-kick-regs = <0x38 0x83E70B13
+                                     0x3c 0x95A4F1E0>;
+        };
diff --git a/Documentation/devicetree/bindings/c6x/emifa.txt b/Documentation/devicetree/bindings/c6x/emifa.txt
new file mode 100644
index 00000000000..0ff6e9b9a13
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/emifa.txt
@@ -0,0 +1,62 @@
+External Memory Interface
+-------------------------
+The emifa node describes a simple external bus controller found on some C6X
+SoCs. This interface provides external busses with a number of chip selects.
+Required properties:
+- compatible: must be "ti,c64x+emifa", "simple-bus"
+- reg: register area base and size
+- #address-cells: must be 2 (chip-select + offset)
+- #size-cells: must be 1
+- ranges: mapping from EMIFA space to parent space
+Optional properties:
+- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
+- ti,emifa-burst-priority:
+      Number of memory transfers after which the EMIF will elevate the priority
+      of the oldest command in the command FIFO. Setting this field to 255
+      disables this feature, thereby allowing old commands to stay in the FIFO
+      indefinitely.
+- ti,emifa-ce-config:
+      Configuration values for each of the supported chip selects.
+Example:
+        emifa@70000000 {
+                compatible = "ti,c64x+emifa", "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <1>;
+                reg = <0x70000000 0x100>;
+                ranges = <0x2 0x0 0xa0000000 0x00000008
+                          0x3 0x0 0xb0000000 0x00400000
+                          0x4 0x0 0xc0000000 0x10000000
+                          0x5 0x0 0xD0000000 0x10000000>;
+                ti,dscr-dev-enable = <13>;
+                ti,emifa-burst-priority = <255>;
+                ti,emifa-ce-config = <0x00240120
+                                      0x00240120
+                                      0x00240122
+                                      0x00240122>;
+                flash@3,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x3 0x0 0x400000>;
+                        bank-width = <1>;
+                        device-width = <1>;
+                        partition@0 {
+                                reg = <0x0 0x400000>;
+                                label = "NOR";
+                        };
+                };
+        };
+This shows a flash chip attached to chip select 3.
diff --git a/Documentation/devicetree/bindings/c6x/interrupt.txt b/Documentation/devicetree/bindings/c6x/interrupt.txt
new file mode 100644
index 00000000000..42bb796cc4a
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/interrupt.txt
@@ -0,0 +1,104 @@
+C6X Interrupt Chips
+-------------------
+* C64X+ Core Interrupt Controller
+  The core interrupt controller provides 16 prioritized interrupts to the
+  C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
+  Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
+  sources coming from outside the core.
+  Required properties:
+  --------------------
+  - compatible: Should be "ti,c64x+core-pic";
+  - #interrupt-cells: <1>
+  Interrupt Specifier Definition
+  ------------------------------
+  Single cell specifying the core interrupt priority level (4-15) where
+  4 is highest priority and 15 is lowest priority.
+  Example
+  -------
+  core_pic: interrupt-controller@0 {
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        compatible = "ti,c64x+core-pic";
+  };
+* C64x+ Megamodule Interrupt Controller
+  The megamodule PIC consists of four interrupt mupliplexers each of which
+  combine up to 32 interrupt inputs into a single interrupt output which
+  may be cascaded into the core interrupt controller. The megamodule PIC
+  has a total of 12 outputs cascading into the core interrupt controller.
+  One for each core interrupt priority level. In addition to the combined
+  interrupt sources, individual megamodule interrupts may be cascaded to
+  the core interrupt controller. When an individual interrupt is cascaded,
+  it is no longer handled through a megamodule interrupt combiner and is
+  considered to have the core interrupt controller as the parent.
+  Required properties:
+  --------------------
+  - compatible: "ti,c64x+megamod-pic"
+  - interrupt-controller
+  - #interrupt-cells: <1>
+  - reg: base address and size of register area
+  - interrupt-parent: must be core interrupt controller
+  - interrupts: This should have four cells; one for each interrupt combiner.
+                The cells contain the core priority interrupt to which the
+                corresponding combiner output is wired.
+  Optional properties:
+  --------------------
+  - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
+                             priority interrupts. The first cell corresponds to
+                             core priority 4 and the last cell corresponds to
+                             core priority 15. The value of each cell is the
+                             megamodule interrupt source which is MUXed to
+                             the core interrupt corresponding to the cell
+                             position. Allowed values are 4 - 127. Mapping for
+                             interrupts 0 - 3 (combined interrupt sources) are
+                             ignored.
+  Interrupt Specifier Definition
+  ------------------------------
+  Single cell specifying the megamodule interrupt source (4-127). Note that
+  interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
+  use the core interrupt controller as their parent and the specifier will
+  be the core priority level, not the megamodule interrupt number.
+  Examples
+  --------
+  megamod_pic: interrupt-controller@1800000 {
+        compatible = "ti,c64x+megamod-pic";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        reg = <0x1800000 0x1000>;
+        interrupt-parent = <&core_pic>;
+        interrupts = < 12 13 14 15 >;
+  };
+  This is a minimal example where all individual interrupts go through a
+  combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
+  to interrupt 13, etc.
+  megamod_pic: interrupt-controller@1800000 {
+        compatible = "ti,c64x+megamod-pic";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        reg = <0x1800000 0x1000>;
+        interrupt-parent = <&core_pic>;
+        interrupts = < 12 13 14 15 >;
+        ti,c64x+megamod-pic-mux = <  0  0  0  0
+                                    32  0  0  0
+                                     0  0  0  0 >;
+  };
+  This the same as the first example except that megamodule interrupt 32 is
+  mapped directly to core priority interrupt 8. The node using this interrupt
+  must set the core controller as its interrupt parent and use 8 in the
+  interrupt specifier value.
diff --git a/Documentation/devicetree/bindings/c6x/soc.txt b/Documentation/devicetree/bindings/c6x/soc.txt
new file mode 100644
index 00000000000..b1e4973b576
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/soc.txt
@@ -0,0 +1,28 @@
+C6X System-on-Chip
+------------------
+Required properties:
+- compatible: "simple-bus"
+- #address-cells: must be 1
+- #size-cells: must be 1
+- ranges
+Optional properties:
+- model: specific SoC model
+- nodes for IP blocks within SoC
+Example:
+        soc {
+                compatible = "simple-bus";
+                model = "tms320c6455";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ...
+        };
diff --git a/Documentation/devicetree/bindings/c6x/timer64.txt b/Documentation/devicetree/bindings/c6x/timer64.txt
new file mode 100644
index 00000000000..95911fe7022
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/timer64.txt
@@ -0,0 +1,26 @@
+Timer64
+-------
+The timer64 node describes C6X event timers.
+Required properties:
+- compatible: must be "ti,c64x+timer64"
+- reg: base address and size of register region
+- interrupt-parent: interrupt controller
+- interrupts: interrupt id
+Optional properties:
+- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
+- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
+Example:
+        timer0: timer@25e0000 {
+                compatible = "ti,c64x+timer64";
+                ti,core-mask = < 0x01 >;
+                reg = <0x25e0000 0x40>;
+                interrupt-parent = <&megamod_pic>;
+                interrupts = < 16 >;
+        };
diff --git a/Documentation/devicetree/bindings/dma/arm-pl330.txt b/Documentation/devicetree/bindings/dma/arm-pl330.txt
new file mode 100644
index 00000000000..a4cd273b2a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/arm-pl330.txt
@@ -0,0 +1,30 @@
+* ARM PrimeCell PL330 DMA Controller
+The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
+between memory and peripherals or memory to memory.
+Required properties:
+  - compatible: should include both "arm,pl330" and "arm,primecell".
+  - reg: physical base address of the controller and length of memory mapped
+    region.
+  - interrupts: interrupt number to the cpu.
+Example:
+        pdma0: pdma@12680000 {
+                compatible = "arm,pl330", "arm,primecell";
+                reg = <0x12680000 0x1000>;
+                interrupts = <99>;
+        };
+Client drivers (device nodes requiring dma transfers from dev-to-mem or
+mem-to-dev) should specify the DMA channel numbers using a two-value pair
+as shown below.
+  [property name]  = <[phandle of the dma controller] [dma request id]>;
+      where 'dma request id' is the dma request number which is connected
+      to the client controller. The 'property name' is recommended to be
+      of the form <name>-dma-channel.
+  Example:  tx-dma-channel = <&pdma0 12>;
diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt
new file mode 100644
index 00000000000..3c046ee6e8b
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/atmel-dma.txt
@@ -0,0 +1,14 @@
+* Atmel Direct Memory Access Controller (DMA)
+Required properties:
+- compatible: Should be "atmel,<chip>-dma"
+- reg: Should contain DMA registers location and length
+- interrupts: Should contain DMA interrupt
+Examples:
+dma@ffffec00 {
+        compatible = "atmel,at91sam9g45-dma";
+        reg = <0xffffec00 0x200>;
+        interrupts = <21>;
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-samsung.txt b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
new file mode 100644
index 00000000000..8f50fe5e6c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-samsung.txt
@@ -0,0 +1,40 @@
+Samsung Exynos4 GPIO Controller
+Required properties:
+- compatible: Compatible property value should be "samsung,exynos4-gpio>".
+- reg: Physical base address of the controller and length of memory mapped
+  region.
+- #gpio-cells: Should be 4. The syntax of the gpio specifier used by client nodes
+  should be the following with values derived from the SoC user manual.
+     <[phandle of the gpio controller node]
+      [pin number within the gpio controller]
+      [mux function]
+      [pull up/down]
+      [drive strength]>
+  Values for gpio specifier:
+  - Pin number: is a value between 0 to 7.
+  - Pull Up/Down: 0 - Pull Up/Down Disabled.
+                  1 - Pull Down Enabled.
+                  3 - Pull Up Enabled.
+  - Drive Strength: 0 - 1x,
+                    1 - 3x,
+                    2 - 2x,
+                    3 - 4x
+- gpio-controller: Specifies that the node is a gpio controller.
+- #address-cells: should be 1.
+- #size-cells: should be 1.
+Example:
+        gpa0: gpio-controller@11400000 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "samsung,exynos4-gpio";
+                reg = <0x11400000 0x20>;
+                #gpio-cells = <4>;
+                gpio-controller;
+        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
new file mode 100644
index 00000000000..e42a2ee233e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
@@ -0,0 +1,22 @@
+* Synopsys DesignWare I2C
+Required properties :
+ - compatible : should be "snps,designware-i2c"
+ - reg : Offset and length of the register set for the device
+ - interrupts : <IRQ> where IRQ is the interrupt number.
+Recommended properties :
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+Example :
+        i2c@f0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "snps,designware-i2c";
+                reg = <0xf0000 0x1000>;
+                interrupts = <11>;
+                clock-frequency = <400000>;
+        };
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
new file mode 100644
index 00000000000..1a85f986961
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -0,0 +1,58 @@
+This is a list of trivial i2c devices that have simple device tree
+bindings, consisting only of a compatible field, an address and
+possibly an interrupt line.
+If a device needs more specific bindings, such as properties to
+describe some aspect of it, there needs to be a specific binding
+document for it just like any other devices.
+Compatible              Vendor / Chip
+==========              =============
+ad,ad7414               SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
+ad,adm9240              ADM9240:  Complete System Hardware Monitor for uProcessor-Based Systems
+adi,adt7461             +/-1C TDM Extended Temp Range I.C
+adt7461                 +/-1C TDM Extended Temp Range I.C
+at,24c08                i2c serial eeprom  (24cxx)
+atmel,24c02             i2c serial eeprom  (24cxx)
+catalyst,24c32          i2c serial eeprom
+dallas,ds1307           64 x 8, Serial, I2C Real-Time Clock
+dallas,ds1338           I2C RTC with 56-Byte NV RAM
+dallas,ds1339           I2C Serial Real-Time Clock
+dallas,ds1340           I2C RTC with Trickle Charger
+dallas,ds1374           I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
+dallas,ds1631           High-Precision Digital Thermometer
+dallas,ds1682           Total-Elapsed-Time Recorder with Alarm
+dallas,ds1775           Tiny Digital Thermometer and Thermostat
+dallas,ds3232           Extremely Accurate I²C RTC with Integrated Crystal and SRAM
+dallas,ds4510           CPU Supervisor with Nonvolatile Memory and Programmable I/O
+dallas,ds75             Digital Thermometer and Thermostat
+dialog,da9053           DA9053: flexible system level PMIC with multicore support
+epson,rx8025            High-Stability. I2C-Bus INTERFACE REAL TIME CLOCK MODULE
+epson,rx8581            I2C-BUS INTERFACE REAL TIME CLOCK MODULE
+fsl,mag3110             MAG3110: Xtrinsic High Accuracy, 3D Magnetometer
+fsl,mc13892             MC13892: Power Management Integrated Circuit (PMIC) for i.MX35/51
+fsl,mma8450             MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer
+fsl,mpr121              MPR121: Proximity Capacitive Touch Sensor Controller
+fsl,sgtl5000            SGTL5000: Ultra Low-Power Audio Codec
+maxim,ds1050            5 Bit Programmable, Pulse-Width Modulator
+maxim,max1237           Low-Power, 4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
+maxim,max6625           9-Bit/12-Bit Temperature Sensors with I²C-Compatible Serial Interface
+mc,rv3029c2             Real Time Clock Module with I2C-Bus
+national,lm75           I2C TEMP SENSOR
+national,lm80           Serial Interface ACPI-Compatible Microprocessor System Hardware Monitor
+national,lm92           ±0.33°C Accurate, 12-Bit + Sign Temperature Sensor and Thermal Window Comparator with Two-Wire Interface
+nxp,pca9556             Octal SMBus and I2C registered interface
+nxp,pca9557             8-bit I2C-bus and SMBus I/O port with reset
+nxp,pcf8563             Real-time clock/calendar
+ovti,ov5642             OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
+pericom,pt7c4338        Real-time Clock Module
+plx,pex8648             48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
+ramtron,24c64           i2c serial eeprom  (24cxx)
+ricoh,rs5c372a          I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC
+samsung,24ad0xd1        S524AD0XF1 (128K/256K-bit Serial EEPROM for Low Power)
+st-micro,24c256         i2c serial eeprom  (24cxx)
+stm,m41t00              Serial Access TIMEKEEPER
+stm,m41t62              Serial real-time clock (RTC) with alarm
+stm,m41t80              M41T80 - SERIAL ACCESS RTC WITH ALARMS
+ti,tsc2003              I2C Touch-Screen Controller
diff --git a/Documentation/devicetree/bindings/input/samsung-keypad.txt b/Documentation/devicetree/bindings/input/samsung-keypad.txt
new file mode 100644
index 00000000000..ce3e394c0e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/samsung-keypad.txt
@@ -0,0 +1,88 @@
+* Samsung's Keypad Controller device tree bindings
+Samsung's Keypad controller is used to interface a SoC with a matrix-type
+keypad device. The keypad controller supports multiple row and column lines.
+A key can be placed at each intersection of a unique row and a unique column.
+The keypad controller can sense a key-press and key-release and report the
+event using a interrupt to the cpu.
+Required SoC Specific Properties:
+- compatible: should be one of the following
+  - "samsung,s3c6410-keypad": For controllers compatible with s3c6410 keypad
+    controller.
+  - "samsung,s5pv210-keypad": For controllers compatible with s5pv210 keypad
+    controller.
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: The interrupt number to the cpu.
+Required Board Specific Properties:
+- samsung,keypad-num-rows: Number of row lines connected to the keypad
+  controller.
+- samsung,keypad-num-columns: Number of column lines connected to the
+  keypad controller.
+- row-gpios: List of gpios used as row lines. The gpio specifier for
+  this property depends on the gpio controller to which these row lines
+  are connected.
+- col-gpios: List of gpios used as column lines. The gpio specifier for
+  this property depends on the gpio controller to which these column
+  lines are connected.
+- Keys represented as child nodes: Each key connected to the keypad
+  controller is represented as a child node to the keypad controller
+  device node and should include the following properties.
+  - keypad,row: the row number to which the key is connected.
+  - keypad,column: the column number to which the key is connected.
+  - linux,code: the key-code to be reported when the key is pressed
+    and released.
+Optional Properties specific to linux:
+- linux,keypad-no-autorepeat: do no enable autorepeat feature.
+- linux,keypad-wakeup: use any event on keypad as wakeup event.
+Example:
+        keypad@100A0000 {
+                compatible = "samsung,s5pv210-keypad";
+                reg = <0x100A0000 0x100>;
+                interrupts = <173>;
+                samsung,keypad-num-rows = <2>;
+                samsung,keypad-num-columns = <8>;
+                linux,input-no-autorepeat;
+                linux,input-wakeup;
+                row-gpios = <&gpx2 0 3 3 0
+                             &gpx2 1 3 3 0>;
+                col-gpios = <&gpx1 0 3 0 0
+                             &gpx1 1 3 0 0
+                             &gpx1 2 3 0 0
+                             &gpx1 3 3 0 0
+                             &gpx1 4 3 0 0
+                             &gpx1 5 3 0 0
+                             &gpx1 6 3 0 0
+                             &gpx1 7 3 0 0>;
+                key_1 {
+                        keypad,row = <0>;
+                        keypad,column = <3>;
+                        linux,code = <2>;
+                };
+                key_2 {
+                        keypad,row = <0>;
+                        keypad,column = <4>;
+                        linux,code = <3>;
+                };
+                key_3 {
+                        keypad,row = <0>;
+                        keypad,column = <5>;
+                        linux,code = <4>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/input/tegra-kbc.txt b/Documentation/devicetree/bindings/input/tegra-kbc.txt
new file mode 100644
index 00000000000..5ecfa99089b
--- /dev/null
+++ b/Documentation/devicetree/bindings/input/tegra-kbc.txt
@@ -0,0 +1,18 @@
+* Tegra keyboard controller
+Required properties:
+- compatible: "nvidia,tegra20-kbc"
+Optional properties:
+- debounce-delay: delay in milliseconds per row scan for debouncing
+- repeat-delay: delay in milliseconds before repeat starts
+- ghost-filter: enable ghost filtering for this device
+- wakeup-source: configure keyboard as a wakeup source for suspend/resume
+Example:
+keyboard: keyboard {
+        compatible = "nvidia,tegra20-kbc";
+        reg = <0x7000e200 0x100>;
+        ghost-filter;
+};
diff --git a/Documentation/devicetree/bindings/mfd/mc13xxx.txt b/Documentation/devicetree/bindings/mfd/mc13xxx.txt
new file mode 100644
index 00000000000..19f6af47a79
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mc13xxx.txt
@@ -0,0 +1,78 @@
+* Freescale MC13783/MC13892 Power Management Integrated Circuit (PMIC)
+Required properties:
+- compatible : Should be "fsl,mc13783" or "fsl,mc13892"
+Optional properties:
+- fsl,mc13xxx-uses-adc : Indicate the ADC is being used
+- fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
+- fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
+- fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
+Sub-nodes:
+- regulators : Contain the regulator nodes.  The MC13892 regulators are
+  bound using their names as listed below with their registers and bits
+  for enabling.
+    vcoincell : regulator VCOINCELL (register 13, bit 23)
+    sw1       : regulator SW1       (register 24, bit 0)
+    sw2       : regulator SW2       (register 25, bit 0)
+    sw3       : regulator SW3       (register 26, bit 0)
+    sw4       : regulator SW4       (register 27, bit 0)
+    swbst     : regulator SWBST     (register 29, bit 20)
+    vgen1     : regulator VGEN1     (register 32, bit 0)
+    viohi     : regulator VIOHI     (register 32, bit 3)
+    vdig      : regulator VDIG      (register 32, bit 9)
+    vgen2     : regulator VGEN2     (register 32, bit 12)
+    vpll      : regulator VPLL      (register 32, bit 15)
+    vusb2     : regulator VUSB2     (register 32, bit 18)
+    vgen3     : regulator VGEN3     (register 33, bit 0)
+    vcam      : regulator VCAM      (register 33, bit 6)
+    vvideo    : regulator VVIDEO    (register 33, bit 12)
+    vaudio    : regulator VAUDIO    (register 33, bit 15)
+    vsd       : regulator VSD       (register 33, bit 18)
+    gpo1      : regulator GPO1      (register 34, bit 6)
+    gpo2      : regulator GPO2      (register 34, bit 8)
+    gpo3      : regulator GPO3      (register 34, bit 10)
+    gpo4      : regulator GPO4      (register 34, bit 12)
+    pwgt1spi  : regulator PWGT1SPI  (register 34, bit 15)
+    pwgt2spi  : regulator PWGT2SPI  (register 34, bit 16)
+    vusb      : regulator VUSB      (register 50, bit 3)
+  The bindings details of individual regulator device can be found in:
+  Documentation/devicetree/bindings/regulator/regulator.txt
+Examples:
+ecspi@70010000 { /* ECSPI1 */
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
+                   <&gpio3 25 0>; /* GPIO4_25 */
+        status = "okay";
+        pmic: mc13892@0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "fsl,mc13892";
+                spi-max-frequency = <6000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <8>;
+                regulators {
+                        sw1_reg: mc13892__sw1 {
+                                regulator-min-microvolt = <600000>;
+                                regulator-max-microvolt = <1375000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw2_reg: mc13892__sw2 {
+                                regulator-min-microvolt = <900000>;
+                                regulator-max-microvolt = <1850000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
diff --git a/Documentation/devicetree/bindings/mfd/twl-familly.txt b/Documentation/devicetree/bindings/mfd/twl-familly.txt
new file mode 100644
index 00000000000..a66fcf94675
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/twl-familly.txt
@@ -0,0 +1,47 @@
+Texas Instruments TWL family
+The TWLs are Integrated Power Management Chips.
+Some version might contain much more analog function like
+USB transceiver or Audio amplifier.
+These chips are connected to an i2c bus.
+Required properties:
+- compatible : Must be "ti,twl4030";
+  For Integrated power-management/audio CODEC device used in OMAP3
+  based boards
+- compatible : Must be "ti,twl6030";
+  For Integrated power-management used in OMAP4 based boards
+- interrupts : This i2c device has an IRQ line connected to the main SoC
+- interrupt-controller : Since the twl support several interrupts internally,
+  it is considered as an interrupt controller cascaded to the SoC one.
+- #interrupt-cells = <1>;
+- interrupt-parent : The parent interrupt controller.
+Optional node:
+- Child nodes contain in the twl. The twl family is made of several variants
+  that support a different number of features.
+  The children nodes will thus depend of the capability of the variant.
+Example:
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/twl6030.pdf
+ */
+twl@48 {
+    compatible = "ti,twl6030";
+    reg = <0x48>;
+    interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
+    interrupt-controller;
+    #interrupt-cells = <1>;
+    interrupt-parent = <&gic>;
+    #address-cells = <1>;
+    #size-cells = <0>;
+    twl_rtc {
+        compatible = "ti,twl_rtc";
+        interrupts = <11>;
+        reg = <0>;
+    };
+};
diff --git a/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
new file mode 100644
index 00000000000..719f4dc58df
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/gpio-control-nand.txt
@@ -0,0 +1,44 @@
+GPIO assisted NAND flash
+The GPIO assisted NAND flash uses a memory mapped interface to
+read/write the NAND commands and data and GPIO pins for the control
+signals.
+Required properties:
+- compatible : "gpio-control-nand"
+- reg : should specify localbus chip select and size used for the chip.  The
+  resource describes the data bus connected to the NAND flash and all accesses
+  are made in native endianness.
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+  representing partitions.
+- gpios : specifies the gpio pins to control the NAND device.  nwp is an
+  optional gpio and may be set to 0 if not present.
+Optional properties:
+- bank-width : Width (in bytes) of the device.  If not present, the width
+  defaults to 1 byte.
+- chip-delay : chip dependent delay for transferring data from array to
+  read registers (tR).  If not present then a default of 20us is used.
+- gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
+  location used to guard against bus reordering with regards to accesses to
+  the GPIO's and the NAND flash data bus.  If present, then after changing
+  GPIO state and before and after command byte writes, this register will be
+  read to ensure that the GPIO accesses have completed.
+Examples:
+gpio-nand@1,0 {
+        compatible = "gpio-control-nand";
+        reg = <1 0x0000 0x2>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        gpios = <&banka 1 0     /* rdy */
+                 &banka 2 0     /* nce */
+                 &banka 3 0     /* ale */
+                 &banka 4 0     /* cle */
+                 0              /* nwp */>;
+        partition@0 {
+        ...
+        };
+};
diff --git a/Documentation/devicetree/bindings/net/calxeda-xgmac.txt b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
new file mode 100644
index 00000000000..411727a3f82
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/calxeda-xgmac.txt
@@ -0,0 +1,15 @@
+* Calxeda Highbank 10Gb XGMAC Ethernet
+Required properties:
+- compatible : Should be "calxeda,hb-xgmac"
+- reg : Address and length of the register set for the device
+- interrupts : Should contain 3 xgmac interrupts. The 1st is main interrupt.
+  The 2nd is pwr mgt interrupt. The 3rd is low power state interrupt.
+Example:
+ethernet@fff50000 {
+        compatible = "calxeda,hb-xgmac";
+        reg = <0xfff50000 0x1000>;
+        interrupts = <0 77 4  0 78 4  0 79 4>;
+};
diff --git a/Documentation/devicetree/bindings/net/can/cc770.txt b/Documentation/devicetree/bindings/net/can/cc770.txt
new file mode 100644
index 00000000000..77027bf6460
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/can/cc770.txt
@@ -0,0 +1,53 @@
+Memory mapped Bosch CC770 and Intel AN82527 CAN controller
+Note: The CC770 is a CAN controller from Bosch, which is 100%
+compatible with the old AN82527 from Intel, but with "bugs" being fixed.
+Required properties:
+- compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
+        for the AN82527.
+- reg : should specify the chip select, address offset and size required
+        to map the registers of the controller. The size is usually 0x80.
+- interrupts : property with a value describing the interrupt source
+        (number and sensitivity) required for the controller.
+Optional properties:
+- bosch,external-clock-frequency : frequency of the external oscillator
+        clock in Hz. Note that the internal clock frequency used by the
+        controller is half of that value. If not specified, a default
+        value of 16000000 (16 MHz) is used.
+- bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
+        If not specified or if the specified value is 0, the CLKOUT pin
+        will be disabled.
+- bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
+        a resonable value will be calculated.
+- bosch,disconnect-rx0-input : see data sheet.
+- bosch,disconnect-rx1-input : see data sheet.
+- bosch,disconnect-tx1-output : see data sheet.
+- bosch,polarity-dominant : see data sheet.
+- bosch,divide-memory-clock : see data sheet.
+- bosch,iso-low-speed-mux : see data sheet.
+For further information, please have a look to the CC770 or AN82527.
+Examples:
+can@3,100 {
+        compatible = "bosch,cc770";
+        reg = <3 0x100 0x80>;
+        interrupts = <2 0>;
+        interrupt-parent = <&mpic>;
+        bosch,external-clock-frequency = <16000000>;
+};
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
new file mode 100644
index 00000000000..44afa0e5057
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -0,0 +1,25 @@
+* Cadence MACB/GEM Ethernet controller
+Required properties:
+- compatible: Should be "cdns,[<chip>-]{macb|gem}"
+  Use "cdns,at91sam9260-macb" Atmel at91sam9260 and at91sam9263 SoCs.
+  Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
+  Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on
+  the Cadence GEM, or the generic form: "cdns,gem".
+- reg: Address and length of the register set for the device
+- interrupts: Should contain macb interrupt
+- phy-mode: String, operation mode of the PHY interface.
+  Supported values are: "mii", "rmii", "gmii", "rgmii".
+Optional properties:
+- local-mac-address: 6 bytes, mac address
+Examples:
+        macb0: ethernet@fffc4000 {
+                compatible = "cdns,at32ap7000-macb";
+                reg = <0xfffc4000 0x4000>;
+                interrupts = <21>;
+                phy-mode = "rmii";
+                local-mac-address = [3a 0e 03 04 05 06];
+        };
diff --git a/Documentation/devicetree/bindings/nvec/nvec_nvidia.txt b/Documentation/devicetree/bindings/nvec/nvec_nvidia.txt
new file mode 100644
index 00000000000..5aeee53ff9f
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvec/nvec_nvidia.txt
@@ -0,0 +1,9 @@
+NVIDIA compliant embedded controller
+Required properties:
+- compatible : should be "nvidia,nvec".
+- reg : the iomem of the i2c slave controller
+- interrupts : the interrupt line of the i2c slave controller
+- clock-frequency : the frequency of the i2c bus
+- gpios : the gpio used for ec request
+- slave-addr: the i2c address of the slave controller
diff --git a/Documentation/devicetree/bindings/power_supply/olpc_battery.txt b/Documentation/devicetree/bindings/power_supply/olpc_battery.txt
new file mode 100644
index 00000000000..c8901b3992d
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/olpc_battery.txt
@@ -0,0 +1,5 @@
+OLPC battery
+~~~~~~~~~~~~
+Required properties:
+  - compatible : "olpc,xo1-battery"
diff --git a/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt b/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt
new file mode 100644
index 00000000000..c40e8926fac
--- /dev/null
+++ b/Documentation/devicetree/bindings/power_supply/sbs_sbs-battery.txt
@@ -0,0 +1,23 @@
+SBS sbs-battery
+~~~~~~~~~~
+Required properties :
+ - compatible : "sbs,sbs-battery"
+Optional properties :
+ - sbs,i2c-retry-count : The number of times to retry i2c transactions on i2c
+   IO failure.
+ - sbs,poll-retry-count : The number of times to try looking for new status
+   after an external change notification.
+ - sbs,battery-detect-gpios : The gpio which signals battery detection and
+   a flag specifying its polarity.
+Example:
+        bq20z75@b {
+                compatible = "sbs,sbs-battery";
+                reg = < 0xb >;
+                sbs,i2c-retry-count = <2>;
+                sbs,poll-retry-count = <10>;
+                sbs,battery-detect-gpios = <&gpio-controller 122 1>;
+        }
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt
new file mode 100644
index 00000000000..b9a8a2bcfae
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/srio-rmu.txt
@@ -0,0 +1,163 @@
+Message unit node:
+For SRIO controllers that implement the message unit as part of the controller
+this node is required.  For devices with RMAN this node should NOT exist.  The
+node is composed of three types of sub-nodes ("fsl-srio-msg-unit",
+"fsl-srio-dbell-unit" and "fsl-srio-port-write-unit").
+See srio.txt for more details about generic SRIO controller details.
+   - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,srio-rmu-vX.Y", "fsl,srio-rmu".
+        The version X.Y should match the general SRIO controller's IP Block
+        revision register's Major(X) and Minor (Y) value.
+   - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address and
+                length of the SRIO configuration registers for message units
+                and doorbell units.
+   - fsl,liodn
+        Usage: optional-but-recommended (for devices with PAMU)
+        Value type: <prop-encoded-array>
+        Definition: The logical I/O device number for the PAMU (IOMMU) to be
+                correctly configured for SRIO accesses.  The property should
+                not exist on devices that do not support PAMU.
+                The LIODN value is associated with all RMU transactions
+                (msg-unit, doorbell, port-write).
+Sub-Nodes for RMU:  The RMU node is composed of multiple sub-nodes that
+correspond to the actual sub-controllers in the RMU.  The manual for a given
+SoC will detail which and how many of these sub-controllers are implemented.
+Message Unit:
+   - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,srio-msg-unit-vX.Y", "fsl,srio-msg-unit".
+        The version X.Y should match the general SRIO controller's IP Block
+        revision register's Major(X) and Minor (Y) value.
+   - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address and
+                length of the SRIO configuration registers for message units
+                and doorbell units.
+   - interrupts
+        Usage: required
+        Value type: <prop_encoded-array>
+        Definition:  Specifies the interrupts generated by this device.  The
+                value of the interrupts property consists of one interrupt
+                specifier. The format of the specifier is defined by the
+                binding document describing the node's interrupt parent.
+                A pair of IRQs are specified in this property.  The first
+                element is associated with the transmit (TX) interrupt and the
+                second element is associated with the receive (RX) interrupt.
+Doorbell Unit:
+   - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include:
+                "fsl,srio-dbell-unit-vX.Y", "fsl,srio-dbell-unit"
+        The version X.Y should match the general SRIO controller's IP Block
+        revision register's Major(X) and Minor (Y) value.
+   - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address and
+                length of the SRIO configuration registers for message units
+                and doorbell units.
+   - interrupts
+        Usage: required
+        Value type: <prop_encoded-array>
+        Definition:  Specifies the interrupts generated by this device.  The
+                value of the interrupts property consists of one interrupt
+                specifier. The format of the specifier is defined by the
+                binding document describing the node's interrupt parent.
+                A pair of IRQs are specified in this property.  The first
+                element is associated with the transmit (TX) interrupt and the
+                second element is associated with the receive (RX) interrupt.
+Port-Write Unit:
+   - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include:
+                 "fsl,srio-port-write-unit-vX.Y", "fsl,srio-port-write-unit"
+        The version X.Y should match the general SRIO controller's IP Block
+        revision register's Major(X) and Minor (Y) value.
+   - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address and
+                length of the SRIO configuration registers for message units
+                and doorbell units.
+   - interrupts
+        Usage: required
+        Value type: <prop_encoded-array>
+        Definition:  Specifies the interrupts generated by this device.  The
+                value of the interrupts property consists of one interrupt
+                specifier. The format of the specifier is defined by the
+                binding document describing the node's interrupt parent.
+                A single IRQ that handles port-write conditions is
+                specified by this property.  (Typically shared with error).
+   Note: All other standard properties (see the ePAPR) are allowed
+   but are optional.
+Example:
+        rmu: rmu@d3000 {
+                compatible = "fsl,srio-rmu";
+                reg = <0xd3000 0x400>;
+                ranges = <0x0 0xd3000 0x400>;
+                fsl,liodn = <0xc8>;
+                message-unit@0 {
+                        compatible = "fsl,srio-msg-unit";
+                        reg = <0x0 0x100>;
+                        interrupts = <
+                                60 2 0 0  /* msg1_tx_irq */
+                                61 2 0 0>;/* msg1_rx_irq */
+                };
+                message-unit@100 {
+                        compatible = "fsl,srio-msg-unit";
+                        reg = <0x100 0x100>;
+                        interrupts = <
+                                62 2 0 0  /* msg2_tx_irq */
+                                63 2 0 0>;/* msg2_rx_irq */
+                };
+                doorbell-unit@400 {
+                        compatible = "fsl,srio-dbell-unit";
+                        reg = <0x400 0x80>;
+                        interrupts = <
+                                56 2 0 0  /* bell_outb_irq */
+                                57 2 0 0>;/* bell_inb_irq */
+                };
+                port-write-unit@4e0 {
+                        compatible = "fsl,srio-port-write-unit";
+                        reg = <0x4e0 0x20>;
+                        interrupts = <16 2 1 11>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/srio.txt b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
new file mode 100644
index 00000000000..b039bcbee13
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/srio.txt
@@ -0,0 +1,103 @@
+* Freescale Serial RapidIO (SRIO) Controller
+RapidIO port node:
+Properties:
+   - compatible
+        Usage: required
+        Value type: <string>
+        Definition: Must include "fsl,srio" for IP blocks with IP Block
+        Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
+        Optionally, a compatiable string of "fsl,srio-vX.Y" where X is Major
+        version in IP Block Revision Register and Y is Minor version.  If this
+        compatiable is provided it should be ordered before "fsl,srio".
+   - reg
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies the physical address and
+                length of the SRIO configuration registers.  The size should
+                be set to 0x11000.
+   - interrupts
+        Usage: required
+        Value type: <prop_encoded-array>
+        Definition:  Specifies the interrupts generated by this device.  The
+                value of the interrupts property consists of one interrupt
+                specifier. The format of the specifier is defined by the
+                binding document describing the node's interrupt parent.
+                A single IRQ that handles error conditions is specified by this
+                property.  (Typically shared with port-write).
+   - fsl,srio-rmu-handle:
+        Usage: required if rmu node is defined
+        Value type: <phandle>
+        Definition: A single <phandle> value that points to the RMU.
+        (See srio-rmu.txt for more details on RMU node binding)
+Port Child Nodes:  There should a port child node for each port that exists in
+the controller.  The ports are numbered starting at one (1) and should have
+the following properties:
+   - cell-index
+        Usage: required
+        Value type: <u32>
+        Definition: A standard property.  Matches the port id.
+   - ranges
+        Usage: required if local access windows preset
+        Value type: <prop-encoded-array>
+        Definition: A standard property. Utilized to describe the memory mapped
+                IO space utilized by the controller.  This corresponds to the
+                setting of the local access windows that are targeted to this
+                SRIO port.
+   - fsl,liodn
+        Usage: optional-but-recommended (for devices with PAMU)
+        Value type: <prop-encoded-array>
+        Definition: The logical I/O device number for the PAMU (IOMMU) to be
+                correctly configured for SRIO accesses.  The property should
+                not exist on devices that do not support PAMU.
+                For HW (ie, the P4080) that only supports a LIODN for both
+                memory and maintenance transactions then a single LIODN is
+                represented in the property for both transactions.
+                For HW (ie, the P304x/P5020, etc) that supports an LIODN for
+                memory transactions and a unique LIODN for maintenance
+                transactions then a pair of LIODNs are represented in the
+                property.  Within the pair, the first element represents the
+                LIODN associated with memory transactions and the second element
+                represents the LIODN associated with maintenance transactions
+                for the port.
+Note: All other standard properties (see ePAPR) are allowed but are optional.
+Example:
+        rapidio: rapidio@ffe0c0000 {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                reg = <0xf 0xfe0c0000 0 0x11000>;
+                compatible = "fsl,srio";
+                interrupts = <16 2 1 11>; /* err_irq */
+                fsl,srio-rmu-handle = <&rmu>;
+                ranges;
+                port1 {
+                        cell-index = <1>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        fsl,liodn = <34>;
+                        ranges = <0 0 0xc 0x20000000 0 0x10000000>;
+                };
+                port2 {
+                        cell-index = <2>;
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        fsl,liodn = <48>;
+                        ranges = <0 0 0xc 0x30000000 0 0x10000000>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
new file mode 100644
index 00000000000..9cf57fd042d
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
@@ -0,0 +1,29 @@
+Fixed Voltage regulators
+Required properties:
+- compatible: Must be "regulator-fixed";
+Optional properties:
+- gpio: gpio to use for enable control
+- startup-delay-us: startup time in microseconds
+- enable-active-high: Polarity of GPIO is Active high
+If this property is missing, the default assumed is Active low.
+Any property defined as part of the core regulator
+binding, defined in regulator.txt, can also be used.
+However a fixed voltage regulator is expected to have the
+regulator-min-microvolt and regulator-max-microvolt
+to be the same.
+Example:
+        abc: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "fixed-supply";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                gpio = <&gpio1 16 0>;
+                startup-delay-us = <70000>;
+                enable-active-high;
+                regulator-boot-on
+        };
diff --git a/Documentation/devicetree/bindings/regulator/regulator.txt b/Documentation/devicetree/bindings/regulator/regulator.txt
new file mode 100644
index 00000000000..5b7a408acda
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/regulator.txt
@@ -0,0 +1,54 @@
+Voltage/Current Regulators
+Optional properties:
+- regulator-name: A string used as a descriptive name for regulator outputs
+- regulator-min-microvolt: smallest voltage consumers may set
+- regulator-max-microvolt: largest voltage consumers may set
+- regulator-microvolt-offset: Offset applied to voltages to compensate for voltage drops
+- regulator-min-microamp: smallest current consumers may set
+- regulator-max-microamp: largest current consumers may set
+- regulator-always-on: boolean, regulator should never be disabled
+- regulator-boot-on: bootloader/firmware enabled regulator
+- <name>-supply: phandle to the parent supply/regulator node
+Example:
+        xyzreg: regulator@0 {
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <2500000>;
+                regulator-always-on;
+                vin-supply = <&vin>;
+        };
+Regulator Consumers:
+Consumer nodes can reference one or more of its supplies/
+regulators using the below bindings.
+- <name>-supply: phandle to the regulator node
+These are the same bindings that a regulator in the above
+example used to reference its own supply, in which case
+its just seen as a special case of a regulator being a
+consumer itself.
+Example of a consumer device node (mmc) referencing two
+regulators (twl_reg1 and twl_reg2),
+        twl_reg1: regulator@0 {
+                ...
+                ...
+                ...
+        };
+        twl_reg2: regulator@1 {
+                ...
+                ...
+                ...
+        };
+        mmc: mmc@0x0 {
+                ...
+                ...
+                vmmc-supply = <&twl_reg1>;
+                vmmcaux-supply = <&twl_reg2>;
+        };
diff --git a/Documentation/devicetree/bindings/resource-names.txt b/Documentation/devicetree/bindings/resource-names.txt
new file mode 100644
index 00000000000..e280fef6f26
--- /dev/null
+++ b/Documentation/devicetree/bindings/resource-names.txt
@@ -0,0 +1,54 @@
+Some properties contain an ordered list of 1 or more datum which are
+normally accessed by index.  However, some devices will have multiple
+values which are more naturally accessed by name.  Device nodes can
+include a supplemental property for assigning names to each of the list
+items.  The names property consists of a list of strings in the same
+order as the data in the resource property.
+The following supplemental names properties are defined.
+Resource Property       Supplemental Names Property
+-----------------       ---------------------------
+reg                     reg-names
+clocks                  clock-names
+interrupts              interrupt-names
+Usage:
+The -names property must be used in conjunction with the normal resource
+property. If not it will be ignored.
+Examples:
+l4-abe {
+        compatible = "simple-bus";
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <0 0 0x48000000 0x00001000>, /* MPU path */
+                 <1 0 0x49000000 0x00001000>; /* L3 path */
+        mcasp {
+                compatible = "ti,mcasp";
+                reg = <0 0x10 0x10>, <0 0x20 0x10>,
+                      <1 0x10 0x10>, <1 0x20 0x10>;
+                reg-names = "mpu", "dat",
+                            "dma", "dma_dat";
+                interrupts = <11>, <12>;
+                interrupt-names = "rx", "tx";
+        };
+        timer {
+                compatible = "ti,timer";
+                reg = <0 0x40 0x10>, <1 0x40 0x10>;
+                reg-names = "mpu", "dma";
+        };
+};
+usb {
+        compatible = "ti,usb-host";
+        reg = <0x4a064000 0x800>, <0x4a064800 0x200>,
+              <0x4a064c00 0x200>;
+        reg-names = "config", "ohci", "ehci";
+        interrupts = <14>, <15>;
+        interrupt-names = "ohci", "ehci";
+};
diff --git a/Documentation/devicetree/bindings/rtc/s3c-rtc.txt b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
new file mode 100644
index 00000000000..90ec45fd33e
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/s3c-rtc.txt
@@ -0,0 +1,20 @@
+* Samsung's S3C Real Time Clock controller
+Required properties:
+- compatible: should be one of the following.
+    * "samsung,s3c2410-rtc" - for controllers compatible with s3c2410 rtc.
+    * "samsung,s3c6410-rtc" - for controllers compatible with s3c6410 rtc.
+- reg: physical base address of the controller and length of memory mapped
+  region.
+- interrupts: Two interrupt numbers to the cpu should be specified. First
+  interrupt number is the rtc alarm interupt and second interrupt number
+  is the rtc tick interrupt. The number of cells representing a interrupt
+  depends on the parent interrupt controller.
+Example:
+        rtc@10070000 {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x10070000 0x100>;
+                interrupts = <44 0 45 0>;
+        };
diff --git a/Documentation/devicetree/bindings/rtc/twl-rtc.txt b/Documentation/devicetree/bindings/rtc/twl-rtc.txt
new file mode 100644
index 00000000000..596e0c97be7
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/twl-rtc.txt
@@ -0,0 +1,12 @@
+* TI twl RTC
+The TWL family (twl4030/6030) contains a RTC.
+Required properties:
+- compatible : Should be twl4030-rtc
+Examples:
+rtc@0 {
+    compatible = "ti,twl4030-rtc";
+};
diff --git a/Documentation/devicetree/bindings/serial/omap_serial.txt b/Documentation/devicetree/bindings/serial/omap_serial.txt
new file mode 100644
index 00000000000..342eedd1005
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/omap_serial.txt
@@ -0,0 +1,10 @@
+OMAP UART controller
+Required properties:
+- compatible : should be "ti,omap2-uart" for OMAP2 controllers
+- compatible : should be "ti,omap3-uart" for OMAP3 controllers
+- compatible : should be "ti,omap4-uart" for OMAP4 controllers
+- ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
+Optional properties:
+- clock-frequency : frequency of the clock input to the UART
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.txt b/Documentation/devicetree/bindings/serial/samsung_uart.txt
new file mode 100644
index 00000000000..2c8a17cf5cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.txt
@@ -0,0 +1,14 @@
+* Samsung's UART Controller
+The Samsung's UART controller is used for interfacing SoC with serial communicaion
+devices.
+Required properties:
+- compatible: should be
+  - "samsung,exynos4210-uart", for UART's compatible with Exynos4210 uart ports.
+- reg: base physical address of the controller and length of memory mapped
+  region.
+- interrupts: interrupt number to the cpu. The interrupt specifier format depends
+  on the interrupt controller parent.
diff --git a/Documentation/devicetree/bindings/sound/tegra-audio-wm8903.txt b/Documentation/devicetree/bindings/sound/tegra-audio-wm8903.txt
new file mode 100644
index 00000000000..d5b0da8bf1d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tegra-audio-wm8903.txt
@@ -0,0 +1,71 @@
+NVIDIA Tegra audio complex
+Required properties:
+- compatible : "nvidia,tegra-audio-wm8903"
+- nvidia,model : The user-visible name of this sound complex.
+- nvidia,audio-routing : A list of the connections between audio components.
+  Each entry is a pair of strings, the first being the connection's sink,
+  the second being the connection's source. Valid names for sources and
+  sinks are the WM8903's pins, and the jacks on the board:
+  WM8903 pins:
+  * IN1L
+  * IN1R
+  * IN2L
+  * IN2R
+  * IN3L
+  * IN3R
+  * DMICDAT
+  * HPOUTL
+  * HPOUTR
+  * LINEOUTL
+  * LINEOUTR
+  * LOP
+  * LON
+  * ROP
+  * RON
+  * MICBIAS
+  Board connectors:
+  * Headphone Jack
+  * Int Spk
+  * Mic Jack
+- nvidia,i2s-controller : The phandle of the Tegra I2S1 controller
+- nvidia,audio-codec : The phandle of the WM8903 audio codec
+Optional properties:
+- nvidia,spkr-en-gpios : The GPIO that enables the speakers
+- nvidia,hp-mute-gpios : The GPIO that mutes the headphones
+- nvidia,hp-det-gpios : The GPIO that detect headphones are plugged in
+- nvidia,int-mic-en-gpios : The GPIO that enables the internal microphone
+- nvidia,ext-mic-en-gpios : The GPIO that enables the external microphone
+Example:
+sound {
+        compatible = "nvidia,tegra-audio-wm8903-harmony",
+                     "nvidia,tegra-audio-wm8903"
+        nvidia,model = "tegra-wm8903-harmony";
+        nvidia,audio-routing =
+                "Headphone Jack", "HPOUTR",
+                "Headphone Jack", "HPOUTL",
+                "Int Spk", "ROP",
+                "Int Spk", "RON",
+                "Int Spk", "LOP",
+                "Int Spk", "LON",
+                "Mic Jack", "MICBIAS",
+                "IN1L", "Mic Jack";
+        nvidia,i2s-controller = <&i2s1>;
+        nvidia,audio-codec = <&wm8903>;
+        nvidia,spkr-en-gpios = <&codec 2 0>;
+        nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
+        nvidia,int-mic-en-gpios = <&gpio 184 0>; /*gpio PX0 */
+        nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
+};
diff --git a/Documentation/devicetree/bindings/sound/tegra20-das.txt b/Documentation/devicetree/bindings/sound/tegra20-das.txt
new file mode 100644
index 00000000000..6de3a7ee4ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tegra20-das.txt
@@ -0,0 +1,12 @@
+NVIDIA Tegra 20 DAS (Digital Audio Switch) controller
+Required properties:
+- compatible : "nvidia,tegra20-das"
+- reg : Should contain DAS registers location and length
+Example:
+das@70000c00 {
+        compatible = "nvidia,tegra20-das";
+        reg = <0x70000c00 0x80>;
+};
diff --git a/Documentation/devicetree/bindings/sound/tegra20-i2s.txt b/Documentation/devicetree/bindings/sound/tegra20-i2s.txt
new file mode 100644
index 00000000000..0df2b5c816e
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/tegra20-i2s.txt
@@ -0,0 +1,17 @@
+NVIDIA Tegra 20 I2S controller
+Required properties:
+- compatible : "nvidia,tegra20-i2s"
+- reg : Should contain I2S registers location and length
+- interrupts : Should contain I2S interrupt
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+  request selector for this I2S controller
+Example:
+i2s@70002800 {
+        compatible = "nvidia,tegra20-i2s";
+        reg = <0x70002800 0x200>;
+        interrupts = < 45 >;
+        nvidia,dma-request-selector = < &apbdma 2 >;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8903.txt b/Documentation/devicetree/bindings/sound/wm8903.txt
new file mode 100644
index 00000000000..f102cbc4269
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8903.txt
@@ -0,0 +1,50 @@
+WM8903 audio CODEC
+This device supports I2C only.
+Required properties:
+  - compatible : "wlf,wm8903"
+  - reg : the I2C address of the device.
+  - gpio-controller : Indicates this device is a GPIO controller.
+  - #gpio-cells : Should be two. The first cell is the pin number and the
+    second cell is used to specify optional parameters (currently unused).
+Optional properties:
+  - interrupts : The interrupt line the codec is connected to.
+  - micdet-cfg : Default register value for R6 (Mic Bias). If absent, the
+    default is 0.
+  - micdet-delay : The debounce delay for microphone detection in mS. If
+    absent, the default is 100.
+  - gpio-cfg : A list of GPIO configuration register values. The list must
+    be 5 entries long. If absent, no configuration of these registers is
+    performed. If any entry has the value 0xffffffff, that GPIO's
+    configuration will not be modified.
+Example:
+codec: wm8903@1a {
+        compatible = "wlf,wm8903";
+        reg = <0x1a>;
+        interrupts = < 347 >;
+        gpio-controller;
+        #gpio-cells = <2>;
+        micdet-cfg = <0>;
+        micdet-delay = <100>;
+        gpio-cfg = <
+                0x0600 /* DMIC_LR, output */
+                0x0680 /* DMIC_DAT, input */
+                0x0000 /* GPIO, output, low */
+                0x0200 /* Interrupt, output */
+                0x01a0 /* BCLK, input, active high */
+        >;
+};
diff --git a/Documentation/devicetree/bindings/sound/wm8994.txt b/Documentation/devicetree/bindings/sound/wm8994.txt
new file mode 100644
index 00000000000..7a7eb1e7bda
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/wm8994.txt
@@ -0,0 +1,18 @@
+WM1811/WM8994/WM8958 audio CODEC
+These devices support both I2C and SPI (configured with pin strapping
+on the board).
+Required properties:
+  - compatible : "wlf,wm1811", "wlf,wm8994", "wlf,wm8958"
+  - reg : the I2C address of the device for I2C, the chip select
+          number for SPI.
+Example:
+codec: wm8994@1a {
+        compatible = "wlf,wm8994";
+        reg = <0x1a>;
+};
diff --git a/Documentation/devicetree/bindings/usb/tegra-usb.txt b/Documentation/devicetree/bindings/usb/tegra-usb.txt
new file mode 100644
index 00000000000..035d63d5646
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/tegra-usb.txt
@@ -0,0 +1,13 @@
+Tegra SOC USB controllers
+The device node for a USB controller that is part of a Tegra
+SOC is as described in the document "Open Firmware Recommended
+Practice : Universal Serial Bus" with the following modifications
+and additions :
+Required properties :
+ - compatible : Should be "nvidia,tegra20-ehci" for USB controllers
+   used in host mode.
+ - phy_type : Should be one of "ulpi" or "utmi".
+ - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
+   activated for the bus to be powered.
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 874921e9780..ecc6a6cd26c 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -8,7 +8,9 @@ amcc	Applied Micro Circuits Corporation (APM, formally AMCC)
 apm     Applied Micro Circuits Corporation (APM)
 arm     ARM Ltd.
 atmel   Atmel Corporation
+cavium  Cavium, Inc.
 chrp    Common Hardware Reference Platform
+cortina Cortina Systems, Inc.
 dallas  Maxim Integrated Products (formerly Dallas Semiconductor)
 denx    Denx Software Engineering
 epson   Seiko Epson Corp.
@@ -32,10 +34,13 @@ powervr	Imagination Technologies
 qcom    Qualcomm, Inc.
 ramtron Ramtron International
 samsung Samsung Semiconductor
+sbs     Smart Battery System
 schindler       Schindler
 sil     Silicon Image
 simtek
 sirf    SiRF Technology, Inc.
+st      STMicroelectronics
 stericsson      ST-Ericsson
 ti      Texas Instruments
+wlf     Wolfson Microelectronics
 xlnx    Xilinx
diff --git a/Documentation/digsig.txt b/Documentation/digsig.txt
new file mode 100644
index 00000000000..3f682889068
--- /dev/null
+++ b/Documentation/digsig.txt
@@ -0,0 +1,96 @@
+Digital Signature Verification API
+CONTENTS
+1. Introduction
+2. API
+3. User-space utilities
+1. Introduction
+Digital signature verification API provides a method to verify digital signature.
+Currently digital signatures are used by the IMA/EVM integrity protection subsystem.
+Digital signature verification is implemented using cut-down kernel port of
+GnuPG multi-precision integers (MPI) library. The kernel port provides
+memory allocation errors handling, has been refactored according to kernel
+coding style, and checkpatch.pl reported errors and warnings have been fixed.
+Public key and signature consist of header and MPIs.
+struct pubkey_hdr {
+        uint8_t         version;        /* key format version */
+        time_t          timestamp;      /* key made, always 0 for now */
+        uint8_t         algo;
+        uint8_t         nmpi;
+        char            mpi[0];
+} __packed;
+struct signature_hdr {
+        uint8_t         version;        /* signature format version */
+        time_t          timestamp;      /* signature made */
+        uint8_t         algo;
+        uint8_t         hash;
+        uint8_t         keyid[8];
+        uint8_t         nmpi;
+        char            mpi[0];
+} __packed;
+keyid equals to SHA1[12-19] over the total key content.
+Signature header is used as an input to generate a signature.
+Such approach insures that key or signature header could not be changed.
+It protects timestamp from been changed and can be used for rollback
+protection.
+2. API
+API currently includes only 1 function:
+        digsig_verify() - digital signature verification with public key
+/**
+ * digsig_verify() - digital signature verification with public key
+ * @keyring:    keyring to search key in
+ * @sig:        digital signature
+ * @sigen:      length of the signature
+ * @data:       data
+ * @datalen:    length of the data
+ * @return:     0 on success, -EINVAL otherwise
+ *
+ * Verifies data integrity against digital signature.
+ * Currently only RSA is supported.
+ * Normally hash of the content is used as a data for this function.
+ *
+ */
+int digsig_verify(struct key *keyring, const char *sig, int siglen,
+                                                const char *data, int datalen);
+3. User-space utilities
+The signing and key management utilities evm-utils provide functionality
+to generate signatures, to load keys into the kernel keyring.
+Keys can be in PEM or converted to the kernel format.
+When the key is added to the kernel keyring, the keyid defines the name
+of the key: 5D2B05FC633EE3E8 in the example bellow.
+Here is example output of the keyctl utility.
+$ keyctl show
+Session Keyring
+       -3 --alswrv      0     0  keyring: _ses
+603976250 --alswrv      0    -1   \_ keyring: _uid.0
+817777377 --alswrv      0     0       \_ user: kmk
+891974900 --alswrv      0     0       \_ encrypted: evm-key
+170323636 --alswrv      0     0       \_ keyring: _module
+548221616 --alswrv      0     0       \_ keyring: _ima
+128198054 --alswrv      0     0       \_ keyring: _evm
+$ keyctl list 128198054
+1 key in keyring:
+620789745: --alswrv     0     0 user: 5D2B05FC633EE3E8
+Dmitry Kasatkin
+06.10.2011
diff --git a/Documentation/dma-buf-sharing.txt b/Documentation/dma-buf-sharing.txt
new file mode 100644
index 00000000000..225f96d88f5
--- /dev/null
+++ b/Documentation/dma-buf-sharing.txt
@@ -0,0 +1,228 @@
+                    DMA Buffer Sharing API Guide
+                    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+                            Sumit Semwal
+                <sumit dot semwal at linaro dot org>
+                 <sumit dot semwal at ti dot com>
+This document serves as a guide to device-driver writers on what is the dma-buf
+buffer sharing API, how to use it for exporting and using shared buffers.
+Any device driver which wishes to be a part of DMA buffer sharing, can do so as
+either the 'exporter' of buffers, or the 'user' of buffers.
+Say a driver A wants to use buffers created by driver B, then we call B as the
+exporter, and A as buffer-user.
+The exporter
+- implements and manages operations[1] for the buffer
+- allows other users to share the buffer by using dma_buf sharing APIs,
+- manages the details of buffer allocation,
+- decides about the actual backing storage where this allocation happens,
+- takes care of any migration of scatterlist - for all (shared) users of this
+   buffer,
+The buffer-user
+- is one of (many) sharing users of the buffer.
+- doesn't need to worry about how the buffer is allocated, or where.
+- needs a mechanism to get access to the scatterlist that makes up this buffer
+   in memory, mapped into its own address space, so it can access the same area
+   of memory.
+*IMPORTANT*: [see https://lkml.org/lkml/2011/12/20/211 for more details]
+For this first version, A buffer shared using the dma_buf sharing API:
+- *may* be exported to user space using "mmap" *ONLY* by exporter, outside of
+   this framework.
+- may be used *ONLY* by importers that do not need CPU access to the buffer.
+The dma_buf buffer sharing API usage contains the following steps:
+1. Exporter announces that it wishes to export a buffer
+2. Userspace gets the file descriptor associated with the exported buffer, and
+   passes it around to potential buffer-users based on use case
+3. Each buffer-user 'connects' itself to the buffer
+4. When needed, buffer-user requests access to the buffer from exporter
+5. When finished with its use, the buffer-user notifies end-of-DMA to exporter
+6. when buffer-user is done using this buffer completely, it 'disconnects'
+   itself from the buffer.
+1. Exporter's announcement of buffer export
+   The buffer exporter announces its wish to export a buffer. In this, it
+   connects its own private buffer data, provides implementation for operations
+   that can be performed on the exported dma_buf, and flags for the file
+   associated with this buffer.
+   Interface:
+      struct dma_buf *dma_buf_export(void *priv, struct dma_buf_ops *ops,
+                                     size_t size, int flags)
+   If this succeeds, dma_buf_export allocates a dma_buf structure, and returns a
+   pointer to the same. It also associates an anonymous file with this buffer,
+   so it can be exported. On failure to allocate the dma_buf object, it returns
+   NULL.
+2. Userspace gets a handle to pass around to potential buffer-users
+   Userspace entity requests for a file-descriptor (fd) which is a handle to the
+   anonymous file associated with the buffer. It can then share the fd with other
+   drivers and/or processes.
+   Interface:
+      int dma_buf_fd(struct dma_buf *dmabuf)
+   This API installs an fd for the anonymous file associated with this buffer;
+   returns either 'fd', or error.
+3. Each buffer-user 'connects' itself to the buffer
+   Each buffer-user now gets a reference to the buffer, using the fd passed to
+   it.
+   Interface:
+      struct dma_buf *dma_buf_get(int fd)
+   This API will return a reference to the dma_buf, and increment refcount for
+   it.
+   After this, the buffer-user needs to attach its device with the buffer, which
+   helps the exporter to know of device buffer constraints.
+   Interface:
+      struct dma_buf_attachment *dma_buf_attach(struct dma_buf *dmabuf,
+                                                struct device *dev)
+   This API returns reference to an attachment structure, which is then used
+   for scatterlist operations. It will optionally call the 'attach' dma_buf
+   operation, if provided by the exporter.
+   The dma-buf sharing framework does the bookkeeping bits related to managing
+   the list of all attachments to a buffer.
+Until this stage, the buffer-exporter has the option to choose not to actually
+allocate the backing storage for this buffer, but wait for the first buffer-user
+to request use of buffer for allocation.
+4. When needed, buffer-user requests access to the buffer
+   Whenever a buffer-user wants to use the buffer for any DMA, it asks for
+   access to the buffer using dma_buf_map_attachment API. At least one attach to
+   the buffer must have happened before map_dma_buf can be called.
+   Interface:
+      struct sg_table * dma_buf_map_attachment(struct dma_buf_attachment *,
+                                         enum dma_data_direction);
+   This is a wrapper to dma_buf->ops->map_dma_buf operation, which hides the
+   "dma_buf->ops->" indirection from the users of this interface.
+   In struct dma_buf_ops, map_dma_buf is defined as
+      struct sg_table * (*map_dma_buf)(struct dma_buf_attachment *,
+                                                enum dma_data_direction);
+   It is one of the buffer operations that must be implemented by the exporter.
+   It should return the sg_table containing scatterlist for this buffer, mapped
+   into caller's address space.
+   If this is being called for the first time, the exporter can now choose to
+   scan through the list of attachments for this buffer, collate the requirements
+   of the attached devices, and choose an appropriate backing storage for the
+   buffer.
+   Based on enum dma_data_direction, it might be possible to have multiple users
+   accessing at the same time (for reading, maybe), or any other kind of sharing
+   that the exporter might wish to make available to buffer-users.
+   map_dma_buf() operation can return -EINTR if it is interrupted by a signal.
+5. When finished, the buffer-user notifies end-of-DMA to exporter
+   Once the DMA for the current buffer-user is over, it signals 'end-of-DMA' to
+   the exporter using the dma_buf_unmap_attachment API.
+   Interface:
+      void dma_buf_unmap_attachment(struct dma_buf_attachment *,
+                                    struct sg_table *);
+   This is a wrapper to dma_buf->ops->unmap_dma_buf() operation, which hides the
+   "dma_buf->ops->" indirection from the users of this interface.
+   In struct dma_buf_ops, unmap_dma_buf is defined as
+      void (*unmap_dma_buf)(struct dma_buf_attachment *, struct sg_table *);
+   unmap_dma_buf signifies the end-of-DMA for the attachment provided. Like
+   map_dma_buf, this API also must be implemented by the exporter.
+6. when buffer-user is done using this buffer, it 'disconnects' itself from the
+   buffer.
+   After the buffer-user has no more interest in using this buffer, it should
+   disconnect itself from the buffer:
+   - it first detaches itself from the buffer.
+   Interface:
+      void dma_buf_detach(struct dma_buf *dmabuf,
+                          struct dma_buf_attachment *dmabuf_attach);
+   This API removes the attachment from the list in dmabuf, and optionally calls
+   dma_buf->ops->detach(), if provided by exporter, for any housekeeping bits.
+   - Then, the buffer-user returns the buffer reference to exporter.
+   Interface:
+     void dma_buf_put(struct dma_buf *dmabuf);
+   This API then reduces the refcount for this buffer.
+   If, as a result of this call, the refcount becomes 0, the 'release' file
+   operation related to this fd is called. It calls the dmabuf->ops->release()
+   operation in turn, and frees the memory allocated for dmabuf when exported.
+NOTES:
+- Importance of attach-detach and {map,unmap}_dma_buf operation pairs
+   The attach-detach calls allow the exporter to figure out backing-storage
+   constraints for the currently-interested devices. This allows preferential
+   allocation, and/or migration of pages across different types of storage
+   available, if possible.
+   Bracketing of DMA access with {map,unmap}_dma_buf operations is essential
+   to allow just-in-time backing of storage, and migration mid-way through a
+   use-case.
+- Migration of backing storage if needed
+   If after
+   - at least one map_dma_buf has happened,
+   - and the backing storage has been allocated for this buffer,
+   another new buffer-user intends to attach itself to this buffer, it might
+   be allowed, if possible for the exporter.
+   In case it is allowed by the exporter:
+    if the new buffer-user has stricter 'backing-storage constraints', and the
+    exporter can handle these constraints, the exporter can just stall on the
+    map_dma_buf until all outstanding access is completed (as signalled by
+    unmap_dma_buf).
+    Once all users have finished accessing and have unmapped this buffer, the
+    exporter could potentially move the buffer to the stricter backing-storage,
+    and then allow further {map,unmap}_dma_buf operations from any buffer-user
+    from the migrated backing-storage.
+   If the exporter cannot fulfil the backing-storage constraints of the new
+   buffer-user device as requested, dma_buf_attach() would return an error to
+   denote non-compatibility of the new buffer-sharing request with the current
+   buffer.
+   If the exporter chooses not to allow an attach() operation once a
+   map_dma_buf() API has been called, it simply returns an error.
+Miscellaneous notes:
+- Any exporters or users of the dma-buf buffer sharing framework must have
+  a 'select DMA_SHARED_BUFFER' in their respective Kconfigs.
+References:
+[1] struct dma_buf_ops in include/linux/dma-buf.h
+[2] All interfaces mentioned above defined in include/linux/dma-buf.h
diff --git a/Documentation/dmaengine.txt b/Documentation/dmaengine.txt
index 94b7e0f96b3..bbe6cb3d185 100644
--- a/Documentation/dmaengine.txt
+++ b/Documentation/dmaengine.txt
@@ -75,6 +75,10 @@ The slave DMA usage consists of following steps:
   slave_sg     - DMA a list of scatter gather buffers from/to a peripheral
   dma_cyclic   - Perform a cyclic DMA operation from/to a peripheral till the
                  operation is explicitly stopped.
+   interleaved_dma - This is common to Slave as well as M2M clients. For slave
+                 address of devices' fifo could be already known to the driver.
+                 Various types of operations could be expressed by setting
+                 appropriate values to the 'dma_interleaved_template' members.
   A non-NULL return of this transfer API represents a "descriptor" for
   the given transaction.
@@ -89,6 +93,10 @@ The slave DMA usage consists of following steps:
                struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
                size_t period_len, enum dma_data_direction direction);
+        struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
+                struct dma_chan *chan, struct dma_interleaved_template *xt,
+                unsigned long flags);
   The peripheral driver is expected to have mapped the scatterlist for
   the DMA operation prior to calling device_prep_slave_sg, and must
   keep the scatterlist mapped until the DMA operation has completed.
diff --git a/Documentation/dontdiff b/Documentation/dontdiff
index dfa6fc6e4b2..0c083c5c2fa 100644
--- a/Documentation/dontdiff
+++ b/Documentation/dontdiff
@@ -66,7 +66,6 @@ GRTAGS
 GSYMS
 GTAGS
 Image
-Kerntypes
 Module.markers
 Module.symvers
 PENDING
diff --git a/Documentation/driver-model/devres.txt b/Documentation/driver-model/devres.txt
index d79aead9418..10c64c8a13d 100644
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -262,6 +262,7 @@ IOMAP
  devm_ioremap()
  devm_ioremap_nocache()
  devm_iounmap()
+  devm_request_and_ioremap() : checks resource, requests region, ioremaps
  pcim_iomap()
  pcim_iounmap()
  pcim_iomap_table()    : array of mapped addresses indexed by BAR
diff --git a/Documentation/fb/api.txt b/Documentation/fb/api.txt
new file mode 100644
index 00000000000..d4ff7de8570
--- /dev/null
+++ b/Documentation/fb/api.txt
@@ -0,0 +1,306 @@
+                        The Frame Buffer Device API
+                        ---------------------------
+Last revised: June 21, 2011
+0. Introduction
+---------------
+This document describes the frame buffer API used by applications to interact
+with frame buffer devices. In-kernel APIs between device drivers and the frame
+buffer core are not described.
+Due to a lack of documentation in the original frame buffer API, drivers
+behaviours differ in subtle (and not so subtle) ways. This document describes
+the recommended API implementation, but applications should be prepared to
+deal with different behaviours.
+1. Capabilities
+---------------
+Device and driver capabilities are reported in the fixed screen information
+capabilities field.
+struct fb_fix_screeninfo {
+        ...
+        __u16 capabilities;             /* see FB_CAP_*                 */
+        ...
+};
+Application should use those capabilities to find out what features they can
+expect from the device and driver.
+- FB_CAP_FOURCC
+The driver supports the four character code (FOURCC) based format setting API.
+When supported, formats are configured using a FOURCC instead of manually
+specifying color components layout.
+2. Types and visuals
+--------------------
+Pixels are stored in memory in hardware-dependent formats. Applications need
+to be aware of the pixel storage format in order to write image data to the
+frame buffer memory in the format expected by the hardware.
+Formats are described by frame buffer types and visuals. Some visuals require
+additional information, which are stored in the variable screen information
+bits_per_pixel, grayscale, red, green, blue and transp fields.
+Visuals describe how color information is encoded and assembled to create
+macropixels. Types describe how macropixels are stored in memory. The following
+types and visuals are supported.
+- FB_TYPE_PACKED_PIXELS
+Macropixels are stored contiguously in a single plane. If the number of bits
+per macropixel is not a multiple of 8, whether macropixels are padded to the
+next multiple of 8 bits or packed together into bytes depends on the visual.
+Padding at end of lines may be present and is then reported through the fixed
+screen information line_length field.
+- FB_TYPE_PLANES
+Macropixels are split across multiple planes. The number of planes is equal to
+the number of bits per macropixel, with plane i'th storing i'th bit from all
+macropixels.
+Planes are located contiguously in memory.
+- FB_TYPE_INTERLEAVED_PLANES
+Macropixels are split across multiple planes. The number of planes is equal to
+the number of bits per macropixel, with plane i'th storing i'th bit from all
+macropixels.
+Planes are interleaved in memory. The interleave factor, defined as the
+distance in bytes between the beginning of two consecutive interleaved blocks
+belonging to different planes, is stored in the fixed screen information
+type_aux field.
+- FB_TYPE_FOURCC
+Macropixels are stored in memory as described by the format FOURCC identifier
+stored in the variable screen information grayscale field.
+- FB_VISUAL_MONO01
+Pixels are black or white and stored on a number of bits (typically one)
+specified by the variable screen information bpp field.
+Black pixels are represented by all bits set to 1 and white pixels by all bits
+set to 0. When the number of bits per pixel is smaller than 8, several pixels
+are packed together in a byte.
+FB_VISUAL_MONO01 is currently used with FB_TYPE_PACKED_PIXELS only.
+- FB_VISUAL_MONO10
+Pixels are black or white and stored on a number of bits (typically one)
+specified by the variable screen information bpp field.
+Black pixels are represented by all bits set to 0 and white pixels by all bits
+set to 1. When the number of bits per pixel is smaller than 8, several pixels
+are packed together in a byte.
+FB_VISUAL_MONO01 is currently used with FB_TYPE_PACKED_PIXELS only.
+- FB_VISUAL_TRUECOLOR
+Pixels are broken into red, green and blue components, and each component
+indexes a read-only lookup table for the corresponding value. Lookup tables
+are device-dependent, and provide linear or non-linear ramps.
+Each component is stored in a macropixel according to the variable screen
+information red, green, blue and transp fields.
+- FB_VISUAL_PSEUDOCOLOR and FB_VISUAL_STATIC_PSEUDOCOLOR
+Pixel values are encoded as indices into a colormap that stores red, green and
+blue components. The colormap is read-only for FB_VISUAL_STATIC_PSEUDOCOLOR
+and read-write for FB_VISUAL_PSEUDOCOLOR.
+Each pixel value is stored in the number of bits reported by the variable
+screen information bits_per_pixel field.
+- FB_VISUAL_DIRECTCOLOR
+Pixels are broken into red, green and blue components, and each component
+indexes a programmable lookup table for the corresponding value.
+Each component is stored in a macropixel according to the variable screen
+information red, green, blue and transp fields.
+- FB_VISUAL_FOURCC
+Pixels are encoded and  interpreted as described by the format FOURCC
+identifier stored in the variable screen information grayscale field.
+3. Screen information
+---------------------
+Screen information are queried by applications using the FBIOGET_FSCREENINFO
+and FBIOGET_VSCREENINFO ioctls. Those ioctls take a pointer to a
+fb_fix_screeninfo and fb_var_screeninfo structure respectively.
+struct fb_fix_screeninfo stores device independent unchangeable information
+about the frame buffer device and the current format. Those information can't
+be directly modified by applications, but can be changed by the driver when an
+application modifies the format.
+struct fb_fix_screeninfo {
+        char id[16];                    /* identification string eg "TT Builtin" */
+        unsigned long smem_start;       /* Start of frame buffer mem */
+                                        /* (physical address) */
+        __u32 smem_len;                 /* Length of frame buffer mem */
+        __u32 type;                     /* see FB_TYPE_*                */
+        __u32 type_aux;                 /* Interleave for interleaved Planes */
+        __u32 visual;                   /* see FB_VISUAL_*              */
+        __u16 xpanstep;                 /* zero if no hardware panning  */
+        __u16 ypanstep;                 /* zero if no hardware panning  */
+        __u16 ywrapstep;                /* zero if no hardware ywrap    */
+        __u32 line_length;              /* length of a line in bytes    */
+        unsigned long mmio_start;       /* Start of Memory Mapped I/O   */
+                                        /* (physical address) */
+        __u32 mmio_len;                 /* Length of Memory Mapped I/O  */
+        __u32 accel;                    /* Indicate to driver which     */
+                                        /*  specific chip/card we have  */
+        __u16 capabilities;             /* see FB_CAP_*                 */
+        __u16 reserved[2];              /* Reserved for future compatibility */
+};
+struct fb_var_screeninfo stores device independent changeable information
+about a frame buffer device, its current format and video mode, as well as
+other miscellaneous parameters.
+struct fb_var_screeninfo {
+        __u32 xres;                     /* visible resolution           */
+        __u32 yres;
+        __u32 xres_virtual;             /* virtual resolution           */
+        __u32 yres_virtual;
+        __u32 xoffset;                  /* offset from virtual to visible */
+        __u32 yoffset;                  /* resolution                   */
+        __u32 bits_per_pixel;           /* guess what                   */
+        __u32 grayscale;                /* 0 = color, 1 = grayscale,    */
+                                        /* >1 = FOURCC                  */
+        struct fb_bitfield red;         /* bitfield in fb mem if true color, */
+        struct fb_bitfield green;       /* else only length is significant */
+        struct fb_bitfield blue;
+        struct fb_bitfield transp;      /* transparency                 */
+        __u32 nonstd;                   /* != 0 Non standard pixel format */
+        __u32 activate;                 /* see FB_ACTIVATE_*            */
+        __u32 height;                   /* height of picture in mm    */
+        __u32 width;                    /* width of picture in mm     */
+        __u32 accel_flags;              /* (OBSOLETE) see fb_info.flags */
+        /* Timing: All values in pixclocks, except pixclock (of course) */
+        __u32 pixclock;                 /* pixel clock in ps (pico seconds) */
+        __u32 left_margin;              /* time from sync to picture    */
+        __u32 right_margin;             /* time from picture to sync    */
+        __u32 upper_margin;             /* time from sync to picture    */
+        __u32 lower_margin;
+        __u32 hsync_len;                /* length of horizontal sync    */
+        __u32 vsync_len;                /* length of vertical sync      */
+        __u32 sync;                     /* see FB_SYNC_*                */
+        __u32 vmode;                    /* see FB_VMODE_*               */
+        __u32 rotate;                   /* angle we rotate counter clockwise */
+        __u32 colorspace;               /* colorspace for FOURCC-based modes */
+        __u32 reserved[4];              /* Reserved for future compatibility */
+};
+To modify variable information, applications call the FBIOPUT_VSCREENINFO
+ioctl with a pointer to a fb_var_screeninfo structure. If the call is
+successful, the driver will update the fixed screen information accordingly.
+Instead of filling the complete fb_var_screeninfo structure manually,
+applications should call the FBIOGET_VSCREENINFO ioctl and modify only the
+fields they care about.
+4. Format configuration
+-----------------------
+Frame buffer devices offer two ways to configure the frame buffer format: the
+legacy API and the FOURCC-based API.
+The legacy API has been the only frame buffer format configuration API for a
+long time and is thus widely used by application. It is the recommended API
+for applications when using RGB and grayscale formats, as well as legacy
+non-standard formats.
+To select a format, applications set the fb_var_screeninfo bits_per_pixel field
+to the desired frame buffer depth. Values up to 8 will usually map to
+monochrome, grayscale or pseudocolor visuals, although this is not required.
+- For grayscale formats, applications set the grayscale field to one. The red,
+  blue, green and transp fields must be set to 0 by applications and ignored by
+  drivers. Drivers must fill the red, blue and green offsets to 0 and lengths
+  to the bits_per_pixel value.
+- For pseudocolor formats, applications set the grayscale field to zero. The
+  red, blue, green and transp fields must be set to 0 by applications and
+  ignored by drivers. Drivers must fill the red, blue and green offsets to 0
+  and lengths to the bits_per_pixel value.
+- For truecolor and directcolor formats, applications set the grayscale field
+  to zero, and the red, blue, green and transp fields to describe the layout of
+  color components in memory.
+struct fb_bitfield {
+        __u32 offset;                   /* beginning of bitfield        */
+        __u32 length;                   /* length of bitfield           */
+        __u32 msb_right;                /* != 0 : Most significant bit is */
+                                        /* right */
+};
+  Pixel values are bits_per_pixel wide and are split in non-overlapping red,
+  green, blue and alpha (transparency) components. Location and size of each
+  component in the pixel value are described by the fb_bitfield offset and
+  length fields. Offset are computed from the right.
+  Pixels are always stored in an integer number of bytes. If the number of
+  bits per pixel is not a multiple of 8, pixel values are padded to the next
+  multiple of 8 bits.
+Upon successful format configuration, drivers update the fb_fix_screeninfo
+type, visual and line_length fields depending on the selected format.
+The FOURCC-based API replaces format descriptions by four character codes
+(FOURCC). FOURCCs are abstract identifiers that uniquely define a format
+without explicitly describing it. This is the only API that supports YUV
+formats. Drivers are also encouraged to implement the FOURCC-based API for RGB
+and grayscale formats.
+Drivers that support the FOURCC-based API report this capability by setting
+the FB_CAP_FOURCC bit in the fb_fix_screeninfo capabilities field.
+FOURCC definitions are located in the linux/videodev2.h header. However, and
+despite starting with the V4L2_PIX_FMT_prefix, they are not restricted to V4L2
+and don't require usage of the V4L2 subsystem. FOURCC documentation is
+available in Documentation/DocBook/v4l/pixfmt.xml.
+To select a format, applications set the grayscale field to the desired FOURCC.
+For YUV formats, they should also select the appropriate colorspace by setting
+the colorspace field to one of the colorspaces listed in linux/videodev2.h and
+documented in Documentation/DocBook/v4l/colorspaces.xml.
+The red, green, blue and transp fields are not used with the FOURCC-based API.
+For forward compatibility reasons applications must zero those fields, and
+drivers must ignore them. Values other than 0 may get a meaning in future
+extensions.
+Upon successful format configuration, drivers update the fb_fix_screeninfo
+type, visual and line_length fields depending on the selected format. The type
+and visual fields are set to FB_TYPE_FOURCC and FB_VISUAL_FOURCC respectively.
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
index fed5a34a727..1bea46a54b1 100644
--- a/Documentation/feature-removal-schedule.txt
+++ b/Documentation/feature-removal-schedule.txt
@@ -85,17 +85,6 @@ Who:	Robin Getz <rgetz@blackfin.uclinux.org> & Matt Mackall <mpm@selenic.com>
 ---------------------------
-What:   Deprecated snapshot ioctls
-When:   2.6.36
-Why:    The ioctls in kernel/power/user.c were marked as deprecated long time
-        ago. Now they notify users about that so that they need to replace
-        their userspace. After some more time, remove them completely.
-Who:    Jiri Slaby <jirislaby@gmail.com>
---------------------------
 What:   The ieee80211_regdom module parameter
 When:   March 2010 / desktop catchup
@@ -263,8 +252,7 @@ Who:	Ravikiran Thirumalai <kiran@scalex86.org>
 What:   Code that is now under CONFIG_WIRELESS_EXT_SYSFS
        (in net/core/net-sysfs.c)
-When:   After the only user (hal) has seen a release with the patches
+When:   3.5
-        for enough time, probably some time in 2010.
 Why:    Over 1K .text/.data size reduction, data is available in other
        ways (ioctls)
 Who:    Johannes Berg <johannes@sipsolutions.net>
@@ -362,15 +350,6 @@ Who: 	anybody or Florian Mickler <florian@mickler.org>
 ----------------------------
-What:   KVM paravirt mmu host support
-When:   January 2011
-Why:    The paravirt mmu host support is slower than non-paravirt mmu, both
-        on newer and older hardware.  It is already not exposed to the guest,
-        and kept only for live migration purposes.
-Who:    Avi Kivity <avi@redhat.com>
----------------------------
 What:   iwlwifi 50XX module parameters
 When:   3.0
 Why:    The "..50" modules parameters were used to configure 5000 series and
@@ -489,6 +468,20 @@ Why:    In 3.0, we can now autodetect internal 3G device and already have
        information log when acer-wmi initial.
 Who:    Lee, Chun-Yi <jlee@novell.com>
+---------------------------
+What:   /sys/devices/platform/_UDC_/udc/_UDC_/is_dualspeed file and
+        is_dualspeed line in /sys/devices/platform/ci13xxx_*/udc/device file.
+When:   3.8
+Why:    The is_dualspeed file is superseded by maximum_speed in the same
+        directory and is_dualspeed line in device file is superseded by
+        max_speed line in the same file.
+        The maximum_speed/max_speed specifies maximum speed supported by UDC.
+        To check if dualspeeed is supported, check if the value is >= 3.
+        Various possible speeds are defined in <linux/usb/ch9.h>.
+Who:    Michal Nazarewicz <mina86@mina86.com>
 ----------------------------
 What:   The XFS nodelaylog mount option
@@ -505,3 +498,15 @@ When:	3.5
 Why:    The iwlagn module has been renamed iwlwifi.  The alias will be around
        for backward compatibility for several cycles and then dropped.
 Who:    Don Fry <donald.h.fry@intel.com>
+----------------------------
+What:   pci_scan_bus_parented()
+When:   3.5
+Why:    The pci_scan_bus_parented() interface creates a new root bus.  The
+        bus is created with default resources (ioport_resource and
+        iomem_resource) that are always wrong, so we rely on arch code to
+        correct them later.  Callers of pci_scan_bus_parented() should
+        convert to using pci_scan_root_bus() so they can supply a list of
+        bus resources when the bus is created.
+Who:    Bjorn Helgaas <bhelgaas@google.com>
diff --git a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking
index d819ba16a0c..4fca82e5276 100644
--- a/Documentation/filesystems/Locking
+++ b/Documentation/filesystems/Locking
@@ -37,15 +37,15 @@ d_manage:	no		no		yes (ref-walk)	maybe
 --------------------------- inode_operations --------------------------- 
 prototypes:
-        int (*create) (struct inode *,struct dentry *,int, struct nameidata *);
+        int (*create) (struct inode *,struct dentry *,umode_t, struct nameidata *);
        struct dentry * (*lookup) (struct inode *,struct dentry *, struct nameid
 ata *);
        int (*link) (struct dentry *,struct inode *,struct dentry *);
        int (*unlink) (struct inode *,struct dentry *);
        int (*symlink) (struct inode *,struct dentry *,const char *);
-        int (*mkdir) (struct inode *,struct dentry *,int);
+        int (*mkdir) (struct inode *,struct dentry *,umode_t);
        int (*rmdir) (struct inode *,struct dentry *);
-        int (*mknod) (struct inode *,struct dentry *,int,dev_t);
+        int (*mknod) (struct inode *,struct dentry *,umode_t,dev_t);
        int (*rename) (struct inode *, struct dentry *,
                        struct inode *, struct dentry *);
        int (*readlink) (struct dentry *, char __user *,int);
@@ -117,7 +117,7 @@ prototypes:
        int (*statfs) (struct dentry *, struct kstatfs *);
        int (*remount_fs) (struct super_block *, int *, char *);
        void (*umount_begin) (struct super_block *);
-        int (*show_options)(struct seq_file *, struct vfsmount *);
+        int (*show_options)(struct seq_file *, struct dentry *);
        ssize_t (*quota_read)(struct super_block *, int, char *, size_t, loff_t);
        ssize_t (*quota_write)(struct super_block *, int, const char *, size_t, loff_t);
        int (*bdev_try_to_free_page)(struct super_block*, struct page*, gfp_t);
diff --git a/Documentation/filesystems/ceph.txt b/Documentation/filesystems/ceph.txt
index 763d8ebbbeb..d6030aa3337 100644
--- a/Documentation/filesystems/ceph.txt
+++ b/Documentation/filesystems/ceph.txt
@@ -119,12 +119,20 @@ Mount Options
        must rely on TCP's error correction to detect data corruption
        in the data payload.
-  noasyncreaddir
+  dcache
-        Disable client's use its local cache to satisfy readdir
+        Use the dcache contents to perform negative lookups and
-        requests.  (This does not change correctness; the client uses
+        readdir when the client has the entire directory contents in
-        cached metadata only when a lease or capability ensures it is
+        its cache.  (This does not change correctness; the client uses
-        valid.)
+        cached metadata only when a lease or capability ensures it is
+        valid.)
+  nodcache
+        Do not use the dcache as above.  This avoids a significant amount of
+        complex code, sacrificing performance without affecting correctness,
+        and is useful for tracking down bugs.
+  noasyncreaddir
+        Do not use the dcache as above for readdir.
 More Information
 ================
diff --git a/Documentation/filesystems/configfs/configfs.txt b/Documentation/filesystems/configfs/configfs.txt
index dd57bb6bb39..b40fec9d3f5 100644
--- a/Documentation/filesystems/configfs/configfs.txt
+++ b/Documentation/filesystems/configfs/configfs.txt
@@ -192,7 +192,7 @@ attribute value uses the store_attribute() method.
        struct configfs_attribute {
                char                    *ca_name;
                struct module           *ca_owner;
-                mode_t                  ca_mode;
+                umode_t                  ca_mode;
        };
 When a config_item wants an attribute to appear as a file in the item's
diff --git a/Documentation/filesystems/debugfs.txt b/Documentation/filesystems/debugfs.txt
index 742cc06e138..6872c91bce3 100644
--- a/Documentation/filesystems/debugfs.txt
+++ b/Documentation/filesystems/debugfs.txt
@@ -35,7 +35,7 @@ described below will work.
 The most general way to create a file within a debugfs directory is with:
-    struct dentry *debugfs_create_file(const char *name, mode_t mode,
+    struct dentry *debugfs_create_file(const char *name, umode_t mode,
                                       struct dentry *parent, void *data,
                                       const struct file_operations *fops);
@@ -53,13 +53,13 @@ actually necessary; the debugfs code provides a number of helper functions
 for simple situations.  Files containing a single integer value can be
 created with any of:
-    struct dentry *debugfs_create_u8(const char *name, mode_t mode,
+    struct dentry *debugfs_create_u8(const char *name, umode_t mode,
                                     struct dentry *parent, u8 *value);
-    struct dentry *debugfs_create_u16(const char *name, mode_t mode,
+    struct dentry *debugfs_create_u16(const char *name, umode_t mode,
                                      struct dentry *parent, u16 *value);
-    struct dentry *debugfs_create_u32(const char *name, mode_t mode,
+    struct dentry *debugfs_create_u32(const char *name, umode_t mode,
                                      struct dentry *parent, u32 *value);
-    struct dentry *debugfs_create_u64(const char *name, mode_t mode,
+    struct dentry *debugfs_create_u64(const char *name, umode_t mode,
                                      struct dentry *parent, u64 *value);
 These files support both reading and writing the given value; if a specific
@@ -67,13 +67,13 @@ file should not be written to, simply set the mode bits accordingly.  The
 values in these files are in decimal; if hexadecimal is more appropriate,
 the following functions can be used instead:
-    struct dentry *debugfs_create_x8(const char *name, mode_t mode,
+    struct dentry *debugfs_create_x8(const char *name, umode_t mode,
                                     struct dentry *parent, u8 *value);
-    struct dentry *debugfs_create_x16(const char *name, mode_t mode,
+    struct dentry *debugfs_create_x16(const char *name, umode_t mode,
                                      struct dentry *parent, u16 *value);
-    struct dentry *debugfs_create_x32(const char *name, mode_t mode,
+    struct dentry *debugfs_create_x32(const char *name, umode_t mode,
                                      struct dentry *parent, u32 *value);
-    struct dentry *debugfs_create_x64(const char *name, mode_t mode,
+    struct dentry *debugfs_create_x64(const char *name, umode_t mode,
                                      struct dentry *parent, u64 *value);
 These functions are useful as long as the developer knows the size of the
@@ -81,7 +81,7 @@ value to be exported.  Some types can have different widths on different
 architectures, though, complicating the situation somewhat.  There is a
 function meant to help out in one special case:
-    struct dentry *debugfs_create_size_t(const char *name, mode_t mode,
+    struct dentry *debugfs_create_size_t(const char *name, umode_t mode,
                                         struct dentry *parent, 
                                         size_t *value);
@@ -90,21 +90,22 @@ a variable of type size_t.
 Boolean values can be placed in debugfs with:
-    struct dentry *debugfs_create_bool(const char *name, mode_t mode,
+    struct dentry *debugfs_create_bool(const char *name, umode_t mode,
                                       struct dentry *parent, u32 *value);
 A read on the resulting file will yield either Y (for non-zero values) or
 N, followed by a newline.  If written to, it will accept either upper- or
 lower-case values, or 1 or 0.  Any other input will be silently ignored.
-Finally, a block of arbitrary binary data can be exported with:
+Another option is exporting a block of arbitrary binary data, with
+this structure and function:
    struct debugfs_blob_wrapper {
        void *data;
        unsigned long size;
    };
-    struct dentry *debugfs_create_blob(const char *name, mode_t mode,
+    struct dentry *debugfs_create_blob(const char *name, umode_t mode,
                                       struct dentry *parent,
                                       struct debugfs_blob_wrapper *blob);
@@ -115,6 +116,35 @@ can be used to export binary information, but there does not appear to be
 any code which does so in the mainline.  Note that all files created with
 debugfs_create_blob() are read-only.
+If you want to dump a block of registers (something that happens quite
+often during development, even if little such code reaches mainline.
+Debugfs offers two functions: one to make a registers-only file, and
+another to insert a register block in the middle of another sequential
+file.
+    struct debugfs_reg32 {
+        char *name;
+        unsigned long offset;
+    };
+    struct debugfs_regset32 {
+        struct debugfs_reg32 *regs;
+        int nregs;
+        void __iomem *base;
+    };
+    struct dentry *debugfs_create_regset32(const char *name, mode_t mode,
+                                     struct dentry *parent,
+                                     struct debugfs_regset32 *regset);
+    int debugfs_print_regs32(struct seq_file *s, struct debugfs_reg32 *regs,
+                         int nregs, void __iomem *base, char *prefix);
+The "base" argument may be 0, but you may want to build the reg32 array
+using __stringify, and a number of register names (macros) are actually
+byte offsets over a base for the register block.
 There are a couple of other directory-oriented helper functions:
    struct dentry *debugfs_rename(struct dentry *old_dir, 
diff --git a/Documentation/filesystems/ext4.txt b/Documentation/filesystems/ext4.txt
index 4917cf24a5e..10ec4639f15 100644
--- a/Documentation/filesystems/ext4.txt
+++ b/Documentation/filesystems/ext4.txt
@@ -581,6 +581,13 @@ Table of Ext4 specific ioctls
                              behaviour may change in the future as it is
                              not necessary and has been done this way only
                              for sake of simplicity.
+ EXT4_IOC_RESIZE_FS           Resize the filesystem to a new size.  The number
+                              of blocks of resized filesystem is passed in via
+                              64 bit integer argument.  The kernel allocates
+                              bitmaps and inode table, the userspace tool thus
+                              just passes the new number of blocks.
 ..............................................................................
 References
diff --git a/Documentation/filesystems/nfs/00-INDEX b/Documentation/filesystems/nfs/00-INDEX
index a57e12411d2..1716874a651 100644
--- a/Documentation/filesystems/nfs/00-INDEX
+++ b/Documentation/filesystems/nfs/00-INDEX
@@ -2,6 +2,8 @@
        - this file (nfs-related documentation).
 Exporting
        - explanation of how to make filesystems exportable.
+fault_injection.txt
+        - information for using fault injection on the server
 knfsd-stats.txt
        - statistics which the NFS server makes available to user space.
 nfs.txt
diff --git a/Documentation/filesystems/nfs/fault_injection.txt b/Documentation/filesystems/nfs/fault_injection.txt
new file mode 100644
index 00000000000..426d166089a
--- /dev/null
+++ b/Documentation/filesystems/nfs/fault_injection.txt
@@ -0,0 +1,69 @@
+Fault Injection
+===============
+Fault injection is a method for forcing errors that may not normally occur, or
+may be difficult to reproduce.  Forcing these errors in a controlled environment
+can help the developer find and fix bugs before their code is shipped in a
+production system.  Injecting an error on the Linux NFS server will allow us to
+observe how the client reacts and if it manages to recover its state correctly.
+NFSD_FAULT_INJECTION must be selected when configuring the kernel to use this
+feature.
+Using Fault Injection
+=====================
+On the client, mount the fault injection server through NFS v4.0+ and do some
+work over NFS (open files, take locks, ...).
+On the server, mount the debugfs filesystem to <debug_dir> and ls
+<debug_dir>/nfsd.  This will show a list of files that will be used for
+injecting faults on the NFS server.  As root, write a number n to the file
+corresponding to the action you want the server to take.  The server will then
+process the first n items it finds.  So if you want to forget 5 locks, echo '5'
+to <debug_dir>/nfsd/forget_locks.  A value of 0 will tell the server to forget
+all corresponding items.  A log message will be created containing the number
+of items forgotten (check dmesg).
+Go back to work on the client and check if the client recovered from the error
+correctly.
+Available Faults
+================
+forget_clients:
+     The NFS server keeps a list of clients that have placed a mount call.  If
+     this list is cleared, the server will have no knowledge of who the client
+     is, forcing the client to reauthenticate with the server.
+forget_openowners:
+     The NFS server keeps a list of what files are currently opened and who
+     they were opened by.  Clearing this list will force the client to reopen
+     its files.
+forget_locks:
+     The NFS server keeps a list of what files are currently locked in the VFS.
+     Clearing this list will force the client to reclaim its locks (files are
+     unlocked through the VFS as they are cleared from this list).
+forget_delegations:
+     A delegation is used to assure the client that a file, or part of a file,
+     has not changed since the delegation was awarded.  Clearing this list will
+     force the client to reaquire its delegation before accessing the file
+     again.
+recall_delegations:
+     Delegations can be recalled by the server when another client attempts to
+     access a file.  This test will notify the client that its delegation has
+     been revoked, forcing the client to reaquire the delegation before using
+     the file again.
+tools/nfs/inject_faults.sh script
+=================================
+This script has been created to ease the fault injection process.  This script
+will detect the mounted debugfs directory and write to the files located there
+based on the arguments passed by the user.  For example, running
+`inject_faults.sh forget_locks 1` as root will instruct the server to forget
+one lock.  Running `inject_faults forget_locks` will instruct the server to
+forgetall locks.
diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt
index 0ec91f03422..a76a26a1db8 100644
--- a/Documentation/filesystems/proc.txt
+++ b/Documentation/filesystems/proc.txt
@@ -41,6 +41,8 @@ Table of Contents
  3.5   /proc/<pid>/mountinfo - Information about mounts
  3.6   /proc/<pid>/comm  & /proc/<pid>/task/<tid>/comm
+  4     Configuring procfs
+  4.1   Mount options
 ------------------------------------------------------------------------------
 Preface
@@ -305,6 +307,9 @@ Table 1-4: Contents of the stat files (as of 2.6.30-rc7)
  blkio_ticks   time spent waiting for block IO
  gtime         guest time of the task in jiffies
  cgtime        guest time of the task children in jiffies
+  start_data    address above which program data+bss is placed
+  end_data      address below which program data+bss is placed
+  start_brk     address above which program heap can be expanded with brk()
 ..............................................................................
 The /proc/PID/maps file containing the currently mapped memory regions and
@@ -1542,3 +1547,40 @@ a task to set its own or one of its thread siblings comm value. The comm value
 is limited in size compared to the cmdline value, so writing anything longer
 then the kernel's TASK_COMM_LEN (currently 16 chars) will result in a truncated
 comm value.
+------------------------------------------------------------------------------
+Configuring procfs
+------------------------------------------------------------------------------
+4.1     Mount options
+---------------------
+The following mount options are supported:
+        hidepid=        Set /proc/<pid>/ access mode.
+        gid=            Set the group authorized to learn processes information.
+hidepid=0 means classic mode - everybody may access all /proc/<pid>/ directories
+(default).
+hidepid=1 means users may not access any /proc/<pid>/ directories but their
+own.  Sensitive files like cmdline, sched*, status are now protected against
+other users.  This makes it impossible to learn whether any user runs
+specific program (given the program doesn't reveal itself by its behaviour).
+As an additional bonus, as /proc/<pid>/cmdline is unaccessible for other users,
+poorly written programs passing sensitive information via program arguments are
+now protected against local eavesdroppers.
+hidepid=2 means hidepid=1 plus all /proc/<pid>/ will be fully invisible to other
+users.  It doesn't mean that it hides a fact whether a process with a specific
+pid value exists (it can be learned by other means, e.g. by "kill -0 $PID"),
+but it hides process' uid and gid, which may be learned by stat()'ing
+/proc/<pid>/ otherwise.  It greatly complicates an intruder's task of gathering
+information about running processes, whether some daemon runs with elevated
+privileges, whether other user runs some sensitive program, whether other users
+run any program at all, etc.
+gid= defines a group authorized to learn processes information otherwise
+prohibited by hidepid=.  If you use some daemon like identd which needs to learn
+information about processes information, just add identd to this group.
diff --git a/Documentation/filesystems/squashfs.txt b/Documentation/filesystems/squashfs.txt
index 7db3ebda5a4..403c090aca3 100644
--- a/Documentation/filesystems/squashfs.txt
+++ b/Documentation/filesystems/squashfs.txt
@@ -93,8 +93,8 @@ byte alignment:
 Compressed data blocks are written to the filesystem as files are read from
 the source directory, and checked for duplicates.  Once all file data has been
-written the completed inode, directory, fragment, export and uid/gid lookup
+written the completed inode, directory, fragment, export, uid/gid lookup and
-tables are written.
+xattr tables are written.
 3.1 Compression options
 -----------------------
@@ -151,7 +151,7 @@ in each metadata block.  Directories are sorted in alphabetical order,
 and at lookup the index is scanned linearly looking for the first filename
 alphabetically larger than the filename being looked up.  At this point the
 location of the metadata block the filename is in has been found.
-The general idea of the index is ensure only one metadata block needs to be
+The general idea of the index is to ensure only one metadata block needs to be
 decompressed to do a lookup irrespective of the length of the directory.
 This scheme has the advantage that it doesn't require extra memory overhead
 and doesn't require much extra storage on disk.
diff --git a/Documentation/filesystems/sysfs.txt b/Documentation/filesystems/sysfs.txt
index 07235caec22..a6619b7064b 100644
--- a/Documentation/filesystems/sysfs.txt
+++ b/Documentation/filesystems/sysfs.txt
@@ -70,7 +70,7 @@ An attribute definition is simply:
 struct attribute {
        char                    * name;
        struct module           *owner;
-        mode_t                  mode;
+        umode_t                 mode;
 };
diff --git a/Documentation/filesystems/vfs.txt b/Documentation/filesystems/vfs.txt
index 43cbd082172..3d9393b845b 100644
--- a/Documentation/filesystems/vfs.txt
+++ b/Documentation/filesystems/vfs.txt
@@ -225,7 +225,7 @@ struct super_operations {
        void (*clear_inode) (struct inode *);
        void (*umount_begin) (struct super_block *);
-        int (*show_options)(struct seq_file *, struct vfsmount *);
+        int (*show_options)(struct seq_file *, struct dentry *);
        ssize_t (*quota_read)(struct super_block *, int, char *, size_t, loff_t);
        ssize_t (*quota_write)(struct super_block *, int, const char *, size_t, loff_t);
@@ -341,14 +341,14 @@ This describes how the VFS can manipulate an inode in your
 filesystem. As of kernel 2.6.22, the following members are defined:
 struct inode_operations {
-        int (*create) (struct inode *,struct dentry *,int, struct nameidata *);
+        int (*create) (struct inode *,struct dentry *, umode_t, struct nameidata *);
        struct dentry * (*lookup) (struct inode *,struct dentry *, struct nameidata *);
        int (*link) (struct dentry *,struct inode *,struct dentry *);
        int (*unlink) (struct inode *,struct dentry *);
        int (*symlink) (struct inode *,struct dentry *,const char *);
-        int (*mkdir) (struct inode *,struct dentry *,int);
+        int (*mkdir) (struct inode *,struct dentry *,umode_t);
        int (*rmdir) (struct inode *,struct dentry *);
-        int (*mknod) (struct inode *,struct dentry *,int,dev_t);
+        int (*mknod) (struct inode *,struct dentry *,umode_t,dev_t);
        int (*rename) (struct inode *, struct dentry *,
                        struct inode *, struct dentry *);
        int (*readlink) (struct dentry *, char __user *,int);
diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87
index 6f496a58673..23b7def21ba 100644
--- a/Documentation/hwmon/it87
+++ b/Documentation/hwmon/it87
@@ -26,6 +26,10 @@ Supported chips:
    Prefix: 'it8721'
    Addresses scanned: from Super I/O config space (8 I/O ports)
    Datasheet: Not publicly available
+  * IT8728F
+    Prefix: 'it8728'
+    Addresses scanned: from Super I/O config space (8 I/O ports)
+    Datasheet: Not publicly available
  * SiS950   [clone of IT8705F]
    Prefix: 'it87'
    Addresses scanned: from Super I/O config space (8 I/O ports)
@@ -71,7 +75,7 @@ Description
 -----------
 This driver implements support for the IT8705F, IT8712F, IT8716F,
-IT8718F, IT8720F, IT8721F, IT8726F, IT8758E and SiS950 chips.
+IT8718F, IT8720F, IT8721F, IT8726F, IT8728F, IT8758E and SiS950 chips.
 These chips are 'Super I/O chips', supporting floppy disks, infrared ports,
 joysticks and other miscellaneous stuff. For hardware monitoring, they
@@ -105,6 +109,9 @@ The IT8726F is just bit enhanced IT8716F with additional hardware
 for AMD power sequencing. Therefore the chip will appear as IT8716F
 to userspace applications.
+The IT8728F is considered compatible with the IT8721F, until a datasheet
+becomes available (hopefully.)
 Temperatures are measured in degrees Celsius. An alarm is triggered once
 when the Overtemperature Shutdown limit is crossed.
@@ -121,8 +128,8 @@ alarm is triggered if the voltage has crossed a programmable minimum or
 maximum limit. Note that minimum in this case always means 'closest to
 zero'; this is important for negative voltage measurements. All voltage
 inputs can measure voltages between 0 and 4.08 volts, with a resolution of
-0.016 volt (except IT8721F/IT8758E: 0.012 volt.) The battery voltage in8 does
+0.016 volt (except IT8721F/IT8758E and IT8728F: 0.012 volt.) The battery
-not have limit registers.
+voltage in8 does not have limit registers.
 On the IT8721F/IT8758E, some voltage inputs are internal and scaled inside
 the chip (in7, in8 and optionally in3). The driver handles this transparently
diff --git a/Documentation/hwmon/lm63 b/Documentation/hwmon/lm63
index b9843eab1af..4d30d209881 100644
--- a/Documentation/hwmon/lm63
+++ b/Documentation/hwmon/lm63
@@ -12,6 +12,11 @@ Supported chips:
    Addresses scanned: I2C 0x18 and 0x4e
    Datasheet: Publicly available at the National Semiconductor website
               http://www.national.com/pf/LM/LM64.html
+  * National Semiconductor LM96163
+    Prefix: 'lm96163'
+    Addresses scanned: I2C 0x4c
+    Datasheet: Publicly available at the National Semiconductor website
+               http://www.national.com/pf/LM/LM96163.html
 Author: Jean Delvare <khali@linux-fr.org>
@@ -49,16 +54,24 @@ value for measuring the speed of the fan. It can measure fan speeds down to
 Note that the pin used for fan monitoring is shared with an alert out
 function. Depending on how the board designer wanted to use the chip, fan
 speed monitoring will or will not be possible. The proper chip configuration
-is left to the BIOS, and the driver will blindly trust it.
+is left to the BIOS, and the driver will blindly trust it. Only the original
+LM63 suffers from this limitation, the LM64 and LM96163 have separate pins
+for fan monitoring and alert out. On the LM64, monitoring is always enabled;
+on the LM96163 it can be disabled.
 A PWM output can be used to control the speed of the fan. The LM63 has two
 PWM modes: manual and automatic. Automatic mode is not fully implemented yet
 (you cannot define your custom PWM/temperature curve), and mode change isn't
 supported either.
-The lm63 driver will not update its values more frequently than every
+The lm63 driver will not update its values more frequently than configured with
-second; reading them more often will do no harm, but will return 'old'
+the update_interval sysfs attribute; reading them more often will do no harm,
-values.
+but will return 'old' values. Values in the automatic fan control lookup table
+(attributes pwm1_auto_*) have their own independent lifetime of 5 seconds.
 The LM64 is effectively an LM63 with GPIO lines. The driver does not
 support these GPIO lines at present.
+The LM96163 is an enhanced version of LM63 with improved temperature accuracy
+and better PWM resolution. For LM96163, the external temperature sensor type is
+configurable as CPU embedded diode(1) or 3904 transistor(2).
diff --git a/Documentation/hwmon/pmbus b/Documentation/hwmon/pmbus
index 15ac911ce51..d28b591753d 100644
--- a/Documentation/hwmon/pmbus
+++ b/Documentation/hwmon/pmbus
@@ -2,9 +2,8 @@ Kernel driver pmbus
 ====================
 Supported chips:
-  * Ericsson BMR45X series
+  * Ericsson BMR453, BMR454
-    DC/DC Converter
+    Prefixes: 'bmr453', 'bmr454'
-    Prefixes: 'bmr450', 'bmr451', 'bmr453', 'bmr454'
    Addresses scanned: -
    Datasheet:
 http://archive.ericsson.net/service/internet/picov/get?DocNo=28701-EN/LZT146395
diff --git a/Documentation/hwmon/sysfs-interface b/Documentation/hwmon/sysfs-interface
index a4aa8f600e0..1f4dd855a29 100644
--- a/Documentation/hwmon/sysfs-interface
+++ b/Documentation/hwmon/sysfs-interface
@@ -304,7 +304,7 @@ value (fastest fan speed) wins.
 temp[1-*]_type  Sensor type selection.
                Integers 1 to 6
                RW
-                1: PII/Celeron Diode
+                1: CPU embedded diode
                2: 3904 transistor
                3: thermal diode
                4: thermistor
diff --git a/Documentation/hwmon/zl6100 b/Documentation/hwmon/zl6100
index 7617798b5c9..51f76a189fe 100644
--- a/Documentation/hwmon/zl6100
+++ b/Documentation/hwmon/zl6100
@@ -6,6 +6,10 @@ Supported chips:
    Prefix: 'zl2004'
    Addresses scanned: -
    Datasheet: http://www.intersil.com/data/fn/fn6847.pdf
+  * Intersil / Zilker Labs ZL2005
+    Prefix: 'zl2005'
+    Addresses scanned: -
+    Datasheet: http://www.intersil.com/data/fn/fn6848.pdf
  * Intersil / Zilker Labs ZL2006
    Prefix: 'zl2006'
    Addresses scanned: -
@@ -30,6 +34,17 @@ Supported chips:
    Prefix: 'zl6105'
    Addresses scanned: -
    Datasheet: http://www.intersil.com/data/fn/fn6906.pdf
+  * Ericsson BMR450, BMR451
+    Prefix: 'bmr450', 'bmr451'
+    Addresses scanned: -
+    Datasheet:
+http://archive.ericsson.net/service/internet/picov/get?DocNo=28701-EN/LZT146401
+  * Ericsson BMR462, BMR463, BMR464
+    Prefixes: 'bmr462', 'bmr463', 'bmr464'
+    Addresses scanned: -
+    Datasheet:
+http://archive.ericsson.net/service/internet/picov/get?DocNo=28701-EN/LZT146256
 Author: Guenter Roeck <guenter.roeck@ericsson.com>
diff --git a/Documentation/input/alps.txt b/Documentation/input/alps.txt
new file mode 100644
index 00000000000..f274c28b510
--- /dev/null
+++ b/Documentation/input/alps.txt
@@ -0,0 +1,188 @@
+ALPS Touchpad Protocol
+----------------------
+Introduction
+------------
+Currently the ALPS touchpad driver supports four protocol versions in use by
+ALPS touchpads, called versions 1, 2, 3, and 4. Information about the various
+protocol versions is contained in the following sections.
+Detection
+---------
+All ALPS touchpads should respond to the "E6 report" command sequence:
+E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
+00-00-64.
+If the E6 report is successful, the touchpad model is identified using the "E7
+report" sequence: E8-E7-E7-E7-E9. The response is the model signature and is
+matched against known models in the alps_model_data_array.
+With protocol versions 3 and 4, the E7 report model signature is always
+73-02-64. To differentiate between these versions, the response from the
+"Enter Command Mode" sequence must be inspected as described below.
+Command Mode
+------------
+Protocol versions 3 and 4 have a command mode that is used to read and write
+one-byte device registers in a 16-bit address space. The command sequence
+EC-EC-EC-E9 places the device in command mode, and the device will respond
+with 88-07 followed by a third byte. This third byte can be used to determine
+whether the devices uses the version 3 or 4 protocol.
+To exit command mode, PSMOUSE_CMD_SETSTREAM (EA) is sent to the touchpad.
+While in command mode, register addresses can be set by first sending a
+specific command, either EC for v3 devices or F5 for v4 devices. Then the
+address is sent one nibble at a time, where each nibble is encoded as a
+command with optional data. This enoding differs slightly between the v3 and
+v4 protocols.
+Once an address has been set, the addressed register can be read by sending
+PSMOUSE_CMD_GETINFO (E9). The first two bytes of the response contains the
+address of the register being read, and the third contains the value of the
+register. Registers are written by writing the value one nibble at a time
+using the same encoding used for addresses.
+Packet Format
+-------------
+In the following tables, the following notation is used.
+ CAPITALS = stick, miniscules = touchpad
+?'s can have different meanings on different models, such as wheel rotation,
+extra buttons, stick buttons on a dualpoint, etc.
+PS/2 packet format
+------------------
+ byte 0:  0    0 YSGN XSGN    1    M    R    L
+ byte 1: X7   X6   X5   X4   X3   X2   X1   X0
+ byte 2: Y7   Y6   Y5   Y4   Y3   Y2   Y1   Y0
+Note that the device never signals overflow condition.
+ALPS Absolute Mode - Protocol Verion 1
+--------------------------------------
+ byte 0:  1    0    0    0    1   x9   x8   x7
+ byte 1:  0   x6   x5   x4   x3   x2   x1   x0
+ byte 2:  0    ?    ?    l    r    ?  fin  ges
+ byte 3:  0    ?    ?    ?    ?   y9   y8   y7
+ byte 4:  0   y6   y5   y4   y3   y2   y1   y0
+ byte 5:  0   z6   z5   z4   z3   z2   z1   z0
+ALPS Absolute Mode - Protocol Version 2
+---------------------------------------
+ byte 0:  1    ?    ?    ?    1    ?    ?    ?
+ byte 1:  0   x6   x5   x4   x3   x2   x1   x0
+ byte 2:  0  x10   x9   x8   x7    ?  fin  ges
+ byte 3:  0   y9   y8   y7    1    M    R    L
+ byte 4:  0   y6   y5   y4   y3   y2   y1   y0
+ byte 5:  0   z6   z5   z4   z3   z2   z1   z0
+Dualpoint device -- interleaved packet format
+---------------------------------------------
+ byte 0:    1    1    0    0    1    1    1    1
+ byte 1:    0   x6   x5   x4   x3   x2   x1   x0
+ byte 2:    0  x10   x9   x8   x7    0  fin  ges
+ byte 3:    0    0 YSGN XSGN    1    1    1    1
+ byte 4:   X7   X6   X5   X4   X3   X2   X1   X0
+ byte 5:   Y7   Y6   Y5   Y4   Y3   Y2   Y1   Y0
+ byte 6:    0   y9   y8   y7    1    m    r    l
+ byte 7:    0   y6   y5   y4   y3   y2   y1   y0
+ byte 8:    0   z6   z5   z4   z3   z2   z1   z0
+ALPS Absolute Mode - Protocol Version 3
+---------------------------------------
+ALPS protocol version 3 has three different packet formats. The first two are
+associated with touchpad events, and the third is associatd with trackstick
+events.
+The first type is the touchpad position packet.
+ byte 0:    1    ?   x1   x0    1    1    1    1
+ byte 1:    0  x10   x9   x8   x7   x6   x5   x4
+ byte 2:    0  y10   y9   y8   y7   y6   y5   y4
+ byte 3:    0    M    R    L    1    m    r    l
+ byte 4:    0   mt   x3   x2   y3   y2   y1   y0
+ byte 5:    0   z6   z5   z4   z3   z2   z1   z0
+Note that for some devices the trackstick buttons are reported in this packet,
+and on others it is reported in the trackstick packets.
+The second packet type contains bitmaps representing the x and y axes. In the
+bitmaps a given bit is set if there is a finger covering that position on the
+given axis. Thus the bitmap packet can be used for low-resolution multi-touch
+data, although finger tracking is not possible.  This packet also encodes the
+number of contacts (f1 and f0 in the table below).
+ byte 0:    1    1   x1   x0    1    1    1    1
+ byte 1:    0   x8   x7   x6   x5   x4   x3   x2
+ byte 2:    0   y7   y6   y5   y4   y3   y2   y1
+ byte 3:    0  y10   y9   y8    1    1    1    1
+ byte 4:    0  x14  x13  x12  x11  x10   x9   y0
+ byte 5:    0    1    ?    ?    ?    ?   f1   f0
+This packet only appears after a position packet with the mt bit set, and
+ususally only appears when there are two or more contacts (although
+ocassionally it's seen with only a single contact).
+The final v3 packet type is the trackstick packet.
+ byte 0:    1    1   x7   y7    1    1    1    1
+ byte 1:    0   x6   x5   x4   x3   x2   x1   x0
+ byte 2:    0   y6   y5   y4   y3   y2   y1   y0
+ byte 3:    0    1    0    0    1    0    0    0
+ byte 4:    0   z4   z3   z2   z1   z0    ?    ?
+ byte 5:    0    0    1    1    1    1    1    1
+ALPS Absolute Mode - Protocol Version 4
+---------------------------------------
+Protocol version 4 has an 8-byte packet format.
+ byte 0:    1    ?   x1   x0    1    1    1    1
+ byte 1:    0  x10   x9   x8   x7   x6   x5   x4
+ byte 2:    0  y10   y9   y8   y7   y6   y5   y4
+ byte 3:    0    1   x3   x2   y3   y2   y1   y0
+ byte 4:    0    ?    ?    ?    1    ?    r    l
+ byte 5:    0   z6   z5   z4   z3   z2   z1   z0
+ byte 6:    bitmap data (described below)
+ byte 7:    bitmap data (described below)
+The last two bytes represent a partial bitmap packet, with 3 full packets
+required to construct a complete bitmap packet.  Once assembled, the 6-byte
+bitmap packet has the following format:
+ byte 0:    0    1   x7   x6   x5   x4   x3   x2
+ byte 1:    0   x1   x0   y4   y3   y2   y1   y0
+ byte 2:    0    0    ?  x14  x13  x12  x11  x10
+ byte 3:    0   x9   x8   y9   y8   y7   y6   y5
+ byte 4:    0    0    0    0    0    0    0    0
+ byte 5:    0    0    0    0    0    0    0  y10
+There are several things worth noting here.
+ 1) In the bitmap data, bit 6 of byte 0 serves as a sync byte to
+    identify the first fragment of a bitmap packet.
+ 2) The bitmaps represent the same data as in the v3 bitmap packets, although
+    the packet layout is different.
+ 3) There doesn't seem to be a count of the contact points anywhere in the v4
+    protocol packets. Deriving a count of contact points must be done by
+    analyzing the bitmaps.
+ 4) There is a 3 to 1 ratio of position packets to bitmap packets. Therefore
+    MT position can only be updated for every third ST position update, and
+    the count of contact points can only be updated every third packet as
+    well.
+So far no v4 devices with tracksticks have been encountered.
diff --git a/Documentation/input/gpio-tilt.txt b/Documentation/input/gpio-tilt.txt
new file mode 100644
index 00000000000..06d60c3ff5e
--- /dev/null
+++ b/Documentation/input/gpio-tilt.txt
@@ -0,0 +1,103 @@
+Driver for tilt-switches connected via GPIOs
+============================================
+Generic driver to read data from tilt switches connected via gpios.
+Orientation can be provided by one or more than one tilt switches,
+i.e. each tilt switch providing one axis, and the number of axes
+is also not limited.
+Data structures:
+----------------
+The array of struct gpio in the gpios field is used to list the gpios
+that represent the current tilt state.
+The array of struct gpio_tilt_axis describes the axes that are reported
+to the input system. The values set therein are used for the
+input_set_abs_params calls needed to init the axes.
+The array of struct gpio_tilt_state maps gpio states to the corresponding
+values to report. The gpio state is represented as a bitfield where the
+bit-index corresponds to the index of the gpio in the struct gpio array.
+In the same manner the values stored in the axes array correspond to
+the elements of the gpio_tilt_axis-array.
+Example:
+--------
+Example configuration for a single TS1003 tilt switch that rotates around
+one axis in 4 steps and emitts the current tilt via two GPIOs.
+static int sg060_tilt_enable(struct device *dev) {
+        /* code to enable the sensors */
+};
+static void sg060_tilt_disable(struct device *dev) {
+        /* code to disable the sensors */
+};
+static struct gpio sg060_tilt_gpios[] = {
+        { SG060_TILT_GPIO_SENSOR1, GPIOF_IN, "tilt_sensor1" },
+        { SG060_TILT_GPIO_SENSOR2, GPIOF_IN, "tilt_sensor2" },
+};
+static struct gpio_tilt_state sg060_tilt_states[] = {
+        {
+                .gpios = (0 << 1) | (0 << 0),
+                .axes = (int[]) {
+                        0,
+                },
+        }, {
+                .gpios = (0 << 1) | (1 << 0),
+                .axes = (int[]) {
+                        1, /* 90 degrees */
+                },
+        }, {
+                .gpios = (1 << 1) | (1 << 0),
+                .axes = (int[]) {
+                        2, /* 180 degrees */
+                },
+        }, {
+                .gpios = (1 << 1) | (0 << 0),
+                .axes = (int[]) {
+                        3, /* 270 degrees */
+                },
+        },
+};
+static struct gpio_tilt_axis sg060_tilt_axes[] = {
+        {
+                .axis = ABS_RY,
+                .min = 0,
+                .max = 3,
+                .fuzz = 0,
+                .flat = 0,
+        },
+};
+static struct gpio_tilt_platform_data sg060_tilt_pdata= {
+        .gpios = sg060_tilt_gpios,
+        .nr_gpios = ARRAY_SIZE(sg060_tilt_gpios),
+        .axes = sg060_tilt_axes,
+        .nr_axes = ARRAY_SIZE(sg060_tilt_axes),
+        .states = sg060_tilt_states,
+        .nr_states = ARRAY_SIZE(sg060_tilt_states),
+        .debounce_interval = 100,
+        .poll_interval = 1000,
+        .enable = sg060_tilt_enable,
+        .disable = sg060_tilt_disable,
+};
+static struct platform_device sg060_device_tilt = {
+        .name = "gpio-tilt-polled",
+        .id = -1,
+        .dev = {
+                .platform_data = &sg060_tilt_pdata,
+        },
+};
diff --git a/Documentation/input/sentelic.txt b/Documentation/input/sentelic.txt
index b2ef125b71f..89251e2a3eb 100644
--- a/Documentation/input/sentelic.txt
+++ b/Documentation/input/sentelic.txt
@@ -1,5 +1,5 @@
-Copyright (C) 2002-2010 Sentelic Corporation.
+Copyright (C) 2002-2011 Sentelic Corporation.
-Last update: Jan-13-2010
+Last update: Dec-07-2011
 ==============================================================================
 * Finger Sensing Pad Intellimouse Mode(scrolling wheel, 4th and 5th buttons)
@@ -140,6 +140,7 @@ BYTE  |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------
 Byte 1: Bit7~Bit6 => 00, Normal data packet
                  => 01, Absolute coordination packet
                  => 10, Notify packet
+                  => 11, Normal data packet with on-pad click
        Bit5 => Valid bit, 0 means that the coordinate is invalid or finger up.
                When both fingers are up, the last two reports have zero valid
                bit.
@@ -164,6 +165,7 @@ BYTE  |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------
 Byte 1: Bit7~Bit6 => 00, Normal data packet
                  => 01, Absolute coordinates packet
                  => 10, Notify packet
+                  => 11, Normal data packet with on-pad click
        Bit5 => Valid bit, 0 means that the coordinate is invalid or finger up.
                When both fingers are up, the last two reports have zero valid
                bit.
@@ -188,6 +190,7 @@ BYTE  |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------
 Byte 1: Bit7~Bit6 => 00, Normal data packet
                  => 01, Absolute coordinates packet
                  => 10, Notify packet
+                  => 11, Normal data packet with on-pad click
        Bit5 => 1
        Bit4 => when in absolute coordinates mode (valid when EN_PKT_GO is 1):
                0: left button is generated by the on-pad command
@@ -205,7 +208,7 @@ Byte 4: Bit7 => scroll right button
        Bit6 => scroll left button
        Bit5 => scroll down button
        Bit4 => scroll up button
-            * Note that if gesture and additional buttoni (Bit4~Bit7)
+            * Note that if gesture and additional button (Bit4~Bit7)
              happen at the same time, the button information will not
              be sent.
        Bit3~Bit0 => Reserved
@@ -227,6 +230,7 @@ BYTE  |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------
 Byte 1: Bit7~Bit6 => 00, Normal data packet
                  => 01, Absolute coordinates packet
                  => 10, Notify packet
+                  => 11, Normal data packet with on-pad click
        Bit5 => Valid bit, 0 means that the coordinate is invalid or finger up.
                When both fingers are up, the last two reports have zero valid
                bit.
@@ -253,6 +257,7 @@ BYTE  |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------
 Byte 1: Bit7~Bit6 => 00, Normal data packet
                  => 01, Absolute coordination packet
                  => 10, Notify packet
+                  => 11, Normal data packet with on-pad click
        Bit5 => Valid bit, 0 means that the coordinate is invalid or finger up.
                When both fingers are up, the last two reports have zero valid
                bit.
@@ -279,8 +284,9 @@ BYTE  |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------
 Byte 1: Bit7~Bit6 => 00, Normal data packet
                  => 01, Absolute coordination packet
                  => 10, Notify packet
+                  => 11, Normal data packet with on-pad click
        Bit5 => 1
-        Bit4 => when in absolute coordinate mode (valid when EN_PKT_GO is 1):
+        Bit4 => when in absolute coordinates mode (valid when EN_PKT_GO is 1):
                0: left button is generated by the on-pad command
                1: left button is generated by the external button
        Bit3 => 1
@@ -307,6 +313,110 @@ Sample sequence of Multi-finger, Multi-coordinate mode:
        abs pkt 2, ..., notify packet (valid bit == 0)
 ==============================================================================
+* Absolute position for STL3888-Cx and STL3888-Dx.
+==============================================================================
+Single Finger, Absolute Coordinate Mode (SFAC)
+   Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
+BYTE  |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
+  1   |0|1|0|P|1|M|R|L|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 |r|l|B|F|X|X|Y|Y|
+      |---------------|     |---------------|    |---------------|    |---------------|
+Byte 1: Bit7~Bit6 => 00, Normal data packet
+                  => 01, Absolute coordinates packet
+                  => 10, Notify packet
+        Bit5 => Coordinate mode(always 0 in SFAC mode):
+                0: single-finger absolute coordinates (SFAC) mode
+                1: multi-finger, multiple coordinates (MFMC) mode
+        Bit4 => 0: The LEFT button is generated by on-pad command (OPC)
+                1: The LEFT button is generated by external button
+                Default is 1 even if the LEFT button is not pressed.
+        Bit3 => Always 1, as specified by PS/2 protocol.
+        Bit2 => Middle Button, 1 is pressed, 0 is not pressed.
+        Bit1 => Right Button, 1 is pressed, 0 is not pressed.
+        Bit0 => Left Button, 1 is pressed, 0 is not pressed.
+Byte 2: X coordinate (xpos[9:2])
+Byte 3: Y coordinate (ypos[9:2])
+Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
+        Bit3~Bit2 => X coordinate (ypos[1:0])
+        Bit4 => 4th mouse button(forward one page)
+        Bit5 => 5th mouse button(backward one page)
+        Bit6 => scroll left button
+        Bit7 => scroll right button
+Multi Finger, Multiple Coordinates Mode (MFMC):
+   Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
+BYTE  |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
+  1   |0|1|1|P|1|F|R|L|  2  |X|X|X|X|X|X|X|X|  3 |Y|Y|Y|Y|Y|Y|Y|Y|  4 |r|l|B|F|X|X|Y|Y|
+      |---------------|     |---------------|    |---------------|    |---------------|
+Byte 1: Bit7~Bit6 => 00, Normal data packet
+                  => 01, Absolute coordination packet
+                  => 10, Notify packet
+        Bit5 => Coordinate mode (always 1 in MFMC mode):
+                0: single-finger absolute coordinates (SFAC) mode
+                1: multi-finger, multiple coordinates (MFMC) mode
+        Bit4 => 0: The LEFT button is generated by on-pad command (OPC)
+                1: The LEFT button is generated by external button
+                Default is 1 even if the LEFT button is not pressed.
+        Bit3 => Always 1, as specified by PS/2 protocol.
+        Bit2 => Finger index, 0 is the first finger, 1 is the second finger.
+                If bit 1 and 0 are all 1 and bit 4 is 0, the middle external
+                button is pressed.
+        Bit1 => Right Button, 1 is pressed, 0 is not pressed.
+        Bit0 => Left Button, 1 is pressed, 0 is not pressed.
+Byte 2: X coordinate (xpos[9:2])
+Byte 3: Y coordinate (ypos[9:2])
+Byte 4: Bit1~Bit0 => Y coordinate (xpos[1:0])
+        Bit3~Bit2 => X coordinate (ypos[1:0])
+        Bit4 => 4th mouse button(forward one page)
+        Bit5 => 5th mouse button(backward one page)
+        Bit6 => scroll left button
+        Bit7 => scroll right button
+  When one of the two fingers is up, the device will output four consecutive
+MFMC#0 report packets with zero X and Y to represent 1st finger is up or
+four consecutive MFMC#1 report packets with zero X and Y to represent that
+the 2nd finger is up.  On the other hand, if both fingers are up, the device
+will output four consecutive single-finger, absolute coordinate(SFAC) packets
+with zero X and Y.
+Notify Packet for STL3888-Cx/Dx
+   Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
+BYTE  |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
+  1   |1|0|0|P|1|M|R|L|  2  |C|C|C|C|C|C|C|C|  3 |0|0|F|F|0|0|0|i|  4 |r|l|u|d|0|0|0|0|
+      |---------------|     |---------------|    |---------------|    |---------------|
+Byte 1: Bit7~Bit6 => 00, Normal data packet
+                  => 01, Absolute coordinates packet
+                  => 10, Notify packet
+        Bit5 => Always 0
+        Bit4 => 0: The LEFT button is generated by on-pad command(OPC)
+                1: The LEFT button is generated by external button
+                Default is 1 even if the LEFT button is not pressed.
+        Bit3 => 1
+        Bit2 => Middle Button, 1 is pressed, 0 is not pressed.
+        Bit1 => Right Button, 1 is pressed, 0 is not pressed.
+        Bit0 => Left Button, 1 is pressed, 0 is not pressed.
+Byte 2: Message type:
+        0xba => gesture information
+        0xc0 => one finger hold-rotating gesture
+Byte 3: The first parameter for the received message:
+        0xba => gesture ID (refer to the 'Gesture ID' section)
+        0xc0 => region ID
+Byte 4: The second parameter for the received message:
+        0xba => N/A
+        0xc0 => finger up/down information
+Sample sequence of Multi-finger, Multi-coordinates mode:
+        notify packet (valid bit == 1), MFMC packet 1 (byte 1, bit 2 == 0),
+        MFMC packet 2 (byte 1, bit 2 == 1), MFMC packet 1, MFMC packet 2,
+        ..., notify packet (valid bit == 0)
+        That is, when the device is in MFMC mode, the host will receive
+        interleaved absolute coordinate packets for each finger.
+==============================================================================
 * FSP Enable/Disable packet
 ==============================================================================
   Bit 7 6 5 4 3 2 1 0       7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0      7 6 5 4 3 2 1 0
@@ -348,9 +458,10 @@ http://www.computer-engineering.org/ps2mouse/
 ==============================================================================
 1. Identify FSP by reading device ID(0x00) and version(0x01) register
-2. Determine number of buttons by reading status2 (0x0b) register
+2a. For FSP version < STL3888 Cx, determine number of buttons by reading
+    the 'test mode status' (0x20) register:
-        buttons = reg[0x0b] & 0x30
+        buttons = reg[0x20] & 0x30
        if buttons == 0x30 or buttons == 0x20:
                # two/four buttons
@@ -365,6 +476,10 @@ http://www.computer-engineering.org/ps2mouse/
                Refer to 'Finger Sensing Pad PS/2 Mouse Intellimouse'
                section A for packet parsing detail
+2b. For FSP version >= STL3888 Cx:
+        Refer to 'Finger Sensing Pad PS/2 Mouse Intellimouse'
+        section A for packet parsing detail (ignore byte 4, bit ~ 7)
 ==============================================================================
 * Programming Sequence for Register Reading/Writing
 ==============================================================================
@@ -374,7 +489,7 @@ Register inversion requirement:
  Following values needed to be inverted(the '~' operator in C) before being
 sent to FSP:
-        0xe9, 0xee, 0xf2 and 0xff.
+        0xe8, 0xe9, 0xee, 0xf2, 0xf3 and 0xff.
 Register swapping requirement:
@@ -415,7 +530,18 @@ Register reading sequence:
        8. send 0xe9(status request) PS/2 command to FSP;
-        9. the response read from FSP should be the requested register value.
+        9. the 4th byte of the response read from FSP should be the
+        requested register value(?? indicates don't care byte):
+                host: 0xe9
+                3888: 0xfa (??) (??) (val)
+        * Note that since the Cx release, the hardware will return 1's
+        complement of the register value at the 3rd byte of status request
+        result:
+                host: 0xe9
+                3888: 0xfa (??) (~val) (val)
 Register writing sequence:
@@ -465,71 +591,194 @@ Register writing sequence:
        9. the register writing sequence is completed.
+        * Note that since the Cx release, the hardware will return 1's
+        complement of the register value at the 3rd byte of status request
+        result. Host can optionally send another 0xe9 (status request) PS/2
+        command to FSP at the end of register writing to verify that the
+        register writing operation is successful (?? indicates don't care
+        byte):
+                host: 0xe9
+                3888: 0xfa (??) (~val) (val)
+==============================================================================
+* Programming Sequence for Page Register Reading/Writing
+==============================================================================
+  In order to overcome the limitation of maximum number of registers
+supported, the hardware separates register into different groups called
+'pages.' Each page is able to include up to 255 registers.
+  The default page after power up is 0x82; therefore, if one has to get
+access to register 0x8301, one has to use following sequence to switch
+to page 0x83, then start reading/writing from/to offset 0x01 by using
+the register read/write sequence described in previous section.
+Page register reading sequence:
+        1. send 0xf3 PS/2 command to FSP;
+        2. send 0x66 PS/2 command to FSP;
+        3. send 0x88 PS/2 command to FSP;
+        4. send 0xf3 PS/2 command to FSP;
+        5. send 0x83 PS/2 command to FSP;
+        6. send 0x88 PS/2 command to FSP;
+        7. send 0xe9(status request) PS/2 command to FSP;
+        8. the response read from FSP should be the requested page value.
+Page register writing sequence:
+        1. send 0xf3 PS/2 command to FSP;
+        2. send 0x38 PS/2 command to FSP;
+        3. send 0x88 PS/2 command to FSP;
+        4. send 0xf3 PS/2 command to FSP;
+        5. if the page address being written is not required to be
+        inverted(refer to the 'Register inversion requirement' section),
+        goto step 6
+        5a. send 0x47 PS/2 command to FSP;
+        5b. send the inverted page address to FSP and goto step 9;
+        6. if the page address being written is not required to be
+        swapped(refer to the 'Register swapping requirement' section),
+        goto step 7
+        6a. send 0x44 PS/2 command to FSP;
+        6b. send the swapped page address to FSP and goto step 9;
+        7. send 0x33 PS/2 command to FSP;
+        8. send the page address to FSP;
+        9. the page register writing sequence is completed.
+==============================================================================
+* Gesture ID
+==============================================================================
+  Unlike other devices which sends multiple fingers' coordinates to host,
+FSP processes multiple fingers' coordinates internally and convert them
+into a 8 bits integer, namely 'Gesture ID.'  Following is a list of
+supported gesture IDs:
+        ID      Description
+        0x86    2 finger straight up
+        0x82    2 finger straight down
+        0x80    2 finger straight right
+        0x84    2 finger straight left
+        0x8f    2 finger zoom in
+        0x8b    2 finger zoom out
+        0xc0    2 finger curve, counter clockwise
+        0xc4    2 finger curve, clockwise
+        0x2e    3 finger straight up
+        0x2a    3 finger straight down
+        0x28    3 finger straight right
+        0x2c    3 finger straight left
+        0x38    palm
 ==============================================================================
 * Register Listing
 ==============================================================================
+  Registers are represented in 16 bits values. The higher 8 bits represent
+the page address and the lower 8 bits represent the relative offset within
+that particular page.  Refer to the 'Programming Sequence for Page Register
+Reading/Writing' section for instructions on how to change current page
+address.
 offset  width           default r/w     name
-0x00    bit7~bit0       0x01    RO      device ID
+0x8200  bit7~bit0       0x01    RO      device ID
-0x01    bit7~bit0       0xc0    RW      version ID
+0x8201  bit7~bit0               RW      version ID
+                                        0xc1: STL3888 Ax
+                                        0xd0 ~ 0xd2: STL3888 Bx
+                                        0xe0 ~ 0xe1: STL3888 Cx
+                                        0xe2 ~ 0xe3: STL3888 Dx
-0x02    bit7~bit0       0x01    RO      vendor ID
+0x8202  bit7~bit0       0x01    RO      vendor ID
-0x03    bit7~bit0       0x01    RO      product ID
+0x8203  bit7~bit0       0x01    RO      product ID
-0x04    bit3~bit0       0x01    RW      revision ID
+0x8204  bit3~bit0       0x01    RW      revision ID
-0x0b                            RO      test mode status 1
+0x820b                                  test mode status 1
-        bit3            1       RO      0: rotate 180 degree, 1: no rotation
+        bit3            1       RO      0: rotate 180 degree
+                                        1: no rotation
+                                        *only supported by H/W prior to Cx
-        bit5~bit4               RO      number of buttons
+0x820f                                  register file page control
-                        11 => 2, lbtn/rbtn
+        bit2            0       RW      1: rotate 180 degree
-                        10 => 4, lbtn/rbtn/scru/scrd
+                                        0: no rotation
-                        01 => 6, lbtn/rbtn/scru/scrd/scrl/scrr
+                                        *supported since Cx
-                        00 => 6, lbtn/rbtn/scru/scrd/fbtn/bbtn
-0x0f                            RW      register file page control
        bit0            0       RW      1 to enable page 1 register files
+                                        *only supported by H/W prior to Cx
-0x10                            RW      system control 1
+0x8210                          RW      system control 1
        bit0            1       RW      Reserved, must be 1
        bit1            0       RW      Reserved, must be 0
-        bit4            1       RW      Reserved, must be 0
+        bit4            0       RW      Reserved, must be 0
-        bit5            0       RW      register clock gating enable
+        bit5            1       RW      register clock gating enable
                                        0: read only, 1: read/write enable
        (Note that following registers does not require clock gating being
        enabled prior to write: 05 06 07 08 09 0c 0f 10 11 12 16 17 18 23 2e
        40 41 42 43.  In addition to that, this bit must be 1 when gesture
        mode is enabled)
-0x31                            RW      on-pad command detection
+0x8220                                  test mode status
+        bit5~bit4               RO      number of buttons
+                                        11 => 2, lbtn/rbtn
+                                        10 => 4, lbtn/rbtn/scru/scrd
+                                        01 => 6, lbtn/rbtn/scru/scrd/scrl/scrr
+                                        00 => 6, lbtn/rbtn/scru/scrd/fbtn/bbtn
+                                        *only supported by H/W prior to Cx
+0x8231                          RW      on-pad command detection
        bit7            0       RW      on-pad command left button down tag
                                        enable
                                        0: disable, 1: enable
+                                        *only supported by H/W prior to Cx
-0x34                            RW      on-pad command control 5
+0x8234                          RW      on-pad command control 5
        bit4~bit0       0x05    RW      XLO in 0s/4/1, so 03h = 0010.1b = 2.5
        (Note that position unit is in 0.5 scanline)
+                                        *only supported by H/W prior to Cx
        bit7            0       RW      on-pad tap zone enable
                                        0: disable, 1: enable
+                                        *only supported by H/W prior to Cx
-0x35                            RW      on-pad command control 6
+0x8235                          RW      on-pad command control 6
        bit4~bit0       0x1d    RW      XHI in 0s/4/1, so 19h = 1100.1b = 12.5
        (Note that position unit is in 0.5 scanline)
+                                        *only supported by H/W prior to Cx
-0x36                            RW      on-pad command control 7
+0x8236                          RW      on-pad command control 7
        bit4~bit0       0x04    RW      YLO in 0s/4/1, so 03h = 0010.1b = 2.5
        (Note that position unit is in 0.5 scanline)
+                                        *only supported by H/W prior to Cx
-0x37                            RW      on-pad command control 8
+0x8237                          RW      on-pad command control 8
        bit4~bit0       0x13    RW      YHI in 0s/4/1, so 11h = 1000.1b = 8.5
        (Note that position unit is in 0.5 scanline)
+                                        *only supported by H/W prior to Cx
-0x40                            RW      system control 5
+0x8240                          RW      system control 5
        bit1            0       RW      FSP Intellimouse mode enable
                                        0: disable, 1: enable
+                                        *only supported by H/W prior to Cx
        bit2            0       RW      movement + abs. coordinate mode enable
                                        0: disable, 1: enable
@@ -537,6 +786,7 @@ offset	width		default	r/w	name
        bit 1 is not set. However, the format is different from that of bit 1.
        In addition, when bit 1 and bit 2 are set at the same time, bit 2 will
        override bit 1.)
+                                        *only supported by H/W prior to Cx
        bit3            0       RW      abs. coordinate only mode enable
                                        0: disable, 1: enable
@@ -544,9 +794,11 @@ offset	width		default	r/w	name
        bit 1 is not set. However, the format is different from that of bit 1.
        In addition, when bit 1, bit 2 and bit 3 are set at the same time,
        bit 3 will override bit 1 and 2.)
+                                        *only supported by H/W prior to Cx
        bit5            0       RW      auto switch enable
                                        0: disable, 1: enable
+                                        *only supported by H/W prior to Cx
        bit6            0       RW      G0 abs. + notify packet format enable
                                        0: disable, 1: enable
@@ -554,18 +806,68 @@ offset	width		default	r/w	name
        bit 2 and 3.  That is, if any of those bit is 1, host will receive
        absolute coordinates; otherwise, host only receives packets with
        relative coordinate.)
+                                        *only supported by H/W prior to Cx
        bit7            0       RW      EN_PS2_F2: PS/2 gesture mode 2nd
                                        finger packet enable
                                        0: disable, 1: enable
+                                        *only supported by H/W prior to Cx
-0x43                            RW      on-pad control
+0x8243                          RW      on-pad control
        bit0            0       RW      on-pad control enable
                                        0: disable, 1: enable
        (Note that if this bit is cleared, bit 3/5 will be ineffective)
+                                        *only supported by H/W prior to Cx
        bit3            0       RW      on-pad fix vertical scrolling enable
                                        0: disable, 1: enable
+                                        *only supported by H/W prior to Cx
        bit5            0       RW      on-pad fix horizontal scrolling enable
                                        0: disable, 1: enable
+                                        *only supported by H/W prior to Cx
+0x8290                          RW      software control register 1
+        bit0            0       RW      absolute coordination mode
+                                        0: disable, 1: enable
+                                        *supported since Cx
+        bit1            0       RW      gesture ID output
+                                        0: disable, 1: enable
+                                        *supported since Cx
+        bit2            0       RW      two fingers' coordinates output
+                                        0: disable, 1: enable
+                                        *supported since Cx
+        bit3            0       RW      finger up one packet output
+                                        0: disable, 1: enable
+                                        *supported since Cx
+        bit4            0       RW      absolute coordination continuous mode
+                                        0: disable, 1: enable
+                                        *supported since Cx
+        bit6~bit5       00      RW      gesture group selection
+                                        00: basic
+                                        01: suite
+                                        10: suite pro
+                                        11: advanced
+                                        *supported since Cx
+        bit7            0       RW      Bx packet output compatible mode
+                                        0: disable, 1: enable                                   *supported since Cx
+                                        *supported since Cx
+0x833d                          RW      on-pad command control 1
+        bit7            1       RW      on-pad command detection enable
+                                        0: disable, 1: enable
+                                        *supported since Cx
+0x833e                          RW      on-pad command detection
+        bit7            0       RW      on-pad command left button down tag
+                                        enable. Works only in H/W based PS/2
+                                        data packet mode.
+                                        0: disable, 1: enable
+                                        *supported since Cx
diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt
index 54078ed96b3..4840334ea97 100644
--- a/Documentation/ioctl/ioctl-number.txt
+++ b/Documentation/ioctl/ioctl-number.txt
@@ -149,6 +149,7 @@ Code  Seq#(hex)	Include File		Comments
 'M'     01-03   drivers/scsi/megaraid/megaraid_sas.h
 'M'     00-0F   drivers/video/fsl-diu-fb.h      conflict!
 'N'     00-1F   drivers/usb/scanner.h
+'N'     40-7F   drivers/block/nvme.c
 'O'     00-06   mtd/ubi-user.h          UBI
 'P'     all     linux/soundcard.h       conflict!
 'P'     60-6F   sound/sscape_ioctl.h    conflict!
diff --git a/Documentation/kbuild/makefiles.txt b/Documentation/kbuild/makefiles.txt
index f47cdefb4d1..ab0a984530d 100644
--- a/Documentation/kbuild/makefiles.txt
+++ b/Documentation/kbuild/makefiles.txt
@@ -33,14 +33,15 @@ This document describes the Linux kernel Makefiles.
        === 6 Architecture Makefiles
           --- 6.1 Set variables to tweak the build to the architecture
-           --- 6.2 Add prerequisites to archprepare:
+           --- 6.2 Add prerequisites to archheaders:
-           --- 6.3 List directories to visit when descending
+           --- 6.3 Add prerequisites to archprepare:
-           --- 6.4 Architecture-specific boot images
+           --- 6.4 List directories to visit when descending
-           --- 6.5 Building non-kbuild targets
+           --- 6.5 Architecture-specific boot images
-           --- 6.6 Commands useful for building a boot image
+           --- 6.6 Building non-kbuild targets
-           --- 6.7 Custom kbuild commands
+           --- 6.7 Commands useful for building a boot image
-           --- 6.8 Preprocessing linker scripts
+           --- 6.8 Custom kbuild commands
-           --- 6.9 Generic header files
+           --- 6.9 Preprocessing linker scripts
+           --- 6.10 Generic header files
        === 7 Kbuild syntax for exported headers
                --- 7.1 header-y
@@ -252,7 +253,7 @@ more details, with real examples.
        This will create a library lib.a based on delay.o. For kbuild to
        actually recognize that there is a lib.a being built, the directory
        shall be listed in libs-y.
-        See also "6.3 List directories to visit when descending".
+        See also "6.4 List directories to visit when descending".
        Use of lib-y is normally restricted to lib/ and arch/*/lib.
@@ -974,7 +975,20 @@ When kbuild executes, the following steps are followed (roughly):
        $(KBUILD_ARFLAGS) set by the top level Makefile to "D" (deterministic
        mode) if this option is supported by $(AR).
--- 6.2 Add prerequisites to archprepare:
+--- 6.2 Add prerequisites to archheaders:
+        The archheaders: rule is used to generate header files that
+        may be installed into user space by "make header_install" or
+        "make headers_install_all".  In order to support
+        "make headers_install_all", this target has to be able to run
+        on an unconfigured tree, or a tree configured for another
+        architecture.
+        It is run before "make archprepare" when run on the
+        architecture itself.
+--- 6.3 Add prerequisites to archprepare:
        The archprepare: rule is used to list prerequisites that need to be
        built before starting to descend down in the subdirectories.
@@ -990,7 +1004,7 @@ When kbuild executes, the following steps are followed (roughly):
        generating offset header files.
--- 6.3 List directories to visit when descending
+--- 6.4 List directories to visit when descending
        An arch Makefile cooperates with the top Makefile to define variables
        which specify how to build the vmlinux file.  Note that there is no
@@ -1019,7 +1033,7 @@ When kbuild executes, the following steps are followed (roughly):
                drivers-$(CONFIG_OPROFILE)  += arch/sparc64/oprofile/
--- 6.4 Architecture-specific boot images
+--- 6.5 Architecture-specific boot images
        An arch Makefile specifies goals that take the vmlinux file, compress
        it, wrap it in bootstrapping code, and copy the resulting files
@@ -1070,7 +1084,7 @@ When kbuild executes, the following steps are followed (roughly):
        When "make" is executed without arguments, bzImage will be built.
--- 6.5 Building non-kbuild targets
+--- 6.6 Building non-kbuild targets
    extra-y
@@ -1090,7 +1104,7 @@ When kbuild executes, the following steps are followed (roughly):
        shall be built, but shall not be linked as part of built-in.o.
--- 6.6 Commands useful for building a boot image
+--- 6.7 Commands useful for building a boot image
        Kbuild provides a few macros that are useful when building a
        boot image.
@@ -1112,7 +1126,7 @@ When kbuild executes, the following steps are followed (roughly):
        always be built.
        Assignments to $(targets) are without $(obj)/ prefix.
        if_changed may be used in conjunction with custom commands as
-        defined in 6.7 "Custom kbuild commands".
+        defined in 6.8 "Custom kbuild commands".
        Note: It is a typical mistake to forget the FORCE prerequisite.
        Another common pitfall is that whitespace is sometimes
@@ -1171,7 +1185,7 @@ When kbuild executes, the following steps are followed (roughly):
                $(obj)/%.dtb: $(src)/%.dts
                        $(call cmd,dtc)
--- 6.7 Custom kbuild commands
+--- 6.8 Custom kbuild commands
        When kbuild is executing with KBUILD_VERBOSE=0, then only a shorthand
        of a command is normally displayed.
@@ -1198,7 +1212,7 @@ When kbuild executes, the following steps are followed (roughly):
        will be displayed with "make KBUILD_VERBOSE=0".
--- 6.8 Preprocessing linker scripts
+--- 6.9 Preprocessing linker scripts
        When the vmlinux image is built, the linker script
        arch/$(ARCH)/kernel/vmlinux.lds is used.
@@ -1228,7 +1242,7 @@ When kbuild executes, the following steps are followed (roughly):
        The kbuild infrastructure for *lds file are used in several
        architecture-specific files.
--- 6.9 Generic header files
+--- 6.10 Generic header files
        The directory include/asm-generic contains the header files
        that may be shared between individual architectures.
diff --git a/Documentation/kdump/kdump.txt b/Documentation/kdump/kdump.txt
index 7a9e0b4b290..506c7390c2b 100644
--- a/Documentation/kdump/kdump.txt
+++ b/Documentation/kdump/kdump.txt
@@ -17,8 +17,8 @@ You can use common commands, such as cp and scp, to copy the
 memory image to a dump file on the local disk, or across the network to
 a remote system.
-Kdump and kexec are currently supported on the x86, x86_64, ppc64 and ia64
+Kdump and kexec are currently supported on the x86, x86_64, ppc64, ia64,
-architectures.
+and s390x architectures.
 When the system kernel boots, it reserves a small section of memory for
 the dump-capture kernel. This ensures that ongoing Direct Memory Access
@@ -34,11 +34,18 @@ Similarly on PPC64 machines first 32KB of physical memory is needed for
 booting regardless of where the kernel is loaded and to support 64K page
 size kexec backs up the first 64KB memory.
+For s390x, when kdump is triggered, the crashkernel region is exchanged
+with the region [0, crashkernel region size] and then the kdump kernel
+runs in [0, crashkernel region size]. Therefore no relocatable kernel is
+needed for s390x.
 All of the necessary information about the system kernel's core image is
 encoded in the ELF format, and stored in a reserved area of memory
 before a crash. The physical address of the start of the ELF header is
 passed to the dump-capture kernel through the elfcorehdr= boot
-parameter.
+parameter. Optionally the size of the ELF header can also be passed
+when using the elfcorehdr=[size[KMG]@]offset[KMG] syntax.
 With the dump-capture kernel, you can access the memory image, or "old
 memory," in two ways:
@@ -291,6 +298,10 @@ Boot into System Kernel
   The region may be automatically placed on ia64, see the
   dump-capture kernel config option notes above.
+   On s390x, typically use "crashkernel=xxM". The value of xx is dependent
+   on the memory consumption of the kdump system. In general this is not
+   dependent on the memory size of the production system.
 Load the Dump-capture Kernel
 ============================
@@ -308,6 +319,8 @@ For ppc64:
        - Use vmlinux
 For ia64:
        - Use vmlinux or vmlinuz.gz
+For s390x:
+        - Use image or bzImage
 If you are using a uncompressed vmlinux image then use following command
@@ -337,6 +350,8 @@ For i386, x86_64 and ia64:
 For ppc64:
        "1 maxcpus=1 noirqdistrib reset_devices"
+For s390x:
+        "1 maxcpus=1 cgroup_disable=memory"
 Notes on loading the dump-capture kernel:
@@ -362,6 +377,20 @@ Notes on loading the dump-capture kernel:
  dump. Hence generally it is useful either to build a UP dump-capture
  kernel or specify maxcpus=1 option while loading dump-capture kernel.
+* For s390x there are two kdump modes: If a ELF header is specified with
+  the elfcorehdr= kernel parameter, it is used by the kdump kernel as it
+  is done on all other architectures. If no elfcorehdr= kernel parameter is
+  specified, the s390x kdump kernel dynamically creates the header. The
+  second mode has the advantage that for CPU and memory hotplug, kdump has
+  not to be reloaded with kexec_load().
+* For s390x systems with many attached devices the "cio_ignore" kernel
+  parameter should be used for the kdump kernel in order to prevent allocation
+  of kernel memory for devices that are not relevant for kdump. The same
+  applies to systems that use SCSI/FCP devices. In that case the
+  "allow_lun_scan" zfcp module parameter should be set to zero before
+  setting FCP devices online.
 Kernel Panic
 ============
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 81c287fad79..b29f3c41629 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -329,6 +329,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                                    is a lot of faster
                        off       - do not initialize any AMD IOMMU found in
                                    the system
+                        force_isolation - Force device isolation for all
+                                          devices. The IOMMU driver is not
+                                          allowed anymore to lift isolation
+                                          requirements as needed. This option
+                                          does not override iommu=pt
        amijoy.map=     [HW,JOY] Amiga joystick support
                        Map of devices attached to JOY0DAT and JOY1DAT
@@ -623,6 +628,25 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
        no_debug_objects
                        [KNL] Disable object debugging
+        debug_guardpage_minorder=
+                        [KNL] When CONFIG_DEBUG_PAGEALLOC is set, this
+                        parameter allows control of the order of pages that will
+                        be intentionally kept free (and hence protected) by the
+                        buddy allocator. Bigger value increase the probability
+                        of catching random memory corruption, but reduce the
+                        amount of memory for normal system use. The maximum
+                        possible value is MAX_ORDER/2.  Setting this parameter
+                        to 1 or 2 should be enough to identify most random
+                        memory corruption problems caused by bugs in kernel or
+                        driver code when a CPU writes to (or reads from) a
+                        random memory location. Note that there exists a class
+                        of memory corruptions problems caused by buggy H/W or
+                        F/W or by drivers badly programing DMA (basically when
+                        memory is written at bus level and the CPU MMU is
+                        bypassed) which are not detectable by
+                        CONFIG_DEBUG_PAGEALLOC, hence this option will not help
+                        tracking down these problems.
        debugpat        [X86] Enable PAT debugging
        decnet.addr=    [HW,NET]
@@ -1059,7 +1083,9 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                nomerge
                forcesac
                soft
-                pt      [x86, IA-64]
+                pt              [x86, IA-64]
+                group_mf        [x86, IA-64]
        io7=            [HW] IO7 for Marvel based alpha systems
                        See comment before marvel_specify_io7 in
@@ -1178,9 +1204,6 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
        kvm.ignore_msrs=[KVM] Ignore guest accesses to unhandled MSRs.
                        Default is 0 (don't ignore, but inject #GP)
-        kvm.oos_shadow= [KVM] Disable out-of-sync shadow paging.
-                        Default is 1 (enabled)
        kvm.mmu_audit=  [KVM] This is a R/W parameter which allows audit
                        KVM MMU at runtime.
                        Default is 0 (off)
@@ -1630,12 +1653,17 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                        The default is to return 64-bit inode numbers.
        nfs.nfs4_disable_idmapping=
-                        [NFSv4] When set, this option disables the NFSv4
+                        [NFSv4] When set to the default of '1', this option
-                        idmapper on the client, but only if the mount
+                        ensures that both the RPC level authentication
-                        is using the 'sec=sys' security flavour. This may
+                        scheme and the NFS level operations agree to use
-                        make migration from legacy NFSv2/v3 systems easier
+                        numeric uids/gids if the mount is using the
-                        provided that the server has the appropriate support.
+                        'sec=sys' security flavour. In effect it is
-                        The default is to always enable NFSv4 idmapping.
+                        disabling idmapping, which can make migration from
+                        legacy NFSv2/v3 systems to NFSv4 easier.
+                        Servers that do not support this mode of operation
+                        will be autodetected by the client, and it will fall
+                        back to using the idmapper.
+                        To turn off this behaviour, set the value to '0'.
        nmi_debug=      [KNL,AVR32,SH] Specify one or more actions to take
                        when a NMI is triggered.
@@ -1796,6 +1824,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
        nomfgpt         [X86-32] Disable Multi-Function General Purpose
                        Timer usage (for AMD Geode machines).
+        nonmi_ipi       [X86] Disable using NMI IPIs during panic/reboot to
+                        shutdown the other cpus.  Instead use the REBOOT_VECTOR
+                        irq.
        nopat           [X86] Disable PAT (page attribute table extension of
                        pagetables) support.
@@ -1885,6 +1917,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                        arch_perfmon: [X86] Force use of architectural
                                perfmon on Intel CPUs instead of the
                                CPU specific event set.
+                        timer: [X86] Force use of architectural NMI
+                                timer mode (see also oprofile.timer
+                                for generic hr timer mode)
+                                [s390] Force legacy basic mode sampling
+                                (report cpu_type "timer")
        oops=panic      Always panic on oopses. Default is to just kill the
                        process, but there is a small probability of
@@ -2362,6 +2399,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
        slram=          [HW,MTD]
+        slab_max_order= [MM, SLAB]
+                        Determines the maximum allowed order for slabs.
+                        A high setting may cause OOMs due to memory
+                        fragmentation.  Defaults to 1 for systems with
+                        more than 32MB of RAM, 0 otherwise.
        slub_debug[=options[,slabs]]    [MM, SLUB]
                        Enabling slub_debug allows one to determine the
                        culprit if slab objects become corrupted. Enabling
@@ -2432,6 +2475,14 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
        stacktrace      [FTRACE]
                        Enabled the stack tracer on boot up.
+        stacktrace_filter=[function-list]
+                        [FTRACE] Limit the functions that the stack tracer
+                        will trace at boot up. function-list is a comma separated
+                        list of functions. This list can be changed at run
+                        time by the stack_trace_filter file in the debugfs
+                        tracing directory. Note, this enables stack tracing
+                        and the stacktrace above is not needed.
        sti=            [PARISC,HW]
                        Format: <num>
                        Set the STI (builtin display/keyboard on the HP-PARISC
@@ -2632,6 +2683,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                        [USB] Start with the old device initialization
                        scheme (default 0 = off).
+        usbcore.usbfs_memory_mb=
+                        [USB] Memory limit (in MB) for buffers allocated by
+                        usbfs (default = 16, 0 = max = 2047).
        usbcore.use_both_schemes=
                        [USB] Try the other device initialization scheme
                        if the first one fails (default 1 = enabled).
@@ -2750,11 +2805,10 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
                        functions are at fixed addresses, they make nice
                        targets for exploits that can control RIP.
-                        emulate     Vsyscalls turn into traps and are emulated
+                        emulate     [default] Vsyscalls turn into traps and are
-                                    reasonably safely.
+                                    emulated reasonably safely.
-                        native      [default] Vsyscalls are native syscall
+                        native      Vsyscalls are native syscall instructions.
-                                    instructions.
                                    This is a little bit faster than trapping
                                    and makes a few dynamic recompilers work
                                    better than they would in emulation mode.
diff --git a/Documentation/kmemleak.txt b/Documentation/kmemleak.txt
index 51063e681ca..b6e39739a36 100644
--- a/Documentation/kmemleak.txt
+++ b/Documentation/kmemleak.txt
@@ -127,7 +127,10 @@ See the include/linux/kmemleak.h header for the functions prototype.
 kmemleak_init            - initialize kmemleak
 kmemleak_alloc           - notify of a memory block allocation
+kmemleak_alloc_percpu    - notify of a percpu memory block allocation
 kmemleak_free            - notify of a memory block freeing
+kmemleak_free_part       - notify of a partial memory block freeing
+kmemleak_free_percpu     - notify of a percpu memory block freeing
 kmemleak_not_leak        - mark an object as not a leak
 kmemleak_ignore          - do not scan or report an object as leak
 kmemleak_scan_area       - add scan areas inside a memory block
diff --git a/Documentation/lockdep-design.txt b/Documentation/lockdep-design.txt
index abf768c681e..5dbc99c04f6 100644
--- a/Documentation/lockdep-design.txt
+++ b/Documentation/lockdep-design.txt
@@ -221,3 +221,66 @@ when the chain is validated for the first time, is then put into a hash
 table, which hash-table can be checked in a lockfree manner. If the
 locking chain occurs again later on, the hash table tells us that we
 dont have to validate the chain again.
+Troubleshooting:
+----------------
+The validator tracks a maximum of MAX_LOCKDEP_KEYS number of lock classes.
+Exceeding this number will trigger the following lockdep warning:
+        (DEBUG_LOCKS_WARN_ON(id >= MAX_LOCKDEP_KEYS))
+By default, MAX_LOCKDEP_KEYS is currently set to 8191, and typical
+desktop systems have less than 1,000 lock classes, so this warning
+normally results from lock-class leakage or failure to properly
+initialize locks.  These two problems are illustrated below:
+1.      Repeated module loading and unloading while running the validator
+        will result in lock-class leakage.  The issue here is that each
+        load of the module will create a new set of lock classes for
+        that module's locks, but module unloading does not remove old
+        classes (see below discussion of reuse of lock classes for why).
+        Therefore, if that module is loaded and unloaded repeatedly,
+        the number of lock classes will eventually reach the maximum.
+2.      Using structures such as arrays that have large numbers of
+        locks that are not explicitly initialized.  For example,
+        a hash table with 8192 buckets where each bucket has its own
+        spinlock_t will consume 8192 lock classes -unless- each spinlock
+        is explicitly initialized at runtime, for example, using the
+        run-time spin_lock_init() as opposed to compile-time initializers
+        such as __SPIN_LOCK_UNLOCKED().  Failure to properly initialize
+        the per-bucket spinlocks would guarantee lock-class overflow.
+        In contrast, a loop that called spin_lock_init() on each lock
+        would place all 8192 locks into a single lock class.
+        The moral of this story is that you should always explicitly
+        initialize your locks.
+One might argue that the validator should be modified to allow
+lock classes to be reused.  However, if you are tempted to make this
+argument, first review the code and think through the changes that would
+be required, keeping in mind that the lock classes to be removed are
+likely to be linked into the lock-dependency graph.  This turns out to
+be harder to do than to say.
+Of course, if you do run out of lock classes, the next thing to do is
+to find the offending lock classes.  First, the following command gives
+you the number of lock classes currently in use along with the maximum:
+        grep "lock-classes" /proc/lockdep_stats
+This command produces the following output on a modest system:
+         lock-classes:                          748 [max: 8191]
+If the number allocated (748 above) increases continually over time,
+then there is likely a leak.  The following command can be used to
+identify the leaking lock classes:
+        grep "BD" /proc/lockdep
+Run the command and save the output, then compare against the output from
+a later run of this command to identify the leakers.  This same output
+can also help you find situations where runtime lock initialization has
+been omitted.
diff --git a/Documentation/md.txt b/Documentation/md.txt
index fc94770f44a..993fba37b7d 100644
--- a/Documentation/md.txt
+++ b/Documentation/md.txt
@@ -357,14 +357,14 @@ Each directory contains:
        written to, that device.
      state
-        A file recording the current state of the device in the array
+        A file recording the current state of the device in the array
        which can be a comma separated list of
              faulty   - device has been kicked from active use due to
-                         a detected fault or it has unacknowledged bad
+                         a detected fault, or it has unacknowledged bad
-                         blocks
+                         blocks
              in_sync  - device is a fully in-sync member of the array
              writemostly - device will only be subject to read
-                         requests if there are no other options.
+                         requests if there are no other options.
                         This applies only to raid1 arrays.
              blocked  - device has failed, and the failure hasn't been
                         acknowledged yet by the metadata handler.
@@ -374,6 +374,13 @@ Each directory contains:
                         This includes spares that are in the process
                         of being recovered to
              write_error - device has ever seen a write error.
+              want_replacement - device is (mostly) working but probably
+                         should be replaced, either due to errors or
+                         due to user request.
+              replacement - device is a replacement for another active
+                         device with same raid_disk.
        This list may grow in future.
        This can be written to.
        Writing "faulty"  simulates a failure on the device.
@@ -386,6 +393,13 @@ Each directory contains:
        Writing "in_sync" sets the in_sync flag.
        Writing "write_error" sets writeerrorseen flag.
        Writing "-write_error" clears writeerrorseen flag.
+        Writing "want_replacement" is allowed at any time except to a
+                replacement device or a spare.  It sets the flag.
+        Writing "-want_replacement" is allowed at any time.  It clears
+                the flag.
+        Writing "replacement" or "-replacement" is only allowed before
+                starting the array.  It sets or clears the flag.
        This file responds to select/poll. Any change to 'faulty'
        or 'blocked' causes an event.
diff --git a/Documentation/mmc/mmc-dev-attrs.txt b/Documentation/mmc/mmc-dev-attrs.txt
index 8898a95b41e..22ae8441489 100644
--- a/Documentation/mmc/mmc-dev-attrs.txt
+++ b/Documentation/mmc/mmc-dev-attrs.txt
@@ -64,3 +64,13 @@ Note on Erase Size and Preferred Erase Size:
        size specified by the card.
        "preferred_erase_size" is in bytes.
+SD/MMC/SDIO Clock Gating Attribute
+==================================
+Read and write access is provided to following attribute.
+This attribute appears only if CONFIG_MMC_CLKGATE is enabled.
+        clkgate_delay   Tune the clock gating delay with desired value in milliseconds.
+echo <desired delay> > /sys/class/mmc_host/mmcX/clkgate_delay
diff --git a/Documentation/mmc/mmc-dev-parts.txt b/Documentation/mmc/mmc-dev-parts.txt
index 2db28b8e662..f08d078d43c 100644
--- a/Documentation/mmc/mmc-dev-parts.txt
+++ b/Documentation/mmc/mmc-dev-parts.txt
@@ -25,3 +25,16 @@ echo 0 > /sys/block/mmcblkXbootY/force_ro
 To re-enable read-only access:
 echo 1 > /sys/block/mmcblkXbootY/force_ro
+The boot partitions can also be locked read only until the next power on,
+with:
+echo 1 > /sys/block/mmcblkXbootY/ro_lock_until_next_power_on
+This is a feature of the card and not of the kernel. If the card does
+not support boot partition locking, the file will not exist. If the
+feature has been disabled on the card, the file will be read-only.
+The boot partitions can also be locked permanently, but this feature is
+not accessible through sysfs in order to avoid accidental or malicious
+bricking.
diff --git a/Documentation/networking/00-INDEX b/Documentation/networking/00-INDEX
index bbce1215434..9ad9ddeb384 100644
--- a/Documentation/networking/00-INDEX
+++ b/Documentation/networking/00-INDEX
@@ -144,6 +144,8 @@ nfc.txt
        - The Linux Near Field Communication (NFS) subsystem.
 olympic.txt
        - IBM PCI Pit/Pit-Phy/Olympic Token Ring driver info.
+openvswitch.txt
+        - Open vSwitch developer documentation.
 operstates.txt
        - Overview of network interface operational states.
 packet_mmap.txt
diff --git a/Documentation/networking/batman-adv.txt b/Documentation/networking/batman-adv.txt
index c86d03f18a5..221ad0cdf11 100644
--- a/Documentation/networking/batman-adv.txt
+++ b/Documentation/networking/batman-adv.txt
@@ -200,15 +200,16 @@ abled  during run time. Following log_levels are defined:
 0 - All  debug  output  disabled
 1 - Enable messages related to routing / flooding / broadcasting
-2 - Enable route or tt entry added / changed / deleted
+2 - Enable messages related to route added / changed / deleted
-3 - Enable all messages
+4 - Enable messages related to translation table operations
+7 - Enable all messages
 The debug output can be changed at runtime  using  the  file
 /sys/class/net/bat0/mesh/log_level. e.g.
 # echo 2 > /sys/class/net/bat0/mesh/log_level
-will enable debug messages for when routes or TTs change.
+will enable debug messages for when routes change.
 BATCTL
diff --git a/Documentation/networking/bonding.txt b/Documentation/networking/bonding.txt
index 91df678fb7f..080ad26690a 100644
--- a/Documentation/networking/bonding.txt
+++ b/Documentation/networking/bonding.txt
@@ -196,6 +196,23 @@ or, for backwards compatibility, the option value.  E.g.,
        The parameters are as follows:
+active_slave
+        Specifies the new active slave for modes that support it
+        (active-backup, balance-alb and balance-tlb).  Possible values
+        are the name of any currently enslaved interface, or an empty
+        string.  If a name is given, the slave and its link must be up in order
+        to be selected as the new active slave.  If an empty string is
+        specified, the current active slave is cleared, and a new active
+        slave is selected automatically.
+        Note that this is only available through the sysfs interface. No module
+        parameter by this name exists.
+        The normal value of this option is the name of the currently
+        active slave, or the empty string if there is no active slave or
+        the current mode does not use an active slave.
 ad_select
        Specifies the 802.3ad aggregation selection logic to use.  The
diff --git a/Documentation/networking/ieee802154.txt b/Documentation/networking/ieee802154.txt
index f41ea240522..1dc1c24a754 100644
--- a/Documentation/networking/ieee802154.txt
+++ b/Documentation/networking/ieee802154.txt
@@ -78,3 +78,30 @@ in software. This is currently WIP.
 See header include/net/mac802154.h and several drivers in drivers/ieee802154/.
+6LoWPAN Linux implementation
+============================
+The IEEE 802.15.4 standard specifies an MTU of 128 bytes, yielding about 80
+octets of actual MAC payload once security is turned on, on a wireless link
+with a link throughput of 250 kbps or less.  The 6LoWPAN adaptation format
+[RFC4944] was specified to carry IPv6 datagrams over such constrained links,
+taking into account limited bandwidth, memory, or energy resources that are
+expected in applications such as wireless Sensor Networks.  [RFC4944] defines
+a Mesh Addressing header to support sub-IP forwarding, a Fragmentation header
+to support the IPv6 minimum MTU requirement [RFC2460], and stateless header
+compression for IPv6 datagrams (LOWPAN_HC1 and LOWPAN_HC2) to reduce the
+relatively large IPv6 and UDP headers down to (in the best case) several bytes.
+In Semptember 2011 the standard update was published - [RFC6282].
+It deprecates HC1 and HC2 compression and defines IPHC encoding format which is
+used in this Linux implementation.
+All the code related to 6lowpan you may find in files: net/ieee802154/6lowpan.*
+To setup 6lowpan interface you need (busybox release > 1.17.0):
+1. Add IEEE802.15.4 interface and initialize PANid;
+2. Add 6lowpan interface by command like:
+   # ip link add link wpan0 name lowpan0 type lowpan
+3. Set MAC (if needs):
+   # ip link set lowpan0 address de:ad:be:ef:ca:fe:ba:be
+4. Bring up 'lowpan0' interface
diff --git a/Documentation/networking/ifenslave.c b/Documentation/networking/ifenslave.c
index 65968fbf1e4..ac5debb2f16 100644
--- a/Documentation/networking/ifenslave.c
+++ b/Documentation/networking/ifenslave.c
@@ -539,12 +539,14 @@ static int if_getconfig(char *ifname)
                metric = 0;
        } else
                metric = ifr.ifr_metric;
+        printf("The result of SIOCGIFMETRIC is %d\n", metric);
        strcpy(ifr.ifr_name, ifname);
        if (ioctl(skfd, SIOCGIFMTU, &ifr) < 0)
                mtu = 0;
        else
                mtu = ifr.ifr_mtu;
+        printf("The result of SIOCGIFMTU is %d\n", mtu);
        strcpy(ifr.ifr_name, ifname);
        if (ioctl(skfd, SIOCGIFDSTADDR, &ifr) < 0) {
diff --git a/Documentation/networking/ip-sysctl.txt b/Documentation/networking/ip-sysctl.txt
index 589f2da5d54..ad3e80e17b4 100644
--- a/Documentation/networking/ip-sysctl.txt
+++ b/Documentation/networking/ip-sysctl.txt
@@ -31,6 +31,16 @@ neigh/default/gc_thresh3 - INTEGER
        when using large numbers of interfaces and when communicating
        with large numbers of directly-connected peers.
+neigh/default/unres_qlen_bytes - INTEGER
+        The maximum number of bytes which may be used by packets
+        queued for each unresolved address by other network layers.
+        (added in linux 3.3)
+neigh/default/unres_qlen - INTEGER
+        The maximum number of packets which may be queued for each
+        unresolved address by other network layers.
+        (deprecated in linux 3.3) : use unres_qlen_bytes instead.
 mtu_expires - INTEGER
        Time, in seconds, that cached PMTU information is kept.
@@ -165,6 +175,9 @@ tcp_congestion_control - STRING
        connections. The algorithm "reno" is always available, but
        additional choices may be available based on kernel configuration.
        Default is set as part of kernel configuration.
+        For passive connections, the listener congestion control choice
+        is inherited.
+        [see setsockopt(listenfd, SOL_TCP, TCP_CONGESTION, "name" ...) ]
 tcp_cookie_size - INTEGER
        Default size of TCP Cookie Transactions (TCPCT) option, that may be
diff --git a/Documentation/networking/openvswitch.txt b/Documentation/networking/openvswitch.txt
new file mode 100644
index 00000000000..b8a048b8df3
--- /dev/null
+++ b/Documentation/networking/openvswitch.txt
@@ -0,0 +1,195 @@
+Open vSwitch datapath developer documentation
+=============================================
+The Open vSwitch kernel module allows flexible userspace control over
+flow-level packet processing on selected network devices.  It can be
+used to implement a plain Ethernet switch, network device bonding,
+VLAN processing, network access control, flow-based network control,
+and so on.
+The kernel module implements multiple "datapaths" (analogous to
+bridges), each of which can have multiple "vports" (analogous to ports
+within a bridge).  Each datapath also has associated with it a "flow
+table" that userspace populates with "flows" that map from keys based
+on packet headers and metadata to sets of actions.  The most common
+action forwards the packet to another vport; other actions are also
+implemented.
+When a packet arrives on a vport, the kernel module processes it by
+extracting its flow key and looking it up in the flow table.  If there
+is a matching flow, it executes the associated actions.  If there is
+no match, it queues the packet to userspace for processing (as part of
+its processing, userspace will likely set up a flow to handle further
+packets of the same type entirely in-kernel).
+Flow key compatibility
+----------------------
+Network protocols evolve over time.  New protocols become important
+and existing protocols lose their prominence.  For the Open vSwitch
+kernel module to remain relevant, it must be possible for newer
+versions to parse additional protocols as part of the flow key.  It
+might even be desirable, someday, to drop support for parsing
+protocols that have become obsolete.  Therefore, the Netlink interface
+to Open vSwitch is designed to allow carefully written userspace
+applications to work with any version of the flow key, past or future.
+To support this forward and backward compatibility, whenever the
+kernel module passes a packet to userspace, it also passes along the
+flow key that it parsed from the packet.  Userspace then extracts its
+own notion of a flow key from the packet and compares it against the
+kernel-provided version:
+    - If userspace's notion of the flow key for the packet matches the
+      kernel's, then nothing special is necessary.
+    - If the kernel's flow key includes more fields than the userspace
+      version of the flow key, for example if the kernel decoded IPv6
+      headers but userspace stopped at the Ethernet type (because it
+      does not understand IPv6), then again nothing special is
+      necessary.  Userspace can still set up a flow in the usual way,
+      as long as it uses the kernel-provided flow key to do it.
+    - If the userspace flow key includes more fields than the
+      kernel's, for example if userspace decoded an IPv6 header but
+      the kernel stopped at the Ethernet type, then userspace can
+      forward the packet manually, without setting up a flow in the
+      kernel.  This case is bad for performance because every packet
+      that the kernel considers part of the flow must go to userspace,
+      but the forwarding behavior is correct.  (If userspace can
+      determine that the values of the extra fields would not affect
+      forwarding behavior, then it could set up a flow anyway.)
+How flow keys evolve over time is important to making this work, so
+the following sections go into detail.
+Flow key format
+---------------
+A flow key is passed over a Netlink socket as a sequence of Netlink
+attributes.  Some attributes represent packet metadata, defined as any
+information about a packet that cannot be extracted from the packet
+itself, e.g. the vport on which the packet was received.  Most
+attributes, however, are extracted from headers within the packet,
+e.g. source and destination addresses from Ethernet, IP, or TCP
+headers.
+The <linux/openvswitch.h> header file defines the exact format of the
+flow key attributes.  For informal explanatory purposes here, we write
+them as comma-separated strings, with parentheses indicating arguments
+and nesting.  For example, the following could represent a flow key
+corresponding to a TCP packet that arrived on vport 1:
+    in_port(1), eth(src=e0:91:f5:21:d0:b2, dst=00:02:e3:0f:80:a4),
+    eth_type(0x0800), ipv4(src=172.16.0.20, dst=172.18.0.52, proto=17, tos=0,
+    frag=no), tcp(src=49163, dst=80)
+Often we ellipsize arguments not important to the discussion, e.g.:
+    in_port(1), eth(...), eth_type(0x0800), ipv4(...), tcp(...)
+Basic rule for evolving flow keys
+---------------------------------
+Some care is needed to really maintain forward and backward
+compatibility for applications that follow the rules listed under
+"Flow key compatibility" above.
+The basic rule is obvious:
+    ------------------------------------------------------------------
+    New network protocol support must only supplement existing flow
+    key attributes.  It must not change the meaning of already defined
+    flow key attributes.
+    ------------------------------------------------------------------
+This rule does have less-obvious consequences so it is worth working
+through a few examples.  Suppose, for example, that the kernel module
+did not already implement VLAN parsing.  Instead, it just interpreted
+the 802.1Q TPID (0x8100) as the Ethertype then stopped parsing the
+packet.  The flow key for any packet with an 802.1Q header would look
+essentially like this, ignoring metadata:
+    eth(...), eth_type(0x8100)
+Naively, to add VLAN support, it makes sense to add a new "vlan" flow
+key attribute to contain the VLAN tag, then continue to decode the
+encapsulated headers beyond the VLAN tag using the existing field
+definitions.  With this change, an TCP packet in VLAN 10 would have a
+flow key much like this:
+    eth(...), vlan(vid=10, pcp=0), eth_type(0x0800), ip(proto=6, ...), tcp(...)
+But this change would negatively affect a userspace application that
+has not been updated to understand the new "vlan" flow key attribute.
+The application could, following the flow compatibility rules above,
+ignore the "vlan" attribute that it does not understand and therefore
+assume that the flow contained IP packets.  This is a bad assumption
+(the flow only contains IP packets if one parses and skips over the
+802.1Q header) and it could cause the application's behavior to change
+across kernel versions even though it follows the compatibility rules.
+The solution is to use a set of nested attributes.  This is, for
+example, why 802.1Q support uses nested attributes.  A TCP packet in
+VLAN 10 is actually expressed as:
+    eth(...), eth_type(0x8100), vlan(vid=10, pcp=0), encap(eth_type(0x0800),
+    ip(proto=6, ...), tcp(...)))
+Notice how the "eth_type", "ip", and "tcp" flow key attributes are
+nested inside the "encap" attribute.  Thus, an application that does
+not understand the "vlan" key will not see either of those attributes
+and therefore will not misinterpret them.  (Also, the outer eth_type
+is still 0x8100, not changed to 0x0800.)
+Handling malformed packets
+--------------------------
+Don't drop packets in the kernel for malformed protocol headers, bad
+checksums, etc.  This would prevent userspace from implementing a
+simple Ethernet switch that forwards every packet.
+Instead, in such a case, include an attribute with "empty" content.
+It doesn't matter if the empty content could be valid protocol values,
+as long as those values are rarely seen in practice, because userspace
+can always forward all packets with those values to userspace and
+handle them individually.
+For example, consider a packet that contains an IP header that
+indicates protocol 6 for TCP, but which is truncated just after the IP
+header, so that the TCP header is missing.  The flow key for this
+packet would include a tcp attribute with all-zero src and dst, like
+this:
+    eth(...), eth_type(0x0800), ip(proto=6, ...), tcp(src=0, dst=0)
+As another example, consider a packet with an Ethernet type of 0x8100,
+indicating that a VLAN TCI should follow, but which is truncated just
+after the Ethernet type.  The flow key for this packet would include
+an all-zero-bits vlan and an empty encap attribute, like this:
+    eth(...), eth_type(0x8100), vlan(0), encap()
+Unlike a TCP packet with source and destination ports 0, an
+all-zero-bits VLAN TCI is not that rare, so the CFI bit (aka
+VLAN_TAG_PRESENT inside the kernel) is ordinarily set in a vlan
+attribute expressly to allow this situation to be distinguished.
+Thus, the flow key in this second example unambiguously indicates a
+missing or malformed VLAN TCI.
+Other rules
+-----------
+The other rules for flow keys are much less subtle:
+    - Duplicate attributes are not allowed at a given nesting level.
+    - Ordering of attributes is not significant.
+    - When the kernel sends a given flow key to userspace, it always
+      composes it the same way.  This allows userspace to hash and
+      compare entire flow keys that it may not be able to fully
+      interpret.
diff --git a/Documentation/networking/packet_mmap.txt b/Documentation/networking/packet_mmap.txt
index 4acea660372..1c08a4b0981 100644
--- a/Documentation/networking/packet_mmap.txt
+++ b/Documentation/networking/packet_mmap.txt
@@ -155,7 +155,7 @@ As capture, each frame contains two parts:
 /* fill sockaddr_ll struct to prepare binding */
 my_addr.sll_family = AF_PACKET;
- my_addr.sll_protocol = ETH_P_ALL;
+ my_addr.sll_protocol = htons(ETH_P_ALL);
 my_addr.sll_ifindex =  s_ifr.ifr_ifindex;
 /* bind socket to eth0 */
diff --git a/Documentation/networking/scaling.txt b/Documentation/networking/scaling.txt
index a177de21d28..579994afbe0 100644
--- a/Documentation/networking/scaling.txt
+++ b/Documentation/networking/scaling.txt
@@ -208,7 +208,7 @@ The counter in rps_dev_flow_table values records the length of the current
 CPU's backlog when a packet in this flow was last enqueued. Each backlog
 queue has a head counter that is incremented on dequeue. A tail counter
 is computed as head counter + queue length. In other words, the counter
-in rps_dev_flow_table[i] records the last element in flow i that has
+in rps_dev_flow[i] records the last element in flow i that has
 been enqueued onto the currently designated CPU for flow i (of course,
 entry i is actually selected by hash and multiple flows may hash to the
 same entry i).
@@ -224,7 +224,7 @@ following is true:
 - The current CPU's queue head counter >= the recorded tail counter
  value in rps_dev_flow[i]
- The current CPU is unset (equal to NR_CPUS)
+- The current CPU is unset (equal to RPS_NO_CPU)
 - The current CPU is offline
 After this check, the packet is sent to the (possibly updated) current
@@ -235,7 +235,7 @@ CPU.
 ==== RFS Configuration
-RFS is only available if the kconfig symbol CONFIG_RFS is enabled (on
+RFS is only available if the kconfig symbol CONFIG_RPS is enabled (on
 by default for SMP). The functionality remains disabled until explicitly
 configured. The number of entries in the global flow table is set through:
@@ -258,7 +258,7 @@ For a single queue device, the rps_flow_cnt value for the single queue
 would normally be configured to the same value as rps_sock_flow_entries.
 For a multi-queue device, the rps_flow_cnt for each queue might be
 configured as rps_sock_flow_entries / N, where N is the number of
-queues. So for instance, if rps_flow_entries is set to 32768 and there
+queues. So for instance, if rps_sock_flow_entries is set to 32768 and there
 are 16 configured receive queues, rps_flow_cnt for each queue might be
 configured as 2048.
diff --git a/Documentation/networking/stmmac.txt b/Documentation/networking/stmmac.txt
index 8d67980fabe..d0aeeadd264 100644
--- a/Documentation/networking/stmmac.txt
+++ b/Documentation/networking/stmmac.txt
@@ -4,14 +4,16 @@ Copyright (C) 2007-2010  STMicroelectronics Ltd
 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
 This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers
-(Synopsys IP blocks); it has been fully tested on STLinux platforms.
+(Synopsys IP blocks).
 Currently this network device driver is for all STM embedded MAC/GMAC
-(i.e. 7xxx/5xxx SoCs) and it's known working on other platforms i.e. ARM SPEAr.
+(i.e. 7xxx/5xxx SoCs), SPEAr (arm), Loongson1B (mips) and XLINX XC2V3000
+FF1152AMT0221 D1215994A VIRTEX FPGA board.
-DWC Ether MAC 10/100/1000 Universal version 3.41a and DWC Ether MAC 10/100
+DWC Ether MAC 10/100/1000 Universal version 3.60a (and older) and DWC Ether MAC 10/100
-Universal version 4.0 have been used for developing the first code
+Universal version 4.0 have been used for developing this driver.
-implementation.
+This driver supports both the platform bus and PCI.
 Please, for more information also visit: www.stlinux.com
@@ -277,5 +279,5 @@ In fact, these can generate an huge amount of debug messages.
 6) TODO:
 o XGMAC is not supported.
- o Review the timer optimisation code to use an embedded device that will be
+ o Add the EEE - Energy Efficient Ethernet
-  available in new chip generations.
+ o Add the PTP - precision time protocol
diff --git a/Documentation/networking/team.txt b/Documentation/networking/team.txt
new file mode 100644
index 00000000000..5a013686b9e
--- /dev/null
+++ b/Documentation/networking/team.txt
@@ -0,0 +1,2 @@
+Team devices are driven from userspace via libteam library which is here:
+        https://github.com/jpirko/libteam
diff --git a/Documentation/pinctrl.txt b/Documentation/pinctrl.txt
index b04cb7d45a1..6727b92bc2f 100644
--- a/Documentation/pinctrl.txt
+++ b/Documentation/pinctrl.txt
@@ -7,12 +7,9 @@ This subsystem deals with:
 - Multiplexing of pins, pads, fingers (etc) see below for details
-The intention is to also deal with:
+- Configuration of pins, pads, fingers (etc), such as software-controlled
+  biasing and driving mode specific pins, such as pull-up/down, open drain,
- Software-controlled biasing and driving mode specific pins, such as
+  load capacitance etc.
-  pull-up/down, open drain etc, load capacitance configuration when controlled
-  by software, etc.
 Top-level interface
 ===================
@@ -32,7 +29,7 @@ Definition of PIN:
  be sparse - i.e. there may be gaps in the space with numbers where no
  pin exists.
-When a PIN CONTROLLER is instatiated, it will register a descriptor to the
+When a PIN CONTROLLER is instantiated, it will register a descriptor to the
 pin control framework, and this descriptor contains an array of pin descriptors
 describing the pins handled by this specific pin controller.
@@ -61,14 +58,14 @@ this in our driver:
 #include <linux/pinctrl/pinctrl.h>
-const struct pinctrl_pin_desc __refdata foo_pins[] = {
+const struct pinctrl_pin_desc foo_pins[] = {
-      PINCTRL_PIN(0, "A1"),
+      PINCTRL_PIN(0, "A8"),
-      PINCTRL_PIN(1, "A2"),
+      PINCTRL_PIN(1, "B8"),
-      PINCTRL_PIN(2, "A3"),
+      PINCTRL_PIN(2, "C8"),
      ...
-      PINCTRL_PIN(61, "H6"),
+      PINCTRL_PIN(61, "F1"),
-      PINCTRL_PIN(62, "H7"),
+      PINCTRL_PIN(62, "G1"),
-      PINCTRL_PIN(63, "H8"),
+      PINCTRL_PIN(63, "H1"),
 };
 static struct pinctrl_desc foo_desc = {
@@ -88,11 +85,16 @@ int __init foo_probe(void)
                pr_err("could not register foo pin driver\n");
 }
+To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
+selected drivers, you need to select them from your machine's Kconfig entry,
+since these are so tightly integrated with the machines they are used on.
+See for example arch/arm/mach-u300/Kconfig for an example.
 Pins usually have fancier names than this. You can find these in the dataheet
 for your chip. Notice that the core pinctrl.h file provides a fancy macro
 called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
-the pins from 0 in the upper left corner to 63 in the lower right corner,
+the pins from 0 in the upper left corner to 63 in the lower right corner.
-this enumeration was arbitrarily chosen, in practice you need to think
+This enumeration was arbitrarily chosen, in practice you need to think
 through your numbering system so that it matches the layout of registers
 and such things in your driver, or the code may become complicated. You must
 also consider matching of offsets to the GPIO ranges that may be handled by
@@ -133,8 +135,8 @@ struct foo_group {
        const unsigned num_pins;
 };
-static unsigned int spi0_pins[] = { 0, 8, 16, 24 };
+static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
-static unsigned int i2c0_pins[] = { 24, 25 };
+static const unsigned int i2c0_pins[] = { 24, 25 };
 static const struct foo_group foo_groups[] = {
        {
@@ -193,6 +195,88 @@ structure, for example specific register ranges associated with each group
 and so on.
+Pin configuration
+=================
+Pins can sometimes be software-configured in an various ways, mostly related
+to their electronic properties when used as inputs or outputs. For example you
+may be able to make an output pin high impedance, or "tristate" meaning it is
+effectively disconnected. You may be able to connect an input pin to VDD or GND
+using a certain resistor value - pull up and pull down - so that the pin has a
+stable value when nothing is driving the rail it is connected to, or when it's
+unconnected.
+For example, a platform may do this:
+ret = pin_config_set("foo-dev", "FOO_GPIO_PIN", PLATFORM_X_PULL_UP);
+To pull up a pin to VDD. The pin configuration driver implements callbacks for
+changing pin configuration in the pin controller ops like this:
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinconf.h>
+#include "platform_x_pindefs.h"
+static int foo_pin_config_get(struct pinctrl_dev *pctldev,
+                    unsigned offset,
+                    unsigned long *config)
+{
+        struct my_conftype conf;
+        ... Find setting for pin @ offset ...
+        *config = (unsigned long) conf;
+}
+static int foo_pin_config_set(struct pinctrl_dev *pctldev,
+                    unsigned offset,
+                    unsigned long config)
+{
+        struct my_conftype *conf = (struct my_conftype *) config;
+        switch (conf) {
+                case PLATFORM_X_PULL_UP:
+                ...
+                }
+        }
+}
+static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
+                    unsigned selector,
+                    unsigned long *config)
+{
+        ...
+}
+static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
+                    unsigned selector,
+                    unsigned long config)
+{
+        ...
+}
+static struct pinconf_ops foo_pconf_ops = {
+        .pin_config_get = foo_pin_config_get,
+        .pin_config_set = foo_pin_config_set,
+        .pin_config_group_get = foo_pin_config_group_get,
+        .pin_config_group_set = foo_pin_config_group_set,
+};
+/* Pin config operations are handled by some pin controller */
+static struct pinctrl_desc foo_desc = {
+        ...
+        .confops = &foo_pconf_ops,
+};
+Since some controllers have special logic for handling entire groups of pins
+they can exploit the special whole-group pin control function. The
+pin_config_group_set() callback is allowed to return the error code -EAGAIN,
+for groups it does not want to handle, or if it just wants to do some
+group-level handling and then fall through to iterate over all pins, in which
+case each individual pin will be treated by separate pin_config_set() calls as
+well.
 Interaction with the GPIO subsystem
 ===================================
@@ -214,19 +298,20 @@ static struct pinctrl_gpio_range gpio_range_a = {
        .name = "chip a",
        .id = 0,
        .base = 32,
+        .pin_base = 32,
        .npins = 16,
        .gc = &chip_a;
 };
-static struct pinctrl_gpio_range gpio_range_a = {
+static struct pinctrl_gpio_range gpio_range_b = {
        .name = "chip b",
        .id = 0,
        .base = 48,
+        .pin_base = 64,
        .npins = 8,
        .gc = &chip_b;
 };
 {
        struct pinctrl_dev *pctl;
        ...
@@ -235,42 +320,39 @@ static struct pinctrl_gpio_range gpio_range_a = {
 }
 So this complex system has one pin controller handling two different
-GPIO chips. Chip a has 16 pins and chip b has 8 pins. They are mapped in
+GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
-the global GPIO pin space at:
+"chip b" have different .pin_base, which means a start pin number of the
+GPIO range.
+The GPIO range of "chip a" starts from the GPIO base of 32 and actual
+pin range also starts from 32. However "chip b" has different starting
+offset for the GPIO range and pin range. The GPIO range of "chip b" starts
+from GPIO number 48, while the pin range of "chip b" starts from 64.
+We can convert a gpio number to actual pin number using this "pin_base".
+They are mapped in the global GPIO pin space at:
-chip a: [32 .. 47]
+chip a:
-chip b: [48 .. 55]
+ - GPIO range : [32 .. 47]
+ - pin range  : [32 .. 47]
+chip b:
+ - GPIO range : [48 .. 55]
+ - pin range  : [64 .. 71]
 When GPIO-specific functions in the pin control subsystem are called, these
-ranges will be used to look up the apropriate pin controller by inspecting
+ranges will be used to look up the appropriate pin controller by inspecting
 and matching the pin to the pin ranges across all controllers. When a
 pin controller handling the matching range is found, GPIO-specific functions
 will be called on that specific pin controller.
 For all functionalities dealing with pin biasing, pin muxing etc, the pin
 controller subsystem will subtract the range's .base offset from the passed
-in gpio pin number, and pass that on to the pin control driver, so the driver
+in gpio number, and add the ranges's .pin_base offset to retrive a pin number.
-will get an offset into its handled number range. Further it is also passed
+After that, the subsystem passes it on to the pin control driver, so the driver
+will get an pin number into its handled number range. Further it is also passed
 the range ID value, so that the pin controller knows which range it should
 deal with.
-For example: if a user issues pinctrl_gpio_set_foo(50), the pin control
-subsystem will find that the second range on this pin controller matches,
-subtract the base 48 and call the
-pinctrl_driver_gpio_set_foo(pinctrl, range, 2) where the latter function has
-this signature:
-int pinctrl_driver_gpio_set_foo(struct pinctrl_dev *pctldev,
-    struct pinctrl_gpio_range *rangeid,
-    unsigned offset);
-Now the driver knows that we want to do some GPIO-specific operation on the
-second GPIO range handled by "chip b", at offset 2 in that specific range.
-(If the GPIO subsystem is ever refactored to use a local per-GPIO controller
-pin space, this mapping will need to be augmented accordingly.)
 PINMUX interfaces
 =================
@@ -438,7 +520,7 @@ you. Define enumerators only for the pins you can control if that makes sense.
 Assumptions:
-We assume that the number possible function maps to pin groups is limited by
+We assume that the number of possible function maps to pin groups is limited by
 the hardware. I.e. we assume that there is no system where any function can be
 mapped to any pin, like in a phone exchange. So the available pins groups for
 a certain function will be limited to a few choices (say up to eight or so),
@@ -585,7 +667,7 @@ int foo_list_funcs(struct pinctrl_dev *pctldev, unsigned selector)
 const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
 {
-        return myfuncs[selector].name;
+        return foo_functions[selector].name;
 }
 static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
@@ -600,16 +682,16 @@ static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
 int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
                unsigned group)
 {
-        u8 regbit = (1 << group);
+        u8 regbit = (1 << selector + group);
        writeb((readb(MUX)|regbit), MUX)
        return 0;
 }
-int foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
+void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
                unsigned group)
 {
-        u8 regbit = (1 << group);
+        u8 regbit = (1 << selector + group);
        writeb((readb(MUX) & ~(regbit)), MUX)
        return 0;
@@ -647,6 +729,17 @@ All the above functions are mandatory to implement for a pinmux driver.
 Pinmux interaction with the GPIO subsystem
 ==========================================
+The public pinmux API contains two functions named pinmux_request_gpio()
+and pinmux_free_gpio(). These two functions shall *ONLY* be called from
+gpiolib-based drivers as part of their gpio_request() and
+gpio_free() semantics. Likewise the pinmux_gpio_direction_[input|output]
+shall only be called from within respective gpio_direction_[input|output]
+gpiolib implementation.
+NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
+muxed in. Instead, implement a proper gpiolib driver and have that driver
+request proper muxing for its pins.
 The function list could become long, especially if you can convert every
 individual pin into a GPIO pin independent of any other pins, and then try
 the approach to define every pin as a function.
@@ -654,19 +747,24 @@ the approach to define every pin as a function.
 In this case, the function array would become 64 entries for each GPIO
 setting and then the device functions.
-For this reason there is an additional function a pinmux driver can implement
+For this reason there are two functions a pinmux driver can implement
-to enable only GPIO on an individual pin: .gpio_request_enable(). The same
+to enable only GPIO on an individual pin: .gpio_request_enable() and
-.free() function as for other functions is assumed to be usable also for
+.gpio_disable_free().
-GPIO pins.
 This function will pass in the affected GPIO range identified by the pin
 controller core, so you know which GPIO pins are being affected by the request
 operation.
-Alternatively it is fully allowed to use named functions for each GPIO
+If your driver needs to have an indication from the framework of whether the
-pin, the pinmux_request_gpio() will attempt to obtain the function "gpioN"
+GPIO pin shall be used for input or output you can implement the
-where "N" is the global GPIO pin number if no special GPIO-handler is
+.gpio_set_direction() function. As described this shall be called from the
-registered.
+gpiolib driver and the affected GPIO range, pin offset and desired direction
+will be passed along to this function.
+Alternatively to using these special functions, it is fully allowed to use
+named functions for each GPIO pin, the pinmux_request_gpio() will attempt to
+obtain the function "gpioN" where "N" is the global GPIO pin number if no
+special GPIO-handler is registered.
 Pinmux board/machine configuration
@@ -683,19 +781,19 @@ spi on the second function mapping:
 #include <linux/pinctrl/machine.h>
-static struct pinmux_map pmx_mapping[] = {
+static const struct pinmux_map __initdata pmx_mapping[] = {
        {
-                .ctrl_dev_name = "pinctrl.0",
+                .ctrl_dev_name = "pinctrl-foo",
                .function = "spi0",
                .dev_name = "foo-spi.0",
        },
        {
-                .ctrl_dev_name = "pinctrl.0",
+                .ctrl_dev_name = "pinctrl-foo",
                .function = "i2c0",
                .dev_name = "foo-i2c.0",
        },
        {
-                .ctrl_dev_name = "pinctrl.0",
+                .ctrl_dev_name = "pinctrl-foo",
                .function = "mmc0",
                .dev_name = "foo-mmc.0",
        },
@@ -714,14 +812,14 @@ for example if they are not yet instantiated or cumbersome to obtain.
 You register this pinmux mapping to the pinmux subsystem by simply:
-       ret = pinmux_register_mappings(&pmx_mapping, ARRAY_SIZE(pmx_mapping));
+       ret = pinmux_register_mappings(pmx_mapping, ARRAY_SIZE(pmx_mapping));
 Since the above construct is pretty common there is a helper macro to make
-it even more compact which assumes you want to use pinctrl.0 and position
+it even more compact which assumes you want to use pinctrl-foo and position
 0 for mapping, for example:
-static struct pinmux_map pmx_mapping[] = {
+static struct pinmux_map __initdata pmx_mapping[] = {
-       PINMUX_MAP_PRIMARY("I2CMAP", "i2c0", "foo-i2c.0"),
+       PINMUX_MAP("I2CMAP", "pinctrl-foo", "i2c0", "foo-i2c.0"),
 };
@@ -734,14 +832,14 @@ As it is possible to map a function to different groups of pins an optional
 ...
 {
        .name = "spi0-pos-A",
-        .ctrl_dev_name = "pinctrl.0",
+        .ctrl_dev_name = "pinctrl-foo",
        .function = "spi0",
        .group = "spi0_0_grp",
        .dev_name = "foo-spi.0",
 },
 {
        .name = "spi0-pos-B",
-        .ctrl_dev_name = "pinctrl.0",
+        .ctrl_dev_name = "pinctrl-foo",
        .function = "spi0",
        .group = "spi0_1_grp",
        .dev_name = "foo-spi.0",
@@ -760,44 +858,44 @@ case), we define a mapping like this:
 ...
 {
        .name "2bit"
-        .ctrl_dev_name = "pinctrl.0",
+        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
-        .group = "mmc0_0_grp",
+        .group = "mmc0_1_grp",
        .dev_name = "foo-mmc.0",
 },
 {
        .name "4bit"
-        .ctrl_dev_name = "pinctrl.0",
+        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
-        .group = "mmc0_0_grp",
+        .group = "mmc0_1_grp",
        .dev_name = "foo-mmc.0",
 },
 {
        .name "4bit"
-        .ctrl_dev_name = "pinctrl.0",
+        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
-        .group = "mmc0_1_grp",
+        .group = "mmc0_2_grp",
        .dev_name = "foo-mmc.0",
 },
 {
        .name "8bit"
-        .ctrl_dev_name = "pinctrl.0",
+        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
-        .group = "mmc0_0_grp",
+        .group = "mmc0_1_grp",
        .dev_name = "foo-mmc.0",
 },
 {
        .name "8bit"
-        .ctrl_dev_name = "pinctrl.0",
+        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
-        .group = "mmc0_1_grp",
+        .group = "mmc0_2_grp",
        .dev_name = "foo-mmc.0",
 },
 {
        .name "8bit"
-        .ctrl_dev_name = "pinctrl.0",
+        .ctrl_dev_name = "pinctrl-foo",
        .function = "mmc0",
-        .group = "mmc0_2_grp",
+        .group = "mmc0_3_grp",
        .dev_name = "foo-mmc.0",
 },
 ...
@@ -898,7 +996,7 @@ like this:
 {
        .name "POWERMAP"
-        .ctrl_dev_name = "pinctrl.0",
+        .ctrl_dev_name = "pinctrl-foo",
        .function = "power_func",
        .hog_on_boot = true,
 },
diff --git a/Documentation/power/charger-manager.txt b/Documentation/power/charger-manager.txt
new file mode 100644
index 00000000000..fdcca991df3
--- /dev/null
+++ b/Documentation/power/charger-manager.txt
@@ -0,0 +1,163 @@
+Charger Manager
+        (C) 2011 MyungJoo Ham <myungjoo.ham@samsung.com>, GPL
+Charger Manager provides in-kernel battery charger management that
+requires temperature monitoring during suspend-to-RAM state
+and where each battery may have multiple chargers attached and the userland
+wants to look at the aggregated information of the multiple chargers.
+Charger Manager is a platform_driver with power-supply-class entries.
+An instance of Charger Manager (a platform-device created with Charger-Manager)
+represents an independent battery with chargers. If there are multiple
+batteries with their own chargers acting independently in a system,
+the system may need multiple instances of Charger Manager.
+1. Introduction
+===============
+Charger Manager supports the following:
+* Support for multiple chargers (e.g., a device with USB, AC, and solar panels)
+        A system may have multiple chargers (or power sources) and some of
+        they may be activated at the same time. Each charger may have its
+        own power-supply-class and each power-supply-class can provide
+        different information about the battery status. This framework
+        aggregates charger-related information from multiple sources and
+        shows combined information as a single power-supply-class.
+* Support for in suspend-to-RAM polling (with suspend_again callback)
+        While the battery is being charged and the system is in suspend-to-RAM,
+        we may need to monitor the battery health by looking at the ambient or
+        battery temperature. We can accomplish this by waking up the system
+        periodically. However, such a method wakes up devices unncessary for
+        monitoring the battery health and tasks, and user processes that are
+        supposed to be kept suspended. That, in turn, incurs unnecessary power
+        consumption and slow down charging process. Or even, such peak power
+        consumption can stop chargers in the middle of charging
+        (external power input < device power consumption), which not
+        only affects the charging time, but the lifespan of the battery.
+        Charger Manager provides a function "cm_suspend_again" that can be
+        used as suspend_again callback of platform_suspend_ops. If the platform
+        requires tasks other than cm_suspend_again, it may implement its own
+        suspend_again callback that calls cm_suspend_again in the middle.
+        Normally, the platform will need to resume and suspend some devices
+        that are used by Charger Manager.
+2. Global Charger-Manager Data related with suspend_again
+========================================================
+In order to setup Charger Manager with suspend-again feature
+(in-suspend monitoring), the user should provide charger_global_desc
+with setup_charger_manager(struct charger_global_desc *).
+This charger_global_desc data for in-suspend monitoring is global
+as the name suggests. Thus, the user needs to provide only once even
+if there are multiple batteries. If there are multiple batteries, the
+multiple instances of Charger Manager share the same charger_global_desc
+and it will manage in-suspend monitoring for all instances of Charger Manager.
+The user needs to provide all the two entries properly in order to activate
+in-suspend monitoring:
+struct charger_global_desc {
+char *rtc_name;
+        : The name of rtc (e.g., "rtc0") used to wakeup the system from
+        suspend for Charger Manager. The alarm interrupt (AIE) of the rtc
+        should be able to wake up the system from suspend. Charger Manager
+        saves and restores the alarm value and use the previously-defined
+        alarm if it is going to go off earlier than Charger Manager so that
+        Charger Manager does not interfere with previously-defined alarms.
+bool (*rtc_only_wakeup)(void);
+        : This callback should let CM know whether
+        the wakeup-from-suspend is caused only by the alarm of "rtc" in the
+        same struct. If there is any other wakeup source triggered the
+        wakeup, it should return false. If the "rtc" is the only wakeup
+        reason, it should return true.
+};
+3. How to setup suspend_again
+=============================
+Charger Manager provides a function "extern bool cm_suspend_again(void)".
+When cm_suspend_again is called, it monitors every battery. The suspend_ops
+callback of the system's platform_suspend_ops can call cm_suspend_again
+function to know whether Charger Manager wants to suspend again or not.
+If there are no other devices or tasks that want to use suspend_again
+feature, the platform_suspend_ops may directly refer to cm_suspend_again
+for its suspend_again callback.
+The cm_suspend_again() returns true (meaning "I want to suspend again")
+if the system was woken up by Charger Manager and the polling
+(in-suspend monitoring) results in "normal".
+4. Charger-Manager Data (struct charger_desc)
+=============================================
+For each battery charged independently from other batteries (if a series of
+batteries are charged by a single charger, they are counted as one independent
+battery), an instance of Charger Manager is attached to it.
+struct charger_desc {
+char *psy_name;
+        : The power-supply-class name of the battery. Default is
+        "battery" if psy_name is NULL. Users can access the psy entries
+        at "/sys/class/power_supply/[psy_name]/".
+enum polling_modes polling_mode;
+        : CM_POLL_DISABLE: do not poll this battery.
+          CM_POLL_ALWAYS: always poll this battery.
+          CM_POLL_EXTERNAL_POWER_ONLY: poll this battery if and only if
+                                       an external power source is attached.
+          CM_POLL_CHARGING_ONLY: poll this battery if and only if the
+                                 battery is being charged.
+unsigned int fullbatt_uV;
+        : If specified with a non-zero value, Charger Manager assumes
+        that the battery is full (capacity = 100) if the battery is not being
+        charged and the battery voltage is equal to or greater than
+        fullbatt_uV.
+unsigned int polling_interval_ms;
+        : Required polling interval in ms. Charger Manager will poll
+        this battery every polling_interval_ms or more frequently.
+enum data_source battery_present;
+        CM_FUEL_GAUGE: get battery presence information from fuel gauge.
+        CM_CHARGER_STAT: get battery presence from chargers.
+char **psy_charger_stat;
+        : An array ending with NULL that has power-supply-class names of
+        chargers. Each power-supply-class should provide "PRESENT" (if
+        battery_present is "CM_CHARGER_STAT"), "ONLINE" (shows whether an
+        external power source is attached or not), and "STATUS" (shows whether
+        the battery is {"FULL" or not FULL} or {"FULL", "Charging",
+        "Discharging", "NotCharging"}).
+int num_charger_regulators;
+struct regulator_bulk_data *charger_regulators;
+        : Regulators representing the chargers in the form for
+        regulator framework's bulk functions.
+char *psy_fuel_gauge;
+        : Power-supply-class name of the fuel gauge.
+int (*temperature_out_of_range)(int *mC);
+bool measure_battery_temp;
+        : This callback returns 0 if the temperature is safe for charging,
+        a positive number if it is too hot to charge, and a negative number
+        if it is too cold to charge. With the variable mC, the callback returns
+        the temperature in 1/1000 of centigrade.
+        The source of temperature can be battery or ambient one according to
+        the value of measure_battery_temp.
+};
+5. Other Considerations
+=======================
+At the charger/battery-related events such as battery-pulled-out,
+charger-pulled-out, charger-inserted, DCIN-over/under-voltage, charger-stopped,
+and others critical to chargers, the system should be configured to wake up.
+At least the following should wake up the system from a suspend:
+a) charger-on/off b) external-power-in/out c) battery-in/out (while charging)
+It is usually accomplished by configuring the PMIC as a wakeup source.
diff --git a/Documentation/power/devices.txt b/Documentation/power/devices.txt
index 3139fb505dc..20af7def23c 100644
--- a/Documentation/power/devices.txt
+++ b/Documentation/power/devices.txt
@@ -126,7 +126,9 @@ The core methods to suspend and resume devices reside in struct dev_pm_ops
 pointed to by the ops member of struct dev_pm_domain, or by the pm member of
 struct bus_type, struct device_type and struct class.  They are mostly of
 interest to the people writing infrastructure for platforms and buses, like PCI
-or USB, or device type and device class drivers.
+or USB, or device type and device class drivers.  They also are relevant to the
+writers of device drivers whose subsystems (PM domains, device types, device
+classes and bus types) don't provide all power management methods.
 Bus drivers implement these methods as appropriate for the hardware and the
 drivers using it; PCI works differently from USB, and so on.  Not many people
@@ -268,32 +270,35 @@ various phases always run after tasks have been frozen and before they are
 unfrozen.  Furthermore, the *_noirq phases run at a time when IRQ handlers have
 been disabled (except for those marked with the IRQF_NO_SUSPEND flag).
-All phases use PM domain, bus, type, or class callbacks (that is, methods
+All phases use PM domain, bus, type, class or driver callbacks (that is, methods
-defined in dev->pm_domain->ops, dev->bus->pm, dev->type->pm, or dev->class->pm).
+defined in dev->pm_domain->ops, dev->bus->pm, dev->type->pm, dev->class->pm or
-These callbacks are regarded by the PM core as mutually exclusive.  Moreover,
+dev->driver->pm).  These callbacks are regarded by the PM core as mutually
-PM domain callbacks always take precedence over bus, type and class callbacks,
+exclusive.  Moreover, PM domain callbacks always take precedence over all of the
-while type callbacks take precedence over bus and class callbacks, and class
+other callbacks and, for example, type callbacks take precedence over bus, class
-callbacks take precedence over bus callbacks.  To be precise, the following
+and driver callbacks.  To be precise, the following rules are used to determine
-rules are used to determine which callback to execute in the given phase:
+which callback to execute in the given phase:
-    1.  If dev->pm_domain is present, the PM core will attempt to execute the
+    1.  If dev->pm_domain is present, the PM core will choose the callback
-        callback included in dev->pm_domain->ops.  If that callback is not
+        included in dev->pm_domain->ops for execution
-        present, no action will be carried out for the given device.
    2.  Otherwise, if both dev->type and dev->type->pm are present, the callback
-        included in dev->type->pm will be executed.
+        included in dev->type->pm will be chosen for execution.
    3.  Otherwise, if both dev->class and dev->class->pm are present, the
-        callback included in dev->class->pm will be executed.
+        callback included in dev->class->pm will be chosen for execution.
    4.  Otherwise, if both dev->bus and dev->bus->pm are present, the callback
-        included in dev->bus->pm will be executed.
+        included in dev->bus->pm will be chosen for execution.
 This allows PM domains and device types to override callbacks provided by bus
 types or device classes if necessary.
-These callbacks may in turn invoke device- or driver-specific methods stored in
+The PM domain, type, class and bus callbacks may in turn invoke device- or
-dev->driver->pm, but they don't have to.
+driver-specific methods stored in dev->driver->pm, but they don't have to do
+that.
+If the subsystem callback chosen for execution is not present, the PM core will
+execute the corresponding method from dev->driver->pm instead if there is one.
 Entering System Suspend
diff --git a/Documentation/power/freezing-of-tasks.txt b/Documentation/power/freezing-of-tasks.txt
index 316c2ba187f..6ccb68f68da 100644
--- a/Documentation/power/freezing-of-tasks.txt
+++ b/Documentation/power/freezing-of-tasks.txt
@@ -21,7 +21,7 @@ freeze_processes() (defined in kernel/power/process.c) is called.  It executes
 try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and
 either wakes them up, if they are kernel threads, or sends fake signals to them,
 if they are user space processes.  A task that has TIF_FREEZE set, should react
-to it by calling the function called refrigerator() (defined in
+to it by calling the function called __refrigerator() (defined in
 kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state
 to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it.
 Then, we say that the task is 'frozen' and therefore the set of functions
@@ -29,10 +29,10 @@ handling this mechanism is referred to as 'the freezer' (these functions are
 defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h).
 User space processes are generally frozen before kernel threads.
-It is not recommended to call refrigerator() directly.  Instead, it is
+__refrigerator() must not be called directly.  Instead, use the
-recommended to use the try_to_freeze() function (defined in
+try_to_freeze() function (defined in include/linux/freezer.h), that checks
-include/linux/freezer.h), that checks the task's TIF_FREEZE flag and makes the
+the task's TIF_FREEZE flag and makes the task enter __refrigerator() if the
-task enter refrigerator() if the flag is set.
+flag is set.
 For user space processes try_to_freeze() is called automatically from the
 signal-handling code, but the freezable kernel threads need to call it
@@ -61,13 +61,13 @@ wait_event_freezable() and wait_event_freezable_timeout() macros.
 After the system memory state has been restored from a hibernation image and
 devices have been reinitialized, the function thaw_processes() is called in
 order to clear the PF_FROZEN flag for each frozen task.  Then, the tasks that
-have been frozen leave refrigerator() and continue running.
+have been frozen leave __refrigerator() and continue running.
 III. Which kernel threads are freezable?
 Kernel threads are not freezable by default.  However, a kernel thread may clear
 PF_NOFREEZE for itself by calling set_freezable() (the resetting of PF_NOFREEZE
-directly is strongly discouraged).  From this point it is regarded as freezable
+directly is not allowed).  From this point it is regarded as freezable
 and must call try_to_freeze() in a suitable place.
 IV. Why do we do that?
@@ -176,3 +176,28 @@ tasks, since it generally exists anyway.
 A driver must have all firmwares it may need in RAM before suspend() is called.
 If keeping them is not practical, for example due to their size, they must be
 requested early enough using the suspend notifier API described in notifiers.txt.
+VI. Are there any precautions to be taken to prevent freezing failures?
+Yes, there are.
+First of all, grabbing the 'pm_mutex' lock to mutually exclude a piece of code
+from system-wide sleep such as suspend/hibernation is not encouraged.
+If possible, that piece of code must instead hook onto the suspend/hibernation
+notifiers to achieve mutual exclusion. Look at the CPU-Hotplug code
+(kernel/cpu.c) for an example.
+However, if that is not feasible, and grabbing 'pm_mutex' is deemed necessary,
+it is strongly discouraged to directly call mutex_[un]lock(&pm_mutex) since
+that could lead to freezing failures, because if the suspend/hibernate code
+successfully acquired the 'pm_mutex' lock, and hence that other entity failed
+to acquire the lock, then that task would get blocked in TASK_UNINTERRUPTIBLE
+state. As a consequence, the freezer would not be able to freeze that task,
+leading to freezing failure.
+However, the [un]lock_system_sleep() APIs are safe to use in this scenario,
+since they ask the freezer to skip freezing this task, since it is anyway
+"frozen enough" as it is blocked on 'pm_mutex', which will be released
+only after the entire suspend/hibernation sequence is complete.
+So, to summarize, use [un]lock_system_sleep() instead of directly using
+mutex_[un]lock(&pm_mutex). That would prevent freezing failures.
diff --git a/Documentation/power/regulator/regulator.txt b/Documentation/power/regulator/regulator.txt
index 3f8b528f237..e272d9909e3 100644
--- a/Documentation/power/regulator/regulator.txt
+++ b/Documentation/power/regulator/regulator.txt
@@ -12,7 +12,7 @@ Drivers can register a regulator by calling :-
 struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc,
        struct device *dev, struct regulator_init_data *init_data,
-        void *driver_data);
+        void *driver_data, struct device_node *of_node);
 This will register the regulators capabilities and operations to the regulator
 core.
diff --git a/Documentation/power/runtime_pm.txt b/Documentation/power/runtime_pm.txt
index c2ae8bf77d4..4abe83e1045 100644
--- a/Documentation/power/runtime_pm.txt
+++ b/Documentation/power/runtime_pm.txt
@@ -57,6 +57,10 @@ the following:
  4. Bus type of the device, if both dev->bus and dev->bus->pm are present.
+If the subsystem chosen by applying the above rules doesn't provide the relevant
+callback, the PM core will invoke the corresponding driver callback stored in
+dev->driver->pm directly (if present).
 The PM core always checks which callback to use in the order given above, so the
 priority order of callbacks from high to low is: PM domain, device type, class
 and bus type.  Moreover, the high-priority one will always take precedence over
@@ -64,86 +68,88 @@ a low-priority one.  The PM domain, bus type, device type and class callbacks
 are referred to as subsystem-level callbacks in what follows.
 By default, the callbacks are always invoked in process context with interrupts
-enabled.  However, subsystems can use the pm_runtime_irq_safe() helper function
+enabled.  However, the pm_runtime_irq_safe() helper function can be used to tell
-to tell the PM core that their ->runtime_suspend(), ->runtime_resume() and
+the PM core that it is safe to run the ->runtime_suspend(), ->runtime_resume()
->runtime_idle() callbacks may be invoked in atomic context with interrupts
+and ->runtime_idle() callbacks for the given device in atomic context with
-disabled for a given device.  This implies that the callback routines in
+interrupts disabled.  This implies that the callback routines in question must
-question must not block or sleep, but it also means that the synchronous helper
+not block or sleep, but it also means that the synchronous helper functions
-functions listed at the end of Section 4 may be used for that device within an
+listed at the end of Section 4 may be used for that device within an interrupt
-interrupt handler or generally in an atomic context.
+handler or generally in an atomic context.
-The subsystem-level suspend callback is _entirely_ _responsible_ for handling
+The subsystem-level suspend callback, if present, is _entirely_ _responsible_
-the suspend of the device as appropriate, which may, but need not include
+for handling the suspend of the device as appropriate, which may, but need not
-executing the device driver's own ->runtime_suspend() callback (from the
+include executing the device driver's own ->runtime_suspend() callback (from the
 PM core's point of view it is not necessary to implement a ->runtime_suspend()
 callback in a device driver as long as the subsystem-level suspend callback
 knows what to do to handle the device).
-  * Once the subsystem-level suspend callback has completed successfully
+  * Once the subsystem-level suspend callback (or the driver suspend callback,
-    for given device, the PM core regards the device as suspended, which need
+    if invoked directly) has completed successfully for the given device, the PM
-    not mean that the device has been put into a low power state.  It is
+    core regards the device as suspended, which need not mean that it has been
-    supposed to mean, however, that the device will not process data and will
+    put into a low power state.  It is supposed to mean, however, that the
-    not communicate with the CPU(s) and RAM until the subsystem-level resume
+    device will not process data and will not communicate with the CPU(s) and
-    callback is executed for it.  The runtime PM status of a device after
+    RAM until the appropriate resume callback is executed for it.  The runtime
-    successful execution of the subsystem-level suspend callback is 'suspended'.
+    PM status of a device after successful execution of the suspend callback is
+    'suspended'.
-  * If the subsystem-level suspend callback returns -EBUSY or -EAGAIN,
-    the device's runtime PM status is 'active', which means that the device
+  * If the suspend callback returns -EBUSY or -EAGAIN, the device's runtime PM
-    _must_ be fully operational afterwards.
+    status remains 'active', which means that the device _must_ be fully
+    operational afterwards.
-  * If the subsystem-level suspend callback returns an error code different
-    from -EBUSY or -EAGAIN, the PM core regards this as a fatal error and will
+  * If the suspend callback returns an error code different from -EBUSY and
-    refuse to run the helper functions described in Section 4 for the device,
+    -EAGAIN, the PM core regards this as a fatal error and will refuse to run
-    until the status of it is directly set either to 'active', or to 'suspended'
+    the helper functions described in Section 4 for the device until its status
-    (the PM core provides special helper functions for this purpose).
+    is directly set to  either'active', or 'suspended' (the PM core provides
+    special helper functions for this purpose).
-In particular, if the driver requires remote wake-up capability (i.e. hardware
+In particular, if the driver requires remote wakeup capability (i.e. hardware
 mechanism allowing the device to request a change of its power state, such as
 PCI PME) for proper functioning and device_run_wake() returns 'false' for the
 device, then ->runtime_suspend() should return -EBUSY.  On the other hand, if
-device_run_wake() returns 'true' for the device and the device is put into a low
+device_run_wake() returns 'true' for the device and the device is put into a
-power state during the execution of the subsystem-level suspend callback, it is
+low-power state during the execution of the suspend callback, it is expected
-expected that remote wake-up will be enabled for the device.  Generally, remote
+that remote wakeup will be enabled for the device.  Generally, remote wakeup
-wake-up should be enabled for all input devices put into a low power state at
+should be enabled for all input devices put into low-power states at run time.
-run time.
+The subsystem-level resume callback, if present, is _entirely_ _responsible_ for
-The subsystem-level resume callback is _entirely_ _responsible_ for handling the
+handling the resume of the device as appropriate, which may, but need not
-resume of the device as appropriate, which may, but need not include executing
+include executing the device driver's own ->runtime_resume() callback (from the
-the device driver's own ->runtime_resume() callback (from the PM core's point of
+PM core's point of view it is not necessary to implement a ->runtime_resume()
-view it is not necessary to implement a ->runtime_resume() callback in a device
+callback in a device driver as long as the subsystem-level resume callback knows
-driver as long as the subsystem-level resume callback knows what to do to handle
+what to do to handle the device).
-the device).
+  * Once the subsystem-level resume callback (or the driver resume callback, if
-  * Once the subsystem-level resume callback has completed successfully, the PM
+    invoked directly) has completed successfully, the PM core regards the device
-    core regards the device as fully operational, which means that the device
+    as fully operational, which means that the device _must_ be able to complete
-    _must_ be able to complete I/O operations as needed.  The runtime PM status
+    I/O operations as needed.  The runtime PM status of the device is then
-    of the device is then 'active'.
+    'active'.
-  * If the subsystem-level resume callback returns an error code, the PM core
+  * If the resume callback returns an error code, the PM core regards this as a
-    regards this as a fatal error and will refuse to run the helper functions
+    fatal error and will refuse to run the helper functions described in Section
-    described in Section 4 for the device, until its status is directly set
+    4 for the device, until its status is directly set to either 'active', or
-    either to 'active' or to 'suspended' (the PM core provides special helper
+    'suspended' (by means of special helper functions provided by the PM core
-    functions for this purpose).
+    for this purpose).
-The subsystem-level idle callback is executed by the PM core whenever the device
+The idle callback (a subsystem-level one, if present, or the driver one) is
-appears to be idle, which is indicated to the PM core by two counters, the
+executed by the PM core whenever the device appears to be idle, which is
-device's usage counter and the counter of 'active' children of the device.
+indicated to the PM core by two counters, the device's usage counter and the
+counter of 'active' children of the device.
  * If any of these counters is decreased using a helper function provided by
    the PM core and it turns out to be equal to zero, the other counter is
    checked.  If that counter also is equal to zero, the PM core executes the
-    subsystem-level idle callback with the device as an argument.
+    idle callback with the device as its argument.
-The action performed by a subsystem-level idle callback is totally dependent on
+The action performed by the idle callback is totally dependent on the subsystem
-the subsystem in question, but the expected and recommended action is to check
+(or driver) in question, but the expected and recommended action is to check
 if the device can be suspended (i.e. if all of the conditions necessary for
 suspending the device are satisfied) and to queue up a suspend request for the
 device in that case.  The value returned by this callback is ignored by the PM
 core.
 The helper functions provided by the PM core, described in Section 4, guarantee
-that the following constraints are met with respect to the bus type's runtime
+that the following constraints are met with respect to runtime PM callbacks for
-PM callbacks:
+one device:
 (1) The callbacks are mutually exclusive (e.g. it is forbidden to execute
    ->runtime_suspend() in parallel with ->runtime_resume() or with another
diff --git a/Documentation/s390/Debugging390.txt b/Documentation/s390/Debugging390.txt
index efe998becc5..462321c1aee 100644
--- a/Documentation/s390/Debugging390.txt
+++ b/Documentation/s390/Debugging390.txt
@@ -41,7 +41,6 @@ ldd
 Debugging modules
 The proc file system
 Starting points for debugging scripting languages etc.
-Dumptool & Lcrash
 SysRq
 References
 Special Thanks
@@ -2455,39 +2454,6 @@ jdb <filename> another fully interactive gdb style debugger.
-Dumptool & Lcrash ( lkcd )
-==========================
-Michael Holzheu & others here at IBM have a fairly mature port of 
-SGI's lcrash tool which allows one to look at kernel structures in a
-running kernel.
-It also complements a tool called dumptool which dumps all the kernel's
-memory pages & registers to either a tape or a disk.
-This can be used by tech support or an ambitious end user do
-post mortem debugging of a machine like gdb core dumps.
-Going into how to use this tool in detail will be explained
-in other documentation supplied by IBM with the patches & the 
-lcrash homepage http://oss.sgi.com/projects/lkcd/ & the lcrash manpage.
-How they work
-------------
-Lcrash is a perfectly normal program,however, it requires 2 
-additional files, Kerntypes which is built using a patch to the 
-linux kernel sources in the linux root directory & the System.map.
-Kerntypes is an objectfile whose sole purpose in life
-is to provide stabs debug info to lcrash, to do this
-Kerntypes is built from kerntypes.c which just includes the most commonly
-referenced header files used when debugging, lcrash can then read the
-.stabs section of this file.
-Debugging a live system it uses /dev/mem
-alternatively for post mortem debugging it uses the data 
-collected by dumptool.
 SysRq
 =====
 This is now supported by linux for s/390 & z/Architecture.
diff --git a/Documentation/scsi/53c700.txt b/Documentation/scsi/53c700.txt
index 0da681d497a..e31aceb6df1 100644
--- a/Documentation/scsi/53c700.txt
+++ b/Documentation/scsi/53c700.txt
@@ -16,32 +16,13 @@ fill in to get the driver working.
 Compile Time Flags
 ==================
-The driver may be either io mapped or memory mapped.  This is
+A compile time flag is:
-selectable by configuration flags:
-CONFIG_53C700_MEM_MAPPED
-define if the driver is memory mapped.
-CONFIG_53C700_IO_MAPPED
-define if the driver is to be io mapped.
-One or other of the above flags *must* be defined.
-Other flags are:
 CONFIG_53C700_LE_ON_BE
 define if the chipset must be supported in little endian mode on a big
 endian architecture (used for the 700 on parisc).
-CONFIG_53C700_USE_CONSISTENT
-allocate consistent memory (should only be used if your architecture
-has a mixture of consistent and inconsistent memory).  Fully
-consistent or fully inconsistent architectures should not define this.
 Using the Chip Core Driver
 ==========================
diff --git a/Documentation/scsi/ChangeLog.megaraid_sas b/Documentation/scsi/ChangeLog.megaraid_sas
index 64adb98b181..57566bacb4c 100644
--- a/Documentation/scsi/ChangeLog.megaraid_sas
+++ b/Documentation/scsi/ChangeLog.megaraid_sas
@@ -1,3 +1,13 @@
+Release Date    : Fri. Jan 6, 2012 17:00:00 PST 2010 -
+                        (emaild-id:megaraidlinux@lsi.com)
+                        Adam Radford
+Current Version : 00.00.06.14-rc1
+Old Version     : 00.00.06.12-rc1
+    1. Fix reglockFlags for degraded raid5/6 for MR 9360/9380.
+    2. Mask off flags in ioctl path to prevent memory scribble with older
+       MegaCLI versions.
+    3. Remove poll_mode_io module paramater, sysfs node, and associated code.
+-------------------------------------------------------------------------------
 Release Date    : Wed. Oct 5, 2011 17:00:00 PST 2010 -
                        (emaild-id:megaraidlinux@lsi.com)
                        Adam Radford
diff --git a/Documentation/scsi/LICENSE.qla4xxx b/Documentation/scsi/LICENSE.qla4xxx
index 494980e4049..ab899591ecb 100644
--- a/Documentation/scsi/LICENSE.qla4xxx
+++ b/Documentation/scsi/LICENSE.qla4xxx
@@ -1,32 +1,11 @@
 Copyright (c) 2003-2011 QLogic Corporation
-QLogic Linux iSCSI HBA Driver
+QLogic Linux iSCSI Driver
 This program includes a device driver for Linux 3.x.
 You may modify and redistribute the device driver code under the
 GNU General Public License (a copy of which is attached hereto as
 Exhibit A) published by the Free Software Foundation (version 2).
-REGARDLESS OF WHAT LICENSING MECHANISM IS USED OR APPLICABLE,
-THIS PROGRAM IS PROVIDED BY QLOGIC CORPORATION "AS IS'' AND ANY
-EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
-BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-USER ACKNOWLEDGES AND AGREES THAT USE OF THIS PROGRAM WILL NOT
-CREATE OR GIVE GROUNDS FOR A LICENSE BY IMPLICATION, ESTOPPEL, OR
-OTHERWISE IN ANY INTELLECTUAL PROPERTY RIGHTS (PATENT, COPYRIGHT,
-TRADE SECRET, MASK WORK, OR OTHER PROPRIETARY RIGHT) EMBODIED IN
-ANY OTHER QLOGIC HARDWARE OR SOFTWARE EITHER SOLELY OR IN
-COMBINATION WITH THIS PROGRAM.
 EXHIBIT A
diff --git a/Documentation/security/00-INDEX b/Documentation/security/00-INDEX
index 19bc49439ca..99b85d39751 100644
--- a/Documentation/security/00-INDEX
+++ b/Documentation/security/00-INDEX
@@ -1,5 +1,7 @@
 00-INDEX
        - this file.
+LSM.txt
+        - description of the Linux Security Module framework.
 SELinux.txt
        - how to get started with the SELinux security enhancement.
 Smack.txt
diff --git a/Documentation/security/LSM.txt b/Documentation/security/LSM.txt
new file mode 100644
index 00000000000..c335a763a2e
--- /dev/null
+++ b/Documentation/security/LSM.txt
@@ -0,0 +1,34 @@
+Linux Security Module framework
+-------------------------------
+The Linux Security Module (LSM) framework provides a mechanism for
+various security checks to be hooked by new kernel extensions. The name
+"module" is a bit of a misnomer since these extensions are not actually
+loadable kernel modules. Instead, they are selectable at build-time via
+CONFIG_DEFAULT_SECURITY and can be overridden at boot-time via the
+"security=..." kernel command line argument, in the case where multiple
+LSMs were built into a given kernel.
+The primary users of the LSM interface are Mandatory Access Control
+(MAC) extensions which provide a comprehensive security policy. Examples
+include SELinux, Smack, Tomoyo, and AppArmor. In addition to the larger
+MAC extensions, other extensions can be built using the LSM to provide
+specific changes to system operation when these tweaks are not available
+in the core functionality of Linux itself.
+Without a specific LSM built into the kernel, the default LSM will be the
+Linux capabilities system. Most LSMs choose to extend the capabilities
+system, building their checks on top of the defined capability hooks.
+For more details on capabilities, see capabilities(7) in the Linux
+man-pages project.
+Based on http://kerneltrap.org/Linux/Documenting_Security_Module_Intent,
+a new LSM is accepted into the kernel when its intent (a description of
+what it tries to protect against and in what cases one would expect to
+use it) has been appropriately documented in Documentation/security/.
+This allows an LSM's code to be easily compared to its goals, and so
+that end users and distros can make a more informed decision about which
+LSMs suit their requirements.
+For extensive documentation on the available LSM hook interfaces, please
+see include/linux/security.h.
diff --git a/Documentation/security/credentials.txt b/Documentation/security/credentials.txt
index fc0366cbd7c..86257052e31 100644
--- a/Documentation/security/credentials.txt
+++ b/Documentation/security/credentials.txt
@@ -221,10 +221,10 @@ The Linux kernel supports the following types of credentials:
 (5) LSM
     The Linux Security Module allows extra controls to be placed over the
-     operations that a task may do.  Currently Linux supports two main
+     operations that a task may do.  Currently Linux supports several LSM
-     alternate LSM options: SELinux and Smack.
+     options.
-     Both work by labelling the objects in a system and then applying sets of
+     Some work by labelling the objects in a system and then applying sets of
     rules (policies) that say what operations a task with one label may do to
     an object with another label.
diff --git a/Documentation/serial/driver b/Documentation/serial/driver
index 77ba0afbe4d..0a25a919186 100644
--- a/Documentation/serial/driver
+++ b/Documentation/serial/driver
@@ -101,7 +101,7 @@ hardware.
        Returns the current state of modem control inputs.  The state
        of the outputs should not be returned, since the core keeps
        track of their state.  The state information should include:
-                - TIOCM_DCD     state of DCD signal
+                - TIOCM_CAR     state of DCD signal
                - TIOCM_CTS     state of CTS signal
                - TIOCM_DSR     state of DSR signal
                - TIOCM_RI      state of RI signal
diff --git a/Documentation/sound/alsa/HD-Audio-Models.txt b/Documentation/sound/alsa/HD-Audio-Models.txt
index edad99abec2..c8c54544abc 100644
--- a/Documentation/sound/alsa/HD-Audio-Models.txt
+++ b/Documentation/sound/alsa/HD-Audio-Models.txt
@@ -42,19 +42,7 @@ ALC260
 ALC262
 ======
-  fujitsu       Fujitsu Laptop
+  N/A
-  benq          Benq ED8
-  benq-t31      Benq T31
-  hippo         Hippo (ATI) with jack detection, Sony UX-90s
-  hippo_1       Hippo (Benq) with jack detection
-  toshiba-s06   Toshiba S06
-  toshiba-rx1   Toshiba RX1
-  tyan          Tyan Thunder n6650W (S2915-E)
-  ultra         Samsung Q1 Ultra Vista model
-  lenovo-3000   Lenovo 3000 y410
-  nec           NEC Versa S9100
-  basic         fixed pin assignment w/o SPDIF
-  auto          auto-config reading BIOS (default)
 ALC267/268
 ==========
@@ -350,7 +338,6 @@ STAC92HD83*
  mic-ref       Reference board with power management for ports
  dell-s14      Dell laptop
  dell-vostro-3500      Dell Vostro 3500 laptop
-  hp            HP laptops with (inverted) mute-LED
  hp-dv7-4000   HP dv-7 4000
  auto          BIOS setup (default)
diff --git a/Documentation/sound/alsa/compress_offload.txt b/Documentation/sound/alsa/compress_offload.txt
new file mode 100644
index 00000000000..c83a835350f
--- /dev/null
+++ b/Documentation/sound/alsa/compress_offload.txt
@@ -0,0 +1,188 @@
+                compress_offload.txt
+                =====================
+        Pierre-Louis.Bossart <pierre-louis.bossart@linux.intel.com>
+                Vinod Koul <vinod.koul@linux.intel.com>
+Overview
+Since its early days, the ALSA API was defined with PCM support or
+constant bitrates payloads such as IEC61937 in mind. Arguments and
+returned values in frames are the norm, making it a challenge to
+extend the existing API to compressed data streams.
+In recent years, audio digital signal processors (DSP) were integrated
+in system-on-chip designs, and DSPs are also integrated in audio
+codecs. Processing compressed data on such DSPs results in a dramatic
+reduction of power consumption compared to host-based
+processing. Support for such hardware has not been very good in Linux,
+mostly because of a lack of a generic API available in the mainline
+kernel.
+Rather than requiring a compability break with an API change of the
+ALSA PCM interface, a new 'Compressed Data' API is introduced to
+provide a control and data-streaming interface for audio DSPs.
+The design of this API was inspired by the 2-year experience with the
+Intel Moorestown SOC, with many corrections required to upstream the
+API in the mainline kernel instead of the staging tree and make it
+usable by others.
+Requirements
+The main requirements are:
+- separation between byte counts and time. Compressed formats may have
+  a header per file, per frame, or no header at all. The payload size
+  may vary from frame-to-frame. As a result, it is not possible to
+  estimate reliably the duration of audio buffers when handling
+  compressed data. Dedicated mechanisms are required to allow for
+  reliable audio-video synchronization, which requires precise
+  reporting of the number of samples rendered at any given time.
+- Handling of multiple formats. PCM data only requires a specification
+  of the sampling rate, number of channels and bits per sample. In
+  contrast, compressed data comes in a variety of formats. Audio DSPs
+  may also provide support for a limited number of audio encoders and
+  decoders embedded in firmware, or may support more choices through
+  dynamic download of libraries.
+- Focus on main formats. This API provides support for the most
+  popular formats used for audio and video capture and playback. It is
+  likely that as audio compression technology advances, new formats
+  will be added.
+- Handling of multiple configurations. Even for a given format like
+  AAC, some implementations may support AAC multichannel but HE-AAC
+  stereo. Likewise WMA10 level M3 may require too much memory and cpu
+  cycles. The new API needs to provide a generic way of listing these
+  formats.
+- Rendering/Grabbing only. This API does not provide any means of
+  hardware acceleration, where PCM samples are provided back to
+  user-space for additional processing. This API focuses instead on
+  streaming compressed data to a DSP, with the assumption that the
+  decoded samples are routed to a physical output or logical back-end.
+ - Complexity hiding. Existing user-space multimedia frameworks all
+  have existing enums/structures for each compressed format. This new
+  API assumes the existence of a platform-specific compatibility layer
+  to expose, translate and make use of the capabilities of the audio
+  DSP, eg. Android HAL or PulseAudio sinks. By construction, regular
+  applications are not supposed to make use of this API.
+Design
+The new API shares a number of concepts with with the PCM API for flow
+control. Start, pause, resume, drain and stop commands have the same
+semantics no matter what the content is.
+The concept of memory ring buffer divided in a set of fragments is
+borrowed from the ALSA PCM API. However, only sizes in bytes can be
+specified.
+Seeks/trick modes are assumed to be handled by the host.
+The notion of rewinds/forwards is not supported. Data committed to the
+ring buffer cannot be invalidated, except when dropping all buffers.
+The Compressed Data API does not make any assumptions on how the data
+is transmitted to the audio DSP. DMA transfers from main memory to an
+embedded audio cluster or to a SPI interface for external DSPs are
+possible. As in the ALSA PCM case, a core set of routines is exposed;
+each driver implementer will have to write support for a set of
+mandatory routines and possibly make use of optional ones.
+The main additions are
+- get_caps
+This routine returns the list of audio formats supported. Querying the
+codecs on a capture stream will return encoders, decoders will be
+listed for playback streams.
+- get_codec_caps For each codec, this routine returns a list of
+capabilities. The intent is to make sure all the capabilities
+correspond to valid settings, and to minimize the risks of
+configuration failures. For example, for a complex codec such as AAC,
+the number of channels supported may depend on a specific profile. If
+the capabilities were exposed with a single descriptor, it may happen
+that a specific combination of profiles/channels/formats may not be
+supported. Likewise, embedded DSPs have limited memory and cpu cycles,
+it is likely that some implementations make the list of capabilities
+dynamic and dependent on existing workloads. In addition to codec
+settings, this routine returns the minimum buffer size handled by the
+implementation. This information can be a function of the DMA buffer
+sizes, the number of bytes required to synchronize, etc, and can be
+used by userspace to define how much needs to be written in the ring
+buffer before playback can start.
+- set_params
+This routine sets the configuration chosen for a specific codec. The
+most important field in the parameters is the codec type; in most
+cases decoders will ignore other fields, while encoders will strictly
+comply to the settings
+- get_params
+This routines returns the actual settings used by the DSP. Changes to
+the settings should remain the exception.
+- get_timestamp
+The timestamp becomes a multiple field structure. It lists the number
+of bytes transferred, the number of samples processed and the number
+of samples rendered/grabbed. All these values can be used to determine
+the avarage bitrate, figure out if the ring buffer needs to be
+refilled or the delay due to decoding/encoding/io on the DSP.
+Note that the list of codecs/profiles/modes was derived from the
+OpenMAX AL specification instead of reinventing the wheel.
+Modifications include:
+- Addition of FLAC and IEC formats
+- Merge of encoder/decoder capabilities
+- Profiles/modes listed as bitmasks to make descriptors more compact
+- Addition of set_params for decoders (missing in OpenMAX AL)
+- Addition of AMR/AMR-WB encoding modes (missing in OpenMAX AL)
+- Addition of format information for WMA
+- Addition of encoding options when required (derived from OpenMAX IL)
+- Addition of rateControlSupported (missing in OpenMAX AL)
+Not supported:
+- Support for VoIP/circuit-switched calls is not the target of this
+  API. Support for dynamic bit-rate changes would require a tight
+  coupling between the DSP and the host stack, limiting power savings.
+- Packet-loss concealment is not supported. This would require an
+  additional interface to let the decoder synthesize data when frames
+  are lost during transmission. This may be added in the future.
+- Volume control/routing is not handled by this API. Devices exposing a
+  compressed data interface will be considered as regular ALSA devices;
+  volume changes and routing information will be provided with regular
+  ALSA kcontrols.
+- Embedded audio effects. Such effects should be enabled in the same
+  manner, no matter if the input was PCM or compressed.
+- multichannel IEC encoding. Unclear if this is required.
+- Encoding/decoding acceleration is not supported as mentioned
+  above. It is possible to route the output of a decoder to a capture
+  stream, or even implement transcoding capabilities. This routing
+  would be enabled with ALSA kcontrols.
+- Audio policy/resource management. This API does not provide any
+  hooks to query the utilization of the audio DSP, nor any premption
+  mechanisms.
+- No notion of underun/overrun. Since the bytes written are compressed
+  in nature and data written/read doesn't translate directly to
+  rendered output in time, this does not deal with underrun/overun and
+  maybe dealt in user-library
+Credits:
+- Mark Brown and Liam Girdwood for discussions on the need for this API
+- Harsha Priya for her work on intel_sst compressed API
+- Rakesh Ughreja for valuable feedback
+- Sing Nallasellan, Sikkandar Madar and Prasanna Samaga for
+  demonstrating and quantifying the benefits of audio offload on a
+  real platform.
diff --git a/Documentation/sysctl/kernel.txt b/Documentation/sysctl/kernel.txt
index 1f2463671a1..8c20fbd8b42 100644
--- a/Documentation/sysctl/kernel.txt
+++ b/Documentation/sysctl/kernel.txt
@@ -49,6 +49,7 @@ show up in /proc/sys/kernel:
 - panic
 - panic_on_oops
 - panic_on_unrecovered_nmi
+- panic_on_stackoverflow
 - pid_max
 - powersave-nap               [ PPC only ]
 - printk
@@ -393,6 +394,19 @@ Controls the kernel's behaviour when an oops or BUG is encountered.
 ==============================================================
+panic_on_stackoverflow:
+Controls the kernel's behavior when detecting the overflows of
+kernel, IRQ and exception stacks except a user stack.
+This file shows up if CONFIG_DEBUG_STACKOVERFLOW is enabled.
+0: try to continue operation.
+1: panic immediately.
+==============================================================
 pid_max:
 PID allocation wrap value.  When the kernel's next PID value
@@ -401,6 +415,14 @@ PIDs of value pid_max or larger are not allocated.
 ==============================================================
+ns_last_pid:
+The last pid allocated in the current (the one task using this sysctl
+lives in) pid namespace. When selecting a pid for a next task on fork
+kernel tries to allocate a number starting from this one.
+==============================================================
 powersave-nap: (PPC only)
 If set, Linux-PPC will use the 'nap' mode of powersaving,
diff --git a/Documentation/trace/events-kmem.txt b/Documentation/trace/events-kmem.txt
index aa82ee4a5a8..19480041006 100644
--- a/Documentation/trace/events-kmem.txt
+++ b/Documentation/trace/events-kmem.txt
@@ -40,8 +40,8 @@ but the call_site can usually be used to extrapolate that information.
 ==================
 mm_page_alloc             page=%p pfn=%lu order=%d migratetype=%d gfp_flags=%s
 mm_page_alloc_zone_locked page=%p pfn=%lu order=%u migratetype=%d cpu=%d percpu_refill=%d
-mm_page_free_direct       page=%p pfn=%lu order=%d
+mm_page_free              page=%p pfn=%lu order=%d
-mm_pagevec_free           page=%p pfn=%lu order=%d cold=%d
+mm_page_free_batched      page=%p pfn=%lu order=%d cold=%d
 These four events deal with page allocation and freeing. mm_page_alloc is
 a simple indicator of page allocator activity. Pages may be allocated from
@@ -53,13 +53,13 @@ amounts of activity imply high activity on the zone->lock. Taking this lock
 impairs performance by disabling interrupts, dirtying cache lines between
 CPUs and serialising many CPUs.
-When a page is freed directly by the caller, the mm_page_free_direct event
+When a page is freed directly by the caller, the only mm_page_free event
 is triggered. Significant amounts of activity here could indicate that the
 callers should be batching their activities.
-When pages are freed using a pagevec, the mm_pagevec_free is
+When pages are freed in batch, the also mm_page_free_batched is triggered.
-triggered. Broadly speaking, pages are taken off the LRU lock in bulk and
+Broadly speaking, pages are taken off the LRU lock in bulk and
-freed in batch with a pagevec. Significant amounts of activity here could
+freed in batch with a page list. Significant amounts of activity here could
 indicate that the system is under memory pressure and can also indicate
 contention on the zone->lru_lock.
diff --git a/Documentation/trace/events.txt b/Documentation/trace/events.txt
index b510564aac7..bb24c2a0e87 100644
--- a/Documentation/trace/events.txt
+++ b/Documentation/trace/events.txt
@@ -191,8 +191,6 @@ And for string fields they are:
 Currently, only exact string matches are supported.
-Currently, the maximum number of predicates in a filter is 16.
 5.2 Setting filters
 -------------------
diff --git a/Documentation/trace/postprocess/trace-pagealloc-postprocess.pl b/Documentation/trace/postprocess/trace-pagealloc-postprocess.pl
index 7df50e8cf4d..0a120aae33c 100644
--- a/Documentation/trace/postprocess/trace-pagealloc-postprocess.pl
+++ b/Documentation/trace/postprocess/trace-pagealloc-postprocess.pl
@@ -17,8 +17,8 @@ use Getopt::Long;
 # Tracepoint events
 use constant MM_PAGE_ALLOC              => 1;
-use constant MM_PAGE_FREE_DIRECT        => 2;
+use constant MM_PAGE_FREE               => 2;
-use constant MM_PAGEVEC_FREE            => 3;
+use constant MM_PAGE_FREE_BATCHED       => 3;
 use constant MM_PAGE_PCPU_DRAIN         => 4;
 use constant MM_PAGE_ALLOC_ZONE_LOCKED  => 5;
 use constant MM_PAGE_ALLOC_EXTFRAG      => 6;
@@ -223,10 +223,10 @@ EVENT_PROCESS:
                # Perl Switch() sucks majorly
                if ($tracepoint eq "mm_page_alloc") {
                        $perprocesspid{$process_pid}->{MM_PAGE_ALLOC}++;
-                } elsif ($tracepoint eq "mm_page_free_direct") {
+                } elsif ($tracepoint eq "mm_page_free") {
-                        $perprocesspid{$process_pid}->{MM_PAGE_FREE_DIRECT}++;
+                        $perprocesspid{$process_pid}->{MM_PAGE_FREE}++
-                } elsif ($tracepoint eq "mm_pagevec_free") {
+                } elsif ($tracepoint eq "mm_page_free_batched") {
-                        $perprocesspid{$process_pid}->{MM_PAGEVEC_FREE}++;
+                        $perprocesspid{$process_pid}->{MM_PAGE_FREE_BATCHED}++;
                } elsif ($tracepoint eq "mm_page_pcpu_drain") {
                        $perprocesspid{$process_pid}->{MM_PAGE_PCPU_DRAIN}++;
                        $perprocesspid{$process_pid}->{STATE_PCPU_PAGES_DRAINED}++;
@@ -336,8 +336,8 @@ sub dump_stats {
                        $process_pid,
                        $stats{$process_pid}->{MM_PAGE_ALLOC},
                        $stats{$process_pid}->{MM_PAGE_ALLOC_ZONE_LOCKED},
-                        $stats{$process_pid}->{MM_PAGE_FREE_DIRECT},
+                        $stats{$process_pid}->{MM_PAGE_FREE},
-                        $stats{$process_pid}->{MM_PAGEVEC_FREE},
+                        $stats{$process_pid}->{MM_PAGE_FREE_BATCHED},
                        $stats{$process_pid}->{MM_PAGE_PCPU_DRAIN},
                        $stats{$process_pid}->{HIGH_PCPU_DRAINS},
                        $stats{$process_pid}->{HIGH_PCPU_REFILLS},
@@ -364,8 +364,8 @@ sub aggregate_perprocesspid() {
                $perprocess{$process}->{MM_PAGE_ALLOC} += $perprocesspid{$process_pid}->{MM_PAGE_ALLOC};
                $perprocess{$process}->{MM_PAGE_ALLOC_ZONE_LOCKED} += $perprocesspid{$process_pid}->{MM_PAGE_ALLOC_ZONE_LOCKED};
-                $perprocess{$process}->{MM_PAGE_FREE_DIRECT} += $perprocesspid{$process_pid}->{MM_PAGE_FREE_DIRECT};
+                $perprocess{$process}->{MM_PAGE_FREE} += $perprocesspid{$process_pid}->{MM_PAGE_FREE};
-                $perprocess{$process}->{MM_PAGEVEC_FREE} += $perprocesspid{$process_pid}->{MM_PAGEVEC_FREE};
+                $perprocess{$process}->{MM_PAGE_FREE_BATCHED} += $perprocesspid{$process_pid}->{MM_PAGE_FREE_BATCHED};
                $perprocess{$process}->{MM_PAGE_PCPU_DRAIN} += $perprocesspid{$process_pid}->{MM_PAGE_PCPU_DRAIN};
                $perprocess{$process}->{HIGH_PCPU_DRAINS} += $perprocesspid{$process_pid}->{HIGH_PCPU_DRAINS};
                $perprocess{$process}->{HIGH_PCPU_REFILLS} += $perprocesspid{$process_pid}->{HIGH_PCPU_REFILLS};
diff --git a/Documentation/trace/tracepoint-analysis.txt b/Documentation/trace/tracepoint-analysis.txt
index 87bee3c129b..058cc6c9dc5 100644
--- a/Documentation/trace/tracepoint-analysis.txt
+++ b/Documentation/trace/tracepoint-analysis.txt
@@ -93,14 +93,14 @@ By specifying the -a switch and analysing sleep, the system-wide events
 for a duration of time can be examined.
 $ perf stat -a \
-        -e kmem:mm_page_alloc -e kmem:mm_page_free_direct \
+        -e kmem:mm_page_alloc -e kmem:mm_page_free \
-        -e kmem:mm_pagevec_free \
+        -e kmem:mm_page_free_batched \
        sleep 10
 Performance counter stats for 'sleep 10':
           9630  kmem:mm_page_alloc
-           2143  kmem:mm_page_free_direct
+           2143  kmem:mm_page_free
-           7424  kmem:mm_pagevec_free
+           7424  kmem:mm_page_free_batched
   10.002577764  seconds time elapsed
@@ -119,15 +119,15 @@ basis using set_ftrace_pid.
 Events can be activated and tracked for the duration of a process on a local
 basis using PCL such as follows.
-  $ perf stat -e kmem:mm_page_alloc -e kmem:mm_page_free_direct \
+  $ perf stat -e kmem:mm_page_alloc -e kmem:mm_page_free \
-                 -e kmem:mm_pagevec_free ./hackbench 10
+                 -e kmem:mm_page_free_batched ./hackbench 10
  Time: 0.909
    Performance counter stats for './hackbench 10':
          17803  kmem:mm_page_alloc
-          12398  kmem:mm_page_free_direct
+          12398  kmem:mm_page_free
-           4827  kmem:mm_pagevec_free
+           4827  kmem:mm_page_free_batched
    0.973913387  seconds time elapsed
@@ -146,8 +146,8 @@ to know what the standard deviation is. By and large, this is left to the
 performance analyst to do it by hand. In the event that the discrete event
 occurrences are useful to the performance analyst, then perf can be used.
-  $ perf stat --repeat 5 -e kmem:mm_page_alloc -e kmem:mm_page_free_direct
+  $ perf stat --repeat 5 -e kmem:mm_page_alloc -e kmem:mm_page_free
-                        -e kmem:mm_pagevec_free ./hackbench 10
+                        -e kmem:mm_page_free_batched ./hackbench 10
  Time: 0.890
  Time: 0.895
  Time: 0.915
@@ -157,8 +157,8 @@ occurrences are useful to the performance analyst, then perf can be used.
   Performance counter stats for './hackbench 10' (5 runs):
          16630  kmem:mm_page_alloc         ( +-   3.542% )
-          11486  kmem:mm_page_free_direct   ( +-   4.771% )
+          11486  kmem:mm_page_free          ( +-   4.771% )
-           4730  kmem:mm_pagevec_free       ( +-   2.325% )
+           4730  kmem:mm_page_free_batched  ( +-   2.325% )
    0.982653002  seconds time elapsed   ( +-   1.448% )
@@ -168,15 +168,15 @@ aggregation of discrete events, then a script would need to be developed.
 Using --repeat, it is also possible to view how events are fluctuating over
 time on a system-wide basis using -a and sleep.
-  $ perf stat -e kmem:mm_page_alloc -e kmem:mm_page_free_direct \
+  $ perf stat -e kmem:mm_page_alloc -e kmem:mm_page_free \
-                -e kmem:mm_pagevec_free \
+                -e kmem:mm_page_free_batched \
                -a --repeat 10 \
                sleep 1
  Performance counter stats for 'sleep 1' (10 runs):
           1066  kmem:mm_page_alloc         ( +-  26.148% )
-            182  kmem:mm_page_free_direct   ( +-   5.464% )
+            182  kmem:mm_page_free          ( +-   5.464% )
-            890  kmem:mm_pagevec_free       ( +-  30.079% )
+            890  kmem:mm_page_free_batched  ( +-  30.079% )
    1.002251757  seconds time elapsed   ( +-   0.005% )
@@ -220,8 +220,8 @@ were generating events within the kernel. To begin this sort of analysis, the
 data must be recorded. At the time of writing, this required root:
  $ perf record -c 1 \
-        -e kmem:mm_page_alloc -e kmem:mm_page_free_direct \
+        -e kmem:mm_page_alloc -e kmem:mm_page_free \
-        -e kmem:mm_pagevec_free \
+        -e kmem:mm_page_free_batched \
        ./hackbench 10
  Time: 0.894
  [ perf record: Captured and wrote 0.733 MB perf.data (~32010 samples) ]
@@ -260,8 +260,8 @@ noticed that X was generating an insane amount of page allocations so let's look
 at it:
  $ perf record -c 1 -f \
-                -e kmem:mm_page_alloc -e kmem:mm_page_free_direct \
+                -e kmem:mm_page_alloc -e kmem:mm_page_free \
-                -e kmem:mm_pagevec_free \
+                -e kmem:mm_page_free_batched \
                -p `pidof X`
 This was interrupted after a few seconds and
diff --git a/Documentation/usb/usbmon.txt b/Documentation/usb/usbmon.txt
index a4efa0462f0..5335fa8b06e 100644
--- a/Documentation/usb/usbmon.txt
+++ b/Documentation/usb/usbmon.txt
@@ -47,10 +47,11 @@ This allows to filter away annoying devices that talk continuously.
 2. Find which bus connects to the desired device
-Run "cat /proc/bus/usb/devices", and find the T-line which corresponds to
+Run "cat /sys/kernel/debug/usb/devices", and find the T-line which corresponds
-the device. Usually you do it by looking for the vendor string. If you have
+to the device. Usually you do it by looking for the vendor string. If you have
-many similar devices, unplug one and compare two /proc/bus/usb/devices outputs.
+many similar devices, unplug one and compare the two
-The T-line will have a bus number. Example:
+/sys/kernel/debug/usb/devices outputs. The T-line will have a bus number.
+Example:
 T:  Bus=03 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#=  2 Spd=12  MxCh= 0
 D:  Ver= 1.10 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 8 #Cfgs=  1
@@ -58,7 +59,10 @@ P:  Vendor=0557 ProdID=2004 Rev= 1.00
 S:  Manufacturer=ATEN
 S:  Product=UC100KM V2.00
-Bus=03 means it's bus 3.
+"Bus=03" means it's bus 3. Alternatively, you can look at the output from
+"lsusb" and get the bus number from the appropriate line. Example:
+Bus 003 Device 002: ID 0557:2004 ATEN UC100KM V2.00
 3. Start 'cat'
diff --git a/Documentation/vgaarbiter.txt b/Documentation/vgaarbiter.txt
index b7d401e0eae..014423e2824 100644
--- a/Documentation/vgaarbiter.txt
+++ b/Documentation/vgaarbiter.txt
@@ -177,7 +177,7 @@ II. Credits
 Benjamin Herrenschmidt (IBM?) started this work when he discussed such design
 with the Xorg community in 2005 [1, 2]. In the end of 2007, Paulo Zanoni and
-Tiago Vignatti (both of C3SL/Federal University of Paran�) proceeded his work
+Tiago Vignatti (both of C3SL/Federal University of Paraná) proceeded his work
 enhancing the kernel code to adapt as a kernel module and also did the
 implementation of the user space side [3]. Now (2009) Tiago Vignatti and Dave
 Airlie finally put this work in shape and queued to Jesse Barnes' PCI tree.
diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt
index e2a4b528736..e1d94bf4056 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -1466,6 +1466,31 @@ is supported; 2 if the processor requires all virtual machines to have
 an RMA, or 1 if the processor can use an RMA but doesn't require it,
 because it supports the Virtual RMA (VRMA) facility.
+4.64 KVM_NMI
+Capability: KVM_CAP_USER_NMI
+Architectures: x86
+Type: vcpu ioctl
+Parameters: none
+Returns: 0 on success, -1 on error
+Queues an NMI on the thread's vcpu.  Note this is well defined only
+when KVM_CREATE_IRQCHIP has not been called, since this is an interface
+between the virtual cpu core and virtual local APIC.  After KVM_CREATE_IRQCHIP
+has been called, this interface is completely emulated within the kernel.
+To use this to emulate the LINT1 input with KVM_CREATE_IRQCHIP, use the
+following algorithm:
+  - pause the vpcu
+  - read the local APIC's state (KVM_GET_LAPIC)
+  - check whether changing LINT1 will queue an NMI (see the LVT entry for LINT1)
+  - if so, issue KVM_NMI
+  - resume the vcpu
+Some guests configure the LINT1 NMI input to cause a panic, aiding in
+debugging.
 5. The kvm_run structure
 Application code obtains a pointer to the kvm_run structure by
diff --git a/Documentation/virtual/lguest/lguest.c b/Documentation/virtual/lguest/lguest.c
deleted file mode 100644
index c095d79cae7..00000000000
--- a/Documentation/virtual/lguest/lguest.c
+++ /dev/null
@@ -1,2065 +0,0 @@
-/*P:100
- * This is the Launcher code, a simple program which lays out the "physical"
- * memory for the new Guest by mapping the kernel image and the virtual
- * devices, then opens /dev/lguest to tell the kernel about the Guest and
- * control it.
-:*/
-#define _LARGEFILE64_SOURCE
-#define _GNU_SOURCE
-#include <stdio.h>
-#include <string.h>
-#include <unistd.h>
-#include <err.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <elf.h>
-#include <sys/mman.h>
-#include <sys/param.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/wait.h>
-#include <sys/eventfd.h>
-#include <fcntl.h>
-#include <stdbool.h>
-#include <errno.h>
-#include <ctype.h>
-#include <sys/socket.h>
-#include <sys/ioctl.h>
-#include <sys/time.h>
-#include <time.h>
-#include <netinet/in.h>
-#include <net/if.h>
-#include <linux/sockios.h>
-#include <linux/if_tun.h>
-#include <sys/uio.h>
-#include <termios.h>
-#include <getopt.h>
-#include <assert.h>
-#include <sched.h>
-#include <limits.h>
-#include <stddef.h>
-#include <signal.h>
-#include <pwd.h>
-#include <grp.h>
-#include <linux/virtio_config.h>
-#include <linux/virtio_net.h>
-#include <linux/virtio_blk.h>
-#include <linux/virtio_console.h>
-#include <linux/virtio_rng.h>
-#include <linux/virtio_ring.h>
-#include <asm/bootparam.h>
-#include "../../../include/linux/lguest_launcher.h"
-/*L:110
- * We can ignore the 43 include files we need for this program, but I do want
- * to draw attention to the use of kernel-style types.
- *
- * As Linus said, "C is a Spartan language, and so should your naming be."  I
- * like these abbreviations, so we define them here.  Note that u64 is always
- * unsigned long long, which works on all Linux systems: this means that we can
- * use %llu in printf for any u64.
- */
-typedef unsigned long long u64;
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-/*:*/
-#define BRIDGE_PFX "bridge:"
-#ifndef SIOCBRADDIF
-#define SIOCBRADDIF     0x89a2          /* add interface to bridge      */
-#endif
-/* We can have up to 256 pages for devices. */
-#define DEVICE_PAGES 256
-/* This will occupy 3 pages: it must be a power of 2. */
-#define VIRTQUEUE_NUM 256
-/*L:120
- * verbose is both a global flag and a macro.  The C preprocessor allows
- * this, and although I wouldn't recommend it, it works quite nicely here.
- */
-static bool verbose;
-#define verbose(args...) \
-        do { if (verbose) printf(args); } while(0)
-/*:*/
-/* The pointer to the start of guest memory. */
-static void *guest_base;
-/* The maximum guest physical address allowed, and maximum possible. */
-static unsigned long guest_limit, guest_max;
-/* The /dev/lguest file descriptor. */
-static int lguest_fd;
-/* a per-cpu variable indicating whose vcpu is currently running */
-static unsigned int __thread cpu_id;
-/* This is our list of devices. */
-struct device_list {
-        /* Counter to assign interrupt numbers. */
-        unsigned int next_irq;
-        /* Counter to print out convenient device numbers. */
-        unsigned int device_num;
-        /* The descriptor page for the devices. */
-        u8 *descpage;
-        /* A single linked list of devices. */
-        struct device *dev;
-        /* And a pointer to the last device for easy append. */
-        struct device *lastdev;
-};
-/* The list of Guest devices, based on command line arguments. */
-static struct device_list devices;
-/* The device structure describes a single device. */
-struct device {
-        /* The linked-list pointer. */
-        struct device *next;
-        /* The device's descriptor, as mapped into the Guest. */
-        struct lguest_device_desc *desc;
-        /* We can't trust desc values once Guest has booted: we use these. */
-        unsigned int feature_len;
-        unsigned int num_vq;
-        /* The name of this device, for --verbose. */
-        const char *name;
-        /* Any queues attached to this device */
-        struct virtqueue *vq;
-        /* Is it operational */
-        bool running;
-        /* Device-specific data. */
-        void *priv;
-};
-/* The virtqueue structure describes a queue attached to a device. */
-struct virtqueue {
-        struct virtqueue *next;
-        /* Which device owns me. */
-        struct device *dev;
-        /* The configuration for this queue. */
-        struct lguest_vqconfig config;
-        /* The actual ring of buffers. */
-        struct vring vring;
-        /* Last available index we saw. */
-        u16 last_avail_idx;
-        /* How many are used since we sent last irq? */
-        unsigned int pending_used;
-        /* Eventfd where Guest notifications arrive. */
-        int eventfd;
-        /* Function for the thread which is servicing this virtqueue. */
-        void (*service)(struct virtqueue *vq);
-        pid_t thread;
-};
-/* Remember the arguments to the program so we can "reboot" */
-static char **main_args;
-/* The original tty settings to restore on exit. */
-static struct termios orig_term;
-/*
- * We have to be careful with barriers: our devices are all run in separate
- * threads and so we need to make sure that changes visible to the Guest happen
- * in precise order.
- */
-#define wmb() __asm__ __volatile__("" : : : "memory")
-#define mb() __asm__ __volatile__("" : : : "memory")
-/*
- * Convert an iovec element to the given type.
- *
- * This is a fairly ugly trick: we need to know the size of the type and
- * alignment requirement to check the pointer is kosher.  It's also nice to
- * have the name of the type in case we report failure.
- *
- * Typing those three things all the time is cumbersome and error prone, so we
- * have a macro which sets them all up and passes to the real function.
- */
-#define convert(iov, type) \
-        ((type *)_convert((iov), sizeof(type), __alignof__(type), #type))
-static void *_convert(struct iovec *iov, size_t size, size_t align,
-                      const char *name)
-{
-        if (iov->iov_len != size)
-                errx(1, "Bad iovec size %zu for %s", iov->iov_len, name);
-        if ((unsigned long)iov->iov_base % align != 0)
-                errx(1, "Bad alignment %p for %s", iov->iov_base, name);
-        return iov->iov_base;
-}
-/* Wrapper for the last available index.  Makes it easier to change. */
-#define lg_last_avail(vq)       ((vq)->last_avail_idx)
-/*
- * The virtio configuration space is defined to be little-endian.  x86 is
- * little-endian too, but it's nice to be explicit so we have these helpers.
- */
-#define cpu_to_le16(v16) (v16)
-#define cpu_to_le32(v32) (v32)
-#define cpu_to_le64(v64) (v64)
-#define le16_to_cpu(v16) (v16)
-#define le32_to_cpu(v32) (v32)
-#define le64_to_cpu(v64) (v64)
-/* Is this iovec empty? */
-static bool iov_empty(const struct iovec iov[], unsigned int num_iov)
-{
-        unsigned int i;
-        for (i = 0; i < num_iov; i++)
-                if (iov[i].iov_len)
-                        return false;
-        return true;
-}
-/* Take len bytes from the front of this iovec. */
-static void iov_consume(struct iovec iov[], unsigned num_iov, unsigned len)
-{
-        unsigned int i;
-        for (i = 0; i < num_iov; i++) {
-                unsigned int used;
-                used = iov[i].iov_len < len ? iov[i].iov_len : len;
-                iov[i].iov_base += used;
-                iov[i].iov_len -= used;
-                len -= used;
-        }
-        assert(len == 0);
-}
-/* The device virtqueue descriptors are followed by feature bitmasks. */
-static u8 *get_feature_bits(struct device *dev)
-{
-        return (u8 *)(dev->desc + 1)
-                + dev->num_vq * sizeof(struct lguest_vqconfig);
-}
-/*L:100
- * The Launcher code itself takes us out into userspace, that scary place where
- * pointers run wild and free!  Unfortunately, like most userspace programs,
- * it's quite boring (which is why everyone likes to hack on the kernel!).
- * Perhaps if you make up an Lguest Drinking Game at this point, it will get
- * you through this section.  Or, maybe not.
- *
- * The Launcher sets up a big chunk of memory to be the Guest's "physical"
- * memory and stores it in "guest_base".  In other words, Guest physical ==
- * Launcher virtual with an offset.
- *
- * This can be tough to get your head around, but usually it just means that we
- * use these trivial conversion functions when the Guest gives us its
- * "physical" addresses:
- */
-static void *from_guest_phys(unsigned long addr)
-{
-        return guest_base + addr;
-}
-static unsigned long to_guest_phys(const void *addr)
-{
-        return (addr - guest_base);
-}
-/*L:130
- * Loading the Kernel.
- *
- * We start with couple of simple helper routines.  open_or_die() avoids
- * error-checking code cluttering the callers:
- */
-static int open_or_die(const char *name, int flags)
-{
-        int fd = open(name, flags);
-        if (fd < 0)
-                err(1, "Failed to open %s", name);
-        return fd;
-}
-/* map_zeroed_pages() takes a number of pages. */
-static void *map_zeroed_pages(unsigned int num)
-{
-        int fd = open_or_die("/dev/zero", O_RDONLY);
-        void *addr;
-        /*
-         * We use a private mapping (ie. if we write to the page, it will be
-         * copied). We allocate an extra two pages PROT_NONE to act as guard
-         * pages against read/write attempts that exceed allocated space.
-         */
-        addr = mmap(NULL, getpagesize() * (num+2),
-                    PROT_NONE, MAP_PRIVATE, fd, 0);
-        if (addr == MAP_FAILED)
-                err(1, "Mmapping %u pages of /dev/zero", num);
-        if (mprotect(addr + getpagesize(), getpagesize() * num,
-                     PROT_READ|PROT_WRITE) == -1)
-                err(1, "mprotect rw %u pages failed", num);
-        /*
-         * One neat mmap feature is that you can close the fd, and it
-         * stays mapped.
-         */
-        close(fd);
-        /* Return address after PROT_NONE page */
-        return addr + getpagesize();
-}
-/* Get some more pages for a device. */
-static void *get_pages(unsigned int num)
-{
-        void *addr = from_guest_phys(guest_limit);
-        guest_limit += num * getpagesize();
-        if (guest_limit > guest_max)
-                errx(1, "Not enough memory for devices");
-        return addr;
-}
-/*
- * This routine is used to load the kernel or initrd.  It tries mmap, but if
- * that fails (Plan 9's kernel file isn't nicely aligned on page boundaries),
- * it falls back to reading the memory in.
- */
-static void map_at(int fd, void *addr, unsigned long offset, unsigned long len)
-{
-        ssize_t r;
-        /*
-         * We map writable even though for some segments are marked read-only.
-         * The kernel really wants to be writable: it patches its own
-         * instructions.
-         *
-         * MAP_PRIVATE means that the page won't be copied until a write is
-         * done to it.  This allows us to share untouched memory between
-         * Guests.
-         */
-        if (mmap(addr, len, PROT_READ|PROT_WRITE,
-                 MAP_FIXED|MAP_PRIVATE, fd, offset) != MAP_FAILED)
-                return;
-        /* pread does a seek and a read in one shot: saves a few lines. */
-        r = pread(fd, addr, len, offset);
-        if (r != len)
-                err(1, "Reading offset %lu len %lu gave %zi", offset, len, r);
-}
-/*
- * This routine takes an open vmlinux image, which is in ELF, and maps it into
- * the Guest memory.  ELF = Embedded Linking Format, which is the format used
- * by all modern binaries on Linux including the kernel.
- *
- * The ELF headers give *two* addresses: a physical address, and a virtual
- * address.  We use the physical address; the Guest will map itself to the
- * virtual address.
- *
- * We return the starting address.
- */
-static unsigned long map_elf(int elf_fd, const Elf32_Ehdr *ehdr)
-{
-        Elf32_Phdr phdr[ehdr->e_phnum];
-        unsigned int i;
-        /*
-         * Sanity checks on the main ELF header: an x86 executable with a
-         * reasonable number of correctly-sized program headers.
-         */
-        if (ehdr->e_type != ET_EXEC
-            || ehdr->e_machine != EM_386
-            || ehdr->e_phentsize != sizeof(Elf32_Phdr)
-            || ehdr->e_phnum < 1 || ehdr->e_phnum > 65536U/sizeof(Elf32_Phdr))
-                errx(1, "Malformed elf header");
-        /*
-         * An ELF executable contains an ELF header and a number of "program"
-         * headers which indicate which parts ("segments") of the program to
-         * load where.
-         */
-        /* We read in all the program headers at once: */
-        if (lseek(elf_fd, ehdr->e_phoff, SEEK_SET) < 0)
-                err(1, "Seeking to program headers");
-        if (read(elf_fd, phdr, sizeof(phdr)) != sizeof(phdr))
-                err(1, "Reading program headers");
-        /*
-         * Try all the headers: there are usually only three.  A read-only one,
-         * a read-write one, and a "note" section which we don't load.
-         */
-        for (i = 0; i < ehdr->e_phnum; i++) {
-                /* If this isn't a loadable segment, we ignore it */
-                if (phdr[i].p_type != PT_LOAD)
-                        continue;
-                verbose("Section %i: size %i addr %p\n",
-                        i, phdr[i].p_memsz, (void *)phdr[i].p_paddr);
-                /* We map this section of the file at its physical address. */
-                map_at(elf_fd, from_guest_phys(phdr[i].p_paddr),
-                       phdr[i].p_offset, phdr[i].p_filesz);
-        }
-        /* The entry point is given in the ELF header. */
-        return ehdr->e_entry;
-}
-/*L:150
- * A bzImage, unlike an ELF file, is not meant to be loaded.  You're supposed
- * to jump into it and it will unpack itself.  We used to have to perform some
- * hairy magic because the unpacking code scared me.
- *
- * Fortunately, Jeremy Fitzhardinge convinced me it wasn't that hard and wrote
- * a small patch to jump over the tricky bits in the Guest, so now we just read
- * the funky header so we know where in the file to load, and away we go!
- */
-static unsigned long load_bzimage(int fd)
-{
-        struct boot_params boot;
-        int r;
-        /* Modern bzImages get loaded at 1M. */
-        void *p = from_guest_phys(0x100000);
-        /*
-         * Go back to the start of the file and read the header.  It should be
-         * a Linux boot header (see Documentation/x86/boot.txt)
-         */
-        lseek(fd, 0, SEEK_SET);
-        read(fd, &boot, sizeof(boot));
-        /* Inside the setup_hdr, we expect the magic "HdrS" */
-        if (memcmp(&boot.hdr.header, "HdrS", 4) != 0)
-                errx(1, "This doesn't look like a bzImage to me");
-        /* Skip over the extra sectors of the header. */
-        lseek(fd, (boot.hdr.setup_sects+1) * 512, SEEK_SET);
-        /* Now read everything into memory. in nice big chunks. */
-        while ((r = read(fd, p, 65536)) > 0)
-                p += r;
-        /* Finally, code32_start tells us where to enter the kernel. */
-        return boot.hdr.code32_start;
-}
-/*L:140
- * Loading the kernel is easy when it's a "vmlinux", but most kernels
- * come wrapped up in the self-decompressing "bzImage" format.  With a little
- * work, we can load those, too.
- */
-static unsigned long load_kernel(int fd)
-{
-        Elf32_Ehdr hdr;
-        /* Read in the first few bytes. */
-        if (read(fd, &hdr, sizeof(hdr)) != sizeof(hdr))
-                err(1, "Reading kernel");
-        /* If it's an ELF file, it starts with "\177ELF" */
-        if (memcmp(hdr.e_ident, ELFMAG, SELFMAG) == 0)
-                return map_elf(fd, &hdr);
-        /* Otherwise we assume it's a bzImage, and try to load it. */
-        return load_bzimage(fd);
-}
-/*
- * This is a trivial little helper to align pages.  Andi Kleen hated it because
- * it calls getpagesize() twice: "it's dumb code."
- *
- * Kernel guys get really het up about optimization, even when it's not
- * necessary.  I leave this code as a reaction against that.
- */
-static inline unsigned long page_align(unsigned long addr)
-{
-        /* Add upwards and truncate downwards. */
-        return ((addr + getpagesize()-1) & ~(getpagesize()-1));
-}
-/*L:180
- * An "initial ram disk" is a disk image loaded into memory along with the
- * kernel which the kernel can use to boot from without needing any drivers.
- * Most distributions now use this as standard: the initrd contains the code to
- * load the appropriate driver modules for the current machine.
- *
- * Importantly, James Morris works for RedHat, and Fedora uses initrds for its
- * kernels.  He sent me this (and tells me when I break it).
- */
-static unsigned long load_initrd(const char *name, unsigned long mem)
-{
-        int ifd;
-        struct stat st;
-        unsigned long len;
-        ifd = open_or_die(name, O_RDONLY);
-        /* fstat() is needed to get the file size. */
-        if (fstat(ifd, &st) < 0)
-                err(1, "fstat() on initrd '%s'", name);
-        /*
-         * We map the initrd at the top of memory, but mmap wants it to be
-         * page-aligned, so we round the size up for that.
-         */
-        len = page_align(st.st_size);
-        map_at(ifd, from_guest_phys(mem - len), 0, st.st_size);
-        /*
-         * Once a file is mapped, you can close the file descriptor.  It's a
-         * little odd, but quite useful.
-         */
-        close(ifd);
-        verbose("mapped initrd %s size=%lu @ %p\n", name, len, (void*)mem-len);
-        /* We return the initrd size. */
-        return len;
-}
-/*:*/
-/*
- * Simple routine to roll all the commandline arguments together with spaces
- * between them.
- */
-static void concat(char *dst, char *args[])
-{
-        unsigned int i, len = 0;
-        for (i = 0; args[i]; i++) {
-                if (i) {
-                        strcat(dst+len, " ");
-                        len++;
-                }
-                strcpy(dst+len, args[i]);
-                len += strlen(args[i]);
-        }
-        /* In case it's empty. */
-        dst[len] = '\0';
-}
-/*L:185
- * This is where we actually tell the kernel to initialize the Guest.  We
- * saw the arguments it expects when we looked at initialize() in lguest_user.c:
- * the base of Guest "physical" memory, the top physical page to allow and the
- * entry point for the Guest.
- */
-static void tell_kernel(unsigned long start)
-{
-        unsigned long args[] = { LHREQ_INITIALIZE,
-                                 (unsigned long)guest_base,
-                                 guest_limit / getpagesize(), start };
-        verbose("Guest: %p - %p (%#lx)\n",
-                guest_base, guest_base + guest_limit, guest_limit);
-        lguest_fd = open_or_die("/dev/lguest", O_RDWR);
-        if (write(lguest_fd, args, sizeof(args)) < 0)
-                err(1, "Writing to /dev/lguest");
-}
-/*:*/
-/*L:200
- * Device Handling.
- *
- * When the Guest gives us a buffer, it sends an array of addresses and sizes.
- * We need to make sure it's not trying to reach into the Launcher itself, so
- * we have a convenient routine which checks it and exits with an error message
- * if something funny is going on:
- */
-static void *_check_pointer(unsigned long addr, unsigned int size,
-                            unsigned int line)
-{
-        /*
-         * Check if the requested address and size exceeds the allocated memory,
-         * or addr + size wraps around.
-         */
-        if ((addr + size) > guest_limit || (addr + size) < addr)
-                errx(1, "%s:%i: Invalid address %#lx", __FILE__, line, addr);
-        /*
-         * We return a pointer for the caller's convenience, now we know it's
-         * safe to use.
-         */
-        return from_guest_phys(addr);
-}
-/* A macro which transparently hands the line number to the real function. */
-#define check_pointer(addr,size) _check_pointer(addr, size, __LINE__)
-/*
- * Each buffer in the virtqueues is actually a chain of descriptors.  This
- * function returns the next descriptor in the chain, or vq->vring.num if we're
- * at the end.
- */
-static unsigned next_desc(struct vring_desc *desc,
-                          unsigned int i, unsigned int max)
-{
-        unsigned int next;
-        /* If this descriptor says it doesn't chain, we're done. */
-        if (!(desc[i].flags & VRING_DESC_F_NEXT))
-                return max;
-        /* Check they're not leading us off end of descriptors. */
-        next = desc[i].next;
-        /* Make sure compiler knows to grab that: we don't want it changing! */
-        wmb();
-        if (next >= max)
-                errx(1, "Desc next is %u", next);
-        return next;
-}
-/*
- * This actually sends the interrupt for this virtqueue, if we've used a
- * buffer.
- */
-static void trigger_irq(struct virtqueue *vq)
-{
-        unsigned long buf[] = { LHREQ_IRQ, vq->config.irq };
-        /* Don't inform them if nothing used. */
-        if (!vq->pending_used)
-                return;
-        vq->pending_used = 0;
-        /* If they don't want an interrupt, don't send one... */
-        if (vq->vring.avail->flags & VRING_AVAIL_F_NO_INTERRUPT) {
-                return;
-        }
-        /* Send the Guest an interrupt tell them we used something up. */
-        if (write(lguest_fd, buf, sizeof(buf)) != 0)
-                err(1, "Triggering irq %i", vq->config.irq);
-}
-/*
- * This looks in the virtqueue for the first available buffer, and converts
- * it to an iovec for convenient access.  Since descriptors consist of some
- * number of output then some number of input descriptors, it's actually two
- * iovecs, but we pack them into one and note how many of each there were.
- *
- * This function waits if necessary, and returns the descriptor number found.
- */
-static unsigned wait_for_vq_desc(struct virtqueue *vq,
-                                 struct iovec iov[],
-                                 unsigned int *out_num, unsigned int *in_num)
-{
-        unsigned int i, head, max;
-        struct vring_desc *desc;
-        u16 last_avail = lg_last_avail(vq);
-        /* There's nothing available? */
-        while (last_avail == vq->vring.avail->idx) {
-                u64 event;
-                /*
-                 * Since we're about to sleep, now is a good time to tell the
-                 * Guest about what we've used up to now.
-                 */
-                trigger_irq(vq);
-                /* OK, now we need to know about added descriptors. */
-                vq->vring.used->flags &= ~VRING_USED_F_NO_NOTIFY;
-                /*
-                 * They could have slipped one in as we were doing that: make
-                 * sure it's written, then check again.
-                 */
-                mb();
-                if (last_avail != vq->vring.avail->idx) {
-                        vq->vring.used->flags |= VRING_USED_F_NO_NOTIFY;
-                        break;
-                }
-                /* Nothing new?  Wait for eventfd to tell us they refilled. */
-                if (read(vq->eventfd, &event, sizeof(event)) != sizeof(event))
-                        errx(1, "Event read failed?");
-                /* We don't need to be notified again. */
-                vq->vring.used->flags |= VRING_USED_F_NO_NOTIFY;
-        }
-        /* Check it isn't doing very strange things with descriptor numbers. */
-        if ((u16)(vq->vring.avail->idx - last_avail) > vq->vring.num)
-                errx(1, "Guest moved used index from %u to %u",
-                     last_avail, vq->vring.avail->idx);
-        /*
-         * Grab the next descriptor number they're advertising, and increment
-         * the index we've seen.
-         */
-        head = vq->vring.avail->ring[last_avail % vq->vring.num];
-        lg_last_avail(vq)++;
-        /* If their number is silly, that's a fatal mistake. */
-        if (head >= vq->vring.num)
-                errx(1, "Guest says index %u is available", head);
-        /* When we start there are none of either input nor output. */
-        *out_num = *in_num = 0;
-        max = vq->vring.num;
-        desc = vq->vring.desc;
-        i = head;
-        /*
-         * If this is an indirect entry, then this buffer contains a descriptor
-         * table which we handle as if it's any normal descriptor chain.
-         */
-        if (desc[i].flags & VRING_DESC_F_INDIRECT) {
-                if (desc[i].len % sizeof(struct vring_desc))
-                        errx(1, "Invalid size for indirect buffer table");
-                max = desc[i].len / sizeof(struct vring_desc);
-                desc = check_pointer(desc[i].addr, desc[i].len);
-                i = 0;
-        }
-        do {
-                /* Grab the first descriptor, and check it's OK. */
-                iov[*out_num + *in_num].iov_len = desc[i].len;
-                iov[*out_num + *in_num].iov_base
-                        = check_pointer(desc[i].addr, desc[i].len);
-                /* If this is an input descriptor, increment that count. */
-                if (desc[i].flags & VRING_DESC_F_WRITE)
-                        (*in_num)++;
-                else {
-                        /*
-                         * If it's an output descriptor, they're all supposed
-                         * to come before any input descriptors.
-                         */
-                        if (*in_num)
-                                errx(1, "Descriptor has out after in");
-                        (*out_num)++;
-                }
-                /* If we've got too many, that implies a descriptor loop. */
-                if (*out_num + *in_num > max)
-                        errx(1, "Looped descriptor");
-        } while ((i = next_desc(desc, i, max)) != max);
-        return head;
-}
-/*
- * After we've used one of their buffers, we tell the Guest about it.  Sometime
- * later we'll want to send them an interrupt using trigger_irq(); note that
- * wait_for_vq_desc() does that for us if it has to wait.
- */
-static void add_used(struct virtqueue *vq, unsigned int head, int len)
-{
-        struct vring_used_elem *used;
-        /*
-         * The virtqueue contains a ring of used buffers.  Get a pointer to the
-         * next entry in that used ring.
-         */
-        used = &vq->vring.used->ring[vq->vring.used->idx % vq->vring.num];
-        used->id = head;
-        used->len = len;
-        /* Make sure buffer is written before we update index. */
-        wmb();
-        vq->vring.used->idx++;
-        vq->pending_used++;
-}
-/* And here's the combo meal deal.  Supersize me! */
-static void add_used_and_trigger(struct virtqueue *vq, unsigned head, int len)
-{
-        add_used(vq, head, len);
-        trigger_irq(vq);
-}
-/*
- * The Console
- *
- * We associate some data with the console for our exit hack.
- */
-struct console_abort {
-        /* How many times have they hit ^C? */
-        int count;
-        /* When did they start? */
-        struct timeval start;
-};
-/* This is the routine which handles console input (ie. stdin). */
-static void console_input(struct virtqueue *vq)
-{
-        int len;
-        unsigned int head, in_num, out_num;
-        struct console_abort *abort = vq->dev->priv;
-        struct iovec iov[vq->vring.num];
-        /* Make sure there's a descriptor available. */
-        head = wait_for_vq_desc(vq, iov, &out_num, &in_num);
-        if (out_num)
-                errx(1, "Output buffers in console in queue?");
-        /* Read into it.  This is where we usually wait. */
-        len = readv(STDIN_FILENO, iov, in_num);
-        if (len <= 0) {
-                /* Ran out of input? */
-                warnx("Failed to get console input, ignoring console.");
-                /*
-                 * For simplicity, dying threads kill the whole Launcher.  So
-                 * just nap here.
-                 */
-                for (;;)
-                        pause();
-        }
-        /* Tell the Guest we used a buffer. */
-        add_used_and_trigger(vq, head, len);
-        /*
-         * Three ^C within one second?  Exit.
-         *
-         * This is such a hack, but works surprisingly well.  Each ^C has to
-         * be in a buffer by itself, so they can't be too fast.  But we check
-         * that we get three within about a second, so they can't be too
-         * slow.
-         */
-        if (len != 1 || ((char *)iov[0].iov_base)[0] != 3) {
-                abort->count = 0;
-                return;
-        }
-        abort->count++;
-        if (abort->count == 1)
-                gettimeofday(&abort->start, NULL);
-        else if (abort->count == 3) {
-                struct timeval now;
-                gettimeofday(&now, NULL);
-                /* Kill all Launcher processes with SIGINT, like normal ^C */
-                if (now.tv_sec <= abort->start.tv_sec+1)
-                        kill(0, SIGINT);
-                abort->count = 0;
-        }
-}
-/* This is the routine which handles console output (ie. stdout). */
-static void console_output(struct virtqueue *vq)
-{
-        unsigned int head, out, in;
-        struct iovec iov[vq->vring.num];
-        /* We usually wait in here, for the Guest to give us something. */
-        head = wait_for_vq_desc(vq, iov, &out, &in);
-        if (in)
-                errx(1, "Input buffers in console output queue?");
-        /* writev can return a partial write, so we loop here. */
-        while (!iov_empty(iov, out)) {
-                int len = writev(STDOUT_FILENO, iov, out);
-                if (len <= 0) {
-                        warn("Write to stdout gave %i (%d)", len, errno);
-                        break;
-                }
-                iov_consume(iov, out, len);
-        }
-        /*
-         * We're finished with that buffer: if we're going to sleep,
-         * wait_for_vq_desc() will prod the Guest with an interrupt.
-         */
-        add_used(vq, head, 0);
-}
-/*
- * The Network
- *
- * Handling output for network is also simple: we get all the output buffers
- * and write them to /dev/net/tun.
- */
-struct net_info {
-        int tunfd;
-};
-static void net_output(struct virtqueue *vq)
-{
-        struct net_info *net_info = vq->dev->priv;
-        unsigned int head, out, in;
-        struct iovec iov[vq->vring.num];
-        /* We usually wait in here for the Guest to give us a packet. */
-        head = wait_for_vq_desc(vq, iov, &out, &in);
-        if (in)
-                errx(1, "Input buffers in net output queue?");
-        /*
-         * Send the whole thing through to /dev/net/tun.  It expects the exact
-         * same format: what a coincidence!
-         */
-        if (writev(net_info->tunfd, iov, out) < 0)
-                warnx("Write to tun failed (%d)?", errno);
-        /*
-         * Done with that one; wait_for_vq_desc() will send the interrupt if
-         * all packets are processed.
-         */
-        add_used(vq, head, 0);
-}
-/*
- * Handling network input is a bit trickier, because I've tried to optimize it.
- *
- * First we have a helper routine which tells is if from this file descriptor
- * (ie. the /dev/net/tun device) will block:
- */
-static bool will_block(int fd)
-{
-        fd_set fdset;
-        struct timeval zero = { 0, 0 };
-        FD_ZERO(&fdset);
-        FD_SET(fd, &fdset);
-        return select(fd+1, &fdset, NULL, NULL, &zero) != 1;
-}
-/*
- * This handles packets coming in from the tun device to our Guest.  Like all
- * service routines, it gets called again as soon as it returns, so you don't
- * see a while(1) loop here.
- */
-static void net_input(struct virtqueue *vq)
-{
-        int len;
-        unsigned int head, out, in;
-        struct iovec iov[vq->vring.num];
-        struct net_info *net_info = vq->dev->priv;
-        /*
-         * Get a descriptor to write an incoming packet into.  This will also
-         * send an interrupt if they're out of descriptors.
-         */
-        head = wait_for_vq_desc(vq, iov, &out, &in);
-        if (out)
-                errx(1, "Output buffers in net input queue?");
-        /*
-         * If it looks like we'll block reading from the tun device, send them
-         * an interrupt.
-         */
-        if (vq->pending_used && will_block(net_info->tunfd))
-                trigger_irq(vq);
-        /*
-         * Read in the packet.  This is where we normally wait (when there's no
-         * incoming network traffic).
-         */
-        len = readv(net_info->tunfd, iov, in);
-        if (len <= 0)
-                warn("Failed to read from tun (%d).", errno);
-        /*
-         * Mark that packet buffer as used, but don't interrupt here.  We want
-         * to wait until we've done as much work as we can.
-         */
-        add_used(vq, head, len);
-}
-/*:*/
-/* This is the helper to create threads: run the service routine in a loop. */
-static int do_thread(void *_vq)
-{
-        struct virtqueue *vq = _vq;
-        for (;;)
-                vq->service(vq);
-        return 0;
-}
-/*
- * When a child dies, we kill our entire process group with SIGTERM.  This
- * also has the side effect that the shell restores the console for us!
- */
-static void kill_launcher(int signal)
-{
-        kill(0, SIGTERM);
-}
-static void reset_device(struct device *dev)
-{
-        struct virtqueue *vq;
-        verbose("Resetting device %s\n", dev->name);
-        /* Clear any features they've acked. */
-        memset(get_feature_bits(dev) + dev->feature_len, 0, dev->feature_len);
-        /* We're going to be explicitly killing threads, so ignore them. */
-        signal(SIGCHLD, SIG_IGN);
-        /* Zero out the virtqueues, get rid of their threads */
-        for (vq = dev->vq; vq; vq = vq->next) {
-                if (vq->thread != (pid_t)-1) {
-                        kill(vq->thread, SIGTERM);
-                        waitpid(vq->thread, NULL, 0);
-                        vq->thread = (pid_t)-1;
-                }
-                memset(vq->vring.desc, 0,
-                       vring_size(vq->config.num, LGUEST_VRING_ALIGN));
-                lg_last_avail(vq) = 0;
-        }
-        dev->running = false;
-        /* Now we care if threads die. */
-        signal(SIGCHLD, (void *)kill_launcher);
-}
-/*L:216
- * This actually creates the thread which services the virtqueue for a device.
- */
-static void create_thread(struct virtqueue *vq)
-{
-        /*
-         * Create stack for thread.  Since the stack grows upwards, we point
-         * the stack pointer to the end of this region.
-         */
-        char *stack = malloc(32768);
-        unsigned long args[] = { LHREQ_EVENTFD,
-                                 vq->config.pfn*getpagesize(), 0 };
-        /* Create a zero-initialized eventfd. */
-        vq->eventfd = eventfd(0, 0);
-        if (vq->eventfd < 0)
-                err(1, "Creating eventfd");
-        args[2] = vq->eventfd;
-        /*
-         * Attach an eventfd to this virtqueue: it will go off when the Guest
-         * does an LHCALL_NOTIFY for this vq.
-         */
-        if (write(lguest_fd, &args, sizeof(args)) != 0)
-                err(1, "Attaching eventfd");
-        /*
-         * CLONE_VM: because it has to access the Guest memory, and SIGCHLD so
-         * we get a signal if it dies.
-         */
-        vq->thread = clone(do_thread, stack + 32768, CLONE_VM | SIGCHLD, vq);
-        if (vq->thread == (pid_t)-1)
-                err(1, "Creating clone");
-        /* We close our local copy now the child has it. */
-        close(vq->eventfd);
-}
-static void start_device(struct device *dev)
-{
-        unsigned int i;
-        struct virtqueue *vq;
-        verbose("Device %s OK: offered", dev->name);
-        for (i = 0; i < dev->feature_len; i++)
-                verbose(" %02x", get_feature_bits(dev)[i]);
-        verbose(", accepted");
-        for (i = 0; i < dev->feature_len; i++)
-                verbose(" %02x", get_feature_bits(dev)
-                        [dev->feature_len+i]);
-        for (vq = dev->vq; vq; vq = vq->next) {
-                if (vq->service)
-                        create_thread(vq);
-        }
-        dev->running = true;
-}
-static void cleanup_devices(void)
-{
-        struct device *dev;
-        for (dev = devices.dev; dev; dev = dev->next)
-                reset_device(dev);
-        /* If we saved off the original terminal settings, restore them now. */
-        if (orig_term.c_lflag & (ISIG|ICANON|ECHO))
-                tcsetattr(STDIN_FILENO, TCSANOW, &orig_term);
-}
-/* When the Guest tells us they updated the status field, we handle it. */
-static void update_device_status(struct device *dev)
-{
-        /* A zero status is a reset, otherwise it's a set of flags. */
-        if (dev->desc->status == 0)
-                reset_device(dev);
-        else if (dev->desc->status & VIRTIO_CONFIG_S_FAILED) {
-                warnx("Device %s configuration FAILED", dev->name);
-                if (dev->running)
-                        reset_device(dev);
-        } else {
-                if (dev->running)
-                        err(1, "Device %s features finalized twice", dev->name);
-                start_device(dev);
-        }
-}
-/*L:215
- * This is the generic routine we call when the Guest uses LHCALL_NOTIFY.  In
- * particular, it's used to notify us of device status changes during boot.
- */
-static void handle_output(unsigned long addr)
-{
-        struct device *i;
-        /* Check each device. */
-        for (i = devices.dev; i; i = i->next) {
-                struct virtqueue *vq;
-                /*
-                 * Notifications to device descriptors mean they updated the
-                 * device status.
-                 */
-                if (from_guest_phys(addr) == i->desc) {
-                        update_device_status(i);
-                        return;
-                }
-                /* Devices should not be used before features are finalized. */
-                for (vq = i->vq; vq; vq = vq->next) {
-                        if (addr != vq->config.pfn*getpagesize())
-                                continue;
-                        errx(1, "Notification on %s before setup!", i->name);
-                }
-        }
-        /*
-         * Early console write is done using notify on a nul-terminated string
-         * in Guest memory.  It's also great for hacking debugging messages
-         * into a Guest.
-         */
-        if (addr >= guest_limit)
-                errx(1, "Bad NOTIFY %#lx", addr);
-        write(STDOUT_FILENO, from_guest_phys(addr),
-              strnlen(from_guest_phys(addr), guest_limit - addr));
-}
-/*L:190
- * Device Setup
- *
- * All devices need a descriptor so the Guest knows it exists, and a "struct
- * device" so the Launcher can keep track of it.  We have common helper
- * routines to allocate and manage them.
- */
-/*
- * The layout of the device page is a "struct lguest_device_desc" followed by a
- * number of virtqueue descriptors, then two sets of feature bits, then an
- * array of configuration bytes.  This routine returns the configuration
- * pointer.
- */
-static u8 *device_config(const struct device *dev)
-{
-        return (void *)(dev->desc + 1)
-                + dev->num_vq * sizeof(struct lguest_vqconfig)
-                + dev->feature_len * 2;
-}
-/*
- * This routine allocates a new "struct lguest_device_desc" from descriptor
- * table page just above the Guest's normal memory.  It returns a pointer to
- * that descriptor.
- */
-static struct lguest_device_desc *new_dev_desc(u16 type)
-{
-        struct lguest_device_desc d = { .type = type };
-        void *p;
-        /* Figure out where the next device config is, based on the last one. */
-        if (devices.lastdev)
-                p = device_config(devices.lastdev)
-                        + devices.lastdev->desc->config_len;
-        else
-                p = devices.descpage;
-        /* We only have one page for all the descriptors. */
-        if (p + sizeof(d) > (void *)devices.descpage + getpagesize())
-                errx(1, "Too many devices");
-        /* p might not be aligned, so we memcpy in. */
-        return memcpy(p, &d, sizeof(d));
-}
-/*
- * Each device descriptor is followed by the description of its virtqueues.  We
- * specify how many descriptors the virtqueue is to have.
- */
-static void add_virtqueue(struct device *dev, unsigned int num_descs,
-                          void (*service)(struct virtqueue *))
-{
-        unsigned int pages;
-        struct virtqueue **i, *vq = malloc(sizeof(*vq));
-        void *p;
-        /* First we need some memory for this virtqueue. */
-        pages = (vring_size(num_descs, LGUEST_VRING_ALIGN) + getpagesize() - 1)
-                / getpagesize();
-        p = get_pages(pages);
-        /* Initialize the virtqueue */
-        vq->next = NULL;
-        vq->last_avail_idx = 0;
-        vq->dev = dev;
-        /*
-         * This is the routine the service thread will run, and its Process ID
-         * once it's running.
-         */
-        vq->service = service;
-        vq->thread = (pid_t)-1;
-        /* Initialize the configuration. */
-        vq->config.num = num_descs;
-        vq->config.irq = devices.next_irq++;
-        vq->config.pfn = to_guest_phys(p) / getpagesize();
-        /* Initialize the vring. */
-        vring_init(&vq->vring, num_descs, p, LGUEST_VRING_ALIGN);
-        /*
-         * Append virtqueue to this device's descriptor.  We use
-         * device_config() to get the end of the device's current virtqueues;
-         * we check that we haven't added any config or feature information
-         * yet, otherwise we'd be overwriting them.
-         */
-        assert(dev->desc->config_len == 0 && dev->desc->feature_len == 0);
-        memcpy(device_config(dev), &vq->config, sizeof(vq->config));
-        dev->num_vq++;
-        dev->desc->num_vq++;
-        verbose("Virtqueue page %#lx\n", to_guest_phys(p));
-        /*
-         * Add to tail of list, so dev->vq is first vq, dev->vq->next is
-         * second.
-         */
-        for (i = &dev->vq; *i; i = &(*i)->next);
-        *i = vq;
-}
-/*
- * The first half of the feature bitmask is for us to advertise features.  The
- * second half is for the Guest to accept features.
- */
-static void add_feature(struct device *dev, unsigned bit)
-{
-        u8 *features = get_feature_bits(dev);
-        /* We can't extend the feature bits once we've added config bytes */
-        if (dev->desc->feature_len <= bit / CHAR_BIT) {
-                assert(dev->desc->config_len == 0);
-                dev->feature_len = dev->desc->feature_len = (bit/CHAR_BIT) + 1;
-        }
-        features[bit / CHAR_BIT] |= (1 << (bit % CHAR_BIT));
-}
-/*
- * This routine sets the configuration fields for an existing device's
- * descriptor.  It only works for the last device, but that's OK because that's
- * how we use it.
- */
-static void set_config(struct device *dev, unsigned len, const void *conf)
-{
-        /* Check we haven't overflowed our single page. */
-        if (device_config(dev) + len > devices.descpage + getpagesize())
-                errx(1, "Too many devices");
-        /* Copy in the config information, and store the length. */
-        memcpy(device_config(dev), conf, len);
-        dev->desc->config_len = len;
-        /* Size must fit in config_len field (8 bits)! */
-        assert(dev->desc->config_len == len);
-}
-/*
- * This routine does all the creation and setup of a new device, including
- * calling new_dev_desc() to allocate the descriptor and device memory.  We
- * don't actually start the service threads until later.
- *
- * See what I mean about userspace being boring?
- */
-static struct device *new_device(const char *name, u16 type)
-{
-        struct device *dev = malloc(sizeof(*dev));
-        /* Now we populate the fields one at a time. */
-        dev->desc = new_dev_desc(type);
-        dev->name = name;
-        dev->vq = NULL;
-        dev->feature_len = 0;
-        dev->num_vq = 0;
-        dev->running = false;
-        /*
-         * Append to device list.  Prepending to a single-linked list is
-         * easier, but the user expects the devices to be arranged on the bus
-         * in command-line order.  The first network device on the command line
-         * is eth0, the first block device /dev/vda, etc.
-         */
-        if (devices.lastdev)
-                devices.lastdev->next = dev;
-        else
-                devices.dev = dev;
-        devices.lastdev = dev;
-        return dev;
-}
-/*
- * Our first setup routine is the console.  It's a fairly simple device, but
- * UNIX tty handling makes it uglier than it could be.
- */
-static void setup_console(void)
-{
-        struct device *dev;
-        /* If we can save the initial standard input settings... */
-        if (tcgetattr(STDIN_FILENO, &orig_term) == 0) {
-                struct termios term = orig_term;
-                /*
-                 * Then we turn off echo, line buffering and ^C etc: We want a
-                 * raw input stream to the Guest.
-                 */
-                term.c_lflag &= ~(ISIG|ICANON|ECHO);
-                tcsetattr(STDIN_FILENO, TCSANOW, &term);
-        }
-        dev = new_device("console", VIRTIO_ID_CONSOLE);
-        /* We store the console state in dev->priv, and initialize it. */
-        dev->priv = malloc(sizeof(struct console_abort));
-        ((struct console_abort *)dev->priv)->count = 0;
-        /*
-         * The console needs two virtqueues: the input then the output.  When
-         * they put something the input queue, we make sure we're listening to
-         * stdin.  When they put something in the output queue, we write it to
-         * stdout.
-         */
-        add_virtqueue(dev, VIRTQUEUE_NUM, console_input);
-        add_virtqueue(dev, VIRTQUEUE_NUM, console_output);
-        verbose("device %u: console\n", ++devices.device_num);
-}
-/*:*/
-/*M:010
- * Inter-guest networking is an interesting area.  Simplest is to have a
- * --sharenet=<name> option which opens or creates a named pipe.  This can be
- * used to send packets to another guest in a 1:1 manner.
- *
- * More sophisticated is to use one of the tools developed for project like UML
- * to do networking.
- *
- * Faster is to do virtio bonding in kernel.  Doing this 1:1 would be
- * completely generic ("here's my vring, attach to your vring") and would work
- * for any traffic.  Of course, namespace and permissions issues need to be
- * dealt with.  A more sophisticated "multi-channel" virtio_net.c could hide
- * multiple inter-guest channels behind one interface, although it would
- * require some manner of hotplugging new virtio channels.
- *
- * Finally, we could use a virtio network switch in the kernel, ie. vhost.
-:*/
-static u32 str2ip(const char *ipaddr)
-{
-        unsigned int b[4];
-        if (sscanf(ipaddr, "%u.%u.%u.%u", &b[0], &b[1], &b[2], &b[3]) != 4)
-                errx(1, "Failed to parse IP address '%s'", ipaddr);
-        return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
-}
-static void str2mac(const char *macaddr, unsigned char mac[6])
-{
-        unsigned int m[6];
-        if (sscanf(macaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
-                   &m[0], &m[1], &m[2], &m[3], &m[4], &m[5]) != 6)
-                errx(1, "Failed to parse mac address '%s'", macaddr);
-        mac[0] = m[0];
-        mac[1] = m[1];
-        mac[2] = m[2];
-        mac[3] = m[3];
-        mac[4] = m[4];
-        mac[5] = m[5];
-}
-/*
- * This code is "adapted" from libbridge: it attaches the Host end of the
- * network device to the bridge device specified by the command line.
- *
- * This is yet another James Morris contribution (I'm an IP-level guy, so I
- * dislike bridging), and I just try not to break it.
- */
-static void add_to_bridge(int fd, const char *if_name, const char *br_name)
-{
-        int ifidx;
-        struct ifreq ifr;
-        if (!*br_name)
-                errx(1, "must specify bridge name");
-        ifidx = if_nametoindex(if_name);
-        if (!ifidx)
-                errx(1, "interface %s does not exist!", if_name);
-        strncpy(ifr.ifr_name, br_name, IFNAMSIZ);
-        ifr.ifr_name[IFNAMSIZ-1] = '\0';
-        ifr.ifr_ifindex = ifidx;
-        if (ioctl(fd, SIOCBRADDIF, &ifr) < 0)
-                err(1, "can't add %s to bridge %s", if_name, br_name);
-}
-/*
- * This sets up the Host end of the network device with an IP address, brings
- * it up so packets will flow, the copies the MAC address into the hwaddr
- * pointer.
- */
-static void configure_device(int fd, const char *tapif, u32 ipaddr)
-{
-        struct ifreq ifr;
-        struct sockaddr_in sin;
-        memset(&ifr, 0, sizeof(ifr));
-        strcpy(ifr.ifr_name, tapif);
-        /* Don't read these incantations.  Just cut & paste them like I did! */
-        sin.sin_family = AF_INET;
-        sin.sin_addr.s_addr = htonl(ipaddr);
-        memcpy(&ifr.ifr_addr, &sin, sizeof(sin));
-        if (ioctl(fd, SIOCSIFADDR, &ifr) != 0)
-                err(1, "Setting %s interface address", tapif);
-        ifr.ifr_flags = IFF_UP;
-        if (ioctl(fd, SIOCSIFFLAGS, &ifr) != 0)
-                err(1, "Bringing interface %s up", tapif);
-}
-static int get_tun_device(char tapif[IFNAMSIZ])
-{
-        struct ifreq ifr;
-        int netfd;
-        /* Start with this zeroed.  Messy but sure. */
-        memset(&ifr, 0, sizeof(ifr));
-        /*
-         * We open the /dev/net/tun device and tell it we want a tap device.  A
-         * tap device is like a tun device, only somehow different.  To tell
-         * the truth, I completely blundered my way through this code, but it
-         * works now!
-         */
-        netfd = open_or_die("/dev/net/tun", O_RDWR);
-        ifr.ifr_flags = IFF_TAP | IFF_NO_PI | IFF_VNET_HDR;
-        strcpy(ifr.ifr_name, "tap%d");
-        if (ioctl(netfd, TUNSETIFF, &ifr) != 0)
-                err(1, "configuring /dev/net/tun");
-        if (ioctl(netfd, TUNSETOFFLOAD,
-                  TUN_F_CSUM|TUN_F_TSO4|TUN_F_TSO6|TUN_F_TSO_ECN) != 0)
-                err(1, "Could not set features for tun device");
-        /*
-         * We don't need checksums calculated for packets coming in this
-         * device: trust us!
-         */
-        ioctl(netfd, TUNSETNOCSUM, 1);
-        memcpy(tapif, ifr.ifr_name, IFNAMSIZ);
-        return netfd;
-}
-/*L:195
- * Our network is a Host<->Guest network.  This can either use bridging or
- * routing, but the principle is the same: it uses the "tun" device to inject
- * packets into the Host as if they came in from a normal network card.  We
- * just shunt packets between the Guest and the tun device.
- */
-static void setup_tun_net(char *arg)
-{
-        struct device *dev;
-        struct net_info *net_info = malloc(sizeof(*net_info));
-        int ipfd;
-        u32 ip = INADDR_ANY;
-        bool bridging = false;
-        char tapif[IFNAMSIZ], *p;
-        struct virtio_net_config conf;
-        net_info->tunfd = get_tun_device(tapif);
-        /* First we create a new network device. */
-        dev = new_device("net", VIRTIO_ID_NET);
-        dev->priv = net_info;
-        /* Network devices need a recv and a send queue, just like console. */
-        add_virtqueue(dev, VIRTQUEUE_NUM, net_input);
-        add_virtqueue(dev, VIRTQUEUE_NUM, net_output);
-        /*
-         * We need a socket to perform the magic network ioctls to bring up the
-         * tap interface, connect to the bridge etc.  Any socket will do!
-         */
-        ipfd = socket(PF_INET, SOCK_DGRAM, IPPROTO_IP);
-        if (ipfd < 0)
-                err(1, "opening IP socket");
-        /* If the command line was --tunnet=bridge:<name> do bridging. */
-        if (!strncmp(BRIDGE_PFX, arg, strlen(BRIDGE_PFX))) {
-                arg += strlen(BRIDGE_PFX);
-                bridging = true;
-        }
-        /* A mac address may follow the bridge name or IP address */
-        p = strchr(arg, ':');
-        if (p) {
-                str2mac(p+1, conf.mac);
-                add_feature(dev, VIRTIO_NET_F_MAC);
-                *p = '\0';
-        }
-        /* arg is now either an IP address or a bridge name */
-        if (bridging)
-                add_to_bridge(ipfd, tapif, arg);
-        else
-                ip = str2ip(arg);
-        /* Set up the tun device. */
-        configure_device(ipfd, tapif, ip);
-        /* Expect Guest to handle everything except UFO */
-        add_feature(dev, VIRTIO_NET_F_CSUM);
-        add_feature(dev, VIRTIO_NET_F_GUEST_CSUM);
-        add_feature(dev, VIRTIO_NET_F_GUEST_TSO4);
-        add_feature(dev, VIRTIO_NET_F_GUEST_TSO6);
-        add_feature(dev, VIRTIO_NET_F_GUEST_ECN);
-        add_feature(dev, VIRTIO_NET_F_HOST_TSO4);
-        add_feature(dev, VIRTIO_NET_F_HOST_TSO6);
-        add_feature(dev, VIRTIO_NET_F_HOST_ECN);
-        /* We handle indirect ring entries */
-        add_feature(dev, VIRTIO_RING_F_INDIRECT_DESC);
-        set_config(dev, sizeof(conf), &conf);
-        /* We don't need the socket any more; setup is done. */
-        close(ipfd);
-        devices.device_num++;
-        if (bridging)
-                verbose("device %u: tun %s attached to bridge: %s\n",
-                        devices.device_num, tapif, arg);
-        else
-                verbose("device %u: tun %s: %s\n",
-                        devices.device_num, tapif, arg);
-}
-/*:*/
-/* This hangs off device->priv. */
-struct vblk_info {
-        /* The size of the file. */
-        off64_t len;
-        /* The file descriptor for the file. */
-        int fd;
-};
-/*L:210
- * The Disk
- *
- * The disk only has one virtqueue, so it only has one thread.  It is really
- * simple: the Guest asks for a block number and we read or write that position
- * in the file.
- *
- * Before we serviced each virtqueue in a separate thread, that was unacceptably
- * slow: the Guest waits until the read is finished before running anything
- * else, even if it could have been doing useful work.
- *
- * We could have used async I/O, except it's reputed to suck so hard that
- * characters actually go missing from your code when you try to use it.
- */
-static void blk_request(struct virtqueue *vq)
-{
-        struct vblk_info *vblk = vq->dev->priv;
-        unsigned int head, out_num, in_num, wlen;
-        int ret;
-        u8 *in;
-        struct virtio_blk_outhdr *out;
-        struct iovec iov[vq->vring.num];
-        off64_t off;
-        /*
-         * Get the next request, where we normally wait.  It triggers the
-         * interrupt to acknowledge previously serviced requests (if any).
-         */
-        head = wait_for_vq_desc(vq, iov, &out_num, &in_num);
-        /*
-         * Every block request should contain at least one output buffer
-         * (detailing the location on disk and the type of request) and one
-         * input buffer (to hold the result).
-         */
-        if (out_num == 0 || in_num == 0)
-                errx(1, "Bad virtblk cmd %u out=%u in=%u",
-                     head, out_num, in_num);
-        out = convert(&iov[0], struct virtio_blk_outhdr);
-        in = convert(&iov[out_num+in_num-1], u8);
-        /*
-         * For historical reasons, block operations are expressed in 512 byte
-         * "sectors".
-         */
-        off = out->sector * 512;
-        /*
-         * In general the virtio block driver is allowed to try SCSI commands.
-         * It'd be nice if we supported eject, for example, but we don't.
-         */
-        if (out->type & VIRTIO_BLK_T_SCSI_CMD) {
-                fprintf(stderr, "Scsi commands unsupported\n");
-                *in = VIRTIO_BLK_S_UNSUPP;
-                wlen = sizeof(*in);
-        } else if (out->type & VIRTIO_BLK_T_OUT) {
-                /*
-                 * Write
-                 *
-                 * Move to the right location in the block file.  This can fail
-                 * if they try to write past end.
-                 */
-                if (lseek64(vblk->fd, off, SEEK_SET) != off)
-                        err(1, "Bad seek to sector %llu", out->sector);
-                ret = writev(vblk->fd, iov+1, out_num-1);
-                verbose("WRITE to sector %llu: %i\n", out->sector, ret);
-                /*
-                 * Grr... Now we know how long the descriptor they sent was, we
-                 * make sure they didn't try to write over the end of the block
-                 * file (possibly extending it).
-                 */
-                if (ret > 0 && off + ret > vblk->len) {
-                        /* Trim it back to the correct length */
-                        ftruncate64(vblk->fd, vblk->len);
-                        /* Die, bad Guest, die. */
-                        errx(1, "Write past end %llu+%u", off, ret);
-                }
-                wlen = sizeof(*in);
-                *in = (ret >= 0 ? VIRTIO_BLK_S_OK : VIRTIO_BLK_S_IOERR);
-        } else if (out->type & VIRTIO_BLK_T_FLUSH) {
-                /* Flush */
-                ret = fdatasync(vblk->fd);
-                verbose("FLUSH fdatasync: %i\n", ret);
-                wlen = sizeof(*in);
-                *in = (ret >= 0 ? VIRTIO_BLK_S_OK : VIRTIO_BLK_S_IOERR);
-        } else {
-                /*
-                 * Read
-                 *
-                 * Move to the right location in the block file.  This can fail
-                 * if they try to read past end.
-                 */
-                if (lseek64(vblk->fd, off, SEEK_SET) != off)
-                        err(1, "Bad seek to sector %llu", out->sector);
-                ret = readv(vblk->fd, iov+1, in_num-1);
-                verbose("READ from sector %llu: %i\n", out->sector, ret);
-                if (ret >= 0) {
-                        wlen = sizeof(*in) + ret;
-                        *in = VIRTIO_BLK_S_OK;
-                } else {
-                        wlen = sizeof(*in);
-                        *in = VIRTIO_BLK_S_IOERR;
-                }
-        }
-        /* Finished that request. */
-        add_used(vq, head, wlen);
-}
-/*L:198 This actually sets up a virtual block device. */
-static void setup_block_file(const char *filename)
-{
-        struct device *dev;
-        struct vblk_info *vblk;
-        struct virtio_blk_config conf;
-        /* Creat the device. */
-        dev = new_device("block", VIRTIO_ID_BLOCK);
-        /* The device has one virtqueue, where the Guest places requests. */
-        add_virtqueue(dev, VIRTQUEUE_NUM, blk_request);
-        /* Allocate the room for our own bookkeeping */
-        vblk = dev->priv = malloc(sizeof(*vblk));
-        /* First we open the file and store the length. */
-        vblk->fd = open_or_die(filename, O_RDWR|O_LARGEFILE);
-        vblk->len = lseek64(vblk->fd, 0, SEEK_END);
-        /* We support FLUSH. */
-        add_feature(dev, VIRTIO_BLK_F_FLUSH);
-        /* Tell Guest how many sectors this device has. */
-        conf.capacity = cpu_to_le64(vblk->len / 512);
-        /*
-         * Tell Guest not to put in too many descriptors at once: two are used
-         * for the in and out elements.
-         */
-        add_feature(dev, VIRTIO_BLK_F_SEG_MAX);
-        conf.seg_max = cpu_to_le32(VIRTQUEUE_NUM - 2);
-        /* Don't try to put whole struct: we have 8 bit limit. */
-        set_config(dev, offsetof(struct virtio_blk_config, geometry), &conf);
-        verbose("device %u: virtblock %llu sectors\n",
-                ++devices.device_num, le64_to_cpu(conf.capacity));
-}
-/*L:211
- * Our random number generator device reads from /dev/random into the Guest's
- * input buffers.  The usual case is that the Guest doesn't want random numbers
- * and so has no buffers although /dev/random is still readable, whereas
- * console is the reverse.
- *
- * The same logic applies, however.
- */
-struct rng_info {
-        int rfd;
-};
-static void rng_input(struct virtqueue *vq)
-{
-        int len;
-        unsigned int head, in_num, out_num, totlen = 0;
-        struct rng_info *rng_info = vq->dev->priv;
-        struct iovec iov[vq->vring.num];
-        /* First we need a buffer from the Guests's virtqueue. */
-        head = wait_for_vq_desc(vq, iov, &out_num, &in_num);
-        if (out_num)
-                errx(1, "Output buffers in rng?");
-        /*
-         * Just like the console write, we loop to cover the whole iovec.
-         * In this case, short reads actually happen quite a bit.
-         */
-        while (!iov_empty(iov, in_num)) {
-                len = readv(rng_info->rfd, iov, in_num);
-                if (len <= 0)
-                        err(1, "Read from /dev/random gave %i", len);
-                iov_consume(iov, in_num, len);
-                totlen += len;
-        }
-        /* Tell the Guest about the new input. */
-        add_used(vq, head, totlen);
-}
-/*L:199
- * This creates a "hardware" random number device for the Guest.
- */
-static void setup_rng(void)
-{
-        struct device *dev;
-        struct rng_info *rng_info = malloc(sizeof(*rng_info));
-        /* Our device's privat info simply contains the /dev/random fd. */
-        rng_info->rfd = open_or_die("/dev/random", O_RDONLY);
-        /* Create the new device. */
-        dev = new_device("rng", VIRTIO_ID_RNG);
-        dev->priv = rng_info;
-        /* The device has one virtqueue, where the Guest places inbufs. */
-        add_virtqueue(dev, VIRTQUEUE_NUM, rng_input);
-        verbose("device %u: rng\n", devices.device_num++);
-}
-/* That's the end of device setup. */
-/*L:230 Reboot is pretty easy: clean up and exec() the Launcher afresh. */
-static void __attribute__((noreturn)) restart_guest(void)
-{
-        unsigned int i;
-        /*
-         * Since we don't track all open fds, we simply close everything beyond
-         * stderr.
-         */
-        for (i = 3; i < FD_SETSIZE; i++)
-                close(i);
-        /* Reset all the devices (kills all threads). */
-        cleanup_devices();
-        execv(main_args[0], main_args);
-        err(1, "Could not exec %s", main_args[0]);
-}
-/*L:220
- * Finally we reach the core of the Launcher which runs the Guest, serves
- * its input and output, and finally, lays it to rest.
- */
-static void __attribute__((noreturn)) run_guest(void)
-{
-        for (;;) {
-                unsigned long notify_addr;
-                int readval;
-                /* We read from the /dev/lguest device to run the Guest. */
-                readval = pread(lguest_fd, &notify_addr,
-                                sizeof(notify_addr), cpu_id);
-                /* One unsigned long means the Guest did HCALL_NOTIFY */
-                if (readval == sizeof(notify_addr)) {
-                        verbose("Notify on address %#lx\n", notify_addr);
-                        handle_output(notify_addr);
-                /* ENOENT means the Guest died.  Reading tells us why. */
-                } else if (errno == ENOENT) {
-                        char reason[1024] = { 0 };
-                        pread(lguest_fd, reason, sizeof(reason)-1, cpu_id);
-                        errx(1, "%s", reason);
-                /* ERESTART means that we need to reboot the guest */
-                } else if (errno == ERESTART) {
-                        restart_guest();
-                /* Anything else means a bug or incompatible change. */
-                } else
-                        err(1, "Running guest failed");
-        }
-}
-/*L:240
- * This is the end of the Launcher.  The good news: we are over halfway
- * through!  The bad news: the most fiendish part of the code still lies ahead
- * of us.
- *
- * Are you ready?  Take a deep breath and join me in the core of the Host, in
- * "make Host".
-:*/
-static struct option opts[] = {
-        { "verbose", 0, NULL, 'v' },
-        { "tunnet", 1, NULL, 't' },
-        { "block", 1, NULL, 'b' },
-        { "rng", 0, NULL, 'r' },
-        { "initrd", 1, NULL, 'i' },
-        { "username", 1, NULL, 'u' },
-        { "chroot", 1, NULL, 'c' },
-        { NULL },
-};
-static void usage(void)
-{
-        errx(1, "Usage: lguest [--verbose] "
-             "[--tunnet=(<ipaddr>:<macaddr>|bridge:<bridgename>:<macaddr>)\n"
-             "|--block=<filename>|--initrd=<filename>]...\n"
-             "<mem-in-mb> vmlinux [args...]");
-}
-/*L:105 The main routine is where the real work begins: */
-int main(int argc, char *argv[])
-{
-        /* Memory, code startpoint and size of the (optional) initrd. */
-        unsigned long mem = 0, start, initrd_size = 0;
-        /* Two temporaries. */
-        int i, c;
-        /* The boot information for the Guest. */
-        struct boot_params *boot;
-        /* If they specify an initrd file to load. */
-        const char *initrd_name = NULL;
-        /* Password structure for initgroups/setres[gu]id */
-        struct passwd *user_details = NULL;
-        /* Directory to chroot to */
-        char *chroot_path = NULL;
-        /* Save the args: we "reboot" by execing ourselves again. */
-        main_args = argv;
-        /*
-         * First we initialize the device list.  We keep a pointer to the last
-         * device, and the next interrupt number to use for devices (1:
-         * remember that 0 is used by the timer).
-         */
-        devices.lastdev = NULL;
-        devices.next_irq = 1;
-        /* We're CPU 0.  In fact, that's the only CPU possible right now. */
-        cpu_id = 0;
-        /*
-         * We need to know how much memory so we can set up the device
-         * descriptor and memory pages for the devices as we parse the command
-         * line.  So we quickly look through the arguments to find the amount
-         * of memory now.
-         */
-        for (i = 1; i < argc; i++) {
-                if (argv[i][0] != '-') {
-                        mem = atoi(argv[i]) * 1024 * 1024;
-                        /*
-                         * We start by mapping anonymous pages over all of
-                         * guest-physical memory range.  This fills it with 0,
-                         * and ensures that the Guest won't be killed when it
-                         * tries to access it.
-                         */
-                        guest_base = map_zeroed_pages(mem / getpagesize()
-                                                      + DEVICE_PAGES);
-                        guest_limit = mem;
-                        guest_max = mem + DEVICE_PAGES*getpagesize();
-                        devices.descpage = get_pages(1);
-                        break;
-                }
-        }
-        /* The options are fairly straight-forward */
-        while ((c = getopt_long(argc, argv, "v", opts, NULL)) != EOF) {
-                switch (c) {
-                case 'v':
-                        verbose = true;
-                        break;
-                case 't':
-                        setup_tun_net(optarg);
-                        break;
-                case 'b':
-                        setup_block_file(optarg);
-                        break;
-                case 'r':
-                        setup_rng();
-                        break;
-                case 'i':
-                        initrd_name = optarg;
-                        break;
-                case 'u':
-                        user_details = getpwnam(optarg);
-                        if (!user_details)
-                                err(1, "getpwnam failed, incorrect username?");
-                        break;
-                case 'c':
-                        chroot_path = optarg;
-                        break;
-                default:
-                        warnx("Unknown argument %s", argv[optind]);
-                        usage();
-                }
-        }
-        /*
-         * After the other arguments we expect memory and kernel image name,
-         * followed by command line arguments for the kernel.
-         */
-        if (optind + 2 > argc)
-                usage();
-        verbose("Guest base is at %p\n", guest_base);
-        /* We always have a console device */
-        setup_console();
-        /* Now we load the kernel */
-        start = load_kernel(open_or_die(argv[optind+1], O_RDONLY));
-        /* Boot information is stashed at physical address 0 */
-        boot = from_guest_phys(0);
-        /* Map the initrd image if requested (at top of physical memory) */
-        if (initrd_name) {
-                initrd_size = load_initrd(initrd_name, mem);
-                /*
-                 * These are the location in the Linux boot header where the
-                 * start and size of the initrd are expected to be found.
-                 */
-                boot->hdr.ramdisk_image = mem - initrd_size;
-                boot->hdr.ramdisk_size = initrd_size;
-                /* The bootloader type 0xFF means "unknown"; that's OK. */
-                boot->hdr.type_of_loader = 0xFF;
-        }
-        /*
-         * The Linux boot header contains an "E820" memory map: ours is a
-         * simple, single region.
-         */
-        boot->e820_entries = 1;
-        boot->e820_map[0] = ((struct e820entry) { 0, mem, E820_RAM });
-        /*
-         * The boot header contains a command line pointer: we put the command
-         * line after the boot header.
-         */
-        boot->hdr.cmd_line_ptr = to_guest_phys(boot + 1);
-        /* We use a simple helper to copy the arguments separated by spaces. */
-        concat((char *)(boot + 1), argv+optind+2);
-        /* Set kernel alignment to 16M (CONFIG_PHYSICAL_ALIGN) */
-        boot->hdr.kernel_alignment = 0x1000000;
-        /* Boot protocol version: 2.07 supports the fields for lguest. */
-        boot->hdr.version = 0x207;
-        /* The hardware_subarch value of "1" tells the Guest it's an lguest. */
-        boot->hdr.hardware_subarch = 1;
-        /* Tell the entry path not to try to reload segment registers. */
-        boot->hdr.loadflags |= KEEP_SEGMENTS;
-        /* We tell the kernel to initialize the Guest. */
-        tell_kernel(start);
-        /* Ensure that we terminate if a device-servicing child dies. */
-        signal(SIGCHLD, kill_launcher);
-        /* If we exit via err(), this kills all the threads, restores tty. */
-        atexit(cleanup_devices);
-        /* If requested, chroot to a directory */
-        if (chroot_path) {
-                if (chroot(chroot_path) != 0)
-                        err(1, "chroot(\"%s\") failed", chroot_path);
-                if (chdir("/") != 0)
-                        err(1, "chdir(\"/\") failed");
-                verbose("chroot done\n");
-        }
-        /* If requested, drop privileges */
-        if (user_details) {
-                uid_t u;
-                gid_t g;
-                u = user_details->pw_uid;
-                g = user_details->pw_gid;
-                if (initgroups(user_details->pw_name, g) != 0)
-                        err(1, "initgroups failed");
-                if (setresgid(g, g, g) != 0)
-                        err(1, "setresgid failed");
-                if (setresuid(u, u, u) != 0)
-                        err(1, "setresuid failed");
-                verbose("Dropping privileges completed\n");
-        }
-        /* Finally, run the Guest.  This doesn't return. */
-        run_guest();
-}
-/*:*/
-/*M:999
- * Mastery is done: you now know everything I do.
- *
- * But surely you have seen code, features and bugs in your wanderings which
- * you now yearn to attack?  That is the real game, and I look forward to you
- * patching and forking lguest into the Your-Name-Here-visor.
- *
- * Farewell, and good coding!
- * Rusty Russell.
- */
diff --git a/Documentation/vm/slub.txt b/Documentation/vm/slub.txt
index f464f47bc60..6752870c497 100644
--- a/Documentation/vm/slub.txt
+++ b/Documentation/vm/slub.txt
@@ -117,7 +117,7 @@ can be influenced by kernel parameters:
 slub_min_objects=x              (default 4)
 slub_min_order=x                (default 0)
-slub_max_order=x                (default 1)
+slub_max_order=x                (default 3 (PAGE_ALLOC_COSTLY_ORDER))
 slub_min_objects allows to specify how many objects must at least fit
 into one slab in order for the allocation order to be acceptable.
@@ -131,7 +131,10 @@ slub_min_objects.
 slub_max_order specified the order at which slub_min_objects should no
 longer be checked. This is useful to avoid SLUB trying to generate
 super large order pages to fit slub_min_objects of a slab cache with
-large object sizes into one high order page.
+large object sizes into one high order page. Setting command line
+parameter debug_guardpage_minorder=N (N > 0), forces setting
+slub_max_order to 0, what cause minimum possible order of slabs
+allocation.
 SLUB Debug output
 -----------------
diff --git a/Documentation/watchdog/00-INDEX b/Documentation/watchdog/00-INDEX
index fc51128071c..fc9082a1477 100644
--- a/Documentation/watchdog/00-INDEX
+++ b/Documentation/watchdog/00-INDEX
@@ -1,5 +1,7 @@
 00-INDEX
        - this file.
+convert_drivers_to_kernel_api.txt
+        - how-to for converting old watchdog drivers to the new kernel API.
 hpwdt.txt
        - information on the HP iLO2 NMI watchdog
 pcwd-watchdog.txt
diff --git a/Documentation/watchdog/convert_drivers_to_kernel_api.txt b/Documentation/watchdog/convert_drivers_to_kernel_api.txt
index ae1e90036d0..be8119bb15d 100644
--- a/Documentation/watchdog/convert_drivers_to_kernel_api.txt
+++ b/Documentation/watchdog/convert_drivers_to_kernel_api.txt
@@ -163,6 +163,25 @@ Here is a simple example for a watchdog device:
 +};
+Handle the 'nowayout' feature
+-----------------------------
+A few drivers use nowayout statically, i.e. there is no module parameter for it
+and only CONFIG_WATCHDOG_NOWAYOUT determines if the feature is going to be
+used. This needs to be converted by initializing the status variable of the
+watchdog_device like this:
+        .status = WATCHDOG_NOWAYOUT_INIT_STATUS,
+Most drivers, however, also allow runtime configuration of nowayout, usually
+by adding a module parameter. The conversion for this would be something like:
+        watchdog_set_nowayout(&s3c2410_wdd, nowayout);
+The module parameter itself needs to stay, everything else related to nowayout
+can go, though. This will likely be some code in open(), close() or write().
 Register the watchdog device
 ----------------------------
diff --git a/Documentation/watchdog/watchdog-kernel-api.txt b/Documentation/watchdog/watchdog-kernel-api.txt
index 4f7c894244d..4b93c28e35c 100644
--- a/Documentation/watchdog/watchdog-kernel-api.txt
+++ b/Documentation/watchdog/watchdog-kernel-api.txt
@@ -1,6 +1,6 @@
 The Linux WatchDog Timer Driver Core kernel API.
 ===============================================
-Last reviewed: 22-Jul-2011
+Last reviewed: 29-Nov-2011
 Wim Van Sebroeck <wim@iguana.be>
@@ -142,6 +142,14 @@ bit-operations. The status bits that are defined are:
 * WDOG_NO_WAY_OUT: this bit stores the nowayout setting for the watchdog.
  If this bit is set then the watchdog timer will not be able to stop.
+  To set the WDOG_NO_WAY_OUT status bit (before registering your watchdog
+  timer device) you can either:
+  * set it statically in your watchdog_device struct with
+        .status = WATCHDOG_NOWAYOUT_INIT_STATUS,
+    (this will set the value the same as CONFIG_WATCHDOG_NOWAYOUT) or
+  * use the following helper function:
+  static inline void watchdog_set_nowayout(struct watchdog_device *wdd, int nowayout)
 Note: The WatchDog Timer Driver Core supports the magic close feature and
 the nowayout feature. To use the magic close feature you must set the
 WDIOF_MAGICCLOSE bit in the options field of the watchdog's info structure.
diff --git a/MAINTAINERS b/MAINTAINERS
index c3ec9555adc..89b70df91f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -184,11 +184,6 @@ S:	Maintained
 F:      Documentation/filesystems/9p.txt
 F:      fs/9p/
-A2232 SERIAL BOARD DRIVER
-L:      linux-m68k@lists.linux-m68k.org
-S:      Orphan
-F:      drivers/staging/generic_serial/ser_a2232*
 AACRAID SCSI RAID DRIVER
 M:      Adaptec OEM Raid Solutions <aacraid@adaptec.com>
 L:      linux-scsi@vger.kernel.org
@@ -347,7 +342,7 @@ S:	Supported
 F:      drivers/mfd/adp5520.c
 F:      drivers/video/backlight/adp5520_bl.c
 F:      drivers/leds/leds-adp5520.c
-F:      drivers/gpio/adp5520-gpio.c
+F:      drivers/gpio/gpio-adp5520.c
 F:      drivers/input/keyboard/adp5520-keys.c
 ADP5588 QWERTY KEYPAD AND IO EXPANDER DRIVER (ADP5588/ADP5587)
@@ -356,7 +351,7 @@ L:	device-drivers-devel@blackfin.uclinux.org
 W:      http://wiki.analog.com/ADP5588
 S:      Supported
 F:      drivers/input/keyboard/adp5588-keys.c
-F:      drivers/gpio/adp5588-gpio.c
+F:      drivers/gpio/gpio-adp5588.c
 ADP8860 BACKLIGHT DRIVER (ADP8860/ADP8861/ADP8863)
 M:      Michael Hennerich <michael.hennerich@analog.com>
@@ -542,6 +537,7 @@ F:	sound/soc/codecs/adau*
 F:      sound/soc/codecs/adav*
 F:      sound/soc/codecs/ad1*
 F:      sound/soc/codecs/ssm*
+F:      sound/soc/codecs/sigmadsp.*
 ANALOG DEVICES INC ASOC DRIVERS
 L:      uclinux-dist-devel@blackfin.uclinux.org
@@ -749,6 +745,7 @@ M:	Barry Song <baohua.song@csr.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 F:      arch/arm/mach-prima2/
+F:      drivers/dma/sirf-dma*
 ARM/EBSA110 MACHINE SUPPORT
 M:      Russell King <linux@arm.linux.org.uk>
@@ -919,7 +916,6 @@ M:	Lennert Buytenhek <kernel@wantstofly.org>
 M:      Nicolas Pitre <nico@fluxnic.net>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Odd Fixes
-F:      arch/arm/mach-loki/
 F:      arch/arm/mach-kirkwood/
 F:      arch/arm/mach-mv78xx0/
 F:      arch/arm/mach-orion5x/
@@ -1081,8 +1077,8 @@ L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 F:      arch/arm/mach-s5pv210/mach-aquila.c
 F:      arch/arm/mach-s5pv210/mach-goni.c
-F:      arch/arm/mach-exynos4/mach-universal_c210.c
+F:      arch/arm/mach-exynos/mach-universal_c210.c
-F:      arch/arm/mach-exynos4/mach-nuri.c
+F:      arch/arm/mach-exynos/mach-nuri.c
 ARM/SAMSUNG S5P SERIES FIMC SUPPORT
 M:      Kyungmin Park <kyungmin.park@samsung.com>
@@ -1110,7 +1106,6 @@ M:	Tomasz Stanislawski <t.stanislaws@samsung.com>
 L:      linux-arm-kernel@lists.infradead.org
 L:      linux-media@vger.kernel.org
 S:      Maintained
-F:      arch/arm/plat-s5p/dev-tv.c
 F:      drivers/media/video/s5p-tv/
 ARM/SHMOBILE ARM ARCHITECTURE
@@ -1124,13 +1119,6 @@ S:	Supported
 F:      arch/arm/mach-shmobile/
 F:      drivers/sh/
-ARM/TELECHIPS ARM ARCHITECTURE
-M:      "Hans J. Koch" <hjk@hansjkoch.de>
-L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-S:      Maintained
-F:      arch/arm/plat-tcc/
-F:      arch/arm/mach-tcc8k/
 ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
 M:      Lennert Buytenhek <kernel@wantstofly.org>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@@ -1152,14 +1140,13 @@ L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 W:      http://www.mcuos.com
 S:      Maintained
 F:      arch/arm/mach-w90x900/
-F:      arch/arm/mach-nuc93x/
 F:      drivers/input/keyboard/w90p910_keypad.c
 F:      drivers/input/touchscreen/w90p910_ts.c
 F:      drivers/watchdog/nuc900_wdt.c
 F:      drivers/net/ethernet/nuvoton/w90p910_ether.c
 F:      drivers/mtd/nand/nuc900_nand.c
 F:      drivers/rtc/rtc-nuc900.c
-F:      drivers/spi/spi_nuc900.c
+F:      drivers/spi/spi-nuc900.c
 F:      drivers/usb/host/ehci-w90x900.c
 F:      drivers/video/nuc900fb.c
@@ -1184,7 +1171,6 @@ L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:      Maintained
 F:      arch/arm/mach-ux500/
 F:      drivers/dma/ste_dma40*
-F:      drivers/mfd/ab3550*
 F:      drivers/mfd/abx500*
 F:      drivers/mfd/ab8500*
 F:      drivers/mfd/stmpe*
@@ -1364,7 +1350,7 @@ F:	drivers/net/ethernet/cadence/
 ATMEL SPI DRIVER
 M:      Nicolas Ferre <nicolas.ferre@atmel.com>
 S:      Supported
-F:      drivers/spi/atmel_spi.*
+F:      drivers/spi/spi-atmel.*
 ATMEL USBA UDC DRIVER
 M:      Nicolas Ferre <nicolas.ferre@atmel.com>
@@ -1426,6 +1412,7 @@ F:	net/ax25/
 B43 WIRELESS DRIVER
 M:      Stefano Brivio <stefano.brivio@polimi.it>
 L:      linux-wireless@vger.kernel.org
+L:      b43-dev@lists.infradead.org (moderated for non-subscribers)
 W:      http://linuxwireless.org/en/users/Drivers/b43
 S:      Maintained
 F:      drivers/net/wireless/b43/
@@ -1503,7 +1490,7 @@ M:	Sonic Zhang <sonic.zhang@analog.com>
 L:      uclinux-dist-devel@blackfin.uclinux.org
 W:      http://blackfin.uclinux.org
 S:      Supported
-F:      drivers/tty/serial/bfin_5xx.c
+F:      drivers/tty/serial/bfin_uart.c
 BLACKFIN WATCHDOG DRIVER
 M:      Mike Frysinger <vapier.adi@gmail.com>
@@ -1594,7 +1581,7 @@ M:	Franky (Zhenhui) Lin <frankyl@broadcom.com>
 M:      Kan Yan <kanyan@broadcom.com>
 L:      linux-wireless@vger.kernel.org
 S:      Supported
-F:      drivers/staging/brcm80211/
+F:      drivers/net/wireless/brcm80211/
 BROADCOM BNX2FC 10 GIGABIT FCOE DRIVER
 M:      Bhanu Prakash Gollapudi <bprakash@broadcom.com>
@@ -1602,6 +1589,13 @@ L:	linux-scsi@vger.kernel.org
 S:      Supported
 F:      drivers/scsi/bnx2fc/
+BROADCOM SPECIFIC AMBA DRIVER (BCMA)
+M:      Rafał Miłecki <zajec5@gmail.com>
+L:      linux-wireless@vger.kernel.org
+S:      Maintained
+F:      drivers/bcma/
+F:      include/linux/bcma/
 BROCADE BFA FC SCSI DRIVER
 M:      Jing Huang <huangj@brocade.com>
 L:      linux-scsi@vger.kernel.org
@@ -1633,7 +1627,7 @@ BT8XXGPIO DRIVER
 M:      Michael Buesch <m@bues.ch>
 W:      http://bu3sch.de/btgpio.php
 S:      Maintained
-F:      drivers/gpio/bt8xxgpio.c
+F:      drivers/gpio/gpio-bt8xx.c
 BTRFS FILE SYSTEM
 M:      Chris Mason <chris.mason@oracle.com>
@@ -1661,6 +1655,14 @@ T:	git git://git.alsa-project.org/alsa-kernel.git
 S:      Maintained
 F:      sound/pci/oxygen/
+C6X ARCHITECTURE
+M:      Mark Salter <msalter@redhat.com>
+M:      Aurelien Jacquiot <a-jacquiot@ti.com>
+L:      linux-c6x-dev@linux-c6x.org
+W:      http://www.linux-c6x.org/wiki/index.php/Main_Page
+S:      Maintained
+F:      arch/c6x/
 CACHEFILES: FS-CACHE BACKEND FOR CACHING ON MOUNTED FILESYSTEMS
 M:      David Howells <dhowells@redhat.com>
 L:      linux-cachefs@redhat.com
@@ -1674,7 +1676,7 @@ L:	linux-media@vger.kernel.org
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6.git
 S:      Maintained
 F:      Documentation/video4linux/cafe_ccic
-F:      drivers/media/video/cafe_ccic*
+F:      drivers/media/video/marvell-ccic/
 CAIF NETWORK LAYER
 M:      Sjur Braendeland <sjur.brandeland@stericsson.com>
@@ -1898,12 +1900,6 @@ L:	platform-driver-x86@vger.kernel.org
 S:      Maintained
 F:      drivers/platform/x86/compal-laptop.c
-COMPUTONE INTELLIPORT MULTIPORT CARD
-W:      http://www.wittsend.com/computone.html
-S:      Orphan
-F:      Documentation/serial/computone.txt
-F:      drivers/staging/tty/ip2/
 CONEXANT ACCESSRUNNER USB DRIVER
 M:      Simon Arlott <cxacru@fire.lp0.eu>
 L:      accessrunner-general@lists.sourceforge.net
@@ -2118,7 +2114,7 @@ DAVICOM FAST ETHERNET (DMFE) NETWORK DRIVER
 L:      netdev@vger.kernel.org
 S:      Orphan
 F:      Documentation/networking/dmfe.txt
-F:      drivers/net/ethernet/tulip/dmfe.c
+F:      drivers/net/ethernet/dec/tulip/dmfe.c
 DC390/AM53C974 SCSI driver
 M:      Kurt Garloff <garloff@suse.de>
@@ -2191,6 +2187,13 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git
 S:      Maintained
 F:      drivers/usb/dwc3/
+DEVICE FREQUENCY (DEVFREQ)
+M:      MyungJoo Ham <myungjoo.ham@samsung.com>
+M:      Kyungmin Park <kyungmin.park@samsung.com>
+L:      linux-kernel@vger.kernel.org
+S:      Maintained
+F:      drivers/devfreq/
 DEVICE NUMBER REGISTRY
 M:      Torben Mathiasen <device@lanana.org>
 W:      http://lanana.org/docs/device-list/index.html
@@ -2207,15 +2210,6 @@ F:	drivers/md/dm*
 F:      include/linux/device-mapper.h
 F:      include/linux/dm-*.h
-DIGI INTL. EPCA DRIVER
-M:      "Digi International, Inc" <Eng.Linux@digi.com>
-L:      Eng.Linux@digi.com
-W:      http://www.digi.com
-S:      Orphan
-F:      Documentation/serial/digiepca.txt
-F:      drivers/staging/tty/epca*
-F:      drivers/staging/tty/digi*
 DIOLAN U2C-12 I2C DRIVER
 M:      Guenter Roeck <guenter.roeck@ericsson.com>
 L:      linux-i2c@vger.kernel.org
@@ -2927,6 +2921,7 @@ F:	include/linux/gigaset_dev.h
 GPIO SUBSYSTEM
 M:      Grant Likely <grant.likely@secretlab.ca>
+M:      Linus Walleij <linus.walleij@stericsson.com>
 S:      Maintained
 T:      git git://git.secretlab.ca/git/linux-2.6.git
 F:      Documentation/gpio.txt
@@ -2944,7 +2939,7 @@ GRETH 10/100/1G Ethernet MAC device driver
 M:      Kristoffer Glembo <kristoffer@gaisler.com>
 L:      netdev@vger.kernel.org
 S:      Maintained
-F:      drivers/net/greth*
+F:      drivers/net/ethernet/aeroflex/
 GSPCA FINEPIX SUBDRIVER
 M:      Frank Zago <frank@zago.net>
@@ -3196,6 +3191,16 @@ M:	William Irwin <wli@holomorphy.com>
 S:      Maintained
 F:      fs/hugetlbfs/
+Hyper-V CORE AND DRIVERS
+M:      K. Y. Srinivasan <kys@microsoft.com>
+M:      Haiyang Zhang <haiyangz@microsoft.com>
+L:      devel@linuxdriverproject.org
+S:      Maintained
+F:      drivers/hv/
+F:      drivers/hid/hid-hyperv.c
+F:      drivers/net/hyperv/
+F:      drivers/staging/hv/
 I2C/SMBUS STUB DRIVER
 M:      "Mark M. Hoffman" <mhoffman@lightlink.com>
 L:      linux-i2c@vger.kernel.org
@@ -3205,6 +3210,7 @@ F:	drivers/i2c/busses/i2c-stub.c
 I2C SUBSYSTEM
 M:      "Jean Delvare (PC drivers, core)" <khali@linux-fr.org>
 M:      "Ben Dooks (embedded platforms)" <ben-linux@fluff.org>
+M:      "Wolfram Sang (embedded platforms)" <w.sang@pengutronix.de>
 L:      linux-i2c@vger.kernel.org
 W:      http://i2c.wiki.kernel.org/
 T:      quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-i2c/
@@ -3591,8 +3597,7 @@ F:	net/netfilter/ipvs/
 IPWIRELESS DRIVER
 M:      Jiri Kosina <jkosina@suse.cz>
 M:      David Sterba <dsterba@suse.cz>
-S:      Maintained
+S:      Odd Fixes
-T:      git git://git.kernel.org/pub/scm/linux/kernel/git/jikos/ipwireless_cs.git
 F:      drivers/tty/ipwireless/
 IPX NETWORK LAYER
@@ -3787,7 +3792,6 @@ S:	Odd Fixes
 KERNEL NFSD, SUNRPC, AND LOCKD SERVERS
 M:      "J. Bruce Fields" <bfields@fieldses.org>
-M:      Neil Brown <neilb@suse.de>
 L:      linux-nfs@vger.kernel.org
 W:      http://nfs.sourceforge.net/
 S:      Supported
@@ -3885,8 +3889,7 @@ L:	keyrings@linux-nfs.org
 S:      Supported
 F:      Documentation/security/keys-trusted-encrypted.txt
 F:      include/keys/encrypted-type.h
-F:      security/keys/encrypted.c
+F:      security/keys/encrypted-keys/
-F:      security/keys/encrypted.h
 KGDB / KDB /debug_core
 M:      Jason Wessel <jason.wessel@windriver.com>
@@ -4019,7 +4022,7 @@ M:	Josh Boyer <jwboyer@gmail.com>
 M:      Matt Porter <mporter@kernel.crashing.org>
 W:      http://www.penguinppc.org/
 L:      linuxppc-dev@lists.ozlabs.org
-T:      git git://git.kernel.org/pub/scm/linux/kernel/git/jwboyer/powerpc-4xx.git
+T:      git git://git.infradead.org/users/jwboyer/powerpc-4xx.git
 S:      Maintained
 F:      arch/powerpc/platforms/40x/
 F:      arch/powerpc/platforms/44x/
@@ -4697,6 +4700,8 @@ Q:	http://patchwork.kernel.org/project/linux-omap/list/
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
 S:      Maintained
 F:      arch/arm/*omap*/
+F:      drivers/i2c/busses/i2c-omap.c
+F:      include/linux/i2c-omap.h
 OMAP CLOCK FRAMEWORK SUPPORT
 M:      Paul Walmsley <paul@pwsan.com>
@@ -4862,6 +4867,14 @@ S:	Maintained
 T:      git git://openrisc.net/~jonas/linux
 F:      arch/openrisc
+OPENVSWITCH
+M:      Jesse Gross <jesse@nicira.com>
+L:      dev@openvswitch.org
+W:      http://openvswitch.org
+T:      git git://git.kernel.org/pub/scm/linux/kernel/git/jesse/openvswitch.git
+S:      Maintained
+F:      net/openvswitch/
 OPL4 DRIVER
 M:      Clemens Ladisch <clemens@ladisch.de>
 L:      alsa-devel@alsa-project.org (moderated for non-subscribers)
@@ -5128,10 +5141,19 @@ L:	linux-mtd@lists.infradead.org
 S:      Maintained
 F:      drivers/mtd/devices/phram.c
+PICOXCELL SUPPORT
+M:      Jamie Iles <jamie@jamieiles.com>
+L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+T:      git git://github.com/jamieiles/linux-2.6-ji.git
+S:      Supported
+F:      arch/arm/mach-picoxcell
+F:      drivers/*/picoxcell*
+F:      drivers/*/*/picoxcell*
 PIN CONTROL SUBSYSTEM
 M:      Linus Walleij <linus.walleij@linaro.org>
 S:      Maintained
-F:      drivers/pinmux/
+F:      drivers/pinctrl/
 PKTCDVD DRIVER
 M:      Peter Osterlund <petero2@telia.com>
@@ -5314,35 +5336,27 @@ F:	drivers/media/video/pvrusb2/
 PXA2xx/PXA3xx SUPPORT
 M:      Eric Miao <eric.y.miao@gmail.com>
 M:      Russell King <linux@arm.linux.org.uk>
+M:      Haojian Zhuang <haojian.zhuang@marvell.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+T:      git git://github.com/hzhuang1/linux.git
+T:      git git://git.linaro.org/people/ycmiao/pxa-linux.git
 S:      Maintained
 F:      arch/arm/mach-pxa/
 F:      drivers/pcmcia/pxa2xx*
-F:      drivers/spi/pxa2xx*
+F:      drivers/spi/spi-pxa2xx*
 F:      drivers/usb/gadget/pxa2*
 F:      include/sound/pxa2xx-lib.h
 F:      sound/arm/pxa*
 F:      sound/soc/pxa
-PXA168 SUPPORT
+MMP SUPPORT
 M:      Eric Miao <eric.y.miao@gmail.com>
-M:      Jason Chagas <jason.chagas@marvell.com>
-L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-T:      git git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git
-S:      Maintained
-PXA910 SUPPORT
-M:      Eric Miao <eric.y.miao@gmail.com>
-L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-T:      git git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git
-S:      Maintained
-MMP2 SUPPORT (aka ARMADA610)
 M:      Haojian Zhuang <haojian.zhuang@marvell.com>
-M:      Eric Miao <eric.y.miao@gmail.com>
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-T:      git git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git
+T:      git git://github.com/hzhuang1/linux.git
+T:      git git://git.linaro.org/people/ycmiao/pxa-linux.git
 S:      Maintained
+F:      arch/arm/mach-mmp/
 PXA MMCI DRIVER
 S:      Orphan
@@ -5381,6 +5395,7 @@ S:	Supported
 F:      drivers/scsi/qla4xxx/
 QLOGIC QLA3XXX NETWORK DRIVER
+M:      Jitendra Kalsaria <jitendra.kalsaria@qlogic.com>
 M:      Ron Mercer <ron.mercer@qlogic.com>
 M:      linux-driver@qlogic.com
 L:      netdev@vger.kernel.org
@@ -5551,11 +5566,6 @@ M:	Maxim Levitsky <maximlevitsky@gmail.com>
 S:      Maintained
 F:      drivers/memstick/host/r592.*
-RISCOM8 DRIVER
-S:      Orphan
-F:      Documentation/serial/riscom8.txt
-F:      drivers/staging/tty/riscom8*
 ROCKETPORT DRIVER
 P:      Comtrol Corp.
 W:      http://www.comtrol.com
@@ -5676,6 +5686,12 @@ L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
 S:      Supported
 F:      sound/soc/samsung
+SAMSUNG FRAMEBUFFER DRIVER
+M:      Jingoo Han <jg1.han@samsung.com>
+L:      linux-fbdev@vger.kernel.org
+S:      Maintained
+F:      drivers/video/s3c-fb.c
 SERIAL DRIVERS
 M:      Alan Cox <alan@linux.intel.com>
 L:      linux-serial@vger.kernel.org
@@ -5815,13 +5831,14 @@ L:	linux-mmc@vger.kernel.org
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc.git
 S:      Maintained
 F:      drivers/mmc/host/sdhci.*
+F:      drivers/mmc/host/sdhci-pltfm.[ch]
 SECURE DIGITAL HOST CONTROLLER INTERFACE, OPEN FIRMWARE BINDINGS (SDHCI-OF)
 M:      Anton Vorontsov <avorontsov@ru.mvista.com>
 L:      linuxppc-dev@lists.ozlabs.org
 L:      linux-mmc@vger.kernel.org
 S:      Maintained
-F:      drivers/mmc/host/sdhci-of.*
+F:      drivers/mmc/host/sdhci-pltfm.[ch]
 SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) SAMSUNG DRIVER
 M:      Ben Dooks <ben-linux@fluff.org>
@@ -5838,7 +5855,7 @@ F:	drivers/mmc/host/sdhci-spear.c
 SECURITY SUBSYSTEM
 M:      James Morris <jmorris@namei.org>
 L:      linux-security-module@vger.kernel.org (suggested Cc:)
-T:      git git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/security-testing-2.6.git
+T:      git git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security.git
 W:      http://security.wiki.kernel.org/
 S:      Supported
 F:      security/
@@ -5900,7 +5917,6 @@ F:	drivers/net/ethernet/emulex/benet/
 SFC NETWORK DRIVER
 M:      Solarflare linux maintainers <linux-net-drivers@solarflare.com>
-M:      Steve Hodgson <shodgson@solarflare.com>
 M:      Ben Hutchings <bhutchings@solarflare.com>
 L:      netdev@vger.kernel.org
 S:      Supported
@@ -5965,6 +5981,7 @@ L:	davinci-linux-open-source@linux.davincidsp.com (subscribers-only)
 Q:      http://patchwork.kernel.org/project/linux-davinci/list/
 S:      Supported
 F:      arch/arm/mach-davinci
+F:      drivers/i2c/busses/i2c-davinci.c
 SIS 190 ETHERNET DRIVER
 M:      Francois Romieu <romieu@fr.zoreil.com>
@@ -6108,13 +6125,6 @@ S:	Maintained
 F:      drivers/ssb/
 F:      include/linux/ssb/
-BROADCOM SPECIFIC AMBA DRIVER (BCMA)
-M:      Rafał Miłecki <zajec5@gmail.com>
-L:      linux-wireless@vger.kernel.org
-S:      Maintained
-F:      drivers/bcma/
-F:      include/linux/bcma/
 SONY VAIO CONTROL DEVICE DRIVER
 M:      Mattia Dongili <malattia@linux.it>
 L:      platform-driver-x86@vger.kernel.org
@@ -6201,9 +6211,7 @@ M:	Viresh Kumar <viresh.kumar@st.com>
 W:      http://www.st.com/spear
 S:      Maintained
 F:      arch/arm/mach-spear*/clock.c
-F:      arch/arm/mach-spear*/include/mach/clkdev.h
 F:      arch/arm/plat-spear/clock.c
-F:      arch/arm/plat-spear/include/plat/clkdev.h
 F:      arch/arm/plat-spear/include/plat/clock.h
 SPEAR PAD MULTIPLEXING SUPPORT
@@ -6219,11 +6227,6 @@ F:	arch/arm/mach-spear3xx/spear3*0_evb.c
 F:      arch/arm/mach-spear6xx/spear600.c
 F:      arch/arm/mach-spear6xx/spear600_evb.c
-SPECIALIX IO8+ MULTIPORT SERIAL CARD DRIVER
-S:      Orphan
-F:      Documentation/serial/specialix.txt
-F:      drivers/staging/tty/specialix*
 SPI SUBSYSTEM
 M:      Grant Likely <grant.likely@secretlab.ca>
 L:      spi-devel-general@lists.sourceforge.net
@@ -6266,7 +6269,7 @@ F:	arch/alpha/kernel/srm_env.c
 STABLE BRANCH
 M:      Greg Kroah-Hartman <greg@kroah.com>
-L:      stable@kernel.org
+L:      stable@vger.kernel.org
 S:      Maintained
 STAGING SUBSYSTEM
@@ -6301,11 +6304,6 @@ M:	Manu Abraham <abraham.manu@gmail.com>
 S:      Odd Fixes
 F:      drivers/staging/crystalhd/
-STAGING - CYPRESS WESTBRIDGE SUPPORT
-M:      David Cross <david.cross@cypress.com>
-S:      Odd Fixes
-F:      drivers/staging/westbridge/
 STAGING - ECHO CANCELLER
 M:      Steve Underwood <steveu@coppice.org>
 M:      David Rowe <david@rowetel.com>
@@ -6327,12 +6325,6 @@ M:	David Täht <d@teklibre.com>
 S:      Odd Fixes
 F:      drivers/staging/frontier/
-STAGING - HYPER-V (MICROSOFT)
-M:      Hank Janssen <hjanssen@microsoft.com>
-M:      Haiyang Zhang <haiyangz@microsoft.com>
-S:      Odd Fixes
-F:      drivers/staging/hv/
 STAGING - INDUSTRIAL IO
 M:      Jonathan Cameron <jic23@cam.ac.uk>
 L:      linux-iio@vger.kernel.org
@@ -6343,7 +6335,7 @@ STAGING - LIRC (LINUX INFRARED REMOTE CONTROL) DRIVERS
 M:      Jarod Wilson <jarod@wilsonet.com>
 W:      http://www.lirc.org/
 S:      Odd Fixes
-F:      drivers/staging/lirc/
+F:      drivers/staging/media/lirc/
 STAGING - NVIDIA COMPLIANT EMBEDDED CONTROLLER INTERFACE (nvec)
 M:      Julian Andres Klode <jak@jak-linux.org>
@@ -6379,7 +6371,7 @@ F:	drivers/staging/sm7xx/
 STAGING - SOFTLOGIC 6x10 MPEG CODEC
 M:      Ben Collins <bcollins@bluecherry.net>
 S:      Odd Fixes
-F:      drivers/staging/solo6x10/
+F:      drivers/staging/media/solo6x10/
 STAGING - SPEAKUP CONSOLE SPEECH DRIVER
 M:      William Hubbs <w.d.hubbs@gmail.com>
@@ -6417,7 +6409,7 @@ S:	Odd Fixes
 F:      drivers/staging/winbond/
 STAGING - XGI Z7,Z9,Z11 PCI DISPLAY DRIVER
-M:      Arnaud Patard <apatard@mandriva.com>
+M:      Arnaud Patard <arnaud.patard@rtp-net.org>
 S:      Odd Fixes
 F:      drivers/staging/xgifb/
@@ -6508,6 +6500,13 @@ W:	http://tcp-lp-mod.sourceforge.net/
 S:      Maintained
 F:      net/ipv4/tcp_lp.c
+TEAM DRIVER
+M:      Jiri Pirko <jpirko@redhat.com>
+L:      netdev@vger.kernel.org
+S:      Supported
+F:      drivers/net/team/
+F:      include/linux/if_team.h
 TEGRA SUPPORT
 M:      Colin Cross <ccross@android.com>
 M:      Olof Johansson <olof@lixom.net>
@@ -6675,7 +6674,7 @@ TULIP NETWORK DRIVERS
 M:      Grant Grundler <grundler@parisc-linux.org>
 L:      netdev@vger.kernel.org
 S:      Maintained
-F:      drivers/net/ethernet/tulip/
+F:      drivers/net/ethernet/dec/tulip/
 TUN/TAP driver
 M:      Maxim Krasnyansky <maxk@qualcomm.com>
@@ -7201,7 +7200,7 @@ S:	Maintained
 F:      drivers/net/vmxnet3/
 VMware PVSCSI driver
-M:      Alok Kataria <akataria@vmware.com>
+M:      Arvind Kumar <arvindkumar@vmware.com>
 M:      VMware PV-Drivers <pv-drivers@vmware.com>
 L:      linux-scsi@vger.kernel.org
 S:      Maintained
diff --git a/Makefile b/Makefile
index adddd11c3b3..156ac69c961 100644
--- a/Makefile
+++ b/Makefile
@@ -312,7 +312,7 @@ endif
 # If the user is running make -s (silent mode), suppress echoing of
 # commands
-ifneq ($(findstring s,$(MAKEFLAGS)),)
+ifneq ($(filter s% -s%,$(MAKEFLAGS)),)
  quiet=silent_
 endif
@@ -442,7 +442,7 @@ asm-generic:
 no-dot-config-targets := clean mrproper distclean \
                         cscope gtags TAGS tags help %docs check% coccicheck \
-                         include/linux/version.h headers_% \
+                         include/linux/version.h headers_% archheaders \
                         kernelversion %src-pkg
 config-targets := 0
@@ -979,7 +979,7 @@ prepare1: prepare2 include/linux/version.h include/generated/utsrelease.h \
                   include/config/auto.conf
        $(cmd_crmodverdir)
-archprepare: prepare1 scripts_basic
+archprepare: archheaders prepare1 scripts_basic
 prepare0: archprepare FORCE
        $(Q)$(MAKE) $(build)=.
@@ -1046,8 +1046,11 @@ hdr-inst := -rR -f $(srctree)/scripts/Makefile.headersinst obj
 # If we do an all arch process set dst to asm-$(hdr-arch)
 hdr-dst = $(if $(KBUILD_HEADERS), dst=include/asm-$(hdr-arch), dst=include/asm)
+PHONY += archheaders
+archheaders:
 PHONY += __headers
-__headers: include/linux/version.h scripts_basic asm-generic FORCE
+__headers: include/linux/version.h scripts_basic asm-generic archheaders FORCE
        $(Q)$(MAKE) $(build)=scripts build_unifdef
 PHONY += headers_install_all
diff --git a/arch/Kconfig b/arch/Kconfig
index 4b0669cbb3b..4f55c736be1 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -30,6 +30,10 @@ config OPROFILE_EVENT_MULTIPLEX
 config HAVE_OPROFILE
        bool
+config OPROFILE_NMI_TIMER
+        def_bool y
+        depends on PERF_EVENTS && HAVE_PERF_EVENTS_NMI
 config KPROBES
        bool "Kprobes"
        depends on MODULES
@@ -181,4 +185,18 @@ config HAVE_RCU_TABLE_FREE
 config ARCH_HAVE_NMI_SAFE_CMPXCHG
        bool
+config HAVE_ALIGNED_STRUCT_PAGE
+        bool
+        help
+          This makes sure that struct pages are double word aligned and that
+          e.g. the SLUB allocator can perform double word atomic operations
+          on a struct page for better performance. However selecting this
+          might increase the size of a struct page by a word.
+config HAVE_CMPXCHG_LOCAL
+        bool
+config HAVE_CMPXCHG_DOUBLE
+        bool
 source "kernel/gcov/Kconfig"
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 3d74801a401..56a4df952fb 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -70,10 +70,6 @@ config GENERIC_ISA_DMA
        bool
        default y
-config GENERIC_IOMAP
-        bool
-        default n
 source "init/Kconfig"
 source "kernel/Kconfig.freezer"
@@ -319,6 +315,7 @@ config ISA_DMA_API
 config PCI
        bool
        depends on !ALPHA_JENSEN
+        select GENERIC_PCI_IOMAP
        default y
        help
          Find out whether you have a PCI motherboard. PCI is the name of a
diff --git a/arch/alpha/include/asm/ipcbuf.h b/arch/alpha/include/asm/ipcbuf.h
index d9c0e1a5070..84c7e51cb6d 100644
--- a/arch/alpha/include/asm/ipcbuf.h
+++ b/arch/alpha/include/asm/ipcbuf.h
@@ -1,28 +1 @@
-#ifndef _ALPHA_IPCBUF_H
+#include <asm-generic/ipcbuf.h>
-#define _ALPHA_IPCBUF_H
-/* 
- * The ipc64_perm structure for alpha architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit seq
- * - 2 miscellaneous 64-bit values
- */
-struct ipc64_perm
-{
-        __kernel_key_t  key;
-        __kernel_uid_t  uid;
-        __kernel_gid_t  gid;
-        __kernel_uid_t  cuid;
-        __kernel_gid_t  cgid;
-        __kernel_mode_t mode; 
-        unsigned short  seq;
-        unsigned short  __pad1;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-};
-#endif /* _ALPHA_IPCBUF_H */
diff --git a/arch/alpha/include/asm/socket.h b/arch/alpha/include/asm/socket.h
index 06edfefc337..082355f159e 100644
--- a/arch/alpha/include/asm/socket.h
+++ b/arch/alpha/include/asm/socket.h
@@ -69,6 +69,9 @@
 #define SO_RXQ_OVFL             40
+#define SO_WIFI_STATUS          41
+#define SCM_WIFI_STATUS         SO_WIFI_STATUS
 /* O_NONBLOCK clashes with the bits used for socket types.  Therefore we
 * have to define SOCK_NONBLOCK to a different value here.
 */
diff --git a/arch/alpha/include/asm/thread_info.h b/arch/alpha/include/asm/thread_info.h
index ff73db02234..28335bd40e4 100644
--- a/arch/alpha/include/asm/thread_info.h
+++ b/arch/alpha/include/asm/thread_info.h
@@ -79,7 +79,6 @@ register struct thread_info *__current_thread_info __asm__("$8");
 #define TIF_UAC_SIGBUS          12      /* ! userspace part of 'osf_sysinfo' */
 #define TIF_MEMDIE              13      /* is terminating due to OOM killer */
 #define TIF_RESTORE_SIGMASK     14      /* restore signal mask in do_signal */
-#define TIF_FREEZE              16      /* is freezing for suspend */
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
@@ -87,7 +86,6 @@ register struct thread_info *__current_thread_info __asm__("$8");
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
-#define _TIF_FREEZE             (1<<TIF_FREEZE)
 /* Work to do on interrupt/exception return.  */
 #define _TIF_WORK_MASK          (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
diff --git a/arch/alpha/include/asm/types.h b/arch/alpha/include/asm/types.h
index 881544339c2..0a0579076f4 100644
--- a/arch/alpha/include/asm/types.h
+++ b/arch/alpha/include/asm/types.h
@@ -15,9 +15,4 @@
 #include <asm-generic/int-l64.h>
 #endif
-#ifndef __ASSEMBLY__
-typedef unsigned int umode_t;
-#endif /* __ASSEMBLY__ */
 #endif /* _ALPHA_TYPES_H */
diff --git a/arch/alpha/kernel/pci-noop.c b/arch/alpha/kernel/pci-noop.c
index 246100ef07c..04eea4894ef 100644
--- a/arch/alpha/kernel/pci-noop.c
+++ b/arch/alpha/kernel/pci-noop.c
@@ -185,15 +185,3 @@ struct dma_map_ops alpha_noop_ops = {
 struct dma_map_ops *dma_ops = &alpha_noop_ops;
 EXPORT_SYMBOL(dma_ops);
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        return NULL;
-}
-void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
-{
-}
-EXPORT_SYMBOL(pci_iomap);
-EXPORT_SYMBOL(pci_iounmap);
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index c9ab94ee1ca..8c723c1b086 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -281,27 +281,9 @@ pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
 void __devinit
 pcibios_fixup_bus(struct pci_bus *bus)
 {
-        /* Propagate hose info into the subordinate devices.  */
-        struct pci_controller *hose = bus->sysdata;
        struct pci_dev *dev = bus->self;
-        if (!dev) {
+        if (pci_probe_only && dev &&
-                /* Root bus. */
-                u32 pci_mem_end;
-                u32 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
-                unsigned long end;
-                bus->resource[0] = hose->io_space;
-                bus->resource[1] = hose->mem_space;
-                /* Adjust hose mem_space limit to prevent PCI allocations
-                   in the iommu windows. */
-                pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
-                end = hose->mem_space->start + pci_mem_end;
-                if (hose->mem_space->end > end)
-                        hose->mem_space->end = end;
-        } else if (pci_probe_only &&
                   (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
                pci_read_bridge_bases(bus);
                pcibios_fixup_device_resources(dev, bus);
@@ -414,13 +396,31 @@ void __init
 common_init_pci(void)
 {
        struct pci_controller *hose;
+        struct list_head resources;
        struct pci_bus *bus;
        int next_busno;
        int need_domain_info = 0;
+        u32 pci_mem_end;
+        u32 sg_base;
+        unsigned long end;
        /* Scan all of the recorded PCI controllers.  */
        for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
-                bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose);
+                sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
+                /* Adjust hose mem_space limit to prevent PCI allocations
+                   in the iommu windows. */
+                pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
+                end = hose->mem_space->start + pci_mem_end;
+                if (hose->mem_space->end > end)
+                        hose->mem_space->end = end;
+                INIT_LIST_HEAD(&resources);
+                pci_add_resource(&resources, hose->io_space);
+                pci_add_resource(&resources, hose->mem_space);
+                bus = pci_scan_root_bus(NULL, next_busno, alpha_mv.pci_ops,
+                                        hose, &resources);
                hose->bus = bus;
                hose->need_domain_info = need_domain_info;
                next_busno = bus->subordinate + 1;
@@ -508,30 +508,7 @@ sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
        return -EOPNOTSUPP;
 }
-/* Create an __iomem token from a PCI BAR.  Copied from lib/iomap.c with
+/* Destroy an __iomem token.  Not copied from lib/iomap.c.  */
-   no changes, since we don't want the other things in that object file.  */
-void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
-{
-        resource_size_t start = pci_resource_start(dev, bar);
-        resource_size_t len = pci_resource_len(dev, bar);
-        unsigned long flags = pci_resource_flags(dev, bar);
-        if (!len || !start)
-                return NULL;
-        if (maxlen && len > maxlen)
-                len = maxlen;
-        if (flags & IORESOURCE_IO)
-                return ioport_map(start, len);
-        if (flags & IORESOURCE_MEM) {
-                /* Not checking IORESOURCE_CACHEABLE because alpha does
-                   not distinguish between ioremap and ioremap_nocache.  */
-                return ioremap(start, len);
-        }
-        return NULL;
-}
-/* Destroy that token.  Not copied from lib/iomap.c.  */
 void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
 {
@@ -539,7 +516,6 @@ void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
                iounmap(addr);
 }
-EXPORT_SYMBOL(pci_iomap);
 EXPORT_SYMBOL(pci_iounmap);
 /* FIXME: Some boxes have multiple ISA bridges! */
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b259c7c644e..24626b0419e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARM
        select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
        select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
        select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
+        select ARCH_BINFMT_ELF_RANDOMIZE_PIE
        select HAVE_GENERIC_DMA_COHERENT
        select HAVE_KERNEL_GZIP
        select HAVE_KERNEL_LZO
@@ -30,6 +31,7 @@ config ARM
        select HAVE_SPARSE_IRQ
        select GENERIC_IRQ_SHOW
        select CPU_PM if (SUSPEND || CPU_IDLE)
+        select GENERIC_PCI_IOMAP
        help
          The ARM series is a line of low-power-consumption RISC chip designs
          licensed by ARM Ltd and targeted at embedded applications and
@@ -258,6 +260,7 @@ config ARCH_INTEGRATOR
        select ARCH_HAS_CPUFREQ
        select CLKDEV_LOOKUP
        select HAVE_MACH_CLKDEV
+        select HAVE_TCM
        select ICST
        select GENERIC_CLOCKEVENTS
        select PLAT_VERSATILE
@@ -341,10 +344,12 @@ config ARCH_HIGHBANK
        select ARM_AMBA
        select ARM_GIC
        select ARM_TIMER_SP804
+        select CACHE_L2X0
        select CLKDEV_LOOKUP
        select CPU_V7
        select GENERIC_CLOCKEVENTS
        select HAVE_ARM_SCU
+        select HAVE_SMP
        select USE_OF
        help
          Support for the Calxeda Highbank SoC based boards.
@@ -362,6 +367,7 @@ config ARCH_CNS3XXX
        select CPU_V6K
        select GENERIC_CLOCKEVENTS
        select ARM_GIC
+        select MIGHT_HAVE_CACHE_L2X0
        select MIGHT_HAVE_PCI
        select PCI_DOMAINS if PCI
        help
@@ -382,6 +388,7 @@ config ARCH_PRIMA2
        select GENERIC_CLOCKEVENTS
        select CLKDEV_LOOKUP
        select GENERIC_IRQ_CHIP
+        select MIGHT_HAVE_CACHE_L2X0
        select USE_OF
        select ZONE_DMA
        help
@@ -442,6 +449,7 @@ config ARCH_MXS
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
        select CLKSRC_MMIO
+        select HAVE_CLK_PREPARE
        help
          Support for Freescale MXS-based family of processors
@@ -592,6 +600,7 @@ config ARCH_MMP
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
        select GENERIC_CLOCKEVENTS
+        select GPIO_PXA
        select HAVE_SCHED_CLOCK
        select TICK_ONESHOT
        select PLAT_PXA
@@ -634,6 +643,8 @@ config ARCH_TEGRA
        select GENERIC_GPIO
        select HAVE_CLK
        select HAVE_SCHED_CLOCK
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
        select ARCH_HAS_CPUFREQ
        help
          This enables support for NVIDIA Tegra based systems (Tegra APX,
@@ -651,6 +662,7 @@ config ARCH_PICOXCELL
        select HAVE_SCHED_CLOCK
        select HAVE_TCM
        select NO_IOPORT
+        select SPARSE_IRQ
        select USE_OF
        help
          This enables support for systems based on the Picochip picoXcell
@@ -674,6 +686,7 @@ config ARCH_PXA
        select CLKSRC_MMIO
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_CLOCKEVENTS
+        select GPIO_PXA
        select HAVE_SCHED_CLOCK
        select TICK_ONESHOT
        select PLAT_PXA
@@ -703,7 +716,9 @@ config ARCH_SHMOBILE
        select HAVE_CLK
        select CLKDEV_LOOKUP
        select HAVE_MACH_CLKDEV
+        select HAVE_SMP
        select GENERIC_CLOCKEVENTS
+        select MIGHT_HAVE_CACHE_L2X0
        select NO_IOPORT
        select SPARSE_IRQ
        select MULTI_IRQ_HANDLER
@@ -739,7 +754,7 @@ config ARCH_SA1100
        select ARCH_HAS_CPUFREQ
        select CPU_FREQ
        select GENERIC_CLOCKEVENTS
-        select HAVE_CLK
+        select CLKDEV_LOOKUP
        select HAVE_SCHED_CLOCK
        select TICK_ONESHOT
        select ARCH_REQUIRE_GPIOLIB
@@ -868,16 +883,6 @@ config ARCH_SHARK
          Support for the StrongARM based Digital DNARD machine, also known
          as "Shark" (<http://www.shark-linux.de/shark.html>).
-config ARCH_TCC_926
-        bool "Telechips TCC ARM926-based systems"
-        select CLKSRC_MMIO
-        select CPU_ARM926T
-        select HAVE_CLK
-        select CLKDEV_LOOKUP
-        select GENERIC_CLOCKEVENTS
-        help
-          Support for Telechips TCC ARM926-based systems.
 config ARCH_U300
        bool "ST-Ericsson U300 Series"
        depends on MMU
@@ -893,7 +898,6 @@ config ARCH_U300
        select HAVE_MACH_CLKDEV
        select GENERIC_GPIO
        select ARCH_REQUIRE_GPIOLIB
-        select NEED_MACH_MEMORY_H
        help
          Support for ST-Ericsson U300 series mobile platforms.
@@ -905,6 +909,8 @@ config ARCH_U8500
        select CLKDEV_LOOKUP
        select ARCH_REQUIRE_GPIOLIB
        select ARCH_HAS_CPUFREQ
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
        help
          Support for ST-Ericsson's Ux500 architecture
@@ -915,6 +921,7 @@ config ARCH_NOMADIK
        select CPU_ARM926T
        select CLKDEV_LOOKUP
        select GENERIC_CLOCKEVENTS
+        select MIGHT_HAVE_CACHE_L2X0
        select ARCH_REQUIRE_GPIOLIB
        help
          Support for the Nomadik platform by ST-Ericsson
@@ -974,6 +981,7 @@ config ARCH_ZYNQ
        select ARM_GIC
        select ARM_AMBA
        select ICST
+        select MIGHT_HAVE_CACHE_L2X0
        select USE_OF
        help
          Support for Xilinx Zynq ARM Cortex A9 Platform
@@ -1060,8 +1068,6 @@ source "arch/arm/plat-s5p/Kconfig"
 source "arch/arm/plat-spear/Kconfig"
-source "arch/arm/plat-tcc/Kconfig"
 if ARCH_S3C2410
 source "arch/arm/mach-s3c2410/Kconfig"
 source "arch/arm/mach-s3c2412/Kconfig"
@@ -1126,6 +1132,11 @@ config ARM_TIMER_SP804
 source arch/arm/mm/Kconfig
+config ARM_NR_BANKS
+        int
+        default 16 if ARCH_EP93XX
+        default 8
 config IWMMXT
        bool "Enable iWMMXt support"
        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
@@ -1134,10 +1145,9 @@ config IWMMXT
          Enable support for iWMMXt context switching at run time if
          running on a CPU that supports it.
-#  bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
 config XSCALE_PMU
        bool
-        depends on CPU_XSCALE && !XSCALE_PMU_TIMER
+        depends on CPU_XSCALE
        default y
 config CPU_HAS_PMU
@@ -1435,14 +1445,20 @@ menu "Kernel Features"
 source "kernel/time/Kconfig"
+config HAVE_SMP
+        bool
+        help
+          This option should be selected by machines which have an SMP-
+          capable CPU.
+          The only effect of this option is to make the SMP-related
+          options available to the user for configuration.
 config SMP
        bool "Symmetric Multi-Processing"
        depends on CPU_V6K || CPU_V7
        depends on GENERIC_CLOCKEVENTS
-        depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
+        depends on HAVE_SMP
-                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
-                 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
-                 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
        depends on MMU
        select USE_GENERIC_SMP_HELPERS
        select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
@@ -1560,6 +1576,16 @@ config LOCAL_TIMERS
          accounting to be spread across the timer interval, preventing a
          "thundering herd" at every timer tick.
+config ARCH_NR_GPIO
+        int
+        default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
+        default 350 if ARCH_U8500
+        default 0
+        help
+          Maximum number of GPIOs in the system.
+          If unsure, leave the default value.
 source kernel/Kconfig.preempt
 config HZ
@@ -1972,7 +1998,7 @@ endchoice
 config XIP_KERNEL
        bool "Kernel Execute-In-Place from ROM"
-        depends on !ZBOOT_ROM
+        depends on !ZBOOT_ROM && !ARM_LPAE
        help
          Execute-In-Place allows the kernel to run from non-volatile storage
          directly addressable by the CPU, such as NOR flash. This saves RAM
@@ -2002,7 +2028,7 @@ config XIP_PHYS_ADDR
 config KEXEC
        bool "Kexec system call (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
+        depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
        help
          kexec is a system call that implements the ability to shutdown your
          current kernel, and to start another kernel.  It is like a reboot
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index c5213e78606..e0d236d7ff7 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -100,6 +100,14 @@ choice
                  Note that the system will appear to hang during boot if there
                  is nothing connected to read from the DCC.
+        config AT91_DEBUG_LL_DBGU0
+                bool "Kernel low-level debugging on rm9200, 9260/9g20, 9261/9g10 and 9rl"
+                depends on HAVE_AT91_DBGU0
+        config AT91_DEBUG_LL_DBGU1
+                bool "Kernel low-level debugging on 9263, 9g45 and cap9"
+                depends on HAVE_AT91_DBGU1
        config DEBUG_FOOTBRIDGE_COM1
                bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1"
                depends on FOOTBRIDGE
@@ -247,6 +255,43 @@ choice
                  their output to the standard serial port on the RealView
                  PB1176 platform.
+        config DEBUG_MSM_UART1
+                bool "Kernel low-level debugging messages via MSM UART1"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the first serial port on MSM devices.
+        config DEBUG_MSM_UART2
+                bool "Kernel low-level debugging messages via MSM UART2"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the second serial port on MSM devices.
+        config DEBUG_MSM_UART3
+                bool "Kernel low-level debugging messages via MSM UART3"
+                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the third serial port on MSM devices.
+        config DEBUG_MSM8660_UART
+                bool "Kernel low-level debugging messages via MSM 8660 UART"
+                depends on ARCH_MSM8X60
+                select MSM_HAS_DEBUG_UART_HS
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the serial port on MSM 8660 devices.
+        config DEBUG_MSM8960_UART
+                bool "Kernel low-level debugging messages via MSM 8960 UART"
+                depends on ARCH_MSM8960
+                select MSM_HAS_DEBUG_UART_HS
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to the serial port on MSM 8960 devices.
 endchoice
 config EARLY_PRINTK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index dfcf3b033e1..40319d91bb7 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -184,7 +184,6 @@ machine-$(CONFIG_ARCH_EXYNOS4)		:= exynos
 machine-$(CONFIG_ARCH_SA1100)           := sa1100
 machine-$(CONFIG_ARCH_SHARK)            := shark
 machine-$(CONFIG_ARCH_SHMOBILE)         := shmobile
-machine-$(CONFIG_ARCH_TCC8K)            := tcc8k
 machine-$(CONFIG_ARCH_TEGRA)            := tegra
 machine-$(CONFIG_ARCH_U300)             := u300
 machine-$(CONFIG_ARCH_U8500)            := ux500
@@ -204,7 +203,6 @@ machine-$(CONFIG_ARCH_ZYNQ)		:= zynq
 plat-$(CONFIG_ARCH_MXC)         := mxc
 plat-$(CONFIG_ARCH_OMAP)        := omap
 plat-$(CONFIG_ARCH_S3C64XX)     := samsung
-plat-$(CONFIG_ARCH_TCC_926)     := tcc
 plat-$(CONFIG_ARCH_ZYNQ)        := versatile
 plat-$(CONFIG_PLAT_IOP)         := iop
 plat-$(CONFIG_PLAT_NOMADIK)     := nomadik
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 5df26a9976a..fc871e719aa 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -59,9 +59,11 @@ $(obj)/zImage:	$(obj)/compressed/vmlinux FORCE
 endif
+targets += $(dtb-y)
 # Rule to build device tree blobs
-$(obj)/%.dtb: $(src)/dts/%.dts
+$(obj)/%.dtb: $(src)/dts/%.dts FORCE
-        $(call cmd,dtc)
+        $(call if_changed_dep,dtc)
 $(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 21f56ff3279..cf0a64ce4b8 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -126,7 +126,8 @@ ccflags-y := -fpic -fno-builtin -I$(obj)
 asflags-y := -Wa,-march=all
 # Supply kernel BSS size to the decompressor via a linker symbol.
-KBSS_SZ = $(shell size $(obj)/../../../../vmlinux | awk 'END{print $$3}')
+KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
+                awk 'END{print $$3}')
 LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
 # Supply ZRELADDR to the decompressor via a linker symbol.
 ifneq ($(CONFIG_AUTO_ZRELADDR),y)
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c2effc91725..c5d60250d43 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -659,6 +659,7 @@ __armv7_mmu_cache_on:
                mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
                mcrne   p15, 0, r1, c3, c0, 0   @ load domain access control
 #endif
+                mcr     p15, 0, r0, c7, c5, 4   @ ISB
                mcr     p15, 0, r0, c1, c0, 0   @ load control register
                mrc     p15, 0, r0, c1, c0, 0   @ and read it back
                mov     r0, #0
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index aeef04269cf..07603b8c950 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -114,6 +114,13 @@
                                atmel,use-dma-tx;
                                status = "disabled";
                        };
+                        macb0: ethernet@fffc4000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xfffc4000 0x100>;
+                                interrupts = <21>;
+                                status = "disabled";
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index db6a45202f2..fffa005300a 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -101,6 +101,13 @@
                                atmel,use-dma-tx;
                                status = "disabled";
                        };
+                        macb0: ethernet@fffbc000 {
+                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
+                                reg = <0xfffbc000 0x100>;
+                                interrupts = <25>;
+                                status = "disabled";
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 85b34f59cd8..a387e7704ce 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -30,6 +30,11 @@
                        usart1: serial@fff90000 {
                                status = "okay";
                        };
+                        macb0: ethernet@fffbc000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
new file mode 100644
index 00000000000..b8c476384ee
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -0,0 +1,137 @@
+/*
+ * Samsung's Exynos4210 based Origen board device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * Device tree source file for Insignal's Origen board which is based on
+ * Samsung's Exynos4210 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/dts-v1/;
+/include/ "exynos4210.dtsi"
+/ {
+        model = "Insignal Origen evaluation board based on Exynos4210";
+        compatible = "insignal,origen", "samsung,exynos4210";
+        memory {
+                reg = <0x40000000 0x40000000>;
+        };
+        chosen {
+                bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc";
+        };
+        sdhci@12530000 {
+                samsung,sdhci-bus-width = <4>;
+                linux,mmc_cap_4_bit_data;
+                samsung,sdhci-cd-internal;
+                gpio-cd = <&gpk2 2 2 3 3>;
+                gpios = <&gpk2 0 2 0 3>,
+                        <&gpk2 1 2 0 3>,
+                        <&gpk2 3 2 3 3>,
+                        <&gpk2 4 2 3 3>,
+                        <&gpk2 5 2 3 3>,
+                        <&gpk2 6 2 3 3>;
+        };
+        sdhci@12510000 {
+                samsung,sdhci-bus-width = <4>;
+                linux,mmc_cap_4_bit_data;
+                samsung,sdhci-cd-internal;
+                gpio-cd = <&gpk0 2 2 3 3>;
+                gpios = <&gpk0 0 2 0 3>,
+                        <&gpk0 1 2 0 3>,
+                        <&gpk0 3 2 3 3>,
+                        <&gpk0 4 2 3 3>,
+                        <&gpk0 5 2 3 3>,
+                        <&gpk0 6 2 3 3>;
+        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                up {
+                        label = "Up";
+                        gpios = <&gpx2 0 0 0 2>;
+                        linux,code = <103>;
+                };
+                down {
+                        label = "Down";
+                        gpios = <&gpx2 1 0 0 2>;
+                        linux,code = <108>;
+                };
+                back {
+                        label = "Back";
+                        gpios = <&gpx1 7 0 0 2>;
+                        linux,code = <158>;
+                };
+                home {
+                        label = "Home";
+                        gpios = <&gpx1 6 0 0 2>;
+                        linux,code = <102>;
+                };
+                menu {
+                        label = "Menu";
+                        gpios = <&gpx1 5 0 0 2>;
+                        linux,code = <139>;
+                };
+        };
+        keypad@100A0000 {
+                status = "disabled";
+        };
+        sdhci@12520000 {
+                status = "disabled";
+        };
+        sdhci@12540000 {
+                status = "disabled";
+        };
+        i2c@13860000 {
+                status = "disabled";
+        };
+        i2c@13870000 {
+                status = "disabled";
+        };
+        i2c@13880000 {
+                status = "disabled";
+        };
+        i2c@13890000 {
+                status = "disabled";
+        };
+        i2c@138A0000 {
+                status = "disabled";
+        };
+        i2c@138B0000 {
+                status = "disabled";
+        };
+        i2c@138C0000 {
+                status = "disabled";
+        };
+        i2c@138D0000 {
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
new file mode 100644
index 00000000000..27afc8e535c
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -0,0 +1,182 @@
+/*
+ * Samsung's Exynos4210 based SMDKV310 board device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * Device tree source file for Samsung's SMDKV310 board which is based on
+ * Samsung's Exynos4210 SoC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/dts-v1/;
+/include/ "exynos4210.dtsi"
+/ {
+        model = "Samsung smdkv310 evaluation board based on Exynos4210";
+        compatible = "samsung,smdkv310", "samsung,exynos4210";
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+        chosen {
+                bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
+        };
+        sdhci@12530000 {
+                samsung,sdhci-bus-width = <4>;
+                linux,mmc_cap_4_bit_data;
+                samsung,sdhci-cd-internal;
+                gpio-cd = <&gpk2 2 2 3 3>;
+                gpios = <&gpk2 0 2 0 3>,
+                        <&gpk2 1 2 0 3>,
+                        <&gpk2 3 2 3 3>,
+                        <&gpk2 4 2 3 3>,
+                        <&gpk2 5 2 3 3>,
+                        <&gpk2 6 2 3 3>;
+        };
+        keypad@100A0000 {
+                samsung,keypad-num-rows = <2>;
+                samsung,keypad-num-columns = <8>;
+                linux,keypad-no-autorepeat;
+                linux,keypad-wakeup;
+                row-gpios = <&gpx2 0 3 3 0>,
+                            <&gpx2 1 3 3 0>;
+                col-gpios = <&gpx1 0 3 0 0>,
+                            <&gpx1 1 3 0 0>,
+                            <&gpx1 2 3 0 0>,
+                            <&gpx1 3 3 0 0>,
+                            <&gpx1 4 3 0 0>,
+                            <&gpx1 5 3 0 0>,
+                            <&gpx1 6 3 0 0>,
+                            <&gpx1 7 3 0 0>;
+                key_1 {
+                        keypad,row = <0>;
+                        keypad,column = <3>;
+                        linux,code = <2>;
+                };
+                key_2 {
+                        keypad,row = <0>;
+                        keypad,column = <4>;
+                        linux,code = <3>;
+                };
+                key_3 {
+                        keypad,row = <0>;
+                        keypad,column = <5>;
+                        linux,code = <4>;
+                };
+                key_4 {
+                        keypad,row = <0>;
+                        keypad,column = <6>;
+                        linux,code = <5>;
+                };
+                key_5 {
+                        keypad,row = <0>;
+                        keypad,column = <7>;
+                        linux,code = <6>;
+                };
+                key_a {
+                        keypad,row = <1>;
+                        keypad,column = <3>;
+                        linux,code = <30>;
+                };
+                key_b {
+                        keypad,row = <1>;
+                        keypad,column = <4>;
+                        linux,code = <48>;
+                };
+                key_c {
+                        keypad,row = <1>;
+                        keypad,column = <5>;
+                        linux,code = <46>;
+                };
+                key_d {
+                        keypad,row = <1>;
+                        keypad,column = <6>;
+                        linux,code = <32>;
+                };
+                key_e {
+                        keypad,row = <1>;
+                        keypad,column = <7>;
+                        linux,code = <18>;
+                };
+        };
+        i2c@13860000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-max-bus-freq = <20000>;
+                gpios = <&gpd1 0 2 3 0>,
+                        <&gpd1 1 2 3 0>;
+                eeprom@50 {
+                        compatible = "samsung,24ad0xd1";
+                        reg = <0x50>;
+                };
+                eeprom@52 {
+                        compatible = "samsung,24ad0xd1";
+                        reg = <0x52>;
+                };
+        };
+        sdhci@12510000 {
+                status = "disabled";
+        };
+        sdhci@12520000 {
+                status = "disabled";
+        };
+        sdhci@12540000 {
+                status = "disabled";
+        };
+        i2c@13870000 {
+                status = "disabled";
+        };
+        i2c@13880000 {
+                status = "disabled";
+        };
+        i2c@13890000 {
+                status = "disabled";
+        };
+        i2c@138A0000 {
+                status = "disabled";
+        };
+        i2c@138B0000 {
+                status = "disabled";
+        };
+        i2c@138C0000 {
+                status = "disabled";
+        };
+        i2c@138D0000 {
+                status = "disabled";
+        };
+};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
new file mode 100644
index 00000000000..63d7578856c
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -0,0 +1,397 @@
+/*
+ * Samsung's Exynos4210 SoC device tree source
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "samsung,exynos4210";
+        interrupt-parent = <&gic>;
+        gic:interrupt-controller@10490000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x10490000 0x1000>, <0x10480000 0x100>;
+        };
+        watchdog@10060000 {
+                compatible = "samsung,s3c2410-wdt";
+                reg = <0x10060000 0x100>;
+                interrupts = <0 43 0>;
+        };
+        rtc@10070000 {
+                compatible = "samsung,s3c6410-rtc";
+                reg = <0x10070000 0x100>;
+                interrupts = <0 44 0>, <0 45 0>;
+        };
+        keypad@100A0000 {
+                compatible = "samsung,s5pv210-keypad";
+                reg = <0x100A0000 0x100>;
+                interrupts = <0 109 0>;
+        };
+        sdhci@12510000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12510000 0x100>;
+                interrupts = <0 73 0>;
+        };
+        sdhci@12520000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12520000 0x100>;
+                interrupts = <0 74 0>;
+        };
+        sdhci@12530000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12530000 0x100>;
+                interrupts = <0 75 0>;
+        };
+        sdhci@12540000 {
+                compatible = "samsung,exynos4210-sdhci";
+                reg = <0x12540000 0x100>;
+                interrupts = <0 76 0>;
+        };
+        serial@13800000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13800000 0x100>;
+                interrupts = <0 52 0>;
+        };
+        serial@13810000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13810000 0x100>;
+                interrupts = <0 53 0>;
+        };
+        serial@13820000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13820000 0x100>;
+                interrupts = <0 54 0>;
+        };
+        serial@13830000 {
+                compatible = "samsung,exynos4210-uart";
+                reg = <0x13830000 0x100>;
+                interrupts = <0 55 0>;
+        };
+        i2c@13860000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13860000 0x100>;
+                interrupts = <0 58 0>;
+        };
+        i2c@13870000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13870000 0x100>;
+                interrupts = <0 59 0>;
+        };
+        i2c@13880000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13880000 0x100>;
+                interrupts = <0 60 0>;
+        };
+        i2c@13890000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x13890000 0x100>;
+                interrupts = <0 61 0>;
+        };
+        i2c@138A0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138A0000 0x100>;
+                interrupts = <0 62 0>;
+        };
+        i2c@138B0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138B0000 0x100>;
+                interrupts = <0 63 0>;
+        };
+        i2c@138C0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138C0000 0x100>;
+                interrupts = <0 64 0>;
+        };
+        i2c@138D0000 {
+                compatible = "samsung,s3c2440-i2c";
+                reg = <0x138D0000 0x100>;
+                interrupts = <0 65 0>;
+        };
+        amba {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "arm,amba-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+                pdma0: pdma@12680000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x12680000 0x1000>;
+                        interrupts = <0 35 0>;
+                };
+                pdma1: pdma@12690000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x12690000 0x1000>;
+                        interrupts = <0 36 0>;
+                };
+        };
+        gpio-controllers {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                gpio-controller;
+                ranges;
+                gpa0: gpio-controller@11400000 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400000 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpa1: gpio-controller@11400020 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400020 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpb: gpio-controller@11400040 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400040 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpc0: gpio-controller@11400060 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400060 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpc1: gpio-controller@11400080 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400080 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpd0: gpio-controller@114000A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114000A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpd1: gpio-controller@114000C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114000C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpe0: gpio-controller@114000E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114000E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpe1: gpio-controller@11400100 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400100 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpe2: gpio-controller@11400120 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400120 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpe3: gpio-controller@11400140 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400140 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpe4: gpio-controller@11400160 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400160 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpf0: gpio-controller@11400180 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11400180 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpf1: gpio-controller@114001A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114001A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpf2: gpio-controller@114001C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114001C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpf3: gpio-controller@114001E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x114001E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpj0: gpio-controller@11000000 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000000 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpj1: gpio-controller@11000020 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000020 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpk0: gpio-controller@11000040 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000040 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpk1: gpio-controller@11000060 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000060 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpk2: gpio-controller@11000080 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000080 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpk3: gpio-controller@110000A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110000A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpl0: gpio-controller@110000C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110000C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpl1: gpio-controller@110000E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110000E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpl2: gpio-controller@11000100 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000100 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpy0: gpio-controller@11000120 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000120 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpy1: gpio-controller@11000140 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000140 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpy2: gpio-controller@11000160 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000160 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpy3: gpio-controller@11000180 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000180 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpy4: gpio-controller@110001A0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110001A0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpy5: gpio-controller@110001C0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110001C0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpy6: gpio-controller@110001E0 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x110001E0 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpx0: gpio-controller@11000C00 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000C00 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpx1: gpio-controller@11000C20 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000C20 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpx2: gpio-controller@11000C40 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000C40 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpx3: gpio-controller@11000C60 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x11000C60 0x20>;
+                        #gpio-cells = <4>;
+                };
+                gpz: gpio-controller@03860000 {
+                        compatible = "samsung,exynos4-gpio";
+                        reg = <0x03860000 0x20>;
+                        #gpio-cells = <4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index aeb1a7578fa..305635bd45c 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -194,5 +194,17 @@
                        reg = <0xfff3d000 0x1000>;
                        interrupts = <0 92 4>;
                };
+                ethernet@fff50000 {
+                        compatible = "calxeda,hb-xgmac";
+                        reg = <0xfff50000 0x1000>;
+                        interrupts = <0 77 4  0 78 4  0 79 4>;
+                };
+                ethernet@fff51000 {
+                        compatible = "calxeda,hb-xgmac";
+                        reg = <0xfff51000 0x1000>;
+                        interrupts = <0 80 4  0 81 4  0 82 4>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index f8766af1121..564cb8c19f1 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -35,20 +35,19 @@
                                };
                                esdhc@70008000 { /* ESDHC2 */
-                                        cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
+                                        cd-gpios = <&gpio1 6 0>;
-                                        wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
+                                        wp-gpios = <&gpio1 5 0>;
                                        status = "okay";
                                };
-                                uart2: uart@7000c000 { /* UART3 */
+                                uart3: uart@7000c000 {
                                        fsl,uart-has-rtscts;
                                        status = "okay";
                                };
                                ecspi@70010000 { /* ECSPI1 */
                                        fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
+                                        cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
-                                                   <&gpio3 25 0>; /* GPIO4_25 */
                                        status = "okay";
                                        pmic: mc13892@0 {
@@ -57,7 +56,7 @@
                                                compatible = "fsl,mc13892";
                                                spi-max-frequency = <6000000>;
                                                reg = <0>;
-                                                mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
+                                                mc13xxx-irq-gpios = <&gpio1 8 0>;
                                                fsl,mc13xxx-uses-regulator;
                                        };
@@ -91,12 +90,12 @@
                                reg = <0x73fa8000 0x4000>;
                        };
-                        uart0: uart@73fbc000 {
+                        uart1: uart@73fbc000 {
                                fsl,uart-has-rtscts;
                                status = "okay";
                        };
-                        uart1: uart@73fc0000 {
+                        uart2: uart@73fc0000 {
                                status = "okay";
                        };
                };
@@ -127,7 +126,7 @@
                power {
                        label = "Power Button";
-                        gpios = <&gpio1 21 0>;
+                        gpios = <&gpio2 21 0>;
                        linux,code = <116>; /* KEY_POWER */
                        gpio-key,wakeup;
                };
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 327ab8e3a4c..6663986fe1c 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -14,9 +14,9 @@
 / {
        aliases {
-                serial0 = &uart0;
+                serial0 = &uart1;
-                serial1 = &uart1;
+                serial1 = &uart2;
-                serial2 = &uart2;
+                serial2 = &uart3;
        };
        tzic: tz-interrupt-controller@e0000000 {
@@ -86,7 +86,7 @@
                                        status = "disabled";
                                };
-                                uart2: uart@7000c000 { /* UART3 */
+                                uart3: uart@7000c000 {
                                        compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                        reg = <0x7000c000 0x4000>;
                                        interrupts = <33>;
@@ -117,7 +117,7 @@
                                };
                        };
-                        gpio0: gpio@73f84000 { /* GPIO1 */
+                        gpio1: gpio@73f84000 {
                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                reg = <0x73f84000 0x4000>;
                                interrupts = <50 51>;
@@ -127,7 +127,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio1: gpio@73f88000 { /* GPIO2 */
+                        gpio2: gpio@73f88000 {
                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                reg = <0x73f88000 0x4000>;
                                interrupts = <52 53>;
@@ -137,7 +137,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio2: gpio@73f8c000 { /* GPIO3 */
+                        gpio3: gpio@73f8c000 {
                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                reg = <0x73f8c000 0x4000>;
                                interrupts = <54 55>;
@@ -147,7 +147,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio3: gpio@73f90000 { /* GPIO4 */
+                        gpio4: gpio@73f90000 {
                                compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
                                reg = <0x73f90000 0x4000>;
                                interrupts = <56 57>;
@@ -171,14 +171,14 @@
                                status = "disabled";
                        };
-                        uart0: uart@73fbc000 {
+                        uart1: uart@73fbc000 {
                                compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                reg = <0x73fbc000 0x4000>;
                                interrupts = <31>;
                                status = "disabled";
                        };
-                        uart1: uart@73fc0000 {
+                        uart2: uart@73fc0000 {
                                compatible = "fsl,imx51-uart", "fsl,imx21-uart";
                                reg = <0x73fc0000 0x4000>;
                                interrupts = <32>;
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 2ab7f80a0a3..2dccce46ed8 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -29,8 +29,8 @@
                aips@50000000 { /* AIPS1 */
                        spba@50000000 {
                                esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */
+                                        cd-gpios = <&gpio1 1 0>;
-                                        wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */
+                                        wp-gpios = <&gpio1 9 0>;
                                        status = "okay";
                                };
                        };
@@ -44,7 +44,7 @@
                                reg = <0x53fa8000 0x4000>;
                        };
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                status = "okay";
                        };
                };
@@ -67,7 +67,7 @@
                        compatible = "smsc,lan9220", "smsc,lan9115";
                        reg = <0xf4000000 0x2000000>;
                        phy-mode = "mii";
-                        interrupt-parent = <&gpio1>;
+                        interrupt-parent = <&gpio2>;
                        interrupts = <31>;
                        reg-io-width = <4>;
                        smsc,irq-push-pull;
@@ -79,34 +79,34 @@
                home {
                        label = "Home";
-                        gpios = <&gpio4 10 0>; /* GPIO5_10 */
+                        gpios = <&gpio5 10 0>;
                        linux,code = <102>; /* KEY_HOME */
                        gpio-key,wakeup;
                };
                back {
                        label = "Back";
-                        gpios = <&gpio4 11 0>; /* GPIO5_11 */
+                        gpios = <&gpio5 11 0>;
                        linux,code = <158>; /* KEY_BACK */
                        gpio-key,wakeup;
                };
                program {
                        label = "Program";
-                        gpios = <&gpio4 12 0>; /* GPIO5_12 */
+                        gpios = <&gpio5 12 0>;
                        linux,code = <362>; /* KEY_PROGRAM */
                        gpio-key,wakeup;
                };
                volume-up {
                        label = "Volume Up";
-                        gpios = <&gpio4 13 0>; /* GPIO5_13 */
+                        gpios = <&gpio5 13 0>;
                        linux,code = <115>; /* KEY_VOLUMEUP */
                };
                volume-down {
                        label = "Volume Down";
-                        gpios = <&gpio3 0 0>; /* GPIO4_0 */
+                        gpios = <&gpio4 0 0>;
                        linux,code = <114>; /* KEY_VOLUMEDOWN */
                };
        };
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
index 3f3a88185ff..5bac4aa4800 100644
--- a/arch/arm/boot/dts/imx53-evk.dts
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -29,15 +29,14 @@
                aips@50000000 { /* AIPS1 */
                        spba@50000000 {
                                esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
+                                        cd-gpios = <&gpio3 13 0>;
-                                        wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */
+                                        wp-gpios = <&gpio3 14 0>;
                                        status = "okay";
                                };
                                ecspi@50010000 { /* ECSPI1 */
                                        fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
+                                        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
-                                                   <&gpio2 19 0>; /* GPIO3_19 */
                                        status = "okay";
                                        flash: at45db321d@1 {
@@ -61,8 +60,8 @@
                                };
                                esdhc@50020000 { /* ESDHC3 */
-                                        cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
+                                        cd-gpios = <&gpio3 11 0>;
-                                        wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
+                                        wp-gpios = <&gpio3 12 0>;
                                        status = "okay";
                                };
                        };
@@ -76,7 +75,7 @@
                                reg = <0x53fa8000 0x4000>;
                        };
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                status = "okay";
                        };
                };
@@ -102,7 +101,7 @@
                        fec@63fec000 {
                                phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                phy-reset-gpios = <&gpio7 6 0>;
                                status = "okay";
                        };
                };
@@ -113,7 +112,7 @@
                green {
                        label = "Heartbeat";
-                        gpios = <&gpio6 7 0>; /* GPIO7_7 */
+                        gpios = <&gpio7 7 0>;
                        linux,default-trigger = "heartbeat";
                };
        };
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index ae6de6d0c3f..5c57c8672c3 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -29,13 +29,13 @@
                aips@50000000 { /* AIPS1 */
                        spba@50000000 {
                                esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
+                                        cd-gpios = <&gpio3 13 0>;
                                        status = "okay";
                                };
                                esdhc@50020000 { /* ESDHC3 */
-                                        cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
+                                        cd-gpios = <&gpio3 11 0>;
-                                        wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
+                                        wp-gpios = <&gpio3 12 0>;
                                        status = "okay";
                                };
                        };
@@ -49,7 +49,7 @@
                                reg = <0x53fa8000 0x4000>;
                        };
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                status = "okay";
                        };
                };
@@ -84,7 +84,7 @@
                        fec@63fec000 {
                                phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                phy-reset-gpios = <&gpio7 6 0>;
                                status = "okay";
                        };
                };
@@ -95,20 +95,20 @@
                power {
                        label = "Power Button";
-                        gpios = <&gpio0 8 0>; /* GPIO1_8 */
+                        gpios = <&gpio1 8 0>;
                        linux,code = <116>; /* KEY_POWER */
                        gpio-key,wakeup;
                };
                volume-up {
                        label = "Volume Up";
-                        gpios = <&gpio1 14 0>; /* GPIO2_14 */
+                        gpios = <&gpio2 14 0>;
                        linux,code = <115>; /* KEY_VOLUMEUP */
                };
                volume-down {
                        label = "Volume Down";
-                        gpios = <&gpio1 15 0>; /* GPIO2_15 */
+                        gpios = <&gpio2 15 0>;
                        linux,code = <114>; /* KEY_VOLUMEDOWN */
                };
        };
@@ -118,7 +118,7 @@
                user {
                        label = "Heartbeat";
-                        gpios = <&gpio6 7 0>; /* GPIO7_7 */
+                        gpios = <&gpio7 7 0>;
                        linux,default-trigger = "heartbeat";
                };
        };
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index b1c062eea71..c7ee86c2dfb 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -29,8 +29,8 @@
                aips@50000000 { /* AIPS1 */
                        spba@50000000 {
                                esdhc@50004000 { /* ESDHC1 */
-                                        cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
+                                        cd-gpios = <&gpio3 13 0>;
-                                        wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */
+                                        wp-gpios = <&gpio4 11 0>;
                                        status = "okay";
                                };
@@ -39,15 +39,14 @@
                                        status = "okay";
                                };
-                                uart2: uart@5000c000 { /* UART3 */
+                                uart3: uart@5000c000 {
                                        fsl,uart-has-rtscts;
                                        status = "okay";
                                };
                                ecspi@50010000 { /* ECSPI1 */
                                        fsl,spi-num-chipselects = <2>;
-                                        cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
+                                        cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
-                                                   <&gpio2 19 0>; /* GPIO3_19 */
                                        status = "okay";
                                        zigbee: mc1323@0 {
@@ -91,11 +90,11 @@
                                reg = <0x53fa8000 0x4000>;
                        };
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                status = "okay";
                        };
-                        uart1: uart@53fc0000 { /* UART2 */
+                        uart2: uart@53fc0000 {
                                status = "okay";
                        };
                };
@@ -145,7 +144,7 @@
                        fec@63fec000 {
                                phy-mode = "rmii";
-                                phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
+                                phy-reset-gpios = <&gpio7 6 0>;
                                status = "okay";
                        };
                };
@@ -156,13 +155,13 @@
                volume-up {
                        label = "Volume Up";
-                        gpios = <&gpio1 14 0>; /* GPIO2_14 */
+                        gpios = <&gpio2 14 0>;
                        linux,code = <115>; /* KEY_VOLUMEUP */
                };
                volume-down {
                        label = "Volume Down";
-                        gpios = <&gpio1 15 0>; /* GPIO2_15 */
+                        gpios = <&gpio2 15 0>;
                        linux,code = <114>; /* KEY_VOLUMEDOWN */
                };
        };
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 099cd84ee37..5dd91b942c9 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -14,11 +14,11 @@
 / {
        aliases {
-                serial0 = &uart0;
+                serial0 = &uart1;
-                serial1 = &uart1;
+                serial1 = &uart2;
-                serial2 = &uart2;
+                serial2 = &uart3;
-                serial3 = &uart3;
+                serial3 = &uart4;
-                serial4 = &uart4;
+                serial4 = &uart5;
        };
        tzic: tz-interrupt-controller@0fffc000 {
@@ -88,7 +88,7 @@
                                        status = "disabled";
                                };
-                                uart2: uart@5000c000 { /* UART3 */
+                                uart3: uart@5000c000 {
                                        compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                        reg = <0x5000c000 0x4000>;
                                        interrupts = <33>;
@@ -119,7 +119,7 @@
                                };
                        };
-                        gpio0: gpio@53f84000 { /* GPIO1 */
+                        gpio1: gpio@53f84000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                reg = <0x53f84000 0x4000>;
                                interrupts = <50 51>;
@@ -129,7 +129,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio1: gpio@53f88000 { /* GPIO2 */
+                        gpio2: gpio@53f88000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                reg = <0x53f88000 0x4000>;
                                interrupts = <52 53>;
@@ -139,7 +139,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio2: gpio@53f8c000 { /* GPIO3 */
+                        gpio3: gpio@53f8c000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                reg = <0x53f8c000 0x4000>;
                                interrupts = <54 55>;
@@ -149,7 +149,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio3: gpio@53f90000 { /* GPIO4 */
+                        gpio4: gpio@53f90000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                reg = <0x53f90000 0x4000>;
                                interrupts = <56 57>;
@@ -173,21 +173,21 @@
                                status = "disabled";
                        };
-                        uart0: uart@53fbc000 { /* UART1 */
+                        uart1: uart@53fbc000 {
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x53fbc000 0x4000>;
                                interrupts = <31>;
                                status = "disabled";
                        };
-                        uart1: uart@53fc0000 { /* UART2 */
+                        uart2: uart@53fc0000 {
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x53fc0000 0x4000>;
                                interrupts = <32>;
                                status = "disabled";
                        };
-                        gpio4: gpio@53fdc000 { /* GPIO5 */
+                        gpio5: gpio@53fdc000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                reg = <0x53fdc000 0x4000>;
                                interrupts = <103 104>;
@@ -197,7 +197,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio5: gpio@53fe0000 { /* GPIO6 */
+                        gpio6: gpio@53fe0000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                reg = <0x53fe0000 0x4000>;
                                interrupts = <105 106>;
@@ -207,7 +207,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio6: gpio@53fe4000 { /* GPIO7 */
+                        gpio7: gpio@53fe4000 {
                                compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
                                reg = <0x53fe4000 0x4000>;
                                interrupts = <107 108>;
@@ -226,7 +226,7 @@
                                status = "disabled";
                        };
-                        uart3: uart@53ff0000 { /* UART4 */
+                        uart4: uart@53ff0000 {
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x53ff0000 0x4000>;
                                interrupts = <13>;
@@ -241,7 +241,7 @@
                        reg = <0x60000000 0x10000000>;
                        ranges;
-                        uart4: uart@63f90000 { /* UART5 */
+                        uart5: uart@63f90000 {
                                compatible = "fsl,imx53-uart", "fsl,imx21-uart";
                                reg = <0x63f90000 0x4000>;
                                interrupts = <86>;
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
new file mode 100644
index 00000000000..c3977e0478b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx6q.dtsi"
+/ {
+        model = "Freescale i.MX6 Quad Armadillo2 Board";
+        compatible = "fsl,imx6q-arm2", "fsl,imx6q";
+        chosen {
+                bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
+        };
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+        soc {
+                aips-bus@02100000 { /* AIPS2 */
+                        enet@02188000 {
+                                phy-mode = "rgmii";
+                                local-mac-address = [00 04 9F 01 1B 61];
+                                status = "okay";
+                        };
+                        usdhc@02198000 { /* uSDHC3 */
+                                cd-gpios = <&gpio6 11 0>;
+                                wp-gpios = <&gpio6 14 0>;
+                                status = "okay";
+                        };
+                        usdhc@0219c000 { /* uSDHC4 */
+                                fsl,card-wired;
+                                status = "okay";
+                        };
+                        uart4: uart@021f0000 {
+                                status = "okay";
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                debug-led {
+                        label = "Heartbeat";
+                        gpios = <&gpio3 25 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
deleted file mode 100644
index 072974e443f..00000000000
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-/dts-v1/;
-/include/ "imx6q.dtsi"
-/ {
-        model = "Freescale i.MX6 Quad SABRE Automotive Board";
-        compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
-        chosen {
-                bootargs = "console=ttymxc0,115200 root=/dev/mmcblk3p3 rootwait";
-        };
-        memory {
-                reg = <0x10000000 0x80000000>;
-        };
-        soc {
-                aips-bus@02100000 { /* AIPS2 */
-                        enet@02188000 {
-                                phy-mode = "rgmii";
-                                local-mac-address = [00 04 9F 01 1B 61];
-                                status = "okay";
-                        };
-                        usdhc@02198000 { /* uSDHC3 */
-                                cd-gpios = <&gpio5 11 0>; /* GPIO6_11 */
-                                wp-gpios = <&gpio5 14 0>; /* GPIO6_14 */
-                                status = "okay";
-                        };
-                        usdhc@0219c000 { /* uSDHC4 */
-                                fsl,card-wired;
-                                status = "okay";
-                        };
-                        uart3: uart@021f0000 { /* UART4 */
-                                status = "okay";
-                        };
-                };
-        };
-        leds {
-                compatible = "gpio-leds";
-                debug-led {
-                        label = "Heartbeat";
-                        gpios = <&gpio2 25 0>; /* GPIO3_25 */
-                        linux,default-trigger = "heartbeat";
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
new file mode 100644
index 00000000000..08d920de728
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "imx6q.dtsi"
+/ {
+        model = "Freescale i.MX6 Quad SABRE Lite Board";
+        compatible = "fsl,imx6q-sabrelite", "fsl,imx6q";
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+        soc {
+                aips-bus@02100000 { /* AIPS2 */
+                        enet@02188000 {
+                                phy-mode = "rgmii";
+                                phy-reset-gpios = <&gpio3 23 0>;
+                                status = "okay";
+                        };
+                        usdhc@02198000 { /* uSDHC3 */
+                                cd-gpios = <&gpio7 0 0>;
+                                wp-gpios = <&gpio7 1 0>;
+                                status = "okay";
+                        };
+                        usdhc@0219c000 { /* uSDHC4 */
+                                cd-gpios = <&gpio2 6 0>;
+                                wp-gpios = <&gpio2 7 0>;
+                                status = "okay";
+                        };
+                        uart2: uart@021e8000 {
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 7dda599558c..263e8f3664b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -14,11 +14,11 @@
 / {
        aliases {
-                serial0 = &uart0;
+                serial0 = &uart1;
-                serial1 = &uart1;
+                serial1 = &uart2;
-                serial2 = &uart2;
+                serial2 = &uart3;
-                serial3 = &uart3;
+                serial3 = &uart4;
-                serial4 = &uart4;
+                serial4 = &uart5;
        };
        cpus {
@@ -165,7 +165,7 @@
                                        status = "disabled";
                                };
-                                uart0: uart@02020000 { /* UART1 */
+                                uart1: uart@02020000 {
                                        compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                        reg = <0x02020000 0x4000>;
                                        interrupts = <0 26 0x04>;
@@ -247,7 +247,7 @@
                                interrupts = <0 55 0x04>;
                        };
-                        gpio0: gpio@0209c000 { /* GPIO1 */
+                        gpio1: gpio@0209c000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                reg = <0x0209c000 0x4000>;
                                interrupts = <0 66 0x04 0 67 0x04>;
@@ -257,7 +257,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio1: gpio@020a0000 { /* GPIO2 */
+                        gpio2: gpio@020a0000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                reg = <0x020a0000 0x4000>;
                                interrupts = <0 68 0x04 0 69 0x04>;
@@ -267,7 +267,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio2: gpio@020a4000 { /* GPIO3 */
+                        gpio3: gpio@020a4000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                reg = <0x020a4000 0x4000>;
                                interrupts = <0 70 0x04 0 71 0x04>;
@@ -277,7 +277,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio3: gpio@020a8000 { /* GPIO4 */
+                        gpio4: gpio@020a8000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                reg = <0x020a8000 0x4000>;
                                interrupts = <0 72 0x04 0 73 0x04>;
@@ -287,7 +287,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio4: gpio@020ac000 { /* GPIO5 */
+                        gpio5: gpio@020ac000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                reg = <0x020ac000 0x4000>;
                                interrupts = <0 74 0x04 0 75 0x04>;
@@ -297,7 +297,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio5: gpio@020b0000 { /* GPIO6 */
+                        gpio6: gpio@020b0000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                reg = <0x020b0000 0x4000>;
                                interrupts = <0 76 0x04 0 77 0x04>;
@@ -307,7 +307,7 @@
                                #interrupt-cells = <1>;
                        };
-                        gpio6: gpio@020b4000 { /* GPIO7 */
+                        gpio7: gpio@020b4000 {
                                compatible = "fsl,imx6q-gpio", "fsl,imx31-gpio";
                                reg = <0x020b4000 0x4000>;
                                interrupts = <0 78 0x04 0 79 0x04>;
@@ -543,28 +543,28 @@
                                interrupts = <0 18 0x04>;
                        };
-                        uart1: uart@021e8000 { /* UART2 */
+                        uart2: uart@021e8000 {
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021e8000 0x4000>;
                                interrupts = <0 27 0x04>;
                                status = "disabled";
                        };
-                        uart2: uart@021ec000 { /* UART3 */
+                        uart3: uart@021ec000 {
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021ec000 0x4000>;
                                interrupts = <0 28 0x04>;
                                status = "disabled";
                        };
-                        uart3: uart@021f0000 { /* UART4 */
+                        uart4: uart@021f0000 {
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021f0000 0x4000>;
                                interrupts = <0 29 0x04>;
                                status = "disabled";
                        };
-                        uart4: uart@021f4000 { /* UART5 */
+                        uart5: uart@021f4000 {
                                compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
                                reg = <0x021f4000 0x4000>;
                                interrupts = <0 30 0x04>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
new file mode 100644
index 00000000000..f2ab4ea7cc0
--- /dev/null
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Device Tree Source for OMAP2 SoC
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+        };
+        cpus {
+                cpu@0 {
+                        compatible = "arm,arm1136jf-s";
+                };
+        };
+        soc {
+                compatible = "ti,omap-infra";
+                mpu {
+                        compatible = "ti,omap2-mpu";
+                        ti,hwmods = "mpu";
+                };
+        };
+        ocp {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ti,hwmods = "l3_main";
+                intc: interrupt-controller@1 {
+                        compatible = "ti,omap2-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+                uart1: serial@4806a000 {
+                        compatible = "ti,omap2-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+                uart2: serial@4806c000 {
+                        compatible = "ti,omap2-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+                uart3: serial@4806e000 {
+                        compatible = "ti,omap2-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index d202bb5ec7e..216c3317461 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -13,6 +13,13 @@
 / {
        compatible = "ti,omap3430", "ti,omap3";
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+        };
        cpus {
                cpu@0 {
                        compatible = "arm,cortex-a8";
@@ -59,5 +66,29 @@
                        interrupt-controller;
                        #interrupt-cells = <1>;
                };
+                uart1: serial@0x4806a000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+                uart2: serial@0x4806c000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+                uart3: serial@0x49020000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+                uart4: serial@0x49042000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 4c61c829043..e8fe75fac7c 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -21,6 +21,10 @@
        interrupt-parent = <&gic>;
        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
        };
        cpus {
@@ -99,5 +103,29 @@
                        reg = <0x48241000 0x1000>,
                              <0x48240100 0x0100>;
                };
+                uart1: serial@0x4806a000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+                uart2: serial@0x4806c000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+                uart3: serial@0x48020000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+                uart4: serial@0x4806e000 {
+                        compatible = "ti,omap4-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra-cardhu.dts
new file mode 100644
index 00000000000..70c41fc897d
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-cardhu.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+/include/ "tegra30.dtsi"
+/ {
+        model = "NVIDIA Tegra30 Cardhu evaluation board";
+        compatible = "nvidia,cardhu", "nvidia,tegra30";
+        memory {
+                reg = < 0x80000000 0x40000000 >;
+        };
+        serial@70006000 {
+                clock-frequency = < 408000000 >;
+        };
+        i2c@7000c000 {
+                clock-frequency = <100000>;
+        };
+        i2c@7000c400 {
+                clock-frequency = <100000>;
+        };
+        i2c@7000c500 {
+                clock-frequency = <100000>;
+        };
+        i2c@7000c700 {
+                clock-frequency = <100000>;
+        };
+        i2c@7000d000 {
+                clock-frequency = <100000>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra-harmony.dts
index 0e225b86b65..80afa1b70b8 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra-harmony.dts
@@ -1,16 +1,11 @@
 /dts-v1/;
-/memreserve/ 0x1c000000 0x04000000;
 /include/ "tegra20.dtsi"
 / {
        model = "NVIDIA Tegra2 Harmony evaluation board";
        compatible = "nvidia,harmony", "nvidia,tegra20";
-        chosen {
-                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootwait";
-        };
        memory@0 {
                reg = < 0x00000000 0x40000000 >;
        };
@@ -52,16 +47,40 @@
                ext-mic-en-gpios = <&gpio 185 0>;
        };
+        serial@70006000 {
+                status = "disable";
+        };
+        serial@70006040 {
+                status = "disable";
+        };
+        serial@70006200 {
+                status = "disable";
+        };
        serial@70006300 {
                clock-frequency = < 216000000 >;
        };
+        serial@70006400 {
+                status = "disable";
+        };
+        sdhci@c8000000 {
+                status = "disable";
+        };
        sdhci@c8000200 {
                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
                power-gpios = <&gpio 155 0>; /* gpio PT3 */
        };
+        sdhci@c8000400 {
+                status = "disable";
+        };
        sdhci@c8000600 {
                cd-gpios = <&gpio 58 0>; /* gpio PH2 */
                wp-gpios = <&gpio 59 0>; /* gpio PH3 */
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts
new file mode 100644
index 00000000000..1a1d7023b69
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-paz00.dts
@@ -0,0 +1,77 @@
+/dts-v1/;
+/include/ "tegra20.dtsi"
+/ {
+        model = "Toshiba AC100 / Dynabook AZ";
+        compatible = "compal,paz00", "nvidia,tegra20";
+        memory@0 {
+                reg = <0x00000000 0x20000000>;
+        };
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000c500 {
+                status = "disable";
+        };
+        nvec@7000c500 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,nvec";
+                reg = <0x7000C500 0x100>;
+                interrupts = <0 92 0x04>;
+                clock-frequency = <80000>;
+                request-gpios = <&gpio 170 0>;
+                slave-addr = <138>;
+        };
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+        };
+        serial@70006000 {
+                clock-frequency = <216000000>;
+        };
+        serial@70006040 {
+                status = "disable";
+        };
+        serial@70006200 {
+                status = "disable";
+        };
+        serial@70006300 {
+                clock-frequency = <216000000>;
+        };
+        serial@70006400 {
+                status = "disable";
+        };
+        sdhci@c8000000 {
+                cd-gpios = <&gpio 173 0>; /* gpio PV5 */
+                wp-gpios = <&gpio 57 0>;  /* gpio PH1 */
+                power-gpios = <&gpio 155 0>; /* gpio PT3 */
+        };
+        sdhci@c8000200 {
+                status = "disable";
+        };
+        sdhci@c8000400 {
+                status = "disable";
+        };
+        sdhci@c8000600 {
+                support-8bit;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra-seaboard.dts
index a72299b8e66..b55a02e34ba 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra-seaboard.dts
@@ -1,25 +1,65 @@
 /dts-v1/;
-/memreserve/ 0x1c000000 0x04000000;
 /include/ "tegra20.dtsi"
 / {
        model = "NVIDIA Seaboard";
        compatible = "nvidia,seaboard", "nvidia,tegra20";
-        chosen {
-                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
-        };
        memory {
                device_type = "memory";
                reg = < 0x00000000 0x40000000 >;
        };
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+                adt7461@4c {
+                        compatible = "adt7461";
+                        reg = <0x4c>;
+                };
+        };
+        serial@70006000 {
+                status = "disable";
+        };
+        serial@70006040 {
+                status = "disable";
+        };
+        serial@70006200 {
+                status = "disable";
+        };
        serial@70006300 {
                clock-frequency = < 216000000 >;
        };
+        serial@70006400 {
+                status = "disable";
+        };
+        sdhci@c8000000 {
+                status = "disable";
+        };
+        sdhci@c8000200 {
+                status = "disable";
+        };
        sdhci@c8000400 {
                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
@@ -29,4 +69,28 @@
        sdhci@c8000600 {
                support-8bit;
        };
+        usb@c5000000 {
+                nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                power {
+                        label = "Power";
+                        gpios = <&gpio 170 1>; /* gpio PV2, active low */
+                        linux,code = <116>; /* KEY_POWER */
+                        gpio-key,wakeup;
+                };
+                lid {
+                        label = "Lid";
+                        gpios = <&gpio 23 0>; /* gpio PC7 */
+                        linux,input-type = <5>; /* EV_SW */
+                        linux,code = <0>; /* SW_LID */
+                        debounce-interval = <1>;
+                        gpio-key,wakeup;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra-trimslice.dts
new file mode 100644
index 00000000000..3b3ee7db99f
--- /dev/null
+++ b/arch/arm/boot/dts/tegra-trimslice.dts
@@ -0,0 +1,65 @@
+/dts-v1/;
+/include/ "tegra20.dtsi"
+/ {
+        model = "Compulab TrimSlice board";
+        compatible = "compulab,trimslice", "nvidia,tegra20";
+        memory@0 {
+                reg = < 0x00000000 0x40000000 >;
+        };
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000d000 {
+                status = "disable";
+        };
+        serial@70006000 {
+                clock-frequency = < 216000000 >;
+        };
+        serial@70006040 {
+                status = "disable";
+        };
+        serial@70006200 {
+                status = "disable";
+        };
+        serial@70006300 {
+                status = "disable";
+        };
+        serial@70006400 {
+                status = "disable";
+        };
+        sdhci@c8000000 {
+                status = "disable";
+        };
+        sdhci@c8000200 {
+                status = "disable";
+        };
+        sdhci@c8000400 {
+                status = "disable";
+        };
+        sdhci@c8000600 {
+                cd-gpios = <&gpio 121 0>;
+                wp-gpios = <&gpio 122 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra-ventana.dts
index 3f9abd6b696..c7d3b87f29d 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra-ventana.dts
@@ -1,24 +1,59 @@
 /dts-v1/;
-/memreserve/ 0x1c000000 0x04000000;
 /include/ "tegra20.dtsi"
 / {
        model = "NVIDIA Tegra2 Ventana evaluation board";
        compatible = "nvidia,ventana", "nvidia,tegra20";
-        chosen {
-                bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/ram rdinit=/sbin/init";
-        };
        memory {
                reg = < 0x00000000 0x40000000 >;
        };
+        i2c@7000c000 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000c400 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000c500 {
+                clock-frequency = <400000>;
+        };
+        i2c@7000d000 {
+                clock-frequency = <400000>;
+        };
+        serial@70006000 {
+                status = "disable";
+        };
+        serial@70006040 {
+                status = "disable";
+        };
+        serial@70006200 {
+                status = "disable";
+        };
        serial@70006300 {
                clock-frequency = < 216000000 >;
        };
+        serial@70006400 {
+                status = "disable";
+        };
+        sdhci@c8000000 {
+                status = "disable";
+        };
+        sdhci@c8000200 {
+                status = "disable";
+        };
        sdhci@c8000400 {
                cd-gpios = <&gpio 69 0>; /* gpio PI5 */
                wp-gpios = <&gpio 57 0>; /* gpio PH1 */
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 65d7e6a333e..3da7afd4532 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -5,9 +5,9 @@
        interrupt-parent = <&intc>;
        intc: interrupt-controller@50041000 {
-                compatible = "nvidia,tegra20-gic";
+                compatible = "arm,cortex-a9-gic";
                interrupt-controller;
-                #interrupt-cells = <1>;
+                #interrupt-cells = <3>;
                reg = < 0x50041000 0x1000 >,
                      < 0x50040100 0x0100 >;
        };
@@ -17,7 +17,7 @@
                #size-cells = <0>;
                compatible = "nvidia,tegra20-i2c";
                reg = <0x7000C000 0x100>;
-                interrupts = < 70 >;
+                interrupts = < 0 38 0x04 >;
        };
        i2c@7000c400 {
@@ -25,7 +25,7 @@
                #size-cells = <0>;
                compatible = "nvidia,tegra20-i2c";
                reg = <0x7000C400 0x100>;
-                interrupts = < 116 >;
+                interrupts = < 0 84 0x04 >;
        };
        i2c@7000c500 {
@@ -33,38 +33,32 @@
                #size-cells = <0>;
                compatible = "nvidia,tegra20-i2c";
                reg = <0x7000C500 0x100>;
-                interrupts = < 124 >;
+                interrupts = < 0 92 0x04 >;
        };
        i2c@7000d000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "nvidia,tegra20-i2c";
+                compatible = "nvidia,tegra20-i2c-dvc";
                reg = <0x7000D000 0x200>;
-                interrupts = < 85 >;
+                interrupts = < 0 53 0x04 >;
        };
        i2s@70002800 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                compatible = "nvidia,tegra20-i2s";
                reg = <0x70002800 0x200>;
-                interrupts = < 45 >;
+                interrupts = < 0 13 0x04 >;
                dma-channel = < 2 >;
        };
        i2s@70002a00 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                compatible = "nvidia,tegra20-i2s";
                reg = <0x70002a00 0x200>;
-                interrupts = < 35 >;
+                interrupts = < 0 3 0x04 >;
                dma-channel = < 1 >;
        };
        das@70000c00 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                compatible = "nvidia,tegra20-das";
                reg = <0x70000c00 0x80>;
        };
@@ -72,7 +66,13 @@
        gpio: gpio@6000d000 {
                compatible = "nvidia,tegra20-gpio";
                reg = < 0x6000d000 0x1000 >;
-                interrupts = < 64 65 66 67 87 119 121 >;
+                interrupts = < 0 32 0x04
+                               0 33 0x04
+                               0 34 0x04
+                               0 35 0x04
+                               0 55 0x04
+                               0 87 0x04
+                               0 89 0x04 >;
                #gpio-cells = <2>;
                gpio-controller;
        };
@@ -89,59 +89,80 @@
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006000 0x40>;
                reg-shift = <2>;
-                interrupts = < 68 >;
+                interrupts = < 0 36 0x04 >;
        };
        serial@70006040 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006040 0x40>;
                reg-shift = <2>;
-                interrupts = < 69 >;
+                interrupts = < 0 37 0x04 >;
        };
        serial@70006200 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006200 0x100>;
                reg-shift = <2>;
-                interrupts = < 78 >;
+                interrupts = < 0 46 0x04 >;
        };
        serial@70006300 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006300 0x100>;
                reg-shift = <2>;
-                interrupts = < 122 >;
+                interrupts = < 0 90 0x04 >;
        };
        serial@70006400 {
                compatible = "nvidia,tegra20-uart";
                reg = <0x70006400 0x100>;
                reg-shift = <2>;
-                interrupts = < 123 >;
+                interrupts = < 0 91 0x04 >;
        };
        sdhci@c8000000 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000000 0x200>;
-                interrupts = < 46 >;
+                interrupts = < 0 14 0x04 >;
        };
        sdhci@c8000200 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000200 0x200>;
-                interrupts = < 47 >;
+                interrupts = < 0 15 0x04 >;
        };
        sdhci@c8000400 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000400 0x200>;
-                interrupts = < 51 >;
+                interrupts = < 0 19 0x04 >;
        };
        sdhci@c8000600 {
                compatible = "nvidia,tegra20-sdhci";
                reg = <0xc8000600 0x200>;
-                interrupts = < 63 >;
+                interrupts = < 0 31 0x04 >;
+        };
+        usb@c5000000 {
+                compatible = "nvidia,tegra20-ehci", "usb-ehci";
+                reg = <0xc5000000 0x4000>;
+                interrupts = < 0 20 0x04 >;
+                phy_type = "utmi";
+        };
+        usb@c5004000 {
+                compatible = "nvidia,tegra20-ehci", "usb-ehci";
+                reg = <0xc5004000 0x4000>;
+                interrupts = < 0 21 0x04 >;
+                phy_type = "ulpi";
+        };
+        usb@c5008000 {
+                compatible = "nvidia,tegra20-ehci", "usb-ehci";
+                reg = <0xc5008000 0x4000>;
+                interrupts = < 0 97 0x04 >;
+                phy_type = "utmi";
        };
 };
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
new file mode 100644
index 00000000000..ee7db9892e0
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -0,0 +1,127 @@
+/include/ "skeleton.dtsi"
+/ {
+        compatible = "nvidia,tegra30";
+        interrupt-parent = <&intc>;
+        intc: interrupt-controller@50041000 {
+                compatible = "arm,cortex-a9-gic";
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                reg = < 0x50041000 0x1000 >,
+                      < 0x50040100 0x0100 >;
+        };
+        i2c@7000c000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000C000 0x100>;
+                interrupts = < 0 38 0x04 >;
+        };
+        i2c@7000c400 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000C400 0x100>;
+                interrupts = < 0 84 0x04 >;
+        };
+        i2c@7000c500 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000C500 0x100>;
+                interrupts = < 0 92 0x04 >;
+        };
+        i2c@7000c700 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000c700 0x100>;
+                interrupts = < 0 120 0x04 >;
+        };
+        i2c@7000d000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
+                reg = <0x7000D000 0x100>;
+                interrupts = < 0 53 0x04 >;
+        };
+        gpio: gpio@6000d000 {
+                compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
+                reg = < 0x6000d000 0x1000 >;
+                interrupts = < 0 32 0x04 0 33 0x04 0 34 0x04 0 35 0x04 0 55 0x04 0 87 0x04 0 89 0x04 >;
+                #gpio-cells = <2>;
+                gpio-controller;
+        };
+        serial@70006000 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006000 0x40>;
+                reg-shift = <2>;
+                interrupts = < 0 36 0x04 >;
+        };
+        serial@70006040 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006040 0x40>;
+                reg-shift = <2>;
+                interrupts = < 0 37 0x04 >;
+        };
+        serial@70006200 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006200 0x100>;
+                reg-shift = <2>;
+                interrupts = < 0 46 0x04 >;
+        };
+        serial@70006300 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006300 0x100>;
+                reg-shift = <2>;
+                interrupts = < 0 90 0x04 >;
+        };
+        serial@70006400 {
+                compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
+                reg = <0x70006400 0x100>;
+                reg-shift = <2>;
+                interrupts = < 0 91 0x04 >;
+        };
+        sdhci@78000000 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000000 0x200>;
+                interrupts = < 0 14 0x04 >;
+        };
+        sdhci@78000200 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000200 0x200>;
+                interrupts = < 0 15 0x04 >;
+        };
+        sdhci@78000400 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000400 0x200>;
+                interrupts = < 0 19 0x04 >;
+        };
+        sdhci@78000600 {
+                compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
+                reg = <0x78000600 0x200>;
+                interrupts = < 0 31 0x04 >;
+        };
+        pinmux: pinmux@70000000 {
+                compatible = "nvidia,tegra30-pinmux";
+                reg = < 0x70000868 0xd0     /* Pad control registers */
+                        0x70003000 0x3e0 >; /* Mux registers */
+        };
+};
diff --git a/arch/arm/boot/dts/testcases/tests-phandle.dtsi b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
new file mode 100644
index 00000000000..ec0c4e6212c
--- /dev/null
+++ b/arch/arm/boot/dts/testcases/tests-phandle.dtsi
@@ -0,0 +1,37 @@
+/ {
+        testcase-data {
+                phandle-tests {
+                        provider0: provider0 {
+                                #phandle-cells = <0>;
+                        };
+                        provider1: provider1 {
+                                #phandle-cells = <1>;
+                        };
+                        provider2: provider2 {
+                                #phandle-cells = <2>;
+                        };
+                        provider3: provider3 {
+                                #phandle-cells = <3>;
+                        };
+                        consumer-a {
+                                phandle-list =  <&provider1 1>,
+                                                <&provider2 2 0>,
+                                                <0>,
+                                                <&provider3 4 4 3>,
+                                                <&provider2 5 100>,
+                                                <&provider0>,
+                                                <&provider1 7>;
+                                phandle-list-names = "first", "second", "third";
+                                phandle-list-bad-phandle = <12345678 0 0>;
+                                phandle-list-bad-args = <&provider2 1 0>,
+                                                        <&provider3 0>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/testcases/tests.dtsi b/arch/arm/boot/dts/testcases/tests.dtsi
new file mode 100644
index 00000000000..a7c5067622e
--- /dev/null
+++ b/arch/arm/boot/dts/testcases/tests.dtsi
@@ -0,0 +1 @@
+/include/ "tests-phandle.dtsi"
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
index d66e2c00ac3..f04b535477f 100644
--- a/arch/arm/boot/dts/usb_a9g20.dts
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -25,6 +25,11 @@
                        dbgu: serial@fffff200 {
                                status = "okay";
                        };
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index 8a614e39800..166461073b7 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -46,3 +46,5 @@
                };
        };
 };
+/include/ "testcases/tests.dtsi"
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 74df9ca2be3..81a933eb090 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,8 +1,14 @@
 config ARM_GIC
        select IRQ_DOMAIN
+        select MULTI_IRQ_HANDLER
+        bool
+config GIC_NON_BANKED
        bool
 config ARM_VIC
+        select IRQ_DOMAIN
+        select MULTI_IRQ_HANDLER
        bool
 config ARM_VIC_NR
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 410a546060a..b2dc2dd7f1d 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -40,13 +40,36 @@
 #include <linux/slab.h>
 #include <asm/irq.h>
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
-static DEFINE_RAW_SPINLOCK(irq_controller_lock);
+union gic_base {
+        void __iomem *common_base;
+        void __percpu __iomem **percpu_base;
+};
-/* Address of GIC 0 CPU interface */
+struct gic_chip_data {
-void __iomem *gic_cpu_base_addr __read_mostly;
+        unsigned int irq_offset;
+        union gic_base dist_base;
+        union gic_base cpu_base;
+#ifdef CONFIG_CPU_PM
+        u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
+        u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
+        u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
+        u32 __percpu *saved_ppi_enable;
+        u32 __percpu *saved_ppi_conf;
+#endif
+#ifdef CONFIG_IRQ_DOMAIN
+        struct irq_domain domain;
+#endif
+        unsigned int gic_irqs;
+#ifdef CONFIG_GIC_NON_BANKED
+        void __iomem *(*get_base)(union gic_base *);
+#endif
+};
+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 /*
 * Supported arch specific GIC irq extension.
@@ -67,16 +90,48 @@ struct irq_chip gic_arch_extn = {
 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
+#ifdef CONFIG_GIC_NON_BANKED
+static void __iomem *gic_get_percpu_base(union gic_base *base)
+{
+        return *__this_cpu_ptr(base->percpu_base);
+}
+static void __iomem *gic_get_common_base(union gic_base *base)
+{
+        return base->common_base;
+}
+static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
+{
+        return data->get_base(&data->dist_base);
+}
+static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
+{
+        return data->get_base(&data->cpu_base);
+}
+static inline void gic_set_base_accessor(struct gic_chip_data *data,
+                                         void __iomem *(*f)(union gic_base *))
+{
+        data->get_base = f;
+}
+#else
+#define gic_data_dist_base(d)   ((d)->dist_base.common_base)
+#define gic_data_cpu_base(d)    ((d)->cpu_base.common_base)
+#define gic_set_base_accessor(d,f)
+#endif
 static inline void __iomem *gic_dist_base(struct irq_data *d)
 {
        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-        return gic_data->dist_base;
+        return gic_data_dist_base(gic_data);
 }
 static inline void __iomem *gic_cpu_base(struct irq_data *d)
 {
        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-        return gic_data->cpu_base;
+        return gic_data_cpu_base(gic_data);
 }
 static inline unsigned int gic_irq(struct irq_data *d)
@@ -215,6 +270,32 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
 #define gic_set_wake    NULL
 #endif
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+        u32 irqstat, irqnr;
+        struct gic_chip_data *gic = &gic_data[0];
+        void __iomem *cpu_base = gic_data_cpu_base(gic);
+        do {
+                irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
+                irqnr = irqstat & ~0x1c00;
+                if (likely(irqnr > 15 && irqnr < 1021)) {
+                        irqnr = irq_domain_to_irq(&gic->domain, irqnr);
+                        handle_IRQ(irqnr, regs);
+                        continue;
+                }
+                if (irqnr < 16) {
+                        writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+                        handle_IPI(irqnr, regs);
+#endif
+                        continue;
+                }
+                break;
+        } while (1);
+}
 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
        struct gic_chip_data *chip_data = irq_get_handler_data(irq);
@@ -225,7 +306,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
        chained_irq_enter(chip, desc);
        raw_spin_lock(&irq_controller_lock);
-        status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
+        status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
        raw_spin_unlock(&irq_controller_lock);
        gic_irq = (status & 0x3ff);
@@ -270,7 +351,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
        u32 cpumask;
        unsigned int gic_irqs = gic->gic_irqs;
        struct irq_domain *domain = &gic->domain;
-        void __iomem *base = gic->dist_base;
+        void __iomem *base = gic_data_dist_base(gic);
        u32 cpu = 0;
 #ifdef CONFIG_SMP
@@ -330,8 +411,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
 static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
 {
-        void __iomem *dist_base = gic->dist_base;
+        void __iomem *dist_base = gic_data_dist_base(gic);
-        void __iomem *base = gic->cpu_base;
+        void __iomem *base = gic_data_cpu_base(gic);
        int i;
        /*
@@ -368,7 +449,7 @@ static void gic_dist_save(unsigned int gic_nr)
                BUG();
        gic_irqs = gic_data[gic_nr].gic_irqs;
-        dist_base = gic_data[gic_nr].dist_base;
+        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
        if (!dist_base)
                return;
@@ -403,7 +484,7 @@ static void gic_dist_restore(unsigned int gic_nr)
                BUG();
        gic_irqs = gic_data[gic_nr].gic_irqs;
-        dist_base = gic_data[gic_nr].dist_base;
+        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
        if (!dist_base)
                return;
@@ -439,8 +520,8 @@ static void gic_cpu_save(unsigned int gic_nr)
        if (gic_nr >= MAX_GIC_NR)
                BUG();
-        dist_base = gic_data[gic_nr].dist_base;
+        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-        cpu_base = gic_data[gic_nr].cpu_base;
+        cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
        if (!dist_base || !cpu_base)
                return;
@@ -465,8 +546,8 @@ static void gic_cpu_restore(unsigned int gic_nr)
        if (gic_nr >= MAX_GIC_NR)
                BUG();
-        dist_base = gic_data[gic_nr].dist_base;
+        dist_base = gic_data_dist_base(&gic_data[gic_nr]);
-        cpu_base = gic_data[gic_nr].cpu_base;
+        cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
        if (!dist_base || !cpu_base)
                return;
@@ -491,6 +572,11 @@ static int gic_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
        int i;
        for (i = 0; i < MAX_GIC_NR; i++) {
+#ifdef CONFIG_GIC_NON_BANKED
+                /* Skip over unused GICs */
+                if (!gic_data[i].get_base)
+                        continue;
+#endif
                switch (cmd) {
                case CPU_PM_ENTER:
                        gic_cpu_save(i);
@@ -564,8 +650,9 @@ const struct irq_domain_ops gic_irq_domain_ops = {
 #endif
 };
-void __init gic_init(unsigned int gic_nr, int irq_start,
+void __init gic_init_bases(unsigned int gic_nr, int irq_start,
-        void __iomem *dist_base, void __iomem *cpu_base)
+                           void __iomem *dist_base, void __iomem *cpu_base,
+                           u32 percpu_offset)
 {
        struct gic_chip_data *gic;
        struct irq_domain *domain;
@@ -575,8 +662,36 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
        gic = &gic_data[gic_nr];
        domain = &gic->domain;
-        gic->dist_base = dist_base;
+#ifdef CONFIG_GIC_NON_BANKED
-        gic->cpu_base = cpu_base;
+        if (percpu_offset) { /* Frankein-GIC without banked registers... */
+                unsigned int cpu;
+                gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
+                gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
+                if (WARN_ON(!gic->dist_base.percpu_base ||
+                            !gic->cpu_base.percpu_base)) {
+                        free_percpu(gic->dist_base.percpu_base);
+                        free_percpu(gic->cpu_base.percpu_base);
+                        return;
+                }
+                for_each_possible_cpu(cpu) {
+                        unsigned long offset = percpu_offset * cpu_logical_map(cpu);
+                        *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
+                        *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
+                }
+                gic_set_base_accessor(gic, gic_get_percpu_base);
+        } else
+#endif
+        {                       /* Normal, sane GIC... */
+                WARN(percpu_offset,
+                     "GIC_NON_BANKED not enabled, ignoring %08x offset!",
+                     percpu_offset);
+                gic->dist_base.common_base = dist_base;
+                gic->cpu_base.common_base = cpu_base;
+                gic_set_base_accessor(gic, gic_get_common_base);
+        }
        /*
         * For primary GICs, skip over SGIs.
@@ -584,8 +699,6 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
         */
        domain->hwirq_base = 32;
        if (gic_nr == 0) {
-                gic_cpu_base_addr = cpu_base;
                if ((irq_start & 31) > 0) {
                        domain->hwirq_base = 16;
                        if (irq_start != -1)
@@ -597,7 +710,7 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
         * Find out how many interrupts are supported.
         * The GIC only supports up to 1020 interrupt sources.
         */
-        gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
+        gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
        gic_irqs = (gic_irqs + 1) * 32;
        if (gic_irqs > 1020)
                gic_irqs = 1020;
@@ -645,7 +758,7 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
        dsb();
        /* this always happens on GIC0 */
-        writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
+        writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
 }
 #endif
@@ -656,6 +769,7 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
 {
        void __iomem *cpu_base;
        void __iomem *dist_base;
+        u32 percpu_offset;
        int irq;
        struct irq_domain *domain = &gic_data[gic_cnt].domain;
@@ -668,9 +782,12 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
        cpu_base = of_iomap(node, 1);
        WARN(!cpu_base, "unable to map gic cpu registers\n");
+        if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
+                percpu_offset = 0;
        domain->of_node = of_node_get(node);
-        gic_init(gic_cnt, -1, dist_base, cpu_base);
+        gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset);
        if (parent) {
                irq = irq_of_parse_and_map(node, 0);
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index b539ec855e1..d1bcd7b13eb 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -299,8 +299,8 @@ int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
                goto err1;
        }
-        sys->resource[0] = &it8152_io;
+        pci_add_resource(&sys->resources, &it8152_io);
-        sys->resource[1] = &it8152_mem;
+        pci_add_resource(&sys->resources, &it8152_mem);
        if (platform_notify || platform_notify_remove) {
                printk(KERN_ERR "PCI: Can't use platform_notify\n");
@@ -327,6 +327,9 @@ err0:
 */
 unsigned int pcibios_max_latency = 255;
+/* ITE bridge requires setting latency timer to avoid early bus access
+   termination by PCI bus master devices
+*/
 void pcibios_set_master(struct pci_dev *dev)
 {
        u8 lat;
@@ -352,7 +355,7 @@ void pcibios_set_master(struct pci_dev *dev)
 struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
 {
-        return pci_scan_bus(nr, &it8152_ops, sys);
+        return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources);
 }
 EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index 8d8df744f7a..d8e44a43047 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1467,13 +1467,19 @@ int pl330_update(const struct pl330_info *pi)
        /* Now that we are in no hurry, do the callbacks */
        while (!list_empty(&pl330->req_done)) {
+                struct pl330_req *r;
                rqdone = container_of(pl330->req_done.next,
                                        struct _pl330_req, rqd);
                list_del_init(&rqdone->rqd);
+                /* Detach the req */
+                r = rqdone->r;
+                rqdone->r = NULL;
                spin_unlock_irqrestore(&pl330->lock, flags);
-                _callback(rqdone->r, PL330_ERR_NONE);
+                _callback(r, PL330_ERR_NONE);
                spin_lock_irqsave(&pl330->lock, flags);
        }
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index 2393b5bc96f..8794a34eae6 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -143,7 +143,6 @@ static int sp804_set_next_event(unsigned long next,
 }
 static struct clock_event_device sp804_clockevent = {
-        .shift          = 32,
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .set_mode       = sp804_set_mode,
        .set_next_event = sp804_set_next_event,
@@ -169,13 +168,9 @@ void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
        clkevt_base = base;
        clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
        evt->name = name;
        evt->irq = irq;
-        evt->mult = div_sc(rate, NSEC_PER_SEC, evt->shift);
-        evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
-        evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
        setup_irq(irq, &sp804_timer_irq);
-        clockevents_register_device(evt);
+        clockevents_config_and_register(evt, rate, 0xf, 0xffffffff);
 }
diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c
index 8421d39109b..67dd2affc57 100644
--- a/arch/arm/common/via82c505.c
+++ b/arch/arm/common/via82c505.c
@@ -86,7 +86,8 @@ int __init via82c505_setup(int nr, struct pci_sys_data *sys)
 struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata)
 {
        if (nr == 0)
-                return pci_scan_bus(0, &via82c505_ops, sysdata);
+                return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata,
+                                         &sysdata->resources);
        return NULL;
 }
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 01f18a421b1..dcb004a804c 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -19,17 +19,22 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/syscore_ops.h>
 #include <linux/device.h>
 #include <linux/amba/bus.h>
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
-#ifdef CONFIG_PM
 /**
 * struct vic_device - VIC PM device
 * @irq: The IRQ number for the base of the VIC.
@@ -40,6 +45,7 @@
 * @int_enable: Save for VIC_INT_ENABLE.
 * @soft_int: Save for VIC_INT_SOFT.
 * @protect: Save for VIC_PROTECT.
+ * @domain: The IRQ domain for the VIC.
 */
 struct vic_device {
        void __iomem    *base;
@@ -50,13 +56,13 @@ struct vic_device {
        u32             int_enable;
        u32             soft_int;
        u32             protect;
+        struct irq_domain domain;
 };
 /* we cannot allocate memory when VICs are initially registered */
 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
 static int vic_id;
-#endif /* CONFIG_PM */
 /**
 * vic_init2 - common initialisation code
@@ -156,39 +162,50 @@ static int __init vic_pm_init(void)
        return 0;
 }
 late_initcall(vic_pm_init);
+#endif /* CONFIG_PM */
 /**
- * vic_pm_register - Register a VIC for later power management control
+ * vic_register() - Register a VIC.
 * @base: The base address of the VIC.
 * @irq: The base IRQ for the VIC.
 * @resume_sources: bitmask of interrupts allowed for resume sources.
+ * @node: The device tree node associated with the VIC.
 *
 * Register the VIC with the system device tree so that it can be notified
 * of suspend and resume requests and ensure that the correct actions are
 * taken to re-instate the settings on resume.
+ *
+ * This also configures the IRQ domain for the VIC.
 */
-static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
+static void __init vic_register(void __iomem *base, unsigned int irq,
+                                u32 resume_sources, struct device_node *node)
 {
        struct vic_device *v;
-        if (vic_id >= ARRAY_SIZE(vic_devices))
+        if (vic_id >= ARRAY_SIZE(vic_devices)) {
                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
-        else {
+                return;
-                v = &vic_devices[vic_id];
-                v->base = base;
-                v->resume_sources = resume_sources;
-                v->irq = irq;
-                vic_id++;
        }
+        v = &vic_devices[vic_id];
+        v->base = base;
+        v->resume_sources = resume_sources;
+        v->irq = irq;
+        vic_id++;
+        v->domain.irq_base = irq;
+        v->domain.nr_irq = 32;
+#ifdef CONFIG_OF_IRQ
+        v->domain.of_node = of_node_get(node);
+#endif /* CONFIG_OF */
+        v->domain.ops = &irq_domain_simple_ops;
+        irq_domain_add(&v->domain);
 }
-#else
-static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
-#endif /* CONFIG_PM */
 static void vic_ack_irq(struct irq_data *d)
 {
        void __iomem *base = irq_data_get_irq_chip_data(d);
-        unsigned int irq = d->irq & 31;
+        unsigned int irq = d->hwirq;
        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
        /* moreover, clear the soft-triggered, in case it was the reason */
        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
@@ -197,14 +214,14 @@ static void vic_ack_irq(struct irq_data *d)
 static void vic_mask_irq(struct irq_data *d)
 {
        void __iomem *base = irq_data_get_irq_chip_data(d);
-        unsigned int irq = d->irq & 31;
+        unsigned int irq = d->hwirq;
        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
 }
 static void vic_unmask_irq(struct irq_data *d)
 {
        void __iomem *base = irq_data_get_irq_chip_data(d);
-        unsigned int irq = d->irq & 31;
+        unsigned int irq = d->hwirq;
        writel(1 << irq, base + VIC_INT_ENABLE);
 }
@@ -226,7 +243,7 @@ static struct vic_device *vic_from_irq(unsigned int irq)
 static int vic_set_wake(struct irq_data *d, unsigned int on)
 {
        struct vic_device *v = vic_from_irq(d->irq);
-        unsigned int off = d->irq & 31;
+        unsigned int off = d->hwirq;
        u32 bit = 1 << off;
        if (!v)
@@ -301,7 +318,7 @@ static void __init vic_set_irq_sources(void __iomem *base,
 *  and 020 within the page. We call this "second block".
 */
 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
-                                u32 vic_sources)
+                               u32 vic_sources, struct device_node *node)
 {
        unsigned int i;
        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
@@ -328,17 +345,12 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
        }
        vic_set_irq_sources(base, irq_start, vic_sources);
+        vic_register(base, irq_start, 0, node);
 }
-/**
+static void __init __vic_init(void __iomem *base, unsigned int irq_start,
- * vic_init - initialise a vectored interrupt controller
+                              u32 vic_sources, u32 resume_sources,
- * @base: iomem base address
+                              struct device_node *node)
- * @irq_start: starting interrupt number, must be muliple of 32
- * @vic_sources: bitmask of interrupt sources to allow
- * @resume_sources: bitmask of interrupt sources to allow for resume
- */
-void __init vic_init(void __iomem *base, unsigned int irq_start,
-                     u32 vic_sources, u32 resume_sources)
 {
        unsigned int i;
        u32 cellid = 0;
@@ -356,7 +368,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
        switch(vendor) {
        case AMBA_VENDOR_ST:
-                vic_init_st(base, irq_start, vic_sources);
+                vic_init_st(base, irq_start, vic_sources, node);
                return;
        default:
                printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
@@ -375,5 +387,81 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
        vic_set_irq_sources(base, irq_start, vic_sources);
-        vic_pm_register(base, irq_start, resume_sources);
+        vic_register(base, irq_start, resume_sources, node);
+}
+/**
+ * vic_init() - initialise a vectored interrupt controller
+ * @base: iomem base address
+ * @irq_start: starting interrupt number, must be muliple of 32
+ * @vic_sources: bitmask of interrupt sources to allow
+ * @resume_sources: bitmask of interrupt sources to allow for resume
+ */
+void __init vic_init(void __iomem *base, unsigned int irq_start,
+                     u32 vic_sources, u32 resume_sources)
+{
+        __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
+}
+#ifdef CONFIG_OF
+int __init vic_of_init(struct device_node *node, struct device_node *parent)
+{
+        void __iomem *regs;
+        int irq_base;
+        if (WARN(parent, "non-root VICs are not supported"))
+                return -EINVAL;
+        regs = of_iomap(node, 0);
+        if (WARN_ON(!regs))
+                return -EIO;
+        irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
+        if (WARN_ON(irq_base < 0))
+                goto out_unmap;
+        __vic_init(regs, irq_base, ~0, ~0, node);
+        return 0;
+ out_unmap:
+        iounmap(regs);
+        return -EIO;
+}
+#endif /* CONFIG OF */
+/*
+ * Handle each interrupt in a single VIC.  Returns non-zero if we've
+ * handled at least one interrupt.  This does a single read of the
+ * status register and handles all interrupts in order from LSB first.
+ */
+static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
+{
+        u32 stat, irq;
+        int handled = 0;
+        stat = readl_relaxed(vic->base + VIC_IRQ_STATUS);
+        while (stat) {
+                irq = ffs(stat) - 1;
+                handle_IRQ(irq_domain_to_irq(&vic->domain, irq), regs);
+                stat &= ~(1 << irq);
+                handled = 1;
+        }
+        return handled;
+}
+/*
+ * Keep iterating over all registered VIC's until there are no pending
+ * interrupts.
+ */
+asmlinkage void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
+{
+        int i, handled;
+        do {
+                for (i = 0, handled = 0; i < vic_id; ++i)
+                        handled |= handle_one_vic(&vic_devices[i], regs);
+        } while (handled);
 }
diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig
new file mode 100644
index 00000000000..54571082d92
--- /dev/null
+++ b/arch/arm/configs/bonito_defconfig
@@ -0,0 +1,72 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_R8A7740=y
+CONFIG_MACH_BONITO=y
+# CONFIG_SH_TIMER_TMU is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_ARM_INTEGRATOR=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=9
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_SH_MOBILE=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_UIO=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index cf497ce41df..a22e9307906 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -68,7 +68,6 @@ CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_ADV_OPTIONS=y
 CONFIG_MTD_CFI_GEOMETRY=y
 # CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
 # CONFIG_MTD_CFI_I2 is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_PHYSMAP=y
diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/kota2_defconfig
new file mode 100644
index 00000000000..b7735d6347a
--- /dev/null
+++ b/arch/arm/configs/kota2_defconfig
@@ -0,0 +1,122 @@
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_CPUSETS=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+CONFIG_ARCH_SH73A0=y
+CONFIG_MACH_KOTA2=y
+CONFIG_MEMORY_SIZE=0x1e0000000
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_SWP_EMULATE is not set
+CONFIG_CPU_BPREDICT_DISABLE=y
+CONFIG_ARM_ERRATA_460075=y
+CONFIG_ARM_ERRATA_742230=y
+CONFIG_ARM_ERRATA_742231=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_751472=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_NO_HZ=y
+CONFIG_SMP=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_KEXEC=y
+CONFIG_CPU_IDLE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_CFG80211=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_MAC80211=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_B43=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_DEBUG=y
+CONFIG_INPUT_SPARSEKMAP=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_SH_KEYSC=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=9
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_SH_MOBILE=y
+# CONFIG_HWMON is not set
+CONFIG_BCMA=y
+CONFIG_BCMA_DEBUG=y
+CONFIG_FB=y
+CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_RENESAS_TPU=y
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
new file mode 100644
index 00000000000..864f9a5c39d
--- /dev/null
+++ b/arch/arm/configs/marzen_defconfig
@@ -0,0 +1,87 @@
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_KERNEL_LZMA=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+# CONFIG_BLOCK is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_R8A7779=y
+CONFIG_MACH_MARZEN=y
+CONFIG_MEMORY_START=0x60000000
+CONFIG_MEMORY_SIZE=0x10000000
+CONFIG_SHMOBILE_TIMER_HZ=1024
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_SWP_EMULATE is not set
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_458693=y
+CONFIG_ARM_ERRATA_460075=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_NO_HZ=y
+CONFIG_SMP=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_SMC911X=y
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_SSB=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_UIO=y
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_AVERAGE=y
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index 945a34f2a34..dde2a1af7b3 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -48,7 +48,6 @@ CONFIG_MACH_SX1=y
 CONFIG_MACH_NOKIA770=y
 CONFIG_MACH_AMS_DELTA=y
 CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_OMAP_ARM_182MHZ=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_PCCARD=y
 CONFIG_OMAP_CF=y
diff --git a/arch/arm/configs/pcontrol_g20_defconfig b/arch/arm/configs/pcontrol_g20_defconfig
deleted file mode 100644
index c75c9fcede5..00000000000
--- a/arch/arm/configs/pcontrol_g20_defconfig
+++ /dev/null
@@ -1,175 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_CROSS_COMPILE="/opt/arm-2010q1/bin/arm-none-linux-gnueabi-"
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_TREE_PREEMPT_RCU=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_NAMESPACES=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-# CONFIG_SYSCTL_SYSCALL is not set
-# CONFIG_KALLSYMS is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_DEFAULT_DEADLINE=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9G20=y
-CONFIG_MACH_PCONTROL_G20=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200 mem=128M mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) root=/dev/mmcblk0p1 rootwait rw"
-CONFIG_VFP=y
-CONFIG_BINFMT_MISC=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_VLAN_8021Q=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_TCLIB=y
-CONFIG_EEPROM_AT24=m
-CONFIG_SCSI=m
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=m
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-CONFIG_MACVLAN=m
-CONFIG_TUN=m
-CONFIG_SMSC_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MACB=y
-CONFIG_SMSC911X=m
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-CONFIG_PPP=m
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_MPPE=m
-CONFIG_INPUT_POLLDEV=y
-CONFIG_INPUT_SPARSEKMAP=y
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_MATRIX=m
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
-# CONFIG_SERIO is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_MAX3100=m
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_R3964=m
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-# CONFIG_I2C_HELPER_AUTO is not set
-CONFIG_I2C_GPIO=m
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=m
-CONFIG_SPI_SPIDEV=m
-CONFIG_GPIO_SYSFS=y
-CONFIG_W1=m
-CONFIG_W1_MASTER_GPIO=m
-CONFIG_W1_SLAVE_DS2431=m
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_MFD_SUPPORT is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_LIBUSUAL=y
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_GADGET=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_G_HID=m
-CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_AUXDISPLAY=y
-CONFIG_UIO=y
-CONFIG_UIO_PDRV=y
-CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
-CONFIG_IIO=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_UTF8=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ANSI_CPRNG=y
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 195729760ae..fd5d3041d71 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -9,9 +9,8 @@ CONFIG_RESOURCE_COUNTERS=y
 CONFIG_CGROUP_SCHED=y
 CONFIG_RT_GROUP_SCHED=y
 CONFIG_BLK_DEV_INITRD=y
-CONFIG_EMBEDDED=y
-# CONFIG_SYSCTL_SYSCALL is not set
 # CONFIG_ELF_CORE is not set
+CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
@@ -20,6 +19,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
 CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TEGRA_2x_SOC=y
+CONFIG_ARCH_TEGRA_3x_SOC=y
 CONFIG_MACH_HARMONY=y
 CONFIG_MACH_KAEN=y
 CONFIG_MACH_PAZ00=y
@@ -78,14 +79,12 @@ CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
 CONFIG_DUMMY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_R8169=y
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
 CONFIG_USB_PEGASUS=y
 CONFIG_USB_USBNET=y
 CONFIG_USB_NET_SMSC75XX=y
 CONFIG_USB_NET_SMSC95XX=y
+# CONFIG_WLAN is not set
 # CONFIG_INPUT is not set
 # CONFIG_SERIO is not set
 # CONFIG_VT is not set
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 29035e86a59..b6e65dedfd7 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -187,6 +187,17 @@
 #endif
 /*
+ * Instruction barrier
+ */
+        .macro  instr_sync
+#if __LINUX_ARM_ARCH__ >= 7
+        isb
+#elif __LINUX_ARM_ARCH__ == 6
+        mcr     p15, 0, r0, c7, c5, 4
+#endif
+        .endm
+/*
 * SMP data memory barrier
 */
        .macro  smp_dmb mode
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index 9abe7a07d5a..fac79dceb73 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -32,7 +32,6 @@
 #define __BUG(__file, __line, __value)                          \
 do {                                                            \
-        BUILD_BUG_ON(sizeof(struct bug_entry) != 12);           \
        asm volatile("1:\t" BUG_INSTR_TYPE #__value "\n"        \
                ".pushsection .rodata.str, \"aMS\", %progbits, 1\n" \
                "2:\t.asciz " #__file "\n"                      \
diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
new file mode 100644
index 00000000000..a0ada3ea435
--- /dev/null
+++ b/arch/arm/include/asm/cti.h
@@ -0,0 +1,179 @@
+#ifndef __ASMARM_CTI_H
+#define __ASMARM_CTI_H
+#include        <asm/io.h>
+/* The registers' definition is from section 3.2 of
+ * Embedded Cross Trigger Revision: r0p0
+ */
+#define         CTICONTROL              0x000
+#define         CTISTATUS               0x004
+#define         CTILOCK                 0x008
+#define         CTIPROTECTION           0x00C
+#define         CTIINTACK               0x010
+#define         CTIAPPSET               0x014
+#define         CTIAPPCLEAR             0x018
+#define         CTIAPPPULSE             0x01c
+#define         CTIINEN                 0x020
+#define         CTIOUTEN                0x0A0
+#define         CTITRIGINSTATUS         0x130
+#define         CTITRIGOUTSTATUS        0x134
+#define         CTICHINSTATUS           0x138
+#define         CTICHOUTSTATUS          0x13c
+#define         CTIPERIPHID0            0xFE0
+#define         CTIPERIPHID1            0xFE4
+#define         CTIPERIPHID2            0xFE8
+#define         CTIPERIPHID3            0xFEC
+#define         CTIPCELLID0             0xFF0
+#define         CTIPCELLID1             0xFF4
+#define         CTIPCELLID2             0xFF8
+#define         CTIPCELLID3             0xFFC
+/* The below are from section 3.6.4 of
+ * CoreSight v1.0 Architecture Specification
+ */
+#define         LOCKACCESS              0xFB0
+#define         LOCKSTATUS              0xFB4
+/* write this value to LOCKACCESS will unlock the module, and
+ * other value will lock the module
+ */
+#define         LOCKCODE                0xC5ACCE55
+/**
+ * struct cti - cross trigger interface struct
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out_for_irq: triger out number which will cause
+ *      the @irq happen
+ *
+ * cti struct used to operate cti registers.
+ */
+struct cti {
+        void __iomem *base;
+        int irq;
+        int trig_out_for_irq;
+};
+/**
+ * cti_init - initialize the cti instance
+ * @cti: cti instance
+ * @base: mapped virtual address for the cti base
+ * @irq: irq number for the cti
+ * @trig_out: triger out number which will cause
+ *      the @irq happen
+ *
+ * called by machine code to pass the board dependent
+ * @base, @irq and @trig_out to cti.
+ */
+static inline void cti_init(struct cti *cti,
+        void __iomem *base, int irq, int trig_out)
+{
+        cti->base = base;
+        cti->irq  = irq;
+        cti->trig_out_for_irq = trig_out;
+}
+/**
+ * cti_map_trigger - use the @chan to map @trig_in to @trig_out
+ * @cti: cti instance
+ * @trig_in: trigger in number
+ * @trig_out: trigger out number
+ * @channel: channel number
+ *
+ * This function maps one trigger in of @trig_in to one trigger
+ * out of @trig_out using the channel @chan.
+ */
+static inline void cti_map_trigger(struct cti *cti,
+        int trig_in, int trig_out, int chan)
+{
+        void __iomem *base = cti->base;
+        unsigned long val;
+        val = __raw_readl(base + CTIINEN + trig_in * 4);
+        val |= BIT(chan);
+        __raw_writel(val, base + CTIINEN + trig_in * 4);
+        val = __raw_readl(base + CTIOUTEN + trig_out * 4);
+        val |= BIT(chan);
+        __raw_writel(val, base + CTIOUTEN + trig_out * 4);
+}
+/**
+ * cti_enable - enable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_enable(struct cti *cti)
+{
+        __raw_writel(0x1, cti->base + CTICONTROL);
+}
+/**
+ * cti_disable - disable the cti module
+ * @cti: cti instance
+ *
+ * enable the cti module
+ */
+static inline void cti_disable(struct cti *cti)
+{
+        __raw_writel(0, cti->base + CTICONTROL);
+}
+/**
+ * cti_irq_ack - clear the cti irq
+ * @cti: cti instance
+ *
+ * clear the cti irq
+ */
+static inline void cti_irq_ack(struct cti *cti)
+{
+        void __iomem *base = cti->base;
+        unsigned long val;
+        val = __raw_readl(base + CTIINTACK);
+        val |= BIT(cti->trig_out_for_irq);
+        __raw_writel(val, base + CTIINTACK);
+}
+/**
+ * cti_unlock - unlock cti module
+ * @cti: cti instance
+ *
+ * unlock the cti module, or else any writes to the cti
+ * module is not allowed.
+ */
+static inline void cti_unlock(struct cti *cti)
+{
+        void __iomem *base = cti->base;
+        unsigned long val;
+        val = __raw_readl(base + LOCKSTATUS);
+        if (val & 1) {
+                val = LOCKCODE;
+                __raw_writel(val, base + LOCKACCESS);
+        }
+}
+/**
+ * cti_lock - lock cti module
+ * @cti: cti instance
+ *
+ * lock the cti module, so any writes to the cti
+ * module will be not allowed.
+ */
+static inline void cti_lock(struct cti *cti)
+{
+        void __iomem *base = cti->base;
+        unsigned long val;
+        val = __raw_readl(base + LOCKSTATUS);
+        if (!(val & 1)) {
+                val = ~LOCKCODE;
+                __raw_writel(val, base + LOCKACCESS);
+        }
+}
+#endif
diff --git a/arch/arm/include/asm/edac.h b/arch/arm/include/asm/edac.h
new file mode 100644
index 00000000000..0df7a2c1fc3
--- /dev/null
+++ b/arch/arm/include/asm/edac.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ * Based on PPC version Copyright 2007 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef ASM_EDAC_H
+#define ASM_EDAC_H
+/*
+ * ECC atomic, DMA, SMP and interrupt safe scrub function.
+ * Implements the per arch atomic_scrub() that EDAC use for software
+ * ECC scrubbing.  It reads memory and then writes back the original
+ * value, allowing the hardware to detect and correct memory errors.
+ */
+static inline void atomic_scrub(void *va, u32 size)
+{
+#if __LINUX_ARM_ARCH__ >= 6
+        unsigned int *virt_addr = va;
+        unsigned int temp, temp2;
+        unsigned int i;
+        for (i = 0; i < size / sizeof(*virt_addr); i++, virt_addr++) {
+                /* Very carefully read and write to memory atomically
+                 * so we are interrupt, DMA and SMP safe.
+                 */
+                __asm__ __volatile__("\n"
+                        "1:     ldrex   %0, [%2]\n"
+                        "       strex   %1, %0, [%2]\n"
+                        "       teq     %1, #0\n"
+                        "       bne     1b\n"
+                        : "=&r"(temp), "=&r"(temp2)
+                        : "r"(virt_addr)
+                        : "cc");
+        }
+#endif
+}
+#endif
diff --git a/arch/arm/include/asm/entry-macro-vic2.S b/arch/arm/include/asm/entry-macro-vic2.S
deleted file mode 100644
index 3ceb85e4385..00000000000
--- a/arch/arm/include/asm/entry-macro-vic2.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/* arch/arm/include/asm/entry-macro-vic2.S
- *
- * Originally arch/arm/mach-s3c6400/include/mach/entry-macro.S
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Low-level IRQ helper macros for a device with two VICs
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
-*/
-/* This should be included from <mach/entry-macro.S> with the necessary
- * defines for virtual addresses and IRQ bases for the two vics.
- *
- * The code needs the following defined:
- *      IRQ_VIC0_BASE   IRQ number of VIC0's first IRQ
- *      IRQ_VIC1_BASE   IRQ number of VIC1's first IRQ
- *      VA_VIC0         Virtual address of VIC0
- *      VA_VIC1         Virtual address of VIC1
- *
- * Note, code assumes VIC0's virtual address is an ARM immediate constant
- * away from VIC1.
-*/
-#include <asm/hardware/vic.h>
-        .macro  disable_fiq
-        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =VA_VIC0
-        .endm
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ check the vic0
-        mov     \irqnr, #IRQ_VIC0_BASE + 31
-        ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
-        teq     \irqstat, #0
-        @ otherwise try vic1
-        addeq   \tmp, \base, #(VA_VIC1 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #(IRQ_VIC1_BASE - IRQ_VIC0_BASE)
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        clzne   \irqstat, \irqstat
-        subne   \irqnr, \irqnr, \irqstat
-        .endm
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 11ad0bfbb0a..c402e9b31f4 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -1,6 +1,10 @@
 #ifndef _ARCH_ARM_GPIO_H
 #define _ARCH_ARM_GPIO_H
+#if CONFIG_ARCH_NR_GPIO > 0
+#define ARCH_NR_GPIOS CONFIG_ARCH_NR_GPIO
+#endif
 /* not all ARM platforms necessarily support this API ... */
 #include <mach/gpio.h>
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index ddf07a92a6c..436e60b2cf7 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -27,23 +27,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu);
 #define arch_irq_stat_cpu       smp_irq_stat_cpu
-#if NR_IRQS > 512
-#define HARDIRQ_BITS    10
-#elif NR_IRQS > 256
-#define HARDIRQ_BITS    9
-#else
-#define HARDIRQ_BITS    8
-#endif
-/*
- * The hardirq mask has to be large enough to have space
- * for potentially all IRQ sources in the system nesting
- * on a single CPU:
- */
-#if (1 << HARDIRQ_BITS) < NR_IRQS
-# error HARDIRQ_BITS is too low!
-#endif
 #define __ARCH_IRQ_EXIT_IRQS_DISABLED   1
 #endif /* __ASM_HARDIRQ_H */
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
deleted file mode 100644
index 74ebc803904..00000000000
--- a/arch/arm/include/asm/hardware/entry-macro-gic.S
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/include/asm/hardware/entry-macro-gic.S
- *
- * Low-level IRQ helper macros for GIC
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/hardware/gic.h>
-#ifndef HAVE_GET_IRQNR_PREAMBLE
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =gic_cpu_base_addr
-        ldr     \base, [\base]
-        .endm
-#endif
-/*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec.  To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-31 are local.  We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt.  We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-        /* bits 12-10 = src CPU, 9-0 = int # */
-        ldr     \tmp, =1021
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #15
-        cmpcc   \irqnr, \irqnr
-        cmpne   \irqnr, \tmp
-        cmpcs   \irqnr, \irqnr
-        .endm
-/* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-        .macro test_for_ipi, irqnr, irqstat, base, tmp
-        bic     \irqnr, \irqstat, #0x1c00
-        cmp     \irqnr, #16
-        strcc   \irqstat, [\base, #GIC_CPU_EOI]
-        cmpcs   \irqnr, \irqnr
-        .endm
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 3e91f22046f..4bdfe001869 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -36,30 +36,22 @@
 #include <linux/irqdomain.h>
 struct device_node;
-extern void __iomem *gic_cpu_base_addr;
 extern struct irq_chip gic_arch_extn;
-void gic_init(unsigned int, int, void __iomem *, void __iomem *);
+void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
+                    u32 offset);
 int gic_of_init(struct device_node *node, struct device_node *parent);
 void gic_secondary_init(unsigned int);
+void gic_handle_irq(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
-struct gic_chip_data {
+static inline void gic_init(unsigned int nr, int start,
-        void __iomem *dist_base;
+                            void __iomem *dist , void __iomem *cpu)
-        void __iomem *cpu_base;
+{
-#ifdef CONFIG_CPU_PM
+        gic_init_bases(nr, start, dist, cpu, 0);
-        u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
+}
-        u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
-        u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
-        u32 __percpu *saved_ppi_enable;
-        u32 __percpu *saved_ppi_conf;
-#endif
-#ifdef CONFIG_IRQ_DOMAIN
-        struct irq_domain domain;
-#endif
-        unsigned int gic_irqs;
-};
 #endif
 #endif
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index 5daea2961d4..077c32326c6 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -234,6 +234,7 @@ extern int iop3xx_get_init_atu(void);
 void iop3xx_map_io(void);
 void iop_init_cp6_handler(void);
 void iop_init_time(unsigned long tickrate);
+void iop3xx_restart(char, const char *);
 static inline u32 read_tmr0(void)
 {
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index 5d72550a809..f42ebd61959 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -41,7 +41,15 @@
 #define VIC_PL192_VECT_ADDR             0xF00
 #ifndef __ASSEMBLY__
+#include <linux/compiler.h>
+#include <linux/types.h>
+struct device_node;
+struct pt_regs;
 void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
-#endif
+int vic_of_init(struct device_node *node, struct device_node *parent);
+void vic_handle_irq(struct pt_regs *regs);
+#endif /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index c93a22a8b92..917626128a1 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -25,7 +25,8 @@
 #define HWCAP_IDIVT     (1 << 18)
 #define HWCAP_IDIV      (HWCAP_IDIVA | HWCAP_IDIVT)
-#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+#if defined(__KERNEL__)
+#if !defined(__ASSEMBLY__)
 /*
 * This yields a mask that user programs can use to figure out what
 * instruction set this cpu supports.
@@ -33,5 +34,6 @@
 #define ELF_HWCAP       (elf_hwcap)
 extern unsigned int elf_hwcap;
 #endif
+#endif
 #endif
diff --git a/arch/arm/include/asm/idmap.h b/arch/arm/include/asm/idmap.h
new file mode 100644
index 00000000000..bf863edb517
--- /dev/null
+++ b/arch/arm/include/asm/idmap.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_IDMAP_H
+#define __ASM_IDMAP_H
+#include <linux/compiler.h>
+#include <asm/pgtable.h>
+/* Tag a function as requiring to be executed via an identity mapping. */
+#define __idmap __section(.idmap.text) noinline notrace
+extern pgd_t *idmap_pgd;
+void setup_mm_for_reboot(void);
+#endif  /* __ASM_IDMAP_H */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 065d100fa63..9275828feb3 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -27,6 +27,7 @@
 #include <asm/byteorder.h>
 #include <asm/memory.h>
 #include <asm/system.h>
+#include <asm-generic/pci_iomap.h>
 /*
 * ISA I/O bus memory addresses are 1:1 with the physical address.
@@ -306,7 +307,6 @@ extern void ioport_unmap(void __iomem *addr);
 struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 /*
diff --git a/arch/arm/include/asm/ipcbuf.h b/arch/arm/include/asm/ipcbuf.h
index 97683975f7d..84c7e51cb6d 100644
--- a/arch/arm/include/asm/ipcbuf.h
+++ b/arch/arm/include/asm/ipcbuf.h
@@ -1,29 +1 @@
-#ifndef __ASMARM_IPCBUF_H
+#include <asm-generic/ipcbuf.h>
-#define __ASMARM_IPCBUF_H
-/*
- * The ipc64_perm structure for arm architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit mode_t and seq
- * - 2 miscellaneous 32-bit values
- */
-struct ipc64_perm
-{
-        __kernel_key_t          key;
-        __kernel_uid32_t        uid;
-        __kernel_gid32_t        gid;
-        __kernel_uid32_t        cuid;
-        __kernel_gid32_t        cgid;
-        __kernel_mode_t         mode;
-        unsigned short          __pad1;
-        unsigned short          seq;
-        unsigned short          __pad2;
-        unsigned long           __unused1;
-        unsigned long           __unused2;
-};
-#endif /* __ASMARM_IPCBUF_H */
diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h
index feec86768f9..f82ec22eeb1 100644
--- a/arch/arm/include/asm/kprobes.h
+++ b/arch/arm/include/asm/kprobes.h
@@ -24,7 +24,6 @@
 #define MAX_INSN_SIZE                   2
 #define MAX_STACK_SIZE                  64      /* 32 would probably be OK */
-#define regs_return_value(regs)         ((regs)->ARM_r0)
 #define flush_insn_slot(p)              do { } while (0)
 #define kretprobe_blacklist_size        0
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 2b0efc3104a..d7692cafde7 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -19,7 +19,7 @@ struct machine_desc {
        unsigned int            nr;             /* architecture number  */
        const char              *name;          /* architecture name    */
        unsigned long           atag_offset;    /* tagged list (relative) */
-        const char              **dt_compat;    /* array of device tree
+        const char *const       *dt_compat;     /* array of device tree
                                                 * 'compatible' strings */
        unsigned int            nr_irqs;        /* number of IRQs */
@@ -31,10 +31,10 @@ struct machine_desc {
        unsigned int            video_start;    /* start of video RAM   */
        unsigned int            video_end;      /* end of video RAM     */
-        unsigned int            reserve_lp0 :1; /* never has lp0        */
+        unsigned char           reserve_lp0 :1; /* never has lp0        */
-        unsigned int            reserve_lp1 :1; /* never has lp1        */
+        unsigned char           reserve_lp1 :1; /* never has lp1        */
-        unsigned int            reserve_lp2 :1; /* never has lp2        */
+        unsigned char           reserve_lp2 :1; /* never has lp2        */
-        unsigned int            soft_reboot :1; /* soft reboot          */
+        char                    restart_mode;   /* default restart mode */
        void                    (*fixup)(struct tag *, char **,
                                         struct meminfo *);
        void                    (*reserve)(void);/* reserve mem blocks  */
@@ -46,6 +46,7 @@ struct machine_desc {
 #ifdef CONFIG_MULTI_IRQ_HANDLER
        void                    (*handle_irq)(struct pt_regs *);
 #endif
+        void                    (*restart)(char, const char *);
 };
 /*
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 186efd4e05c..d943b7d20f1 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -40,7 +40,7 @@ struct pci_sys_data {
        u64             mem_offset;     /* bus->cpu memory mapping offset       */
        unsigned long   io_offset;      /* bus->cpu IO mapping offset           */
        struct pci_bus  *bus;           /* PCI bus                              */
-        struct resource *resource[3];   /* Primary PCI bus resources            */
+        struct list_head resources;     /* root bus resources (apertures)       */
                                        /* Bridge swizzling                     */
        u8              (*swizzle)(struct pci_dev *, u8 *);
                                        /* IRQ mapping                          */
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h
index d5adaae5ee2..f73c908b7fa 100644
--- a/arch/arm/include/asm/mach/time.h
+++ b/arch/arm/include/asm/mach/time.h
@@ -10,8 +10,6 @@
 #ifndef __ASM_ARM_MACH_TIME_H
 #define __ASM_ARM_MACH_TIME_H
-#include <linux/sysdev.h>
 /*
 * This is our kernel timer structure.
 *
diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h
index b8da2e415e4..00ca5f92648 100644
--- a/arch/arm/include/asm/memblock.h
+++ b/arch/arm/include/asm/memblock.h
@@ -6,4 +6,6 @@ struct machine_desc;
 extern void arm_memblock_init(struct meminfo *, struct machine_desc *);
+phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align);
 #endif
diff --git a/arch/arm/include/asm/opcodes.h b/arch/arm/include/asm/opcodes.h
new file mode 100644
index 00000000000..c0efdd60966
--- /dev/null
+++ b/arch/arm/include/asm/opcodes.h
@@ -0,0 +1,20 @@
+/*
+ *  arch/arm/include/asm/opcodes.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_OPCODES_H
+#define __ASM_ARM_OPCODES_H
+#ifndef __ASSEMBLY__
+extern asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr);
+#endif
+#define ARM_OPCODE_CONDTEST_FAIL   0
+#define ARM_OPCODE_CONDTEST_PASS   1
+#define ARM_OPCODE_CONDTEST_UNCOND 2
+#endif /* __ASM_ARM_OPCODES_H */
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index ca94653f1ec..97b440c25c5 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -151,7 +151,11 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
 #define clear_page(page)        memset((void *)(page), 0, PAGE_SIZE)
 extern void copy_page(void *to, const void *from);
+#ifdef CONFIG_ARM_LPAE
+#include <asm/pgtable-3level-types.h>
+#else
 #include <asm/pgtable-2level-types.h>
+#endif
 #endif /* CONFIG_MMU */
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 2b1f245db0c..da337ba57ff 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -31,18 +31,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
 }
 #endif /* CONFIG_PCI_DOMAINS */
-#ifdef CONFIG_PCI_HOST_ITE8152
-/* ITE bridge requires setting latency timer to avoid early bus access
-   termination by PIC bus mater devices
-*/
-extern void pcibios_set_master(struct pci_dev *dev);
-#else
-static inline void pcibios_set_master(struct pci_dev *dev)
-{
-        /* No special bus mastering setup handling */
-}
-#endif
 static inline void pcibios_penalize_isa_irq(int irq, int active)
 {
        /* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 0f8e3827a89..99cfe360798 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -32,7 +32,4 @@ enum arm_perf_pmu_ids {
 extern enum arm_perf_pmu_ids
 armpmu_get_pmu_id(void);
-extern int
-armpmu_get_max_events(void);
 #endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h
index 3e08fd3fbb6..943504f53f5 100644
--- a/arch/arm/include/asm/pgalloc.h
+++ b/arch/arm/include/asm/pgalloc.h
@@ -25,12 +25,34 @@
 #define _PAGE_USER_TABLE        (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
 #define _PAGE_KERNEL_TABLE      (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
+#ifdef CONFIG_ARM_LPAE
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        return (pmd_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
+}
+static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+        BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
+        free_page((unsigned long)pmd);
+}
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+        set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE));
+}
+#else   /* !CONFIG_ARM_LPAE */
 /*
 * Since we have only two-level page tables, these are trivial
 */
 #define pmd_alloc_one(mm,addr)          ({ BUG(); ((pmd_t *)2); })
 #define pmd_free(mm, pmd)               do { } while (0)
-#define pgd_populate(mm,pmd,pte)        BUG()
+#define pud_populate(mm,pmd,pte)        BUG()
+#endif  /* CONFIG_ARM_LPAE */
 extern pgd_t *pgd_alloc(struct mm_struct *mm);
 extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
@@ -109,7 +131,9 @@ static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte,
 {
        pmdval_t pmdval = (pte + PTE_HWTABLE_OFF) | prot;
        pmdp[0] = __pmd(pmdval);
+#ifndef CONFIG_ARM_LPAE
        pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
+#endif
        flush_pmd_entry(pmdp);
 }
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
index 470457e1cfc..2317a71c8f8 100644
--- a/arch/arm/include/asm/pgtable-2level.h
+++ b/arch/arm/include/asm/pgtable-2level.h
@@ -140,4 +140,45 @@
 #define L_PTE_MT_DEV_CACHED     (_AT(pteval_t, 0x0b) << 2)      /* 1011 */
 #define L_PTE_MT_MASK           (_AT(pteval_t, 0x0f) << 2)
+#ifndef __ASSEMBLY__
+/*
+ * The "pud_xxx()" functions here are trivial when the pmd is folded into
+ * the pud: the pud entry is never bad, always exists, and can't be set or
+ * cleared.
+ */
+#define pud_none(pud)           (0)
+#define pud_bad(pud)            (0)
+#define pud_present(pud)        (1)
+#define pud_clear(pudp)         do { } while (0)
+#define set_pud(pud,pudp)       do { } while (0)
+static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
+{
+        return (pmd_t *)pud;
+}
+#define pmd_bad(pmd)            (pmd_val(pmd) & 2)
+#define copy_pmd(pmdpd,pmdps)           \
+        do {                            \
+                pmdpd[0] = pmdps[0];    \
+                pmdpd[1] = pmdps[1];    \
+                flush_pmd_entry(pmdpd); \
+        } while (0)
+#define pmd_clear(pmdp)                 \
+        do {                            \
+                pmdp[0] = __pmd(0);     \
+                pmdp[1] = __pmd(0);     \
+                clean_pmd_entry(pmdp);  \
+        } while (0)
+/* we don't need complex calculations here as the pmd is folded into the pgd */
+#define pmd_addr_end(addr,end) (end)
+#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
+#endif /* __ASSEMBLY__ */
 #endif /* _ASM_PGTABLE_2LEVEL_H */
diff --git a/arch/arm/include/asm/pgtable-3level-hwdef.h b/arch/arm/include/asm/pgtable-3level-hwdef.h
new file mode 100644
index 00000000000..d7952824c5c
--- /dev/null
+++ b/arch/arm/include/asm/pgtable-3level-hwdef.h
@@ -0,0 +1,77 @@
+/*
+ * arch/arm/include/asm/pgtable-3level-hwdef.h
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_PGTABLE_3LEVEL_HWDEF_H
+#define _ASM_PGTABLE_3LEVEL_HWDEF_H
+/*
+ * Hardware page table definitions.
+ *
+ * + Level 1/2 descriptor
+ *   - common
+ */
+#define PMD_TYPE_MASK           (_AT(pmdval_t, 3) << 0)
+#define PMD_TYPE_FAULT          (_AT(pmdval_t, 0) << 0)
+#define PMD_TYPE_TABLE          (_AT(pmdval_t, 3) << 0)
+#define PMD_TYPE_SECT           (_AT(pmdval_t, 1) << 0)
+#define PMD_BIT4                (_AT(pmdval_t, 0))
+#define PMD_DOMAIN(x)           (_AT(pmdval_t, 0))
+/*
+ *   - section
+ */
+#define PMD_SECT_BUFFERABLE     (_AT(pmdval_t, 1) << 2)
+#define PMD_SECT_CACHEABLE      (_AT(pmdval_t, 1) << 3)
+#define PMD_SECT_S              (_AT(pmdval_t, 3) << 8)
+#define PMD_SECT_AF             (_AT(pmdval_t, 1) << 10)
+#define PMD_SECT_nG             (_AT(pmdval_t, 1) << 11)
+#define PMD_SECT_XN             (_AT(pmdval_t, 1) << 54)
+#define PMD_SECT_AP_WRITE       (_AT(pmdval_t, 0))
+#define PMD_SECT_AP_READ        (_AT(pmdval_t, 0))
+#define PMD_SECT_TEX(x)         (_AT(pmdval_t, 0))
+/*
+ * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
+ */
+#define PMD_SECT_UNCACHED       (_AT(pmdval_t, 0) << 2) /* strongly ordered */
+#define PMD_SECT_BUFFERED       (_AT(pmdval_t, 1) << 2) /* normal non-cacheable */
+#define PMD_SECT_WT             (_AT(pmdval_t, 2) << 2) /* normal inner write-through */
+#define PMD_SECT_WB             (_AT(pmdval_t, 3) << 2) /* normal inner write-back */
+#define PMD_SECT_WBWA           (_AT(pmdval_t, 7) << 2) /* normal inner write-alloc */
+/*
+ * + Level 3 descriptor (PTE)
+ */
+#define PTE_TYPE_MASK           (_AT(pteval_t, 3) << 0)
+#define PTE_TYPE_FAULT          (_AT(pteval_t, 0) << 0)
+#define PTE_TYPE_PAGE           (_AT(pteval_t, 3) << 0)
+#define PTE_BUFFERABLE          (_AT(pteval_t, 1) << 2)         /* AttrIndx[0] */
+#define PTE_CACHEABLE           (_AT(pteval_t, 1) << 3)         /* AttrIndx[1] */
+#define PTE_EXT_SHARED          (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
+#define PTE_EXT_AF              (_AT(pteval_t, 1) << 10)        /* Access Flag */
+#define PTE_EXT_NG              (_AT(pteval_t, 1) << 11)        /* nG */
+#define PTE_EXT_XN              (_AT(pteval_t, 1) << 54)        /* XN */
+/*
+ * 40-bit physical address supported.
+ */
+#define PHYS_MASK_SHIFT         (40)
+#define PHYS_MASK               ((1ULL << PHYS_MASK_SHIFT) - 1)
+#endif
diff --git a/arch/arm/include/asm/pgtable-3level-types.h b/arch/arm/include/asm/pgtable-3level-types.h
new file mode 100644
index 00000000000..921aa30259c
--- /dev/null
+++ b/arch/arm/include/asm/pgtable-3level-types.h
@@ -0,0 +1,70 @@
+/*
+ * arch/arm/include/asm/pgtable-3level-types.h
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_PGTABLE_3LEVEL_TYPES_H
+#define _ASM_PGTABLE_3LEVEL_TYPES_H
+#include <asm/types.h>
+typedef u64 pteval_t;
+typedef u64 pmdval_t;
+typedef u64 pgdval_t;
+#undef STRICT_MM_TYPECHECKS
+#ifdef STRICT_MM_TYPECHECKS
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { pteval_t pte; } pte_t;
+typedef struct { pmdval_t pmd; } pmd_t;
+typedef struct { pgdval_t pgd; } pgd_t;
+typedef struct { pteval_t pgprot; } pgprot_t;
+#define pte_val(x)      ((x).pte)
+#define pmd_val(x)      ((x).pmd)
+#define pgd_val(x)      ((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+#define __pte(x)        ((pte_t) { (x) } )
+#define __pmd(x)        ((pmd_t) { (x) } )
+#define __pgd(x)        ((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+#else   /* !STRICT_MM_TYPECHECKS */
+typedef pteval_t pte_t;
+typedef pmdval_t pmd_t;
+typedef pgdval_t pgd_t;
+typedef pteval_t pgprot_t;
+#define pte_val(x)      (x)
+#define pmd_val(x)      (x)
+#define pgd_val(x)      (x)
+#define pgprot_val(x)   (x)
+#define __pte(x)        (x)
+#define __pmd(x)        (x)
+#define __pgd(x)        (x)
+#define __pgprot(x)     (x)
+#endif  /* STRICT_MM_TYPECHECKS */
+#endif  /* _ASM_PGTABLE_3LEVEL_TYPES_H */
diff --git a/arch/arm/include/asm/pgtable-3level.h b/arch/arm/include/asm/pgtable-3level.h
new file mode 100644
index 00000000000..759af70f9a0
--- /dev/null
+++ b/arch/arm/include/asm/pgtable-3level.h
@@ -0,0 +1,155 @@
+/*
+ * arch/arm/include/asm/pgtable-3level.h
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef _ASM_PGTABLE_3LEVEL_H
+#define _ASM_PGTABLE_3LEVEL_H
+/*
+ * With LPAE, there are 3 levels of page tables. Each level has 512 entries of
+ * 8 bytes each, occupying a 4K page. The first level table covers a range of
+ * 512GB, each entry representing 1GB. Since we are limited to 4GB input
+ * address range, only 4 entries in the PGD are used.
+ *
+ * There are enough spare bits in a page table entry for the kernel specific
+ * state.
+ */
+#define PTRS_PER_PTE            512
+#define PTRS_PER_PMD            512
+#define PTRS_PER_PGD            4
+#define PTE_HWTABLE_PTRS        (PTRS_PER_PTE)
+#define PTE_HWTABLE_OFF         (0)
+#define PTE_HWTABLE_SIZE        (PTRS_PER_PTE * sizeof(u64))
+/*
+ * PGDIR_SHIFT determines the size a top-level page table entry can map.
+ */
+#define PGDIR_SHIFT             30
+/*
+ * PMD_SHIFT determines the size a middle-level page table entry can map.
+ */
+#define PMD_SHIFT               21
+#define PMD_SIZE                (1UL << PMD_SHIFT)
+#define PMD_MASK                (~(PMD_SIZE-1))
+#define PGDIR_SIZE              (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK              (~(PGDIR_SIZE-1))
+/*
+ * section address mask and size definitions.
+ */
+#define SECTION_SHIFT           21
+#define SECTION_SIZE            (1UL << SECTION_SHIFT)
+#define SECTION_MASK            (~(SECTION_SIZE-1))
+#define USER_PTRS_PER_PGD       (PAGE_OFFSET / PGDIR_SIZE)
+/*
+ * "Linux" PTE definitions for LPAE.
+ *
+ * These bits overlap with the hardware bits but the naming is preserved for
+ * consistency with the classic page table format.
+ */
+#define L_PTE_PRESENT           (_AT(pteval_t, 3) << 0)         /* Valid */
+#define L_PTE_FILE              (_AT(pteval_t, 1) << 2)         /* only when !PRESENT */
+#define L_PTE_BUFFERABLE        (_AT(pteval_t, 1) << 2)         /* AttrIndx[0] */
+#define L_PTE_CACHEABLE         (_AT(pteval_t, 1) << 3)         /* AttrIndx[1] */
+#define L_PTE_USER              (_AT(pteval_t, 1) << 6)         /* AP[1] */
+#define L_PTE_RDONLY            (_AT(pteval_t, 1) << 7)         /* AP[2] */
+#define L_PTE_SHARED            (_AT(pteval_t, 3) << 8)         /* SH[1:0], inner shareable */
+#define L_PTE_YOUNG             (_AT(pteval_t, 1) << 10)        /* AF */
+#define L_PTE_XN                (_AT(pteval_t, 1) << 54)        /* XN */
+#define L_PTE_DIRTY             (_AT(pteval_t, 1) << 55)        /* unused */
+#define L_PTE_SPECIAL           (_AT(pteval_t, 1) << 56)        /* unused */
+/*
+ * To be used in assembly code with the upper page attributes.
+ */
+#define L_PTE_XN_HIGH           (1 << (54 - 32))
+#define L_PTE_DIRTY_HIGH        (1 << (55 - 32))
+/*
+ * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
+ */
+#define L_PTE_MT_UNCACHED       (_AT(pteval_t, 0) << 2) /* strongly ordered */
+#define L_PTE_MT_BUFFERABLE     (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
+#define L_PTE_MT_WRITETHROUGH   (_AT(pteval_t, 2) << 2) /* normal inner write-through */
+#define L_PTE_MT_WRITEBACK      (_AT(pteval_t, 3) << 2) /* normal inner write-back */
+#define L_PTE_MT_WRITEALLOC     (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
+#define L_PTE_MT_DEV_SHARED     (_AT(pteval_t, 4) << 2) /* device */
+#define L_PTE_MT_DEV_NONSHARED  (_AT(pteval_t, 4) << 2) /* device */
+#define L_PTE_MT_DEV_WC         (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
+#define L_PTE_MT_DEV_CACHED     (_AT(pteval_t, 3) << 2) /* normal inner write-back */
+#define L_PTE_MT_MASK           (_AT(pteval_t, 7) << 2)
+/*
+ * Software PGD flags.
+ */
+#define L_PGD_SWAPPER           (_AT(pgdval_t, 1) << 55)        /* swapper_pg_dir entry */
+#ifndef __ASSEMBLY__
+#define pud_none(pud)           (!pud_val(pud))
+#define pud_bad(pud)            (!(pud_val(pud) & 2))
+#define pud_present(pud)        (pud_val(pud))
+#define pud_clear(pudp)                 \
+        do {                            \
+                *pudp = __pud(0);       \
+                clean_pmd_entry(pudp);  \
+        } while (0)
+#define set_pud(pudp, pud)              \
+        do {                            \
+                *pudp = pud;            \
+                flush_pmd_entry(pudp);  \
+        } while (0)
+static inline pmd_t *pud_page_vaddr(pud_t pud)
+{
+        return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
+}
+/* Find an entry in the second-level page table.. */
+#define pmd_index(addr)         (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
+static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
+{
+        return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
+}
+#define pmd_bad(pmd)            (!(pmd_val(pmd) & 2))
+#define copy_pmd(pmdpd,pmdps)           \
+        do {                            \
+                *pmdpd = *pmdps;        \
+                flush_pmd_entry(pmdpd); \
+        } while (0)
+#define pmd_clear(pmdp)                 \
+        do {                            \
+                *pmdp = __pmd(0);       \
+                clean_pmd_entry(pmdp);  \
+        } while (0)
+#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_PGTABLE_3LEVEL_H */
diff --git a/arch/arm/include/asm/pgtable-hwdef.h b/arch/arm/include/asm/pgtable-hwdef.h
index 183111164ce..8426229ba29 100644
--- a/arch/arm/include/asm/pgtable-hwdef.h
+++ b/arch/arm/include/asm/pgtable-hwdef.h
@@ -10,6 +10,10 @@
 #ifndef _ASMARM_PGTABLE_HWDEF_H
 #define _ASMARM_PGTABLE_HWDEF_H
+#ifdef CONFIG_ARM_LPAE
+#include <asm/pgtable-3level-hwdef.h>
+#else
 #include <asm/pgtable-2level-hwdef.h>
+#endif
 #endif
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 9451dce3a55..f66626d71e7 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -11,20 +11,24 @@
 #define _ASMARM_PGTABLE_H
 #include <linux/const.h>
-#include <asm-generic/4level-fixup.h>
 #include <asm/proc-fns.h>
 #ifndef CONFIG_MMU
+#include <asm-generic/4level-fixup.h>
 #include "pgtable-nommu.h"
 #else
+#include <asm-generic/pgtable-nopud.h>
 #include <asm/memory.h>
-#include <mach/vmalloc.h>
 #include <asm/pgtable-hwdef.h>
+#ifdef CONFIG_ARM_LPAE
+#include <asm/pgtable-3level.h>
+#else
 #include <asm/pgtable-2level.h>
+#endif
 /*
 * Just any arbitrary offset to the start of the vmalloc VM area: the
@@ -33,15 +37,10 @@
 * any out-of-bounds memory accesses will hopefully be caught.
 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 * area for the same reason. ;)
- *
- * Note that platforms may override VMALLOC_START, but they must provide
- * VMALLOC_END.  VMALLOC_END defines the (exclusive) limit of this space,
- * which may not overlap IO space.
 */
-#ifndef VMALLOC_START
 #define VMALLOC_OFFSET          (8*1024*1024)
 #define VMALLOC_START           (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
-#endif
+#define VMALLOC_END             0xff000000UL
 #define LIBRARY_TEXT_START      0x0c000000
@@ -163,39 +162,8 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 /* to find an entry in a kernel page-table-directory */
 #define pgd_offset_k(addr)      pgd_offset(&init_mm, addr)
-/*
- * The "pgd_xxx()" functions here are trivial for a folded two-level
- * setup: the pgd is never bad, and a pmd always exists (as it's folded
- * into the pgd entry)
- */
-#define pgd_none(pgd)           (0)
-#define pgd_bad(pgd)            (0)
-#define pgd_present(pgd)        (1)
-#define pgd_clear(pgdp)         do { } while (0)
-#define set_pgd(pgd,pgdp)       do { } while (0)
-#define set_pud(pud,pudp)       do { } while (0)
-/* Find an entry in the second-level page table.. */
-#define pmd_offset(dir, addr)   ((pmd_t *)(dir))
 #define pmd_none(pmd)           (!pmd_val(pmd))
 #define pmd_present(pmd)        (pmd_val(pmd))
-#define pmd_bad(pmd)            (pmd_val(pmd) & 2)
-#define copy_pmd(pmdpd,pmdps)           \
-        do {                            \
-                pmdpd[0] = pmdps[0];    \
-                pmdpd[1] = pmdps[1];    \
-                flush_pmd_entry(pmdpd); \
-        } while (0)
-#define pmd_clear(pmdp)                 \
-        do {                            \
-                pmdp[0] = __pmd(0);     \
-                pmdp[1] = __pmd(0);     \
-                clean_pmd_entry(pmdp);  \
-        } while (0)
 static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 {
@@ -204,10 +172,6 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 #define pmd_page(pmd)           pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK))
-/* we don't need complex calculations here as the pmd is folded into the pgd */
-#define pmd_addr_end(addr,end)  (end)
 #ifndef CONFIG_HIGHPTE
 #define __pte_map(pmd)          pmd_page_vaddr(*(pmd))
 #define __pte_unmap(pte)        do { } while (0)
@@ -229,7 +193,6 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 #define pte_page(pte)           pfn_to_page(pte_pfn(pte))
 #define mk_pte(page,prot)       pfn_pte(page_to_pfn(page), prot)
-#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
 #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
 #if __LINUX_ARM_ARCH__ < 6
@@ -336,6 +299,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 * We provide our own arch_get_unmapped_area to cope with VIPT caches.
 */
 #define HAVE_ARCH_UNMAPPED_AREA
+#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
 /*
 * remap a physical page `pfn' of size `size' with page protection `prot'
@@ -346,9 +310,6 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 #define pgtable_cache_init() do { } while (0)
-void identity_mapping_add(pgd_t *, unsigned long, unsigned long);
-void identity_mapping_del(pgd_t *, unsigned long, unsigned long);
 #endif /* !__ASSEMBLY__ */
 #endif /* CONFIG_MMU */
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 0bda22c094a..b5a5be2536c 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -27,13 +27,22 @@ enum arm_pmu_type {
 /*
 * struct arm_pmu_platdata - ARM PMU platform data
 *
- * @handle_irq: an optional handler which will be called from the interrupt and
+ * @handle_irq: an optional handler which will be called from the
- * passed the address of the low level handler, and can be used to implement
+ *      interrupt and passed the address of the low level handler,
- * any platform specific handling before or after calling it.
+ *      and can be used to implement any platform specific handling
+ *      before or after calling it.
+ * @enable_irq: an optional handler which will be called after
+ *      request_irq and be used to handle some platform specific
+ *      irq enablement
+ * @disable_irq: an optional handler which will be called before
+ *      free_irq and be used to handle some platform specific
+ *      irq disablement
 */
 struct arm_pmu_platdata {
        irqreturn_t (*handle_irq)(int irq, void *dev,
                                  irq_handler_t pmu_handler);
+        void (*enable_irq)(int irq);
+        void (*disable_irq)(int irq);
 };
 #ifdef CONFIG_CPU_HAS_PMU
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 9e92cb205e6..f3628fb3d2b 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -65,7 +65,11 @@ extern struct processor {
         * Set a possibly extended PTE.  Non-extended PTEs should
         * ignore 'ext'.
         */
+#ifdef CONFIG_ARM_LPAE
+        void (*set_pte_ext)(pte_t *ptep, pte_t pte);
+#else
        void (*set_pte_ext)(pte_t *ptep, pte_t pte, unsigned int ext);
+#endif
        /* Suspend/resume */
        unsigned int suspend_size;
@@ -79,7 +83,11 @@ extern void cpu_proc_fin(void);
 extern int cpu_do_idle(void);
 extern void cpu_dcache_clean_area(void *, int);
 extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
+#ifdef CONFIG_ARM_LPAE
+extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
+#else
 extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
+#endif
 extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
 /* These three are private to arch/arm/kernel/suspend.c */
@@ -107,6 +115,18 @@ extern void cpu_resume(void);
 #define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
+#ifdef CONFIG_ARM_LPAE
+#define cpu_get_pgd()   \
+        ({                                              \
+                unsigned long pg, pg2;                  \
+                __asm__("mrrc   p15, 0, %0, %1, c2"     \
+                        : "=r" (pg), "=r" (pg2)         \
+                        :                               \
+                        : "cc");                        \
+                pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1);  \
+                (pgd_t *)phys_to_virt(pg);              \
+        })
+#else
 #define cpu_get_pgd()   \
        ({                                              \
                unsigned long pg;                       \
@@ -115,6 +135,7 @@ extern void cpu_resume(void);
                pg &= ~0x3fff;                          \
                (pgd_t *)phys_to_virt(pg);              \
        })
+#endif
 #endif
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index b2d9df5667a..ce280b8d613 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -123,6 +123,8 @@ static inline void prefetch(const void *ptr)
 #endif
+#define HAVE_ARCH_PICK_MMAP_LAYOUT
 #endif
 #endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h
index 6f65ca86a5e..ee036330791 100644
--- a/arch/arm/include/asm/prom.h
+++ b/arch/arm/include/asm/prom.h
@@ -13,7 +13,6 @@
 #ifdef CONFIG_OF
-#include <asm/setup.h>
 #include <asm/irq.h>
 extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 96187ff58c2..451808ba121 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -189,6 +189,11 @@ static inline int valid_user_regs(struct pt_regs *regs)
        return 0;
 }
+static inline long regs_return_value(struct pt_regs *regs)
+{
+        return regs->ARM_r0;
+}
 #define instruction_pointer(regs)       (regs)->ARM_pc
 #ifdef CONFIG_SMP
diff --git a/arch/arm/include/asm/sched_clock.h b/arch/arm/include/asm/sched_clock.h
index c8e6ddf3e86..e3f75726343 100644
--- a/arch/arm/include/asm/sched_clock.h
+++ b/arch/arm/include/asm/sched_clock.h
@@ -8,113 +8,7 @@
 #ifndef ASM_SCHED_CLOCK
 #define ASM_SCHED_CLOCK
-#include <linux/kernel.h>
-#include <linux/types.h>
-struct clock_data {
-        u64 epoch_ns;
-        u32 epoch_cyc;
-        u32 epoch_cyc_copy;
-        u32 mult;
-        u32 shift;
-};
-#define DEFINE_CLOCK_DATA(name) struct clock_data name
-static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
-{
-        return (cyc * mult) >> shift;
-}
-/*
- * Atomically update the sched_clock epoch.  Your update callback will
- * be called from a timer before the counter wraps - read the current
- * counter value, and call this function to safely move the epochs
- * forward.  Only use this from the update callback.
- */
-static inline void update_sched_clock(struct clock_data *cd, u32 cyc, u32 mask)
-{
-        unsigned long flags;
-        u64 ns = cd->epoch_ns +
-                cyc_to_ns((cyc - cd->epoch_cyc) & mask, cd->mult, cd->shift);
-        /*
-         * Write epoch_cyc and epoch_ns in a way that the update is
-         * detectable in cyc_to_fixed_sched_clock().
-         */
-        raw_local_irq_save(flags);
-        cd->epoch_cyc = cyc;
-        smp_wmb();
-        cd->epoch_ns = ns;
-        smp_wmb();
-        cd->epoch_cyc_copy = cyc;
-        raw_local_irq_restore(flags);
-}
-/*
- * If your clock rate is known at compile time, using this will allow
- * you to optimize the mult/shift loads away.  This is paired with
- * init_fixed_sched_clock() to ensure that your mult/shift are correct.
- */
-static inline unsigned long long cyc_to_fixed_sched_clock(struct clock_data *cd,
-        u32 cyc, u32 mask, u32 mult, u32 shift)
-{
-        u64 epoch_ns;
-        u32 epoch_cyc;
-        /*
-         * Load the epoch_cyc and epoch_ns atomically.  We do this by
-         * ensuring that we always write epoch_cyc, epoch_ns and
-         * epoch_cyc_copy in strict order, and read them in strict order.
-         * If epoch_cyc and epoch_cyc_copy are not equal, then we're in
-         * the middle of an update, and we should repeat the load.
-         */
-        do {
-                epoch_cyc = cd->epoch_cyc;
-                smp_rmb();
-                epoch_ns = cd->epoch_ns;
-                smp_rmb();
-        } while (epoch_cyc != cd->epoch_cyc_copy);
-        return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, mult, shift);
-}
-/*
- * Otherwise, you need to use this, which will obtain the mult/shift
- * from the clock_data structure.  Use init_sched_clock() with this.
- */
-static inline unsigned long long cyc_to_sched_clock(struct clock_data *cd,
-        u32 cyc, u32 mask)
-{
-        return cyc_to_fixed_sched_clock(cd, cyc, mask, cd->mult, cd->shift);
-}
-/*
- * Initialize the clock data - calculate the appropriate multiplier
- * and shift.  Also setup a timer to ensure that the epoch is refreshed
- * at the appropriate time interval, which will call your update
- * handler.
- */
-void init_sched_clock(struct clock_data *, void (*)(void),
-        unsigned int, unsigned long);
-/*
- * Use this initialization function rather than init_sched_clock() if
- * you're using cyc_to_fixed_sched_clock, which will warn if your
- * constants are incorrect.
- */
-static inline void init_fixed_sched_clock(struct clock_data *cd,
-        void (*update)(void), unsigned int bits, unsigned long rate,
-        u32 mult, u32 shift)
-{
-        init_sched_clock(cd, update, bits, rate);
-        if (cd->mult != mult || cd->shift != shift) {
-                pr_crit("sched_clock: wrong multiply/shift: %u>>%u vs calculated %u>>%u\n"
-                        "sched_clock: fix multiply/shift to avoid scheduler hiccups\n",
-                        mult, shift, cd->mult, cd->shift);
-        }
-}
 extern void sched_clock_postinit(void);
+extern void setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate);
 #endif
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 915696dd9c7..23ebc0c82a3 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -192,11 +192,7 @@ static const struct tagtable __tagtable_##fn __tag = { tag, fn }
 /*
 * Memory map description
 */
-#ifdef CONFIG_ARCH_EP93XX
+#define NR_BANKS        CONFIG_ARM_NR_BANKS
-# define NR_BANKS 16
-#else
-# define NR_BANKS 8
-#endif
 struct membank {
        phys_addr_t start;
diff --git a/arch/arm/include/asm/socket.h b/arch/arm/include/asm/socket.h
index 90ffd04b8e7..dec6f9afb3c 100644
--- a/arch/arm/include/asm/socket.h
+++ b/arch/arm/include/asm/socket.h
@@ -62,4 +62,7 @@
 #define SO_RXQ_OVFL             40
+#define SO_WIFI_STATUS          41
+#define SCM_WIFI_STATUS         SO_WIFI_STATUS
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/arm/include/asm/swab.h b/arch/arm/include/asm/swab.h
index 9997ad20eff..b859d82e30c 100644
--- a/arch/arm/include/asm/swab.h
+++ b/arch/arm/include/asm/swab.h
@@ -22,14 +22,16 @@
 #  define __SWAB_64_THRU_32__
 #endif
-#if defined(__KERNEL__) && __LINUX_ARM_ARCH__ >= 6
+#if defined(__KERNEL__)
+#if __LINUX_ARM_ARCH__ >= 6
-static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
+static inline __attribute_const__ __u32 __arch_swahb32(__u32 x)
 {
        __asm__ ("rev16 %0, %1" : "=r" (x) : "r" (x));
        return x;
 }
-#define __arch_swab16 __arch_swab16
+#define __arch_swahb32 __arch_swahb32
+#define __arch_swab16(x) ((__u16)__arch_swahb32(x))
 static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 {
@@ -38,8 +40,10 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 }
 #define __arch_swab32 __arch_swab32
-#else
+#endif
+#endif
+#if !defined(__KERNEL__) || __LINUX_ARM_ARCH__ < 6
 static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
 {
        __u32 t;
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 984014b9264..e4c96cc6ec0 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -80,6 +80,14 @@ struct siginfo;
 void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
                unsigned long err, unsigned long trap);
+#ifdef CONFIG_ARM_LPAE
+#define FAULT_CODE_ALIGNMENT    33
+#define FAULT_CODE_DEBUG        34
+#else
+#define FAULT_CODE_ALIGNMENT    1
+#define FAULT_CODE_DEBUG        2
+#endif
 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
                                       struct pt_regs *),
                     int sig, int code, const char *name);
@@ -100,7 +108,7 @@ extern void __show_regs(struct pt_regs *);
 extern int __pure cpu_architecture(void);
 extern void cpu_init(void);
-void arm_machine_restart(char mode, const char *cmd);
+void soft_restart(unsigned long);
 extern void (*arm_pm_restart)(char str, const char *cmd);
 #define UDBG_UNDEFINED  (1 << 0)
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 7b5cc8dae06..d4c24d412a8 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -129,6 +129,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
 /*
 * thread information flags:
 *  TIF_SYSCALL_TRACE   - syscall trace active
+ *  TIF_SYSCAL_AUDIT    - syscall auditing active
 *  TIF_SIGPENDING      - signal pending
 *  TIF_NEED_RESCHED    - rescheduling necessary
 *  TIF_NOTIFY_RESUME   - callback before returning to user
@@ -139,10 +140,10 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define TIF_NEED_RESCHED        1
 #define TIF_NOTIFY_RESUME       2       /* callback before returning to user */
 #define TIF_SYSCALL_TRACE       8
+#define TIF_SYSCALL_AUDIT       9
 #define TIF_POLLING_NRFLAG      16
 #define TIF_USING_IWMMXT        17
 #define TIF_MEMDIE              18      /* is terminating due to OOM killer */
-#define TIF_FREEZE              19
 #define TIF_RESTORE_SIGMASK     20
 #define TIF_SECCOMP             21
@@ -150,12 +151,15 @@ extern void vfp_flush_hwstate(struct thread_info *);
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
 #define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
+#define _TIF_SYSCALL_AUDIT      (1 << TIF_SYSCALL_AUDIT)
 #define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
 #define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
-#define _TIF_FREEZE             (1 << TIF_FREEZE)
 #define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
 #define _TIF_SECCOMP            (1 << TIF_SECCOMP)
+/* Checks for any syscall work in entry-common.S */
+#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
 /*
 * Change these and you break ASM code in entry-common.S
 */
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 265f908c4a6..5d3ed7e3856 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -202,8 +202,18 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
        tlb_remove_page(tlb, pte);
 }
+static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
+                                  unsigned long addr)
+{
+#ifdef CONFIG_ARM_LPAE
+        tlb_add_flush(tlb, addr);
+        tlb_remove_page(tlb, virt_to_page(pmdp));
+#endif
+}
 #define pte_free_tlb(tlb, ptep, addr)   __pte_free_tlb(tlb, ptep, addr)
-#define pmd_free_tlb(tlb, pmdp, addr)   pmd_free((tlb)->mm, pmdp)
+#define pmd_free_tlb(tlb, pmdp, addr)   __pmd_free_tlb(tlb, pmdp, addr)
+#define pud_free_tlb(tlb, pudp, addr)   pud_free((tlb)->mm, pudp)
 #define tlb_migrate_finish(mm)          do { } while (0)
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index 48192ac3a23..28beab917ff 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -3,12 +3,6 @@
 #include <asm-generic/int-ll64.h>
-#ifndef __ASSEMBLY__
-typedef unsigned short umode_t;
-#endif /* __ASSEMBLY__ */
 /*
 * These aren't exported outside the kernel to avoid name space clashes
 */
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
index bc631161e9c..f5989f46b4d 100644
--- a/arch/arm/include/asm/unified.h
+++ b/arch/arm/include/asm/unified.h
@@ -37,8 +37,8 @@
 #define THUMB(x...)     x
 #ifdef __ASSEMBLY__
 #define W(instr)        instr.w
-#endif
 #define BSYM(sym)       sym + 1
+#endif
 #else   /* !CONFIG_THUMB2_KERNEL */
@@ -49,8 +49,8 @@
 #define THUMB(x...)
 #ifdef __ASSEMBLY__
 #define W(instr)        instr
-#endif
 #define BSYM(sym)       sym
+#endif
 #endif  /* CONFIG_THUMB2_KERNEL */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 4a112378380..512cd147345 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -427,7 +427,8 @@
 /*
 * The following syscalls are obsolete and no longer available for EABI.
 */
-#if defined(__ARM_EABI__) && !defined(__KERNEL__)
+#if !defined(__KERNEL__)
+#if defined(__ARM_EABI__)
 #undef __NR_time
 #undef __NR_umount
 #undef __NR_stime
@@ -441,6 +442,7 @@
 #undef __NR_syscall
 #undef __NR_ipc
 #endif
+#endif
 #ifdef __KERNEL__
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 16eed6aebfa..43b740d0e37 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -13,7 +13,7 @@ CFLAGS_REMOVE_return_address.o = -pg
 # Object file lists.
-obj-y           := elf.o entry-armv.o entry-common.o irq.o \
+obj-y           := elf.o entry-armv.o entry-common.o irq.o opcodes.o \
                   process.o ptrace.o return_address.o setup.o signal.o \
                   sys_arm.o stacktrace.o time.o traps.o
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index b530e9116a0..f58ba358990 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -316,21 +316,6 @@ pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
        }
 }
-static void __devinit
-pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root)
-{
-        struct pci_dev *dev = bus->self;
-        int i;
-        if (!dev) {
-                /*
-                 * Assign root bus resources.
-                 */
-                for (i = 0; i < 3; i++)
-                        bus->resource[i] = root->resource[i];
-        }
-}
 /*
 * pcibios_fixup_bus - Called after each bus is probed,
 * but before its children are examined.
@@ -341,8 +326,6 @@ void pcibios_fixup_bus(struct pci_bus *bus)
        struct pci_dev *dev;
        u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
-        pbus_assign_bus_resources(bus, root);
        /*
         * Walk the devices on this bus, working out what we can
         * and can't support.
@@ -508,12 +491,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
                sys->busnr   = busnr;
                sys->swizzle = hw->swizzle;
                sys->map_irq = hw->map_irq;
-                sys->resource[0] = &ioport_resource;
+                INIT_LIST_HEAD(&sys->resources);
-                sys->resource[1] = &iomem_resource;
                ret = hw->setup(nr, sys);
                if (ret > 0) {
+                        if (list_empty(&sys->resources)) {
+                                pci_add_resource(&sys->resources,
+                                                 &ioport_resource);
+                                pci_add_resource(&sys->resources,
+                                                 &iomem_resource);
+                        }
                        sys->bus = hw->scan(nr, sys);
                        if (!sys->bus)
@@ -571,6 +560,13 @@ void __init pci_common_init(struct hw_pci *hw)
        }
 }
+#ifndef CONFIG_PCI_HOST_ITE8152
+void pcibios_set_master(struct pci_dev *dev)
+{
+        /* No special bus mastering setup handling */
+}
+#endif
 char * __init pcibios_setup(char *str)
 {
        if (!strcmp(str, "debug")) {
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index b145f16c91b..3a456c6c700 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -36,12 +36,11 @@
 #ifdef CONFIG_MULTI_IRQ_HANDLER
        ldr     r1, =handle_arch_irq
        mov     r0, sp
-        ldr     r1, [r1]
        adr     lr, BSYM(9997f)
-        teq     r1, #0
+        ldr     pc, [r1]
-        movne   pc, r1
+#else
-#endif
        arch_irq_handler_default
+#endif
 9997:
        .endm
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index b2a27b6b004..520889cf1b5 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -87,7 +87,7 @@ ENTRY(ret_from_fork)
        get_thread_info tsk
        ldr     r1, [tsk, #TI_FLAGS]            @ check for syscall tracing
        mov     why, #1
-        tst     r1, #_TIF_SYSCALL_TRACE         @ are we tracing syscalls?
+        tst     r1, #_TIF_SYSCALL_WORK          @ are we tracing syscalls?
        beq     ret_slow_syscall
        mov     r1, sp
        mov     r0, #1                          @ trace exit [IP = 1]
@@ -443,7 +443,7 @@ ENTRY(vector_swi)
 1:
 #endif
-        tst     r10, #_TIF_SYSCALL_TRACE                @ are we tracing syscalls?
+        tst     r10, #_TIF_SYSCALL_WORK         @ are we tracing syscalls?
        bne     __sys_trace
        cmp     scno, #NR_syscalls              @ check upper syscall limit
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 08c82fd844a..6d579114406 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -39,8 +39,14 @@
 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
 #endif
+#ifdef CONFIG_ARM_LPAE
+        /* LPAE requires an additional page for the PGD */
+#define PG_DIR_SIZE     0x5000
+#define PMD_ORDER       3
+#else
 #define PG_DIR_SIZE     0x4000
 #define PMD_ORDER       2
+#endif
        .globl  swapper_pg_dir
        .equ    swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
@@ -93,6 +99,14 @@ ENTRY(stext)
 THUMB( it      eq )            @ force fixup-able long branch encoding
        beq     __error_p                       @ yes, error 'p'
+#ifdef CONFIG_ARM_LPAE
+        mrc     p15, 0, r3, c0, c1, 4           @ read ID_MMFR0
+        and     r3, r3, #0xf                    @ extract VMSA support
+        cmp     r3, #5                          @ long-descriptor translation table format?
+ THUMB( it      lo )                            @ force fixup-able long branch encoding
+        blo     __error_p                       @ only classic page table format
+#endif
 #ifndef CONFIG_XIP_KERNEL
        adr     r3, 2f
        ldmia   r3, {r4, r8}
@@ -164,17 +178,36 @@ __create_page_tables:
        teq     r0, r6
        bne     1b
+#ifdef CONFIG_ARM_LPAE
+        /*
+         * Build the PGD table (first level) to point to the PMD table. A PGD
+         * entry is 64-bit wide.
+         */
+        mov     r0, r4
+        add     r3, r4, #0x1000                 @ first PMD table address
+        orr     r3, r3, #3                      @ PGD block type
+        mov     r6, #4                          @ PTRS_PER_PGD
+        mov     r7, #1 << (55 - 32)             @ L_PGD_SWAPPER
+1:      str     r3, [r0], #4                    @ set bottom PGD entry bits
+        str     r7, [r0], #4                    @ set top PGD entry bits
+        add     r3, r3, #0x1000                 @ next PMD table
+        subs    r6, r6, #1
+        bne     1b
+        add     r4, r4, #0x1000                 @ point to the PMD tables
+#endif
        ldr     r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
        /*
         * Create identity mapping to cater for __enable_mmu.
         * This identity mapping will be removed by paging_init().
         */
-        adr     r0, __enable_mmu_loc
+        adr     r0, __turn_mmu_on_loc
        ldmia   r0, {r3, r5, r6}
        sub     r0, r0, r3                      @ virt->phys offset
-        add     r5, r5, r0                      @ phys __enable_mmu
+        add     r5, r5, r0                      @ phys __turn_mmu_on
-        add     r6, r6, r0                      @ phys __enable_mmu_end
+        add     r6, r6, r0                      @ phys __turn_mmu_on_end
        mov     r5, r5, lsr #SECTION_SHIFT
        mov     r6, r6, lsr #SECTION_SHIFT
@@ -219,8 +252,8 @@ __create_page_tables:
 #endif
        /*
-         * Then map boot params address in r2 or
+         * Then map boot params address in r2 or the first 1MB (2MB with LPAE)
-         * the first 1MB of ram if boot params address is not specified.
+         * of ram if boot params address is not specified.
         */
        mov     r0, r2, lsr #SECTION_SHIFT
        movs    r0, r0, lsl #SECTION_SHIFT
@@ -251,7 +284,15 @@ __create_page_tables:
        mov     r3, r7, lsr #SECTION_SHIFT
        ldr     r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
        orr     r3, r7, r3, lsl #SECTION_SHIFT
+#ifdef CONFIG_ARM_LPAE
+        mov     r7, #1 << (54 - 32)             @ XN
+#else
+        orr     r3, r3, #PMD_SECT_XN
+#endif
 1:      str     r3, [r0], #4
+#ifdef CONFIG_ARM_LPAE
+        str     r7, [r0], #4
+#endif
        add     r3, r3, #1 << SECTION_SHIFT
        cmp     r0, r6
        blo     1b
@@ -283,14 +324,17 @@ __create_page_tables:
        str     r3, [r0]
 #endif
 #endif
+#ifdef CONFIG_ARM_LPAE
+        sub     r4, r4, #0x1000         @ point to the PGD table
+#endif
        mov     pc, lr
 ENDPROC(__create_page_tables)
        .ltorg
        .align
-__enable_mmu_loc:
+__turn_mmu_on_loc:
        .long   .
-        .long   __enable_mmu
+        .long   __turn_mmu_on
-        .long   __enable_mmu_end
+        .long   __turn_mmu_on_end
 #if defined(CONFIG_SMP)
        __CPUINIT
@@ -374,12 +418,17 @@ __enable_mmu:
 #ifdef CONFIG_CPU_ICACHE_DISABLE
        bic     r0, r0, #CR_I
 #endif
+#ifdef CONFIG_ARM_LPAE
+        mov     r5, #0
+        mcrr    p15, 0, r4, r5, c2              @ load TTBR0
+#else
        mov     r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
                      domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
                      domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
                      domain_val(DOMAIN_IO, DOMAIN_CLIENT))
        mcr     p15, 0, r5, c3, c0, 0           @ load domain access register
        mcr     p15, 0, r4, c2, c0, 0           @ load page table pointer
+#endif
        b       __turn_mmu_on
 ENDPROC(__enable_mmu)
@@ -398,15 +447,19 @@ ENDPROC(__enable_mmu)
 * other registers depend on the function called upon completion
 */
        .align  5
-__turn_mmu_on:
+        .pushsection    .idmap.text, "ax"
+ENTRY(__turn_mmu_on)
        mov     r0, r0
+        instr_sync
        mcr     p15, 0, r0, c1, c0, 0           @ write control reg
        mrc     p15, 0, r3, c0, c0, 0           @ read id reg
+        instr_sync
        mov     r3, r3
        mov     r3, r13
        mov     pc, r3
-__enable_mmu_end:
+__turn_mmu_on_end:
 ENDPROC(__turn_mmu_on)
+        .popsection
 #ifdef CONFIG_SMP_ON_UP
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 814a52a9dc3..d6a95ef9131 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -1016,10 +1016,10 @@ static int __init arch_hw_breakpoint_init(void)
        }
        /* Register debug fault handler. */
-        hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
+        hook_fault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
-                        "watchpoint debug exception");
+                        TRAP_HWBKPT, "watchpoint debug exception");
-        hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
+        hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
-                        "breakpoint debug exception");
+                        TRAP_HWBKPT, "breakpoint debug exception");
        /* Register hotplug notifier. */
        register_cpu_notifier(&dbg_reset_nb);
diff --git a/arch/arm/kernel/kprobes-test.c b/arch/arm/kernel/kprobes-test.c
index e17cdd6d90d..1862d8f2fd4 100644
--- a/arch/arm/kernel/kprobes-test.c
+++ b/arch/arm/kernel/kprobes-test.c
@@ -202,6 +202,8 @@
 #include <linux/slab.h>
 #include <linux/kprobes.h>
+#include <asm/opcodes.h>
 #include "kprobes.h"
 #include "kprobes-test.h"
@@ -1050,65 +1052,9 @@ static int test_instance;
 static unsigned long test_check_cc(int cc, unsigned long cpsr)
 {
-        unsigned long temp;
+        int ret = arm_check_condition(cc << 28, cpsr);
-        switch (cc) {
-        case 0x0: /* eq */
-                return cpsr & PSR_Z_BIT;
-        case 0x1: /* ne */
-                return (~cpsr) & PSR_Z_BIT;
-        case 0x2: /* cs */
-                return cpsr & PSR_C_BIT;
-        case 0x3: /* cc */
-                return (~cpsr) & PSR_C_BIT;
-        case 0x4: /* mi */
-                return cpsr & PSR_N_BIT;
-        case 0x5: /* pl */
-                return (~cpsr) & PSR_N_BIT;
-        case 0x6: /* vs */
-                return cpsr & PSR_V_BIT;
-        case 0x7: /* vc */
-                return (~cpsr) & PSR_V_BIT;
-        case 0x8: /* hi */
+        return (ret != ARM_OPCODE_CONDTEST_FAIL);
-                cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
-                return cpsr & PSR_C_BIT;
-        case 0x9: /* ls */
-                cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
-                return (~cpsr) & PSR_C_BIT;
-        case 0xa: /* ge */
-                cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
-                return (~cpsr) & PSR_N_BIT;
-        case 0xb: /* lt */
-                cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
-                return cpsr & PSR_N_BIT;
-        case 0xc: /* gt */
-                temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
-                temp |= (cpsr << 1);       /* PSR_N_BIT |= PSR_Z_BIT */
-                return (~temp) & PSR_N_BIT;
-        case 0xd: /* le */
-                temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
-                temp |= (cpsr << 1);       /* PSR_N_BIT |= PSR_Z_BIT */
-                return temp & PSR_N_BIT;
-        case 0xe: /* al */
-        case 0xf: /* unconditional */
-                return true;
-        }
-        BUG();
-        return false;
 }
 static int is_last_scenario;
@@ -1128,7 +1074,9 @@ static unsigned long test_context_cpsr(int scenario)
        if (!test_case_is_thumb) {
                /* Testing ARM code */
-                probe_should_run = test_check_cc(current_instruction >> 28, cpsr) != 0;
+                int cc = current_instruction >> 28;
+                probe_should_run = test_check_cc(cc, cpsr) != 0;
                if (scenario == 15)
                        is_last_scenario = true;
diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c
index 0bcd3834157..1911dae19e4 100644
--- a/arch/arm/kernel/leds.c
+++ b/arch/arm/kernel/leds.c
@@ -9,7 +9,7 @@
 */
 #include <linux/export.h>
 #include <linux/init.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/string.h>
@@ -34,8 +34,8 @@ static const struct leds_evt_name evt_names[] = {
        { "red",   led_red_on,   led_red_off   },
 };
-static ssize_t leds_store(struct sys_device *dev,
+static ssize_t leds_store(struct device *dev,
-                        struct sysdev_attribute *attr,
+                        struct device_attribute *attr,
                        const char *buf, size_t size)
 {
        int ret = -EINVAL, len = strcspn(buf, " ");
@@ -69,15 +69,16 @@ static ssize_t leds_store(struct sys_device *dev,
        return ret;
 }
-static SYSDEV_ATTR(event, 0200, NULL, leds_store);
+static DEVICE_ATTR(event, 0200, NULL, leds_store);
-static struct sysdev_class leds_sysclass = {
+static struct bus_type leds_subsys = {
        .name           = "leds",
+        .dev_name       = "leds",
 };
-static struct sys_device leds_device = {
+static struct device leds_device = {
        .id             = 0,
-        .cls            = &leds_sysclass,
+        .bus            = &leds_subsys,
 };
 static int leds_suspend(void)
@@ -105,11 +106,11 @@ static struct syscore_ops leds_syscore_ops = {
 static int __init leds_init(void)
 {
        int ret;
-        ret = sysdev_class_register(&leds_sysclass);
+        ret = subsys_system_register(&leds_subsys, NULL);
        if (ret == 0)
-                ret = sysdev_register(&leds_device);
+                ret = device_register(&leds_device);
        if (ret == 0)
-                ret = sysdev_create_file(&leds_device, &attr_event);
+                ret = device_create_file(&leds_device, &dev_attr_event);
        if (ret == 0)
                register_syscore_ops(&leds_syscore_ops);
        return ret;
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index e59bbd496c3..764bd456d84 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -12,12 +12,11 @@
 #include <asm/mmu_context.h>
 #include <asm/cacheflush.h>
 #include <asm/mach-types.h>
+#include <asm/system.h>
 extern const unsigned char relocate_new_kernel[];
 extern const unsigned int relocate_new_kernel_size;
-extern void setup_mm_for_reboot(char mode);
 extern unsigned long kexec_start_address;
 extern unsigned long kexec_indirection_page;
 extern unsigned long kexec_mach_type;
@@ -111,14 +110,6 @@ void machine_kexec(struct kimage *image)
        if (kexec_reinit)
                kexec_reinit();
-        local_irq_disable();
-        local_fiq_disable();
+        soft_restart(reboot_code_buffer_phys);
-        setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
-        flush_cache_all();
-        outer_flush_all();
-        outer_disable();
-        cpu_proc_fin();
-        outer_inv_all();
-        flush_cache_all();
-        cpu_reset(reboot_code_buffer_phys);
 }
diff --git a/arch/arm/kernel/opcodes.c b/arch/arm/kernel/opcodes.c
new file mode 100644
index 00000000000..f8179c6a817
--- /dev/null
+++ b/arch/arm/kernel/opcodes.c
@@ -0,0 +1,72 @@
+/*
+ *  linux/arch/arm/kernel/opcodes.c
+ *
+ *  A32 condition code lookup feature moved from nwfpe/fpopcode.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <asm/opcodes.h>
+#define ARM_OPCODE_CONDITION_UNCOND 0xf
+/*
+ * condition code lookup table
+ * index into the table is test code: EQ, NE, ... LT, GT, AL, NV
+ *
+ * bit position in short is condition code: NZCV
+ */
+static const unsigned short cc_map[16] = {
+        0xF0F0,                 /* EQ == Z set            */
+        0x0F0F,                 /* NE                     */
+        0xCCCC,                 /* CS == C set            */
+        0x3333,                 /* CC                     */
+        0xFF00,                 /* MI == N set            */
+        0x00FF,                 /* PL                     */
+        0xAAAA,                 /* VS == V set            */
+        0x5555,                 /* VC                     */
+        0x0C0C,                 /* HI == C set && Z clear */
+        0xF3F3,                 /* LS == C clear || Z set */
+        0xAA55,                 /* GE == (N==V)           */
+        0x55AA,                 /* LT == (N!=V)           */
+        0x0A05,                 /* GT == (!Z && (N==V))   */
+        0xF5FA,                 /* LE == (Z || (N!=V))    */
+        0xFFFF,                 /* AL always              */
+        0                       /* NV                     */
+};
+/*
+ * Returns:
+ * ARM_OPCODE_CONDTEST_FAIL   - if condition fails
+ * ARM_OPCODE_CONDTEST_PASS   - if condition passes (including AL)
+ * ARM_OPCODE_CONDTEST_UNCOND - if NV condition, or separate unconditional
+ *                              opcode space from v5 onwards
+ *
+ * Code that tests whether a conditional instruction would pass its condition
+ * check should check that return value == ARM_OPCODE_CONDTEST_PASS.
+ *
+ * Code that tests if a condition means that the instruction would be executed
+ * (regardless of conditional or unconditional) should instead check that the
+ * return value != ARM_OPCODE_CONDTEST_FAIL.
+ */
+asmlinkage unsigned int arm_check_condition(u32 opcode, u32 psr)
+{
+        u32 cc_bits  = opcode >> 28;
+        u32 psr_cond = psr >> 28;
+        unsigned int ret;
+        if (cc_bits != ARM_OPCODE_CONDITION_UNCOND) {
+                if ((cc_map[cc_bits] >> (psr_cond)) & 1)
+                        ret = ARM_OPCODE_CONDTEST_PASS;
+                else
+                        ret = ARM_OPCODE_CONDTEST_FAIL;
+        } else {
+                ret = ARM_OPCODE_CONDTEST_UNCOND;
+        }
+        return ret;
+}
+EXPORT_SYMBOL_GPL(arm_check_condition);
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 88b0941ce51..5bb91bf3d47 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -59,8 +59,7 @@ armpmu_get_pmu_id(void)
 }
 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
-int
+int perf_num_counters(void)
-armpmu_get_max_events(void)
 {
        int max_events = 0;
@@ -69,12 +68,6 @@ armpmu_get_max_events(void)
        return max_events;
 }
-EXPORT_SYMBOL_GPL(armpmu_get_max_events);
-int perf_num_counters(void)
-{
-        return armpmu_get_max_events();
-}
 EXPORT_SYMBOL_GPL(perf_num_counters);
 #define HW_OP_UNSUPPORTED               0xFFFF
@@ -380,6 +373,8 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
 {
        int i, irq, irqs;
        struct platform_device *pmu_device = armpmu->plat_device;
+        struct arm_pmu_platdata *plat =
+                dev_get_platdata(&pmu_device->dev);
        irqs = min(pmu_device->num_resources, num_possible_cpus());
@@ -387,8 +382,11 @@ armpmu_release_hardware(struct arm_pmu *armpmu)
                if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
                        continue;
                irq = platform_get_irq(pmu_device, i);
-                if (irq >= 0)
+                if (irq >= 0) {
+                        if (plat && plat->disable_irq)
+                                plat->disable_irq(irq);
                        free_irq(irq, armpmu);
+                }
        }
        release_pmu(armpmu->type);
@@ -448,7 +446,8 @@ armpmu_reserve_hardware(struct arm_pmu *armpmu)
                                irq);
                        armpmu_release_hardware(armpmu);
                        return err;
-                }
+                } else if (plat && plat->enable_irq)
+                        plat->enable_irq(irq);
                cpumask_set_cpu(i, &armpmu->active_irqs);
        }
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index e63d8115c01..533be9930ec 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -65,13 +65,15 @@ enum armv6_counters {
 * accesses/misses in hardware.
 */
 static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV6_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV6_PERFCTR_INSTR_EXEC,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV6_PERFCTR_BR_EXEC,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV6_PERFCTR_BR_MISPREDICT,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV6_PERFCTR_LSU_FULL_STALL,
 };
 static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -218,13 +220,15 @@ enum armv6mpcore_perf_types {
 * accesses/misses in hardware.
 */
 static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV6MPCORE_PERFCTR_BR_EXEC,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6MPCORE_PERFCTR_IBUF_STALL,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV6MPCORE_PERFCTR_LSU_FULL_STALL,
 };
 static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 1ef6d0034b8..460bbbb6b88 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -28,165 +28,87 @@ static struct arm_pmu armv7pmu;
 * they are not available.
 */
 enum armv7_perf_types {
-        ARMV7_PERFCTR_PMNC_SW_INCR              = 0x00,
+        ARMV7_PERFCTR_PMNC_SW_INCR                      = 0x00,
-        ARMV7_PERFCTR_IFETCH_MISS               = 0x01,
+        ARMV7_PERFCTR_L1_ICACHE_REFILL                  = 0x01,
-        ARMV7_PERFCTR_ITLB_MISS                 = 0x02,
+        ARMV7_PERFCTR_ITLB_REFILL                       = 0x02,
-        ARMV7_PERFCTR_DCACHE_REFILL             = 0x03, /* L1 */
+        ARMV7_PERFCTR_L1_DCACHE_REFILL                  = 0x03,
-        ARMV7_PERFCTR_DCACHE_ACCESS             = 0x04, /* L1 */
+        ARMV7_PERFCTR_L1_DCACHE_ACCESS                  = 0x04,
-        ARMV7_PERFCTR_DTLB_REFILL               = 0x05,
+        ARMV7_PERFCTR_DTLB_REFILL                       = 0x05,
-        ARMV7_PERFCTR_DREAD                     = 0x06,
+        ARMV7_PERFCTR_MEM_READ                          = 0x06,
-        ARMV7_PERFCTR_DWRITE                    = 0x07,
+        ARMV7_PERFCTR_MEM_WRITE                         = 0x07,
-        ARMV7_PERFCTR_INSTR_EXECUTED            = 0x08,
+        ARMV7_PERFCTR_INSTR_EXECUTED                    = 0x08,
-        ARMV7_PERFCTR_EXC_TAKEN                 = 0x09,
+        ARMV7_PERFCTR_EXC_TAKEN                         = 0x09,
-        ARMV7_PERFCTR_EXC_EXECUTED              = 0x0A,
+        ARMV7_PERFCTR_EXC_EXECUTED                      = 0x0A,
-        ARMV7_PERFCTR_CID_WRITE                 = 0x0B,
+        ARMV7_PERFCTR_CID_WRITE                         = 0x0B,
-        /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
+        /*
+         * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
         * It counts:
-         *  - all branch instructions,
+         *  - all (taken) branch instructions,
         *  - instructions that explicitly write the PC,
         *  - exception generating instructions.
         */
-        ARMV7_PERFCTR_PC_WRITE                  = 0x0C,
+        ARMV7_PERFCTR_PC_WRITE                          = 0x0C,
-        ARMV7_PERFCTR_PC_IMM_BRANCH             = 0x0D,
+        ARMV7_PERFCTR_PC_IMM_BRANCH                     = 0x0D,
-        ARMV7_PERFCTR_PC_PROC_RETURN            = 0x0E,
+        ARMV7_PERFCTR_PC_PROC_RETURN                    = 0x0E,
-        ARMV7_PERFCTR_UNALIGNED_ACCESS          = 0x0F,
+        ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS              = 0x0F,
+        ARMV7_PERFCTR_PC_BRANCH_MIS_PRED                = 0x10,
+        ARMV7_PERFCTR_CLOCK_CYCLES                      = 0x11,
+        ARMV7_PERFCTR_PC_BRANCH_PRED                    = 0x12,
        /* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */
-        ARMV7_PERFCTR_PC_BRANCH_MIS_PRED        = 0x10,
+        ARMV7_PERFCTR_MEM_ACCESS                        = 0x13,
-        ARMV7_PERFCTR_CLOCK_CYCLES              = 0x11,
+        ARMV7_PERFCTR_L1_ICACHE_ACCESS                  = 0x14,
-        ARMV7_PERFCTR_PC_BRANCH_PRED            = 0x12,
+        ARMV7_PERFCTR_L1_DCACHE_WB                      = 0x15,
-        ARMV7_PERFCTR_MEM_ACCESS                = 0x13,
+        ARMV7_PERFCTR_L2_CACHE_ACCESS                   = 0x16,
-        ARMV7_PERFCTR_L1_ICACHE_ACCESS          = 0x14,
+        ARMV7_PERFCTR_L2_CACHE_REFILL                   = 0x17,
-        ARMV7_PERFCTR_L1_DCACHE_WB              = 0x15,
+        ARMV7_PERFCTR_L2_CACHE_WB                       = 0x18,
-        ARMV7_PERFCTR_L2_DCACHE_ACCESS          = 0x16,
+        ARMV7_PERFCTR_BUS_ACCESS                        = 0x19,
-        ARMV7_PERFCTR_L2_DCACHE_REFILL          = 0x17,
+        ARMV7_PERFCTR_MEM_ERROR                         = 0x1A,
-        ARMV7_PERFCTR_L2_DCACHE_WB              = 0x18,
+        ARMV7_PERFCTR_INSTR_SPEC                        = 0x1B,
-        ARMV7_PERFCTR_BUS_ACCESS                = 0x19,
+        ARMV7_PERFCTR_TTBR_WRITE                        = 0x1C,
-        ARMV7_PERFCTR_MEMORY_ERROR              = 0x1A,
+        ARMV7_PERFCTR_BUS_CYCLES                        = 0x1D,
-        ARMV7_PERFCTR_INSTR_SPEC                = 0x1B,
-        ARMV7_PERFCTR_TTBR_WRITE                = 0x1C,
+        ARMV7_PERFCTR_CPU_CYCLES                        = 0xFF
-        ARMV7_PERFCTR_BUS_CYCLES                = 0x1D,
-        ARMV7_PERFCTR_CPU_CYCLES                = 0xFF
 };
 /* ARMv7 Cortex-A8 specific event types */
 enum armv7_a8_perf_types {
-        ARMV7_PERFCTR_WRITE_BUFFER_FULL         = 0x40,
+        ARMV7_A8_PERFCTR_L2_CACHE_ACCESS                = 0x43,
-        ARMV7_PERFCTR_L2_STORE_MERGED           = 0x41,
+        ARMV7_A8_PERFCTR_L2_CACHE_REFILL                = 0x44,
-        ARMV7_PERFCTR_L2_STORE_BUFF             = 0x42,
+        ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS               = 0x50,
-        ARMV7_PERFCTR_L2_ACCESS                 = 0x43,
+        ARMV7_A8_PERFCTR_STALL_ISIDE                    = 0x56,
-        ARMV7_PERFCTR_L2_CACH_MISS              = 0x44,
-        ARMV7_PERFCTR_AXI_READ_CYCLES           = 0x45,
-        ARMV7_PERFCTR_AXI_WRITE_CYCLES          = 0x46,
-        ARMV7_PERFCTR_MEMORY_REPLAY             = 0x47,
-        ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY   = 0x48,
-        ARMV7_PERFCTR_L1_DATA_MISS              = 0x49,
-        ARMV7_PERFCTR_L1_INST_MISS              = 0x4A,
-        ARMV7_PERFCTR_L1_DATA_COLORING          = 0x4B,
-        ARMV7_PERFCTR_L1_NEON_DATA              = 0x4C,
-        ARMV7_PERFCTR_L1_NEON_CACH_DATA         = 0x4D,
-        ARMV7_PERFCTR_L2_NEON                   = 0x4E,
-        ARMV7_PERFCTR_L2_NEON_HIT               = 0x4F,
-        ARMV7_PERFCTR_L1_INST                   = 0x50,
-        ARMV7_PERFCTR_PC_RETURN_MIS_PRED        = 0x51,
-        ARMV7_PERFCTR_PC_BRANCH_FAILED          = 0x52,
-        ARMV7_PERFCTR_PC_BRANCH_TAKEN           = 0x53,
-        ARMV7_PERFCTR_PC_BRANCH_EXECUTED        = 0x54,
-        ARMV7_PERFCTR_OP_EXECUTED               = 0x55,
-        ARMV7_PERFCTR_CYCLES_INST_STALL         = 0x56,
-        ARMV7_PERFCTR_CYCLES_INST               = 0x57,
-        ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL    = 0x58,
-        ARMV7_PERFCTR_CYCLES_NEON_INST_STALL    = 0x59,
-        ARMV7_PERFCTR_NEON_CYCLES               = 0x5A,
-        ARMV7_PERFCTR_PMU0_EVENTS               = 0x70,
-        ARMV7_PERFCTR_PMU1_EVENTS               = 0x71,
-        ARMV7_PERFCTR_PMU_EVENTS                = 0x72,
 };
 /* ARMv7 Cortex-A9 specific event types */
 enum armv7_a9_perf_types {
-        ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC     = 0x40,
+        ARMV7_A9_PERFCTR_INSTR_CORE_RENAME              = 0x68,
-        ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC     = 0x41,
+        ARMV7_A9_PERFCTR_STALL_ICACHE                   = 0x60,
-        ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC       = 0x42,
+        ARMV7_A9_PERFCTR_STALL_DISPATCH                 = 0x66,
-        ARMV7_PERFCTR_COHERENT_LINE_MISS        = 0x50,
-        ARMV7_PERFCTR_COHERENT_LINE_HIT         = 0x51,
-        ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES   = 0x60,
-        ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES   = 0x61,
-        ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
-        ARMV7_PERFCTR_STREX_EXECUTED_PASSED     = 0x63,
-        ARMV7_PERFCTR_STREX_EXECUTED_FAILED     = 0x64,
-        ARMV7_PERFCTR_DATA_EVICTION             = 0x65,
-        ARMV7_PERFCTR_ISSUE_STAGE_NO_INST       = 0x66,
-        ARMV7_PERFCTR_ISSUE_STAGE_EMPTY         = 0x67,
-        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE  = 0x68,
-        ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
-        ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST   = 0x70,
-        ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
-        ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST  = 0x72,
-        ARMV7_PERFCTR_FP_EXECUTED_INST          = 0x73,
-        ARMV7_PERFCTR_NEON_EXECUTED_INST        = 0x74,
-        ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
-        ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES  = 0x81,
-        ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
-        ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
-        ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
-        ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
-        ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES      = 0x86,
-        ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
-        ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
-        ARMV7_PERFCTR_ISB_INST                  = 0x90,
-        ARMV7_PERFCTR_DSB_INST                  = 0x91,
-        ARMV7_PERFCTR_DMB_INST                  = 0x92,
-        ARMV7_PERFCTR_EXT_INTERRUPTS            = 0x93,
-        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
-        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
-        ARMV7_PERFCTR_PLE_FIFO_FLUSH            = 0xA2,
-        ARMV7_PERFCTR_PLE_RQST_COMPLETED        = 0xA3,
-        ARMV7_PERFCTR_PLE_FIFO_OVERFLOW         = 0xA4,
-        ARMV7_PERFCTR_PLE_RQST_PROG             = 0xA5
 };
 /* ARMv7 Cortex-A5 specific event types */
 enum armv7_a5_perf_types {
-        ARMV7_PERFCTR_IRQ_TAKEN                 = 0x86,
+        ARMV7_A5_PERFCTR_PREFETCH_LINEFILL              = 0xc2,
-        ARMV7_PERFCTR_FIQ_TAKEN                 = 0x87,
+        ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP         = 0xc3,
-        ARMV7_PERFCTR_EXT_MEM_RQST              = 0xc0,
-        ARMV7_PERFCTR_NC_EXT_MEM_RQST           = 0xc1,
-        ARMV7_PERFCTR_PREFETCH_LINEFILL         = 0xc2,
-        ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP    = 0xc3,
-        ARMV7_PERFCTR_ENTER_READ_ALLOC          = 0xc4,
-        ARMV7_PERFCTR_READ_ALLOC                = 0xc5,
-        ARMV7_PERFCTR_STALL_SB_FULL             = 0xc9,
 };
 /* ARMv7 Cortex-A15 specific event types */
 enum armv7_a15_perf_types {
-        ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS     = 0x40,
+        ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ         = 0x40,
-        ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS    = 0x41,
+        ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE        = 0x41,
-        ARMV7_PERFCTR_L1_DCACHE_READ_REFILL     = 0x42,
+        ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ         = 0x42,
-        ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL    = 0x43,
+        ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE        = 0x43,
-        ARMV7_PERFCTR_L1_DTLB_READ_REFILL       = 0x4C,
+        ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ           = 0x4C,
-        ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL      = 0x4D,
+        ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE          = 0x4D,
-        ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS     = 0x50,
+        ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ          = 0x50,
-        ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS    = 0x51,
+        ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE         = 0x51,
-        ARMV7_PERFCTR_L2_DCACHE_READ_REFILL     = 0x52,
+        ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ          = 0x52,
-        ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL    = 0x53,
+        ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE         = 0x53,
-        ARMV7_PERFCTR_SPEC_PC_WRITE             = 0x76,
+        ARMV7_A15_PERFCTR_PC_WRITE_SPEC                 = 0x76,
 };
 /*
@@ -197,13 +119,15 @@ enum armv7_a15_perf_types {
 * accesses/misses in hardware.
 */
 static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_PERFCTR_INSTR_EXECUTED,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_PERFCTR_PC_WRITE,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 };
 static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -217,12 +141,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                 * combined.
                 */
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -231,12 +155,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(L1I)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -245,12 +169,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(LL)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -274,11 +198,11 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(ITLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -287,14 +211,12 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(BPU)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -321,14 +243,15 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 * Cortex-A9 HW events mapping
 */
 static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        =
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME,
-                                        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_DCACHE_ACCESS,
+        [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-        [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_DCACHE_REFILL,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_PERFCTR_PC_WRITE,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV7_A9_PERFCTR_STALL_DISPATCH,
 };
 static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -342,12 +265,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                 * combined.
                 */
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -357,11 +280,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(L1I)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -399,11 +322,11 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(ITLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -412,14 +335,12 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(BPU)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -446,13 +367,15 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 * Cortex-A5 HW events mapping
 */
 static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_PERFCTR_INSTR_EXECUTED,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_PERFCTR_PC_WRITE,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 };
 static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -460,42 +383,34 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
        [C(L1D)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                                        = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_DCACHE_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-                                        = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_DCACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
-                                        = ARMV7_PERFCTR_PREFETCH_LINEFILL,
+                        [C(RESULT_MISS)]        = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
                },
        },
        [C(L1I)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                /*
                 * The prefetch counters don't differentiate between the I
                 * side and the D side.
                 */
                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL,
-                                        = ARMV7_PERFCTR_PREFETCH_LINEFILL,
+                        [C(RESULT_MISS)]        = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PREFETCH_LINEFILL_DROP,
                },
        },
        [C(LL)] = {
@@ -529,11 +444,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(ITLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -543,13 +458,11 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(BPU)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -562,13 +475,15 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 * Cortex-A15 HW events mapping
 */
 static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_CPU_CYCLES]              = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV7_PERFCTR_INSTR_EXECUTED,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = ARMV7_PERFCTR_L1_DCACHE_REFILL,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_SPEC_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV7_A15_PERFCTR_PC_WRITE_SPEC,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_BUS_CYCLES,
+        [PERF_COUNT_HW_BUS_CYCLES]              = ARMV7_PERFCTR_BUS_CYCLES,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 };
 static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
@@ -576,16 +491,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
        [C(L1D)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ,
-                                        = ARMV7_PERFCTR_L1_DCACHE_READ_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_L1_DCACHE_READ_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE,
-                                        = ARMV7_PERFCTR_L1_DCACHE_WRITE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_L1_DCACHE_WRITE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -601,11 +512,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                 */
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_ICACHE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -614,16 +525,12 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        },
        [C(LL)] = {
                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
-                                        = ARMV7_PERFCTR_L2_DCACHE_READ_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_L2_DCACHE_READ_REFILL,
                },
                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]
+                        [C(RESULT_ACCESS)]      = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
-                                        = ARMV7_PERFCTR_L2_DCACHE_WRITE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_L2_DCACHE_WRITE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -633,13 +540,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(DTLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ,
-                                        = ARMV7_PERFCTR_L1_DTLB_READ_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE,
-                                        = ARMV7_PERFCTR_L1_DTLB_WRITE_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -649,11 +554,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(ITLB)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_REFILL,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
@@ -663,13 +568,11 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
        [C(BPU)] = {
                [C(OP_READ)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_WRITE)] = {
                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_BRANCH_PRED,
-                        [C(RESULT_MISS)]
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
                },
                [C(OP_PREFETCH)] = {
                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index e0cca10a841..3b99d826982 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -48,13 +48,15 @@ enum xscale_counters {
 };
 static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = XSCALE_PERFCTR_CCNT,
+        [PERF_COUNT_HW_CPU_CYCLES]              = XSCALE_PERFCTR_CCNT,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = XSCALE_PERFCTR_INSTRUCTION,
+        [PERF_COUNT_HW_INSTRUCTIONS]            = XSCALE_PERFCTR_INSTRUCTION,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]            = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = XSCALE_PERFCTR_BRANCH,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = XSCALE_PERFCTR_BRANCH_MISS,
+        [PERF_COUNT_HW_BRANCH_MISSES]           = XSCALE_PERFCTR_BRANCH_MISS,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BUS_CYCLES]              = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER,
+        [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = HW_OP_UNSUPPORTED,
 };
 static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 3d0c6fb74ae..971d65c253a 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -57,7 +57,7 @@ static const char *isa_modes[] = {
  "ARM" , "Thumb" , "Jazelle", "ThumbEE"
 };
-extern void setup_mm_for_reboot(char mode);
+extern void setup_mm_for_reboot(void);
 static volatile int hlt_counter;
@@ -92,18 +92,24 @@ static int __init hlt_setup(char *__unused)
 __setup("nohlt", nohlt_setup);
 __setup("hlt", hlt_setup);
-void arm_machine_restart(char mode, const char *cmd)
+extern void call_with_stack(void (*fn)(void *), void *arg, void *sp);
+typedef void (*phys_reset_t)(unsigned long);
+/*
+ * A temporary stack to use for CPU reset. This is static so that we
+ * don't clobber it with the identity mapping. When running with this
+ * stack, any references to the current task *will not work* so you
+ * should really do as little as possible before jumping to your reset
+ * code.
+ */
+static u64 soft_restart_stack[16];
+static void __soft_restart(void *addr)
 {
-        /* Disable interrupts first */
+        phys_reset_t phys_reset;
-        local_irq_disable();
-        local_fiq_disable();
-        /*
+        /* Take out a flat memory mapping. */
-         * Tell the mm system that we are going to reboot -
+        setup_mm_for_reboot();
-         * we may need it to insert some 1:1 mappings so that
-         * soft boot works.
-         */
-        setup_mm_for_reboot(mode);
        /* Clean and invalidate caches */
        flush_cache_all();
@@ -114,18 +120,35 @@ void arm_machine_restart(char mode, const char *cmd)
        /* Push out any further dirty data, and ensure cache is empty */
        flush_cache_all();
-        /*
+        /* Switch to the identity mapping. */
-         * Now call the architecture specific reboot code.
+        phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
-         */
+        phys_reset((unsigned long)addr);
-        arch_reset(mode, cmd);
-        /*
+        /* Should never get here. */
-         * Whoops - the architecture was unable to reboot.
+        BUG();
-         * Tell the user!
+}
-         */
-        mdelay(1000);
+void soft_restart(unsigned long addr)
-        printk("Reboot failed -- System halted\n");
+{
-        while (1);
+        u64 *stack = soft_restart_stack + ARRAY_SIZE(soft_restart_stack);
+        /* Disable interrupts first */
+        local_irq_disable();
+        local_fiq_disable();
+        /* Disable the L2 if we're the last man standing. */
+        if (num_online_cpus() == 1)
+                outer_disable();
+        /* Change to the new stack and continue with the reset. */
+        call_with_stack(__soft_restart, (void *)addr, (void *)stack);
+        /* Should never get here. */
+        BUG();
+}
+static void null_restart(char mode, const char *cmd)
+{
 }
 /*
@@ -134,7 +157,7 @@ void arm_machine_restart(char mode, const char *cmd)
 void (*pm_power_off)(void);
 EXPORT_SYMBOL(pm_power_off);
-void (*arm_pm_restart)(char str, const char *cmd) = arm_machine_restart;
+void (*arm_pm_restart)(char str, const char *cmd) = null_restart;
 EXPORT_SYMBOL_GPL(arm_pm_restart);
 static void do_nothing(void *unused)
@@ -183,7 +206,8 @@ void cpu_idle(void)
        /* endless idle loop with no priority at all */
        while (1) {
-                tick_nohz_stop_sched_tick(1);
+                tick_nohz_idle_enter();
+                rcu_idle_enter();
                leds_event(led_idle_start);
                while (!need_resched()) {
 #ifdef CONFIG_HOTPLUG_CPU
@@ -213,7 +237,8 @@ void cpu_idle(void)
                        }
                }
                leds_event(led_idle_end);
-                tick_nohz_restart_sched_tick();
+                rcu_idle_exit();
+                tick_nohz_idle_exit();
                preempt_enable_no_resched();
                schedule();
                preempt_disable();
@@ -253,7 +278,15 @@ void machine_power_off(void)
 void machine_restart(char *cmd)
 {
        machine_shutdown();
        arm_pm_restart(reboot_mode, cmd);
+        /* Give a grace period for failure to restart of 1s */
+        mdelay(1000);
+        /* Whoops - the platform was unable to reboot. Tell the user! */
+        printk("Reboot failed -- System halted\n");
+        while (1);
 }
 void __show_regs(struct pt_regs *regs)
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 483727ad689..e1d5e1929fb 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -906,11 +906,6 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
 {
        unsigned long ip;
-        if (!test_thread_flag(TIF_SYSCALL_TRACE))
-                return scno;
-        if (!(current->ptrace & PT_PTRACED))
-                return scno;
        /*
         * Save IP.  IP is used to denote syscall entry/exit:
         *  IP = 0 -> entry, = 1 -> exit
@@ -918,6 +913,17 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
        ip = regs->ARM_ip;
        regs->ARM_ip = why;
+        if (!ip)
+                audit_syscall_exit(regs);
+        else
+                audit_syscall_entry(AUDIT_ARCH_ARMEB, scno, regs->ARM_r0,
+                                    regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
+        if (!test_thread_flag(TIF_SYSCALL_TRACE))
+                return scno;
+        if (!(current->ptrace & PT_PTRACED))
+                return scno;
        current_thread_info()->syscall = scno;
        /* the 0x80 provides a way for the tracing parent to distinguish
diff --git a/arch/arm/kernel/sched_clock.c b/arch/arm/kernel/sched_clock.c
index 9a46370fe9d..5416c7c1252 100644
--- a/arch/arm/kernel/sched_clock.c
+++ b/arch/arm/kernel/sched_clock.c
@@ -14,61 +14,153 @@
 #include <asm/sched_clock.h>
+struct clock_data {
+        u64 epoch_ns;
+        u32 epoch_cyc;
+        u32 epoch_cyc_copy;
+        u32 mult;
+        u32 shift;
+};
 static void sched_clock_poll(unsigned long wrap_ticks);
 static DEFINE_TIMER(sched_clock_timer, sched_clock_poll, 0, 0);
-static void (*sched_clock_update_fn)(void);
+static struct clock_data cd = {
+        .mult   = NSEC_PER_SEC / HZ,
+};
+static u32 __read_mostly sched_clock_mask = 0xffffffff;
+static u32 notrace jiffy_sched_clock_read(void)
+{
+        return (u32)(jiffies - INITIAL_JIFFIES);
+}
+static u32 __read_mostly (*read_sched_clock)(void) = jiffy_sched_clock_read;
+static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
+{
+        return (cyc * mult) >> shift;
+}
+static unsigned long long cyc_to_sched_clock(u32 cyc, u32 mask)
+{
+        u64 epoch_ns;
+        u32 epoch_cyc;
+        /*
+         * Load the epoch_cyc and epoch_ns atomically.  We do this by
+         * ensuring that we always write epoch_cyc, epoch_ns and
+         * epoch_cyc_copy in strict order, and read them in strict order.
+         * If epoch_cyc and epoch_cyc_copy are not equal, then we're in
+         * the middle of an update, and we should repeat the load.
+         */
+        do {
+                epoch_cyc = cd.epoch_cyc;
+                smp_rmb();
+                epoch_ns = cd.epoch_ns;
+                smp_rmb();
+        } while (epoch_cyc != cd.epoch_cyc_copy);
+        return epoch_ns + cyc_to_ns((cyc - epoch_cyc) & mask, cd.mult, cd.shift);
+}
+/*
+ * Atomically update the sched_clock epoch.
+ */
+static void notrace update_sched_clock(void)
+{
+        unsigned long flags;
+        u32 cyc;
+        u64 ns;
+        cyc = read_sched_clock();
+        ns = cd.epoch_ns +
+                cyc_to_ns((cyc - cd.epoch_cyc) & sched_clock_mask,
+                          cd.mult, cd.shift);
+        /*
+         * Write epoch_cyc and epoch_ns in a way that the update is
+         * detectable in cyc_to_fixed_sched_clock().
+         */
+        raw_local_irq_save(flags);
+        cd.epoch_cyc = cyc;
+        smp_wmb();
+        cd.epoch_ns = ns;
+        smp_wmb();
+        cd.epoch_cyc_copy = cyc;
+        raw_local_irq_restore(flags);
+}
 static void sched_clock_poll(unsigned long wrap_ticks)
 {
        mod_timer(&sched_clock_timer, round_jiffies(jiffies + wrap_ticks));
-        sched_clock_update_fn();
+        update_sched_clock();
 }
-void __init init_sched_clock(struct clock_data *cd, void (*update)(void),
+void __init setup_sched_clock(u32 (*read)(void), int bits, unsigned long rate)
-        unsigned int clock_bits, unsigned long rate)
 {
        unsigned long r, w;
        u64 res, wrap;
        char r_unit;
-        sched_clock_update_fn = update;
+        BUG_ON(bits > 32);
+        WARN_ON(!irqs_disabled());
+        WARN_ON(read_sched_clock != jiffy_sched_clock_read);
+        read_sched_clock = read;
+        sched_clock_mask = (1 << bits) - 1;
        /* calculate the mult/shift to convert counter ticks to ns. */
-        clocks_calc_mult_shift(&cd->mult, &cd->shift, rate, NSEC_PER_SEC, 0);
+        clocks_calc_mult_shift(&cd.mult, &cd.shift, rate, NSEC_PER_SEC, 0);
        r = rate;
        if (r >= 4000000) {
                r /= 1000000;
                r_unit = 'M';
-        } else {
+        } else if (r >= 1000) {
                r /= 1000;
                r_unit = 'k';
-        }
+        } else
+                r_unit = ' ';
        /* calculate how many ns until we wrap */
-        wrap = cyc_to_ns((1ULL << clock_bits) - 1, cd->mult, cd->shift);
+        wrap = cyc_to_ns((1ULL << bits) - 1, cd.mult, cd.shift);
        do_div(wrap, NSEC_PER_MSEC);
        w = wrap;
        /* calculate the ns resolution of this counter */
-        res = cyc_to_ns(1ULL, cd->mult, cd->shift);
+        res = cyc_to_ns(1ULL, cd.mult, cd.shift);
        pr_info("sched_clock: %u bits at %lu%cHz, resolution %lluns, wraps every %lums\n",
-                clock_bits, r, r_unit, res, w);
+                bits, r, r_unit, res, w);
        /*
         * Start the timer to keep sched_clock() properly updated and
         * sets the initial epoch.
         */
        sched_clock_timer.data = msecs_to_jiffies(w - (w / 10));
-        update();
+        update_sched_clock();
        /*
         * Ensure that sched_clock() starts off at 0ns
         */
-        cd->epoch_ns = 0;
+        cd.epoch_ns = 0;
+        pr_debug("Registered %pF as sched_clock source\n", read);
+}
+unsigned long long notrace sched_clock(void)
+{
+        u32 cyc = read_sched_clock();
+        return cyc_to_sched_clock(cyc, sched_clock_mask);
 }
 void __init sched_clock_postinit(void)
 {
+        /*
+         * If no sched_clock function has been provided at that point,
+         * make it the final one one.
+         */
+        if (read_sched_clock == jiffy_sched_clock_read)
+                setup_sched_clock(jiffy_sched_clock_read, 32, HZ);
        sched_clock_poll(sched_clock_timer.data);
 }
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 8fc2c8fcbdc..129fbd55bde 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -31,6 +31,7 @@
 #include <linux/memblock.h>
 #include <linux/bug.h>
 #include <linux/compiler.h>
+#include <linux/sort.h>
 #include <asm/unified.h>
 #include <asm/cpu.h>
@@ -52,6 +53,7 @@
 #include <asm/mach/time.h>
 #include <asm/traps.h>
 #include <asm/unwind.h>
+#include <asm/memblock.h>
 #if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 #include "compat.h"
@@ -890,6 +892,12 @@ static struct machine_desc * __init setup_machine_tags(unsigned int nr)
        return mdesc;
 }
+static int __init meminfo_cmp(const void *_a, const void *_b)
+{
+        const struct membank *a = _a, *b = _b;
+        long cmp = bank_pfn_start(a) - bank_pfn_start(b);
+        return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
+}
 void __init setup_arch(char **cmdline_p)
 {
@@ -908,8 +916,8 @@ void __init setup_arch(char **cmdline_p)
                arm_dma_zone_size = mdesc->dma_zone_size;
        }
 #endif
-        if (mdesc->soft_reboot)
+        if (mdesc->restart_mode)
-                reboot_setup("s");
+                reboot_setup(&mdesc->restart_mode);
        init_mm.start_code = (unsigned long) _text;
        init_mm.end_code   = (unsigned long) _etext;
@@ -922,12 +930,16 @@ void __init setup_arch(char **cmdline_p)
        parse_early_param();
+        sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
        sanity_check_meminfo();
        arm_memblock_init(&meminfo, mdesc);
        paging_init(mdesc);
        request_standard_resources(mdesc);
+        if (mdesc->restart)
+                arm_pm_restart = mdesc->restart;
        unflatten_device_tree();
 #ifdef CONFIG_SMP
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index 020e99c845e..1f268bda455 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -54,14 +54,18 @@ ENDPROC(cpu_suspend_abort)
 * r0 = control register value
 */
        .align  5
+        .pushsection    .idmap.text,"ax"
 ENTRY(cpu_resume_mmu)
        ldr     r3, =cpu_resume_after_mmu
+        instr_sync
        mcr     p15, 0, r0, c1, c0, 0   @ turn on MMU, I-cache, etc
        mrc     p15, 0, r0, c0, c0, 0   @ read id reg
+        instr_sync
        mov     r0, r0
        mov     r0, r0
        mov     pc, r3                  @ jump to virtual address
 ENDPROC(cpu_resume_mmu)
+        .popsection
 cpu_resume_after_mmu:
        bl      cpu_init                @ restore the und/abt/irq banked regs
        mov     r0, #0                  @ return zero on success
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ef5640b9e21..57db122a4f6 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -31,6 +31,7 @@
 #include <asm/cpu.h>
 #include <asm/cputype.h>
 #include <asm/exception.h>
+#include <asm/idmap.h>
 #include <asm/topology.h>
 #include <asm/mmu_context.h>
 #include <asm/pgtable.h>
@@ -61,7 +62,6 @@ int __cpuinit __cpu_up(unsigned int cpu)
 {
        struct cpuinfo_arm *ci = &per_cpu(cpu_data, cpu);
        struct task_struct *idle = ci->idle;
-        pgd_t *pgd;
        int ret;
        /*
@@ -84,29 +84,11 @@ int __cpuinit __cpu_up(unsigned int cpu)
        }
        /*
-         * Allocate initial page tables to allow the new CPU to
-         * enable the MMU safely.  This essentially means a set
-         * of our "standard" page tables, with the addition of
-         * a 1:1 mapping for the physical address of the kernel.
-         */
-        pgd = pgd_alloc(&init_mm);
-        if (!pgd)
-                return -ENOMEM;
-        if (PHYS_OFFSET != PAGE_OFFSET) {
-#ifndef CONFIG_HOTPLUG_CPU
-                identity_mapping_add(pgd, __pa(__init_begin), __pa(__init_end));
-#endif
-                identity_mapping_add(pgd, __pa(_stext), __pa(_etext));
-                identity_mapping_add(pgd, __pa(_sdata), __pa(_edata));
-        }
-        /*
         * We need to tell the secondary core where to find
         * its stack and the page tables.
         */
        secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
-        secondary_data.pgdir = virt_to_phys(pgd);
+        secondary_data.pgdir = virt_to_phys(idmap_pgd);
        secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
        __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
        outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
@@ -142,16 +124,6 @@ int __cpuinit __cpu_up(unsigned int cpu)
        secondary_data.stack = NULL;
        secondary_data.pgdir = 0;
-        if (PHYS_OFFSET != PAGE_OFFSET) {
-#ifndef CONFIG_HOTPLUG_CPU
-                identity_mapping_del(pgd, __pa(__init_begin), __pa(__init_end));
-#endif
-                identity_mapping_del(pgd, __pa(_stext), __pa(_etext));
-                identity_mapping_del(pgd, __pa(_sdata), __pa(_edata));
-        }
-        pgd_free(&init_mm, pgd);
        return ret;
 }
@@ -550,6 +522,10 @@ static void ipi_cpu_stop(unsigned int cpu)
        local_fiq_disable();
        local_irq_disable();
+#ifdef CONFIG_HOTPLUG_CPU
+        platform_cpu_kill(cpu);
+#endif
        while (1)
                cpu_relax();
 }
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index a8a6682d6b5..c8e938553d4 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -10,8 +10,11 @@
 */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
 #include <linux/delay.h>
 #include <linux/device.h>
+#include <linux/err.h>
 #include <linux/smp.h>
 #include <linux/jiffies.h>
 #include <linux/clockchips.h>
@@ -25,6 +28,7 @@
 /* set up by the platform code */
 void __iomem *twd_base;
+static struct clk *twd_clk;
 static unsigned long twd_timer_rate;
 static struct clock_event_device __percpu **twd_evt;
@@ -89,6 +93,52 @@ void twd_timer_stop(struct clock_event_device *clk)
        disable_percpu_irq(clk->irq);
 }
+#ifdef CONFIG_CPU_FREQ
+/*
+ * Updates clockevent frequency when the cpu frequency changes.
+ * Called on the cpu that is changing frequency with interrupts disabled.
+ */
+static void twd_update_frequency(void *data)
+{
+        twd_timer_rate = clk_get_rate(twd_clk);
+        clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate);
+}
+static int twd_cpufreq_transition(struct notifier_block *nb,
+        unsigned long state, void *data)
+{
+        struct cpufreq_freqs *freqs = data;
+        /*
+         * The twd clock events must be reprogrammed to account for the new
+         * frequency.  The timer is local to a cpu, so cross-call to the
+         * changing cpu.
+         */
+        if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
+                smp_call_function_single(freqs->cpu, twd_update_frequency,
+                        NULL, 1);
+        return NOTIFY_OK;
+}
+static struct notifier_block twd_cpufreq_nb = {
+        .notifier_call = twd_cpufreq_transition,
+};
+static int twd_cpufreq_init(void)
+{
+        if (!IS_ERR(twd_clk))
+                return cpufreq_register_notifier(&twd_cpufreq_nb,
+                        CPUFREQ_TRANSITION_NOTIFIER);
+        return 0;
+}
+core_initcall(twd_cpufreq_init);
+#endif
 static void __cpuinit twd_calibrate_rate(void)
 {
        unsigned long count;
@@ -140,6 +190,35 @@ static irqreturn_t twd_handler(int irq, void *dev_id)
        return IRQ_NONE;
 }
+static struct clk *twd_get_clock(void)
+{
+        struct clk *clk;
+        int err;
+        clk = clk_get_sys("smp_twd", NULL);
+        if (IS_ERR(clk)) {
+                pr_err("smp_twd: clock not found: %d\n", (int)PTR_ERR(clk));
+                return clk;
+        }
+        err = clk_prepare(clk);
+        if (err) {
+                pr_err("smp_twd: clock failed to prepare: %d\n", err);
+                clk_put(clk);
+                return ERR_PTR(err);
+        }
+        err = clk_enable(clk);
+        if (err) {
+                pr_err("smp_twd: clock failed to enable: %d\n", err);
+                clk_unprepare(clk);
+                clk_put(clk);
+                return ERR_PTR(err);
+        }
+        return clk;
+}
 /*
 * Setup the local clock events for a CPU.
 */
@@ -165,7 +244,13 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
                }
        }
-        twd_calibrate_rate();
+        if (!twd_clk)
+                twd_clk = twd_get_clock();
+        if (!IS_ERR_OR_NULL(twd_clk))
+                twd_timer_rate = clk_get_rate(twd_clk);
+        else
+                twd_calibrate_rate();
        clk->name = "local_timer";
        clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
@@ -173,15 +258,11 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
        clk->rating = 350;
        clk->set_mode = twd_set_mode;
        clk->set_next_event = twd_set_next_event;
-        clk->shift = 20;
-        clk->mult = div_sc(twd_timer_rate, NSEC_PER_SEC, clk->shift);
-        clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
-        clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
        this_cpu_clk = __this_cpu_ptr(twd_evt);
        *this_cpu_clk = clk;
-        clockevents_register_device(clk);
+        clockevents_config_and_register(clk, twd_timer_rate,
+                                        0xf, 0xffffffff);
        enable_percpu_irq(clk->irq, 0);
 }
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
index 93a22d282c1..1794cc3b0f1 100644
--- a/arch/arm/kernel/suspend.c
+++ b/arch/arm/kernel/suspend.c
@@ -1,13 +1,12 @@
 #include <linux/init.h>
+#include <asm/idmap.h>
 #include <asm/pgalloc.h>
 #include <asm/pgtable.h>
 #include <asm/memory.h>
 #include <asm/suspend.h>
 #include <asm/tlbflush.h>
-static pgd_t *suspend_pgd;
 extern int __cpu_suspend(unsigned long, int (*)(unsigned long));
 extern void cpu_resume_mmu(void);
@@ -21,7 +20,7 @@ void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
        *save_ptr = virt_to_phys(ptr);
        /* This must correspond to the LDM in cpu_resume() assembly */
-        *ptr++ = virt_to_phys(suspend_pgd);
+        *ptr++ = virt_to_phys(idmap_pgd);
        *ptr++ = sp;
        *ptr++ = virt_to_phys(cpu_do_resume);
@@ -42,7 +41,7 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
        struct mm_struct *mm = current->active_mm;
        int ret;
-        if (!suspend_pgd)
+        if (!idmap_pgd)
                return -EINVAL;
        /*
@@ -59,14 +58,3 @@ int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
        return ret;
 }
-static int __init cpu_suspend_init(void)
-{
-        suspend_pgd = pgd_alloc(&init_mm);
-        if (suspend_pgd) {
-                unsigned long addr = virt_to_phys(cpu_resume_mmu);
-                identity_mapping_add(suspend_pgd, addr, addr + SECTION_SIZE);
-        }
-        return suspend_pgd ? 0 : -ENOMEM;
-}
-core_initcall(cpu_suspend_init);
diff --git a/arch/arm/kernel/swp_emulate.c b/arch/arm/kernel/swp_emulate.c
index 5f452f8fde0..df745188f5d 100644
--- a/arch/arm/kernel/swp_emulate.c
+++ b/arch/arm/kernel/swp_emulate.c
@@ -25,6 +25,7 @@
 #include <linux/syscalls.h>
 #include <linux/perf_event.h>
+#include <asm/opcodes.h>
 #include <asm/traps.h>
 #include <asm/uaccess.h>
@@ -185,6 +186,21 @@ static int swp_handler(struct pt_regs *regs, unsigned int instr)
        perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, regs->ARM_pc);
+        res = arm_check_condition(instr, regs->ARM_cpsr);
+        switch (res) {
+        case ARM_OPCODE_CONDTEST_PASS:
+                break;
+        case ARM_OPCODE_CONDTEST_FAIL:
+                /* Condition failed - return to next instruction */
+                regs->ARM_pc += 4;
+                return 0;
+        case ARM_OPCODE_CONDTEST_UNCOND:
+                /* If unconditional encoding - not a SWP, undef */
+                return -EFAULT;
+        default:
+                return -EINVAL;
+        }
        if (current->pid != previous_pid) {
                pr_debug("\"%s\" (%ld) uses deprecated SWP{B} instruction\n",
                         current->comm, (unsigned long)current->pid);
diff --git a/arch/arm/kernel/tcm.c b/arch/arm/kernel/tcm.c
index 30e302d33e0..01ec453bb92 100644
--- a/arch/arm/kernel/tcm.c
+++ b/arch/arm/kernel/tcm.c
@@ -180,9 +180,9 @@ static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks,
 */
 void __init tcm_init(void)
 {
-        u32 tcm_status = read_cpuid_tcmstatus();
+        u32 tcm_status;
-        u8 dtcm_banks = (tcm_status >> 16) & 0x03;
+        u8 dtcm_banks;
-        u8 itcm_banks = (tcm_status & 0x03);
+        u8 itcm_banks;
        size_t dtcm_code_sz = &__edtcm_data - &__sdtcm_data;
        size_t itcm_code_sz = &__eitcm_text - &__sitcm_text;
        char *start;
@@ -191,6 +191,22 @@ void __init tcm_init(void)
        int ret;
        int i;
+        /*
+         * Prior to ARMv5 there is no TCM, and trying to read the status
+         * register will hang the processor.
+         */
+        if (cpu_architecture() < CPU_ARCH_ARMv5) {
+                if (dtcm_code_sz || itcm_code_sz)
+                        pr_info("CPU TCM: %u bytes of DTCM and %u bytes of "
+                                "ITCM code compiled in, but no TCM present "
+                                "in pre-v5 CPU\n", dtcm_code_sz, itcm_code_sz);
+                return;
+        }
+        tcm_status = read_cpuid_tcmstatus();
+        dtcm_banks = (tcm_status >> 16) & 0x03;
+        itcm_banks = (tcm_status & 0x03);
        /* Values greater than 2 for D/ITCM banks are "reserved" */
        if (dtcm_banks > 2)
                dtcm_banks = 0;
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 20b3041e086..f76e7554867 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -13,6 +13,12 @@
        *(.proc.info.init)                                              \
        VMLINUX_SYMBOL(__proc_info_end) = .;
+#define IDMAP_TEXT                                                      \
+        ALIGN_FUNCTION();                                               \
+        VMLINUX_SYMBOL(__idmap_text_start) = .;                         \
+        *(.idmap.text)                                                  \
+        VMLINUX_SYMBOL(__idmap_text_end) = .;
 #ifdef CONFIG_HOTPLUG_CPU
 #define ARM_CPU_DISCARD(x)
 #define ARM_CPU_KEEP(x)         x
@@ -92,6 +98,7 @@ SECTIONS
                        SCHED_TEXT
                        LOCK_TEXT
                        KPROBES_TEXT
+                        IDMAP_TEXT
 #ifdef CONFIG_MMU
                        *(.fixup)
 #endif
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index cf73a7f742d..0ade0acc1ed 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -13,7 +13,8 @@ lib-y		:= backtrace.o changebit.o csumipv6.o csumpartial.o   \
                   testchangebit.o testclearbit.o testsetbit.o        \
                   ashldi3.o ashrdi3.o lshrdi3.o muldi3.o             \
                   ucmpdi2.o lib1funcs.o div64.o                      \
-                   io-readsb.o io-writesb.o io-readsl.o io-writesl.o
+                   io-readsb.o io-writesb.o io-readsl.o io-writesl.o  \
+                   call_with_stack.o
 mmu-y   := clear_user.o copy_page.o getuser.o putuser.o
diff --git a/arch/arm/lib/call_with_stack.S b/arch/arm/lib/call_with_stack.S
new file mode 100644
index 00000000000..916c80f13ae
--- /dev/null
+++ b/arch/arm/lib/call_with_stack.S
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/lib/call_with_stack.S
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ * Written by Will Deacon <will.deacon@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+/*
+ * void call_with_stack(void (*fn)(void *), void *arg, void *sp)
+ *
+ * Change the stack to that pointed at by sp, then invoke fn(arg) with
+ * the new stack.
+ */
+ENTRY(call_with_stack)
+        str     sp, [r2, #-4]!
+        str     lr, [r2, #-4]!
+        mov     sp, r2
+        mov     r2, r0
+        mov     r0, r1
+        adr     lr, BSYM(1f)
+        mov     pc, r2
+1:      ldr     lr, [sp]
+        ldr     sp, [sp, #4]
+        mov     pc, lr
+ENDPROC(call_with_stack)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index d111c3e9924..4f991f29528 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -3,6 +3,12 @@ if ARCH_AT91
 config HAVE_AT91_DATAFLASH_CARD
        bool
+config HAVE_AT91_DBGU0
+        bool
+config HAVE_AT91_DBGU1
+        bool
 config HAVE_AT91_USART3
        bool
@@ -21,12 +27,14 @@ config ARCH_AT91RM9200
        bool "AT91RM9200"
        select CPU_ARM920T
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU0
        select HAVE_AT91_USART3
 config ARCH_AT91SAM9260
        bool "AT91SAM9260 or AT91SAM9XE"
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU0
        select HAVE_AT91_USART3
        select HAVE_AT91_USART4
        select HAVE_AT91_USART5
@@ -37,11 +45,13 @@ config ARCH_AT91SAM9261
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
        select HAVE_FB_ATMEL
+        select HAVE_AT91_DBGU0
 config ARCH_AT91SAM9G10
        bool "AT91SAM9G10"
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU0
        select HAVE_FB_ATMEL
 config ARCH_AT91SAM9263
@@ -50,6 +60,7 @@ config ARCH_AT91SAM9263
        select GENERIC_CLOCKEVENTS
        select HAVE_FB_ATMEL
        select HAVE_NET_MACB
+        select HAVE_AT91_DBGU1
 config ARCH_AT91SAM9RL
        bool "AT91SAM9RL"
@@ -57,11 +68,13 @@ config ARCH_AT91SAM9RL
        select GENERIC_CLOCKEVENTS
        select HAVE_AT91_USART3
        select HAVE_FB_ATMEL
+        select HAVE_AT91_DBGU0
 config ARCH_AT91SAM9G20
        bool "AT91SAM9G20"
        select CPU_ARM926T
        select GENERIC_CLOCKEVENTS
+        select HAVE_AT91_DBGU0
        select HAVE_AT91_USART3
        select HAVE_AT91_USART4
        select HAVE_AT91_USART5
@@ -74,6 +87,7 @@ config ARCH_AT91SAM9G45
        select HAVE_AT91_USART3
        select HAVE_FB_ATMEL
        select HAVE_NET_MACB
+        select HAVE_AT91_DBGU1
 config ARCH_AT91CAP9
        bool "AT91CAP9"
@@ -81,6 +95,7 @@ config ARCH_AT91CAP9
        select GENERIC_CLOCKEVENTS
        select HAVE_FB_ATMEL
        select HAVE_NET_MACB
+        select HAVE_AT91_DBGU1
 config ARCH_AT91X40
        bool "AT91x40"
@@ -510,8 +525,13 @@ config AT91_TIMER_HZ
 choice
        prompt "Select a UART for early kernel messages"
-config AT91_EARLY_DBGU
+config AT91_EARLY_DBGU0
-        bool "DBGU"
+        bool "DBGU on rm9200, 9260/9g20, 9261/9g10 and 9rl"
+        depends on HAVE_AT91_DBGU0
+config AT91_EARLY_DBGU1
+        bool "DBGU on 9263, 9g45 and cap9"
+        depends on HAVE_AT91_DBGU1
 config AT91_EARLY_USART0
        bool "USART0"
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index ecdd54dd68c..edb879ac04c 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -13,7 +13,6 @@
 */
 #include <linux/module.h>
-#include <linux/pm.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -23,11 +22,11 @@
 #include <mach/at91cap9.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 /* --------------------------------------------------------------------
 *  Clocks
@@ -137,7 +136,7 @@ static struct clk pwm_clk = {
        .type           = CLK_TYPE_PERIPHERAL,
 };
 static struct clk macb_clk = {
-        .name           = "macb_clk",
+        .name           = "pclk",
        .pmc_mask       = 1 << AT91CAP9_ID_EMAC,
        .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -210,6 +209,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 static struct clk_lookup periph_clocks_lookups[] = {
+        /* One additional fake clock for macb_hclk */
+        CLKDEV_CON_ID("hclk", &macb_clk),
        CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
        CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
@@ -221,6 +222,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+        CLKDEV_CON_ID("pioA", &pioABCD_clk),
+        CLKDEV_CON_ID("pioB", &pioABCD_clk),
+        CLKDEV_CON_ID("pioC", &pioABCD_clk),
+        CLKDEV_CON_ID("pioD", &pioABCD_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -293,37 +298,27 @@ void __init at91cap9_set_console_clock(int id)
 *  GPIO
 * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91cap9_gpio[] = {
+static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
        {
                .id             = AT91CAP9_ID_PIOABCD,
-                .offset         = AT91_PIOA,
+                .regbase        = AT91CAP9_BASE_PIOA,
-                .clock          = &pioABCD_clk,
        }, {
                .id             = AT91CAP9_ID_PIOABCD,
-                .offset         = AT91_PIOB,
+                .regbase        = AT91CAP9_BASE_PIOB,
-                .clock          = &pioABCD_clk,
        }, {
                .id             = AT91CAP9_ID_PIOABCD,
-                .offset         = AT91_PIOC,
+                .regbase        = AT91CAP9_BASE_PIOC,
-                .clock          = &pioABCD_clk,
        }, {
                .id             = AT91CAP9_ID_PIOABCD,
-                .offset         = AT91_PIOD,
+                .regbase        = AT91CAP9_BASE_PIOD,
-                .clock          = &pioABCD_clk,
        }
 };
-static void at91cap9_reset(void)
+static void at91cap9_restart(char mode, const char *cmd)
 {
        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
-static void at91cap9_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
 /* --------------------------------------------------------------------
 *  AT91CAP9 processor initialization
 * -------------------------------------------------------------------- */
@@ -333,10 +328,16 @@ static void __init at91cap9_map_io(void)
        at91_init_sram(0, AT91CAP9_SRAM_BASE, AT91CAP9_SRAM_SIZE);
 }
+static void __init at91cap9_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
+}
 static void __init at91cap9_initialize(void)
 {
-        at91_arch_reset = at91cap9_reset;
+        arm_pm_restart = at91cap9_restart;
-        pm_power_off = at91cap9_poweroff;
        at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
        /* Register GPIO subsystem */
@@ -394,6 +395,7 @@ static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91cap9_soc = {
        .map_io = at91cap9_map_io,
        .default_irq_priority = at91cap9_default_irq_priority,
+        .ioremap_registers = at91cap9_ioremap_registers,
        .register_clocks = at91cap9_register_clocks,
        .init = at91cap9_initialize,
 };
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index adad70db70e..d298fb7cb21 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -76,7 +76,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
        /* Enable VBus control for UHP ports */
        for (i = 0; i < data->ports; i++) {
-                if (data->vbus_pin[i])
+                if (gpio_is_valid(data->vbus_pin[i]))
                        at91_set_gpio_output(data->vbus_pin[i], 0);
        }
@@ -179,7 +179,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
-        if (data && data->vbus_pin > 0) {
+        if (data && gpio_is_valid(data->vbus_pin)) {
                at91_set_gpio_input(data->vbus_pin, 0);
                at91_set_deglitch(data->vbus_pin, 1);
                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
@@ -200,7 +200,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) {}
 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
+static struct macb_platform_data eth_data;
 static struct resource eth_resources[] = {
        [0] = {
@@ -227,12 +227,12 @@ static struct platform_device at91cap9_eth_device = {
        .num_resources  = ARRAY_SIZE(eth_resources),
 };
-void __init at91_add_device_eth(struct at91_eth_data *data)
+void __init at91_add_device_eth(struct macb_platform_data *data)
 {
        if (!data)
                return;
-        if (data->phy_irq_pin) {
+        if (gpio_is_valid(data->phy_irq_pin)) {
                at91_set_gpio_input(data->phy_irq_pin, 0);
                at91_set_deglitch(data->phy_irq_pin, 1);
        }
@@ -264,7 +264,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
        platform_device_register(&at91cap9_eth_device);
 }
 #else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+void __init at91_add_device_eth(struct macb_platform_data *data) {}
 #endif
@@ -332,13 +332,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                return;
        /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 1);
                at91_set_deglitch(data->det_pin, 1);
        }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                at91_set_gpio_output(data->vcc_pin, 0);
        if (mmc_id == 0) {              /* MCI0 */
@@ -398,8 +398,8 @@ static struct resource nand_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = AT91_BASE_SYS + AT91_ECC,
+                .start  = AT91CAP9_BASE_ECC,
-                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .end    = AT91CAP9_BASE_ECC + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -425,15 +425,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                at91_set_gpio_output(data->enable_pin, 1);
        /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                at91_set_gpio_input(data->rdy_pin, 1);
        /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                at91_set_gpio_input(data->det_pin, 1);
        nand_data = *data;
@@ -670,8 +670,8 @@ static void __init at91_add_device_tc(void) { }
 static struct resource rtt_resources[] = {
        {
-                .start  = AT91_BASE_SYS + AT91_RTT,
+                .start  = AT91CAP9_BASE_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .end    = AT91CAP9_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -694,10 +694,19 @@ static void __init at91_add_device_rtt(void)
 * -------------------------------------------------------------------- */
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91CAP9_BASE_WDT,
+                .end    = AT91CAP9_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
 static struct platform_device at91cap9_wdt_device = {
        .name           = "at91_wdt",
        .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 static void __init at91_add_device_watchdog(void)
@@ -807,7 +816,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
        at91_set_A_periph(AT91_PIN_PA9, 0);     /* AC97RX */
        /* reset */
-        if (data->reset_pin)
+        if (gpio_is_valid(data->reset_pin))
                at91_set_gpio_output(data->reset_pin, 0);
        ac97_data = *data;
@@ -1021,8 +1030,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
        [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
+                .start  = AT91CAP9_BASE_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .end    = AT91CAP9_BASE_DBGU + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 713d3bdbd28..99c3174e24a 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -23,6 +23,7 @@
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 static struct map_desc at91rm9200_io_desc[] __initdata = {
        {
@@ -195,6 +196,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioC_clk),
+        CLKDEV_CON_ID("pioD", &pioD_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -268,27 +273,23 @@ void __init at91rm9200_set_console_clock(int id)
 *  GPIO
 * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91rm9200_gpio[] = {
+static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
        {
                .id             = AT91RM9200_ID_PIOA,
-                .offset         = AT91_PIOA,
+                .regbase        = AT91RM9200_BASE_PIOA,
-                .clock          = &pioA_clk,
        }, {
                .id             = AT91RM9200_ID_PIOB,
-                .offset         = AT91_PIOB,
+                .regbase        = AT91RM9200_BASE_PIOB,
-                .clock          = &pioB_clk,
        }, {
                .id             = AT91RM9200_ID_PIOC,
-                .offset         = AT91_PIOC,
+                .regbase        = AT91RM9200_BASE_PIOC,
-                .clock          = &pioC_clk,
        }, {
                .id             = AT91RM9200_ID_PIOD,
-                .offset         = AT91_PIOD,
+                .regbase        = AT91RM9200_BASE_PIOD,
-                .clock          = &pioD_clk,
        }
 };
-static void at91rm9200_reset(void)
+static void at91rm9200_restart(char mode, const char *cmd)
 {
        /*
         * Perform a hardware reset with the use of the Watchdog timer.
@@ -307,9 +308,13 @@ static void __init at91rm9200_map_io(void)
        iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
 }
+static void __init at91rm9200_ioremap_registers(void)
+{
+}
 static void __init at91rm9200_initialize(void)
 {
-        at91_arch_reset = at91rm9200_reset;
+        arm_pm_restart = at91rm9200_restart;
        at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
                        | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
                        | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
@@ -366,6 +371,7 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91rm9200_soc = {
        .map_io = at91rm9200_map_io,
        .default_irq_priority = at91rm9200_default_irq_priority,
+        .ioremap_registers = at91rm9200_ioremap_registers,
        .register_clocks = at91rm9200_register_clocks,
        .init = at91rm9200_initialize,
 };
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index ad930688358..18bacec2b09 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -114,11 +114,11 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
        if (!data)
                return;
-        if (data->vbus_pin) {
+        if (gpio_is_valid(data->vbus_pin)) {
                at91_set_gpio_input(data->vbus_pin, 0);
                at91_set_deglitch(data->vbus_pin, 1);
        }
-        if (data->pullup_pin)
+        if (gpio_is_valid(data->pullup_pin))
                at91_set_gpio_output(data->pullup_pin, 0);
        udc_data = *data;
@@ -135,7 +135,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
 #if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
 static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
+static struct macb_platform_data eth_data;
 static struct resource eth_resources[] = {
        [0] = {
@@ -162,12 +162,12 @@ static struct platform_device at91rm9200_eth_device = {
        .num_resources  = ARRAY_SIZE(eth_resources),
 };
-void __init at91_add_device_eth(struct at91_eth_data *data)
+void __init at91_add_device_eth(struct macb_platform_data *data)
 {
        if (!data)
                return;
-        if (data->phy_irq_pin) {
+        if (gpio_is_valid(data->phy_irq_pin)) {
                at91_set_gpio_input(data->phy_irq_pin, 0);
                at91_set_deglitch(data->phy_irq_pin, 1);
        }
@@ -199,7 +199,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
        platform_device_register(&at91rm9200_eth_device);
 }
 #else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+void __init at91_add_device_eth(struct macb_platform_data *data) {}
 #endif
@@ -260,7 +260,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        );
        /* input/irq */
-        if (data->irq_pin) {
+        if (gpio_is_valid(data->irq_pin)) {
                at91_set_gpio_input(data->irq_pin, 1);
                at91_set_deglitch(data->irq_pin, 1);
        }
@@ -268,7 +268,7 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        at91_set_deglitch(data->det_pin, 1);
        /* outputs, initially off */
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                at91_set_gpio_output(data->vcc_pin, 0);
        at91_set_gpio_output(data->rst_pin, 0);
@@ -328,13 +328,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                return;
        /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 1);
                at91_set_deglitch(data->det_pin, 1);
        }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                at91_set_gpio_output(data->vcc_pin, 0);
        /* CLK */
@@ -419,15 +419,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        );
        /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                at91_set_gpio_output(data->enable_pin, 1);
        /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                at91_set_gpio_input(data->rdy_pin, 1);
        /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                at91_set_gpio_input(data->det_pin, 1);
        at91_set_A_periph(AT91_PIN_PC1, 0);             /* SMOE */
@@ -665,10 +665,24 @@ static void __init at91_add_device_tc(void) { }
 * -------------------------------------------------------------------- */
 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = AT91RM9200_BASE_RTC,
+                .end    = AT91RM9200_BASE_RTC + SZ_256 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
 static struct platform_device at91rm9200_rtc_device = {
        .name           = "at91_rtc",
        .id             = -1,
-        .num_resources  = 0,
+        .resource       = rtc_resources,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
 };
 static void __init at91_add_device_rtc(void)
@@ -877,8 +891,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
        [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
+                .start  = AT91RM9200_BASE_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .end    = AT91RM9200_BASE_DBGU + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 1dd69c85dfe..a028cdf8f97 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -32,6 +32,8 @@ static unsigned long last_crtr;
 static u32 irqmask;
 static struct clock_event_device clkevt;
+#define RM9200_TIMER_LATCH      ((AT91_SLOW_CLOCK + HZ/2) / HZ)
 /*
 * The ST_CRTR is updated asynchronously to the master clock ... but
 * the updates as seen by the CPU don't seem to be strictly monotonic.
@@ -74,8 +76,8 @@ static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
        if (sr & AT91_ST_PITS) {
                u32     crtr = read_CRTR();
-                while (((crtr - last_crtr) & AT91_ST_CRTV) >= LATCH) {
+                while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
-                        last_crtr += LATCH;
+                        last_crtr += RM9200_TIMER_LATCH;
                        clkevt.event_handler(&clkevt);
                }
                return IRQ_HANDLED;
@@ -116,7 +118,7 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev)
        case CLOCK_EVT_MODE_PERIODIC:
                /* PIT for periodic irqs; fixed rate of 1/HZ */
                irqmask = AT91_ST_PITS;
-                at91_sys_write(AT91_ST_PIMR, LATCH);
+                at91_sys_write(AT91_ST_PIMR, RM9200_TIMER_LATCH);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
                /* ALM for oneshot irqs, set by next_event()
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 0d20677fbef..5e46e4a9643 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -11,7 +11,6 @@
 */
 #include <linux/module.h>
-#include <linux/pm.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -21,11 +20,11 @@
 #include <mach/at91sam9260.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 /* --------------------------------------------------------------------
 *  Clocks
@@ -120,7 +119,7 @@ static struct clk ohci_clk = {
        .type           = CLK_TYPE_PERIPHERAL,
 };
 static struct clk macb_clk = {
-        .name           = "macb_clk",
+        .name           = "pclk",
        .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
        .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -190,6 +189,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 static struct clk_lookup periph_clocks_lookups[] = {
+        /* One additional fake clock for macb_hclk */
+        CLKDEV_CON_ID("hclk", &macb_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
@@ -209,6 +210,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioC_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -270,28 +274,19 @@ void __init at91sam9260_set_console_clock(int id)
 *  GPIO
 * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91sam9260_gpio[] = {
+static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
        {
                .id             = AT91SAM9260_ID_PIOA,
-                .offset         = AT91_PIOA,
+                .regbase        = AT91SAM9260_BASE_PIOA,
-                .clock          = &pioA_clk,
        }, {
                .id             = AT91SAM9260_ID_PIOB,
-                .offset         = AT91_PIOB,
+                .regbase        = AT91SAM9260_BASE_PIOB,
-                .clock          = &pioB_clk,
        }, {
                .id             = AT91SAM9260_ID_PIOC,
-                .offset         = AT91_PIOC,
+                .regbase        = AT91SAM9260_BASE_PIOC,
-                .clock          = &pioC_clk,
        }
 };
-static void at91sam9260_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
 /* --------------------------------------------------------------------
 *  AT91SAM9260 processor initialization
 * -------------------------------------------------------------------- */
@@ -325,10 +320,16 @@ static void __init at91sam9260_map_io(void)
        }
 }
+static void __init at91sam9260_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
+}
 static void __init at91sam9260_initialize(void)
 {
-        at91_arch_reset = at91sam9_alt_reset;
+        arm_pm_restart = at91sam9_alt_restart;
-        pm_power_off = at91sam9260_poweroff;
        at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                        | (1 << AT91SAM9260_ID_IRQ2);
@@ -381,6 +382,7 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9260_soc = {
        .map_io = at91sam9260_map_io,
        .default_irq_priority = at91sam9260_default_irq_priority,
+        .ioremap_registers = at91sam9260_ioremap_registers,
        .register_clocks = at91sam9260_register_clocks,
        .init = at91sam9260_initialize,
 };
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 629fa977497..642ccb6d26b 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -115,7 +115,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
        if (!data)
                return;
-        if (data->vbus_pin) {
+        if (gpio_is_valid(data->vbus_pin)) {
                at91_set_gpio_input(data->vbus_pin, 0);
                at91_set_deglitch(data->vbus_pin, 1);
        }
@@ -136,7 +136,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
+static struct macb_platform_data eth_data;
 static struct resource eth_resources[] = {
        [0] = {
@@ -163,12 +163,12 @@ static struct platform_device at91sam9260_eth_device = {
        .num_resources  = ARRAY_SIZE(eth_resources),
 };
-void __init at91_add_device_eth(struct at91_eth_data *data)
+void __init at91_add_device_eth(struct macb_platform_data *data)
 {
        if (!data)
                return;
-        if (data->phy_irq_pin) {
+        if (gpio_is_valid(data->phy_irq_pin)) {
                at91_set_gpio_input(data->phy_irq_pin, 0);
                at91_set_deglitch(data->phy_irq_pin, 1);
        }
@@ -200,7 +200,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
        platform_device_register(&at91sam9260_eth_device);
 }
 #else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+void __init at91_add_device_eth(struct macb_platform_data *data) {}
 #endif
@@ -243,13 +243,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                return;
        /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 1);
                at91_set_deglitch(data->det_pin, 1);
        }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                at91_set_gpio_output(data->vcc_pin, 0);
        /* CLK */
@@ -330,11 +330,11 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
        for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
                if (data->slot[i].bus_width) {
                        /* input/irq */
-                        if (data->slot[i].detect_pin) {
+                        if (gpio_is_valid(data->slot[i].detect_pin)) {
                                at91_set_gpio_input(data->slot[i].detect_pin, 1);
                                at91_set_deglitch(data->slot[i].detect_pin, 1);
                        }
-                        if (data->slot[i].wp_pin)
+                        if (gpio_is_valid(data->slot[i].wp_pin))
                                at91_set_gpio_input(data->slot[i].wp_pin, 1);
                        switch (i) {
@@ -399,8 +399,8 @@ static struct resource nand_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = AT91_BASE_SYS + AT91_ECC,
+                .start  = AT91SAM9260_BASE_ECC,
-                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .end    = AT91SAM9260_BASE_ECC + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -426,15 +426,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                at91_set_gpio_output(data->enable_pin, 1);
        /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                at91_set_gpio_input(data->rdy_pin, 1);
        /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                at91_set_gpio_input(data->det_pin, 1);
        nand_data = *data;
@@ -714,8 +714,8 @@ static void __init at91_add_device_tc(void) { }
 static struct resource rtt_resources[] = {
        {
-                .start  = AT91_BASE_SYS + AT91_RTT,
+                .start  = AT91SAM9260_BASE_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .end    = AT91SAM9260_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -738,10 +738,19 @@ static void __init at91_add_device_rtt(void)
 * -------------------------------------------------------------------- */
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91SAM9260_BASE_WDT,
+                .end    = AT91SAM9260_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
 static struct platform_device at91sam9260_wdt_device = {
        .name           = "at91_wdt",
        .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 static void __init at91_add_device_watchdog(void)
@@ -837,8 +846,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
        [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
+                .start  = AT91SAM9260_BASE_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .end    = AT91SAM9260_BASE_DBGU + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -1281,17 +1290,17 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        at91_sys_write(AT91_MATRIX_EBICSA, csa);
-        if (data->rst_pin) {
+        if (gpio_is_valid(data->rst_pin)) {
                at91_set_multi_drive(data->rst_pin, 0);
                at91_set_gpio_output(data->rst_pin, 1);
        }
-        if (data->irq_pin) {
+        if (gpio_is_valid(data->irq_pin)) {
                at91_set_gpio_input(data->irq_pin, 0);
                at91_set_deglitch(data->irq_pin, 1);
        }
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 0);
                at91_set_deglitch(data->det_pin, 1);
        }
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 658a5185abf..b85b9ea6017 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -11,7 +11,6 @@
 */
 #include <linux/module.h>
-#include <linux/pm.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -20,11 +19,11 @@
 #include <mach/at91sam9261.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 /* --------------------------------------------------------------------
 *  Clocks
@@ -176,6 +175,9 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioC_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -251,28 +253,19 @@ void __init at91sam9261_set_console_clock(int id)
 *  GPIO
 * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91sam9261_gpio[] = {
+static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
        {
                .id             = AT91SAM9261_ID_PIOA,
-                .offset         = AT91_PIOA,
+                .regbase        = AT91SAM9261_BASE_PIOA,
-                .clock          = &pioA_clk,
        }, {
                .id             = AT91SAM9261_ID_PIOB,
-                .offset         = AT91_PIOB,
+                .regbase        = AT91SAM9261_BASE_PIOB,
-                .clock          = &pioB_clk,
        }, {
                .id             = AT91SAM9261_ID_PIOC,
-                .offset         = AT91_PIOC,
+                .regbase        = AT91SAM9261_BASE_PIOC,
-                .clock          = &pioC_clk,
        }
 };
-static void at91sam9261_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
 /* --------------------------------------------------------------------
 *  AT91SAM9261 processor initialization
 * -------------------------------------------------------------------- */
@@ -285,10 +278,16 @@ static void __init at91sam9261_map_io(void)
                at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
 }
+static void __init at91sam9261_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
+}
 static void __init at91sam9261_initialize(void)
 {
-        at91_arch_reset = at91sam9_alt_reset;
+        arm_pm_restart = at91sam9_alt_restart;
-        pm_power_off = at91sam9261_poweroff;
        at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
                        | (1 << AT91SAM9261_ID_IRQ2);
@@ -341,6 +340,7 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9261_soc = {
        .map_io = at91sam9261_map_io,
        .default_irq_priority = at91sam9261_default_irq_priority,
+        .ioremap_registers = at91sam9261_ioremap_registers,
        .register_clocks = at91sam9261_register_clocks,
        .init = at91sam9261_initialize,
 };
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index a178b58b0b9..fc59cbdb0e3 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -118,7 +118,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
        if (!data)
                return;
-        if (data->vbus_pin) {
+        if (gpio_is_valid(data->vbus_pin)) {
                at91_set_gpio_input(data->vbus_pin, 0);
                at91_set_deglitch(data->vbus_pin, 1);
        }
@@ -171,13 +171,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                return;
        /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 1);
                at91_set_deglitch(data->det_pin, 1);
        }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                at91_set_gpio_output(data->vcc_pin, 0);
        /* CLK */
@@ -240,15 +240,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                at91_set_gpio_output(data->enable_pin, 1);
        /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                at91_set_gpio_input(data->rdy_pin, 1);
        /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                at91_set_gpio_input(data->det_pin, 1);
        at91_set_A_periph(AT91_PIN_PC0, 0);             /* NANDOE */
@@ -600,8 +600,8 @@ static void __init at91_add_device_tc(void) { }
 static struct resource rtt_resources[] = {
        {
-                .start  = AT91_BASE_SYS + AT91_RTT,
+                .start  = AT91SAM9261_BASE_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .end    = AT91SAM9261_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -624,10 +624,19 @@ static void __init at91_add_device_rtt(void)
 * -------------------------------------------------------------------- */
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91SAM9261_BASE_WDT,
+                .end    = AT91SAM9261_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
 static struct platform_device at91sam9261_wdt_device = {
        .name           = "at91_wdt",
        .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 static void __init at91_add_device_watchdog(void)
@@ -816,8 +825,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
        [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
+                .start  = AT91SAM9261_BASE_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .end    = AT91SAM9261_BASE_DBGU + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index f83fbb0ee0c..79e3669b111 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -11,7 +11,6 @@
 */
 #include <linux/module.h>
-#include <linux/pm.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -19,11 +18,11 @@
 #include <mach/at91sam9263.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 /* --------------------------------------------------------------------
 *  Clocks
@@ -118,7 +117,7 @@ static struct clk pwm_clk = {
        .type           = CLK_TYPE_PERIPHERAL,
 };
 static struct clk macb_clk = {
-        .name           = "macb_clk",
+        .name           = "pclk",
        .pmc_mask       = 1 << AT91SAM9263_ID_EMAC,
        .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -182,6 +181,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 static struct clk_lookup periph_clocks_lookups[] = {
+        /* One additional fake clock for macb_hclk */
+        CLKDEV_CON_ID("hclk", &macb_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
@@ -191,6 +192,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioCDE_clk),
+        CLKDEV_CON_ID("pioD", &pioCDE_clk),
+        CLKDEV_CON_ID("pioE", &pioCDE_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -263,36 +269,25 @@ void __init at91sam9263_set_console_clock(int id)
 *  GPIO
 * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91sam9263_gpio[] = {
+static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
        {
                .id             = AT91SAM9263_ID_PIOA,
-                .offset         = AT91_PIOA,
+                .regbase        = AT91SAM9263_BASE_PIOA,
-                .clock          = &pioA_clk,
        }, {
                .id             = AT91SAM9263_ID_PIOB,
-                .offset         = AT91_PIOB,
+                .regbase        = AT91SAM9263_BASE_PIOB,
-                .clock          = &pioB_clk,
        }, {
                .id             = AT91SAM9263_ID_PIOCDE,
-                .offset         = AT91_PIOC,
+                .regbase        = AT91SAM9263_BASE_PIOC,
-                .clock          = &pioCDE_clk,
        }, {
                .id             = AT91SAM9263_ID_PIOCDE,
-                .offset         = AT91_PIOD,
+                .regbase        = AT91SAM9263_BASE_PIOD,
-                .clock          = &pioCDE_clk,
        }, {
                .id             = AT91SAM9263_ID_PIOCDE,
-                .offset         = AT91_PIOE,
+                .regbase        = AT91SAM9263_BASE_PIOE,
-                .clock          = &pioCDE_clk,
        }
 };
-static void at91sam9263_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
 /* --------------------------------------------------------------------
 *  AT91SAM9263 processor initialization
 * -------------------------------------------------------------------- */
@@ -303,10 +298,17 @@ static void __init at91sam9263_map_io(void)
        at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
 }
+static void __init at91sam9263_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
+        at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
+}
 static void __init at91sam9263_initialize(void)
 {
-        at91_arch_reset = at91sam9_alt_reset;
+        arm_pm_restart = at91sam9_alt_restart;
-        pm_power_off = at91sam9263_poweroff;
        at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
        /* Register GPIO subsystem */
@@ -358,6 +360,7 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9263_soc = {
        .map_io = at91sam9263_map_io,
        .default_irq_priority = at91sam9263_default_irq_priority,
+        .ioremap_registers = at91sam9263_ioremap_registers,
        .register_clocks = at91sam9263_register_clocks,
        .init = at91sam9263_initialize,
 };
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index d5fbac9ff4f..7b46b278702 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -70,7 +70,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
        /* Enable VBus control for UHP ports */
        for (i = 0; i < data->ports; i++) {
-                if (data->vbus_pin[i])
+                if (gpio_is_valid(data->vbus_pin[i]))
                        at91_set_gpio_output(data->vbus_pin[i], 0);
        }
@@ -123,7 +123,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data)
        if (!data)
                return;
-        if (data->vbus_pin) {
+        if (gpio_is_valid(data->vbus_pin)) {
                at91_set_gpio_input(data->vbus_pin, 0);
                at91_set_deglitch(data->vbus_pin, 1);
        }
@@ -144,7 +144,7 @@ void __init at91_add_device_udc(struct at91_udc_data *data) {}
 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
+static struct macb_platform_data eth_data;
 static struct resource eth_resources[] = {
        [0] = {
@@ -171,12 +171,12 @@ static struct platform_device at91sam9263_eth_device = {
        .num_resources  = ARRAY_SIZE(eth_resources),
 };
-void __init at91_add_device_eth(struct at91_eth_data *data)
+void __init at91_add_device_eth(struct macb_platform_data *data)
 {
        if (!data)
                return;
-        if (data->phy_irq_pin) {
+        if (gpio_is_valid(data->phy_irq_pin)) {
                at91_set_gpio_input(data->phy_irq_pin, 0);
                at91_set_deglitch(data->phy_irq_pin, 1);
        }
@@ -208,7 +208,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
        platform_device_register(&at91sam9263_eth_device);
 }
 #else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+void __init at91_add_device_eth(struct macb_platform_data *data) {}
 #endif
@@ -276,13 +276,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                return;
        /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 1);
                at91_set_deglitch(data->det_pin, 1);
        }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                at91_set_gpio_output(data->vcc_pin, 0);
        if (mmc_id == 0) {              /* MCI0 */
@@ -430,17 +430,17 @@ void __init at91_add_device_cf(struct at91_cf_data *data)
        }
        at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 1);
                at91_set_deglitch(data->det_pin, 1);
        }
-        if (data->irq_pin) {
+        if (gpio_is_valid(data->irq_pin)) {
                at91_set_gpio_input(data->irq_pin, 1);
                at91_set_deglitch(data->irq_pin, 1);
        }
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                /* initially off */
                at91_set_gpio_output(data->vcc_pin, 0);
@@ -473,8 +473,8 @@ static struct resource nand_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = AT91_BASE_SYS + AT91_ECC0,
+                .start  = AT91SAM9263_BASE_ECC0,
-                .end    = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1,
+                .end    = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -500,15 +500,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                at91_set_gpio_output(data->enable_pin, 1);
        /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                at91_set_gpio_input(data->rdy_pin, 1);
        /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                at91_set_gpio_input(data->det_pin, 1);
        nand_data = *data;
@@ -749,7 +749,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
        at91_set_A_periph(AT91_PIN_PB3, 0);     /* AC97RX */
        /* reset */
-        if (data->reset_pin)
+        if (gpio_is_valid(data->reset_pin))
                at91_set_gpio_output(data->reset_pin, 0);
        ac97_data = *data;
@@ -956,8 +956,8 @@ static void __init at91_add_device_tc(void) { }
 static struct resource rtt0_resources[] = {
        {
-                .start  = AT91_BASE_SYS + AT91_RTT0,
+                .start  = AT91SAM9263_BASE_RTT0,
-                .end    = AT91_BASE_SYS + AT91_RTT0 + SZ_16 - 1,
+                .end    = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -971,8 +971,8 @@ static struct platform_device at91sam9263_rtt0_device = {
 static struct resource rtt1_resources[] = {
        {
-                .start  = AT91_BASE_SYS + AT91_RTT1,
+                .start  = AT91SAM9263_BASE_RTT1,
-                .end    = AT91_BASE_SYS + AT91_RTT1 + SZ_16 - 1,
+                .end    = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -996,10 +996,19 @@ static void __init at91_add_device_rtt(void)
 * -------------------------------------------------------------------- */
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91SAM9263_BASE_WDT,
+                .end    = AT91SAM9263_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
 static struct platform_device at91sam9263_wdt_device = {
        .name           = "at91_wdt",
        .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 static void __init at91_add_device_watchdog(void)
@@ -1196,8 +1205,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 static struct resource dbgu_resources[] = {
        [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
+                .start  = AT91SAM9263_BASE_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .end    = AT91SAM9263_BASE_DBGU + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index 4ba85499fa9..d89ead740a9 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -25,7 +25,17 @@
 static u32 pit_cycle;           /* write-once */
 static u32 pit_cnt;             /* access only w/system irq blocked */
+static void __iomem *pit_base_addr __read_mostly;
+static inline unsigned int pit_read(unsigned int reg_offset)
+{
+        return __raw_readl(pit_base_addr + reg_offset);
+}
+static inline void pit_write(unsigned int reg_offset, unsigned long value)
+{
+        __raw_writel(value, pit_base_addr + reg_offset);
+}
 /*
 * Clocksource:  just a monotonic counter of MCK/16 cycles.
@@ -39,7 +49,7 @@ static cycle_t read_pit_clk(struct clocksource *cs)
        raw_local_irq_save(flags);
        elapsed = pit_cnt;
-        t = at91_sys_read(AT91_PIT_PIIR);
+        t = pit_read(AT91_PIT_PIIR);
        raw_local_irq_restore(flags);
        elapsed += PIT_PICNT(t) * pit_cycle;
@@ -64,8 +74,8 @@ pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
                /* update clocksource counter */
-                pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+                pit_cnt += pit_cycle * PIT_PICNT(pit_read(AT91_PIT_PIVR));
-                at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
+                pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
                                | AT91_PIT_PITIEN);
                break;
        case CLOCK_EVT_MODE_ONESHOT:
@@ -74,7 +84,7 @@ pit_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
        case CLOCK_EVT_MODE_SHUTDOWN:
        case CLOCK_EVT_MODE_UNUSED:
                /* disable irq, leaving the clocksource active */
-                at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+                pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
                break;
        case CLOCK_EVT_MODE_RESUME:
                break;
@@ -103,11 +113,11 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id)
        /* The PIT interrupt may be disabled, and is shared */
        if ((pit_clkevt.mode == CLOCK_EVT_MODE_PERIODIC)
-                        && (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
+                        && (pit_read(AT91_PIT_SR) & AT91_PIT_PITS)) {
                unsigned nr_ticks;
                /* Get number of ticks performed before irq, and ack it */
-                nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+                nr_ticks = PIT_PICNT(pit_read(AT91_PIT_PIVR));
                do {
                        pit_cnt += pit_cycle;
                        pit_clkevt.event_handler(&pit_clkevt);
@@ -129,14 +139,14 @@ static struct irqaction at91sam926x_pit_irq = {
 static void at91sam926x_pit_reset(void)
 {
        /* Disable timer and irqs */
-        at91_sys_write(AT91_PIT_MR, 0);
+        pit_write(AT91_PIT_MR, 0);
        /* Clear any pending interrupts, wait for PIT to stop counting */
-        while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
+        while (PIT_CPIV(pit_read(AT91_PIT_PIVR)) != 0)
                cpu_relax();
        /* Start PIT but don't enable IRQ */
-        at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+        pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
 }
 /*
@@ -178,7 +188,15 @@ static void __init at91sam926x_pit_init(void)
 static void at91sam926x_pit_suspend(void)
 {
        /* Disable timer */
-        at91_sys_write(AT91_PIT_MR, 0);
+        pit_write(AT91_PIT_MR, 0);
+}
+void __init at91sam926x_ioremap_pit(u32 addr)
+{
+        pit_base_addr = ioremap(addr, 16);
+        if (!pit_base_addr)
+                panic("Impossible to ioremap PIT\n");
 }
 struct sys_timer at91sam926x_timer = {
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index e0256deb91f..d3f931c5942 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -14,20 +14,15 @@
 */
 #include <linux/linkage.h>
-#include <asm/system.h>
 #include <mach/hardware.h>
 #include <mach/at91sam9_sdramc.h>
 #include <mach/at91_rstc.h>
                        .arm
-                        .globl  at91sam9_alt_reset
+                        .globl  at91sam9_alt_restart
-at91sam9_alt_reset:     mrc     p15, 0, r0, c1, c0, 0
+at91sam9_alt_restart:   ldr     r0, .at91_va_base_sdramc        @ preload constants
-                        orr     r0, r0, #CR_I
-                        mcr     p15, 0, r0, c1, c0, 0           @ enable I-cache
-                        ldr     r0, .at91_va_base_sdramc        @ preload constants
                        ldr     r1, .at91_va_base_rstc_cr
                        mov     r2, #1
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 318b0407ea0..7032dd32cdf 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -11,7 +11,6 @@
 */
 #include <linux/module.h>
-#include <linux/pm.h>
 #include <linux/dma-mapping.h>
 #include <asm/irq.h>
@@ -20,12 +19,12 @@
 #include <mach/at91sam9g45.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 #include <mach/cpu.h>
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 /* --------------------------------------------------------------------
 *  Clocks
@@ -150,7 +149,7 @@ static struct clk ac97_clk = {
        .type           = CLK_TYPE_PERIPHERAL,
 };
 static struct clk macb_clk = {
-        .name           = "macb_clk",
+        .name           = "pclk",
        .pmc_mask       = 1 << AT91SAM9G45_ID_EMAC,
        .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -209,6 +208,8 @@ static struct clk *periph_clocks[] __initdata = {
 };
 static struct clk_lookup periph_clocks_lookups[] = {
+        /* One additional fake clock for macb_hclk */
+        CLKDEV_CON_ID("hclk", &macb_clk),
        /* One additional fake clock for ohci */
        CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
        CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
@@ -231,6 +232,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
        /* fake hclk clock */
        CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioC_clk),
+        CLKDEV_CON_ID("pioD", &pioDE_clk),
+        CLKDEV_CON_ID("pioE", &pioDE_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -293,41 +299,30 @@ void __init at91sam9g45_set_console_clock(int id)
 *  GPIO
 * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91sam9g45_gpio[] = {
+static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
        {
                .id             = AT91SAM9G45_ID_PIOA,
-                .offset         = AT91_PIOA,
+                .regbase        = AT91SAM9G45_BASE_PIOA,
-                .clock          = &pioA_clk,
        }, {
                .id             = AT91SAM9G45_ID_PIOB,
-                .offset         = AT91_PIOB,
+                .regbase        = AT91SAM9G45_BASE_PIOB,
-                .clock          = &pioB_clk,
        }, {
                .id             = AT91SAM9G45_ID_PIOC,
-                .offset         = AT91_PIOC,
+                .regbase        = AT91SAM9G45_BASE_PIOC,
-                .clock          = &pioC_clk,
        }, {
                .id             = AT91SAM9G45_ID_PIODE,
-                .offset         = AT91_PIOD,
+                .regbase        = AT91SAM9G45_BASE_PIOD,
-                .clock          = &pioDE_clk,
        }, {
                .id             = AT91SAM9G45_ID_PIODE,
-                .offset         = AT91_PIOE,
+                .regbase        = AT91SAM9G45_BASE_PIOE,
-                .clock          = &pioDE_clk,
        }
 };
-static void at91sam9g45_reset(void)
+static void at91sam9g45_restart(char mode, const char *cmd)
 {
        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
-static void at91sam9g45_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
 /* --------------------------------------------------------------------
 *  AT91SAM9G45 processor initialization
 * -------------------------------------------------------------------- */
@@ -338,10 +333,16 @@ static void __init at91sam9g45_map_io(void)
        init_consistent_dma_size(SZ_4M);
 }
+static void __init at91sam9g45_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
+}
 static void __init at91sam9g45_initialize(void)
 {
-        at91_arch_reset = at91sam9g45_reset;
+        arm_pm_restart = at91sam9g45_restart;
-        pm_power_off = at91sam9g45_poweroff;
        at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
        /* Register GPIO subsystem */
@@ -393,6 +394,7 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9g45_soc = {
        .map_io = at91sam9g45_map_io,
        .default_irq_priority = at91sam9g45_default_irq_priority,
+        .ioremap_registers = at91sam9g45_ioremap_registers,
        .register_clocks = at91sam9g45_register_clocks,
        .init = at91sam9g45_initialize,
 };
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 09a16d6bd5c..b7582dd10dc 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -44,8 +44,8 @@ static struct at_dma_platform_data atdma_pdata = {
 static struct resource hdmac_resources[] = {
        [0] = {
-                .start  = AT91_BASE_SYS + AT91_DMA,
+                .start  = AT91SAM9G45_BASE_DMA,
-                .end    = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
+                .end    = AT91SAM9G45_BASE_DMA + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
@@ -120,7 +120,7 @@ void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
        /* Enable VBus control for UHP ports */
        for (i = 0; i < data->ports; i++) {
-                if (data->vbus_pin[i])
+                if (gpio_is_valid(data->vbus_pin[i]))
                        at91_set_gpio_output(data->vbus_pin[i], 0);
        }
@@ -181,7 +181,7 @@ void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
        /* Enable VBus control for UHP ports */
        for (i = 0; i < data->ports; i++) {
-                if (data->vbus_pin[i])
+                if (gpio_is_valid(data->vbus_pin[i]))
                        at91_set_gpio_output(data->vbus_pin[i], 0);
        }
@@ -263,7 +263,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
-        if (data && data->vbus_pin > 0) {
+        if (data && gpio_is_valid(data->vbus_pin)) {
                at91_set_gpio_input(data->vbus_pin, 0);
                at91_set_deglitch(data->vbus_pin, 1);
                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
@@ -284,7 +284,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data) {}
 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
 static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
+static struct macb_platform_data eth_data;
 static struct resource eth_resources[] = {
        [0] = {
@@ -311,12 +311,12 @@ static struct platform_device at91sam9g45_eth_device = {
        .num_resources  = ARRAY_SIZE(eth_resources),
 };
-void __init at91_add_device_eth(struct at91_eth_data *data)
+void __init at91_add_device_eth(struct macb_platform_data *data)
 {
        if (!data)
                return;
-        if (data->phy_irq_pin) {
+        if (gpio_is_valid(data->phy_irq_pin)) {
                at91_set_gpio_input(data->phy_irq_pin, 0);
                at91_set_deglitch(data->phy_irq_pin, 1);
        }
@@ -348,7 +348,7 @@ void __init at91_add_device_eth(struct at91_eth_data *data)
        platform_device_register(&at91sam9g45_eth_device);
 }
 #else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
+void __init at91_add_device_eth(struct macb_platform_data *data) {}
 #endif
@@ -449,11 +449,11 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
        /* input/irq */
-        if (data->slot[0].detect_pin) {
+        if (gpio_is_valid(data->slot[0].detect_pin)) {
                at91_set_gpio_input(data->slot[0].detect_pin, 1);
                at91_set_deglitch(data->slot[0].detect_pin, 1);
        }
-        if (data->slot[0].wp_pin)
+        if (gpio_is_valid(data->slot[0].wp_pin))
                at91_set_gpio_input(data->slot[0].wp_pin, 1);
        if (mmc_id == 0) {              /* MCI0 */
@@ -529,8 +529,8 @@ static struct resource nand_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = AT91_BASE_SYS + AT91_ECC,
+                .start  = AT91SAM9G45_BASE_ECC,
-                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .end    = AT91SAM9G45_BASE_ECC + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -556,15 +556,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                at91_set_gpio_output(data->enable_pin, 1);
        /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                at91_set_gpio_input(data->rdy_pin, 1);
        /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                at91_set_gpio_input(data->det_pin, 1);
        nand_data = *data;
@@ -859,7 +859,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
        at91_set_A_periph(AT91_PIN_PD6, 0);     /* AC97RX */
        /* reset */
-        if (data->reset_pin)
+        if (gpio_is_valid(data->reset_pin))
                at91_set_gpio_output(data->reset_pin, 0);
        ac97_data = *data;
@@ -1009,10 +1009,24 @@ static void __init at91_add_device_tc(void) { }
 * -------------------------------------------------------------------- */
 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_RTC,
+                .end    = AT91SAM9G45_BASE_RTC + SZ_256 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
 static struct platform_device at91sam9g45_rtc_device = {
        .name           = "at91_rtc",
        .id             = -1,
-        .num_resources  = 0,
+        .resource       = rtc_resources,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
 };
 static void __init at91_add_device_rtc(void)
@@ -1081,8 +1095,8 @@ void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
 static struct resource rtt_resources[] = {
        {
-                .start  = AT91_BASE_SYS + AT91_RTT,
+                .start  = AT91SAM9G45_BASE_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .end    = AT91SAM9G45_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -1133,10 +1147,19 @@ static void __init at91_add_device_trng(void) {}
 * -------------------------------------------------------------------- */
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91SAM9G45_BASE_WDT,
+                .end    = AT91SAM9G45_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
 static struct platform_device at91sam9g45_wdt_device = {
        .name           = "at91_wdt",
        .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 static void __init at91_add_device_watchdog(void)
@@ -1332,8 +1355,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
        [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
+                .start  = AT91SAM9G45_BASE_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .end    = AT91SAM9G45_BASE_DBGU + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index a238105d2c1..d6bcb1da11d 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -10,7 +10,6 @@
 */
 #include <linux/module.h>
-#include <linux/pm.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
@@ -20,11 +19,11 @@
 #include <mach/at91sam9rl.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
-#include <mach/at91_shdwc.h>
 #include "soc.h"
 #include "generic.h"
 #include "clock.h"
+#include "sam9_smc.h"
 /* --------------------------------------------------------------------
 *  Clocks
@@ -184,6 +183,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_ID("pioA", &pioA_clk),
+        CLKDEV_CON_ID("pioB", &pioB_clk),
+        CLKDEV_CON_ID("pioC", &pioC_clk),
+        CLKDEV_CON_ID("pioD", &pioD_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
@@ -243,32 +246,22 @@ void __init at91sam9rl_set_console_clock(int id)
 *  GPIO
 * -------------------------------------------------------------------- */
-static struct at91_gpio_bank at91sam9rl_gpio[] = {
+static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
        {
                .id             = AT91SAM9RL_ID_PIOA,
-                .offset         = AT91_PIOA,
+                .regbase        = AT91SAM9RL_BASE_PIOA,
-                .clock          = &pioA_clk,
        }, {
                .id             = AT91SAM9RL_ID_PIOB,
-                .offset         = AT91_PIOB,
+                .regbase        = AT91SAM9RL_BASE_PIOB,
-                .clock          = &pioB_clk,
        }, {
                .id             = AT91SAM9RL_ID_PIOC,
-                .offset         = AT91_PIOC,
+                .regbase        = AT91SAM9RL_BASE_PIOC,
-                .clock          = &pioC_clk,
        }, {
                .id             = AT91SAM9RL_ID_PIOD,
-                .offset         = AT91_PIOD,
+                .regbase        = AT91SAM9RL_BASE_PIOD,
-                .clock          = &pioD_clk,
        }
 };
-static void at91sam9rl_poweroff(void)
-{
-        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
-}
 /* --------------------------------------------------------------------
 *  AT91SAM9RL processor initialization
 * -------------------------------------------------------------------- */
@@ -290,10 +283,16 @@ static void __init at91sam9rl_map_io(void)
        at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
 }
+static void __init at91sam9rl_ioremap_registers(void)
+{
+        at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
+        at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
+        at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
+}
 static void __init at91sam9rl_initialize(void)
 {
-        at91_arch_reset = at91sam9_alt_reset;
+        arm_pm_restart = at91sam9_alt_restart;
-        pm_power_off = at91sam9rl_poweroff;
        at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
        /* Register GPIO subsystem */
@@ -345,6 +344,7 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
 struct at91_init_soc __initdata at91sam9rl_soc = {
        .map_io = at91sam9rl_map_io,
        .default_irq_priority = at91sam9rl_default_irq_priority,
+        .ioremap_registers = at91sam9rl_ioremap_registers,
        .register_clocks = at91sam9rl_register_clocks,
        .init = at91sam9rl_initialize,
 };
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 628eb566d60..61908dce978 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -39,8 +39,8 @@ static struct at_dma_platform_data atdma_pdata = {
 static struct resource hdmac_resources[] = {
        [0] = {
-                .start  = AT91_BASE_SYS + AT91_DMA,
+                .start  = AT91SAM9RL_BASE_DMA,
-                .end    = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
+                .end    = AT91SAM9RL_BASE_DMA + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [2] = {
@@ -147,7 +147,7 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));
-        if (data && data->vbus_pin > 0) {
+        if (data && gpio_is_valid(data->vbus_pin)) {
                at91_set_gpio_input(data->vbus_pin, 0);
                at91_set_deglitch(data->vbus_pin, 1);
                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
@@ -201,13 +201,13 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                return;
        /* input/irq */
-        if (data->det_pin) {
+        if (gpio_is_valid(data->det_pin)) {
                at91_set_gpio_input(data->det_pin, 1);
                at91_set_deglitch(data->det_pin, 1);
        }
-        if (data->wp_pin)
+        if (gpio_is_valid(data->wp_pin))
                at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
+        if (gpio_is_valid(data->vcc_pin))
                at91_set_gpio_output(data->vcc_pin, 0);
        /* CLK */
@@ -248,8 +248,8 @@ static struct resource nand_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = AT91_BASE_SYS + AT91_ECC,
+                .start  = AT91SAM9RL_BASE_ECC,
-                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .end    = AT91SAM9RL_BASE_ECC + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -275,15 +275,15 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
        /* enable pin */
-        if (data->enable_pin)
+        if (gpio_is_valid(data->enable_pin))
                at91_set_gpio_output(data->enable_pin, 1);
        /* ready/busy pin */
-        if (data->rdy_pin)
+        if (gpio_is_valid(data->rdy_pin))
                at91_set_gpio_input(data->rdy_pin, 1);
        /* card detect pin */
-        if (data->det_pin)
+        if (gpio_is_valid(data->det_pin))
                at91_set_gpio_input(data->det_pin, 1);
        at91_set_A_periph(AT91_PIN_PB4, 0);             /* NANDOE */
@@ -483,7 +483,7 @@ void __init at91_add_device_ac97(struct ac97c_platform_data *data)
        at91_set_A_periph(AT91_PIN_PD4, 0);     /* AC97RX */
        /* reset */
-        if (data->reset_pin)
+        if (gpio_is_valid(data->reset_pin))
                at91_set_gpio_output(data->reset_pin, 0);
        ac97_data = *data;
@@ -685,8 +685,8 @@ static void __init at91_add_device_rtc(void) {}
 static struct resource rtt_resources[] = {
        {
-                .start  = AT91_BASE_SYS + AT91_RTT,
+                .start  = AT91SAM9RL_BASE_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .end    = AT91SAM9RL_BASE_RTT + SZ_16 - 1,
                .flags  = IORESOURCE_MEM,
        }
 };
@@ -709,10 +709,19 @@ static void __init at91_add_device_rtt(void)
 * -------------------------------------------------------------------- */
 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct resource wdt_resources[] = {
+        {
+                .start  = AT91SAM9RL_BASE_WDT,
+                .end    = AT91SAM9RL_BASE_WDT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
 static struct platform_device at91sam9rl_wdt_device = {
        .name           = "at91_wdt",
        .id             = -1,
-        .num_resources  = 0,
+        .resource       = wdt_resources,
+        .num_resources  = ARRAY_SIZE(wdt_resources),
 };
 static void __init at91_add_device_watchdog(void)
@@ -908,8 +917,8 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
 #if defined(CONFIG_SERIAL_ATMEL)
 static struct resource dbgu_resources[] = {
        [0] = {
-                .start  = AT91_BASE_SYS + AT91_DBGU,
+                .start  = AT91SAM9RL_BASE_DBGU,
-                .end    = AT91_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .end    = AT91SAM9RL_BASE_DBGU + SZ_512 - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 367d5cd5e36..2628384aaae 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -63,13 +63,15 @@ static void __init onearm_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata onearm_eth_data = {
+static struct macb_platform_data __initdata onearm_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC4,
        .is_rmii        = 1,
 };
 static struct at91_usbh_data __initdata onearm_usbh_data = {
        .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata onearm_udc_data = {
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 4282d96dffa..3bb40694b02 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -75,6 +75,8 @@ static void __init afeb9260_init_early(void)
 */
 static struct at91_usbh_data __initdata afeb9260_usbh_data = {
        .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -82,7 +84,7 @@ static struct at91_usbh_data __initdata afeb9260_usbh_data = {
 */
 static struct at91_udc_data __initdata afeb9260_udc_data = {
        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
@@ -103,7 +105,7 @@ static struct spi_board_info afeb9260_spi_devices[] = {
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata afeb9260_macb_data = {
+static struct macb_platform_data __initdata afeb9260_macb_data = {
        .phy_irq_pin    = AT91_PIN_PA9,
        .is_rmii        = 0,
 };
@@ -138,6 +140,7 @@ static struct atmel_nand_data __initdata afeb9260_nand_data = {
        .bus_width_16   = 0,
        .parts          = afeb9260_nand_partition,
        .num_parts      = ARRAY_SIZE(afeb9260_nand_partition),
+        .det_pin        = -EINVAL,
 };
@@ -149,6 +152,7 @@ static struct at91_mmc_data __initdata afeb9260_mmc_data = {
        .wp_pin         = AT91_PIN_PC4,
        .slot_b         = 1,
        .wire4          = 1,
+        .vcc_pin        = -EINVAL,
 };
@@ -169,6 +173,8 @@ static struct i2c_board_info __initdata afeb9260_i2c_devices[] = {
 static struct at91_cf_data afeb9260_cf_data = {
        .chipselect = 4,
        .irq_pin    = AT91_PIN_PA6,
+        .det_pin        = -EINVAL,
+        .vcc_pin        = -EINVAL,
        .rst_pin    = AT91_PIN_PA7,
        .flags      = AT91_CF_TRUE_IDE,
 };
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index f90cfb32bad..8510e9e5498 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -62,6 +62,8 @@ static void __init cam60_init_early(void)
 */
 static struct at91_usbh_data __initdata cam60_usbh_data = {
        .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
@@ -115,7 +117,7 @@ static struct spi_board_info cam60_spi_devices[] __initdata = {
 /*
 * MACB Ethernet device
 */
-static struct __initdata at91_eth_data cam60_macb_data = {
+static struct __initdata macb_platform_data cam60_macb_data = {
        .phy_irq_pin    = AT91_PIN_PB5,
        .is_rmii        = 0,
 };
@@ -135,7 +137,7 @@ static struct mtd_partition __initdata cam60_nand_partition[] = {
 static struct atmel_nand_data __initdata cam60_nand_data = {
        .ale            = 21,
        .cle            = 22,
-        // .det_pin     = ... not there
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PA9,
        .enable_pin     = AT91_PIN_PA7,
        .parts          = cam60_nand_partition,
@@ -163,7 +165,7 @@ static struct sam9_smc_config __initdata cam60_nand_smc_config = {
 static void __init cam60_add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &cam60_nand_smc_config);
+        sam9_smc_configure(0, 3, &cam60_nand_smc_config);
        at91_add_device_nand(&cam60_nand_data);
 }
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index 5dffd3be62d..ac3de4f7c31 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -70,6 +70,8 @@ static void __init cap9adk_init_early(void)
 */
 static struct at91_usbh_data __initdata cap9adk_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -144,16 +146,17 @@ static struct spi_board_info cap9adk_spi_devices[] = {
 */
 static struct at91_mmc_data __initdata cap9adk_mmc_data = {
        .wire4          = 1,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
-//      .wp_pin         = ... not connected
+        .wp_pin         = -EINVAL,
-//      .vcc_pin        = ... not connected
+        .vcc_pin        = -EINVAL,
 };
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata cap9adk_macb_data = {
+static struct macb_platform_data __initdata cap9adk_macb_data = {
+        .phy_irq_pin    = -EINVAL,
        .is_rmii        = 1,
 };
@@ -172,8 +175,8 @@ static struct mtd_partition __initdata cap9adk_nand_partitions[] = {
 static struct atmel_nand_data __initdata cap9adk_nand_data = {
        .ale            = 21,
        .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
-//      .rdy_pin        = ... not connected
+        .rdy_pin        = -EINVAL,
        .enable_pin     = AT91_PIN_PD15,
        .parts          = cap9adk_nand_partitions,
        .num_parts      = ARRAY_SIZE(cap9adk_nand_partitions),
@@ -212,7 +215,7 @@ static void __init cap9adk_add_device_nand(void)
                cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_8;
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &cap9adk_nand_smc_config);
+        sam9_smc_configure(0, 3, &cap9adk_nand_smc_config);
        at91_add_device_nand(&cap9adk_nand_data);
 }
@@ -282,7 +285,7 @@ static __init void cap9adk_add_device_nor(void)
        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
        /* configure chip-select 0 (NOR) */
-        sam9_smc_configure(0, &cap9adk_nor_smc_config);
+        sam9_smc_configure(0, 0, &cap9adk_nor_smc_config);
        platform_device_register(&cap9adk_nor_flash);
 }
@@ -351,7 +354,7 @@ static struct atmel_lcdfb_info __initdata cap9adk_lcdc_data;
 * AC97
 */
 static struct ac97c_platform_data cap9adk_ac97_data = {
-//      .reset_pin      = ... not connected
+        .reset_pin      = -EINVAL,
 };
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 774c87fcbd5..59d9cf99753 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -57,13 +57,15 @@ static void __init carmeva_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata carmeva_eth_data = {
+static struct macb_platform_data __initdata carmeva_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC4,
        .is_rmii        = 1,
 };
 static struct at91_usbh_data __initdata carmeva_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata carmeva_udc_data = {
@@ -75,8 +77,8 @@ static struct at91_udc_data __initdata carmeva_udc_data = {
 // static struct at91_cf_data __initdata carmeva_cf_data = {
 //      .det_pin        = AT91_PIN_PB0,
 //      .rst_pin        = AT91_PIN_PC5,
-        // .irq_pin     = ... not connected
+        // .irq_pin     = -EINVAL,
-        // .vcc_pin     = ... always powered
+        // .vcc_pin     = -EINVAL,
 // };
 static struct at91_mmc_data __initdata carmeva_mmc_data = {
@@ -84,6 +86,7 @@ static struct at91_mmc_data __initdata carmeva_mmc_data = {
        .wire4          = 1,
        .det_pin        = AT91_PIN_PB10,
        .wp_pin         = AT91_PIN_PC14,
+        .vcc_pin        = -EINVAL,
 };
 static struct spi_board_info carmeva_spi_devices[] = {
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index fc885a4ce24..9ab3d1ea326 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -86,6 +86,8 @@ static void __init cpu9krea_init_early(void)
 */
 static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -93,13 +95,14 @@ static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
 */
 static struct at91_udc_data __initdata cpu9krea_udc_data = {
        .vbus_pin       = AT91_PIN_PC8,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata cpu9krea_macb_data = {
+static struct macb_platform_data __initdata cpu9krea_macb_data = {
+        .phy_irq_pin    = -EINVAL,
        .is_rmii        = 1,
 };
@@ -112,6 +115,7 @@ static struct atmel_nand_data __initdata cpu9krea_nand_data = {
        .rdy_pin        = AT91_PIN_PC13,
        .enable_pin     = AT91_PIN_PC14,
        .bus_width_16   = 0,
+        .det_pin        = -EINVAL,
 };
 #ifdef CONFIG_MACH_CPU9260
@@ -156,7 +160,7 @@ static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
 static void __init cpu9krea_add_device_nand(void)
 {
-        sam9_smc_configure(3, &cpu9krea_nand_smc_config);
+        sam9_smc_configure(0, 3, &cpu9krea_nand_smc_config);
        at91_add_device_nand(&cpu9krea_nand_data);
 }
@@ -238,7 +242,7 @@ static __init void cpu9krea_add_device_nor(void)
        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
        /* configure chip-select 0 (NOR) */
-        sam9_smc_configure(0, &cpu9krea_nor_smc_config);
+        sam9_smc_configure(0, 0, &cpu9krea_nor_smc_config);
        platform_device_register(&cpu9krea_nor_flash);
 }
@@ -337,6 +341,8 @@ static struct at91_mmc_data __initdata cpu9krea_mmc_data = {
        .slot_b         = 0,
        .wire4          = 1,
        .det_pin        = AT91_PIN_PA29,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 static void __init cpu9krea_board_init(void)
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index d35e65b08cc..368e1427ad9 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -82,12 +82,15 @@ static void __init cpuat91_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata cpuat91_eth_data = {
+static struct macb_platform_data __initdata cpuat91_eth_data = {
+        .phy_irq_pin    = -EINVAL,
        .is_rmii        = 1,
 };
 static struct at91_usbh_data __initdata cpuat91_usbh_data = {
        .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata cpuat91_udc_data = {
@@ -98,6 +101,8 @@ static struct at91_udc_data __initdata cpuat91_udc_data = {
 static struct at91_mmc_data __initdata cpuat91_mmc_data = {
        .det_pin        = AT91_PIN_PC2,
        .wire4          = 1,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 static struct physmap_flash_data cpuat91_flash_data = {
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index c3936665e64..1a1547b1ce4 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -58,18 +58,20 @@ static void __init csb337_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata csb337_eth_data = {
+static struct macb_platform_data __initdata csb337_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC2,
        .is_rmii        = 0,
 };
 static struct at91_usbh_data __initdata csb337_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata csb337_udc_data = {
-        // this has no VBUS sensing pin
        .pullup_pin     = AT91_PIN_PA24,
+        .vbus_pin       = -EINVAL,
 };
 static struct i2c_board_info __initdata csb337_i2c_devices[] = {
@@ -98,6 +100,7 @@ static struct at91_mmc_data __initdata csb337_mmc_data = {
        .slot_b         = 0,
        .wire4          = 1,
        .wp_pin         = AT91_PIN_PD6,
+        .vcc_pin        = -EINVAL,
 };
 static struct spi_board_info csb337_spi_devices[] = {
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 586100e2acb..f650bf39455 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -52,13 +52,15 @@ static void __init csb637_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata csb637_eth_data = {
+static struct macb_platform_data __initdata csb637_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC0,
        .is_rmii        = 0,
 };
 static struct at91_usbh_data __initdata csb637_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata csb637_udc_data = {
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index 0b7d3277821..bb6b434ec0c 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -50,6 +50,7 @@ static void __init ek_init_early(void)
 static struct atmel_nand_data __initdata ek_nand_data = {
        .ale            = 21,
        .cle            = 22,
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PC8,
        .enable_pin     = AT91_PIN_PC14,
 };
@@ -82,7 +83,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index 45db7a3dbef..d302ca3eeb6 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -60,13 +60,15 @@ static void __init eb9200_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata eb9200_eth_data = {
+static struct macb_platform_data __initdata eb9200_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC4,
        .is_rmii        = 1,
 };
 static struct at91_usbh_data __initdata eb9200_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata eb9200_udc_data = {
@@ -75,15 +77,18 @@ static struct at91_udc_data __initdata eb9200_udc_data = {
 };
 static struct at91_cf_data __initdata eb9200_cf_data = {
+        .irq_pin        = -EINVAL,
        .det_pin        = AT91_PIN_PB0,
+        .vcc_pin        = -EINVAL,
        .rst_pin        = AT91_PIN_PC5,
-        // .irq_pin     = ... not connected
-        // .vcc_pin     = ... always powered
 };
 static struct at91_mmc_data __initdata eb9200_mmc_data = {
        .slot_b         = 0,
        .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 2f9c16d2921..69966ce4d77 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -64,18 +64,23 @@ static void __init ecb_at91init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata ecb_at91eth_data = {
+static struct macb_platform_data __initdata ecb_at91eth_data = {
        .phy_irq_pin    = AT91_PIN_PC4,
        .is_rmii        = 0,
 };
 static struct at91_usbh_data __initdata ecb_at91usbh_data = {
        .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_mmc_data __initdata ecb_at91mmc_data = {
        .slot_b         = 0,
        .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 8252c722607..07ef35b0ec2 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -47,13 +47,15 @@ static void __init eco920_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata eco920_eth_data = {
+static struct macb_platform_data __initdata eco920_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC2,
        .is_rmii        = 1,
 };
 static struct at91_usbh_data __initdata eco920_usbh_data = {
        .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata eco920_udc_data = {
@@ -64,6 +66,9 @@ static struct at91_udc_data __initdata eco920_udc_data = {
 static struct at91_mmc_data __initdata eco920_mmc_data = {
        .slot_b         = 0,
        .wire4          = 0,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 static struct physmap_flash_data eco920_flash_data = {
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 4c3f65d9c59..eec02cd57ce 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -52,12 +52,14 @@ static void __init flexibity_init_early(void)
 /* USB Host port */
 static struct at91_usbh_data __initdata flexibity_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /* USB Device port */
 static struct at91_udc_data __initdata flexibity_udc_data = {
        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 /* SPI devices */
@@ -76,6 +78,7 @@ static struct at91_mmc_data __initdata flexibity_mmc_data = {
        .wire4          = 1,
        .det_pin        = AT91_PIN_PC9,
        .wp_pin         = AT91_PIN_PC4,
+        .vcc_pin        = -EINVAL,
 };
 /* LEDs */
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index f27d1a780cf..caf017f0f4e 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -106,6 +106,8 @@ static void __init foxg20_init_early(void)
 */
 static struct at91_usbh_data __initdata foxg20_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -113,7 +115,7 @@ static struct at91_usbh_data __initdata foxg20_usbh_data = {
 */
 static struct at91_udc_data __initdata foxg20_udc_data = {
        .vbus_pin       = AT91_PIN_PC6,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
@@ -135,7 +137,7 @@ static struct spi_board_info foxg20_spi_devices[] = {
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata foxg20_macb_data = {
+static struct macb_platform_data __initdata foxg20_macb_data = {
        .phy_irq_pin    = AT91_PIN_PA7,
        .is_rmii        = 1,
 };
@@ -147,6 +149,9 @@ static struct at91_eth_data __initdata foxg20_macb_data = {
 static struct at91_mmc_data __initdata foxg20_mmc_data = {
        .slot_b         = 1,
        .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index 2e95949737e..230e71969fb 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -80,6 +80,8 @@ static void __init gsia18s_init_early(void)
 */
 static struct at91_usbh_data __initdata usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -87,13 +89,13 @@ static struct at91_usbh_data __initdata usbh_data = {
 */
 static struct at91_udc_data __initdata udc_data = {
        .vbus_pin       = AT91_PIN_PA22,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata macb_data = {
+static struct macb_platform_data __initdata macb_data = {
        .phy_irq_pin    = AT91_PIN_PA28,
        .is_rmii        = 1,
 };
@@ -530,6 +532,7 @@ static struct i2c_board_info __initdata gsia18s_i2c_devices[] = {
 static struct at91_cf_data __initdata gsia18s_cf1_data = {
        .irq_pin        = AT91_PIN_PA27,
        .det_pin        = AT91_PIN_PB30,
+        .vcc_pin        = -EINVAL,
        .rst_pin        = AT91_PIN_PB31,
        .chipselect     = 5,
        .flags          = AT91_CF_TRUE_IDE,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 3bae73e6363..efde1b2327c 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -61,13 +61,15 @@ static void __init kafa_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata kafa_eth_data = {
+static struct macb_platform_data __initdata kafa_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC4,
        .is_rmii        = 0,
 };
 static struct at91_usbh_data __initdata kafa_usbh_data = {
        .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata kafa_udc_data = {
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index e61351ffad5..d75a4a2ad9c 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -69,13 +69,15 @@ static void __init kb9202_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata kb9202_eth_data = {
+static struct macb_platform_data __initdata kb9202_eth_data = {
        .phy_irq_pin    = AT91_PIN_PB29,
        .is_rmii        = 0,
 };
 static struct at91_usbh_data __initdata kb9202_usbh_data = {
        .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata kb9202_udc_data = {
@@ -87,6 +89,8 @@ static struct at91_mmc_data __initdata kb9202_mmc_data = {
        .det_pin        = AT91_PIN_PB2,
        .slot_b         = 0,
        .wire4          = 1,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 static struct mtd_partition __initdata kb9202_nand_partition[] = {
@@ -100,7 +104,7 @@ static struct mtd_partition __initdata kb9202_nand_partition[] = {
 static struct atmel_nand_data __initdata kb9202_nand_data = {
        .ale            = 22,
        .cle            = 21,
-        // .det_pin     = ... not there
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PC29,
        .enable_pin     = AT91_PIN_PC28,
        .parts          = kb9202_nand_partition,
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index ef816c17dc6..3f8617c0e04 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -72,6 +72,7 @@ static void __init neocore926_init_early(void)
 static struct at91_usbh_data __initdata neocore926_usbh_data = {
        .ports          = 2,
        .vbus_pin       = { AT91_PIN_PA24, AT91_PIN_PA21 },
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -79,7 +80,7 @@ static struct at91_usbh_data __initdata neocore926_usbh_data = {
 */
 static struct at91_udc_data __initdata neocore926_udc_data = {
        .vbus_pin       = AT91_PIN_PA25,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
@@ -149,13 +150,14 @@ static struct at91_mmc_data __initdata neocore926_mmc_data = {
        .wire4          = 1,
        .det_pin        = AT91_PIN_PE18,
        .wp_pin         = AT91_PIN_PE19,
+        .vcc_pin        = -EINVAL,
 };
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata neocore926_macb_data = {
+static struct macb_platform_data __initdata neocore926_macb_data = {
        .phy_irq_pin    = AT91_PIN_PE31,
        .is_rmii        = 1,
 };
@@ -190,6 +192,7 @@ static struct atmel_nand_data __initdata neocore926_nand_data = {
        .enable_pin             = AT91_PIN_PD15,
        .parts                  = neocore926_nand_partition,
        .num_parts              = ARRAY_SIZE(neocore926_nand_partition),
+        .det_pin                = -EINVAL,
 };
 static struct sam9_smc_config __initdata neocore926_nand_smc_config = {
@@ -213,7 +216,7 @@ static struct sam9_smc_config __initdata neocore926_nand_smc_config = {
 static void __init neocore926_add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &neocore926_nand_smc_config);
+        sam9_smc_configure(0, 3, &neocore926_nand_smc_config);
        at91_add_device_nand(&neocore926_nand_data);
 }
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 49e3f699b48..b4a12fc184c 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -96,9 +96,9 @@ static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
 static void __init add_device_pcontrol(void)
 {
        /* configure chip-select 4 (IO compatible to 8051  X4 ) */
-        sam9_smc_configure(4, &pcontrol_smc_config[0]);
+        sam9_smc_configure(0, 4, &pcontrol_smc_config[0]);
        /* configure chip-select 7 (FerroRAM 256KiBx16bit MR2A16A  D4 ) */
-        sam9_smc_configure(7, &pcontrol_smc_config[1]);
+        sam9_smc_configure(0, 7, &pcontrol_smc_config[1]);
 }
@@ -107,6 +107,8 @@ static void __init add_device_pcontrol(void)
 */
 static struct at91_usbh_data __initdata usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
@@ -122,7 +124,7 @@ static struct at91_udc_data __initdata pcontrol_g20_udc_data = {
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata macb_data = {
+static struct macb_platform_data __initdata macb_data = {
        .phy_irq_pin    = AT91_PIN_PA28,
        .is_rmii        = 1,
 };
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 0a8fe6a1b7c..ab024fa11d5 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -60,13 +60,15 @@ static void __init picotux200_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata picotux200_eth_data = {
+static struct macb_platform_data __initdata picotux200_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC4,
        .is_rmii        = 1,
 };
 static struct at91_usbh_data __initdata picotux200_usbh_data = {
        .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_mmc_data __initdata picotux200_mmc_data = {
@@ -74,6 +76,7 @@ static struct at91_mmc_data __initdata picotux200_mmc_data = {
        .slot_b         = 0,
        .wire4          = 1,
        .wp_pin         = AT91_PIN_PA17,
+        .vcc_pin        = -EINVAL,
 };
 #define PICOTUX200_FLASH_BASE   AT91_CHIPSELECT_0
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 07421bdb88e..e029d220cb8 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -77,6 +77,8 @@ static void __init ek_init_early(void)
 */
 static struct at91_usbh_data __initdata ek_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -84,7 +86,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
 */
 static struct at91_udc_data __initdata ek_udc_data = {
        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 /*
@@ -104,7 +106,7 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
        .phy_irq_pin    = AT91_PIN_PA31,
        .is_rmii        = 1,
 };
@@ -133,7 +135,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
        .ale            = 21,
        .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PC13,
        .enable_pin     = AT91_PIN_PC14,
        .parts          = ek_nand_partition,
@@ -161,7 +163,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 static void __init ek_add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
@@ -172,9 +174,9 @@ static void __init ek_add_device_nand(void)
 static struct at91_mmc_data __initdata ek_mmc_data = {
        .slot_b         = 0,
        .wire4          = 1,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
-//      .wp_pin         = ... not connected
+        .wp_pin         = -EINVAL,
-//      .vcc_pin        = ... not connected
+        .vcc_pin        = -EINVAL,
 };
 /*
@@ -251,7 +253,7 @@ static void __init ek_board_init(void)
        /* LEDs */
        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
        /* shutdown controller, wakeup button (5 msec low) */
-        at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
+        at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
                                | AT91_SHDW_RTTWKEN);
 }
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 80a8c9c6e92..782f37946af 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -65,13 +65,15 @@ static void __init dk_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata dk_eth_data = {
+static struct macb_platform_data __initdata dk_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC4,
        .is_rmii        = 1,
 };
 static struct at91_usbh_data __initdata dk_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata dk_udc_data = {
@@ -80,16 +82,19 @@ static struct at91_udc_data __initdata dk_udc_data = {
 };
 static struct at91_cf_data __initdata dk_cf_data = {
+        .irq_pin        = -EINVAL,
        .det_pin        = AT91_PIN_PB0,
+        .vcc_pin        = -EINVAL,
        .rst_pin        = AT91_PIN_PC5,
-        // .irq_pin     = ... not connected
-        // .vcc_pin     = ... always powered
 };
 #ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
 static struct at91_mmc_data __initdata dk_mmc_data = {
        .slot_b         = 0,
        .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 #endif
@@ -143,7 +148,7 @@ static struct atmel_nand_data __initdata dk_nand_data = {
        .cle            = 21,
        .det_pin        = AT91_PIN_PB1,
        .rdy_pin        = AT91_PIN_PC2,
-        // .enable_pin  = ... not there
+        .enable_pin     = -EINVAL,
        .parts          = dk_nand_partition,
        .num_parts      = ARRAY_SIZE(dk_nand_partition),
 };
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 99fd7f8aee0..ef7c12a9224 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -65,13 +65,15 @@ static void __init ek_init_early(void)
        at91_set_serial_console(0);
 }
-static struct at91_eth_data __initdata ek_eth_data = {
+static struct macb_platform_data __initdata ek_eth_data = {
        .phy_irq_pin    = AT91_PIN_PC4,
        .is_rmii        = 1,
 };
 static struct at91_usbh_data __initdata ek_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata ek_udc_data = {
@@ -85,6 +87,7 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
        .slot_b         = 0,
        .wire4          = 1,
        .wp_pin         = AT91_PIN_PA17,
+        .vcc_pin        = -EINVAL,
 };
 #endif
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index e927df0175d..af0750fafa2 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -60,7 +60,7 @@ static void __init rsi_ews_init_early(void)
 /*
 * Ethernet
 */
-static struct at91_eth_data rsi_ews_eth_data __initdata = {
+static struct macb_platform_data rsi_ews_eth_data __initdata = {
        .phy_irq_pin    = AT91_PIN_PC4,
        .is_rmii        = 1,
 };
@@ -70,6 +70,8 @@ static struct at91_eth_data rsi_ews_eth_data __initdata = {
 */
 static struct at91_usbh_data rsi_ews_usbh_data __initdata = {
        .ports          = 1,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 072d53af98d..84bce587735 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -72,6 +72,8 @@ static void __init ek_init_early(void)
 */
 static struct at91_usbh_data __initdata ek_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -79,7 +81,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
 */
 static struct at91_udc_data __initdata ek_udc_data = {
        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
@@ -109,7 +111,7 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
        .phy_irq_pin    = AT91_PIN_PA7,
        .is_rmii        = 0,
 };
@@ -134,7 +136,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
        .ale            = 21,
        .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PC13,
        .enable_pin     = AT91_PIN_PC14,
        .parts          = ek_nand_partition,
@@ -162,7 +164,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 static void __init ek_add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
@@ -176,7 +178,7 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
        .wire4          = 1,
        .det_pin        = AT91_PIN_PC8,
        .wp_pin         = AT91_PIN_PC4,
-//      .vcc_pin        = ... not connected
+        .vcc_pin        = -EINVAL,
 };
 static void __init ek_board_init(void)
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 4f10181a078..be8233bcabd 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -75,6 +75,8 @@ static void __init ek_init_early(void)
 */
 static struct at91_usbh_data __initdata ek_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -82,7 +84,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
 */
 static struct at91_udc_data __initdata ek_udc_data = {
        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
@@ -151,7 +153,7 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
        .phy_irq_pin    = AT91_PIN_PA7,
        .is_rmii        = 1,
 };
@@ -176,7 +178,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
        .ale            = 21,
        .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PC13,
        .enable_pin     = AT91_PIN_PC14,
        .parts          = ek_nand_partition,
@@ -211,7 +213,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
@@ -223,9 +225,9 @@ static void __init ek_add_device_nand(void)
 static struct at91_mmc_data __initdata ek_mmc_data = {
        .slot_b         = 1,
        .wire4          = 1,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
-//      .wp_pin         = ... not connected
+        .wp_pin         = -EINVAL,
-//      .vcc_pin        = ... not connected
+        .vcc_pin        = -EINVAL,
 };
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index b005b738e8f..40895072a1a 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -131,7 +131,7 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
 static void __init ek_add_device_dm9000(void)
 {
        /* Configure chip-select 2 (DM9000) */
-        sam9_smc_configure(2, &dm9000_smc_config);
+        sam9_smc_configure(0, 2, &dm9000_smc_config);
        /* Configure Reset signal as output */
        at91_set_gpio_output(AT91_PIN_PC10, 0);
@@ -151,6 +151,8 @@ static void __init ek_add_device_dm9000(void) {}
 */
 static struct at91_usbh_data __initdata ek_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
@@ -159,7 +161,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
 */
 static struct at91_udc_data __initdata ek_udc_data = {
        .vbus_pin       = AT91_PIN_PB29,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
@@ -182,7 +184,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
        .ale            = 22,
        .cle            = 21,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PC15,
        .enable_pin     = AT91_PIN_PC14,
        .parts          = ek_nand_partition,
@@ -217,7 +219,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
@@ -345,6 +347,9 @@ static struct spi_board_info ek_spi_devices[] = {
 */
 static struct at91_mmc_data __initdata ek_mmc_data = {
        .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 #endif /* CONFIG_SPI_ATMEL_* */
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index bccdcf23caa..29f66052fe6 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -74,6 +74,7 @@ static void __init ek_init_early(void)
 static struct at91_usbh_data __initdata ek_usbh_data = {
        .ports          = 2,
        .vbus_pin       = { AT91_PIN_PA24, AT91_PIN_PA21 },
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -81,7 +82,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
 */
 static struct at91_udc_data __initdata ek_udc_data = {
        .vbus_pin       = AT91_PIN_PA25,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
@@ -151,14 +152,14 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
        .wire4          = 1,
        .det_pin        = AT91_PIN_PE18,
        .wp_pin         = AT91_PIN_PE19,
-//      .vcc_pin        = ... not connected
+        .vcc_pin        = -EINVAL,
 };
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
        .phy_irq_pin    = AT91_PIN_PE31,
        .is_rmii        = 1,
 };
@@ -183,7 +184,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
        .ale            = 21,
        .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PA22,
        .enable_pin     = AT91_PIN_PD15,
        .parts          = ek_nand_partition,
@@ -218,7 +219,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
@@ -353,6 +354,7 @@ static void __init ek_add_device_buttons(void) {}
 * reset_pin is not connected: NRST
 */
 static struct ac97c_platform_data ek_ac97_data = {
+        .reset_pin      = -EINVAL,
 };
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 64fc75c9d0a..843d6286c6f 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -86,6 +86,8 @@ static void __init ek_init_early(void)
 */
 static struct at91_usbh_data __initdata ek_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -93,7 +95,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
 */
 static struct at91_udc_data __initdata ek_udc_data = {
        .vbus_pin       = AT91_PIN_PC5,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
@@ -123,7 +125,7 @@ static struct spi_board_info ek_spi_devices[] = {
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
        .phy_irq_pin    = AT91_PIN_PA7,
        .is_rmii        = 1,
 };
@@ -163,6 +165,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
        .cle            = 22,
        .rdy_pin        = AT91_PIN_PC13,
        .enable_pin     = AT91_PIN_PC14,
+        .det_pin        = -EINVAL,
        .parts          = ek_nand_partition,
        .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
@@ -195,7 +198,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
@@ -210,6 +213,7 @@ static struct mci_platform_data __initdata ek_mmc_data = {
        .slot[1] = {
                .bus_width      = 4,
                .detect_pin     = AT91_PIN_PC9,
+                .wp_pin         = -EINVAL,
        },
 };
@@ -218,6 +222,8 @@ static struct at91_mmc_data __initdata ek_mmc_data = {
        .slot_b         = 1,    /* Only one slot so use slot B */
        .wire4          = 1,
        .det_pin        = AT91_PIN_PC9,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 #endif
@@ -227,6 +233,7 @@ static void __init ek_add_device_mmc(void)
        if (ek_have_2mmc()) {
                ek_mmc_data.slot[0].bus_width = 4;
                ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
+                ek_mmc_data.slot[0].wp_pin = -1;
        }
        at91_add_device_mci(0, &ek_mmc_data);
 #else
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 92de9127923..ea0d1b9c2b7 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -69,6 +69,7 @@ static void __init ek_init_early(void)
 static struct at91_usbh_data __initdata ek_usbh_hs_data = {
        .ports          = 2,
        .vbus_pin       = {AT91_PIN_PD1, AT91_PIN_PD3},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
@@ -100,6 +101,7 @@ static struct mci_platform_data __initdata mci0_data = {
        .slot[0] = {
                .bus_width      = 4,
                .detect_pin     = AT91_PIN_PD10,
+                .wp_pin         = -EINVAL,
        },
 };
@@ -115,7 +117,7 @@ static struct mci_platform_data __initdata mci1_data = {
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
        .phy_irq_pin    = AT91_PIN_PD5,
        .is_rmii        = 1,
 };
@@ -143,6 +145,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
        .cle            = 22,
        .rdy_pin        = AT91_PIN_PC8,
        .enable_pin     = AT91_PIN_PC14,
+        .det_pin        = -EINVAL,
        .parts          = ek_nand_partition,
        .num_parts      = ARRAY_SIZE(ek_nand_partition),
 };
@@ -175,7 +178,7 @@ static void __init ek_add_device_nand(void)
                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
@@ -330,6 +333,7 @@ static void __init ek_add_device_buttons(void) {}
 * reset_pin is not connected: NRST
 */
 static struct ac97c_platform_data ek_ac97_data = {
+        .reset_pin      = -EINVAL,
 };
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index b2b748239f3..c1366d0032b 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -67,8 +67,8 @@ static struct usba_platform_data __initdata ek_usba_udc_data = {
 static struct at91_mmc_data __initdata ek_mmc_data = {
        .wire4          = 1,
        .det_pin        = AT91_PIN_PA15,
-//      .wp_pin         = ... not connected
+        .wp_pin         = -EINVAL,
-//      .vcc_pin        = ... not connected
+        .vcc_pin        = -EINVAL,
 };
@@ -91,7 +91,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
        .ale            = 21,
        .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PD17,
        .enable_pin     = AT91_PIN_PB6,
        .parts          = ek_nand_partition,
@@ -119,7 +119,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 static void __init ek_add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &ek_nand_smc_config);
+        sam9_smc_configure(0, 3, &ek_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
@@ -204,6 +204,7 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data;
 * reset_pin is not connected: NRST
 */
 static struct ac97c_platform_data ek_ac97_data = {
+        .reset_pin      = -EINVAL,
 };
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 0df01c6e2d0..4770db08e5a 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -57,15 +57,19 @@ static void __init snapper9260_init_early(void)
 static struct at91_usbh_data __initdata snapper9260_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 static struct at91_udc_data __initdata snapper9260_udc_data = {
        .vbus_pin               = SNAPPER9260_IO_EXP_GPIO(5),
        .vbus_active_low        = 1,
        .vbus_polled            = 1,
+        .pullup_pin             = -EINVAL,
 };
-static struct at91_eth_data snapper9260_macb_data = {
+static struct macb_platform_data snapper9260_macb_data = {
+        .phy_irq_pin    = -EINVAL,
        .is_rmii        = 1,
 };
@@ -104,6 +108,8 @@ static struct atmel_nand_data __initdata snapper9260_nand_data = {
        .parts          = snapper9260_nand_partitions,
        .num_parts      = ARRAY_SIZE(snapper9260_nand_partitions),
        .bus_width_16   = 0,
+        .enable_pin     = -EINVAL,
+        .det_pin        = -EINVAL,
 };
 static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
@@ -149,7 +155,7 @@ static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
 static void __init snapper9260_add_device_nand(void)
 {
        at91_set_A_periph(AT91_PIN_PC14, 0);
-        sam9_smc_configure(3, &snapper9260_nand_smc_config);
+        sam9_smc_configure(0, 3, &snapper9260_nand_smc_config);
        at91_add_device_nand(&snapper9260_nand_data);
 }
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index 936e5fd7f40..72eb3b4d9ab 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -85,6 +85,7 @@ static struct atmel_nand_data __initdata nand_data = {
        .rdy_pin        = AT91_PIN_PC13,
        .enable_pin     = AT91_PIN_PC14,
        .bus_width_16   = 0,
+        .det_pin        = -EINVAL,
 };
 static struct sam9_smc_config __initdata nand_smc_config = {
@@ -108,7 +109,7 @@ static struct sam9_smc_config __initdata nand_smc_config = {
 static void __init add_device_nand(void)
 {
        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &nand_smc_config);
+        sam9_smc_configure(0, 3, &nand_smc_config);
        at91_add_device_nand(&nand_data);
 }
@@ -122,12 +123,17 @@ static void __init add_device_nand(void)
 static struct mci_platform_data __initdata mmc_data = {
        .slot[0] = {
                .bus_width      = 4,
+                .detect_pin     = -1,
+                .wp_pin         = -1,
        },
 };
 #else
 static struct at91_mmc_data __initdata mmc_data = {
        .slot_b         = 0,
        .wire4          = 1,
+        .det_pin        = -EINVAL,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 #endif
@@ -137,6 +143,8 @@ static struct at91_mmc_data __initdata mmc_data = {
 */
 static struct at91_usbh_data __initdata usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
@@ -145,19 +153,19 @@ static struct at91_usbh_data __initdata usbh_data = {
 */
 static struct at91_udc_data __initdata portuxg20_udc_data = {
        .vbus_pin       = AT91_PIN_PC7,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
        .vbus_pin       = AT91_PIN_PA22,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata macb_data = {
+static struct macb_platform_data __initdata macb_data = {
        .phy_irq_pin    = AT91_PIN_PA28,
        .is_rmii        = 1,
 };
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 0a20bab21f9..26c36fc2d1e 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -66,6 +66,8 @@ static void __init ek_init_early(void)
 */
 static struct at91_usbh_data __initdata ek_usbh_data = {
        .ports          = 2,
+        .vbus_pin       = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -73,7 +75,7 @@ static struct at91_usbh_data __initdata ek_usbh_data = {
 */
 static struct at91_udc_data __initdata ek_udc_data = {
        .vbus_pin       = AT91_PIN_PB11,
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
+        .pullup_pin     = -EINVAL,              /* pull-up driven by UDC */
 };
 static void __init ek_add_device_udc(void)
@@ -146,7 +148,7 @@ static void __init ek_add_device_spi(void)
 /*
 * MACB Ethernet device
 */
-static struct at91_eth_data __initdata ek_macb_data = {
+static struct macb_platform_data __initdata ek_macb_data = {
        .phy_irq_pin    = AT91_PIN_PE31,
        .is_rmii        = 1,
 };
@@ -193,7 +195,7 @@ static struct mtd_partition __initdata ek_nand_partition[] = {
 static struct atmel_nand_data __initdata ek_nand_data = {
        .ale            = 21,
        .cle            = 22,
-//      .det_pin        = ... not connected
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PA22,
        .enable_pin     = AT91_PIN_PD15,
        .parts          = ek_nand_partition,
@@ -245,9 +247,9 @@ static void __init ek_add_device_nand(void)
        /* configure chip-select 3 (NAND) */
        if (machine_is_usb_a9g20())
-                sam9_smc_configure(3, &usb_a9g20_nand_smc_config);
+                sam9_smc_configure(0, 3, &usb_a9g20_nand_smc_config);
        else
-                sam9_smc_configure(3, &usb_a9260_nand_smc_config);
+                sam9_smc_configure(0, 3, &usb_a9260_nand_smc_config);
        at91_add_device_nand(&ek_nand_data);
 }
@@ -344,7 +346,7 @@ static void __init ek_board_init(void)
                /* I2C */
                at91_add_device_i2c(NULL, 0);
                /* shutdown controller, wakeup button (5 msec low) */
-                at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10)
+                at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10)
                                | AT91_SHDW_WKMODE0_LOW
                                | AT91_SHDW_RTTWKEN);
        }
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index 12a3f955162..bbd553e1cd9 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -110,7 +110,7 @@ static struct gpio_led yl9200_leds[] = {
 /*
 * Ethernet
 */
-static struct at91_eth_data __initdata yl9200_eth_data = {
+static struct macb_platform_data __initdata yl9200_eth_data = {
        .phy_irq_pin            = AT91_PIN_PB28,
        .is_rmii                = 1,
 };
@@ -120,6 +120,8 @@ static struct at91_eth_data __initdata yl9200_eth_data = {
 */
 static struct at91_usbh_data __initdata yl9200_usbh_data = {
        .ports                  = 1,    /* PQFP version of AT91RM9200 */
+        .vbus_pin               = {-EINVAL, -EINVAL},
+        .overcurrent_pin= {-EINVAL, -EINVAL},
 };
 /*
@@ -137,8 +139,9 @@ static struct at91_udc_data __initdata yl9200_udc_data = {
 */
 static struct at91_mmc_data __initdata yl9200_mmc_data = {
        .det_pin        = AT91_PIN_PB9,
-        // .wp_pin      = ... not connected
        .wire4          = 1,
+        .wp_pin         = -EINVAL,
+        .vcc_pin        = -EINVAL,
 };
 /*
@@ -175,7 +178,7 @@ static struct mtd_partition __initdata yl9200_nand_partition[] = {
 static struct atmel_nand_data __initdata yl9200_nand_data = {
        .ale            = 6,
        .cle            = 7,
-        // .det_pin     = ... not connected
+        .det_pin        = -EINVAL,
        .rdy_pin        = AT91_PIN_PC14,        /* R/!B (Sheet10) */
        .enable_pin     = AT91_PIN_PC15,        /* !CE  (Sheet10) */
        .parts          = yl9200_nand_partition,
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 938b34f5774..4866b8180d6 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -29,6 +29,7 @@ extern void __init at91_aic_init(unsigned int priority[]);
 /* Timer */
 struct sys_timer;
 extern struct sys_timer at91rm9200_timer;
+extern void at91sam926x_ioremap_pit(u32 addr);
 extern struct sys_timer at91sam926x_timer;
 extern struct sys_timer at91x40_timer;
@@ -57,7 +58,10 @@ extern void at91_irq_suspend(void);
 extern void at91_irq_resume(void);
 /* reset */
-extern void at91sam9_alt_reset(void);
+extern void at91sam9_alt_restart(char, const char *);
+/* shutdown */
+extern void at91_ioremap_shdwc(u32 base_addr);
 /* GPIO */
 #define AT91RM9200_PQFP         3       /* AT91RM9200 PQFP package has 3 banks */
@@ -65,11 +69,9 @@ extern void at91sam9_alt_reset(void);
 struct at91_gpio_bank {
        unsigned short id;              /* peripheral ID */
-        unsigned long offset;           /* offset from system peripheral base */
+        unsigned long regbase;          /* offset from system peripheral base */
-        struct clk *clock;              /* associated clock */
 };
 extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
 extern void __init at91_gpio_irq_setup(void);
-extern void (*at91_arch_reset)(void);
 extern int at91_extern_irq;
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 224e9e2f867..74d6783eeab 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -29,8 +29,9 @@
 struct at91_gpio_chip {
        struct gpio_chip        chip;
        struct at91_gpio_chip   *next;          /* Bank sharing same clock */
-        struct at91_gpio_bank   *bank;          /* Bank definition */
+        int                     id;             /* ID of register bank */
        void __iomem            *regbase;       /* Base of register bank */
+        struct clk              *clock;         /* associated clock */
 };
 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
@@ -58,18 +59,17 @@ static int at91_gpiolib_direction_input(struct gpio_chip *chip,
        }
 static struct at91_gpio_chip gpio_chip[] = {
-        AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32),
+        AT91_GPIO_CHIP("pioA", 0x00, 32),
-        AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32),
+        AT91_GPIO_CHIP("pioB", 0x20, 32),
-        AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32),
+        AT91_GPIO_CHIP("pioC", 0x40, 32),
-        AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32),
+        AT91_GPIO_CHIP("pioD", 0x60, 32),
-        AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32),
+        AT91_GPIO_CHIP("pioE", 0x80, 32),
 };
 static int gpio_banks;
 static inline void __iomem *pin_to_controller(unsigned pin)
 {
-        pin -= PIN_BASE;
        pin /= 32;
        if (likely(pin < gpio_banks))
                return gpio_chip[pin].regbase;
@@ -79,7 +79,6 @@ static inline void __iomem *pin_to_controller(unsigned pin)
 static inline unsigned pin_to_mask(unsigned pin)
 {
-        pin -= PIN_BASE;
        return 1 << (pin % 32);
 }
@@ -274,8 +273,9 @@ static u32 backups[MAX_GPIO_BANKS];
 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
 {
-        unsigned        mask = pin_to_mask(d->irq);
+        unsigned        pin = irq_to_gpio(d->irq);
-        unsigned        bank = (d->irq - PIN_BASE) / 32;
+        unsigned        mask = pin_to_mask(pin);
+        unsigned        bank = pin / 32;
        if (unlikely(bank >= MAX_GPIO_BANKS))
                return -EINVAL;
@@ -285,7 +285,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
        else
                wakeups[bank] &= ~mask;
-        irq_set_irq_wake(gpio_chip[bank].bank->id, state);
+        irq_set_irq_wake(gpio_chip[bank].id, state);
        return 0;
 }
@@ -302,7 +302,7 @@ void at91_gpio_suspend(void)
                __raw_writel(wakeups[i], pio + PIO_IER);
                if (!wakeups[i])
-                        clk_disable(gpio_chip[i].bank->clock);
+                        clk_disable(gpio_chip[i].clock);
                else {
 #ifdef CONFIG_PM_DEBUG
                        printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
@@ -319,7 +319,7 @@ void at91_gpio_resume(void)
                void __iomem    *pio = gpio_chip[i].regbase;
                if (!wakeups[i])
-                        clk_enable(gpio_chip[i].bank->clock);
+                        clk_enable(gpio_chip[i].clock);
                __raw_writel(wakeups[i], pio + PIO_IDR);
                __raw_writel(backups[i], pio + PIO_IER);
@@ -344,8 +344,9 @@ void at91_gpio_resume(void)
 static void gpio_irq_mask(struct irq_data *d)
 {
-        void __iomem    *pio = pin_to_controller(d->irq);
+        unsigned        pin = irq_to_gpio(d->irq);
-        unsigned        mask = pin_to_mask(d->irq);
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
        if (pio)
                __raw_writel(mask, pio + PIO_IDR);
@@ -353,8 +354,9 @@ static void gpio_irq_mask(struct irq_data *d)
 static void gpio_irq_unmask(struct irq_data *d)
 {
-        void __iomem    *pio = pin_to_controller(d->irq);
+        unsigned        pin = irq_to_gpio(d->irq);
-        unsigned        mask = pin_to_mask(d->irq);
+        void __iomem    *pio = pin_to_controller(pin);
+        unsigned        mask = pin_to_mask(pin);
        if (pio)
                __raw_writel(mask, pio + PIO_IER);
@@ -382,7 +384,7 @@ static struct irq_chip gpio_irqchip = {
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
-        unsigned        pin;
+        unsigned        irq_pin;
        struct irq_data *idata = irq_desc_get_irq_data(desc);
        struct irq_chip *chip = irq_data_get_irq_chip(idata);
        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
@@ -405,12 +407,12 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                        continue;
                }
-                pin = at91_gpio->chip.base;
+                irq_pin = gpio_to_irq(at91_gpio->chip.base);
                while (isr) {
                        if (isr & 1)
-                                generic_handle_irq(pin);
+                                generic_handle_irq(irq_pin);
-                        pin++;
+                        irq_pin++;
                        isr >>= 1;
                }
        }
@@ -438,7 +440,7 @@ static int at91_gpio_show(struct seq_file *s, void *unused)
                seq_printf(s, "%i:\t", j);
                for (bank = 0; bank < gpio_banks; bank++) {
-                        unsigned        pin  = PIN_BASE + (32 * bank) + j;
+                        unsigned        pin  = (32 * bank) + j;
                        void __iomem    *pio = pin_to_controller(pin);
                        unsigned        mask = pin_to_mask(pin);
@@ -491,27 +493,28 @@ static struct lock_class_key gpio_lock_class;
 */
 void __init at91_gpio_irq_setup(void)
 {
-        unsigned                pioc, pin;
+        unsigned                pioc, irq = gpio_to_irq(0);
        struct at91_gpio_chip   *this, *prev;
-        for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL;
+        for (pioc = 0, this = gpio_chip, prev = NULL;
                        pioc++ < gpio_banks;
                        prev = this, this++) {
-                unsigned        id = this->bank->id;
+                unsigned        id = this->id;
                unsigned        i;
                __raw_writel(~0, this->regbase + PIO_IDR);
-                for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
+                for (i = 0, irq = gpio_to_irq(this->chip.base); i < 32;
-                        irq_set_lockdep_class(pin, &gpio_lock_class);
+                     i++, irq++) {
+                        irq_set_lockdep_class(irq, &gpio_lock_class);
                        /*
                         * Can use the "simple" and not "edge" handler since it's
                         * shorter, and the AIC handles interrupts sanely.
                         */
-                        irq_set_chip_and_handler(pin, &gpio_irqchip,
+                        irq_set_chip_and_handler(irq, &gpio_irqchip,
                                                 handle_simple_irq);
-                        set_irq_flags(pin, IRQF_VALID);
+                        set_irq_flags(irq, IRQF_VALID);
                }
                /* The toplevel handler handles one bank of GPIOs, except
@@ -524,7 +527,7 @@ void __init at91_gpio_irq_setup(void)
                irq_set_chip_data(id, this);
                irq_set_chained_handler(id, gpio_irq_handler);
        }
-        pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
+        pr_info("AT91: %d gpio irqs in %d banks\n", irq - gpio_to_irq(0), gpio_banks);
 }
 /* gpiolib support */
@@ -612,16 +615,26 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
        for (i = 0; i < nr_banks; i++) {
                at91_gpio = &gpio_chip[i];
-                at91_gpio->bank = &data[i];
+                at91_gpio->id = data[i].id;
-                at91_gpio->chip.base = PIN_BASE + i * 32;
+                at91_gpio->chip.base = i * 32;
-                at91_gpio->regbase = at91_gpio->bank->offset +
-                        (void __iomem *)AT91_VA_BASE_SYS;
+                at91_gpio->regbase = ioremap(data[i].regbase, 512);
+                if (!at91_gpio->regbase) {
+                        pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", i);
+                        continue;
+                }
+                at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
+                if (!at91_gpio->clock) {
+                        pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", i);
+                        continue;
+                }
                /* enable PIO controller's clock */
-                clk_enable(at91_gpio->bank->clock);
+                clk_enable(at91_gpio->clock);
                /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
-                if (last && last->bank->id == at91_gpio->bank->id)
+                if (last && last->id == at91_gpio->id)
                        last->next = at91_gpio;
                last = at91_gpio;
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
index 03566799d3b..3045781c473 100644
--- a/arch/arm/mach-at91/include/mach/at91_aic.h
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -16,7 +16,19 @@
 #ifndef AT91_AIC_H
 #define AT91_AIC_H
-#define AT91_AIC_SMR(n)         (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_aic_base;
+#define at91_aic_read(field) \
+        __raw_readl(at91_aic_base + field)
+#define at91_aic_write(field, value) \
+        __raw_writel(value, at91_aic_base + field);
+#else
+.extern at91_aic_base
+#endif
+#define AT91_AIC_SMR(n)         ((n) * 4)               /* Source Mode Registers 0-31 */
 #define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
 #define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
 #define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
@@ -24,30 +36,30 @@
 #define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
 #define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
-#define AT91_AIC_SVR(n)         (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
+#define AT91_AIC_SVR(n)         (0x80 + ((n) * 4))      /* Source Vector Registers 0-31 */
-#define AT91_AIC_IVR            (AT91_AIC + 0x100)      /* Interrupt Vector Register */
+#define AT91_AIC_IVR            0x100                   /* Interrupt Vector Register */
-#define AT91_AIC_FVR            (AT91_AIC + 0x104)      /* Fast Interrupt Vector Register */
+#define AT91_AIC_FVR            0x104                   /* Fast Interrupt Vector Register */
-#define AT91_AIC_ISR            (AT91_AIC + 0x108)      /* Interrupt Status Register */
+#define AT91_AIC_ISR            0x108                   /* Interrupt Status Register */
 #define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
-#define AT91_AIC_IPR            (AT91_AIC + 0x10c)      /* Interrupt Pending Register */
+#define AT91_AIC_IPR            0x10c                   /* Interrupt Pending Register */
-#define AT91_AIC_IMR            (AT91_AIC + 0x110)      /* Interrupt Mask Register */
+#define AT91_AIC_IMR            0x110                   /* Interrupt Mask Register */
-#define AT91_AIC_CISR           (AT91_AIC + 0x114)      /* Core Interrupt Status Register */
+#define AT91_AIC_CISR           0x114                   /* Core Interrupt Status Register */
 #define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
 #define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
-#define AT91_AIC_IECR           (AT91_AIC + 0x120)      /* Interrupt Enable Command Register */
+#define AT91_AIC_IECR           0x120                   /* Interrupt Enable Command Register */
-#define AT91_AIC_IDCR           (AT91_AIC + 0x124)      /* Interrupt Disable Command Register */
+#define AT91_AIC_IDCR           0x124                   /* Interrupt Disable Command Register */
-#define AT91_AIC_ICCR           (AT91_AIC + 0x128)      /* Interrupt Clear Command Register */
+#define AT91_AIC_ICCR           0x128                   /* Interrupt Clear Command Register */
-#define AT91_AIC_ISCR           (AT91_AIC + 0x12c)      /* Interrupt Set Command Register */
+#define AT91_AIC_ISCR           0x12c                   /* Interrupt Set Command Register */
-#define AT91_AIC_EOICR          (AT91_AIC + 0x130)      /* End of Interrupt Command Register */
+#define AT91_AIC_EOICR          0x130                   /* End of Interrupt Command Register */
-#define AT91_AIC_SPU            (AT91_AIC + 0x134)      /* Spurious Interrupt Vector Register */
+#define AT91_AIC_SPU            0x134                   /* Spurious Interrupt Vector Register */
-#define AT91_AIC_DCR            (AT91_AIC + 0x138)      /* Debug Control Register */
+#define AT91_AIC_DCR            0x138                   /* Debug Control Register */
 #define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
 #define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
-#define AT91_AIC_FFER           (AT91_AIC + 0x140)      /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC_FFER           0x140                   /* Fast Forcing Enable Register [SAM9 only] */
-#define AT91_AIC_FFDR           (AT91_AIC + 0x144)      /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC_FFDR           0x144                   /* Fast Forcing Disable Register [SAM9 only] */
-#define AT91_AIC_FFSR           (AT91_AIC + 0x148)      /* Fast Forcing Status Register [SAM9 only] */
+#define AT91_AIC_FFSR           0x148                   /* Fast Forcing Status Register [SAM9 only] */
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index dbfe455a4c4..2aa0c5e1349 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -19,7 +19,7 @@
 #define dbgu_readl(dbgu, field) \
        __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
-#ifdef AT91_DBGU
+#if !defined(CONFIG_ARCH_AT91X40)
 #define AT91_DBGU_CR            (0x00)  /* Control Register */
 #define AT91_DBGU_MR            (0x04)  /* Mode Register */
 #define AT91_DBGU_IER           (0x08)  /* Interrupt Enable Register */
diff --git a/arch/arm/mach-at91/include/mach/at91_pit.h b/arch/arm/mach-at91/include/mach/at91_pit.h
index 974d0bd05b5..d1f80ad7f4d 100644
--- a/arch/arm/mach-at91/include/mach/at91_pit.h
+++ b/arch/arm/mach-at91/include/mach/at91_pit.h
@@ -16,16 +16,16 @@
 #ifndef AT91_PIT_H
 #define AT91_PIT_H
-#define AT91_PIT_MR             (AT91_PIT + 0x00)       /* Mode Register */
+#define AT91_PIT_MR             0x00                    /* Mode Register */
 #define         AT91_PIT_PITIEN         (1 << 25)               /* Timer Interrupt Enable */
 #define         AT91_PIT_PITEN          (1 << 24)               /* Timer Enabled */
 #define         AT91_PIT_PIV            (0xfffff)               /* Periodic Interval Value */
-#define AT91_PIT_SR             (AT91_PIT + 0x04)       /* Status Register */
+#define AT91_PIT_SR             0x04                    /* Status Register */
 #define         AT91_PIT_PITS           (1 << 0)                /* Timer Status */
-#define AT91_PIT_PIVR           (AT91_PIT + 0x08)       /* Periodic Interval Value Register */
+#define AT91_PIT_PIVR           0x08                    /* Periodic Interval Value Register */
-#define AT91_PIT_PIIR           (AT91_PIT + 0x0c)       /* Periodic Interval Image Register */
+#define AT91_PIT_PIIR           0x0c                    /* Periodic Interval Image Register */
 #define         AT91_PIT_PICNT          (0xfff << 20)           /* Interval Counter */
 #define         AT91_PIT_CPIV           (0xfffff)               /* Inverval Value */
diff --git a/arch/arm/mach-at91/include/mach/at91_rtc.h b/arch/arm/mach-at91/include/mach/at91_rtc.h
index e56f4701a3e..da1945e5f71 100644
--- a/arch/arm/mach-at91/include/mach/at91_rtc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rtc.h
@@ -16,7 +16,7 @@
 #ifndef AT91_RTC_H
 #define AT91_RTC_H
-#define AT91_RTC_CR             (AT91_RTC + 0x00)       /* Control Register */
+#define AT91_RTC_CR             0x00                    /* Control Register */
 #define         AT91_RTC_UPDTIM         (1 <<  0)               /* Update Request Time Register */
 #define         AT91_RTC_UPDCAL         (1 <<  1)               /* Update Request Calendar Register */
 #define         AT91_RTC_TIMEVSEL       (3 <<  8)               /* Time Event Selection */
@@ -29,44 +29,44 @@
 #define                 AT91_RTC_CALEVSEL_MONTH         (1 << 16)
 #define                 AT91_RTC_CALEVSEL_YEAR          (2 << 16)
-#define AT91_RTC_MR             (AT91_RTC + 0x04)       /* Mode Register */
+#define AT91_RTC_MR             0x04                    /* Mode Register */
 #define                 AT91_RTC_HRMOD          (1 <<  0)               /* 12/24 Hour Mode */
-#define AT91_RTC_TIMR           (AT91_RTC + 0x08)       /* Time Register */
+#define AT91_RTC_TIMR           0x08                    /* Time Register */
 #define         AT91_RTC_SEC            (0x7f <<  0)            /* Current Second */
 #define         AT91_RTC_MIN            (0x7f <<  8)            /* Current Minute */
 #define         AT91_RTC_HOUR           (0x3f << 16)            /* Current Hour */
 #define         AT91_RTC_AMPM           (1    << 22)            /* Ante Meridiem Post Meridiem Indicator */
-#define AT91_RTC_CALR           (AT91_RTC + 0x0c)       /* Calendar Register */
+#define AT91_RTC_CALR           0x0c                    /* Calendar Register */
 #define         AT91_RTC_CENT           (0x7f <<  0)            /* Current Century */
 #define         AT91_RTC_YEAR           (0xff <<  8)            /* Current Year */
 #define         AT91_RTC_MONTH          (0x1f << 16)            /* Current Month */
 #define         AT91_RTC_DAY            (7    << 21)            /* Current Day */
 #define         AT91_RTC_DATE           (0x3f << 24)            /* Current Date */
-#define AT91_RTC_TIMALR         (AT91_RTC + 0x10)       /* Time Alarm Register */
+#define AT91_RTC_TIMALR         0x10                    /* Time Alarm Register */
 #define         AT91_RTC_SECEN          (1 <<  7)               /* Second Alarm Enable */
 #define         AT91_RTC_MINEN          (1 << 15)               /* Minute Alarm Enable */
 #define         AT91_RTC_HOUREN         (1 << 23)               /* Hour Alarm Enable */
-#define AT91_RTC_CALALR         (AT91_RTC + 0x14)       /* Calendar Alarm Register */
+#define AT91_RTC_CALALR         0x14                    /* Calendar Alarm Register */
 #define         AT91_RTC_MTHEN          (1 << 23)               /* Month Alarm Enable */
 #define         AT91_RTC_DATEEN         (1 << 31)               /* Date Alarm Enable */
-#define AT91_RTC_SR             (AT91_RTC + 0x18)       /* Status Register */
+#define AT91_RTC_SR             0x18                    /* Status Register */
 #define         AT91_RTC_ACKUPD         (1 <<  0)               /* Acknowledge for Update */
 #define         AT91_RTC_ALARM          (1 <<  1)               /* Alarm Flag */
 #define         AT91_RTC_SECEV          (1 <<  2)               /* Second Event */
 #define         AT91_RTC_TIMEV          (1 <<  3)               /* Time Event */
 #define         AT91_RTC_CALEV          (1 <<  4)               /* Calendar Event */
-#define AT91_RTC_SCCR           (AT91_RTC + 0x1c)       /* Status Clear Command Register */
+#define AT91_RTC_SCCR           0x1c                    /* Status Clear Command Register */
-#define AT91_RTC_IER            (AT91_RTC + 0x20)       /* Interrupt Enable Register */
+#define AT91_RTC_IER            0x20                    /* Interrupt Enable Register */
-#define AT91_RTC_IDR            (AT91_RTC + 0x24)       /* Interrupt Disable Register */
+#define AT91_RTC_IDR            0x24                    /* Interrupt Disable Register */
-#define AT91_RTC_IMR            (AT91_RTC + 0x28)       /* Interrupt Mask Register */
+#define AT91_RTC_IMR            0x28                    /* Interrupt Mask Register */
-#define AT91_RTC_VER            (AT91_RTC + 0x2c)       /* Valid Entry Register */
+#define AT91_RTC_VER            0x2c                    /* Valid Entry Register */
 #define         AT91_RTC_NVTIM          (1 <<  0)               /* Non valid Time */
 #define         AT91_RTC_NVCAL          (1 <<  1)               /* Non valid Calendar */
 #define         AT91_RTC_NVTIMALR       (1 <<  2)               /* Non valid Time Alarm */
diff --git a/arch/arm/mach-at91/include/mach/at91_shdwc.h b/arch/arm/mach-at91/include/mach/at91_shdwc.h
index c4ce07e8a8f..1d4fe822c77 100644
--- a/arch/arm/mach-at91/include/mach/at91_shdwc.h
+++ b/arch/arm/mach-at91/include/mach/at91_shdwc.h
@@ -16,11 +16,21 @@
 #ifndef AT91_SHDWC_H
 #define AT91_SHDWC_H
-#define AT91_SHDW_CR            (AT91_SHDWC + 0x00)     /* Shut Down Control Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_shdwc_base;
+#define at91_shdwc_read(field) \
+        __raw_readl(at91_shdwc_base + field)
+#define at91_shdwc_write(field, value) \
+        __raw_writel(value, at91_shdwc_base + field);
+#endif
+#define AT91_SHDW_CR            0x00                    /* Shut Down Control Register */
 #define         AT91_SHDW_SHDW          (1    << 0)             /* Shut Down command */
 #define         AT91_SHDW_KEY           (0xa5 << 24)            /* KEY Password */
-#define AT91_SHDW_MR            (AT91_SHDWC + 0x04)     /* Shut Down Mode Register */
+#define AT91_SHDW_MR            0x04                    /* Shut Down Mode Register */
 #define         AT91_SHDW_WKMODE0       (3 << 0)                /* Wake-up 0 Mode Selection */
 #define                 AT91_SHDW_WKMODE0_NONE          0
 #define                 AT91_SHDW_WKMODE0_HIGH          1
@@ -30,7 +40,7 @@
 #define                 AT91_SHDW_CPTWK0_(x)    ((x) << 4)
 #define         AT91_SHDW_RTTWKEN       (1   << 16)             /* Real Time Timer Wake-up Enable */
-#define AT91_SHDW_SR            (AT91_SHDWC + 0x08)     /* Shut Down Status Register */
+#define AT91_SHDW_SR            0x08                    /* Shut Down Status Register */
 #define         AT91_SHDW_WAKEUP0       (1 <<  0)               /* Wake-up 0 Status */
 #define         AT91_SHDW_RTTWK         (1 << 16)               /* Real-time Timer Wake-up */
 #define         AT91_SHDW_RTCWK         (1 << 17)               /* Real-time Clock Wake-up [SAM9RL] */
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index c5df1e8f195..4c0e2f6011d 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -79,29 +79,28 @@
 /*
 * System Peripherals (offset from AT91_BASE_SYS)
 */
-#define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
 #define AT91_BCRAMC     (0xffffe400 - AT91_BASE_SYS)
 #define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffeb10 - AT91_BASE_SYS)
-#define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_GPBR       (cpu_is_at91cap9_revB() ?       \
                        (0xfffffd50 - AT91_BASE_SYS) :  \
                        (0xfffffd60 - AT91_BASE_SYS))
+#define AT91CAP9_BASE_ECC       0xffffe200
+#define AT91CAP9_BASE_DMA       0xffffec00
+#define AT91CAP9_BASE_SMC       0xffffe800
+#define AT91CAP9_BASE_DBGU      AT91_BASE_DBGU1
+#define AT91CAP9_BASE_PIOA      0xfffff200
+#define AT91CAP9_BASE_PIOB      0xfffff400
+#define AT91CAP9_BASE_PIOC      0xfffff600
+#define AT91CAP9_BASE_PIOD      0xfffff800
+#define AT91CAP9_BASE_SHDWC     0xfffffd10
+#define AT91CAP9_BASE_RTT       0xfffffd20
+#define AT91CAP9_BASE_PIT       0xfffffd30
+#define AT91CAP9_BASE_WDT       0xfffffd40
 #define AT91_USART0     AT91CAP9_BASE_US0
 #define AT91_USART1     AT91CAP9_BASE_US1
 #define AT91_USART2     AT91CAP9_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index e4037b50030..bacb5114181 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -79,17 +79,17 @@
 /*
 * System Peripherals (offset from AT91_BASE_SYS)
 */
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)    /* Debug Unit */
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)    /* PIO Controller A */
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)    /* PIO Controller B */
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)    /* PIO Controller C */
-#define AT91_PIOD       (0xfffffa00 - AT91_BASE_SYS)    /* PIO Controller D */
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)    /* Power Management Controller */
 #define AT91_ST         (0xfffffd00 - AT91_BASE_SYS)    /* System Timer */
-#define AT91_RTC        (0xfffffe00 - AT91_BASE_SYS)    /* Real-Time Clock */
 #define AT91_MC         (0xffffff00 - AT91_BASE_SYS)    /* Memory Controllers */
+#define AT91RM9200_BASE_DBGU    AT91_BASE_DBGU0 /* Debug Unit */
+#define AT91RM9200_BASE_PIOA    0xfffff400      /* PIO Controller A */
+#define AT91RM9200_BASE_PIOB    0xfffff600      /* PIO Controller B */
+#define AT91RM9200_BASE_PIOC    0xfffff800      /* PIO Controller C */
+#define AT91RM9200_BASE_PIOD    0xfffffa00      /* PIO Controller D */
+#define AT91RM9200_BASE_RTC     0xfffffe00      /* Real-Time Clock */
 #define AT91_USART0     AT91RM9200_BASE_US0
 #define AT91_USART1     AT91RM9200_BASE_US1
 #define AT91_USART2     AT91RM9200_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 9a791165913..f937c476bb6 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -80,24 +80,23 @@
 /*
 * System Peripherals (offset from AT91_BASE_SYS)
 */
-#define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
 #define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+#define AT91SAM9260_BASE_ECC    0xffffe800
+#define AT91SAM9260_BASE_SMC    0xffffec00
+#define AT91SAM9260_BASE_DBGU   AT91_BASE_DBGU0
+#define AT91SAM9260_BASE_PIOA   0xfffff400
+#define AT91SAM9260_BASE_PIOB   0xfffff600
+#define AT91SAM9260_BASE_PIOC   0xfffff800
+#define AT91SAM9260_BASE_SHDWC  0xfffffd10
+#define AT91SAM9260_BASE_RTT    0xfffffd20
+#define AT91SAM9260_BASE_PIT    0xfffffd30
+#define AT91SAM9260_BASE_WDT    0xfffffd40
 #define AT91_USART0     AT91SAM9260_BASE_US0
 #define AT91_USART1     AT91SAM9260_BASE_US1
 #define AT91_USART2     AT91SAM9260_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index ce596204cef..175604e261b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -66,21 +66,21 @@
 * System Peripherals (offset from AT91_BASE_SYS)
 */
 #define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_GPBR       (0xfffffd50 - AT91_BASE_SYS)
+#define AT91SAM9261_BASE_SMC    0xffffec00
+#define AT91SAM9261_BASE_DBGU   AT91_BASE_DBGU0
+#define AT91SAM9261_BASE_PIOA   0xfffff400
+#define AT91SAM9261_BASE_PIOB   0xfffff600
+#define AT91SAM9261_BASE_PIOC   0xfffff800
+#define AT91SAM9261_BASE_SHDWC  0xfffffd10
+#define AT91SAM9261_BASE_RTT    0xfffffd20
+#define AT91SAM9261_BASE_PIT    0xfffffd30
+#define AT91SAM9261_BASE_WDT    0xfffffd40
 #define AT91_USART0     AT91SAM9261_BASE_US0
 #define AT91_USART1     AT91SAM9261_BASE_US1
 #define AT91_USART2     AT91SAM9261_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index f1b92961a2b..80c915002d8 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -74,30 +74,29 @@
 /*
 * System Peripherals (offset from AT91_BASE_SYS)
 */
-#define AT91_ECC0       (0xffffe000 - AT91_BASE_SYS)
 #define AT91_SDRAMC0    (0xffffe200 - AT91_BASE_SYS)
-#define AT91_SMC0       (0xffffe400 - AT91_BASE_SYS)
-#define AT91_ECC1       (0xffffe600 - AT91_BASE_SYS)
 #define AT91_SDRAMC1    (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SMC1       (0xffffea00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffec00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffed10 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE       (0xfffffa00 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT0       (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_RTT1       (0xfffffd50 - AT91_BASE_SYS)
 #define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
+#define AT91SAM9263_BASE_ECC0   0xffffe000
+#define AT91SAM9263_BASE_SMC0   0xffffe400
+#define AT91SAM9263_BASE_ECC1   0xffffe600
+#define AT91SAM9263_BASE_SMC1   0xffffea00
+#define AT91SAM9263_BASE_DBGU   AT91_BASE_DBGU1
+#define AT91SAM9263_BASE_PIOA   0xfffff200
+#define AT91SAM9263_BASE_PIOB   0xfffff400
+#define AT91SAM9263_BASE_PIOC   0xfffff600
+#define AT91SAM9263_BASE_PIOD   0xfffff800
+#define AT91SAM9263_BASE_PIOE   0xfffffa00
+#define AT91SAM9263_BASE_SHDWC  0xfffffd10
+#define AT91SAM9263_BASE_RTT0   0xfffffd20
+#define AT91SAM9263_BASE_PIT    0xfffffd30
+#define AT91SAM9263_BASE_WDT    0xfffffd40
+#define AT91SAM9263_BASE_RTT1   0xfffffd50
 #define AT91_USART0     AT91SAM9263_BASE_US0
 #define AT91_USART1     AT91SAM9263_BASE_US1
 #define AT91_USART2     AT91SAM9263_BASE_US2
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index 57de6207e57..eb18a70fa64 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -16,7 +16,9 @@
 #ifndef AT91SAM9_SMC_H
 #define AT91SAM9_SMC_H
-#define AT91_SMC_SETUP(n)       (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
+#include <mach/cpu.h>
+#define AT91_SMC_SETUP          0x00                            /* Setup Register for CS n */
 #define         AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
 #define                 AT91_SMC_NWESETUP_(x)   ((x) << 0)
 #define         AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
@@ -26,7 +28,7 @@
 #define         AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
 #define                 AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
-#define AT91_SMC_PULSE(n)       (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
+#define AT91_SMC_PULSE          0x04                            /* Pulse Register for CS n */
 #define         AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
 #define                 AT91_SMC_NWEPULSE_(x)   ((x) << 0)
 #define         AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
@@ -36,13 +38,13 @@
 #define         AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
 #define                 AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-#define AT91_SMC_CYCLE(n)       (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
+#define AT91_SMC_CYCLE          0x08                            /* Cycle Register for CS n */
 #define         AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
 #define                 AT91_SMC_NWECYCLE_(x)   ((x) << 0)
 #define         AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
 #define                 AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
-#define AT91_SMC_MODE(n)        (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
+#define AT91_SMC_MODE           0x0c                            /* Mode Register for CS n */
 #define         AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
 #define         AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
 #define         AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
@@ -66,11 +68,4 @@
 #define                 AT91_SMC_PS_16                  (2 << 28)
 #define                 AT91_SMC_PS_32                  (3 << 28)
-#if defined(AT91_SMC1)          /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)      (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)      (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)      (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)       (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 406bb649680..f0c23c960de 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -86,27 +86,27 @@
 /*
 * System Peripherals (offset from AT91_BASE_SYS)
 */
-#define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
 #define AT91_DDRSDRC1   (0xffffe400 - AT91_BASE_SYS)
 #define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
-#define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOE       (0xfffffa00 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
-#define AT91_RTC        (0xfffffdb0 - AT91_BASE_SYS)
+#define AT91SAM9G45_BASE_ECC    0xffffe200
+#define AT91SAM9G45_BASE_DMA    0xffffec00
+#define AT91SAM9G45_BASE_SMC    0xffffe800
+#define AT91SAM9G45_BASE_DBGU   AT91_BASE_DBGU1
+#define AT91SAM9G45_BASE_PIOA   0xfffff200
+#define AT91SAM9G45_BASE_PIOB   0xfffff400
+#define AT91SAM9G45_BASE_PIOC   0xfffff600
+#define AT91SAM9G45_BASE_PIOD   0xfffff800
+#define AT91SAM9G45_BASE_PIOE   0xfffffa00
+#define AT91SAM9G45_BASE_SHDWC  0xfffffd10
+#define AT91SAM9G45_BASE_RTT    0xfffffd20
+#define AT91SAM9G45_BASE_PIT    0xfffffd30
+#define AT91SAM9G45_BASE_WDT    0xfffffd40
+#define AT91SAM9G45_BASE_RTC    0xfffffdb0
 #define AT91_USART0     AT91SAM9G45_BASE_US0
 #define AT91_USART1     AT91SAM9G45_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 1aabacd315d..2bb359e60b9 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -69,27 +69,26 @@
 /*
 * System Peripherals (offset from AT91_BASE_SYS)
 */
-#define AT91_DMA        (0xffffe600 - AT91_BASE_SYS)
-#define AT91_ECC        (0xffffe800 - AT91_BASE_SYS)
 #define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG       (0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PIOD       (0xfffffa00 - AT91_BASE_SYS)
 #define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
 #define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
 #define AT91_SCKCR      (0xfffffd50 - AT91_BASE_SYS)
 #define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
-#define AT91_RTC        (0xfffffe00 - AT91_BASE_SYS)
+#define AT91SAM9RL_BASE_DMA     0xffffe600
+#define AT91SAM9RL_BASE_ECC     0xffffe800
+#define AT91SAM9RL_BASE_SMC     0xffffec00
+#define AT91SAM9RL_BASE_DBGU    AT91_BASE_DBGU0
+#define AT91SAM9RL_BASE_PIOA    0xfffff400
+#define AT91SAM9RL_BASE_PIOB    0xfffff600
+#define AT91SAM9RL_BASE_PIOC    0xfffff800
+#define AT91SAM9RL_BASE_PIOD    0xfffffa00
+#define AT91SAM9RL_BASE_SHDWC   0xfffffd10
+#define AT91SAM9RL_BASE_RTT     0xfffffd20
+#define AT91SAM9RL_BASE_PIT     0xfffffd30
+#define AT91SAM9RL_BASE_WDT     0xfffffd40
+#define AT91SAM9RL_BASE_RTC     0xfffffe00
 #define AT91_USART0     AT91SAM9RL_BASE_US0
 #define AT91_USART1     AT91SAM9RL_BASE_US1
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index a152ff87e68..a57829f4fd1 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -40,7 +40,6 @@
 #define AT91_PIOA       (0xffff0000 - AT91_BASE_SYS)    /* PIO Controller A */
 #define AT91_PS         (0xffff4000 - AT91_BASE_SYS)    /* Power Save */
 #define AT91_WD         (0xffff8000 - AT91_BASE_SYS)    /* Watchdog Timer */
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
 /*
 * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index eac92e995bb..d0b377b21bd 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -40,13 +40,14 @@
 #include <linux/atmel-mci.h>
 #include <sound/atmel-ac97c.h>
 #include <linux/serial.h>
+#include <linux/platform_data/macb.h>
 /* USB Device */
 struct at91_udc_data {
-        u8      vbus_pin;               /* high == host powering us */
+        int     vbus_pin;               /* high == host powering us */
        u8      vbus_active_low;        /* vbus polarity */
        u8      vbus_polled;            /* Use polling, not interrupt */
-        u8      pullup_pin;             /* active == D+ pulled up */
+        int     pullup_pin;             /* active == D+ pulled up */
        u8      pullup_active_low;      /* true == pullup_pin is active low */
 };
 extern void __init at91_add_device_udc(struct at91_udc_data *data);
@@ -56,10 +57,10 @@ extern void __init at91_add_device_usba(struct usba_platform_data *data);
 /* Compact Flash */
 struct at91_cf_data {
-        u8      irq_pin;                /* I/O IRQ */
+        int     irq_pin;                /* I/O IRQ */
-        u8      det_pin;                /* Card detect */
+        int     det_pin;                /* Card detect */
-        u8      vcc_pin;                /* power switching */
+        int     vcc_pin;                /* power switching */
-        u8      rst_pin;                /* card reset */
+        int     rst_pin;                /* card reset */
        u8      chipselect;             /* EBI Chip Select number */
        u8      flags;
 #define AT91_CF_TRUE_IDE        0x01
@@ -70,37 +71,26 @@ extern void __init at91_add_device_cf(struct at91_cf_data *data);
 /* MMC / SD */
  /* at91_mci platform config */
 struct at91_mmc_data {
-        u8              det_pin;        /* card detect IRQ */
+        int             det_pin;        /* card detect IRQ */
        unsigned        slot_b:1;       /* uses Slot B */
        unsigned        wire4:1;        /* (SD) supports DAT0..DAT3 */
-        u8              wp_pin;         /* (SD) writeprotect detect */
+        int             wp_pin;         /* (SD) writeprotect detect */
-        u8              vcc_pin;        /* power switching (high == on) */
+        int             vcc_pin;        /* power switching (high == on) */
 };
 extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
  /* atmel-mci platform config */
 extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data);
- /* Ethernet (EMAC & MACB) */
+extern void __init at91_add_device_eth(struct macb_platform_data *data);
-struct at91_eth_data {
-        u32             phy_mask;
-        u8              phy_irq_pin;    /* PHY IRQ */
-        u8              is_rmii;        /* using RMII interface? */
-};
-extern void __init at91_add_device_eth(struct at91_eth_data *data);
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
-#define eth_platform_data       at91_eth_data
-#endif
 /* USB Host */
 struct at91_usbh_data {
        u8              ports;          /* number of ports on root hub */
-        u8              vbus_pin[2];    /* port power-control pin */
+        int             vbus_pin[2];    /* port power-control pin */
        u8              vbus_pin_inverted;
        u8              overcurrent_supported;
-        u8              overcurrent_pin[2];
+        int             overcurrent_pin[2];
        u8              overcurrent_status[2];
        u8              overcurrent_changed[2];
 };
@@ -110,9 +100,9 @@ extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
 /* NAND / SmartMedia */
 struct atmel_nand_data {
-        u8              enable_pin;     /* chip enable */
+        int             enable_pin;     /* chip enable */
-        u8              det_pin;        /* card detect */
+        int             det_pin;        /* card detect */
-        u8              rdy_pin;        /* ready/busy */
+        int             rdy_pin;        /* ready/busy */
        u8              rdy_pin_active_low;     /* rdy_pin value is inverted */
        u8              ale;            /* address line number connected to ALE */
        u8              cle;            /* address line number connected to CLE */
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index 0ed8648c645..c6bb9e2d9ba 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -14,9 +14,15 @@
 #include <mach/hardware.h>
 #include <mach/at91_dbgu.h>
+#if defined(CONFIG_AT91_DEBUG_LL_DBGU0)
+#define AT91_DBGU AT91_BASE_DBGU0
+#else
+#define AT91_DBGU AT91_BASE_DBGU1
+#endif
        .macro  addruart, rp, rv, tmp
-        ldr     \rp, =(AT91_BASE_SYS + AT91_DBGU)       @ System peripherals (phys address)
+        ldr     \rp, =AT91_DBGU                         @ System peripherals (phys address)
-        ldr     \rv, =(AT91_VA_BASE_SYS + AT91_DBGU)    @ System peripherals (virt address)
+        ldr     \rv, =AT91_IO_P2V(AT91_DBGU)            @ System peripherals (virt address)
        .endm
        .macro  senduart,rd,rx
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
index 7ab68f97222..423eea0ed74 100644
--- a/arch/arm/mach-at91/include/mach/entry-macro.S
+++ b/arch/arm/mach-at91/include/mach/entry-macro.S
@@ -17,16 +17,17 @@
        .endm
        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =(AT91_VA_BASE_SYS + AT91_AIC)           @ base virtual address of AIC peripheral
+        ldr     \base, =at91_aic_base           @ base virtual address of AIC peripheral
+        ldr     \base, [\base]
        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)]     @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
+        ldr     \irqnr, [\base, #AT91_AIC_IVR]          @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
-        ldr     \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)]   @ read interrupt source number
+        ldr     \irqstat, [\base, #AT91_AIC_ISR]        @ read interrupt source number
-        teq     \irqstat, #0                                    @ ISR is 0 when no current interrupt, or spurious interrupt
+        teq     \irqstat, #0                            @ ISR is 0 when no current interrupt, or spurious interrupt
-        streq   \tmp, [\base, #(AT91_AIC_EOICR - AT91_AIC)]     @ not going to be handled further, then ACK it now.
+        streq   \tmp, [\base, #AT91_AIC_EOICR]          @ not going to be handled further, then ACK it now.
        .endm
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 2b9a1f51210..e3fd225121c 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -16,177 +16,175 @@
 #include <linux/kernel.h>
 #include <asm/irq.h>
-#define PIN_BASE                NR_AIC_IRQS
 #define MAX_GPIO_BANKS          5
-#define NR_BUILTIN_GPIO         (PIN_BASE + (MAX_GPIO_BANKS * 32))
+#define NR_BUILTIN_GPIO         (MAX_GPIO_BANKS * 32)
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
-#define AT91_PIN_PA0    (PIN_BASE + 0x00 + 0)
+#define AT91_PIN_PA0    (0x00 + 0)
-#define AT91_PIN_PA1    (PIN_BASE + 0x00 + 1)
+#define AT91_PIN_PA1    (0x00 + 1)
-#define AT91_PIN_PA2    (PIN_BASE + 0x00 + 2)
+#define AT91_PIN_PA2    (0x00 + 2)
-#define AT91_PIN_PA3    (PIN_BASE + 0x00 + 3)
+#define AT91_PIN_PA3    (0x00 + 3)
-#define AT91_PIN_PA4    (PIN_BASE + 0x00 + 4)
+#define AT91_PIN_PA4    (0x00 + 4)
-#define AT91_PIN_PA5    (PIN_BASE + 0x00 + 5)
+#define AT91_PIN_PA5    (0x00 + 5)
-#define AT91_PIN_PA6    (PIN_BASE + 0x00 + 6)
+#define AT91_PIN_PA6    (0x00 + 6)
-#define AT91_PIN_PA7    (PIN_BASE + 0x00 + 7)
+#define AT91_PIN_PA7    (0x00 + 7)
-#define AT91_PIN_PA8    (PIN_BASE + 0x00 + 8)
+#define AT91_PIN_PA8    (0x00 + 8)
-#define AT91_PIN_PA9    (PIN_BASE + 0x00 + 9)
+#define AT91_PIN_PA9    (0x00 + 9)
-#define AT91_PIN_PA10   (PIN_BASE + 0x00 + 10)
+#define AT91_PIN_PA10   (0x00 + 10)
-#define AT91_PIN_PA11   (PIN_BASE + 0x00 + 11)
+#define AT91_PIN_PA11   (0x00 + 11)
-#define AT91_PIN_PA12   (PIN_BASE + 0x00 + 12)
+#define AT91_PIN_PA12   (0x00 + 12)
-#define AT91_PIN_PA13   (PIN_BASE + 0x00 + 13)
+#define AT91_PIN_PA13   (0x00 + 13)
-#define AT91_PIN_PA14   (PIN_BASE + 0x00 + 14)
+#define AT91_PIN_PA14   (0x00 + 14)
-#define AT91_PIN_PA15   (PIN_BASE + 0x00 + 15)
+#define AT91_PIN_PA15   (0x00 + 15)
-#define AT91_PIN_PA16   (PIN_BASE + 0x00 + 16)
+#define AT91_PIN_PA16   (0x00 + 16)
-#define AT91_PIN_PA17   (PIN_BASE + 0x00 + 17)
+#define AT91_PIN_PA17   (0x00 + 17)
-#define AT91_PIN_PA18   (PIN_BASE + 0x00 + 18)
+#define AT91_PIN_PA18   (0x00 + 18)
-#define AT91_PIN_PA19   (PIN_BASE + 0x00 + 19)
+#define AT91_PIN_PA19   (0x00 + 19)
-#define AT91_PIN_PA20   (PIN_BASE + 0x00 + 20)
+#define AT91_PIN_PA20   (0x00 + 20)
-#define AT91_PIN_PA21   (PIN_BASE + 0x00 + 21)
+#define AT91_PIN_PA21   (0x00 + 21)
-#define AT91_PIN_PA22   (PIN_BASE + 0x00 + 22)
+#define AT91_PIN_PA22   (0x00 + 22)
-#define AT91_PIN_PA23   (PIN_BASE + 0x00 + 23)
+#define AT91_PIN_PA23   (0x00 + 23)
-#define AT91_PIN_PA24   (PIN_BASE + 0x00 + 24)
+#define AT91_PIN_PA24   (0x00 + 24)
-#define AT91_PIN_PA25   (PIN_BASE + 0x00 + 25)
+#define AT91_PIN_PA25   (0x00 + 25)
-#define AT91_PIN_PA26   (PIN_BASE + 0x00 + 26)
+#define AT91_PIN_PA26   (0x00 + 26)
-#define AT91_PIN_PA27   (PIN_BASE + 0x00 + 27)
+#define AT91_PIN_PA27   (0x00 + 27)
-#define AT91_PIN_PA28   (PIN_BASE + 0x00 + 28)
+#define AT91_PIN_PA28   (0x00 + 28)
-#define AT91_PIN_PA29   (PIN_BASE + 0x00 + 29)
+#define AT91_PIN_PA29   (0x00 + 29)
-#define AT91_PIN_PA30   (PIN_BASE + 0x00 + 30)
+#define AT91_PIN_PA30   (0x00 + 30)
-#define AT91_PIN_PA31   (PIN_BASE + 0x00 + 31)
+#define AT91_PIN_PA31   (0x00 + 31)
-#define AT91_PIN_PB0    (PIN_BASE + 0x20 + 0)
+#define AT91_PIN_PB0    (0x20 + 0)
-#define AT91_PIN_PB1    (PIN_BASE + 0x20 + 1)
+#define AT91_PIN_PB1    (0x20 + 1)
-#define AT91_PIN_PB2    (PIN_BASE + 0x20 + 2)
+#define AT91_PIN_PB2    (0x20 + 2)
-#define AT91_PIN_PB3    (PIN_BASE + 0x20 + 3)
+#define AT91_PIN_PB3    (0x20 + 3)
-#define AT91_PIN_PB4    (PIN_BASE + 0x20 + 4)
+#define AT91_PIN_PB4    (0x20 + 4)
-#define AT91_PIN_PB5    (PIN_BASE + 0x20 + 5)
+#define AT91_PIN_PB5    (0x20 + 5)
-#define AT91_PIN_PB6    (PIN_BASE + 0x20 + 6)
+#define AT91_PIN_PB6    (0x20 + 6)
-#define AT91_PIN_PB7    (PIN_BASE + 0x20 + 7)
+#define AT91_PIN_PB7    (0x20 + 7)
-#define AT91_PIN_PB8    (PIN_BASE + 0x20 + 8)
+#define AT91_PIN_PB8    (0x20 + 8)
-#define AT91_PIN_PB9    (PIN_BASE + 0x20 + 9)
+#define AT91_PIN_PB9    (0x20 + 9)
-#define AT91_PIN_PB10   (PIN_BASE + 0x20 + 10)
+#define AT91_PIN_PB10   (0x20 + 10)
-#define AT91_PIN_PB11   (PIN_BASE + 0x20 + 11)
+#define AT91_PIN_PB11   (0x20 + 11)
-#define AT91_PIN_PB12   (PIN_BASE + 0x20 + 12)
+#define AT91_PIN_PB12   (0x20 + 12)
-#define AT91_PIN_PB13   (PIN_BASE + 0x20 + 13)
+#define AT91_PIN_PB13   (0x20 + 13)
-#define AT91_PIN_PB14   (PIN_BASE + 0x20 + 14)
+#define AT91_PIN_PB14   (0x20 + 14)
-#define AT91_PIN_PB15   (PIN_BASE + 0x20 + 15)
+#define AT91_PIN_PB15   (0x20 + 15)
-#define AT91_PIN_PB16   (PIN_BASE + 0x20 + 16)
+#define AT91_PIN_PB16   (0x20 + 16)
-#define AT91_PIN_PB17   (PIN_BASE + 0x20 + 17)
+#define AT91_PIN_PB17   (0x20 + 17)
-#define AT91_PIN_PB18   (PIN_BASE + 0x20 + 18)
+#define AT91_PIN_PB18   (0x20 + 18)
-#define AT91_PIN_PB19   (PIN_BASE + 0x20 + 19)
+#define AT91_PIN_PB19   (0x20 + 19)
-#define AT91_PIN_PB20   (PIN_BASE + 0x20 + 20)
+#define AT91_PIN_PB20   (0x20 + 20)
-#define AT91_PIN_PB21   (PIN_BASE + 0x20 + 21)
+#define AT91_PIN_PB21   (0x20 + 21)
-#define AT91_PIN_PB22   (PIN_BASE + 0x20 + 22)
+#define AT91_PIN_PB22   (0x20 + 22)
-#define AT91_PIN_PB23   (PIN_BASE + 0x20 + 23)
+#define AT91_PIN_PB23   (0x20 + 23)
-#define AT91_PIN_PB24   (PIN_BASE + 0x20 + 24)
+#define AT91_PIN_PB24   (0x20 + 24)
-#define AT91_PIN_PB25   (PIN_BASE + 0x20 + 25)
+#define AT91_PIN_PB25   (0x20 + 25)
-#define AT91_PIN_PB26   (PIN_BASE + 0x20 + 26)
+#define AT91_PIN_PB26   (0x20 + 26)
-#define AT91_PIN_PB27   (PIN_BASE + 0x20 + 27)
+#define AT91_PIN_PB27   (0x20 + 27)
-#define AT91_PIN_PB28   (PIN_BASE + 0x20 + 28)
+#define AT91_PIN_PB28   (0x20 + 28)
-#define AT91_PIN_PB29   (PIN_BASE + 0x20 + 29)
+#define AT91_PIN_PB29   (0x20 + 29)
-#define AT91_PIN_PB30   (PIN_BASE + 0x20 + 30)
+#define AT91_PIN_PB30   (0x20 + 30)
-#define AT91_PIN_PB31   (PIN_BASE + 0x20 + 31)
+#define AT91_PIN_PB31   (0x20 + 31)
-#define AT91_PIN_PC0    (PIN_BASE + 0x40 + 0)
+#define AT91_PIN_PC0    (0x40 + 0)
-#define AT91_PIN_PC1    (PIN_BASE + 0x40 + 1)
+#define AT91_PIN_PC1    (0x40 + 1)
-#define AT91_PIN_PC2    (PIN_BASE + 0x40 + 2)
+#define AT91_PIN_PC2    (0x40 + 2)
-#define AT91_PIN_PC3    (PIN_BASE + 0x40 + 3)
+#define AT91_PIN_PC3    (0x40 + 3)
-#define AT91_PIN_PC4    (PIN_BASE + 0x40 + 4)
+#define AT91_PIN_PC4    (0x40 + 4)
-#define AT91_PIN_PC5    (PIN_BASE + 0x40 + 5)
+#define AT91_PIN_PC5    (0x40 + 5)
-#define AT91_PIN_PC6    (PIN_BASE + 0x40 + 6)
+#define AT91_PIN_PC6    (0x40 + 6)
-#define AT91_PIN_PC7    (PIN_BASE + 0x40 + 7)
+#define AT91_PIN_PC7    (0x40 + 7)
-#define AT91_PIN_PC8    (PIN_BASE + 0x40 + 8)
+#define AT91_PIN_PC8    (0x40 + 8)
-#define AT91_PIN_PC9    (PIN_BASE + 0x40 + 9)
+#define AT91_PIN_PC9    (0x40 + 9)
-#define AT91_PIN_PC10   (PIN_BASE + 0x40 + 10)
+#define AT91_PIN_PC10   (0x40 + 10)
-#define AT91_PIN_PC11   (PIN_BASE + 0x40 + 11)
+#define AT91_PIN_PC11   (0x40 + 11)
-#define AT91_PIN_PC12   (PIN_BASE + 0x40 + 12)
+#define AT91_PIN_PC12   (0x40 + 12)
-#define AT91_PIN_PC13   (PIN_BASE + 0x40 + 13)
+#define AT91_PIN_PC13   (0x40 + 13)
-#define AT91_PIN_PC14   (PIN_BASE + 0x40 + 14)
+#define AT91_PIN_PC14   (0x40 + 14)
-#define AT91_PIN_PC15   (PIN_BASE + 0x40 + 15)
+#define AT91_PIN_PC15   (0x40 + 15)
-#define AT91_PIN_PC16   (PIN_BASE + 0x40 + 16)
+#define AT91_PIN_PC16   (0x40 + 16)
-#define AT91_PIN_PC17   (PIN_BASE + 0x40 + 17)
+#define AT91_PIN_PC17   (0x40 + 17)
-#define AT91_PIN_PC18   (PIN_BASE + 0x40 + 18)
+#define AT91_PIN_PC18   (0x40 + 18)
-#define AT91_PIN_PC19   (PIN_BASE + 0x40 + 19)
+#define AT91_PIN_PC19   (0x40 + 19)
-#define AT91_PIN_PC20   (PIN_BASE + 0x40 + 20)
+#define AT91_PIN_PC20   (0x40 + 20)
-#define AT91_PIN_PC21   (PIN_BASE + 0x40 + 21)
+#define AT91_PIN_PC21   (0x40 + 21)
-#define AT91_PIN_PC22   (PIN_BASE + 0x40 + 22)
+#define AT91_PIN_PC22   (0x40 + 22)
-#define AT91_PIN_PC23   (PIN_BASE + 0x40 + 23)
+#define AT91_PIN_PC23   (0x40 + 23)
-#define AT91_PIN_PC24   (PIN_BASE + 0x40 + 24)
+#define AT91_PIN_PC24   (0x40 + 24)
-#define AT91_PIN_PC25   (PIN_BASE + 0x40 + 25)
+#define AT91_PIN_PC25   (0x40 + 25)
-#define AT91_PIN_PC26   (PIN_BASE + 0x40 + 26)
+#define AT91_PIN_PC26   (0x40 + 26)
-#define AT91_PIN_PC27   (PIN_BASE + 0x40 + 27)
+#define AT91_PIN_PC27   (0x40 + 27)
-#define AT91_PIN_PC28   (PIN_BASE + 0x40 + 28)
+#define AT91_PIN_PC28   (0x40 + 28)
-#define AT91_PIN_PC29   (PIN_BASE + 0x40 + 29)
+#define AT91_PIN_PC29   (0x40 + 29)
-#define AT91_PIN_PC30   (PIN_BASE + 0x40 + 30)
+#define AT91_PIN_PC30   (0x40 + 30)
-#define AT91_PIN_PC31   (PIN_BASE + 0x40 + 31)
+#define AT91_PIN_PC31   (0x40 + 31)
-#define AT91_PIN_PD0    (PIN_BASE + 0x60 + 0)
+#define AT91_PIN_PD0    (0x60 + 0)
-#define AT91_PIN_PD1    (PIN_BASE + 0x60 + 1)
+#define AT91_PIN_PD1    (0x60 + 1)
-#define AT91_PIN_PD2    (PIN_BASE + 0x60 + 2)
+#define AT91_PIN_PD2    (0x60 + 2)
-#define AT91_PIN_PD3    (PIN_BASE + 0x60 + 3)
+#define AT91_PIN_PD3    (0x60 + 3)
-#define AT91_PIN_PD4    (PIN_BASE + 0x60 + 4)
+#define AT91_PIN_PD4    (0x60 + 4)
-#define AT91_PIN_PD5    (PIN_BASE + 0x60 + 5)
+#define AT91_PIN_PD5    (0x60 + 5)
-#define AT91_PIN_PD6    (PIN_BASE + 0x60 + 6)
+#define AT91_PIN_PD6    (0x60 + 6)
-#define AT91_PIN_PD7    (PIN_BASE + 0x60 + 7)
+#define AT91_PIN_PD7    (0x60 + 7)
-#define AT91_PIN_PD8    (PIN_BASE + 0x60 + 8)
+#define AT91_PIN_PD8    (0x60 + 8)
-#define AT91_PIN_PD9    (PIN_BASE + 0x60 + 9)
+#define AT91_PIN_PD9    (0x60 + 9)
-#define AT91_PIN_PD10   (PIN_BASE + 0x60 + 10)
+#define AT91_PIN_PD10   (0x60 + 10)
-#define AT91_PIN_PD11   (PIN_BASE + 0x60 + 11)
+#define AT91_PIN_PD11   (0x60 + 11)
-#define AT91_PIN_PD12   (PIN_BASE + 0x60 + 12)
+#define AT91_PIN_PD12   (0x60 + 12)
-#define AT91_PIN_PD13   (PIN_BASE + 0x60 + 13)
+#define AT91_PIN_PD13   (0x60 + 13)
-#define AT91_PIN_PD14   (PIN_BASE + 0x60 + 14)
+#define AT91_PIN_PD14   (0x60 + 14)
-#define AT91_PIN_PD15   (PIN_BASE + 0x60 + 15)
+#define AT91_PIN_PD15   (0x60 + 15)
-#define AT91_PIN_PD16   (PIN_BASE + 0x60 + 16)
+#define AT91_PIN_PD16   (0x60 + 16)
-#define AT91_PIN_PD17   (PIN_BASE + 0x60 + 17)
+#define AT91_PIN_PD17   (0x60 + 17)
-#define AT91_PIN_PD18   (PIN_BASE + 0x60 + 18)
+#define AT91_PIN_PD18   (0x60 + 18)
-#define AT91_PIN_PD19   (PIN_BASE + 0x60 + 19)
+#define AT91_PIN_PD19   (0x60 + 19)
-#define AT91_PIN_PD20   (PIN_BASE + 0x60 + 20)
+#define AT91_PIN_PD20   (0x60 + 20)
-#define AT91_PIN_PD21   (PIN_BASE + 0x60 + 21)
+#define AT91_PIN_PD21   (0x60 + 21)
-#define AT91_PIN_PD22   (PIN_BASE + 0x60 + 22)
+#define AT91_PIN_PD22   (0x60 + 22)
-#define AT91_PIN_PD23   (PIN_BASE + 0x60 + 23)
+#define AT91_PIN_PD23   (0x60 + 23)
-#define AT91_PIN_PD24   (PIN_BASE + 0x60 + 24)
+#define AT91_PIN_PD24   (0x60 + 24)
-#define AT91_PIN_PD25   (PIN_BASE + 0x60 + 25)
+#define AT91_PIN_PD25   (0x60 + 25)
-#define AT91_PIN_PD26   (PIN_BASE + 0x60 + 26)
+#define AT91_PIN_PD26   (0x60 + 26)
-#define AT91_PIN_PD27   (PIN_BASE + 0x60 + 27)
+#define AT91_PIN_PD27   (0x60 + 27)
-#define AT91_PIN_PD28   (PIN_BASE + 0x60 + 28)
+#define AT91_PIN_PD28   (0x60 + 28)
-#define AT91_PIN_PD29   (PIN_BASE + 0x60 + 29)
+#define AT91_PIN_PD29   (0x60 + 29)
-#define AT91_PIN_PD30   (PIN_BASE + 0x60 + 30)
+#define AT91_PIN_PD30   (0x60 + 30)
-#define AT91_PIN_PD31   (PIN_BASE + 0x60 + 31)
+#define AT91_PIN_PD31   (0x60 + 31)
-#define AT91_PIN_PE0    (PIN_BASE + 0x80 + 0)
+#define AT91_PIN_PE0    (0x80 + 0)
-#define AT91_PIN_PE1    (PIN_BASE + 0x80 + 1)
+#define AT91_PIN_PE1    (0x80 + 1)
-#define AT91_PIN_PE2    (PIN_BASE + 0x80 + 2)
+#define AT91_PIN_PE2    (0x80 + 2)
-#define AT91_PIN_PE3    (PIN_BASE + 0x80 + 3)
+#define AT91_PIN_PE3    (0x80 + 3)
-#define AT91_PIN_PE4    (PIN_BASE + 0x80 + 4)
+#define AT91_PIN_PE4    (0x80 + 4)
-#define AT91_PIN_PE5    (PIN_BASE + 0x80 + 5)
+#define AT91_PIN_PE5    (0x80 + 5)
-#define AT91_PIN_PE6    (PIN_BASE + 0x80 + 6)
+#define AT91_PIN_PE6    (0x80 + 6)
-#define AT91_PIN_PE7    (PIN_BASE + 0x80 + 7)
+#define AT91_PIN_PE7    (0x80 + 7)
-#define AT91_PIN_PE8    (PIN_BASE + 0x80 + 8)
+#define AT91_PIN_PE8    (0x80 + 8)
-#define AT91_PIN_PE9    (PIN_BASE + 0x80 + 9)
+#define AT91_PIN_PE9    (0x80 + 9)
-#define AT91_PIN_PE10   (PIN_BASE + 0x80 + 10)
+#define AT91_PIN_PE10   (0x80 + 10)
-#define AT91_PIN_PE11   (PIN_BASE + 0x80 + 11)
+#define AT91_PIN_PE11   (0x80 + 11)
-#define AT91_PIN_PE12   (PIN_BASE + 0x80 + 12)
+#define AT91_PIN_PE12   (0x80 + 12)
-#define AT91_PIN_PE13   (PIN_BASE + 0x80 + 13)
+#define AT91_PIN_PE13   (0x80 + 13)
-#define AT91_PIN_PE14   (PIN_BASE + 0x80 + 14)
+#define AT91_PIN_PE14   (0x80 + 14)
-#define AT91_PIN_PE15   (PIN_BASE + 0x80 + 15)
+#define AT91_PIN_PE15   (0x80 + 15)
-#define AT91_PIN_PE16   (PIN_BASE + 0x80 + 16)
+#define AT91_PIN_PE16   (0x80 + 16)
-#define AT91_PIN_PE17   (PIN_BASE + 0x80 + 17)
+#define AT91_PIN_PE17   (0x80 + 17)
-#define AT91_PIN_PE18   (PIN_BASE + 0x80 + 18)
+#define AT91_PIN_PE18   (0x80 + 18)
-#define AT91_PIN_PE19   (PIN_BASE + 0x80 + 19)
+#define AT91_PIN_PE19   (0x80 + 19)
-#define AT91_PIN_PE20   (PIN_BASE + 0x80 + 20)
+#define AT91_PIN_PE20   (0x80 + 20)
-#define AT91_PIN_PE21   (PIN_BASE + 0x80 + 21)
+#define AT91_PIN_PE21   (0x80 + 21)
-#define AT91_PIN_PE22   (PIN_BASE + 0x80 + 22)
+#define AT91_PIN_PE22   (0x80 + 22)
-#define AT91_PIN_PE23   (PIN_BASE + 0x80 + 23)
+#define AT91_PIN_PE23   (0x80 + 23)
-#define AT91_PIN_PE24   (PIN_BASE + 0x80 + 24)
+#define AT91_PIN_PE24   (0x80 + 24)
-#define AT91_PIN_PE25   (PIN_BASE + 0x80 + 25)
+#define AT91_PIN_PE25   (0x80 + 25)
-#define AT91_PIN_PE26   (PIN_BASE + 0x80 + 26)
+#define AT91_PIN_PE26   (0x80 + 26)
-#define AT91_PIN_PE27   (PIN_BASE + 0x80 + 27)
+#define AT91_PIN_PE27   (0x80 + 27)
-#define AT91_PIN_PE28   (PIN_BASE + 0x80 + 28)
+#define AT91_PIN_PE28   (0x80 + 28)
-#define AT91_PIN_PE29   (PIN_BASE + 0x80 + 29)
+#define AT91_PIN_PE29   (0x80 + 29)
-#define AT91_PIN_PE30   (PIN_BASE + 0x80 + 30)
+#define AT91_PIN_PE30   (0x80 + 30)
-#define AT91_PIN_PE31   (PIN_BASE + 0x80 + 31)
+#define AT91_PIN_PE31   (0x80 + 31)
 #ifndef __ASSEMBLY__
 /* setup setup routines, called from board init or driver probe() */
@@ -215,8 +213,8 @@ extern void at91_gpio_resume(void);
 #include <asm/errno.h>
-#define gpio_to_irq(gpio) (gpio)
+#define gpio_to_irq(gpio) (gpio + NR_AIC_IRQS)
-#define irq_to_gpio(irq)  (irq)
+#define irq_to_gpio(irq)  (irq - NR_AIC_IRQS)
 #endif  /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 483478d8be6..2d0e4e99856 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -16,6 +16,12 @@
 #include <asm/sizes.h>
+/* DBGU base */
+/* rm9200, 9260/9g20, 9261/9g10, 9rl */
+#define AT91_BASE_DBGU0 0xfffff200
+/* 9263, 9g45, cap9 */
+#define AT91_BASE_DBGU1 0xffffee00
 #if defined(CONFIG_ARCH_AT91RM9200)
 #include <mach/at91rm9200.h>
 #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
@@ -52,6 +58,12 @@
 #endif
 /*
+ * On all at91 have the Advanced Interrupt Controller starts at address
+ * 0xfffff000
+ */
+#define AT91_AIC        0xfffff000
+/*
 * Peripheral identifiers/interrupts.
 */
 #define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index 4298e7806c7..4ca09ef7ca2 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -30,14 +30,6 @@
 #ifndef __ASSEMBLY__
-#ifndef CONFIG_ARCH_AT91X40
-#define __arch_ioremap  at91_ioremap
-#define __arch_iounmap  at91_iounmap
-#endif
-void __iomem *at91_ioremap(unsigned long phys, size_t size, unsigned int type);
-void at91_iounmap(volatile void __iomem *addr);
 static inline unsigned int at91_sys_read(unsigned int reg_offset)
 {
        void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS;
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
index 36bd55f3fc6..ac8b7dfc85e 100644
--- a/arch/arm/mach-at91/include/mach/irqs.h
+++ b/arch/arm/mach-at91/include/mach/irqs.h
@@ -31,7 +31,7 @@
 * Acknowledge interrupt with AIC after interrupt has been handled.
 *   (by kernel/irq.c)
 */
-#define irq_finish(irq) do { at91_sys_write(AT91_AIC_EOICR, 0); } while (0)
+#define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0)
 /*
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h
index 36af14bc13b..cbd64f3bcec 100644
--- a/arch/arm/mach-at91/include/mach/system.h
+++ b/arch/arm/mach-at91/include/mach/system.h
@@ -47,13 +47,4 @@ static inline void arch_idle(void)
 #endif
 }
-void (*at91_arch_reset)(void);
-static inline void arch_reset(char mode, const char *cmd)
-{
-        /* call the CPU-specific reset function */
-        if (at91_arch_reset)
-                (at91_arch_reset)();
-}
 #endif
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 85820ad801c..5e917a66edd 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -23,70 +23,15 @@
 #include <mach/hardware.h>
-#if defined(CONFIG_ARCH_AT91RM9200)
+#ifdef CONFIG_ARCH_AT91X40
-#define CLOCK_TICK_RATE         (AT91_SLOW_CLOCK)
+#define AT91X40_MASTER_CLOCK    40000000
+#define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
-#elif defined(CONFIG_ARCH_AT91SAM9260)
-#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
-#define AT91SAM9_MASTER_CLOCK   90000000
-#else
-#define AT91SAM9_MASTER_CLOCK   99300000
-#endif
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-#elif defined(CONFIG_ARCH_AT91SAM9261)
-#define AT91SAM9_MASTER_CLOCK   99300000
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-#elif defined(CONFIG_ARCH_AT91SAM9G10)
-#define AT91SAM9_MASTER_CLOCK   133000000
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-#elif defined(CONFIG_ARCH_AT91SAM9263)
-#if defined(CONFIG_MACH_USB_A9263)
-#define AT91SAM9_MASTER_CLOCK   90000000
-#else
-#define AT91SAM9_MASTER_CLOCK   99959500
-#endif
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-#elif defined(CONFIG_ARCH_AT91SAM9RL)
-#define AT91SAM9_MASTER_CLOCK   100000000
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-#elif defined(CONFIG_ARCH_AT91SAM9G20)
-#if defined(CONFIG_MACH_USB_A9G20)
-#define AT91SAM9_MASTER_CLOCK   133000000
 #else
-#define AT91SAM9_MASTER_CLOCK   132096000
-#endif
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
-#define AT91SAM9_MASTER_CLOCK   133333333
+#define CLOCK_TICK_RATE         12345678
-#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#define AT91CAP9_MASTER_CLOCK   100000000
-#define CLOCK_TICK_RATE         (AT91CAP9_MASTER_CLOCK/16)
-#elif defined(CONFIG_ARCH_AT91X40)
-#define AT91X40_MASTER_CLOCK    40000000
-#define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
 #endif
-#endif
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 18bdcdeb474..0234fd9d20d 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -24,8 +24,10 @@
 #include <linux/io.h>
 #include <linux/atmel_serial.h>
-#if defined(CONFIG_AT91_EARLY_DBGU)
+#if defined(CONFIG_AT91_EARLY_DBGU0)
-#define UART_OFFSET (AT91_DBGU + AT91_BASE_SYS)
+#define UART_OFFSET AT91_BASE_DBGU0
+#elif defined(CONFIG_AT91_EARLY_DBGU1)
+#define UART_OFFSET AT91_BASE_DBGU1
 #elif defined(CONFIG_AT91_EARLY_USART0)
 #define UART_OFFSET AT91_USART0
 #elif defined(CONFIG_AT91_EARLY_USART1)
diff --git a/arch/arm/mach-at91/include/mach/vmalloc.h b/arch/arm/mach-at91/include/mach/vmalloc.h
deleted file mode 100644
index 8e4a1bd0ab1..00000000000
--- a/arch/arm/mach-at91/include/mach/vmalloc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/vmalloc.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#include <mach/hardware.h>
-#define VMALLOC_END             (AT91_VIRT_BASE & PGDIR_MASK)
-#endif
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index 9665265ec75..be6b639ecd7 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -33,17 +33,18 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
+void __iomem *at91_aic_base;
 static void at91_aic_mask_irq(struct irq_data *d)
 {
        /* Disable interrupt on AIC */
-        at91_sys_write(AT91_AIC_IDCR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IDCR, 1 << d->irq);
 }
 static void at91_aic_unmask_irq(struct irq_data *d)
 {
        /* Enable interrupt on AIC */
-        at91_sys_write(AT91_AIC_IECR, 1 << d->irq);
+        at91_aic_write(AT91_AIC_IECR, 1 << d->irq);
 }
 unsigned int at91_extern_irq;
@@ -77,8 +78,8 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                return -EINVAL;
        }
-        smr = at91_sys_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
+        smr = at91_aic_read(AT91_AIC_SMR(d->irq)) & ~AT91_AIC_SRCTYPE;
-        at91_sys_write(AT91_AIC_SMR(d->irq), smr | srctype);
+        at91_aic_write(AT91_AIC_SMR(d->irq), smr | srctype);
        return 0;
 }
@@ -102,15 +103,15 @@ static int at91_aic_set_wake(struct irq_data *d, unsigned value)
 void at91_irq_suspend(void)
 {
-        backups = at91_sys_read(AT91_AIC_IMR);
+        backups = at91_aic_read(AT91_AIC_IMR);
-        at91_sys_write(AT91_AIC_IDCR, backups);
+        at91_aic_write(AT91_AIC_IDCR, backups);
-        at91_sys_write(AT91_AIC_IECR, wakeups);
+        at91_aic_write(AT91_AIC_IECR, wakeups);
 }
 void at91_irq_resume(void)
 {
-        at91_sys_write(AT91_AIC_IDCR, wakeups);
+        at91_aic_write(AT91_AIC_IDCR, wakeups);
-        at91_sys_write(AT91_AIC_IECR, backups);
+        at91_aic_write(AT91_AIC_IECR, backups);
 }
 #else
@@ -133,34 +134,39 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
 {
        unsigned int i;
+        at91_aic_base = ioremap(AT91_AIC, 512);
+        if (!at91_aic_base)
+                panic("Impossible to ioremap AT91_AIC\n");
        /*
         * The IVR is used by macro get_irqnr_and_base to read and verify.
         * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
         */
        for (i = 0; i < NR_AIC_IRQS; i++) {
                /* Put irq number in Source Vector Register: */
-                at91_sys_write(AT91_AIC_SVR(i), i);
+                at91_aic_write(AT91_AIC_SVR(i), i);
                /* Active Low interrupt, with the specified priority */
-                at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
+                at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
                irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
                if (i < 8)
-                        at91_sys_write(AT91_AIC_EOICR, 0);
+                        at91_aic_write(AT91_AIC_EOICR, 0);
        }
        /*
         * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
         * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
         */
-        at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS);
+        at91_aic_write(AT91_AIC_SPU, NR_AIC_IRQS);
        /* No debugging in AIC: Debug (Protect) Control Register */
-        at91_sys_write(AT91_AIC_DCR, 0);
+        at91_aic_write(AT91_AIC_DCR, 0);
        /* Disable and clear all interrupts initially */
-        at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
+        at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
-        at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
+        at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
 }
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 7046158109d..62ad95556c3 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -34,7 +34,7 @@
 /*
 * Show the reason for the previous system reset.
 */
-#if defined(AT91_SHDWC)
+#if defined(AT91_RSTC)
 #include <mach/at91_rstc.h>
 #include <mach/at91_shdwc.h>
@@ -58,8 +58,11 @@ static void __init show_reset_status(void)
        char *reason, *r2 = reset;
        u32 reset_type, wake_type;
+        if (!at91_shdwc_base)
+                return;
        reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
-        wake_type = at91_sys_read(AT91_SHDW_SR);
+        wake_type = at91_shdwc_read(AT91_SHDW_SR);
        switch (reset_type) {
        case AT91_RSTC_RSTTYP_GENERAL:
@@ -215,7 +218,7 @@ static int at91_pm_enter(suspend_state_t state)
                                        | (1 << AT91_ID_FIQ)
                                        | (1 << AT91_ID_SYS)
                                        | (at91_extern_irq))
-                                & at91_sys_read(AT91_AIC_IMR),
+                                & at91_aic_read(AT91_AIC_IMR),
                        state);
        switch (state) {
@@ -283,7 +286,7 @@ static int at91_pm_enter(suspend_state_t state)
        }
        pr_debug("AT91: PM - wakeup %08x\n",
-                        at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
+                        at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR));
 error:
        target_state = PM_SUSPEND_ON;
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index 5eab6aa621d..8294783b679 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -10,38 +10,58 @@
 #include <linux/module.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 #include <mach/at91sam9_smc.h>
 #include "sam9_smc.h"
-void __init sam9_smc_configure(int cs, struct sam9_smc_config* config)
+#define AT91_SMC_CS(id, n)      (smc_base_addr[id] + ((n) * 0x10))
+static void __iomem *smc_base_addr[2];
+static void __init sam9_smc_cs_configure(void __iomem *base, struct sam9_smc_config* config)
 {
        /* Setup register */
-        at91_sys_write(AT91_SMC_SETUP(cs),
+        __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup)
-                  AT91_SMC_NWESETUP_(config->nwe_setup)
+                   | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
-                | AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
+                   | AT91_SMC_NRDSETUP_(config->nrd_setup)
-                | AT91_SMC_NRDSETUP_(config->nrd_setup)
+                   | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup),
-                | AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup)
+                   base + AT91_SMC_SETUP);
-        );
        /* Pulse register */
-        at91_sys_write(AT91_SMC_PULSE(cs),
+        __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse)
-                  AT91_SMC_NWEPULSE_(config->nwe_pulse)
+                   | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
-                | AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
+                   | AT91_SMC_NRDPULSE_(config->nrd_pulse)
-                | AT91_SMC_NRDPULSE_(config->nrd_pulse)
+                   | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse),
-                | AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse)
+                   base + AT91_SMC_PULSE);
-        );
        /* Cycle register */
-        at91_sys_write(AT91_SMC_CYCLE(cs),
+        __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle)
-                  AT91_SMC_NWECYCLE_(config->write_cycle)
+                   | AT91_SMC_NRDCYCLE_(config->read_cycle),
-                | AT91_SMC_NRDCYCLE_(config->read_cycle)
+                   base + AT91_SMC_CYCLE);
-        );
        /* Mode register */
-        at91_sys_write(AT91_SMC_MODE(cs),
+        __raw_writel(config->mode
-                  config->mode
+                   | AT91_SMC_TDF_(config->tdf_cycles),
-                | AT91_SMC_TDF_(config->tdf_cycles)
+                   base + AT91_SMC_MODE);
-        );
+}
+void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config)
+{
+        sam9_smc_cs_configure(AT91_SMC_CS(id, cs), config);
+}
+void __init at91sam9_ioremap_smc(int id, u32 addr)
+{
+        if (id > 1) {
+                pr_warn("%s: id > 2\n", __func__);
+                return;
+        }
+        smc_base_addr[id] = ioremap(addr, 512);
+        if (!smc_base_addr[id])
+                pr_warn("Impossible to ioremap smc.%d 0x%x\n", id, addr);
 }
diff --git a/arch/arm/mach-at91/sam9_smc.h b/arch/arm/mach-at91/sam9_smc.h
index bf72cfb3455..039c5ce17ae 100644
--- a/arch/arm/mach-at91/sam9_smc.h
+++ b/arch/arm/mach-at91/sam9_smc.h
@@ -30,4 +30,5 @@ struct sam9_smc_config {
        u8 tdf_cycles:4;
 };
-extern void __init sam9_smc_configure(int cs, struct sam9_smc_config* config);
+extern void __init sam9_smc_configure(int id, int cs, struct sam9_smc_config* config);
+extern void __init at91sam9_ioremap_smc(int id, u32 addr);
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index aa64294c7db..8bdcc3cb601 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -8,6 +8,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/mm.h>
+#include <linux/pm.h>
 #include <asm/mach/map.h>
@@ -15,6 +16,7 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91_pmc.h>
+#include <mach/at91_shdwc.h>
 #include "soc.h"
 #include "generic.h"
@@ -73,27 +75,6 @@ static struct map_desc at91_io_desc __initdata = {
        .type           = MT_DEVICE,
 };
-void __iomem *at91_ioremap(unsigned long p, size_t size, unsigned int type)
-{
-        if (p >= AT91_BASE_SYS && p <= (AT91_BASE_SYS + SZ_16K - 1))
-                return (void __iomem *)AT91_IO_P2V(p);
-        return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
-}
-EXPORT_SYMBOL(at91_ioremap);
-void at91_iounmap(volatile void __iomem *addr)
-{
-        unsigned long virt = (unsigned long)addr;
-        if (virt >= VMALLOC_START && virt < VMALLOC_END)
-                __iounmap(addr);
-}
-EXPORT_SYMBOL(at91_iounmap);
-#define AT91_DBGU0      0xfffff200
-#define AT91_DBGU1      0xffffee00
 static void __init soc_detect(u32 dbgu_base)
 {
        u32 cidr, socid;
@@ -266,9 +247,9 @@ void __init at91_map_io(void)
        at91_soc_initdata.type = AT91_SOC_NONE;
        at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
-        soc_detect(AT91_DBGU0);
+        soc_detect(AT91_BASE_DBGU0);
        if (!at91_soc_is_detected())
-                soc_detect(AT91_DBGU1);
+                soc_detect(AT91_BASE_DBGU1);
        if (!at91_soc_is_detected())
                panic("AT91: Impossible to detect the SOC type");
@@ -285,8 +266,25 @@ void __init at91_map_io(void)
                at91_boot_soc.map_io();
 }
+void __iomem *at91_shdwc_base = NULL;
+static void at91sam9_poweroff(void)
+{
+        at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+void __init at91_ioremap_shdwc(u32 base_addr)
+{
+        at91_shdwc_base = ioremap(base_addr, 16);
+        if (!at91_shdwc_base)
+                panic("Impossible to ioremap at91_shdwc_base\n");
+        pm_power_off = at91sam9_poweroff;
+}
 void __init at91_initialize(unsigned long main_clock)
 {
+        at91_boot_soc.ioremap_registers();
        /* Init clock subsystem */
        at91_clock_init(main_clock);
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 21ed8816e6f..4588ae6f7ac 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -7,6 +7,7 @@
 struct at91_init_soc {
        unsigned int *default_irq_priority;
        void (*map_io)(void);
+        void (*ioremap_registers)(void);
        void (*register_clocks)(void);
        void (*init)(void);
 };
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 31a143592c8..9e5e7552498 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -49,7 +49,29 @@ HW_DECLARE_SPINLOCK(gpio)
 #endif
 /* sysctl */
-int bcmring_arch_warm_reboot;   /* do a warm reboot on hard reset */
+static int bcmring_arch_warm_reboot;    /* do a warm reboot on hard reset */
+static void bcmring_restart(char mode, const char *cmd)
+{
+        printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
+        if (mode == 'h') {
+                /* Reboot configured in proc entry */
+                if (bcmring_arch_warm_reboot) {
+                        printk("warm reset\n");
+                        /* Issue Warm reset (do not reset ethernet switch, keep alive) */
+                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
+                } else {
+                        /* Force reset of everything */
+                        printk("force reset\n");
+                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
+                }
+        } else {
+                /* Force reset of everything */
+                printk("force reset\n");
+                chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
+        }
+}
 static struct ctl_table_header *bcmring_sysctl_header;
@@ -173,4 +195,5 @@ MACHINE_START(BCMRING, "BCMRING")
        .init_irq = bcmring_init_irq,
        .timer = &bcmring_timer,
        .init_machine = bcmring_init_machine
+        .restart = bcmring_restart,
 MACHINE_END
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 430da120a29..6b67b7e8426 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -25,7 +25,6 @@
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
-#include <linux/sysdev.h>
 #include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/clkdev.h>
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index f4d4d6d174d..1a1a27dd565 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -1615,7 +1615,7 @@ DMA_MemType_t dma_mem_type(void *addr)
 {
        unsigned long addrVal = (unsigned long)addr;
-        if (addrVal >= VMALLOC_END) {
+        if (addrVal >= CONSISTENT_BASE) {
                /* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */
                /* dma_alloc_xxx pages are physically and virtually contiguous */
diff --git a/arch/arm/mach-bcmring/include/mach/system.h b/arch/arm/mach-bcmring/include/mach/system.h
index 38b37060d42..cb78250db64 100644
--- a/arch/arm/mach-bcmring/include/mach/system.h
+++ b/arch/arm/mach-bcmring/include/mach/system.h
@@ -20,35 +20,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <mach/csp/chipcHw_inline.h>
-extern int bcmring_arch_warm_reboot;
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
-        if (mode == 'h') {
-                /* Reboot configured in proc entry */
-                if (bcmring_arch_warm_reboot) {
-                        printk("warm reset\n");
-                        /* Issue Warm reset (do not reset ethernet switch, keep alive) */
-                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
-                } else {
-                        /* Force reset of everything */
-                        printk("force reset\n");
-                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-                }
-        } else {
-                /* Force reset of everything */
-                printk("force reset\n");
-                chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-        }
-}
 #endif
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
deleted file mode 100644
index 7397bd7817d..00000000000
--- a/arch/arm/mach-bcmring/include/mach/vmalloc.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*
- * Move VMALLOC_END to 0xf0000000 so that the vm space can range from
- * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
- * larger physical memory designs better.
- */
-#define VMALLOC_END       0xf0000000UL
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index 4a197315f0c..f2f0256232e 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -4,7 +4,7 @@
 # Object file lists.
-obj-y                   := irq.o mm.o time.o
+obj-y                   := common.o
 obj-m                   :=
 obj-n                   :=
 obj-                    :=
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 0276091b7f8..3fb79a1d0bd 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -68,5 +68,6 @@ MACHINE_START(AUTCPU12, "autronix autcpu12")
        .map_io         = autcpu12_map_io,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
+        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index 25b3bfd0e85..c314f49d6ef 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -59,4 +59,5 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712")
        .map_io         = cdb89712_map_io,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
+        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
index 1df9ec67aa9..a70147e347a 100644
--- a/arch/arm/mach-clps711x/ceiva.c
+++ b/arch/arm/mach-clps711x/ceiva.c
@@ -60,4 +60,5 @@ MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame")
        .map_io         = ceiva_map_io,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
+        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/clep7312.c
index 80496c09ac5..dbc7842639d 100644
--- a/arch/arm/mach-clps711x/clep7312.c
+++ b/arch/arm/mach-clps711x/clep7312.c
@@ -41,5 +41,6 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
        .map_io         = clps711x_map_io,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
+        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
new file mode 100644
index 00000000000..ab1711b9b4d
--- /dev/null
+++ b/arch/arm/mach-clps711x/common.c
@@ -0,0 +1,227 @@
+/*
+ *  linux/arch/arm/mach-clps711x/core.c
+ *
+ *  Core support for the CLPS711x-based machines.
+ *
+ *  Copyright (C) 2001,2011 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+#include <linux/timex.h>
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/leds.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/clps7111.h>
+/*
+ * This maps the generic CLPS711x registers
+ */
+static struct map_desc clps711x_io_desc[] __initdata = {
+        {
+                .virtual        = CLPS7111_VIRT_BASE,
+                .pfn            = __phys_to_pfn(CLPS7111_PHYS_BASE),
+                .length         = SZ_1M,
+                .type           = MT_DEVICE
+        }
+};
+void __init clps711x_map_io(void)
+{
+        iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
+}
+static void int1_mask(struct irq_data *d)
+{
+        u32 intmr1;
+        intmr1 = clps_readl(INTMR1);
+        intmr1 &= ~(1 << d->irq);
+        clps_writel(intmr1, INTMR1);
+}
+static void int1_ack(struct irq_data *d)
+{
+        u32 intmr1;
+        intmr1 = clps_readl(INTMR1);
+        intmr1 &= ~(1 << d->irq);
+        clps_writel(intmr1, INTMR1);
+        switch (d->irq) {
+        case IRQ_CSINT:  clps_writel(0, COEOI);  break;
+        case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
+        case IRQ_TC2OI:  clps_writel(0, TC2EOI); break;
+        case IRQ_RTCMI:  clps_writel(0, RTCEOI); break;
+        case IRQ_TINT:   clps_writel(0, TEOI);   break;
+        case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
+        }
+}
+static void int1_unmask(struct irq_data *d)
+{
+        u32 intmr1;
+        intmr1 = clps_readl(INTMR1);
+        intmr1 |= 1 << d->irq;
+        clps_writel(intmr1, INTMR1);
+}
+static struct irq_chip int1_chip = {
+        .irq_ack        = int1_ack,
+        .irq_mask       = int1_mask,
+        .irq_unmask     = int1_unmask,
+};
+static void int2_mask(struct irq_data *d)
+{
+        u32 intmr2;
+        intmr2 = clps_readl(INTMR2);
+        intmr2 &= ~(1 << (d->irq - 16));
+        clps_writel(intmr2, INTMR2);
+}
+static void int2_ack(struct irq_data *d)
+{
+        u32 intmr2;
+        intmr2 = clps_readl(INTMR2);
+        intmr2 &= ~(1 << (d->irq - 16));
+        clps_writel(intmr2, INTMR2);
+        switch (d->irq) {
+        case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
+        }
+}
+static void int2_unmask(struct irq_data *d)
+{
+        u32 intmr2;
+        intmr2 = clps_readl(INTMR2);
+        intmr2 |= 1 << (d->irq - 16);
+        clps_writel(intmr2, INTMR2);
+}
+static struct irq_chip int2_chip = {
+        .irq_ack        = int2_ack,
+        .irq_mask       = int2_mask,
+        .irq_unmask     = int2_unmask,
+};
+void __init clps711x_init_irq(void)
+{
+        unsigned int i;
+        for (i = 0; i < NR_IRQS; i++) {
+                if (INT1_IRQS & (1 << i)) {
+                        irq_set_chip_and_handler(i, &int1_chip,
+                                                 handle_level_irq);
+                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+                }
+                if (INT2_IRQS & (1 << i)) {
+                        irq_set_chip_and_handler(i, &int2_chip,
+                                                 handle_level_irq);
+                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+                }
+        }
+        /*
+         * Disable interrupts
+         */
+        clps_writel(0, INTMR1);
+        clps_writel(0, INTMR2);
+        /*
+         * Clear down any pending interrupts
+         */
+        clps_writel(0, COEOI);
+        clps_writel(0, TC1EOI);
+        clps_writel(0, TC2EOI);
+        clps_writel(0, RTCEOI);
+        clps_writel(0, TEOI);
+        clps_writel(0, UMSEOI);
+        clps_writel(0, SYNCIO);
+        clps_writel(0, KBDEOI);
+}
+/*
+ * gettimeoffset() returns time since last timer tick, in usecs.
+ *
+ * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
+ * 'tick' is usecs per jiffy.
+ */
+static unsigned long clps711x_gettimeoffset(void)
+{
+        unsigned long hwticks;
+        hwticks = LATCH - (clps_readl(TC2D) & 0xffff);  /* since last underflow */
+        return (hwticks * (tick_nsec / 1000)) / LATCH;
+}
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t p720t_timer_interrupt(int irq, void *dev_id)
+{
+        timer_tick();
+        return IRQ_HANDLED;
+}
+static struct irqaction clps711x_timer_irq = {
+        .name           = "CLPS711x Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = p720t_timer_interrupt,
+};
+static void __init clps711x_timer_init(void)
+{
+        struct timespec tv;
+        unsigned int syscon;
+        syscon = clps_readl(SYSCON1);
+        syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
+        clps_writel(syscon, SYSCON1);
+        clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
+        setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
+        tv.tv_nsec = 0;
+        tv.tv_sec = clps_readl(RTCDR);
+        do_settimeofday(&tv);
+}
+struct sys_timer clps711x_timer = {
+        .init           = clps711x_timer_init,
+        .offset         = clps711x_gettimeoffset,
+};
+void clps711x_restart(char mode, const char *cmd)
+{
+        soft_restart(0);
+}
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h
index 2b8b801f1dc..fc0f0650dcb 100644
--- a/arch/arm/mach-clps711x/common.h
+++ b/arch/arm/mach-clps711x/common.h
@@ -9,3 +9,4 @@ struct sys_timer;
 extern void clps711x_map_io(void);
 extern void clps711x_init_irq(void);
 extern struct sys_timer clps711x_timer;
+extern void clps711x_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
index 9721f6111dc..5fad0b4f40a 100644
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ b/arch/arm/mach-clps711x/edb7211-arch.c
@@ -62,4 +62,5 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
        .reserve        = edb7211_reserve,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
+        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index d9925668729..3a3f0b702cb 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -78,4 +78,5 @@ MACHINE_START(FORTUNET, "ARM-FortuNet")
        .map_io         = clps711x_map_io,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
+        .restart        = clps711x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h
index f916cd7a477..23d6ef8c84d 100644
--- a/arch/arm/mach-clps711x/include/mach/system.h
+++ b/arch/arm/mach-clps711x/include/mach/system.h
@@ -32,9 +32,4 @@ static inline void arch_idle(void)
        mov     r0, r0");
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        cpu_reset(0);
-}
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/vmalloc.h b/arch/arm/mach-clps711x/include/mach/vmalloc.h
deleted file mode 100644
index 467b96137e4..00000000000
--- a/arch/arm/mach-clps711x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  arch/arm/mach-clps711x/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END       0xd0000000UL
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
deleted file mode 100644
index c2eceee645e..00000000000
--- a/arch/arm/mach-clps711x/irq.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/irq.c
- *
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/io.h>
-#include <asm/mach/irq.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/hardware/clps7111.h>
-static void int1_mask(struct irq_data *d)
-{
-        u32 intmr1;
-        intmr1 = clps_readl(INTMR1);
-        intmr1 &= ~(1 << d->irq);
-        clps_writel(intmr1, INTMR1);
-}
-static void int1_ack(struct irq_data *d)
-{
-        u32 intmr1;
-        intmr1 = clps_readl(INTMR1);
-        intmr1 &= ~(1 << d->irq);
-        clps_writel(intmr1, INTMR1);
-        switch (d->irq) {
-        case IRQ_CSINT:  clps_writel(0, COEOI);  break;
-        case IRQ_TC1OI:  clps_writel(0, TC1EOI); break;
-        case IRQ_TC2OI:  clps_writel(0, TC2EOI); break;
-        case IRQ_RTCMI:  clps_writel(0, RTCEOI); break;
-        case IRQ_TINT:   clps_writel(0, TEOI);   break;
-        case IRQ_UMSINT: clps_writel(0, UMSEOI); break;
-        }
-}
-static void int1_unmask(struct irq_data *d)
-{
-        u32 intmr1;
-        intmr1 = clps_readl(INTMR1);
-        intmr1 |= 1 << d->irq;
-        clps_writel(intmr1, INTMR1);
-}
-static struct irq_chip int1_chip = {
-        .irq_ack        = int1_ack,
-        .irq_mask       = int1_mask,
-        .irq_unmask     = int1_unmask,
-};
-static void int2_mask(struct irq_data *d)
-{
-        u32 intmr2;
-        intmr2 = clps_readl(INTMR2);
-        intmr2 &= ~(1 << (d->irq - 16));
-        clps_writel(intmr2, INTMR2);
-}
-static void int2_ack(struct irq_data *d)
-{
-        u32 intmr2;
-        intmr2 = clps_readl(INTMR2);
-        intmr2 &= ~(1 << (d->irq - 16));
-        clps_writel(intmr2, INTMR2);
-        switch (d->irq) {
-        case IRQ_KBDINT: clps_writel(0, KBDEOI); break;
-        }
-}
-static void int2_unmask(struct irq_data *d)
-{
-        u32 intmr2;
-        intmr2 = clps_readl(INTMR2);
-        intmr2 |= 1 << (d->irq - 16);
-        clps_writel(intmr2, INTMR2);
-}
-static struct irq_chip int2_chip = {
-        .irq_ack        = int2_ack,
-        .irq_mask       = int2_mask,
-        .irq_unmask     = int2_unmask,
-};
-void __init clps711x_init_irq(void)
-{
-        unsigned int i;
-        for (i = 0; i < NR_IRQS; i++) {
-                if (INT1_IRQS & (1 << i)) {
-                        irq_set_chip_and_handler(i, &int1_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                }
-                if (INT2_IRQS & (1 << i)) {
-                        irq_set_chip_and_handler(i, &int2_chip,
-                                                 handle_level_irq);
-                        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                }                       
-        }
-        /*
-         * Disable interrupts
-         */
-        clps_writel(0, INTMR1);
-        clps_writel(0, INTMR2);
-        /*
-         * Clear down any pending interrupts
-         */
-        clps_writel(0, COEOI);
-        clps_writel(0, TC1EOI);
-        clps_writel(0, TC2EOI);
-        clps_writel(0, RTCEOI);
-        clps_writel(0, TEOI);
-        clps_writel(0, UMSEOI);
-        clps_writel(0, SYNCIO);
-        clps_writel(0, KBDEOI);
-}
diff --git a/arch/arm/mach-clps711x/mm.c b/arch/arm/mach-clps711x/mm.c
deleted file mode 100644
index 98659217676..00000000000
--- a/arch/arm/mach-clps711x/mm.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/mm.c
- *
- *  Generic MM setup for the CLPS711x-based machines.
- *
- *  Copyright (C) 2001 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <asm/sizes.h>
-#include <mach/hardware.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <asm/hardware/clps7111.h>
-/*
- * This maps the generic CLPS711x registers
- */
-static struct map_desc clps711x_io_desc[] __initdata = {
-        {
-                .virtual        = CLPS7111_VIRT_BASE,
-                .pfn            = __phys_to_pfn(CLPS7111_PHYS_BASE),
-                .length         = SZ_1M,
-                .type           = MT_DEVICE
-        }
-};
-void __init clps711x_map_io(void)
-{
-        iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc));
-}
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index 6ecea95f38b..42ee8f33eaf 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -93,6 +93,7 @@ MACHINE_START(P720T, "ARM-Prospector720T")
        .map_io         = p720t_map_io,
        .init_irq       = clps711x_init_irq,
        .timer          = &clps711x_timer,
+        .restart        = clps711x_restart,
 MACHINE_END
 static int p720t_hw_init(void)
diff --git a/arch/arm/mach-clps711x/time.c b/arch/arm/mach-clps711x/time.c
deleted file mode 100644
index d581ef0bcd2..00000000000
--- a/arch/arm/mach-clps711x/time.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- *  linux/arch/arm/mach-clps711x/time.c
- *
- *  Copyright (C) 2001 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/timex.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/leds.h>
-#include <asm/hardware/clps7111.h>
-#include <asm/mach/time.h>
-/*
- * gettimeoffset() returns time since last timer tick, in usecs.
- *
- * 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
- * 'tick' is usecs per jiffy.
- */
-static unsigned long clps711x_gettimeoffset(void)
-{
-        unsigned long hwticks;
-        hwticks = LATCH - (clps_readl(TC2D) & 0xffff);  /* since last underflow */
-        return (hwticks * (tick_nsec / 1000)) / LATCH;
-}
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t
-p720t_timer_interrupt(int irq, void *dev_id)
-{
-        timer_tick();
-        return IRQ_HANDLED;
-}
-static struct irqaction clps711x_timer_irq = {
-        .name           = "CLPS711x Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = p720t_timer_interrupt,
-};
-static void __init clps711x_timer_init(void)
-{
-        struct timespec tv;
-        unsigned int syscon;
-        syscon = clps_readl(SYSCON1);
-        syscon |= SYSCON1_TC2S | SYSCON1_TC2M;
-        clps_writel(syscon, SYSCON1);
-        clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
-        setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
-        tv.tv_nsec = 0;
-        tv.tv_sec = clps_readl(RTCDR);
-        do_settimeofday(&tv);
-}
-struct sys_timer clps711x_timer = {
-        .init           = clps711x_timer_init,
-        .offset         = clps711x_gettimeoffset,
-};
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 55f7b4b08ab..2c5fb4c7e50 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -26,6 +26,7 @@
 #include <linux/mtd/partitions.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -201,5 +202,7 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
        .map_io         = cns3420_map_io,
        .init_irq       = cns3xxx_init_irq,
        .timer          = &cns3xxx_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = cns3420_init,
+        .restart        = cns3xxx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index fcd225343c6..4894b8c1715 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -22,5 +22,6 @@ static inline void cns3xxx_l2x0_init(void) {}
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
+void cns3xxx_restart(char, const char *);
 #endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
index d87bfc397d3..01c57df5f71 100644
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -8,8 +8,6 @@
 * published by the Free Software Foundation.
 */
-#include <asm/hardware/entry-macro-gic.S>
                .macro  disable_fiq
                .endm
diff --git a/arch/arm/mach-cns3xxx/include/mach/system.h b/arch/arm/mach-cns3xxx/include/mach/system.h
index 4f16c9b79f7..9e56b7dc133 100644
--- a/arch/arm/mach-cns3xxx/include/mach/system.h
+++ b/arch/arm/mach-cns3xxx/include/mach/system.h
@@ -11,7 +11,6 @@
 #ifndef __MACH_SYSTEM_H
 #define __MACH_SYSTEM_H
-#include <linux/io.h>
 #include <asm/proc-fns.h>
 static inline void arch_idle(void)
@@ -23,6 +22,4 @@ static inline void arch_idle(void)
        cpu_do_idle();
 }
-void arch_reset(char mode, const char *cmd);
 #endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
deleted file mode 100644
index 1dd231d2f77..00000000000
--- a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright 2000 Russell King.
- * Copyright 2003 ARM Limited
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END             0xd8000000UL
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 0f8fca48a5e..e159d69967c 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -151,13 +151,12 @@ static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
        struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
        struct resource *res_io = &cnspci->res_io;
        struct resource *res_mem = &cnspci->res_mem;
-        struct resource **sysres = sys->resource;
        BUG_ON(request_resource(&iomem_resource, res_io) ||
               request_resource(&iomem_resource, res_mem));
-        sysres[0] = res_io;
+        pci_add_resource(&sys->resources, res_io);
-        sysres[1] = res_mem;
+        pci_add_resource(&sys->resources, res_mem);
        return 1;
 }
@@ -169,7 +168,8 @@ static struct pci_ops cns3xxx_pcie_ops = {
 static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
 {
-        return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
+        return pci_scan_root_bus(NULL, sys->busnr, &cns3xxx_pcie_ops, sys,
+                                 &sys->resources);
 }
 static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 0c04678615c..36458080332 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -11,9 +11,9 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/atomic.h>
-#include <mach/system.h>
 #include <mach/cns3xxx.h>
 #include <mach/pm.h>
+#include "core.h"
 void cns3xxx_pwr_clk_en(unsigned int block)
 {
@@ -89,7 +89,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
 }
 EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
-void arch_reset(char mode, const char *cmd)
+void cns3xxx_restart(char mode, const char *cmd)
 {
        /*
         * To reset, we hit the on-board reset register
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 495e31306fc..2db78bd5c83 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -4,7 +4,7 @@
 #
 # Common objects
-obj-y                   := time.o clock.o serial.o io.o psc.o \
+obj-y                   := time.o clock.o serial.o psc.o \
                           dma.o usb.o common.o sram.o aemif.o
 obj-$(CONFIG_DAVINCI_MUX)               += mux.o
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 11c3db98528..dc1afe5be20 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -682,4 +682,5 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
        .timer          = &davinci_timer,
        .init_machine   = da830_evm_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = da8xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6659a90dbca..6b22b543a83 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -127,7 +127,7 @@ static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
        size_t retlen;
        if (!strcmp(mtd->name, "MAC-Address")) {
-                mtd->read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
+                mtd_read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
                if (retlen == ETH_ALEN)
                        pr_info("Read MAC addr from SPI Flash: %pM\n",
                                mac_addr);
@@ -1411,4 +1411,5 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
        .timer          = &davinci_timer,
        .init_machine   = da850_evm_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = da8xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 4e0e707c313..275341f159f 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -357,4 +357,5 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
        .timer        = &davinci_timer,
        .init_machine = dm355_evm_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = davinci_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index ff2d2413279..e99db28181a 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -276,4 +276,5 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
        .timer        = &davinci_timer,
        .init_machine = dm355_leopard_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = davinci_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 46e1f4173b9..346e1de2f5a 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -618,5 +618,6 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
        .timer          = &davinci_timer,
        .init_machine   = dm365_evm_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = davinci_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 0cf8abf78d3..a64b49cfedc 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -719,4 +719,5 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
        .timer        = &davinci_timer,
        .init_machine = davinci_evm_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = davinci_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 635bf774015..64017558860 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -799,6 +799,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
        .timer        = &davinci_timer,
        .init_machine = evm_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = davinci_restart,
 MACHINE_END
 MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
@@ -808,5 +809,6 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
        .timer        = &davinci_timer,
        .init_machine = evm_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = davinci_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 3cfff555e8f..672d820e2aa 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -573,4 +573,5 @@ MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
        .timer          = &davinci_timer,
        .init_machine   = mityomapl138_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = da8xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index e5f231aefee..6c4a16415d4 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -278,4 +278,5 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
        .timer          = &davinci_timer,
        .init_machine = davinci_ntosd2_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = davinci_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index c6701e4a795..e7c0c7c5349 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -344,4 +344,5 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
        .timer          = &davinci_timer,
        .init_machine   = omapl138_hawk_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = da8xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 5dd4da9d230..0b136a831c5 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -157,4 +157,5 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
        .timer        = &davinci_timer,
        .init_machine = davinci_sffsdr_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = davinci_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index f69e40a29e0..5f14e30b00d 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -283,4 +283,5 @@ MACHINE_START(TNETV107X, "TNETV107X EVM")
        .timer          = &davinci_timer,
        .init_machine   = tnetv107x_evm_board_init,
        .dma_zone_size  = SZ_128M,
+        .restart        = tnetv107x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 00861139101..008772e3b84 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -31,19 +31,12 @@ static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
 static DEFINE_SPINLOCK(clockfw_lock);
-static unsigned psc_domain(struct clk *clk)
-{
-        return (clk->flags & PSC_DSP)
-                ? DAVINCI_GPSC_DSPDOMAIN
-                : DAVINCI_GPSC_ARMDOMAIN;
-}
 static void __clk_enable(struct clk *clk)
 {
        if (clk->parent)
                __clk_enable(clk->parent);
        if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
-                davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+                davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
                                true, clk->flags);
 }
@@ -53,7 +46,7 @@ static void __clk_disable(struct clk *clk)
                return;
        if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
            (clk->flags & CLK_PSC))
-                davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+                davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
                                false, clk->flags);
        if (clk->parent)
                __clk_disable(clk->parent);
@@ -237,7 +230,7 @@ static int __init clk_disable_unused(void)
                pr_debug("Clocks: disable unused %s\n", ck->name);
-                davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
+                davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
                                false, ck->flags);
        }
        spin_unlock_irq(&clockfw_lock);
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index a705f367a84..46f0f1bf1a4 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -93,6 +93,7 @@ struct clk {
        u8                      usecount;
        u8                      lpsc;
        u8                      gpsc;
+        u8                      domain;
        u32                     flags;
        struct clk              *parent;
        struct list_head        children;       /* list of children */
@@ -107,11 +108,10 @@ struct clk {
 /* Clock flags: SoC-specific flags start at BIT(16) */
 #define ALWAYS_ENABLED          BIT(1)
 #define CLK_PSC                 BIT(2)
-#define PSC_DSP                 BIT(3) /* PSC uses DSP domain, not ARM */
+#define CLK_PLL                 BIT(3) /* PLL-derived clock */
-#define CLK_PLL                 BIT(4) /* PLL-derived clock */
+#define PRE_PLL                 BIT(4) /* source is before PLL mult/div */
-#define PRE_PLL                 BIT(5) /* source is before PLL mult/div */
+#define PSC_SWRSTDISABLE        BIT(5) /* Disable state is SwRstDisable */
-#define PSC_SWRSTDISABLE        BIT(6) /* Disable state is SwRstDisable */
+#define PSC_FORCE               BIT(6) /* Force module state transtition */
-#define PSC_FORCE               BIT(7) /* Force module state transtition */
 #define CLK(dev, con, ck)       \
        {                       \
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 865ffe5899a..cb9b2e47510 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -97,9 +97,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
        local_flush_tlb_all();
        flush_cache_all();
-        if (!davinci_soc_info.reset)
-                davinci_soc_info.reset = davinci_watchdog_reset;
        /*
         * We want to check CPU revision early for cpu_is_xxxx() macros.
         * IO space mapping must be initialized before we can do that.
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index a6bf5dcaef1..deee5c2da75 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1201,7 +1201,6 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
        .gpio_irq               = IRQ_DA8XX_GPIO0,
        .serial_dev             = &da8xx_serial_device,
        .emac_pdata             = &da8xx_emac_pdata,
-        .reset_device           = &da8xx_wdt_device,
 };
 void __init da830_init(void)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b047f870227..0ed7fdb64ef 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1121,7 +1121,6 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
        .emac_pdata             = &da8xx_emac_pdata,
        .sram_dma               = DA8XX_ARM_RAM_BASE,
        .sram_len               = SZ_8K,
-        .reset_device           = &da8xx_wdt_device,
 };
 void __init da850_init(void)
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 68def718886..42dbf3dc11a 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -363,6 +363,11 @@ struct platform_device da8xx_wdt_device = {
        .resource       = da8xx_watchdog_resources,
 };
+void da8xx_restart(char mode, const char *cmd)
+{
+        davinci_watchdog_reset(&da8xx_wdt_device);
+}
 int __init da8xx_register_watchdog(void)
 {
        return platform_device_register(&da8xx_wdt_device);
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 806a2f02b98..50c0156b426 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -291,6 +291,11 @@ struct platform_device davinci_wdt_device = {
        .resource       = wdt_resources,
 };
+void davinci_restart(char mode, const char *cmd)
+{
+        davinci_watchdog_reset(&davinci_wdt_device);
+}
 static void davinci_init_wdt(void)
 {
        platform_device_register(&davinci_wdt_device);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index fe520d4167a..19667cfc5de 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -853,7 +853,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
        .serial_dev             = &dm355_serial_device,
        .sram_dma               = 0x00010000,
        .sram_len               = SZ_32K,
-        .reset_device           = &davinci_wdt_device,
 };
 void __init dm355_init_asp1(u32 evt_enable, struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 679e168dce3..f15b435cc65 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1083,7 +1083,6 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
        .emac_pdata             = &dm365_emac_pdata,
        .sram_dma               = 0x00010000,
        .sram_len               = SZ_32K,
-        .reset_device           = &davinci_wdt_device,
 };
 void __init dm365_init_asp(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 3470983aa34..43a48ee1917 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -130,7 +130,7 @@ static struct clk dsp_clk = {
        .name = "dsp",
        .parent = &pll1_sysclk1,
        .lpsc = DAVINCI_LPSC_GEM,
-        .flags = PSC_DSP,
+        .domain = DAVINCI_GPSC_DSPDOMAIN,
        .usecount = 1,                  /* REVISIT how to disable? */
 };
@@ -145,7 +145,7 @@ static struct clk vicp_clk = {
        .name = "vicp",
        .parent = &pll1_sysclk2,
        .lpsc = DAVINCI_LPSC_IMCOP,
-        .flags = PSC_DSP,
+        .domain = DAVINCI_GPSC_DSPDOMAIN,
        .usecount = 1,                  /* REVISIT how to disable? */
 };
@@ -767,7 +767,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
        .emac_pdata             = &dm644x_emac_pdata,
        .sram_dma               = 0x00008000,
        .sram_len               = SZ_16K,
-        .reset_device           = &davinci_wdt_device,
 };
 void __init dm644x_init_asp(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index af27c130595..00f774394b1 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -854,7 +854,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
        .emac_pdata             = &dm646x_emac_pdata,
        .sram_dma               = 0x10010000,
        .sram_len               = SZ_32K,
-        .reset_device           = &davinci_wdt_device,
 };
 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index a57cba21e21..5cd39a4e0c9 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -77,14 +77,13 @@ struct davinci_soc_info {
        struct emac_platform_data       *emac_pdata;
        dma_addr_t                      sram_dma;
        unsigned                        sram_len;
-        struct platform_device          *reset_device;
-        void                            (*reset)(struct platform_device *);
 };
 extern struct davinci_soc_info davinci_soc_info;
 extern void davinci_common_init(struct davinci_soc_info *soc_info);
 extern void davinci_init_ide(void);
+void davinci_restart(char mode, const char *cmd);
 /* standard place to map on-chip SRAMs; they *may* support DMA */
 #define SRAM_VIRT       0xfffe0000
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index eaca7d8b9d6..ee3461d7ec1 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -91,6 +91,7 @@ int da8xx_register_cpuidle(void);
 void __iomem * __init da8xx_get_mem_ctlr(void);
 int da850_register_pm(struct platform_device *pdev);
 int __init da850_register_sata(unsigned long refclkpn);
+void da8xx_restart(char mode, const char *cmd);
 extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 2a00fe5ac25..a8ee6c9f0bb 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -16,6 +16,7 @@
 #include <linux/i2c.h>
 #include <linux/videodev2.h>
 #include <linux/davinci_emac.h>
+#include <media/davinci/vpif_types.h>
 #define DM646X_EMAC_BASE                (0x01C80000)
 #define DM646X_EMAC_MDIO_BASE           (DM646X_EMAC_BASE + 0x4000)
@@ -34,58 +35,6 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv);
 void dm646x_video_init(void);
-enum vpif_if_type {
-        VPIF_IF_BT656,
-        VPIF_IF_BT1120,
-        VPIF_IF_RAW_BAYER
-};
-struct vpif_interface {
-        enum vpif_if_type if_type;
-        unsigned hd_pol:1;
-        unsigned vd_pol:1;
-        unsigned fid_pol:1;
-};
-struct vpif_subdev_info {
-        const char *name;
-        struct i2c_board_info board_info;
-        u32 input;
-        u32 output;
-        unsigned can_route:1;
-        struct vpif_interface vpif_if;
-};
-struct vpif_display_config {
-        int (*set_clock)(int, int);
-        struct vpif_subdev_info *subdevinfo;
-        int subdev_count;
-        const char **output;
-        int output_count;
-        const char *card_name;
-};
-struct vpif_input {
-        struct v4l2_input input;
-        const char *subdev_name;
-};
-#define VPIF_CAPTURE_MAX_CHANNELS       2
-struct vpif_capture_chan_config {
-        const struct vpif_input *inputs;
-        int input_count;
-};
-struct vpif_capture_config {
-        int (*setup_input_channel_mode)(int);
-        int (*setup_input_path)(int, const char *);
-        struct vpif_capture_chan_config chan_config[VPIF_CAPTURE_MAX_CHANNELS];
-        struct vpif_subdev_info *subdev_info;
-        int subdev_count;
-        const char *card_name;
-};
 void dm646x_setup_vpif(struct vpif_display_config *,
                       struct vpif_capture_config *);
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index d1b954955c1..b2267d1e1a7 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -21,12 +21,4 @@
 #define __mem_pci(a)            (a)
 #define __mem_isa(a)            (a)
-#ifndef __ASSEMBLER__
-#define __arch_ioremap          davinci_ioremap
-#define __arch_iounmap          davinci_iounmap
-void __iomem *davinci_ioremap(unsigned long phys, size_t size,
-                              unsigned int type);
-void davinci_iounmap(volatile void __iomem *addr);
-#endif
 #endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h
index e65629c2076..fcb7a015aba 100644
--- a/arch/arm/mach-davinci/include/mach/system.h
+++ b/arch/arm/mach-davinci/include/mach/system.h
@@ -18,10 +18,4 @@ static inline void arch_idle(void)
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        if (davinci_soc_info.reset)
-                davinci_soc_info.reset(davinci_soc_info.reset_device);
-}
 #endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 89c1fdc63c0..83e5926f3c4 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -54,6 +54,7 @@ extern struct platform_device tnetv107x_serial_device;
 extern void __init tnetv107x_init(void);
 extern void __init tnetv107x_devices_init(struct tnetv107x_device_info *);
 extern void __init tnetv107x_irq_init(void);
+void tnetv107x_restart(char mode, const char *cmd);
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/vmalloc.h b/arch/arm/mach-davinci/include/mach/vmalloc.h
deleted file mode 100644
index d49646a8e20..00000000000
--- a/arch/arm/mach-davinci/include/mach/vmalloc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * DaVinci vmalloc definitions
- *
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <mach/hardware.h>
-/* Allow vmalloc range until the IO virtual range minus a 2M "hole" */
-#define VMALLOC_END       (IO_VIRT - (2<<20))
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
deleted file mode 100644
index 8ea60a8b249..00000000000
--- a/arch/arm/mach-davinci/io.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * DaVinci I/O mapping code
- *
- * Copyright (C) 2005-2006 Texas Instruments
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/module.h>
-#include <linux/io.h>
-#include <asm/tlb.h>
-#include <asm/mach/map.h>
-#include <mach/common.h>
-/*
- * Intercept ioremap() requests for addresses in our fixed mapping regions.
- */
-void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
-{
-        struct map_desc *desc = davinci_soc_info.io_desc;
-        int desc_num = davinci_soc_info.io_desc_num;
-        int i;
-        for (i = 0; i < desc_num; i++, desc++) {
-                unsigned long iophys = __pfn_to_phys(desc->pfn);
-                unsigned long iosize = desc->length;
-                if (p >= iophys && (p + size) <= (iophys + iosize))
-                        return __io(desc->virtual + p - iophys);
-        }
-        return __arm_ioremap_caller(p, size, type,
-                                        __builtin_return_address(0));
-}
-EXPORT_SYMBOL(davinci_ioremap);
-void davinci_iounmap(volatile void __iomem *addr)
-{
-        unsigned long virt = (unsigned long)addr;
-        if (virt >= VMALLOC_START && virt < VMALLOC_END)
-                __iounmap(addr);
-}
-EXPORT_SYMBOL(davinci_iounmap);
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 409bb869c7c..dc1a209b9b6 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -730,6 +730,11 @@ static void tnetv107x_watchdog_reset(struct platform_device *pdev)
        __raw_writel(1, &regs->kick);
 }
+void tnetv107x_restart(char mode, const char *cmd)
+{
+        tnetv107x_watchdog_reset(&tnetv107x_wdt_device);
+}
 static struct davinci_soc_info tnetv107x_soc_info = {
        .io_desc                = io_desc,
        .io_desc_num            = ARRAY_SIZE(io_desc),
@@ -752,8 +757,6 @@ static struct davinci_soc_info tnetv107x_soc_info = {
        .gpio_num               = TNETV107X_N_GPIO,
        .timer_info             = &timer_info,
        .serial_dev             = &tnetv107x_serial_device,
-        .reset                  = tnetv107x_watchdog_reset,
-        .reset_device           = &tnetv107x_wdt_device,
 };
 void __init tnetv107x_init(void)
diff --git a/arch/arm/mach-dove/addr-map.c b/arch/arm/mach-dove/addr-map.c
index 00be4fc26dd..98b8c83b09a 100644
--- a/arch/arm/mach-dove/addr-map.c
+++ b/arch/arm/mach-dove/addr-map.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
+#include <plat/addr-map.h>
 #include "common.h"
 /*
@@ -34,98 +35,72 @@
 #define ATTR_PCIE_MEM           0xe8
 #define ATTR_SCRATCHPAD         0x0
-/*
- * CPU Address Decode Windows registers
- */
-#define WIN_CTRL(n)     (BRIDGE_VIRT_BASE + ((n) << 4) + 0x0)
-#define WIN_BASE(n)     (BRIDGE_VIRT_BASE + ((n) << 4) + 0x4)
-#define WIN_REMAP_LO(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0x8)
-#define WIN_REMAP_HI(n) (BRIDGE_VIRT_BASE + ((n) << 4) + 0xc)
-struct mbus_dram_target_info dove_mbus_dram_info;
 static inline void __iomem *ddr_map_sc(int i)
 {
        return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4));
 }
-static int cpu_win_can_remap(int win)
+/*
-{
+ * Description of the windows needed by the platform code
-        if (win < 4)
+ */
-                return 1;
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 8,
-        return 0;
+        .remappable_wins = 4,
-}
+        .bridge_virt_base = BRIDGE_VIRT_BASE,
+};
-static void __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        u32 ctrl;
-        base &= 0xffff0000;
-        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
-        writel(base, WIN_BASE(win));
-        writel(ctrl, WIN_CTRL(win));
-        if (cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-                writel(remap & 0xffff0000, WIN_REMAP_LO(win));
-                writel(0, WIN_REMAP_HI(win));
-        }
-}
-void __init dove_setup_cpu_mbus(void)
-{
-        int i;
-        int cs;
+static const struct __initdata orion_addr_map_info addr_map_info[] = {
        /*
-         * First, disable and clear windows.
+         * Windows for PCIe IO+MEM space.
         */
-        for (i = 0; i < 8; i++) {
+        { 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
-                writel(0, WIN_BASE(i));
+          TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE
-                writel(0, WIN_CTRL(i));
+        },
-                if (cpu_win_can_remap(i)) {
+        { 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
-                        writel(0, WIN_REMAP_LO(i));
+          TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE
-                        writel(0, WIN_REMAP_HI(i));
+        },
-                }
+        { 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
-        }
+          TARGET_PCIE0, ATTR_PCIE_MEM, -1
+        },
+        { 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
+          TARGET_PCIE1, ATTR_PCIE_MEM, -1
+        },
        /*
-         * Setup windows for PCIe IO+MEM space.
+         * Window for CESA engine.
         */
-        setup_cpu_win(0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE,
+        { 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
-                      TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE);
+          TARGET_CESA, ATTR_CESA, -1
-        setup_cpu_win(1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE,
+        },
-                      TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE);
-        setup_cpu_win(2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE,
-                      TARGET_PCIE0, ATTR_PCIE_MEM, -1);
-        setup_cpu_win(3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE,
-                      TARGET_PCIE1, ATTR_PCIE_MEM, -1);
        /*
-         * Setup window for CESA engine.
+         * Window to the BootROM for Standby and Sleep Resume
         */
-        setup_cpu_win(4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE,
+        { 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
-                      TARGET_CESA, ATTR_CESA, -1);
+          TARGET_BOOTROM, ATTR_BOOTROM, -1
+        },
        /*
-         * Setup the Window to the BootROM for Standby and Sleep Resume
+         * Window to the PMU Scratch Pad space
         */
-        setup_cpu_win(5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE,
+        { 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
-                      TARGET_BOOTROM, ATTR_BOOTROM, -1);
+          TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1
+        },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 }
+};
+void __init dove_setup_cpu_mbus(void)
+{
+        int i;
+        int cs;
        /*
-         * Setup the Window to the PMU Scratch Pad space
+         * Disable, clear and configure windows.
         */
-        setup_cpu_win(6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE,
+        orion_config_wins(&addr_map_cfg, addr_map_info);
-                      TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1);
        /*
         * Setup MBUS dram target info.
         */
-        dove_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+        orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
        for (i = 0, cs = 0; i < 2; i++) {
                u32 map = readl(ddr_map_sc(i));
@@ -136,7 +111,7 @@ void __init dove_setup_cpu_mbus(void)
                if (map & 1) {
                        struct mbus_dram_window *w;
-                        w = &dove_mbus_dram_info.cs[cs++];
+                        w = &orion_mbus_dram_info.cs[cs++];
                        w->cs_index = i;
                        w->mbus_attr = 0; /* CS address decoding done inside */
                                          /* the DDR controller, no need to  */
@@ -145,5 +120,5 @@ void __init dove_setup_cpu_mbus(void)
                        w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
                }
        }
-        dove_mbus_dram_info.num_cs = cs;
+        orion_mbus_dram_info.num_cs = cs;
 }
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index c8a406f7e94..792b4e2e24f 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -93,4 +93,5 @@ MACHINE_START(CM_A510, "Compulab CM-A510 Board")
        .init_early     = dove_init_early,
        .init_irq       = dove_init_irq,
        .timer          = &dove_timer,
+        .restart        = dove_restart,
 MACHINE_END
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index a9e0dae86a2..dd1429ae640 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -14,7 +14,6 @@
 #include <linux/platform_device.h>
 #include <linux/pci.h>
 #include <linux/clk.h>
-#include <linux/mbus.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
 #include <asm/page.h>
@@ -30,6 +29,7 @@
 #include <linux/irq.h>
 #include <plat/time.h>
 #include <plat/common.h>
+#include <plat/addr-map.h>
 #include "common.h"
 static int get_tclk(void);
@@ -71,8 +71,7 @@ void __init dove_map_io(void)
 ****************************************************************************/
 void __init dove_ehci0_init(void)
 {
-        orion_ehci_init(&dove_mbus_dram_info,
+        orion_ehci_init(DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
-                        DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
 }
 /*****************************************************************************
@@ -80,8 +79,7 @@ void __init dove_ehci0_init(void)
 ****************************************************************************/
 void __init dove_ehci1_init(void)
 {
-        orion_ehci_1_init(&dove_mbus_dram_info,
+        orion_ehci_1_init(DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
-                          DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
 }
 /*****************************************************************************
@@ -89,7 +87,7 @@ void __init dove_ehci1_init(void)
 ****************************************************************************/
 void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge00_init(eth_data, &dove_mbus_dram_info,
+        orion_ge00_init(eth_data,
                        DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
                        0, get_tclk());
 }
@@ -107,8 +105,7 @@ void __init dove_rtc_init(void)
 ****************************************************************************/
 void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        orion_sata_init(sata_data, &dove_mbus_dram_info,
+        orion_sata_init(sata_data, DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
-                        DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
 }
@@ -198,8 +195,7 @@ struct sys_timer dove_timer = {
 ****************************************************************************/
 void __init dove_xor0_init(void)
 {
-        orion_xor0_init(&dove_mbus_dram_info,
+        orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
-                        DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
                        IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
 }
@@ -292,3 +288,19 @@ void __init dove_init(void)
        dove_xor0_init();
        dove_xor1_init();
 }
+void dove_restart(char mode, const char *cmd)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+        while (1)
+                ;
+}
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 6a2046e4470..6432a3ba864 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -15,7 +15,6 @@ struct mv643xx_eth_platform_data;
 struct mv_sata_platform_data;
 extern struct sys_timer dove_timer;
-extern struct mbus_dram_target_info dove_mbus_dram_info;
 /*
 * Basic Dove init functions used early by machine-setup.
@@ -39,5 +38,6 @@ void dove_spi1_init(void);
 void dove_i2c_init(void);
 void dove_sdio0_init(void);
 void dove_sdio1_init(void);
+void dove_restart(char, const char *);
 #endif
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index 11ea34e4fc7..ea77ae430b2 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -100,4 +100,5 @@ MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
        .init_early     = dove_init_early,
        .init_irq       = dove_init_irq,
        .timer          = &dove_timer,
+        .restart        = dove_restart,
 MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index b20ec9af788..ad1165d488c 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -11,8 +11,6 @@
 #ifndef __ASM_ARCH_DOVE_H
 #define __ASM_ARCH_DOVE_H
-#include <mach/vmalloc.h>
 /*
 * Marvell Dove address maps.
 *
diff --git a/arch/arm/mach-dove/include/mach/system.h b/arch/arm/mach-dove/include/mach/system.h
index 356afda5685..3027954f616 100644
--- a/arch/arm/mach-dove/include/mach/system.h
+++ b/arch/arm/mach-dove/include/mach/system.h
@@ -9,28 +9,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <mach/bridge-regs.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        /*
-         * Enable soft reset to assert RSTOUTn.
-         */
-        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-        /*
-         * Assert soft reset.
-         */
-        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-        while (1)
-                ;
-}
 #endif
diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h
deleted file mode 100644
index a28792cf761..00000000000
--- a/arch/arm/mach-dove/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfd800000UL
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index aa2b3a09a51..52e96d397ba 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -10,7 +10,6 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
-#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/mach/pci.h>
 #include <asm/mach/arch.h>
@@ -19,6 +18,7 @@
 #include <plat/pcie.h>
 #include <mach/irqs.h>
 #include <mach/bridge-regs.h>
+#include <plat/addr-map.h>
 #include "common.h"
 struct pcie_port {
@@ -50,7 +50,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
         */
        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
-        orion_pcie_setup(pp->base, &dove_mbus_dram_info);
+        orion_pcie_setup(pp->base);
        /*
         * IORESOURCE_IO
@@ -69,7 +69,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
        pp->res[0].flags = IORESOURCE_IO;
        if (request_resource(&ioport_resource, &pp->res[0]))
                panic("Request PCIe IO resource failed\n");
-        sys->resource[0] = &pp->res[0];
+        pci_add_resource(&sys->resources, &pp->res[0]);
        /*
         * IORESOURCE_MEM
@@ -88,9 +88,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
        pp->res[1].flags = IORESOURCE_MEM;
        if (request_resource(&iomem_resource, &pp->res[1]))
                panic("Request PCIe Memory resource failed\n");
-        sys->resource[1] = &pp->res[1];
+        pci_add_resource(&sys->resources, &pp->res[1]);
-        sys->resource[2] = NULL;
        return 1;
 }
@@ -184,7 +182,8 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
        struct pci_bus *bus;
        if (nr < num_pcie_ports) {
-                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+                bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
+                                        &sys->resources);
        } else {
                bus = NULL;
                BUG();
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index d0ce8abdd4b..294aad07f7a 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -278,13 +278,19 @@ static int __init ebsa110_init(void)
 arch_initcall(ebsa110_init);
+static void ebsa110_restart(char mode, const char *cmd)
+{
+        soft_restart(0x80000000);
+}
 MACHINE_START(EBSA110, "EBSA110")
        /* Maintainer: Russell King */
        .atag_offset    = 0x400,
        .reserve_lp0    = 1,
        .reserve_lp2    = 1,
-        .soft_reboot    = 1,
+        .restart_mode   = 's',
        .map_io         = ebsa110_map_io,
        .init_irq       = ebsa110_init_irq,
        .timer          = &ebsa110_timer,
+        .restart        = ebsa110_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h
index 9a26245bf1f..2e4af65edb6 100644
--- a/arch/arm/mach-ebsa110/include/mach/system.h
+++ b/arch/arm/mach-ebsa110/include/mach/system.h
@@ -34,6 +34,4 @@ static inline void arch_idle(void)
        asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
 }
-#define arch_reset(mode, cmd)   cpu_reset(0x80000000)
 #endif
diff --git a/arch/arm/mach-ebsa110/include/mach/vmalloc.h b/arch/arm/mach-ebsa110/include/mach/vmalloc.h
deleted file mode 100644
index ea141b7a3e0..00000000000
--- a/arch/arm/mach-ebsa110/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  arch/arm/mach-ebsa110/include/mach/vmalloc.h
- *
- *  Copyright (C) 1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       0xdf000000UL
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 0713448206a..681e939407d 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -16,6 +16,7 @@
 #include <mach/hardware.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -36,6 +37,8 @@ MACHINE_START(ADSSPHERE, "ADS Sphere board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = adssphere_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 2432a6b7dca..24203f9a679 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -906,3 +906,15 @@ void __init ep93xx_init_devices(void)
        platform_device_register(&ep93xx_ohci_device);
        platform_device_register(&ep93xx_leds);
 }
+void ep93xx_restart(char mode, const char *cmd)
+{
+        /*
+         * Set then clear the SWRST bit to initiate a software reset
+         */
+        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
+        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
+        while (1)
+                ;
+}
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 70ef8c527d2..d115653edca 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -39,6 +39,7 @@
 #include <mach/ep93xx_spi.h>
 #include <mach/gpio-ep93xx.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -250,8 +251,10 @@ MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
@@ -261,8 +264,10 @@ MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
@@ -272,8 +277,10 @@ MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
@@ -283,8 +290,10 @@ MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
@@ -294,8 +303,10 @@ MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
@@ -305,8 +316,10 @@ MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
@@ -316,8 +329,10 @@ MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
@@ -327,7 +342,9 @@ MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = edb93xx_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 45ee205856f..af46970dc58 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -16,6 +16,7 @@
 #include <mach/hardware.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -36,6 +37,8 @@ MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = gesbc9312_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
index 46d4d876e6f..e82c642fa53 100644
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ b/arch/arm/mach-ep93xx/include/mach/dma.h
@@ -37,7 +37,7 @@
 */
 struct ep93xx_dma_data {
        int                             port;
-        enum dma_data_direction         direction;
+        enum dma_transfer_direction     direction;
        const char                      *name;
 };
@@ -80,14 +80,14 @@ static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)
 * channel supports given DMA direction. Only M2P channels have such
 * limitation, for M2M channels the direction is configurable.
 */
-static inline enum dma_data_direction
+static inline enum dma_transfer_direction
 ep93xx_dma_chan_direction(struct dma_chan *chan)
 {
        if (!ep93xx_dma_chan_is_m2p(chan))
                return DMA_NONE;
        /* even channels are for TX, odd for RX */
-        return (chan->chan_id % 2 == 0) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+        return (chan->chan_id % 2 == 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
 }
 #endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/entry-macro.S b/arch/arm/mach-ep93xx/include/mach/entry-macro.S
index 96b85e2c2c0..9be6edcf904 100644
--- a/arch/arm/mach-ep93xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-ep93xx/include/mach/entry-macro.S
@@ -9,51 +9,9 @@
 * the Free Software Foundation; either version 2 of the License, or (at
 * your option) any later version.
 */
-#include <mach/ep93xx-regs.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \base, =(EP93XX_AHB_VIRT_BASE)
-                orr     \base, \base, #0x000b0000
-                mov     \irqnr, #0
-                ldr     \irqstat, [\base]               @ lower 32 interrupts
-                cmp     \irqstat, #0
-                bne     1001f
-                eor     \base, \base, #0x00070000
-                ldr     \irqstat, [\base]               @ upper 32 interrupts
-                cmp     \irqstat, #0
-                beq     1002f
-                mov     \irqnr, #0x20
-1001:
-                movs    \tmp, \irqstat, lsl #16
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #16
-                movs    \tmp, \irqstat, lsl #8
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #8
-                movs    \tmp, \irqstat, lsl #4
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #4
-                movs    \tmp, \irqstat, lsl #2
-                movne   \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #2
-                movs    \tmp, \irqstat, lsl #1
-                addeq   \irqnr, \irqnr, #1
-                orrs    \base, \base, #1
-1002:
-                .endm
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 50660455b1d..d4c934931f9 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -66,4 +66,6 @@ void ep93xx_register_ac97(void);
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;
+void ep93xx_restart(char, const char *);
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
index 6d661fe9d66..b5bec7cb9b5 100644
--- a/arch/arm/mach-ep93xx/include/mach/system.h
+++ b/arch/arm/mach-ep93xx/include/mach/system.h
@@ -1,24 +1,7 @@
 /*
 * arch/arm/mach-ep93xx/include/mach/system.h
 */
-#include <mach/hardware.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        local_irq_disable();
-        /*
-         * Set then clear the SWRST bit to initiate a software reset
-         */
-        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
-        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
-        while (1)
-                ;
-}
diff --git a/arch/arm/mach-ep93xx/include/mach/vmalloc.h b/arch/arm/mach-ep93xx/include/mach/vmalloc.h
deleted file mode 100644
index 1b3f25d03d3..00000000000
--- a/arch/arm/mach-ep93xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index e72f7368876..7b98084f0c9 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -18,6 +18,7 @@
 #include <mach/hardware.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -80,8 +81,10 @@ MACHINE_START(MICRO9, "Contec Micro9-High")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
@@ -91,8 +94,10 @@ MACHINE_START(MICRO9M, "Contec Micro9-Mid")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
@@ -102,8 +107,10 @@ MACHINE_START(MICRO9L, "Contec Micro9-Lite")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
@@ -113,7 +120,9 @@ MACHINE_START(MICRO9S, "Contec Micro9-Slim")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = micro9_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 52e090dc9d2..f4e553eca21 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -25,6 +25,7 @@
 #include <mach/fb.h>
 #include <mach/gpio-ep93xx.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -80,6 +81,8 @@ MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = simone_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 8121e3aedc0..fd846331ddf 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -31,6 +31,7 @@
 #include <mach/fb.h>
 #include <mach/gpio-ep93xx.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -177,6 +178,8 @@ MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
        .atag_offset    = 0x100,
        .map_io         = ep93xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = snappercl15_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index 8b2f1435bca..79f8ecf07a1 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -23,6 +23,7 @@
 #include <mach/hardware.h>
 #include <mach/ts72xx.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/map.h>
 #include <asm/mach/arch.h>
@@ -247,6 +248,8 @@ MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
        .atag_offset    = 0x100,
        .map_io         = ts72xx_map_io,
        .init_irq       = ep93xx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = ts72xx_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index d96e4dbec6a..03dd4012043 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -361,4 +361,5 @@ MACHINE_START(VISION_EP9307, "Vision Engraving Systems EP9307")
        .init_irq       = ep93xx_init_irq,
        .timer          = &ep93xx_timer,
        .init_machine   = vision_init_machine,
+        .restart        = ep93xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 724ec0f3560..5d602f68a0e 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -17,6 +17,8 @@ choice
 config ARCH_EXYNOS4
        bool "SAMSUNG EXYNOS4"
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
        help
          Samsung EXYNOS4 SoCs based systems
@@ -57,6 +59,11 @@ config EXYNOS4_MCT
        help
          Use MCT (Multi Core Timer) as kernel timers
+config EXYNOS4_DEV_DMA
+        bool
+        help
+          Compile in amba device definitions for DMA controller
 config EXYNOS4_DEV_AHCI
        bool
        help
@@ -82,6 +89,11 @@ config EXYNOS4_DEV_DWMCI
        help
          Compile in platform device definitions for DWMCI
+config EXYNOS4_DEV_USB_OHCI
+        bool
+        help
+          Compile in platform device definition for USB OHCI
 config EXYNOS4_SETUP_I2C1
        bool
        help
@@ -143,6 +155,11 @@ config EXYNOS4_SETUP_USB_PHY
        help
          Common setup code for USB PHY controller
+config EXYNOS4_SETUP_SPI
+        bool
+        help
+          Common setup code for SPI GPIO configurations.
 # machine support
 if ARCH_EXYNOS4
@@ -177,8 +194,10 @@ config MACH_SMDKV310
        select SAMSUNG_DEV_BACKLIGHT
        select EXYNOS4_DEV_AHCI
        select SAMSUNG_DEV_KEYPAD
+        select EXYNOS4_DEV_DMA
        select EXYNOS4_DEV_PD
        select SAMSUNG_DEV_PWM
+        select EXYNOS4_DEV_USB_OHCI
        select EXYNOS4_DEV_SYSMMU
        select EXYNOS4_SETUP_FIMD0
        select EXYNOS4_SETUP_I2C1
@@ -197,6 +216,7 @@ config MACH_ARMLEX4210
        select S3C_DEV_HSMMC2
        select S3C_DEV_HSMMC3
        select EXYNOS4_DEV_AHCI
+        select EXYNOS4_DEV_DMA
        select EXYNOS4_DEV_SYSMMU
        select EXYNOS4_SETUP_SDHCI
        help
@@ -222,6 +242,7 @@ config MACH_UNIVERSAL_C210
        select S5P_DEV_MFC
        select S5P_DEV_ONENAND
        select S5P_DEV_TV
+        select EXYNOS4_DEV_DMA
        select EXYNOS4_DEV_PD
        select EXYNOS4_SETUP_FIMD0
        select EXYNOS4_SETUP_I2C1
@@ -255,6 +276,7 @@ config MACH_NURI
        select S5P_DEV_MFC
        select S5P_DEV_USB_EHCI
        select S5P_SETUP_MIPIPHY
+        select EXYNOS4_DEV_DMA
        select EXYNOS4_DEV_PD
        select EXYNOS4_SETUP_FIMC
        select EXYNOS4_SETUP_FIMD0
@@ -287,7 +309,9 @@ config MACH_ORIGEN
        select S5P_DEV_USB_EHCI
        select SAMSUNG_DEV_BACKLIGHT
        select SAMSUNG_DEV_PWM
+        select EXYNOS4_DEV_DMA
        select EXYNOS4_DEV_PD
+        select EXYNOS4_DEV_USB_OHCI
        select EXYNOS4_SETUP_FIMD0
        select EXYNOS4_SETUP_SDHCI
        select EXYNOS4_SETUP_USB_PHY
@@ -327,6 +351,20 @@ config MACH_SMDK4412
          Machine support for Samsung SMDK4412
 endif
+comment "Flattened Device Tree based board for Exynos4 based SoC"
+config MACH_EXYNOS4_DT
+        bool "Samsung Exynos4 Machine using device tree"
+        select CPU_EXYNOS4210
+        select USE_OF
+        select ARM_AMBA
+        select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+        help
+          Machine support for Samsung Exynos4 machine with device tree enabled.
+          Select this if a fdt blob is available for the Exynos4 SoC based board.
+          Note: This is under development and not all peripherals can be supported
+          with this machine file.
 if ARCH_EXYNOS4
 comment "Configuration for HSMMC 8-bit bus width"
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 59069a35e40..5fc202cdfdb 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -10,15 +10,17 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
-# Core support for EXYNOS4 system
+# Core
-obj-$(CONFIG_ARCH_EXYNOS4)      += cpu.o init.o clock.o irq-combiner.o setup-i2c0.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += common.o clock.o
-obj-$(CONFIG_ARCH_EXYNOS4)      += irq-eint.o dma.o pmu.o
 obj-$(CONFIG_CPU_EXYNOS4210)    += clock-exynos4210.o
 obj-$(CONFIG_SOC_EXYNOS4212)    += clock-exynos4212.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
+obj-$(CONFIG_ARCH_EXYNOS4)      += pmu.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_EXYNOS4_MCT)       += mct.o
@@ -37,6 +39,8 @@ obj-$(CONFIG_MACH_ORIGEN)		+= mach-origen.o
 obj-$(CONFIG_MACH_SMDK4212)             += mach-smdk4x12.o
 obj-$(CONFIG_MACH_SMDK4412)             += mach-smdk4x12.o
+obj-$(CONFIG_MACH_EXYNOS4_DT)           += mach-exynos4-dt.o
 # device support
 obj-$(CONFIG_ARCH_EXYNOS4)              += dev-audio.o
@@ -44,7 +48,10 @@ obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_PD)            += dev-pd.o
 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)        += dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)         += dev-dwmci.o
+obj-$(CONFIG_EXYNOS4_DEV_DMA)           += dma.o
+obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)      += dev-ohci.o
+obj-$(CONFIG_ARCH_EXYNOS4)              += setup-i2c0.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMC)        += setup-fimc.o
 obj-$(CONFIG_EXYNOS4_SETUP_FIMD0)       += setup-fimd0.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C1)        += setup-i2c1.o
@@ -55,6 +62,6 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C5)	+= setup-i2c5.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C6)        += setup-i2c6.o
 obj-$(CONFIG_EXYNOS4_SETUP_I2C7)        += setup-i2c7.o
 obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_EXYNOS4_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
 obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)     += setup-usb-phy.o
+obj-$(CONFIG_EXYNOS4_SETUP_SPI)         += setup-spi.o
diff --git a/arch/arm/mach-exynos/clock-exynos4210.c b/arch/arm/mach-exynos/clock-exynos4210.c
index b9d5ef670eb..a5823a7f249 100644
--- a/arch/arm/mach-exynos/clock-exynos4210.c
+++ b/arch/arm/mach-exynos/clock-exynos4210.c
@@ -23,7 +23,6 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
-#include <plat/exynos4.h>
 #include <plat/pm.h>
 #include <mach/hardware.h>
@@ -31,6 +30,8 @@
 #include <mach/regs-clock.h>
 #include <mach/exynos4-clock.h>
+#include "common.h"
 static struct sleep_save exynos4210_clock_save[] = {
        SAVE_ITEM(S5P_CLKSRC_IMAGE),
        SAVE_ITEM(S5P_CLKSRC_LCD1),
diff --git a/arch/arm/mach-exynos/clock-exynos4212.c b/arch/arm/mach-exynos/clock-exynos4212.c
index 77d5decb34f..26a668b0d10 100644
--- a/arch/arm/mach-exynos/clock-exynos4212.c
+++ b/arch/arm/mach-exynos/clock-exynos4212.c
@@ -23,7 +23,6 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
-#include <plat/exynos4.h>
 #include <plat/pm.h>
 #include <mach/hardware.h>
@@ -31,6 +30,8 @@
 #include <mach/regs-clock.h>
 #include <mach/exynos4-clock.h>
+#include "common.h"
 static struct sleep_save exynos4212_clock_save[] = {
        SAVE_ITEM(S5P_CLKSRC_IMAGE),
        SAVE_ITEM(S5P_CLKDIV_IMAGE),
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 2894f0adef5..5a8c42e9000 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -21,7 +21,6 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
-#include <plat/exynos4.h>
 #include <plat/pm.h>
 #include <mach/map.h>
@@ -29,6 +28,8 @@
 #include <mach/sysmmu.h>
 #include <mach/exynos4-clock.h>
+#include "common.h"
 static struct sleep_save exynos4_clock_save[] = {
        SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
        SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
@@ -553,16 +554,6 @@ static struct clk init_clocks_off[] = {
                .enable         = exynos4_clk_dac_ctrl,
                .ctrlbit        = (1 << 0),
        }, {
-                .name           = "dma",
-                .devname        = "dma-pl330.0",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 0),
-        }, {
-                .name           = "dma",
-                .devname        = "dma-pl330.1",
-                .enable         = exynos4_clk_ip_fsys_ctrl,
-                .ctrlbit        = (1 << 1),
-        }, {
                .name           = "adc",
                .enable         = exynos4_clk_ip_peril_ctrl,
                .ctrlbit        = (1 << 15),
@@ -778,6 +769,20 @@ static struct clk init_clocks[] = {
        }
 };
+static struct clk clk_pdma0 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.0",
+        .enable         = exynos4_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 0),
+};
+static struct clk clk_pdma1 = {
+        .name           = "dma",
+        .devname        = "dma-pl330.1",
+        .enable         = exynos4_clk_ip_fsys_ctrl,
+        .ctrlbit        = (1 << 1),
+};
 struct clk *clkset_group_list[] = {
        [0] = &clk_ext_xtal_mux,
        [1] = &clk_xusbxti,
@@ -1009,46 +1014,6 @@ static struct clksrc_clk clk_dout_mmc4 = {
 static struct clksrc_clk clksrcs[] = {
        {
-                .clk    = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.0",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.1",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.2",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.3",
-                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
-        }, {
                .clk            = {
                        .name           = "sclk_pwm",
                        .enable         = exynos4_clksrc_mask_peril0_ctrl,
@@ -1147,36 +1112,6 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
        }, {
                .clk            = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.0",
-                        .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.1",
-                        .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                        .ctrlbit        = (1 << 20),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.2",
-                        .enable         = exynos4_clksrc_mask_peril1_ctrl,
-                        .ctrlbit        = (1 << 24),
-                },
-                .sources = &clkset_group,
-                .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
                        .name           = "sclk_fimg2d",
                },
                .sources = &clkset_mout_g2d,
@@ -1192,42 +1127,6 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
        }, {
                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .parent         = &clk_dout_mmc0.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 0),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .parent         = &clk_dout_mmc1.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 4),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .parent         = &clk_dout_mmc2.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.3",
-                        .parent         = &clk_dout_mmc3.clk,
-                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
-        }, {
-                .clk            = {
                        .name           = "sclk_dwmmc",
                        .parent         = &clk_dout_mmc4.clk,
                        .enable         = exynos4_clksrc_mask_fsys_ctrl,
@@ -1237,6 +1136,134 @@ static struct clksrc_clk clksrcs[] = {
        }
 };
+static struct clksrc_clk clk_sclk_uart0 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.0",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_uart1 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.1",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_uart2 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.2",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_uart3 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "exynos4210-uart.3",
+                .enable         = exynos4_clksrc_mask_peril0_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .parent         = &clk_dout_mmc0.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 0),
+        },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .parent         = &clk_dout_mmc1.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 4),
+        },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .parent         = &clk_dout_mmc2.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+static struct clksrc_clk clk_sclk_mmc3 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.3",
+                .parent         = &clk_dout_mmc3.clk,
+                .enable         = exynos4_clksrc_mask_fsys_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk            = {
+                .name           = "sclk_spi",
+                .devname                = "s3c64xx-spi.0",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit                = (1 << 16),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk            = {
+                .name           = "sclk_spi",
+                .devname                = "s3c64xx-spi.1",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit                = (1 << 20),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_spi2 = {
+        .clk            = {
+                .name           = "sclk_spi",
+                .devname                = "s3c64xx-spi.2",
+                .enable         = exynos4_clksrc_mask_peril1_ctrl,
+                .ctrlbit                = (1 << 24),
+        },
+        .sources = &clkset_group,
+        .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+        .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
 /* Clock initialization code */
 static struct clksrc_clk *sysclks[] = {
        &clk_mout_apll,
@@ -1271,6 +1298,42 @@ static struct clksrc_clk *sysclks[] = {
        &clk_mout_mfc1,
 };
+static struct clk *clk_cdev[] = {
+        &clk_pdma0,
+        &clk_pdma1,
+};
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uart0,
+        &clk_sclk_uart1,
+        &clk_sclk_uart2,
+        &clk_sclk_uart3,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+        &clk_sclk_mmc3,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+        &clk_sclk_spi2,
+};
+static struct clk_lookup exynos4_clk_lookup[] = {
+        CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
+        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
+        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
+        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
+        CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
+        CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
+};
 static int xtal_rate;
 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
@@ -1478,11 +1541,19 @@ void __init exynos4_register_clocks(void)
        for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
                s3c_register_clksrc(sclk_tv[ptr], 1);
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+                s3c_disable_clocks(clk_cdev[ptr], 1);
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
        register_syscore_ops(&exynos4_clock_syscore_ops);
        s3c24xx_register_clock(&dummy_apb_pclk);
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
new file mode 100644
index 00000000000..c59e1887100
--- /dev/null
+++ b/arch/arm/mach-exynos/common.c
@@ -0,0 +1,699 @@
+/*
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Common Codes for EXYNOS
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/gpio.h>
+#include <linux/sched.h>
+#include <linux/serial_core.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <asm/proc-fns.h>
+#include <asm/exception.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/regs-irq.h>
+#include <mach/regs-pmu.h>
+#include <mach/regs-gpio.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/pm.h>
+#include <plat/sdhci.h>
+#include <plat/gpio-cfg.h>
+#include <plat/adc-core.h>
+#include <plat/fb-core.h>
+#include <plat/fimc-core.h>
+#include <plat/iic-core.h>
+#include <plat/tv-core.h>
+#include <plat/regs-serial.h>
+#include "common.h"
+static const char name_exynos4210[] = "EXYNOS4210";
+static const char name_exynos4212[] = "EXYNOS4212";
+static const char name_exynos4412[] = "EXYNOS4412";
+static struct cpu_table cpu_ids[] __initdata = {
+        {
+                .idcode         = EXYNOS4210_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos_init,
+                .name           = name_exynos4210,
+        }, {
+                .idcode         = EXYNOS4212_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos_init,
+                .name           = name_exynos4212,
+        }, {
+                .idcode         = EXYNOS4412_CPU_ID,
+                .idmask         = EXYNOS4_CPU_MASK,
+                .map_io         = exynos4_map_io,
+                .init_clocks    = exynos4_init_clocks,
+                .init_uarts     = exynos4_init_uarts,
+                .init           = exynos_init,
+                .name           = name_exynos4412,
+        },
+};
+/* Initial IO mappings */
+static struct map_desc exynos_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_CHIPID,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_CHIPID),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_SYS,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_TIMER,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_TIMER),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_WATCHDOG),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SROMC,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_PMU,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_PMU),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_COMBINER),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_UART),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        },
+};
+static struct map_desc exynos4_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_CMU,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
+                .length         = SZ_128K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_L2CC,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO1,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO2,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO3,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
+                .length         = SZ_256,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_DMC0,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+static struct map_desc exynos4_iodesc0[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+static struct map_desc exynos4_iodesc1[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM,
+                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+static void exynos_idle(void)
+{
+        if (!need_resched())
+                cpu_do_idle();
+        local_irq_enable();
+}
+void exynos4_restart(char mode, const char *cmd)
+{
+        __raw_writel(0x1, S5P_SWRESET);
+}
+/*
+ * exynos_map_io
+ *
+ * register the standard cpu IO areas
+ */
+void __init exynos_init_io(struct map_desc *mach_desc, int size)
+{
+        /* initialize the io descriptors we need for initialization */
+        iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
+        if (mach_desc)
+                iotable_init(mach_desc, size);
+        /* detect cpu id and rev. */
+        s5p_init_cpu(S5P_VA_CHIPID);
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+}
+void __init exynos4_map_io(void)
+{
+        iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
+        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
+                iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
+        else
+                iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
+        /* initialize device information early */
+        exynos4_default_sdhci0();
+        exynos4_default_sdhci1();
+        exynos4_default_sdhci2();
+        exynos4_default_sdhci3();
+        s3c_adc_setname("samsung-adc-v3");
+        s3c_fimc_setname(0, "exynos4-fimc");
+        s3c_fimc_setname(1, "exynos4-fimc");
+        s3c_fimc_setname(2, "exynos4-fimc");
+        s3c_fimc_setname(3, "exynos4-fimc");
+        /* The I2C bus controllers are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_i2c1_setname("s3c2440-i2c");
+        s3c_i2c2_setname("s3c2440-i2c");
+        s5p_fb_setname(0, "exynos4-fb");
+        s5p_hdmi_setname("exynos4-hdmi");
+}
+void __init exynos4_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        if (soc_is_exynos4210())
+                exynos4210_register_clocks();
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                exynos4212_register_clocks();
+        exynos4_register_clocks();
+        exynos4_setup_clocks();
+}
+#define COMBINER_ENABLE_SET     0x0
+#define COMBINER_ENABLE_CLEAR   0x4
+#define COMBINER_INT_STATUS     0xC
+static DEFINE_SPINLOCK(irq_controller_lock);
+struct combiner_chip_data {
+        unsigned int irq_offset;
+        unsigned int irq_mask;
+        void __iomem *base;
+};
+static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
+static inline void __iomem *combiner_base(struct irq_data *data)
+{
+        struct combiner_chip_data *combiner_data =
+                irq_data_get_irq_chip_data(data);
+        return combiner_data->base;
+}
+static void combiner_mask_irq(struct irq_data *data)
+{
+        u32 mask = 1 << (data->irq % 32);
+        __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
+}
+static void combiner_unmask_irq(struct irq_data *data)
+{
+        u32 mask = 1 << (data->irq % 32);
+        __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
+}
+static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+{
+        struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
+        struct irq_chip *chip = irq_get_chip(irq);
+        unsigned int cascade_irq, combiner_irq;
+        unsigned long status;
+        chained_irq_enter(chip, desc);
+        spin_lock(&irq_controller_lock);
+        status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+        spin_unlock(&irq_controller_lock);
+        status &= chip_data->irq_mask;
+        if (status == 0)
+                goto out;
+        combiner_irq = __ffs(status);
+        cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
+        if (unlikely(cascade_irq >= NR_IRQS))
+                do_bad_IRQ(cascade_irq, desc);
+        else
+                generic_handle_irq(cascade_irq);
+ out:
+        chained_irq_exit(chip, desc);
+}
+static struct irq_chip combiner_chip = {
+        .name           = "COMBINER",
+        .irq_mask       = combiner_mask_irq,
+        .irq_unmask     = combiner_unmask_irq,
+};
+static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
+{
+        if (combiner_nr >= MAX_COMBINER_NR)
+                BUG();
+        if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
+                BUG();
+        irq_set_chained_handler(irq, combiner_handle_cascade_irq);
+}
+static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
+                          unsigned int irq_start)
+{
+        unsigned int i;
+        if (combiner_nr >= MAX_COMBINER_NR)
+                BUG();
+        combiner_data[combiner_nr].base = base;
+        combiner_data[combiner_nr].irq_offset = irq_start;
+        combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
+        /* Disable all interrupts */
+        __raw_writel(combiner_data[combiner_nr].irq_mask,
+                     base + COMBINER_ENABLE_CLEAR);
+        /* Setup the Linux IRQ subsystem */
+        for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+                                + MAX_IRQ_IN_COMBINER; i++) {
+                irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
+                irq_set_chip_data(i, &combiner_data[combiner_nr]);
+                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+        }
+}
+#ifdef CONFIG_OF
+static const struct of_device_id exynos4_dt_irq_match[] = {
+        { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+        {},
+};
+#endif
+void __init exynos4_init_irq(void)
+{
+        int irq;
+        unsigned int gic_bank_offset;
+        gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
+        if (!of_have_populated_dt())
+                gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset);
+#ifdef CONFIG_OF
+        else
+                of_irq_init(exynos4_dt_irq_match);
+#endif
+        for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
+                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+                                COMBINER_IRQ(irq, 0));
+                combiner_cascade_irq(irq, IRQ_SPI(irq));
+        }
+        /*
+         * The parameters of s5p_init_irq() are for VIC init.
+         * Theses parameters should be NULL and 0 because EXYNOS4
+         * uses GIC instead of VIC.
+         */
+        s5p_init_irq(NULL, 0);
+}
+struct bus_type exynos4_subsys = {
+        .name           = "exynos4-core",
+        .dev_name       = "exynos4-core",
+};
+static struct device exynos4_dev = {
+        .bus    = &exynos4_subsys,
+};
+static int __init exynos4_core_init(void)
+{
+        return subsys_system_register(&exynos4_subsys, NULL);
+}
+core_initcall(exynos4_core_init);
+#ifdef CONFIG_CACHE_L2X0
+static int __init exynos4_l2x0_cache_init(void)
+{
+        /* TAG, Data Latency Control: 2cycle */
+        __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
+        if (soc_is_exynos4210())
+                __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+        else if (soc_is_exynos4212() || soc_is_exynos4412())
+                __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
+        /* L2X0 Prefetch Control */
+        __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
+        /* L2X0 Power Control */
+        __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
+                     S5P_VA_L2CC + L2X0_POWER_CTRL);
+        l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
+        return 0;
+}
+early_initcall(exynos4_l2x0_cache_init);
+#endif
+int __init exynos_init(void)
+{
+        printk(KERN_INFO "EXYNOS: Initializing architecture\n");
+        /* set idle function */
+        pm_idle = exynos_idle;
+        return device_register(&exynos4_dev);
+}
+/* uart registration process */
+void __init exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        struct s3c2410_uartcfg *tcfg = cfg;
+        u32 ucnt;
+        for (ucnt = 0; ucnt < no; ucnt++, tcfg++)
+                tcfg->has_fracval = 1;
+        s3c24xx_init_uartdevs("exynos4210-uart", s5p_uart_resources, cfg, no);
+}
+static DEFINE_SPINLOCK(eint_lock);
+static unsigned int eint0_15_data[16];
+static unsigned int exynos4_get_irq_nr(unsigned int number)
+{
+        u32 ret = 0;
+        switch (number) {
+        case 0 ... 3:
+                ret = (number + IRQ_EINT0);
+                break;
+        case 4 ... 7:
+                ret = (number + (IRQ_EINT4 - 4));
+                break;
+        case 8 ... 15:
+                ret = (number + (IRQ_EINT8 - 8));
+                break;
+        default:
+                printk(KERN_ERR "number available : %d\n", number);
+        }
+        return ret;
+}
+static inline void exynos4_irq_eint_mask(struct irq_data *data)
+{
+        u32 mask;
+        spin_lock(&eint_lock);
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        mask |= eint_irq_to_bit(data->irq);
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        spin_unlock(&eint_lock);
+}
+static void exynos4_irq_eint_unmask(struct irq_data *data)
+{
+        u32 mask;
+        spin_lock(&eint_lock);
+        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        mask &= ~(eint_irq_to_bit(data->irq));
+        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
+        spin_unlock(&eint_lock);
+}
+static inline void exynos4_irq_eint_ack(struct irq_data *data)
+{
+        __raw_writel(eint_irq_to_bit(data->irq),
+                     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
+}
+static void exynos4_irq_eint_maskack(struct irq_data *data)
+{
+        exynos4_irq_eint_mask(data);
+        exynos4_irq_eint_ack(data);
+}
+static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
+{
+        int offs = EINT_OFFSET(data->irq);
+        int shift;
+        u32 ctrl, mask;
+        u32 newvalue = 0;
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                newvalue = S5P_IRQ_TYPE_EDGE_RISING;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
+                break;
+        default:
+                printk(KERN_ERR "No such irq type %d", type);
+                return -EINVAL;
+        }
+        shift = (offs & 0x7) * 4;
+        mask = 0x7 << shift;
+        spin_lock(&eint_lock);
+        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
+        ctrl &= ~mask;
+        ctrl |= newvalue << shift;
+        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
+        spin_unlock(&eint_lock);
+        switch (offs) {
+        case 0 ... 7:
+                s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
+                break;
+        case 8 ... 15:
+                s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
+                break;
+        case 16 ... 23:
+                s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
+                break;
+        case 24 ... 31:
+                s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
+                break;
+        default:
+                printk(KERN_ERR "No such irq number %d", offs);
+        }
+        return 0;
+}
+static struct irq_chip exynos4_irq_eint = {
+        .name           = "exynos4-eint",
+        .irq_mask       = exynos4_irq_eint_mask,
+        .irq_unmask     = exynos4_irq_eint_unmask,
+        .irq_mask_ack   = exynos4_irq_eint_maskack,
+        .irq_ack        = exynos4_irq_eint_ack,
+        .irq_set_type   = exynos4_irq_eint_set_type,
+#ifdef CONFIG_PM
+        .irq_set_wake   = s3c_irqext_wake,
+#endif
+};
+/*
+ * exynos4_irq_demux_eint
+ *
+ * This function demuxes the IRQ from from EINTs 16 to 31.
+ * It is designed to be inlined into the specific handler
+ * s5p_irq_demux_eintX_Y.
+ *
+ * Each EINT pend/mask registers handle eight of them.
+ */
+static inline void exynos4_irq_demux_eint(unsigned int start)
+{
+        unsigned int irq;
+        u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
+        u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
+        status &= ~mask;
+        status &= 0xff;
+        while (status) {
+                irq = fls(status) - 1;
+                generic_handle_irq(irq + start);
+                status &= ~(1 << irq);
+        }
+}
+static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
+{
+        struct irq_chip *chip = irq_get_chip(irq);
+        chained_irq_enter(chip, desc);
+        exynos4_irq_demux_eint(IRQ_EINT(16));
+        exynos4_irq_demux_eint(IRQ_EINT(24));
+        chained_irq_exit(chip, desc);
+}
+static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
+{
+        u32 *irq_data = irq_get_handler_data(irq);
+        struct irq_chip *chip = irq_get_chip(irq);
+        chained_irq_enter(chip, desc);
+        chip->irq_mask(&desc->irq_data);
+        if (chip->irq_ack)
+                chip->irq_ack(&desc->irq_data);
+        generic_handle_irq(*irq_data);
+        chip->irq_unmask(&desc->irq_data);
+        chained_irq_exit(chip, desc);
+}
+int __init exynos4_init_irq_eint(void)
+{
+        int irq;
+        for (irq = 0 ; irq <= 31 ; irq++) {
+                irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+                                         handle_level_irq);
+                set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
+        }
+        irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+        for (irq = 0 ; irq <= 15 ; irq++) {
+                eint0_15_data[irq] = IRQ_EINT(irq);
+                irq_set_handler_data(exynos4_get_irq_nr(irq),
+                                     &eint0_15_data[irq]);
+                irq_set_chained_handler(exynos4_get_irq_nr(irq),
+                                        exynos4_irq_eint0_15);
+        }
+        return 0;
+}
+arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
new file mode 100644
index 00000000000..1ac49de0f39
--- /dev/null
+++ b/arch/arm/mach-exynos/common.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Common Header for EXYNOS machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
+#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
+void exynos_init_io(struct map_desc *mach_desc, int size);
+void exynos4_init_irq(void);
+void exynos4_register_clocks(void);
+void exynos4_setup_clocks(void);
+void exynos4210_register_clocks(void);
+void exynos4212_register_clocks(void);
+void exynos4_restart(char mode, const char *cmd);
+extern struct sys_timer exynos4_timer;
+#ifdef CONFIG_ARCH_EXYNOS
+extern  int exynos_init(void);
+extern void exynos4_map_io(void);
+extern void exynos4_init_clocks(int xtal);
+extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#else
+#define exynos4_init_clocks NULL
+#define exynos4_init_uarts NULL
+#define exynos4_map_io NULL
+#define exynos_init NULL
+#endif
+#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
deleted file mode 100644
index cc8d4bd6d0f..00000000000
--- a/arch/arm/mach-exynos/cpu.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/* linux/arch/arm/mach-exynos/cpu.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/sched.h>
-#include <linux/sysdev.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/proc-fns.h>
-#include <asm/hardware/cache-l2x0.h>
-#include <asm/hardware/gic.h>
-#include <plat/cpu.h>
-#include <plat/clock.h>
-#include <plat/devs.h>
-#include <plat/exynos4.h>
-#include <plat/adc-core.h>
-#include <plat/sdhci.h>
-#include <plat/fb-core.h>
-#include <plat/fimc-core.h>
-#include <plat/iic-core.h>
-#include <plat/reset.h>
-#include <plat/tv-core.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-pmu.h>
-unsigned int gic_bank_offset __read_mostly;
-extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
-                         unsigned int irq_start);
-extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
-/* Initial IO mappings */
-static struct map_desc exynos_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(EXYNOS_PA_SYSTIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_PMU,
-                .pfn            = __phys_to_pfn(EXYNOS_PA_PMU),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_COMBINER_BASE,
-                .pfn            = __phys_to_pfn(EXYNOS_PA_COMBINER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GIC_CPU,
-                .pfn            = __phys_to_pfn(EXYNOS_PA_GIC_CPU),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GIC_DIST,
-                .pfn            = __phys_to_pfn(EXYNOS_PA_GIC_DIST),
-                .length         = SZ_64K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S3C_PA_UART),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-        },
-};
-static struct map_desc exynos4_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_CMU,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
-                .length         = SZ_128K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
-                .length         = SZ_8K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_L2CC,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_L2CC),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO1,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO1),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO2,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO2),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO3,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_GPIO3),
-                .length         = SZ_256,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_DMC0,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-static struct map_desc exynos4_iodesc0[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-static struct map_desc exynos4_iodesc1[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-static void exynos_idle(void)
-{
-        if (!need_resched())
-                cpu_do_idle();
-        local_irq_enable();
-}
-static void exynos4_sw_reset(void)
-{
-        __raw_writel(0x1, S5P_SWRESET);
-}
-/*
- * exynos_map_io
- *
- * register the standard cpu IO areas
- */
-void __init exynos4_map_io(void)
-{
-        iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc));
-        iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
-        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
-                iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
-        else
-                iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
-        /* initialize device information early */
-        exynos4_default_sdhci0();
-        exynos4_default_sdhci1();
-        exynos4_default_sdhci2();
-        exynos4_default_sdhci3();
-        s3c_adc_setname("samsung-adc-v3");
-        s3c_fimc_setname(0, "exynos4-fimc");
-        s3c_fimc_setname(1, "exynos4-fimc");
-        s3c_fimc_setname(2, "exynos4-fimc");
-        s3c_fimc_setname(3, "exynos4-fimc");
-        /* The I2C bus controllers are directly compatible with s3c2440 */
-        s3c_i2c0_setname("s3c2440-i2c");
-        s3c_i2c1_setname("s3c2440-i2c");
-        s3c_i2c2_setname("s3c2440-i2c");
-        s5p_fb_setname(0, "exynos4-fb");
-        s5p_hdmi_setname("exynos4-hdmi");
-}
-void __init exynos4_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        if (soc_is_exynos4210())
-                exynos4210_register_clocks();
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                exynos4212_register_clocks();
-        exynos4_register_clocks();
-        exynos4_setup_clocks();
-}
-static void exynos4_gic_irq_fix_base(struct irq_data *d)
-{
-        struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
-        gic_data->cpu_base = S5P_VA_GIC_CPU +
-                            (gic_bank_offset * smp_processor_id());
-        gic_data->dist_base = S5P_VA_GIC_DIST +
-                            (gic_bank_offset * smp_processor_id());
-}
-void __init exynos4_init_irq(void)
-{
-        int irq;
-        gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
-        gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
-        gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
-        gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
-        gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
-        for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
-                combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
-                                COMBINER_IRQ(irq, 0));
-                combiner_cascade_irq(irq, IRQ_SPI(irq));
-        }
-        /* The parameters of s5p_init_irq() are for VIC init.
-         * Theses parameters should be NULL and 0 because EXYNOS4
-         * uses GIC instead of VIC.
-         */
-        s5p_init_irq(NULL, 0);
-}
-struct sysdev_class exynos4_sysclass = {
-        .name   = "exynos4-core",
-};
-static struct sys_device exynos4_sysdev = {
-        .cls    = &exynos4_sysclass,
-};
-static int __init exynos4_core_init(void)
-{
-        return sysdev_class_register(&exynos4_sysclass);
-}
-core_initcall(exynos4_core_init);
-#ifdef CONFIG_CACHE_L2X0
-static int __init exynos4_l2x0_cache_init(void)
-{
-        /* TAG, Data Latency Control: 2cycle */
-        __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
-        if (soc_is_exynos4210())
-                __raw_writel(0x110, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
-        else if (soc_is_exynos4212() || soc_is_exynos4412())
-                __raw_writel(0x120, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
-        /* L2X0 Prefetch Control */
-        __raw_writel(0x30000007, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
-        /* L2X0 Power Control */
-        __raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
-                     S5P_VA_L2CC + L2X0_POWER_CTRL);
-        l2x0_init(S5P_VA_L2CC, 0x7C470001, 0xC200ffff);
-        return 0;
-}
-early_initcall(exynos4_l2x0_cache_init);
-#endif
-int __init exynos_init(void)
-{
-        printk(KERN_INFO "EXYNOS: Initializing architecture\n");
-        /* set idle function */
-        pm_idle = exynos_idle;
-        /* set sw_reset function */
-        if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
-                s5p_reset_hook = exynos4_sw_reset;
-        return sysdev_register(&exynos4_sysdev);
-}
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
new file mode 100644
index 00000000000..b8e75300c77
--- /dev/null
+++ b/arch/arm/mach-exynos/dev-ohci.c
@@ -0,0 +1,52 @@
+/* linux/arch/arm/mach-exynos/dev-ohci.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - OHCI support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <mach/ohci.h>
+#include <plat/devs.h>
+#include <plat/usb-phy.h>
+static struct resource exynos4_ohci_resource[] = {
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_OHCI, SZ_256),
+        [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
+};
+static u64 exynos4_ohci_dma_mask = DMA_BIT_MASK(32);
+struct platform_device exynos4_device_ohci = {
+        .name           = "exynos-ohci",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(exynos4_ohci_resource),
+        .resource       = exynos4_ohci_resource,
+        .dev            = {
+                .dma_mask               = &exynos4_ohci_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        }
+};
+void __init exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd)
+{
+        struct exynos4_ohci_platdata *npd;
+        npd = s3c_set_platdata(pd, sizeof(struct exynos4_ohci_platdata),
+                        &exynos4_device_ohci);
+        if (!npd->phy_init)
+                npd->phy_init = s5p_usb_phy_init;
+        if (!npd->phy_exit)
+                npd->phy_exit = s5p_usb_phy_exit;
+}
diff --git a/arch/arm/mach-exynos/dma.c b/arch/arm/mach-exynos/dma.c
index 9667c61e64f..b10fcd270f0 100644
--- a/arch/arm/mach-exynos/dma.c
+++ b/arch/arm/mach-exynos/dma.c
@@ -24,6 +24,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl330.h>
+#include <linux/of.h>
 #include <asm/irq.h>
 #include <plat/devs.h>
@@ -35,95 +36,42 @@
 static u64 dma_dmamask = DMA_BIT_MASK(32);
-struct dma_pl330_peri pdma0_peri[28] = {
+u8 pdma0_peri[] = {
-        {
+        DMACH_PCM0_RX,
-                .peri_id = (u8)DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_PCM2_RX,
-        }, {
+        DMACH_PCM2_TX,
-                .peri_id = (u8)DMACH_PCM0_TX,
+        DMACH_MSM_REQ0,
-                .rqtype = MEMTODEV,
+        DMACH_MSM_REQ2,
-        }, {
+        DMACH_SPI0_RX,
-                .peri_id = (u8)DMACH_PCM2_RX,
+        DMACH_SPI0_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_SPI2_RX,
-        }, {
+        DMACH_SPI2_TX,
-                .peri_id = (u8)DMACH_PCM2_TX,
+        DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
+        DMACH_I2S0_RX,
-        }, {
+        DMACH_I2S0_TX,
-                .peri_id = (u8)DMACH_MSM_REQ0,
+        DMACH_I2S2_RX,
-        }, {
+        DMACH_I2S2_TX,
-                .peri_id = (u8)DMACH_MSM_REQ2,
+        DMACH_UART0_RX,
-        }, {
+        DMACH_UART0_TX,
-                .peri_id = (u8)DMACH_SPI0_RX,
+        DMACH_UART2_RX,
-                .rqtype = DEVTOMEM,
+        DMACH_UART2_TX,
-        }, {
+        DMACH_UART4_RX,
-                .peri_id = (u8)DMACH_SPI0_TX,
+        DMACH_UART4_TX,
-                .rqtype = MEMTODEV,
+        DMACH_SLIMBUS0_RX,
-        }, {
+        DMACH_SLIMBUS0_TX,
-                .peri_id = (u8)DMACH_SPI2_RX,
+        DMACH_SLIMBUS2_RX,
-                .rqtype = DEVTOMEM,
+        DMACH_SLIMBUS2_TX,
-        }, {
+        DMACH_SLIMBUS4_RX,
-                .peri_id = (u8)DMACH_SPI2_TX,
+        DMACH_SLIMBUS4_TX,
-                .rqtype = MEMTODEV,
+        DMACH_AC97_MICIN,
-        }, {
+        DMACH_AC97_PCMIN,
-                .peri_id = (u8)DMACH_I2S0S_TX,
+        DMACH_AC97_PCMOUT,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART4_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART4_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS4_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS4_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_AC97_MICIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMOUT,
-                .rqtype = MEMTODEV,
-        },
 };
 struct dma_pl330_platdata exynos4_pdma0_pdata = {
        .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-        .peri = pdma0_peri,
+        .peri_id = pdma0_peri,
 };
 struct amba_device exynos4_device_pdma0 = {
@@ -142,86 +90,37 @@ struct amba_device exynos4_device_pdma0 = {
        .periphid = 0x00041330,
 };
-struct dma_pl330_peri pdma1_peri[25] = {
+u8 pdma1_peri[] = {
-        {
+        DMACH_PCM0_RX,
-                .peri_id = (u8)DMACH_PCM0_RX,
+        DMACH_PCM0_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_PCM1_RX,
-        }, {
+        DMACH_PCM1_TX,
-                .peri_id = (u8)DMACH_PCM0_TX,
+        DMACH_MSM_REQ1,
-                .rqtype = MEMTODEV,
+        DMACH_MSM_REQ3,
-        }, {
+        DMACH_SPI1_RX,
-                .peri_id = (u8)DMACH_PCM1_RX,
+        DMACH_SPI1_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_I2S0S_TX,
-        }, {
+        DMACH_I2S0_RX,
-                .peri_id = (u8)DMACH_PCM1_TX,
+        DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
+        DMACH_I2S1_RX,
-        }, {
+        DMACH_I2S1_TX,
-                .peri_id = (u8)DMACH_MSM_REQ1,
+        DMACH_UART0_RX,
-        }, {
+        DMACH_UART0_TX,
-                .peri_id = (u8)DMACH_MSM_REQ3,
+        DMACH_UART1_RX,
-        }, {
+        DMACH_UART1_TX,
-                .peri_id = (u8)DMACH_SPI1_RX,
+        DMACH_UART3_RX,
-                .rqtype = DEVTOMEM,
+        DMACH_UART3_TX,
-        }, {
+        DMACH_SLIMBUS1_RX,
-                .peri_id = (u8)DMACH_SPI1_TX,
+        DMACH_SLIMBUS1_TX,
-                .rqtype = MEMTODEV,
+        DMACH_SLIMBUS3_RX,
-        }, {
+        DMACH_SLIMBUS3_TX,
-                .peri_id = (u8)DMACH_I2S0S_TX,
+        DMACH_SLIMBUS5_RX,
-                .rqtype = MEMTODEV,
+        DMACH_SLIMBUS5_TX,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_UART3_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS3_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS5_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SLIMBUS5_TX,
-                .rqtype = MEMTODEV,
-        },
 };
 struct dma_pl330_platdata exynos4_pdma1_pdata = {
        .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-        .peri = pdma1_peri,
+        .peri_id = pdma1_peri,
 };
 struct amba_device exynos4_device_pdma1 = {
@@ -242,7 +141,15 @@ struct amba_device exynos4_device_pdma1 = {
 static int __init exynos4_dma_init(void)
 {
+        if (of_have_populated_dt())
+                return 0;
+        dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
        amba_device_register(&exynos4_device_pdma0, &iomem_resource);
+        dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
        amba_device_register(&exynos4_device_pdma1, &iomem_resource);
        return 0;
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index 3cdeb364754..5364d4bfa8b 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -36,6 +36,8 @@ pen:	ldr	r7, [r6]
         * should now contain the SVC stack for this core
         */
        b       secondary_startup
+ENDPROC(exynos4_secondary_startup)
+        .align 2
 1:      .long   .
        .long   pen_release
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
new file mode 100644
index 00000000000..3df27f2d503
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -0,0 +1,34 @@
+/* linux/arch/arm/mach-exynos/include/mach/cpufreq.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * EXYNOS - CPUFreq support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+enum cpufreq_level_index {
+        L0, L1, L2, L3, L4,
+        L5, L6, L7, L8, L9,
+        L10, L11, L12, L13, L14,
+        L15, L16, L17, L18, L19,
+        L20,
+};
+struct exynos_dvfs_info {
+        unsigned long   mpll_freq_khz;
+        unsigned int    pll_safe_idx;
+        unsigned int    pm_lock_idx;
+        unsigned int    max_support_idx;
+        unsigned int    min_support_idx;
+        struct clk      *cpu_clk;
+        unsigned int    *volt_table;
+        struct cpufreq_frequency_table  *freq_table;
+        void (*set_freq)(unsigned int, unsigned int);
+        bool (*need_apll_change)(unsigned int, unsigned int);
+};
+extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/arch/arm/mach-exynos/include/mach/entry-macro.S b/arch/arm/mach-exynos/include/mach/entry-macro.S
index f5e9fd8e37b..3ba4f547534 100644
--- a/arch/arm/mach-exynos/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos/include/mach/entry-macro.S
@@ -9,83 +9,8 @@
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/hardware/gic.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                mov     \tmp, #0
-                mrc     p15, 0, \base, c0, c0, 5
-                and     \base, \base, #3
-                cmp     \base, #0
-                beq     1f
-                ldr     \tmp, =gic_bank_offset
-                ldr     \tmp, [\tmp]
-                cmp     \base, #1
-                beq     1f
-                cmp     \base, #2
-                addeq   \tmp, \tmp, \tmp
-                addne   \tmp, \tmp, \tmp, LSL #1
-1:              ldr     \base, =gic_cpu_base_addr
-                ldr     \base, [\base]
-                add     \base, \base, \tmp
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                /*
-                 * The interrupt numbering scheme is defined in the
-                 * interrupt controller spec.  To wit:
-                 *
-                 * Interrupts 0-15 are IPI
-                 * 16-28 are reserved
-                 * 29-31 are local.  We allow 30 to be used for the watchdog.
-                 * 32-1020 are global
-                 * 1021-1022 are reserved
-                 * 1023 is "spurious" (no interrupt)
-                 *
-                 * For now, we ignore all local interrupts so only return an interrupt if it's
-                 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-                 *
-                 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-                 * valid range for an IRQ (30-1020 inclusive).
-                 */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-                ldr     \tmp, =1021
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #15
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-                addne   \irqnr, \irqnr, #32
-                .endm
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt on the
-                 * controller, since this requires the original irqstat value which
-                 * we won't easily be able to recreate later.
-                 */
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                cmpcs   \irqnr, \irqnr
-                .endm
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index dfd4b7eecb9..f77bce04789 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -17,13 +17,13 @@
 /* PPI: Private Peripheral Interrupt */
-#define IRQ_PPI(x)              S5P_IRQ(x+16)
+#define IRQ_PPI(x)              (x+16)
 #define IRQ_MCT_LOCALTIMER      IRQ_PPI(12)
 /* SPI: Shared Peripheral Interrupt */
-#define IRQ_SPI(x)              S5P_IRQ(x+32)
+#define IRQ_SPI(x)              (x+32)
 #define IRQ_EINT0               IRQ_SPI(16)
 #define IRQ_EINT1               IRQ_SPI(17)
@@ -72,6 +72,9 @@
 #define IRQ_IIC5                IRQ_SPI(63)
 #define IRQ_IIC6                IRQ_SPI(64)
 #define IRQ_IIC7                IRQ_SPI(65)
+#define IRQ_SPI0                IRQ_SPI(66)
+#define IRQ_SPI1                IRQ_SPI(67)
+#define IRQ_SPI2                IRQ_SPI(68)
 #define IRQ_USB_HOST            IRQ_SPI(70)
 #define IRQ_USB_HSOTG           IRQ_SPI(71)
@@ -163,7 +166,9 @@
 #define IRQ_GPIO2_NR_GROUPS     9
 #define IRQ_GPIO_END            (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
+#define IRQ_TIMER_BASE          (IRQ_GPIO_END + 64)
 /* Set the default NR_IRQS */
-#define NR_IRQS                 (IRQ_GPIO_END + 64)
+#define NR_IRQS                 (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 058541d45af..c754a22a2bb 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -87,6 +87,10 @@
 #define EXYNOS4_PA_SYSMMU_TV            0x12E20000
 #define EXYNOS4_PA_SYSMMU_MFC_L         0x13620000
 #define EXYNOS4_PA_SYSMMU_MFC_R         0x13630000
+#define EXYNOS4_PA_SPI0                 0x13920000
+#define EXYNOS4_PA_SPI1                 0x13930000
+#define EXYNOS4_PA_SPI2                 0x13940000
 #define EXYNOS4_PA_GPIO1                0x11400000
 #define EXYNOS4_PA_GPIO2                0x11000000
@@ -107,6 +111,7 @@
 #define EXYNOS4_PA_SROMC                0x12570000
 #define EXYNOS4_PA_EHCI                 0x12580000
+#define EXYNOS4_PA_OHCI                 0x12590000
 #define EXYNOS4_PA_HSPHY                0x125B0000
 #define EXYNOS4_PA_MFC                  0x13400000
@@ -148,8 +153,10 @@
 #define S3C_PA_RTC                      EXYNOS4_PA_RTC
 #define S3C_PA_WDT                      EXYNOS4_PA_WATCHDOG
 #define S3C_PA_UART                     EXYNOS4_PA_UART
+#define S3C_PA_SPI0                     EXYNOS4_PA_SPI0
+#define S3C_PA_SPI1                     EXYNOS4_PA_SPI1
+#define S3C_PA_SPI2                     EXYNOS4_PA_SPI2
-#define S5P_PA_CHIPID                   EXYNOS4_PA_CHIPID
 #define S5P_PA_EHCI                     EXYNOS4_PA_EHCI
 #define S5P_PA_FIMC0                    EXYNOS4_PA_FIMC0
 #define S5P_PA_FIMC1                    EXYNOS4_PA_FIMC1
@@ -166,26 +173,17 @@
 #define S5P_PA_ONENAND_DMA              EXYNOS4_PA_ONENAND_DMA
 #define S5P_PA_SDO                      EXYNOS4_PA_SDO
 #define S5P_PA_SDRAM                    EXYNOS4_PA_SDRAM
-#define S5P_PA_SROMC                    EXYNOS4_PA_SROMC
-#define S5P_PA_SYSCON                   EXYNOS4_PA_SYSCON
-#define S5P_PA_TIMER                    EXYNOS4_PA_TIMER
 #define S5P_PA_VP                       EXYNOS4_PA_VP
 #define SAMSUNG_PA_ADC                  EXYNOS4_PA_ADC
 #define SAMSUNG_PA_ADC1                 EXYNOS4_PA_ADC1
 #define SAMSUNG_PA_KEYPAD               EXYNOS4_PA_KEYPAD
-#define EXYNOS_PA_COMBINER              EXYNOS4_PA_COMBINER
-#define EXYNOS_PA_GIC_CPU               EXYNOS4_PA_GIC_CPU
-#define EXYNOS_PA_GIC_DIST              EXYNOS4_PA_GIC_DIST
-#define EXYNOS_PA_PMU                   EXYNOS4_PA_PMU
-#define EXYNOS_PA_SYSTIMER              EXYNOS4_PA_SYSTIMER
 /* Compatibility UART */
 #define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART(x)                  (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET))
 #define S5P_PA_UART0                    S5P_PA_UART(0)
 #define S5P_PA_UART1                    S5P_PA_UART(1)
 #define S5P_PA_UART2                    S5P_PA_UART(2)
diff --git a/arch/arm/mach-exynos/include/mach/ohci.h b/arch/arm/mach-exynos/include/mach/ohci.h
new file mode 100644
index 00000000000..c256c595be5
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/ohci.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __MACH_EXYNOS_OHCI_H
+#define __MACH_EXYNOS_OHCI_H
+struct exynos4_ohci_platdata {
+        int (*phy_init)(struct platform_device *pdev, int type);
+        int (*phy_exit)(struct platform_device *pdev, int type);
+};
+extern void exynos4_ohci_set_platdata(struct exynos4_ohci_platdata *pd);
+#endif /* __MACH_EXYNOS_OHCI_H */
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
new file mode 100644
index 00000000000..576efdf6d09
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/spi-clocks.h
@@ -0,0 +1,16 @@
+/* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h
+ *
+ * Copyright (C) 2011 Samsung Electronics Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_SPI_CLKS_H
+#define __ASM_ARCH_SPI_CLKS_H __FILE__
+/* Must source from SCLK_SPI */
+#define EXYNOS4_SPI_SRCCLK_SCLK         0
+#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
index 5e3220c18fc..0063a6de3dc 100644
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -13,8 +13,6 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
-#include <plat/system-reset.h>
 static void arch_idle(void)
 {
        /* nothing here yet */
diff --git a/arch/arm/mach-exynos/include/mach/vmalloc.h b/arch/arm/mach-exynos/include/mach/vmalloc.h
deleted file mode 100644
index 284330e571d..00000000000
--- a/arch/arm/mach-exynos/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * EXYNOS4 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H __FILE__
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-exynos/init.c b/arch/arm/mach-exynos/init.c
deleted file mode 100644
index a8a83e3881a..00000000000
--- a/arch/arm/mach-exynos/init.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/arch/arm/mach-exynos4/init.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/serial_core.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/regs-serial.h>
-static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk1",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-};
-/* uart registration process */
-void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-                if (!tcfg->clocks) {
-                        tcfg->has_fracval = 1;
-                        tcfg->clocks = exynos4_serial_clocks;
-                        tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
-                }
-                tcfg->flags |= NO_NEED_CHECK_CLKSRC;
-        }
-        s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
-}
diff --git a/arch/arm/mach-exynos/irq-combiner.c b/arch/arm/mach-exynos/irq-combiner.c
deleted file mode 100644
index 5a2758ab055..00000000000
--- a/arch/arm/mach-exynos/irq-combiner.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/* linux/arch/arm/mach-exynos4/irq-combiner.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Based on arch/arm/common/gic.c
- *
- * IRQ COMBINER support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/io.h>
-#include <asm/mach/irq.h>
-#define COMBINER_ENABLE_SET     0x0
-#define COMBINER_ENABLE_CLEAR   0x4
-#define COMBINER_INT_STATUS     0xC
-static DEFINE_SPINLOCK(irq_controller_lock);
-struct combiner_chip_data {
-        unsigned int irq_offset;
-        unsigned int irq_mask;
-        void __iomem *base;
-};
-static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
-static inline void __iomem *combiner_base(struct irq_data *data)
-{
-        struct combiner_chip_data *combiner_data =
-                irq_data_get_irq_chip_data(data);
-        return combiner_data->base;
-}
-static void combiner_mask_irq(struct irq_data *data)
-{
-        u32 mask = 1 << (data->irq % 32);
-        __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
-}
-static void combiner_unmask_irq(struct irq_data *data)
-{
-        u32 mask = 1 << (data->irq % 32);
-        __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
-}
-static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
-{
-        struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
-        struct irq_chip *chip = irq_get_chip(irq);
-        unsigned int cascade_irq, combiner_irq;
-        unsigned long status;
-        chained_irq_enter(chip, desc);
-        spin_lock(&irq_controller_lock);
-        status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
-        spin_unlock(&irq_controller_lock);
-        status &= chip_data->irq_mask;
-        if (status == 0)
-                goto out;
-        combiner_irq = __ffs(status);
-        cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
-        if (unlikely(cascade_irq >= NR_IRQS))
-                do_bad_IRQ(cascade_irq, desc);
-        else
-                generic_handle_irq(cascade_irq);
- out:
-        chained_irq_exit(chip, desc);
-}
-static struct irq_chip combiner_chip = {
-        .name           = "COMBINER",
-        .irq_mask       = combiner_mask_irq,
-        .irq_unmask     = combiner_unmask_irq,
-};
-void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
-{
-        if (combiner_nr >= MAX_COMBINER_NR)
-                BUG();
-        if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
-                BUG();
-        irq_set_chained_handler(irq, combiner_handle_cascade_irq);
-}
-void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
-                          unsigned int irq_start)
-{
-        unsigned int i;
-        if (combiner_nr >= MAX_COMBINER_NR)
-                BUG();
-        combiner_data[combiner_nr].base = base;
-        combiner_data[combiner_nr].irq_offset = irq_start;
-        combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
-        /* Disable all interrupts */
-        __raw_writel(combiner_data[combiner_nr].irq_mask,
-                     base + COMBINER_ENABLE_CLEAR);
-        /* Setup the Linux IRQ subsystem */
-        for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
-                                + MAX_IRQ_IN_COMBINER; i++) {
-                irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
-                irq_set_chip_data(i, &combiner_data[combiner_nr]);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-        }
-}
diff --git a/arch/arm/mach-exynos/irq-eint.c b/arch/arm/mach-exynos/irq-eint.c
deleted file mode 100644
index badb8c66fc9..00000000000
--- a/arch/arm/mach-exynos/irq-eint.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/* linux/arch/arm/mach-exynos4/irq-eint.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - IRQ EINT support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/sysdev.h>
-#include <linux/gpio.h>
-#include <plat/pm.h>
-#include <plat/cpu.h>
-#include <plat/gpio-cfg.h>
-#include <mach/regs-gpio.h>
-#include <asm/mach/irq.h>
-static DEFINE_SPINLOCK(eint_lock);
-static unsigned int eint0_15_data[16];
-static unsigned int exynos4_get_irq_nr(unsigned int number)
-{
-        u32 ret = 0;
-        switch (number) {
-        case 0 ... 3:
-                ret = (number + IRQ_EINT0);
-                break;
-        case 4 ... 7:
-                ret = (number + (IRQ_EINT4 - 4));
-                break;
-        case 8 ... 15:
-                ret = (number + (IRQ_EINT8 - 8));
-                break;
-        default:
-                printk(KERN_ERR "number available : %d\n", number);
-        }
-        return ret;
-}
-static inline void exynos4_irq_eint_mask(struct irq_data *data)
-{
-        u32 mask;
-        spin_lock(&eint_lock);
-        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-        mask |= eint_irq_to_bit(data->irq);
-        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-        spin_unlock(&eint_lock);
-}
-static void exynos4_irq_eint_unmask(struct irq_data *data)
-{
-        u32 mask;
-        spin_lock(&eint_lock);
-        mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-        mask &= ~(eint_irq_to_bit(data->irq));
-        __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
-        spin_unlock(&eint_lock);
-}
-static inline void exynos4_irq_eint_ack(struct irq_data *data)
-{
-        __raw_writel(eint_irq_to_bit(data->irq),
-                     S5P_EINT_PEND(EINT_REG_NR(data->irq)));
-}
-static void exynos4_irq_eint_maskack(struct irq_data *data)
-{
-        exynos4_irq_eint_mask(data);
-        exynos4_irq_eint_ack(data);
-}
-static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
-{
-        int offs = EINT_OFFSET(data->irq);
-        int shift;
-        u32 ctrl, mask;
-        u32 newvalue = 0;
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                newvalue = S5P_IRQ_TYPE_EDGE_RISING;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                newvalue = S5P_IRQ_TYPE_EDGE_FALLING;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                newvalue = S5P_IRQ_TYPE_EDGE_BOTH;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                newvalue = S5P_IRQ_TYPE_LEVEL_LOW;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                newvalue = S5P_IRQ_TYPE_LEVEL_HIGH;
-                break;
-        default:
-                printk(KERN_ERR "No such irq type %d", type);
-                return -EINVAL;
-        }
-        shift = (offs & 0x7) * 4;
-        mask = 0x7 << shift;
-        spin_lock(&eint_lock);
-        ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
-        ctrl &= ~mask;
-        ctrl |= newvalue << shift;
-        __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
-        spin_unlock(&eint_lock);
-        switch (offs) {
-        case 0 ... 7:
-                s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
-                break;
-        case 8 ... 15:
-                s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE);
-                break;
-        case 16 ... 23:
-                s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE);
-                break;
-        case 24 ... 31:
-                s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE);
-                break;
-        default:
-                printk(KERN_ERR "No such irq number %d", offs);
-        }
-        return 0;
-}
-static struct irq_chip exynos4_irq_eint = {
-        .name           = "exynos4-eint",
-        .irq_mask       = exynos4_irq_eint_mask,
-        .irq_unmask     = exynos4_irq_eint_unmask,
-        .irq_mask_ack   = exynos4_irq_eint_maskack,
-        .irq_ack        = exynos4_irq_eint_ack,
-        .irq_set_type   = exynos4_irq_eint_set_type,
-#ifdef CONFIG_PM
-        .irq_set_wake   = s3c_irqext_wake,
-#endif
-};
-/* exynos4_irq_demux_eint
- *
- * This function demuxes the IRQ from from EINTs 16 to 31.
- * It is designed to be inlined into the specific handler
- * s5p_irq_demux_eintX_Y.
- *
- * Each EINT pend/mask registers handle eight of them.
- */
-static inline void exynos4_irq_demux_eint(unsigned int start)
-{
-        unsigned int irq;
-        u32 status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start)));
-        u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start)));
-        status &= ~mask;
-        status &= 0xff;
-        while (status) {
-                irq = fls(status) - 1;
-                generic_handle_irq(irq + start);
-                status &= ~(1 << irq);
-        }
-}
-static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = irq_get_chip(irq);
-        chained_irq_enter(chip, desc);
-        exynos4_irq_demux_eint(IRQ_EINT(16));
-        exynos4_irq_demux_eint(IRQ_EINT(24));
-        chained_irq_exit(chip, desc);
-}
-static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
-{
-        u32 *irq_data = irq_get_handler_data(irq);
-        struct irq_chip *chip = irq_get_chip(irq);
-        chained_irq_enter(chip, desc);
-        chip->irq_mask(&desc->irq_data);
-        if (chip->irq_ack)
-                chip->irq_ack(&desc->irq_data);
-        generic_handle_irq(*irq_data);
-        chip->irq_unmask(&desc->irq_data);
-        chained_irq_exit(chip, desc);
-}
-int __init exynos4_init_irq_eint(void)
-{
-        int irq;
-        for (irq = 0 ; irq <= 31 ; irq++) {
-                irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
-                                         handle_level_irq);
-                set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
-        }
-        irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
-        for (irq = 0 ; irq <= 15 ; irq++) {
-                eint0_15_data[irq] = IRQ_EINT(irq);
-                irq_set_handler_data(exynos4_get_irq_nr(irq),
-                                     &eint0_15_data[irq]);
-                irq_set_chained_handler(exynos4_get_irq_nr(irq),
-                                        exynos4_irq_eint0_15);
-        }
-        return 0;
-}
-arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-exynos/mach-armlex4210.c b/arch/arm/mach-exynos/mach-armlex4210.c
index f0ca6c157d2..d726fcd3acf 100644
--- a/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/arch/arm/mach-exynos/mach-armlex4210.c
@@ -16,11 +16,11 @@
 #include <linux/smsc911x.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/exynos4.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
@@ -28,6 +28,8 @@
 #include <mach/map.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -187,7 +189,7 @@ static void __init armlex4210_smsc911x_init(void)
 static void __init armlex4210_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        exynos_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(armlex4210_uartcfgs,
                           ARRAY_SIZE(armlex4210_uartcfgs));
@@ -210,6 +212,8 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = armlex4210_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = armlex4210_machine_init,
        .timer          = &exynos4_timer,
+        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
new file mode 100644
index 00000000000..85fa02767d6
--- /dev/null
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -0,0 +1,85 @@
+/*
+ * Samsung's Exynos4210 flattened device tree enabled machine
+ *
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2010-2011 Linaro Ltd.
+ *              www.linaro.org
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/of_platform.h>
+#include <linux/serial_core.h>
+#include <asm/mach/arch.h>
+#include <mach/map.h>
+#include <plat/cpu.h>
+#include <plat/regs-serial.h>
+#include <plat/exynos4.h>
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the Exynos4 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0,
+                                "exynos4210-uart.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1,
+                                "exynos4210-uart.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2,
+                                "exynos4210-uart.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3,
+                                "exynos4210-uart.3", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
+                                "exynos4-sdhci.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
+                                "exynos4-sdhci.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
+                                "exynos4-sdhci.2", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
+                                "exynos4-sdhci.3", NULL),
+        OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
+                                "s3c2440-i2c.0", NULL),
+        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
+        OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+        {},
+};
+static void __init exynos4210_dt_map_io(void)
+{
+        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s3c24xx_init_clocks(24000000);
+}
+static void __init exynos4210_dt_machine_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                                exynos4210_auxdata_lookup, NULL);
+}
+static char const *exynos4210_dt_compat[] __initdata = {
+        "samsung,exynos4210",
+        NULL
+};
+DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
+        /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
+        .init_irq       = exynos4_init_irq,
+        .map_io         = exynos4210_dt_map_io,
+        .init_machine   = exynos4210_dt_machine_init,
+        .timer          = &exynos4_timer,
+        .dt_compat      = exynos4210_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 236bbe18716..b895ec03110 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -32,12 +32,12 @@
 #include <media/v4l2-mediabus.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/adc.h>
 #include <plat/regs-fb-v4.h>
 #include <plat/regs-serial.h>
-#include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
@@ -54,6 +54,8 @@
 #include <mach/map.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define NURI_UCON_DEFAULT       (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -247,13 +249,8 @@ static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
 static int nuri_bl_init(struct device *dev)
 {
-        int ret, gpio = EXYNOS4_GPE2(3);
+        return gpio_request_one(EXYNOS4_GPE2(3), GPIOF_OUT_INIT_LOW,
+                                "LCD_LD0_EN");
-        ret = gpio_request(gpio, "LCD_LDO_EN");
-        if (!ret)
-                gpio_direction_output(gpio, 0);
-        return ret;
 }
 static int nuri_bl_notify(struct device *dev, int brightness)
@@ -1283,7 +1280,7 @@ static struct platform_device *nuri_devices[] __initdata = {
 static void __init nuri_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        exynos_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
 }
@@ -1333,7 +1330,9 @@ MACHINE_START(NURI, "NURI")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = nuri_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = nuri_machine_init,
        .timer          = &exynos4_timer,
        .reserve        = &nuri_reserve,
+        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index f80b563f2be..0679b8ad2d1 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -22,13 +22,13 @@
 #include <linux/lcd.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <video/platform_lcd.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-fb-v4.h>
-#include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/sdhci.h>
@@ -41,8 +41,11 @@
 #include <plat/fb.h>
 #include <plat/mfc.h>
+#include <mach/ohci.h>
 #include <mach/map.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define ORIGEN_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -483,6 +486,16 @@ static void __init origen_ehci_init(void)
        s5p_ehci_set_platdata(pdata);
 }
+/* USB OHCI */
+static struct exynos4_ohci_platdata origen_ohci_pdata;
+static void __init origen_ohci_init(void)
+{
+        struct exynos4_ohci_platdata *pdata = &origen_ohci_pdata;
+        exynos4_ohci_set_platdata(pdata);
+}
 static struct gpio_keys_button origen_gpio_keys_table[] = {
        {
                .code                   = KEY_MENU,
@@ -584,7 +597,8 @@ static struct s3c_fb_pd_win origen_fb_win0 = {
 static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
        .win[0]         = &origen_fb_win0,
        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
-        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
+                                VIDCON1_INV_VCLK,
        .setup_gpio     = exynos4_fimd0_gpio_setup_24bpp,
 };
@@ -606,6 +620,7 @@ static struct platform_device *origen_devices[] __initdata = {
        &s5p_device_mfc_l,
        &s5p_device_mfc_r,
        &s5p_device_mixer,
+        &exynos4_device_ohci,
        &exynos4_device_pd[PD_LCD0],
        &exynos4_device_pd[PD_TV],
        &exynos4_device_pd[PD_G3D],
@@ -638,7 +653,7 @@ static void s5p_tv_setup(void)
 static void __init origen_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        exynos_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
 }
@@ -670,6 +685,7 @@ static void __init origen_machine_init(void)
        s3c_sdhci0_set_platdata(&origen_hsmmc0_pdata);
        origen_ehci_init();
+        origen_ohci_init();
        clk_xusbxti.rate = 24000000;
        s5p_tv_setup();
@@ -694,7 +710,9 @@ MACHINE_START(ORIGEN, "ORIGEN")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = origen_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = origen_machine_init,
        .timer          = &exynos4_timer,
        .reserve        = &origen_reserve,
+        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdk4x12.c b/arch/arm/mach-exynos/mach-smdk4x12.c
index fcf2e0e23d5..d00e4f016a6 100644
--- a/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -21,13 +21,13 @@
 #include <linux/serial_core.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/backlight.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
-#include <plat/exynos4.h>
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 #include <plat/keypad.h>
@@ -36,6 +36,8 @@
 #include <mach/map.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDK4X12_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -249,7 +251,7 @@ static void __init smdk4x12_map_io(void)
 {
        clk_xusbxti.rate = 24000000;
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        exynos_init_io(NULL, 0);
        s3c24xx_init_clocks(clk_xusbxti.rate);
        s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
 }
@@ -287,8 +289,10 @@ MACHINE_START(SMDK4212, "SMDK4212")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdk4x12_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = smdk4x12_machine_init,
        .timer          = &exynos4_timer,
+        .restart        = exynos4_restart,
 MACHINE_END
 MACHINE_START(SMDK4412, "SMDK4412")
@@ -297,6 +301,8 @@ MACHINE_START(SMDK4412, "SMDK4412")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdk4x12_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = smdk4x12_machine_init,
        .timer          = &exynos4_timer,
+        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index cec2afabe7b..b2c5557f50e 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -21,13 +21,13 @@
 #include <linux/pwm_backlight.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <video/platform_lcd.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
 #include <plat/regs-fb-v4.h>
-#include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
@@ -42,6 +42,9 @@
 #include <plat/clock.h>
 #include <mach/map.h>
+#include <mach/ohci.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKV310_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
@@ -129,9 +132,7 @@ static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
                gpio_free(EXYNOS4_GPD0(1));
 #endif
                /* fire nRESET on power up */
-                gpio_request(EXYNOS4_GPX0(6), "GPX0");
+                gpio_request_one(EXYNOS4_GPX0(6), GPIOF_OUT_INIT_HIGH, "GPX0");
-                gpio_direction_output(EXYNOS4_GPX0(6), 1);
                mdelay(100);
                gpio_set_value(EXYNOS4_GPX0(6), 0);
@@ -245,6 +246,16 @@ static void __init smdkv310_ehci_init(void)
        s5p_ehci_set_platdata(pdata);
 }
+/* USB OHCI */
+static struct exynos4_ohci_platdata smdkv310_ohci_pdata;
+static void __init smdkv310_ohci_init(void)
+{
+        struct exynos4_ohci_platdata *pdata = &smdkv310_ohci_pdata;
+        exynos4_ohci_set_platdata(pdata);
+}
 static struct platform_device *smdkv310_devices[] __initdata = {
        &s3c_device_hsmmc0,
        &s3c_device_hsmmc1,
@@ -261,6 +272,7 @@ static struct platform_device *smdkv310_devices[] __initdata = {
        &s5p_device_fimc3,
        &exynos4_device_ac97,
        &exynos4_device_i2s0,
+        &exynos4_device_ohci,
        &samsung_device_keypad,
        &s5p_device_mfc,
        &s5p_device_mfc_l,
@@ -332,7 +344,7 @@ static void s5p_tv_setup(void)
 static void __init smdkv310_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        exynos_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
 }
@@ -363,6 +375,7 @@ static void __init smdkv310_machine_init(void)
        s5p_fimd0_set_platdata(&smdkv310_lcd0_pdata);
        smdkv310_ehci_init();
+        smdkv310_ohci_init();
        clk_xusbxti.rate = 24000000;
        platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
@@ -375,9 +388,11 @@ MACHINE_START(SMDKV310, "SMDKV310")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdkv310_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = smdkv310_machine_init,
        .timer          = &exynos4_timer,
        .reserve        = &smdkv310_reserve,
+        .restart        = exynos4_restart,
 MACHINE_END
 MACHINE_START(SMDKC210, "SMDKC210")
@@ -385,6 +400,8 @@ MACHINE_START(SMDKC210, "SMDKC210")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = smdkv310_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = smdkv310_machine_init,
        .timer          = &exynos4_timer,
+        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index a2a177ff4b4..37ac93e8d6d 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -24,10 +24,10 @@
 #include <linux/i2c/atmel_mxt_ts.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <plat/regs-serial.h>
-#include <plat/exynos4.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/iic.h>
@@ -47,6 +47,8 @@
 #include <media/s5p_fimc.h>
 #include <media/m5mols.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define UNIVERSAL_UCON_DEFAULT  (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -608,8 +610,7 @@ static void __init universal_tsp_init(void)
        /* TSP_LDO_ON: XMDMADDR_11 */
        gpio = EXYNOS4_GPE2(3);
-        gpio_request(gpio, "TSP_LDO_ON");
+        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
-        gpio_direction_output(gpio, 1);
        gpio_export(gpio, 0);
        /* TSP_INT: XMDMADDR_7 */
@@ -669,8 +670,7 @@ static void __init universal_touchkey_init(void)
        i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
        gpio = EXYNOS4_GPE3(3);                 /* XMDMDATA_3 */
-        gpio_request(gpio, "3_TOUCH_EN");
+        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "3_TOUCH_EN");
-        gpio_direction_output(gpio, 1);
 }
 static struct s3c2410_platform_i2c universal_i2c0_platdata __initdata = {
@@ -992,7 +992,7 @@ static struct platform_device *universal_devices[] __initdata = {
 static void __init universal_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        exynos_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
 }
@@ -1000,9 +1000,7 @@ static void __init universal_map_io(void)
 void s5p_tv_setup(void)
 {
        /* direct HPD to HDMI chip */
-        gpio_request(EXYNOS4_GPX3(7), "hpd-plug");
+        gpio_request_one(EXYNOS4_GPX3(7), GPIOF_IN, "hpd-plug");
-        gpio_direction_input(EXYNOS4_GPX3(7));
        s3c_gpio_cfgpin(EXYNOS4_GPX3(7), S3C_GPIO_SFN(0x3));
        s3c_gpio_setpull(EXYNOS4_GPX3(7), S3C_GPIO_PULL_NONE);
@@ -1058,7 +1056,9 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
        .atag_offset    = 0x100,
        .init_irq       = exynos4_init_irq,
        .map_io         = universal_map_io,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = universal_machine_init,
        .timer          = &exynos4_timer,
        .reserve        = &universal_reserve,
+        .restart        = exynos4_restart,
 MACHINE_END
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 69ffb2fb387..683aec786b7 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -24,7 +24,6 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
-#include <asm/unified.h>
 #include <mach/hardware.h>
 #include <mach/regs-clock.h>
@@ -32,7 +31,6 @@
 #include <plat/cpu.h>
-extern unsigned int gic_bank_offset;
 extern void exynos4_secondary_startup(void);
 #define CPU1_BOOT_REG           (samsung_rev() == EXYNOS4210_REV_1_1 ? \
@@ -65,31 +63,6 @@ static void __iomem *scu_base_addr(void)
 static DEFINE_SPINLOCK(boot_lock);
-static void __cpuinit exynos4_gic_secondary_init(void)
-{
-        void __iomem *dist_base = S5P_VA_GIC_DIST +
-                                (gic_bank_offset * smp_processor_id());
-        void __iomem *cpu_base = S5P_VA_GIC_CPU +
-                                (gic_bank_offset * smp_processor_id());
-        int i;
-        /*
-         * Deal with the banked PPI and SGI interrupts - disable all
-         * PPI interrupts, ensure all SGI interrupts are enabled.
-         */
-        __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
-        __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
-        /*
-         * Set priority on PPI and SGI interrupts
-         */
-        for (i = 0; i < 32; i += 4)
-                __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
-        __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
-        __raw_writel(1, cpu_base + GIC_CPU_CTRL);
-}
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
        /*
@@ -97,7 +70,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
         */
-        exynos4_gic_secondary_init();
+        gic_secondary_init(0);
        /*
         * let the primary processor know we're out of the
@@ -163,7 +136,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
        while (time_before(jiffies, timeout)) {
                smp_rmb();
-                __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+                __raw_writel(virt_to_phys(exynos4_secondary_startup),
                        CPU1_BOOT_REG);
                gic_raise_softirq(cpumask_of(cpu), 1);
@@ -218,6 +191,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
         * until it receives a soft interrupt, and then the
         * secondary CPU branches to this address.
         */
-        __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+        __raw_writel(virt_to_phys(exynos4_secondary_startup),
                        CPU1_BOOT_REG);
 }
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 509a435afd4..a4f61a43c7b 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -23,6 +23,7 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/smp_scu.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
@@ -205,7 +206,7 @@ static void exynos4_pm_prepare(void)
 }
-static int exynos4_pm_add(struct sys_device *sysdev)
+static int exynos4_pm_add(struct device *dev)
 {
        pm_cpu_prep = exynos4_pm_prepare;
        pm_cpu_sleep = exynos4_cpu_suspend;
@@ -213,27 +214,6 @@ static int exynos4_pm_add(struct sys_device *sysdev)
        return 0;
 }
-/* This function copy from linux/arch/arm/kernel/smp_scu.c */
-void exynos4_scu_enable(void __iomem *scu_base)
-{
-        u32 scu_ctrl;
-        scu_ctrl = __raw_readl(scu_base);
-        /* already enabled? */
-        if (scu_ctrl & 1)
-                return;
-        scu_ctrl |= 1;
-        __raw_writel(scu_ctrl, scu_base);
-        /*
-         * Ensure that the data accessed by CPU0 before the SCU was
-         * initialised is visible to the other CPUs.
-         */
-        flush_cache_all();
-}
 static unsigned long pll_base_rate;
 static void exynos4_restore_pll(void)
@@ -301,8 +281,10 @@ static void exynos4_restore_pll(void)
        } while (epll_wait || vpll_wait);
 }
-static struct sysdev_driver exynos4_pm_driver = {
+static struct subsys_interface exynos4_pm_interface = {
-        .add            = exynos4_pm_add,
+        .name           = "exynos4_pm",
+        .subsys         = &exynos4_subsys,
+        .add_dev        = exynos4_pm_add,
 };
 static __init int exynos4_pm_drvinit(void)
@@ -325,7 +307,7 @@ static __init int exynos4_pm_drvinit(void)
                clk_put(pll_base);
        }
-        return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
+        return subsys_interface_register(&exynos4_pm_interface);
 }
 arch_initcall(exynos4_pm_drvinit);
@@ -402,7 +384,7 @@ static void exynos4_pm_resume(void)
        exynos4_restore_pll();
-        exynos4_scu_enable(S5P_VA_SCU);
+        scu_enable(S5P_VA_SCU);
 #ifdef CONFIG_CACHE_L2X0
        s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
diff --git a/arch/arm/mach-exynos/setup-sdhci.c b/arch/arm/mach-exynos/setup-sdhci.c
deleted file mode 100644
index 92937b41090..00000000000
--- a/arch/arm/mach-exynos/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-exynos4/setup-sdhci.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/types.h>
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-char *exynos4_hsmmc_clksrcs[4] = {
-        [0] = NULL,
-        [1] = NULL,
-        [2] = "sclk_mmc",       /* mmc_bus */
-        [3] = NULL,
-};
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
new file mode 100644
index 00000000000..833ff40ee0e
--- /dev/null
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -0,0 +1,72 @@
+/* linux/arch/arm/mach-exynos4/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *             http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+        .high_speed     = 1,
+        .clk_from_cmu   = true,
+        .tx_st_done     = 25,
+};
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+        .high_speed     = 1,
+        .clk_from_cmu   = true,
+        .tx_st_done     = 25,
+};
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+#ifdef CONFIG_S3C64XX_DEV_SPI2
+struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+        .high_speed     = 1,
+        .clk_from_cmu   = true,
+        .tx_st_done     = 25,
+};
+int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
+        s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
+                              S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 39aca045f66..41743d21e8c 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -19,6 +19,13 @@
 #include <plat/cpu.h>
 #include <plat/usb-phy.h>
+static atomic_t host_usage;
+static int exynos4_usb_host_phy_is_on(void)
+{
+        return (readl(EXYNOS4_PHYPWR) & PHY1_STD_ANALOG_POWERDOWN) ? 0 : 1;
+}
 static int exynos4_usb_phy1_init(struct platform_device *pdev)
 {
        struct clk *otg_clk;
@@ -27,6 +34,8 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
        u32 rstcon;
        int err;
+        atomic_inc(&host_usage);
        otg_clk = clk_get(&pdev->dev, "otg");
        if (IS_ERR(otg_clk)) {
                dev_err(&pdev->dev, "Failed to get otg clock\n");
@@ -39,6 +48,9 @@ static int exynos4_usb_phy1_init(struct platform_device *pdev)
                return err;
        }
+        if (exynos4_usb_host_phy_is_on())
+                return 0;
        writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
                        S5P_USBHOST_PHY_CONTROL);
@@ -95,6 +107,9 @@ static int exynos4_usb_phy1_exit(struct platform_device *pdev)
        struct clk *otg_clk;
        int err;
+        if (atomic_dec_return(&host_usage) > 0)
+                return 0;
        otg_clk = clk_get(&pdev->dev, "otg");
        if (IS_ERR(otg_clk)) {
                dev_err(&pdev->dev, "Failed to get otg clock\n");
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index d5f17854092..25b453601ac 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -86,9 +86,10 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
 MACHINE_START(CATS, "Chalice-CATS")
        /* Maintainer: Philip Blundell */
        .atag_offset    = 0x100,
-        .soft_reboot    = 1,
+        .restart_mode   = 's',
        .fixup          = fixup_cats,
        .map_io         = footbridge_map_io,
        .init_irq       = footbridge_init_irq,
        .timer          = &isa_timer,
+        .restart        = footbridge_restart,
 MACHINE_END
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 38a44f9b9da..41978ee4f9d 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -199,6 +199,33 @@ void __init footbridge_map_io(void)
                iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
 }
+void footbridge_restart(char mode, const char *cmd)
+{
+        if (mode == 's') {
+                /* Jump into the ROM */
+                soft_restart(0x41000000);
+        } else {
+                /*
+                 * Force the watchdog to do a CPU reset.
+                 *
+                 * After making sure that the watchdog is disabled
+                 * (so we can change the timer registers) we first
+                 * enable the timer to autoreload itself.  Next, the
+                 * timer interval is set really short and any
+                 * current interrupt request is cleared (so we can
+                 * see an edge transition).  Finally, TIMER4 is
+                 * enabled as the watchdog.
+                 */
+                *CSR_SA110_CNTL &= ~(1 << 13);
+                *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
+                                   TIMER_CNTL_AUTORELOAD |
+                                   TIMER_CNTL_DIV16;
+                *CSR_TIMER4_LOAD = 0x2;
+                *CSR_TIMER4_CLR  = 0;
+                *CSR_SA110_CNTL |= (1 << 13);
+        }
+}
 #ifdef CONFIG_FOOTBRIDGE_ADDIN
 static inline unsigned long fb_bus_sdram_offset(void)
diff --git a/arch/arm/mach-footbridge/common.h b/arch/arm/mach-footbridge/common.h
index b05e662d21a..c9767b892cb 100644
--- a/arch/arm/mach-footbridge/common.h
+++ b/arch/arm/mach-footbridge/common.h
@@ -8,3 +8,4 @@ extern void footbridge_map_io(void);
 extern void footbridge_init_irq(void);
 extern void isa_init_irq(unsigned int irq);
+extern void footbridge_restart(char, const char *);
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 18c32a5541d..f685650c25d 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -275,9 +275,9 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
        allocate_resource(&iomem_resource, &res[0], 0x40000000,
                          0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
-        sys->resource[0] = &ioport_resource;
+        pci_add_resource(&sys->resources, &ioport_resource);
-        sys->resource[1] = &res[0];
+        pci_add_resource(&sys->resources, &res[0]);
-        sys->resource[2] = &res[1];
+        pci_add_resource(&sys->resources, &res[1]);
        sys->mem_offset  = DC21285_PCI_MEM;
        return 1;
@@ -285,7 +285,7 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
 struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys)
 {
-        return pci_scan_bus(0, &dc21285_ops, sys);
+        return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources);
 }
 #define dc21285_request_irq(_a, _b, _c, _d, _e) \
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 012210cf7d1..27716a7e5fc 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -21,5 +21,6 @@ MACHINE_START(EBSA285, "EBSA285")
        .map_io         = footbridge_map_io,
        .init_irq       = footbridge_init_irq,
        .timer          = &footbridge_timer,
+        .restart        = footbridge_restart,
 MACHINE_END
diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h
index 0b293156620..a174a5841bc 100644
--- a/arch/arm/mach-footbridge/include/mach/system.h
+++ b/arch/arm/mach-footbridge/include/mach/system.h
@@ -7,63 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <linux/io.h>
-#include <asm/hardware/dec21285.h>
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach-types.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        if (mode == 's') {
-                /*
-                 * Jump into the ROM
-                 */
-                cpu_reset(0x41000000);
-        } else {
-                if (machine_is_netwinder()) {
-                        /* open up the SuperIO chip
-                         */
-                        outb(0x87, 0x370);
-                        outb(0x87, 0x370);
-                        /* aux function group 1 (logical device 7)
-                         */
-                        outb(0x07, 0x370);
-                        outb(0x07, 0x371);
-                        /* set GP16 for WD-TIMER output
-                         */
-                        outb(0xe6, 0x370);
-                        outb(0x00, 0x371);
-                        /* set a RED LED and toggle WD_TIMER for rebooting
-                         */
-                        outb(0xc4, 0x338);
-                } else {
-                        /* 
-                         * Force the watchdog to do a CPU reset.
-                         *
-                         * After making sure that the watchdog is disabled
-                         * (so we can change the timer registers) we first
-                         * enable the timer to autoreload itself.  Next, the
-                         * timer interval is set really short and any
-                         * current interrupt request is cleared (so we can
-                         * see an edge transition).  Finally, TIMER4 is
-                         * enabled as the watchdog.
-                         */
-                        *CSR_SA110_CNTL &= ~(1 << 13);
-                        *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
-                                           TIMER_CNTL_AUTORELOAD |
-                                           TIMER_CNTL_DIV16;
-                        *CSR_TIMER4_LOAD = 0x2;
-                        *CSR_TIMER4_CLR  = 0;
-                        *CSR_SA110_CNTL |= (1 << 13);
-                }
-        }
-}
diff --git a/arch/arm/mach-footbridge/include/mach/vmalloc.h b/arch/arm/mach-footbridge/include/mach/vmalloc.h
deleted file mode 100644
index 40ba78e5782..00000000000
--- a/arch/arm/mach-footbridge/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  arch/arm/mach-footbridge/include/mach/vmalloc.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       0xf0000000UL
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 0d3846f3b60..80a1c5cc907 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -645,6 +645,32 @@ fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi)
 #endif
 }
+static void netwinder_restart(char mode, const char *cmd)
+{
+        if (mode == 's') {
+                /* Jump into the ROM */
+                soft_restart(0x41000000);
+        } else {
+                local_irq_disable();
+                local_fiq_disable();
+                /* open up the SuperIO chip */
+                outb(0x87, 0x370);
+                outb(0x87, 0x370);
+                /* aux function group 1 (logical device 7) */
+                outb(0x07, 0x370);
+                outb(0x07, 0x371);
+                /* set GP16 for WD-TIMER output */
+                outb(0xe6, 0x370);
+                outb(0x00, 0x371);
+                /* set a RED LED and toggle WD_TIMER for rebooting */
+                outb(0xc4, 0x338);
+        }
+}
 MACHINE_START(NETWINDER, "Rebel-NetWinder")
        /* Maintainer: Russell King/Rebel.com */
        .atag_offset    = 0x100,
@@ -656,4 +682,5 @@ MACHINE_START(NETWINDER, "Rebel-NetWinder")
        .map_io         = footbridge_map_io,
        .init_irq       = footbridge_init_irq,
        .timer          = &isa_timer,
+        .restart        = netwinder_restart,
 MACHINE_END
diff --git a/arch/arm/mach-footbridge/personal.c b/arch/arm/mach-footbridge/personal.c
index f41dba39b32..e1e9990fa95 100644
--- a/arch/arm/mach-footbridge/personal.c
+++ b/arch/arm/mach-footbridge/personal.c
@@ -19,5 +19,6 @@ MACHINE_START(PERSONAL_SERVER, "Compaq-PersonalServer")
        .map_io         = footbridge_map_io,
        .init_irq       = footbridge_init_irq,
        .timer          = &footbridge_timer,
+        .restart        = footbridge_restart,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/include/mach/vmalloc.h b/arch/arm/mach-gemini/include/mach/vmalloc.h
deleted file mode 100644
index 45371eb86fc..00000000000
--- a/arch/arm/mach-gemini/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#define VMALLOC_END     0xf0000000UL
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index 51d4e44ab97..f8a2f6bb548 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -242,3 +242,8 @@ void __init h720x_map_io(void)
 {
        iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
 }
+void h720x_restart(char mode, const char *cmd)
+{
+        CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
+}
diff --git a/arch/arm/mach-h720x/common.h b/arch/arm/mach-h720x/common.h
index 7dd5fa604ef..2489537d33d 100644
--- a/arch/arm/mach-h720x/common.h
+++ b/arch/arm/mach-h720x/common.h
@@ -16,6 +16,7 @@
 extern unsigned long h720x_gettimeoffset(void);
 extern void __init h720x_init_irq(void);
 extern void __init h720x_map_io(void);
+extern void h720x_restart(char, const char *);
 #ifdef CONFIG_ARCH_H7202
 extern struct sys_timer h7202_timer;
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
index 9886f19805f..5fdb20c855e 100644
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ b/arch/arm/mach-h720x/h7201-eval.c
@@ -34,4 +34,5 @@ MACHINE_START(H7201, "Hynix GMS30C7201")
        .init_irq       = h720x_init_irq,
        .timer          = &h7201_timer,
        .dma_zone_size  = SZ_256M,
+        .restart        = h720x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
index 284a134819e..169673036c5 100644
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ b/arch/arm/mach-h720x/h7202-eval.c
@@ -77,4 +77,5 @@ MACHINE_START(H7202, "Hynix HMS30C7202")
        .timer          = &h7202_timer,
        .init_machine   = init_eval_h7202,
        .dma_zone_size  = SZ_256M,
+        .restart        = h720x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-h720x/include/mach/system.h b/arch/arm/mach-h720x/include/mach/system.h
index a708d24ee46..16ac46e239a 100644
--- a/arch/arm/mach-h720x/include/mach/system.h
+++ b/arch/arm/mach-h720x/include/mach/system.h
@@ -24,10 +24,4 @@ static void arch_idle(void)
        nop();
 }
-static __inline__ void arch_reset(char mode, const char *cmd)
-{
-        CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
-}
 #endif
diff --git a/arch/arm/mach-h720x/include/mach/vmalloc.h b/arch/arm/mach-h720x/include/mach/vmalloc.h
deleted file mode 100644
index 8520b4a4d4e..00000000000
--- a/arch/arm/mach-h720x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/vmalloc.h
- */
-#ifndef __ARCH_ARM_VMALLOC_H
-#define __ARCH_ARM_VMALLOC_H
-#define VMALLOC_END       0xd0000000UL
-#endif
diff --git a/arch/arm/mach-highbank/core.h b/arch/arm/mach-highbank/core.h
index 7e33fc94cd1..d8e2d0be64a 100644
--- a/arch/arm/mach-highbank/core.h
+++ b/arch/arm/mach-highbank/core.h
@@ -1,5 +1,6 @@
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
 extern void highbank_clocks_init(void);
+extern void highbank_restart(char, const char *);
 extern void __iomem *scu_base_addr;
 #ifdef CONFIG_DEBUG_HIGHBANK_UART
 extern void highbank_lluart_map_io(void);
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 88660d500f5..7afbe1e55be 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -25,7 +25,6 @@
 #include <linux/smp.h>
 #include <asm/cacheflush.h>
-#include <asm/unified.h>
 #include <asm/smp_scu.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
@@ -76,7 +75,7 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
 #ifdef CONFIG_SMP
        cpu = cpu_logical_map(cpu);
 #endif
-        writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));
+        writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
        __cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
        outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
                          HB_JUMP_TABLE_PHYS(cpu) + 15);
@@ -144,6 +143,8 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
        .map_io         = highbank_map_io,
        .init_irq       = highbank_init_irq,
        .timer          = &highbank_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = highbank_init,
        .dt_compat      = highbank_match,
+        .restart        = highbank_restart,
 MACHINE_END
diff --git a/arch/arm/mach-highbank/include/mach/entry-macro.S b/arch/arm/mach-highbank/include/mach/entry-macro.S
index 73c11297509..a14f9e62ca9 100644
--- a/arch/arm/mach-highbank/include/mach/entry-macro.S
+++ b/arch/arm/mach-highbank/include/mach/entry-macro.S
@@ -1,5 +1,3 @@
-#include <asm/hardware/entry-macro-gic.S>
        .macro  disable_fiq
        .endm
diff --git a/arch/arm/mach-highbank/include/mach/system.h b/arch/arm/mach-highbank/include/mach/system.h
index 7e8192296ca..b1d8b5fbe37 100644
--- a/arch/arm/mach-highbank/include/mach/system.h
+++ b/arch/arm/mach-highbank/include/mach/system.h
@@ -21,6 +21,4 @@ static inline void arch_idle(void)
        cpu_do_idle();
 }
-extern void arch_reset(char mode, const char *cmd);
 #endif
diff --git a/arch/arm/mach-highbank/include/mach/vmalloc.h b/arch/arm/mach-highbank/include/mach/vmalloc.h
deleted file mode 100644
index 1969e954277..00000000000
--- a/arch/arm/mach-highbank/include/mach/vmalloc.h
+++ /dev/null
@@ -1 +0,0 @@
-#define VMALLOC_END             0xFEE00000UL
diff --git a/arch/arm/mach-highbank/system.c b/arch/arm/mach-highbank/system.c
index 53f0c4c5ef1..82c27230d4a 100644
--- a/arch/arm/mach-highbank/system.c
+++ b/arch/arm/mach-highbank/system.c
@@ -20,7 +20,7 @@
 #include "core.h"
 #include "sysregs.h"
-void arch_reset(char mode, const char *cmd)
+void highbank_restart(char mode, const char *cmd)
 {
        if (mode == 'h')
                hignbank_set_pwr_hard_reset();
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0e6f1af260b..0e6de366c64 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -98,6 +98,7 @@ config MACH_SCB9328
 config MACH_APF9328
        bool "APF9328"
        select SOC_IMX1
+        select IMX_HAVE_PLATFORM_IMX_I2C
        select IMX_HAVE_PLATFORM_IMX_UART
        help
          Say Yes here if you are using the Armadeus APF9328 development board
@@ -595,13 +596,14 @@ comment "i.MX6 family:"
 config SOC_IMX6Q
        bool "i.MX6 Quad support"
+        select ARM_CPU_SUSPEND if PM
        select ARM_GIC
-        select CACHE_L2X0
        select CPU_V7
        select HAVE_ARM_SCU
        select HAVE_IMX_GPC
        select HAVE_IMX_MMDC
        select HAVE_IMX_SRC
+        select HAVE_SMP
        select USE_OF
        help
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d97f409ce98..f5920c24f7d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -70,4 +70,8 @@ AFLAGS_head-v7.o :=-Wa,-march=armv7-a
 obj-$(CONFIG_SMP) += platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o pm-imx6q.o
+obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
+ifeq ($(CONFIG_PM),y)
+obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
+endif
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index cfede5768aa..5f4d06af491 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -25,3 +25,6 @@ initrd_phys-$(CONFIG_SOC_IMX35)	:= 0x80800000
 zreladdr-$(CONFIG_SOC_IMX6Q)    += 0x10008000
 params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
 initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
+dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
+                           imx6q-sabrelite.dtb
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 039a7abb165..9273c2a24b5 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -1931,14 +1931,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
                val |= 0x1 << BP_CLPCR_LPM;
                val &= ~BM_CLPCR_VSTBY;
                val &= ~BM_CLPCR_SBYOS;
-                val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
                break;
        case STOP_POWER_OFF:
                val |= 0x2 << BP_CLPCR_LPM;
                val |= 0x3 << BP_CLPCR_STBY_COUNT;
                val |= BM_CLPCR_VSTBY;
                val |= BM_CLPCR_SBYOS;
-                val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
                break;
        default:
                return -EINVAL;
diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S
index 6229efbc70c..7e49deb128a 100644
--- a/arch/arm/mach-imx/head-v7.S
+++ b/arch/arm/mach-imx/head-v7.S
@@ -16,7 +16,6 @@
 #include <asm/hardware/cache-l2x0.h>
        .section ".text.head", "ax"
-        __CPUINIT
 /*
 * The secondary kernel init calls v7_flush_dcache_all before it enables
@@ -33,6 +32,7 @@
 */
 ENTRY(v7_invalidate_l1)
        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
        mcr     p15, 2, r0, c0, c0, 0
        mrc     p15, 1, r0, c0, c0, 0
@@ -71,6 +71,7 @@ ENTRY(v7_secondary_startup)
 ENDPROC(v7_secondary_startup)
 #endif
+#ifdef CONFIG_PM
 /*
 * The following code is located into the .data section.  This is to
 * allow phys_l2x0_saved_regs to be accessed with a relative load
@@ -79,6 +80,7 @@ ENDPROC(v7_secondary_startup)
        .data
        .align
+#ifdef CONFIG_CACHE_L2X0
        .macro  pl310_resume
        ldr     r2, phys_l2x0_saved_regs
        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
@@ -88,12 +90,17 @@ ENDPROC(v7_secondary_startup)
        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
        .endm
+        .globl  phys_l2x0_saved_regs
+phys_l2x0_saved_regs:
+        .long   0
+#else
+        .macro  pl310_resume
+        .endm
+#endif
 ENTRY(v7_cpu_resume)
        bl      v7_invalidate_l1
        pl310_resume
        b       cpu_resume
 ENDPROC(v7_cpu_resume)
+#endif
-        .globl  phys_l2x0_saved_regs
-phys_l2x0_saved_regs:
-        .long   0
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 1e486e67dab..f4a63ee9e21 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/dm9000.h>
+#include <linux/i2c.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -41,6 +42,9 @@ static const int apf9328_pins[] __initconst = {
        PB29_PF_UART2_RTS,
        PB30_PF_UART2_TXD,
        PB31_PF_UART2_RXD,
+        /* I2C */
+        PA15_PF_I2C_SDA,
+        PA16_PF_I2C_SCL,
 };
 /*
@@ -103,6 +107,10 @@ static const struct imxuart_platform_data uart1_pdata __initconst = {
        .flags = IMXUART_HAVE_RTSCTS,
 };
+static const struct imxi2c_platform_data apf9328_i2c_data __initconst = {
+        .bitrate = 100000,
+};
 static struct platform_device *devices[] __initdata = {
        &apf9328_flash_device,
        &dm9000x_device,
@@ -119,6 +127,8 @@ static void __init apf9328_init(void)
        imx1_add_imx_uart0(NULL);
        imx1_add_imx_uart1(&uart1_pdata);
+        imx1_add_imx_i2c(&apf9328_i2c_data);
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
@@ -139,4 +149,5 @@ MACHINE_START(APF9328, "Armadeus APF9328")
        .handle_irq   = imx1_handle_irq,
        .timer        = &apf9328_timer,
        .init_machine = apf9328_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index c9a9cf67755..e4f426a0989 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -561,4 +561,5 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
        .handle_irq = imx31_handle_irq,
        .timer = &armadillo5x0_timer,
        .init_machine = armadillo5x0_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index 313f62ddc1e..9a9897749dd 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -65,4 +65,5 @@ MACHINE_START(BUG, "BugLabs BUGBase")
        .handle_irq = imx31_handle_irq,
        .timer = &bug_timer,
        .init_machine = bug_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index edb37305257..d085aea0870 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -318,4 +318,5 @@ MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
        .handle_irq = imx27_handle_irq,
        .timer = &eukrea_cpuimx27_timer,
        .init_machine = eukrea_cpuimx27_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 362aae78060..8ecc872b254 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -207,4 +207,5 @@ MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
        .handle_irq = imx35_handle_irq,
        .timer = &eukrea_cpuimx35_timer,
        .init_machine = eukrea_cpuimx35_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index ab8fbcc472b..76a97a598b9 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -170,4 +170,5 @@ MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
        .handle_irq = imx25_handle_irq,
        .timer = &eukrea_cpuimx25_timer,
        .init_machine = eukrea_cpuimx25_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 38eb9e45110..c2766ae02b4 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -282,4 +282,5 @@ MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
        .handle_irq = imx27_handle_irq,
        .timer = &visstrim_m10_timer,
        .init_machine = visstrim_m10_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 7052155d055..c9d350c5dcc 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -78,4 +78,5 @@ MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
        .handle_irq = imx27_handle_irq,
        .timer = &mx27ipcam_timer,
        .init_machine = mx27ipcam_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 8d6a63521f1..1f45b918922 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -84,4 +84,5 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
        .handle_irq = imx27_handle_irq,
        .timer = &mx27lite_timer,
        .init_machine = mx27lite_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 8deb012189b..c2572810691 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -10,12 +10,17 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
+#include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/phy.h>
+#include <linux/micrel_phy.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
@@ -23,8 +28,57 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
+void imx6q_restart(char mode, const char *cmd)
+{
+        struct device_node *np;
+        void __iomem *wdog_base;
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt");
+        wdog_base = of_iomap(np, 0);
+        if (!wdog_base)
+                goto soft;
+        imx_src_prepare_restart();
+        /* enable wdog */
+        writew_relaxed(1 << 2, wdog_base);
+        /* write twice to ensure the request will not get ignored */
+        writew_relaxed(1 << 2, wdog_base);
+        /* wait for reset to assert ... */
+        mdelay(500);
+        pr_err("Watchdog reset failed to assert reset\n");
+        /* delay to allow the serial port to show the message */
+        mdelay(50);
+soft:
+        /* we'll take a jump through zero as a poor second */
+        soft_restart(0);
+}
+/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
+static int ksz9021rn_phy_fixup(struct phy_device *phydev)
+{
+        /* min rx data delay */
+        phy_write(phydev, 0x0b, 0x8105);
+        phy_write(phydev, 0x0c, 0x0000);
+        /* max rx/tx clock delay, min rx/tx control delay */
+        phy_write(phydev, 0x0b, 0x8104);
+        phy_write(phydev, 0x0c, 0xf0f0);
+        phy_write(phydev, 0x0b, 0x104);
+        return 0;
+}
 static void __init imx6q_init_machine(void)
 {
+        if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
+                phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
+                                           ksz9021rn_phy_fixup);
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
        imx6q_pm_init();
@@ -72,7 +126,8 @@ static struct sys_timer imx6q_timer = {
 };
 static const char *imx6q_dt_compat[] __initdata = {
-        "fsl,imx6q-sabreauto",
+        "fsl,imx6q-arm2",
+        "fsl,imx6q-sabrelite",
        NULL,
 };
@@ -83,4 +138,5 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
        .timer          = &imx6q_timer,
        .init_machine   = imx6q_init_machine,
        .dt_compat      = imx6q_dt_compat,
+        .restart        = imx6q_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 5f37f89e40f..fc78e8071cd 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -279,4 +279,5 @@ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
        .handle_irq = imx31_handle_irq,
        .timer = &kzm_timer,
        .init_machine = kzm_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index fc49785e734..97046088ff1 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -147,6 +147,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
        .handle_irq = imx1_handle_irq,
        .timer = &mx1ads_timer,
        .init_machine = mx1ads_init,
+        .restart        = mxc_restart,
 MACHINE_END
 MACHINE_START(MXLADS, "Freescale MXLADS")
@@ -157,4 +158,5 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
        .handle_irq = imx1_handle_irq,
        .timer = &mx1ads_timer,
        .init_machine = mx1ads_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 25f84028d05..8d9f95514b1 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -312,4 +312,5 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
        .handle_irq = imx21_handle_irq,
        .timer = &mx21ads_timer,
        .init_machine = mx21ads_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 88dccf12224..f26734298aa 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -270,4 +270,5 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
        .handle_irq = imx25_handle_irq,
        .timer = &mx25pdk_timer,
        .init_machine = mx25pdk_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index ba232d79fa8..18f35816706 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -425,4 +425,5 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
        .handle_irq = imx27_handle_irq,
        .timer = &mx27pdk_timer,
        .init_machine = mx27pdk_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 74dd5731eb6..0228d2e07fe 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -351,4 +351,5 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
        .handle_irq = imx27_handle_irq,
        .timer = &mx27ads_timer,
        .init_machine = mx27ads_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index b8c54b84018..4d1aab15440 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -36,6 +36,7 @@
 #include <asm/mach/time.h>
 #include <asm/memory.h>
 #include <asm/mach/map.h>
+#include <asm/memblock.h>
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/3ds_debugboard.h>
@@ -492,7 +493,7 @@ static struct mc13xxx_platform_data mc13783_pdata = {
                .regulators = mx31_3ds_regulators,
                .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
        },
-        .flags  = MC13XXX_USE_TOUCHSCREEN,
+        .flags  = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC,
 };
 /* SPI */
@@ -754,10 +755,8 @@ static struct sys_timer mx31_3ds_timer = {
 static void __init mx31_3ds_reserve(void)
 {
        /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
-        mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
+        mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE,
                                         MX31_3DS_CAMERA_BUF_SIZE);
-        memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
-        memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
 }
 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
@@ -770,4 +769,5 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
        .timer = &mx31_3ds_timer,
        .init_machine = mx31_3ds_init,
        .reserve = mx31_3ds_reserve,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 9cc1a49053b..4917aab0e25 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -542,4 +542,5 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
        .handle_irq = imx31_handle_irq,
        .timer = &mx31ads_timer,
        .init_machine = mx31ads_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 102ec99357c..02401bbd6d5 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -303,4 +303,5 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
        .handle_irq = imx31_handle_irq,
        .timer = &mx31lilly_timer,
        .init_machine = mx31lilly_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 5366d2de18f..ef80751712e 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -287,4 +287,5 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
        .handle_irq = imx31_handle_irq,
        .timer = &mx31lite_timer,
        .init_machine = mx31lite_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 93269150309..f225262b5c3 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -41,6 +41,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <asm/memblock.h>
 #include <mach/board-mx31moboard.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
@@ -584,10 +585,8 @@ struct sys_timer mx31moboard_timer = {
 static void __init mx31moboard_reserve(void)
 {
        /* reserve 4 MiB for mx3-camera */
-        mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
+        mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
                        MX3_CAMERA_BUF_SIZE);
-        memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
-        memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
 }
 MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
@@ -600,4 +599,5 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
        .handle_irq = imx31_handle_irq,
        .timer = &mx31moboard_timer,
        .init_machine = mx31moboard_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 7a462025a0f..0af6c9c5b3f 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -224,4 +224,5 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
        .handle_irq = imx35_handle_irq,
        .timer = &mx35pdk_timer,
        .init_machine = mx35_3ds_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 125c19643b0..8b3d3f07d89 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -274,4 +274,5 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
        .handle_irq = imx27_handle_irq,
        .timer = &mxt_td60_timer,
        .init_machine = mxt_td60_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 26072f4b02e..d3b9c6b5edd 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -442,4 +442,5 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
        .handle_irq = imx27_handle_irq,
        .init_machine = pca100_init,
        .timer = &pca100_timer,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index efd6b536ef6..e48854b9d99 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -39,6 +39,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
+#include <asm/memblock.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx3.h>
@@ -680,10 +681,8 @@ struct sys_timer pcm037_timer = {
 static void __init pcm037_reserve(void)
 {
        /* reserve 4 MiB for mx3-camera */
-        mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
+        mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
                        MX3_CAMERA_BUF_SIZE);
-        memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
-        memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
 }
 MACHINE_START(PCM037, "Phytec Phycore pcm037")
@@ -696,4 +695,5 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
        .handle_irq = imx31_handle_irq,
        .timer = &pcm037_timer,
        .init_machine = pcm037_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index a17e9c7dfca..16f126da9f8 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -357,4 +357,5 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
        .handle_irq = imx27_handle_irq,
        .timer = &pcm038_timer,
        .init_machine = pcm038_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 7366c2ae3ea..06dc106519a 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -425,4 +425,5 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
        .handle_irq = imx35_handle_irq,
        .timer = &pcm043_timer,
        .init_machine = pcm043_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 4ff5faf102a..260621055b6 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -273,4 +273,5 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
        .handle_irq = imx31_handle_irq,
        .timer = &qong_timer,
        .init_machine = qong_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index bb6e5b25d8d..cb9ceae2f64 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -144,4 +144,5 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
        .handle_irq = imx1_handle_irq,
        .timer = &scb9328_timer,
        .init_machine = scb9328_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 69092458f2d..033257e553e 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -322,4 +322,5 @@ MACHINE_START(VPR200, "VPR200")
        .handle_irq = imx35_handle_irq,
        .timer = &vpr200_timer,
        .init_machine = vpr200_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index f20f191d7cc..f7b0c2b1b90 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -64,7 +64,9 @@ void __init imx6q_pm_init(void)
         * address of the data structure used by l2x0 core to save registers,
         * and later restore the necessary ones in imx6q resume entry.
         */
+#ifdef CONFIG_CACHE_L2X0
        phys_l2x0_saved_regs = __pa(&l2x0_saved_regs);
+#endif
        suspend_set_ops(&imx6q_pm_ops);
 }
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index a8e33681b73..29bd1243781 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -15,10 +15,10 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/smp.h>
-#include <asm/unified.h>
 #define SRC_SCR                         0x000
 #define SRC_GPR1                        0x020
+#define BP_SRC_SCR_WARM_RESET_ENABLE    0
 #define BP_SRC_SCR_CORE1_RST            14
 #define BP_SRC_SCR_CORE1_ENABLE         22
@@ -42,15 +42,37 @@ void imx_enable_cpu(int cpu, bool enable)
 void imx_set_cpu_jump(int cpu, void *jump_addr)
 {
        cpu = cpu_logical_map(cpu);
-        writel_relaxed(BSYM(virt_to_phys(jump_addr)),
+        writel_relaxed(virt_to_phys(jump_addr),
                       src_base + SRC_GPR1 + cpu * 8);
 }
+void imx_src_prepare_restart(void)
+{
+        u32 val;
+        /* clear enable bits of secondary cores */
+        val = readl_relaxed(src_base + SRC_SCR);
+        val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
+        writel_relaxed(val, src_base + SRC_SCR);
+        /* clear persistent entry register of primary core */
+        writel_relaxed(0, src_base + SRC_GPR1);
+}
 void __init imx_src_init(void)
 {
        struct device_node *np;
+        u32 val;
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
        src_base = of_iomap(np, 0);
        WARN_ON(!src_base);
+        /*
+         * force warm reset sources to generate cold reset
+         * for a more reliable restart
+         */
+        val = readl_relaxed(src_base + SRC_SCR);
+        val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
+        writel_relaxed(val, src_base + SRC_SCR);
 }
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index dfd18f3b50e..350e26636a0 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -6,6 +6,8 @@ config ARCH_INTEGRATOR_AP
        bool "Support Integrator/AP and Integrator/PP2 platforms"
        select CLKSRC_MMIO
        select MIGHT_HAVE_PCI
+        select SERIAL_AMBA_PL010
+        select SERIAL_AMBA_PL010_CONSOLE
        help
          Include support for the ARM(R) Integrator/AP and
          Integrator/PP2 platforms.
@@ -15,6 +17,8 @@ config ARCH_INTEGRATOR_CP
        select ARCH_CINTEGRATOR
        select ARM_TIMER_SP804
        select PLAT_VERSATILE_CLCD
+        select SERIAL_AMBA_PL011
+        select SERIAL_AMBA_PL011_CONSOLE
        help
          Include support for the ARM(R) Integrator CP platform.
diff --git a/arch/arm/mach-integrator/common.h b/arch/arm/mach-integrator/common.h
index a08f9b0299d..899561d8db2 100644
--- a/arch/arm/mach-integrator/common.h
+++ b/arch/arm/mach-integrator/common.h
@@ -1,2 +1,3 @@
 void integrator_init_early(void);
 void integrator_reserve(void);
+void integrator_restart(char, const char *);
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 4b38e13667a..019f0ab08f6 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -29,6 +29,7 @@
 #include <mach/cm.h>
 #include <asm/system.h>
 #include <asm/leds.h>
+#include <asm/mach-types.h>
 #include <asm/mach/time.h>
 #include <asm/pgtable.h>
@@ -44,7 +45,6 @@ static struct amba_device rtc_device = {
                .flags  = IORESOURCE_MEM,
        },
        .irq            = { IRQ_RTCINT, NO_IRQ },
-        .periphid       = 0x00041030,
 };
 static struct amba_device uart0_device = {
@@ -58,7 +58,6 @@ static struct amba_device uart0_device = {
                .flags  = IORESOURCE_MEM,
        },
        .irq            = { IRQ_UARTINT0, NO_IRQ },
-        .periphid       = 0x0041010,
 };
 static struct amba_device uart1_device = {
@@ -72,7 +71,6 @@ static struct amba_device uart1_device = {
                .flags  = IORESOURCE_MEM,
        },
        .irq            = { IRQ_UARTINT1, NO_IRQ },
-        .periphid       = 0x0041010,
 };
 static struct amba_device kmi0_device = {
@@ -85,7 +83,6 @@ static struct amba_device kmi0_device = {
                .flags  = IORESOURCE_MEM,
        },
        .irq            = { IRQ_KMIINT0, NO_IRQ },
-        .periphid       = 0x00041050,
 };
 static struct amba_device kmi1_device = {
@@ -98,7 +95,6 @@ static struct amba_device kmi1_device = {
                .flags  = IORESOURCE_MEM,
        },
        .irq            = { IRQ_KMIINT1, NO_IRQ },
-        .periphid       = 0x00041050,
 };
 static struct amba_device *amba_devs[] __initdata = {
@@ -157,6 +153,19 @@ static int __init integrator_init(void)
 {
        int i;
+        /*
+         * The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to
+         * hard-code them. The Integator/CP and forward have proper cell IDs.
+         * Else we leave them undefined to the bus driver can autoprobe them.
+         */
+        if (machine_is_integrator()) {
+                rtc_device.periphid     = 0x00041030;
+                uart0_device.periphid   = 0x00041010;
+                uart1_device.periphid   = 0x00041010;
+                kmi0_device.periphid    = 0x00041050;
+                kmi1_device.periphid    = 0x00041050;
+        }
        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                struct amba_device *d = amba_devs[i];
                amba_device_register(d, &iomem_resource);
@@ -238,3 +247,11 @@ void __init integrator_reserve(void)
 {
        memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
 }
+/*
+ * To reset, we hit the on-board reset register in the system FPGA
+ */
+void integrator_restart(char mode, const char *cmd)
+{
+        cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
+}
diff --git a/arch/arm/mach-integrator/include/mach/system.h b/arch/arm/mach-integrator/include/mach/system.h
index e1551b8dab7..901514eba4a 100644
--- a/arch/arm/mach-integrator/include/mach/system.h
+++ b/arch/arm/mach-integrator/include/mach/system.h
@@ -21,8 +21,6 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <mach/cm.h>
 static inline void arch_idle(void)
 {
        /*
@@ -32,13 +30,4 @@ static inline void arch_idle(void)
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        /*
-         * To reset, we hit the on-board reset register
-         * in the system FPGA
-         */
-        cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
-}
 #endif
diff --git a/arch/arm/mach-integrator/include/mach/vmalloc.h b/arch/arm/mach-integrator/include/mach/vmalloc.h
deleted file mode 100644
index 2f5a2bafb11..00000000000
--- a/arch/arm/mach-integrator/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  arch/arm/mach-integrator/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END       0xd0000000UL
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index a1769f35a86..21a1d6cbef4 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -472,4 +472,5 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
        .init_irq       = ap_init_irq,
        .timer          = &ap_timer,
        .init_machine   = ap_init,
+        .restart        = integrator_restart,
 MACHINE_END
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 5de49c33e4d..a8b6aa6003f 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -14,7 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/string.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/kmi.h>
 #include <linux/amba/clcd.h>
@@ -499,4 +499,5 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
        .init_irq       = intcp_init_irq,
        .timer          = &cp_timer,
        .init_machine   = intcp_init,
+        .restart        = integrator_restart,
 MACHINE_END
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index b4d8f8b8a08..3c82566acec 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -359,7 +359,7 @@ static struct resource pre_mem = {
        .flags  = IORESOURCE_MEM | IORESOURCE_PREFETCH,
 };
-static int __init pci_v3_setup_resources(struct resource **resource)
+static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
 {
        if (request_resource(&iomem_resource, &non_mem)) {
                printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
@@ -374,13 +374,13 @@ static int __init pci_v3_setup_resources(struct resource **resource)
        }
        /*
-         * bus->resource[0] is the IO resource for this bus
+         * the IO resource for this bus
-         * bus->resource[1] is the mem resource for this bus
+         * the mem resource for this bus
-         * bus->resource[2] is the prefetch mem resource for this bus
+         * the prefetch mem resource for this bus
         */
-        resource[0] = &ioport_resource;
+        pci_add_resource(&sys->resources, &ioport_resource);
-        resource[1] = &non_mem;
+        pci_add_resource(&sys->resources, &non_mem);
-        resource[2] = &pre_mem;
+        pci_add_resource(&sys->resources, &pre_mem);
        return 1;
 }
@@ -481,7 +481,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
        if (nr == 0) {
                sys->mem_offset = PHYS_PCI_MEM_BASE;
-                ret = pci_v3_setup_resources(sys->resource);
+                ret = pci_v3_setup_resources(sys);
        }
        return ret;
@@ -489,7 +489,8 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
 struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
 {
-        return pci_scan_bus(sys->busnr, &pci_v3_ops, sys);
+        return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys,
+                                 &sys->resources);
 }
 /*
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index 52b7fab7ef6..07e9ff7adaf 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -10,6 +10,7 @@ void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
 void iop13xx_add_tpmi_devices(void);
 void iop13xx_init_irq(void);
+void iop13xx_restart(char, const char *);
 /* CPUID CP6 R0 Page 0 */
 static inline int iop13xx_cpu_id(void)
diff --git a/arch/arm/mach-iop13xx/include/mach/system.h b/arch/arm/mach-iop13xx/include/mach/system.h
index d0c66ef450a..1f31ed3f8ae 100644
--- a/arch/arm/mach-iop13xx/include/mach/system.h
+++ b/arch/arm/mach-iop13xx/include/mach/system.h
@@ -7,21 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <mach/iop13xx.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        /*
-         * Reset the internal bus (warning both cores are reset)
-         */
-        write_wdtcr(IOP_WDTCR_EN_ARM);
-        write_wdtcr(IOP_WDTCR_EN);
-        write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
-        write_wdtcr(0x1000);
-        for(;;);
-}
diff --git a/arch/arm/mach-iop13xx/include/mach/vmalloc.h b/arch/arm/mach-iop13xx/include/mach/vmalloc.h
deleted file mode 100644
index c5345674034..00000000000
--- a/arch/arm/mach-iop13xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _VMALLOC_H_
-#define _VMALLOC_H_
-#define VMALLOC_END     0xfa000000UL
-#endif
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index 4cf2cc477ea..abaee883358 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -96,4 +96,5 @@ MACHINE_START(IQ81340MC, "Intel IQ81340MC")
        .init_irq       = iop13xx_init_irq,
        .timer          = &iq81340mc_timer,
        .init_machine   = iq81340mc_init,
+        .restart        = iop13xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index cd9e27499a1..690916a09dc 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -98,4 +98,5 @@ MACHINE_START(IQ81340SC, "Intel IQ81340SC")
        .init_irq       = iop13xx_init_irq,
        .timer          = &iq81340sc_timer,
        .init_machine   = iq81340sc_init,
+        .restart        = iop13xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index db012fadf88..b8f5a873651 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -537,14 +537,14 @@ struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
                        while(time_before(jiffies, atux_trhfa_timeout))
                                udelay(100);
-                bus = pci_bus_atux = pci_scan_bus(sys->busnr,
+                bus = pci_bus_atux = pci_scan_root_bus(NULL, sys->busnr,
-                                                  &iop13xx_atux_ops,
+                                                       &iop13xx_atux_ops,
-                                                  sys);
+                                                       sys, &sys->resources);
                break;
        case IOP13XX_INIT_ATU_ATUE:
-                bus = pci_bus_atue = pci_scan_bus(sys->busnr,
+                bus = pci_bus_atue = pci_scan_root_bus(NULL, sys->busnr,
-                                                  &iop13xx_atue_ops,
+                                                       &iop13xx_atue_ops,
-                                                  sys);
+                                                       sys, &sys->resources);
                break;
        }
@@ -1084,9 +1084,8 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
        request_resource(&ioport_resource, &res[0]);
        request_resource(&iomem_resource, &res[1]);
-        sys->resource[0] = &res[0];
+        pci_add_resource(&sys->resources, &res[0]);
-        sys->resource[1] = &res[1];
+        pci_add_resource(&sys->resources, &res[1]);
-        sys->resource[2] = NULL;
        return 1;
 }
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index a5b989728b9..daabb1fa6c2 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -606,3 +606,14 @@ static int __init iop13xx_init_adma_setup(char *str)
 __setup("iop13xx_init_adma", iop13xx_init_adma_setup);
 __setup("iop13xx_init_uart", iop13xx_init_uart_setup);
 __setup("iop13xx_init_i2c", iop13xx_init_i2c_setup);
+void iop13xx_restart(char mode, const char *cmd)
+{
+        /*
+         * Reset the internal bus (warning both cores are reset)
+         */
+        write_wdtcr(IOP_WDTCR_EN_ARM);
+        write_wdtcr(IOP_WDTCR_EN);
+        write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
+        write_wdtcr(0x1000);
+}
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 4325055d4e1..24069e03fdc 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -208,4 +208,5 @@ MACHINE_START(EM7210, "Lanner EM7210")
        .init_irq       = iop32x_init_irq,
        .timer          = &em7210_timer,
        .init_machine   = em7210_init_machine,
+        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 0edc8802057..204e1d1cd76 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -212,4 +212,5 @@ MACHINE_START(GLANTANK, "GLAN Tank")
        .init_irq       = iop32x_init_irq,
        .timer          = &glantank_timer,
        .init_machine   = glantank_init_machine,
+        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
index 059c783ce0b..2d88264b986 100644
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ b/arch/arm/mach-iop32x/include/mach/io.h
@@ -13,15 +13,8 @@
 #include <asm/hardware/iop3xx.h>
-extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
-        unsigned int mtype);
-extern void __iop3xx_iounmap(void __iomem *addr);
 #define IO_SPACE_LIMIT          0xffffffff
 #define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
 #define __mem_pci(a)            (a)
-#define __arch_ioremap  __iop3xx_ioremap
-#define __arch_iounmap  __iop3xx_iounmap
 #endif
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h
index a4b808fe0d8..4a88727bca9 100644
--- a/arch/arm/mach-iop32x/include/mach/system.h
+++ b/arch/arm/mach-iop32x/include/mach/system.h
@@ -7,28 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <asm/mach-types.h>
-#include <asm/hardware/iop3xx.h>
-#include <mach/n2100.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        local_irq_disable();
-        if (machine_is_n2100()) {
-                gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
-                gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
-                while (1)
-                        ;
-        }
-        *IOP3XX_PCSR = 0x30;
-        /* Jump into ROM at address 0 */
-        cpu_reset(0);
-}
diff --git a/arch/arm/mach-iop32x/include/mach/vmalloc.h b/arch/arm/mach-iop32x/include/mach/vmalloc.h
deleted file mode 100644
index c4862d48e58..00000000000
--- a/arch/arm/mach-iop32x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-iop32x/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 9e7aaccfeba..3eb642af1cd 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -318,6 +318,7 @@ MACHINE_START(IQ31244, "Intel IQ31244")
        .init_irq       = iop32x_init_irq,
        .timer          = &iq31244_timer,
        .init_machine   = iq31244_init_machine,
+        .restart        = iop3xx_restart,
 MACHINE_END
 /* There should have been an ep80219 machine identifier from the beginning.
@@ -332,4 +333,5 @@ MACHINE_START(EP80219, "Intel EP80219")
        .init_irq       = iop32x_init_irq,
        .timer          = &iq31244_timer,
        .init_machine   = iq31244_init_machine,
+        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 53ea86f649d..2ec724b58a2 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -191,4 +191,5 @@ MACHINE_START(IQ80321, "Intel IQ80321")
        .init_irq       = iop32x_init_irq,
        .timer          = &iq80321_timer,
        .init_machine   = iq80321_init_machine,
+        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index d7269279968..6b6d5591244 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -291,6 +291,14 @@ static void n2100_power_off(void)
                ;
 }
+static void n2100_restart(char mode, const char *cmd)
+{
+        gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
+        gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
+        while (1)
+                ;
+}
 static struct timer_list power_button_poll_timer;
@@ -332,4 +340,5 @@ MACHINE_START(N2100, "Thecus N2100")
        .init_irq       = iop32x_init_irq,
        .timer          = &n2100_timer,
        .init_machine   = n2100_init_machine,
+        .restart        = n2100_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
index 39e893e97c2..a8a66fc8fbd 100644
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ b/arch/arm/mach-iop33x/include/mach/io.h
@@ -13,15 +13,8 @@
 #include <asm/hardware/iop3xx.h>
-extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
-        unsigned int mtype);
-extern void __iop3xx_iounmap(void __iomem *addr);
 #define IO_SPACE_LIMIT          0xffffffff
 #define __io(p)         ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
 #define __mem_pci(a)            (a)
-#define __arch_ioremap  __iop3xx_ioremap
-#define __arch_iounmap  __iop3xx_iounmap
 #endif
diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h
index f192a34be07..4f98e765397 100644
--- a/arch/arm/mach-iop33x/include/mach/system.h
+++ b/arch/arm/mach-iop33x/include/mach/system.h
@@ -7,17 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <asm/hardware/iop3xx.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        *IOP3XX_PCSR = 0x30;
-        /* Jump into ROM at address 0 */
-        cpu_reset(0);
-}
diff --git a/arch/arm/mach-iop33x/include/mach/vmalloc.h b/arch/arm/mach-iop33x/include/mach/vmalloc.h
deleted file mode 100644
index 48331dc2370..00000000000
--- a/arch/arm/mach-iop33x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-iop33x/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 9e14ccc56f8..abce934f381 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -146,4 +146,5 @@ MACHINE_START(IQ80331, "Intel IQ80331")
        .init_irq       = iop33x_init_irq,
        .timer          = &iq80331_timer,
        .init_machine   = iq80331_init_machine,
+        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 09c899a2523..7513559e25b 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -146,4 +146,5 @@ MACHINE_START(IQ80332, "Intel IQ80332")
        .init_irq       = iop33x_init_irq,
        .timer          = &iq80332_timer,
        .init_machine   = iq80332_init_machine,
+        .restart        = iop3xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 24f0fe35f4a..81c45370a4e 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -515,3 +515,7 @@ void __init ixp2000_init_irq(void)
        }
 }
+void ixp2000_restart(char mode, const char *cmd)
+{
+        ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
+}
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index af9994537e0..e872d238cd0 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -145,7 +145,8 @@ static struct pci_ops enp2611_pci_ops = {
 static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
                                                struct pci_sys_data *sys)
 {
-        return pci_scan_bus(sys->busnr, &enp2611_pci_ops, sys);
+        return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys,
+                                 &sys->resources);
 }
 static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
@@ -259,6 +260,7 @@ MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
        .init_irq       = ixp2000_init_irq,
        .timer          = &enp2611_timer,
        .init_machine   = enp2611_init_machine,
+        .restart        = ixp2000_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h
index 42182c79ed9..bb0f8dcf9ee 100644
--- a/arch/arm/mach-ixp2000/include/mach/platform.h
+++ b/arch/arm/mach-ixp2000/include/mach/platform.h
@@ -122,6 +122,7 @@ void ixp2000_map_io(void);
 void ixp2000_uart_init(void);
 void ixp2000_init_irq(void);
 void ixp2000_init_time(unsigned long);
+void ixp2000_restart(char, const char *);
 unsigned long ixp2000_gettimeoffset(void);
 struct pci_sys_data;
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h
index de370992c84..a7fb08b2b8e 100644
--- a/arch/arm/mach-ixp2000/include/mach/system.h
+++ b/arch/arm/mach-ixp2000/include/mach/system.h
@@ -8,42 +8,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        local_irq_disable();
-        /*
-         * Reset flash banking register so that we are pointing at
-         * RedBoot bank.
-         */
-        if (machine_is_ixdp2401()) {
-                ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
-                                        ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
-                                                | IXDP2X01_CPLD_FLASH_INTERN));
-                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
-        }
-        /*
-         * On IXDP2801 we need to write this magic sequence to the CPLD
-         * to cause a complete reset of the CPU and all external devices
-         * and move the flash bank register back to 0.
-         */
-        if (machine_is_ixdp2801() || machine_is_ixdp28x5()) {
-                unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
-                reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
-                ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
-                ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
-        }
-        ixp2000_reg_wrb(IXP2000_RESET0, RSTALL);
-}
diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
deleted file mode 100644
index 61c8dae24f9..00000000000
--- a/arch/arm/mach-ixp2000/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-ixp2000/include/mach/vmalloc.h
- *
- * Author: Naeem Afzal <naeem.m.afzal@intel.com>
- *
- * Copyright 2002 Intel Corp.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_END         0xfb000000UL
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index f7dfd970014..f53e911ec94 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -176,5 +176,6 @@ MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform")
        .init_irq       = ixdp2400_init_irq,
        .timer          = &ixdp2400_timer,
        .init_machine   = ixdp2x00_init_machine,
+        .restart        = ixp2000_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index d33bcac1ec9..a2e7c393e74 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -291,5 +291,6 @@ MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
        .init_irq       = ixdp2800_init_irq,
        .timer          = &ixdp2800_timer,
        .init_machine   = ixdp2x00_init_machine,
+        .restart        = ixp2000_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 61a28676b5b..7632beadabf 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -413,6 +413,35 @@ static void __init ixdp2x01_init_machine(void)
        ixdp2x01_uart_init();
 }
+static void ixdp2401_restart(char mode, const char *cmd)
+{
+        /*
+         * Reset flash banking register so that we are pointing at
+         * RedBoot bank.
+         */
+        ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
+                                ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
+                                        | IXDP2X01_CPLD_FLASH_INTERN));
+        ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff);
+        ixp2000_restart(mode, cmd);
+}
+static void ixdp280x_restart(char mode, const char *cmd)
+{
+        /*
+         * On IXDP2801 we need to write this magic sequence to the CPLD
+         * to cause a complete reset of the CPU and all external devices
+         * and move the flash bank register back to 0.
+         */
+        unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
+        reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
+        ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg);
+        ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000);
+        ixp2000_restart(mode, cmd);
+}
 #ifdef CONFIG_ARCH_IXDP2401
 MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
@@ -422,6 +451,7 @@ MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
        .init_irq       = ixdp2x01_init_irq,
        .timer          = &ixdp2x01_timer,
        .init_machine   = ixdp2x01_init_machine,
+        .restart        = ixdp2401_restart,
 MACHINE_END
 #endif
@@ -433,6 +463,7 @@ MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
        .init_irq       = ixdp2x01_init_irq,
        .timer          = &ixdp2x01_timer,
        .init_machine   = ixdp2x01_init_machine,
+        .restart        = ixdp280x_restart,
 MACHINE_END
 /*
@@ -446,6 +477,7 @@ MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
        .init_irq       = ixdp2x01_init_irq,
        .timer          = &ixdp2x01_timer,
        .init_machine   = ixdp2x01_init_machine,
+        .restart        = ixdp280x_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index f5098b306fd..626fda435aa 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -132,7 +132,8 @@ static struct pci_ops ixp2000_pci_ops = {
 struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
 {
-        return pci_scan_bus(sysdata->busnr, &ixp2000_pci_ops, sysdata);
+        return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops,
+                                 sysdata, &sysdata->resources);
 }
@@ -242,9 +243,8 @@ int ixp2000_pci_setup(int nr, struct pci_sys_data *sys)
        if (nr >= 1)
                return 0;
-        sys->resource[0] = &ixp2000_pci_io_space;
+        pci_add_resource(&sys->resources, &ixp2000_pci_io_space);
-        sys->resource[1] = &ixp2000_pci_mem_space;
+        pci_add_resource(&sys->resources, &ixp2000_pci_mem_space);
-        sys->resource[2] = NULL;
        return 1;
 }
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index a1bee33d183..0923bb905cc 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -444,3 +444,9 @@ void __init ixp23xx_sys_init(void)
        *IXP23XX_EXP_UNIT_FUSE |= 0xf;
        platform_add_devices(ixp23xx_devices, ARRAY_SIZE(ixp23xx_devices));
 }
+void ixp23xx_restart(char mode, const char *cmd)
+{
+        /* Use on-chip reset capability */
+        *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
+}
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
index 30dd31652e9..8f2487e1fc4 100644
--- a/arch/arm/mach-ixp23xx/espresso.c
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -90,4 +90,5 @@ MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
        .timer          = &ixp23xx_timer,
        .atag_offset    = 0x100,
        .init_machine   = espresso_init,
+        .restart        = ixp23xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
index a1749d0fd89..4ce4353b9f7 100644
--- a/arch/arm/mach-ixp23xx/include/mach/io.h
+++ b/arch/arm/mach-ixp23xx/include/mach/io.h
@@ -20,33 +20,4 @@
 #define __io(p)         ((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
 #define __mem_pci(a)    (a)
-static inline void __iomem *
-ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype)
-{
-        if (addr >= IXP23XX_PCI_MEM_START &&
-                addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
-                if (addr + size > IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE)
-                        return NULL;
-                return (void __iomem *)
-                        ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
-        }
-        return __arm_ioremap(addr, size, mtype);
-}
-static inline void
-ixp23xx_iounmap(void __iomem *addr)
-{
-        if ((((u32)addr) >= IXP23XX_PCI_MEM_VIRT) &&
-            (((u32)addr) < IXP23XX_PCI_MEM_VIRT + IXP23XX_PCI_MEM_SIZE))
-                return;
-        __iounmap(addr);
-}
-#define __arch_ioremap  ixp23xx_ioremap
-#define __arch_iounmap  ixp23xx_iounmap
 #endif
diff --git a/arch/arm/mach-ixp23xx/include/mach/platform.h b/arch/arm/mach-ixp23xx/include/mach/platform.h
index db9d9416e5e..50de558e722 100644
--- a/arch/arm/mach-ixp23xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp23xx/include/mach/platform.h
@@ -34,6 +34,7 @@ struct pci_sys_data;
 void ixp23xx_map_io(void);
 void ixp23xx_init_irq(void);
 void ixp23xx_sys_init(void);
+void ixp23xx_restart(char, const char *);
 int ixp23xx_pci_setup(int, struct pci_sys_data *);
 void ixp23xx_pci_preinit(void);
 struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
diff --git a/arch/arm/mach-ixp23xx/include/mach/system.h b/arch/arm/mach-ixp23xx/include/mach/system.h
index 8920ff2dff1..277dda7334b 100644
--- a/arch/arm/mach-ixp23xx/include/mach/system.h
+++ b/arch/arm/mach-ixp23xx/include/mach/system.h
@@ -7,10 +7,6 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
 static inline void arch_idle(void)
 {
 #if 0
@@ -18,16 +14,3 @@ static inline void arch_idle(void)
                cpu_do_idle();
 #endif
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        /* First try machine specific support */
-        if (machine_is_ixdp2351()) {
-                *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
-                (void) *IXDP2351_CPLD_RESET1_REG;
-                *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
-        }
-        /* Use on-chip reset capability */
-        *IXP23XX_RESET0 |= IXP23XX_RST_ALL;
-}
diff --git a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
deleted file mode 100644
index 896c56a1c00..00000000000
--- a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * arch/arm/mach-ixp23xx/include/mach/vmalloc.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- * NPU mappings end at 0xf0000000 and we allocate 64MB for board
- * specific static I/O.
- */
-#define VMALLOC_END     (0xec000000UL)
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index b3a57e0f341..5d5dd3e8d06 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -326,6 +326,17 @@ static void __init ixdp2351_init(void)
        ixp23xx_sys_init();
 }
+static void ixdp2351_restart(char mode, const char *cmd)
+{
+        /* First try machine specific support */
+        *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_MAGIC;
+        (void) *IXDP2351_CPLD_RESET1_REG;
+        *IXDP2351_CPLD_RESET1_REG = IXDP2351_CPLD_RESET1_ENABLE;
+        ixp23xx_restart(mode, cmd);
+}
 MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
        /* Maintainer: MontaVista Software, Inc. */
        .map_io         = ixdp2351_map_io,
@@ -333,4 +344,5 @@ MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
        .timer          = &ixp23xx_timer,
        .atag_offset    = 0x100,
        .init_machine   = ixdp2351_init,
+        .restart        = ixdp2351_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index e6be5711c70..25b5c462cea 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -143,7 +143,8 @@ struct pci_ops ixp23xx_pci_ops = {
 struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
 {
-        return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
+        return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops,
+                                 sysdata, &sysdata->resources);
 }
 int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
@@ -280,9 +281,8 @@ int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
        if (nr >= 1)
                return 0;
-        sys->resource[0] = &ixp23xx_pci_io_space;
+        pci_add_resource(&sys->resources, &ixp23xx_pci_io_space);
-        sys->resource[1] = &ixp23xx_pci_mem_space;
+        pci_add_resource(&sys->resources, &ixp23xx_pci_mem_space);
-        sys->resource[2] = NULL;
        return 1;
 }
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
index 8f4dcbba902..377283fc658 100644
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -177,4 +177,5 @@ MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
        .timer          = &ixp23xx_timer,
        .atag_offset    = 0x100,
        .init_machine   = roadrunner_init,
+        .restart        = ixp23xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index 37609a22c45..a7277ad470a 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -172,6 +172,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
 /*
@@ -190,6 +191,7 @@ MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 8325058ef87..5eff15f24bc 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -472,9 +472,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
        request_resource(&ioport_resource, &res[0]);
        request_resource(&iomem_resource, &res[1]);
-        sys->resource[0] = &res[0];
+        pci_add_resource(&sys->resources, &res[0]);
-        sys->resource[1] = &res[1];
+        pci_add_resource(&sys->resources, &res[1]);
-        sys->resource[2] = NULL;
        platform_notify = ixp4xx_pci_platform_notify;
        platform_notify_remove = ixp4xx_pci_platform_notify_remove;
@@ -484,7 +483,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
 struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
 {
-        return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
+        return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys,
+                                 &sys->resources);
 }
 int dma_set_coherent_mask(struct device *dev, u64 mask)
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index b86a0055ab9..3841ab4146b 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -17,7 +17,6 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/serial.h>
-#include <linux/sched.h>
 #include <linux/tty.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
@@ -403,18 +402,9 @@ void __init ixp4xx_sys_init(void)
 /*
 * sched_clock()
 */
-static DEFINE_CLOCK_DATA(cd);
+static u32 notrace ixp4xx_read_sched_clock(void)
-unsigned long long notrace sched_clock(void)
-{
-        u32 cyc = *IXP4XX_OSTS;
-        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-static void notrace ixp4xx_update_sched_clock(void)
 {
-        u32 cyc = *IXP4XX_OSTS;
+        return *IXP4XX_OSTS;
-        update_sched_clock(&cd, cyc, (u32)~0);
 }
 /*
@@ -430,7 +420,7 @@ unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
 EXPORT_SYMBOL(ixp4xx_timer_freq);
 static void __init ixp4xx_clocksource_init(void)
 {
-        init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq);
+        setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
        clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
                        ixp4xx_clocksource_read);
@@ -501,3 +491,23 @@ static void __init ixp4xx_clockevent_init(void)
        clockevents_register_device(&clockevent_ixp4xx);
 }
+void ixp4xx_restart(char mode, const char *cmd)
+{
+        if ( 1 && mode == 's') {
+                /* Jump into ROM at address 0 */
+                soft_restart(0);
+        } else {
+                /* Use on-chip reset capability */
+                /* set the "key" register to enable access to
+                 * "timer" and "enable" registers
+                 */
+                *IXP4XX_OSWK = IXP4XX_WDT_KEY;
+                /* write 0 to the timer register for an immediate reset */
+                *IXP4XX_OSWT = 0;
+                *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
+        }
+}
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index 81dfec31842..a74f86ce8bc 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -117,6 +117,7 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
 #endif
@@ -132,6 +133,7 @@ MACHINE_START(IXDPG425, "Intel IXDPG425")
        .timer          = &ixp4xx_timer,
        .atag_offset    = 0x100,
        .init_machine   = coyote_init,
+        .restart        = ixp4xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 8837fbca27c..67be177b336 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -286,4 +286,5 @@ MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 2887c3578c1..6d5818285af 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -277,5 +277,6 @@ MACHINE_START(FSG, "Freecom FSG-3")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index d69d1b053bb..7ecf9b28f1c 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -104,5 +104,6 @@ MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index bf6678d1a92..c0e3d69a8ae 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -504,4 +504,5 @@ MACHINE_START(GORAMO_MLR, "MultiLink")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index aa029fc1914..a23f8939145 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -172,6 +172,7 @@ MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/include/mach/platform.h b/arch/arm/mach-ixp4xx/include/mach/platform.h
index e824c02c825..df9250bbf13 100644
--- a/arch/arm/mach-ixp4xx/include/mach/platform.h
+++ b/arch/arm/mach-ixp4xx/include/mach/platform.h
@@ -125,6 +125,7 @@ extern void ixp4xx_init_irq(void);
 extern void ixp4xx_sys_init(void);
 extern void ixp4xx_timer_init(void);
 extern struct sys_timer ixp4xx_timer;
+extern void ixp4xx_restart(char, const char *);
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;
 extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h
index 54c0af7fa2d..140a9bef446 100644
--- a/arch/arm/mach-ixp4xx/include/mach/system.h
+++ b/arch/arm/mach-ixp4xx/include/mach/system.h
@@ -8,9 +8,6 @@
 * published by the Free Software Foundation.
 *
 */
-#include <mach/hardware.h>
 static inline void arch_idle(void)
 {
        /* ixp4xx does not implement the XScale PWRMODE register,
@@ -20,25 +17,3 @@ static inline void arch_idle(void)
        cpu_do_idle();
 #endif
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        if ( 1 && mode == 's') {
-                /* Jump into ROM at address 0 */
-                cpu_reset(0);
-        } else {
-                /* Use on-chip reset capability */
-                /* set the "key" register to enable access to
-                 * "timer" and "enable" registers
-                 */
-                *IXP4XX_OSWK = IXP4XX_WDT_KEY;
-                /* write 0 to the timer register for an immediate reset */
-                *IXP4XX_OSWT = 0;
-                *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
-        }
-}
diff --git a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
deleted file mode 100644
index 9bcd64d5985..00000000000
--- a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-ixp4xx/include/mach/vmalloc.h
- */
-#define VMALLOC_END       (0xff000000UL)
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index f235f829dfa..8a38b39999f 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -261,6 +261,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index de716fa1aab..1010eb7b008 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -321,4 +321,5 @@ MACHINE_START(NAS100D, "Iomega NAS 100d")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index ac81ccb26bf..aa355c360d5 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -307,4 +307,5 @@ MACHINE_START(NSLU2, "Linksys NSLU2")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/omixp-setup.c b/arch/arm/mach-ixp4xx/omixp-setup.c
index 3b6a81a696f..0940869fcfd 100644
--- a/arch/arm/mach-ixp4xx/omixp-setup.c
+++ b/arch/arm/mach-ixp4xx/omixp-setup.c
@@ -246,6 +246,7 @@ MACHINE_START(DEVIXP, "Omicron DEVIXP")
        .init_irq       = ixp4xx_init_irq,
        .timer          = &ixp4xx_timer,
        .init_machine   = omixp_init,
+        .restart        = ixp4xx_restart,
 MACHINE_END
 #endif
@@ -259,6 +260,7 @@ MACHINE_START(MICCPT, "Omicron MICCPT")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
 #endif
@@ -269,5 +271,6 @@ MACHINE_START(MIC256, "Omicron MIC256")
        .init_irq       = ixp4xx_init_irq,
        .timer          = &ixp4xx_timer,
        .init_machine   = omixp_init,
+        .restart        = ixp4xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index 27e469ef452..9dec2068329 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -244,4 +244,5 @@ MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index b14144b967a..5ac0f0a0fd8 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -105,5 +105,6 @@ MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
 #if defined(CONFIG_PCI)
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = ixp4xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 8d03bcef518..e9a7180863d 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -13,12 +13,12 @@
 #include <linux/mbus.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <plat/addr-map.h>
 #include "common.h"
 /*
 * Generic Address Decode Windows bit settings
 */
-#define TARGET_DDR              0
 #define TARGET_DEV_BUS          1
 #define TARGET_SRAM             3
 #define TARGET_PCIE             4
@@ -36,118 +36,55 @@
 #define ATTR_SRAM               0x01
 /*
- * Helpers to get DDR bank info
+ * Description of the windows needed by the platform code
 */
-#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
-#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
+        .num_wins = 8,
+        .remappable_wins = 4,
-/*
+        .bridge_virt_base = BRIDGE_VIRT_BASE,
- * CPU Address Decode Windows registers
+};
- */
-#define WIN_OFF(n)              (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
-#define WIN_CTRL_OFF            0x0000
-#define WIN_BASE_OFF            0x0004
-#define WIN_REMAP_LO_OFF        0x0008
-#define WIN_REMAP_HI_OFF        0x000c
-struct mbus_dram_target_info kirkwood_mbus_dram_info;
-static int __init cpu_win_can_remap(int win)
-{
-        if (win < 4)
-                return 1;
-        return 0;
-}
-static void __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        void __iomem *addr = (void __iomem *)WIN_OFF(win);
-        u32 ctrl;
-        base &= 0xffff0000;
-        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
-        writel(base, addr + WIN_BASE_OFF);
-        writel(ctrl, addr + WIN_CTRL_OFF);
-        if (cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
-                writel(0, addr + WIN_REMAP_HI_OFF);
-        }
-}
-void __init kirkwood_setup_cpu_mbus(void)
-{
-        void __iomem *addr;
-        int i;
-        int cs;
+static const struct __initdata orion_addr_map_info addr_map_info[] = {
        /*
-         * First, disable and clear windows.
+         * Windows for PCIe IO+MEM space.
         */
-        for (i = 0; i < 8; i++) {
+        { 0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
-                addr = (void __iomem *)WIN_OFF(i);
+          TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE
+        },
-                writel(0, addr + WIN_BASE_OFF);
+        { 1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
-                writel(0, addr + WIN_CTRL_OFF);
+          TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE
-                if (cpu_win_can_remap(i)) {
+        },
-                        writel(0, addr + WIN_REMAP_LO_OFF);
+        { 2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
-                        writel(0, addr + WIN_REMAP_HI_OFF);
+          TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE
-                }
+        },
-        }
+        { 3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+          TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE
+        },
        /*
-         * Setup windows for PCIe IO+MEM space.
+         * Window for NAND controller.
         */
-        setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
+        { 4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
-                      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
+          TARGET_DEV_BUS, ATTR_DEV_NAND, -1
-        setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
+        },
-                      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
-        setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
-                      TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
-        setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
-                      TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
        /*
-         * Setup window for NAND controller.
+         * Window for SRAM.
         */
-        setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+        { 5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
-                      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
+          TARGET_SRAM, ATTR_SRAM, -1
+        },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 }
+};
+void __init kirkwood_setup_cpu_mbus(void)
+{
        /*
-         * Setup window for SRAM.
+         * Disable, clear and configure windows.
         */
-        setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+        orion_config_wins(&addr_map_cfg, addr_map_info);
-                      TARGET_SRAM, ATTR_SRAM, -1);
        /*
         * Setup MBUS dram target info.
         */
-        kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+        orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
-        addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
-        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
-                /*
-                 * Chip select enabled?
-                 */
-                if (size & 1) {
-                        struct mbus_dram_window *w;
-                        w = &kirkwood_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xffff0000;
-                        w->size = (size | 0x0000ffff) + 1;
-                }
-        }
-        kirkwood_mbus_dram_info.num_cs = cs;
 }
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index f3248cfbe51..cc15426787b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -12,7 +12,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
-#include <linux/mbus.h>
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
 #include <linux/dma-mapping.h>
@@ -30,6 +29,7 @@
 #include <plat/orion_nand.h>
 #include <plat/common.h>
 #include <plat/time.h>
+#include <plat/addr-map.h>
 #include "common.h"
 /*****************************************************************************
@@ -73,8 +73,7 @@ unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
 void __init kirkwood_ehci_init(void)
 {
        kirkwood_clk_ctrl |= CGC_USB0;
-        orion_ehci_init(&kirkwood_mbus_dram_info,
+        orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
-                        USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
 }
@@ -85,7 +84,7 @@ void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
        kirkwood_clk_ctrl |= CGC_GE0;
-        orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
+        orion_ge00_init(eth_data,
                        GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
                        IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
 }
@@ -99,7 +98,7 @@ void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
        kirkwood_clk_ctrl |= CGC_GE1;
-        orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
+        orion_ge01_init(eth_data,
                        GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
                        IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
 }
@@ -178,8 +177,7 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
        if (sata_data->n_ports > 1)
                kirkwood_clk_ctrl |= CGC_SATA1;
-        orion_sata_init(sata_data, &kirkwood_mbus_dram_info,
+        orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
-                        SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
 }
@@ -221,7 +219,6 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
                mvsdio_data->clock = 100000000;
        else
                mvsdio_data->clock = 200000000;
-        mvsdio_data->dram = &kirkwood_mbus_dram_info;
        kirkwood_clk_ctrl |= CGC_SDIO;
        kirkwood_sdio.dev.platform_data = mvsdio_data;
        platform_device_register(&kirkwood_sdio);
@@ -285,8 +282,7 @@ static void __init kirkwood_xor0_init(void)
 {
        kirkwood_clk_ctrl |= CGC_XOR0;
-        orion_xor0_init(&kirkwood_mbus_dram_info,
+        orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
-                        XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
                        IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
 }
@@ -364,7 +360,6 @@ static struct resource kirkwood_i2s_resources[] = {
 };
 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
-        .dram        = &kirkwood_mbus_dram_info,
        .burst       = 128,
 };
@@ -430,6 +425,8 @@ static char * __init kirkwood_id(void)
        } else if (dev == MV88F6282_DEV_ID) {
                if (rev == MV88F6282_REV_A0)
                        return "MV88F6282-Rev-A0";
+                else if (rev == MV88F6282_REV_A1)
+                        return "MV88F6282-Rev-A1";
                else
                        return "MV88F6282-Rev-Unsupported";
        } else {
@@ -534,3 +531,19 @@ static int __init kirkwood_clock_gate(void)
        return 0;
 }
 late_initcall(kirkwood_clock_gate);
+void kirkwood_restart(char mode, const char *cmd)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+        while (1)
+                ;
+}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index b9b0f0968a3..9071a397136 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -30,7 +30,6 @@ void kirkwood_init(void);
 void kirkwood_init_early(void);
 void kirkwood_init_irq(void);
-extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
 void kirkwood_setup_cpu_mbus(void);
 void kirkwood_enable_pcie(void);
@@ -50,6 +49,7 @@ void kirkwood_uart1_init(void);
 void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
 void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *));
 void kirkwood_audio_init(void);
+void kirkwood_restart(char, const char *);
 extern int kirkwood_tclk;
 extern struct sys_timer kirkwood_timer;
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index f457e07a65f..6e1bac929ab 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -227,4 +227,5 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index ff4c21c1f92..d9335937959 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -103,4 +103,5 @@ MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index e4d199b2b1e..61d9a552a05 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -108,4 +108,5 @@ MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 6c40f784b51..bdaed3867d1 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -127,4 +127,5 @@ MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
index 1aaddc364f2..49dd0cb5e16 100644
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ b/arch/arm/mach-kirkwood/include/mach/io.h
@@ -19,31 +19,6 @@ static inline void __iomem *__io(unsigned long addr)
                                        + KIRKWOOD_PCIE_IO_VIRT_BASE);
 }
-static inline void __iomem *
-__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
-{
-        void __iomem *retval;
-        unsigned long offs = paddr - KIRKWOOD_REGS_PHYS_BASE;
-        if (mtype == MT_DEVICE && size && offs < KIRKWOOD_REGS_SIZE &&
-            size <= KIRKWOOD_REGS_SIZE && offs + size <= KIRKWOOD_REGS_SIZE) {
-                retval = (void __iomem *)KIRKWOOD_REGS_VIRT_BASE + offs;
-        } else {
-                retval = __arm_ioremap(paddr, size, mtype);
-        }
-        return retval;
-}
-static inline void
-__arch_iounmap(void __iomem *addr)
-{
-        if (addr < (void __iomem *)KIRKWOOD_REGS_VIRT_BASE ||
-            addr >= (void __iomem *)(KIRKWOOD_REGS_VIRT_BASE + KIRKWOOD_REGS_SIZE))
-                __iounmap(addr);
-}
-#define __arch_ioremap          __arch_ioremap
-#define __arch_iounmap          __arch_iounmap
 #define __io(a)                 __io(a)
 #define __mem_pci(a)            (a)
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 010bdeb4ac5..fede3d503ef 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -135,4 +135,5 @@
 #define MV88F6282_DEV_ID        0x6282
 #define MV88F6282_REV_A0        0
+#define MV88F6282_REV_A1        1
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/system.h b/arch/arm/mach-kirkwood/include/mach/system.h
index 7568e95d279..5fddde002b5 100644
--- a/arch/arm/mach-kirkwood/include/mach/system.h
+++ b/arch/arm/mach-kirkwood/include/mach/system.h
@@ -9,28 +9,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <mach/bridge-regs.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        /*
-         * Enable soft reset to assert RSTOUTn.
-         */
-        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-        /*
-         * Assert soft reset.
-         */
-        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-        while (1)
-                ;
-}
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/vmalloc.h b/arch/arm/mach-kirkwood/include/mach/vmalloc.h
deleted file mode 100644
index bf162ca3d2c..00000000000
--- a/arch/arm/mach-kirkwood/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index cc431fa22cc..0c6ad63f10c 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -10,7 +10,6 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mbus.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
 #include <plat/mpp.h>
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index ac787957e2d..e8fda45c073 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -102,6 +102,7 @@
 #define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 1, 0,   1,   1,   1,   1 )
 #define MPP12_GPO               MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_GPIO              MPP( 12, 0x0, 1, 1, 0,   0,   0,   1,   0 )
 #define MPP12_SD_CLK            MPP( 12, 0x1, 0, 1, 1,   1,   1,   1,   1 )
 #define MPP12_AU_SPDIF0         MPP( 12, 0xa, 0, 1, 0,   0,   0,   0,   1 )
 #define MPP12_SPI_MOSI          MPP( 12, 0xb, 0, 1, 0,   0,   0,   0,   1 )
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 9a1e917352f..85f6169c248 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -169,4 +169,5 @@ MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 8849bcc7328..e6bba01bae3 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -264,6 +264,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -275,6 +276,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -286,5 +288,6 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 1ba12c4dff8..31ae8de34e9 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -405,6 +405,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -416,5 +417,6 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 5660ca6c3d8..01f8c899288 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -220,6 +220,7 @@ MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -232,6 +233,7 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -244,5 +246,6 @@ MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 74b992d810e..a066a6d8d9d 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -11,12 +11,12 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
 #include <linux/slab.h>
-#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
 #include <mach/bridge-regs.h>
+#include <plat/addr-map.h>
 #include "common.h"
 void kirkwood_enable_pcie(void)
@@ -198,9 +198,8 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
        if (request_resource(&iomem_resource, &pp->res[1]))
                panic("Request PCIe%d Memory resource failed\n", index);
-        sys->resource[0] = &pp->res[0];
+        pci_add_resource(&sys->resources, &pp->res[0]);
-        sys->resource[1] = &pp->res[1];
+        pci_add_resource(&sys->resources, &pp->res[1]);
-        sys->resource[2] = NULL;
        sys->io_offset = 0;
        /*
@@ -208,7 +207,7 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
         */
        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
-        orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
+        orion_pcie_setup(pp->base);
        return 1;
 }
@@ -236,7 +235,8 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
        struct pci_bus *bus;
        if (nr < num_pcie_ports) {
-                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+                bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
+                                        &sys->resources);
        } else {
                bus = NULL;
                BUG();
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 6663869773a..fd2c9c8b683 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -85,4 +85,5 @@ MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 66b3c05e37a..ef922079348 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -121,4 +121,5 @@ MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 8b102d62e82..4ea70e5f713 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -107,7 +107,7 @@ static void __init sheevaplug_init(void)
        kirkwood_init();
        /* setup gpio pin select */
-        if (machine_is_sheeva_esata())
+        if (machine_is_esata_sheevaplug())
                kirkwood_mpp_conf(sheeva_esata_mpp_config);
        else
                kirkwood_mpp_conf(sheevaplug_mpp_config);
@@ -123,11 +123,11 @@ static void __init sheevaplug_init(void)
        kirkwood_ge00_init(&sheevaplug_ge00_data);
        /* honor lower power consumption for plugs with out eSATA */
-        if (machine_is_sheeva_esata())
+        if (machine_is_esata_sheevaplug())
                kirkwood_sata_init(&sheeva_esata_sata_data);
        /* enable sd wp and sd cd on plugs with esata */
-        if (machine_is_sheeva_esata())
+        if (machine_is_esata_sheevaplug())
                kirkwood_sdio_init(&sheeva_esata_mvsdio_data);
        else
                kirkwood_sdio_init(&sheevaplug_mvsdio_data);
@@ -144,6 +144,7 @@ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
@@ -155,5 +156,6 @@ MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index ea104fb5ec3..966b2b3bb81 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -207,4 +207,5 @@ MACHINE_START(T5325, "HP t5325 Thin Client")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 262c034836d..73e2b6ca956 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -138,4 +138,5 @@ MACHINE_START(TS219, "QNAP TS-119/TS-219")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index b68f5b4a9ec..5bbca268044 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -182,4 +182,5 @@ MACHINE_START(TS41X, "QNAP TS-41x")
        .init_early     = kirkwood_init_early,
        .init_irq       = kirkwood_init_irq,
        .timer          = &kirkwood_timer,
+        .restart        = kirkwood_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
index a91f99d265a..255502ddd87 100644
--- a/arch/arm/mach-ks8695/board-acs5k.c
+++ b/arch/arm/mach-ks8695/board-acs5k.c
@@ -228,4 +228,5 @@ MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board")
        .init_irq       = ks8695_init_irq,
        .init_machine   = acs5k_init,
        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ks8695/board-dsm320.c b/arch/arm/mach-ks8695/board-dsm320.c
index d24bcef2e2d..e0d36cef2c5 100644
--- a/arch/arm/mach-ks8695/board-dsm320.c
+++ b/arch/arm/mach-ks8695/board-dsm320.c
@@ -126,4 +126,5 @@ MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player")
        .init_irq       = ks8695_init_irq,
        .init_machine   = dsm320_init,
        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c
index 16c95657f8f..a8270725b76 100644
--- a/arch/arm/mach-ks8695/board-micrel.c
+++ b/arch/arm/mach-ks8695/board-micrel.c
@@ -58,4 +58,5 @@ MACHINE_START(KS8695, "KS8695 Centaur Development Board")
        .init_irq       = ks8695_init_irq,
        .init_machine   = micrel_init,
        .timer          = &ks8695_timer,
+        .restart        = ks8695_restart,
 MACHINE_END
diff --git a/arch/arm/mach-ks8695/generic.h b/arch/arm/mach-ks8695/generic.h
index 2fbfab8d5fa..f8bdb11a9c3 100644
--- a/arch/arm/mach-ks8695/generic.h
+++ b/arch/arm/mach-ks8695/generic.h
@@ -12,4 +12,5 @@
 extern __init void ks8695_map_io(void);
 extern __init void ks8695_init_irq(void);
+extern void ks8695_restart(char, const char *);
 extern struct sys_timer ks8695_timer;
diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h
index fb1dda9be2d..59fe992395b 100644
--- a/arch/arm/mach-ks8695/include/mach/system.h
+++ b/arch/arm/mach-ks8695/include/mach/system.h
@@ -14,9 +14,6 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <linux/io.h>
-#include <mach/regs-timer.h>
 static void arch_idle(void)
 {
        /*
@@ -27,22 +24,4 @@ static void arch_idle(void)
 }
-static void arch_reset(char mode, const char *cmd)
-{
-        unsigned int reg;
-        if (mode == 's')
-                cpu_reset(0);
-        /* disable timer0 */
-        reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
-        __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
-        /* enable watchdog mode */
-        __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
-        /* re-enable timer0 */
-        __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
-}
 #endif
diff --git a/arch/arm/mach-ks8695/include/mach/vmalloc.h b/arch/arm/mach-ks8695/include/mach/vmalloc.h
deleted file mode 100644
index 744ac66be3a..00000000000
--- a/arch/arm/mach-ks8695/include/mach/vmalloc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/vmalloc.h
- *
- * Copyright (C) 2006 Ben Dooks
- * Copyright (C) 2006 Simtec Electronics <linux@simtec.co.uk>
- *
- * KS8695 vmalloc definition
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END       (KS8695_IO_VA & PGDIR_MASK)
-#endif
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c
index a78092dcd6f..76802aac0f4 100644
--- a/arch/arm/mach-ks8695/irq.c
+++ b/arch/arm/mach-ks8695/irq.c
@@ -23,7 +23,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index c7c9a188d10..b26f992071d 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -143,7 +143,8 @@ static struct pci_ops ks8695_pci_ops = {
 static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
 {
-        return pci_scan_bus(sys->busnr, &ks8695_pci_ops, sys);
+        return pci_scan_root_bus(NULL, sys->busnr, &ks8695_pci_ops, sys,
+                                 &sys->resources);
 }
 static struct resource pci_mem = {
@@ -168,9 +169,8 @@ static int __init ks8695_pci_setup(int nr, struct pci_sys_data *sys)
        request_resource(&iomem_resource, &pci_mem);
        request_resource(&ioport_resource, &pci_io);
-        sys->resource[0] = &pci_io;
+        pci_add_resource(&sys->resources, &pci_io);
-        sys->resource[1] = &pci_mem;
+        pci_add_resource(&sys->resources, &pci_mem);
-        sys->resource[2] = NULL;
        /* Assign and enable processor bridge */
        ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA);
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index 69c072c2c0f..37dfcd5bd2a 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -109,3 +109,21 @@ struct sys_timer ks8695_timer = {
        .offset         = ks8695_gettimeoffset,
        .resume         = ks8695_timer_setup,
 };
+void ks8695_restart(char mode, const char *cmd)
+{
+        unsigned int reg;
+        if (mode == 's')
+                soft_restart(0);
+        /* disable timer0 */
+        reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
+        __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+        /* enable watchdog mode */
+        __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
+        /* re-enable timer0 */
+        __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+}
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 205b2dbb565..369b152896c 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -164,7 +164,7 @@ int clk_is_sysclk_mainosc(void)
 /*
 * System reset via the watchdog timer
 */
-void lpc32xx_watchdog_reset(void)
+static void lpc32xx_watchdog_reset(void)
 {
        /* Make sure WDT clocks are enabled */
        __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
@@ -311,3 +311,21 @@ void __init lpc32xx_map_io(void)
 {
        iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
 }
+void lpc23xx_restart(char mode, const char *cmd)
+{
+        switch (mode) {
+        case 's':
+        case 'h':
+                lpc32xx_watchdog_reset();
+                break;
+        default:
+                /* Do nothing */
+                break;
+        }
+        /* Wait for watchdog to reset system */
+        while (1)
+                ;
+}
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 5583f52662b..4b4e700343c 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -39,6 +39,8 @@ extern void __init lpc32xx_init_irq(void);
 extern void __init lpc32xx_map_io(void);
 extern void __init lpc32xx_serial_init(void);
 extern void __init lpc32xx_gpio_init(void);
+extern void lpc23xx_restart(char, const char *);
 /*
 * Structure used for setting up and querying the PLLS
diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h
index df3b0dea4d7..bf176c99152 100644
--- a/arch/arm/mach-lpc32xx/include/mach/system.h
+++ b/arch/arm/mach-lpc32xx/include/mach/system.h
@@ -24,29 +24,4 @@ static void arch_idle(void)
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        extern void lpc32xx_watchdog_reset(void);
-        switch (mode) {
-        case 's':
-        case 'h':
-                printk(KERN_CRIT "RESET: Rebooting system\n");
-                /* Disable interrupts */
-                local_irq_disable();
-                lpc32xx_watchdog_reset();
-                break;
-        default:
-                /* Do nothing */
-                break;
-        }
-        /* Wait for watchdog to reset system */
-        while (1)
-                ;
-}
 #endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
deleted file mode 100644
index 720fa43a60b..00000000000
--- a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-lpc32xx/include/mach/vmalloc.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END     0xF0000000UL
-#endif
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 6d2f0d1b937..bfee5b45510 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -18,7 +18,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/dma-mapping.h>
@@ -388,4 +388,5 @@ MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
        .init_irq       = lpc32xx_init_irq,
        .timer          = &lpc32xx_timer,
        .init_machine   = phy3250_board_init,
+        .restart        = lpc23xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 7a60bbbce7a..17cb7606012 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -120,8 +120,8 @@ static struct resource smc91x_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = gpio_to_irq(27),
+                .start  = MMP_GPIO_TO_IRQ(27),
-                .end    = gpio_to_irq(27),
+                .end    = MMP_GPIO_TO_IRQ(27),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        }
 };
@@ -232,6 +232,7 @@ static void __init common_init(void)
        pxa168_add_nand(&aspenite_nand_info);
        pxa168_add_fb(&aspenite_lcd_info);
        pxa168_add_keypad(&aspenite_keypad_info);
+        platform_device_register(&pxa168_device_gpio);
        /* off-chip devices */
        platform_device_register(&smc91x_device);
@@ -243,6 +244,7 @@ MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
        .init_irq       = pxa168_init_irq,
        .timer          = &pxa168_timer,
        .init_machine   = common_init,
+        .restart        = pxa168_restart,
 MACHINE_END
 MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
@@ -251,4 +253,5 @@ MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
        .init_irq       = pxa168_init_irq,
        .timer          = &pxa168_timer,
        .init_machine   = common_init,
+        .restart        = pxa168_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c
index 39f0878d64a..b148a9dc5a4 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -38,6 +38,7 @@ static void __init avengers_lite_init(void)
        /* on-chip devices */
        pxa168_add_uart(2);
+        platform_device_register(&pxa168_device_gpio);
 }
 MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
@@ -45,4 +46,5 @@ MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
        .init_irq       = pxa168_init_irq,
        .timer          = &pxa168_timer,
        .init_machine   = avengers_lite_init,
+        .restart        = pxa168_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
index 983cfb15fbd..d839fe6421e 100644
--- a/arch/arm/mach-mmp/brownstone.c
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -202,6 +202,7 @@ static void __init brownstone_init(void)
        /* on-chip devices */
        mmp2_add_uart(1);
        mmp2_add_uart(3);
+        platform_device_register(&mmp2_device_gpio);
        mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
        mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
        mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */
@@ -219,4 +220,5 @@ MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
        .init_irq       = mmp2_init_irq,
        .timer          = &mmp2_timer,
        .init_machine   = brownstone_init,
+        .restart        = mmp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c
index 5720674739f..062b5b93c50 100644
--- a/arch/arm/mach-mmp/common.c
+++ b/arch/arm/mach-mmp/common.c
@@ -45,3 +45,8 @@ void __init mmp_map_io(void)
        /* this is early, initialize mmp_chip_id here */
        mmp_chip_id = __raw_readl(MMP_CHIPID);
 }
+void mmp_restart(char mode, const char *cmd)
+{
+        soft_restart(0);
+}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index ec8d65ded25..1c9d6c1ea97 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -6,3 +6,4 @@ extern void timer_init(int irq);
 extern void __init icu_init_irq(void);
 extern void __init mmp_map_io(void);
+extern void mmp_restart(char, const char *);
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index c4fd806b15b..2ee8cd7829d 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -87,8 +87,8 @@ static struct resource smc91x_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = gpio_to_irq(155),
+                .start  = MMP_GPIO_TO_IRQ(155),
-                .end    = gpio_to_irq(155),
+                .end    = MMP_GPIO_TO_IRQ(155),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        }
 };
@@ -110,6 +110,7 @@ static void __init flint_init(void)
        /* on-chip devices */
        mmp2_add_uart(1);
        mmp2_add_uart(2);
+        platform_device_register(&mmp2_device_gpio);
        /* off-chip devices */
        platform_device_register(&smc91x_device);
@@ -121,4 +122,5 @@ MACHINE_START(FLINT, "Flint Development Platform")
        .init_irq       = mmp2_init_irq,
        .timer          = &mmp2_timer,
        .init_machine   = flint_init,
+        .restart        = mmp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
index 4665767a4f7..87765467de6 100644
--- a/arch/arm/mach-mmp/gplugd.c
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -184,6 +184,7 @@ static void __init gplugd_init(void)
        pxa168_add_uart(3);
        pxa168_add_ssp(1);
        pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
+        platform_device_register(&pxa168_device_gpio);
        pxa168_add_eth(&gplugd_eth_platform_data);
 }
@@ -194,4 +195,5 @@ MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform")
        .init_irq       = pxa168_init_irq,
        .timer          = &pxa168_timer,
        .init_machine   = gplugd_init,
+        .restart        = pxa168_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/include/mach/gpio-pxa.h b/arch/arm/mach-mmp/include/mach/gpio-pxa.h
index 99b4ce1b656..0e135a599f3 100644
--- a/arch/arm/mach-mmp/include/mach/gpio-pxa.h
+++ b/arch/arm/mach-mmp/include/mach/gpio-pxa.h
@@ -2,6 +2,7 @@
 #define __ASM_MACH_GPIO_PXA_H
 #include <mach/addr-map.h>
+#include <mach/cputype.h>
 #include <mach/irqs.h>
 #define GPIO_REGS_VIRT  (APB_VIRT_BASE + 0x19000)
@@ -9,8 +10,6 @@
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 #define GPIO_REG(x)     (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
-#define NR_BUILTIN_GPIO         IRQ_GPIO_NUM
 #define gpio_to_bank(gpio)      ((gpio) >> 5)
 /* NOTE: these macros are defined here to make optimization of
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h
index 681262359d1..13219ebf512 100644
--- a/arch/arm/mach-mmp/include/mach/gpio.h
+++ b/arch/arm/mach-mmp/include/mach/gpio.h
@@ -3,11 +3,6 @@
 #include <asm-generic/gpio.h>
-#define gpio_to_irq(gpio)       (IRQ_GPIO_START + (gpio))
+#include <mach/cputype.h>
-#define irq_to_gpio(irq)        ((irq) - IRQ_GPIO_START)
-#define __gpio_is_inverted(gpio)        (0)
-#define __gpio_is_occupied(gpio)        (0)
-#include <plat/gpio.h>
 #endif /* __ASM_MACH_GPIO_H */
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h
index a09d328e2dd..34635a0bbb5 100644
--- a/arch/arm/mach-mmp/include/mach/irqs.h
+++ b/arch/arm/mach-mmp/include/mach/irqs.h
@@ -219,10 +219,10 @@
 #define IRQ_MMP2_MUX_END                (IRQ_MMP2_SSP_BASE + 2)
 #define IRQ_GPIO_START                  128
-#define IRQ_GPIO_NUM                    192
+#define MMP_NR_BUILTIN_GPIO             192
-#define IRQ_GPIO(x)                     (IRQ_GPIO_START + (x))
+#define MMP_GPIO_TO_IRQ(gpio)           (IRQ_GPIO_START + (gpio))
-#define IRQ_BOARD_START                 (IRQ_GPIO_START + IRQ_GPIO_NUM)
+#define IRQ_BOARD_START                 (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO)
 #define NR_IRQS                         (IRQ_BOARD_START)
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index 2f7b2d3c2b1..cba22fed226 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -32,6 +32,8 @@ extern struct pxa_device_desc mmp2_device_sdh3;
 extern struct pxa_device_desc mmp2_device_asram;
 extern struct pxa_device_desc mmp2_device_isram;
+extern struct platform_device mmp2_device_gpio;
 static inline int mmp2_add_uart(int id)
 {
        struct pxa_device_desc *d = NULL;
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 7fb568d2845..dc03d580a06 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -5,6 +5,7 @@ struct sys_timer;
 extern struct sys_timer pxa168_timer;
 extern void __init pxa168_init_irq(void);
+extern void pxa168_restart(char, const char *);
 extern void pxa168_clear_keypad_wakeup(void);
 #include <linux/i2c.h>
@@ -42,6 +43,8 @@ struct pxa168_usb_pdata {
 /* pdata can be NULL */
 int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata);
+extern struct platform_device pxa168_device_gpio;
 static inline int pxa168_add_uart(int id)
 {
        struct pxa_device_desc *d = NULL;
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index 91be7559139..4de13abef7b 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -21,6 +21,8 @@ extern struct pxa_device_desc pxa910_device_pwm3;
 extern struct pxa_device_desc pxa910_device_pwm4;
 extern struct pxa_device_desc pxa910_device_nand;
+extern struct platform_device pxa910_device_gpio;
 static inline int pxa910_add_uart(int id)
 {
        struct pxa_device_desc *d = NULL;
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h
index 1a8a25edb1b..1d001eab81e 100644
--- a/arch/arm/mach-mmp/include/mach/system.h
+++ b/arch/arm/mach-mmp/include/mach/system.h
@@ -9,18 +9,8 @@
 #ifndef __ASM_MACH_SYSTEM_H
 #define __ASM_MACH_SYSTEM_H
-#include <mach/cputype.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        if (cpu_is_pxa168())
-                cpu_reset(0xffff0000);
-        else
-                cpu_reset(0);
-}
 #endif /* __ASM_MACH_SYSTEM_H */
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h
deleted file mode 100644
index 1d0bac003ad..00000000000
--- a/arch/arm/mach-mmp/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 8bfac661262..96cf5c8fe47 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -175,4 +175,5 @@ MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
        .init_irq       = mmp2_init_irq,
        .timer          = &mmp2_timer,
        .init_machine   = jasper_init,
+        .restart        = mmp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index 5dd1d4a6aeb..617c60a170a 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -13,6 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <asm/hardware/cache-tauros2.h>
@@ -24,7 +25,6 @@
 #include <mach/irqs.h>
 #include <mach/dma.h>
 #include <mach/mfp.h>
-#include <mach/gpio-pxa.h>
 #include <mach/devices.h>
 #include <mach/mmp2.h>
@@ -33,8 +33,6 @@
 #define MFPR_VIRT_BASE  (APB_VIRT_BASE + 0x1e000)
-#define APMASK(i)       (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c)
 static struct mfp_addr_map mmp2_addr_map[] __initdata = {
        MFP_ADDR_X(GPIO0, GPIO58, 0x54),
@@ -95,24 +93,9 @@ void mmp2_clear_pmic_int(void)
        __raw_writel(data, mfpr_pmic);
 }
-static void __init mmp2_init_gpio(void)
-{
-        int i;
-        /* enable GPIO clock */
-        __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_MMP2_GPIO);
-        /* unmask GPIO edge detection for all 6 banks -- APMASKx */
-        for (i = 0; i < 6; i++)
-                __raw_writel(0xffffffff, APMASK(i));
-        pxa_init_gpio(IRQ_MMP2_GPIO, 0, 167, NULL);
-}
 void __init mmp2_init_irq(void)
 {
        mmp2_init_icu();
-        mmp2_init_gpio();
 }
 static void sdhc_clk_enable(struct clk *clk)
@@ -149,6 +132,7 @@ static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
 static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
 static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
 static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
+static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
 static APMU_CLK(nand, NAND, 0xbf, 100000000);
 static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
@@ -168,6 +152,7 @@ static struct clk_lookup mmp2_clkregs[] = {
        INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
        INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
        INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
        INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
        INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
@@ -230,3 +215,21 @@ MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000);
 /* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */
 MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000);
+struct resource mmp2_resource_gpio[] = {
+        {
+                .start  = 0xd4019000,
+                .end    = 0xd4019fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_MMP2_GPIO,
+                .end    = IRQ_MMP2_GPIO,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mmp2_device_gpio = {
+        .name           = "pxa-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mmp2_resource_gpio),
+        .resource       = mmp2_resource_gpio,
+};
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 76ca15c00e4..7bc17eaa12e 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -13,6 +13,7 @@
 #include <linux/list.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/platform_device.h>
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
@@ -20,7 +21,6 @@
 #include <mach/regs-apbc.h>
 #include <mach/regs-apmu.h>
 #include <mach/irqs.h>
-#include <mach/gpio-pxa.h>
 #include <mach/dma.h>
 #include <mach/devices.h>
 #include <mach/mfp.h>
@@ -43,26 +43,9 @@ static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata =
        MFP_ADDR_END,
 };
-#define APMASK(i)       (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
-static void __init pxa168_init_gpio(void)
-{
-        int i;
-        /* enable GPIO clock */
-        __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO);
-        /* unmask GPIO edge detection for all 4 banks - APMASKx */
-        for (i = 0; i < 4; i++)
-                __raw_writel(0xffffffff, APMASK(i));
-        pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL);
-}
 void __init pxa168_init_irq(void)
 {
        icu_init_irq();
-        pxa168_init_gpio();
 }
 /* APB peripheral clocks */
@@ -80,6 +63,7 @@ static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
 static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
 static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
+static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
 static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
@@ -105,6 +89,7 @@ static struct clk_lookup pxa168_clkregs[] = {
        INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
        INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
        INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
        INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
        INIT_CLKREG(&clk_usb, "pxa168-ehci", "PXA168-USBCLK"),
@@ -174,6 +159,25 @@ PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
 PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
 PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff);
+struct resource pxa168_resource_gpio[] = {
+        {
+                .start  = 0xd4019000,
+                .end    = 0xd4019fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PXA168_GPIOX,
+                .end    = IRQ_PXA168_GPIOX,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device pxa168_device_gpio = {
+        .name           = "pxa-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa168_resource_gpio),
+        .resource       = pxa168_resource_gpio,
+};
 struct resource pxa168_usb_host_resources[] = {
        /* USB Host conroller register base */
        [0] = {
@@ -214,3 +218,8 @@ int __init pxa168_add_usb_host(struct pxa168_usb_pdata *pdata)
        pxa168_device_usb_host.dev.platform_data = pdata;
        return platform_device_register(&pxa168_device_usb_host);
 }
+void pxa168_restart(char mode, const char *cmd)
+{
+        soft_restart(0xffff0000);
+}
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 4ebbfbba39f..3241a25784d 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <asm/mach/time.h>
 #include <mach/addr-map.h>
@@ -19,7 +20,6 @@
 #include <mach/regs-apmu.h>
 #include <mach/cputype.h>
 #include <mach/irqs.h>
-#include <mach/gpio-pxa.h>
 #include <mach/dma.h>
 #include <mach/mfp.h>
 #include <mach/devices.h>
@@ -77,26 +77,9 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
        MFP_ADDR_END,
 };
-#define APMASK(i)       (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c)
-static void __init pxa910_init_gpio(void)
-{
-        int i;
-        /* enable GPIO clock */
-        __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO);
-        /* unmask GPIO edge detection for all 4 banks - APMASKx */
-        for (i = 0; i < 4; i++)
-                __raw_writel(0xffffffff, APMASK(i));
-        pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL);
-}
 void __init pxa910_init_irq(void)
 {
        icu_init_irq();
-        pxa910_init_gpio();
 }
 /* APB peripheral clocks */
@@ -108,6 +91,7 @@ static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000);
 static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
+static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
 static APMU_CLK(nand, NAND, 0x19b, 156000000);
 static APMU_CLK(u2o, USB, 0x1b, 480000000);
@@ -123,6 +107,7 @@ static struct clk_lookup pxa910_clkregs[] = {
        INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
        INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
        INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
 };
@@ -179,3 +164,22 @@ PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10);
 PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10);
 PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10);
 PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99);
+struct resource pxa910_resource_gpio[] = {
+        {
+                .start  = 0xd4019000,
+                .end    = 0xd4019fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PXA910_AP_GPIO,
+                .end    = IRQ_PXA910_AP_GPIO,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device pxa910_device_gpio = {
+        .name           = "pxa-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa910_resource_gpio),
+        .resource       = pxa910_resource_gpio,
+};
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c
index eb5be879fd8..8e3b5af04a5 100644
--- a/arch/arm/mach-mmp/tavorevb.c
+++ b/arch/arm/mach-mmp/tavorevb.c
@@ -19,6 +19,7 @@
 #include <mach/addr-map.h>
 #include <mach/mfp-pxa910.h>
 #include <mach/pxa910.h>
+#include <mach/irqs.h>
 #include "common.h"
@@ -71,8 +72,8 @@ static struct resource smc91x_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = gpio_to_irq(80),
+                .start  = MMP_GPIO_TO_IRQ(80),
-                .end    = gpio_to_irq(80),
+                .end    = MMP_GPIO_TO_IRQ(80),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        }
 };
@@ -93,6 +94,7 @@ static void __init tavorevb_init(void)
        /* on-chip devices */
        pxa910_add_uart(1);
+        platform_device_register(&pxa910_device_gpio);
        /* off-chip devices */
        platform_device_register(&smc91x_device);
@@ -103,4 +105,5 @@ MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)")
        .init_irq       = pxa910_init_irq,
        .timer          = &pxa910_timer,
        .init_machine   = tavorevb_init,
+        .restart        = mmp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c
index bbe4727b96c..0523e422990 100644
--- a/arch/arm/mach-mmp/teton_bga.c
+++ b/arch/arm/mach-mmp/teton_bga.c
@@ -66,7 +66,7 @@ static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
 static struct i2c_board_info teton_bga_i2c_info[] __initdata = {
        {
                I2C_BOARD_INFO("ds1337", 0x68),
-                .irq = gpio_to_irq(RTC_INT_GPIO)
+                .irq = MMP_GPIO_TO_IRQ(RTC_INT_GPIO)
        },
 };
@@ -78,6 +78,7 @@ static void __init teton_bga_init(void)
        pxa168_add_uart(1);
        pxa168_add_keypad(&teton_bga_keypad_info);
        pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
+        platform_device_register(&pxa168_device_gpio);
 }
 MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
@@ -86,4 +87,5 @@ MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
        .init_irq       = pxa168_init_irq,
        .timer          = &pxa168_timer,
        .init_machine   = teton_bga_init,
+        .restart        = pxa168_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 4e91ee6e27c..71fc4ee4602 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -25,7 +25,6 @@
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/sched.h>
 #include <asm/sched_clock.h>
 #include <mach/addr-map.h>
@@ -42,8 +41,6 @@
 #define MAX_DELTA               (0xfffffffe)
 #define MIN_DELTA               (16)
-static DEFINE_CLOCK_DATA(cd);
 /*
 * FIXME: the timer needs some delay to stablize the counter capture
 */
@@ -59,16 +56,9 @@ static inline uint32_t timer_read(void)
        return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
 }
-unsigned long long notrace sched_clock(void)
+static u32 notrace mmp_read_sched_clock(void)
 {
-        u32 cyc = timer_read();
+        return timer_read();
-        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-static void notrace mmp_update_sched_clock(void)
-{
-        u32 cyc = timer_read();
-        update_sched_clock(&cd, cyc, (u32)~0);
 }
 static irqreturn_t timer_interrupt(int irq, void *dev_id)
@@ -201,7 +191,7 @@ void __init timer_init(int irq)
 {
        timer_config();
-        init_sched_clock(&cd, mmp_update_sched_clock, 32, CLOCK_TICK_RATE);
+        setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
        ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
        ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 176515a7698..5ac5d5832e4 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -24,12 +24,13 @@
 #include <mach/addr-map.h>
 #include <mach/mfp-pxa910.h>
 #include <mach/pxa910.h>
+#include <mach/irqs.h>
 #include "common.h"
-#define TTCDKB_GPIO_EXT0(x)     (NR_BUILTIN_GPIO + ((x < 0) ? 0 :       \
+#define TTCDKB_GPIO_EXT0(x)     (MMP_NR_BUILTIN_GPIO + ((x < 0) ? 0 :   \
                                ((x < 16) ? x : 15)))
-#define TTCDKB_GPIO_EXT1(x)     (NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 :  \
+#define TTCDKB_GPIO_EXT1(x)     (MMP_NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \
                                ((x < 16) ? x : 15)))
 /*
@@ -122,6 +123,7 @@ static struct platform_device ttc_dkb_device_onenand = {
 };
 static struct platform_device *ttc_dkb_devices[] = {
+        &pxa910_device_gpio,
        &ttc_dkb_device_onenand,
 };
@@ -136,7 +138,7 @@ static struct i2c_board_info ttc_dkb_i2c_info[] = {
        {
                .type           = "max7312",
                .addr           = 0x23,
-                .irq            = IRQ_GPIO(80),
+                .irq            = MMP_GPIO_TO_IRQ(80),
                .platform_data  = &max7312_data,
        },
 };
@@ -159,4 +161,5 @@ MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
        .init_irq       = pxa910_init_irq,
        .timer          = &pxa910_timer,
        .init_machine   = ttc_dkb_init,
+        .restart        = mmp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index ebde97f5d5f..1cd40ad301d 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -13,7 +13,6 @@ config ARCH_MSM7X00A
        select CPU_V6
        select GPIO_MSM_V1
        select MSM_PROC_COMM
-        select HAS_MSM_DEBUG_UART_PHYS
 config ARCH_MSM7X30
        bool "MSM7x30"
@@ -25,7 +24,6 @@ config ARCH_MSM7X30
        select MSM_GPIOMUX
        select GPIO_MSM_V1
        select MSM_PROC_COMM
-        select HAS_MSM_DEBUG_UART_PHYS
 config ARCH_QSD8X50
        bool "QSD8X50"
@@ -37,7 +35,6 @@ config ARCH_QSD8X50
        select MSM_GPIOMUX
        select GPIO_MSM_V1
        select MSM_PROC_COMM
-        select HAS_MSM_DEBUG_UART_PHYS
 config ARCH_MSM8X60
        bool "MSM8X60"
@@ -63,19 +60,20 @@ config ARCH_MSM8960
 endchoice
+config MSM_HAS_DEBUG_UART_HS
+        bool
 config MSM_SOC_REV_A
        bool
 config  ARCH_MSM_SCORPIONMP
        bool
+        select HAVE_SMP
 config  ARCH_MSM_ARM11
        bool
 config  ARCH_MSM_SCORPION
        bool
-config HAS_MSM_DEBUG_UART_PHYS
-        bool
 config  MSM_VIC
        bool
@@ -152,32 +150,6 @@ config MACH_MSM8960_RUMI3
 endmenu
-config MSM_DEBUG_UART
-        int
-        default 1 if MSM_DEBUG_UART1
-        default 2 if MSM_DEBUG_UART2
-        default 3 if MSM_DEBUG_UART3
-if HAS_MSM_DEBUG_UART_PHYS
-choice
-        prompt "Debug UART"
-        default MSM_DEBUG_UART_NONE
-        config MSM_DEBUG_UART_NONE
-                bool "None"
-        config MSM_DEBUG_UART1
-                bool "UART1"
-        config MSM_DEBUG_UART2
-                bool "UART2"
-        config MSM_DEBUG_UART3
-                bool "UART3"
-endchoice
-endif
 config MSM_SMD_PKG3
        bool
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 6dc1cbd2a59..ed359812853 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -99,6 +99,7 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
        .map_io = msm8960_map_io,
        .init_irq = msm8960_init_irq,
        .timer = &msm_timer,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8960_sim_init,
 MACHINE_END
@@ -108,6 +109,7 @@ MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
        .map_io = msm8960_map_io,
        .init_irq = msm8960_init_irq,
        .timer = &msm_timer,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8960_rumi3_init,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 44bf7168837..0a113424632 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -108,6 +108,7 @@ MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
        .reserve = msm8x60_reserve,
        .map_io = msm8x60_map_io,
        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8x60_init,
        .timer = &msm_timer,
 MACHINE_END
@@ -117,6 +118,7 @@ MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
        .reserve = msm8x60_reserve,
        .map_io = msm8x60_map_io,
        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8x60_init,
        .timer = &msm_timer,
 MACHINE_END
@@ -126,6 +128,7 @@ MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
        .reserve = msm8x60_reserve,
        .map_io = msm8x60_map_io,
        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8x60_init,
        .timer = &msm_timer,
 MACHINE_END
@@ -135,6 +138,7 @@ MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
        .reserve = msm8x60_reserve,
        .map_io = msm8x60_map_io,
        .init_irq = msm8x60_init_irq,
+        .handle_irq = gic_handle_irq,
        .init_machine = msm8x60_init,
        .timer = &msm_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 32b465763db..97b8191d9d3 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -18,7 +18,7 @@
 #include <linux/input.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/delay.h>
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
index 0c631a9f864..bcd5af223de 100644
--- a/arch/arm/mach-msm/headsmp.S
+++ b/arch/arm/mach-msm/headsmp.S
@@ -34,6 +34,7 @@ pen:	ldr	r7, [r6]
         * should now contain the SVC stack for this core
         */
        b       secondary_startup
+ENDPROC(msm_secondary_startup)
        .align
 1:      .long   .
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 2dc73ccddb1..3ffd8668c9a 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -1,6 +1,7 @@
-/* arch/arm/mach-msm7200/include/mach/debug-macro.S
+/*
 *
 * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
 * Author: Brian Swetland <swetland@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
@@ -14,40 +15,52 @@
 *
 */
 #include <mach/hardware.h>
 #include <mach/msm_iomap.h>
-#if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE)
        .macro  addruart, rp, rv, tmp
+#ifdef MSM_DEBUG_UART_PHYS
        ldr     \rp, =MSM_DEBUG_UART_PHYS
        ldr     \rv, =MSM_DEBUG_UART_BASE
+#endif
        .endm
-        .macro  senduart,rd,rx
+        .macro  senduart, rd, rx
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+        @ Write the 1 character to UARTDM_TF
+        str     \rd, [\rx, #0x70]
+#else
        teq     \rx, #0
        strne   \rd, [\rx, #0x0C]
+#endif
        .endm
-        .macro  waituart,rd,rx
+        .macro  waituart, rd, rx
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+        @ check for TX_EMT in UARTDM_SR
+        ldr     \rd, [\rx, #0x08]
+        tst     \rd, #0x08
+        bne     1002f
+        @ wait for TXREADY in UARTDM_ISR
+1001:   ldr     \rd, [\rx, #0x14]
+        tst     \rd, #0x80
+        beq     1001b
+1002:
+        @ Clear TX_READY by writing to the UARTDM_CR register
+        mov     \rd, #0x300
+        str     \rd, [\rx, #0x10]
+        @ Write 0x1 to NCF register
+        mov     \rd, #0x1
+        str     \rd, [\rx, #0x40]
+        @ UARTDM reg. Read to induce delay
+        ldr     \rd, [\rx, #0x08]
+#else
        @ wait for TX_READY
 1001:   ldr     \rd, [\rx, #0x08]
        tst     \rd, #0x04
        beq     1001b
-        .endm
-#else
-        .macro  addruart, rp, rv, tmp
-        mov     \rv, #0xff000000
-        orr     \rv, \rv, #0x00f00000
-        .endm
-        .macro  senduart,rd,rx
-        .endm
-        .macro  waituart,rd,rx
-        .endm
 #endif
+        .endm
-        .macro  busyuart,rd,rx
+        .macro  busyuart, rd, rx
        .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
deleted file mode 100644
index 717076f3ca7..00000000000
--- a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Low-level IRQ helper macros
- *
- * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/hardware/entry-macro-gic.S>
-        .macro  disable_fiq
-        .endm
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-vic.S b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
deleted file mode 100644
index 70563ed11b3..00000000000
--- a/arch/arm/mach-msm/include/mach/entry-macro-vic.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#include <mach/msm_iomap.h>
-        .macro  disable_fiq
-        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        @ enable imprecise aborts
-        cpsie   a
-        mov     \base, #MSM_VIC_BASE
-        .endm
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ 0xD0 has irq# or old irq# if the irq has been handled
-        @ 0xD4 has irq# or -1 if none pending *but* if you just
-        @ read 0xD4 you never get the first irq for some reason
-        ldr     \irqnr, [\base, #0xD0]
-        ldr     \irqnr, [\base, #0xD4]
-        cmp     \irqnr, #0xffffffff
-        .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
index b16f082eeb6..41f7003ef34 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -16,8 +16,27 @@
 *
 */
-#if defined(CONFIG_ARM_GIC)
+        .macro  disable_fiq
-#include <mach/entry-macro-qgic.S>
+        .endm
-#else
-#include <mach/entry-macro-vic.S>
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+#if !defined(CONFIG_ARM_GIC)
+#include <mach/msm_iomap.h>
+        .macro  get_irqnr_preamble, base, tmp
+        @ enable imprecise aborts
+        cpsie   a
+        mov     \base, #MSM_VIC_BASE
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ 0xD0 has irq# or old irq# if the irq has been handled
+        @ 0xD4 has irq# or -1 if none pending *but* if you just
+        @ read 0xD4 you never get the first irq for some reason
+        ldr     \irqnr, [\base, #0xD0]
+        ldr     \irqnr, [\base, #0xD4]
+        cmp     \irqnr, #0xffffffff
+        .endm
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
index 94fe9fe6feb..8af46123dab 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x00.h
@@ -78,18 +78,6 @@
 #define MSM_UART3_PHYS        0xA9C00000
 #define MSM_UART3_SIZE        SZ_4K
-#ifdef CONFIG_MSM_DEBUG_UART
-#define MSM_DEBUG_UART_BASE   0xE1000000
-#if CONFIG_MSM_DEBUG_UART == 1
-#define MSM_DEBUG_UART_PHYS   MSM_UART1_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 2
-#define MSM_DEBUG_UART_PHYS   MSM_UART2_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 3
-#define MSM_DEBUG_UART_PHYS   MSM_UART3_PHYS
-#endif
-#define MSM_DEBUG_UART_SIZE   SZ_4K
-#endif
 #define MSM_SDC1_PHYS         0xA0400000
 #define MSM_SDC1_SIZE         SZ_4K
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
index 37694442d1b..198202c267c 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-7x30.h
@@ -89,18 +89,6 @@
 #define MSM_UART3_PHYS        0xACC00000
 #define MSM_UART3_SIZE        SZ_4K
-#ifdef CONFIG_MSM_DEBUG_UART
-#define MSM_DEBUG_UART_BASE   0xE1000000
-#if CONFIG_MSM_DEBUG_UART == 1
-#define MSM_DEBUG_UART_PHYS   MSM_UART1_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 2
-#define MSM_DEBUG_UART_PHYS   MSM_UART2_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 3
-#define MSM_DEBUG_UART_PHYS   MSM_UART3_PHYS
-#endif
-#define MSM_DEBUG_UART_SIZE   SZ_4K
-#endif
 #define MSM_MDC_BASE          IOMEM(0xE0200000)
 #define MSM_MDC_PHYS          0xAA500000
 #define MSM_MDC_SIZE          SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
index 3c9d9602a31..800b55767e6 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
@@ -45,4 +45,9 @@
 #define MSM8960_TMR0_PHYS       0x0208A000
 #define MSM8960_TMR0_SIZE       SZ_4K
+#ifdef CONFIG_DEBUG_MSM8960_UART
+#define MSM_DEBUG_UART_BASE     0xE1040000
+#define MSM_DEBUG_UART_PHYS     0x16440000
+#endif
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index d67cd73316f..0faa894729b 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -83,18 +83,6 @@
 #define MSM_UART3_PHYS        0xA9C00000
 #define MSM_UART3_SIZE        SZ_4K
-#ifdef CONFIG_MSM_DEBUG_UART
-#define MSM_DEBUG_UART_BASE   0xE1000000
-#if CONFIG_MSM_DEBUG_UART == 1
-#define MSM_DEBUG_UART_PHYS   MSM_UART1_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 2
-#define MSM_DEBUG_UART_PHYS   MSM_UART2_PHYS
-#elif CONFIG_MSM_DEBUG_UART == 3
-#define MSM_DEBUG_UART_PHYS   MSM_UART3_PHYS
-#endif
-#define MSM_DEBUG_UART_SIZE   SZ_4K
-#endif
 #define MSM_MDC_BASE          IOMEM(0xE0200000)
 #define MSM_MDC_PHYS          0xAA500000
 #define MSM_MDC_SIZE          SZ_1M
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
index 3b19b8f244b..54e12caa8d8 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
@@ -62,4 +62,9 @@
 #define MSM8X60_TMR0_PHYS       0x02040000
 #define MSM8X60_TMR0_SIZE       SZ_4K
+#ifdef CONFIG_DEBUG_MSM8660_UART
+#define MSM_DEBUG_UART_BASE     0xE1040000
+#define MSM_DEBUG_UART_PHYS     0x19C40000
+#endif
 #endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index 4ded15238b6..90682f4599d 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -55,6 +55,18 @@
 #include "msm_iomap-8960.h"
+#define MSM_DEBUG_UART_SIZE     SZ_4K
+#if defined(CONFIG_DEBUG_MSM_UART1)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART1_PHYS
+#elif defined(CONFIG_DEBUG_MSM_UART2)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART2_PHYS
+#elif defined(CONFIG_DEBUG_MSM_UART3)
+#define MSM_DEBUG_UART_BASE     0xE1000000
+#define MSM_DEBUG_UART_PHYS     MSM_UART3_PHYS
+#endif
 /* Virtual addresses shared across all MSM targets. */
 #define MSM_CSR_BASE            IOMEM(0xE0001000)
 #define MSM_QGIC_DIST_BASE      IOMEM(0xF0000000)
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
index d2e83f42ba1..311db2b35da 100644
--- a/arch/arm/mach-msm/include/mach/system.h
+++ b/arch/arm/mach-msm/include/mach/system.h
@@ -12,16 +12,8 @@
 * GNU General Public License for more details.
 *
 */
-#include <mach/hardware.h>
 void arch_idle(void);
-static inline void arch_reset(char mode, const char *cmd)
-{
-        for (;;) ;  /* depends on IPC w/ other core */
-}
 /* low level hardware reset hook -- for example, hitting the
 * PSHOLD line on the PMIC to hard reset the system
 */
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
index d94292c29d8..169a8400745 100644
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ b/arch/arm/mach-msm/include/mach/uncompress.h
@@ -1,6 +1,6 @@
-/* arch/arm/mach-msm/include/mach/uncompress.h
+/*
- *
 * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -14,17 +14,40 @@
 */
 #ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
+#define __ASM_ARCH_MSM_UNCOMPRESS_H
+#include <asm/processor.h>
+#include <mach/msm_iomap.h>
+#define UART_CSR      (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))
+#define UART_TF       (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c))
-#include "hardware.h"
+#define UART_DM_SR    (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)))
-#include "linux/io.h"
+#define UART_DM_CR    (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10)))
-#include "mach/msm_iomap.h"
+#define UART_DM_ISR   (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14)))
+#define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40)))
+#define UART_DM_TF    (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70)))
 static void putc(int c)
 {
 #if defined(MSM_DEBUG_UART_PHYS)
-        unsigned base = MSM_DEBUG_UART_PHYS;
+#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
-        while (!(readl(base + 0x08) & 0x04)) ;
+        /*
-        writel(c, base + 0x0c);
+         * Wait for TX_READY to be set; but skip it if we have a
+         * TX underrun.
+         */
+        if (UART_DM_SR & 0x08)
+                while (!(UART_DM_ISR & 0x80))
+                        cpu_relax();
+        UART_DM_CR = 0x300;
+        UART_DM_NCHAR = 0x1;
+        UART_DM_TF = c;
+#else
+        while (!(UART_CSR & 0x04))
+                cpu_relax();
+        UART_TF = c;
+#endif
 #endif
 }
diff --git a/arch/arm/mach-msm/include/mach/vmalloc.h b/arch/arm/mach-msm/include/mach/vmalloc.h
deleted file mode 100644
index d138448eff1..00000000000
--- a/arch/arm/mach-msm/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* arch/arm/mach-msm/include/mach/vmalloc.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_MSM_VMALLOC_H
-#define __ASM_ARCH_MSM_VMALLOC_H
-#define VMALLOC_END       0xd0000000UL
-#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 8759ecf7454..578b04e42de 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -47,7 +47,8 @@ static struct map_desc msm_io_desc[] __initdata = {
        MSM_CHIP_DEVICE(GPIO1, MSM7X00),
        MSM_CHIP_DEVICE(GPIO2, MSM7X00),
        MSM_DEVICE(CLK_CTL),
-#ifdef CONFIG_MSM_DEBUG_UART
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+        defined(CONFIG_DEBUG_MSM_UART3)
        MSM_DEVICE(DEBUG_UART),
 #endif
 #ifdef CONFIG_ARCH_MSM7X30
@@ -84,7 +85,8 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
        MSM_DEVICE(SCPLL),
        MSM_DEVICE(AD5),
        MSM_DEVICE(MDC),
-#ifdef CONFIG_MSM_DEBUG_UART
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+        defined(CONFIG_DEBUG_MSM_UART3)
        MSM_DEVICE(DEBUG_UART),
 #endif
        {
@@ -109,6 +111,9 @@ static struct map_desc msm8x60_io_desc[] __initdata = {
        MSM_CHIP_DEVICE(TMR0, MSM8X60),
        MSM_DEVICE(ACC),
        MSM_DEVICE(GCC),
+#ifdef CONFIG_DEBUG_MSM8660_UART
+        MSM_DEVICE(DEBUG_UART),
+#endif
 };
 void __init msm_map_msm8x60_io(void)
@@ -123,6 +128,9 @@ static struct map_desc msm8960_io_desc[] __initdata = {
        MSM_CHIP_DEVICE(QGIC_CPU, MSM8960),
        MSM_CHIP_DEVICE(TMR, MSM8960),
        MSM_CHIP_DEVICE(TMR0, MSM8960),
+#ifdef CONFIG_DEBUG_MSM8960_UART
+        MSM_DEVICE(DEBUG_UART),
+#endif
 };
 void __init msm_map_msm8960_io(void)
@@ -146,7 +154,8 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
        MSM_DEVICE(SAW),
        MSM_DEVICE(GCC),
        MSM_DEVICE(TCSR),
-#ifdef CONFIG_MSM_DEBUG_UART
+#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
+        defined(CONFIG_DEBUG_MSM_UART3)
        MSM_DEVICE(DEBUG_UART),
 #endif
        {
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index fdec58aaa35..0b3e357c4c8 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -79,7 +79,7 @@ static __cpuinit void prepare_cold_cpu(unsigned int cpu)
        ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
                                SCM_FLAG_COLDBOOT_CPU1);
        if (ret == 0) {
-                void *sc1_base_ptr;
+                void __iomem *sc1_base_ptr;
                sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
                if (sc1_base_ptr) {
                        writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
diff --git a/arch/arm/mach-msm/smd_debug.c b/arch/arm/mach-msm/smd_debug.c
index 8736afff82f..0c56a5aaf58 100644
--- a/arch/arm/mach-msm/smd_debug.c
+++ b/arch/arm/mach-msm/smd_debug.c
@@ -215,7 +215,7 @@ static const struct file_operations debug_ops = {
        .llseek = default_llseek,
 };
-static void debug_create(const char *name, mode_t mode,
+static void debug_create(const char *name, umode_t mode,
                         struct dentry *dent,
                         int (*fill)(char *buf, int max))
 {
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index afeeca52fc6..11d0d8f2656 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -1,6 +1,7 @@
-/* linux/arch/arm/mach-msm/timer.c
+/*
 *
 * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -13,306 +14,207 @@
 *
 */
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <linux/init.h>
-#include <linux/time.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/delay.h>
 #include <linux/io.h>
 #include <asm/mach/time.h>
 #include <asm/hardware/gic.h>
+#include <asm/localtimer.h>
 #include <mach/msm_iomap.h>
 #include <mach/cpu.h>
+#include <mach/board.h>
 #define TIMER_MATCH_VAL         0x0000
 #define TIMER_COUNT_VAL         0x0004
 #define TIMER_ENABLE            0x0008
-#define TIMER_ENABLE_CLR_ON_MATCH_EN    2
+#define TIMER_ENABLE_CLR_ON_MATCH_EN    BIT(1)
-#define TIMER_ENABLE_EN                 1
+#define TIMER_ENABLE_EN                 BIT(0)
 #define TIMER_CLEAR             0x000C
 #define DGT_CLK_CTL             0x0034
-enum {
+#define DGT_CLK_CTL_DIV_4       0x3
-        DGT_CLK_CTL_DIV_1 = 0,
-        DGT_CLK_CTL_DIV_2 = 1,
-        DGT_CLK_CTL_DIV_3 = 2,
-        DGT_CLK_CTL_DIV_4 = 3,
-};
-#define CSR_PROTECTION          0x0020
-#define CSR_PROTECTION_EN               1
 #define GPT_HZ 32768
-enum timer_location {
+#define MSM_DGT_SHIFT 5
-        LOCAL_TIMER = 0,
-        GLOBAL_TIMER = 1,
-};
-#define MSM_GLOBAL_TIMER MSM_CLOCK_DGT
-/* TODO: Remove these ifdefs */
-#if defined(CONFIG_ARCH_QSD8X50)
-#define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */
-#define MSM_DGT_SHIFT (0)
-#elif defined(CONFIG_ARCH_MSM7X30)
-#define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */
-#define MSM_DGT_SHIFT (0)
-#elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
-#define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */
-#define MSM_DGT_SHIFT (0)
-#else
-#define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */
-#define MSM_DGT_SHIFT (5)
-#endif
-struct msm_clock {
+static void __iomem *event_base;
-        struct clock_event_device   clockevent;
-        struct clocksource          clocksource;
-        unsigned int                irq;
-        void __iomem                *regbase;
-        uint32_t                    freq;
-        uint32_t                    shift;
-        void __iomem                *global_counter;
-        void __iomem                *local_counter;
-        union {
-                struct clock_event_device               *evt;
-                struct clock_event_device __percpu      **percpu_evt;
-        };              
-};
-enum {
-        MSM_CLOCK_GPT,
-        MSM_CLOCK_DGT,
-        NR_TIMERS,
-};
-static struct msm_clock msm_clocks[];
 static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
 {
        struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
-        if (evt->event_handler == NULL)
+        /* Stop the timer tick */
-                return IRQ_HANDLED;
+        if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
+                u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
+                ctrl &= ~TIMER_ENABLE_EN;
+                writel_relaxed(ctrl, event_base + TIMER_ENABLE);
+        }
        evt->event_handler(evt);
        return IRQ_HANDLED;
 }
-static cycle_t msm_read_timer_count(struct clocksource *cs)
-{
-        struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource);
-        /*
-         * Shift timer count down by a constant due to unreliable lower bits
-         * on some targets.
-         */
-        return readl(clk->global_counter) >> clk->shift;
-}
-static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt)
-{
-#ifdef CONFIG_SMP
-        int i;
-        for (i = 0; i < NR_TIMERS; i++)
-                if (evt == &(msm_clocks[i].clockevent))
-                        return &msm_clocks[i];
-        return &msm_clocks[MSM_GLOBAL_TIMER];
-#else
-        return container_of(evt, struct msm_clock, clockevent);
-#endif
-}
 static int msm_timer_set_next_event(unsigned long cycles,
                                    struct clock_event_device *evt)
 {
-        struct msm_clock *clock = clockevent_to_clock(evt);
+        u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
-        uint32_t now = readl(clock->local_counter);
-        uint32_t alarm = now + (cycles << clock->shift);
-        writel(alarm, clock->regbase + TIMER_MATCH_VAL);
+        writel_relaxed(0, event_base + TIMER_CLEAR);
+        writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
+        writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
        return 0;
 }
 static void msm_timer_set_mode(enum clock_event_mode mode,
                              struct clock_event_device *evt)
 {
-        struct msm_clock *clock = clockevent_to_clock(evt);
+        u32 ctrl;
+        ctrl = readl_relaxed(event_base + TIMER_ENABLE);
+        ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
        switch (mode) {
        case CLOCK_EVT_MODE_RESUME:
        case CLOCK_EVT_MODE_PERIODIC:
                break;
        case CLOCK_EVT_MODE_ONESHOT:
-                writel(TIMER_ENABLE_EN, clock->regbase + TIMER_ENABLE);
+                /* Timer is enabled in set_next_event */
                break;
        case CLOCK_EVT_MODE_UNUSED:
        case CLOCK_EVT_MODE_SHUTDOWN:
-                writel(0, clock->regbase + TIMER_ENABLE);
                break;
        }
+        writel_relaxed(ctrl, event_base + TIMER_ENABLE);
 }
-static struct msm_clock msm_clocks[] = {
+static struct clock_event_device msm_clockevent = {
-        [MSM_CLOCK_GPT] = {
+        .name           = "gp_timer",
-                .clockevent = {
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
-                        .name           = "gp_timer",
+        .rating         = 200,
-                        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .set_next_event = msm_timer_set_next_event,
-                        .shift          = 32,
+        .set_mode       = msm_timer_set_mode,
-                        .rating         = 200,
+};
-                        .set_next_event = msm_timer_set_next_event,
-                        .set_mode       = msm_timer_set_mode,
+static union {
-                },
+        struct clock_event_device *evt;
-                .clocksource = {
+        struct clock_event_device __percpu **percpu_evt;
-                        .name           = "gp_timer",
+} msm_evt;
-                        .rating         = 200,
-                        .read           = msm_read_timer_count,
+static void __iomem *source_base;
-                        .mask           = CLOCKSOURCE_MASK(32),
-                        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+static cycle_t msm_read_timer_count(struct clocksource *cs)
-                },
+{
-                .irq = INT_GP_TIMER_EXP,
+        return readl_relaxed(source_base + TIMER_COUNT_VAL);
-                .freq = GPT_HZ,
+}
-        },
-        [MSM_CLOCK_DGT] = {
+static cycle_t msm_read_timer_count_shift(struct clocksource *cs)
-                .clockevent = {
+{
-                        .name           = "dg_timer",
+        /*
-                        .features       = CLOCK_EVT_FEAT_ONESHOT,
+         * Shift timer count down by a constant due to unreliable lower bits
-                        .shift          = 32 + MSM_DGT_SHIFT,
+         * on some targets.
-                        .rating         = 300,
+         */
-                        .set_next_event = msm_timer_set_next_event,
+        return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
-                        .set_mode       = msm_timer_set_mode,
+}
-                },
-                .clocksource = {
+static struct clocksource msm_clocksource = {
-                        .name           = "dg_timer",
+        .name   = "dg_timer",
-                        .rating         = 300,
+        .rating = 300,
-                        .read           = msm_read_timer_count,
+        .read   = msm_read_timer_count,
-                        .mask           = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
+        .mask   = CLOCKSOURCE_MASK(32),
-                        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
-                },
-                .irq = INT_DEBUG_TIMER_EXP,
-                .freq = DGT_HZ >> MSM_DGT_SHIFT,
-                .shift = MSM_DGT_SHIFT,
-        }
 };
 static void __init msm_timer_init(void)
 {
-        int i;
+        struct clock_event_device *ce = &msm_clockevent;
+        struct clocksource *cs = &msm_clocksource;
        int res;
-        int global_offset = 0;
+        u32 dgt_hz;
        if (cpu_is_msm7x01()) {
-                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
+                event_base = MSM_CSR_BASE;
-                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
+                source_base = MSM_CSR_BASE + 0x10;
+                dgt_hz = 19200000 >> MSM_DGT_SHIFT; /* 600 KHz */
+                cs->read = msm_read_timer_count_shift;
+                cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
        } else if (cpu_is_msm7x30()) {
-                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE + 0x04;
+                event_base = MSM_CSR_BASE + 0x04;
-                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x24;
+                source_base = MSM_CSR_BASE + 0x24;
+                dgt_hz = 24576000 / 4;
        } else if (cpu_is_qsd8x50()) {
-                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_CSR_BASE;
+                event_base = MSM_CSR_BASE;
-                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_CSR_BASE + 0x10;
+                source_base = MSM_CSR_BASE + 0x10;
+                dgt_hz = 19200000 / 4;
        } else if (cpu_is_msm8x60() || cpu_is_msm8960()) {
-                msm_clocks[MSM_CLOCK_GPT].regbase = MSM_TMR_BASE + 0x04;
+                event_base = MSM_TMR_BASE + 0x04;
-                msm_clocks[MSM_CLOCK_DGT].regbase = MSM_TMR_BASE + 0x24;
+                /* Use CPU0's timer as the global clock source. */
+                source_base = MSM_TMR0_BASE + 0x24;
-                /* Use CPU0's timer as the global timer. */
+                dgt_hz = 27000000 / 4;
-                global_offset = MSM_TMR0_BASE - MSM_TMR_BASE;
+                writel_relaxed(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
        } else
                BUG();
-#ifdef CONFIG_ARCH_MSM_SCORPIONMP
+        writel_relaxed(0, event_base + TIMER_ENABLE);
-        writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
+        writel_relaxed(0, event_base + TIMER_CLEAR);
-#endif
+        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
+        ce->cpumask = cpumask_of(0);
-        for (i = 0; i < ARRAY_SIZE(msm_clocks); i++) {
-                struct msm_clock *clock = &msm_clocks[i];
+        ce->irq = INT_GP_TIMER_EXP;
-                struct clock_event_device *ce = &clock->clockevent;
+        clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff);
-                struct clocksource *cs = &clock->clocksource;
+        if (cpu_is_msm8x60() || cpu_is_msm8960()) {
+                msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *);
-                clock->local_counter = clock->regbase + TIMER_COUNT_VAL;
+                if (!msm_evt.percpu_evt) {
-                clock->global_counter = clock->local_counter + global_offset;
+                        pr_err("memory allocation failed for %s\n", ce->name);
+                        goto err;
-                writel(0, clock->regbase + TIMER_ENABLE);
-                writel(0, clock->regbase + TIMER_CLEAR);
-                writel(~0, clock->regbase + TIMER_MATCH_VAL);
-                ce->mult = div_sc(clock->freq, NSEC_PER_SEC, ce->shift);
-                /* allow at least 10 seconds to notice that the timer wrapped */
-                ce->max_delta_ns =
-                        clockevent_delta2ns(0xf0000000 >> clock->shift, ce);
-                /* 4 gets rounded down to 3 */
-                ce->min_delta_ns = clockevent_delta2ns(4, ce);
-                ce->cpumask = cpumask_of(0);
-                res = clocksource_register_hz(cs, clock->freq);
-                if (res)
-                        printk(KERN_ERR "msm_timer_init: clocksource_register "
-                               "failed for %s\n", cs->name);
-                ce->irq = clock->irq;
-                if (cpu_is_msm8x60() || cpu_is_msm8960()) {
-                        clock->percpu_evt = alloc_percpu(struct clock_event_device *);
-                        if (!clock->percpu_evt) {
-                                pr_err("msm_timer_init: memory allocation "
-                                       "failed for %s\n", ce->name);
-                                continue;
-                        }
-                        *__this_cpu_ptr(clock->percpu_evt) = ce;
-                        res = request_percpu_irq(ce->irq, msm_timer_interrupt,
-                                                 ce->name, clock->percpu_evt);
-                        if (!res)
-                                enable_percpu_irq(ce->irq, 0);
-                } else {
-                        clock->evt = ce;
-                        res = request_irq(ce->irq, msm_timer_interrupt,
-                                          IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
-                                          ce->name, &clock->evt);
                }
+                *__this_cpu_ptr(msm_evt.percpu_evt) = ce;
-                if (res)
+                res = request_percpu_irq(ce->irq, msm_timer_interrupt,
-                        pr_err("msm_timer_init: request_irq failed for %s\n",
+                                         ce->name, msm_evt.percpu_evt);
-                               ce->name);
+                if (!res)
+                        enable_percpu_irq(ce->irq, 0);
-                clockevents_register_device(ce);
+        } else {
+                msm_evt.evt = ce;
+                res = request_irq(ce->irq, msm_timer_interrupt,
+                                  IRQF_TIMER | IRQF_NOBALANCING |
+                                  IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
        }
+        if (res)
+                pr_err("request_irq failed for %s\n", ce->name);
+err:
+        writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
+        res = clocksource_register_hz(cs, dgt_hz);
+        if (res)
+                pr_err("clocksource_register failed\n");
 }
-#ifdef CONFIG_SMP
+#ifdef CONFIG_LOCAL_TIMERS
 int __cpuinit local_timer_setup(struct clock_event_device *evt)
 {
-        static bool local_timer_inited;
-        struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
        /* Use existing clock_event for cpu 0 */
        if (!smp_processor_id())
                return 0;
-        writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
+        writel_relaxed(0, event_base + TIMER_ENABLE);
+        writel_relaxed(0, event_base + TIMER_CLEAR);
-        if (!local_timer_inited) {
+        writel_relaxed(~0, event_base + TIMER_MATCH_VAL);
-                writel(0, clock->regbase  + TIMER_ENABLE);
+        evt->irq = msm_clockevent.irq;
-                writel(0, clock->regbase + TIMER_CLEAR);
-                writel(~0, clock->regbase + TIMER_MATCH_VAL);
-                local_timer_inited = true;
-        }
-        evt->irq = clock->irq;
        evt->name = "local_timer";
-        evt->features = CLOCK_EVT_FEAT_ONESHOT;
+        evt->features = msm_clockevent.features;
-        evt->rating = clock->clockevent.rating;
+        evt->rating = msm_clockevent.rating;
        evt->set_mode = msm_timer_set_mode;
        evt->set_next_event = msm_timer_set_next_event;
-        evt->shift = clock->clockevent.shift;
+        evt->shift = msm_clockevent.shift;
-        evt->mult = div_sc(clock->freq, NSEC_PER_SEC, evt->shift);
+        evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
-        evt->max_delta_ns =
+        evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
-                clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
        evt->min_delta_ns = clockevent_delta2ns(4, evt);
-        *__this_cpu_ptr(clock->percpu_evt) = evt;
+        *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
-        enable_percpu_irq(evt->irq, 0);
        clockevents_register_device(evt);
+        enable_percpu_irq(evt->irq, 0);
        return 0;
 }
@@ -321,8 +223,7 @@ void local_timer_stop(struct clock_event_device *evt)
        evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
        disable_percpu_irq(evt->irq);
 }
+#endif /* CONFIG_LOCAL_TIMERS */
-#endif
 struct sys_timer msm_timer = {
        .init = msm_timer_init
diff --git a/arch/arm/mach-msm/vreg.c b/arch/arm/mach-msm/vreg.c
index a9103bc6615..bd66ed04d6d 100644
--- a/arch/arm/mach-msm/vreg.c
+++ b/arch/arm/mach-msm/vreg.c
@@ -19,6 +19,7 @@
 #include <linux/device.h>
 #include <linux/init.h>
 #include <linux/debugfs.h>
+#include <linux/module.h>
 #include <linux/string.h>
 #include <mach/vreg.h>
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 311d5b0e9bc..62b53d710ef 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -12,12 +12,12 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
+#include <plat/addr-map.h>
 #include "common.h"
 /*
 * Generic Address Decode Windows bit settings
 */
-#define TARGET_DDR              0
 #define TARGET_DEV_BUS          1
 #define TARGET_PCIE0            4
 #define TARGET_PCIE1            8
@@ -32,23 +32,10 @@
 #define ATTR_PCIE_MEM(l)        (0xf8 & ~(0x10 << (l)))
 /*
- * Helpers to get DDR bank info
- */
-#define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
-#define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
-/*
 * CPU Address Decode Windows registers
 */
 #define WIN0_OFF(n)             (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
 #define WIN8_OFF(n)             (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
-#define WIN_CTRL_OFF            0x0000
-#define WIN_BASE_OFF            0x0004
-#define WIN_REMAP_LO_OFF        0x0008
-#define WIN_REMAP_HI_OFF        0x000c
-struct mbus_dram_target_info mv78xx0_mbus_dram_info;
 static void __init __iomem *win_cfg_base(int win)
 {
@@ -63,94 +50,43 @@ static void __init __iomem *win_cfg_base(int win)
        return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
 }
-static int __init cpu_win_can_remap(int win)
+/*
-{
+ * Description of the windows needed by the platform code
-        if (win < 8)
+ */
-                return 1;
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 14,
-        return 0;
+        .remappable_wins = 8,
-}
+        .win_cfg_base = win_cfg_base,
+};
-static void __init setup_cpu_win(int win, u32 base, u32 size,
-                                 u8 target, u8 attr, int remap)
-{
-        void __iomem *addr = win_cfg_base(win);
-        u32 ctrl;
-        base &= 0xffff0000;
-        ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
-        writel(base, addr + WIN_BASE_OFF);
-        writel(ctrl, addr + WIN_CTRL_OFF);
-        if (cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-                writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
-                writel(0, addr + WIN_REMAP_HI_OFF);
-        }
-}
 void __init mv78xx0_setup_cpu_mbus(void)
 {
-        void __iomem *addr;
-        int i;
-        int cs;
        /*
-         * First, disable and clear windows.
+         * Disable, clear and configure windows.
         */
-        for (i = 0; i < 14; i++) {
+        orion_config_wins(&addr_map_cfg, NULL);
-                addr = win_cfg_base(i);
-                writel(0, addr + WIN_BASE_OFF);
-                writel(0, addr + WIN_CTRL_OFF);
-                if (cpu_win_can_remap(i)) {
-                        writel(0, addr + WIN_REMAP_LO_OFF);
-                        writel(0, addr + WIN_REMAP_HI_OFF);
-                }
-        }
        /*
         * Setup MBUS dram target info.
         */
-        mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
        if (mv78xx0_core_index() == 0)
-                addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
+                orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                            DDR_WINDOW_CPU0_BASE);
        else
-                addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
+                orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                            DDR_WINDOW_CPU1_BASE);
-        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
-                /*
-                 * Chip select enabled?
-                 */
-                if (size & 1) {
-                        struct mbus_dram_window *w;
-                        w = &mv78xx0_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xffff0000;
-                        w->size = (size | 0x0000ffff) + 1;
-                }
-        }
-        mv78xx0_mbus_dram_info.num_cs = cs;
 }
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
                                      int maj, int min)
 {
-        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
+        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
-                      ATTR_PCIE_IO(min), -1);
+                            TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
 }
 void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
                                       int maj, int min)
 {
-        setup_cpu_win(window, base, size, TARGET_PCIE(maj),
+        orion_setup_cpu_win(&addr_map_cfg, window, base, size,
-                      ATTR_PCIE_MEM(min), -1);
+                            TARGET_PCIE(maj), ATTR_PCIE_MEM(min), -1);
 }
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index 0e94268d6e6..ee74ec97c14 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -151,4 +151,5 @@ MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
        .init_early     = mv78xx0_init_early,
        .init_irq       = mv78xx0_init_irq,
        .timer          = &mv78xx0_timer,
+        .restart        = mv78xx0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 23d3980ef59..0cdd41004ad 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -12,7 +12,6 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
-#include <linux/mbus.h>
 #include <linux/ata_platform.h>
 #include <linux/ethtool.h>
 #include <asm/mach/map.h>
@@ -23,6 +22,7 @@
 #include <plat/orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
+#include <plat/addr-map.h>
 #include "common.h"
 static int get_tclk(void);
@@ -169,8 +169,7 @@ void __init mv78xx0_map_io(void)
 ****************************************************************************/
 void __init mv78xx0_ehci0_init(void)
 {
-        orion_ehci_init(&mv78xx0_mbus_dram_info,
+        orion_ehci_init(USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
-                        USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
 }
@@ -179,8 +178,7 @@ void __init mv78xx0_ehci0_init(void)
 ****************************************************************************/
 void __init mv78xx0_ehci1_init(void)
 {
-        orion_ehci_1_init(&mv78xx0_mbus_dram_info,
+        orion_ehci_1_init(USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
-                          USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
 }
@@ -189,8 +187,7 @@ void __init mv78xx0_ehci1_init(void)
 ****************************************************************************/
 void __init mv78xx0_ehci2_init(void)
 {
-        orion_ehci_2_init(&mv78xx0_mbus_dram_info,
+        orion_ehci_2_init(USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
-                          USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
 }
@@ -199,7 +196,7 @@ void __init mv78xx0_ehci2_init(void)
 ****************************************************************************/
 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge00_init(eth_data,
                        GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
                        IRQ_MV78XX0_GE_ERR, get_tclk());
 }
@@ -210,7 +207,7 @@ void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 ****************************************************************************/
 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge01_init(eth_data,
                        GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
                        NO_IRQ, get_tclk());
 }
@@ -234,7 +231,7 @@ void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
                eth_data->duplex = DUPLEX_FULL;
        }
-        orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge10_init(eth_data,
                        GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
                        NO_IRQ, get_tclk());
 }
@@ -258,7 +255,7 @@ void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
                eth_data->duplex = DUPLEX_FULL;
        }
-        orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
+        orion_ge11_init(eth_data,
                        GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
                        NO_IRQ, get_tclk());
 }
@@ -277,8 +274,7 @@ void __init mv78xx0_i2c_init(void)
 ****************************************************************************/
 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
+        orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
-                        SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
 }
@@ -401,3 +397,19 @@ void __init mv78xx0_init(void)
        feroceon_l2_init(is_l2_writethrough());
 #endif
 }
+void mv78xx0_restart(char mode, const char *cmd)
+{
+        /*
+         * Enable soft reset to assert RSTOUTn.
+         */
+        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
+        /*
+         * Assert soft reset.
+         */
+        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
+        while (1)
+                ;
+}
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index 632e63d65e7..507c767d49e 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -23,7 +23,6 @@ void mv78xx0_init(void);
 void mv78xx0_init_early(void);
 void mv78xx0_init_irq(void);
-extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
 void mv78xx0_setup_cpu_mbus(void);
 void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
                               int maj, int min);
@@ -46,6 +45,7 @@ void mv78xx0_uart1_init(void);
 void mv78xx0_uart2_init(void);
 void mv78xx0_uart3_init(void);
 void mv78xx0_i2c_init(void);
+void mv78xx0_restart(char, const char *);
 extern struct sys_timer mv78xx0_timer;
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index 50b85ae2da5..4d6d48bf51e 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -99,4 +99,5 @@ MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
        .init_early     = mv78xx0_init_early,
        .init_irq       = mv78xx0_init_irq,
        .timer          = &mv78xx0_timer,
+        .restart        = mv78xx0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/include/mach/system.h b/arch/arm/mach-mv78xx0/include/mach/system.h
index 66e7ce4e90b..8c3a5387cec 100644
--- a/arch/arm/mach-mv78xx0/include/mach/system.h
+++ b/arch/arm/mach-mv78xx0/include/mach/system.h
@@ -9,28 +9,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <mach/bridge-regs.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        /*
-         * Enable soft reset to assert RSTOUTn.
-         */
-        writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-        /*
-         * Assert soft reset.
-         */
-        writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-        while (1)
-                ;
-}
 #endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
deleted file mode 100644
index ba26fe98e64..00000000000
--- a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/include/mach/vmalloc.h
- */
-#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index cf4e494d44b..df50342179e 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -10,7 +10,6 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mbus.h>
 #include <linux/io.h>
 #include <plat/mpp.h>
 #include <mach/hardware.h>
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index c51af1cac30..8459f6d7d8c 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -10,11 +10,11 @@
 #include <linux/kernel.h>
 #include <linux/pci.h>
-#include <linux/mbus.h>
 #include <video/vga.h>
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <plat/addr-map.h>
 #include "common.h"
 struct pcie_port {
@@ -153,11 +153,10 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
         * Generic PCIe unit setup.
         */
        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
-        orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info);
+        orion_pcie_setup(pp->base);
-        sys->resource[0] = &pp->res[0];
+        pci_add_resource(&sys->resources, &pp->res[0]);
-        sys->resource[1] = &pp->res[1];
+        pci_add_resource(&sys->resources, &pp->res[1]);
-        sys->resource[2] = NULL;
        return 1;
 }
@@ -251,7 +250,8 @@ mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
        struct pci_bus *bus;
        if (nr < num_pcie_ports) {
-                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+                bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
+                                        &sys->resources);
        } else {
                bus = NULL;
                BUG();
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index e85222e5357..9a882706e13 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -84,4 +84,5 @@ MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
        .init_early     = mv78xx0_init_early,
        .init_irq       = mv78xx0_init_irq,
        .timer          = &mv78xx0_timer,
+        .restart        = mv78xx0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 1fc11034804..944025da833 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -297,4 +297,5 @@ MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
        .handle_irq = imx51_handle_irq,
        .timer = &mxc_timer,
        .init_machine = eukrea_cpuimx51_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index 52a11c1898e..9fbe923c8b0 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -335,4 +335,5 @@ MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
        .handle_irq = imx51_handle_irq,
        .timer = &mxc_timer,
        .init_machine = eukrea_cpuimx51sd_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index fc3621d90bd..42b66e8d961 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -222,4 +222,5 @@ MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
        .handle_irq = imx50_handle_irq,
        .timer = &mx50_rdp_timer,
        .init_machine = mx50_rdp_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 05783906db2..83eab4176ca 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -175,4 +175,5 @@ MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
        .handle_irq = imx51_handle_irq,
        .timer = &mx51_3ds_timer,
        .init_machine = mx51_3ds_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 24994bb5214..e4b822e9f71 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -426,4 +426,5 @@ MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
        .handle_irq = imx51_handle_irq,
        .timer = &mx51_babbage_timer,
        .init_machine = mx51_babbage_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index a9e48662cf7..3a5ed2dd885 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -182,7 +182,7 @@ static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initcon
        .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
 };
-void mx51_efikamx_reset(void)
+static void mx51_efikamx_restart(char mode, const char *cmd)
 {
        if (system_rev == 0x11)
                gpio_direction_output(EFIKAMX_RESET1_1, 0);
@@ -292,4 +292,5 @@ MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
        .handle_irq = imx51_handle_irq,
        .timer = &mx51_efikamx_timer,
        .init_machine = mx51_efikamx_init,
+        .restart = mx51_efikamx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
index 38c4a3e28d3..ea5f65b0381 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -287,4 +287,5 @@ MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
        .handle_irq = imx51_handle_irq,
        .init_machine =  efikasb_board_init,
        .timer = &mx51_efikasb_timer,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
index 0d7f0fffb23..5f224f1c3eb 100644
--- a/arch/arm/mach-mx5/board-mx53_ard.c
+++ b/arch/arm/mach-mx5/board-mx53_ard.c
@@ -257,4 +257,5 @@ MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
        .handle_irq = imx53_handle_irq,
        .timer = &mx53_ard_timer,
        .init_machine = mx53_ard_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 64bbfcea6f3..d6ce137896d 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -175,4 +175,5 @@ MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
        .handle_irq = imx53_handle_irq,
        .timer = &mx53_evk_timer,
        .init_machine = mx53_evk_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 237bdecd933..fd8b524e1c5 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -317,4 +317,5 @@ MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
        .handle_irq = imx53_handle_irq,
        .timer = &mx53_loco_timer,
        .init_machine = mx53_loco_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index d42132a80e8..22c53c9b18a 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -164,4 +164,5 @@ MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
        .handle_irq = imx53_handle_irq,
        .timer = &mx53_smd_timer,
        .init_machine = mx53_smd_board_init,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-mx5/imx51-dt.c
index 596edd967db..e6bad17b908 100644
--- a/arch/arm/mach-mx5/imx51-dt.c
+++ b/arch/arm/mach-mx5/imx51-dt.c
@@ -115,4 +115,5 @@ DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
        .timer          = &imx51_timer,
        .init_machine   = imx51_dt_init,
        .dt_compat      = imx51_dt_board_compat,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-mx5/imx53-dt.c
index 85bfd5ff21b..05ebb3e6867 100644
--- a/arch/arm/mach-mx5/imx53-dt.c
+++ b/arch/arm/mach-mx5/imx53-dt.c
@@ -125,4 +125,5 @@ DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
        .timer          = &imx53_timer,
        .init_machine   = imx53_dt_init,
        .dt_compat      = imx53_dt_board_compat,
+        .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index df4a508f240..bc17dfea381 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -13,6 +13,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
+#include <linux/clk.h>
 #include <asm/mach/map.h>
@@ -21,10 +22,26 @@
 #include <mach/devices-common.h>
 #include <mach/iomux-v3.h>
+static struct clk *gpc_dvfs_clk;
 static void imx5_idle(void)
 {
-        if (!need_resched())
+        if (!need_resched()) {
+                /* gpc clock is needed for SRPG */
+                if (gpc_dvfs_clk == NULL) {
+                        gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
+                        if (IS_ERR(gpc_dvfs_clk))
+                                goto err0;
+                }
+                clk_enable(gpc_dvfs_clk);
                mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+                if (tzic_enable_wake())
+                        goto err1;
+                cpu_do_idle();
+err1:
+                clk_disable(gpc_dvfs_clk);
+        }
+err0:
        local_irq_enable();
 }
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
index 144ebebc4a6..5eebfaad122 100644
--- a/arch/arm/mach-mx5/system.c
+++ b/arch/arm/mach-mx5/system.c
@@ -55,9 +55,6 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
                        stop_mode = 1;
                }
                arm_srpgcr |= MXC_SRPGCR_PCR;
-                if (tzic_enable_wake(1) != 0)
-                        return;
                break;
        case STOP_POWER_ON:
                ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET;
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index 0163b6d8377..e12e11231dc 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -545,11 +545,11 @@ int __init mx23_clocks_init(void)
         */
        clk_set_parent(&ssp_clk, &ref_io_clk);
-        clk_enable(&cpu_clk);
+        clk_prepare_enable(&cpu_clk);
-        clk_enable(&hbus_clk);
+        clk_prepare_enable(&hbus_clk);
-        clk_enable(&xbus_clk);
+        clk_prepare_enable(&xbus_clk);
-        clk_enable(&emi_clk);
+        clk_prepare_enable(&emi_clk);
-        clk_enable(&uart_clk);
+        clk_prepare_enable(&uart_clk);
        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index da6e4aad177..5d68e415222 100644
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/jiffies.h>
 #include <linux/clkdev.h>
+#include <linux/spinlock.h>
 #include <asm/clkdev.h>
 #include <asm/div64.h>
@@ -29,6 +30,7 @@
 #include <mach/mx28.h>
 #include <mach/common.h>
 #include <mach/clock.h>
+#include <mach/digctl.h>
 #include "regs-clkctrl-mx28.h"
@@ -43,6 +45,33 @@ static struct clk emi_clk;
 static struct clk saif0_clk;
 static struct clk saif1_clk;
 static struct clk clk32k_clk;
+static DEFINE_SPINLOCK(clkmux_lock);
+/*
+ * HW_SAIF_CLKMUX_SEL:
+ *  DIRECT(0x0): SAIF0 clock pins selected for SAIF0 input clocks, and SAIF1
+ *              clock pins selected for SAIF1 input clocks.
+ *  CROSSINPUT(0x1): SAIF1 clock inputs selected for SAIF0 input clocks, and
+ *              SAIF0 clock inputs selected for SAIF1 input clocks.
+ *  EXTMSTR0(0x2): SAIF0 clock pin selected for both SAIF0 and SAIF1 input
+ *              clocks.
+ *  EXTMSTR1(0x3): SAIF1 clock pin selected for both SAIF0 and SAIF1 input
+ *              clocks.
+ */
+int mxs_saif_clkmux_select(unsigned int clkmux)
+{
+        if (clkmux > 0x3)
+                return -EINVAL;
+        spin_lock(&clkmux_lock);
+        __raw_writel(BM_DIGCTL_CTRL_SAIF_CLKMUX,
+                        DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_CLR_ADDR);
+        __raw_writel(clkmux << BP_DIGCTL_CTRL_SAIF_CLKMUX,
+                        DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL + MXS_SET_ADDR);
+        spin_unlock(&clkmux_lock);
+        return 0;
+}
 static int _raw_clk_enable(struct clk *clk)
 {
@@ -775,16 +804,25 @@ int __init mx28_clocks_init(void)
        clk_set_parent(&ssp0_clk, &ref_io0_clk);
        clk_set_parent(&ssp1_clk, &ref_io0_clk);
-        clk_enable(&cpu_clk);
+        clk_prepare_enable(&cpu_clk);
-        clk_enable(&hbus_clk);
+        clk_prepare_enable(&hbus_clk);
-        clk_enable(&xbus_clk);
+        clk_prepare_enable(&xbus_clk);
-        clk_enable(&emi_clk);
+        clk_prepare_enable(&emi_clk);
-        clk_enable(&uart_clk);
+        clk_prepare_enable(&uart_clk);
        clk_set_parent(&lcdif_clk, &ref_pix_clk);
        clk_set_parent(&saif0_clk, &pll0_clk);
        clk_set_parent(&saif1_clk, &pll0_clk);
+        /*
+         * Set an initial clock rate for the saif internal logic to work
+         * properly. This is important when working in EXTMASTER mode that
+         * uses the other saif's BITCLK&LRCLK but it still needs a basic
+         * clock which should be fast enough for the internal logic.
+         */
+        clk_set_rate(&saif0_clk, 24000000);
+        clk_set_rate(&saif1_clk, 24000000);
        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
        mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
index a7093c88e6a..97a6f4acc6c 100644
--- a/arch/arm/mach-mxs/clock.c
+++ b/arch/arm/mach-mxs/clock.c
@@ -74,10 +74,15 @@ static int __clk_enable(struct clk *clk)
        return 0;
 }
-/* This function increments the reference count on the clock and enables the
+/*
- * clock if not already enabled. The parent clock tree is recursively enabled
+ * The clk_enable/clk_disable could be called by drivers in atomic context,
+ * so they should not really hold mutex.  Instead, clk_prepare/clk_unprepare
+ * can hold a mutex, as the pair will only be called in non-atomic context.
+ * Before migrating to common clk framework, we can have __clk_enable and
+ * __clk_disable called in clk_prepare/clk_unprepare with mutex held and
+ * leave clk_enable/clk_disable as the dummy functions.
 */
-int clk_enable(struct clk *clk)
+int clk_prepare(struct clk *clk)
 {
        int ret = 0;
@@ -90,13 +95,9 @@ int clk_enable(struct clk *clk)
        return ret;
 }
-EXPORT_SYMBOL(clk_enable);
+EXPORT_SYMBOL(clk_prepare);
-/* This function decrements the reference count on the clock and disables
+void clk_unprepare(struct clk *clk)
- * the clock when reference count is 0. The parent clock tree is
- * recursively disabled
- */
-void clk_disable(struct clk *clk)
 {
        if (clk == NULL || IS_ERR(clk))
                return;
@@ -105,6 +106,18 @@ void clk_disable(struct clk *clk)
        __clk_disable(clk);
        mutex_unlock(&clocks_mutex);
 }
+EXPORT_SYMBOL(clk_unprepare);
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+void clk_disable(struct clk *clk)
+{
+        /* nothing to do */
+}
 EXPORT_SYMBOL(clk_disable);
 /* Retrieve the *current* clock rate. If the clock itself
@@ -166,7 +179,7 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
                return ret;
        if (clk->usecount)
-                clk_enable(parent);
+                clk_prepare_enable(parent);
        mutex_lock(&clocks_mutex);
        ret = clk->set_parent(clk, parent);
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index c8887103f0e..4f50094e293 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -47,6 +47,7 @@ struct platform_device *__init mx28_add_mxsfb(
                const struct mxsfb_platform_data *pdata);
 extern const struct mxs_saif_data mx28_saif_data[] __initconst;
-#define mx28_add_saif(id)              mxs_add_saif(&mx28_saif_data[id])
+#define mx28_add_saif(id, pdata) \
+        mxs_add_saif(&mx28_saif_data[id], pdata)
 struct platform_device *__init mx28_add_rtc_stmp3xxx(void);
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-saif.c b/arch/arm/mach-mxs/devices/platform-mxs-saif.c
index 1ec965e9fe9..f6e3a60b420 100644
--- a/arch/arm/mach-mxs/devices/platform-mxs-saif.c
+++ b/arch/arm/mach-mxs/devices/platform-mxs-saif.c
@@ -32,7 +32,8 @@ const struct mxs_saif_data mx28_saif_data[] __initconst = {
 };
 #endif
-struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data)
+struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data,
+                                const struct mxs_saif_platform_data *pdata)
 {
        struct resource res[] = {
                {
@@ -56,5 +57,5 @@ struct platform_device *__init mxs_add_saif(const struct mxs_saif_data *data)
        };
        return mxs_add_platform_device("mxs-saif", data->id, res,
-                                        ARRAY_SIZE(res), NULL, 0);
+                                ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
index 635bb5d9a20..e1237ab2586 100644
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -16,6 +16,8 @@ struct clk;
 extern const u32 *mxs_get_ocotp(void);
 extern int mxs_reset_block(void __iomem *);
 extern void mxs_timer_init(struct clk *, int);
+extern void mxs_restart(char, const char *);
+extern int mxs_saif_clkmux_select(unsigned int clkmux);
 extern int mx23_register_gpios(void);
 extern int mx23_clocks_init(void);
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index a8080f44c03..dc369c1239f 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -94,6 +94,7 @@ struct platform_device *__init mxs_add_mxs_pwm(
                resource_size_t iobase, int id);
 /* saif */
+#include <sound/saif.h>
 struct mxs_saif_data {
        int id;
        resource_size_t iobase;
@@ -103,4 +104,5 @@ struct mxs_saif_data {
 };
 struct platform_device *__init mxs_add_saif(
-                const struct mxs_saif_data *data);
+                const struct mxs_saif_data *data,
+                const struct mxs_saif_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h
new file mode 100644
index 00000000000..49a888c65d6
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/digctl.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __MACH_DIGCTL_H__
+#define __MACH_DIGCTL_H__
+/* MXS DIGCTL SAIF CLKMUX */
+#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT           0x0
+#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT       0x1
+#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0         0x2
+#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1         0x3
+#define HW_DIGCTL_CTRL                  0x0
+#define  BP_DIGCTL_CTRL_SAIF_CLKMUX     10
+#define  BM_DIGCTL_CTRL_SAIF_CLKMUX     (0x3 << 10)
+#endif
diff --git a/arch/arm/mach-mxs/include/mach/system.h b/arch/arm/mach-mxs/include/mach/system.h
index 0e428239b43..e7ad1bb2942 100644
--- a/arch/arm/mach-mxs/include/mach/system.h
+++ b/arch/arm/mach-mxs/include/mach/system.h
@@ -22,6 +22,4 @@ static inline void arch_idle(void)
        cpu_do_idle();
 }
-void arch_reset(char mode, const char *cmd);
 #endif /* __MACH_MXS_SYSTEM_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/vmalloc.h b/arch/arm/mach-mxs/include/mach/vmalloc.h
deleted file mode 100644
index 103b0165ed0..00000000000
--- a/arch/arm/mach-mxs/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  Copyright (C) 2000 Russell King.
- *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_MXS_VMALLOC_H__
-#define __MACH_MXS_VMALLOC_H__
-/* vmalloc ending address */
-#define VMALLOC_END       0xf4000000UL
-#endif /* __MACH_MXS_VMALLOC_H__ */
diff --git a/arch/arm/mach-mxs/mach-m28evk.c b/arch/arm/mach-mxs/mach-m28evk.c
index 6b00577b702..2f2758230ed 100644
--- a/arch/arm/mach-mxs/mach-m28evk.c
+++ b/arch/arm/mach-mxs/mach-m28evk.c
@@ -363,4 +363,5 @@ MACHINE_START(M28EVK, "DENX M28 EVK")
        .init_irq       = mx28_init_irq,
        .timer          = &m28evk_timer,
        .init_machine   = m28evk_init,
+        .restart        = mxs_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index c325fbe4e4c..5ea1c57d260 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -184,4 +184,5 @@ MACHINE_START(MX23EVK, "Freescale MX23 EVK")
        .init_irq       = mx23_init_irq,
        .timer          = &mx23evk_timer,
        .init_machine   = mx23evk_init,
+        .restart        = mxs_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 064ec5abaa5..fdb0a5664dd 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -27,6 +27,7 @@
 #include <mach/common.h>
 #include <mach/iomux-mx28.h>
+#include <mach/digctl.h>
 #include "devices-mx28.h"
@@ -228,7 +229,7 @@ static void __init mx28evk_fec_reset(void)
        /* Enable fec phy clock */
        clk = clk_get_sys("pll2", NULL);
        if (!IS_ERR(clk))
-                clk_enable(clk);
+                clk_prepare_enable(clk);
        /* Power up fec phy */
        ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power");
@@ -421,6 +422,18 @@ static struct gpio mx28evk_lcd_gpios[] = {
        { MX28EVK_BL_ENABLE, GPIOF_OUT_INIT_HIGH, "bl-enable" },
 };
+static const struct mxs_saif_platform_data
+                        mx28evk_mxs_saif_pdata[] __initconst = {
+        /* working on EXTMSTR0 mode (saif0 master, saif1 slave) */
+        {
+                .master_mode = 1,
+                .master_id = 0,
+        }, {
+                .master_mode = 0,
+                .master_id = 0,
+        },
+};
 static void __init mx28evk_init(void)
 {
        int ret;
@@ -454,8 +467,9 @@ static void __init mx28evk_init(void)
        else
                mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
-        mx28_add_saif(0);
+        mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
-        mx28_add_saif(1);
+        mx28_add_saif(0, &mx28evk_mxs_saif_pdata[0]);
+        mx28_add_saif(1, &mx28evk_mxs_saif_pdata[1]);
        mx28_add_mxs_i2c(0);
        i2c_register_board_info(0, mxs_i2c0_board_info,
@@ -501,4 +515,5 @@ MACHINE_START(MX28EVK, "Freescale MX28 EVK")
        .init_irq       = mx28_init_irq,
        .timer          = &mx28evk_timer,
        .init_machine   = mx28evk_init,
+        .restart        = mxs_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
index 6834dea38c0..a626c07b871 100644
--- a/arch/arm/mach-mxs/mach-stmp378x_devb.c
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -117,4 +117,5 @@ MACHINE_START(STMP378X, "STMP378X")
        .init_irq       = mx23_init_irq,
        .timer          = &stmp378x_dvb_timer,
        .init_machine   = stmp378x_dvb_init,
+        .restart        = mxs_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
index 9a1f0e7a338..2c0862e655e 100644
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -178,4 +178,5 @@ MACHINE_START(TX28, "Ka-Ro electronics TX28 module")
        .init_irq = mx28_init_irq,
        .timer = &tx28_timer,
        .init_machine = tx28_stk5v3_init,
+        .restart        = mxs_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
index 20ec3bddf7c..54f91ad1c96 100644
--- a/arch/arm/mach-mxs/system.c
+++ b/arch/arm/mach-mxs/system.c
@@ -42,7 +42,7 @@ static void __iomem *mxs_clkctrl_reset_addr;
 /*
 * Reset the system. It is called by machine_restart().
 */
-void arch_reset(char mode, const char *cmd)
+void mxs_restart(char mode, const char *cmd)
 {
        /* reset the chip */
        __mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr);
@@ -53,7 +53,7 @@ void arch_reset(char mode, const char *cmd)
        mdelay(50);
        /* We'll take a jump through zero as a poor second */
-        cpu_reset(0);
+        soft_restart(0);
 }
 static int __init mxs_arch_reset_init(void)
@@ -66,7 +66,7 @@ static int __init mxs_arch_reset_init(void)
        clk = clk_get_sys("rtc", NULL);
        if (!IS_ERR(clk))
-                clk_enable(clk);
+                clk_prepare_enable(clk);
        return 0;
 }
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index cace0d2e5a5..564a63279f1 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -245,7 +245,7 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
 void __init mxs_timer_init(struct clk *timer_clk, int irq)
 {
-        clk_enable(timer_clk);
+        clk_prepare_enable(timer_clk);
        /*
         * Initialize timers to a known state
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 00023b5cf12..59e67979f19 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -187,3 +187,8 @@ static int __init netx_init(void)
 subsys_initcall(netx_init);
+void netx_restart(char mode, const char *cmd)
+{
+        writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
+               NETX_SYSTEM_RES_CR);
+}
diff --git a/arch/arm/mach-netx/generic.h b/arch/arm/mach-netx/generic.h
index ede2d35341c..9b915119b8d 100644
--- a/arch/arm/mach-netx/generic.h
+++ b/arch/arm/mach-netx/generic.h
@@ -19,6 +19,7 @@
 extern void __init netx_map_io(void);
 extern void __init netx_init_irq(void);
+extern void netx_restart(char, const char *);
 struct sys_timer;
 extern struct sys_timer netx_timer;
diff --git a/arch/arm/mach-netx/include/mach/entry-macro.S b/arch/arm/mach-netx/include/mach/entry-macro.S
index 844f1f9acbd..6e9f1cbe163 100644
--- a/arch/arm/mach-netx/include/mach/entry-macro.S
+++ b/arch/arm/mach-netx/include/mach/entry-macro.S
@@ -18,22 +18,9 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <mach/hardware.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =io_p2v(0x001ff000)
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqstat, [\base, #0]
-                clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #31
-                cmp     \irqstat, #0
-                .endm
diff --git a/arch/arm/mach-netx/include/mach/system.h b/arch/arm/mach-netx/include/mach/system.h
index dc7b4bc003c..b38fa36d58c 100644
--- a/arch/arm/mach-netx/include/mach/system.h
+++ b/arch/arm/mach-netx/include/mach/system.h
@@ -19,20 +19,10 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include "netx-regs.h"
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES,
-               NETX_SYSTEM_RES_CR);
-}
 #endif
diff --git a/arch/arm/mach-netx/include/mach/vmalloc.h b/arch/arm/mach-netx/include/mach/vmalloc.h
deleted file mode 100644
index 871f1ef7bff..00000000000
--- a/arch/arm/mach-netx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  arch/arm/mach-netx/include/mach/vmalloc.h
- *
- * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END       0xd0000000UL
diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
index 90903dd44cb..180ea899a48 100644
--- a/arch/arm/mach-netx/nxdb500.c
+++ b/arch/arm/mach-netx/nxdb500.c
@@ -28,6 +28,7 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
 #include <mach/eth.h>
@@ -203,6 +204,8 @@ MACHINE_START(NXDB500, "Hilscher nxdb500")
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &netx_timer,
        .init_machine   = nxdb500_init,
+        .restart        = netx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
index c63384aba50..58009e29b20 100644
--- a/arch/arm/mach-netx/nxdkn.c
+++ b/arch/arm/mach-netx/nxdkn.c
@@ -28,6 +28,7 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
 #include <mach/eth.h>
@@ -96,6 +97,8 @@ MACHINE_START(NXDKN, "Hilscher nxdkn")
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &netx_timer,
        .init_machine   = nxdkn_init,
+        .restart        = netx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
index 8f548ec83ad..122e99826ef 100644
--- a/arch/arm/mach-netx/nxeb500hmi.c
+++ b/arch/arm/mach-netx/nxeb500hmi.c
@@ -28,6 +28,7 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/vic.h>
 #include <mach/netx-regs.h>
 #include <mach/eth.h>
@@ -180,6 +181,8 @@ MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
        .atag_offset    = 0x100,
        .map_io         = netx_map_io,
        .init_irq       = netx_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &netx_timer,
        .init_machine   = nxeb500hmi_init,
+        .restart        = netx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 0cbb74c96ef..7c878bf0034 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -21,6 +21,7 @@
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
+#include <asm/hardware/vic.h>
 #include <asm/sizes.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -34,6 +35,8 @@
 #include <mach/nand.h>
 #include <mach/fsmc.h>
+#include "cpu-8815.h"
 /* Initial value for SRC control register: all timers use MXTAL/8 source */
 #define SRC_CR_INIT_MASK        0x00007fff
 #define SRC_CR_INIT_VAL         0x2aaa8000
@@ -280,6 +283,8 @@ MACHINE_START(NOMADIK, "NHK8815")
        .atag_offset    = 0x100,
        .map_io         = cpu8815_map_io,
        .init_irq       = cpu8815_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &nomadik_timer,
        .init_machine   = nhk8815_platform_init,
+        .restart        = cpu8815_restart,
 MACHINE_END
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index dc67717db6f..65df7b4fdd3 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -21,6 +21,7 @@
 #include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/platform_device.h>
+#include <linux/io.h>
 #include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
@@ -32,6 +33,7 @@
 #include <asm/hardware/cache-l2x0.h>
 #include "clock.h"
+#include "cpu-8815.h"
 #define __MEM_4K_RESOURCE(x) \
        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
@@ -164,3 +166,13 @@ void __init cpu8815_init_irq(void)
 #endif
         return;
 }
+void cpu8815_restart(char mode, const char *cmd)
+{
+        void __iomem *src_rstsr = io_p2v(NOMADIK_SRC_BASE + 0x18);
+        /* FIXME: use egpio when implemented */
+        /* Write anything to Reset status register */
+        writel(1, src_rstsr);
+}
diff --git a/arch/arm/mach-nomadik/cpu-8815.h b/arch/arm/mach-nomadik/cpu-8815.h
new file mode 100644
index 00000000000..71c21e8a11d
--- /dev/null
+++ b/arch/arm/mach-nomadik/cpu-8815.h
@@ -0,0 +1,4 @@
+extern void cpu8815_map_io(void);
+extern void cpu8815_platform_init(void);
+extern void cpu8815_init_irq(void);
+extern void cpu8815_restart(char, const char *);
diff --git a/arch/arm/mach-nomadik/include/mach/entry-macro.S b/arch/arm/mach-nomadik/include/mach/entry-macro.S
index 49f1aa3bb42..98ea1c1fbba 100644
--- a/arch/arm/mach-nomadik/include/mach/entry-macro.S
+++ b/arch/arm/mach-nomadik/include/mach/entry-macro.S
@@ -6,38 +6,8 @@
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
        .macro  disable_fiq
        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =IO_ADDRESS(NOMADIK_IC_BASE)
-        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        /* This stanza gets the irq mask from one of two status registers */
-        mov     \irqnr, #0
-        ldr     \irqstat, [\base, #VIC_REG_IRQSR0]      @ get masked status
-        cmp     \irqstat, #0
-        bne     1001f
-        add     \irqnr, \irqnr, #32
-        ldr     \irqstat, [\base, #VIC_REG_IRQSR1]      @ get masked status
-1001:   tst     \irqstat, #15
-        bne     1002f
-        add     \irqnr, \irqnr, #4
-        movs    \irqstat, \irqstat, lsr #4
-        bne     1001b
-1002:   tst     \irqstat, #1
-        bne     1003f
-        add     \irqnr, \irqnr, #1
-        movs    \irqstat, \irqstat, lsr #1
-        bne     1002b
-1003:   /* EQ will be set if no irqs pending */
-        .endm
diff --git a/arch/arm/mach-nomadik/include/mach/setup.h b/arch/arm/mach-nomadik/include/mach/setup.h
index b7897edf1f3..bcaeaf41c05 100644
--- a/arch/arm/mach-nomadik/include/mach/setup.h
+++ b/arch/arm/mach-nomadik/include/mach/setup.h
@@ -12,9 +12,6 @@
 #ifdef CONFIG_NOMADIK_8815
-extern void cpu8815_map_io(void);
-extern void cpu8815_platform_init(void);
-extern void cpu8815_init_irq(void);
 extern void nmdk_timer_init(void);
 #endif /* NOMADIK_8815 */
diff --git a/arch/arm/mach-nomadik/include/mach/system.h b/arch/arm/mach-nomadik/include/mach/system.h
index 7119f688116..25e198b8976 100644
--- a/arch/arm/mach-nomadik/include/mach/system.h
+++ b/arch/arm/mach-nomadik/include/mach/system.h
@@ -20,9 +20,6 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <linux/io.h>
-#include <mach/hardware.h>
 static inline void arch_idle(void)
 {
        /*
@@ -32,14 +29,4 @@ static inline void arch_idle(void)
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        void __iomem *src_rstsr = io_p2v(NOMADIK_SRC_BASE + 0x18);
-        /* FIXME: use egpio when implemented */
-        /* Write anything to Reset status register */
-        writel(1, src_rstsr);
-}
 #endif
diff --git a/arch/arm/mach-nomadik/include/mach/vmalloc.h b/arch/arm/mach-nomadik/include/mach/vmalloc.h
deleted file mode 100644
index f83d574d944..00000000000
--- a/arch/arm/mach-nomadik/include/mach/vmalloc.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#define VMALLOC_END       0xe8000000UL
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index 73f287d6429..4f8d66f044e 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -168,70 +168,6 @@ config MACH_OMAP_GENERIC
          custom OMAP boards. Say Y here if you have a custom
          board.
-comment "OMAP CPU Speed"
-        depends on ARCH_OMAP1
-config OMAP_ARM_216MHZ
-        bool "OMAP ARM 216 MHz CPU (1710 only)"
-        depends on ARCH_OMAP1 && ARCH_OMAP16XX
-        help
-          Enable 216 MHz clock for OMAP1710 CPU. If unsure, say N.
-config OMAP_ARM_195MHZ
-        bool "OMAP ARM 195 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 195MHz clock for OMAP CPU. If unsure, say N.
-config OMAP_ARM_192MHZ
-        bool "OMAP ARM 192 MHz CPU"
-        depends on ARCH_OMAP1 && ARCH_OMAP16XX
-        help
-          Enable 192MHz clock for OMAP CPU. If unsure, say N.
-config OMAP_ARM_182MHZ
-        bool "OMAP ARM 182 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 182MHz clock for OMAP CPU. If unsure, say N.
-config OMAP_ARM_168MHZ
-        bool "OMAP ARM 168 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 168MHz clock for OMAP CPU. If unsure, say N.
-config OMAP_ARM_150MHZ
-        bool "OMAP ARM 150 MHz CPU"
-        depends on ARCH_OMAP1 && ARCH_OMAP15XX
-        help
-          Enable 150MHz clock for OMAP CPU. If unsure, say N.
-config OMAP_ARM_120MHZ
-        bool "OMAP ARM 120 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 120MHz clock for OMAP CPU. If unsure, say N.
-config OMAP_ARM_96MHZ
-        bool "OMAP ARM 96 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 96MHz clock for OMAP CPU. If unsure, say N.
-config OMAP_ARM_60MHZ
-        bool "OMAP ARM 60 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        default y
-        help
-          Enable 60MHz clock for OMAP CPU. If unsure, say Y.
-config OMAP_ARM_30MHZ
-        bool "OMAP ARM 30 MHz CPU"
-        depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850)
-        help
-          Enable 30MHz clock for OMAP CPU. If unsure, say N.
 endmenu
 endif
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index b0f15d234a1..88909cc0b25 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -35,7 +35,7 @@
 #include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <mach/camera.h>
 #include <mach/ams-delta-fiq.h>
@@ -386,6 +386,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
        .init_irq       = omap1_init_irq,
        .init_machine   = ams_delta_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
 EXPORT_SYMBOL(ams_delta_latch1_write);
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 23178275f96..0b9464b4121 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -32,7 +32,7 @@
 #include <plat/flash.h>
 #include <plat/fpga.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 /* fsample is pretty close to p2-sample */
@@ -390,4 +390,5 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_fsample_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index dc5b75de531..9a5fe581bc1 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -25,7 +25,7 @@
 #include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 /* assume no Mini-AB port */
@@ -89,4 +89,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_generic_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index b334b148167..00ad6b22d60 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -43,7 +43,7 @@
 #include <plat/irda.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/flash.h>
 #include "board-h2.h"
@@ -456,4 +456,5 @@ MACHINE_START(OMAP_H2, "TI-H2")
        .init_irq       = omap1_init_irq,
        .init_machine   = h2_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 74ebe72c984..4a7f2514970 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -45,7 +45,7 @@
 #include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/dma.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/flash.h>
 #include "board-h3.h"
@@ -444,4 +444,5 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
        .init_irq       = omap1_init_irq,
        .init_machine   = h3_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 3e91baab1a8..731cc3db7ab 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -41,7 +41,7 @@
 #include <asm/mach/arch.h>
 #include <plat/omap7xx.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/usb.h>
@@ -610,4 +610,5 @@ MACHINE_START(HERALD, "HTC Herald")
        .init_irq       = omap1_init_irq,
        .init_machine   = htcherald_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 273153dba15..309369ea697 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -37,7 +37,7 @@
 #include <plat/tc.h>
 #include <plat/usb.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/mmc.h>
 /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
@@ -460,4 +460,5 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
        .init_irq       = omap1_init_irq,
        .init_machine   = innovator_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 6798b848831..f9efc036ba9 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -30,7 +30,7 @@
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/hwa742.h>
 #include <plat/lcd_mipid.h>
 #include <plat/mmc.h>
@@ -259,4 +259,5 @@ MACHINE_START(NOKIA770, "Nokia 770")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_nokia770_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index c3859278d25..675de06557a 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -51,7 +51,7 @@
 #include <plat/usb.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
-#include <plat/common.h>
+#include "common.h"
 /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
 #define OMAP_OSK_ETHR_START             0x04800300
@@ -578,4 +578,5 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
        .init_irq       = omap1_init_irq,
        .init_machine   = osk_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index f9c44cb15b4..81fa27f8836 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -41,7 +41,7 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #define PALMTE_USBDETECT_GPIO   0
 #define PALMTE_USB_OR_DC_GPIO   1
@@ -270,4 +270,5 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmte_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 11a98539f7b..81cb8217838 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -39,7 +39,7 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -317,4 +317,5 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmtt_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 42061573e38..e881945ce8e 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -41,7 +41,7 @@
 #include <plat/board.h>
 #include <plat/irda.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
@@ -334,4 +334,5 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_palmz71_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 203ae07550d..c000bed7627 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -32,7 +32,7 @@
 #include <plat/fpga.h>
 #include <plat/flash.h>
 #include <plat/keypad.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 static const unsigned int p2_keymap[] = {
@@ -352,4 +352,5 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_perseus2_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 092a4c04640..7bcd82ab0fd 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -40,7 +40,7 @@
 #include <plat/usb.h>
 #include <plat/tc.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/keypad.h>
 #include <plat/board-sx1.h>
@@ -416,4 +416,5 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
        .init_irq       = omap1_init_irq,
        .init_machine   = omap_sx1_init,
        .timer          = &omap1_timer,
+        .restart        = omap1_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 61ed6cdab2b..f83a502dc93 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -28,13 +28,12 @@
 #include <linux/export.h>
 #include <mach/hardware.h>
-#include <mach/system.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <plat/board-voiceblue.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/flash.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
@@ -221,7 +220,7 @@ void voiceblue_wdt_ping(void)
        gpio_set_value(0, wdt_gpio_state);
 }
-static void voiceblue_reset(char mode, const char *cmd)
+static void voiceblue_restart(char mode, const char *cmd)
 {
        /*
         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
@@ -285,8 +284,6 @@ static void __init voiceblue_init(void)
         * (it is connected through invertor) */
        omap_writeb(0x00, OMAP_LPG1_LCR);
        omap_writeb(0x00, OMAP_LPG1_PMR);       /* Disable clock */
-        arch_reset = voiceblue_reset;
 }
 MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
@@ -298,4 +295,5 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
        .init_irq       = omap1_init_irq,
        .init_machine   = voiceblue_init,
        .timer          = &omap1_timer,
+        .restart        = voiceblue_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 84ef70476b5..0c50df05d13 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -197,11 +197,10 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
        ref_rate = ck_ref_p->rate;
        for (ptr = omap1_rate_table; ptr->rate; ptr++) {
-                if (ptr->xtal != ref_rate)
+                if (!(ptr->flags & cpu_mask))
                        continue;
-                /* DPLL1 cannot be reprogrammed without risking system crash */
+                if (ptr->xtal != ref_rate)
-                if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate)
                        continue;
                /* Can check only after xtal frequency check */
@@ -215,12 +214,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
        /*
         * In most cases we should not need to reprogram DPLL.
         * Reprogramming the DPLL is tricky, it must be done from SRAM.
-         * (on 730, bit 13 must always be 1)
         */
-        if (cpu_is_omap7xx())
+        omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
-                omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
-        else
-                omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
        /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
        ck_dpll1_p->rate = ptr->pll_rate;
@@ -290,6 +285,9 @@ long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
        highest_rate = -EINVAL;
        for (ptr = omap1_rate_table; ptr->rate; ptr++) {
+                if (!(ptr->flags & cpu_mask))
+                        continue;
                if (ptr->xtal != ref_rate)
                        continue;
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h
index 16b1423b454..3d04f4f6767 100644
--- a/arch/arm/mach-omap1/clock.h
+++ b/arch/arm/mach-omap1/clock.h
@@ -111,4 +111,7 @@ extern const struct clkops clkops_dummy;
 extern const struct clkops clkops_uart_16xx;
 extern const struct clkops clkops_generic;
+/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
+extern u32 cpu_mask;
 #endif
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 9ff90a744a2..94699a82a73 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -25,6 +25,7 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/clkdev_omap.h>
+#include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
 #include <plat/usb.h>   /* for OTG_BASE */
 #include "clock.h"
@@ -778,12 +779,14 @@ static void __init omap1_show_rates(void)
                arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
 }
+u32 cpu_mask;
 int __init omap1_clk_init(void)
 {
        struct omap_clk *c;
        const struct omap_clock_config *info;
        int crystal_type = 0; /* Default 12 MHz */
-        u32 reg, cpu_mask;
+        u32 reg;
 #ifdef CONFIG_DEBUG_LL
        /*
@@ -808,6 +811,8 @@ int __init omap1_clk_init(void)
                clk_preinit(c->lk.clk);
        cpu_mask = 0;
+        if (cpu_is_omap1710())
+                cpu_mask |= CK_1710;
        if (cpu_is_omap16xx())
                cpu_mask |= CK_16XX;
        if (cpu_is_omap1510())
@@ -931,17 +936,13 @@ void __init omap1_clk_late_init(void)
 {
        unsigned long rate = ck_dpll1.rate;
-        if (rate >= OMAP1_DPLL1_SANE_VALUE)
-                return;
-        /* System booting at unusable rate, force reprogramming of DPLL1 */
-        ck_dpll1_p->rate = 0;
        /* Find the highest supported frequency and enable it */
        if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
                pr_err("System frequencies not set, using default. Check your config.\n");
-                omap_writew(0x2290, DPLL_CTL);
+                /*
-                omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL);
+                 * Reprogramming the DPLL is tricky, it must be done from SRAM.
+                 */
+                omap_sram_reprogram_clock(0x2290, 0x0005);
                ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
        }
        propagate_rate(&ck_dpll1);
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
new file mode 100644
index 00000000000..a9a5146dd2d
--- /dev/null
+++ b/arch/arm/mach-omap1/common.h
@@ -0,0 +1,62 @@
+/*
+ *
+ * Header for code common to all OMAP1 machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP1_COMMON_H
+#define __ARCH_ARM_MACH_OMAP1_COMMON_H
+#include <plat/common.h>
+#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+void omap7xx_map_io(void);
+#else
+static inline void omap7xx_map_io(void)
+{
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP15XX
+void omap15xx_map_io(void);
+#else
+static inline void omap15xx_map_io(void)
+{
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+void omap16xx_map_io(void);
+#else
+static inline void omap16xx_map_io(void)
+{
+}
+#endif
+void omap1_init_early(void);
+void omap1_init_irq(void);
+void omap1_restart(char, const char *);
+extern struct sys_timer omap1_timer;
+extern bool omap_32k_timer_init(void);
+#endif /* __ARCH_ARM_MACH_OMAP1_COMMON_H */
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 475cb2f50d8..1d76a63c098 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -22,7 +22,7 @@
 #include <mach/hardware.h>
 #include <asm/mach/map.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/tc.h>
 #include <plat/board.h>
 #include <plat/mux.h>
diff --git a/arch/arm/mach-omap1/include/mach/vmalloc.h b/arch/arm/mach-omap1/include/mach/vmalloc.h
deleted file mode 100644
index 22ec4a47957..00000000000
--- a/arch/arm/mach-omap1/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  arch/arm/mach-omap1/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END     0xd8000000UL
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 7969cfda445..8e55b6fb347 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -121,7 +121,6 @@ void __init omap16xx_map_io(void)
 void omap1_init_early(void)
 {
        omap_check_revision();
-        omap_ioremap_init();
        /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort
         * on a Posted Write in the TIPB Bridge".
diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h
index 07074d79adc..79a683864a5 100644
--- a/arch/arm/mach-omap1/opp.h
+++ b/arch/arm/mach-omap1/opp.h
@@ -21,6 +21,7 @@ struct mpu_rate {
        unsigned long           pll_rate;
        __u16                   ckctl_val;
        __u16                   dpllctl_val;
+        u32                     flags;
 };
 extern struct mpu_rate omap1_rate_table[];
diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c
index 75a54651499..9cd4ddb5139 100644
--- a/arch/arm/mach-omap1/opp_data.c
+++ b/arch/arm/mach-omap1/opp_data.c
@@ -10,6 +10,7 @@
 * published by the Free Software Foundation.
 */
+#include <plat/clkdev_omap.h>
 #include "opp.h"
 /*-------------------------------------------------------------------------
@@ -20,40 +21,34 @@ struct mpu_rate omap1_rate_table[] = {
         * NOTE: Comment order here is different from bits in CKCTL value:
         * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
         */
-#if defined(CONFIG_OMAP_ARM_216MHZ)
+        { 216000000, 12000000, 216000000, 0x050d, 0x2910, /* 1/1/2/2/2/8 */
-        { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
+                        CK_1710 },
-#endif
+        { 195000000, 13000000, 195000000, 0x050e, 0x2790, /* 1/1/2/2/4/8 */
-#if defined(CONFIG_OMAP_ARM_195MHZ)
+                        CK_7XX },
-        { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
+        { 192000000, 19200000, 192000000, 0x050f, 0x2510, /* 1/1/2/2/8/8 */
-#endif
+                        CK_16XX },
-#if defined(CONFIG_OMAP_ARM_192MHZ)
+        { 192000000, 12000000, 192000000, 0x050f, 0x2810, /* 1/1/2/2/8/8 */
-        { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
+                        CK_16XX },
-        { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
+        {  96000000, 12000000, 192000000, 0x055f, 0x2810, /* 2/2/2/2/8/8 */
-        {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
+                        CK_16XX },
-        {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
+        {  48000000, 12000000, 192000000, 0x0baf, 0x2810, /* 4/4/4/8/8/8 */
-        {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
+                        CK_16XX },
-#endif
+        {  24000000, 12000000, 192000000, 0x0fff, 0x2810, /* 8/8/8/8/8/8 */
-#if defined(CONFIG_OMAP_ARM_182MHZ)
+                        CK_16XX },
-        { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
+        { 182000000, 13000000, 182000000, 0x050e, 0x2710, /* 1/1/2/2/4/8 */
-#endif
+                        CK_7XX },
-#if defined(CONFIG_OMAP_ARM_168MHZ)
+        { 168000000, 12000000, 168000000, 0x010f, 0x2710, /* 1/1/1/2/8/8 */
-        { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
+                        CK_16XX|CK_7XX },
-#endif
+        { 150000000, 12000000, 150000000, 0x010a, 0x2cb0, /* 1/1/1/2/4/4 */
-#if defined(CONFIG_OMAP_ARM_150MHZ)
+                        CK_1510 },
-        { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
+        { 120000000, 12000000, 120000000, 0x010a, 0x2510, /* 1/1/1/2/4/4 */
-#endif
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
-#if defined(CONFIG_OMAP_ARM_120MHZ)
+        {  96000000, 12000000,  96000000, 0x0005, 0x2410, /* 1/1/1/1/2/2 */
-        { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
-#endif
+        {  60000000, 12000000,  60000000, 0x0005, 0x2290, /* 1/1/1/1/2/2 */
-#if defined(CONFIG_OMAP_ARM_96MHZ)
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
-        {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
+        {  30000000, 12000000,  60000000, 0x0555, 0x2290, /* 2/2/2/2/2/2 */
-#endif
+                        CK_16XX|CK_1510|CK_310|CK_7XX },
-#if defined(CONFIG_OMAP_ARM_60MHZ)
-        {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
-#endif
-#if defined(CONFIG_OMAP_ARM_30MHZ)
-        {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
-#endif
        { 0, 0, 0, 0, 0 },
 };
diff --git a/arch/arm/mach-omap1/reset.c b/arch/arm/mach-omap1/reset.c
index ad951ee6920..91d199b6497 100644
--- a/arch/arm/mach-omap1/reset.c
+++ b/arch/arm/mach-omap1/reset.c
@@ -5,10 +5,9 @@
 #include <linux/io.h>
 #include <mach/hardware.h>
-#include <mach/system.h>
 #include <plat/prcm.h>
-void omap1_arch_reset(char mode, const char *cmd)
+void omap1_restart(char mode, const char *cmd)
 {
        /*
         * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
@@ -21,5 +20,3 @@ void omap1_arch_reset(char mode, const char *cmd)
        omap_writew(1, ARM_RSTCT1);
 }
-void (*arch_reset)(char, const char *) = omap1_arch_reset;
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index a1837771e03..b8faffa44f9 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -37,7 +37,6 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
-#include <linux/sched.h>
 #include <linux/spinlock.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -54,7 +53,7 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <plat/common.h>
+#include "common.h"
 #ifdef CONFIG_OMAP_MPU_TIMER
@@ -190,30 +189,9 @@ static __init void omap_init_mpu_timer(unsigned long rate)
 * ---------------------------------------------------------------------------
 */
-static DEFINE_CLOCK_DATA(cd);
+static u32 notrace omap_mpu_read_sched_clock(void)
-static inline unsigned long long notrace _omap_mpu_sched_clock(void)
-{
-        u32 cyc = ~omap_mpu_timer_read(1);
-        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-#ifndef CONFIG_OMAP_32K_TIMER
-unsigned long long notrace sched_clock(void)
-{
-        return _omap_mpu_sched_clock();
-}
-#else
-static unsigned long long notrace omap_mpu_sched_clock(void)
-{
-        return _omap_mpu_sched_clock();
-}
-#endif
-static void notrace mpu_update_sched_clock(void)
 {
-        u32 cyc = ~omap_mpu_timer_read(1);
+        return ~omap_mpu_timer_read(1);
-        update_sched_clock(&cd, cyc, (u32)~0);
 }
 static void __init omap_init_clocksource(unsigned long rate)
@@ -223,7 +201,7 @@ static void __init omap_init_clocksource(unsigned long rate)
                        "%s: can't register clocksource!\n";
        omap_mpu_timer_start(1, ~0, 1);
-        init_sched_clock(&cd, mpu_update_sched_clock, 32, rate);
+        setup_sched_clock(omap_mpu_read_sched_clock, 32, rate);
        if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
                        300, 32, clocksource_mmio_readl_down))
@@ -254,30 +232,6 @@ static inline void omap_mpu_timer_init(void)
 }
 #endif  /* CONFIG_OMAP_MPU_TIMER */
-#if defined(CONFIG_OMAP_MPU_TIMER) && defined(CONFIG_OMAP_32K_TIMER)
-static unsigned long long (*preferred_sched_clock)(void);
-unsigned long long notrace sched_clock(void)
-{
-        if (!preferred_sched_clock)
-                return 0;
-        return preferred_sched_clock();
-}
-static inline void preferred_sched_clock_init(bool use_32k_sched_clock)
-{
-        if (use_32k_sched_clock)
-                preferred_sched_clock = omap_32k_sched_clock;
-        else
-                preferred_sched_clock = omap_mpu_sched_clock;
-}
-#else
-static inline void preferred_sched_clock_init(bool use_32k_sched_clcok)
-{
-}
-#endif
 static inline int omap_32k_timer_usable(void)
 {
        int res = false;
@@ -299,12 +253,8 @@ static inline int omap_32k_timer_usable(void)
 */
 static void __init omap1_timer_init(void)
 {
-        if (omap_32k_timer_usable()) {
+        if (!omap_32k_timer_usable())
-                preferred_sched_clock_init(1);
-        } else {
                omap_mpu_timer_init();
-                preferred_sched_clock_init(0);
-        }
 }
 struct sys_timer omap1_timer = {
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 96604a50c4f..9a54ef4dcf5 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -52,7 +52,7 @@
 #include <asm/irq.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/dmtimer.h>
 /*
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e1293aa513d..a8ba7b96dcd 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -25,6 +25,7 @@ config ARCH_OMAP2
        depends on ARCH_OMAP2PLUS
        default y
        select CPU_V6
+        select MULTI_IRQ_HANDLER
 config ARCH_OMAP3
        bool "TI OMAP3"
@@ -36,13 +37,16 @@ config ARCH_OMAP3
        select ARCH_HAS_OPP
        select PM_OPP if PM
        select ARM_CPU_SUSPEND if PM
+        select MULTI_IRQ_HANDLER
 config ARCH_OMAP4
        bool "TI OMAP4"
        default y
        depends on ARCH_OMAP2PLUS
+        select CACHE_L2X0
        select CPU_V7
        select ARM_GIC
+        select HAVE_SMP
        select LOCAL_TIMERS if SMP
        select PL310_ERRATA_588369
        select PL310_ERRATA_727915
@@ -74,8 +78,13 @@ config SOC_OMAP3430
        default y
        select ARCH_OMAP_OTG
-config SOC_OMAPTI816X
+config SOC_OMAPTI81XX
-        bool "TI816X support"
+        bool "TI81XX support"
+        depends on ARCH_OMAP3
+        default y
+config SOC_OMAPAM33XX
+        bool "AM33XX support"
        depends on ARCH_OMAP3
        default y
@@ -312,7 +321,12 @@ config MACH_OMAP_3630SDP
 config MACH_TI8168EVM
        bool "TI8168 Evaluation Module"
-        depends on SOC_OMAPTI816X
+        depends on SOC_OMAPTI81XX
+        default y
+config MACH_TI8148EVM
+        bool "TI8148 Evaluation Module"
+        depends on SOC_OMAPTI81XX
        default y
 config MACH_OMAP_4430SDP
@@ -351,6 +365,27 @@ config OMAP3_SDRC_AC_TIMING
          wish to say no.  Selecting yes without understanding what is
          going on could result in system crashes;
+config OMAP4_ERRATA_I688
+        bool "OMAP4 errata: Async Bridge Corruption (BROKEN)"
+        depends on ARCH_OMAP4 && BROKEN
+        select ARCH_HAS_BARRIERS
+        help
+          If a data is stalled inside asynchronous bridge because of back
+          pressure, it may be accepted multiple times, creating pointer
+          misalignment that will corrupt next transfers on that data path
+          until next reset of the system (No recovery procedure once the
+          issue is hit, the path remains consistently broken). Async bridge
+          can be found on path between MPU to EMIF and MPU to L3 interconnect.
+          This situation can happen only when the idle is initiated by a
+          Master Request Disconnection (which is trigged by software when
+          executing WFI on CPU).
+          The work-around for this errata needs all the initiators connected
+          through async bridge must ensure that data path is properly drained
+          before issuing WFI. This condition will be met if one Strongly ordered
+          access is performed to the target right before executing the WFI.
+          In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
+          IO barrier ensure that there is no synchronisation loss on initiators
+          operating on both interconnect port simultaneously.
 endmenu
 endif
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b009f17dee5..fc9b238cbc1 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -11,10 +11,11 @@ hwmod-common				= omap_hwmod.o \
                                          omap_hwmod_common_data.o
 clock-common                            = clock.o clock_common_data.o \
                                          clkt_dpll.o clkt_clksel.o
+secure-common                          = omap-smc.o omap-secure.o
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common)
+obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
 obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
@@ -24,11 +25,13 @@ obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
 obj-$(CONFIG_SMP)                       += omap-smp.o omap-headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)              += timer-mpu.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
-obj-$(CONFIG_ARCH_OMAP4)                += omap44xx-smc.o omap4-common.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap4-common.o omap-wakeupgen.o \
+                                           sleep44xx.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a$(plus_sec)
-AFLAGS_omap44xx-smc.o                   :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_omap-smc.o                       :=-Wa,-march=armv7-a$(plus_sec)
+AFLAGS_sleep44xx.o                      :=-Wa,-march=armv7-a$(plus_sec)
 # Functions loaded to SRAM
 obj-$(CONFIG_SOC_OMAP2420)              += sram242x.o
@@ -62,7 +65,8 @@ obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o \
                                           cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o \
+                                           cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)   += smartreflex-class3.o
@@ -77,6 +81,7 @@ endif
 endif
 # PRCM
+obj-y                                   += prm_common.o
 obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP3)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
                                           vc3xxx_data.o vp3xxx_data.o
@@ -86,7 +91,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o \
 obj-$(CONFIG_ARCH_OMAP4)                += prcm.o cm2xxx_3xxx.o cminst44xx.o \
                                           cm44xx.o prcm_mpu44xx.o \
                                           prminst44xx.o vc44xx_data.o \
-                                           vp44xx_data.o
+                                           vp44xx_data.o prm44xx.o
 # OMAP voltage domains
 voltagedomain-common                    := voltage.o vc.o vp.o
@@ -232,6 +237,7 @@ obj-$(CONFIG_MACH_CRANEBOARD)		+= board-am3517crane.o
 obj-$(CONFIG_MACH_SBC3530)              += board-omap3stalker.o
 obj-$(CONFIG_MACH_TI8168EVM)            += board-ti8168evm.o
+obj-$(CONFIG_MACH_TI8148EVM)            += board-ti8168evm.o
 # Platform specific device init code
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index d704f0ac328..7370983f809 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -34,7 +34,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <plat/gpmc-smc91x.h>
@@ -301,6 +301,8 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
        .map_io         = omap243x_map_io,
        .init_early     = omap2430_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_2430sdp_init,
        .timer          = &omap2_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 77142c13fa1..383717ba63b 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -33,7 +33,7 @@
 #include <plat/mcspi.h>
 #include <plat/board.h>
 #include <plat/usb.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <video/omapdss.h>
@@ -475,106 +475,8 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-static struct omap_device_pad serial1_pads[] __initdata = {
-        /*
-         * Note that off output enable is an active low
-         * signal. So setting this means pin is a
-         * input enabled in off mode
-         */
-        OMAP_MUX_STATIC("uart1_cts.uart1_cts",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart1_rts.uart1_rts",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart1_rx.uart1_rx",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart1_tx.uart1_tx",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial2_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
-                         OMAP_PIN_INPUT_PULLUP |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial3_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
-                         OMAP_PIN_INPUT_PULLDOWN |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
-                         OMAP_PIN_INPUT |
-                         OMAP_PIN_OFF_INPUT_PULLDOWN |
-                         OMAP_OFFOUT_EN |
-                         OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
-                         OMAP_PIN_OUTPUT |
-                         OMAP_OFF_EN |
-                         OMAP_MUX_MODE0),
-};
-static struct omap_board_data serial1_data __initdata = {
-        .id             = 0,
-        .pads           = serial1_pads,
-        .pads_cnt       = ARRAY_SIZE(serial1_pads),
-};
-static struct omap_board_data serial2_data __initdata = {
-        .id             = 1,
-        .pads           = serial2_pads,
-        .pads_cnt       = ARRAY_SIZE(serial2_pads),
-};
-static struct omap_board_data serial3_data __initdata = {
-        .id             = 2,
-        .pads           = serial3_pads,
-        .pads_cnt       = ARRAY_SIZE(serial3_pads),
-};
-static inline void board_serial_init(void)
-{
-        omap_serial_init_port(&serial1_data);
-        omap_serial_init_port(&serial2_data);
-        omap_serial_init_port(&serial3_data);
-}
 #else
 #define board_mux       NULL
-static inline void board_serial_init(void)
-{
-        omap_serial_init();
-}
 #endif
 /*
@@ -711,7 +613,7 @@ static void __init omap_3430sdp_init(void)
        else
                gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
        omap_ads7846_init(1, gpio_pendown, 310, NULL);
-        board_serial_init();
+        omap_serial_init();
        omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
        usb_musb_init(NULL);
        board_smc91x_init();
@@ -728,6 +630,8 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_3430sdp_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index f552305162f..6ef350d1ae4 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -16,7 +16,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 #include <plat/gpmc-smc91x.h>
 #include <plat/usb.h>
@@ -215,6 +215,8 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_sdp_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 515646886b5..39fba9df17f 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -27,13 +27,13 @@
 #include <linux/leds_pwm.h>
 #include <mach/hardware.h>
-#include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <plat/omap4-keypad.h>
@@ -372,11 +372,17 @@ static struct platform_device sdp4430_vbat = {
        },
 };
+static struct platform_device sdp4430_dmic_codec = {
+        .name   = "dmic-codec",
+        .id     = -1,
+};
 static struct platform_device *sdp4430_devices[] __initdata = {
        &sdp4430_gpio_keys_device,
        &sdp4430_leds_gpio,
        &sdp4430_leds_pwm,
        &sdp4430_vbat,
+        &sdp4430_dmic_codec,
 };
 static struct omap_musb_board_data musb_board_data = {
@@ -404,6 +410,7 @@ static struct omap2_hsmmc_info mmc[] = {
        {
                .mmc            = 5,
                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+                .pm_caps        = MMC_PM_KEEP_POWER,
                .gpio_cd        = -EINVAL,
                .gpio_wp        = -EINVAL,
                .ocr_mask       = MMC_VDD_165_195,
@@ -595,20 +602,6 @@ static void __init omap_sfh7741prox_init(void)
                        __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
 }
-static void sdp4430_hdmi_mux_init(void)
-{
-        /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
-        omap_mux_init_signal("hdmi_hpd",
-                        OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("hdmi_cec",
-                        OMAP_PIN_INPUT_PULLUP);
-        /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
-        omap_mux_init_signal("hdmi_ddc_scl",
-                        OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("hdmi_ddc_sda",
-                        OMAP_PIN_INPUT_PULLUP);
-}
 static struct gpio sdp4430_hdmi_gpios[] = {
        { HDMI_GPIO_HPD,        GPIOF_OUT_INIT_HIGH,    "hdmi_gpio_hpd"   },
        { HDMI_GPIO_LS_OE,      GPIOF_OUT_INIT_HIGH,    "hdmi_gpio_ls_oe" },
@@ -826,9 +819,16 @@ static void omap_4430sdp_display_init(void)
                pr_err("%s: Could not get display_sel GPIO\n", __func__);
        sdp4430_lcd_init();
-        sdp4430_hdmi_mux_init();
        sdp4430_picodlp_init();
        omap_display_init(&sdp4430_dss_data);
+        /*
+         * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
+         * later have external pull up on the HDMI I2C lines
+         */
+        if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
+                omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
+        else
+                omap_hdmi_init(0);
 }
 #ifdef CONFIG_OMAP_MUX
@@ -837,74 +837,8 @@ static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-static struct omap_device_pad serial2_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial3_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial4_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart4_rx.uart4_rx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart4_tx.uart4_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_board_data serial2_data __initdata = {
-        .id             = 1,
-        .pads           = serial2_pads,
-        .pads_cnt       = ARRAY_SIZE(serial2_pads),
-};
-static struct omap_board_data serial3_data __initdata = {
-        .id             = 2,
-        .pads           = serial3_pads,
-        .pads_cnt       = ARRAY_SIZE(serial3_pads),
-};
-static struct omap_board_data serial4_data __initdata = {
-        .id             = 3,
-        .pads           = serial4_pads,
-        .pads_cnt       = ARRAY_SIZE(serial4_pads),
-};
-static inline void board_serial_init(void)
-{
-        struct omap_board_data bdata;
-        bdata.flags     = 0;
-        bdata.pads      = NULL;
-        bdata.pads_cnt  = 0;
-        bdata.id        = 0;
-        /* pass dummy data for UART1 */
-        omap_serial_init_port(&bdata);
-        omap_serial_init_port(&serial2_data);
-        omap_serial_init_port(&serial3_data);
-        omap_serial_init_port(&serial4_data);
-}
 #else
 #define board_mux       NULL
-static inline void board_serial_init(void)
-{
-        omap_serial_init();
-}
 #endif
 static void omap4_sdp4430_wifi_mux_init(void)
@@ -954,7 +888,7 @@ static void __init omap_4430sdp_init(void)
        omap4_i2c_init();
        omap_sfh7741prox_init();
        platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
-        board_serial_init();
+        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
        omap4_sdp4430_wifi_init();
        omap4_twl6030_hsmmc_init(mmc);
@@ -984,6 +918,8 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = omap_4430sdp_init,
        .timer          = &omap4_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 7834536ab41..c3851e8de28 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -27,7 +27,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include "mux.h"
@@ -98,6 +98,8 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
        .map_io         = omap3_map_io,
        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = am3517_crane_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index d314f033c9d..4b1cfe32e6b 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -24,6 +24,7 @@
 #include <linux/i2c/pca953x.h>
 #include <linux/can/platform/ti_hecc.h>
 #include <linux/davinci_emac.h>
+#include <linux/mmc/host.h>
 #include <mach/hardware.h>
 #include <mach/am35xx.h>
@@ -32,7 +33,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
@@ -40,6 +41,7 @@
 #include "mux.h"
 #include "control.h"
+#include "hsmmc.h"
 #define AM35XX_EVM_MDIO_FREQUENCY       (1000000)
@@ -455,6 +457,23 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
 static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
 };
+static struct omap2_hsmmc_info mmc[] = {
+        {
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = 127,
+                .gpio_wp        = 126,
+        },
+        {
+                .mmc            = 2,
+                .caps           = MMC_CAP_4_BIT_DATA,
+                .gpio_cd        = 128,
+                .gpio_wp        = 129,
+        },
+        {}      /* Terminator */
+};
 static void __init am3517_evm_init(void)
 {
        omap_board_config = am3517_evm_config;
@@ -483,6 +502,9 @@ static void __init am3517_evm_init(void)
        /* MUSB */
        am3517_evm_musb_init();
+        /* MMC init function */
+        omap2_hsmmc_init(mmc);
 }
 MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
@@ -491,6 +513,8 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
        .map_io         = omap3_map_io,
        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = am3517_evm_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index de8134b7f58..ac773829941 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -37,7 +37,7 @@
 #include <plat/led.h>
 #include <plat/usb.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <video/omapdss.h>
@@ -354,6 +354,8 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_apollon_init,
        .timer          = &omap2_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index bd1bcacb40f..e921e3be24a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -37,7 +37,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/nand.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
@@ -53,7 +53,8 @@
 #include "hsmmc.h"
 #include "common-board-devices.h"
-#define CM_T35_GPIO_PENDOWN     57
+#define CM_T35_GPIO_PENDOWN             57
+#define SB_T35_USB_HUB_RESET_GPIO       167
 #define CM_T35_SMSC911X_CS      5
 #define CM_T35_SMSC911X_GPIO    163
@@ -339,8 +340,10 @@ static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
 };
-static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
+static struct regulator_consumer_supply cm_t35_vio_supplies[] = {
-        REGULATOR_SUPPLY("vdvi", "omapdss"),
+        REGULATOR_SUPPLY("vcc", "spi1.0"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
 };
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -373,6 +376,19 @@ static struct regulator_init_data cm_t35_vsim = {
        .consumer_supplies      = cm_t35_vsim_supply,
 };
+static struct regulator_init_data cm_t35_vio = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(cm_t35_vio_supplies),
+        .consumer_supplies      = cm_t35_vio_supplies,
+};
 static uint32_t cm_t35_keymap[] = {
        KEY(0, 0, KEY_A),       KEY(0, 1, KEY_B),       KEY(0, 2, KEY_LEFT),
        KEY(1, 0, KEY_UP),      KEY(1, 1, KEY_ENTER),   KEY(1, 2, KEY_DOWN),
@@ -421,6 +437,23 @@ static struct usbhs_omap_board_data usbhs_bdata __initdata = {
        .reset_gpio_port[2]  = -EINVAL
 };
+static void cm_t35_init_usbh(void)
+{
+        int err;
+        err = gpio_request_one(SB_T35_USB_HUB_RESET_GPIO,
+                               GPIOF_OUT_INIT_LOW, "usb hub rst");
+        if (err) {
+                pr_err("SB-T35: usb hub rst gpio request failed: %d\n", err);
+        } else {
+                udelay(10);
+                gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
+                msleep(1);
+        }
+        usbhs_init(&usbhs_bdata);
+}
 static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
                                 unsigned ngpio)
 {
@@ -456,17 +489,14 @@ static struct twl4030_platform_data cm_t35_twldata = {
        .gpio           = &cm_t35_gpio_data,
        .vmmc1          = &cm_t35_vmmc1,
        .vsim           = &cm_t35_vsim,
+        .vio            = &cm_t35_vio,
 };
 static void __init cm_t35_init_i2c(void)
 {
        omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
-                        TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+                              TWL_COMMON_REGULATOR_VDAC |
+                              TWL_COMMON_PDATA_AUDIO);
-        cm_t35_twldata.vpll2->constraints.name = "VDVI";
-        cm_t35_twldata.vpll2->num_consumer_supplies =
-                                                ARRAY_SIZE(cm_t35_vdvi_supply);
-        cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
        omap3_pmic_init("tps65930", &cm_t35_twldata);
 }
@@ -570,24 +600,28 @@ static void __init cm_t3x_common_dss_mux_init(int mux_mode)
 static void __init cm_t35_init_mux(void)
 {
-        omap_mux_init_signal("gpio_70", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+        int mux_mode = OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT;
-        omap_mux_init_signal("gpio_71", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("gpio_72", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("dss_data0.dss_data0", mux_mode);
-        omap_mux_init_signal("gpio_73", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("dss_data1.dss_data1", mux_mode);
-        omap_mux_init_signal("gpio_74", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("dss_data2.dss_data2", mux_mode);
-        omap_mux_init_signal("gpio_75", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("dss_data3.dss_data3", mux_mode);
-        cm_t3x_common_dss_mux_init(OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("dss_data4.dss_data4", mux_mode);
+        omap_mux_init_signal("dss_data5.dss_data5", mux_mode);
+        cm_t3x_common_dss_mux_init(mux_mode);
 }
 static void __init cm_t3730_init_mux(void)
 {
-        omap_mux_init_signal("sys_boot0", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+        int mux_mode = OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT;
-        omap_mux_init_signal("sys_boot1", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
-        omap_mux_init_signal("sys_boot3", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sys_boot0", mux_mode);
-        omap_mux_init_signal("sys_boot4", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sys_boot1", mux_mode);
-        omap_mux_init_signal("sys_boot5", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sys_boot3", mux_mode);
-        omap_mux_init_signal("sys_boot6", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sys_boot4", mux_mode);
-        cm_t3x_common_dss_mux_init(OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+        omap_mux_init_signal("sys_boot5", mux_mode);
+        omap_mux_init_signal("sys_boot6", mux_mode);
+        cm_t3x_common_dss_mux_init(mux_mode);
 }
 #else
 static inline void cm_t35_init_mux(void) {}
@@ -612,7 +646,7 @@ static void __init cm_t3x_common_init(void)
        cm_t35_init_display();
        usb_musb_init(NULL);
-        usbhs_init(&usbhs_bdata);
+        cm_t35_init_usbh();
 }
 static void __init cm_t35_init(void)
@@ -634,8 +668,10 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t35_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
 MACHINE_START(CM_T3730, "Compulab CM-T3730")
@@ -644,6 +680,8 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t3730_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 3f4dc662684..f36d694d215 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -39,7 +39,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include <plat/nand.h>
 #include <plat/gpmc.h>
@@ -299,6 +299,8 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
        .map_io         = omap3_map_io,
        .init_early     = am35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = cm_t3517_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 90154e411da..e873063f4fd 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -41,7 +41,7 @@
 #include <asm/mach/flash.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
@@ -660,6 +660,8 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = devkit8000_init,
        .timer          = &omap3_secure_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index fb55fa3dad5..d5875606048 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -20,8 +20,7 @@
 #include <asm/mach/arch.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
-#include <mach/omap4-common.h>
 #include "common-board-devices.h"
 /*
@@ -70,7 +69,6 @@ static void __init omap_generic_init(void)
        if (node)
                irq_domain_add_simple(node, 0);
-        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
        of_platform_populate(NULL, omap_dt_match_table, NULL, NULL);
@@ -107,6 +105,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
        .init_machine   = omap_generic_init,
        .timer          = &omap2_timer,
        .dt_compat      = omap242x_boards_compat,
+        .restart        = omap_prcm_restart,
 MACHINE_END
 #endif
@@ -122,9 +121,11 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
        .map_io         = omap243x_map_io,
        .init_early     = omap2430_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_generic_init,
        .timer          = &omap2_timer,
        .dt_compat      = omap243x_boards_compat,
+        .restart        = omap_prcm_restart,
 MACHINE_END
 #endif
@@ -143,6 +144,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
        .init_machine   = omap3_init,
        .timer          = &omap3_timer,
        .dt_compat      = omap3_boards_compat,
+        .restart        = omap_prcm_restart,
 MACHINE_END
 #endif
@@ -161,5 +163,6 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
        .init_machine   = omap4_init,
        .timer          = &omap4_timer,
        .dt_compat      = omap4_boards_compat,
+        .restart        = omap_prcm_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 8b351d92a1c..54af800d143 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -34,7 +34,7 @@
 #include <plat/usb.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/menelaus.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
@@ -396,6 +396,8 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = omap_h4_init,
        .timer          = &omap2_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index d0a3f78a9b6..a59ace0ed56 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -28,7 +28,7 @@
 #include <asm/mach/arch.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/usb.h>
 #include <video/omapdss.h>
@@ -672,8 +672,10 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = igep_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
 MACHINE_START(IGEP0030, "IGEP OMAP3 module")
@@ -682,6 +684,8 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = igep_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index e179da0c4da..2d2a61f7dcb 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -36,7 +36,7 @@
 #include <plat/mcspi.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <mach/board-zoom.h>
@@ -434,6 +434,8 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_ldp_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index e9d5f4a3d06..42a4d11fad2 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -26,7 +26,7 @@
 #include <asm/mach-types.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/menelaus.h>
 #include <mach/irqs.h>
 #include <plat/mcspi.h>
@@ -46,7 +46,7 @@ static struct device *mmc_device;
 #define TUSB6010_GPIO_ENABLE    0
 #define TUSB6010_DMACHAN        0x3f
-#ifdef CONFIG_USB_MUSB_TUSB6010
+#if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_TUSB6010_MODULE)
 /*
 * Enable or disable power to TUSB6010. When enabling, turn on 3.3 V and
 * 1.5 V voltage regulators of PM companion chip. Companion chip will then
@@ -644,15 +644,15 @@ static inline void board_serial_init(void)
        bdata.pads_cnt = 0;
        bdata.id = 0;
-        omap_serial_init_port(&bdata);
+        omap_serial_init_port(&bdata, NULL);
        bdata.id = 1;
-        omap_serial_init_port(&bdata);
+        omap_serial_init_port(&bdata, NULL);
        bdata.id = 2;
        bdata.pads = serial2_pads;
        bdata.pads_cnt = ARRAY_SIZE(serial2_pads);
-        omap_serial_init_port(&bdata);
+        omap_serial_init_port(&bdata, NULL);
 }
 #else
@@ -689,8 +689,10 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
 MACHINE_START(NOKIA_N810, "Nokia N810")
@@ -699,8 +701,10 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
 MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
@@ -709,6 +713,8 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
        .map_io         = omap242x_map_io,
        .init_early     = omap2420_init_early,
        .init_irq       = omap2_init_irq,
+        .handle_irq     = omap2_intc_handle_irq,
        .init_machine   = n8x0_init_machine,
        .timer          = &omap2_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 4a71cb7e42d..7ffcd2839e7 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -40,7 +40,7 @@
 #include <asm/mach/flash.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-dvi.h>
 #include <plat/gpmc.h>
@@ -559,6 +559,8 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
        .map_io         = omap3_map_io,
        .init_early     = omap3_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_beagle_init,
        .timer          = &omap3_secure_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index ec00b2ec702..003fe34c934 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -43,7 +43,7 @@
 #include <plat/board.h>
 #include <plat/usb.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/mcspi.h>
 #include <video/omapdss.h>
 #include <video/omap-panel-dvi.h>
@@ -681,6 +681,8 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_evm_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 7c0f193f246..4198dd017d8 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -40,7 +40,7 @@
 #include <plat/mux.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc-smsc911x.h>
 #include <plat/gpmc.h>
 #include <plat/sdrc.h>
@@ -208,8 +208,10 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3logic_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
 MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
@@ -217,6 +219,8 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3logic_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index f7811f4cfc3..1644b73017f 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -41,7 +41,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <mach/hardware.h>
 #include <plat/mcspi.h>
 #include <plat/usb.h>
@@ -606,6 +606,8 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3pandora_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index ddb7d6663c6..cb089a46f62 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -35,7 +35,7 @@
 #include <asm/mach/flash.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
@@ -454,6 +454,8 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
        .map_io                 = omap3_map_io,
        .init_early             = omap35xx_init_early,
        .init_irq               = omap3_init_irq,
+        .handle_irq             = omap3_intc_handle_irq,
        .init_machine           = omap3_stalker_init,
        .timer                  = &omap3_secure_timer,
+        .restart                = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index a2d0d1971e2..a0b851aafcc 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -44,7 +44,7 @@
 #include <asm/mach/flash.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
@@ -381,6 +381,8 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap3_touchbook_init,
        .timer          = &omap3_secure_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index a8c2c4263e3..30ad40db2cf 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -30,14 +30,14 @@
 #include <linux/wl12xx.h>
 #include <mach/hardware.h>
-#include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <video/omapdss.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <video/omap-panel-dvi.h>
@@ -364,74 +364,8 @@ static struct omap_board_mux board_mux[] __initdata = {
        { .reg_offset = OMAP_MUX_TERMINATOR },
 };
-static struct omap_device_pad serial2_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart2_cts.uart2_cts",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rts.uart2_rts",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_rx.uart2_rx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart2_tx.uart2_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial3_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart3_cts_rctx.uart3_cts_rctx",
-                         OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rts_sd.uart3_rts_sd",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_rx_irrx.uart3_rx_irrx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart3_tx_irtx.uart3_tx_irtx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_device_pad serial4_pads[] __initdata = {
-        OMAP_MUX_STATIC("uart4_rx.uart4_rx",
-                         OMAP_PIN_INPUT | OMAP_MUX_MODE0),
-        OMAP_MUX_STATIC("uart4_tx.uart4_tx",
-                         OMAP_PIN_OUTPUT | OMAP_MUX_MODE0),
-};
-static struct omap_board_data serial2_data __initdata = {
-        .id             = 1,
-        .pads           = serial2_pads,
-        .pads_cnt       = ARRAY_SIZE(serial2_pads),
-};
-static struct omap_board_data serial3_data __initdata = {
-        .id             = 2,
-        .pads           = serial3_pads,
-        .pads_cnt       = ARRAY_SIZE(serial3_pads),
-};
-static struct omap_board_data serial4_data __initdata = {
-        .id             = 3,
-        .pads           = serial4_pads,
-        .pads_cnt       = ARRAY_SIZE(serial4_pads),
-};
-static inline void board_serial_init(void)
-{
-        struct omap_board_data bdata;
-        bdata.flags     = 0;
-        bdata.pads      = NULL;
-        bdata.pads_cnt  = 0;
-        bdata.id        = 0;
-        /* pass dummy data for UART1 */
-        omap_serial_init_port(&bdata);
-        omap_serial_init_port(&serial2_data);
-        omap_serial_init_port(&serial3_data);
-        omap_serial_init_port(&serial4_data);
-}
 #else
 #define board_mux       NULL
-static inline void board_serial_init(void)
-{
-        omap_serial_init();
-}
 #endif
 /* Display DVI */
@@ -478,21 +412,6 @@ int __init omap4_panda_dvi_init(void)
        return r;
 }
-static void omap4_panda_hdmi_mux_init(void)
-{
-        /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
-        omap_mux_init_signal("hdmi_hpd",
-                        OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("hdmi_cec",
-                        OMAP_PIN_INPUT_PULLUP);
-        /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
-        omap_mux_init_signal("hdmi_ddc_scl",
-                        OMAP_PIN_INPUT_PULLUP);
-        omap_mux_init_signal("hdmi_ddc_sda",
-                        OMAP_PIN_INPUT_PULLUP);
-}
 static struct gpio panda_hdmi_gpios[] = {
        { HDMI_GPIO_HPD,        GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd"   },
        { HDMI_GPIO_LS_OE,      GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
@@ -544,8 +463,16 @@ void omap4_panda_display_init(void)
        if (r)
                pr_err("error initializing panda DVI\n");
-        omap4_panda_hdmi_mux_init();
        omap_display_init(&omap4_panda_dss_data);
+        /*
+         * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
+         * later have external pull up on the HDMI I2C lines
+         */
+        if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
+                omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
+        else
+                omap_hdmi_init(0);
 }
 static void __init omap4_panda_init(void)
@@ -562,7 +489,7 @@ static void __init omap4_panda_init(void)
        omap4_panda_i2c_init();
        platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
        platform_device_register(&omap_vwlan_device);
-        board_serial_init();
+        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
        omap4_twl6030_hsmmc_init(mmc);
        omap4_ehci_init();
@@ -577,6 +504,8 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
        .map_io         = omap4_map_io,
        .init_early     = omap4430_init_early,
        .init_irq       = gic_init_irq,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = omap4_panda_init,
        .timer          = &omap4_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4cf7aeabab8..52c0cef7716 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -43,7 +43,7 @@
 #include <asm/mach/map.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <video/omapdss.h>
 #include <video/omap-panel-generic-dpi.h>
 #include <video/omap-panel-dvi.h>
@@ -562,6 +562,8 @@ MACHINE_START(OVERO, "Gumstix Overo")
        .map_io         = omap3_map_io,
        .init_early     = omap35xx_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = overo_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 616fb39763b..8678b386c6a 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -25,7 +25,7 @@
 #include <plat/mmc.h>
 #include <plat/usb.h>
 #include <plat/gpmc.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/onenand.h>
 #include "mux.h"
@@ -149,6 +149,8 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = rm680_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index c15c5c9c908..acb4e77b39e 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -15,6 +15,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
 #include <linux/wl12xx.h>
+#include <linux/spi/tsc2005.h>
 #include <linux/i2c.h>
 #include <linux/i2c/twl.h>
 #include <linux/clk.h>
@@ -27,7 +28,7 @@
 #include <plat/mcspi.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <plat/onenand.h>
@@ -58,6 +59,9 @@
 #define RX51_USB_TRANSCEIVER_RST_GPIO   67
+#define RX51_TSC2005_RESET_GPIO         104
+#define RX51_TSC2005_IRQ_GPIO           100
 /* list all spi devices here */
 enum {
        RX51_SPI_WL1251,
@@ -66,6 +70,7 @@ enum {
 };
 static struct wl12xx_platform_data wl1251_pdata;
+static struct tsc2005_platform_data tsc2005_pdata;
 #if defined(CONFIG_SENSORS_TSL2563) || defined(CONFIG_SENSORS_TSL2563_MODULE)
 static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
@@ -167,10 +172,10 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
                .modalias               = "tsc2005",
                .bus_num                = 1,
                .chip_select            = 0,
-                /* .irq = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),*/
+                .irq                    = OMAP_GPIO_IRQ(RX51_TSC2005_IRQ_GPIO),
                .max_speed_hz           = 6000000,
                .controller_data        = &tsc2005_mcspi_config,
-                /* .platform_data = &tsc2005_config,*/
+                .platform_data          = &tsc2005_pdata,
        },
 };
@@ -940,6 +945,9 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
        },
 #endif
        {
+                I2C_BOARD_INFO("bq27200", 0x55),
+        },
+        {
                I2C_BOARD_INFO("tpa6130a2", 0x60),
                .platform_data = &rx51_tpa6130a2_data,
        }
@@ -1086,6 +1094,42 @@ error:
         */
 }
+static struct tsc2005_platform_data tsc2005_pdata = {
+        .ts_pressure_max        = 2048,
+        .ts_pressure_fudge      = 2,
+        .ts_x_max               = 4096,
+        .ts_x_fudge             = 4,
+        .ts_y_max               = 4096,
+        .ts_y_fudge             = 7,
+        .ts_x_plate_ohm         = 280,
+        .esd_timeout_ms         = 8000,
+};
+static void rx51_tsc2005_set_reset(bool enable)
+{
+        gpio_set_value(RX51_TSC2005_RESET_GPIO, enable);
+}
+static void __init rx51_init_tsc2005(void)
+{
+        int r;
+        r = gpio_request_one(RX51_TSC2005_IRQ_GPIO, GPIOF_IN, "tsc2005 IRQ");
+        if (r < 0) {
+                printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 IRQ");
+                rx51_peripherals_spi_board_info[RX51_SPI_TSC2005].irq = 0;
+        }
+        r = gpio_request_one(RX51_TSC2005_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
+                "tsc2005 reset");
+        if (r >= 0) {
+                tsc2005_pdata.set_reset = rx51_tsc2005_set_reset;
+        } else {
+                printk(KERN_ERR "unable to get %s GPIO\n", "tsc2005 reset");
+                tsc2005_pdata.esd_timeout_ms = 0;
+        }
+}
 void __init rx51_peripherals_init(void)
 {
        rx51_i2c_init();
@@ -1094,6 +1138,7 @@ void __init rx51_peripherals_init(void)
        board_smc91x_init();
        rx51_add_gpio_keys();
        rx51_init_wl1251();
+        rx51_init_tsc2005();
        rx51_init_si4713();
        spi_register_board_info(rx51_peripherals_spi_board_info,
                                ARRAY_SIZE(rx51_peripherals_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 4af7c4b2881..27f01f051df 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -25,7 +25,7 @@
 #include <plat/mcspi.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
@@ -127,6 +127,8 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = rx51_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index e6ee8842285..ab9a7a9e9d6 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -1,5 +1,5 @@
 /*
- * Code for TI8168 EVM.
+ * Code for TI8168/TI8148 EVM.
 *
 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
 *
@@ -22,30 +22,46 @@
 #include <plat/irqs.h>
 #include <plat/board.h>
-#include <plat/common.h>
+#include "common.h"
+#include <plat/usb.h>
-static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
+static struct omap_musb_board_data musb_board_data = {
+        .set_phy_power  = ti81xx_musb_phy_power,
+        .interface_type = MUSB_INTERFACE_ULPI,
+        .mode           = MUSB_OTG,
+        .power          = 500,
 };
-static void __init ti8168_evm_init(void)
+static struct omap_board_config_kernel ti81xx_evm_config[] __initdata = {
+};
+static void __init ti81xx_evm_init(void)
 {
        omap_serial_init();
        omap_sdrc_init(NULL, NULL);
-        omap_board_config = ti8168_evm_config;
+        omap_board_config = ti81xx_evm_config;
-        omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
+        omap_board_config_size = ARRAY_SIZE(ti81xx_evm_config);
-}
+        usb_musb_init(&musb_board_data);
-static void __init ti8168_evm_map_io(void)
-{
-        omapti816x_map_common_io();
 }
 MACHINE_START(TI8168EVM, "ti8168evm")
        /* Maintainer: Texas Instruments */
        .atag_offset    = 0x100,
-        .map_io         = ti8168_evm_map_io,
+        .map_io         = ti81xx_map_io,
-        .init_early     = ti816x_init_early,
+        .init_early     = ti81xx_init_early,
-        .init_irq       = ti816x_init_irq,
+        .init_irq       = ti81xx_init_irq,
+        .timer          = &omap3_timer,
+        .init_machine   = ti81xx_evm_init,
+        .restart        = omap_prcm_restart,
+MACHINE_END
+MACHINE_START(TI8148EVM, "ti8148evm")
+        /* Maintainer: Texas Instruments */
+        .atag_offset    = 0x100,
+        .map_io         = ti81xx_map_io,
+        .init_early     = ti81xx_init_early,
+        .init_irq       = ti81xx_init_irq,
        .timer          = &omap3_timer,
-        .init_machine   = ti8168_evm_init,
+        .init_machine   = ti81xx_evm_init,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 6d0aa4fcb7c..8d7ce11cfea 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -24,7 +24,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/usb.h>
 #include <mach/board-zoom.h>
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index be6684dc4f5..5c20bcc57f2 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -21,7 +21,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 #include <plat/usb.h>
@@ -135,8 +135,10 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
        .map_io         = omap3_map_io,
        .init_early     = omap3430_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
 MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
@@ -145,6 +147,8 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
        .map_io         = omap3_map_io,
        .init_early     = omap3630_init_early,
        .init_irq       = omap3_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
        .init_machine   = omap_zoom_init,
        .timer          = &omap3_timer,
+        .restart        = omap_prcm_restart,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1f3481f8d69..f57ed5baecc 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -35,7 +35,7 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
-u8 cpu_mask;
+u16 cpu_mask;
 /*
 * clkdm_control: if true, then when a clock is enabled in the
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 2311bc21722..b8c2a686481 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -132,7 +132,7 @@ void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
                               const char *core_ck_name,
                               const char *mpu_ck_name);
-extern u8 cpu_mask;
+extern u16 cpu_mask;
 extern const struct clkops clkops_omap2_dflt_wait;
 extern const struct clkops clkops_dummy;
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 5d0064a4fb5..d75e5f6b8a0 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2480,6 +2480,16 @@ static struct clk uart4_fck = {
        .recalc         = &followparent_recalc,
 };
+static struct clk uart4_fck_am35xx = {
+        .name           = "uart4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &per_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = OMAP3430_EN_UART4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
+};
 static struct clk gpt2_fck = {
        .name           = "gpt2_fck",
        .ops            = &clkops_omap2_dflt_wait,
@@ -3287,7 +3297,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
        CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
@@ -3323,7 +3333,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
        CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
@@ -3369,20 +3379,18 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "hs_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "fs_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs-omap.0",     "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs-omap.0",     "init_60m_fclk",        &dummy_ck,      CK_3XXX),
+        CLK("usbhs_omap",       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
@@ -3403,6 +3411,7 @@ static struct omap_clk omap3xxx_clks[] = {
        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
        CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
+        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_3505 | CK_3517),
        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
@@ -3517,6 +3526,10 @@ int __init omap3xxx_clk_init(void)
        } else if (cpu_is_ti816x()) {
                cpu_mask = RATE_IN_TI816X;
                cpu_clkflg = CK_TI816X;
+        } else if (cpu_is_am33xx()) {
+                cpu_mask = RATE_IN_AM33XX;
+        } else if (cpu_is_ti814x()) {
+                cpu_mask = RATE_IN_TI814X;
        } else if (cpu_is_omap34xx()) {
                if (omap_rev() == OMAP3430_REV_ES1_0) {
                        cpu_mask = RATE_IN_3430ES1;
@@ -3600,7 +3613,7 @@ int __init omap3xxx_clk_init(void)
         * Lock DPLL5 -- here only until other device init code can
         * handle this
         */
-        if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
+        if (!cpu_is_ti81xx() && (omap_rev() >= OMAP3430_REV_ES2_0))
                omap3_clk_lock_dpll5();
        /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 0798a802497..08e86d793a1 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -1206,6 +1206,14 @@ static const struct clksel ocp_abe_iclk_div[] = {
        { .parent = NULL },
 };
+static struct clk mpu_periphclk = {
+        .name           = "mpu_periphclk",
+        .parent         = &dpll_mpu_ck,
+        .ops            = &clkops_null,
+        .fixed_div      = 2,
+        .recalc         = &omap_fixed_divisor_recalc,
+};
 static struct clk ocp_abe_iclk = {
        .name           = "ocp_abe_iclk",
        .parent         = &aess_fclk,
@@ -3189,6 +3197,7 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
+        CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
@@ -3295,7 +3304,7 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "uart2_fck",                    &uart2_fck,     CK_443X),
        CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
        CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
-        CLK("usbhs-omap.0",     "fs_fck",               &usb_host_fs_fck,       CK_443X),
+        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
@@ -3306,7 +3315,7 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
-        CLK("usbhs-omap.0",     "hs_fck",               &usb_host_hs_fck,       CK_443X),
+        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
        CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
@@ -3314,7 +3323,7 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
-        CLK("usbhs-omap.0",     "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
        CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
@@ -3374,8 +3383,8 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
        CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
        CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
-        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
+        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
-        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
+        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
        CLK("omap_timer.1",     "32k_ck",       &sys_32k_ck,    CK_443X),
        CLK("omap_timer.2",     "32k_ck",       &sys_32k_ck,    CK_443X),
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 38830d8d478..04d39cdd211 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include "cm.h"
 #include "cm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index e96f53ea01a..6a836303252 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include "cm.h"
 #include "cm1_44xx.h"
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index eb2a472bbf4..6204deaf85b 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -20,7 +20,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include "cm.h"
 #include "cm1_44xx.h"
diff --git a/arch/arm/mach-omap2/common.c b/arch/arm/mach-omap2/common.c
index 110e5b9db14..aaf421178c9 100644
--- a/arch/arm/mach-omap2/common.c
+++ b/arch/arm/mach-omap2/common.c
@@ -17,7 +17,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/board.h>
 #include <plat/mux.h>
@@ -110,23 +110,49 @@ void __init omap3_map_io(void)
 /*
 * Adjust TAP register base such that omap3_check_revision accesses the correct
- * TI816X register for checking device ID (it adds 0x204 to tap base while
+ * TI81XX register for checking device ID (it adds 0x204 to tap base while
- * TI816X DEVICE ID register is at offset 0x600 from control base).
+ * TI81XX DEVICE ID register is at offset 0x600 from control base).
 */
-#define TI816X_TAP_BASE         (TI816X_CTRL_BASE + \
+#define TI81XX_TAP_BASE         (TI81XX_CTRL_BASE + \
-                                TI816X_CONTROL_DEVICE_ID - 0x204)
+                                TI81XX_CONTROL_DEVICE_ID - 0x204)
-static struct omap_globals ti816x_globals = {
+static struct omap_globals ti81xx_globals = {
        .class  = OMAP343X_CLASS,
-        .tap    = OMAP2_L4_IO_ADDRESS(TI816X_TAP_BASE),
+        .tap    = OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE),
-        .ctrl   = OMAP2_L4_IO_ADDRESS(TI816X_CTRL_BASE),
+        .ctrl   = OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
-        .prm    = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
+        .prm    = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
-        .cm     = OMAP2_L4_IO_ADDRESS(TI816X_PRCM_BASE),
+        .cm     = OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE),
 };
-void __init omap2_set_globals_ti816x(void)
+void __init omap2_set_globals_ti81xx(void)
 {
-        __omap2_set_globals(&ti816x_globals);
+        __omap2_set_globals(&ti81xx_globals);
+}
+void __init ti81xx_map_io(void)
+{
+        omapti81xx_map_common_io();
+}
+#define AM33XX_TAP_BASE         (AM33XX_CTRL_BASE + \
+                                TI81XX_CONTROL_DEVICE_ID - 0x204)
+static struct omap_globals am33xx_globals = {
+        .class  = AM335X_CLASS,
+        .tap    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE),
+        .ctrl   = AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
+        .prm    = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+        .cm     = AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE),
+};
+void __init omap2_set_globals_am33xx(void)
+{
+        __omap2_set_globals(&am33xx_globals);
+}
+void __init am33xx_map_io(void)
+{
+        omapam33xx_map_common_io();
 }
 #endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
new file mode 100644
index 00000000000..febffde2ff1
--- /dev/null
+++ b/arch/arm/mach-omap2/common.h
@@ -0,0 +1,239 @@
+/*
+ * Header for code common to all OMAP2+ machines.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
+#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
+#ifndef __ASSEMBLER__
+#include <linux/delay.h>
+#include <plat/common.h>
+#include <asm/proc-fns.h>
+#ifdef CONFIG_SOC_OMAP2420
+extern void omap242x_map_common_io(void);
+#else
+static inline void omap242x_map_common_io(void)
+{
+}
+#endif
+#ifdef CONFIG_SOC_OMAP2430
+extern void omap243x_map_common_io(void);
+#else
+static inline void omap243x_map_common_io(void)
+{
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP3
+extern void omap34xx_map_common_io(void);
+#else
+static inline void omap34xx_map_common_io(void)
+{
+}
+#endif
+#ifdef CONFIG_SOC_OMAPTI81XX
+extern void omapti81xx_map_common_io(void);
+#else
+static inline void omapti81xx_map_common_io(void)
+{
+}
+#endif
+#ifdef CONFIG_SOC_OMAPAM33XX
+extern void omapam33xx_map_common_io(void);
+#else
+static inline void omapam33xx_map_common_io(void)
+{
+}
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+extern void omap44xx_map_common_io(void);
+#else
+static inline void omap44xx_map_common_io(void)
+{
+}
+#endif
+extern void omap2_init_common_infrastructure(void);
+extern struct sys_timer omap2_timer;
+extern struct sys_timer omap3_timer;
+extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap4_timer;
+void omap2420_init_early(void);
+void omap2430_init_early(void);
+void omap3430_init_early(void);
+void omap35xx_init_early(void);
+void omap3630_init_early(void);
+void omap3_init_early(void);    /* Do not use this one */
+void am35xx_init_early(void);
+void ti81xx_init_early(void);
+void omap4430_init_early(void);
+void omap_prcm_restart(char, const char *);
+/*
+ * IO bases for various OMAP processors
+ * Except the tap base, rest all the io bases
+ * listed are physical addresses.
+ */
+struct omap_globals {
+        u32             class;          /* OMAP class to detect */
+        void __iomem    *tap;           /* Control module ID code */
+        void __iomem    *sdrc;           /* SDRAM Controller */
+        void __iomem    *sms;            /* SDRAM Memory Scheduler */
+        void __iomem    *ctrl;           /* System Control Module */
+        void __iomem    *ctrl_pad;      /* PAD Control Module */
+        void __iomem    *prm;            /* Power and Reset Management */
+        void __iomem    *cm;             /* Clock Management */
+        void __iomem    *cm2;
+};
+void omap2_set_globals_242x(void);
+void omap2_set_globals_243x(void);
+void omap2_set_globals_3xxx(void);
+void omap2_set_globals_443x(void);
+void omap2_set_globals_ti81xx(void);
+void omap2_set_globals_am33xx(void);
+/* These get called from omap2_set_globals_xxxx(), do not call these */
+void omap2_set_globals_tap(struct omap_globals *);
+void omap2_set_globals_sdrc(struct omap_globals *);
+void omap2_set_globals_control(struct omap_globals *);
+void omap2_set_globals_prcm(struct omap_globals *);
+void omap242x_map_io(void);
+void omap243x_map_io(void);
+void omap3_map_io(void);
+void am33xx_map_io(void);
+void omap4_map_io(void);
+void ti81xx_map_io(void);
+/**
+ * omap_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_test_timeout(cond, timeout, index)                 \
+({                                                              \
+        for (index = 0; index < timeout; index++) {             \
+                if (cond)                                       \
+                        break;                                  \
+                udelay(1);                                      \
+        }                                                       \
+})
+extern struct device *omap2_get_mpuss_device(void);
+extern struct device *omap2_get_iva_device(void);
+extern struct device *omap2_get_l3_device(void);
+extern struct device *omap4_get_dsp_device(void);
+void omap2_init_irq(void);
+void omap3_init_irq(void);
+void ti81xx_init_irq(void);
+extern int omap_irq_pending(void);
+void omap_intc_save_context(void);
+void omap_intc_restore_context(void);
+void omap3_intc_suspend(void);
+void omap3_intc_prepare_idle(void);
+void omap3_intc_resume_idle(void);
+void omap2_intc_handle_irq(struct pt_regs *regs);
+void omap3_intc_handle_irq(struct pt_regs *regs);
+#ifdef CONFIG_CACHE_L2X0
+extern void __iomem *omap4_get_l2cache_base(void);
+#endif
+#ifdef CONFIG_SMP
+extern void __iomem *omap4_get_scu_base(void);
+#else
+static inline void __iomem *omap4_get_scu_base(void)
+{
+        return NULL;
+}
+#endif
+extern void __init gic_init_irq(void);
+extern void omap_smc1(u32 fn, u32 arg);
+extern void __iomem *omap4_get_sar_ram_base(void);
+extern void omap_do_wfi(void);
+#ifdef CONFIG_SMP
+/* Needed for secondary core boot */
+extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
+extern u32 omap_read_auxcoreboot0(void);
+#endif
+#if defined(CONFIG_SMP) && defined(CONFIG_PM)
+extern int omap4_mpuss_init(void);
+extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
+extern int omap4_finish_suspend(unsigned long cpu_state);
+extern void omap4_cpu_resume(void);
+extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
+extern u32 omap4_mpuss_read_prev_context_state(void);
+#else
+static inline int omap4_enter_lowpower(unsigned int cpu,
+                                        unsigned int power_state)
+{
+        cpu_do_idle();
+        return 0;
+}
+static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+{
+        cpu_do_idle();
+        return 0;
+}
+static inline int omap4_mpuss_init(void)
+{
+        return 0;
+}
+static inline int omap4_finish_suspend(unsigned long cpu_state)
+{
+        return 0;
+}
+static inline void omap4_cpu_resume(void)
+{}
+static inline u32 omap4_mpuss_read_prev_context_state(void)
+{
+        return 0;
+}
+#endif
+#endif /* __ASSEMBLER__ */
+#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index e34d27f8c49..114c037e433 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -15,7 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/sdrc.h>
 #include "cm-regbits-34xx.h"
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index d4ef75d5a38..0ba68d3764b 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -52,8 +52,8 @@
 #define OMAP343X_CONTROL_PADCONFS_WKUP  0xa00
 #define OMAP343X_CONTROL_GENERAL_WKUP   0xa60
-/* TI816X spefic control submodules */
+/* TI81XX spefic control submodules */
-#define TI816X_CONTROL_DEVCONF          0x600
+#define TI81XX_CONTROL_DEVCONF          0x600
 /* Control register offsets - read/write with omap_ctrl_{read,write}{bwl}() */
@@ -244,8 +244,8 @@
 #define OMAP3_PADCONF_SAD2D_MSTANDBY   0x250
 #define OMAP3_PADCONF_SAD2D_IDLEACK    0x254
-/* TI816X CONTROL_DEVCONF register offsets */
+/* TI81XX CONTROL_DEVCONF register offsets */
-#define TI816X_CONTROL_DEVICE_ID        (TI816X_CONTROL_DEVCONF + 0x000)
+#define TI81XX_CONTROL_DEVICE_ID        (TI81XX_CONTROL_DEVCONF + 0x000)
 /*
 * REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 942bb4f19f9..464cffde58f 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -25,15 +25,16 @@
 #include <linux/sched.h>
 #include <linux/cpuidle.h>
 #include <linux/export.h>
+#include <linux/cpu_pm.h>
 #include <plat/prcm.h>
 #include <plat/irqs.h>
 #include "powerdomain.h"
 #include "clockdomain.h"
-#include <plat/serial.h>
 #include "pm.h"
 #include "control.h"
+#include "common.h"
 #ifdef CONFIG_CPU_IDLE
@@ -123,9 +124,23 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
                pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
        }
+        /*
+         * Call idle CPU PM enter notifier chain so that
+         * VFP context is saved.
+         */
+        if (mpu_state == PWRDM_POWER_OFF)
+                cpu_pm_enter();
        /* Execute ARM wfi */
        omap_sram_idle();
+        /*
+         * Call idle CPU PM enter notifier chain to restore
+         * VFP context.
+         */
+        if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
+                cpu_pm_exit();
        /* Re-allow idle for C1 */
        if (index == 0) {
                pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
@@ -244,11 +259,6 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
        struct omap3_idle_statedata *cx;
        int ret;
-        if (!omap3_can_sleep()) {
-                new_state_idx = drv->safe_state_index;
-                goto select_state;
-        }
        /*
         * Prevent idle completely if CAM is active.
         * CAM does not have wakeup capability in OMAP3.
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
new file mode 100644
index 00000000000..cfdbb86bc84
--- /dev/null
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -0,0 +1,245 @@
+/*
+ * OMAP4 CPU idle Routines
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ * Rajendra Nayak <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/sched.h>
+#include <linux/cpuidle.h>
+#include <linux/cpu_pm.h>
+#include <linux/export.h>
+#include <linux/clockchips.h>
+#include <asm/proc-fns.h>
+#include "common.h"
+#include "pm.h"
+#include "prm.h"
+#ifdef CONFIG_CPU_IDLE
+/* Machine specific information to be recorded in the C-state driver_data */
+struct omap4_idle_statedata {
+        u32 cpu_state;
+        u32 mpu_logic_state;
+        u32 mpu_state;
+        u8 valid;
+};
+static struct cpuidle_params cpuidle_params_table[] = {
+        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+        {.exit_latency = 2 + 2 , .target_residency = 5, .valid = 1},
+        /* C2- CPU0 OFF + CPU1 OFF + MPU CSWR */
+        {.exit_latency = 328 + 440 , .target_residency = 960, .valid = 1},
+        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+        {.exit_latency = 460 + 518 , .target_residency = 1100, .valid = 1},
+};
+#define OMAP4_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
+struct omap4_idle_statedata omap4_idle_data[OMAP4_NUM_STATES];
+static struct powerdomain *mpu_pd, *cpu0_pd, *cpu1_pd;
+/**
+ * omap4_enter_idle - Programs OMAP4 to enter the specified state
+ * @dev: cpuidle device
+ * @drv: cpuidle driver
+ * @index: the index of state to be entered
+ *
+ * Called from the CPUidle framework to program the device to the
+ * specified low power state selected by the governor.
+ * Returns the amount of time spent in the low power state.
+ */
+static int omap4_enter_idle(struct cpuidle_device *dev,
+                        struct cpuidle_driver *drv,
+                        int index)
+{
+        struct omap4_idle_statedata *cx =
+                        cpuidle_get_statedata(&dev->states_usage[index]);
+        struct timespec ts_preidle, ts_postidle, ts_idle;
+        u32 cpu1_state;
+        int idle_time;
+        int new_state_idx;
+        int cpu_id = smp_processor_id();
+        /* Used to keep track of the total time in idle */
+        getnstimeofday(&ts_preidle);
+        local_irq_disable();
+        local_fiq_disable();
+        /*
+         * CPU0 has to stay ON (i.e in C1) until CPU1 is OFF state.
+         * This is necessary to honour hardware recommondation
+         * of triggeing all the possible low power modes once CPU1 is
+         * out of coherency and in OFF mode.
+         * Update dev->last_state so that governor stats reflects right
+         * data.
+         */
+        cpu1_state = pwrdm_read_pwrst(cpu1_pd);
+        if (cpu1_state != PWRDM_POWER_OFF) {
+                new_state_idx = drv->safe_state_index;
+                cx = cpuidle_get_statedata(&dev->states_usage[new_state_idx]);
+        }
+        if (index > 0)
+                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
+        /*
+         * Call idle CPU PM enter notifier chain so that
+         * VFP and per CPU interrupt context is saved.
+         */
+        if (cx->cpu_state == PWRDM_POWER_OFF)
+                cpu_pm_enter();
+        pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
+        omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
+        /*
+         * Call idle CPU cluster PM enter notifier chain
+         * to save GIC and wakeupgen context.
+         */
+        if ((cx->mpu_state == PWRDM_POWER_RET) &&
+                (cx->mpu_logic_state == PWRDM_POWER_OFF))
+                        cpu_cluster_pm_enter();
+        omap4_enter_lowpower(dev->cpu, cx->cpu_state);
+        /*
+         * Call idle CPU PM exit notifier chain to restore
+         * VFP and per CPU IRQ context. Only CPU0 state is
+         * considered since CPU1 is managed by CPU hotplug.
+         */
+        if (pwrdm_read_prev_pwrst(cpu0_pd) == PWRDM_POWER_OFF)
+                cpu_pm_exit();
+        /*
+         * Call idle CPU cluster PM exit notifier chain
+         * to restore GIC and wakeupgen context.
+         */
+        if (omap4_mpuss_read_prev_context_state())
+                cpu_cluster_pm_exit();
+        if (index > 0)
+                clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
+        getnstimeofday(&ts_postidle);
+        ts_idle = timespec_sub(ts_postidle, ts_preidle);
+        local_irq_enable();
+        local_fiq_enable();
+        idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
+                                                                USEC_PER_SEC;
+        /* Update cpuidle counters */
+        dev->last_residency = idle_time;
+        return index;
+}
+DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
+struct cpuidle_driver omap4_idle_driver = {
+        .name =         "omap4_idle",
+        .owner =        THIS_MODULE,
+};
+static inline void _fill_cstate(struct cpuidle_driver *drv,
+                                        int idx, const char *descr)
+{
+        struct cpuidle_state *state = &drv->states[idx];
+        state->exit_latency     = cpuidle_params_table[idx].exit_latency;
+        state->target_residency = cpuidle_params_table[idx].target_residency;
+        state->flags            = CPUIDLE_FLAG_TIME_VALID;
+        state->enter            = omap4_enter_idle;
+        sprintf(state->name, "C%d", idx + 1);
+        strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
+}
+static inline struct omap4_idle_statedata *_fill_cstate_usage(
+                                        struct cpuidle_device *dev,
+                                        int idx)
+{
+        struct omap4_idle_statedata *cx = &omap4_idle_data[idx];
+        struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
+        cx->valid               = cpuidle_params_table[idx].valid;
+        cpuidle_set_statedata(state_usage, cx);
+        return cx;
+}
+/**
+ * omap4_idle_init - Init routine for OMAP4 idle
+ *
+ * Registers the OMAP4 specific cpuidle driver to the cpuidle
+ * framework with the valid set of states.
+ */
+int __init omap4_idle_init(void)
+{
+        struct omap4_idle_statedata *cx;
+        struct cpuidle_device *dev;
+        struct cpuidle_driver *drv = &omap4_idle_driver;
+        unsigned int cpu_id = 0;
+        mpu_pd = pwrdm_lookup("mpu_pwrdm");
+        cpu0_pd = pwrdm_lookup("cpu0_pwrdm");
+        cpu1_pd = pwrdm_lookup("cpu1_pwrdm");
+        if ((!mpu_pd) || (!cpu0_pd) || (!cpu1_pd))
+                return -ENODEV;
+        drv->safe_state_index = -1;
+        dev = &per_cpu(omap4_idle_dev, cpu_id);
+        dev->cpu = cpu_id;
+        /* C1 - CPU0 ON + CPU1 ON + MPU ON */
+        _fill_cstate(drv, 0, "MPUSS ON");
+        drv->safe_state_index = 0;
+        cx = _fill_cstate_usage(dev, 0);
+        cx->valid = 1;  /* C1 is always valid */
+        cx->cpu_state = PWRDM_POWER_ON;
+        cx->mpu_state = PWRDM_POWER_ON;
+        cx->mpu_logic_state = PWRDM_POWER_RET;
+        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
+        _fill_cstate(drv, 1, "MPUSS CSWR");
+        cx = _fill_cstate_usage(dev, 1);
+        cx->cpu_state = PWRDM_POWER_OFF;
+        cx->mpu_state = PWRDM_POWER_RET;
+        cx->mpu_logic_state = PWRDM_POWER_RET;
+        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
+        _fill_cstate(drv, 2, "MPUSS OSWR");
+        cx = _fill_cstate_usage(dev, 2);
+        cx->cpu_state = PWRDM_POWER_OFF;
+        cx->mpu_state = PWRDM_POWER_RET;
+        cx->mpu_logic_state = PWRDM_POWER_OFF;
+        drv->state_count = OMAP4_NUM_STATES;
+        cpuidle_register_driver(&omap4_idle_driver);
+        dev->state_count = OMAP4_NUM_STATES;
+        if (cpuidle_register_device(dev)) {
+                pr_err("%s: CPUidle register device failed\n", __func__);
+                        return -EIO;
+                }
+        return 0;
+}
+#else
+int __init omap4_idle_init(void)
+{
+        return 0;
+}
+#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index c15cfada5f1..0b510ad01a0 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -127,6 +127,10 @@ static struct platform_device omap2cam_device = {
 };
 #endif
+#if defined(CONFIG_IOMMU_API)
+#include <plat/iommu.h>
 static struct resource omap3isp_resources[] = {
        {
                .start          = OMAP3430_ISP_BASE,
@@ -211,12 +215,27 @@ static struct platform_device omap3isp_device = {
        .resource       = omap3isp_resources,
 };
+static struct omap_iommu_arch_data omap3_isp_iommu = {
+        .name = "isp",
+};
 int omap3_init_camera(struct isp_platform_data *pdata)
 {
        omap3isp_device.dev.platform_data = pdata;
+        omap3isp_device.dev.archdata.iommu = &omap3_isp_iommu;
        return platform_device_register(&omap3isp_device);
 }
+#else /* !CONFIG_IOMMU_API */
+int omap3_init_camera(struct isp_platform_data *pdata)
+{
+        return 0;
+}
+#endif
 static inline void omap_init_camera(void)
 {
 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
@@ -336,6 +355,27 @@ static void omap_init_mcpdm(void)
 static inline void omap_init_mcpdm(void) {}
 #endif
+#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
+                defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
+static void omap_init_dmic(void)
+{
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+        oh = omap_hwmod_lookup("dmic");
+        if (!oh) {
+                printk(KERN_ERR "Could not look up mcpdm hw_mod\n");
+                return;
+        }
+        pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
+}
+#else
+static inline void omap_init_dmic(void) {}
+#endif
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 #include <plat/mcspi.h>
@@ -681,6 +721,7 @@ static int __init omap2_init_devices(void)
         */
        omap_init_audio();
        omap_init_mcpdm();
+        omap_init_dmic();
        omap_init_camera();
        omap_init_mbox();
        omap_init_mcspi();
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index dce9905d64b..3c446d1a178 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -22,13 +22,15 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/err.h>
+#include <linux/delay.h>
 #include <video/omapdss.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
-#include <plat/common.h>
+#include "common.h"
+#include "mux.h"
 #include "control.h"
 #include "display.h"
@@ -96,6 +98,36 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
        { "dss_hdmi", "omapdss_hdmi", -1 },
 };
+static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
+{
+        u32 reg;
+        u16 control_i2c_1;
+        /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
+        omap_mux_init_signal("hdmi_hpd",
+                        OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_signal("hdmi_cec",
+                        OMAP_PIN_INPUT_PULLUP);
+        /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
+        omap_mux_init_signal("hdmi_ddc_scl",
+                        OMAP_PIN_INPUT_PULLUP);
+        omap_mux_init_signal("hdmi_ddc_sda",
+                        OMAP_PIN_INPUT_PULLUP);
+        /*
+         * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
+         * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
+         * internal pull up resistor.
+         */
+        if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
+                control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
+                reg = omap4_ctrl_pad_readl(control_i2c_1);
+                reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
+                        OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
+                        omap4_ctrl_pad_writel(reg, control_i2c_1);
+        }
+}
 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 {
        u32 enable_mask, enable_shift;
@@ -129,6 +161,14 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
        return 0;
 }
+int omap_hdmi_init(enum omap_hdmi_flags flags)
+{
+        if (cpu_is_omap44xx())
+                omap4_hdmi_mux_pads(flags);
+        return 0;
+}
 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 {
        if (cpu_is_omap44xx())
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index f4a1020559a..bd844af13af 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -171,6 +171,17 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
        }
 }
+static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
+{
+        u32 reg;
+        if (mmc->slots[0].internal_clock) {
+                reg = omap_ctrl_readl(control_devconf1_offset);
+                reg |= OMAP2_MMCSDIO2ADPCLKISEL;
+                omap_ctrl_writel(reg, control_devconf1_offset);
+        }
+}
 static void hsmmc23_before_set_reg(struct device *dev, int slot,
                                   int power_on, int vdd)
 {
@@ -179,16 +190,19 @@ static void hsmmc23_before_set_reg(struct device *dev, int slot,
        if (mmc->slots[0].remux)
                mmc->slots[0].remux(dev, slot, power_on);
-        if (power_on) {
+        if (power_on)
-                /* Only MMC2 supports a CLKIN */
+                hsmmc2_select_input_clk_src(mmc);
-                if (mmc->slots[0].internal_clock) {
+}
-                        u32 reg;
-                        reg = omap_ctrl_readl(control_devconf1_offset);
+static int am35x_hsmmc2_set_power(struct device *dev, int slot,
-                        reg |= OMAP2_MMCSDIO2ADPCLKISEL;
+                                  int power_on, int vdd)
-                        omap_ctrl_writel(reg, control_devconf1_offset);
+{
-                }
+        struct omap_mmc_platform_data *mmc = dev->platform_data;
-        }
+        if (power_on)
+                hsmmc2_select_input_clk_src(mmc);
+        return 0;
 }
 static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
@@ -200,10 +214,12 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
 static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
                        int controller_nr)
 {
-        if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
+        if (gpio_is_valid(mmc_controller->slots[0].switch_pin) &&
+                (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
                omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
                                        OMAP_PIN_INPUT_PULLUP);
-        if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
+        if (gpio_is_valid(mmc_controller->slots[0].gpio_wp) &&
+                (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
                omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
                                        OMAP_PIN_INPUT_PULLUP);
        if (cpu_is_omap34xx()) {
@@ -296,6 +312,7 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
        mmc->slots[0].name = hc_name;
        mmc->nr_slots = 1;
        mmc->slots[0].caps = c->caps;
+        mmc->slots[0].pm_caps = c->pm_caps;
        mmc->slots[0].internal_clock = !c->ext_clock;
        mmc->dma_mask = 0xffffffff;
        if (cpu_is_omap44xx())
@@ -336,11 +353,17 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
         *
         * temporary HACK: ocr_mask instead of fixed supply
         */
-        mmc->slots[0].ocr_mask = c->ocr_mask;
+        if (cpu_is_omap3505() || cpu_is_omap3517())
+                mmc->slots[0].ocr_mask = MMC_VDD_165_195 |
-        if (cpu_is_omap3517() || cpu_is_omap3505())
+                                         MMC_VDD_26_27 |
-                mmc->slots[0].set_power = nop_mmc_set_power;
+                                         MMC_VDD_27_28 |
+                                         MMC_VDD_29_30 |
+                                         MMC_VDD_30_31 |
+                                         MMC_VDD_31_32;
        else
+                mmc->slots[0].ocr_mask = c->ocr_mask;
+        if (!cpu_is_omap3517() && !cpu_is_omap3505())
                mmc->slots[0].features |= HSMMC_HAS_PBIAS;
        if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
@@ -363,6 +386,9 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
                        }
                }
+                if (cpu_is_omap3517() || cpu_is_omap3505())
+                        mmc->slots[0].set_power = nop_mmc_set_power;
                /* OMAP3630 HSMMC1 supports only 4-bit */
                if (cpu_is_omap3630() &&
                                (c->caps & MMC_CAP_8_BIT_DATA)) {
@@ -372,6 +398,9 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
                }
                break;
        case 2:
+                if (cpu_is_omap3517() || cpu_is_omap3505())
+                        mmc->slots[0].set_power = am35x_hsmmc2_set_power;
                if (c->ext_clock)
                        c->transceiver = 1;
                if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
diff --git a/arch/arm/mach-omap2/hsmmc.h b/arch/arm/mach-omap2/hsmmc.h
index f757e78d4d4..c4409730c4b 100644
--- a/arch/arm/mach-omap2/hsmmc.h
+++ b/arch/arm/mach-omap2/hsmmc.h
@@ -12,6 +12,7 @@ struct omap2_hsmmc_info {
        u8      mmc;            /* controller 1/2/3 */
        u32     caps;           /* 4/8 wires and any additional host
                                 * capabilities OR'd (ref. linux/mmc/host.h) */
+        u32     pm_caps;        /* PM capabilities */
        bool    transceiver;    /* MMC-2 option */
        bool    ext_clock;      /* use external pin for input clock */
        bool    cover_only;     /* No card detect - just cover switch */
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index ace99944e96..a12e224eb97 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -21,7 +21,7 @@
 #include <plat/cpu.h>
 #include <plat/i2c.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/omap_hwmod.h>
 #include "mux.h"
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 7f47092a193..6c5826605ea 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -21,7 +21,7 @@
 #include <asm/cputype.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/cpu.h>
 #include <mach/id.h>
@@ -226,7 +226,7 @@ static void __init omap4_check_features(void)
        }
 }
-static void __init ti816x_check_features(void)
+static void __init ti81xx_check_features(void)
 {
        omap_features = OMAP3_HAS_NEON;
 }
@@ -340,6 +340,29 @@ static void __init omap3_check_revision(const char **cpu_rev)
                        break;
                }
                break;
+        case 0xb944:
+                omap_revision = AM335X_REV_ES1_0;
+                *cpu_rev = "1.0";
+        case 0xb8f2:
+                switch (rev) {
+                case 0:
+                /* FALLTHROUGH */
+                case 1:
+                        omap_revision = TI8148_REV_ES1_0;
+                        *cpu_rev = "1.0";
+                        break;
+                case 2:
+                        omap_revision = TI8148_REV_ES2_0;
+                        *cpu_rev = "2.0";
+                        break;
+                case 3:
+                /* FALLTHROUGH */
+                default:
+                        omap_revision = TI8148_REV_ES2_1;
+                        *cpu_rev = "2.1";
+                        break;
+                }
+                break;
        default:
                /* Unknown default to latest silicon rev as default */
                omap_revision = OMAP3630_REV_ES1_2;
@@ -367,7 +390,7 @@ static void __init omap4_check_revision(void)
         * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
         * Use ARM register to detect the correct ES version
         */
-        if (!rev && (hawkeye != 0xb94e)) {
+        if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
                idcode = read_cpuid(CPUID_ID);
                rev = (idcode & 0xf) - 1;
        }
@@ -389,8 +412,11 @@ static void __init omap4_check_revision(void)
                        omap_revision = OMAP4430_REV_ES2_1;
                        break;
                case 4:
-                default:
                        omap_revision = OMAP4430_REV_ES2_2;
+                        break;
+                case 6:
+                default:
+                        omap_revision = OMAP4430_REV_ES2_3;
                }
                break;
        case 0xb94e:
@@ -401,9 +427,17 @@ static void __init omap4_check_revision(void)
                        break;
                }
                break;
+        case 0xb975:
+                switch (rev) {
+                case 0:
+                default:
+                        omap_revision = OMAP4470_REV_ES1_0;
+                        break;
+                }
+                break;
        default:
                /* Unknown default to latest silicon rev as default */
-                omap_revision = OMAP4430_REV_ES2_2;
+                omap_revision = OMAP4430_REV_ES2_3;
        }
        pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
@@ -432,6 +466,10 @@ static void __init omap3_cpuinfo(const char *cpu_rev)
                cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
        } else if (cpu_is_ti816x()) {
                cpu_name = "TI816X";
+        } else if (cpu_is_am335x()) {
+                cpu_name =  "AM335X";
+        } else if (cpu_is_ti814x()) {
+                cpu_name = "TI814X";
        } else if (omap3_has_iva() && omap3_has_sgx()) {
                /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
                cpu_name = "OMAP3430/3530";
@@ -472,11 +510,11 @@ void __init omap2_check_revision(void)
        } else if (cpu_is_omap34xx()) {
                omap3_check_revision(&cpu_rev);
-                /* TI816X doesn't have feature register */
+                /* TI81XX doesn't have feature register */
-                if (!cpu_is_ti816x())
+                if (!cpu_is_ti81xx())
                        omap3_check_features();
                else
-                        ti816x_check_features();
+                        ti81xx_check_features();
                omap3_cpuinfo(cpu_rev);
                return;
diff --git a/arch/arm/mach-omap2/include/mach/barriers.h b/arch/arm/mach-omap2/include/mach/barriers.h
new file mode 100644
index 00000000000..4fa72c7cc7c
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/barriers.h
@@ -0,0 +1,31 @@
+/*
+ * OMAP memory barrier header.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *  Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *  Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __MACH_BARRIERS_H
+#define __MACH_BARRIERS_H
+extern void omap_bus_sync(void);
+#define rmb()           dsb()
+#define wmb()           do { dsb(); outer_sync(); omap_bus_sync(); } while (0)
+#define mb()            wmb()
+#endif  /* __MACH_BARRIERS_H */
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 13f98e59cfe..cdfc2a1f0e7 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -66,11 +66,11 @@ omap_uart_lsr:	.word	0
                beq     34f                     @ configure OMAP3UART4
                cmp     \rp, #OMAP4UART4        @ only on 44xx
                beq     44f                     @ configure OMAP4UART4
-                cmp     \rp, #TI816XUART1       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART1       @ ti81Xx UART offsets different
                beq     81f                     @ configure UART1
-                cmp     \rp, #TI816XUART2       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART2       @ ti81Xx UART offsets different
                beq     82f                     @ configure UART2
-                cmp     \rp, #TI816XUART3       @ ti816x UART offsets different
+                cmp     \rp, #TI81XXUART3       @ ti81Xx UART offsets different
                beq     83f                     @ configure UART3
                cmp     \rp, #ZOOM_UART         @ only on zoom2/3
                beq     95f                     @ configure ZOOM_UART
@@ -94,11 +94,11 @@ omap_uart_lsr:	.word	0
                b       98f
 44:             mov     \rp, #UART_OFFSET(OMAP4_UART4_BASE)
                b       98f
-81:             mov     \rp, #UART_OFFSET(TI816X_UART1_BASE)
+81:             mov     \rp, #UART_OFFSET(TI81XX_UART1_BASE)
                b       98f
-82:             mov     \rp, #UART_OFFSET(TI816X_UART2_BASE)
+82:             mov     \rp, #UART_OFFSET(TI81XX_UART2_BASE)
                b       98f
-83:             mov     \rp, #UART_OFFSET(TI816X_UART3_BASE)
+83:             mov     \rp, #UART_OFFSET(TI81XX_UART3_BASE)
                b       98f
 95:             ldr     \rp, =ZOOM_UART_BASE
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index feb90a10945..56964a0c4c7 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -10,146 +10,9 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-#include <asm/hardware/gic.h>
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-#include <plat/multi.h>
-#define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
-#define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
-#define OMAP4_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
-#define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
-#define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
                .macro  disable_fiq
                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-/*
- * Unoptimized irq functions for multi-omap2, 3 and 4
- */
-#ifdef MULTI_OMAP2
-                /*
-                 * Configure the interrupt base on the first interrupt.
-                 * See also omap_irq_base_init for setting omap_irq_base.
-                 */
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =omap_irq_base   @ irq base address
-                ldr     \base, [\base, #0]      @ irq base value
-                .endm
-                /* Check the pending interrupts. Note that base already set */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                tst     \base, #0x100           @ gic address?
-                bne     4401f                   @ found gic
-                /* Handle omap2 and omap3 */
-                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-                cmp     \irqnr, #0x0
-                bne     9998f
-                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-                cmp     \irqnr, #0x0
-                bne     9998f
-                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-                cmp     \irqnr, #0x0
-                bne     9998f
-                /*
-                 * ti816x has additional IRQ pending register. Checking this
-                 * register on omap2 & omap3 has no effect (read as 0).
-                 */
-                ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
-                cmp     \irqnr, #0x0
-9998:
-                ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-                and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-                b       9999f
-                /* Handle omap4 */
-4401:           ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-                ldr     \tmp, =1021
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #15
-                cmpcc   \irqnr, \irqnr
-                cmpne   \irqnr, \tmp
-                cmpcs   \irqnr, \irqnr
-9999:
-                .endm
-#ifdef CONFIG_SMP
-                /* We assume that irqstat (the raw value of the IRQ acknowledge
-                 * register) is preserved from the macro above.
-                 * If there is an IPI, we immediately signal end of interrupt
-                 * on the controller, since this requires the original irqstat
-                 * value which we won't easily be able to recreate later.
-                 */
-                .macro test_for_ipi, irqnr, irqstat, base, tmp
-                bic     \irqnr, \irqstat, #0x1c00
-                cmp     \irqnr, #16
-                it      cc
-                strcc   \irqstat, [\base, #GIC_CPU_EOI]
-                it      cs
-                cmpcs   \irqnr, \irqnr
-                .endm
-#endif  /* CONFIG_SMP */
-#else   /* MULTI_OMAP2 */
-/*
- * Optimized irq functions for omap2, 3 and 4
- */
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-                .macro  get_irqnr_preamble, base, tmp
-#ifdef CONFIG_ARCH_OMAP2
-                ldr     \base, =OMAP2_IRQ_BASE
-#else
-                ldr     \base, =OMAP3_IRQ_BASE
-#endif
-                .endm
-                /* Check the pending interrupts. Note that base already set */
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                ldr     \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-                cmp     \irqnr, #0x0
-                bne     9999f
-                ldr     \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-                cmp     \irqnr, #0x0
-                bne     9999f
-                ldr     \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-                cmp     \irqnr, #0x0
-#ifdef CONFIG_SOC_OMAPTI816X
-                bne     9999f
-                ldr     \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
-                cmp     \irqnr, #0x0
-#endif
-9999:
-                ldrne   \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-                and     \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-                .endm
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-                .macro  get_irqnr_preamble, base, tmp
-                ldr     \base, =OMAP4_IRQ_BASE
-                .endm
-#endif
-#endif  /* MULTI_OMAP2 */
diff --git a/arch/arm/mach-omap2/include/mach/omap-secure.h b/arch/arm/mach-omap2/include/mach/omap-secure.h
new file mode 100644
index 00000000000..c90a43589ab
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap-secure.h
@@ -0,0 +1,57 @@
+/*
+ * omap-secure.h: OMAP Secure infrastructure header.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_OMAP_SECURE_H
+#define OMAP_ARCH_OMAP_SECURE_H
+/* Monitor error code */
+#define  API_HAL_RET_VALUE_NS2S_CONVERSION_ERROR        0xFFFFFFFE
+#define  API_HAL_RET_VALUE_SERVICE_UNKNWON              0xFFFFFFFF
+/* HAL API error codes */
+#define  API_HAL_RET_VALUE_OK           0x00
+#define  API_HAL_RET_VALUE_FAIL         0x01
+/* Secure HAL API flags */
+#define FLAG_START_CRITICAL             0x4
+#define FLAG_IRQFIQ_MASK                0x3
+#define FLAG_IRQ_ENABLE                 0x2
+#define FLAG_FIQ_ENABLE                 0x1
+#define NO_FLAG                         0x0
+/* Maximum Secure memory storage size */
+#define OMAP_SECURE_RAM_STORAGE (88 * SZ_1K)
+/* Secure low power HAL API index */
+#define OMAP4_HAL_SAVESECURERAM_INDEX   0x1a
+#define OMAP4_HAL_SAVEHW_INDEX          0x1b
+#define OMAP4_HAL_SAVEALL_INDEX         0x1c
+#define OMAP4_HAL_SAVEGIC_INDEX         0x1d
+/* Secure Monitor mode APIs */
+#define OMAP4_MON_SCU_PWR_INDEX         0x108
+#define OMAP4_MON_L2X0_DBG_CTRL_INDEX   0x100
+#define OMAP4_MON_L2X0_CTRL_INDEX       0x102
+#define OMAP4_MON_L2X0_AUXCTRL_INDEX    0x109
+#define OMAP4_MON_L2X0_PREFETCH_INDEX   0x113
+/* Secure PPA(Primary Protected Application) APIs */
+#define OMAP4_PPA_L2_POR_INDEX          0x23
+#define OMAP4_PPA_CPU_ACTRL_SMP_INDEX   0x25
+#ifndef __ASSEMBLER__
+extern u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs,
+                                u32 arg1, u32 arg2, u32 arg3, u32 arg4);
+extern u32 omap_smc2(u32 id, u32 falg, u32 pargs);
+extern phys_addr_t omap_secure_ram_mempool_base(void);
+#endif /* __ASSEMBLER__ */
+#endif /* OMAP_ARCH_OMAP_SECURE_H */
diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
new file mode 100644
index 00000000000..d79321b0f2a
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h
@@ -0,0 +1,39 @@
+/*
+ * OMAP WakeupGen header file
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_WAKEUPGEN_H
+#define OMAP_ARCH_WAKEUPGEN_H
+#define OMAP_WKG_CONTROL_0                      0x00
+#define OMAP_WKG_ENB_A_0                        0x10
+#define OMAP_WKG_ENB_B_0                        0x14
+#define OMAP_WKG_ENB_C_0                        0x18
+#define OMAP_WKG_ENB_D_0                        0x1c
+#define OMAP_WKG_ENB_SECURE_A_0                 0x20
+#define OMAP_WKG_ENB_SECURE_B_0                 0x24
+#define OMAP_WKG_ENB_SECURE_C_0                 0x28
+#define OMAP_WKG_ENB_SECURE_D_0                 0x2c
+#define OMAP_WKG_ENB_A_1                        0x410
+#define OMAP_WKG_ENB_B_1                        0x414
+#define OMAP_WKG_ENB_C_1                        0x418
+#define OMAP_WKG_ENB_D_1                        0x41c
+#define OMAP_WKG_ENB_SECURE_A_1                 0x420
+#define OMAP_WKG_ENB_SECURE_B_1                 0x424
+#define OMAP_WKG_ENB_SECURE_C_1                 0x428
+#define OMAP_WKG_ENB_SECURE_D_1                 0x42c
+#define OMAP_AUX_CORE_BOOT_0                    0x800
+#define OMAP_AUX_CORE_BOOT_1                    0x804
+#define OMAP_PTMSYNCREQ_MASK                    0xc00
+#define OMAP_PTMSYNCREQ_EN                      0xc04
+#define OMAP_TIMESTAMPCYCLELO                   0xc08
+#define OMAP_TIMESTAMPCYCLEHI                   0xc0c
+extern int __init omap_wakeupgen_init(void);
+#endif
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
deleted file mode 100644
index e4bd8761973..00000000000
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * omap4-common.h: OMAP4 specific common header file
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- *
- * Author:
- *      Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef OMAP_ARCH_OMAP4_COMMON_H
-#define OMAP_ARCH_OMAP4_COMMON_H
-/*
- * wfi used in low power code. Directly opcode is used instead
- * of instruction to avoid mulit-omap build break
- */
-#ifdef CONFIG_THUMB2_KERNEL
-#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory")
-#else
-#define do_wfi()                        \
-                __asm__ __volatile__ (".word    0xe320f003" : : : "memory")
-#endif
-#ifdef CONFIG_CACHE_L2X0
-extern void __iomem *l2cache_base;
-#endif
-extern void __iomem *gic_dist_base_addr;
-extern void __init gic_init_irq(void);
-extern void omap_smc1(u32 fn, u32 arg);
-#ifdef CONFIG_SMP
-/* Needed for secondary core boot */
-extern void omap_secondary_startup(void);
-extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
-extern void omap_auxcoreboot_addr(u32 cpu_addr);
-extern u32 omap_read_auxcoreboot0(void);
-#endif
-#endif
diff --git a/arch/arm/mach-omap2/include/mach/vmalloc.h b/arch/arm/mach-omap2/include/mach/vmalloc.h
deleted file mode 100644
index 86631994776..00000000000
--- a/arch/arm/mach-omap2/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  arch/arm/plat-omap/include/mach/vmalloc.h
- *
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define VMALLOC_END       0xf8000000UL
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 25d20ced03e..3f174d51f67 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -35,7 +35,7 @@
 #include "clock3xxx.h"
 #include "clock44xx.h"
-#include <plat/common.h>
+#include "common.h"
 #include <plat/omap-pm.h>
 #include "voltage.h"
 #include "powerdomain.h"
@@ -43,7 +43,7 @@
 #include "clockdomain.h"
 #include <plat/omap_hwmod.h>
 #include <plat/multi.h>
-#include <plat/common.h>
+#include "common.h"
 /*
 * The machine specific code may provide the extra mapping besides the
@@ -176,14 +176,31 @@ static struct map_desc omap34xx_io_desc[] __initdata = {
 };
 #endif
-#ifdef CONFIG_SOC_OMAPTI816X
+#ifdef CONFIG_SOC_OMAPTI81XX
-static struct map_desc omapti816x_io_desc[] __initdata = {
+static struct map_desc omapti81xx_io_desc[] __initdata = {
+        {
+                .virtual        = L4_34XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_34XX_PHYS),
+                .length         = L4_34XX_SIZE,
+                .type           = MT_DEVICE
+        }
+};
+#endif
+#ifdef CONFIG_SOC_OMAPAM33XX
+static struct map_desc omapam33xx_io_desc[] __initdata = {
        {
                .virtual        = L4_34XX_VIRT,
                .pfn            = __phys_to_pfn(L4_34XX_PHYS),
                .length         = L4_34XX_SIZE,
                .type           = MT_DEVICE
        },
+        {
+                .virtual        = L4_WK_AM33XX_VIRT,
+                .pfn            = __phys_to_pfn(L4_WK_AM33XX_PHYS),
+                .length         = L4_WK_AM33XX_SIZE,
+                .type           = MT_DEVICE
+        }
 };
 #endif
@@ -237,6 +254,15 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
                .length         = L4_EMU_44XX_SIZE,
                .type           = MT_DEVICE,
        },
+#ifdef CONFIG_OMAP4_ERRATA_I688
+        {
+                .virtual        = OMAP4_SRAM_VA,
+                .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
+                .length         = PAGE_SIZE,
+                .type           = MT_MEMORY_SO,
+        },
+#endif
 };
 #endif
@@ -263,10 +289,17 @@ void __init omap34xx_map_common_io(void)
 }
 #endif
-#ifdef CONFIG_SOC_OMAPTI816X
+#ifdef CONFIG_SOC_OMAPTI81XX
-void __init omapti816x_map_common_io(void)
+void __init omapti81xx_map_common_io(void)
 {
-        iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
+        iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
+}
+#endif
+#ifdef CONFIG_SOC_OMAPAM33XX
+void __init omapam33xx_map_common_io(void)
+{
+        iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
 }
 #endif
@@ -316,13 +349,9 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
        return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 }
-/* See irq.c, omap4-common.c and entry-macro.S */
-void __iomem *omap_irq_base;
 static void __init omap_common_init_early(void)
 {
        omap2_check_revision();
-        omap_ioremap_init();
        omap_init_consistent_dma_size();
 }
@@ -422,9 +451,9 @@ void __init am35xx_init_early(void)
        omap3_init_early();
 }
-void __init ti816x_init_early(void)
+void __init ti81xx_init_early(void)
 {
-        omap2_set_globals_ti816x();
+        omap2_set_globals_ti81xx();
        omap_common_init_early();
        omap3xxx_voltagedomains_init();
        omap3xxx_powerdomains_init();
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 65f1be6a182..1fef061f792 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -15,6 +15,7 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
@@ -35,6 +36,11 @@
 /* Number of IRQ state bits in each MIR register */
 #define IRQ_BITS_PER_REG        32
+#define OMAP2_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP3_IRQ_BASE          OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
+#define INTCPS_SIR_IRQ_OFFSET   0x0040  /* omap2/3 active interrupt offset */
+#define ACTIVEIRQ_MASK          0x7f    /* omap2/3 active interrupt bits */
 /*
 * OMAP2 has a number of different interrupt controllers, each interrupt
 * controller is identified as its own "bank". Register definitions are
@@ -143,6 +149,7 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
 static void __init omap_init_irq(u32 base, int nr_irqs)
 {
+        void __iomem *omap_irq_base;
        unsigned long nr_of_irqs = 0;
        unsigned int nr_banks = 0;
        int i, j;
@@ -186,11 +193,49 @@ void __init omap3_init_irq(void)
        omap_init_irq(OMAP34XX_IC_BASE, 96);
 }
-void __init ti816x_init_irq(void)
+void __init ti81xx_init_irq(void)
 {
        omap_init_irq(OMAP34XX_IC_BASE, 128);
 }
+static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
+{
+        u32 irqnr;
+        do {
+                irqnr = readl_relaxed(base_addr + 0x98);
+                if (irqnr)
+                        goto out;
+                irqnr = readl_relaxed(base_addr + 0xb8);
+                if (irqnr)
+                        goto out;
+                irqnr = readl_relaxed(base_addr + 0xd8);
+#ifdef CONFIG_SOC_OMAPTI816X
+                if (irqnr)
+                        goto out;
+                irqnr = readl_relaxed(base_addr + 0xf8);
+#endif
+out:
+                if (!irqnr)
+                        break;
+                irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
+                irqnr &= ACTIVEIRQ_MASK;
+                if (irqnr)
+                        handle_IRQ(irqnr, regs);
+        } while (irqnr);
+}
+asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
+{
+        void __iomem *base_addr = OMAP2_IRQ_BASE;
+        omap_intc_handle_irq(base_addr, regs);
+}
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
@@ -263,4 +308,10 @@ void omap3_intc_resume_idle(void)
        /* Re-enable autoidle */
        intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
 }
+asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
+{
+        void __iomem *base_addr = OMAP3_IRQ_BASE;
+        omap_intc_handle_irq(base_addr, regs);
+}
 #endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 28fcb27005d..fb4bcf81a18 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -156,6 +156,9 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
                else
                        /* The FIFO has 128 locations */
                        pdata->buffer_size = 0x80;
+        } else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
+                /* The FIFO has 128 locations for all instances */
+                pdata->buffer_size = 0x80;
        }
        if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 655e9480eb9..e1cc75d1a57 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -32,6 +32,8 @@
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/uaccess.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
 #include <asm/system.h>
@@ -39,6 +41,7 @@
 #include "control.h"
 #include "mux.h"
+#include "prm.h"
 #define OMAP_MUX_BASE_OFFSET            0x30    /* Offset from CTRL_BASE */
 #define OMAP_MUX_BASE_SZ                0x5ca
@@ -306,7 +309,8 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
                pad->idle = bpad->idle;
                pad->off = bpad->off;
-                if (pad->flags & OMAP_DEVICE_PAD_REMUX)
+                if (pad->flags &
+                    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP))
                        nr_pads_dynamic++;
                pr_debug("%s: Initialized %s\n", __func__, pad->name);
@@ -331,7 +335,8 @@ omap_hwmod_mux_init(struct omap_device_pad *bpads, int nr_pads)
        for (i = 0; i < hmux->nr_pads; i++) {
                struct omap_device_pad *pad = &hmux->pads[i];
-                if (pad->flags & OMAP_DEVICE_PAD_REMUX) {
+                if (pad->flags &
+                    (OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP)) {
                        pr_debug("%s: pad %s tagged dynamic\n",
                                        __func__, pad->name);
                        hmux->pads_dynamic[nr_pads_dynamic] = pad;
@@ -351,6 +356,78 @@ err1:
        return NULL;
 }
+/**
+ * omap_hwmod_mux_scan_wakeups - omap hwmod scan wakeup pads
+ * @hmux: Pads for a hwmod
+ * @mpu_irqs: MPU irq array for a hwmod
+ *
+ * Scans the wakeup status of pads for a single hwmod.  If an irq
+ * array is defined for this mux, the parser will call the registered
+ * ISRs for corresponding pads, otherwise the parser will stop at the
+ * first wakeup active pad and return.  Returns true if there is a
+ * pending and non-served wakeup event for the mux, otherwise false.
+ */
+static bool omap_hwmod_mux_scan_wakeups(struct omap_hwmod_mux_info *hmux,
+                struct omap_hwmod_irq_info *mpu_irqs)
+{
+        int i, irq;
+        unsigned int val;
+        u32 handled_irqs = 0;
+        for (i = 0; i < hmux->nr_pads_dynamic; i++) {
+                struct omap_device_pad *pad = hmux->pads_dynamic[i];
+                if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP) ||
+                    !(pad->idle & OMAP_WAKEUP_EN))
+                        continue;
+                val = omap_mux_read(pad->partition, pad->mux->reg_offset);
+                if (!(val & OMAP_WAKEUP_EVENT))
+                        continue;
+                if (!hmux->irqs)
+                        return true;
+                irq = hmux->irqs[i];
+                /* make sure we only handle each irq once */
+                if (handled_irqs & 1 << irq)
+                        continue;
+                handled_irqs |= 1 << irq;
+                generic_handle_irq(mpu_irqs[irq].irq);
+        }
+        return false;
+}
+/**
+ * _omap_hwmod_mux_handle_irq - Process wakeup events for a single hwmod
+ *
+ * Checks a single hwmod for every wakeup capable pad to see if there is an
+ * active wakeup event. If this is the case, call the corresponding ISR.
+ */
+static int _omap_hwmod_mux_handle_irq(struct omap_hwmod *oh, void *data)
+{
+        if (!oh->mux || !oh->mux->enabled)
+                return 0;
+        if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs))
+                generic_handle_irq(oh->mpu_irqs[0].irq);
+        return 0;
+}
+/**
+ * omap_hwmod_mux_handle_irq - Process pad wakeup irqs.
+ *
+ * Calls a function for each registered omap_hwmod to check
+ * pad wakeup statuses.
+ */
+static irqreturn_t omap_hwmod_mux_handle_irq(int irq, void *unused)
+{
+        omap_hwmod_for_each(_omap_hwmod_mux_handle_irq, NULL);
+        return IRQ_HANDLED;
+}
 /* Assumes the calling function takes care of locking */
 void omap_hwmod_mux(struct omap_hwmod_mux_info *hmux, u8 state)
 {
@@ -715,6 +792,7 @@ static void __init omap_mux_free_names(struct omap_mux *m)
 static int __init omap_mux_late_init(void)
 {
        struct omap_mux_partition *partition;
+        int ret;
        list_for_each_entry(partition, &mux_partitions, node) {
                struct omap_mux_entry *e, *tmp;
@@ -735,6 +813,13 @@ static int __init omap_mux_late_init(void)
                }
        }
+        ret = request_irq(omap_prcm_event_to_irq("io"),
+                omap_hwmod_mux_handle_irq, IRQF_SHARED | IRQF_NO_SUSPEND,
+                        "hwmod_io", omap_mux_late_init);
+        if (ret)
+                pr_warning("mux: Failed to setup hwmod io irq %d\n", ret);
        omap_mux_dbg_init();
        return 0;
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 4ee6aeca885..b13ef7ef5ef 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -18,11 +18,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
-/* Physical address needed since MMU not enabled yet on secondary core */
-#define OMAP4_AUX_CORE_BOOT1_PA                 0x48281804
-        __INIT
 /*
 * OMAP4 specific entry point for secondary CPU to jump from ROM
 * code.  This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 4976b9393e4..adbe4d8c7ca 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -19,7 +19,10 @@
 #include <linux/smp.h>
 #include <asm/cacheflush.h>
-#include <mach/omap4-common.h>
+#include "common.h"
+#include "powerdomain.h"
 int platform_cpu_kill(unsigned int cpu)
 {
@@ -32,6 +35,8 @@ int platform_cpu_kill(unsigned int cpu)
 */
 void platform_cpu_die(unsigned int cpu)
 {
+        unsigned int this_cpu;
        flush_cache_all();
        dsb();
@@ -39,15 +44,15 @@ void platform_cpu_die(unsigned int cpu)
         * we're ready for shutdown now, so do it
         */
        if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
-                printk(KERN_CRIT "Secure clear status failed\n");
+                pr_err("Secure clear status failed\n");
        for (;;) {
                /*
-                 * Execute WFI
+                 * Enter into low power state
                 */
-                do_wfi();
+                omap4_hotplug_cpu(cpu, PWRDM_POWER_OFF);
+                this_cpu = smp_processor_id();
-                if (omap_read_auxcoreboot0() == cpu) {
+                if (omap_read_auxcoreboot0() == this_cpu) {
                        /*
                         * OK, proper wakeup, we're done
                         */
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
new file mode 100644
index 00000000000..1d5d0105655
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -0,0 +1,398 @@
+/*
+ * OMAP MPUSS low power code
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
+ * Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
+ * CPU0 and CPU1 LPRM modules.
+ * CPU0, CPU1 and MPUSS each have there own power domain and
+ * hence multiple low power combinations of MPUSS are possible.
+ *
+ * The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
+ * because the mode is not supported by hw constraints of dormant
+ * mode. While waking up from the dormant mode, a reset  signal
+ * to the Cortex-A9 processor must be asserted by the external
+ * power controller.
+ *
+ * With architectural inputs and hardware recommendations, only
+ * below modes are supported from power gain vs latency point of view.
+ *
+ *      CPU0            CPU1            MPUSS
+ *      ----------------------------------------------
+ *      ON              ON              ON
+ *      ON(Inactive)    OFF             ON(Inactive)
+ *      OFF             OFF             CSWR
+ *      OFF             OFF             OSWR
+ *      OFF             OFF             OFF(Device OFF *TBD)
+ *      ----------------------------------------------
+ *
+ * Note: CPU0 is the master core and it is the last CPU to go down
+ * and first to wake-up when MPUSS low power states are excercised
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/linkage.h>
+#include <linux/smp.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/smp_scu.h>
+#include <asm/system.h>
+#include <asm/pgalloc.h>
+#include <asm/suspend.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <plat/omap44xx.h>
+#include "common.h"
+#include "omap4-sar-layout.h"
+#include "pm.h"
+#include "prcm_mpu44xx.h"
+#include "prminst44xx.h"
+#include "prcm44xx.h"
+#include "prm44xx.h"
+#include "prm-regbits-44xx.h"
+#ifdef CONFIG_SMP
+struct omap4_cpu_pm_info {
+        struct powerdomain *pwrdm;
+        void __iomem *scu_sar_addr;
+        void __iomem *wkup_sar_addr;
+        void __iomem *l2x0_sar_addr;
+};
+static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
+static struct powerdomain *mpuss_pd;
+static void __iomem *sar_base;
+/*
+ * Program the wakeup routine address for the CPU0 and CPU1
+ * used for OFF or DORMANT wakeup.
+ */
+static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        __raw_writel(addr, pm_info->wkup_sar_addr);
+}
+/*
+ * Set the CPUx powerdomain's previous power state
+ */
+static inline void set_cpu_next_pwrst(unsigned int cpu_id,
+                                unsigned int power_state)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
+}
+/*
+ * Read CPU's previous power state
+ */
+static inline unsigned int read_cpu_prev_pwrst(unsigned int cpu_id)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        return pwrdm_read_prev_pwrst(pm_info->pwrdm);
+}
+/*
+ * Clear the CPUx powerdomain's previous power state
+ */
+static inline void clear_cpu_prev_pwrst(unsigned int cpu_id)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+}
+/*
+ * Store the SCU power status value to scratchpad memory
+ */
+static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        u32 scu_pwr_st;
+        switch (cpu_state) {
+        case PWRDM_POWER_RET:
+                scu_pwr_st = SCU_PM_DORMANT;
+                break;
+        case PWRDM_POWER_OFF:
+                scu_pwr_st = SCU_PM_POWEROFF;
+                break;
+        case PWRDM_POWER_ON:
+        case PWRDM_POWER_INACTIVE:
+        default:
+                scu_pwr_st = SCU_PM_NORMAL;
+                break;
+        }
+        __raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
+}
+/* Helper functions for MPUSS OSWR */
+static inline void mpuss_clear_prev_logic_pwrst(void)
+{
+        u32 reg;
+        reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+        omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
+                OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+}
+static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
+{
+        u32 reg;
+        if (cpu_id) {
+                reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
+                                        OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+                omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
+                                        OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET);
+        } else {
+                reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
+                                        OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+                omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
+                                        OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET);
+        }
+}
+/**
+ * omap4_mpuss_read_prev_context_state:
+ * Function returns the MPUSS previous context state
+ */
+u32 omap4_mpuss_read_prev_context_state(void)
+{
+        u32 reg;
+        reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+                OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
+        reg &= OMAP4430_LOSTCONTEXT_DFF_MASK;
+        return reg;
+}
+/*
+ * Store the CPU cluster state for L2X0 low power operations.
+ */
+static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
+{
+        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
+        __raw_writel(save_state, pm_info->l2x0_sar_addr);
+}
+/*
+ * Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
+ * in every restore MPUSS OFF path.
+ */
+#ifdef CONFIG_CACHE_L2X0
+static void save_l2x0_context(void)
+{
+        u32 val;
+        void __iomem *l2x0_base = omap4_get_l2cache_base();
+        val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
+        __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
+        val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
+        __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
+}
+#else
+static void save_l2x0_context(void)
+{}
+#endif
+/**
+ * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
+ * The purpose of this function is to manage low power programming
+ * of OMAP4 MPUSS subsystem
+ * @cpu : CPU ID
+ * @power_state: Low power state.
+ *
+ * MPUSS states for the context save:
+ * save_state =
+ *      0 - Nothing lost and no need to save: MPUSS INACTIVE
+ *      1 - CPUx L1 and logic lost: MPUSS CSWR
+ *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
+ *      3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
+ */
+int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
+{
+        unsigned int save_state = 0;
+        unsigned int wakeup_cpu;
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return -ENXIO;
+        switch (power_state) {
+        case PWRDM_POWER_ON:
+        case PWRDM_POWER_INACTIVE:
+                save_state = 0;
+                break;
+        case PWRDM_POWER_OFF:
+                save_state = 1;
+                break;
+        case PWRDM_POWER_RET:
+        default:
+                /*
+                 * CPUx CSWR is invalid hardware state. Also CPUx OSWR
+                 * doesn't make much scense, since logic is lost and $L1
+                 * needs to be cleaned because of coherency. This makes
+                 * CPUx OSWR equivalent to CPUX OFF and hence not supported
+                 */
+                WARN_ON(1);
+                return -ENXIO;
+        }
+        pwrdm_pre_transition();
+        /*
+         * Check MPUSS next state and save interrupt controller if needed.
+         * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
+         */
+        mpuss_clear_prev_logic_pwrst();
+        pwrdm_clear_all_prev_pwrst(mpuss_pd);
+        if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
+                (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
+                save_state = 2;
+        clear_cpu_prev_pwrst(cpu);
+        cpu_clear_prev_logic_pwrst(cpu);
+        set_cpu_next_pwrst(cpu, power_state);
+        set_cpu_wakeup_addr(cpu, virt_to_phys(omap4_cpu_resume));
+        scu_pwrst_prepare(cpu, power_state);
+        l2x0_pwrst_prepare(cpu, save_state);
+        /*
+         * Call low level function  with targeted low power state.
+         */
+        cpu_suspend(save_state, omap4_finish_suspend);
+        /*
+         * Restore the CPUx power state to ON otherwise CPUx
+         * power domain can transitions to programmed low power
+         * state while doing WFI outside the low powe code. On
+         * secure devices, CPUx does WFI which can result in
+         * domain transition
+         */
+        wakeup_cpu = smp_processor_id();
+        set_cpu_next_pwrst(wakeup_cpu, PWRDM_POWER_ON);
+        pwrdm_post_transition();
+        return 0;
+}
+/**
+ * omap4_hotplug_cpu: OMAP4 CPU hotplug entry
+ * @cpu : CPU ID
+ * @power_state: CPU low power state.
+ */
+int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
+{
+        unsigned int cpu_state = 0;
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return -ENXIO;
+        if (power_state == PWRDM_POWER_OFF)
+                cpu_state = 1;
+        clear_cpu_prev_pwrst(cpu);
+        set_cpu_next_pwrst(cpu, power_state);
+        set_cpu_wakeup_addr(cpu, virt_to_phys(omap_secondary_startup));
+        scu_pwrst_prepare(cpu, power_state);
+        /*
+         * CPU never retuns back if targetted power state is OFF mode.
+         * CPU ONLINE follows normal CPU ONLINE ptah via
+         * omap_secondary_startup().
+         */
+        omap4_finish_suspend(cpu_state);
+        set_cpu_next_pwrst(cpu, PWRDM_POWER_ON);
+        return 0;
+}
+/*
+ * Initialise OMAP4 MPUSS
+ */
+int __init omap4_mpuss_init(void)
+{
+        struct omap4_cpu_pm_info *pm_info;
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+                return -ENODEV;
+        }
+        sar_base = omap4_get_sar_ram_base();
+        /* Initilaise per CPU PM information */
+        pm_info = &per_cpu(omap4_pm_info, 0x0);
+        pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
+        pm_info->wkup_sar_addr = sar_base + CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
+        pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+        pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
+        if (!pm_info->pwrdm) {
+                pr_err("Lookup failed for CPU0 pwrdm\n");
+                return -ENODEV;
+        }
+        /* Clear CPU previous power domain state */
+        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+        cpu_clear_prev_logic_pwrst(0);
+        /* Initialise CPU0 power domain state to ON */
+        pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
+        pm_info = &per_cpu(omap4_pm_info, 0x1);
+        pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
+        pm_info->wkup_sar_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
+        pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+        pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
+        if (!pm_info->pwrdm) {
+                pr_err("Lookup failed for CPU1 pwrdm\n");
+                return -ENODEV;
+        }
+        /* Clear CPU previous power domain state */
+        pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
+        cpu_clear_prev_logic_pwrst(1);
+        /* Initialise CPU1 power domain state to ON */
+        pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
+        mpuss_pd = pwrdm_lookup("mpu_pwrdm");
+        if (!mpuss_pd) {
+                pr_err("Failed to lookup MPUSS power domain\n");
+                return -ENODEV;
+        }
+        pwrdm_clear_all_prev_pwrst(mpuss_pd);
+        mpuss_clear_prev_logic_pwrst();
+        /* Save device type on scratchpad for low level code to use */
+        if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+                __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
+        else
+                __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
+        save_l2x0_context();
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
new file mode 100644
index 00000000000..d8f8ef40290
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -0,0 +1,72 @@
+/*
+ * OMAP Secure API infrastructure.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/memblock.h>
+#include <asm/cacheflush.h>
+#include <asm/memblock.h>
+#include <mach/omap-secure.h>
+static phys_addr_t omap_secure_memblock_base;
+/**
+ * omap_sec_dispatcher: Routine to dispatch low power secure
+ * service routines
+ * @idx: The HAL API index
+ * @flag: The flag indicating criticality of operation
+ * @nargs: Number of valid arguments out of four.
+ * @arg1, arg2, arg3 args4: Parameters passed to secure API
+ *
+ * Return the non-zero error value on failure.
+ */
+u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
+                                                         u32 arg3, u32 arg4)
+{
+        u32 ret;
+        u32 param[5];
+        param[0] = nargs;
+        param[1] = arg1;
+        param[2] = arg2;
+        param[3] = arg3;
+        param[4] = arg4;
+        /*
+         * Secure API needs physical address
+         * pointer for the parameters
+         */
+        flush_cache_all();
+        outer_clean_range(__pa(param), __pa(param + 5));
+        ret = omap_smc2(idx, flag, __pa(param));
+        return ret;
+}
+/* Allocate the memory to save secure ram */
+int __init omap_secure_ram_reserve_memblock(void)
+{
+        u32 size = OMAP_SECURE_RAM_STORAGE;
+        size = ALIGN(size, SZ_1M);
+        omap_secure_memblock_base = arm_memblock_steal(size, SZ_1M);
+        return 0;
+}
+phys_addr_t omap_secure_ram_mempool_base(void)
+{
+        return omap_secure_memblock_base;
+}
diff --git a/arch/arm/mach-omap2/omap-smc.S b/arch/arm/mach-omap2/omap-smc.S
new file mode 100644
index 00000000000..f6441c13cd8
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-smc.S
@@ -0,0 +1,80 @@
+/*
+ * OMAP44xx secure APIs file.
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+/*
+ * This is common routine to manage secure monitor API
+ * used to modify the PL310 secure registers.
+ * 'r0' contains the value to be modified and 'r12' contains
+ * the monitor API number. It uses few CPU registers
+ * internally and hence they need be backed up including
+ * link register "lr".
+ * Function signature : void omap_smc1(u32 fn, u32 arg)
+ */
+ENTRY(omap_smc1)
+        stmfd   sp!, {r2-r12, lr}
+        mov     r12, r0
+        mov     r0, r1
+        dsb
+        smc     #0
+        ldmfd   sp!, {r2-r12, pc}
+ENDPROC(omap_smc1)
+/**
+ * u32 omap_smc2(u32 id, u32 falg, u32 pargs)
+ * Low level common routine for secure HAL and PPA APIs.
+ * @id: Application ID of HAL APIs
+ * @flag: Flag to indicate the criticality of operation
+ * @pargs: Physical address of parameter list starting
+ *          with number of parametrs
+ */
+ENTRY(omap_smc2)
+        stmfd   sp!, {r4-r12, lr}
+        mov     r3, r2
+        mov     r2, r1
+        mov     r1, #0x0        @ Process ID
+        mov     r6, #0xff
+        mov     r12, #0x00      @ Secure Service ID
+        mov     r7, #0
+        mcr     p15, 0, r7, c7, c5, 6
+        dsb
+        dmb
+        smc     #0
+        ldmfd   sp!, {r4-r12, pc}
+ENDPROC(omap_smc2)
+ENTRY(omap_modify_auxcoreboot0)
+        stmfd   sp!, {r1-r12, lr}
+        ldr     r12, =0x104
+        dsb
+        smc     #0
+        ldmfd   sp!, {r1-r12, pc}
+ENDPROC(omap_modify_auxcoreboot0)
+ENTRY(omap_auxcoreboot_addr)
+        stmfd   sp!, {r2-r12, lr}
+        ldr     r12, =0x105
+        dsb
+        smc     #0
+        ldmfd   sp!, {r2-r12, pc}
+ENDPROC(omap_auxcoreboot_addr)
+ENTRY(omap_read_auxcoreboot0)
+        stmfd   sp!, {r2-r12, lr}
+        ldr     r12, =0x103
+        dsb
+        smc     #0
+        mov     r0, r0, lsr #9
+        ldmfd   sp!, {r2-r12, pc}
+ENDPROC(omap_read_auxcoreboot0)
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 4412ddb7b3f..c1bf3ef0ba0 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -24,16 +24,37 @@
 #include <asm/hardware/gic.h>
 #include <asm/smp_scu.h>
 #include <mach/hardware.h>
-#include <mach/omap4-common.h>
+#include <mach/omap-secure.h>
+#include "common.h"
+#include "clockdomain.h"
 /* SCU base address */
 static void __iomem *scu_base;
 static DEFINE_SPINLOCK(boot_lock);
+void __iomem *omap4_get_scu_base(void)
+{
+        return scu_base;
+}
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
        /*
+         * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
+         * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
+         * init and for CPU1, a secure PPA API provided. CPU0 must be ON
+         * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
+         * OMAP443X GP devices- SMP bit isn't accessible.
+         * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
+         */
+        if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+                omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
+                                                        4, 0, 0, 0, 0, 0);
+        /*
         * If any interrupts are already enabled for the primary
         * core (e.g. timer irq), then they will not have been enabled
         * for us: do so
@@ -49,6 +70,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
+        static struct clockdomain *cpu1_clkdm;
+        static bool booted;
        /*
         * Set synchronisation state between this boot processor
         * and the secondary one
@@ -64,6 +87,29 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
        omap_modify_auxcoreboot0(0x200, 0xfffffdff);
        flush_cache_all();
        smp_wmb();
+        if (!cpu1_clkdm)
+                cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
+        /*
+         * The SGI(Software Generated Interrupts) are not wakeup capable
+         * from low power states. This is known limitation on OMAP4 and
+         * needs to be worked around by using software forced clockdomain
+         * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
+         * software force wakeup. The clockdomain is then put back to
+         * hardware supervised mode.
+         * More details can be found in OMAP4430 TRM - Version J
+         * Section :
+         *      4.3.4.2 Power States of CPU0 and CPU1
+         */
+        if (booted) {
+                clkdm_wakeup(cpu1_clkdm);
+                clkdm_allow_idle(cpu1_clkdm);
+        } else {
+                dsb_sev();
+                booted = true;
+        }
        gic_raise_softirq(cpumask_of(cpu), 1);
        /*
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
new file mode 100644
index 00000000000..d3d8971d7f3
--- /dev/null
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -0,0 +1,389 @@
+/*
+ * OMAP WakeupGen Source file
+ *
+ * OMAP WakeupGen is the interrupt controller extension used along
+ * with ARM GIC to wake the CPU out from low power states on
+ * external interrupts. It is responsible for generating wakeup
+ * event from the incoming interrupts and enable bits. It is
+ * implemented in MPU always ON power domain. During normal operation,
+ * WakeupGen delivers external interrupts directly to the GIC.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/cpu.h>
+#include <linux/notifier.h>
+#include <linux/cpu_pm.h>
+#include <asm/hardware/gic.h>
+#include <mach/omap-wakeupgen.h>
+#include <mach/omap-secure.h>
+#include "omap4-sar-layout.h"
+#include "common.h"
+#define NR_REG_BANKS            4
+#define MAX_IRQS                128
+#define WKG_MASK_ALL            0x00000000
+#define WKG_UNMASK_ALL          0xffffffff
+#define CPU_ENA_OFFSET          0x400
+#define CPU0_ID                 0x0
+#define CPU1_ID                 0x1
+static void __iomem *wakeupgen_base;
+static void __iomem *sar_base;
+static DEFINE_PER_CPU(u32 [NR_REG_BANKS], irqmasks);
+static DEFINE_SPINLOCK(wakeupgen_lock);
+static unsigned int irq_target_cpu[NR_IRQS];
+/*
+ * Static helper functions.
+ */
+static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
+{
+        return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
+                                (cpu * CPU_ENA_OFFSET) + (idx * 4));
+}
+static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
+{
+        __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
+                                (cpu * CPU_ENA_OFFSET) + (idx * 4));
+}
+static inline void sar_writel(u32 val, u32 offset, u8 idx)
+{
+        __raw_writel(val, sar_base + offset + (idx * 4));
+}
+static void _wakeupgen_set_all(unsigned int cpu, unsigned int reg)
+{
+        u8 i;
+        for (i = 0; i < NR_REG_BANKS; i++)
+                wakeupgen_writel(reg, i, cpu);
+}
+static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
+{
+        unsigned int spi_irq;
+        /*
+         * PPIs and SGIs are not supported.
+         */
+        if (irq < OMAP44XX_IRQ_GIC_START)
+                return -EINVAL;
+        /*
+         * Subtract the GIC offset.
+         */
+        spi_irq = irq - OMAP44XX_IRQ_GIC_START;
+        if (spi_irq > MAX_IRQS) {
+                pr_err("omap wakeupGen: Invalid IRQ%d\n", irq);
+                return -EINVAL;
+        }
+        /*
+         * Each WakeupGen register controls 32 interrupt.
+         * i.e. 1 bit per SPI IRQ
+         */
+        *reg_index = spi_irq >> 5;
+        *bit_posn = spi_irq %= 32;
+        return 0;
+}
+static void _wakeupgen_clear(unsigned int irq, unsigned int cpu)
+{
+        u32 val, bit_number;
+        u8 i;
+        if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
+                return;
+        val = wakeupgen_readl(i, cpu);
+        val &= ~BIT(bit_number);
+        wakeupgen_writel(val, i, cpu);
+}
+static void _wakeupgen_set(unsigned int irq, unsigned int cpu)
+{
+        u32 val, bit_number;
+        u8 i;
+        if (_wakeupgen_get_irq_info(irq, &bit_number, &i))
+                return;
+        val = wakeupgen_readl(i, cpu);
+        val |= BIT(bit_number);
+        wakeupgen_writel(val, i, cpu);
+}
+static void _wakeupgen_save_masks(unsigned int cpu)
+{
+        u8 i;
+        for (i = 0; i < NR_REG_BANKS; i++)
+                per_cpu(irqmasks, cpu)[i] = wakeupgen_readl(i, cpu);
+}
+static void _wakeupgen_restore_masks(unsigned int cpu)
+{
+        u8 i;
+        for (i = 0; i < NR_REG_BANKS; i++)
+                wakeupgen_writel(per_cpu(irqmasks, cpu)[i], i, cpu);
+}
+/*
+ * Architecture specific Mask extension
+ */
+static void wakeupgen_mask(struct irq_data *d)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&wakeupgen_lock, flags);
+        _wakeupgen_clear(d->irq, irq_target_cpu[d->irq]);
+        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+}
+/*
+ * Architecture specific Unmask extension
+ */
+static void wakeupgen_unmask(struct irq_data *d)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&wakeupgen_lock, flags);
+        _wakeupgen_set(d->irq, irq_target_cpu[d->irq]);
+        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+}
+/*
+ * Mask or unmask all interrupts on given CPU.
+ *      0 = Mask all interrupts on the 'cpu'
+ *      1 = Unmask all interrupts on the 'cpu'
+ * Ensure that the initial mask is maintained. This is faster than
+ * iterating through GIC registers to arrive at the correct masks.
+ */
+static void wakeupgen_irqmask_all(unsigned int cpu, unsigned int set)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&wakeupgen_lock, flags);
+        if (set) {
+                _wakeupgen_save_masks(cpu);
+                _wakeupgen_set_all(cpu, WKG_MASK_ALL);
+        } else {
+                _wakeupgen_set_all(cpu, WKG_UNMASK_ALL);
+                _wakeupgen_restore_masks(cpu);
+        }
+        spin_unlock_irqrestore(&wakeupgen_lock, flags);
+}
+#ifdef CONFIG_CPU_PM
+/*
+ * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
+ * ROM code. WakeupGen IP is integrated along with GIC to manage the
+ * interrupt wakeups from CPU low power states. It manages
+ * masking/unmasking of Shared peripheral interrupts(SPI). So the
+ * interrupt enable/disable control should be in sync and consistent
+ * at WakeupGen and GIC so that interrupts are not lost.
+ */
+static void irq_save_context(void)
+{
+        u32 i, val;
+        if (omap_rev() == OMAP4430_REV_ES1_0)
+                return;
+        if (!sar_base)
+                sar_base = omap4_get_sar_ram_base();
+        for (i = 0; i < NR_REG_BANKS; i++) {
+                /* Save the CPUx interrupt mask for IRQ 0 to 127 */
+                val = wakeupgen_readl(i, 0);
+                sar_writel(val, WAKEUPGENENB_OFFSET_CPU0, i);
+                val = wakeupgen_readl(i, 1);
+                sar_writel(val, WAKEUPGENENB_OFFSET_CPU1, i);
+                /*
+                 * Disable the secure interrupts for CPUx. The restore
+                 * code blindly restores secure and non-secure interrupt
+                 * masks from SAR RAM. Secure interrupts are not suppose
+                 * to be enabled from HLOS. So overwrite the SAR location
+                 * so that the secure interrupt remains disabled.
+                 */
+                sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0, i);
+                sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1, i);
+        }
+        /* Save AuxBoot* registers */
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+        /* Save SyncReq generation logic */
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+        /* Save SyncReq generation logic */
+        val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
+        __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
+        val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
+        __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
+        /* Set the Backup Bit Mask status */
+        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+        val |= SAR_BACKUP_STATUS_WAKEUPGEN;
+        __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+}
+/*
+ * Clear WakeupGen SAR backup status.
+ */
+void irq_sar_clear(void)
+{
+        u32 val;
+        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+        val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
+        __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+}
+/*
+ * Save GIC and Wakeupgen interrupt context using secure API
+ * for HS/EMU devices.
+ */
+static void irq_save_secure_context(void)
+{
+        u32 ret;
+        ret = omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX,
+                                FLAG_START_CRITICAL,
+                                0, 0, 0, 0, 0);
+        if (ret != API_HAL_RET_VALUE_OK)
+                pr_err("GIC and Wakeupgen context save failed\n");
+}
+#endif
+#ifdef CONFIG_HOTPLUG_CPU
+static int __cpuinit irq_cpu_hotplug_notify(struct notifier_block *self,
+                                         unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (unsigned int)hcpu;
+        switch (action) {
+        case CPU_ONLINE:
+                wakeupgen_irqmask_all(cpu, 0);
+                break;
+        case CPU_DEAD:
+                wakeupgen_irqmask_all(cpu, 1);
+                break;
+        }
+        return NOTIFY_OK;
+}
+static struct notifier_block __refdata irq_hotplug_notifier = {
+        .notifier_call = irq_cpu_hotplug_notify,
+};
+static void __init irq_hotplug_init(void)
+{
+        register_hotcpu_notifier(&irq_hotplug_notifier);
+}
+#else
+static void __init irq_hotplug_init(void)
+{}
+#endif
+#ifdef CONFIG_CPU_PM
+static int irq_notifier(struct notifier_block *self, unsigned long cmd, void *v)
+{
+        switch (cmd) {
+        case CPU_CLUSTER_PM_ENTER:
+                if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+                        irq_save_context();
+                else
+                        irq_save_secure_context();
+                break;
+        case CPU_CLUSTER_PM_EXIT:
+                if (omap_type() == OMAP2_DEVICE_TYPE_GP)
+                        irq_sar_clear();
+                break;
+        }
+        return NOTIFY_OK;
+}
+static struct notifier_block irq_notifier_block = {
+        .notifier_call = irq_notifier,
+};
+static void __init irq_pm_init(void)
+{
+        cpu_pm_register_notifier(&irq_notifier_block);
+}
+#else
+static void __init irq_pm_init(void)
+{}
+#endif
+/*
+ * Initialise the wakeupgen module.
+ */
+int __init omap_wakeupgen_init(void)
+{
+        int i;
+        unsigned int boot_cpu = smp_processor_id();
+        /* Not supported on OMAP4 ES1.0 silicon */
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
+                return -EPERM;
+        }
+        /* Static mapping, never released */
+        wakeupgen_base = ioremap(OMAP44XX_WKUPGEN_BASE, SZ_4K);
+        if (WARN_ON(!wakeupgen_base))
+                return -ENOMEM;
+        /* Clear all IRQ bitmasks at wakeupGen level */
+        for (i = 0; i < NR_REG_BANKS; i++) {
+                wakeupgen_writel(0, i, CPU0_ID);
+                wakeupgen_writel(0, i, CPU1_ID);
+        }
+        /*
+         * Override GIC architecture specific functions to add
+         * OMAP WakeupGen interrupt controller along with GIC
+         */
+        gic_arch_extn.irq_mask = wakeupgen_mask;
+        gic_arch_extn.irq_unmask = wakeupgen_unmask;
+        gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;
+        /*
+         * FIXME: Add support to set_smp_affinity() once the core
+         * GIC code has necessary hooks in place.
+         */
+        /* Associate all the IRQs to boot CPU like GIC init does. */
+        for (i = 0; i < NR_IRQS; i++)
+                irq_target_cpu[i] = boot_cpu;
+        irq_hotplug_init();
+        irq_pm_init();
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 35ac3e5f6e9..40a8fbc07e4 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -15,24 +15,76 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/memblock.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/map.h>
+#include <asm/memblock.h>
 #include <plat/irqs.h>
+#include <plat/sram.h>
 #include <mach/hardware.h>
-#include <mach/omap4-common.h>
+#include <mach/omap-wakeupgen.h>
+#include "common.h"
+#include "omap4-sar-layout.h"
 #ifdef CONFIG_CACHE_L2X0
-void __iomem *l2cache_base;
+static void __iomem *l2cache_base;
 #endif
-void __iomem *gic_dist_base_addr;
+static void __iomem *sar_ram_base;
+#ifdef CONFIG_OMAP4_ERRATA_I688
+/* Used to implement memory barrier on DRAM path */
+#define OMAP4_DRAM_BARRIER_VA                   0xfe600000
+void __iomem *dram_sync, *sram_sync;
+void omap_bus_sync(void)
+{
+        if (dram_sync && sram_sync) {
+                writel_relaxed(readl_relaxed(dram_sync), dram_sync);
+                writel_relaxed(readl_relaxed(sram_sync), sram_sync);
+                isb();
+        }
+}
+static int __init omap_barriers_init(void)
+{
+        struct map_desc dram_io_desc[1];
+        phys_addr_t paddr;
+        u32 size;
+        if (!cpu_is_omap44xx())
+                return -ENODEV;
+        size = ALIGN(PAGE_SIZE, SZ_1M);
+        paddr = arm_memblock_steal(size, SZ_1M);
+        dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
+        dram_io_desc[0].pfn = __phys_to_pfn(paddr);
+        dram_io_desc[0].length = size;
+        dram_io_desc[0].type = MT_MEMORY_SO;
+        iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
+        dram_sync = (void __iomem *) dram_io_desc[0].virtual;
+        sram_sync = (void __iomem *) OMAP4_SRAM_VA;
+        pr_info("OMAP4: Map 0x%08llx to 0x%08lx for dram barrier\n",
+                (long long) paddr, dram_io_desc[0].virtual);
+        return 0;
+}
+core_initcall(omap_barriers_init);
+#endif
 void __init gic_init_irq(void)
 {
+        void __iomem *omap_irq_base;
+        void __iomem *gic_dist_base_addr;
        /* Static mapping, never released */
        gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
        BUG_ON(!gic_dist_base_addr);
@@ -41,11 +93,18 @@ void __init gic_init_irq(void)
        omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
        BUG_ON(!omap_irq_base);
+        omap_wakeupgen_init();
        gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
 }
 #ifdef CONFIG_CACHE_L2X0
+void __iomem *omap4_get_l2cache_base(void)
+{
+        return l2cache_base;
+}
 static void omap4_l2x0_disable(void)
 {
        /* Disable PL310 L2 Cache controller */
@@ -71,7 +130,8 @@ static int __init omap_l2_cache_init(void)
        /* Static mapping, never released */
        l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
-        BUG_ON(!l2cache_base);
+        if (WARN_ON(!l2cache_base))
+                return -ENOMEM;
        /*
         * 16-way associativity, parity disabled
@@ -111,3 +171,30 @@ static int __init omap_l2_cache_init(void)
 }
 early_initcall(omap_l2_cache_init);
 #endif
+void __iomem *omap4_get_sar_ram_base(void)
+{
+        return sar_ram_base;
+}
+/*
+ * SAR RAM used to save and restore the HW
+ * context in low power modes
+ */
+static int __init omap4_sar_ram_init(void)
+{
+        /*
+         * To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!cpu_is_omap44xx())
+                return -ENOMEM;
+        /* Static mapping, never released */
+        sar_ram_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K);
+        if (WARN_ON(!sar_ram_base))
+                return -ENOMEM;
+        return 0;
+}
+early_initcall(omap4_sar_ram_init);
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
new file mode 100644
index 00000000000..fe5b545ad44
--- /dev/null
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -0,0 +1,50 @@
+/*
+ * omap4-sar-layout.h: OMAP4 SAR RAM layout header file
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef OMAP_ARCH_OMAP4_SAR_LAYOUT_H
+#define OMAP_ARCH_OMAP4_SAR_LAYOUT_H
+/*
+ * SAR BANK offsets from base address OMAP44XX_SAR_RAM_BASE
+ */
+#define SAR_BANK1_OFFSET                0x0000
+#define SAR_BANK2_OFFSET                0x1000
+#define SAR_BANK3_OFFSET                0x2000
+#define SAR_BANK4_OFFSET                0x3000
+/* Scratch pad memory offsets from SAR_BANK1 */
+#define SCU_OFFSET0                             0xd00
+#define SCU_OFFSET1                             0xd04
+#define OMAP_TYPE_OFFSET                        0xd10
+#define L2X0_SAVE_OFFSET0                       0xd14
+#define L2X0_SAVE_OFFSET1                       0xd18
+#define L2X0_AUXCTRL_OFFSET                     0xd1c
+#define L2X0_PREFETCH_CTRL_OFFSET               0xd20
+/* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
+#define CPU0_WAKEUP_NS_PA_ADDR_OFFSET           0xa04
+#define CPU1_WAKEUP_NS_PA_ADDR_OFFSET           0xa08
+#define SAR_BACKUP_STATUS_OFFSET                (SAR_BANK3_OFFSET + 0x500)
+#define SAR_SECURE_RAM_SIZE_OFFSET              (SAR_BANK3_OFFSET + 0x504)
+#define SAR_SECRAM_SAVED_AT_OFFSET              (SAR_BANK3_OFFSET + 0x508)
+/* WakeUpGen save restore offset from OMAP44XX_SAR_RAM_BASE */
+#define WAKEUPGENENB_OFFSET_CPU0                (SAR_BANK3_OFFSET + 0x684)
+#define WAKEUPGENENB_SECURE_OFFSET_CPU0         (SAR_BANK3_OFFSET + 0x694)
+#define WAKEUPGENENB_OFFSET_CPU1                (SAR_BANK3_OFFSET + 0x6a4)
+#define WAKEUPGENENB_SECURE_OFFSET_CPU1         (SAR_BANK3_OFFSET + 0x6b4)
+#define AUXCOREBOOT0_OFFSET                     (SAR_BANK3_OFFSET + 0x6c4)
+#define AUXCOREBOOT1_OFFSET                     (SAR_BANK3_OFFSET + 0x6c8)
+#define PTMSYNCREQ_MASK_OFFSET                  (SAR_BANK3_OFFSET + 0x6cc)
+#define PTMSYNCREQ_EN_OFFSET                    (SAR_BANK3_OFFSET + 0x6d0)
+#define SAR_BACKUP_STATUS_WAKEUPGEN             0x10
+#endif
diff --git a/arch/arm/mach-omap2/omap44xx-smc.S b/arch/arm/mach-omap2/omap44xx-smc.S
deleted file mode 100644
index e69d37d9520..00000000000
--- a/arch/arm/mach-omap2/omap44xx-smc.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * OMAP44xx secure APIs file.
- *
- * Copyright (C) 2010 Texas Instruments, Inc.
- * Written by Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- *
- * This program is free software,you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-/*
- * This is common routine to manage secure monitor API
- * used to modify the PL310 secure registers.
- * 'r0' contains the value to be modified and 'r12' contains
- * the monitor API number. It uses few CPU registers
- * internally and hence they need be backed up including
- * link register "lr".
- * Function signature : void omap_smc1(u32 fn, u32 arg)
- */
-ENTRY(omap_smc1)
-        stmfd   sp!, {r2-r12, lr}
-        mov     r12, r0
-        mov     r0, r1
-        dsb
-        smc     #0
-        ldmfd   sp!, {r2-r12, pc}
-ENDPROC(omap_smc1)
-ENTRY(omap_modify_auxcoreboot0)
-        stmfd   sp!, {r1-r12, lr}
-        ldr     r12, =0x104
-        dsb
-        smc     #0
-        ldmfd   sp!, {r1-r12, pc}
-ENDPROC(omap_modify_auxcoreboot0)
-ENTRY(omap_auxcoreboot_addr)
-        stmfd   sp!, {r2-r12, lr}
-        ldr     r12, =0x105
-        dsb
-        smc     #0
-        ldmfd   sp!, {r2-r12, pc}
-ENDPROC(omap_auxcoreboot_addr)
-ENTRY(omap_read_auxcoreboot0)
-        stmfd   sp!, {r2-r12, lr}
-        ldr     r12, =0x103
-        dsb
-        smc     #0
-        mov     r0, r0, lsr #9
-        ldmfd   sp!, {r2-r12, pc}
-ENDPROC(omap_read_auxcoreboot0)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 207a2ff9a8c..5192cabb40e 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -136,8 +136,9 @@
 #include <linux/list.h>
 #include <linux/mutex.h>
 #include <linux/spinlock.h>
+#include <linux/slab.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/cpu.h>
 #include "clockdomain.h"
 #include "powerdomain.h"
@@ -381,6 +382,51 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
 }
 /**
+ * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
+ * @oh: struct omap_hwmod *
+ * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
+ *
+ * Set or clear the I/O pad wakeup flag in the mux entries for the
+ * hwmod @oh.  This function changes the @oh->mux->pads_dynamic array
+ * in memory.  If the hwmod is currently idled, and the new idle
+ * values don't match the previous ones, this function will also
+ * update the SCM PADCTRL registers.  Otherwise, if the hwmod is not
+ * currently idled, this function won't touch the hardware: the new
+ * mux settings are written to the SCM PADCTRL registers when the
+ * hwmod is idled.  No return value.
+ */
+static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
+{
+        struct omap_device_pad *pad;
+        bool change = false;
+        u16 prev_idle;
+        int j;
+        if (!oh->mux || !oh->mux->enabled)
+                return;
+        for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
+                pad = oh->mux->pads_dynamic[j];
+                if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
+                        continue;
+                prev_idle = pad->idle;
+                if (set_wake)
+                        pad->idle |= OMAP_WAKEUP_EN;
+                else
+                        pad->idle &= ~OMAP_WAKEUP_EN;
+                if (prev_idle != pad->idle)
+                        change = true;
+        }
+        if (change && oh->_state == _HWMOD_STATE_IDLE)
+                omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
+}
+/**
 * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
 * @oh: struct omap_hwmod *
 *
@@ -706,27 +752,65 @@ static void _enable_module(struct omap_hwmod *oh)
 }
 /**
- * _disable_module - enable CLKCTRL modulemode on OMAP4
+ * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to enter slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully enters
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_idle() function.
+ */
+static int _omap4_wait_target_disable(struct omap_hwmod *oh)
+{
+        if (!cpu_is_omap44xx())
+                return 0;
+        if (!oh)
+                return -EINVAL;
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+                return 0;
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+        return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
+                                             oh->clkdm->cm_inst,
+                                             oh->clkdm->clkdm_offs,
+                                             oh->prcm.omap4.clkctrl_offs);
+}
+/**
+ * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
 * @oh: struct omap_hwmod *
 *
 * Disable the PRCM module mode related to the hwmod @oh.
- * No return value.
+ * Return EINVAL if the modulemode is not supported and 0 in case of success.
 */
-static void _disable_module(struct omap_hwmod *oh)
+static int _omap4_disable_module(struct omap_hwmod *oh)
 {
+        int v;
        /* The module mode does not exist prior OMAP4 */
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+        if (!cpu_is_omap44xx())
-                return;
+                return -EINVAL;
        if (!oh->clkdm || !oh->prcm.omap4.modulemode)
-                return;
+                return -EINVAL;
-        pr_debug("omap_hwmod: %s: _disable_module\n", oh->name);
+        pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
        omap4_cminst_module_disable(oh->clkdm->prcm_partition,
                                    oh->clkdm->cm_inst,
                                    oh->clkdm->clkdm_offs,
                                    oh->prcm.omap4.clkctrl_offs);
+        v = _omap4_wait_target_disable(oh);
+        if (v)
+                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+                        oh->name);
+        return 0;
 }
 /**
@@ -1153,36 +1237,6 @@ static int _wait_target_ready(struct omap_hwmod *oh)
 }
 /**
- * _wait_target_disable - wait for a module to be disabled
- * @oh: struct omap_hwmod *
- *
- * Wait for a module @oh to enter slave idle.  Returns 0 if the module
- * does not have an IDLEST bit or if the module successfully enters
- * slave idle; otherwise, pass along the return value of the
- * appropriate *_cm*_wait_module_idle() function.
- */
-static int _wait_target_disable(struct omap_hwmod *oh)
-{
-        /* TODO: For now just handle OMAP4+ */
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                return 0;
-        if (!oh)
-                return -EINVAL;
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
-                return 0;
-        if (oh->flags & HWMOD_NO_IDLEST)
-                return 0;
-        return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
-                                             oh->clkdm->cm_inst,
-                                             oh->clkdm->clkdm_offs,
-                                             oh->prcm.omap4.clkctrl_offs);
-}
-/**
 * _lookup_hardreset - fill register bit info for this hwmod/reset line
 * @oh: struct omap_hwmod *
 * @name: name of the reset line in the context of this hwmod
@@ -1441,6 +1495,25 @@ static int _enable(struct omap_hwmod *oh)
        pr_debug("omap_hwmod: %s: enabling\n", oh->name);
+        /*
+         * hwmods with HWMOD_INIT_NO_IDLE flag set are left
+         * in enabled state at init.
+         * Now that someone is really trying to enable them,
+         * just ensure that the hwmod mux is set.
+         */
+        if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
+                /*
+                 * If the caller has mux data populated, do the mux'ing
+                 * which wouldn't have been done as part of the _enable()
+                 * done during setup.
+                 */
+                if (oh->mux)
+                        omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
+                oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
+                return 0;
+        }
        if (oh->_state != _HWMOD_STATE_INITIALIZED &&
            oh->_state != _HWMOD_STATE_IDLE &&
            oh->_state != _HWMOD_STATE_DISABLED) {
@@ -1524,8 +1597,6 @@ static int _enable(struct omap_hwmod *oh)
 */
 static int _idle(struct omap_hwmod *oh)
 {
-        int ret;
        pr_debug("omap_hwmod: %s: idling\n", oh->name);
        if (oh->_state != _HWMOD_STATE_ENABLED) {
@@ -1537,11 +1608,9 @@ static int _idle(struct omap_hwmod *oh)
        if (oh->class->sysc)
                _idle_sysc(oh);
        _del_initiator_dep(oh, mpu_oh);
-        _disable_module(oh);
-        ret = _wait_target_disable(oh);
+        _omap4_disable_module(oh);
-        if (ret)
-                pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
-                        oh->name);
        /*
         * The module must be in idle mode before disabling any parents
         * clocks. Otherwise, the parent clock might be disabled before
@@ -1642,11 +1711,7 @@ static int _shutdown(struct omap_hwmod *oh)
        if (oh->_state == _HWMOD_STATE_ENABLED) {
                _del_initiator_dep(oh, mpu_oh);
                /* XXX what about the other system initiators here? dma, dsp */
-                _disable_module(oh);
+                _omap4_disable_module(oh);
-                ret = _wait_target_disable(oh);
-                if (ret)
-                        pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
-                                oh->name);
                _disable_clocks(oh);
                if (oh->clkdm)
                        clkdm_hwmod_disable(oh->clkdm, oh);
@@ -1744,8 +1809,10 @@ static int _setup(struct omap_hwmod *oh, void *data)
         * it should be set by the core code as a runtime flag during startup
         */
        if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
-            (postsetup_state == _HWMOD_STATE_IDLE))
+            (postsetup_state == _HWMOD_STATE_IDLE)) {
+                oh->_int_flags |= _HWMOD_SKIP_ENABLE;
                postsetup_state = _HWMOD_STATE_ENABLED;
+        }
        if (postsetup_state == _HWMOD_STATE_IDLE)
                _idle(oh);
@@ -2416,6 +2483,7 @@ int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
        v = oh->_sysc_cache;
        _enable_wakeup(oh, &v);
        _write_sysconfig(v, oh);
+        _set_idle_ioring_wakeup(oh, true);
        spin_unlock_irqrestore(&oh->_lock, flags);
        return 0;
@@ -2446,6 +2514,7 @@ int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
        v = oh->_sysc_cache;
        _disable_wakeup(oh, &v);
        _write_sysconfig(v, oh);
+        _set_idle_ioring_wakeup(oh, false);
        spin_unlock_irqrestore(&oh->_lock, flags);
        return 0;
@@ -2662,3 +2731,57 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
        return 0;
 }
+/**
+ * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ
+ * @oh: struct omap_hwmod * containing hwmod mux entries
+ * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup
+ * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup
+ *
+ * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux
+ * entry number @pad_idx for the hwmod @oh, trigger the interrupt
+ * service routine for the hwmod's mpu_irqs array index @irq_idx.  If
+ * this function is not called for a given pad_idx, then the ISR
+ * associated with @oh's first MPU IRQ will be triggered when an I/O
+ * pad wakeup occurs on that pad.  Note that @pad_idx is the index of
+ * the _dynamic or wakeup_ entry: if there are other entries not
+ * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these
+ * entries are NOT COUNTED in the dynamic pad index.  This function
+ * must be called separately for each pad that requires its interrupt
+ * to be re-routed this way.  Returns -EINVAL if there is an argument
+ * problem or if @oh does not have hwmod mux entries or MPU IRQs;
+ * returns -ENOMEM if memory cannot be allocated; or 0 upon success.
+ *
+ * XXX This function interface is fragile.  Rather than using array
+ * indexes, which are subject to unpredictable change, it should be
+ * using hwmod IRQ names, and some other stable key for the hwmod mux
+ * pad records.
+ */
+int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
+{
+        int nr_irqs;
+        might_sleep();
+        if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 ||
+            pad_idx >= oh->mux->nr_pads_dynamic)
+                return -EINVAL;
+        /* Check the number of available mpu_irqs */
+        for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++)
+                ;
+        if (irq_idx >= nr_irqs)
+                return -EINVAL;
+        if (!oh->mux->irqs) {
+                /* XXX What frees this? */
+                oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic,
+                        GFP_KERNEL);
+                if (!oh->mux->irqs)
+                        return -ENOMEM;
+        }
+        oh->mux->irqs[pad_idx] = irq_idx;
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index eef43e2e163..5324e8d93bc 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -84,6 +84,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
+static struct omap_hwmod omap3xxx_usb_host_hs_hwmod;
+static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod;
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -164,6 +166,7 @@ static struct omap_hwmod omap3xxx_uart1_hwmod;
 static struct omap_hwmod omap3xxx_uart2_hwmod;
 static struct omap_hwmod omap3xxx_uart3_hwmod;
 static struct omap_hwmod omap3xxx_uart4_hwmod;
+static struct omap_hwmod am35xx_uart4_hwmod;
 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 /* l3_core -> usbhsotg interface */
@@ -299,6 +302,23 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
+/* AM35xx: L4 CORE -> UART4 interface */
+static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
+        {
+                .pa_start       = OMAP3_UART4_AM35XX_BASE,
+                .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
+                .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+        },
+};
+static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_uart4_hwmod,
+        .clk            = "uart4_ick",
+        .addr           = am35xx_uart4_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 /* L4 CORE -> I2C1 interface */
 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
        .master         = &omap3xxx_l4_core_hwmod,
@@ -1162,6 +1182,7 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .clockact       = CLOCKACT_TEST_ICLK,
        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -1309,6 +1330,39 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
        .class          = &omap2_uart_class,
 };
+static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
+        { .irq = INT_35XX_UART4_IRQ, },
+};
+static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
+        { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
+        { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
+};
+static struct omap_hwmod_ocp_if *am35xx_uart4_slaves[] = {
+        &am35xx_l4_core__uart4,
+};
+static struct omap_hwmod am35xx_uart4_hwmod = {
+        .name           = "uart4",
+        .mpu_irqs       = am35xx_uart4_mpu_irqs,
+        .sdma_reqs      = am35xx_uart4_sdma_reqs,
+        .main_clk       = "uart4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_UART4_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
+                },
+        },
+        .slaves         = am35xx_uart4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(am35xx_uart4_slaves),
+        .class          = &omap2_uart_class,
+};
 static struct omap_hwmod_class i2c_class = {
        .name   = "i2c",
        .sysc   = &i2c_sysc,
@@ -1636,7 +1690,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
        .name           = "i2c1",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap2_i2c1_mpu_irqs,
        .sdma_reqs      = omap2_i2c1_sdma_reqs,
        .main_clk       = "i2c1_fck",
@@ -1670,7 +1724,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
        .name           = "i2c2",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap2_i2c2_mpu_irqs,
        .sdma_reqs      = omap2_i2c2_sdma_reqs,
        .main_clk       = "i2c2_fck",
@@ -1715,7 +1769,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
        .name           = "i2c3",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = i2c3_mpu_irqs,
        .sdma_reqs      = i2c3_sdma_reqs,
        .main_clk       = "i2c3_fck",
@@ -3072,7 +3126,35 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
        .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 };
-static struct omap_hwmod omap3xxx_mmc1_hwmod = {
+/* See 35xx errata 2.1.1.128 in SPRZ278F */
+static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
+        .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
+                  OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
+};
+static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
+        .name           = "mmc1",
+        .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
+        .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
+        .opt_clks       = omap34xx_mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
+        .main_clk       = "mmchs1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MMC1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
+                },
+        },
+        .dev_attr       = &mmc1_pre_es3_dev_attr,
+        .slaves         = omap3xxx_mmc1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
+        .class          = &omap34xx_mmc_class,
+};
+static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
        .name           = "mmc1",
        .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
        .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
@@ -3115,7 +3197,34 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
        &omap3xxx_l4_core__mmc2,
 };
-static struct omap_hwmod omap3xxx_mmc2_hwmod = {
+/* See 35xx errata 2.1.1.128 in SPRZ278F */
+static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
+        .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
+};
+static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
+        .name           = "mmc2",
+        .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
+        .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
+        .opt_clks       = omap34xx_mmc2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
+        .main_clk       = "mmchs2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MMC2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
+                },
+        },
+        .dev_attr       = &mmc2_pre_es3_dev_attr,
+        .slaves         = omap3xxx_mmc2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
+        .class          = &omap34xx_mmc_class,
+};
+static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
        .name           = "mmc2",
        .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
        .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
@@ -3177,13 +3286,223 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
        .class          = &omap34xx_mmc_class,
 };
+/*
+ * 'usb_host_hs' class
+ * high-speed multi-port usb host controller
+ */
+static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
+        .master         = &omap3xxx_usb_host_hs_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
+        .name = "usb_host_hs",
+        .sysc = &omap3xxx_usb_host_hs_sysc,
+};
+static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_masters[] = {
+        &omap3xxx_usb_host_hs__l3_main_2,
+};
+static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
+        {
+                .name           = "uhh",
+                .pa_start       = 0x48064000,
+                .pa_end         = 0x480643ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "ohci",
+                .pa_start       = 0x48064400,
+                .pa_end         = 0x480647ff,
+        },
+        {
+                .name           = "ehci",
+                .pa_start       = 0x48064800,
+                .pa_end         = 0x48064cff,
+        },
+        {}
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_usb_host_hs_hwmod,
+        .clk            = "usbhost_ick",
+        .addr           = omap3xxx_usb_host_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if *omap3xxx_usb_host_hs_slaves[] = {
+        &omap3xxx_l4_core__usb_host_hs,
+};
+static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
+          { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
+};
+static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
+        { .name = "ohci-irq", .irq = 76 },
+        { .name = "ehci-irq", .irq = 77 },
+        { .irq = -1 }
+};
+static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
+        .name           = "usb_host_hs",
+        .class          = &omap3xxx_usb_host_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
+        .main_clk       = "usbhost_48m_fck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = OMAP3430ES2_USBHOST_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
+                        .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
+                },
+        },
+        .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
+        .slaves         = omap3xxx_usb_host_hs_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usb_host_hs_slaves),
+        .masters        = omap3xxx_usb_host_hs_masters,
+        .masters_cnt    = ARRAY_SIZE(omap3xxx_usb_host_hs_masters),
+        /*
+         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
+         * id: i660
+         *
+         * Description:
+         * In the following configuration :
+         * - USBHOST module is set to smart-idle mode
+         * - PRCM asserts idle_req to the USBHOST module ( This typically
+         *   happens when the system is going to a low power mode : all ports
+         *   have been suspended, the master part of the USBHOST module has
+         *   entered the standby state, and SW has cut the functional clocks)
+         * - an USBHOST interrupt occurs before the module is able to answer
+         *   idle_ack, typically a remote wakeup IRQ.
+         * Then the USB HOST module will enter a deadlock situation where it
+         * is no more accessible nor functional.
+         *
+         * Workaround:
+         * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
+         */
+        /*
+         * Errata: USB host EHCI may stall when entering smart-standby mode
+         * Id: i571
+         *
+         * Description:
+         * When the USBHOST module is set to smart-standby mode, and when it is
+         * ready to enter the standby state (i.e. all ports are suspended and
+         * all attached devices are in suspend mode), then it can wrongly assert
+         * the Mstandby signal too early while there are still some residual OCP
+         * transactions ongoing. If this condition occurs, the internal state
+         * machine may go to an undefined state and the USB link may be stuck
+         * upon the next resume.
+         *
+         * Workaround:
+         * Don't use smart standby; use only force standby,
+         * hence HWMOD_SWSUP_MSTANDBY
+         */
+        /*
+         * During system boot; If the hwmod framework resets the module
+         * the module will have smart idle settings; which can lead to deadlock
+         * (above Errata Id:i660); so, dont reset the module during boot;
+         * Use HWMOD_INIT_NO_RESET.
+         */
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+                          HWMOD_INIT_NO_RESET,
+};
+/*
+ * 'usb_tll_hs' class
+ * usb_tll_hs module is the adapter on the usb_host_hs ports
+ */
+static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
+        .name = "usb_tll_hs",
+        .sysc = &omap3xxx_usb_tll_hs_sysc,
+};
+static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
+        { .name = "tll-irq", .irq = 78 },
+        { .irq = -1 }
+};
+static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
+        {
+                .name           = "tll",
+                .pa_start       = 0x48062000,
+                .pa_end         = 0x48062fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {}
+};
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_usb_tll_hs_hwmod,
+        .clk            = "usbtll_ick",
+        .addr           = omap3xxx_usb_tll_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if *omap3xxx_usb_tll_hs_slaves[] = {
+        &omap3xxx_l4_core__usb_tll_hs,
+};
+static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
+        .name           = "usb_tll_hs",
+        .class          = &omap3xxx_usb_tll_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
+        .main_clk       = "usbtll_fck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 3,
+                        .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
+                        .idlest_reg_id = 3,
+                        .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_usb_tll_hs_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_usb_tll_hs_slaves),
+};
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap3xxx_l3_main_hwmod,
        &omap3xxx_l4_core_hwmod,
        &omap3xxx_l4_per_hwmod,
        &omap3xxx_l4_wkup_hwmod,
-        &omap3xxx_mmc1_hwmod,
-        &omap3xxx_mmc2_hwmod,
        &omap3xxx_mmc3_hwmod,
        &omap3xxx_mpu_hwmod,
@@ -3198,12 +3517,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        &omap3xxx_timer9_hwmod,
        &omap3xxx_timer10_hwmod,
        &omap3xxx_timer11_hwmod,
-        &omap3xxx_timer12_hwmod,
        &omap3xxx_wd_timer2_hwmod,
        &omap3xxx_uart1_hwmod,
        &omap3xxx_uart2_hwmod,
        &omap3xxx_uart3_hwmod,
        /* dss class */
        &omap3xxx_dss_dispc_hwmod,
        &omap3xxx_dss_dsi1_hwmod,
@@ -3245,6 +3564,12 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
        NULL,
 };
+/* GP-only hwmods */
+static __initdata struct omap_hwmod *omap3xxx_gp_hwmods[] = {
+        &omap3xxx_timer12_hwmod,
+        NULL
+};
 /* 3430ES1-only hwmods */
 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
        &omap3430es1_dss_core_hwmod,
@@ -3255,6 +3580,22 @@ static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
        &omap3xxx_dss_core_hwmod,
        &omap3xxx_usbhsotg_hwmod,
+        &omap3xxx_usb_host_hs_hwmod,
+        &omap3xxx_usb_tll_hs_hwmod,
+        NULL
+};
+/* <= 3430ES3-only hwmods */
+static struct omap_hwmod *omap3430_pre_es3_hwmods[] __initdata = {
+        &omap3xxx_pre_es3_mmc1_hwmod,
+        &omap3xxx_pre_es3_mmc2_hwmod,
+        NULL
+};
+/* 3430ES3+-only hwmods */
+static struct omap_hwmod *omap3430_es3plus_hwmods[] __initdata = {
+        &omap3xxx_es3plus_mmc1_hwmod,
+        &omap3xxx_es3plus_mmc2_hwmod,
        NULL
 };
@@ -3276,12 +3617,21 @@ static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
        &omap36xx_sr2_hwmod,
        &omap3xxx_usbhsotg_hwmod,
        &omap3xxx_mailbox_hwmod,
+        &omap3xxx_usb_host_hs_hwmod,
+        &omap3xxx_usb_tll_hs_hwmod,
+        &omap3xxx_es3plus_mmc1_hwmod,
+        &omap3xxx_es3plus_mmc2_hwmod,
        NULL
 };
 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
        &omap3xxx_dss_core_hwmod, /* XXX ??? */
        &am35xx_usbhsotg_hwmod,
+        &am35xx_uart4_hwmod,
+        &omap3xxx_usb_host_hs_hwmod,
+        &omap3xxx_usb_tll_hs_hwmod,
+        &omap3xxx_es3plus_mmc1_hwmod,
+        &omap3xxx_es3plus_mmc2_hwmod,
        NULL
 };
@@ -3296,6 +3646,13 @@ int __init omap3xxx_hwmod_init(void)
        if (r < 0)
                return r;
+        /* Register GP-only hwmods. */
+        if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
+                r = omap_hwmod_register(omap3xxx_gp_hwmods);
+                if (r < 0)
+                        return r;
+        }
        rev = omap_rev();
        /*
@@ -3334,6 +3691,21 @@ int __init omap3xxx_hwmod_init(void)
                h = omap3430es2plus_hwmods;
        };
+        if (h) {
+                r = omap_hwmod_register(h);
+                if (r < 0)
+                        return r;
+        }
+        h = NULL;
+        if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
+            rev == OMAP3430_REV_ES2_1) {
+                h = omap3430_pre_es3_hwmods;
+        } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
+                   rev == OMAP3430_REV_ES3_1_2) {
+                h = omap3430_es3plus_hwmods;
+        };
        if (h)
                r = omap_hwmod_register(h);
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index daaf165af69..f9f15108176 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -70,6 +70,8 @@ static struct omap_hwmod omap44xx_mmc2_hwmod;
 static struct omap_hwmod omap44xx_mpu_hwmod;
 static struct omap_hwmod omap44xx_mpu_private_hwmod;
 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
+static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
+static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
 /*
 * Interconnects omap_hwmod structures
@@ -2246,6 +2248,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
                           SIDLE_SMART_WKUP),
+        .clockact       = CLOCKACT_TEST_ICLK,
        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
@@ -2300,7 +2303,7 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
        .name           = "i2c1",
        .class          = &omap44xx_i2c_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_i2c1_irqs,
        .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
        .main_clk       = "i2c1_fck",
@@ -2356,7 +2359,7 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
        .name           = "i2c2",
        .class          = &omap44xx_i2c_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_i2c2_irqs,
        .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
        .main_clk       = "i2c2_fck",
@@ -2412,7 +2415,7 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
        .name           = "i2c3",
        .class          = &omap44xx_i2c_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_i2c3_irqs,
        .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
        .main_clk       = "i2c3_fck",
@@ -2468,7 +2471,7 @@ static struct omap_hwmod omap44xx_i2c4_hwmod = {
        .name           = "i2c4",
        .class          = &omap44xx_i2c_hwmod_class,
        .clkdm_name     = "l4_per_clkdm",
-        .flags          = HWMOD_16BIT_REG,
+        .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
        .mpu_irqs       = omap44xx_i2c4_irqs,
        .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
        .main_clk       = "i2c4_fck",
@@ -5276,6 +5279,207 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
        .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
 };
+/*
+ * 'usb_host_hs' class
+ * high-speed multi-port usb host controller
+ */
+static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
+        .master         = &omap44xx_usb_host_hs_hwmod,
+        .slave          = &omap44xx_l3_main_2_hwmod,
+        .clk            = "l3_div_ck",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
+        .name = "usb_host_hs",
+        .sysc = &omap44xx_usb_host_hs_sysc,
+};
+static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
+        &omap44xx_usb_host_hs__l3_main_2,
+};
+static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
+        {
+                .name           = "uhh",
+                .pa_start       = 0x4a064000,
+                .pa_end         = 0x4a0647ff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {
+                .name           = "ohci",
+                .pa_start       = 0x4a064800,
+                .pa_end         = 0x4a064bff,
+        },
+        {
+                .name           = "ehci",
+                .pa_start       = 0x4a064c00,
+                .pa_end         = 0x4a064fff,
+        },
+        {}
+};
+static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
+        { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
+        { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_usb_host_hs_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_usb_host_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
+        &omap44xx_l4_cfg__usb_host_hs,
+};
+static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
+        .name           = "usb_host_hs",
+        .class          = &omap44xx_usb_host_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .main_clk       = "usb_host_hs_fck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .mpu_irqs       = omap44xx_usb_host_hs_irqs,
+        .slaves         = omap44xx_usb_host_hs_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
+        .masters        = omap44xx_usb_host_hs_masters,
+        .masters_cnt    = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
+        /*
+         * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
+         * id: i660
+         *
+         * Description:
+         * In the following configuration :
+         * - USBHOST module is set to smart-idle mode
+         * - PRCM asserts idle_req to the USBHOST module ( This typically
+         *   happens when the system is going to a low power mode : all ports
+         *   have been suspended, the master part of the USBHOST module has
+         *   entered the standby state, and SW has cut the functional clocks)
+         * - an USBHOST interrupt occurs before the module is able to answer
+         *   idle_ack, typically a remote wakeup IRQ.
+         * Then the USB HOST module will enter a deadlock situation where it
+         * is no more accessible nor functional.
+         *
+         * Workaround:
+         * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
+         */
+        /*
+         * Errata: USB host EHCI may stall when entering smart-standby mode
+         * Id: i571
+         *
+         * Description:
+         * When the USBHOST module is set to smart-standby mode, and when it is
+         * ready to enter the standby state (i.e. all ports are suspended and
+         * all attached devices are in suspend mode), then it can wrongly assert
+         * the Mstandby signal too early while there are still some residual OCP
+         * transactions ongoing. If this condition occurs, the internal state
+         * machine may go to an undefined state and the USB link may be stuck
+         * upon the next resume.
+         *
+         * Workaround:
+         * Don't use smart standby; use only force standby,
+         * hence HWMOD_SWSUP_MSTANDBY
+         */
+        /*
+         * During system boot; If the hwmod framework resets the module
+         * the module will have smart idle settings; which can lead to deadlock
+         * (above Errata Id:i660); so, dont reset the module during boot;
+         * Use HWMOD_INIT_NO_RESET.
+         */
+        .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
+                          HWMOD_INIT_NO_RESET,
+};
+/*
+ * 'usb_tll_hs' class
+ * usb_tll_hs module is the adapter on the usb_host_hs ports
+ */
+static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
+        .name = "usb_tll_hs",
+        .sysc = &omap44xx_usb_tll_hs_sysc,
+};
+static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
+        { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
+        {
+                .name           = "tll",
+                .pa_start       = 0x4a062000,
+                .pa_end         = 0x4a063fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        {}
+};
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_usb_tll_hs_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_usb_tll_hs_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
+        &omap44xx_l4_cfg__usb_tll_hs,
+};
+static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
+        .name           = "usb_tll_hs",
+        .class          = &omap44xx_usb_tll_hs_hwmod_class,
+        .clkdm_name     = "l3_init_clkdm",
+        .main_clk       = "usb_tll_hs_ick",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
+        .slaves         = omap44xx_usb_tll_hs_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
+};
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
        /* dmm class */
@@ -5415,13 +5619,16 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
        &omap44xx_uart3_hwmod,
        &omap44xx_uart4_hwmod,
+        /* usb host class */
+        &omap44xx_usb_host_hs_hwmod,
+        &omap44xx_usb_tll_hs_hwmod,
        /* usb_otg_hs class */
        &omap44xx_usb_otg_hs_hwmod,
        /* wd_timer class */
        &omap44xx_wd_timer2_hwmod,
        &omap44xx_wd_timer3_hwmod,
        NULL,
 };
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 58775e3c847..4c90477e6f8 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -260,3 +260,38 @@ void am35x_set_mode(u8 musb_mode)
        omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
 }
+void ti81xx_musb_phy_power(u8 on)
+{
+        void __iomem *scm_base = NULL;
+        u32 usbphycfg;
+        scm_base = ioremap(TI81XX_SCM_BASE, SZ_2K);
+        if (!scm_base) {
+                pr_err("system control module ioremap failed\n");
+                return;
+        }
+        usbphycfg = __raw_readl(scm_base + USBCTRL0);
+        if (on) {
+                if (cpu_is_ti816x()) {
+                        usbphycfg |= TI816X_USBPHY0_NORMAL_MODE;
+                        usbphycfg &= ~TI816X_USBPHY_REFCLK_OSC;
+                } else if (cpu_is_ti814x()) {
+                        usbphycfg &= ~(USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN
+                                | USBPHY_DPINPUT | USBPHY_DMINPUT);
+                        usbphycfg |= (USBPHY_OTGVDET_EN | USBPHY_OTGSESSEND_EN
+                                | USBPHY_DPOPBUFCTL | USBPHY_DMOPBUFCTL);
+                }
+        } else {
+                if (cpu_is_ti816x())
+                        usbphycfg &= ~TI816X_USBPHY0_NORMAL_MODE;
+                else if (cpu_is_ti814x())
+                        usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
+        }
+        __raw_writel(usbphycfg, scm_base + USBCTRL0);
+        iounmap(scm_base);
+}
diff --git a/arch/arm/mach-omap2/opp2xxx.h b/arch/arm/mach-omap2/opp2xxx.h
index 8affc66a92c..8fae534eb15 100644
--- a/arch/arm/mach-omap2/opp2xxx.h
+++ b/arch/arm/mach-omap2/opp2xxx.h
@@ -51,7 +51,7 @@ struct prcm_config {
        unsigned long cm_clksel2_pll;   /* dpllx1 or x2 out */
        unsigned long cm_clksel_mdm;    /* modem dividers 2430 only */
        unsigned long base_sdrc_rfr;    /* base refresh timing for a set */
-        unsigned char flags;
+        unsigned short flags;
 };
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 00bff46ca48..1881fe91514 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -18,7 +18,7 @@
 #include <plat/omap-pm.h>
 #include <plat/omap_device.h>
-#include <plat/common.h>
+#include "common.h"
 #include "voltage.h"
 #include "powerdomain.h"
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 4e166add2f3..b737b11e449 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -21,6 +21,7 @@ extern void omap_sram_idle(void);
 extern int omap3_can_sleep(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
 extern int omap3_idle_init(void);
+extern int omap4_idle_init(void);
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index cf0c216132a..b8822f8b289 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -30,7 +30,6 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
-#include <linux/console.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
@@ -42,6 +41,7 @@
 #include <plat/dma.h>
 #include <plat/board.h>
+#include "common.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 #include "cm2xxx_3xxx.h"
@@ -126,27 +126,11 @@ static void omap2_enter_full_retention(void)
        if (omap_irq_pending())
                goto no_sleep;
-        /* Block console output in case it is on one of the OMAP UARTs */
-        if (!is_suspending())
-                if (!console_trylock())
-                        goto no_sleep;
-        omap_uart_prepare_idle(0);
-        omap_uart_prepare_idle(1);
-        omap_uart_prepare_idle(2);
        /* Jump to SRAM suspend code */
        omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
                           OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
                           OMAP_SDRC_REGADDR(SDRC_POWER));
-        omap_uart_resume_idle(2);
-        omap_uart_resume_idle(1);
-        omap_uart_resume_idle(0);
-        if (!is_suspending())
-                console_unlock();
 no_sleep:
        omap2_gpio_resume_after_idle();
@@ -238,8 +222,6 @@ static int omap2_can_sleep(void)
 {
        if (omap2_fclks_active())
                return 0;
-        if (!omap_uart_can_sleep())
-                return 0;
        if (osc_ck->usecount > 1)
                return 0;
        if (omap_dma_running())
@@ -290,7 +272,6 @@ static int omap2_pm_suspend(void)
        mir1 = omap_readl(0x480fe0a4);
        omap_writel(1 << 5, 0x480fe0ac);
-        omap_uart_prepare_suspend();
        omap2_enter_full_retention();
        omap_writel(mir1, 0x480fe0a4);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index efa66494c1e..fc698757892 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,7 +28,6 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
-#include <linux/console.h>
 #include <trace/events/power.h>
 #include <asm/suspend.h>
@@ -36,12 +35,12 @@
 #include <plat/sram.h>
 #include "clockdomain.h"
 #include "powerdomain.h"
-#include <plat/serial.h>
 #include <plat/sdrc.h>
 #include <plat/prcm.h>
 #include <plat/gpmc.h>
 #include <plat/dma.h>
+#include "common.h"
 #include "cm2xxx_3xxx.h"
 #include "cm-regbits-34xx.h"
 #include "prm-regbits-34xx.h"
@@ -53,15 +52,6 @@
 #ifdef CONFIG_SUSPEND
 static suspend_state_t suspend_state = PM_SUSPEND_ON;
-static inline bool is_suspending(void)
-{
-        return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
-}
-#else
-static inline bool is_suspending(void)
-{
-        return false;
-}
 #endif
 /* pm34xx errata defined in pm.h */
@@ -194,7 +184,7 @@ static void omap3_save_secure_ram_context(void)
 * that any peripheral wake-up events occurring while attempting to
 * clear the PM_WKST_x are detected and cleared.
 */
-static int prcm_clear_mod_irqs(s16 module, u8 regs)
+static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
 {
        u32 wkst, fclk, iclk, clken;
        u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
@@ -206,6 +196,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
        wkst = omap2_prm_read_mod_reg(module, wkst_off);
        wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
+        wkst &= ~ignore_bits;
        if (wkst) {
                iclk = omap2_cm_read_mod_reg(module, iclk_off);
                fclk = omap2_cm_read_mod_reg(module, fclk_off);
@@ -221,6 +212,7 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
                        omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
                        omap2_prm_write_mod_reg(wkst, module, wkst_off);
                        wkst = omap2_prm_read_mod_reg(module, wkst_off);
+                        wkst &= ~ignore_bits;
                        c++;
                }
                omap2_cm_write_mod_reg(iclk, module, iclk_off);
@@ -230,76 +222,35 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs)
        return c;
 }
-static int _prcm_int_handle_wakeup(void)
+static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
 {
        int c;
-        c = prcm_clear_mod_irqs(WKUP_MOD, 1);
+        c = prcm_clear_mod_irqs(WKUP_MOD, 1,
-        c += prcm_clear_mod_irqs(CORE_MOD, 1);
+                ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
-        c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
-        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                c += prcm_clear_mod_irqs(CORE_MOD, 3);
-                c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
-        }
-        return c;
+        return c ? IRQ_HANDLED : IRQ_NONE;
 }
-/*
+static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
- * PRCM Interrupt Handler
- *
- * The PRM_IRQSTATUS_MPU register indicates if there are any pending
- * interrupts from the PRCM for the MPU. These bits must be cleared in
- * order to clear the PRCM interrupt. The PRCM interrupt handler is
- * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
- * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
- * register indicates that a wake-up event is pending for the MPU and
- * this bit can only be cleared if the all the wake-up events latched
- * in the various PM_WKST_x registers have been cleared. The interrupt
- * handler is implemented using a do-while loop so that if a wake-up
- * event occurred during the processing of the prcm interrupt handler
- * (setting a bit in the corresponding PM_WKST_x register and thus
- * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
- * this would be handled.
- */
-static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 {
-        u32 irqenable_mpu, irqstatus_mpu;
+        int c;
-        int c = 0;
-        irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
-                                         OMAP3_PRM_IRQENABLE_MPU_OFFSET);
-        irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
-                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-        irqstatus_mpu &= irqenable_mpu;
-        do {
-                if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
-                                     OMAP3430_IO_ST_MASK)) {
-                        c = _prcm_int_handle_wakeup();
-                        /*
-                         * Is the MPU PRCM interrupt handler racing with the
-                         * IVA2 PRCM interrupt handler ?
-                         */
-                        WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
-                             "but no wakeup sources are marked\n");
-                } else {
-                        /* XXX we need to expand our PRCM interrupt handler */
-                        WARN(1, "prcm: WARNING: PRCM interrupt received, but "
-                             "no code to handle it (%08x)\n", irqstatus_mpu);
-                }
-                omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
-                                        OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-                irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
-                                        OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
-                irqstatus_mpu &= irqenable_mpu;
-        } while (irqstatus_mpu);
+        /*
+         * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
+         * these are handled in a separate handler to avoid acking
+         * IO events before parsing in mux code
+         */
+        c = prcm_clear_mod_irqs(WKUP_MOD, 1,
+                OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
+        c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
+        c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
+        if (omap_rev() > OMAP3430_REV_ES1_0) {
+                c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
+                c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
+        }
-        return IRQ_HANDLED;
+        return c ? IRQ_HANDLED : IRQ_NONE;
 }
 static void omap34xx_save_context(u32 *save)
@@ -375,20 +326,11 @@ void omap_sram_idle(void)
                        omap3_enable_io_chain();
        }
-        /* Block console output in case it is on one of the OMAP UARTs */
-        if (!is_suspending())
-                if (per_next_state < PWRDM_POWER_ON ||
-                    core_next_state < PWRDM_POWER_ON)
-                        if (!console_trylock())
-                                goto console_still_active;
        pwrdm_pre_transition();
        /* PER */
        if (per_next_state < PWRDM_POWER_ON) {
                per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
-                omap_uart_prepare_idle(2);
-                omap_uart_prepare_idle(3);
                omap2_gpio_prepare_for_idle(per_going_off);
                if (per_next_state == PWRDM_POWER_OFF)
                                omap3_per_save_context();
@@ -396,8 +338,6 @@ void omap_sram_idle(void)
        /* CORE */
        if (core_next_state < PWRDM_POWER_ON) {
-                omap_uart_prepare_idle(0);
-                omap_uart_prepare_idle(1);
                if (core_next_state == PWRDM_POWER_OFF) {
                        omap3_core_save_context();
                        omap3_cm_save_context();
@@ -446,8 +386,6 @@ void omap_sram_idle(void)
                        omap3_sram_restore_context();
                        omap2_sms_restore_context();
                }
-                omap_uart_resume_idle(0);
-                omap_uart_resume_idle(1);
                if (core_next_state == PWRDM_POWER_OFF)
                        omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
                                               OMAP3430_GR_MOD,
@@ -463,14 +401,8 @@ void omap_sram_idle(void)
                omap2_gpio_resume_after_idle();
                if (per_prev_state == PWRDM_POWER_OFF)
                        omap3_per_restore_context();
-                omap_uart_resume_idle(2);
-                omap_uart_resume_idle(3);
        }
-        if (!is_suspending())
-                console_unlock();
-console_still_active:
        /* Disable IO-PAD and IO-CHAIN wakeup */
        if (omap3_has_io_wakeup() &&
            (per_next_state < PWRDM_POWER_ON ||
@@ -484,21 +416,11 @@ console_still_active:
        clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 }
-int omap3_can_sleep(void)
-{
-        if (!omap_uart_can_sleep())
-                return 0;
-        return 1;
-}
 static void omap3_pm_idle(void)
 {
        local_irq_disable();
        local_fiq_disable();
-        if (!omap3_can_sleep())
-                goto out;
        if (omap_irq_pending() || need_resched())
                goto out;
@@ -532,7 +454,6 @@ static int omap3_pm_suspend(void)
                        goto restore;
        }
-        omap_uart_prepare_suspend();
        omap3_intc_suspend();
        omap_sram_idle();
@@ -579,22 +500,27 @@ static int omap3_pm_begin(suspend_state_t state)
 {
        disable_hlt();
        suspend_state = state;
-        omap_uart_enable_irqs(0);
+        omap_prcm_irq_prepare();
        return 0;
 }
 static void omap3_pm_end(void)
 {
        suspend_state = PM_SUSPEND_ON;
-        omap_uart_enable_irqs(1);
        enable_hlt();
        return;
 }
+static void omap3_pm_finish(void)
+{
+        omap_prcm_irq_complete();
+}
 static const struct platform_suspend_ops omap_pm_ops = {
        .begin          = omap3_pm_begin,
        .end            = omap3_pm_end,
        .enter          = omap3_pm_enter,
+        .finish         = omap3_pm_finish,
        .valid          = suspend_valid_only_mem,
 };
 #endif /* CONFIG_SUSPEND */
@@ -700,10 +626,6 @@ static void __init prcm_setup_regs(void)
                          OMAP3430_GRPSEL_GPT1_MASK |
                          OMAP3430_GRPSEL_GPT12_MASK,
                          WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
-        /* For some reason IO doesn't generate wakeup event even if
-         * it is selected to mpu wakeup goup */
-        omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
-                          OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
        /* Enable PM_WKEN to support DSS LPR */
        omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
@@ -880,12 +802,21 @@ static int __init omap3_pm_init(void)
         * supervised mode for powerdomains */
        prcm_setup_regs();
-        ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
+        ret = request_irq(omap_prcm_event_to_irq("wkup"),
-                          (irq_handler_t)prcm_interrupt_handler,
+                _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
-                          IRQF_DISABLED, "prcm", NULL);
+        if (ret) {
+                pr_err("pm: Failed to request pm_wkup irq\n");
+                goto err1;
+        }
+        /* IO interrupt is shared with mux code */
+        ret = request_irq(omap_prcm_event_to_irq("io"),
+                _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
+                omap3_pm_init);
        if (ret) {
-                printk(KERN_ERR "request_irq failed to register for 0x%x\n",
+                pr_err("pm: Failed to request pm_io irq\n");
-                       INT_34XX_PRCM_MPU_IRQ);
                goto err1;
        }
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 59a870be839..c264ef7219c 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -1,8 +1,9 @@
 /*
 * OMAP4 Power Management Routines
 *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
@@ -16,14 +17,17 @@
 #include <linux/err.h>
 #include <linux/slab.h>
+#include "common.h"
+#include "clockdomain.h"
 #include "powerdomain.h"
-#include <mach/omap4-common.h>
+#include "pm.h"
 struct power_state {
        struct powerdomain *pwrdm;
        u32 next_state;
 #ifdef CONFIG_SUSPEND
        u32 saved_state;
+        u32 saved_logic_state;
 #endif
        struct list_head node;
 };
@@ -33,7 +37,50 @@ static LIST_HEAD(pwrst_list);
 #ifdef CONFIG_SUSPEND
 static int omap4_pm_suspend(void)
 {
-        do_wfi();
+        struct power_state *pwrst;
+        int state, ret = 0;
+        u32 cpu_id = smp_processor_id();
+        /* Save current powerdomain state */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
+                pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
+        }
+        /* Set targeted power domain states by suspend */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+                pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
+        }
+        /*
+         * For MPUSS to hit power domain retention(CSWR or OSWR),
+         * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
+         * since CPU power domain CSWR is not supported by hardware
+         * Only master CPU follows suspend path. All other CPUs follow
+         * CPU hotplug path in system wide suspend. On OMAP4, CPU power
+         * domain CSWR is not supported by hardware.
+         * More details can be found in OMAP4430 TRM section 4.3.4.2.
+         */
+        omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
+        /* Restore next powerdomain state */
+        list_for_each_entry(pwrst, &pwrst_list, node) {
+                state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
+                if (state > pwrst->next_state) {
+                        pr_info("Powerdomain (%s) didn't enter "
+                               "target state %d\n",
+                               pwrst->pwrdm->name, pwrst->next_state);
+                        ret = -1;
+                }
+                omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
+                pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
+        }
+        if (ret)
+                pr_crit("Could not enter target state in pm_suspend\n");
+        else
+                pr_info("Successfully put all powerdomains to target state\n");
        return 0;
 }
@@ -73,6 +120,22 @@ static const struct platform_suspend_ops omap_pm_ops = {
 };
 #endif /* CONFIG_SUSPEND */
+/*
+ * Enable hardware supervised mode for all clockdomains if it's
+ * supported. Initiate sleep transition for other clockdomains, if
+ * they are not used
+ */
+static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
+{
+        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+                clkdm_allow_idle(clkdm);
+        else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
+                        atomic_read(&clkdm->usecount) == 0)
+                clkdm_sleep(clkdm);
+        return 0;
+}
 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 {
        struct power_state *pwrst;
@@ -80,14 +143,48 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
        if (!pwrdm->pwrsts)
                return 0;
+        /*
+         * Skip CPU0 and CPU1 power domains. CPU1 is programmed
+         * through hotplug path and CPU0 explicitly programmed
+         * further down in the code path
+         */
+        if (!strncmp(pwrdm->name, "cpu", 3))
+                return 0;
+        /*
+         * FIXME: Remove this check when core retention is supported
+         * Only MPUSS power domain is added in the list.
+         */
+        if (strcmp(pwrdm->name, "mpu_pwrdm"))
+                return 0;
        pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
        if (!pwrst)
                return -ENOMEM;
        pwrst->pwrdm = pwrdm;
-        pwrst->next_state = PWRDM_POWER_ON;
+        pwrst->next_state = PWRDM_POWER_RET;
        list_add(&pwrst->node, &pwrst_list);
-        return pwrdm_set_next_pwrst(pwrst->pwrdm, pwrst->next_state);
+        return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
+}
+/**
+ * omap_default_idle - OMAP4 default ilde routine.'
+ *
+ * Implements OMAP4 memory, IO ordering requirements which can't be addressed
+ * with default arch_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
+ * by secondary CPU with CONFIG_CPUIDLE.
+ */
+static void omap_default_idle(void)
+{
+        local_irq_disable();
+        local_fiq_disable();
+        omap_do_wfi();
+        local_fiq_enable();
+        local_irq_enable();
 }
 /**
@@ -99,10 +196,17 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 static int __init omap4_pm_init(void)
 {
        int ret;
+        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
+        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
        if (!cpu_is_omap44xx())
                return -ENODEV;
+        if (omap_rev() == OMAP4430_REV_ES1_0) {
+                WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
+                return -ENODEV;
+        }
        pr_err("Power Management for TI OMAP4.\n");
        ret = pwrdm_for_each(pwrdms_setup, NULL);
@@ -111,10 +215,51 @@ static int __init omap4_pm_init(void)
                goto err2;
        }
+        /*
+         * The dynamic dependency between MPUSS -> MEMIF and
+         * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
+         * expected. The hardware recommendation is to enable static
+         * dependencies for these to avoid system lock ups or random crashes.
+         */
+        mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
+        emif_clkdm = clkdm_lookup("l3_emif_clkdm");
+        l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
+        l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
+        l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
+        ducati_clkdm = clkdm_lookup("ducati_clkdm");
+        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
+                (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
+                goto err2;
+        ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
+        ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
+        ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
+        ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
+        ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
+        ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
+        if (ret) {
+                pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
+                                "wakeup dependency\n");
+                goto err2;
+        }
+        ret = omap4_mpuss_init();
+        if (ret) {
+                pr_err("Failed to initialise OMAP4 MPUSS\n");
+                goto err2;
+        }
+        (void) clkdm_for_each(clkdms_setup, NULL);
 #ifdef CONFIG_SUSPEND
        suspend_set_ops(&omap_pm_ops);
 #endif /* CONFIG_SUSPEND */
+        /* Overwrite the default arch_idle() */
+        pm_idle = omap_default_idle;
+        omap4_idle_init();
 err2:
        return ret;
 }
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 0363dcb0ef9..5aa5435e3ff 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -4,7 +4,7 @@
 /*
 * OMAP2/3 PRCM base and module definitions
 *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2009 Nokia Corporation
 *
 * Written by Paul Walmsley
@@ -201,6 +201,8 @@
 #define OMAP3430_EN_MMC2_SHIFT                          25
 #define OMAP3430_EN_MMC1_MASK                           (1 << 24)
 #define OMAP3430_EN_MMC1_SHIFT                          24
+#define OMAP3430_EN_UART4_MASK                          (1 << 23)
+#define OMAP3430_EN_UART4_SHIFT                         23
 #define OMAP3430_EN_MCSPI4_MASK                         (1 << 21)
 #define OMAP3430_EN_MCSPI4_SHIFT                        21
 #define OMAP3430_EN_MCSPI3_MASK                         (1 << 20)
@@ -408,6 +410,79 @@
 extern void __iomem *prm_base;
 extern void __iomem *cm_base;
 extern void __iomem *cm2_base;
+/**
+ * struct omap_prcm_irq - describes a PRCM interrupt bit
+ * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
+ * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs
+ * @priority: should this interrupt be handled before @priority=false IRQs?
+ *
+ * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers.
+ * On systems with multiple PRM MPU IRQ registers, the bitfields read from
+ * the registers are concatenated, so @offset could be > 31 on these systems -
+ * see omap_prm_irq_handler() for more details.  I/O ring interrupts should
+ * have @priority set to true.
+ */
+struct omap_prcm_irq {
+        const char *name;
+        unsigned int offset;
+        bool priority;
+};
+/**
+ * struct omap_prcm_irq_setup - PRCM interrupt controller details
+ * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register
+ * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register
+ * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers
+ * @nr_irqs: number of entries in the @irqs array
+ * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs)
+ * @irq: MPU IRQ asserted when a PRCM interrupt arrives
+ * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending
+ * @ocp_barrier: fn ptr to force buffered PRM writes to complete
+ * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
+ * @restore_irqen: fn ptr to save and clear IRQENABLE regs
+ * @saved_mask: IRQENABLE regs are saved here during suspend
+ * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
+ * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
+ * @suspended: set to true after Linux suspend code has called our ->prepare()
+ * @suspend_save_flag: set to true after IRQ masks have been saved and disabled
+ *
+ * @saved_mask, @priority_mask, @base_irq, @suspended, and
+ * @suspend_save_flag are populated dynamically, and are not to be
+ * specified in static initializers.
+ */
+struct omap_prcm_irq_setup {
+        u16 ack;
+        u16 mask;
+        u8 nr_regs;
+        u8 nr_irqs;
+        const struct omap_prcm_irq *irqs;
+        int irq;
+        void (*read_pending_irqs)(unsigned long *events);
+        void (*ocp_barrier)(void);
+        void (*save_and_clear_irqen)(u32 *saved_mask);
+        void (*restore_irqen)(u32 *saved_mask);
+        u32 *saved_mask;
+        u32 *priority_mask;
+        int base_irq;
+        bool suspended;
+        bool suspend_save_flag;
+};
+/* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */
+#define OMAP_PRCM_IRQ(_name, _offset, _priority) {      \
+        .name = _name,                                  \
+        .offset = _offset,                              \
+        .priority = _priority                           \
+        }
+extern void omap_prcm_irq_cleanup(void);
+extern int omap_prcm_register_chain_handler(
+        struct omap_prcm_irq_setup *irq_setup);
+extern int omap_prcm_event_to_irq(const char *event);
+extern void omap_prcm_irq_prepare(void);
+extern void omap_prcm_irq_complete(void);
 # endif
 #endif
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 597e2da831b..626acfad719 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -25,8 +25,7 @@
 #include <linux/delay.h>
 #include <linux/export.h>
-#include <mach/system.h>
+#include "common.h"
-#include <plat/common.h>
 #include <plat/prcm.h>
 #include <plat/irqs.h>
@@ -59,7 +58,7 @@ u32 omap_prcm_get_reset_sources(void)
 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 /* Resets clock rates and reboots the system. Only called from system.h */
-static void omap_prcm_arch_reset(char mode, const char *cmd)
+void omap_prcm_restart(char mode, const char *cmd)
 {
        s16 prcm_offs = 0;
@@ -110,8 +109,6 @@ static void omap_prcm_arch_reset(char mode, const char *cmd)
        omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
 }
-void (*arch_reset)(char, const char *) = omap_prcm_arch_reset;
 /**
 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
 * @reg: physical address of module IDLEST register
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index 171fe171a74..ca669b50f39 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -15,7 +15,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prcm_mpu44xx.h"
 #include "cm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index f02d87f68e5..c1c4d86a79a 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -1,7 +1,7 @@
 /*
 * OMAP2/3 PRM module functions
 *
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 * Benoît Cousson
 * Paul Walmsley
@@ -16,7 +16,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/cpu.h>
 #include <plat/prcm.h>
@@ -27,6 +27,24 @@
 #include "prm-regbits-24xx.h"
 #include "prm-regbits-34xx.h"
+static const struct omap_prcm_irq omap3_prcm_irqs[] = {
+        OMAP_PRCM_IRQ("wkup",   0,      0),
+        OMAP_PRCM_IRQ("io",     9,      1),
+};
+static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
+        .ack                    = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
+        .mask                   = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
+        .nr_regs                = 1,
+        .irqs                   = omap3_prcm_irqs,
+        .nr_irqs                = ARRAY_SIZE(omap3_prcm_irqs),
+        .irq                    = INT_34XX_PRCM_MPU_IRQ,
+        .read_pending_irqs      = &omap3xxx_prm_read_pending_irqs,
+        .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
+        .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
+        .restore_irqen          = &omap3xxx_prm_restore_irqen,
+};
 u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
 {
        return __raw_readl(prm_base + module + idx);
@@ -212,3 +230,80 @@ u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 {
        return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
 }
+/**
+ * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
+ * @events: ptr to a u32, preallocated by caller
+ *
+ * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
+ * MPU IRQs, and store the result into the u32 pointed to by @events.
+ * No return value.
+ */
+void omap3xxx_prm_read_pending_irqs(unsigned long *events)
+{
+        u32 mask, st;
+        /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
+        mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
+        events[0] = mask & st;
+}
+/**
+ * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
+ *
+ * Force any buffered writes to the PRM IP block to complete.  Needed
+ * by the PRM IRQ handler, which reads and writes directly to the IP
+ * block, to avoid race conditions after acknowledging or clearing IRQ
+ * bits.  No return value.
+ */
+void omap3xxx_prm_ocp_barrier(void)
+{
+        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+}
+/**
+ * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
+ * @saved_mask: ptr to a u32 array to save IRQENABLE bits
+ *
+ * Save the PRM_IRQENABLE_MPU register to @saved_mask.  @saved_mask
+ * must be allocated by the caller.  Intended to be used in the PRM
+ * interrupt handler suspend callback.  The OCP barrier is needed to
+ * ensure the write to disable PRM interrupts reaches the PRM before
+ * returning; otherwise, spurious interrupts might occur.  No return
+ * value.
+ */
+void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
+{
+        saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
+                                               OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+        /* OCP barrier */
+        omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
+}
+/**
+ * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
+ * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
+ *
+ * Restore the PRM_IRQENABLE_MPU register from @saved_mask.  Intended
+ * to be used in the PRM interrupt handler resume callback to restore
+ * values saved by omap3xxx_prm_save_and_clear_irqen().  No OCP
+ * barrier should be needed here; any pending PRM interrupts will fire
+ * once the writes reach the PRM.  No return value.
+ */
+void omap3xxx_prm_restore_irqen(u32 *saved_mask)
+{
+        omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
+                                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
+}
+static int __init omap3xxx_prcm_init(void)
+{
+        if (cpu_is_omap34xx())
+                return omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
+        return 0;
+}
+subsys_initcall(omap3xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index cef533df086..70ac2a19dc5 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -1,7 +1,7 @@
 /*
 * OMAP2/3 Power/Reset Management (PRM) register definitions
 *
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
 * Copyright (C) 2008-2010 Nokia Corporation
 * Paul Walmsley
 *
@@ -314,6 +314,13 @@ void omap3_prm_vp_clear_txdone(u8 vp_id);
 extern u32 omap3_prm_vcvp_read(u8 offset);
 extern void omap3_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+/* PRM interrupt-related functions */
+extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
+extern void omap3xxx_prm_ocp_barrier(void);
+extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
 #endif  /* CONFIG_ARCH_OMAP4 */
 #endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 495a31a7e8a..33dd655e6aa 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -17,7 +17,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/cpu.h>
 #include <plat/prcm.h>
@@ -27,6 +27,24 @@
 #include "prcm44xx.h"
 #include "prminst44xx.h"
+static const struct omap_prcm_irq omap4_prcm_irqs[] = {
+        OMAP_PRCM_IRQ("wkup",   0,      0),
+        OMAP_PRCM_IRQ("io",     9,      1),
+};
+static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
+        .ack                    = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
+        .mask                   = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
+        .nr_regs                = 2,
+        .irqs                   = omap4_prcm_irqs,
+        .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
+        .irq                    = OMAP44XX_IRQ_PRCM,
+        .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
+        .ocp_barrier            = &omap44xx_prm_ocp_barrier,
+        .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
+        .restore_irqen          = &omap44xx_prm_restore_irqen,
+};
 /* PRM low-level functions */
 /* Read a register in a CM/PRM instance in the PRM module */
@@ -121,3 +139,101 @@ u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
                                               OMAP4430_PRM_DEVICE_INST,
                                               offset);
 }
+static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
+{
+        u32 mask, st;
+        /* XXX read mask from RAM? */
+        mask = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqen_offs);
+        st = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, irqst_offs);
+        return mask & st;
+}
+/**
+ * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
+ * @events: ptr to two consecutive u32s, preallocated by caller
+ *
+ * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
+ * MPU IRQs, and store the result into the two u32s pointed to by @events.
+ * No return value.
+ */
+void omap44xx_prm_read_pending_irqs(unsigned long *events)
+{
+        events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
+                                          OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
+        events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
+                                          OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
+}
+/**
+ * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
+ *
+ * Force any buffered writes to the PRM IP block to complete.  Needed
+ * by the PRM IRQ handler, which reads and writes directly to the IP
+ * block, to avoid race conditions after acknowledging or clearing IRQ
+ * bits.  No return value.
+ */
+void omap44xx_prm_ocp_barrier(void)
+{
+        omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                OMAP4_REVISION_PRM_OFFSET);
+}
+/**
+ * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
+ * @saved_mask: ptr to a u32 array to save IRQENABLE bits
+ *
+ * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
+ * @saved_mask.  @saved_mask must be allocated by the caller.
+ * Intended to be used in the PRM interrupt handler suspend callback.
+ * The OCP barrier is needed to ensure the write to disable PRM
+ * interrupts reaches the PRM before returning; otherwise, spurious
+ * interrupts might occur.  No return value.
+ */
+void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
+{
+        saved_mask[0] =
+                omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                        OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
+        saved_mask[1] =
+                omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                        OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
+        omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
+        omap4_prm_write_inst_reg(0, OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
+        /* OCP barrier */
+        omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
+                                OMAP4_REVISION_PRM_OFFSET);
+}
+/**
+ * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
+ * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
+ *
+ * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
+ * @saved_mask.  Intended to be used in the PRM interrupt handler resume
+ * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
+ * No OCP barrier should be needed here; any pending PRM interrupts will fire
+ * once the writes reach the PRM.  No return value.
+ */
+void omap44xx_prm_restore_irqen(u32 *saved_mask)
+{
+        omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_OFFSET);
+        omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_DEVICE_INST,
+                                 OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
+}
+static int __init omap4xxx_prcm_init(void)
+{
+        if (cpu_is_omap44xx())
+                return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
+        return 0;
+}
+subsys_initcall(omap4xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 3d66ccd849d..7978092946d 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -1,7 +1,7 @@
 /*
 * OMAP44xx PRM instance offset macros
 *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
 * Copyright (C) 2009-2010 Nokia Corporation
 *
 * Paul Walmsley (paul@pwsan.com)
@@ -763,6 +763,12 @@ extern u32 omap4_prm_vcvp_read(u8 offset);
 extern void omap4_prm_vcvp_write(u32 val, u8 offset);
 extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
+/* PRM interrupt-related functions */
+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+extern void omap44xx_prm_ocp_barrier(void);
+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
 # endif
 #endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
new file mode 100644
index 00000000000..860118ab43e
--- /dev/null
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -0,0 +1,320 @@
+/*
+ * OMAP2+ common Power & Reset Management (PRM) IP block functions
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ * For historical purposes, the API used to configure the PRM
+ * interrupt handler refers to it as the "PRCM interrupt."  The
+ * underlying registers are located in the PRM on OMAP3/4.
+ *
+ * XXX This code should eventually be moved to a PRM driver.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <mach/system.h>
+#include <plat/common.h>
+#include <plat/prcm.h>
+#include <plat/irqs.h>
+#include "prm2xxx_3xxx.h"
+#include "prm44xx.h"
+/*
+ * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
+ * XXX this is technically not needed, since
+ * omap_prcm_register_chain_handler() could allocate this based on the
+ * actual amount of memory needed for the SoC
+ */
+#define OMAP_PRCM_MAX_NR_PENDING_REG            2
+/*
+ * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
+ * by the PRCM interrupt handler code.  There will be one 'chip' per
+ * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
+ * one "chip" and OMAP4 will have two.)
+ */
+static struct irq_chip_generic **prcm_irq_chips;
+/*
+ * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
+ * is currently running on.  Defined and passed by initialization code
+ * that calls omap_prcm_register_chain_handler().
+ */
+static struct omap_prcm_irq_setup *prcm_irq_setup;
+/* Private functions */
+/*
+ * Move priority events from events to priority_events array
+ */
+static void omap_prcm_events_filter_priority(unsigned long *events,
+        unsigned long *priority_events)
+{
+        int i;
+        for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
+                priority_events[i] =
+                        events[i] & prcm_irq_setup->priority_mask[i];
+                events[i] ^= priority_events[i];
+        }
+}
+/*
+ * PRCM Interrupt Handler
+ *
+ * This is a common handler for the OMAP PRCM interrupts. Pending
+ * interrupts are detected by a call to prcm_pending_events and
+ * dispatched accordingly. Clearing of the wakeup events should be
+ * done by the SoC specific individual handlers.
+ */
+static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
+        unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        unsigned int virtirq;
+        int nr_irqs = prcm_irq_setup->nr_regs * 32;
+        /*
+         * If we are suspended, mask all interrupts from PRCM level,
+         * this does not ack them, and they will be pending until we
+         * re-enable the interrupts, at which point the
+         * omap_prcm_irq_handler will be executed again.  The
+         * _save_and_clear_irqen() function must ensure that the PRM
+         * write to disable all IRQs has reached the PRM before
+         * returning, or spurious PRCM interrupts may occur during
+         * suspend.
+         */
+        if (prcm_irq_setup->suspended) {
+                prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
+                prcm_irq_setup->suspend_save_flag = true;
+        }
+        /*
+         * Loop until all pending irqs are handled, since
+         * generic_handle_irq() can cause new irqs to come
+         */
+        while (!prcm_irq_setup->suspended) {
+                prcm_irq_setup->read_pending_irqs(pending);
+                /* No bit set, then all IRQs are handled */
+                if (find_first_bit(pending, nr_irqs) >= nr_irqs)
+                        break;
+                omap_prcm_events_filter_priority(pending, priority_pending);
+                /*
+                 * Loop on all currently pending irqs so that new irqs
+                 * cannot starve previously pending irqs
+                 */
+                /* Serve priority events first */
+                for_each_set_bit(virtirq, priority_pending, nr_irqs)
+                        generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
+                /* Serve normal events next */
+                for_each_set_bit(virtirq, pending, nr_irqs)
+                        generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
+        }
+        if (chip->irq_ack)
+                chip->irq_ack(&desc->irq_data);
+        if (chip->irq_eoi)
+                chip->irq_eoi(&desc->irq_data);
+        chip->irq_unmask(&desc->irq_data);
+        prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
+}
+/* Public functions */
+/**
+ * omap_prcm_event_to_irq - given a PRCM event name, returns the
+ * corresponding IRQ on which the handler should be registered
+ * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
+ *
+ * Returns the Linux internal IRQ ID corresponding to @name upon success,
+ * or -ENOENT upon failure.
+ */
+int omap_prcm_event_to_irq(const char *name)
+{
+        int i;
+        if (!prcm_irq_setup || !name)
+                return -ENOENT;
+        for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
+                if (!strcmp(prcm_irq_setup->irqs[i].name, name))
+                        return prcm_irq_setup->base_irq +
+                                prcm_irq_setup->irqs[i].offset;
+        return -ENOENT;
+}
+/**
+ * omap_prcm_irq_cleanup - reverses memory allocated and other steps
+ * done by omap_prcm_register_chain_handler()
+ *
+ * No return value.
+ */
+void omap_prcm_irq_cleanup(void)
+{
+        int i;
+        if (!prcm_irq_setup) {
+                pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
+                return;
+        }
+        if (prcm_irq_chips) {
+                for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
+                        if (prcm_irq_chips[i])
+                                irq_remove_generic_chip(prcm_irq_chips[i],
+                                        0xffffffff, 0, 0);
+                        prcm_irq_chips[i] = NULL;
+                }
+                kfree(prcm_irq_chips);
+                prcm_irq_chips = NULL;
+        }
+        kfree(prcm_irq_setup->saved_mask);
+        prcm_irq_setup->saved_mask = NULL;
+        kfree(prcm_irq_setup->priority_mask);
+        prcm_irq_setup->priority_mask = NULL;
+        irq_set_chained_handler(prcm_irq_setup->irq, NULL);
+        if (prcm_irq_setup->base_irq > 0)
+                irq_free_descs(prcm_irq_setup->base_irq,
+                        prcm_irq_setup->nr_regs * 32);
+        prcm_irq_setup->base_irq = 0;
+}
+void omap_prcm_irq_prepare(void)
+{
+        prcm_irq_setup->suspended = true;
+}
+void omap_prcm_irq_complete(void)
+{
+        prcm_irq_setup->suspended = false;
+        /* If we have not saved the masks, do not attempt to restore */
+        if (!prcm_irq_setup->suspend_save_flag)
+                return;
+        prcm_irq_setup->suspend_save_flag = false;
+        /*
+         * Re-enable all masked PRCM irq sources, this causes the PRCM
+         * interrupt to fire immediately if the events were masked
+         * previously in the chain handler
+         */
+        prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
+}
+/**
+ * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
+ * handler based on provided parameters
+ * @irq_setup: hardware data about the underlying PRM/PRCM
+ *
+ * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
+ * one generic IRQ chip per PRM interrupt status/enable register pair.
+ * Returns 0 upon success, -EINVAL if called twice or if invalid
+ * arguments are passed, or -ENOMEM on any other error.
+ */
+int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
+{
+        int nr_regs = irq_setup->nr_regs;
+        u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
+        int offset, i;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        if (!irq_setup)
+                return -EINVAL;
+        if (prcm_irq_setup) {
+                pr_err("PRCM: already initialized; won't reinitialize\n");
+                return -EINVAL;
+        }
+        if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
+                pr_err("PRCM: nr_regs too large\n");
+                return -EINVAL;
+        }
+        prcm_irq_setup = irq_setup;
+        prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
+        prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
+        prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
+                GFP_KERNEL);
+        if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
+            !prcm_irq_setup->priority_mask) {
+                pr_err("PRCM: kzalloc failed\n");
+                goto err;
+        }
+        memset(mask, 0, sizeof(mask));
+        for (i = 0; i < irq_setup->nr_irqs; i++) {
+                offset = irq_setup->irqs[i].offset;
+                mask[offset >> 5] |= 1 << (offset & 0x1f);
+                if (irq_setup->irqs[i].priority)
+                        irq_setup->priority_mask[offset >> 5] |=
+                                1 << (offset & 0x1f);
+        }
+        irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
+        irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
+                0);
+        if (irq_setup->base_irq < 0) {
+                pr_err("PRCM: failed to allocate irq descs: %d\n",
+                        irq_setup->base_irq);
+                goto err;
+        }
+        for (i = 0; i <= irq_setup->nr_regs; i++) {
+                gc = irq_alloc_generic_chip("PRCM", 1,
+                        irq_setup->base_irq + i * 32, prm_base,
+                        handle_level_irq);
+                if (!gc) {
+                        pr_err("PRCM: failed to allocate generic chip\n");
+                        goto err;
+                }
+                ct = gc->chip_types;
+                ct->chip.irq_ack = irq_gc_ack_set_bit;
+                ct->chip.irq_mask = irq_gc_mask_clr_bit;
+                ct->chip.irq_unmask = irq_gc_mask_set_bit;
+                ct->regs.ack = irq_setup->ack + i * 4;
+                ct->regs.mask = irq_setup->mask + i * 4;
+                irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
+                prcm_irq_chips[i] = gc;
+        }
+        return 0;
+err:
+        omap_prcm_irq_cleanup();
+        return -ENOMEM;
+}
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 3a7bab16edd..f6de5bc6b12 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -16,7 +16,7 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm44xx.h"
 #include "prminst44xx.h"
diff --git a/arch/arm/mach-omap2/sdram-nokia.c b/arch/arm/mach-omap2/sdram-nokia.c
index 14caa228bc0..7479d7ea137 100644
--- a/arch/arm/mach-omap2/sdram-nokia.c
+++ b/arch/arm/mach-omap2/sdram-nokia.c
@@ -1,7 +1,7 @@
 /*
 * SDRC register values for Nokia boards
 *
- * Copyright (C) 2008, 2010 Nokia Corporation
+ * Copyright (C) 2008, 2010-2011 Nokia Corporation
 *
 * Lauri Leukkunen <lauri.leukkunen@nokia.com>
 *
@@ -18,7 +18,7 @@
 #include <linux/io.h>
 #include <plat/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/clock.h>
 #include <plat/sdrc.h>
@@ -107,14 +107,37 @@ static const struct sdram_timings nokia_195dot2mhz_timings[] = {
        },
 };
+static const struct sdram_timings nokia_200mhz_timings[] = {
+        {
+                .casl = 3,
+                .tDAL = 30000,
+                .tDPL = 15000,
+                .tRRD = 10000,
+                .tRCD = 20000,
+                .tRP = 15000,
+                .tRAS = 40000,
+                .tRC = 55000,
+                .tRFC = 140000,
+                .tXSR = 200000,
+                .tREF = 7800,
+                .tXP = 2,
+                .tCKE = 4,
+                .tWTR = 2
+        },
+};
 static const struct {
        long rate;
        struct sdram_timings const *data;
 } nokia_timings[] = {
        { 83000000, nokia_166mhz_timings },
        { 97600000, nokia_97dot6mhz_timings },
+        { 100000000, nokia_200mhz_timings },
        { 166000000, nokia_166mhz_timings },
        { 195200000, nokia_195dot2mhz_timings },
+        { 200000000, nokia_200mhz_timings },
 };
 static struct omap_sdrc_params nokia_sdrc_params[ARRAY_SIZE(nokia_timings) + 1];
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 8f278287477..e3d345f4640 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -23,7 +23,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/clock.h>
 #include <plat/sram.h>
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index ccdb010f169..791a63cdceb 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,7 +24,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/clock.h>
 #include <plat/sram.h>
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 9992dbfdfdb..247d89478f2 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -19,26 +19,21 @@
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/serial_reg.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
-#include <linux/serial_8250.h>
 #include <linux/pm_runtime.h>
 #include <linux/console.h>
-#ifdef CONFIG_SERIAL_OMAP
 #include <plat/omap-serial.h>
-#endif
+#include "common.h"
-#include <plat/common.h>
 #include <plat/board.h>
-#include <plat/clock.h>
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/omap-pm.h>
 #include "prm2xxx_3xxx.h"
 #include "pm.h"
@@ -47,603 +42,226 @@
 #include "control.h"
 #include "mux.h"
-#define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
-#define UART_OMAP_WER           0x17    /* Wake-up enable register */
-#define UART_ERRATA_FIFO_FULL_ABORT     (0x1 << 0)
-#define UART_ERRATA_i202_MDR1_ACCESS    (0x1 << 1)
 /*
- * NOTE: By default the serial timeout is disabled as it causes lost characters
+ * NOTE: By default the serial auto_suspend timeout is disabled as it causes
- * over the serial ports. This means that the UART clocks will stay on until
+ * lost characters over the serial ports. This means that the UART clocks will
- * disabled via sysfs. This also causes that any deeper omap sleep states are
+ * stay on until power/autosuspend_delay is set for the uart from sysfs.
- * blocked. 
+ * This also causes that any deeper omap sleep states are blocked.
 */
-#define DEFAULT_TIMEOUT 0
+#define DEFAULT_AUTOSUSPEND_DELAY       -1
 #define MAX_UART_HWMOD_NAME_LEN         16
 struct omap_uart_state {
        int num;
        int can_sleep;
-        struct timer_list timer;
-        u32 timeout;
-        void __iomem *wk_st;
-        void __iomem *wk_en;
-        u32 wk_mask;
-        u32 padconf;
-        u32 dma_enabled;
-        struct clk *ick;
-        struct clk *fck;
-        int clocked;
-        int irq;
-        int regshift;
-        int irqflags;
-        void __iomem *membase;
-        resource_size_t mapbase;
        struct list_head node;
        struct omap_hwmod *oh;
        struct platform_device *pdev;
-        u32 errata;
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
-        int context_valid;
-        /* Registers to be saved/restored for OFF-mode */
-        u16 dll;
-        u16 dlh;
-        u16 ier;
-        u16 sysc;
-        u16 scr;
-        u16 wer;
-        u16 mcr;
-#endif
 };
 static LIST_HEAD(uart_list);
 static u8 num_uarts;
+static u8 console_uart_id = -1;
+static u8 no_console_suspend;
+static u8 uart_debug;
+#define DEFAULT_RXDMA_POLLRATE          1       /* RX DMA polling rate (us) */
+#define DEFAULT_RXDMA_BUFSIZE           4096    /* RX DMA buffer size */
+#define DEFAULT_RXDMA_TIMEOUT           (3 * HZ)/* RX DMA timeout (jiffies) */
+static struct omap_uart_port_info omap_serial_default_info[] __initdata = {
+        {
+                .dma_enabled    = false,
+                .dma_rx_buf_size = DEFAULT_RXDMA_BUFSIZE,
+                .dma_rx_poll_rate = DEFAULT_RXDMA_POLLRATE,
+                .dma_rx_timeout = DEFAULT_RXDMA_TIMEOUT,
+                .autosuspend_timeout = DEFAULT_AUTOSUSPEND_DELAY,
+        },
+};
-static inline unsigned int __serial_read_reg(struct uart_port *up,
+#ifdef CONFIG_PM
-                                             int offset)
+static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
-{
-        offset <<= up->regshift;
-        return (unsigned int)__raw_readb(up->membase + offset);
-}
-static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
-                                           int offset)
 {
-        offset <<= uart->regshift;
+        struct omap_device *od = to_omap_device(pdev);
-        return (unsigned int)__raw_readb(uart->membase + offset);
-}
-static inline void __serial_write_reg(struct uart_port *up, int offset,
+        if (!od)
-                int value)
+                return;
-{
-        offset <<= up->regshift;
-        __raw_writeb(value, up->membase + offset);
-}
-static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
+        if (enable)
-                                    int value)
+                omap_hwmod_enable_wakeup(od->hwmods[0]);
-{
+        else
-        offset <<= uart->regshift;
+                omap_hwmod_disable_wakeup(od->hwmods[0]);
-        __raw_writeb(value, uart->membase + offset);
 }
 /*
- * Internal UARTs need to be initialized for the 8250 autoconfig to work
+ * Errata i291: [UART]:Cannot Acknowledge Idle Requests
- * properly. Note that the TX watermark initialization may not be needed
+ * in Smartidle Mode When Configured for DMA Operations.
- * once the 8250.c watermark handling code is merged.
+ * WA: configure uart in force idle mode.
 */
+static void omap_uart_set_noidle(struct platform_device *pdev)
-static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 {
-        serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+        struct omap_device *od = to_omap_device(pdev);
-        serial_write_reg(uart, UART_OMAP_SCR, 0x08);
-        serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
-}
-#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
-/*
+        omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_NO);
- * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
- * The access to uart register after MDR1 Access
- * causes UART to corrupt data.
- *
- * Need a delay =
- * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
- * give 10 times as much
- */
-static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
-                u8 fcr_val)
-{
-        u8 timeout = 255;
-        serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
-        udelay(2);
-        serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
-                        UART_FCR_CLEAR_RCVR);
-        /*
-         * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
-         * TX_FIFO_E bit is 1.
-         */
-        while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
-                                (UART_LSR_THRE | UART_LSR_DR))) {
-                timeout--;
-                if (!timeout) {
-                        /* Should *never* happen. we warn and carry on */
-                        dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
-                        serial_read_reg(uart, UART_LSR));
-                        break;
-                }
-                udelay(1);
-        }
 }
-static void omap_uart_save_context(struct omap_uart_state *uart)
+static void omap_uart_set_forceidle(struct platform_device *pdev)
 {
-        u16 lcr = 0;
+        struct omap_device *od = to_omap_device(pdev);
-        if (!enable_off_mode)
+        omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_FORCE);
-                return;
-        lcr = serial_read_reg(uart, UART_LCR);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        uart->dll = serial_read_reg(uart, UART_DLL);
-        uart->dlh = serial_read_reg(uart, UART_DLM);
-        serial_write_reg(uart, UART_LCR, lcr);
-        uart->ier = serial_read_reg(uart, UART_IER);
-        uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
-        uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
-        uart->wer = serial_read_reg(uart, UART_OMAP_WER);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
-        uart->mcr = serial_read_reg(uart, UART_MCR);
-        serial_write_reg(uart, UART_LCR, lcr);
-        uart->context_valid = 1;
 }
-static void omap_uart_restore_context(struct omap_uart_state *uart)
-{
-        u16 efr = 0;
-        if (!enable_off_mode)
-                return;
-        if (!uart->context_valid)
-                return;
-        uart->context_valid = 0;
-        if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
-                omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
-        else
-                serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        efr = serial_read_reg(uart, UART_EFR);
-        serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
-        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(uart, UART_IER, 0x0);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        serial_write_reg(uart, UART_DLL, uart->dll);
-        serial_write_reg(uart, UART_DLM, uart->dlh);
-        serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
-        serial_write_reg(uart, UART_IER, uart->ier);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
-        serial_write_reg(uart, UART_MCR, uart->mcr);
-        serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
-        serial_write_reg(uart, UART_EFR, efr);
-        serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
-        serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
-        serial_write_reg(uart, UART_OMAP_WER, uart->wer);
-        serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
-        if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
-                omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
-        else
-                /* UART 16x mode */
-                serial_write_reg(uart, UART_OMAP_MDR1,
-                                UART_OMAP_MDR1_16X_MODE);
-}
 #else
-static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
+static void omap_uart_enable_wakeup(struct platform_device *pdev, bool enable)
-static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
+{}
-#endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
+static void omap_uart_set_noidle(struct platform_device *pdev) {}
+static void omap_uart_set_forceidle(struct platform_device *pdev) {}
-static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
+#endif /* CONFIG_PM */
-{
-        if (uart->clocked)
-                return;
-        omap_device_enable(uart->pdev);
-        uart->clocked = 1;
-        omap_uart_restore_context(uart);
-}
-#ifdef CONFIG_PM
-static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
-{
-        if (!uart->clocked)
-                return;
-        omap_uart_save_context(uart);
-        uart->clocked = 0;
-        omap_device_idle(uart->pdev);
-}
-static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
-{
-        /* Set wake-enable bit */
-        if (uart->wk_en && uart->wk_mask) {
-                u32 v = __raw_readl(uart->wk_en);
-                v |= uart->wk_mask;
-                __raw_writel(v, uart->wk_en);
-        }
-        /* Ensure IOPAD wake-enables are set */
-        if (cpu_is_omap34xx() && uart->padconf) {
-                u16 v = omap_ctrl_readw(uart->padconf);
-                v |= OMAP3_PADCONF_WAKEUPENABLE0;
-                omap_ctrl_writew(v, uart->padconf);
-        }
-}
-static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
-{
-        /* Clear wake-enable bit */
-        if (uart->wk_en && uart->wk_mask) {
-                u32 v = __raw_readl(uart->wk_en);
-                v &= ~uart->wk_mask;
-                __raw_writel(v, uart->wk_en);
-        }
-        /* Ensure IOPAD wake-enables are cleared */
-        if (cpu_is_omap34xx() && uart->padconf) {
-                u16 v = omap_ctrl_readw(uart->padconf);
-                v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
-                omap_ctrl_writew(v, uart->padconf);
-        }
-}
-static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
-                                               int enable)
-{
-        u8 idlemode;
-        if (enable) {
-                /**
-                 * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
-                 * in Smartidle Mode When Configured for DMA Operations.
-                 */
-                if (uart->dma_enabled)
-                        idlemode = HWMOD_IDLEMODE_FORCE;
-                else
-                        idlemode = HWMOD_IDLEMODE_SMART;
-        } else {
-                idlemode = HWMOD_IDLEMODE_NO;
-        }
-        omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
-}
-static void omap_uart_block_sleep(struct omap_uart_state *uart)
-{
-        omap_uart_enable_clocks(uart);
-        omap_uart_smart_idle_enable(uart, 0);
-        uart->can_sleep = 0;
-        if (uart->timeout)
-                mod_timer(&uart->timer, jiffies + uart->timeout);
-        else
-                del_timer(&uart->timer);
-}
-static void omap_uart_allow_sleep(struct omap_uart_state *uart)
-{
-        if (device_may_wakeup(&uart->pdev->dev))
-                omap_uart_enable_wakeup(uart);
-        else
-                omap_uart_disable_wakeup(uart);
-        if (!uart->clocked)
-                return;
-        omap_uart_smart_idle_enable(uart, 1);
-        uart->can_sleep = 1;
-        del_timer(&uart->timer);
-}
-static void omap_uart_idle_timer(unsigned long data)
-{
-        struct omap_uart_state *uart = (struct omap_uart_state *)data;
-        omap_uart_allow_sleep(uart);
-}
-void omap_uart_prepare_idle(int num)
-{
-        struct omap_uart_state *uart;
-        list_for_each_entry(uart, &uart_list, node) {
-                if (num == uart->num && uart->can_sleep) {
-                        omap_uart_disable_clocks(uart);
-                        return;
-                }
-        }
-}
-void omap_uart_resume_idle(int num)
-{
-        struct omap_uart_state *uart;
-        list_for_each_entry(uart, &uart_list, node) {
-                if (num == uart->num && uart->can_sleep) {
-                        omap_uart_enable_clocks(uart);
-                        /* Check for IO pad wakeup */
-                        if (cpu_is_omap34xx() && uart->padconf) {
-                                u16 p = omap_ctrl_readw(uart->padconf);
-                                if (p & OMAP3_PADCONF_WAKEUPEVENT0)
-                                        omap_uart_block_sleep(uart);
-                        }
-                        /* Check for normal UART wakeup */
-                        if (__raw_readl(uart->wk_st) & uart->wk_mask)
-                                omap_uart_block_sleep(uart);
-                        return;
-                }
-        }
-}
-void omap_uart_prepare_suspend(void)
-{
-        struct omap_uart_state *uart;
-        list_for_each_entry(uart, &uart_list, node) {
-                omap_uart_allow_sleep(uart);
-        }
-}
-int omap_uart_can_sleep(void)
-{
-        struct omap_uart_state *uart;
-        int can_sleep = 1;
-        list_for_each_entry(uart, &uart_list, node) {
-                if (!uart->clocked)
-                        continue;
-                if (!uart->can_sleep) {
-                        can_sleep = 0;
-                        continue;
-                }
-                /* This UART can now safely sleep. */
-                omap_uart_allow_sleep(uart);
-        }
-        return can_sleep;
-}
-/**
+#ifdef CONFIG_OMAP_MUX
- * omap_uart_interrupt()
+static struct omap_device_pad default_uart1_pads[] __initdata = {
- *
+        {
- * This handler is used only to detect that *any* UART interrupt has
+                .name   = "uart1_cts.uart1_cts",
- * occurred.  It does _nothing_ to handle the interrupt.  Rather,
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
- * any UART interrupt will trigger the inactivity timer so the
+        },
- * UART will not idle or sleep for its timeout period.
+        {
- *
+                .name   = "uart1_rts.uart1_rts",
- **/
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-/* static int first_interrupt; */
+        },
-static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
+        {
-{
+                .name   = "uart1_tx.uart1_tx",
-        struct omap_uart_state *uart = dev_id;
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart1_rx.uart1_rx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+};
-        omap_uart_block_sleep(uart);
+static struct omap_device_pad default_uart2_pads[] __initdata = {
+        {
+                .name   = "uart2_cts.uart2_cts",
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart2_rts.uart2_rts",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart2_tx.uart2_tx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart2_rx.uart2_rx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+};
-        return IRQ_NONE;
+static struct omap_device_pad default_uart3_pads[] __initdata = {
-}
+        {
+                .name   = "uart3_cts_rctx.uart3_cts_rctx",
+                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart3_rts_sd.uart3_rts_sd",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart3_tx_irtx.uart3_tx_irtx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
+        },
+        {
+                .name   = "uart3_rx_irrx.uart3_rx_irrx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+        },
+};
-static void omap_uart_idle_init(struct omap_uart_state *uart)
+static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
-{
+        {
-        int ret;
+                .name   = "gpmc_wait2.uart4_tx",
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        uart->can_sleep = 0;
+        },
-        uart->timeout = DEFAULT_TIMEOUT;
+        {
-        setup_timer(&uart->timer, omap_uart_idle_timer,
+                .name   = "gpmc_wait3.uart4_rx",
-                    (unsigned long) uart);
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-        if (uart->timeout)
+                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-                mod_timer(&uart->timer, jiffies + uart->timeout);
+                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-        omap_uart_smart_idle_enable(uart, 0);
+        },
+};
-        if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
-                u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
-                u32 wk_mask = 0;
-                u32 padconf = 0;
-                /* XXX These PRM accesses do not belong here */
-                uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
-                uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
-                switch (uart->num) {
-                case 0:
-                        wk_mask = OMAP3430_ST_UART1_MASK;
-                        padconf = 0x182;
-                        break;
-                case 1:
-                        wk_mask = OMAP3430_ST_UART2_MASK;
-                        padconf = 0x17a;
-                        break;
-                case 2:
-                        wk_mask = OMAP3430_ST_UART3_MASK;
-                        padconf = 0x19e;
-                        break;
-                case 3:
-                        wk_mask = OMAP3630_ST_UART4_MASK;
-                        padconf = 0x0d2;
-                        break;
-                }
-                uart->wk_mask = wk_mask;
-                uart->padconf = padconf;
-        } else if (cpu_is_omap24xx()) {
-                u32 wk_mask = 0;
-                u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
-                switch (uart->num) {
-                case 0:
-                        wk_mask = OMAP24XX_ST_UART1_MASK;
-                        break;
-                case 1:
-                        wk_mask = OMAP24XX_ST_UART2_MASK;
-                        break;
-                case 2:
-                        wk_en = OMAP24XX_PM_WKEN2;
-                        wk_st = OMAP24XX_PM_WKST2;
-                        wk_mask = OMAP24XX_ST_UART3_MASK;
-                        break;
-                }
-                uart->wk_mask = wk_mask;
-                if (cpu_is_omap2430()) {
-                        uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
-                        uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
-                } else if (cpu_is_omap2420()) {
-                        uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
-                        uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
-                }
-        } else {
-                uart->wk_en = NULL;
-                uart->wk_st = NULL;
-                uart->wk_mask = 0;
-                uart->padconf = 0;
-        }
-        uart->irqflags |= IRQF_SHARED;
+static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
-        ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
+        {
-                                   IRQF_SHARED, "serial idle", (void *)uart);
+                .name   = "uart4_tx.uart4_tx",
-        WARN_ON(ret);
+                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-}
+        },
+        {
+                .name   = "uart4_rx.uart4_rx",
+                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
+                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
+        },
+};
-void omap_uart_enable_irqs(int enable)
+static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
 {
-        int ret;
+        switch (bdata->id) {
-        struct omap_uart_state *uart;
+        case 0:
+                bdata->pads = default_uart1_pads;
-        list_for_each_entry(uart, &uart_list, node) {
+                bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
-                if (enable) {
+                break;
-                        pm_runtime_put_sync(&uart->pdev->dev);
+        case 1:
-                        ret = request_threaded_irq(uart->irq, NULL,
+                bdata->pads = default_uart2_pads;
-                                                   omap_uart_interrupt,
+                bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
-                                                   IRQF_SHARED,
+                break;
-                                                   "serial idle",
+        case 2:
-                                                   (void *)uart);
+                bdata->pads = default_uart3_pads;
-                } else {
+                bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
-                        pm_runtime_get_noresume(&uart->pdev->dev);
+                break;
-                        free_irq(uart->irq, (void *)uart);
+        case 3:
+                if (cpu_is_omap44xx()) {
+                        bdata->pads = default_omap4_uart4_pads;
+                        bdata->pads_cnt =
+                                ARRAY_SIZE(default_omap4_uart4_pads);
+                } else if (cpu_is_omap3630()) {
+                        bdata->pads = default_omap36xx_uart4_pads;
+                        bdata->pads_cnt =
+                                ARRAY_SIZE(default_omap36xx_uart4_pads);
                }
+                break;
+        default:
+                break;
        }
 }
-static ssize_t sleep_timeout_show(struct device *dev,
-                                  struct device_attribute *attr,
-                                  char *buf)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct omap_device *odev = to_omap_device(pdev);
-        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
-        return sprintf(buf, "%u\n", uart->timeout / HZ);
-}
-static ssize_t sleep_timeout_store(struct device *dev,
-                                   struct device_attribute *attr,
-                                   const char *buf, size_t n)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct omap_device *odev = to_omap_device(pdev);
-        struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
-        unsigned int value;
-        if (sscanf(buf, "%u", &value) != 1) {
-                dev_err(dev, "sleep_timeout_store: Invalid value\n");
-                return -EINVAL;
-        }
-        uart->timeout = value * HZ;
-        if (uart->timeout)
-                mod_timer(&uart->timer, jiffies + uart->timeout);
-        else
-                /* A zero value means disable timeout feature */
-                omap_uart_block_sleep(uart);
-        return n;
-}
-static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
-                sleep_timeout_store);
-#define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 #else
-static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
+static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
-static void omap_uart_block_sleep(struct omap_uart_state *uart)
+#endif
-{
-        /* Needed to enable UART clocks when built without CONFIG_PM */
-        omap_uart_enable_clocks(uart);
-}
-#define DEV_CREATE_FILE(dev, attr)
-#endif /* CONFIG_PM */
-#ifndef CONFIG_SERIAL_OMAP
-/*
- * Override the default 8250 read handler: mem_serial_in()
- * Empty RX fifo read causes an abort on omap3630 and omap4
- * This function makes sure that an empty rx fifo is not read on these silicons
- * (OMAP1/2/3430 are not affected)
- */
-static unsigned int serial_in_override(struct uart_port *up, int offset)
-{
-        if (UART_RX == offset) {
-                unsigned int lsr;
-                lsr = __serial_read_reg(up, UART_LSR);
-                if (!(lsr & UART_LSR_DR))
-                        return -EPERM;
-        }
-        return __serial_read_reg(up, offset);
-}
-static void serial_out_override(struct uart_port *up, int offset, int value)
+char *cmdline_find_option(char *str)
 {
-        unsigned int status, tmout = 10000;
+        extern char *saved_command_line;
-        status = __serial_read_reg(up, UART_LSR);
+        return strstr(saved_command_line, str);
-        while (!(status & UART_LSR_THRE)) {
-                /* Wait up to 10ms for the character(s) to be sent. */
-                if (--tmout == 0)
-                        break;
-                udelay(1);
-                status = __serial_read_reg(up, UART_LSR);
-        }
-        __serial_write_reg(up, offset, value);
 }
-#endif
 static int __init omap_serial_early_init(void)
 {
-        int i = 0;
        do {
                char oh_name[MAX_UART_HWMOD_NAME_LEN];
                struct omap_hwmod *oh;
                struct omap_uart_state *uart;
+                char uart_name[MAX_UART_HWMOD_NAME_LEN];
                snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
-                         "uart%d", i + 1);
+                         "uart%d", num_uarts + 1);
                oh = omap_hwmod_lookup(oh_name);
                if (!oh)
                        break;
@@ -653,21 +271,35 @@ static int __init omap_serial_early_init(void)
                        return -ENODEV;
                uart->oh = oh;
-                uart->num = i++;
+                uart->num = num_uarts++;
                list_add_tail(&uart->node, &uart_list);
-                num_uarts++;
+                snprintf(uart_name, MAX_UART_HWMOD_NAME_LEN,
+                                "%s%d", OMAP_SERIAL_NAME, uart->num);
-                /*
-                 * NOTE: omap_hwmod_setup*() has not yet been called,
+                if (cmdline_find_option(uart_name)) {
-                 *       so no hwmod functions will work yet.
+                        console_uart_id = uart->num;
-                 */
+                        if (console_loglevel >= 10) {
-                /*
+                                uart_debug = true;
-                 * During UART early init, device need to be probed
+                                pr_info("%s used as console in debug mode"
-                 * to determine SoC specific init before omap_device
+                                                " uart%d clocks will not be"
-                 * is ready.  Therefore, don't allow idle here
+                                                " gated", uart_name, uart->num);
-                 */
+                        }
-                uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+                        if (cmdline_find_option("no_console_suspend"))
+                                no_console_suspend = true;
+                        /*
+                         * omap-uart can be used for earlyprintk logs
+                         * So if omap-uart is used as console then prevent
+                         * uart reset and idle to get logs from omap-uart
+                         * until uart console driver is available to take
+                         * care for console messages.
+                         * Idling or resetting omap-uart while printing logs
+                         * early boot logs can stall the boot-up.
+                         */
+                        oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
+                }
        } while (1);
        return 0;
@@ -677,6 +309,7 @@ core_initcall(omap_serial_early_init);
 /**
 * omap_serial_init_port() - initialize single serial port
 * @bdata: port specific board data pointer
+ * @info: platform specific data pointer
 *
 * This function initialies serial driver for given port only.
 * Platforms can call this function instead of omap_serial_init()
@@ -685,7 +318,8 @@ core_initcall(omap_serial_early_init);
 * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 * use only one of the two.
 */
-void __init omap_serial_init_port(struct omap_board_data *bdata)
+void __init omap_serial_init_port(struct omap_board_data *bdata,
+                        struct omap_uart_port_info *info)
 {
        struct omap_uart_state *uart;
        struct omap_hwmod *oh;
@@ -693,15 +327,7 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
        void *pdata = NULL;
        u32 pdata_size = 0;
        char *name;
-#ifndef CONFIG_SERIAL_OMAP
-        struct plat_serial8250_port ports[2] = {
-                {},
-                {.flags = 0},
-        };
-        struct plat_serial8250_port *p = &ports[0];
-#else
        struct omap_uart_port_info omap_up;
-#endif
        if (WARN_ON(!bdata))
                return;
@@ -713,66 +339,34 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
        list_for_each_entry(uart, &uart_list, node)
                if (bdata->id == uart->num)
                        break;
+        if (!info)
+                info = omap_serial_default_info;
        oh = uart->oh;
-        uart->dma_enabled = 0;
-#ifndef CONFIG_SERIAL_OMAP
-        name = "serial8250";
-        /*
-         * !! 8250 driver does not use standard IORESOURCE* It
-         * has it's own custom pdata that can be taken from
-         * the hwmod resource data.  But, this needs to be
-         * done after the build.
-         *
-         * ?? does it have to be done before the register ??
-         * YES, because platform_device_data_add() copies
-         * pdata, it does not use a pointer.
-         */
-        p->flags = UPF_BOOT_AUTOCONF;
-        p->iotype = UPIO_MEM;
-        p->regshift = 2;
-        p->uartclk = OMAP24XX_BASE_BAUD * 16;
-        p->irq = oh->mpu_irqs[0].irq;
-        p->mapbase = oh->slaves[0]->addr->pa_start;
-        p->membase = omap_hwmod_get_mpu_rt_va(oh);
-        p->irqflags = IRQF_SHARED;
-        p->private_data = uart;
-        /*
-         * omap44xx, ti816x: Never read empty UART fifo
-         * omap3xxx: Never read empty UART fifo on UARTs
-         * with IP rev >=0x52
-         */
-        uart->regshift = p->regshift;
-        uart->membase = p->membase;
-        if (cpu_is_omap44xx() || cpu_is_ti816x())
-                uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
-        else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
-                        >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
-                uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
-        if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
-                p->serial_in = serial_in_override;
-                p->serial_out = serial_out_override;
-        }
-        pdata = &ports[0];
-        pdata_size = 2 * sizeof(struct plat_serial8250_port);
-#else
        name = DRIVER_NAME;
-        omap_up.dma_enabled = uart->dma_enabled;
+        omap_up.dma_enabled = info->dma_enabled;
        omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
-        omap_up.mapbase = oh->slaves[0]->addr->pa_start;
+        omap_up.flags = UPF_BOOT_AUTOCONF;
-        omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
+        omap_up.get_context_loss_count = omap_pm_get_dev_context_loss_count;
-        omap_up.irqflags = IRQF_SHARED;
+        omap_up.set_forceidle = omap_uart_set_forceidle;
-        omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+        omap_up.set_noidle = omap_uart_set_noidle;
+        omap_up.enable_wakeup = omap_uart_enable_wakeup;
+        omap_up.dma_rx_buf_size = info->dma_rx_buf_size;
+        omap_up.dma_rx_timeout = info->dma_rx_timeout;
+        omap_up.dma_rx_poll_rate = info->dma_rx_poll_rate;
+        omap_up.autosuspend_timeout = info->autosuspend_timeout;
+        /* Enable the MDR1 Errata i202 for OMAP2430/3xxx/44xx */
+        if (!cpu_is_omap2420() && !cpu_is_ti816x())
+                omap_up.errata |= UART_ERRATA_i202_MDR1_ACCESS;
+        /* Enable DMA Mode Force Idle Errata i291 for omap34xx/3630 */
+        if (cpu_is_omap34xx() || cpu_is_omap3630())
+                omap_up.errata |= UART_ERRATA_i291_DMA_FORCEIDLE;
        pdata = &omap_up;
        pdata_size = sizeof(struct omap_uart_port_info);
-#endif
        if (WARN_ON(!oh))
                return;
@@ -782,64 +376,29 @@ void __init omap_serial_init_port(struct omap_board_data *bdata)
        WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
             name, oh->name);
-        omap_device_disable_idle_on_suspend(pdev);
+        if ((console_uart_id == bdata->id) && no_console_suspend)
+                omap_device_disable_idle_on_suspend(pdev);
        oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
-        uart->irq = oh->mpu_irqs[0].irq;
-        uart->regshift = 2;
-        uart->mapbase = oh->slaves[0]->addr->pa_start;
-        uart->membase = omap_hwmod_get_mpu_rt_va(oh);
        uart->pdev = pdev;
        oh->dev_attr = uart;
-        console_lock(); /* in case the earlycon is on the UART */
+        if (((cpu_is_omap34xx() || cpu_is_omap44xx()) && bdata->pads)
+                        && !uart_debug)
-        /*
-         * Because of early UART probing, UART did not get idled
-         * on init.  Now that omap_device is ready, ensure full idle
-         * before doing omap_device_enable().
-         */
-        omap_hwmod_idle(uart->oh);
-        omap_device_enable(uart->pdev);
-        omap_uart_idle_init(uart);
-        omap_uart_reset(uart);
-        omap_hwmod_enable_wakeup(uart->oh);
-        omap_device_idle(uart->pdev);
-        /*
-         * Need to block sleep long enough for interrupt driven
-         * driver to start.  Console driver is in polling mode
-         * so device needs to be kept enabled while polling driver
-         * is in use.
-         */
-        if (uart->timeout)
-                uart->timeout = (30 * HZ);
-        omap_uart_block_sleep(uart);
-        uart->timeout = DEFAULT_TIMEOUT;
-        console_unlock();
-        if ((cpu_is_omap34xx() && uart->padconf) ||
-            (uart->wk_en && uart->wk_mask)) {
                device_init_wakeup(&pdev->dev, true);
-                DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
-        }
-        /* Enable the MDR1 errata for OMAP3 */
-        if (cpu_is_omap34xx() && !cpu_is_ti816x())
-                uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 }
 /**
- * omap_serial_init() - initialize all supported serial ports
+ * omap_serial_board_init() - initialize all supported serial ports
+ * @info: platform specific data pointer
 *
 * Initializes all available UARTs as serial ports. Platforms
 * can call this function when they want to have default behaviour
 * for serial ports (e.g initialize them all as serial ports).
 */
-void __init omap_serial_init(void)
+void __init omap_serial_board_init(struct omap_uart_port_info *info)
 {
        struct omap_uart_state *uart;
        struct omap_board_data bdata;
@@ -849,7 +408,25 @@ void __init omap_serial_init(void)
                bdata.flags = 0;
                bdata.pads = NULL;
                bdata.pads_cnt = 0;
-                omap_serial_init_port(&bdata);
+                if (cpu_is_omap44xx() || cpu_is_omap34xx())
+                        omap_serial_fill_default_pads(&bdata);
+                if (!info)
+                        omap_serial_init_port(&bdata, NULL);
+                else
+                        omap_serial_init_port(&bdata, &info[uart->num]);
        }
 }
+/**
+ * omap_serial_init() - initialize all supported serial ports
+ *
+ * Initializes all available UARTs.
+ * Platforms can call this function when they want to have default behaviour
+ * for serial ports (e.g initialize them all as serial ports).
+ */
+void __init omap_serial_init(void)
+{
+        omap_serial_board_init(NULL);
+}
diff --git a/arch/arm/mach-omap2/sleep44xx.S b/arch/arm/mach-omap2/sleep44xx.S
new file mode 100644
index 00000000000..abd28340049
--- /dev/null
+++ b/arch/arm/mach-omap2/sleep44xx.S
@@ -0,0 +1,379 @@
+/*
+ * OMAP44xx sleep code.
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ *      Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This program is free software,you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/smp_scu.h>
+#include <asm/memory.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <plat/omap44xx.h>
+#include <mach/omap-secure.h>
+#include "common.h"
+#include "omap4-sar-layout.h"
+#if defined(CONFIG_SMP) && defined(CONFIG_PM)
+.macro  DO_SMC
+        dsb
+        smc     #0
+        dsb
+.endm
+ppa_zero_params:
+        .word           0x0
+ppa_por_params:
+        .word           1, 0
+/*
+ * =============================
+ * == CPU suspend finisher ==
+ * =============================
+ *
+ * void omap4_finish_suspend(unsigned long cpu_state)
+ *
+ * This function code saves the CPU context and performs the CPU
+ * power down sequence. Calling WFI effectively changes the CPU
+ * power domains states to the desired target power state.
+ *
+ * @cpu_state : contains context save state (r0)
+ *      0 - No context lost
+ *      1 - CPUx L1 and logic lost: MPUSS CSWR
+ *      2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
+ *      3 - CPUx L1 and logic lost + GIC + L2 lost: MPUSS OFF
+ * @return: This function never returns for CPU OFF and DORMANT power states.
+ * Post WFI, CPU transitions to DORMANT or OFF power state and on wake-up
+ * from this follows a full CPU reset path via ROM code to CPU restore code.
+ * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
+ * It returns to the caller for CPU INACTIVE and ON power states or in case
+ * CPU failed to transition to targeted OFF/DORMANT state.
+ */
+ENTRY(omap4_finish_suspend)
+        stmfd   sp!, {lr}
+        cmp     r0, #0x0
+        beq     do_WFI                          @ No lowpower state, jump to WFI
+        /*
+         * Flush all data from the L1 data cache before disabling
+         * SCTLR.C bit.
+         */
+        bl      omap4_get_sar_ram_base
+        ldr     r9, [r0, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Check for HS device
+        bne     skip_secure_l1_clean
+        mov     r0, #SCU_PM_NORMAL
+        mov     r1, #0xFF                       @ clean seucre L1
+        stmfd   r13!, {r4-r12, r14}
+        ldr     r12, =OMAP4_MON_SCU_PWR_INDEX
+        DO_SMC
+        ldmfd   r13!, {r4-r12, r14}
+skip_secure_l1_clean:
+        bl      v7_flush_dcache_all
+        /*
+         * Clear the SCTLR.C bit to prevent further data cache
+         * allocation. Clearing SCTLR.C would make all the data accesses
+         * strongly ordered and would not hit the cache.
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        bic     r0, r0, #(1 << 2)               @ Disable the C bit
+        mcr     p15, 0, r0, c1, c0, 0
+        isb
+        /*
+         * Invalidate L1 data cache. Even though only invalidate is
+         * necessary exported flush API is used here. Doing clean
+         * on already clean cache would be almost NOP.
+         */
+        bl      v7_flush_dcache_all
+        /*
+         * Switch the CPU from Symmetric Multiprocessing (SMP) mode
+         * to AsymmetricMultiprocessing (AMP) mode by programming
+         * the SCU power status to DORMANT or OFF mode.
+         * This enables the CPU to be taken out of coherency by
+         * preventing the CPU from receiving cache, TLB, or BTB
+         * maintenance operations broadcast by other CPUs in the cluster.
+         */
+        bl      omap4_get_sar_ram_base
+        mov     r8, r0
+        ldr     r9, [r8, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Check for HS device
+        bne     scu_gp_set
+        mrc     p15, 0, r0, c0, c0, 5           @ Read MPIDR
+        ands    r0, r0, #0x0f
+        ldreq   r0, [r8, #SCU_OFFSET0]
+        ldrne   r0, [r8, #SCU_OFFSET1]
+        mov     r1, #0x00
+        stmfd   r13!, {r4-r12, r14}
+        ldr     r12, =OMAP4_MON_SCU_PWR_INDEX
+        DO_SMC
+        ldmfd   r13!, {r4-r12, r14}
+        b       skip_scu_gp_set
+scu_gp_set:
+        mrc     p15, 0, r0, c0, c0, 5           @ Read MPIDR
+        ands    r0, r0, #0x0f
+        ldreq   r1, [r8, #SCU_OFFSET0]
+        ldrne   r1, [r8, #SCU_OFFSET1]
+        bl      omap4_get_scu_base
+        bl      scu_power_mode
+skip_scu_gp_set:
+        mrc     p15, 0, r0, c1, c1, 2           @ Read NSACR data
+        tst     r0, #(1 << 18)
+        mrcne   p15, 0, r0, c1, c0, 1
+        bicne   r0, r0, #(1 << 6)               @ Disable SMP bit
+        mcrne   p15, 0, r0, c1, c0, 1
+        isb
+        dsb
+#ifdef CONFIG_CACHE_L2X0
+        /*
+         * Clean and invalidate the L2 cache.
+         * Common cache-l2x0.c functions can't be used here since it
+         * uses spinlocks. We are out of coherency here with data cache
+         * disabled. The spinlock implementation uses exclusive load/store
+         * instruction which can fail without data cache being enabled.
+         * OMAP4 hardware doesn't support exclusive monitor which can
+         * overcome exclusive access issue. Because of this, CPU can
+         * lead to deadlock.
+         */
+        bl      omap4_get_sar_ram_base
+        mov     r8, r0
+        mrc     p15, 0, r5, c0, c0, 5           @ Read MPIDR
+        ands    r5, r5, #0x0f
+        ldreq   r0, [r8, #L2X0_SAVE_OFFSET0]    @ Retrieve L2 state from SAR
+        ldrne   r0, [r8, #L2X0_SAVE_OFFSET1]    @ memory.
+        cmp     r0, #3
+        bne     do_WFI
+#ifdef CONFIG_PL310_ERRATA_727915
+        mov     r0, #0x03
+        mov     r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+        DO_SMC
+#endif
+        bl      omap4_get_l2cache_base
+        mov     r2, r0
+        ldr     r0, =0xffff
+        str     r0, [r2, #L2X0_CLEAN_INV_WAY]
+wait:
+        ldr     r0, [r2, #L2X0_CLEAN_INV_WAY]
+        ldr     r1, =0xffff
+        ands    r0, r0, r1
+        bne     wait
+#ifdef CONFIG_PL310_ERRATA_727915
+        mov     r0, #0x00
+        mov     r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX
+        DO_SMC
+#endif
+l2x_sync:
+        bl      omap4_get_l2cache_base
+        mov     r2, r0
+        mov     r0, #0x0
+        str     r0, [r2, #L2X0_CACHE_SYNC]
+sync:
+        ldr     r0, [r2, #L2X0_CACHE_SYNC]
+        ands    r0, r0, #0x1
+        bne     sync
+#endif
+do_WFI:
+        bl      omap_do_wfi
+        /*
+         * CPU is here when it failed to enter OFF/DORMANT or
+         * no low power state was attempted.
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        tst     r0, #(1 << 2)                   @ Check C bit enabled?
+        orreq   r0, r0, #(1 << 2)               @ Enable the C bit
+        mcreq   p15, 0, r0, c1, c0, 0
+        isb
+        /*
+         * Ensure the CPU power state is set to NORMAL in
+         * SCU power state so that CPU is back in coherency.
+         * In non-coherent mode CPU can lock-up and lead to
+         * system deadlock.
+         */
+        mrc     p15, 0, r0, c1, c0, 1
+        tst     r0, #(1 << 6)                   @ Check SMP bit enabled?
+        orreq   r0, r0, #(1 << 6)
+        mcreq   p15, 0, r0, c1, c0, 1
+        isb
+        bl      omap4_get_sar_ram_base
+        mov     r8, r0
+        ldr     r9, [r8, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Check for HS device
+        bne     scu_gp_clear
+        mov     r0, #SCU_PM_NORMAL
+        mov     r1, #0x00
+        stmfd   r13!, {r4-r12, r14}
+        ldr     r12, =OMAP4_MON_SCU_PWR_INDEX
+        DO_SMC
+        ldmfd   r13!, {r4-r12, r14}
+        b       skip_scu_gp_clear
+scu_gp_clear:
+        bl      omap4_get_scu_base
+        mov     r1, #SCU_PM_NORMAL
+        bl      scu_power_mode
+skip_scu_gp_clear:
+        isb
+        dsb
+        ldmfd   sp!, {pc}
+ENDPROC(omap4_finish_suspend)
+/*
+ * ============================
+ * == CPU resume entry point ==
+ * ============================
+ *
+ * void omap4_cpu_resume(void)
+ *
+ * ROM code jumps to this function while waking up from CPU
+ * OFF or DORMANT state. Physical address of the function is
+ * stored in the SAR RAM while entering to OFF or DORMANT mode.
+ * The restore function pointer is stored at CPUx_WAKEUP_NS_PA_ADDR_OFFSET.
+ */
+ENTRY(omap4_cpu_resume)
+        /*
+         * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
+         * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
+         * init and for CPU1, a secure PPA API provided. CPU0 must be ON
+         * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
+         * OMAP443X GP devices- SMP bit isn't accessible.
+         * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
+         */
+        ldr     r8, =OMAP44XX_SAR_RAM_BASE
+        ldr     r9, [r8, #OMAP_TYPE_OFFSET]
+        cmp     r9, #0x1                        @ Skip if GP device
+        bne     skip_ns_smp_enable
+        mrc     p15, 0, r0, c0, c0, 5
+        ands    r0, r0, #0x0f
+        beq     skip_ns_smp_enable
+ppa_actrl_retry:
+        mov     r0, #OMAP4_PPA_CPU_ACTRL_SMP_INDEX
+        adr     r3, ppa_zero_params             @ Pointer to parameters
+        mov     r1, #0x0                        @ Process ID
+        mov     r2, #0x4                        @ Flag
+        mov     r6, #0xff
+        mov     r12, #0x00                      @ Secure Service ID
+        DO_SMC
+        cmp     r0, #0x0                        @ API returns 0 on success.
+        beq     enable_smp_bit
+        b       ppa_actrl_retry
+enable_smp_bit:
+        mrc     p15, 0, r0, c1, c0, 1
+        tst     r0, #(1 << 6)                   @ Check SMP bit enabled?
+        orreq   r0, r0, #(1 << 6)
+        mcreq   p15, 0, r0, c1, c0, 1
+        isb
+skip_ns_smp_enable:
+#ifdef CONFIG_CACHE_L2X0
+        /*
+         * Restore the L2 AUXCTRL and enable the L2 cache.
+         * OMAP4_MON_L2X0_AUXCTRL_INDEX =  Program the L2X0 AUXCTRL
+         * OMAP4_MON_L2X0_CTRL_INDEX =  Enable the L2 using L2X0 CTRL
+         * register r0 contains value to be programmed.
+         * L2 cache is already invalidate by ROM code as part
+         * of MPUSS OFF wakeup path.
+         */
+        ldr     r2, =OMAP44XX_L2CACHE_BASE
+        ldr     r0, [r2, #L2X0_CTRL]
+        and     r0, #0x0f
+        cmp     r0, #1
+        beq     skip_l2en                       @ Skip if already enabled
+        ldr     r3, =OMAP44XX_SAR_RAM_BASE
+        ldr     r1, [r3, #OMAP_TYPE_OFFSET]
+        cmp     r1, #0x1                        @ Check for HS device
+        bne     set_gp_por
+        ldr     r0, =OMAP4_PPA_L2_POR_INDEX
+        ldr     r1, =OMAP44XX_SAR_RAM_BASE
+        ldr     r4, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
+        adr     r3, ppa_por_params
+        str     r4, [r3, #0x04]
+        mov     r1, #0x0                        @ Process ID
+        mov     r2, #0x4                        @ Flag
+        mov     r6, #0xff
+        mov     r12, #0x00                      @ Secure Service ID
+        DO_SMC
+        b       set_aux_ctrl
+set_gp_por:
+        ldr     r1, =OMAP44XX_SAR_RAM_BASE
+        ldr     r0, [r1, #L2X0_PREFETCH_CTRL_OFFSET]
+        ldr     r12, =OMAP4_MON_L2X0_PREFETCH_INDEX     @ Setup L2 PREFETCH
+        DO_SMC
+set_aux_ctrl:
+        ldr     r1, =OMAP44XX_SAR_RAM_BASE
+        ldr     r0, [r1, #L2X0_AUXCTRL_OFFSET]
+        ldr     r12, =OMAP4_MON_L2X0_AUXCTRL_INDEX      @ Setup L2 AUXCTRL
+        DO_SMC
+        mov     r0, #0x1
+        ldr     r12, =OMAP4_MON_L2X0_CTRL_INDEX         @ Enable L2 cache
+        DO_SMC
+skip_l2en:
+#endif
+        b       cpu_resume                      @ Jump to generic resume
+ENDPROC(omap4_cpu_resume)
+#endif
+#ifndef CONFIG_OMAP4_ERRATA_I688
+ENTRY(omap_bus_sync)
+        mov     pc, lr
+ENDPROC(omap_bus_sync)
+#endif
+ENTRY(omap_do_wfi)
+        stmfd   sp!, {lr}
+        /* Drain interconnect write buffers. */
+        bl omap_bus_sync
+        /*
+         * Execute an ISB instruction to ensure that all of the
+         * CP15 register changes have been committed.
+         */
+        isb
+        /*
+         * Execute a barrier instruction to ensure that all cache,
+         * TLB and branch predictor maintenance operations issued
+         * by any CPU in the cluster have completed.
+         */
+        dsb
+        dmb
+        /*
+         * Execute a WFI instruction and wait until the
+         * STANDBYWFI output is asserted to indicate that the
+         * CPU is in idle and low power state. CPU can specualatively
+         * prefetch the instructions so add NOPs after WFI. Sixteen
+         * NOPs as per Cortex-A9 pipeline.
+         */
+        wfi                                     @ Wait For Interrupt
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        ldmfd   sp!, {pc}
+ENDPROC(omap_do_wfi)
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index cf246b39bac..9dd93453e56 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -26,7 +26,7 @@
 #include <linux/slab.h>
 #include <linux/pm_runtime.h>
-#include <plat/common.h>
+#include "common.h"
 #include "pm.h"
 #include "smartreflex.h"
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 037b0d7d4e0..6eeff0e0ae0 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -41,7 +41,7 @@
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
 #include <asm/sched_clock.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 #include <plat/omap-pm.h>
@@ -254,7 +254,6 @@ static struct omap_dm_timer clksrc;
 /*
 * clocksource
 */
-static DEFINE_CLOCK_DATA(cd);
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
        return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
@@ -268,23 +267,12 @@ static struct clocksource clocksource_gpt = {
        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
-static void notrace dmtimer_update_sched_clock(void)
+static u32 notrace dmtimer_read_sched_clock(void)
 {
-        u32 cyc;
-        cyc = __omap_dm_timer_read_counter(&clksrc, 1);
-        update_sched_clock(&cd, cyc, (u32)~0);
-}
-unsigned long long notrace sched_clock(void)
-{
-        u32 cyc = 0;
        if (clksrc.reserved)
-                cyc = __omap_dm_timer_read_counter(&clksrc, 1);
+                return __omap_dm_timer_read_counter(clksrc.io_base, 1);
-        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+        return 0;
 }
 /* Setup free-running counter for clocksource */
@@ -301,7 +289,7 @@ static void __init omap2_gp_clocksource_init(int gptimer_id,
        __omap_dm_timer_load_start(&clksrc,
                        OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
-        init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
+        setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
        if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
                pr_err("Could not register clocksource %s\n",
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 89ae29847c5..771dc781b74 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -28,51 +28,28 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <plat/usb.h>
+#include <plat/omap_device.h>
 #include "mux.h"
 #ifdef CONFIG_MFD_OMAP_USB_HOST
-#define OMAP_USBHS_DEVICE       "usbhs-omap"
+#define OMAP_USBHS_DEVICE       "usbhs_omap"
+#define USBHS_UHH_HWMODNAME     "usb_host_hs"
-static struct resource usbhs_resources[] = {
+#define USBHS_TLL_HWMODNAME     "usb_tll_hs"
-        {
-                .name   = "uhh",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "tll",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "ehci",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "ehci-irq",
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .name   = "ohci",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .name   = "ohci-irq",
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device usbhs_device = {
-        .name           = OMAP_USBHS_DEVICE,
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(usbhs_resources),
-        .resource       = usbhs_resources,
-};
 static struct usbhs_omap_platform_data          usbhs_data;
 static struct ehci_hcd_omap_platform_data       ehci_data;
 static struct ohci_hcd_omap_platform_data       ohci_data;
+static struct omap_device_pm_latency omap_uhhtll_latency[] = {
+          {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+          },
+};
 /* MUX settings for EHCI pins */
 /*
 * setup_ehci_io_mux - initialize IO pad mux for USBHOST
@@ -508,7 +485,10 @@ static void setup_4430ohci_io_mux(const enum usbhs_omap_port_mode *port_mode)
 void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
 {
-        int     i;
+        struct omap_hwmod       *oh[2];
+        struct omap_device      *od;
+        int                     bus_id = -1;
+        int                     i;
        for (i = 0; i < OMAP3_HS_USB_PORTS; i++) {
                usbhs_data.port_mode[i] = pdata->port_mode[i];
@@ -523,44 +503,34 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
        usbhs_data.ohci_data = &ohci_data;
        if (cpu_is_omap34xx()) {
-                usbhs_resources[0].start = OMAP34XX_UHH_CONFIG_BASE;
-                usbhs_resources[0].end = OMAP34XX_UHH_CONFIG_BASE + SZ_1K - 1;
-                usbhs_resources[1].start = OMAP34XX_USBTLL_BASE;
-                usbhs_resources[1].end = OMAP34XX_USBTLL_BASE + SZ_4K - 1;
-                usbhs_resources[2].start        = OMAP34XX_EHCI_BASE;
-                usbhs_resources[2].end  = OMAP34XX_EHCI_BASE + SZ_1K - 1;
-                usbhs_resources[3].start = INT_34XX_EHCI_IRQ;
-                usbhs_resources[4].start        = OMAP34XX_OHCI_BASE;
-                usbhs_resources[4].end  = OMAP34XX_OHCI_BASE + SZ_1K - 1;
-                usbhs_resources[5].start = INT_34XX_OHCI_IRQ;
                setup_ehci_io_mux(pdata->port_mode);
                setup_ohci_io_mux(pdata->port_mode);
        } else if (cpu_is_omap44xx()) {
-                usbhs_resources[0].start = OMAP44XX_UHH_CONFIG_BASE;
-                usbhs_resources[0].end = OMAP44XX_UHH_CONFIG_BASE + SZ_1K - 1;
-                usbhs_resources[1].start = OMAP44XX_USBTLL_BASE;
-                usbhs_resources[1].end = OMAP44XX_USBTLL_BASE + SZ_4K - 1;
-                usbhs_resources[2].start = OMAP44XX_HSUSB_EHCI_BASE;
-                usbhs_resources[2].end = OMAP44XX_HSUSB_EHCI_BASE + SZ_1K - 1;
-                usbhs_resources[3].start = OMAP44XX_IRQ_EHCI;
-                usbhs_resources[4].start = OMAP44XX_HSUSB_OHCI_BASE;
-                usbhs_resources[4].end = OMAP44XX_HSUSB_OHCI_BASE + SZ_1K - 1;
-                usbhs_resources[5].start = OMAP44XX_IRQ_OHCI;
                setup_4430ehci_io_mux(pdata->port_mode);
                setup_4430ohci_io_mux(pdata->port_mode);
        }
-        if (platform_device_add_data(&usbhs_device,
+        oh[0] = omap_hwmod_lookup(USBHS_UHH_HWMODNAME);
-                                &usbhs_data, sizeof(usbhs_data)) < 0) {
+        if (!oh[0]) {
-                printk(KERN_ERR "USBHS platform_device_add_data failed\n");
+                pr_err("Could not look up %s\n", USBHS_UHH_HWMODNAME);
-                goto init_end;
+                return;
        }
-        if (platform_device_register(&usbhs_device) < 0)
+        oh[1] = omap_hwmod_lookup(USBHS_TLL_HWMODNAME);
-                printk(KERN_ERR "USBHS platform_device_register failed\n");
+        if (!oh[1]) {
+                pr_err("Could not look up %s\n", USBHS_TLL_HWMODNAME);
+                return;
+        }
-init_end:
+        od = omap_device_build_ss(OMAP_USBHS_DEVICE, bus_id, oh, 2,
-        return;
+                                (void *)&usbhs_data, sizeof(usbhs_data),
+                                omap_uhhtll_latency,
+                                ARRAY_SIZE(omap_uhhtll_latency), false);
+        if (IS_ERR(od)) {
+                pr_err("Could not build hwmod devices %s,%s\n",
+                        USBHS_UHH_HWMODNAME, USBHS_TLL_HWMODNAME);
+                return;
+        }
 }
 #else
@@ -570,5 +540,3 @@ void __init usbhs_init(const struct usbhs_omap_board_data *pdata)
 }
 #endif
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 267975086a7..8d5ed775dd5 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -93,6 +93,9 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
        if (cpu_is_omap3517() || cpu_is_omap3505()) {
                oh_name = "am35x_otg_hs";
                name = "musb-am35x";
+        } else if (cpu_is_ti81xx()) {
+                oh_name = "usb_otg_hs";
+                name = "musb-ti81xx";
        } else {
                oh_name = "usb_otg_hs";
                name = "musb-omap2430";
diff --git a/arch/arm/mach-omap2/vc3xxx_data.c b/arch/arm/mach-omap2/vc3xxx_data.c
index cfe348e1af0..a5ec7f8f2ea 100644
--- a/arch/arm/mach-omap2/vc3xxx_data.c
+++ b/arch/arm/mach-omap2/vc3xxx_data.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm-regbits-34xx.h"
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/vc44xx_data.c b/arch/arm/mach-omap2/vc44xx_data.c
index 2740a968145..d70b930f273 100644
--- a/arch/arm/mach-omap2/vc44xx_data.c
+++ b/arch/arm/mach-omap2/vc44xx_data.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 1f8fdf736e6..8a36342e60d 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -27,7 +27,7 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm-regbits-34xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/voltagedomains3xxx_data.c b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
index 071101debbb..c005e2f5e38 100644
--- a/arch/arm/mach-omap2/voltagedomains3xxx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains3xxx_data.c
@@ -18,7 +18,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include <plat/cpu.h>
 #include "prm-regbits-34xx.h"
@@ -31,6 +31,14 @@
 * VDD data
 */
+/* OMAP3-common voltagedomain data */
+static struct voltagedomain omap3_voltdm_wkup = {
+        .name = "wakeup",
+};
+/* 34xx/36xx voltagedomain data */
 static const struct omap_vfsm_instance omap3_vdd1_vfsm = {
        .voltsetup_reg = OMAP3_PRM_VOLTSETUP1_OFFSET,
        .voltsetup_mask = OMAP3430_SETUP_TIME1_MASK,
@@ -63,10 +71,6 @@ static struct voltagedomain omap3_voltdm_core = {
        .vp = &omap3_vp_core,
 };
-static struct voltagedomain omap3_voltdm_wkup = {
-        .name = "wakeup",
-};
 static struct voltagedomain *voltagedomains_omap3[] __initdata = {
        &omap3_voltdm_mpu,
        &omap3_voltdm_core,
@@ -74,11 +78,30 @@ static struct voltagedomain *voltagedomains_omap3[] __initdata = {
        NULL,
 };
+/* AM35xx voltagedomain data */
+static struct voltagedomain am35xx_voltdm_mpu = {
+        .name = "mpu_iva",
+};
+static struct voltagedomain am35xx_voltdm_core = {
+        .name = "core",
+};
+static struct voltagedomain *voltagedomains_am35xx[] __initdata = {
+        &am35xx_voltdm_mpu,
+        &am35xx_voltdm_core,
+        &omap3_voltdm_wkup,
+        NULL,
+};
 static const char *sys_clk_name __initdata = "sys_ck";
 void __init omap3xxx_voltagedomains_init(void)
 {
        struct voltagedomain *voltdm;
+        struct voltagedomain **voltdms;
        int i;
        /*
@@ -93,8 +116,13 @@ void __init omap3xxx_voltagedomains_init(void)
                omap3_voltdm_core.volt_data = omap34xx_vddcore_volt_data;
        }
-        for (i = 0; voltdm = voltagedomains_omap3[i], voltdm; i++)
+        if (cpu_is_omap3517() || cpu_is_omap3505())
+                voltdms = voltagedomains_am35xx;
+        else
+                voltdms = voltagedomains_omap3;
+        for (i = 0; voltdm = voltdms[i], voltdm; i++)
                voltdm->sys_clk.name = sys_clk_name;
-        voltdm_init(voltagedomains_omap3);
+        voltdm_init(voltdms);
 };
diff --git a/arch/arm/mach-omap2/voltagedomains44xx_data.c b/arch/arm/mach-omap2/voltagedomains44xx_data.c
index c4584e9ac71..4e11d022595 100644
--- a/arch/arm/mach-omap2/voltagedomains44xx_data.c
+++ b/arch/arm/mach-omap2/voltagedomains44xx_data.c
@@ -21,7 +21,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm-regbits-44xx.h"
 #include "prm44xx.h"
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index 66bd700a2b9..807391d84a9 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -1,7 +1,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "voltage.h"
 #include "vp.h"
diff --git a/arch/arm/mach-omap2/vp3xxx_data.c b/arch/arm/mach-omap2/vp3xxx_data.c
index 260c554b154..bd89f80089f 100644
--- a/arch/arm/mach-omap2/vp3xxx_data.c
+++ b/arch/arm/mach-omap2/vp3xxx_data.c
@@ -19,7 +19,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm-regbits-34xx.h"
 #include "voltage.h"
diff --git a/arch/arm/mach-omap2/vp44xx_data.c b/arch/arm/mach-omap2/vp44xx_data.c
index b4e77044891..8c031d16879 100644
--- a/arch/arm/mach-omap2/vp44xx_data.c
+++ b/arch/arm/mach-omap2/vp44xx_data.c
@@ -19,7 +19,7 @@
 #include <linux/err.h>
 #include <linux/init.h>
-#include <plat/common.h>
+#include "common.h"
 #include "prm44xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index 5ceafdccc45..3638e5c12b7 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -14,8 +14,8 @@
 #include <linux/init.h>
 #include <linux/mbus.h>
 #include <linux/io.h>
-#include <linux/errno.h>
 #include <mach/hardware.h>
+#include <plat/addr-map.h>
 #include "common.h"
 /*
@@ -41,7 +41,6 @@
 /*
 * Generic Address Decode Windows bit settings
 */
-#define TARGET_DDR              0
 #define TARGET_DEV_BUS          1
 #define TARGET_PCI              3
 #define TARGET_PCIE             4
@@ -57,27 +56,10 @@
 #define ATTR_DEV_BOOT           0xf
 #define ATTR_SRAM               0x0
-/*
- * Helpers to get DDR bank info
- */
-#define ORION5X_DDR_REG(x)      (ORION5X_DDR_VIRT_BASE | (x))
-#define DDR_BASE_CS(n)          ORION5X_DDR_REG(0x1500 + ((n) << 3))
-#define DDR_SIZE_CS(n)          ORION5X_DDR_REG(0x1504 + ((n) << 3))
-/*
- * CPU Address Decode Windows registers
- */
-#define ORION5X_BRIDGE_REG(x)   (ORION5X_BRIDGE_VIRT_BASE | (x))
-#define CPU_WIN_CTRL(n)         ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
-#define CPU_WIN_BASE(n)         ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
-#define CPU_WIN_REMAP_LO(n)     ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
-#define CPU_WIN_REMAP_HI(n)     ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
-struct mbus_dram_target_info orion5x_mbus_dram_info;
 static int __initdata win_alloc_count;
-static int __init orion5x_cpu_win_can_remap(int win)
+static int __init cpu_win_can_remap(const struct orion_addr_map_cfg *cfg,
+                  const int win)
 {
        u32 dev, rev;
@@ -91,116 +73,82 @@ static int __init orion5x_cpu_win_can_remap(int win)
        return 0;
 }
-static int __init setup_cpu_win(int win, u32 base, u32 size,
+/*
-                                 u8 target, u8 attr, int remap)
+ * Description of the windows needed by the platform code
-{
+ */
-        if (win >= 8) {
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
-                printk(KERN_ERR "setup_cpu_win: trying to allocate "
+        .num_wins = 8,
-                                "window %d\n", win);
+        .cpu_win_can_remap = cpu_win_can_remap,
-                return -ENOSPC;
+        .bridge_virt_base = ORION5X_BRIDGE_VIRT_BASE,
-        }
+};
-        writel(base & 0xffff0000, CPU_WIN_BASE(win));
-        writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
-                CPU_WIN_CTRL(win));
-        if (orion5x_cpu_win_can_remap(win)) {
-                if (remap < 0)
-                        remap = base;
-                writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
-                writel(0, CPU_WIN_REMAP_HI(win));
-        }
-        return 0;
-}
-void __init orion5x_setup_cpu_mbus_bridge(void)
-{
-        int i;
-        int cs;
+static const struct __initdata orion_addr_map_info addr_map_info[] = {
        /*
-         * First, disable and clear windows.
+         * Setup windows for PCI+PCIe IO+MEM space.
         */
-        for (i = 0; i < 8; i++) {
+        { 0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
-                writel(0, CPU_WIN_BASE(i));
+          TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE
-                writel(0, CPU_WIN_CTRL(i));
+        },
-                if (orion5x_cpu_win_can_remap(i)) {
+        { 1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
-                        writel(0, CPU_WIN_REMAP_LO(i));
+          TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE
-                        writel(0, CPU_WIN_REMAP_HI(i));
+        },
-                }
+        { 2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
-        }
+          TARGET_PCIE, ATTR_PCIE_MEM, -1
+        },
+        { 3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
+          TARGET_PCI, ATTR_PCI_MEM, -1
+        },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 }
+};
+void __init orion5x_setup_cpu_mbus_bridge(void)
+{
        /*
-         * Setup windows for PCI+PCIe IO+MEM space.
+         * Disable, clear and configure windows.
         */
-        setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
+        orion_config_wins(&addr_map_cfg, addr_map_info);
-                TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
-        setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
-                TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
-        setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
-                TARGET_PCIE, ATTR_PCIE_MEM, -1);
-        setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
-                TARGET_PCI, ATTR_PCI_MEM, -1);
        win_alloc_count = 4;
        /*
         * Setup MBUS dram target info.
         */
-        orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+        orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
-        for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(DDR_BASE_CS(i));
-                u32 size = readl(DDR_SIZE_CS(i));
-                /*
-                 * Chip select enabled?
-                 */
-                if (size & 1) {
-                        struct mbus_dram_window *w;
-                        w = &orion5x_mbus_dram_info.cs[cs++];
-                        w->cs_index = i;
-                        w->mbus_attr = 0xf & ~(1 << i);
-                        w->base = base & 0xffff0000;
-                        w->size = (size | 0x0000ffff) + 1;
-                }
-        }
-        orion5x_mbus_dram_info.num_cs = cs;
 }
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
+                            TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
 }
 void __init orion5x_setup_dev0_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
+                            TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
 }
 void __init orion5x_setup_dev1_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
+                            TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
 }
 void __init orion5x_setup_dev2_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                      TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
+                            TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
 }
 void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
 {
-        setup_cpu_win(win_alloc_count++, base, size,
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++, base, size,
-                      TARGET_PCIE, ATTR_PCIE_WA, -1);
+                            TARGET_PCIE, ATTR_PCIE_WA, -1);
 }
-int __init orion5x_setup_sram_win(void)
+void __init orion5x_setup_sram_win(void)
 {
-        return setup_cpu_win(win_alloc_count++, ORION5X_SRAM_PHYS_BASE,
+        orion_setup_cpu_win(&addr_map_cfg, win_alloc_count++,
-                        ORION5X_SRAM_SIZE, TARGET_SRAM, ATTR_SRAM, -1);
+                            ORION5X_SRAM_PHYS_BASE, ORION5X_SRAM_SIZE,
+                            TARGET_SRAM, ATTR_SRAM, -1);
 }
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 22ace0bf2f9..0e28bae20bd 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -15,9 +15,9 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/serial_8250.h>
-#include <linux/mbus.h>
 #include <linux/mv643xx_i2c.h>
 #include <linux/ata_platform.h>
+#include <linux/delay.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/setup.h>
@@ -31,6 +31,7 @@
 #include <plat/orion_nand.h>
 #include <plat/time.h>
 #include <plat/common.h>
+#include <plat/addr-map.h>
 #include "common.h"
 /*****************************************************************************
@@ -71,8 +72,7 @@ void __init orion5x_map_io(void)
 ****************************************************************************/
 void __init orion5x_ehci0_init(void)
 {
-        orion_ehci_init(&orion5x_mbus_dram_info,
+        orion_ehci_init(ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
-                        ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
 }
@@ -81,8 +81,7 @@ void __init orion5x_ehci0_init(void)
 ****************************************************************************/
 void __init orion5x_ehci1_init(void)
 {
-        orion_ehci_1_init(&orion5x_mbus_dram_info,
+        orion_ehci_1_init(ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
-                          ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
 }
@@ -91,7 +90,7 @@ void __init orion5x_ehci1_init(void)
 ****************************************************************************/
 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
 {
-        orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
+        orion_ge00_init(eth_data,
                        ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
                        IRQ_ORION5X_ETH_ERR, orion5x_tclk);
 }
@@ -121,8 +120,7 @@ void __init orion5x_i2c_init(void)
 ****************************************************************************/
 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 {
-        orion_sata_init(sata_data, &orion5x_mbus_dram_info,
+        orion_sata_init(sata_data, ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
-                        ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
 }
@@ -158,8 +156,7 @@ void __init orion5x_uart1_init(void)
 ****************************************************************************/
 void __init orion5x_xor_init(void)
 {
-        orion_xor0_init(&orion5x_mbus_dram_info,
+        orion_xor0_init(ORION5X_XOR_PHYS_BASE,
-                        ORION5X_XOR_PHYS_BASE,
                        ORION5X_XOR_PHYS_BASE + 0x200,
                        IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
 }
@@ -169,12 +166,7 @@ void __init orion5x_xor_init(void)
 ****************************************************************************/
 static void __init orion5x_crypto_init(void)
 {
-        int ret;
+        orion5x_setup_sram_win();
-        ret = orion5x_setup_sram_win();
-        if (ret)
-                return;
        orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
                          SZ_8K, IRQ_ORION5X_CESA);
 }
@@ -304,6 +296,17 @@ void __init orion5x_init(void)
        orion5x_wdt_init();
 }
+void orion5x_restart(char mode, const char *cmd)
+{
+        /*
+         * Enable and issue soft reset
+         */
+        orion5x_setbits(RSTOUTn_MASK, (1 << 2));
+        orion5x_setbits(CPU_SOFT_RESET, 1);
+        mdelay(200);
+        orion5x_clrbits(CPU_SOFT_RESET, 1);
+}
 /*
 * Many orion-based systems have buggy bootloader implementations.
 * This is a common fixup for bogus memory tags.
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 909489f4d23..d2513ac79ff 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -20,14 +20,13 @@ extern struct sys_timer orion5x_timer;
 * functions to map its interfaces and by the machine-setup to map its on-
 * board devices. Details in /mach-orion/addr-map.c
 */
-extern struct mbus_dram_target_info orion5x_mbus_dram_info;
 void orion5x_setup_cpu_mbus_bridge(void);
 void orion5x_setup_dev_boot_win(u32 base, u32 size);
 void orion5x_setup_dev0_win(u32 base, u32 size);
 void orion5x_setup_dev1_win(u32 base, u32 size);
 void orion5x_setup_dev2_win(u32 base, u32 size);
 void orion5x_setup_pcie_wa_win(u32 base, u32 size);
-int orion5x_setup_sram_win(void);
+void orion5x_setup_sram_win(void);
 void orion5x_ehci0_init(void);
 void orion5x_ehci1_init(void);
@@ -39,6 +38,7 @@ void orion5x_spi_init(void);
 void orion5x_uart0_init(void);
 void orion5x_uart1_init(void);
 void orion5x_xor_init(void);
+void orion5x_restart(char, const char *);
 /*
 * PCIe/PCI functions.
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 8c8300951f4..d75dcfa0f01 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -343,6 +343,7 @@ MACHINE_START(D2NET, "LaCie d2 Network")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
 #endif
@@ -355,6 +356,7 @@ MACHINE_START(BIGDISK, "LaCie Big Disk Network")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 4b79a80d5e1..a104d5a80e1 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -364,4 +364,5 @@ MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 343f60e9639..91b0f478859 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -736,4 +736,5 @@ MACHINE_START(DNS323, "D-Link DNS-323")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 70a4e9265f0..355e962137c 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -258,4 +258,5 @@ MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
index c5196101a23..e9d9afdc265 100644
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ b/arch/arm/mach-orion5x/include/mach/io.h
@@ -15,31 +15,6 @@
 #define IO_SPACE_LIMIT          0xffffffff
-static inline void __iomem *
-__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
-{
-        void __iomem *retval;
-        unsigned long offs = paddr - ORION5X_REGS_PHYS_BASE;
-        if (mtype == MT_DEVICE && size && offs < ORION5X_REGS_SIZE &&
-            size <= ORION5X_REGS_SIZE && offs + size <= ORION5X_REGS_SIZE) {
-                retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + offs;
-        } else {
-                retval = __arm_ioremap(paddr, size, mtype);
-        }
-        return retval;
-}
-static inline void
-__arch_iounmap(void __iomem *addr)
-{
-        if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
-            addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
-                __iounmap(addr);
-}
-#define __arch_ioremap          __arch_ioremap
-#define __arch_iounmap          __arch_iounmap
 #define __io(a)                 __typesafe_io(a)
 #define __mem_pci(a)            (a)
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 0a28bbc7689..2745f5d95b3 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -69,7 +69,7 @@
 ******************************************************************************/
 #define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
+#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE | 0x1500)
 #define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
 #define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
 #define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index a1d6e46ab03..825a2650cef 100644
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -11,23 +11,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <mach/bridge-regs.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        /*
-         * Enable and issue soft reset
-         */
-        orion5x_setbits(RSTOUTn_MASK, (1 << 2));
-        orion5x_setbits(CPU_SOFT_RESET, 1);
-        mdelay(200);
-        orion5x_clrbits(CPU_SOFT_RESET, 1);
-}
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/vmalloc.h b/arch/arm/mach-orion5x/include/mach/vmalloc.h
deleted file mode 100644
index 06b50aeff7b..00000000000
--- a/arch/arm/mach-orion5x/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/vmalloc.h
- */
-#define VMALLOC_END       0xfd800000UL
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index d3cd3f63258..47587b83284 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -386,6 +386,7 @@ MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
 #endif
@@ -399,5 +400,6 @@ MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 9503fff404e..527213169db 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -140,7 +140,7 @@ static struct mv_sata_platform_data lschl_sata_data = {
 static void lschl_power_off(void)
 {
-        arm_machine_restart('h', NULL);
+        orion5x_restart('h', NULL);
 }
 /*****************************************************************************
@@ -325,4 +325,5 @@ MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index ed6d772f4a2..9a8697b97dd 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -186,7 +186,7 @@ static struct mv_sata_platform_data ls_hgl_sata_data = {
 static void ls_hgl_power_off(void)
 {
-        arm_machine_restart('h', NULL);
+        orion5x_restart('h', NULL);
 }
@@ -272,4 +272,5 @@ MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 743f7f1db18..09c73659f46 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -186,7 +186,7 @@ static struct mv_sata_platform_data lsmini_sata_data = {
 static void lsmini_power_off(void)
 {
-        arm_machine_restart('h', NULL);
+        orion5x_restart('h', NULL);
 }
@@ -274,5 +274,6 @@ MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index b6ddd7a5db6..5b70026f478 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -10,7 +10,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mbus.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
 #include <plat/mpp.h>
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 6020e26b1c7..65faaa34de6 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -267,5 +267,6 @@ MACHINE_START(MSS2, "Maxtor Shared Storage II")
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
-        .fixup          = tag_fixup_mem32
+        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 201ae367628..c87fde4deec 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -234,5 +234,6 @@ MACHINE_START(MV2120, "HP Media Vault mv2120")
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
-        .fixup          = tag_fixup_mem32
+        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index 6197c79a2ec..0180c393c71 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -426,5 +426,6 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index bc4a920e26e..09a045f0c40 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -18,6 +18,7 @@
 #include <asm/irq.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <plat/addr-map.h>
 #include "common.h"
 /*****************************************************************************
@@ -145,7 +146,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
        /*
         * Generic PCIe unit setup.
         */
-        orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
+        orion_pcie_setup(PCIE_BASE);
        /*
         * Check whether to apply Orion-1/Orion-NAS PCIe config
@@ -176,7 +177,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
        res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
        if (request_resource(&ioport_resource, &res[0]))
                panic("Request PCIe IO resource failed\n");
-        sys->resource[0] = &res[0];
+        pci_add_resource(&sys->resources, &res[0]);
        /*
         * IORESOURCE_MEM
@@ -187,9 +188,8 @@ static int __init pcie_setup(struct pci_sys_data *sys)
        res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
        if (request_resource(&iomem_resource, &res[1]))
                panic("Request PCIe Memory resource failed\n");
-        sys->resource[1] = &res[1];
+        pci_add_resource(&sys->resources, &res[1]);
-        sys->resource[2] = NULL;
        sys->io_offset = 0;
        return 1;
@@ -477,7 +477,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
        /*
         * Point PCI unit MBUS decode windows to DRAM space.
         */
-        orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
+        orion5x_setup_pci_wins(&orion_mbus_dram_info);
        /*
         * Master + Slave enable
@@ -505,7 +505,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
        res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
        if (request_resource(&ioport_resource, &res[0]))
                panic("Request PCI IO resource failed\n");
-        sys->resource[0] = &res[0];
+        pci_add_resource(&sys->resources, &res[0]);
        /*
         * IORESOURCE_MEM
@@ -516,9 +516,8 @@ static int __init pci_setup(struct pci_sys_data *sys)
        res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
        if (request_resource(&iomem_resource, &res[1]))
                panic("Request PCI Memory resource failed\n");
-        sys->resource[1] = &res[1];
+        pci_add_resource(&sys->resources, &res[1]);
-        sys->resource[2] = NULL;
        sys->io_offset = 0;
        return 1;
@@ -579,9 +578,11 @@ struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys
        struct pci_bus *bus;
        if (nr == 0) {
-                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+                bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
+                                        &sys->resources);
        } else if (nr == 1 && !orion5x_pci_disabled) {
-                bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
+                bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys,
+                                        &sys->resources);
        } else {
                bus = NULL;
                BUG();
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index ebd6767d8e8..292038fc59f 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -175,4 +175,5 @@ MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index 05db2d336b0..c44eabaabc1 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -187,4 +187,5 @@ MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index e47fa0578ae..96438b6b202 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -311,4 +311,5 @@ MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 64317251ec0..2c5fab00d20 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -128,4 +128,5 @@ MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 29f1526f7b7..632a861ef82 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -364,4 +364,5 @@ MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 31e51f9b4b6..5d640874558 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -178,7 +178,7 @@ static struct hw_pci qnap_ts209_pci __initdata = {
 static int __init qnap_ts209_pci_init(void)
 {
-        if (machine_is_ts_x09())
+        if (machine_is_ts209())
                pci_common_init(&qnap_ts209_pci);
        return 0;
@@ -329,4 +329,5 @@ MACHINE_START(TS209, "QNAP TS-109/TS-209")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 0fbcc14e09d..4e6ff759cd3 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -318,4 +318,5 @@ MACHINE_START(TS409, "QNAP TS-409")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index b35e2005a34..c96f37472ed 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -627,4 +627,5 @@ MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
        .init_early     = orion5x_init_early,
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index b8be7d8d0cf..078c03f7cd5 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -179,4 +179,5 @@ MACHINE_START(WNR854T, "Netgear WNR854T")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index faf81a03936..46a9778171c 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -267,4 +267,5 @@ MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
        .init_irq       = orion5x_init_irq,
        .timer          = &orion5x_timer,
        .fixup          = tag_fixup_mem32,
+        .restart        = orion5x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-picoxcell/Makefile b/arch/arm/mach-picoxcell/Makefile
index c550b636348..e5ec4a8d9bc 100644
--- a/arch/arm/mach-picoxcell/Makefile
+++ b/arch/arm/mach-picoxcell/Makefile
@@ -1,3 +1,2 @@
 obj-y   := common.o
 obj-y   += time.o
-obj-y   += io.o
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 34d08347be5..a2e8ae8b582 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -7,23 +7,59 @@
 *
 * All enquiries to support@picochip.com
 */
+#include <linux/delay.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/hardware/vic.h>
+#include <asm/mach/map.h>
 #include <mach/map.h>
 #include <mach/picoxcell_soc.h>
 #include "common.h"
+#define WDT_CTRL_REG_EN_MASK    (1 << 0)
+#define WDT_CTRL_REG_OFFS       (0x00)
+#define WDT_TIMEOUT_REG_OFFS    (0x04)
+static void __iomem *wdt_regs;
+/*
+ * The machine restart method can be called from an atomic context so we won't
+ * be able to ioremap the regs then.
+ */
+static void picoxcell_setup_restart(void)
+{
+        struct device_node *np = of_find_compatible_node(NULL, NULL,
+                                                         "snps,dw-apb-wdg");
+        if (WARN(!np, "unable to setup watchdog restart"))
+                return;
+        wdt_regs = of_iomap(np, 0);
+        WARN(!wdt_regs, "failed to remap watchdog regs");
+}
+static struct map_desc io_map __initdata = {
+        .virtual        = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
+        .pfn            = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
+        .length         = PICOXCELL_PERIPH_LENGTH,
+        .type           = MT_DEVICE,
+};
+static void __init picoxcell_map_io(void)
+{
+        iotable_init(&io_map, 1);
+}
 static void __init picoxcell_init_machine(void)
 {
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+        picoxcell_setup_restart();
 }
 static const char *picoxcell_dt_match[] = {
@@ -33,23 +69,36 @@ static const char *picoxcell_dt_match[] = {
 };
 static const struct of_device_id vic_of_match[] __initconst = {
-        { .compatible = "arm,pl192-vic" },
+        { .compatible = "arm,pl192-vic", .data = vic_of_init, },
        { /* Sentinel */ }
 };
 static void __init picoxcell_init_irq(void)
 {
-        vic_init(IO_ADDRESS(PICOXCELL_VIC0_BASE), 0, ~0, 0);
+        of_irq_init(vic_of_match);
-        vic_init(IO_ADDRESS(PICOXCELL_VIC1_BASE), 32, ~0, 0);
+}
-        irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC0_BASE, 0);
-        irq_domain_generate_simple(vic_of_match, PICOXCELL_VIC1_BASE, 32);
+static void picoxcell_wdt_restart(char mode, const char *cmd)
+{
+        /*
+         * Configure the watchdog to reset with the shortest possible timeout
+         * and give it chance to do the reset.
+         */
+        if (wdt_regs) {
+                writel_relaxed(WDT_CTRL_REG_EN_MASK, wdt_regs + WDT_CTRL_REG_OFFS);
+                writel_relaxed(0, wdt_regs + WDT_TIMEOUT_REG_OFFS);
+                /* No sleeping, possibly atomic. */
+                mdelay(500);
+        }
 }
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
        .map_io         = picoxcell_map_io,
-        .nr_irqs        = ARCH_NR_IRQS,
+        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = picoxcell_init_irq,
+        .handle_irq     = vic_handle_irq,
        .timer          = &picoxcell_timer,
        .init_machine   = picoxcell_init_machine,
        .dt_compat      = picoxcell_dt_match,
+        .restart        = picoxcell_wdt_restart,
 MACHINE_END
diff --git a/arch/arm/mach-picoxcell/common.h b/arch/arm/mach-picoxcell/common.h
index 5263f0fa095..83d55ab956a 100644
--- a/arch/arm/mach-picoxcell/common.h
+++ b/arch/arm/mach-picoxcell/common.h
@@ -13,6 +13,5 @@
 #include <asm/mach/time.h>
 extern struct sys_timer picoxcell_timer;
-extern void picoxcell_map_io(void);
 #endif /* __PICOXCELL_COMMON_H__ */
diff --git a/arch/arm/mach-picoxcell/include/mach/entry-macro.S b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
index a6b09f75d9d..9b505ac00be 100644
--- a/arch/arm/mach-picoxcell/include/mach/entry-macro.S
+++ b/arch/arm/mach-picoxcell/include/mach/entry-macro.S
@@ -9,11 +9,8 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
+        .macro  disable_fiq
-#include <mach/irqs.h>
+        .endm
-#include <mach/map.h>
-#define VA_VIC0         IO_ADDRESS(PICOXCELL_VIC0_BASE)
+        .macro  arch_ret_to_user, tmp1, tmp2
-#define VA_VIC1         IO_ADDRESS(PICOXCELL_VIC1_BASE)
+        .endm
-#include <asm/entry-macro-vic2.S>
diff --git a/arch/arm/mach-picoxcell/include/mach/irqs.h b/arch/arm/mach-picoxcell/include/mach/irqs.h
index 4d13ed97091..59eac1ee282 100644
--- a/arch/arm/mach-picoxcell/include/mach/irqs.h
+++ b/arch/arm/mach-picoxcell/include/mach/irqs.h
@@ -1,8 +1,6 @@
 /*
 * Copyright (c) 2011 Picochip Ltd., Jamie Iles
 *
- * This file contains the hardware definitions of the picoXcell SoC devices.
- *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
@@ -16,10 +14,7 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
-#define ARCH_NR_IRQS                    64
+/* We dynamically allocate our irq_desc's. */
-#define NR_IRQS                         (128 + ARCH_NR_IRQS)
+#define NR_IRQS                         0
-#define IRQ_VIC0_BASE                   0
-#define IRQ_VIC1_BASE                   32
 #endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/memory.h b/arch/arm/mach-picoxcell/include/mach/memory.h
deleted file mode 100644
index 40a8c178f10..00000000000
--- a/arch/arm/mach-picoxcell/include/mach/memory.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty */
diff --git a/arch/arm/mach-picoxcell/include/mach/system.h b/arch/arm/mach-picoxcell/include/mach/system.h
index 67c589b0c1b..1a5d8cb57df 100644
--- a/arch/arm/mach-picoxcell/include/mach/system.h
+++ b/arch/arm/mach-picoxcell/include/mach/system.h
@@ -23,9 +23,4 @@ static inline void arch_idle(void)
        cpu_do_idle();
 }
-static inline void arch_reset(int mode, const char *cmd)
-{
-        /* Watchdog reset to go here. */
-}
 #endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-picoxcell/include/mach/vmalloc.h b/arch/arm/mach-picoxcell/include/mach/vmalloc.h
deleted file mode 100644
index 0216cc4b1f0..00000000000
--- a/arch/arm/mach-picoxcell/include/mach/vmalloc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-picoxcell/io.c b/arch/arm/mach-picoxcell/io.c
deleted file mode 100644
index 39e9b9e8cc3..00000000000
--- a/arch/arm/mach-picoxcell/io.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2011 Picochip Ltd., Jamie Iles
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * All enquiries to support@picochip.com
- */
-#include <linux/io.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <asm/mach/map.h>
-#include <mach/map.h>
-#include <mach/picoxcell_soc.h>
-#include "common.h"
-void __init picoxcell_map_io(void)
-{
-        struct map_desc io_map = {
-                .virtual        = PHYS_TO_IO(PICOXCELL_PERIPH_BASE),
-                .pfn            = __phys_to_pfn(PICOXCELL_PERIPH_BASE),
-                .length         = PICOXCELL_PERIPH_LENGTH,
-                .type           = MT_DEVICE,
-        };
-        iotable_init(&io_map, 1);
-}
diff --git a/arch/arm/mach-picoxcell/time.c b/arch/arm/mach-picoxcell/time.c
index 90a554ff449..2ecba6743b8 100644
--- a/arch/arm/mach-picoxcell/time.c
+++ b/arch/arm/mach-picoxcell/time.c
@@ -11,7 +11,6 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
-#include <linux/sched.h>
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
@@ -66,21 +65,11 @@ static void picoxcell_add_clocksource(struct device_node *source_timer)
        dw_apb_clocksource_register(cs);
 }
-static DEFINE_CLOCK_DATA(cd);
 static void __iomem *sched_io_base;
-unsigned long long notrace sched_clock(void)
+static u32 picoxcell_read_sched_clock(void)
 {
-        cycle_t cyc = sched_io_base ? __raw_readl(sched_io_base) : 0;
+        return __raw_readl(sched_io_base);
-        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-static void notrace picoxcell_update_sched_clock(void)
-{
-        cycle_t cyc = sched_io_base ? __raw_readl(sched_io_base) : 0;
-        update_sched_clock(&cd, cyc, (u32)~0);
 }
 static const struct of_device_id picoxcell_rtc_ids[] __initconst = {
@@ -100,7 +89,7 @@ static void picoxcell_init_sched_clock(void)
        timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
        of_node_put(sched_timer);
-        init_sched_clock(&cd, picoxcell_update_sched_clock, 32, rate);
+        setup_sched_clock(picoxcell_read_sched_clock, 32, rate);
 }
 static const struct of_device_id picoxcell_timer_ids[] __initconst = {
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index cdb95e726f5..4cfb40b2ec1 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -260,6 +260,11 @@ void __init pnx4008_map_io(void)
        iotable_init(pnx4008_io_desc, ARRAY_SIZE(pnx4008_io_desc));
 }
+static void pnx4008_restart(char mode, const char *cmd)
+{
+        soft_restart(0);
+}
 extern struct sys_timer pnx4008_timer;
 MACHINE_START(PNX4008, "Philips PNX4008")
@@ -269,4 +274,5 @@ MACHINE_START(PNX4008, "Philips PNX4008")
        .init_irq               = pnx4008_init_irq,
        .init_machine           = pnx4008_init,
        .timer                  = &pnx4008_timer,
+        .restart                = pnx4008_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h
index 5dda2bb55f8..60cfe718809 100644
--- a/arch/arm/mach-pnx4008/include/mach/system.h
+++ b/arch/arm/mach-pnx4008/include/mach/system.h
@@ -21,18 +21,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
 static void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        cpu_reset(0);
-}
 #endif
diff --git a/arch/arm/mach-pnx4008/include/mach/vmalloc.h b/arch/arm/mach-pnx4008/include/mach/vmalloc.h
deleted file mode 100644
index 184913c7114..00000000000
--- a/arch/arm/mach-pnx4008/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/vmalloc.h
- *
- * Author: Vitaly Wool <source@mvista.com>
- *
- * 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-/*
- * Just any arbitrary offset to the start of the vmalloc VM area: the
- * current 8MB value just means that there will be a 8MB "hole" after the
- * physical memory until the kernel virtual memory starts.  That means that
- * any out-of-bounds memory accesses will hopefully be caught.
- * The vmalloc() routines leaves a hole of 4kB between each vmalloced
- * area for the same reason. ;)
- */
-#define VMALLOC_END       0xd0000000UL
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
index 83e5d212811..b28a930d4f8 100644
--- a/arch/arm/mach-prima2/common.h
+++ b/arch/arm/mach-prima2/common.h
@@ -16,6 +16,7 @@ extern struct sys_timer sirfsoc_timer;
 extern void __init sirfsoc_of_irq_init(void);
 extern void __init sirfsoc_of_clk_init(void);
+extern void sirfsoc_restart(char, const char *);
 #ifndef CONFIG_DEBUG_LL
 static inline void sirfsoc_map_lluart(void)  {}
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h
index 66b1ae2e553..6f243532570 100644
--- a/arch/arm/mach-prima2/include/mach/map.h
+++ b/arch/arm/mach-prima2/include/mach/map.h
@@ -9,8 +9,10 @@
 #ifndef __MACH_PRIMA2_MAP_H__
 #define __MACH_PRIMA2_MAP_H__
-#include <mach/vmalloc.h>
+#include <linux/const.h>
-#define SIRFSOC_VA(x)                   (VMALLOC_END + ((x) & 0x00FFF000))
+#define SIRFSOC_VA_BASE         _AC(0xFEC00000, UL)
+#define SIRFSOC_VA(x)           (SIRFSOC_VA_BASE + ((x) & 0x00FFF000))
 #endif
diff --git a/arch/arm/mach-prima2/include/mach/system.h b/arch/arm/mach-prima2/include/mach/system.h
index 0dbd257ad16..2c7d2a9d0c9 100644
--- a/arch/arm/mach-prima2/include/mach/system.h
+++ b/arch/arm/mach-prima2/include/mach/system.h
@@ -9,21 +9,9 @@
 #ifndef __MACH_SYSTEM_H__
 #define __MACH_SYSTEM_H__
-#include <linux/bitops.h>
-#include <mach/hardware.h>
-#define SIRFSOC_SYS_RST_BIT  BIT(31)
-extern void __iomem *sirfsoc_rstc_base;
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
-}
 #endif
diff --git a/arch/arm/mach-prima2/include/mach/vmalloc.h b/arch/arm/mach-prima2/include/mach/vmalloc.h
deleted file mode 100644
index c9f90fec78e..00000000000
--- a/arch/arm/mach-prima2/include/mach/vmalloc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/ach-prima2/include/mach/vmalloc.h
- *
- * Copyright (c) 2010 – 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#ifndef __MACH_VMALLOC_H
-#define __MACH_VMALLOC_H
-#include <linux/const.h>
-#define VMALLOC_END    _AC(0xFEC00000, UL)
-#endif
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
index a12b689a870..02b9c05ff99 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/prima2.c
@@ -40,4 +40,5 @@ MACHINE_START(PRIMA2_EVB, "prima2cb")
        .dma_zone_size  = SZ_256M,
        .init_machine   = sirfsoc_mach_init,
        .dt_compat      = prima2cb_dt_match,
+        .restart        = sirfsoc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 492cfa8d261..762adb73ab7 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -68,3 +68,10 @@ int sirfsoc_reset_device(struct device *dev)
        return 0;
 }
+#define SIRFSOC_SYS_RST_BIT  BIT(31)
+void sirfsoc_restart(char mode, const char *cmd)
+{
+        writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
+}
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c
index 4cb069fd9af..ccdac4b6a46 100644
--- a/arch/arm/mach-pxa/am200epd.c
+++ b/arch/arm/mach-pxa/am200epd.c
@@ -138,7 +138,7 @@ static void am200_cleanup(struct metronomefb_par *par)
 {
        int i;
-        free_irq(IRQ_GPIO(RDY_GPIO_PIN), par);
+        free_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), par);
        for (i = 0; i < ARRAY_SIZE(gpios); i++)
                gpio_free(gpios[i]);
@@ -292,7 +292,7 @@ static int am200_setup_irq(struct fb_info *info)
 {
        int ret;
-        ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am200_handle_irq,
+        ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am200_handle_irq,
                                IRQF_DISABLED|IRQF_TRIGGER_FALLING,
                                "AM200", info->par);
        if (ret)
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c
index fa8bad235d9..76c4b949403 100644
--- a/arch/arm/mach-pxa/am300epd.c
+++ b/arch/arm/mach-pxa/am300epd.c
@@ -176,7 +176,7 @@ static void am300_cleanup(struct broadsheetfb_par *par)
 {
        int i;
-        free_irq(IRQ_GPIO(RDY_GPIO_PIN), par);
+        free_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), par);
        for (i = 0; i < ARRAY_SIZE(gpios); i++)
                gpio_free(gpios[i]);
@@ -240,7 +240,7 @@ static int am300_setup_irq(struct fb_info *info)
        int ret;
        struct broadsheetfb_par *par = info->par;
-        ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am300_handle_irq,
+        ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am300_handle_irq,
                                IRQF_DISABLED|IRQF_TRIGGER_RISING,
                                "AM300", par);
        if (ret)
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 4b81f59a4cb..c35456f02ac 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -13,6 +13,7 @@
 *  published by the Free Software Foundation.
 */
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
@@ -179,7 +180,7 @@ static unsigned long balloon3_ac97_pin_config[] __initdata = {
 };
 static struct ucb1400_pdata vpac270_ucb1400_pdata = {
-        .irq            = IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ),
+        .irq            = PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ),
 };
@@ -829,4 +830,5 @@ MACHINE_START(BALLOON3, "Balloon3")
        .timer          = &pxa_timer,
        .init_machine   = balloon3_init,
        .atag_offset    = 0x100,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index 4efc16d39c7..c91727d1fe0 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -50,8 +50,8 @@ static struct resource capc7117_ide_resources[] = {
               .flags = IORESOURCE_MEM
        },
        [2] = {
-               .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)),
+               .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO76)),
-               .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO76)),
+               .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO76)),
               .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING
        }
 };
@@ -80,7 +80,7 @@ static void __init capc7117_ide_init(void)
 static struct plat_serial8250_port ti16c752_platform_data[] = {
        [0] = {
               .mapbase = 0x14000000,
-               .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO78)),
+               .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO78)),
               .irqflags = IRQF_TRIGGER_RISING,
               .flags = TI16C752_FLAGS,
               .iotype = UPIO_MEM,
@@ -89,7 +89,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = {
        },
        [1] = {
               .mapbase = 0x14000040,
-               .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO79)),
+               .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO79)),
               .irqflags = IRQF_TRIGGER_RISING,
               .flags = TI16C752_FLAGS,
               .iotype = UPIO_MEM,
@@ -98,7 +98,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = {
        },
        [2] = {
               .mapbase = 0x14000080,
-               .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO80)),
+               .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO80)),
               .irqflags = IRQF_TRIGGER_RISING,
               .flags = TI16C752_FLAGS,
               .iotype = UPIO_MEM,
@@ -107,7 +107,7 @@ static struct plat_serial8250_port ti16c752_platform_data[] = {
        },
        [3] = {
               .mapbase = 0x140000c0,
-               .irq = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO81)),
+               .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO81)),
               .irqflags = IRQF_TRIGGER_RISING,
               .flags = TI16C752_FLAGS,
               .iotype = UPIO_MEM,
@@ -153,5 +153,6 @@ MACHINE_START(CAPC7117,
        .init_irq = pxa3xx_init_irq,
        .handle_irq = pxa3xx_handle_irq,
        .timer = &pxa_timer,
-        .init_machine = capc7117_init
+        .init_machine = capc7117_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
index 13518a70539..431ef56700c 100644
--- a/arch/arm/mach-pxa/cm-x270.c
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -33,7 +33,7 @@
 /* GPIO IRQ usage */
 #define GPIO83_MMC_IRQ          (83)
-#define CMX270_MMC_IRQ          IRQ_GPIO(GPIO83_MMC_IRQ)
+#define CMX270_MMC_IRQ          PXA_GPIO_TO_IRQ(GPIO83_MMC_IRQ)
 /* MMC power enable */
 #define GPIO105_MMC_POWER       (105)
@@ -380,7 +380,7 @@ static struct spi_board_info cm_x270_spi_devices[] __initdata = {
                .modalias               = "libertas_spi",
                .max_speed_hz           = 13000000,
                .bus_num                = 2,
-                .irq                    = gpio_to_irq(95),
+                .irq                    = PXA_GPIO_TO_IRQ(95),
                .chip_select            = 0,
                .controller_data        = &cm_x270_libertas_chip,
                .platform_data          = &cm_x270_libertas_pdata,
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index f2e4190080c..8fa4ad27edf 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -58,8 +58,8 @@ extern void cmx270_init(void);
 #define CMX255_GPIO_IT8152_IRQ  (0)
 #define CMX270_GPIO_IT8152_IRQ  (22)
-#define CMX255_ETHIRQ           IRQ_GPIO(GPIO22_ETHIRQ)
+#define CMX255_ETHIRQ           PXA_GPIO_TO_IRQ(GPIO22_ETHIRQ)
-#define CMX270_ETHIRQ           IRQ_GPIO(GPIO10_ETHIRQ)
+#define CMX270_ETHIRQ           PXA_GPIO_TO_IRQ(GPIO10_ETHIRQ)
 #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
 static struct resource cmx255_dm9000_resource[] = {
@@ -524,4 +524,5 @@ MACHINE_START(ARMCORE, "Compulab CM-X2XX")
 #ifdef CONFIG_PCI
        .dma_zone_size  = SZ_64M,
 #endif
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index e096bba8fd5..4b981b82d2a 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -64,7 +64,7 @@
 #define GPIO82_MMC_IRQ          (82)
 #define GPIO85_MMC_WP           (85)
-#define CM_X300_MMC_IRQ         IRQ_GPIO(GPIO82_MMC_IRQ)
+#define CM_X300_MMC_IRQ         PXA_GPIO_TO_IRQ(GPIO82_MMC_IRQ)
 #define GPIO95_RTC_CS           (95)
 #define GPIO96_RTC_WR           (96)
@@ -229,8 +229,8 @@ static struct resource dm9000_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [2] = {
-                .start  = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)),
+                .start  = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO99)),
-                .end    = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO99)),
+                .end    = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO99)),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        }
 };
@@ -858,4 +858,5 @@ MACHINE_START(CM_X300, "CM-X300 module")
        .timer          = &pxa_timer,
        .init_machine   = cm_x300_init,
        .fixup          = cm_x300_fixup,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c
index 80538b8806e..248804bb2c9 100644
--- a/arch/arm/mach-pxa/colibri-pxa270-income.c
+++ b/arch/arm/mach-pxa/colibri-pxa270-income.c
@@ -183,7 +183,7 @@ static inline void income_lcd_init(void) {}
 /******************************************************************************
 * Backlight
 ******************************************************************************/
-#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM__MODULE)
+#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
 static struct platform_pwm_backlight_data income_backlight_data = {
        .pwm_id         = 0,
        .max_brightness = 0x3ff,
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 05bfa1b1c00..29d5d541f60 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -218,8 +218,8 @@ static struct resource colibri_pxa270_dm9000_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
-                .start  = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO114_COLIBRI_PXA270_ETH_IRQ),
-                .end    = gpio_to_irq(GPIO114_COLIBRI_PXA270_ETH_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO114_COLIBRI_PXA270_ETH_IRQ),
                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
        },
 };
@@ -249,7 +249,7 @@ static pxa2xx_audio_ops_t colibri_pxa270_ac97_pdata = {
 };
 static struct ucb1400_pdata colibri_pxa270_ucb1400_pdata = {
-        .irq            = gpio_to_irq(GPIO113_COLIBRI_PXA270_TS_IRQ),
+        .irq            = PXA_GPIO_TO_IRQ(GPIO113_COLIBRI_PXA270_TS_IRQ),
 };
 static struct platform_device colibri_pxa270_ucb1400_device = {
@@ -313,6 +313,7 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
@@ -322,5 +323,6 @@ MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index c825e8bf2db..0846d210cb0 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -78,8 +78,8 @@ static struct resource colibri_asix_resource[] = {
                .flags = IORESOURCE_MEM,
        },
        [1] = {
-                .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
+                .start = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
-                .end   = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
+                .end   = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
        }
 };
@@ -189,5 +189,6 @@ MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index d23b92b8048..6ad3359063a 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -115,8 +115,8 @@ static struct resource colibri_asix_resource[] = {
                .flags = IORESOURCE_MEM,
        },
        [1] = {
-                .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
+                .start = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
-                .end   = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO),
+                .end   = PXA_GPIO_TO_IRQ(COLIBRI_ETH_IRQ_GPIO),
                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
        }
 };
@@ -259,5 +259,6 @@ MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 549468d088b..11f1e735966 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -436,6 +436,14 @@ static struct platform_device corgiled_device = {
 };
 /*
+ * Corgi Audio
+ */
+static struct platform_device corgi_audio_device = {
+        .name   = "corgi-audio",
+        .id     = -1,
+};
+/*
 * MMC/SD Device
 *
 * The card detect interrupt isn't debounced so we delay it by 250ms
@@ -531,7 +539,7 @@ static struct spi_board_info corgi_spi_devices[] = {
                .chip_select    = 0,
                .platform_data  = &corgi_ads7846_info,
                .controller_data= &corgi_ads7846_chip,
-                .irq            = gpio_to_irq(CORGI_GPIO_TP_INT),
+                .irq            = PXA_GPIO_TO_IRQ(CORGI_GPIO_TP_INT),
        }, {
                .modalias       = "corgi-lcd",
                .max_speed_hz   = 50000,
@@ -641,6 +649,7 @@ static struct platform_device *devices[] __initdata = {
        &corgifb_device,
        &corgikbd_device,
        &corgiled_device,
+        &corgi_audio_device,
        &sharpsl_nand_device,
        &sharpsl_rom_device,
 };
@@ -655,7 +664,7 @@ static void corgi_poweroff(void)
                /* Green LED off tells the bootloader to halt */
                gpio_set_value(CORGI_GPIO_LED_GREEN, 0);
-        arm_machine_restart('h', NULL);
+        pxa_restart('h', NULL);
 }
 static void corgi_restart(char mode, const char *cmd)
@@ -664,13 +673,12 @@ static void corgi_restart(char mode, const char *cmd)
                /* Green LED on tells the bootloader to reboot */
                gpio_set_value(CORGI_GPIO_LED_GREEN, 1);
-        arm_machine_restart('h', cmd);
+        pxa_restart('h', cmd);
 }
 static void __init corgi_init(void)
 {
        pm_power_off = corgi_poweroff;
-        arm_pm_restart = corgi_restart;
        /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
        PCFR |= PCFR_OPDE;
@@ -726,6 +734,7 @@ MACHINE_START(CORGI, "SHARP Corgi")
        .handle_irq     = pxa25x_handle_irq,
        .init_machine   = corgi_init,
        .timer          = &pxa_timer,
+        .restart        = corgi_restart,
 MACHINE_END
 #endif
@@ -737,6 +746,7 @@ MACHINE_START(SHEPHERD, "SHARP Shepherd")
        .handle_irq     = pxa25x_handle_irq,
        .init_machine   = corgi_init,
        .timer          = &pxa_timer,
+        .restart        = corgi_restart,
 MACHINE_END
 #endif
@@ -748,6 +758,7 @@ MACHINE_START(HUSKY, "SHARP Husky")
        .handle_irq     = pxa25x_handle_irq,
        .init_machine   = corgi_init,
        .timer          = &pxa_timer,
+        .restart        = corgi_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 29034778bfd..39e265cfc86 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/apm-emulation.h>
@@ -40,7 +41,9 @@ static struct gpio charger_gpios[] = {
        { CORGI_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" },
        { CORGI_GPIO_CHRG_ON,     GPIOF_OUT_INIT_LOW, "Charger On" },
        { CORGI_GPIO_CHRG_UKN,    GPIOF_OUT_INIT_LOW, "Charger Unknown" },
+        { CORGI_GPIO_AC_IN,       GPIOF_IN, "Charger Detection" },
        { CORGI_GPIO_KEY_INT,     GPIOF_IN, "Key Interrupt" },
+        { CORGI_GPIO_WAKEUP,      GPIOF_IN, "System wakeup notification" },
 };
 static void corgi_charger_init(void)
@@ -90,7 +93,12 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm)
 {
        int is_resume = 0;
-        dev_dbg(sharpsl_pm.dev, "GPLR0 = %x,%x\n", GPLR0, PEDR);
+        dev_dbg(sharpsl_pm.dev, "PEDR = %x, GPIO_AC_IN = %d, "
+                "GPIO_CHRG_FULL = %d, GPIO_KEY_INT = %d, GPIO_WAKEUP = %d\n",
+                PEDR, gpio_get_value(CORGI_GPIO_AC_IN),
+                gpio_get_value(CORGI_GPIO_CHRG_FULL),
+                gpio_get_value(CORGI_GPIO_KEY_INT),
+                gpio_get_value(CORGI_GPIO_WAKEUP));
        if ((PEDR & GPIO_bit(CORGI_GPIO_AC_IN))) {
                if (sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_ACIN)) {
@@ -124,14 +132,21 @@ static int corgi_should_wakeup(unsigned int resume_on_alarm)
 static unsigned long corgi_charger_wakeup(void)
 {
-        return ~GPLR0 & ( GPIO_bit(CORGI_GPIO_AC_IN) | GPIO_bit(CORGI_GPIO_KEY_INT) | GPIO_bit(CORGI_GPIO_WAKEUP) );
+        unsigned long ret;
+        ret = (!gpio_get_value(CORGI_GPIO_AC_IN) << GPIO_bit(CORGI_GPIO_AC_IN))
+                | (!gpio_get_value(CORGI_GPIO_KEY_INT)
+                << GPIO_bit(CORGI_GPIO_KEY_INT))
+                | (!gpio_get_value(CORGI_GPIO_WAKEUP)
+                << GPIO_bit(CORGI_GPIO_WAKEUP));
+        return ret;
 }
 unsigned long corgipm_read_devdata(int type)
 {
        switch(type) {
        case SHARPSL_STATUS_ACIN:
-                return ((GPLR(CORGI_GPIO_AC_IN) & GPIO_bit(CORGI_GPIO_AC_IN)) != 0);
+                return !gpio_get_value(CORGI_GPIO_AC_IN);
        case SHARPSL_STATUS_LOCK:
                return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock);
        case SHARPSL_STATUS_CHRGFULL:
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 5e2cf39e9e4..fb5a51d834e 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -278,4 +278,5 @@ MACHINE_START(CSB726, "Cogent CSB726")
        .handle_irq       = pxa27x_handle_irq,
        .init_machine   = csb726_init,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 2e0425404de..18fd177073f 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -415,9 +415,29 @@ static struct resource pxa_rtc_resources[] = {
        },
 };
+static struct resource sa1100_rtc_resources[] = {
+        [0] = {
+                .start  = 0x40900000,
+                .end    = 0x409000ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_RTC1Hz,
+                .end    = IRQ_RTC1Hz,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_RTCAlrm,
+                .end    = IRQ_RTCAlrm,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
 struct platform_device sa1100_device_rtc = {
        .name           = "sa1100-rtc",
        .id             = -1,
+        .num_resources  = ARRAY_SIZE(sa1100_rtc_resources),
+        .resource       = sa1100_rtc_resources,
 };
 struct platform_device pxa_device_rtc = {
@@ -1051,6 +1071,36 @@ struct platform_device pxa3xx_device_ssp4 = {
 };
 #endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
+struct resource pxa_resource_gpio[] = {
+        {
+                .start  = 0x40e00000,
+                .end    = 0x40e0ffff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_GPIO0,
+                .end    = IRQ_GPIO0,
+                .name   = "gpio0",
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = IRQ_GPIO1,
+                .end    = IRQ_GPIO1,
+                .name   = "gpio1",
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = IRQ_GPIO_2_x,
+                .end    = IRQ_GPIO_2_x,
+                .name   = "gpio_mux",
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct platform_device pxa_device_gpio = {
+        .name           = "pxa-gpio",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa_resource_gpio),
+        .resource       = pxa_resource_gpio,
+};
 /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
 * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
 void __init pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info)
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 2fd5a8b3575..1475db10725 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -16,6 +16,7 @@ extern struct platform_device pxa_device_ficp;
 extern struct platform_device sa1100_device_rtc;
 extern struct platform_device pxa_device_rtc;
 extern struct platform_device pxa_device_ac97;
+extern struct platform_device pxa_device_gpio;
 extern struct platform_device pxa27x_device_i2c_power;
 extern struct platform_device pxa27x_device_ohci;
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 94acc0b01dd..d80c0ba9a09 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -70,7 +70,7 @@
 /* common  GPIOs */
 #define GPIO11_NAND_CS          (11)
 #define GPIO41_ETHIRQ           (41)
-#define EM_X270_ETHIRQ          IRQ_GPIO(GPIO41_ETHIRQ)
+#define EM_X270_ETHIRQ          PXA_GPIO_TO_IRQ(GPIO41_ETHIRQ)
 #define GPIO115_WLAN_PWEN       (115)
 #define GPIO19_WLAN_STRAP       (19)
 #define GPIO9_USB_VBUS_EN       (9)
@@ -805,7 +805,7 @@ static struct spi_board_info em_x270_spi_devices[] __initdata = {
                .modalias               = "libertas_spi",
                .max_speed_hz           = 13000000,
                .bus_num                = 2,
-                .irq                    = IRQ_GPIO(116),
+                .irq                    = PXA_GPIO_TO_IRQ(116),
                .chip_select            = 0,
                .controller_data        = &em_x270_libertas_chip,
                .platform_data          = &em_x270_libertas_pdata,
@@ -1203,7 +1203,7 @@ static struct da903x_platform_data em_x270_da9030_info = {
 static struct i2c_board_info em_x270_i2c_pmic_info = {
        I2C_BOARD_INFO("da9030", 0x49),
-        .irq = IRQ_GPIO(0),
+        .irq = PXA_GPIO_TO_IRQ(0),
        .platform_data = &em_x270_da9030_info,
 };
@@ -1305,6 +1305,7 @@ MACHINE_START(EM_X270, "Compulab EM-X270")
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = em_x270_init,
+        .restart        = pxa_restart,
 MACHINE_END
 MACHINE_START(EXEDA, "Compulab eXeda")
@@ -1314,4 +1315,5 @@ MACHINE_START(EXEDA, "Compulab eXeda")
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = em_x270_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index d82b7aa3c09..4cb2391a782 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -119,8 +119,8 @@ struct resource eseries_tmio_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO_ESERIES_TMIO_IRQ),
-                .end    = IRQ_GPIO(GPIO_ESERIES_TMIO_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO_ESERIES_TMIO_IRQ),
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -196,6 +196,7 @@ MACHINE_START(E330, "Toshiba e330")
        .fixup          = eseries_fixup,
        .init_machine   = e330_init,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -246,6 +247,7 @@ MACHINE_START(E350, "Toshiba e350")
        .fixup          = eseries_fixup,
        .init_machine   = e350_init,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -369,6 +371,7 @@ MACHINE_START(E400, "Toshiba e400")
        .fixup          = eseries_fixup,
        .init_machine   = e400_init,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -525,12 +528,18 @@ static struct platform_device e740_t7l66xb_device = {
        .resource      = eseries_tmio_resources,
 };
+static struct platform_device e740_audio_device = {
+        .name           = "e740-audio",
+        .id             = -1,
+};
 /* ----------------------------------------------------------------------- */
 static struct platform_device *e740_devices[] __initdata = {
        &e740_fb_device,
        &e740_t7l66xb_device,
        &e7xx_gpio_vbus,
+        &e740_audio_device,
 };
 static void __init e740_init(void)
@@ -558,6 +567,7 @@ MACHINE_START(E740, "Toshiba e740")
        .fixup          = eseries_fixup,
        .init_machine   = e740_init,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -718,12 +728,18 @@ static struct platform_device e750_tc6393xb_device = {
        .resource      = eseries_tmio_resources,
 };
+static struct platform_device e750_audio_device = {
+        .name           = "e750-audio",
+        .id             = -1,
+};
 /* ------------------------------------------------------------- */
 static struct platform_device *e750_devices[] __initdata = {
        &e750_fb_device,
        &e750_tc6393xb_device,
        &e7xx_gpio_vbus,
+        &e750_audio_device,
 };
 static void __init e750_init(void)
@@ -750,6 +766,7 @@ MACHINE_START(E750, "Toshiba e750")
        .fixup          = eseries_fixup,
        .init_machine   = e750_init,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -924,12 +941,18 @@ static struct platform_device e800_tc6393xb_device = {
        .resource      = eseries_tmio_resources,
 };
+static struct platform_device e800_audio_device = {
+        .name           = "e800-audio",
+        .id             = -1,
+};
 /* ----------------------------------------------------------------------- */
 static struct platform_device *e800_devices[] __initdata = {
        &e800_fb_device,
        &e800_tc6393xb_device,
        &e800_gpio_vbus,
+        &e800_audio_device,
 };
 static void __init e800_init(void)
@@ -955,5 +978,6 @@ MACHINE_START(E800, "Toshiba e800")
        .fixup          = eseries_fixup,
        .init_machine   = e800_init,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 8308eee5a92..15ab2533667 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -804,6 +804,7 @@ MACHINE_START(EZX_A780, "Motorola EZX A780")
        .handle_irq       = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = a780_init,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -870,6 +871,7 @@ MACHINE_START(EZX_E680, "Motorola EZX E680")
        .handle_irq       = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = e680_init,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -936,6 +938,7 @@ MACHINE_START(EZX_A1200, "Motorola EZX A1200")
        .handle_irq       = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = a1200_init,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -1127,6 +1130,7 @@ MACHINE_START(EZX_A910, "Motorola EZX A910")
        .handle_irq       = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = a910_init,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -1193,6 +1197,7 @@ MACHINE_START(EZX_E6, "Motorola EZX E6")
        .handle_irq       = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = e6_init,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -1233,5 +1238,6 @@ MACHINE_START(EZX_E2, "Motorola EZX E2")
        .handle_irq       = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = e2_init,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 92a2e85ab02..0d729e6619d 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -57,3 +57,5 @@ void __init pxa_set_ffuart_info(void *info);
 void __init pxa_set_btuart_info(void *info);
 void __init pxa_set_stuart_info(void *info);
 void __init pxa_set_hwuart_info(void *info);
+void pxa_restart(char, const char *);
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index ffdd70dad32..ac3b1cef475 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -239,4 +239,5 @@ MACHINE_START(GUMSTIX, "Gumstix")
        .handle_irq     = pxa25x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = gumstix_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index 4b5e110640b..fde6b4c873c 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -209,4 +209,5 @@ MACHINE_START(H5400, "HP iPAQ H5000")
        .handle_irq = pxa25x_handle_irq,
        .timer = &pxa_timer,
        .init_machine = h5000_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index f2c32457084..26d069a9f90 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -164,4 +164,5 @@ MACHINE_START(HIMALAYA, "HTC Himalaya")
        .handle_irq = pxa25x_handle_irq,
        .init_machine = himalaya_init,
        .timer = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 6f6368ece9b..fb9b62dcf4c 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -252,8 +252,8 @@ static struct resource asic3_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ),
-                .end    = gpio_to_irq(GPIO12_HX4700_ASIC3_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO12_HX4700_ASIC3_IRQ),
                .flags  = IORESOURCE_IRQ,
        },
        /* SD part */
@@ -263,8 +263,8 @@ static struct resource asic3_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [3] = {
-                .start  = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
-                .end    = gpio_to_irq(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO66_HX4700_ASIC3_nSDIO_IRQ),
                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -587,7 +587,7 @@ static struct spi_board_info tsc2046_board_info[] __initdata = {
                .modalias        = "ads7846",
                .bus_num         = 2,
                .max_speed_hz    = 2600000, /* 100 kHz sample rate */
-                .irq             = gpio_to_irq(GPIO58_HX4700_TSC2046_nPENIRQ),
+                .irq             = PXA_GPIO_TO_IRQ(GPIO58_HX4700_TSC2046_nPENIRQ),
                .platform_data   = &tsc2046_info,
                .controller_data = &tsc2046_chip,
        },
@@ -635,15 +635,15 @@ static struct resource power_supply_resources[] = {
                .name  = "ac",
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
                         IORESOURCE_IRQ_LOWEDGE,
-                .start = gpio_to_irq(GPIOD9_nAC_IN),
+                .start = PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN),
-                .end   = gpio_to_irq(GPIOD9_nAC_IN),
+                .end   = PXA_GPIO_TO_IRQ(GPIOD9_nAC_IN),
        },
        [1] = {
                .name  = "usb",
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
                         IORESOURCE_IRQ_LOWEDGE,
-                .start = gpio_to_irq(GPIOD14_nUSBC_DETECT),
+                .start = PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT),
-                .end   = gpio_to_irq(GPIOD14_nUSBC_DETECT),
+                .end   = PXA_GPIO_TO_IRQ(GPIOD14_nUSBC_DETECT),
        },
 };
@@ -845,4 +845,5 @@ MACHINE_START(H4700, "HP iPAQ HX4700")
        .handle_irq     = pxa27x_handle_irq,
        .init_machine = hx4700_init,
        .timer        = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index f78d5db758d..67400192ed3 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -86,7 +86,7 @@ static struct spi_board_info mcp251x_board_info[] = {
                .chip_select     = 0,
                .platform_data   = &mcp251x_info,
                .controller_data = &mcp251x_chip_info1,
-                .irq             = gpio_to_irq(ICONTROL_MCP251x_nIRQ1)
+                .irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ1)
        },
        {
                .modalias        = "mcp2515",
@@ -95,7 +95,7 @@ static struct spi_board_info mcp251x_board_info[] = {
                .chip_select     = 1,
                .platform_data   = &mcp251x_info,
                .controller_data = &mcp251x_chip_info2,
-                .irq             = gpio_to_irq(ICONTROL_MCP251x_nIRQ2)
+                .irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ2)
        },
        {
                .modalias        = "mcp2515",
@@ -104,7 +104,7 @@ static struct spi_board_info mcp251x_board_info[] = {
                .chip_select     = 0,
                .platform_data   = &mcp251x_info,
                .controller_data = &mcp251x_chip_info3,
-                .irq             = gpio_to_irq(ICONTROL_MCP251x_nIRQ3)
+                .irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ3)
        },
        {
                .modalias        = "mcp2515",
@@ -113,7 +113,7 @@ static struct spi_board_info mcp251x_board_info[] = {
                .chip_select     = 1,
                .platform_data   = &mcp251x_info,
                .controller_data = &mcp251x_chip_info4,
-                .irq             = gpio_to_irq(ICONTROL_MCP251x_nIRQ4)
+                .irq             = PXA_GPIO_TO_IRQ(ICONTROL_MCP251x_nIRQ4)
        }
 };
@@ -196,5 +196,6 @@ MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
-        .init_machine   = icontrol_init
+        .init_machine   = icontrol_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index ddf20e5c376..8af1840e12c 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -75,8 +75,8 @@ static struct resource smc91x_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = IRQ_GPIO(4),
+                .start  = PXA_GPIO_TO_IRQ(4),
-                .end    = IRQ_GPIO(4),
+                .end    = PXA_GPIO_TO_IRQ(4),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        }
 };
@@ -199,4 +199,5 @@ MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
        .handle_irq     = pxa25x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = idp_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index 6d7eab3d086..f02fa1e6ba8 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -172,9 +172,9 @@ enum balloon3_features {
 /* Balloon3 Interrupts */
 #define BALLOON3_IRQ(x)         (IRQ_BOARD_START + (x))
-#define BALLOON3_AUX_NIRQ       IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ)
+#define BALLOON3_AUX_NIRQ       PXA_GPIO_TO_IRQ(BALLOON3_GPIO_AUX_NIRQ)
-#define BALLOON3_CODEC_IRQ      IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
+#define BALLOON3_CODEC_IRQ      PXA_GPIO_TO_IRQ(BALLOON3_GPIO_CODEC_IRQ)
-#define BALLOON3_S0_CD_IRQ      IRQ_GPIO(BALLOON3_GPIO_S0_CD)
+#define BALLOON3_S0_CD_IRQ      PXA_GPIO_TO_IRQ(BALLOON3_GPIO_S0_CD)
 #define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 16)
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index 5dfd1195a5a..f3c3493b468 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -66,18 +66,18 @@
 /*
 * Corgi Interrupts
 */
-#define CORGI_IRQ_GPIO_KEY_INT          IRQ_GPIO(0)
+#define CORGI_IRQ_GPIO_KEY_INT          PXA_GPIO_TO_IRQ(0)
-#define CORGI_IRQ_GPIO_AC_IN            IRQ_GPIO(1)
+#define CORGI_IRQ_GPIO_AC_IN            PXA_GPIO_TO_IRQ(1)
-#define CORGI_IRQ_GPIO_WAKEUP           IRQ_GPIO(3)
+#define CORGI_IRQ_GPIO_WAKEUP           PXA_GPIO_TO_IRQ(3)
-#define CORGI_IRQ_GPIO_AK_INT           IRQ_GPIO(4)
+#define CORGI_IRQ_GPIO_AK_INT           PXA_GPIO_TO_IRQ(4)
-#define CORGI_IRQ_GPIO_TP_INT           IRQ_GPIO(5)
+#define CORGI_IRQ_GPIO_TP_INT           PXA_GPIO_TO_IRQ(5)
-#define CORGI_IRQ_GPIO_nSD_DETECT       IRQ_GPIO(9)
+#define CORGI_IRQ_GPIO_nSD_DETECT       PXA_GPIO_TO_IRQ(9)
-#define CORGI_IRQ_GPIO_nSD_INT          IRQ_GPIO(10)
+#define CORGI_IRQ_GPIO_nSD_INT          PXA_GPIO_TO_IRQ(10)
-#define CORGI_IRQ_GPIO_MAIN_BAT_LOW     IRQ_GPIO(11)
+#define CORGI_IRQ_GPIO_MAIN_BAT_LOW     PXA_GPIO_TO_IRQ(11)
-#define CORGI_IRQ_GPIO_CF_CD            IRQ_GPIO(14)
+#define CORGI_IRQ_GPIO_CF_CD            PXA_GPIO_TO_IRQ(14)
-#define CORGI_IRQ_GPIO_CHRG_FULL        IRQ_GPIO(16)    /* Battery fully charged */
+#define CORGI_IRQ_GPIO_CHRG_FULL        PXA_GPIO_TO_IRQ(16)     /* Battery fully charged */
-#define CORGI_IRQ_GPIO_CF_IRQ           IRQ_GPIO(17)
+#define CORGI_IRQ_GPIO_CF_IRQ           PXA_GPIO_TO_IRQ(17)
-#define CORGI_IRQ_GPIO_KEY_SENSE(a)     IRQ_GPIO(58+(a))        /* Keyboard Sense lines */
+#define CORGI_IRQ_GPIO_KEY_SENSE(a)     PXA_GPIO_TO_IRQ(58+(a)) /* Keyboard Sense lines */
 /*
@@ -98,7 +98,7 @@
                        CORGI_SCP_MIC_BIAS )
 #define CORGI_SCOOP_IO_OUT      ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
-#define CORGI_SCOOP_GPIO_BASE           (NR_BUILTIN_GPIO)
+#define CORGI_SCOOP_GPIO_BASE           (PXA_NR_BUILTIN_GPIO)
 #define CORGI_GPIO_LED_GREEN            (CORGI_SCOOP_GPIO_BASE + 0)
 #define CORGI_GPIO_SWA                  (CORGI_SCOOP_GPIO_BASE + 1)  /* Hinge Switch A */
 #define CORGI_GPIO_SWB                  (CORGI_SCOOP_GPIO_BASE + 2)  /* Hinge Switch B */
diff --git a/arch/arm/mach-pxa/include/mach/csb726.h b/arch/arm/mach-pxa/include/mach/csb726.h
index 747ab1a71f2..2628e7b7211 100644
--- a/arch/arm/mach-pxa/include/mach/csb726.h
+++ b/arch/arm/mach-pxa/include/mach/csb726.h
@@ -19,8 +19,8 @@
 #define CSB726_FLASH_SIZE       (64 * 1024 * 1024)
 #define CSB726_FLASH_uMON       (8 * 1024 * 1024)
-#define CSB726_IRQ_LAN          gpio_to_irq(CSB726_GPIO_IRQ_LAN)
+#define CSB726_IRQ_LAN          PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_LAN)
-#define CSB726_IRQ_SM501        gpio_to_irq(CSB726_GPIO_IRQ_SM501)
+#define CSB726_IRQ_SM501        PXA_GPIO_TO_IRQ(CSB726_GPIO_IRQ_SM501)
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
index a73bc86a3c2..260c0c17692 100644
--- a/arch/arm/mach-pxa/include/mach/entry-macro.S
+++ b/arch/arm/mach-pxa/include/mach/entry-macro.S
@@ -7,45 +7,9 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
                .macro  disable_fiq
                .endm
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
-                mov     \tmp, \tmp, lsr #13
-                and     \tmp, \tmp, #0x7                @ Core G
-                cmp     \tmp, #1
-                bhi     1002f
-                @ Core Generation 1 (PXA25x)
-                mov     \base, #io_p2v(0x40000000)      @ IIR Ctl = 0x40d00000
-                add     \base, \base, #0x00d00000
-                ldr     \irqstat, [\base, #0]           @ ICIP
-                ldr     \irqnr, [\base, #4]             @ ICMR
-                ands    \irqnr, \irqstat, \irqnr
-                beq     1001f
-                rsb     \irqstat, \irqnr, #0
-                and     \irqstat, \irqstat, \irqnr
-                clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #(31 + PXA_IRQ(0))
-                b       1001f
-1002:
-                @ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
-                mrc     p6, 0, \irqstat, c5, c0, 0      @ ICHP
-                tst     \irqstat, #0x80000000
-                beq     1001f
-                bic     \irqstat, \irqstat, #0x80000000
-                mov     \irqnr, \irqstat, lsr #16
-                add     \irqnr, \irqnr, #(PXA_IRQ(0))
-1001:
-                .endm
diff --git a/arch/arm/mach-pxa/include/mach/gpio-pxa.h b/arch/arm/mach-pxa/include/mach/gpio-pxa.h
deleted file mode 100644
index 41b4c93a96c..00000000000
--- a/arch/arm/mach-pxa/include/mach/gpio-pxa.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Written by Philipp Zabel <philipp.zabel@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-#ifndef __MACH_PXA_GPIO_PXA_H
-#define __MACH_PXA_GPIO_PXA_H
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#define GPIO_REGS_VIRT  io_p2v(0x40E00000)
-#define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
-#define GPIO_REG(x)     (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
-/* GPIO Pin Level Registers */
-#define GPLR0           GPIO_REG(BANK_OFF(0) + 0x00)
-#define GPLR1           GPIO_REG(BANK_OFF(1) + 0x00)
-#define GPLR2           GPIO_REG(BANK_OFF(2) + 0x00)
-#define GPLR3           GPIO_REG(BANK_OFF(3) + 0x00)
-/* GPIO Pin Direction Registers */
-#define GPDR0           GPIO_REG(BANK_OFF(0) + 0x0c)
-#define GPDR1           GPIO_REG(BANK_OFF(1) + 0x0c)
-#define GPDR2           GPIO_REG(BANK_OFF(2) + 0x0c)
-#define GPDR3           GPIO_REG(BANK_OFF(3) + 0x0c)
-/* GPIO Pin Output Set Registers */
-#define GPSR0           GPIO_REG(BANK_OFF(0) + 0x18)
-#define GPSR1           GPIO_REG(BANK_OFF(1) + 0x18)
-#define GPSR2           GPIO_REG(BANK_OFF(2) + 0x18)
-#define GPSR3           GPIO_REG(BANK_OFF(3) + 0x18)
-/* GPIO Pin Output Clear Registers */
-#define GPCR0           GPIO_REG(BANK_OFF(0) + 0x24)
-#define GPCR1           GPIO_REG(BANK_OFF(1) + 0x24)
-#define GPCR2           GPIO_REG(BANK_OFF(2) + 0x24)
-#define GPCR3           GPIO_REG(BANK_OFF(3) + 0x24)
-/* GPIO Rising Edge Detect Registers */
-#define GRER0           GPIO_REG(BANK_OFF(0) + 0x30)
-#define GRER1           GPIO_REG(BANK_OFF(1) + 0x30)
-#define GRER2           GPIO_REG(BANK_OFF(2) + 0x30)
-#define GRER3           GPIO_REG(BANK_OFF(3) + 0x30)
-/* GPIO Falling Edge Detect Registers */
-#define GFER0           GPIO_REG(BANK_OFF(0) + 0x3c)
-#define GFER1           GPIO_REG(BANK_OFF(1) + 0x3c)
-#define GFER2           GPIO_REG(BANK_OFF(2) + 0x3c)
-#define GFER3           GPIO_REG(BANK_OFF(3) + 0x3c)
-/* GPIO Edge Detect Status Registers */
-#define GEDR0           GPIO_REG(BANK_OFF(0) + 0x48)
-#define GEDR1           GPIO_REG(BANK_OFF(1) + 0x48)
-#define GEDR2           GPIO_REG(BANK_OFF(2) + 0x48)
-#define GEDR3           GPIO_REG(BANK_OFF(3) + 0x48)
-/* GPIO Alternate Function Select Registers */
-#define GAFR0_L         GPIO_REG(0x0054)
-#define GAFR0_U         GPIO_REG(0x0058)
-#define GAFR1_L         GPIO_REG(0x005C)
-#define GAFR1_U         GPIO_REG(0x0060)
-#define GAFR2_L         GPIO_REG(0x0064)
-#define GAFR2_U         GPIO_REG(0x0068)
-#define GAFR3_L         GPIO_REG(0x006C)
-#define GAFR3_U         GPIO_REG(0x0070)
-/* More handy macros.  The argument is a literal GPIO number. */
-#define GPIO_bit(x)     (1 << ((x) & 0x1f))
-#define GPLR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
-#define GPDR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
-#define GPSR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
-#define GPCR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
-#define GRER(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
-#define GFER(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
-#define GEDR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
-#define GAFR(x)         GPIO_REG(0x54 + (((x) & 0x70) >> 2))
-#define NR_BUILTIN_GPIO         PXA_GPIO_IRQ_NUM
-#define gpio_to_bank(gpio)      ((gpio) >> 5)
-#ifdef CONFIG_CPU_PXA26x
-/* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
- * as well as their Alternate Function value being '1' for GPIO in GAFRx.
- */
-static inline int __gpio_is_inverted(unsigned gpio)
-{
-        return cpu_is_pxa25x() && gpio > 85;
-}
-#else
-static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
-#endif
-/*
- * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
- * function of a GPIO, and GPDRx cannot be altered once configured. It
- * is attributed as "occupied" here (I know this terminology isn't
- * accurate, you are welcome to propose a better one :-)
- */
-static inline int __gpio_is_occupied(unsigned gpio)
-{
-        if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
-                int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
-                int dir = GPDR(gpio) & GPIO_bit(gpio);
-                if (__gpio_is_inverted(gpio))
-                        return af != 1 || dir == 0;
-                else
-                        return af != 0 || dir != 0;
-        } else
-                return GPDR(gpio) & GPIO_bit(gpio);
-}
-#include <plat/gpio-pxa.h>
-#endif /* __MACH_PXA_GPIO_PXA_H */
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h
index 004cade7bb1..0248e433bc9 100644
--- a/arch/arm/mach-pxa/include/mach/gpio.h
+++ b/arch/arm/mach-pxa/include/mach/gpio.h
@@ -25,24 +25,8 @@
 #define __ASM_ARCH_PXA_GPIO_H
 #include <asm-generic/gpio.h>
-/* The defines for the driver are needed for the accelerated accessors */
-#include "gpio-pxa.h"
-#define gpio_to_irq(gpio)       IRQ_GPIO(gpio)
+#include <mach/irqs.h>
+#include <mach/hardware.h>
-static inline int irq_to_gpio(unsigned int irq)
-{
-        int gpio;
-        if (irq == IRQ_GPIO0 || irq == IRQ_GPIO1)
-                return irq - IRQ_GPIO0;
-        gpio = irq - PXA_GPIO_IRQ_BASE;
-        if (gpio >= 2 && gpio < NR_BUILTIN_GPIO)
-                return gpio;
-        return -1;
-}
-#include <plat/gpio.h>
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h
index 9b898680b20..dba14b6503a 100644
--- a/arch/arm/mach-pxa/include/mach/gumstix.h
+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
@@ -24,7 +24,7 @@ has detected a cable insertion; driven low otherwise. */
 #define GPIO_GUMSTIX_USB_GPIOx          41
 /* usb state change */
-#define GUMSTIX_USB_INTR_IRQ            IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn)
+#define GUMSTIX_USB_INTR_IRQ            PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_USB_GPIOn)
 #define GPIO_GUMSTIX_USB_GPIOn_MD       (GPIO_GUMSTIX_USB_GPIOn | GPIO_IN)
 #define GPIO_GUMSTIX_USB_GPIOx_CON_MD   (GPIO_GUMSTIX_USB_GPIOx | GPIO_OUT)
@@ -35,7 +35,7 @@ has detected a cable insertion; driven low otherwise. */
 */
 #define GUMSTIX_GPIO_nSD_WP             22 /* SD Write Protect */
 #define GUMSTIX_GPIO_nSD_DETECT         11 /* MMC/SD Card Detect */
-#define GUMSTIX_IRQ_GPIO_nSD_DETECT     IRQ_GPIO(GUMSTIX_GPIO_nSD_DETECT)
+#define GUMSTIX_IRQ_GPIO_nSD_DETECT     PXA_GPIO_TO_IRQ(GUMSTIX_GPIO_nSD_DETECT)
 /*
 * SMC Ethernet definitions
@@ -49,10 +49,10 @@ has detected a cable insertion; driven low otherwise. */
 #define GPIO_GUMSTIX_ETH0               36
 #define GPIO_GUMSTIX_ETH0_MD            (GPIO_GUMSTIX_ETH0 | GPIO_IN)
-#define GUMSTIX_ETH0_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH0)
+#define GUMSTIX_ETH0_IRQ                PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH0)
 #define GPIO_GUMSTIX_ETH1               27
 #define GPIO_GUMSTIX_ETH1_MD            (GPIO_GUMSTIX_ETH1 | GPIO_IN)
-#define GUMSTIX_ETH1_IRQ                IRQ_GPIO(GPIO_GUMSTIX_ETH1)
+#define GUMSTIX_ETH1_IRQ                PXA_GPIO_TO_IRQ(GPIO_GUMSTIX_ETH1)
 /* CF reset line */
@@ -63,18 +63,18 @@ has detected a cable insertion; driven low otherwise. */
 #define GPIO4_nSTSCHG                   GPIO4_nBVD1
 #define GPIO11_nCD                      11
 #define GPIO26_PRDY_nBSY                26
-#define GUMSTIX_S0_nSTSCHG_IRQ          IRQ_GPIO(GPIO4_nSTSCHG)
+#define GUMSTIX_S0_nSTSCHG_IRQ          PXA_GPIO_TO_IRQ(GPIO4_nSTSCHG)
-#define GUMSTIX_S0_nCD_IRQ              IRQ_GPIO(GPIO11_nCD)
+#define GUMSTIX_S0_nCD_IRQ              PXA_GPIO_TO_IRQ(GPIO11_nCD)
-#define GUMSTIX_S0_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO26_PRDY_nBSY)
+#define GUMSTIX_S0_PRDY_nBSY_IRQ        PXA_GPIO_TO_IRQ(GPIO26_PRDY_nBSY)
 /* CF slot 1 */
 #define GPIO18_nBVD1                    18
 #define GPIO18_nSTSCHG                  GPIO18_nBVD1
 #define GPIO36_nCD                      36
 #define GPIO27_PRDY_nBSY                27
-#define GUMSTIX_S1_nSTSCHG_IRQ          IRQ_GPIO(GPIO18_nSTSCHG)
+#define GUMSTIX_S1_nSTSCHG_IRQ          PXA_GPIO_TO_IRQ(GPIO18_nSTSCHG)
-#define GUMSTIX_S1_nCD_IRQ              IRQ_GPIO(GPIO36_nCD)
+#define GUMSTIX_S1_nCD_IRQ              PXA_GPIO_TO_IRQ(GPIO36_nCD)
-#define GUMSTIX_S1_PRDY_nBSY_IRQ        IRQ_GPIO(GPIO27_PRDY_nBSY)
+#define GUMSTIX_S1_PRDY_nBSY_IRQ        PXA_GPIO_TO_IRQ(GPIO27_PRDY_nBSY)
 /* CF GPIO line modes */
 #define GPIO4_nSTSCHG_MD                (GPIO4_nSTSCHG | GPIO_IN)
diff --git a/arch/arm/mach-pxa/include/mach/hx4700.h b/arch/arm/mach-pxa/include/mach/hx4700.h
index 37408449ec2..8bc02913517 100644
--- a/arch/arm/mach-pxa/include/mach/hx4700.h
+++ b/arch/arm/mach-pxa/include/mach/hx4700.h
@@ -15,7 +15,7 @@
 #include <linux/gpio.h>
 #include <linux/mfd/asic3.h>
-#define HX4700_ASIC3_GPIO_BASE  NR_BUILTIN_GPIO
+#define HX4700_ASIC3_GPIO_BASE  PXA_NR_BUILTIN_GPIO
 #define HX4700_EGPIO_BASE       (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS)
 #define HX4700_NR_IRQS          (IRQ_BOARD_START + 70)
diff --git a/arch/arm/mach-pxa/include/mach/idp.h b/arch/arm/mach-pxa/include/mach/idp.h
index 5eff96fcc94..22a96f87232 100644
--- a/arch/arm/mach-pxa/include/mach/idp.h
+++ b/arch/arm/mach-pxa/include/mach/idp.h
@@ -131,28 +131,26 @@
 #define PCC_VS2         (1 << 1)
 #define PCC_VS1         (1 << 0)
-#define PCC_DETECT(x)   (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
 /* A listing of interrupts used by external hardware devices */
-#define TOUCH_PANEL_IRQ                 IRQ_GPIO(5)
+#define TOUCH_PANEL_IRQ                 PXA_GPIO_TO_IRQ(5)
-#define IDE_IRQ                         IRQ_GPIO(21)
+#define IDE_IRQ                         PXA_GPIO_TO_IRQ(21)
 #define TOUCH_PANEL_IRQ_EDGE            IRQ_TYPE_EDGE_FALLING
-#define ETHERNET_IRQ                    IRQ_GPIO(4)
+#define ETHERNET_IRQ                    PXA_GPIO_TO_IRQ(4)
 #define ETHERNET_IRQ_EDGE               IRQ_TYPE_EDGE_RISING
 #define IDE_IRQ_EDGE                    IRQ_TYPE_EDGE_RISING
-#define PCMCIA_S0_CD_VALID              IRQ_GPIO(7)
+#define PCMCIA_S0_CD_VALID              PXA_GPIO_TO_IRQ(7)
 #define PCMCIA_S0_CD_VALID_EDGE         IRQ_TYPE_EDGE_BOTH
-#define PCMCIA_S1_CD_VALID              IRQ_GPIO(8)
+#define PCMCIA_S1_CD_VALID              PXA_GPIO_TO_IRQ(8)
 #define PCMCIA_S1_CD_VALID_EDGE         IRQ_TYPE_EDGE_BOTH
-#define PCMCIA_S0_RDYINT                IRQ_GPIO(19)
+#define PCMCIA_S0_RDYINT                PXA_GPIO_TO_IRQ(19)
-#define PCMCIA_S1_RDYINT                IRQ_GPIO(22)
+#define PCMCIA_S1_RDYINT                PXA_GPIO_TO_IRQ(22)
 /*
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 7cc5a781e99..32975adf3ca 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -88,10 +88,8 @@
 #define IRQ_U2P         PXA_IRQ(93)     /* USB PHY D+/D- Lines (PXA935) */
 #define PXA_GPIO_IRQ_BASE       PXA_IRQ(96)
-#define PXA_GPIO_IRQ_NUM        (192)
+#define PXA_NR_BUILTIN_GPIO     (192)
+#define PXA_GPIO_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
-#define GPIO_2_x_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
-#define IRQ_GPIO(x)     (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
 /*
 * The following interrupts are for board specific purposes. Since
@@ -100,7 +98,7 @@
 * By default, no board IRQ is reserved. It should be finished in
 * custom board since sparse IRQ is already enabled.
 */
-#define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
+#define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_NR_BUILTIN_GPIO)
 #define NR_IRQS                 (IRQ_BOARD_START)
diff --git a/arch/arm/mach-pxa/include/mach/littleton.h b/arch/arm/mach-pxa/include/mach/littleton.h
index b6238cbd8ae..8066be54e9f 100644
--- a/arch/arm/mach-pxa/include/mach/littleton.h
+++ b/arch/arm/mach-pxa/include/mach/littleton.h
@@ -1,13 +1,11 @@
 #ifndef __ASM_ARCH_LITTLETON_H
 #define __ASM_ARCH_LITTLETON_H
-#include <mach/gpio-pxa.h>
 #define LITTLETON_ETH_PHYS      0x30000000
 #define LITTLETON_GPIO_LCD_CS   (17)
-#define EXT0_GPIO_BASE  (NR_BUILTIN_GPIO)
+#define EXT0_GPIO_BASE  (PXA_NR_BUILTIN_GPIO)
 #define EXT0_GPIO(x)    (EXT0_GPIO_BASE + (x))
 #define LITTLETON_NR_IRQS       (IRQ_BOARD_START + 8)
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
index 7cbfc5d3f9d..ba6a6e1d29e 100644
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ b/arch/arm/mach-pxa/include/mach/magician.h
@@ -78,7 +78,7 @@
 * CPLD EGPIOs
 */
-#define MAGICIAN_EGPIO_BASE                     NR_BUILTIN_GPIO
+#define MAGICIAN_EGPIO_BASE                     PXA_NR_BUILTIN_GPIO
 #define MAGICIAN_EGPIO(reg,bit) \
        (MAGICIAN_EGPIO_BASE + 8*reg + bit)
diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h
index ae536e86d8e..2c447133657 100644
--- a/arch/arm/mach-pxa/include/mach/palmld.h
+++ b/arch/arm/mach-pxa/include/mach/palmld.h
@@ -68,10 +68,10 @@
 /* 20, 53 and 86 are usb related too */
 /* INTERRUPTS */
-#define IRQ_GPIO_PALMLD_GPIO_RESET      IRQ_GPIO(GPIO_NR_PALMLD_GPIO_RESET)
+#define IRQ_GPIO_PALMLD_GPIO_RESET      PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_GPIO_RESET)
-#define IRQ_GPIO_PALMLD_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMLD_SD_DETECT_N)
+#define IRQ_GPIO_PALMLD_SD_DETECT_N     PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_SD_DETECT_N)
-#define IRQ_GPIO_PALMLD_WM9712_IRQ      IRQ_GPIO(GPIO_NR_PALMLD_WM9712_IRQ)
+#define IRQ_GPIO_PALMLD_WM9712_IRQ      PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_WM9712_IRQ)
-#define IRQ_GPIO_PALMLD_IDE_IRQ         IRQ_GPIO(GPIO_NR_PALMLD_IDE_IRQ)
+#define IRQ_GPIO_PALMLD_IDE_IRQ         PXA_GPIO_TO_IRQ(GPIO_NR_PALMLD_IDE_IRQ)
 /** HERE ARE INIT VALUES **/
diff --git a/arch/arm/mach-pxa/include/mach/palmt5.h b/arch/arm/mach-pxa/include/mach/palmt5.h
index 6baf7469d4e..0bd4f036c72 100644
--- a/arch/arm/mach-pxa/include/mach/palmt5.h
+++ b/arch/arm/mach-pxa/include/mach/palmt5.h
@@ -48,10 +48,10 @@
 #define GPIO_NR_PALMT5_BT_RESET                 83
 /* INTERRUPTS */
-#define IRQ_GPIO_PALMT5_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMT5_SD_DETECT_N)
+#define IRQ_GPIO_PALMT5_SD_DETECT_N     PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_SD_DETECT_N)
-#define IRQ_GPIO_PALMT5_WM9712_IRQ      IRQ_GPIO(GPIO_NR_PALMT5_WM9712_IRQ)
+#define IRQ_GPIO_PALMT5_WM9712_IRQ      PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_WM9712_IRQ)
-#define IRQ_GPIO_PALMT5_USB_DETECT      IRQ_GPIO(GPIO_NR_PALMT5_USB_DETECT)
+#define IRQ_GPIO_PALMT5_USB_DETECT      PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_USB_DETECT)
-#define IRQ_GPIO_PALMT5_GPIO_RESET      IRQ_GPIO(GPIO_NR_PALMT5_GPIO_RESET)
+#define IRQ_GPIO_PALMT5_GPIO_RESET      PXA_GPIO_TO_IRQ(GPIO_NR_PALMT5_GPIO_RESET)
 /** HERE ARE INIT VALUES **/
diff --git a/arch/arm/mach-pxa/include/mach/palmtc.h b/arch/arm/mach-pxa/include/mach/palmtc.h
index 3f9dd3fd463..c383a21680b 100644
--- a/arch/arm/mach-pxa/include/mach/palmtc.h
+++ b/arch/arm/mach-pxa/include/mach/palmtc.h
@@ -52,8 +52,8 @@
 #define GPIO_NR_PALMTC_IR_DISABLE       45
 /* IRQs */
-#define IRQ_GPIO_PALMTC_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMTC_SD_DETECT_N)
+#define IRQ_GPIO_PALMTC_SD_DETECT_N     PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_SD_DETECT_N)
-#define IRQ_GPIO_PALMTC_WLAN_READY      IRQ_GPIO(GPIO_NR_PALMTC_WLAN_READY)
+#define IRQ_GPIO_PALMTC_WLAN_READY      PXA_GPIO_TO_IRQ(GPIO_NR_PALMTC_WLAN_READY)
 /* UCB1400 GPIOs */
 #define GPIO_NR_PALMTC_POWER_DETECT     (0x80 | 0x00)
diff --git a/arch/arm/mach-pxa/include/mach/palmtx.h b/arch/arm/mach-pxa/include/mach/palmtx.h
index 7074a6ed46c..f2e53038025 100644
--- a/arch/arm/mach-pxa/include/mach/palmtx.h
+++ b/arch/arm/mach-pxa/include/mach/palmtx.h
@@ -62,10 +62,10 @@
 #define GPIO_NR_PALMTX_NAND_BUFFER_DIR          79
 /* INTERRUPTS */
-#define IRQ_GPIO_PALMTX_SD_DETECT_N     IRQ_GPIO(GPIO_NR_PALMTX_SD_DETECT_N)
+#define IRQ_GPIO_PALMTX_SD_DETECT_N     PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_SD_DETECT_N)
-#define IRQ_GPIO_PALMTX_WM9712_IRQ      IRQ_GPIO(GPIO_NR_PALMTX_WM9712_IRQ)
+#define IRQ_GPIO_PALMTX_WM9712_IRQ      PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_WM9712_IRQ)
-#define IRQ_GPIO_PALMTX_USB_DETECT      IRQ_GPIO(GPIO_NR_PALMTX_USB_DETECT)
+#define IRQ_GPIO_PALMTX_USB_DETECT      PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_USB_DETECT)
-#define IRQ_GPIO_PALMTX_GPIO_RESET      IRQ_GPIO(GPIO_NR_PALMTX_GPIO_RESET)
+#define IRQ_GPIO_PALMTX_GPIO_RESET      PXA_GPIO_TO_IRQ(GPIO_NR_PALMTX_GPIO_RESET)
 /** HERE ARE INIT VALUES **/
diff --git a/arch/arm/mach-pxa/include/mach/pcm027.h b/arch/arm/mach-pxa/include/mach/pcm027.h
index 4bac588478a..6bf28de228b 100644
--- a/arch/arm/mach-pxa/include/mach/pcm027.h
+++ b/arch/arm/mach-pxa/include/mach/pcm027.h
@@ -34,7 +34,7 @@
 /* I2C RTC */
 #define PCM027_RTC_IRQ_GPIO     0
-#define PCM027_RTC_IRQ          IRQ_GPIO(PCM027_RTC_IRQ_GPIO)
+#define PCM027_RTC_IRQ          PXA_GPIO_TO_IRQ(PCM027_RTC_IRQ_GPIO)
 #define PCM027_RTC_IRQ_EDGE     IRQ_TYPE_EDGE_FALLING
 #define ADR_PCM027_RTC          0x51    /* I2C address */
@@ -43,21 +43,21 @@
 /* Ethernet chip (SMSC91C111) */
 #define PCM027_ETH_IRQ_GPIO     52
-#define PCM027_ETH_IRQ          IRQ_GPIO(PCM027_ETH_IRQ_GPIO)
+#define PCM027_ETH_IRQ          PXA_GPIO_TO_IRQ(PCM027_ETH_IRQ_GPIO)
 #define PCM027_ETH_IRQ_EDGE     IRQ_TYPE_EDGE_RISING
 #define PCM027_ETH_PHYS         PXA_CS5_PHYS
 #define PCM027_ETH_SIZE         (1*1024*1024)
 /* CAN controller SJA1000 (unsupported yet) */
 #define PCM027_CAN_IRQ_GPIO     114
-#define PCM027_CAN_IRQ          IRQ_GPIO(PCM027_CAN_IRQ_GPIO)
+#define PCM027_CAN_IRQ          PXA_GPIO_TO_IRQ(PCM027_CAN_IRQ_GPIO)
 #define PCM027_CAN_IRQ_EDGE     IRQ_TYPE_EDGE_FALLING
 #define PCM027_CAN_PHYS         0x22000000
 #define PCM027_CAN_SIZE         0x100
 /* SPI GPIO expander (unsupported yet) */
 #define PCM027_EGPIO_IRQ_GPIO   27
-#define PCM027_EGPIO_IRQ        IRQ_GPIO(PCM027_EGPIO_IRQ_GPIO)
+#define PCM027_EGPIO_IRQ        PXA_GPIO_TO_IRQ(PCM027_EGPIO_IRQ_GPIO)
 #define PCM027_EGPIO_IRQ_EDGE   IRQ_TYPE_EDGE_FALLING
 #define PCM027_EGPIO_CS         24
 /*
diff --git a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
index 8a4383b776d..d72791695b2 100644
--- a/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
+++ b/arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
@@ -28,14 +28,14 @@
 /* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
 #define PCM990_CTRL_INT_IRQ_GPIO        9
-#define PCM990_CTRL_INT_IRQ             IRQ_GPIO(PCM990_CTRL_INT_IRQ_GPIO)
+#define PCM990_CTRL_INT_IRQ             PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO)
 #define PCM990_CTRL_INT_IRQ_EDGE        IRQ_TYPE_EDGE_RISING
 #define PCM990_CTRL_PHYS                PXA_CS1_PHYS    /* 16-Bit */
 #define PCM990_CTRL_BASE                0xea000000
 #define PCM990_CTRL_SIZE                (1*1024*1024)
 #define PCM990_CTRL_PWR_IRQ_GPIO        14
-#define PCM990_CTRL_PWR_IRQ             IRQ_GPIO(PCM990_CTRL_PWR_IRQ_GPIO)
+#define PCM990_CTRL_PWR_IRQ             PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO)
 #define PCM990_CTRL_PWR_IRQ_EDGE        IRQ_TYPE_EDGE_RISING
 /* visible CPLD (U7) registers */
@@ -132,7 +132,7 @@
 * IDE
 */
 #define PCM990_IDE_IRQ_GPIO     13
-#define PCM990_IDE_IRQ          IRQ_GPIO(PCM990_IDE_IRQ_GPIO)
+#define PCM990_IDE_IRQ          PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO)
 #define PCM990_IDE_IRQ_EDGE     IRQ_TYPE_EDGE_RISING
 #define PCM990_IDE_PLD_PHYS     0x20000000      /* 16 bit wide */
 #define PCM990_IDE_PLD_BASE     0xee000000
@@ -188,11 +188,11 @@
 * Compact Flash
 */
 #define PCM990_CF_IRQ_GPIO      11
-#define PCM990_CF_IRQ           IRQ_GPIO(PCM990_CF_IRQ_GPIO)
+#define PCM990_CF_IRQ           PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO)
 #define PCM990_CF_IRQ_EDGE      IRQ_TYPE_EDGE_RISING
 #define PCM990_CF_CD_GPIO       12
-#define PCM990_CF_CD            IRQ_GPIO(PCM990_CF_CD_GPIO)
+#define PCM990_CF_CD            PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO)
 #define PCM990_CF_CD_EDGE       IRQ_TYPE_EDGE_RISING
 #define PCM990_CF_PLD_PHYS      0x30000000      /* 16 bit wide */
@@ -258,14 +258,14 @@
 * Wolfson AC97 Touch
 */
 #define PCM990_AC97_IRQ_GPIO    10
-#define PCM990_AC97_IRQ         IRQ_GPIO(PCM990_AC97_IRQ_GPIO)
+#define PCM990_AC97_IRQ         PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO)
 #define PCM990_AC97_IRQ_EDGE    IRQ_TYPE_EDGE_RISING
 /*
 * MMC phyCORE
 */
 #define PCM990_MMC0_IRQ_GPIO    9
-#define PCM990_MMC0_IRQ         IRQ_GPIO(PCM990_MMC0_IRQ_GPIO)
+#define PCM990_MMC0_IRQ         PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO)
 #define PCM990_MMC0_IRQ_EDGE    IRQ_TYPE_EDGE_FALLING
 /*
diff --git a/arch/arm/mach-pxa/include/mach/poodle.h b/arch/arm/mach-pxa/include/mach/poodle.h
index 83d1cfd00fc..f32ff75dcca 100644
--- a/arch/arm/mach-pxa/include/mach/poodle.h
+++ b/arch/arm/mach-pxa/include/mach/poodle.h
@@ -47,18 +47,18 @@
 #define POODLE_GPIO_DISCHARGE_ON        (42) /* Enable battery discharge */
 /* PXA GPIOs */
-#define POODLE_IRQ_GPIO_ON_KEY          IRQ_GPIO(0)
+#define POODLE_IRQ_GPIO_ON_KEY          PXA_GPIO_TO_IRQ(0)
-#define POODLE_IRQ_GPIO_AC_IN           IRQ_GPIO(1)
+#define POODLE_IRQ_GPIO_AC_IN           PXA_GPIO_TO_IRQ(1)
-#define POODLE_IRQ_GPIO_HP_IN           IRQ_GPIO(4)
+#define POODLE_IRQ_GPIO_HP_IN           PXA_GPIO_TO_IRQ(4)
-#define POODLE_IRQ_GPIO_CO              IRQ_GPIO(16)
+#define POODLE_IRQ_GPIO_CO              PXA_GPIO_TO_IRQ(16)
-#define POODLE_IRQ_GPIO_TP_INT          IRQ_GPIO(5)
+#define POODLE_IRQ_GPIO_TP_INT          PXA_GPIO_TO_IRQ(5)
-#define POODLE_IRQ_GPIO_WAKEUP          IRQ_GPIO(11)
+#define POODLE_IRQ_GPIO_WAKEUP          PXA_GPIO_TO_IRQ(11)
-#define POODLE_IRQ_GPIO_GA_INT          IRQ_GPIO(10)
+#define POODLE_IRQ_GPIO_GA_INT          PXA_GPIO_TO_IRQ(10)
-#define POODLE_IRQ_GPIO_CF_IRQ          IRQ_GPIO(17)
+#define POODLE_IRQ_GPIO_CF_IRQ          PXA_GPIO_TO_IRQ(17)
-#define POODLE_IRQ_GPIO_CF_CD           IRQ_GPIO(14)
+#define POODLE_IRQ_GPIO_CF_CD           PXA_GPIO_TO_IRQ(14)
-#define POODLE_IRQ_GPIO_nSD_INT         IRQ_GPIO(8)
+#define POODLE_IRQ_GPIO_nSD_INT         PXA_GPIO_TO_IRQ(8)
-#define POODLE_IRQ_GPIO_nSD_DETECT      IRQ_GPIO(9)
+#define POODLE_IRQ_GPIO_nSD_DETECT      PXA_GPIO_TO_IRQ(9)
-#define POODLE_IRQ_GPIO_MAIN_BAT_LOW    IRQ_GPIO(13)
+#define POODLE_IRQ_GPIO_MAIN_BAT_LOW    PXA_GPIO_TO_IRQ(13)
 /* SCOOP GPIOs */
 #define POODLE_SCOOP_CHARGE_ON  SCOOP_GPCR_PA11
@@ -71,7 +71,7 @@
 #define POODLE_SCOOP_IO_DIR     ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
 #define POODLE_SCOOP_IO_OUT     ( 0 )
-#define POODLE_SCOOP_GPIO_BASE  (NR_BUILTIN_GPIO)
+#define POODLE_SCOOP_GPIO_BASE  (PXA_NR_BUILTIN_GPIO)
 #define POODLE_GPIO_CHARGE_ON   (POODLE_SCOOP_GPIO_BASE + 0)
 #define POODLE_GPIO_CP401       (POODLE_SCOOP_GPIO_BASE + 2)
 #define POODLE_GPIO_VPEN        (POODLE_SCOOP_GPIO_BASE + 7)
diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index 685749a51c4..0bfe6507c95 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -108,7 +108,7 @@
 #define SPITZ_SCP_SUS_CLR     (SPITZ_SCP_MUTE_L | SPITZ_SCP_MUTE_R | SPITZ_SCP_JK_A | SPITZ_SCP_ADC_TEMP_ON)
 #define SPITZ_SCP_SUS_SET     0
-#define SPITZ_SCP_GPIO_BASE     (NR_BUILTIN_GPIO)
+#define SPITZ_SCP_GPIO_BASE     (PXA_NR_BUILTIN_GPIO)
 #define SPITZ_GPIO_LED_GREEN    (SPITZ_SCP_GPIO_BASE + 0)
 #define SPITZ_GPIO_JK_B         (SPITZ_SCP_GPIO_BASE + 1)
 #define SPITZ_GPIO_CHRG_ON      (SPITZ_SCP_GPIO_BASE + 2)
@@ -140,7 +140,7 @@
                             SPITZ_SCP2_BACKLIGHT_CONT | SPITZ_SCP2_BACKLIGHT_ON | SPITZ_SCP2_MIC_BIAS)
 #define SPITZ_SCP2_SUS_SET  (SPITZ_SCP2_IR_ON | SPITZ_SCP2_RESERVED_1)
-#define SPITZ_SCP2_GPIO_BASE            (NR_BUILTIN_GPIO + 12)
+#define SPITZ_SCP2_GPIO_BASE            (PXA_NR_BUILTIN_GPIO + 12)
 #define SPITZ_GPIO_IR_ON                (SPITZ_SCP2_GPIO_BASE + 0)
 #define SPITZ_GPIO_AKIN_PULLUP          (SPITZ_SCP2_GPIO_BASE + 1)
 #define SPITZ_GPIO_RESERVED_1           (SPITZ_SCP2_GPIO_BASE + 2)
@@ -152,7 +152,7 @@
 #define SPITZ_GPIO_MIC_BIAS             (SPITZ_SCP2_GPIO_BASE + 8)
 /* Akita IO Expander GPIOs */
-#define AKITA_IOEXP_GPIO_BASE           (NR_BUILTIN_GPIO + 12)
+#define AKITA_IOEXP_GPIO_BASE           (PXA_NR_BUILTIN_GPIO + 12)
 #define AKITA_GPIO_RESERVED_0           (AKITA_IOEXP_GPIO_BASE + 0)
 #define AKITA_GPIO_RESERVED_1           (AKITA_IOEXP_GPIO_BASE + 1)
 #define AKITA_GPIO_MIC_BIAS             (AKITA_IOEXP_GPIO_BASE + 2)
@@ -164,23 +164,23 @@
 /* Spitz IRQ Definitions */
-#define SPITZ_IRQ_GPIO_KEY_INT        IRQ_GPIO(SPITZ_GPIO_KEY_INT)
+#define SPITZ_IRQ_GPIO_KEY_INT        PXA_GPIO_TO_IRQ(SPITZ_GPIO_KEY_INT)
-#define SPITZ_IRQ_GPIO_AC_IN          IRQ_GPIO(SPITZ_GPIO_AC_IN)
+#define SPITZ_IRQ_GPIO_AC_IN          PXA_GPIO_TO_IRQ(SPITZ_GPIO_AC_IN)
-#define SPITZ_IRQ_GPIO_AK_INT         IRQ_GPIO(SPITZ_GPIO_AK_INT)
+#define SPITZ_IRQ_GPIO_AK_INT         PXA_GPIO_TO_IRQ(SPITZ_GPIO_AK_INT)
-#define SPITZ_IRQ_GPIO_HP_IN          IRQ_GPIO(SPITZ_GPIO_HP_IN)
+#define SPITZ_IRQ_GPIO_HP_IN          PXA_GPIO_TO_IRQ(SPITZ_GPIO_HP_IN)
-#define SPITZ_IRQ_GPIO_TP_INT         IRQ_GPIO(SPITZ_GPIO_TP_INT)
+#define SPITZ_IRQ_GPIO_TP_INT         PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT)
-#define SPITZ_IRQ_GPIO_SYNC           IRQ_GPIO(SPITZ_GPIO_SYNC)
+#define SPITZ_IRQ_GPIO_SYNC           PXA_GPIO_TO_IRQ(SPITZ_GPIO_SYNC)
-#define SPITZ_IRQ_GPIO_ON_KEY         IRQ_GPIO(SPITZ_GPIO_ON_KEY)
+#define SPITZ_IRQ_GPIO_ON_KEY         PXA_GPIO_TO_IRQ(SPITZ_GPIO_ON_KEY)
-#define SPITZ_IRQ_GPIO_SWA            IRQ_GPIO(SPITZ_GPIO_SWA)
+#define SPITZ_IRQ_GPIO_SWA            PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWA)
-#define SPITZ_IRQ_GPIO_SWB            IRQ_GPIO(SPITZ_GPIO_SWB)
+#define SPITZ_IRQ_GPIO_SWB            PXA_GPIO_TO_IRQ(SPITZ_GPIO_SWB)
-#define SPITZ_IRQ_GPIO_BAT_COVER      IRQ_GPIO(SPITZ_GPIO_BAT_COVER)
+#define SPITZ_IRQ_GPIO_BAT_COVER      PXA_GPIO_TO_IRQ(SPITZ_GPIO_BAT_COVER)
-#define SPITZ_IRQ_GPIO_FATAL_BAT      IRQ_GPIO(SPITZ_GPIO_FATAL_BAT)
+#define SPITZ_IRQ_GPIO_FATAL_BAT      PXA_GPIO_TO_IRQ(SPITZ_GPIO_FATAL_BAT)
-#define SPITZ_IRQ_GPIO_CO             IRQ_GPIO(SPITZ_GPIO_CO)
+#define SPITZ_IRQ_GPIO_CO             PXA_GPIO_TO_IRQ(SPITZ_GPIO_CO)
-#define SPITZ_IRQ_GPIO_CF_IRQ         IRQ_GPIO(SPITZ_GPIO_CF_IRQ)
+#define SPITZ_IRQ_GPIO_CF_IRQ         PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_IRQ)
-#define SPITZ_IRQ_GPIO_CF_CD          IRQ_GPIO(SPITZ_GPIO_CF_CD)
+#define SPITZ_IRQ_GPIO_CF_CD          PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF_CD)
-#define SPITZ_IRQ_GPIO_CF2_IRQ        IRQ_GPIO(SPITZ_GPIO_CF2_IRQ)
+#define SPITZ_IRQ_GPIO_CF2_IRQ        PXA_GPIO_TO_IRQ(SPITZ_GPIO_CF2_IRQ)
-#define SPITZ_IRQ_GPIO_nSD_INT        IRQ_GPIO(SPITZ_GPIO_nSD_INT)
+#define SPITZ_IRQ_GPIO_nSD_INT        PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_INT)
-#define SPITZ_IRQ_GPIO_nSD_DETECT     IRQ_GPIO(SPITZ_GPIO_nSD_DETECT)
+#define SPITZ_IRQ_GPIO_nSD_DETECT     PXA_GPIO_TO_IRQ(SPITZ_GPIO_nSD_DETECT)
 /*
 * Shared data structures
diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h
index d1fce8b6d10..c5afacd3cc0 100644
--- a/arch/arm/mach-pxa/include/mach/system.h
+++ b/arch/arm/mach-pxa/include/mach/system.h
@@ -9,15 +9,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <asm/proc-fns.h>
-#include "hardware.h"
-#include "pxa2xx-regs.h"
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-void arch_reset(char mode, const char *cmd);
diff --git a/arch/arm/mach-pxa/include/mach/tosa.h b/arch/arm/mach-pxa/include/mach/tosa.h
index 1272c4b56ce..2bb0e862598 100644
--- a/arch/arm/mach-pxa/include/mach/tosa.h
+++ b/arch/arm/mach-pxa/include/mach/tosa.h
@@ -24,7 +24,7 @@
 /*
 * SCOOP2 internal GPIOs
 */
-#define TOSA_SCOOP_GPIO_BASE            NR_BUILTIN_GPIO
+#define TOSA_SCOOP_GPIO_BASE            PXA_NR_BUILTIN_GPIO
 #define TOSA_SCOOP_PXA_VCORE1           SCOOP_GPCR_PA11
 #define TOSA_GPIO_TC6393XB_REST_IN      (TOSA_SCOOP_GPIO_BASE + 1)
 #define TOSA_GPIO_IR_POWERDWN           (TOSA_SCOOP_GPIO_BASE + 2)
@@ -42,7 +42,7 @@
 /*
 * SCOOP2 jacket GPIOs
 */
-#define TOSA_SCOOP_JC_GPIO_BASE         (NR_BUILTIN_GPIO + 12)
+#define TOSA_SCOOP_JC_GPIO_BASE         (PXA_NR_BUILTIN_GPIO + 12)
 #define TOSA_GPIO_BT_LED                (TOSA_SCOOP_JC_GPIO_BASE + 0)
 #define TOSA_GPIO_NOTE_LED              (TOSA_SCOOP_JC_GPIO_BASE + 1)
 #define TOSA_GPIO_CHRG_ERR_LED          (TOSA_SCOOP_JC_GPIO_BASE + 2)
@@ -59,7 +59,7 @@
 /*
 * TC6393XB GPIOs
 */
-#define TOSA_TC6393XB_GPIO_BASE         (NR_BUILTIN_GPIO + 2 * 12)
+#define TOSA_TC6393XB_GPIO_BASE         (PXA_NR_BUILTIN_GPIO + 2 * 12)
 #define TOSA_GPIO_TG_ON                 (TOSA_TC6393XB_GPIO_BASE + 0)
 #define TOSA_GPIO_L_MUTE                (TOSA_TC6393XB_GPIO_BASE + 1)
@@ -141,30 +141,30 @@
 /*
 * Interrupts
 */
-#define TOSA_IRQ_GPIO_WAKEUP            IRQ_GPIO(TOSA_GPIO_WAKEUP)
+#define TOSA_IRQ_GPIO_WAKEUP            PXA_GPIO_TO_IRQ(TOSA_GPIO_WAKEUP)
-#define TOSA_IRQ_GPIO_AC_IN             IRQ_GPIO(TOSA_GPIO_AC_IN)
+#define TOSA_IRQ_GPIO_AC_IN             PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN)
-#define TOSA_IRQ_GPIO_RECORD_BTN        IRQ_GPIO(TOSA_GPIO_RECORD_BTN)
+#define TOSA_IRQ_GPIO_RECORD_BTN        PXA_GPIO_TO_IRQ(TOSA_GPIO_RECORD_BTN)
-#define TOSA_IRQ_GPIO_SYNC              IRQ_GPIO(TOSA_GPIO_SYNC)
+#define TOSA_IRQ_GPIO_SYNC              PXA_GPIO_TO_IRQ(TOSA_GPIO_SYNC)
-#define TOSA_IRQ_GPIO_USB_IN            IRQ_GPIO(TOSA_GPIO_USB_IN)
+#define TOSA_IRQ_GPIO_USB_IN            PXA_GPIO_TO_IRQ(TOSA_GPIO_USB_IN)
-#define TOSA_IRQ_GPIO_JACKET_DETECT     IRQ_GPIO(TOSA_GPIO_JACKET_DETECT)
+#define TOSA_IRQ_GPIO_JACKET_DETECT     PXA_GPIO_TO_IRQ(TOSA_GPIO_JACKET_DETECT)
-#define TOSA_IRQ_GPIO_nSD_INT           IRQ_GPIO(TOSA_GPIO_nSD_INT)
+#define TOSA_IRQ_GPIO_nSD_INT           PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_INT)
-#define TOSA_IRQ_GPIO_nSD_DETECT        IRQ_GPIO(TOSA_GPIO_nSD_DETECT)
+#define TOSA_IRQ_GPIO_nSD_DETECT        PXA_GPIO_TO_IRQ(TOSA_GPIO_nSD_DETECT)
-#define TOSA_IRQ_GPIO_BAT1_CRG          IRQ_GPIO(TOSA_GPIO_BAT1_CRG)
+#define TOSA_IRQ_GPIO_BAT1_CRG          PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_CRG)
-#define TOSA_IRQ_GPIO_CF_CD             IRQ_GPIO(TOSA_GPIO_CF_CD)
+#define TOSA_IRQ_GPIO_CF_CD             PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_CD)
-#define TOSA_IRQ_GPIO_BAT0_CRG          IRQ_GPIO(TOSA_GPIO_BAT0_CRG)
+#define TOSA_IRQ_GPIO_BAT0_CRG          PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_CRG)
-#define TOSA_IRQ_GPIO_TC6393XB_INT      IRQ_GPIO(TOSA_GPIO_TC6393XB_INT)
+#define TOSA_IRQ_GPIO_TC6393XB_INT      PXA_GPIO_TO_IRQ(TOSA_GPIO_TC6393XB_INT)
-#define TOSA_IRQ_GPIO_BAT0_LOW          IRQ_GPIO(TOSA_GPIO_BAT0_LOW)
+#define TOSA_IRQ_GPIO_BAT0_LOW          PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT0_LOW)
-#define TOSA_IRQ_GPIO_EAR_IN            IRQ_GPIO(TOSA_GPIO_EAR_IN)
+#define TOSA_IRQ_GPIO_EAR_IN            PXA_GPIO_TO_IRQ(TOSA_GPIO_EAR_IN)
-#define TOSA_IRQ_GPIO_CF_IRQ            IRQ_GPIO(TOSA_GPIO_CF_IRQ)
+#define TOSA_IRQ_GPIO_CF_IRQ            PXA_GPIO_TO_IRQ(TOSA_GPIO_CF_IRQ)
-#define TOSA_IRQ_GPIO_ON_KEY            IRQ_GPIO(TOSA_GPIO_ON_KEY)
+#define TOSA_IRQ_GPIO_ON_KEY            PXA_GPIO_TO_IRQ(TOSA_GPIO_ON_KEY)
-#define TOSA_IRQ_GPIO_VGA_LINE          IRQ_GPIO(TOSA_GPIO_VGA_LINE)
+#define TOSA_IRQ_GPIO_VGA_LINE          PXA_GPIO_TO_IRQ(TOSA_GPIO_VGA_LINE)
-#define TOSA_IRQ_GPIO_TP_INT            IRQ_GPIO(TOSA_GPIO_TP_INT)
+#define TOSA_IRQ_GPIO_TP_INT            PXA_GPIO_TO_IRQ(TOSA_GPIO_TP_INT)
-#define TOSA_IRQ_GPIO_JC_CF_IRQ         IRQ_GPIO(TOSA_GPIO_JC_CF_IRQ)
+#define TOSA_IRQ_GPIO_JC_CF_IRQ         PXA_GPIO_TO_IRQ(TOSA_GPIO_JC_CF_IRQ)
-#define TOSA_IRQ_GPIO_BAT_LOCKED        IRQ_GPIO(TOSA_GPIO_BAT_LOCKED)
+#define TOSA_IRQ_GPIO_BAT_LOCKED        PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT_LOCKED)
-#define TOSA_IRQ_GPIO_BAT1_LOW          IRQ_GPIO(TOSA_GPIO_BAT1_LOW)
+#define TOSA_IRQ_GPIO_BAT1_LOW          PXA_GPIO_TO_IRQ(TOSA_GPIO_BAT1_LOW)
-#define TOSA_IRQ_GPIO_KEY_SENSE(a)      IRQ_GPIO(69+(a))
+#define TOSA_IRQ_GPIO_KEY_SENSE(a)      PXA_GPIO_TO_IRQ(69+(a))
-#define TOSA_IRQ_GPIO_MAIN_BAT_LOW      IRQ_GPIO(TOSA_GPIO_MAIN_BAT_LOW)
+#define TOSA_IRQ_GPIO_MAIN_BAT_LOW      PXA_GPIO_TO_IRQ(TOSA_GPIO_MAIN_BAT_LOW)
 #define TOSA_KEY_SYNC           KEY_102ND /* ??? */
diff --git a/arch/arm/mach-pxa/include/mach/trizeps4.h b/arch/arm/mach-pxa/include/mach/trizeps4.h
index 903e1a2e664..d2ca01053f6 100644
--- a/arch/arm/mach-pxa/include/mach/trizeps4.h
+++ b/arch/arm/mach-pxa/include/mach/trizeps4.h
@@ -43,30 +43,30 @@
 /* Ethernet Controller Davicom DM9000 */
 #define GPIO_DM9000             101
-#define TRIZEPS4_ETH_IRQ        IRQ_GPIO(GPIO_DM9000)
+#define TRIZEPS4_ETH_IRQ        PXA_GPIO_TO_IRQ(GPIO_DM9000)
 /* UCB1400 audio / TS-controller */
 #define GPIO_UCB1400            1
-#define TRIZEPS4_UCB1400_IRQ    IRQ_GPIO(GPIO_UCB1400)
+#define TRIZEPS4_UCB1400_IRQ    PXA_GPIO_TO_IRQ(GPIO_UCB1400)
 /* PCMCIA socket Compact Flash */
 #define GPIO_PCD                11              /* PCMCIA Card Detect */
-#define TRIZEPS4_CD_IRQ         IRQ_GPIO(GPIO_PCD)
+#define TRIZEPS4_CD_IRQ         PXA_GPIO_TO_IRQ(GPIO_PCD)
 #define GPIO_PRDY               13              /* READY / nINT */
-#define TRIZEPS4_READY_NINT     IRQ_GPIO(GPIO_PRDY)
+#define TRIZEPS4_READY_NINT     PXA_GPIO_TO_IRQ(GPIO_PRDY)
 /* MMC socket */
 #define GPIO_MMC_DET            12
-#define TRIZEPS4_MMC_IRQ        IRQ_GPIO(GPIO_MMC_DET)
+#define TRIZEPS4_MMC_IRQ        PXA_GPIO_TO_IRQ(GPIO_MMC_DET)
 /* DOC NAND chip */
 #define GPIO_DOC_LOCK           94
 #define GPIO_DOC_IRQ            93
-#define TRIZEPS4_DOC_IRQ        IRQ_GPIO(GPIO_DOC_IRQ)
+#define TRIZEPS4_DOC_IRQ        PXA_GPIO_TO_IRQ(GPIO_DOC_IRQ)
 /* SPI interface */
 #define GPIO_SPI                53
-#define TRIZEPS4_SPI_IRQ        IRQ_GPIO(GPIO_SPI)
+#define TRIZEPS4_SPI_IRQ        PXA_GPIO_TO_IRQ(GPIO_SPI)
 /* LEDS using tx2 / rx2 */
 #define GPIO_SYS_BUSY_LED       46
@@ -74,7 +74,7 @@
 /* Off-module PIC on ConXS board */
 #define GPIO_PIC                0
-#define TRIZEPS4_PIC_IRQ        IRQ_GPIO(GPIO_PIC)
+#define TRIZEPS4_PIC_IRQ        PXA_GPIO_TO_IRQ(GPIO_PIC)
 #ifdef CONFIG_MACH_TRIZEPS_CONXS
 /* for CONXS base board define these registers */
diff --git a/arch/arm/mach-pxa/include/mach/vmalloc.h b/arch/arm/mach-pxa/include/mach/vmalloc.h
deleted file mode 100644
index bfecfbf5f46..00000000000
--- a/arch/arm/mach-pxa/include/mach/vmalloc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/vmalloc.h
- *
- * Author:      Nicolas Pitre
- * Copyright:   (C) 2001 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       (0xe8000000UL)
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 532c5d3a97d..5dae15ea671 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -22,7 +22,6 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/gpio-pxa.h>
 #include "generic.h"
@@ -92,44 +91,6 @@ static struct irq_chip pxa_internal_irq_chip = {
        .irq_unmask     = pxa_unmask_irq,
 };
-/*
- * GPIO IRQs for GPIO 0 and 1
- */
-static int pxa_set_low_gpio_type(struct irq_data *d, unsigned int type)
-{
-        int gpio = d->irq - IRQ_GPIO0;
-        if (__gpio_is_occupied(gpio)) {
-                pr_err("%s failed: GPIO is configured\n", __func__);
-                return -EINVAL;
-        }
-        if (type & IRQ_TYPE_EDGE_RISING)
-                GRER0 |= GPIO_bit(gpio);
-        else
-                GRER0 &= ~GPIO_bit(gpio);
-        if (type & IRQ_TYPE_EDGE_FALLING)
-                GFER0 |= GPIO_bit(gpio);
-        else
-                GFER0 &= ~GPIO_bit(gpio);
-        return 0;
-}
-static void pxa_ack_low_gpio(struct irq_data *d)
-{
-        GEDR0 = (1 << (d->irq - IRQ_GPIO0));
-}
-static struct irq_chip pxa_low_gpio_chip = {
-        .name           = "GPIO-l",
-        .irq_ack        = pxa_ack_low_gpio,
-        .irq_mask       = pxa_mask_irq,
-        .irq_unmask     = pxa_unmask_irq,
-        .irq_set_type   = pxa_set_low_gpio_type,
-};
 asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
 {
        uint32_t icip, icmr, mask;
@@ -160,26 +121,7 @@ asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
        } while (1);
 }
-static void __init pxa_init_low_gpio_irq(set_wake_t fn)
+void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
-{
-        int irq;
-        /* clear edge detection on GPIO 0 and 1 */
-        GFER0 &= ~0x3;
-        GRER0 &= ~0x3;
-        GEDR0 = 0x3;
-        for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
-                irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
-                                         handle_edge_irq);
-                irq_set_chip_data(irq, irq_base(0));
-                set_irq_flags(irq, IRQF_VALID);
-        }
-        pxa_low_gpio_chip.irq_set_wake = fn;
-}
-void __init pxa_init_irq(int irq_nr, set_wake_t fn)
 {
        int irq, i, n;
@@ -209,7 +151,6 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
        __raw_writel(1, irq_base(0) + ICCR);
        pxa_internal_irq_chip.irq_set_wake = fn;
-        pxa_init_low_gpio_irq(fn);
 }
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 7b324ec6449..1fb86edb857 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -124,8 +124,8 @@ static struct resource smc91x_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
+                .start  = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO90)),
-                .end    = IRQ_GPIO(mfp_to_gpio(MFP_PIN_GPIO90)),
+                .end    = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO90)),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
        }
 };
@@ -396,7 +396,7 @@ static struct i2c_board_info littleton_i2c_info[] = {
                .type           = "da9034",
                .addr           = 0x34,
                .platform_data  = &littleton_da9034_info,
-                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO18)),
+                .irq            = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO18)),
        },
        [1] = {
                .type           = "max7320",
@@ -445,4 +445,5 @@ MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleto
        .handle_irq     = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = littleton_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 1dd530279e0..cee9ce2fc0b 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -152,8 +152,8 @@ static void __init lpd270_init_irq(void)
                                         handle_level_irq);
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
-        irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
+        irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
-        irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
+        irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
 }
@@ -505,4 +505,5 @@ MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = lpd270_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index c48ce6da918..6ebd276aebe 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -170,8 +170,8 @@ static void __init lubbock_init_irq(void)
                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
        }
-        irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
+        irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lubbock_irq_handler);
-        irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
+        irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
 }
 #ifdef CONFIG_PM
@@ -556,4 +556,5 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
        .handle_irq     = pxa25x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = lubbock_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 4b796c37af3..3d6baf91396 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -184,8 +184,8 @@ static struct resource egpio_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        [1] = {
-                .start = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+                .start = PXA_GPIO_TO_IRQ(GPIO13_MAGICIAN_CPLD_IRQ),
-                .end   = gpio_to_irq(GPIO13_MAGICIAN_CPLD_IRQ),
+                .end   = PXA_GPIO_TO_IRQ(GPIO13_MAGICIAN_CPLD_IRQ),
                .flags = IORESOURCE_IRQ,
        },
 };
@@ -468,8 +468,8 @@ static struct resource pasic3_resources[] = {
        },
        /* No IRQ handler in the PASIC3, DS1WM needs an external IRQ */
        [1] = {
-                .start  = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO107_MAGICIAN_DS1WM_IRQ),
-                .end    = gpio_to_irq(GPIO107_MAGICIAN_DS1WM_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO107_MAGICIAN_DS1WM_IRQ),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        }
 };
@@ -760,4 +760,5 @@ MACHINE_START(MAGICIAN, "HTC Magician")
        .handle_irq = pxa27x_handle_irq,
        .init_machine = magician_init,
        .timer = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 0567d3965fd..1aebaf71946 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -178,8 +178,8 @@ static void __init mainstone_init_irq(void)
        MST_INTMSKENA = 0;
        MST_INTSETCLR = 0;
-        irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
+        irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), mainstone_irq_handler);
-        irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
+        irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
 }
 #ifdef CONFIG_PM
@@ -622,4 +622,5 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = mainstone_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index 43a5f6861ca..f14775536b8 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -13,6 +13,7 @@
 *  published by the Free Software Foundation.
 */
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -20,7 +21,6 @@
 #include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa2xx.h>
-#include <mach/gpio-pxa.h>
 #include "generic.h"
@@ -29,6 +29,10 @@
 #define GAFR_L(x)       __GAFR(0, x)
 #define GAFR_U(x)       __GAFR(1, x)
+#define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
+#define GPLR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5))
+#define GPDR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
 #define PWER_WE35       (1 << 24)
 struct gpio_desc {
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index b938fc2c316..e80a3db735c 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -53,6 +53,7 @@
 #include <mach/pxa27x-udc.h>
 #include <mach/camera.h>
 #include <mach/audio.h>
+#include <mach/smemc.h>
 #include <media/soc_camera.h>
 #include <mach/mioa701.h>
@@ -390,24 +391,19 @@ static struct pxamci_platform_data mioa701_mci_info = {
 };
 /* FlashRAM */
-static struct resource strataflash_resource = {
+static struct resource docg3_resource = {
        .start = PXA_CS0_PHYS,
-        .end   = PXA_CS0_PHYS + SZ_64M - 1,
+        .end   = PXA_CS0_PHYS + SZ_8K - 1,
        .flags = IORESOURCE_MEM,
 };
-static struct physmap_flash_data strataflash_data = {
+static struct platform_device docg3 = {
-        .width = 2,
+        .name          = "docg3",
-        /* .set_vpp = mioa701_set_vpp, */
-};
-static struct platform_device strataflash = {
-        .name          = "physmap-flash",
        .id            = -1,
-        .resource      = &strataflash_resource,
+        .resource      = &docg3_resource,
        .num_resources = 1,
        .dev = {
-                .platform_data = &strataflash_data,
+                .platform_data = NULL,
        },
 };
@@ -541,15 +537,15 @@ static struct pda_power_pdata power_pdata = {
 static struct resource power_resources[] = {
        [0] = {
                .name   = "ac",
-                .start  = gpio_to_irq(GPIO96_AC_DETECT),
+                .start  = PXA_GPIO_TO_IRQ(GPIO96_AC_DETECT),
-                .end    = gpio_to_irq(GPIO96_AC_DETECT),
+                .end    = PXA_GPIO_TO_IRQ(GPIO96_AC_DETECT),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
                IORESOURCE_IRQ_LOWEDGE,
        },
        [1] = {
                .name   = "usb",
-                .start  = gpio_to_irq(GPIO13_nUSB_DETECT),
+                .start  = PXA_GPIO_TO_IRQ(GPIO13_nUSB_DETECT),
-                .end    = gpio_to_irq(GPIO13_nUSB_DETECT),
+                .end    = PXA_GPIO_TO_IRQ(GPIO13_nUSB_DETECT),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE |
                IORESOURCE_IRQ_LOWEDGE,
        },
@@ -685,7 +681,7 @@ static struct platform_device *devices[] __initdata = {
        &pxa2xx_pcm,
        &mioa701_sound,
        &power_dev,
-        &strataflash,
+        &docg3,
        &gpio_vbus,
        &mioa701_camera,
        &mioa701_board,
@@ -696,13 +692,13 @@ static void mioa701_machine_exit(void);
 static void mioa701_poweroff(void)
 {
        mioa701_machine_exit();
-        arm_machine_restart('s', NULL);
+        pxa_restart('s', NULL);
 }
 static void mioa701_restart(char c, const char *cmd)
 {
        mioa701_machine_exit();
-        arm_machine_restart('s', cmd);
+        pxa_restart('s', cmd);
 }
 static struct gpio global_gpios[] = {
@@ -720,6 +716,15 @@ static void __init mioa701_machine_init(void)
        RTTR = 32768 - 1; /* Reset crazy WinCE value */
        UP2OCR = UP2OCR_HXOE;
+        /*
+         * Set up the flash memory : DiskOnChip G3 on first static memory bank
+         */
+        __raw_writel(0x7ff02dd8, MSC0);
+        __raw_writel(0x0001c391, MCMEM0);
+        __raw_writel(0x0001c391, MCATT0);
+        __raw_writel(0x0001c391, MCIO0);
        pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config));
        pxa_set_ffuart_info(NULL);
        pxa_set_btuart_info(NULL);
@@ -734,7 +739,6 @@ static void __init mioa701_machine_init(void)
        pxa_set_udc_info(&mioa701_udc_info);
        pxa_set_ac97_info(&mioa701_ac97_info);
        pm_power_off = mioa701_poweroff;
-        arm_pm_restart = mioa701_restart;
        platform_add_devices(devices, ARRAY_SIZE(devices));
        gsm_init();
@@ -752,9 +756,11 @@ static void mioa701_machine_exit(void)
 MACHINE_START(MIOA701, "MIO A701")
        .atag_offset    = 0x100,
+        .restart_mode   = 's',
        .map_io         = &pxa27x_map_io,
        .init_irq       = &pxa27x_init_irq,
        .handle_irq     = &pxa27x_handle_irq,
        .init_machine   = mioa701_machine_init,
        .timer          = &pxa_timer,
+        .restart        = mioa701_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 4af5d513c38..169bf8f97af 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -98,5 +98,6 @@ MACHINE_START(NEC_MP900, "MobilePro900/C")
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
        .init_machine   = mp900c_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
index 90928d6e1a5..83570a79e7d 100644
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ b/arch/arm/mach-pxa/mxm8x10.c
@@ -417,8 +417,8 @@ static struct resource dm9k_resources[] = {
               .flags = IORESOURCE_MEM
        },
        [2] = {
-               .start = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)),
+               .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO9)),
-               .end = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO9)),
+               .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO9)),
               .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
        }
 };
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 3d4a2819cae..1fa80f4f80c 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -347,5 +347,6 @@ MACHINE_START(PALMLD, "Palm LifeDrive")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
-        .init_machine   = palmld_init
+        .init_machine   = palmld_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 99d6bcf1f97..5ba14316bd9 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -208,5 +208,6 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
-        .init_machine   = palmt5_init
+        .init_machine   = palmt5_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index 2c24c67fd92..29b51b40f09 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -542,5 +542,6 @@ MACHINE_START(PALMTC, "Palm Tungsten|C")
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
        .timer          = &pxa_timer,
-        .init_machine   = palmtc_init
+        .init_machine   = palmtc_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 9376da06404..5ebf49acb82 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -361,5 +361,6 @@ MACHINE_START(PALMTE2, "Palm Tungsten|E2")
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
        .timer          = &pxa_timer,
-        .init_machine   = palmte2_init
+        .init_machine   = palmte2_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 94e9708b349..ec8249156c0 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -452,6 +452,7 @@ MACHINE_START(TREO680, "Palm Treo 680")
        .handle_irq       = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = treo680_init,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -464,5 +465,6 @@ MACHINE_START(CENTRO, "Palm Centro 685")
        .handle_irq       = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = centro_init,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 4e3e45927e9..6170d76dfba 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -369,5 +369,6 @@ MACHINE_START(PALMTX, "Palm T|X")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
-        .init_machine   = palmtx_init
+        .init_machine   = palmtx_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 68e18baf8e0..b2dff9d415e 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -404,5 +404,6 @@ MACHINE_START(PALMZ72, "Palm Zire72")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
-        .init_machine   = palmz72_init
+        .init_machine   = palmz72_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 0b825a35353..fe9054435b6 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -265,4 +265,5 @@ MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = pcm027_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 6d38c6548b3..abab4e2b122 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -378,7 +378,7 @@ struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
 #include <linux/i2c/pca953x.h>
 static struct pca953x_platform_data pca9536_data = {
-        .gpio_base      = NR_BUILTIN_GPIO,
+        .gpio_base      = PXA_NR_BUILTIN_GPIO,
 };
 static int gpio_bus_switch = -EINVAL;
@@ -406,9 +406,9 @@ static unsigned long pcm990_camera_query_bus_param(struct soc_camera_link *link)
        int ret;
        if (gpio_bus_switch < 0) {
-                ret = gpio_request(NR_BUILTIN_GPIO, "camera");
+                ret = gpio_request(PXA_NR_BUILTIN_GPIO, "camera");
                if (!ret) {
-                        gpio_bus_switch = NR_BUILTIN_GPIO;
+                        gpio_bus_switch = PXA_NR_BUILTIN_GPIO;
                        gpio_direction_output(gpio_bus_switch, 0);
                }
        }
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 50c83317786..744baee12c0 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -158,6 +158,11 @@ static struct scoop_pcmcia_config poodle_pcmcia_config = {
 EXPORT_SYMBOL(poodle_scoop_device);
+static struct platform_device poodle_audio_device = {
+        .name   = "poodle-audio",
+        .id     = -1,
+};
 /* LoCoMo device */
 static struct resource locomo_resources[] = {
        [0] = {
@@ -166,8 +171,8 @@ static struct resource locomo_resources[] = {
                .flags          = IORESOURCE_MEM,
        },
        [1] = {
-                .start          = IRQ_GPIO(10),
+                .start          = PXA_GPIO_TO_IRQ(10),
-                .end            = IRQ_GPIO(10),
+                .end            = PXA_GPIO_TO_IRQ(10),
                .flags          = IORESOURCE_IRQ,
        },
 };
@@ -212,7 +217,7 @@ static struct spi_board_info poodle_spi_devices[] = {
                .bus_num        = 1,
                .platform_data  = &poodle_ads7846_info,
                .controller_data= &poodle_ads7846_chip,
-                .irq            = gpio_to_irq(POODLE_GPIO_TP_INT),
+                .irq            = PXA_GPIO_TO_IRQ(POODLE_GPIO_TP_INT),
        },
 };
@@ -407,6 +412,7 @@ static struct platform_device sharpsl_rom_device = {
 static struct platform_device *devices[] __initdata = {
        &poodle_locomo_device,
        &poodle_scoop_device,
+        &poodle_audio_device,
        &sharpsl_nand_device,
        &sharpsl_rom_device,
 };
@@ -417,12 +423,7 @@ static struct i2c_board_info __initdata poodle_i2c_devices[] = {
 static void poodle_poweroff(void)
 {
-        arm_machine_restart('h', NULL);
+        pxa_restart('h', NULL);
-}
-static void poodle_restart(char mode, const char *cmd)
-{
-        arm_machine_restart('h', cmd);
 }
 static void __init poodle_init(void)
@@ -430,7 +431,6 @@ static void __init poodle_init(void)
        int ret = 0;
        pm_power_off = poodle_poweroff;
-        arm_pm_restart = poodle_restart;
        PCFR |= PCFR_OPDE;
@@ -472,4 +472,5 @@ MACHINE_START(POODLE, "SHARP Poodle")
        .handle_irq     = pxa25x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = poodle_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index f05f9486b0c..adf058fa97e 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -17,6 +17,7 @@
 * need be.
 */
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -208,6 +209,8 @@ static struct clk_lookup pxa25x_clkregs[] = {
        INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
        INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
        INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
+        INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 static struct clk_lookup pxa25x_hwuart_clkreg =
@@ -287,7 +290,7 @@ static inline void pxa25x_init_pm(void) {}
 static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
 {
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
        uint32_t mask = 0;
        if (gpio >= 0 && gpio < 85)
@@ -312,14 +315,12 @@ set_pwer:
 void __init pxa25x_init_irq(void)
 {
        pxa_init_irq(32, pxa25x_set_wake);
-        pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake);
 }
 #ifdef CONFIG_CPU_PXA26x
 void __init pxa26x_init_irq(void)
 {
        pxa_init_irq(32, pxa25x_set_wake);
-        pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake);
 }
 #endif
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index bc5a98ebaa7..180bd8675d4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -12,6 +12,7 @@
 * published by the Free Software Foundation.
 */
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -229,6 +230,8 @@ static struct clk_lookup pxa27x_clkregs[] = {
        INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
        INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
        INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
+        INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 #ifdef CONFIG_PM
@@ -355,7 +358,7 @@ static inline void pxa27x_init_pm(void) {}
 */
 static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
 {
-        int gpio = irq_to_gpio(d->irq);
+        int gpio = pxa_irq_to_gpio(d->irq);
        uint32_t mask;
        if (gpio >= 0 && gpio < 128)
@@ -386,7 +389,6 @@ static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
 void __init pxa27x_init_irq(void)
 {
        pxa_init_irq(34, pxa27x_set_wake);
-        pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
 }
 static struct map_desc pxa27x_io_desc[] __initdata = {
@@ -422,6 +424,7 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 }
 static struct platform_device *devices[] __initdata = {
+        &pxa_device_gpio,
        &pxa27x_device_udc,
        &pxa_device_pmu,
        &pxa_device_i2s,
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 40bb16501d8..0388eda7878 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -89,6 +89,7 @@ static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0);
 static struct clk_lookup common_clkregs[] = {
        INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
        INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index 8d614ecd8e9..d487e1ff4c9 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -83,6 +83,7 @@ static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0);
 static struct clk_lookup pxa320_clkregs[] = {
        INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
        INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
 };
 static int __init pxa320_init(void)
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index 0737c59b88a..f107c71c758 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -25,7 +25,6 @@
 #include <asm/mach/map.h>
 #include <asm/suspend.h>
 #include <mach/hardware.h>
-#include <mach/gpio-pxa.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/reset.h>
 #include <mach/ohci.h>
@@ -56,6 +55,7 @@ static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
+static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
@@ -67,6 +67,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
        INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
        /* Power I2C clock is always on */
        INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
        INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
        INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
        INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
@@ -88,6 +89,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
        INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
        INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
        INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
+        INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
 };
 #ifdef CONFIG_PM
@@ -365,7 +367,8 @@ static struct irq_chip pxa_ext_wakeup_chip = {
        .irq_set_type   = pxa_set_ext_wakeup_type,
 };
-static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
+static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
+                                           unsigned int))
 {
        int irq;
@@ -388,7 +391,6 @@ void __init pxa3xx_init_irq(void)
        pxa_init_irq(56, pxa3xx_set_wake);
        pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
-        pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
 }
 static struct map_desc pxa3xx_io_desc[] __initdata = {
@@ -417,6 +419,7 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 }
 static struct platform_device *devices[] __initdata = {
+        &pxa_device_gpio,
        &pxa27x_device_udc,
        &pxa_device_pmu,
        &pxa_device_i2s,
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
index 51371b39d2a..fccc644702e 100644
--- a/arch/arm/mach-pxa/pxa95x.c
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -20,7 +20,6 @@
 #include <linux/syscore_ops.h>
 #include <mach/hardware.h>
-#include <mach/gpio-pxa.h>
 #include <mach/pxa3xx-regs.h>
 #include <mach/pxa930.h>
 #include <mach/reset.h>
@@ -212,11 +211,13 @@ static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_gpio, GPIO, 13000000, 0);
 static struct clk_lookup pxa95x_clkregs[] = {
        INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
        /* Power I2C clock is always on */
        INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
        INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
        INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
        INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
@@ -230,12 +231,12 @@ static struct clk_lookup pxa95x_clkregs[] = {
        INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL),
        INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
        INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
+        INIT_CLKREG(&clk_pxa95x_gpio, "pxa-gpio", NULL),
 };
 void __init pxa95x_init_irq(void)
 {
        pxa_init_irq(96, NULL);
-        pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
 }
 /*
@@ -248,6 +249,7 @@ void __init pxa95x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 }
 static struct platform_device *devices[] __initdata = {
+        &pxa_device_gpio,
        &sa1100_device_rtc,
        &pxa_device_rtc,
        &pxa27x_device_ssp1,
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index f0c05f4d12e..22818c7694a 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -292,8 +292,8 @@ static struct resource smc91x_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
-                .start  = gpio_to_irq(GPIO_ETH_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO_ETH_IRQ),
-                .end    = gpio_to_irq(GPIO_ETH_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO_ETH_IRQ),
                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
        }
 };
@@ -672,7 +672,7 @@ static struct lis3lv02d_platform_data lis3_pdata = {
        .chip_select    = 1,                    \
        .controller_data = (void *) GPIO_ACCEL_CS,      \
        .platform_data  = &lis3_pdata,          \
-        .irq            = gpio_to_irq(GPIO_ACCEL_IRQ),  \
+        .irq            = PXA_GPIO_TO_IRQ(GPIO_ACCEL_IRQ),      \
 }
 #define SPI_DAC7512     \
@@ -956,7 +956,7 @@ static struct eeti_ts_platform_data eeti_ts_pdata = {
 static struct i2c_board_info raumfeld_controller_i2c_board_info __initdata = {
        .type   = "eeti_ts",
        .addr   = 0x0a,
-        .irq    = gpio_to_irq(GPIO_TOUCH_IRQ),
+        .irq    = PXA_GPIO_TO_IRQ(GPIO_TOUCH_IRQ),
        .platform_data = &eeti_ts_pdata,
 };
@@ -1093,6 +1093,7 @@ MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -1104,6 +1105,7 @@ MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -1115,5 +1117,6 @@ MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
        .init_irq       = pxa3xx_init_irq,
        .handle_irq     = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index 01e9d643394..c8497b00cdf 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -81,14 +81,17 @@ static void do_hw_reset(void)
        OSMR3 = OSCR + 368640;  /* ... in 100 ms */
 }
-void arch_reset(char mode, const char *cmd)
+void pxa_restart(char mode, const char *cmd)
 {
+        local_irq_disable();
+        local_fiq_disable();
        clear_reset_status(RESET_STATUS_ALL);
        switch (mode) {
        case 's':
                /* Jump into ROM at address 0 */
-                cpu_reset(0);
+                soft_restart(0);
                break;
        case 'g':
                do_gpio_reset();
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index fc2c1e05af9..0fe354efb93 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -96,8 +96,8 @@ static struct resource smc91x_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)),
+                .start  = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
-                .end    = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO97)),
+                .end    = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        }
 };
@@ -502,7 +502,7 @@ static struct i2c_board_info saar_i2c_info[] = {
                .type           = "da9034",
                .addr           = 0x34,
                .platform_data  = &saar_da9034_info,
-                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+                .irq            = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
        },
 };
@@ -602,4 +602,5 @@ MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
        .handle_irq       = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = saar_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
index 3e999e308a2..febc809ed5a 100644
--- a/arch/arm/mach-pxa/saarb.c
+++ b/arch/arm/mach-pxa/saarb.c
@@ -92,7 +92,7 @@ static struct i2c_board_info saarb_i2c_info[] = {
                .type           = "88PM860x",
                .addr           = 0x34,
                .platform_data  = &saarb_pm8607_info,
-                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+                .irq            = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
        },
 };
@@ -111,5 +111,6 @@ MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)")
        .handle_irq     = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = saarb_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 785880f67b6..8d5168d253a 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -907,24 +907,24 @@ static int __devinit sharpsl_pm_probe(struct platform_device *pdev)
        gpio_direction_input(sharpsl_pm.machinfo->gpio_batlock);
        /* Register interrupt handlers */
-        if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
+        if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) {
-                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin));
+                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin));
        }
-        if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
+        if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) {
-                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock));
+                dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock));
        }
        if (sharpsl_pm.machinfo->gpio_fatal) {
-                if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
+                if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) {
-                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal));
+                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal));
                }
        }
        if (sharpsl_pm.machinfo->batfull_irq) {
                /* Register interrupt handler. */
-                if (request_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
+                if (request_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) {
-                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull));
+                        dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull));
                }
        }
@@ -953,14 +953,14 @@ static int sharpsl_pm_remove(struct platform_device *pdev)
        led_trigger_unregister_simple(sharpsl_charge_led_trigger);
-        free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
+        free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_acin), sharpsl_ac_isr);
-        free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
+        free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batlock), sharpsl_fatal_isr);
        if (sharpsl_pm.machinfo->gpio_fatal)
-                free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
+                free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_fatal), sharpsl_fatal_isr);
        if (sharpsl_pm.machinfo->batfull_irq)
-                free_irq(IRQ_GPIO(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
+                free_irq(PXA_GPIO_TO_IRQ(sharpsl_pm.machinfo->gpio_batfull), sharpsl_chrg_full_isr);
        gpio_free(sharpsl_pm.machinfo->gpio_batlock);
        gpio_free(sharpsl_pm.machinfo->gpio_batfull);
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 953a9195f9e..abf355d0c92 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -552,7 +552,7 @@ static struct spi_board_info spitz_spi_devices[] = {
                .chip_select            = 0,
                .platform_data          = &spitz_ads7846_info,
                .controller_data        = &spitz_ads7846_chip,
-                .irq                    = gpio_to_irq(SPITZ_GPIO_TP_INT),
+                .irq                    = PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT),
        }, {
                .modalias               = "corgi-lcd",
                .max_speed_hz           = 50000,
@@ -926,7 +926,7 @@ static inline void spitz_i2c_init(void) {}
 ******************************************************************************/
 static void spitz_poweroff(void)
 {
-        arm_machine_restart('g', NULL);
+        pxa_restart('g', NULL);
 }
 static void spitz_restart(char mode, const char *cmd)
@@ -943,7 +943,6 @@ static void __init spitz_init(void)
 {
        init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
        pm_power_off = spitz_poweroff;
-        arm_pm_restart = spitz_restart;
        PMCR = 0x00;
@@ -982,33 +981,39 @@ static void __init spitz_fixup(struct tag *tags, char **cmdline,
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
+        .restart_mode   = 'g',
        .fixup          = spitz_fixup,
        .map_io         = pxa27x_map_io,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .init_machine   = spitz_init,
        .timer          = &pxa_timer,
+        .restart        = spitz_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
+        .restart_mode   = 'g',
        .fixup          = spitz_fixup,
        .map_io         = pxa27x_map_io,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .init_machine   = spitz_init,
        .timer          = &pxa_timer,
+        .restart        = spitz_restart,
 MACHINE_END
 #endif
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
+        .restart_mode   = 'g',
        .fixup          = spitz_fixup,
        .map_io         = pxa27x_map_io,
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .init_machine   = spitz_init,
        .timer          = &pxa_timer,
+        .restart        = spitz_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 094279aefe9..34cbdac5152 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -15,6 +15,7 @@
 #include <linux/kernel.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/gpio-pxa.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/apm-emulation.h>
@@ -41,6 +42,7 @@ static int spitz_last_ac_status;
 static struct gpio spitz_charger_gpios[] = {
        { SPITZ_GPIO_KEY_INT,   GPIOF_IN, "Keyboard Interrupt" },
        { SPITZ_GPIO_SYNC,      GPIOF_IN, "Sync" },
+        { SPITZ_GPIO_AC_IN,     GPIOF_IN, "Charger Detection" },
        { SPITZ_GPIO_ADC_TEMP_ON, GPIOF_OUT_INIT_LOW, "ADC Temp On" },
        { SPITZ_GPIO_JK_B,        GPIOF_OUT_INIT_LOW, "JK B" },
        { SPITZ_GPIO_CHRG_ON,     GPIOF_OUT_INIT_LOW, "Charger On" },
@@ -169,14 +171,19 @@ static int spitz_should_wakeup(unsigned int resume_on_alarm)
 static unsigned long spitz_charger_wakeup(void)
 {
-        return (~GPLR0 & GPIO_bit(SPITZ_GPIO_KEY_INT)) | (GPLR0 & GPIO_bit(SPITZ_GPIO_SYNC));
+        unsigned long ret;
+        ret = (!gpio_get_value(SPITZ_GPIO_KEY_INT)
+                << GPIO_bit(SPITZ_GPIO_KEY_INT))
+                | (!gpio_get_value(SPITZ_GPIO_SYNC)
+                << GPIO_bit(SPITZ_GPIO_SYNC));
+        return ret;
 }
 unsigned long spitzpm_read_devdata(int type)
 {
        switch (type) {
        case SHARPSL_STATUS_ACIN:
-                return (((~GPLR(SPITZ_GPIO_AC_IN)) & GPIO_bit(SPITZ_GPIO_AC_IN)) != 0);
+                return !gpio_get_value(SPITZ_GPIO_AC_IN);
        case SHARPSL_STATUS_LOCK:
                return gpio_get_value(sharpsl_pm.machinfo->gpio_batlock);
        case SHARPSL_STATUS_CHRGFULL:
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 4c9a48bef56..b0656e158d9 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -376,7 +376,7 @@ static struct spi_board_info spi_board_info[] __initdata = {
                .bus_num = 1,
                .chip_select = 0,
                .controller_data = &staccel_chip_info,
-                .irq = IRQ_GPIO(96),
+                .irq = PXA_GPIO_TO_IRQ(96),
        }, {
                .modalias = "cc2420",
                .max_speed_hz = 6500000,
@@ -546,7 +546,7 @@ static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = {
                .type = "da9030",
                .addr = 0x49,
                .platform_data = &imote2_da9030_pdata,
-                .irq = gpio_to_irq(1),
+                .irq = PXA_GPIO_TO_IRQ(1),
        },
 };
@@ -560,18 +560,18 @@ static struct i2c_board_info __initdata imote2_i2c_board_info[] = {
                /* Through a nand gate - Also beware, on V2 sensor board the
                 * pull up resistors are missing.
                 */
-                .irq = IRQ_GPIO(99),
+                .irq = PXA_GPIO_TO_IRQ(99),
        }, { /* ITS400 Sensor board only */
                .type = "tsl2561",
                .addr = 0x49,
                /* Through a nand gate - Also beware, on V2 sensor board the
                 * pull up resistors are missing.
                 */
-                .irq = IRQ_GPIO(99),
+                .irq = PXA_GPIO_TO_IRQ(99),
        }, { /* ITS400 Sensor board only */
                .type = "tmp175",
                .addr = 0x4A,
-                .irq = IRQ_GPIO(96),
+                .irq = PXA_GPIO_TO_IRQ(96),
        }, { /* IMB400 Multimedia board */
                .type = "wm8940",
                .addr = 0x1A,
@@ -593,10 +593,16 @@ static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = {
        .udc_command            = sg2_udc_command,
 };
+static struct platform_device imote2_audio_device = {
+        .name = "imote2-audio",
+        .id   = -1,
+};
 static struct platform_device *imote2_devices[] = {
        &stargate2_flash_device,
        &imote2_leds,
        &sht15,
+        &imote2_audio_device,
 };
 static void __init imote2_init(void)
@@ -661,8 +667,8 @@ static struct resource smc91x_resources[] = {
                .flags = IORESOURCE_MEM,
        },
        [1] = {
-                .start = IRQ_GPIO(40),
+                .start = PXA_GPIO_TO_IRQ(40),
-                .end = IRQ_GPIO(40),
+                .end = PXA_GPIO_TO_IRQ(40),
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        }
 };
@@ -707,7 +713,7 @@ static int stargate2_mci_init(struct device *dev,
        }
        gpio_direction_input(SG2_GPIO_nSD_DETECT);
-        err = request_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT),
+        err = request_irq(PXA_GPIO_TO_IRQ(SG2_GPIO_nSD_DETECT),
                          stargate2_detect_int,
                          IRQ_TYPE_EDGE_BOTH,
                          "MMC card detect",
@@ -738,7 +744,7 @@ static void stargate2_mci_setpower(struct device *dev, unsigned int vdd)
 static void stargate2_mci_exit(struct device *dev, void *data)
 {
-        free_irq(IRQ_GPIO(SG2_GPIO_nSD_DETECT), data);
+        free_irq(PXA_GPIO_TO_IRQ(SG2_GPIO_nSD_DETECT), data);
        gpio_free(SG2_SD_POWER_ENABLE);
        gpio_free(SG2_GPIO_nSD_DETECT);
 }
@@ -913,7 +919,7 @@ static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = {
                .type = "da9030",
                .addr = 0x49,
                .platform_data = &stargate2_da9030_pdata,
-                .irq = gpio_to_irq(1),
+                .irq = PXA_GPIO_TO_IRQ(1),
        },
 };
@@ -938,18 +944,18 @@ static struct i2c_board_info __initdata stargate2_i2c_board_info[] = {
                /* Through a nand gate - Also beware, on V2 sensor board the
                 * pull up resistors are missing.
                 */
-                .irq = IRQ_GPIO(99),
+                .irq = PXA_GPIO_TO_IRQ(99),
        }, { /* ITS400 Sensor board only */
                .type = "tsl2561",
                .addr = 0x49,
                /* Through a nand gate - Also beware, on V2 sensor board the
                 * pull up resistors are missing.
                 */
-                .irq = IRQ_GPIO(99),
+                .irq = PXA_GPIO_TO_IRQ(99),
        }, { /* ITS400 Sensor board only */
                .type = "tmp175",
                .addr = 0x4A,
-                .irq = IRQ_GPIO(96),
+                .irq = PXA_GPIO_TO_IRQ(96),
        },
 };
@@ -1005,6 +1011,7 @@ MACHINE_START(INTELMOTE2, "IMOTE 2")
        .timer          = &pxa_timer,
        .init_machine   = imote2_init,
        .atag_offset    = 0x100,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
@@ -1017,5 +1024,6 @@ MACHINE_START(STARGATE2, "Stargate 2")
        .timer = &pxa_timer,
        .init_machine = stargate2_init,
        .atag_offset = 0x100,
+        .restart        = pxa_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index ad47bb98f30..9fb38e80e07 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -85,8 +85,8 @@ static struct resource smc91x_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)),
+                .start  = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO47)),
-                .end    = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO47)),
+                .end    = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO47)),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        }
 };
@@ -495,4 +495,5 @@ MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
        .handle_irq       = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = tavorevb_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
index fd569167302..f7d9305cfd7 100644
--- a/arch/arm/mach-pxa/tavorevb3.c
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -101,7 +101,7 @@ static struct i2c_board_info evb3_i2c_info[] = {
                .type           = "88PM860x",
                .addr           = 0x34,
                .platform_data  = &evb3_pm8607_info,
-                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+                .irq            = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
        },
 };
@@ -132,4 +132,5 @@ MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
        .handle_irq       = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = evb3_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index de684701449..b503049d6d2 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -16,7 +16,6 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/clockchips.h>
-#include <linux/sched.h>
 #include <asm/div64.h>
 #include <asm/mach/irq.h>
@@ -32,18 +31,10 @@
 * long as there is always less than 582 seconds between successive
 * calls to sched_clock() which should always be the case in practice.
 */
-static DEFINE_CLOCK_DATA(cd);
-unsigned long long notrace sched_clock(void)
+static u32 notrace pxa_read_sched_clock(void)
 {
-        u32 cyc = OSCR;
+        return OSCR;
-        return cyc_to_sched_clock(&cd, cyc, (u32)~0);
-}
-static void notrace pxa_update_sched_clock(void)
-{
-        u32 cyc = OSCR;
-        update_sched_clock(&cd, cyc, (u32)~0);
 }
@@ -119,7 +110,7 @@ static void __init pxa_timer_init(void)
        OIER = 0;
        OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
-        init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);
+        setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
        clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
        ckevt_pxa_osmr0.max_delta_ns =
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 402b0c96613..4d4eb60bad1 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -404,8 +404,8 @@ static struct pda_power_pdata tosa_power_data = {
 static struct resource tosa_power_resource[] = {
        {
                .name           = "ac",
-                .start          = gpio_to_irq(TOSA_GPIO_AC_IN),
+                .start          = PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN),
-                .end            = gpio_to_irq(TOSA_GPIO_AC_IN),
+                .end            = PXA_GPIO_TO_IRQ(TOSA_GPIO_AC_IN),
                .flags          = IORESOURCE_IRQ |
                                  IORESOURCE_IRQ_HIGHEDGE |
                                  IORESOURCE_IRQ_LOWEDGE,
@@ -889,6 +889,11 @@ static struct platform_device wm9712_device = {
        .id     = -1,
 };
+static struct platform_device tosa_audio_device = {
+        .name   = "tosa-audio",
+        .id     = -1,
+};
 static struct platform_device *devices[] __initdata = {
        &tosascoop_device,
        &tosascoop_jc_device,
@@ -901,11 +906,12 @@ static struct platform_device *devices[] __initdata = {
        &sharpsl_rom_device,
        &wm9712_device,
        &tosa_gpio_vbus,
+        &tosa_audio_device,
 };
 static void tosa_poweroff(void)
 {
-        arm_machine_restart('g', NULL);
+        pxa_restart('g', NULL);
 }
 static void tosa_restart(char mode, const char *cmd)
@@ -935,7 +941,6 @@ static void __init tosa_init(void)
        init_gpio_reset(TOSA_GPIO_ON_RESET, 0, 0);
        pm_power_off = tosa_poweroff;
-        arm_pm_restart = tosa_restart;
        PCFR |= PCFR_OPDE;
@@ -970,6 +975,7 @@ static void __init fixup_tosa(struct tag *tags, char **cmdline,
 }
 MACHINE_START(TOSA, "SHARP Tosa")
+        .restart_mode   = 'g',
        .fixup          = fixup_tosa,
        .map_io         = pxa25x_map_io,
        .nr_irqs        = TOSA_NR_IRQS,
@@ -977,4 +983,5 @@ MACHINE_START(TOSA, "SHARP Tosa")
        .handle_irq       = pxa25x_handle_irq,
        .init_machine   = tosa_init,
        .timer          = &pxa_timer,
+        .restart        = tosa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 1aaed2b17e1..0f30af617d8 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -561,6 +561,7 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
 MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
@@ -571,4 +572,5 @@ MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 242ddae332d..023d6ca789d 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -422,8 +422,8 @@ static struct resource smc91x_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
-                .start  = gpio_to_irq(VIPER_ETH_GPIO),
+                .start  = PXA_GPIO_TO_IRQ(VIPER_ETH_GPIO),
-                .end    = gpio_to_irq(VIPER_ETH_GPIO),
+                .end    = PXA_GPIO_TO_IRQ(VIPER_ETH_GPIO),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        },
        [2] = {
@@ -546,7 +546,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        /* External UARTs */
        {
                .mapbase        = VIPER_UARTA_PHYS,
-                .irq            = gpio_to_irq(VIPER_UARTA_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(VIPER_UARTA_GPIO),
                .irqflags       = IRQF_TRIGGER_RISING,
                .uartclk        = 1843200,
                .regshift       = 1,
@@ -556,7 +556,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        },
        {
                .mapbase        = VIPER_UARTB_PHYS,
-                .irq            = gpio_to_irq(VIPER_UARTB_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(VIPER_UARTB_GPIO),
                .irqflags       = IRQF_TRIGGER_RISING,
                .uartclk        = 1843200,
                .regshift       = 1,
@@ -596,8 +596,8 @@ static struct resource isp116x_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [2] = {
-                .start  = gpio_to_irq(VIPER_USB_GPIO),
+                .start  = PXA_GPIO_TO_IRQ(VIPER_USB_GPIO),
-                .end    = gpio_to_irq(VIPER_USB_GPIO),
+                .end    = PXA_GPIO_TO_IRQ(VIPER_USB_GPIO),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        },
 };
@@ -998,4 +998,5 @@ MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
        .handle_irq     = pxa25x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = viper_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index ca0c6615028..1f5cfa96f6d 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -395,8 +395,8 @@ static struct resource vpac270_dm9000_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        [2] = {
-                .start  = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ),
+                .start  = PXA_GPIO_TO_IRQ(GPIO114_VPAC270_ETH_IRQ),
-                .end    = IRQ_GPIO(GPIO114_VPAC270_ETH_IRQ),
+                .end    = PXA_GPIO_TO_IRQ(GPIO114_VPAC270_ETH_IRQ),
                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
        },
 };
@@ -433,7 +433,7 @@ static pxa2xx_audio_ops_t vpac270_ac97_pdata = {
 };
 static struct ucb1400_pdata vpac270_ucb1400_pdata = {
-        .irq            = IRQ_GPIO(GPIO113_VPAC270_TS_IRQ),
+        .irq            = PXA_GPIO_TO_IRQ(GPIO113_VPAC270_TS_IRQ),
 };
 static struct platform_device vpac270_ucb1400_device = {
@@ -610,8 +610,8 @@ static struct resource vpac270_ide_resources[] = {
               .flags   = IORESOURCE_DMA
        },
        [3] = { /* IDE IRQ pin */
-               .start   = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ),
+               .start   = PXA_GPIO_TO_IRQ(GPIO36_VPAC270_IDE_IRQ),
-               .end     = gpio_to_irq(GPIO36_VPAC270_IDE_IRQ),
+               .end     = PXA_GPIO_TO_IRQ(GPIO36_VPAC270_IDE_IRQ),
               .flags   = IORESOURCE_IRQ
        }
 };
@@ -721,5 +721,6 @@ MACHINE_START(VPAC270, "Voipac PXA270")
        .init_irq       = pxa27x_init_irq,
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
-        .init_machine   = vpac270_init
+        .init_machine   = vpac270_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index 70e1730ef28..4bbe9a36fe7 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -185,5 +185,6 @@ MACHINE_START(XCEP, "Iskratel XCEP")
        .init_irq       = pxa25x_init_irq,
        .handle_irq     = pxa25x_handle_irq,
        .timer          = &pxa_timer,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index ead32c90fec..b6476848b56 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -573,7 +573,7 @@ static struct spi_board_info spi_board_info[] __initdata = {
        .modalias               = "libertas_spi",
        .platform_data          = &z2_lbs_pdata,
        .controller_data        = &z2_lbs_chip_info,
-        .irq                    = gpio_to_irq(GPIO36_ZIPITZ2_WIFI_IRQ),
+        .irq                    = PXA_GPIO_TO_IRQ(GPIO36_ZIPITZ2_WIFI_IRQ),
        .max_speed_hz           = 13000000,
        .bus_num                = 1,
        .chip_select            = 0,
@@ -725,4 +725,5 @@ MACHINE_START(ZIPIT2, "Zipit Z2")
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = z2_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 498b83b089f..a4dd1c34705 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -233,7 +233,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
        { /* COM1 */
                .mapbase        = 0x10000000,
-                .irq            = gpio_to_irq(ZEUS_UARTA_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
                .irqflags       = IRQF_TRIGGER_RISING,
                .uartclk        = 14745600,
                .regshift       = 1,
@@ -242,7 +242,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        },
        { /* COM2 */
                .mapbase        = 0x10800000,
-                .irq            = gpio_to_irq(ZEUS_UARTB_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
                .irqflags       = IRQF_TRIGGER_RISING,
                .uartclk        = 14745600,
                .regshift       = 1,
@@ -251,7 +251,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        },
        { /* COM3 */
                .mapbase        = 0x11000000,
-                .irq            = gpio_to_irq(ZEUS_UARTC_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
                .irqflags       = IRQF_TRIGGER_RISING,
                .uartclk        = 14745600,
                .regshift       = 1,
@@ -260,7 +260,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
        },
        { /* COM4 */
                .mapbase        = 0x11800000,
-                .irq            = gpio_to_irq(ZEUS_UARTD_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
                .irqflags       = IRQF_TRIGGER_RISING,
                .uartclk        = 14745600,
                .regshift       = 1,
@@ -321,8 +321,8 @@ static struct resource zeus_dm9k0_resource[] = {
                .flags = IORESOURCE_MEM
        },
        [2] = {
-                .start = gpio_to_irq(ZEUS_ETH0_GPIO),
+                .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
-                .end   = gpio_to_irq(ZEUS_ETH0_GPIO),
+                .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
        },
 };
@@ -339,8 +339,8 @@ static struct resource zeus_dm9k1_resource[] = {
                .flags = IORESOURCE_MEM,
        },
        [2] = {
-                .start = gpio_to_irq(ZEUS_ETH1_GPIO),
+                .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
-                .end   = gpio_to_irq(ZEUS_ETH1_GPIO),
+                .end   = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
        },
 };
@@ -423,7 +423,7 @@ static struct spi_board_info zeus_spi_board_info[] = {
        [0] = {
                .modalias       = "mcp2515",
                .platform_data  = &zeus_mcp2515_pdata,
-                .irq            = gpio_to_irq(ZEUS_CAN_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
                .max_speed_hz   = 1*1000*1000,
                .bus_num        = 3,
                .mode           = SPI_MODE_0,
@@ -753,7 +753,7 @@ static struct i2c_board_info __initdata zeus_i2c_devices[] = {
        {
                I2C_BOARD_INFO("pca9535",       0x20),
                .platform_data  = &zeus_pca953x_pdata[2],
-                .irq            = gpio_to_irq(ZEUS_EXTGPIO_GPIO),
+                .irq            = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
        },
        { I2C_BOARD_INFO("lm75a",       0x48) },
        { I2C_BOARD_INFO("24c01",       0x50) },
@@ -911,5 +911,6 @@ MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
        .handle_irq     = pxa27x_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = zeus_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 6c39c332841..98eec80623e 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -408,8 +408,8 @@ static void __init zylonite_init(void)
         * Note: We depend that the bootloader set
         * the correct value to MSC register for SMC91x.
         */
-        smc91x_resources[1].start = gpio_to_irq(gpio_eth_irq);
+        smc91x_resources[1].start = PXA_GPIO_TO_IRQ(gpio_eth_irq);
-        smc91x_resources[1].end   = gpio_to_irq(gpio_eth_irq);
+        smc91x_resources[1].end   = PXA_GPIO_TO_IRQ(gpio_eth_irq);
        platform_device_register(&smc91x_device);
        pxa_set_ac97_info(NULL);
@@ -430,4 +430,5 @@ MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
        .handle_irq     = pxa3xx_handle_irq,
        .timer          = &pxa_timer,
        .init_machine   = zylonite_init,
+        .restart        = pxa_restart,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 93c64d8d7de..86e59c043de 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -231,12 +231,12 @@ static struct i2c_board_info zylonite_i2c_board_info[] = {
                .type           = "pca9539",
                .addr           = 0x74,
                .platform_data  = &gpio_exp[0],
-                .irq            = IRQ_GPIO(18),
+                .irq            = PXA_GPIO_TO_IRQ(18),
        }, {
                .type           = "pca9539",
                .addr           = 0x75,
                .platform_data  = &gpio_exp[1],
-                .irq            = IRQ_GPIO(19),
+                .irq            = PXA_GPIO_TO_IRQ(19),
        },
 };
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index dba6d0c1fc1..c593be428b8 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -12,6 +12,8 @@ config REALVIEW_EB_A9MP
        bool "Support Multicore Cortex-A9 Tile"
        depends on MACH_REALVIEW_EB
        select CPU_V7
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
        help
          Enable support for the Cortex-A9MPCore tile fitted to the
          Realview(R) Emulation Baseboard platform.
@@ -21,6 +23,8 @@ config REALVIEW_EB_ARM11MP
        depends on MACH_REALVIEW_EB
        select CPU_V6K
        select ARCH_HAS_BARRIERS if SMP
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
        help
          Enable support for the ARM11MPCore tile fitted to the Realview(R)
          Emulation Baseboard platform.
@@ -39,6 +43,8 @@ config MACH_REALVIEW_PB11MP
        select CPU_V6K
        select ARM_GIC
        select HAVE_PATA_PLATFORM
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
        select ARCH_HAS_BARRIERS if SMP
        help
          Include support for the ARM(R) RealView(R) Platform Baseboard for
@@ -51,6 +57,7 @@ config MACH_REALVIEW_PB1176
        select CPU_V6
        select ARM_GIC
        select HAVE_TCM
+        select MIGHT_HAVE_CACHE_L2X0
        help
          Include support for the ARM(R) RealView(R) Platform Baseboard for
          ARM1176JZF-S.
@@ -78,6 +85,8 @@ config MACH_REALVIEW_PBX
        bool "Support RealView(R) Platform Baseboard Explore"
        select ARM_GIC
        select HAVE_PATA_PLATFORM
+        select HAVE_SMP
+        select MIGHT_HAVE_CACHE_L2X0
        select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
        select ZONE_DMA if SPARSEMEM
        help
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index d5ed5d4f77d..acd329afc3a 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 47259c89a75..735b57aaf2d 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -65,6 +65,5 @@ extern int realview_usb_register(struct resource *res);
 extern void realview_init_early(void);
 extern void realview_fixup(struct tag *tags, char **from,
                           struct meminfo *meminfo);
-extern void (*realview_reset)(char);
 #endif
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
index 4071164aeba..e8a5179c265 100644
--- a/arch/arm/mach-realview/include/mach/entry-macro.S
+++ b/arch/arm/mach-realview/include/mach/entry-macro.S
@@ -7,8 +7,6 @@
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
                .macro  disable_fiq
                .endm
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h
index 6657ff23116..471b671159c 100644
--- a/arch/arm/mach-realview/include/mach/system.h
+++ b/arch/arm/mach-realview/include/mach/system.h
@@ -21,12 +21,6 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-void (*realview_reset)(char mode);
 static inline void arch_idle(void)
 {
        /*
@@ -36,15 +30,4 @@ static inline void arch_idle(void)
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        /*
-         * To reset, we hit the on-board reset register
-         * in the system FPGA
-         */
-        if (realview_reset)
-                realview_reset(mode);
-        dsb();
-}
 #endif
diff --git a/arch/arm/mach-realview/include/mach/vmalloc.h b/arch/arm/mach-realview/include/mach/vmalloc.h
deleted file mode 100644
index a2a4c686140..00000000000
--- a/arch/arm/mach-realview/include/mach/vmalloc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  arch/arm/mach-realview/include/mach/vmalloc.h
- *
- *  Copyright (C) 2003 ARM Limited
- *  Copyright (C) 2000 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#define VMALLOC_END             0xf8000000UL
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index e83c654a58d..17c878ddbc7 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -17,7 +17,6 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/smp_scu.h>
-#include <asm/unified.h>
 #include <mach/board-eb.h>
 #include <mach/board-pb11mp.h>
@@ -75,6 +74,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
         * until it receives a soft interrupt, and then the
         * secondary CPU branches to this address.
         */
-        __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
+        __raw_writel(virt_to_phys(versatile_secondary_startup),
                     __io_address(REALVIEW_SYS_FLAGSSET));
 }
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 026c66ad7ec..e6296211776 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
@@ -91,8 +91,8 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
 static struct map_desc realview_eb11mp_io_desc[] __initdata = {
        {
-                .virtual        = IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_EB11MP_SCU_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_EB11MP_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_EB11MP_SCU_BASE),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
        }, {
@@ -117,17 +117,14 @@ static void __init realview_eb_map_io(void)
 static struct pl061_platform_data gpio0_plat_data = {
        .gpio_base      = 0,
-        .irq_base       = -1,
 };
 static struct pl061_platform_data gpio1_plat_data = {
        .gpio_base      = 8,
-        .irq_base       = -1,
 };
 static struct pl061_platform_data gpio2_plat_data = {
        .gpio_base      = 16,
-        .irq_base       = -1,
 };
 static struct pl022_ssp_controller ssp0_plat_data = {
@@ -415,7 +412,7 @@ static struct sys_timer realview_eb_timer = {
        .init           = realview_eb_timer_init,
 };
-static void realview_eb_reset(char mode)
+static void realview_eb_restart(char mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
@@ -427,6 +424,7 @@ static void realview_eb_reset(char mode)
        __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
        if (core_tile_eb11mp())
                __raw_writel(0x0008, reset_ctrl);
+        dsb();
 }
 static void __init realview_eb_init(void)
@@ -458,7 +456,6 @@ static void __init realview_eb_init(void)
 #ifdef CONFIG_LEDS
        leds_event = realview_leds_event;
 #endif
-        realview_reset = realview_eb_reset;
 }
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
@@ -469,8 +466,10 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
        .timer          = &realview_eb_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_eb_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
 #endif
+        .restart        = realview_eb_restart,
 MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index c057540ec77..e4abe94fb11 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
@@ -113,17 +113,14 @@ static void __init realview_pb1176_map_io(void)
 static struct pl061_platform_data gpio0_plat_data = {
        .gpio_base      = 0,
-        .irq_base       = -1,
 };
 static struct pl061_platform_data gpio1_plat_data = {
        .gpio_base      = 8,
-        .irq_base       = -1,
 };
 static struct pl061_platform_data gpio2_plat_data = {
        .gpio_base      = 16,
-        .irq_base       = -1,
 };
 static struct pl022_ssp_controller ssp0_plat_data = {
@@ -336,12 +333,13 @@ static struct sys_timer realview_pb1176_timer = {
        .init           = realview_pb1176_timer_init,
 };
-static void realview_pb1176_reset(char mode)
+static void realview_pb1176_restart(char mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
        __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
        __raw_writel(REALVIEW_PB1176_SYS_SOFT_RESET, reset_ctrl);
+        dsb();
 }
 static void realview_pb1176_fixup(struct tag *tags, char **from,
@@ -381,7 +379,6 @@ static void __init realview_pb1176_init(void)
 #ifdef CONFIG_LEDS
        leds_event = realview_leds_event;
 #endif
-        realview_reset = realview_pb1176_reset;
 }
 MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
@@ -392,8 +389,10 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
        .timer          = &realview_pb1176_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pb1176_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
 #endif
+        .restart        = realview_pb1176_restart,
 MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 671ad6d6ff0..127a3fd42ab 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
@@ -112,17 +112,14 @@ static void __init realview_pb11mp_map_io(void)
 static struct pl061_platform_data gpio0_plat_data = {
        .gpio_base      = 0,
-        .irq_base       = -1,
 };
 static struct pl061_platform_data gpio1_plat_data = {
        .gpio_base      = 8,
-        .irq_base       = -1,
 };
 static struct pl061_platform_data gpio2_plat_data = {
        .gpio_base      = 16,
-        .irq_base       = -1,
 };
 static struct pl022_ssp_controller ssp0_plat_data = {
@@ -315,7 +312,7 @@ static struct sys_timer realview_pb11mp_timer = {
        .init           = realview_pb11mp_timer_init,
 };
-static void realview_pb11mp_reset(char mode)
+static void realview_pb11mp_restart(char mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
@@ -327,6 +324,7 @@ static void realview_pb11mp_reset(char mode)
        __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
        __raw_writel(0x0000, reset_ctrl);
        __raw_writel(0x0004, reset_ctrl);
+        dsb();
 }
 static void __init realview_pb11mp_init(void)
@@ -355,7 +353,6 @@ static void __init realview_pb11mp_init(void)
 #ifdef CONFIG_LEDS
        leds_event = realview_leds_event;
 #endif
-        realview_reset = realview_pb11mp_reset;
 }
 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
@@ -366,8 +363,10 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
        .timer          = &realview_pb11mp_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pb11mp_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
 #endif
+        .restart        = realview_pb11mp_restart,
 MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index cbf22df4ad5..25b2e59296f 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -21,7 +21,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
@@ -102,17 +102,14 @@ static void __init realview_pba8_map_io(void)
 static struct pl061_platform_data gpio0_plat_data = {
        .gpio_base      = 0,
-        .irq_base       = -1,
 };
 static struct pl061_platform_data gpio1_plat_data = {
        .gpio_base      = 8,
-        .irq_base       = -1,
 };
 static struct pl061_platform_data gpio2_plat_data = {
        .gpio_base      = 16,
-        .irq_base       = -1,
 };
 static struct pl022_ssp_controller ssp0_plat_data = {
@@ -271,7 +268,7 @@ static struct sys_timer realview_pba8_timer = {
        .init           = realview_pba8_timer_init,
 };
-static void realview_pba8_reset(char mode)
+static void realview_pba8_restart(char mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
@@ -283,6 +280,7 @@ static void realview_pba8_reset(char mode)
        __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
        __raw_writel(0x0000, reset_ctrl);
        __raw_writel(0x0004, reset_ctrl);
+        dsb();
 }
 static void __init realview_pba8_init(void)
@@ -305,7 +303,6 @@ static void __init realview_pba8_init(void)
 #ifdef CONFIG_LEDS
        leds_event = realview_leds_event;
 #endif
-        realview_reset = realview_pba8_reset;
 }
 MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
@@ -316,8 +313,10 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
        .timer          = &realview_pba8_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pba8_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
 #endif
+        .restart        = realview_pba8_restart,
 MACHINE_END
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 63c4114afae..ac715645b86 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -20,7 +20,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
@@ -98,8 +98,8 @@ static struct map_desc realview_pbx_io_desc[] __initdata = {
 static struct map_desc realview_local_io_desc[] __initdata = {
        {
-                .virtual        = IO_ADDRESS(REALVIEW_PBX_TILE_GIC_CPU_BASE),
+                .virtual        = IO_ADDRESS(REALVIEW_PBX_TILE_SCU_BASE),
-                .pfn            = __phys_to_pfn(REALVIEW_PBX_TILE_GIC_CPU_BASE),
+                .pfn            = __phys_to_pfn(REALVIEW_PBX_TILE_SCU_BASE),
                .length         = SZ_4K,
                .type           = MT_DEVICE,
        }, {
@@ -124,17 +124,14 @@ static void __init realview_pbx_map_io(void)
 static struct pl061_platform_data gpio0_plat_data = {
        .gpio_base      = 0,
-        .irq_base       = -1,
 };
 static struct pl061_platform_data gpio1_plat_data = {
        .gpio_base      = 8,
-        .irq_base       = -1,
 };
 static struct pl061_platform_data gpio2_plat_data = {
        .gpio_base      = 16,
-        .irq_base       = -1,
 };
 static struct pl022_ssp_controller ssp0_plat_data = {
@@ -339,7 +336,7 @@ static void realview_pbx_fixup(struct tag *tags, char **from,
 #endif
 }
-static void realview_pbx_reset(char mode)
+static void realview_pbx_restart(char mode, const char *cmd)
 {
        void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
        void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
@@ -351,6 +348,7 @@ static void realview_pbx_reset(char mode)
        __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
        __raw_writel(0x00F0, reset_ctrl);
        __raw_writel(0x00F4, reset_ctrl);
+        dsb();
 }
 static void __init realview_pbx_init(void)
@@ -388,7 +386,6 @@ static void __init realview_pbx_init(void)
 #ifdef CONFIG_LEDS
        leds_event = realview_leds_event;
 #endif
-        realview_reset = realview_pbx_reset;
 }
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
@@ -399,8 +396,10 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
        .init_early     = realview_init_early,
        .init_irq       = gic_init_irq,
        .timer          = &realview_pbx_timer,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = realview_pbx_init,
 #ifdef CONFIG_ZONE_DMA
        .dma_zone_size  = SZ_256M,
 #endif
+        .restart        = realview_pbx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h
index 45c7b935dc4..359bab94b6a 100644
--- a/arch/arm/mach-rpc/include/mach/system.h
+++ b/arch/arm/mach-rpc/include/mach/system.h
@@ -7,21 +7,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/hardware/iomd.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        iomd_writeb(0, IOMD_ROMCR0);
-        /*
-         * Jump into the ROM
-         */
-        cpu_reset(0);
-}
diff --git a/arch/arm/mach-rpc/include/mach/vmalloc.h b/arch/arm/mach-rpc/include/mach/vmalloc.h
deleted file mode 100644
index fb700228637..00000000000
--- a/arch/arm/mach-rpc/include/mach/vmalloc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- *  arch/arm/mach-rpc/include/mach/vmalloc.h
- *
- *  Copyright (C) 1997 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#define VMALLOC_END       0xdc000000UL
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index 8559598ab76..3d44a59fc0d 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -24,6 +24,7 @@
 #include <asm/elf.h>
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
+#include <asm/hardware/iomd.h>
 #include <asm/page.h>
 #include <asm/domain.h>
 #include <asm/setup.h>
@@ -214,6 +215,16 @@ static int __init rpc_init(void)
 arch_initcall(rpc_init);
+static void rpc_restart(char mode, const char *cmd)
+{
+        iomd_writeb(0, IOMD_ROMCR0);
+        /*
+         * Jump into the ROM
+         */
+        soft_restart(0);
+}
 extern struct sys_timer ioc_timer;
 MACHINE_START(RISCPC, "Acorn-RiscPC")
@@ -224,4 +235,5 @@ MACHINE_START(RISCPC, "Acorn-RiscPC")
        .map_io         = rpc_map_io,
        .init_irq       = rpc_init_irq,
        .timer          = &ioc_timer,
+        .restart        = rpc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index bc53d2d16d1..ac7b2ad5c40 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -24,7 +24,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/ioport.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-s3c2410/common.h b/arch/arm/mach-s3c2410/common.h
new file mode 100644
index 00000000000..f65dc806296
--- /dev/null
+++ b/arch/arm/mach-s3c2410/common.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Common Header for S3C2410 machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_S3C2410_COMMON_H
+#define __ARCH_ARM_MACH_S3C2410_COMMON_H
+void s3c2410_restart(char mode, const char *cmd);
+#endif /* __ARCH_ARM_MACH_S3C2410_COMMON_H */
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c
index 75189df995a..7dc6c46b5e2 100644
--- a/arch/arm/mach-s3c2410/cpu-freq.c
+++ b/arch/arm/mach-s3c2410/cpu-freq.c
@@ -16,7 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/cpufreq.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
@@ -115,24 +115,25 @@ static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
 };
-static int s3c2410_cpufreq_add(struct sys_device *sysdev)
+static int s3c2410_cpufreq_add(struct device *dev)
 {
        return s3c_cpufreq_register(&s3c2410_cpufreq_info);
 }
-static struct sysdev_driver s3c2410_cpufreq_driver = {
+static struct subsys_interface s3c2410_cpufreq_interface = {
-        .add            = s3c2410_cpufreq_add,
+        .name           = "s3c2410_cpufreq",
+        .subsys         = &s3c2410_subsys,
+        .add_dev        = s3c2410_cpufreq_add,
 };
 static int __init s3c2410_cpufreq_init(void)
 {
-        return sysdev_driver_register(&s3c2410_sysclass,
+        return subsys_interface_register(&s3c2410_cpufreq_interface);
-                                      &s3c2410_cpufreq_driver);
 }
 arch_initcall(s3c2410_cpufreq_init);
-static int s3c2410a_cpufreq_add(struct sys_device *sysdev)
+static int s3c2410a_cpufreq_add(struct device *dev)
 {
        /* alter the maximum freq settings for S3C2410A. If a board knows
         * it only has a maximum of 200, then it should register its own
@@ -143,17 +144,18 @@ static int s3c2410a_cpufreq_add(struct sys_device *sysdev)
        s3c2410_cpufreq_info.max.pclk =  66500000;
        s3c2410_cpufreq_info.name = "s3c2410a";
-        return s3c2410_cpufreq_add(sysdev);
+        return s3c2410_cpufreq_add(dev);
 }
-static struct sysdev_driver s3c2410a_cpufreq_driver = {
+static struct subsys_interface s3c2410a_cpufreq_interface = {
-        .add            = s3c2410a_cpufreq_add,
+        .name           = "s3c2410a_cpufreq",
+        .subsys         = &s3c2410a_subsys,
+        .add_dev        = s3c2410a_cpufreq_add,
 };
 static int __init s3c2410a_cpufreq_init(void)
 {
-        return sysdev_driver_register(&s3c2410a_sysclass,
+        return subsys_interface_register(&s3c2410a_cpufreq_interface);
-                                      &s3c2410a_cpufreq_driver);
 }
 arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index dbe43df8cfe..2afd00014a7 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -14,7 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/serial_core.h>
 #include <mach/map.h>
@@ -132,7 +132,7 @@ static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
        },
 };
-static int __init s3c2410_dma_add(struct sys_device *sysdev)
+static int __init s3c2410_dma_add(struct device *dev)
 {
        s3c2410_dma_init();
        s3c24xx_dma_order_set(&s3c2410_dma_order);
@@ -140,24 +140,28 @@ static int __init s3c2410_dma_add(struct sys_device *sysdev)
 }
 #if defined(CONFIG_CPU_S3C2410)
-static struct sysdev_driver s3c2410_dma_driver = {
+static struct subsys_interface s3c2410_dma_interface = {
-        .add    = s3c2410_dma_add,
+        .name           = "s3c2410_dma",
+        .subsys         = &s3c2410_subsys,
+        .add_dev        = s3c2410_dma_add,
 };
 static int __init s3c2410_dma_drvinit(void)
 {
-        return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
+        return subsys_interface_register(&s3c2410_interface);
 }
 arch_initcall(s3c2410_dma_drvinit);
-static struct sysdev_driver s3c2410a_dma_driver = {
+static struct subsys_interface s3c2410a_dma_interface = {
-        .add    = s3c2410_dma_add,
+        .name           = "s3c2410a_dma",
+        .subsys         = &s3c2410a_subsys,
+        .add_dev        = s3c2410_dma_add,
 };
 static int __init s3c2410a_dma_drvinit(void)
 {
-        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver);
+        return subsys_interface_register(&s3c2410a_dma_interface);
 }
 arch_initcall(s3c2410a_dma_drvinit);
@@ -165,13 +169,15 @@ arch_initcall(s3c2410a_dma_drvinit);
 #if defined(CONFIG_CPU_S3C2442)
 /* S3C2442 DMA contains the same selection table as the S3C2410 */
-static struct sysdev_driver s3c2442_dma_driver = {
+static struct subsys_interface s3c2442_dma_interface = {
-        .add    = s3c2410_dma_add,
+        .name           = "s3c2442_dma",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2410_dma_add,
 };
 static int __init s3c2442_dma_drvinit(void)
 {
-        return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
+        return subsys_interface_register(&s3c2442_dma_interface);
 }
 arch_initcall(s3c2442_dma_drvinit);
diff --git a/arch/arm/mach-s3c2410/include/mach/dma.h b/arch/arm/mach-s3c2410/include/mach/dma.h
index ae8e482b642..acbdfecd418 100644
--- a/arch/arm/mach-s3c2410/include/mach/dma.h
+++ b/arch/arm/mach-s3c2410/include/mach/dma.h
@@ -13,7 +13,7 @@
 #ifndef __ASM_ARCH_DMA_H
 #define __ASM_ARCH_DMA_H __FILE__
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
@@ -202,7 +202,7 @@ struct s3c2410_dma_chan {
        struct s3c2410_dma_buf  *end;           /* end of queue */
        /* system device */
-        struct sys_device       dev;
+        struct device   dev;
 };
 typedef unsigned long dma_device_t;
diff --git a/arch/arm/mach-s3c2410/include/mach/reset.h b/arch/arm/mach-s3c2410/include/mach/reset.h
deleted file mode 100644
index f8c9387b049..00000000000
--- a/arch/arm/mach-s3c2410/include/mach/reset.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/reset.h
- *
- * Copyright (c) 2007 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 CPU reset controls
-*/
-#ifndef __ASM_ARCH_RESET_H
-#define __ASM_ARCH_RESET_H __FILE__
-/* This allows the over-ride of the default reset code
-*/
-extern void (*s3c24xx_reset_hook)(void);
-#endif /* __ASM_ARCH_RESET_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h
deleted file mode 100644
index 6faadcee772..00000000000
--- a/arch/arm/mach-s3c2410/include/mach/system-reset.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/system-reset.h
- *
- * Copyright (c) 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - System define for arch_reset() function
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <mach/hardware.h>
-#include <plat/watchdog-reset.h>
-extern void (*s3c24xx_reset_hook)(void);
-static void
-arch_reset(char mode, const char *cmd)
-{
-        if (mode == 's') {
-                cpu_reset(0);
-        }
-        if (s3c24xx_reset_hook)
-                s3c24xx_reset_hook();
-        arch_wdt_reset();
-        /* we'll take a jump through zero as a poor second */
-        cpu_reset(0);
-}
diff --git a/arch/arm/mach-s3c2410/include/mach/system.h b/arch/arm/mach-s3c2410/include/mach/system.h
index a8cbca6701e..5e215c1a5c8 100644
--- a/arch/arm/mach-s3c2410/include/mach/system.h
+++ b/arch/arm/mach-s3c2410/include/mach/system.h
@@ -15,12 +15,10 @@
 #include <mach/map.h>
 #include <mach/idle.h>
-#include <mach/reset.h>
 #include <mach/regs-clock.h>
 void (*s3c24xx_idle)(void);
-void (*s3c24xx_reset_hook)(void);
 void s3c24xx_default_idle(void)
 {
@@ -54,5 +52,3 @@ static void arch_idle(void)
        else
                s3c24xx_default_idle();
 }
-#include <mach/system-reset.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
deleted file mode 100644
index 7a311e8dddb..00000000000
--- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/vmalloc.h
- *
- * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 79838942b0a..4220cc60de3 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -63,6 +63,8 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
+#include "common.h"
 static struct resource amlm5900_nor_resource = {
                .start = 0x00000000,
                .end   = 0x01000000 - 1,
@@ -241,4 +243,5 @@ MACHINE_START(AML_M5900, "AML_M5900")
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = amlm5900_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index a20ae1ad406..feeaf73933d 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -66,6 +66,7 @@
 #include "usb-simtec.h"
 #include "nor-simtec.h"
+#include "common.h"
 #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
@@ -164,22 +165,6 @@ static struct map_desc bast_iodesc[] __initdata = {
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        }
-};
 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
@@ -187,8 +172,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = bast_serial_clocks,
-                .clocks_size = ARRAY_SIZE(bast_serial_clocks),
        },
        [1] = {
                .hwport      = 1,
@@ -196,8 +179,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = bast_serial_clocks,
-                .clocks_size = ARRAY_SIZE(bast_serial_clocks),
        },
        /* port 2 is not actually used */
        [2] = {
@@ -206,8 +187,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = bast_serial_clocks,
-                .clocks_size = ARRAY_SIZE(bast_serial_clocks),
        }
 };
@@ -662,4 +641,5 @@ MACHINE_START(BAST, "Simtec-BAST")
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = bast_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 05a7d16e59f..41245a60398 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -18,7 +18,7 @@
 #include <linux/memblock.h>
 #include <linux/timer.h>
 #include <linux/init.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -70,6 +70,8 @@
 #include <sound/uda1380.h>
+#include "common.h"
 #define H1940_LATCH             ((void __force __iomem *)0xF8000000)
 #define H1940_PA_LATCH          S3C2410_CS2
@@ -751,4 +753,5 @@ MACHINE_START(H1940, "IPAQ-H1940")
        .init_irq       = h1940_init_irq,
        .init_machine   = h1940_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 1dc3e323441..383d00ca8f6 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -51,6 +51,8 @@
 #include <plat/s3c2410.h>
 #include <plat/udc.h>
+#include "common.h"
 static struct map_desc n30_iodesc[] __initdata = {
        /* nothing here yet */
 };
@@ -591,6 +593,7 @@ MACHINE_START(N30, "Acer-N30")
        .init_machine   = n30_init,
        .init_irq       = s3c24xx_init_irq,
        .map_io         = n30_map_io,
+        .restart        = s3c2410_restart,
 MACHINE_END
 MACHINE_START(N35, "Acer-N35")
@@ -601,4 +604,5 @@ MACHINE_START(N35, "Acer-N35")
        .init_machine   = n30_init,
        .init_irq       = s3c24xx_init_irq,
        .map_io         = n30_map_io,
+        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index f03f3fd9cec..5f1e0eeb38a 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -38,6 +38,8 @@
 #include <plat/iic.h>
 #include <plat/cpu.h>
+#include "common.h"
 static struct map_desc otom11_iodesc[] __initdata = {
  /* Device area */
        { (u32)OTOM_VA_CS8900A_BASE, OTOM_PA_CS8900A_BASE, SZ_16M, MT_DEVICE },
@@ -121,4 +123,5 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
        .init_machine   = otom11_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 45185215625..91c16d9d245 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -28,7 +28,7 @@
 #include <linux/timer.h>
 #include <linux/init.h>
 #include <linux/gpio.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/spi/spi.h>
@@ -62,6 +62,8 @@
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include "common.h"
 static struct map_desc qt2410_iodesc[] __initdata = {
        { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
 };
@@ -350,6 +352,5 @@ MACHINE_START(QT2410, "QT2410")
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = qt2410_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 99c9dfdb71c..bdc27e77287 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -54,6 +54,8 @@
 #include <plat/common-smdk.h>
+#include "common.h"
 static struct map_desc smdk2410_iodesc[] __initdata = {
  /* nothing here yet */
 };
@@ -116,6 +118,5 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = smdk2410_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index e0d0b6fb280..1114666f0ef 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -54,6 +54,8 @@
 #include <linux/mtd/map.h>
 #include <linux/mtd/physmap.h>
+#include "common.h"
 static struct resource tct_hammer_nor_resource = {
                .start = 0x00000000,
                .end   = 0x01000000 - 1,
@@ -151,4 +153,5 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = tct_hammer_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index df47e8e9006..dbe668a803e 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -53,6 +53,7 @@
 #include "usb-simtec.h"
 #include "nor-simtec.h"
+#include "common.h"
 /* macros for virtual address mods for the io space entries */
 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@@ -109,23 +110,6 @@ static struct map_desc vr1000_iodesc[] __initdata = {
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-/* uart clock source(s) */
-static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0.
-        }
-};
 static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
@@ -133,8 +117,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = vr1000_serial_clocks,
-                .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
        },
        [1] = {
                .hwport      = 1,
@@ -142,8 +124,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = vr1000_serial_clocks,
-                .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
        },
        /* port 2 is not actually used */
        [2] = {
@@ -152,9 +132,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = vr1000_serial_clocks,
-                .clocks_size = ARRAY_SIZE(vr1000_serial_clocks),
        }
 };
@@ -405,4 +382,5 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
        .init_machine   = vr1000_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c
index 8338865e11c..c07438bfc99 100644
--- a/arch/arm/mach-s3c2410/pll.c
+++ b/arch/arm/mach-s3c2410/pll.c
@@ -25,7 +25,7 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/list.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -66,30 +66,34 @@ static struct cpufreq_frequency_table pll_vals_12MHz[] = {
    { .frequency = 270000000, .index = PLLVAL(127, 1, 1),  },
 };
-static int s3c2410_plls_add(struct sys_device *dev)
+static int s3c2410_plls_add(struct device *dev)
 {
        return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
 }
-static struct sysdev_driver s3c2410_plls_drv = {
+static struct subsys_interface s3c2410_plls_interface = {
-        .add    = s3c2410_plls_add,
+        .name           = "s3c2410_plls",
+        .subsys         = &s3c2410_subsys,
+        .add_dev        = s3c2410_plls_add,
 };
 static int __init s3c2410_pll_init(void)
 {
-        return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_plls_drv);
+        return subsys_interface_register(&s3c2410_plls_interface);
 }
 arch_initcall(s3c2410_pll_init);
-static struct sysdev_driver s3c2410a_plls_drv = {
+static struct subsys_interface s3c2410a_plls_interface = {
-        .add    = s3c2410_plls_add,
+        .name           = "s3c2410a_plls",
+        .subsys         = &s3c2410a_subsys,
+        .add_dev        = s3c2410_plls_add,
 };
 static int __init s3c2410a_pll_init(void)
 {
-        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_plls_drv);
+        return subsys_interface_register(&s3c2410a_plls_interface);
 }
 arch_initcall(s3c2410a_pll_init);
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 4728f9aa7df..fda5385deff 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -24,7 +24,7 @@
 #include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/time.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/gpio.h>
 #include <linux/io.h>
@@ -111,7 +111,7 @@ struct syscore_ops s3c2410_pm_syscore_ops = {
        .resume         = s3c2410_pm_resume,
 };
-static int s3c2410_pm_add(struct sys_device *dev)
+static int s3c2410_pm_add(struct device *dev)
 {
        pm_cpu_prep = s3c2410_pm_prepare;
        pm_cpu_sleep = s3c2410_cpu_suspend;
@@ -120,52 +120,60 @@ static int s3c2410_pm_add(struct sys_device *dev)
 }
 #if defined(CONFIG_CPU_S3C2410)
-static struct sysdev_driver s3c2410_pm_driver = {
+static struct subsys_interface s3c2410_pm_interface = {
-        .add            = s3c2410_pm_add,
+        .name           = "s3c2410_pm",
+        .subsys         = &s3c2410_subsys,
+        .add_dev        = s3c2410_pm_add,
 };
 /* register ourselves */
 static int __init s3c2410_pm_drvinit(void)
 {
-        return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_pm_driver);
+        return subsys_interface_register(&s3c2410_pm_interface);
 }
 arch_initcall(s3c2410_pm_drvinit);
-static struct sysdev_driver s3c2410a_pm_driver = {
+static struct subsys_interface s3c2410a_pm_interface = {
-        .add            = s3c2410_pm_add,
+        .name           = "s3c2410a_pm",
+        .subsys         = &s3c2410a_subsys,
+        .add_dev        = s3c2410_pm_add,
 };
 static int __init s3c2410a_pm_drvinit(void)
 {
-        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver);
+        return subsys_interface_register(&s3c2410a_pm_interface);
 }
 arch_initcall(s3c2410a_pm_drvinit);
 #endif
 #if defined(CONFIG_CPU_S3C2440)
-static struct sysdev_driver s3c2440_pm_driver = {
+static struct subsys_interface s3c2440_pm_interface = {
-        .add            = s3c2410_pm_add,
+        .name           = "s3c2440_pm",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2410_pm_add,
 };
 static int __init s3c2440_pm_drvinit(void)
 {
-        return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_pm_driver);
+        return subsys_interface_register(&s3c2440_pm_interface);
 }
 arch_initcall(s3c2440_pm_drvinit);
 #endif
 #if defined(CONFIG_CPU_S3C2442)
-static struct sysdev_driver s3c2442_pm_driver = {
+static struct subsys_interface s3c2442_pm_interface = {
-        .add            = s3c2410_pm_add,
+        .name           = "s3c2442_pm",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2410_pm_add,
 };
 static int __init s3c2442_pm_drvinit(void)
 {
-        return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_pm_driver);
+        return subsys_interface_register(&s3c2442_pm_interface);
 }
 arch_initcall(s3c2442_pm_drvinit);
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 3d7ebc557a7..061b6bb1a55 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -18,7 +18,7 @@
 #include <linux/init.h>
 #include <linux/gpio.h>
 #include <linux/clk.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
@@ -42,6 +42,7 @@
 #include <plat/clock.h>
 #include <plat/pll.h>
 #include <plat/pm.h>
+#include <plat/watchdog-reset.h>
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
@@ -123,30 +124,38 @@ static struct clk s3c2410_armclk = {
        .id     = -1,
 };
+static struct clk_lookup s3c2410_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
+};
 void __init s3c2410_init_clocks(int xtal)
 {
        s3c24xx_register_baseclocks(xtal);
        s3c2410_setup_clocks();
        s3c2410_baseclk_add();
        s3c24xx_register_clock(&s3c2410_armclk);
+        clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
 }
-struct sysdev_class s3c2410_sysclass = {
+struct bus_type s3c2410_subsys = {
        .name = "s3c2410-core",
+        .dev_name = "s3c2410-core",
 };
 /* Note, we would have liked to name this s3c2410-core, but we cannot
- * register two sysdev_class with the same name.
+ * register two subsystems with the same name.
 */
-struct sysdev_class s3c2410a_sysclass = {
+struct bus_type s3c2410a_subsys = {
        .name = "s3c2410a-core",
+        .dev_name = "s3c2410a-core",
 };
-static struct sys_device s3c2410_sysdev = {
+static struct device s3c2410_dev = {
-        .cls            = &s3c2410_sysclass,
+        .bus            = &s3c2410_subsys,
 };
-/* need to register class before we actually register the device, and
+/* need to register the subsystem before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2410 based system)
 * as a driver which may support both 2410 and 2440 may try and use it.
@@ -154,14 +163,14 @@ static struct sys_device s3c2410_sysdev = {
 static int __init s3c2410_core_init(void)
 {
-        return sysdev_class_register(&s3c2410_sysclass);
+        return subsys_system_register(&s3c2410_subsys, NULL);
 }
 core_initcall(s3c2410_core_init);
 static int __init s3c2410a_core_init(void)
 {
-        return sysdev_class_register(&s3c2410a_sysclass);
+        return subsys_system_register(&s3c2410a_subsys, NULL);
 }
 core_initcall(s3c2410a_core_init);
@@ -175,11 +184,23 @@ int __init s3c2410_init(void)
 #endif
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
-        return sysdev_register(&s3c2410_sysdev);
+        return device_register(&s3c2410_dev);
 }
 int __init s3c2410a_init(void)
 {
-        s3c2410_sysdev.cls = &s3c2410a_sysclass;
+        s3c2410_dev.bus = &s3c2410a_subsys;
        return s3c2410_init();
 }
+void s3c2410_restart(char mode, const char *cmd)
+{
+        if (mode == 's') {
+                soft_restart(0);
+        }
+        arch_wdt_reset();
+        /* we'll take a jump through zero as a poor second */
+        soft_restart(0);
+}
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 140711db6c8..d10b695a906 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -26,7 +26,7 @@
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/mutex.h>
 #include <linux/delay.h>
@@ -659,6 +659,12 @@ static struct clk *clks[] __initdata = {
        &clk_armclk,
 };
+static struct clk_lookup s3c2412_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
+};
 int __init s3c2412_baseclk_add(void)
 {
        unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
@@ -751,6 +757,7 @@ int __init s3c2412_baseclk_add(void)
                s3c2412_clkcon_enable(clkp, 0);
        }
+        clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
        s3c_pwmclk_init();
        return 0;
 }
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c2412/cpu-freq.c
index eb3ea172133..d8664b7652c 100644
--- a/arch/arm/mach-s3c2412/cpu-freq.c
+++ b/arch/arm/mach-s3c2412/cpu-freq.c
@@ -16,7 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/cpufreq.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -194,7 +194,7 @@ static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
 };
-static int s3c2412_cpufreq_add(struct sys_device *sysdev)
+static int s3c2412_cpufreq_add(struct device *dev)
 {
        unsigned long fclk_rate;
@@ -244,14 +244,15 @@ err_fclk:
        return -ENOENT;
 }
-static struct sysdev_driver s3c2412_cpufreq_driver = {
+static struct subsys_interface s3c2412_cpufreq_interface = {
-        .add            = s3c2412_cpufreq_add,
+        .name           = "s3c2412_cpufreq",
+        .subsys         = &s3c2412_subsys,
+        .add_dev        = s3c2412_cpufreq_add,
 };
 static int s3c2412_cpufreq_init(void)
 {
-        return sysdev_driver_register(&s3c2412_sysclass,
+        return subsys_interface_register(&s3c2412_cpufreq_interface);
-                                      &s3c2412_cpufreq_driver);
 }
 arch_initcall(s3c2412_cpufreq_init);
diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index d2a7d5ef3e6..142acd3b5e1 100644
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -14,7 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/serial_core.h>
 #include <linux/io.h>
@@ -159,19 +159,21 @@ static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
        .map_size       = ARRAY_SIZE(s3c2412_dma_mappings),
 };
-static int __init s3c2412_dma_add(struct sys_device *sysdev)
+static int __init s3c2412_dma_add(struct device *dev)
 {
        s3c2410_dma_init();
        return s3c24xx_dma_init_map(&s3c2412_dma_sel);
 }
-static struct sysdev_driver s3c2412_dma_driver = {
+static struct subsys_interface s3c2412_dma_interface = {
-        .add    = s3c2412_dma_add,
+        .name           = "s3c2412_dma",
+        .subsys         = &s3c2412_subsys,
+        .add_dev        = s3c2412_dma_add,
 };
 static int __init s3c2412_dma_init(void)
 {
-        return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
+        return subsys_interface_register(&s3c2412_dma_interface);
 }
 arch_initcall(s3c2412_dma_init);
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index 1a1aa220972..a8a46c1644f 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -23,7 +23,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -170,7 +170,7 @@ static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
 static struct irq_chip s3c2412_irq_rtc_chip;
-static int s3c2412_irq_add(struct sys_device *sysdev)
+static int s3c2412_irq_add(struct device *dev)
 {
        unsigned int irqno;
@@ -200,13 +200,15 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s3c2412_irq_driver = {
+static struct subsys_interface s3c2412_irq_interface = {
-        .add            = s3c2412_irq_add,
+        .name           = "s3c2412_irq",
+        .subsys         = &s3c2412_subsys,
+        .add_dev        = s3c2412_irq_add,
 };
 static int s3c2412_irq_init(void)
 {
-        return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_irq_driver);
+        return subsys_interface_register(&s3c2412_irq_interface);
 }
 arch_initcall(s3c2412_irq_init);
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 286ef1738c6..ae73ba34ecc 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -48,6 +48,7 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
+#include <plat/s3c2412.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
@@ -661,4 +662,5 @@ MACHINE_START(JIVE, "JIVE")
        .map_io         = jive_map_io,
        .init_machine   = jive_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index f1eec1b5493..b11451b853d 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -134,6 +134,7 @@ MACHINE_START(S3C2413, "S3C2413")
        .map_io         = smdk2413_map_io,
        .init_machine   = smdk2413_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2412_restart,
 MACHINE_END
 MACHINE_START(SMDK2412, "SMDK2412")
@@ -145,6 +146,7 @@ MACHINE_START(SMDK2412, "SMDK2412")
        .map_io         = smdk2413_map_io,
        .init_machine   = smdk2413_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2412_restart,
 MACHINE_END
 MACHINE_START(SMDK2413, "SMDK2413")
@@ -156,4 +158,5 @@ MACHINE_START(SMDK2413, "SMDK2413")
        .map_io         = smdk2413_map_io,
        .init_machine   = smdk2413_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 1bbb1ef5f4f..94bfaa1fb14 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -162,4 +162,5 @@ MACHINE_START(VSTMS, "VSTMS")
        .init_machine   = vstms_init,
        .map_io         = vstms_map_io,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c
index f4077efa51f..d1adfa65f66 100644
--- a/arch/arm/mach-s3c2412/pm.c
+++ b/arch/arm/mach-s3c2412/pm.c
@@ -16,7 +16,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -56,7 +56,7 @@ static void s3c2412_pm_prepare(void)
 {
 }
-static int s3c2412_pm_add(struct sys_device *sysdev)
+static int s3c2412_pm_add(struct device *dev)
 {
        pm_cpu_prep = s3c2412_pm_prepare;
        pm_cpu_sleep = s3c2412_cpu_suspend;
@@ -87,13 +87,15 @@ static struct sleep_save s3c2412_sleep[] = {
        SAVE_ITEM(S3C2413_GPJSLPCON),
 };
-static struct sysdev_driver s3c2412_pm_driver = {
+static struct subsys_interface s3c2412_pm_interface = {
-        .add            = s3c2412_pm_add,
+        .name           = "s3c2412_pm",
+        .subsys         = &s3c2412_subsys,
+        .add_dev        = s3c2412_pm_add,
 };
 static __init int s3c2412_pm_init(void)
 {
-        return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_pm_driver);
+        return subsys_interface_register(&s3c2412_pm_interface);
 }
 arch_initcall(s3c2412_pm_init);
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 57a1e01e4e5..aff6e85a97c 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -18,7 +18,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
@@ -32,7 +32,6 @@
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
-#include <mach/reset.h>
 #include <mach/idle.h>
 #include <plat/cpu-freq.h>
@@ -131,8 +130,11 @@ static void s3c2412_idle(void)
        cpu_do_idle();
 }
-static void s3c2412_hard_reset(void)
+void s3c2412_restart(char mode, const char *cmd)
 {
+        if (mode == 's')
+                soft_restart(0);
        /* errata "Watch-dog/Software Reset Problem" specifies that
         * this reset must be done with the SYSCLK sourced from
         * EXTCLK instead of FOUT to avoid a glitch in the reset
@@ -164,10 +166,6 @@ void __init s3c2412_map_io(void)
        s3c24xx_idle = s3c2412_idle;
-        /* set custom reset hook */
-        s3c24xx_reset_hook = s3c2412_hard_reset;
        /* register our io-tables */
        iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc));
@@ -220,25 +218,26 @@ void __init s3c2412_init_clocks(int xtal)
        s3c2412_baseclk_add();
 }
-/* need to register class before we actually register the device, and
+/* need to register the subsystem before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2412 based system)
 * as a driver which may support both 2410 and 2440 may try and use it.
 */
-struct sysdev_class s3c2412_sysclass = {
+struct bus_type s3c2412_subsys = {
        .name = "s3c2412-core",
+        .dev_name = "s3c2412-core",
 };
 static int __init s3c2412_core_init(void)
 {
-        return sysdev_class_register(&s3c2412_sysclass);
+        return subsys_system_register(&s3c2412_subsys, NULL);
 }
 core_initcall(s3c2412_core_init);
-static struct sys_device s3c2412_sysdev = {
+static struct device s3c2412_dev = {
-        .cls            = &s3c2412_sysclass,
+        .bus            = &s3c2412_subsys,
 };
 int __init s3c2412_init(void)
@@ -250,5 +249,5 @@ int __init s3c2412_init(void)
 #endif
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
-        return sysdev_register(&s3c2412_sysdev);
+        return device_register(&s3c2412_dev);
 }
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index 7b805b279ca..ca0cd227f87 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_S3C2416_PM)	+= pm.o
 #obj-$(CONFIG_S3C2416_DMA)      += dma.o
 # Device setup
-obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
 obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
 # Machine support
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index afbbe8bc21d..59f54d1d7f8 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -90,39 +90,38 @@ static struct clksrc_clk hsmmc_div[] = {
        },
 };
-static struct clksrc_clk hsmmc_mux[] = {
+static struct clksrc_clk hsmmc_mux0 = {
-        [0] = {
+        .clk    = {
-                .clk    = {
+                .name           = "hsmmc-if",
-                        .name   = "hsmmc-if",
+                .devname        = "s3c-sdhci.0",
-                        .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 6),
-                        .ctrlbit = (1 << 6),
+                .enable         = s3c2443_clkcon_enable_s,
-                        .enable = s3c2443_clkcon_enable_s,
-                },
-                .sources = &(struct clksrc_sources) {
-                        .nr_sources = 2,
-                        .sources = (struct clk *[]) {
-                                [0] = &hsmmc_div[0].clk,
-                                [1] = NULL, /* to fix */
-                        },
-                },
-                .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
        },
-        [1] = {
+        .sources        = &(struct clksrc_sources) {
-                .clk    = {
+                .nr_sources     = 2,
-                        .name   = "hsmmc-if",
+                .sources        = (struct clk * []) {
-                        .devname        = "s3c-sdhci.1",
+                        [0]     = &hsmmc_div[0].clk,
-                        .ctrlbit = (1 << 12),
+                        [1]     = NULL, /* to fix */
-                        .enable = s3c2443_clkcon_enable_s,
                },
-                .sources = &(struct clksrc_sources) {
+        },
-                        .nr_sources = 2,
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
-                        .sources = (struct clk *[]) {
+};
-                                [0] = &hsmmc_div[1].clk,
-                                [1] = NULL, /* to fix */
+static struct clksrc_clk hsmmc_mux1 = {
-                        },
+        .clk    = {
+                .name           = "hsmmc-if",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 12),
+                .enable         = s3c2443_clkcon_enable_s,
+        },
+        .sources        = &(struct clksrc_sources) {
+                .nr_sources     = 2,
+                .sources        = (struct clk * []) {
+                        [0]     = &hsmmc_div[1].clk,
+                        [1]     = NULL, /* to fix */
                },
-                .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
        },
+        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
 };
 static struct clk hsmmc0_clk = {
@@ -144,8 +143,14 @@ static struct clksrc_clk *clksrcs[] __initdata = {
        &hsspi_mux,
        &hsmmc_div[0],
        &hsmmc_div[1],
-        &hsmmc_mux[0],
+        &hsmmc_mux0,
-        &hsmmc_mux[1],
+        &hsmmc_mux1,
+};
+static struct clk_lookup s3c2416_clk_lookup[] = {
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
 };
 void __init s3c2416_init_clocks(int xtal)
@@ -167,6 +172,7 @@ void __init s3c2416_init_clocks(int xtal)
                s3c_register_clksrc(clksrcs[ptr], 1);
        s3c24xx_register_clock(&hsmmc0_clk);
+        clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
        s3c_pwmclk_init();
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index 28ad20d4244..36df761061d 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -25,7 +25,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -213,7 +213,7 @@ static int __init s3c2416_add_sub(unsigned int base,
        return 0;
 }
-static int __init s3c2416_irq_add(struct sys_device *sysdev)
+static int __init s3c2416_irq_add(struct device *dev)
 {
        printk(KERN_INFO "S3C2416: IRQ Support\n");
@@ -234,13 +234,15 @@ static int __init s3c2416_irq_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s3c2416_irq_driver = {
+static struct subsys_interface s3c2416_irq_interface = {
-        .add            = s3c2416_irq_add,
+        .name           = "s3c2416_irq",
+        .subsys         = &s3c2416_subsys,
+        .add_dev        = s3c2416_irq_add,
 };
 static int __init s3c2416_irq_init(void)
 {
-        return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_irq_driver);
+        return subsys_interface_register(&s3c2416_irq_interface);
 }
 arch_initcall(s3c2416_irq_init);
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index a9eee531ca7..eebe1e72b93 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -50,6 +50,7 @@
 #include <plat/nand.h>
 #include <plat/sdhci.h>
 #include <plat/udc.h>
+#include <linux/platform_data/s3c-hsudc.h>
 #include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
@@ -251,4 +252,5 @@ MACHINE_START(SMDK2416, "SMDK2416")
        .map_io         = smdk2416_map_io,
        .init_machine   = smdk2416_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2416/pm.c b/arch/arm/mach-s3c2416/pm.c
index 9ec54f1d8e7..3bdb15a0d41 100644
--- a/arch/arm/mach-s3c2416/pm.c
+++ b/arch/arm/mach-s3c2416/pm.c
@@ -10,7 +10,7 @@
 * published by the Free Software Foundation.
 */
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/io.h>
@@ -48,7 +48,7 @@ static void s3c2416_pm_prepare(void)
        __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
 }
-static int s3c2416_pm_add(struct sys_device *sysdev)
+static int s3c2416_pm_add(struct device *dev)
 {
        pm_cpu_prep = s3c2416_pm_prepare;
        pm_cpu_sleep = s3c2416_cpu_suspend;
@@ -56,13 +56,15 @@ static int s3c2416_pm_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s3c2416_pm_driver = {
+static struct subsys_interface s3c2416_pm_interface = {
-        .add            = s3c2416_pm_add,
+        .name           = "s3c2416_pm",
+        .subsys         = &s3c2416_subsys,
+        .add_dev        = s3c2416_pm_add,
 };
 static __init int s3c2416_pm_init(void)
 {
-        return sysdev_driver_register(&s3c2416_sysclass, &s3c2416_pm_driver);
+        return subsys_interface_register(&s3c2416_pm_interface);
 }
 arch_initcall(s3c2416_pm_init);
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index ee214bc83c8..5287d2808d3 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -31,7 +31,7 @@
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
 #include <linux/io.h>
@@ -44,7 +44,6 @@
 #include <asm/proc-fns.h>
 #include <asm/irq.h>
-#include <mach/reset.h>
 #include <mach/idle.h>
 #include <mach/regs-s3c2443-clock.h>
@@ -68,16 +67,20 @@ static struct map_desc s3c2416_iodesc[] __initdata = {
        IODESC_ENT(TIMER),
 };
-struct sysdev_class s3c2416_sysclass = {
+struct bus_type s3c2416_subsys = {
        .name = "s3c2416-core",
+        .dev_name = "s3c2416-core",
 };
-static struct sys_device s3c2416_sysdev = {
+static struct device s3c2416_dev = {
-        .cls            = &s3c2416_sysclass,
+        .bus            = &s3c2416_subsys,
 };
-static void s3c2416_hard_reset(void)
+void s3c2416_restart(char mode, const char *cmd)
 {
+        if (mode == 's')
+                soft_restart(0);
        __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
 }
@@ -85,7 +88,6 @@ int __init s3c2416_init(void)
 {
        printk(KERN_INFO "S3C2416: Initializing architecture\n");
-        s3c24xx_reset_hook = s3c2416_hard_reset;
        /* s3c24xx_idle = s3c2416_idle; */
        /* change WDT IRQ number */
@@ -105,7 +107,7 @@ int __init s3c2416_init(void)
 #endif
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
-        return sysdev_register(&s3c2416_sysdev);
+        return device_register(&s3c2416_dev);
 }
 void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no)
@@ -133,7 +135,7 @@ void __init s3c2416_map_io(void)
        iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
 }
-/* need to register class before we actually register the device, and
+/* need to register the subsystem before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2416 based system)
 * as a driver which may support both 2443 and 2440 may try and use it.
@@ -141,7 +143,7 @@ void __init s3c2416_map_io(void)
 static int __init s3c2416_core_init(void)
 {
-        return sysdev_class_register(&s3c2416_sysclass);
+        return subsys_system_register(&s3c2416_subsys, NULL);
 }
 core_initcall(s3c2416_core_init);
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
deleted file mode 100644
index cee53955eb0..00000000000
--- a/arch/arm/mach-s3c2416/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
- *
- * Copyright 2010 Promwad Innovation Company
- *      Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
- *
- * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * Based on mach-s3c64xx/setup-sdhci.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/types.h>
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-char *s3c2416_hsmmc_clksrcs[4] = {
-        [0] = "hsmmc",
-        [1] = "hsmmc",
-        [2] = "hsmmc-if",
-        /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index f9e6bdaf41d..bedbc87a342 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -28,12 +28,12 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/device.h>
-#include <linux/sysdev.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/mutex.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/serial_core.h>
 #include <mach/hardware.h>
 #include <linux/atomic.h>
@@ -43,6 +43,7 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
+#include <plat/regs-serial.h>
 /* S3C2440 extended clock support */
@@ -108,7 +109,47 @@ static struct clk s3c2440_clk_ac97 = {
        .ctrlbit        = S3C2440_CLKCON_CAMERA,
 };
-static int s3c2440_clk_add(struct sys_device *sysdev)
+static unsigned long  s3c2440_fclk_n_getrate(struct clk *clk)
+{
+        unsigned long ucon0, ucon1, ucon2, divisor;
+        /* the fun of calculating the uart divisors on the s3c2440 */
+        ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
+        ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
+        ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
+        ucon0 &= S3C2440_UCON0_DIVMASK;
+        ucon1 &= S3C2440_UCON1_DIVMASK;
+        ucon2 &= S3C2440_UCON2_DIVMASK;
+        if (ucon0 != 0)
+                divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
+        else if (ucon1 != 0)
+                divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
+        else if (ucon2 != 0)
+                divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
+        else
+                /* manual calims 44, seems to be 9 */
+                divisor = 9;
+        return clk_get_rate(clk->parent) / divisor;
+}
+static struct clk s3c2440_clk_fclk_n = {
+        .name           = "fclk_n",
+        .parent         = &clk_f,
+        .ops            = &(struct clk_ops) {
+                .get_rate       = s3c2440_fclk_n_getrate,
+        },
+};
+static struct clk_lookup s3c2440_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
+};
+static int s3c2440_clk_add(struct device *dev)
 {
        struct clk *clock_upll;
        struct clk *clock_h;
@@ -126,10 +167,12 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
        s3c2440_clk_cam.parent = clock_h;
        s3c2440_clk_ac97.parent = clock_p;
        s3c2440_clk_cam_upll.parent = clock_upll;
+        s3c24xx_register_clock(&s3c2440_clk_fclk_n);
        s3c24xx_register_clock(&s3c2440_clk_ac97);
        s3c24xx_register_clock(&s3c2440_clk_cam);
        s3c24xx_register_clock(&s3c2440_clk_cam_upll);
+        clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
        clk_disable(&s3c2440_clk_ac97);
        clk_disable(&s3c2440_clk_cam);
@@ -137,13 +180,15 @@ static int s3c2440_clk_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s3c2440_clk_driver = {
+static struct subsys_interface s3c2440_clk_interface = {
-        .add    = s3c2440_clk_add,
+        .name           = "s3c2440_clk",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_clk_add,
 };
-static __init int s3c24xx_clk_driver(void)
+static __init int s3c24xx_clk_init(void)
 {
-        return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
+        return subsys_interface_register(&s3c2440_clk_interface);
 }
-arch_initcall(s3c24xx_clk_driver);
+arch_initcall(s3c24xx_clk_init);
diff --git a/arch/arm/mach-s3c2440/common.h b/arch/arm/mach-s3c2440/common.h
new file mode 100644
index 00000000000..db8a98ac68c
--- /dev/null
+++ b/arch/arm/mach-s3c2440/common.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Common Header for S3C2440 machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_S3C2440_COMMON_H
+#define __ARCH_ARM_MACH_S3C2440_COMMON_H
+void s3c2440_restart(char mode, const char *cmd);
+#endif /* __ARCH_ARM_MACH_S3C2440_COMMON_H */
diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index 0e73f8f9d13..15b1ddf8f62 100644
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -14,7 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/serial_core.h>
 #include <mach/map.h>
@@ -174,20 +174,22 @@ static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
        },
 };
-static int __init s3c2440_dma_add(struct sys_device *sysdev)
+static int __init s3c2440_dma_add(struct device *dev)
 {
        s3c2410_dma_init();
        s3c24xx_dma_order_set(&s3c2440_dma_order);
        return s3c24xx_dma_init_map(&s3c2440_dma_sel);
 }
-static struct sysdev_driver s3c2440_dma_driver = {
+static struct subsys_interface s3c2440_dma_interface = {
-        .add    = s3c2440_dma_add,
+        .name           = "s3c2440_dma",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_dma_add,
 };
 static int __init s3c2440_dma_init(void)
 {
-        return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_dma_driver);
+        return subsys_interface_register(&s3c2440_dma_interface);
 }
 arch_initcall(s3c2440_dma_init);
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index eb1cc0f0705..4fee9bc6bcb 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -23,7 +23,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -92,7 +92,7 @@ static struct irq_chip s3c_irq_wdtac97 = {
        .irq_ack        = s3c_irq_wdtac97_ack,
 };
-static int s3c2440_irq_add(struct sys_device *sysdev)
+static int s3c2440_irq_add(struct device *dev)
 {
        unsigned int irqno;
@@ -113,13 +113,15 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s3c2440_irq_driver = {
+static struct subsys_interface s3c2440_irq_interface = {
-        .add            = s3c2440_irq_add,
+        .name           = "s3c2440_irq",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_irq_add,
 };
 static int s3c2440_irq_init(void)
 {
-        return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
+        return subsys_interface_register(&s3c2440_irq_interface);
 }
 arch_initcall(s3c2440_irq_init);
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 74f92fc3fd0..24569550de1 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -55,6 +55,8 @@
 #include <plat/cpu.h>
 #include <plat/audio-simtec.h>
+#include "common.h"
 #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
 static struct map_desc anubis_iodesc[] __initdata = {
@@ -96,22 +98,6 @@ static struct map_desc anubis_iodesc[] __initdata = {
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        }
-};
 static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
@@ -119,8 +105,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = anubis_serial_clocks,
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
-                .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
        },
        [1] = {
                .hwport      = 2,
@@ -128,8 +113,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = anubis_serial_clocks,
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
-                .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
        },
 };
@@ -503,4 +487,5 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
        .init_machine   = anubis_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2440_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 38887ee0c78..d6a9763110c 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -49,6 +49,8 @@
 #include <plat/cpu.h>
 #include <plat/mci.h>
+#include "common.h"
 static struct map_desc at2440evb_iodesc[] __initdata = {
        /* Nothing here */
 };
@@ -57,22 +59,6 @@ static struct map_desc at2440evb_iodesc[] __initdata = {
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
-static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        }
-};
 static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
@@ -80,8 +66,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = at2440evb_serial_clocks,
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
-                .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
        },
        [1] = {
                .hwport      = 1,
@@ -89,8 +74,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = at2440evb_serial_clocks,
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
-                .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
        },
 };
@@ -238,4 +222,5 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
        .init_machine   = at2440evb_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2440_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index de1e0ff46ce..5859e609d28 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -90,6 +90,7 @@
 #include <plat/iic.h>
 #include <plat/ts.h>
+#include "common.h"
 static struct pcf50633 *gta02_pcf;
@@ -600,4 +601,5 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = gta02_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2440_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index 91fe0b4c95f..adbbb85bc4c 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -60,6 +60,8 @@
 #include <sound/s3c24xx_uda134x.h>
+#include "common.h"
 #define MACH_MINI2440_DM9K_BASE (S3C2410_CS4 + 0x300)
 static struct map_desc mini2440_iodesc[] __initdata = {
@@ -167,6 +169,24 @@ static struct s3c2410fb_display mini2440_lcd_cfg[] __initdata = {
                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
                                   S3C2410_LCDCON5_HWSWP),
        },
+        /* mini2440 + 3.5" TFT (LCD-W35i, LQ035Q1DG06 type) + touchscreen*/
+        [3] = {
+                _LCD_DECLARE(
+                        /* clock */
+                        7,
+                        /* xres, margin_right, margin_left, hsync */
+                        320, 68, 66, 4,
+                        /* yres, margin_top, margin_bottom, vsync */
+                        240, 4, 4, 9,
+                        /* refresh rate */
+                        60),
+                .lcdcon5        = (S3C2410_LCDCON5_FRM565 |
+                                   S3C2410_LCDCON5_INVVDEN |
+                                   S3C2410_LCDCON5_INVVFRAME |
+                                   S3C2410_LCDCON5_INVVLINE |
+                                   S3C2410_LCDCON5_INVVCLK |
+                                   S3C2410_LCDCON5_HWSWP),
+        },
 };
 /* todo - put into gpio header */
@@ -681,4 +701,5 @@ MACHINE_START(MINI2440, "MINI2440")
        .init_machine   = mini2440_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2440_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 61c0bf14816..40eaf844bc1 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -47,6 +47,8 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include "common.h"
 static struct map_desc nexcoder_iodesc[] __initdata = {
        /* nothing here yet */
 };
@@ -156,4 +158,5 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
        .init_machine   = nexcoder_init,
        .init_irq       = s3c24xx_init_irq,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2440_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index dc142ebf8cb..4c480ef734f 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -54,6 +54,8 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include "common.h"
 /* onboard perihperal map */
 static struct map_desc osiris_iodesc[] __initdata = {
@@ -100,21 +102,6 @@ static struct map_desc osiris_iodesc[] __initdata = {
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
-static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
-        [0] = {
-                .name           = "uclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        }
-};
 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
@@ -122,8 +109,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = osiris_serial_clocks,
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
-                .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
        },
        [1] = {
                .hwport      = 1,
@@ -131,8 +117,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = osiris_serial_clocks,
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
-                .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
        },
        [2] = {
                .hwport      = 2,
@@ -140,8 +125,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
                .ucon        = UCON,
                .ulcon       = ULCON,
                .ufcon       = UFCON,
-                .clocks      = osiris_serial_clocks,
+                .clk_sel        = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
-                .clocks_size = ARRAY_SIZE(osiris_serial_clocks),
        }
 };
@@ -452,4 +436,5 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
        .init_irq       = s3c24xx_init_irq,
        .init_machine   = osiris_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2440_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 0d3453bf567..80077f6472e 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -24,7 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/pwm.h>
@@ -62,21 +62,14 @@
 #include <sound/uda1380.h>
+#include "common.h"
 #define LCD_PWM_PERIOD 192960
 #define LCD_PWM_DUTY 127353
 static struct map_desc rx1950_iodesc[] __initdata = {
 };
-static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
-        [0] = {
-               .name = "fclk",
-               .divisor = 0x0a,
-               .min_baud = 0,
-               .max_baud = 0,
-        },
-};
 static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
        [0] = {
               .hwport = 0,
@@ -84,8 +77,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
               .ucon = 0x3c5,
               .ulcon = 0x03,
               .ufcon = 0x51,
-               .clocks = rx1950_serial_clocks,
+                .clk_sel = S3C2410_UCON_CLKSEL3,
-               .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
        },
        [1] = {
               .hwport = 1,
@@ -93,8 +85,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
               .ucon = 0x3c5,
               .ulcon = 0x03,
               .ufcon = 0x51,
-               .clocks = rx1950_serial_clocks,
+                .clk_sel = S3C2410_UCON_CLKSEL3,
-               .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
        },
        /* IR port */
        [2] = {
@@ -103,8 +94,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
               .ucon = 0x3c5,
               .ulcon = 0x43,
               .ufcon = 0xf1,
-               .clocks = rx1950_serial_clocks,
+                .clk_sel = S3C2410_UCON_CLKSEL3,
-               .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
        },
 };
@@ -832,4 +822,5 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
        .init_irq = s3c24xx_init_irq,
        .init_machine = rx1950_init_machine,
        .timer = &s3c24xx_timer,
+        .restart        = s3c2440_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index e19499c2f90..20103bafbd4 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -20,7 +20,7 @@
 #include <linux/init.h>
 #include <linux/tty.h>
 #include <linux/console.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/serial.h>
@@ -51,6 +51,8 @@
 #include <plat/cpu.h>
 #include <plat/pm.h>
+#include "common.h"
 static struct map_desc rx3715_iodesc[] __initdata = {
        /* dump ISA space somewhere unused */
@@ -67,16 +69,6 @@ static struct map_desc rx3715_iodesc[] __initdata = {
        },
 };
-static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
-        [0] = {
-                .name           = "fclk",
-                .divisor        = 0,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        }
-};
 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
        [0] = {
                .hwport      = 0,
@@ -84,8 +76,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
                .ucon        = 0x3c5,
                .ulcon       = 0x03,
                .ufcon       = 0x51,
-                .clocks      = rx3715_serial_clocks,
+                .clk_sel        = S3C2410_UCON_CLKSEL3,
-                .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
        },
        [1] = {
                .hwport      = 1,
@@ -93,8 +84,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
                .ucon        = 0x3c5,
                .ulcon       = 0x03,
                .ufcon       = 0x00,
-                .clocks      = rx3715_serial_clocks,
+                .clk_sel        = S3C2410_UCON_CLKSEL3,
-                .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
        },
        /* IR port */
        [2] = {
@@ -103,8 +93,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
                .ucon        = 0x3c5,
                .ulcon       = 0x43,
                .ufcon       = 0x51,
-                .clocks      = rx3715_serial_clocks,
+                .clk_sel        = S3C2410_UCON_CLKSEL3,
-                .clocks_size = ARRAY_SIZE(rx3715_serial_clocks),
        }
 };
@@ -224,4 +213,5 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
        .init_irq       = rx3715_init_irq,
        .init_machine   = rx3715_init_machine,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2440_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index 36eeb4197a8..1deb60d12a6 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -47,6 +47,8 @@
 #include <plat/common-smdk.h>
+#include "common.h"
 static struct map_desc smdk2440_iodesc[] __initdata = {
        /* ISA IO Space map (memory space selected by A24) */
@@ -181,4 +183,5 @@ MACHINE_START(S3C2440, "SMDK2440")
        .map_io         = smdk2440_map_io,
        .init_machine   = smdk2440_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2440_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
index 976002fb1b8..cf7596694ef 100644
--- a/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
+++ b/arch/arm/mach-s3c2440/s3c2440-cpufreq.c
@@ -17,7 +17,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/cpufreq.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -270,7 +270,7 @@ struct s3c_cpufreq_info s3c2440_cpufreq_info = {
        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
 };
-static int s3c2440_cpufreq_add(struct sys_device *sysdev)
+static int s3c2440_cpufreq_add(struct device *dev)
 {
        xtal = s3c_cpufreq_clk_get(NULL, "xtal");
        hclk = s3c_cpufreq_clk_get(NULL, "hclk");
@@ -285,27 +285,29 @@ static int s3c2440_cpufreq_add(struct sys_device *sysdev)
        return s3c_cpufreq_register(&s3c2440_cpufreq_info);
 }
-static struct sysdev_driver s3c2440_cpufreq_driver = {
+static struct subsys_interface s3c2440_cpufreq_interface = {
-        .add            = s3c2440_cpufreq_add,
+        .name           = "s3c2440_cpufreq",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_cpufreq_add,
 };
 static int s3c2440_cpufreq_init(void)
 {
-        return sysdev_driver_register(&s3c2440_sysclass,
+        return subsys_interface_register(&s3c2440_cpufreq_interface);
-                                      &s3c2440_cpufreq_driver);
 }
 /* arch_initcall adds the clocks we need, so use subsys_initcall. */
 subsys_initcall(s3c2440_cpufreq_init);
-static struct sysdev_driver s3c2442_cpufreq_driver = {
+static struct subsys_interface s3c2442_cpufreq_interface = {
-        .add            = s3c2440_cpufreq_add,
+        .name           = "s3c2442_cpufreq",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2440_cpufreq_add,
 };
 static int s3c2442_cpufreq_init(void)
 {
-        return sysdev_driver_register(&s3c2442_sysclass,
+        return subsys_interface_register(&s3c2442_cpufreq_interface);
-                                      &s3c2442_cpufreq_driver);
 }
 subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
index f105d5e8c47..b5368ae8d7f 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
+++ b/arch/arm/mach-s3c2440/s3c2440-pll-12000000.c
@@ -14,7 +14,7 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -51,7 +51,7 @@ static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
        { .frequency = 400000000,       .index = PLLVAL(0x5c, 1, 1),  },        /* FVco 800.000000 */
 };
-static int s3c2440_plls12_add(struct sys_device *dev)
+static int s3c2440_plls12_add(struct device *dev)
 {
        struct clk *xtal_clk;
        unsigned long xtal;
@@ -72,25 +72,29 @@ static int s3c2440_plls12_add(struct sys_device *dev)
        return 0;
 }
-static struct sysdev_driver s3c2440_plls12_drv = {
+static struct subsys_interface s3c2440_plls12_interface = {
-        .add    = s3c2440_plls12_add,
+        .name           = "s3c2440_plls12",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_plls12_add,
 };
 static int __init s3c2440_pll_12mhz(void)
 {
-        return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_plls12_drv);
+        return subsys_interface_register(&s3c2440_plls12_interface);
 }
 arch_initcall(s3c2440_pll_12mhz);
-static struct sysdev_driver s3c2442_plls12_drv = {
+static struct subsys_interface s3c2442_plls12_interface = {
-        .add    = s3c2440_plls12_add,
+        .name           = "s3c2442_plls12",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2440_plls12_add,
 };
 static int __init s3c2442_pll_12mhz(void)
 {
-        return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv);
+        return subsys_interface_register(&s3c2442_plls12_interface);
 }
diff --git a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
index c8a8f90ef38..42f2b5cd239 100644
--- a/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
+++ b/arch/arm/mach-s3c2440/s3c2440-pll-16934400.c
@@ -14,7 +14,7 @@
 #include <linux/types.h>
 #include <linux/kernel.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -79,7 +79,7 @@ static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
        { .frequency = 402192000,       .index = PLLVAL(87, 2, 1),      },      /* FVco 804.384000 */
 };
-static int s3c2440_plls169344_add(struct sys_device *dev)
+static int s3c2440_plls169344_add(struct device *dev)
 {
        struct clk *xtal_clk;
        unsigned long xtal;
@@ -100,28 +100,28 @@ static int s3c2440_plls169344_add(struct sys_device *dev)
        return 0;
 }
-static struct sysdev_driver s3c2440_plls169344_drv = {
+static struct subsys_interface s3c2440_plls169344_interface = {
-        .add    = s3c2440_plls169344_add,
+        .name           = "s3c2440_plls169344",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c2440_plls169344_add,
 };
 static int __init s3c2440_pll_16934400(void)
 {
-        return sysdev_driver_register(&s3c2440_sysclass,
+        return subsys_interface_register(&s3c2440_plls169344_interface);
-                                      &s3c2440_plls169344_drv);
 }
 arch_initcall(s3c2440_pll_16934400);
-static struct sysdev_driver s3c2442_plls169344_drv = {
+static struct subsys_interface s3c2442_plls169344_interface = {
-        .add    = s3c2440_plls169344_add,
+        .name           = "s3c2442_plls169344",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2440_plls169344_add,
 };
 static int __init s3c2442_pll_16934400(void)
 {
-        return sysdev_driver_register(&s3c2442_sysclass,
+        return subsys_interface_register(&s3c2442_plls169344_interface);
-                                      &s3c2442_plls169344_drv);
 }
 arch_initcall(s3c2442_pll_16934400);
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index 37f8cc6aabd..517623a09fc 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -18,7 +18,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/gpio.h>
 #include <linux/clk.h>
@@ -35,13 +35,14 @@
 #include <plat/cpu.h>
 #include <plat/s3c244x.h>
 #include <plat/pm.h>
+#include <plat/watchdog-reset.h>
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
-static struct sys_device s3c2440_sysdev = {
+static struct device s3c2440_dev = {
-        .cls            = &s3c2440_sysclass,
+        .bus            = &s3c2440_subsys,
 };
 int __init s3c2440_init(void)
@@ -63,7 +64,7 @@ int __init s3c2440_init(void)
        /* register our system device for everything else */
-        return sysdev_register(&s3c2440_sysdev);
+        return device_register(&s3c2440_dev);
 }
 void __init s3c2440_map_io(void)
@@ -73,3 +74,15 @@ void __init s3c2440_map_io(void)
        s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up;
        s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up;
 }
+void s3c2440_restart(char mode, const char *cmd)
+{
+        if (mode == 's') {
+                soft_restart(0);
+        }
+        arch_wdt_reset();
+        /* we'll take a jump through zero as a poor second */
+        soft_restart(0);
+}
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
index 2c822e09392..8004e0497bf 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -28,7 +28,6 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/device.h>
-#include <linux/sysdev.h>
 #include <linux/syscore_ops.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
@@ -123,7 +122,7 @@ static struct clk s3c2442_clk_cam_upll = {
        },
 };
-static int s3c2442_clk_add(struct sys_device *sysdev)
+static int s3c2442_clk_add(struct device *dev)
 {
        struct clk *clock_upll;
        struct clk *clock_h;
@@ -149,20 +148,22 @@ static int s3c2442_clk_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s3c2442_clk_driver = {
+static struct subsys_interface s3c2442_clk_interface = {
-        .add    = s3c2442_clk_add,
+        .name           = "s3c2442_clk",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c2442_clk_add,
 };
 static __init int s3c2442_clk_init(void)
 {
-        return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
+        return subsys_interface_register(&s3c2442_clk_interface);
 }
 arch_initcall(s3c2442_clk_init);
-static struct sys_device s3c2442_sysdev = {
+static struct device s3c2442_dev = {
-        .cls            = &s3c2442_sysclass,
+        .bus            = &s3c2442_subsys,
 };
 int __init s3c2442_init(void)
@@ -175,7 +176,7 @@ int __init s3c2442_init(void)
        register_syscore_ops(&s3c244x_pm_syscore_ops);
        register_syscore_ops(&s3c24xx_irq_syscore_ops);
-        return sysdev_register(&s3c2442_sysdev);
+        return device_register(&s3c2442_dev);
 }
 void __init s3c2442_map_io(void)
diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c2440/s3c244x-clock.c
index 7f5ea0a169a..b3fdbdda3d5 100644
--- a/arch/arm/mach-s3c2440/s3c244x-clock.c
+++ b/arch/arm/mach-s3c2440/s3c244x-clock.c
@@ -28,7 +28,6 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/device.h>
-#include <linux/sysdev.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/clk.h>
@@ -73,7 +72,7 @@ static struct clk clk_arm = {
        },
 };
-static int s3c244x_clk_add(struct sys_device *sysdev)
+static int s3c244x_clk_add(struct device *dev)
 {
        unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
        unsigned long clkdivn;
@@ -115,24 +114,28 @@ static int s3c244x_clk_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s3c2440_clk_driver = {
+static struct subsys_interface s3c2440_clk_interface = {
-        .add            = s3c244x_clk_add,
+        .name           = "s3c2440_clk",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c244x_clk_add,
 };
 static int s3c2440_clk_init(void)
 {
-        return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
+        return subsys_interface_register(&s3c2440_clk_interface);
 }
 arch_initcall(s3c2440_clk_init);
-static struct sysdev_driver s3c2442_clk_driver = {
+static struct subsys_interface s3c2442_clk_interface = {
-        .add            = s3c244x_clk_add,
+        .name           = "s3c2442_clk",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c244x_clk_add,
 };
 static int s3c2442_clk_init(void)
 {
-        return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
+        return subsys_interface_register(&s3c2442_clk_interface);
 }
 arch_initcall(s3c2442_clk_init);
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index c63e8f26d90..74d3dcf46a4 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -23,7 +23,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -91,7 +91,7 @@ static struct irq_chip s3c_irq_cam = {
        .irq_ack        = s3c_irq_cam_ack,
 };
-static int s3c244x_irq_add(struct sys_device *sysdev)
+static int s3c244x_irq_add(struct device *dev)
 {
        unsigned int irqno;
@@ -114,25 +114,29 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s3c2440_irq_driver = {
+static struct subsys_interface s3c2440_irq_interface = {
-        .add            = s3c244x_irq_add,
+        .name           = "s3c2440_irq",
+        .subsys         = &s3c2440_subsys,
+        .add_dev        = s3c244x_irq_add,
 };
 static int s3c2440_irq_init(void)
 {
-        return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
+        return subsys_interface_register(&s3c2440_irq_interface);
 }
 arch_initcall(s3c2440_irq_init);
-static struct sysdev_driver s3c2442_irq_driver = {
+static struct subsys_interface s3c2442_irq_interface = {
-        .add            = s3c244x_irq_add,
+        .name           = "s3c2442_irq",
+        .subsys         = &s3c2442_subsys,
+        .add_dev        = s3c244x_irq_add,
 };
 static int s3c2442_irq_init(void)
 {
-        return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_irq_driver);
+        return subsys_interface_register(&s3c2442_irq_interface);
 }
 arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/mach-s3c2440/s3c244x.c b/arch/arm/mach-s3c2440/s3c244x.c
index 7e8a23d2098..36bc60f61d0 100644
--- a/arch/arm/mach-s3c2440/s3c244x.c
+++ b/arch/arm/mach-s3c2440/s3c244x.c
@@ -18,7 +18,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/syscore_ops.h>
 #include <linux/clk.h>
 #include <linux/io.h>
@@ -135,17 +135,19 @@ void __init s3c244x_init_clocks(int xtal)
        s3c2410_baseclk_add();
 }
-/* Since the S3C2442 and S3C2440 share  items, put both sysclasses here */
+/* Since the S3C2442 and S3C2440 share items, put both subsystems here */
-struct sysdev_class s3c2440_sysclass = {
+struct bus_type s3c2440_subsys = {
        .name           = "s3c2440-core",
+        .dev_name       = "s3c2440-core",
 };
-struct sysdev_class s3c2442_sysclass = {
+struct bus_type s3c2442_subsys = {
        .name           = "s3c2442-core",
+        .dev_name       = "s3c2442-core",
 };
-/* need to register class before we actually register the device, and
+/* need to register the subsystem before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2440 based system)
 * as a driver which may support both 2410 and 2440 may try and use it.
@@ -153,14 +155,14 @@ struct sysdev_class s3c2442_sysclass = {
 static int __init s3c2440_core_init(void)
 {
-        return sysdev_class_register(&s3c2440_sysclass);
+        return subsys_system_register(&s3c2440_subsys, NULL);
 }
 core_initcall(s3c2440_core_init);
 static int __init s3c2442_core_init(void)
 {
-        return sysdev_class_register(&s3c2442_sysclass);
+        return subsys_system_register(&s3c2442_subsys, NULL);
 }
 core_initcall(s3c2442_core_init);
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index 1c2c088aa2e..6dde2696f8f 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -27,7 +27,7 @@
 #include <linux/list.h>
 #include <linux/errno.h>
 #include <linux/err.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/mutex.h>
 #include <linux/serial_core.h>
diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index fe52151d2e8..de6b4a23c9e 100644
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -14,7 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/serial_core.h>
 #include <linux/io.h>
@@ -135,19 +135,21 @@ static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
        .map_size       = ARRAY_SIZE(s3c2443_dma_mappings),
 };
-static int __init s3c2443_dma_add(struct sys_device *sysdev)
+static int __init s3c2443_dma_add(struct device *dev)
 {
        s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
        return s3c24xx_dma_init_map(&s3c2443_dma_sel);
 }
-static struct sysdev_driver s3c2443_dma_driver = {
+static struct subsys_interface s3c2443_dma_interface = {
-        .add    = s3c2443_dma_add,
+        .name           = "s3c2443_dma",
+        .subsys         = &s3c2443_subsys,
+        .add_dev        = s3c2443_dma_add,
 };
 static int __init s3c2443_dma_init(void)
 {
-        return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_dma_driver);
+        return subsys_interface_register(&s3c2443_dma_interface);
 }
 arch_initcall(s3c2443_dma_init);
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index 83ecb1173fb..35e4ff24fb4 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -23,7 +23,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -241,7 +241,7 @@ static int __init s3c2443_add_sub(unsigned int base,
        return 0;
 }
-static int __init s3c2443_irq_add(struct sys_device *sysdev)
+static int __init s3c2443_irq_add(struct device *dev)
 {
        printk("S3C2443: IRQ Support\n");
@@ -265,13 +265,15 @@ static int __init s3c2443_irq_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s3c2443_irq_driver = {
+static struct subsys_interface s3c2443_irq_interface = {
-        .add            = s3c2443_irq_add,
+        .name           = "s3c2443_irq",
+        .subsys         = &s3c2443_subsys,
+        .add_dev        = s3c2443_irq_add,
 };
 static int __init s3c2443_irq_init(void)
 {
-        return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_irq_driver);
+        return subsys_interface_register(&s3c2443_irq_interface);
 }
 arch_initcall(s3c2443_irq_init);
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index bec107e0044..20923695622 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -145,4 +145,5 @@ MACHINE_START(SMDK2443, "SMDK2443")
        .map_io         = smdk2443_map_io,
        .init_machine   = smdk2443_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index a22b771b0f3..b9deaeb0dff 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -19,7 +19,7 @@
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/clk.h>
 #include <linux/io.h>
@@ -31,7 +31,6 @@
 #include <asm/irq.h>
 #include <mach/regs-s3c2443-clock.h>
-#include <mach/reset.h>
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
@@ -49,16 +48,20 @@ static struct map_desc s3c2443_iodesc[] __initdata = {
        IODESC_ENT(TIMER),
 };
-struct sysdev_class s3c2443_sysclass = {
+struct bus_type s3c2443_subsys = {
        .name = "s3c2443-core",
+        .dev_name = "s3c2443-core",
 };
-static struct sys_device s3c2443_sysdev = {
+static struct device s3c2443_dev = {
-        .cls            = &s3c2443_sysclass,
+        .bus            = &s3c2443_subsys,
 };
-static void s3c2443_hard_reset(void)
+void s3c2443_restart(char mode, const char *cmd)
 {
+        if (mode == 's')
+                soft_restart(0);
        __raw_writel(S3C2443_SWRST_RESET, S3C2443_SWRST);
 }
@@ -66,8 +69,6 @@ int __init s3c2443_init(void)
 {
        printk("S3C2443: Initialising architecture\n");
-        s3c24xx_reset_hook = s3c2443_hard_reset;
        s3c_nand_setname("s3c2412-nand");
        s3c_fb_setname("s3c2443-fb");
@@ -77,7 +78,7 @@ int __init s3c2443_init(void)
        s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
        s3c_device_wdt.resource[1].end   = IRQ_S3C2443_WDT;
-        return sysdev_register(&s3c2443_sysdev);
+        return device_register(&s3c2443_dev);
 }
 void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no)
@@ -99,7 +100,7 @@ void __init s3c2443_map_io(void)
        iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc));
 }
-/* need to register class before we actually register the device, and
+/* need to register the subsystem before we actually register the device, and
 * we also need to ensure that it has been initialised before any of the
 * drivers even try to use it (even if not on an s3c2443 based system)
 * as a driver which may support both 2443 and 2440 may try and use it.
@@ -107,7 +108,7 @@ void __init s3c2443_map_io(void)
 static int __init s3c2443_core_init(void)
 {
-        return sysdev_class_register(&s3c2443_sysclass);
+        return subsys_system_register(&s3c2443_subsys, NULL);
 }
 core_initcall(s3c2443_core_init);
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 5552e048c2b..dd20c66cd70 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -8,6 +8,7 @@ config PLAT_S3C64XX
        bool
        depends on ARCH_S3C64XX
        select SAMSUNG_WAKEMASK
+        select PM_GENERIC_DOMAINS
        default y
        help
          Base platform code for any Samsung S3C64XX device
@@ -77,6 +78,11 @@ config S3C64XX_SETUP_SDHCI_GPIO
        help
          Common setup code for S3C64XX SDHCI GPIO configurations
+config S3C64XX_SETUP_SPI
+        bool
+        help
+         Common setup code for SPI GPIO configurations
 # S36400 Macchine support
 config MACH_SMDK6400
@@ -188,7 +194,7 @@ config SMDK6410_WM1190_EV1
        depends on MACH_SMDK6410
        select REGULATOR
        select REGULATOR_WM8350
-        select S3C24XX_GPIO_EXTRA64
+        select SAMSUNG_GPIO_EXTRA64
        select MFD_WM8350_I2C
        select MFD_WM8350_CONFIG_MODE_0
        select MFD_WM8350_CONFIG_MODE_3
@@ -206,7 +212,7 @@ config SMDK6410_WM1192_EV1
        depends on MACH_SMDK6410
        select REGULATOR
        select REGULATOR_WM831X
-        select S3C24XX_GPIO_EXTRA64
+        select SAMSUNG_GPIO_EXTRA64
        select MFD_WM831X
        select MFD_WM831X_I2C
        help
@@ -276,6 +282,7 @@ config MACH_WLF_CRAGG_6410
        select S3C64XX_SETUP_IDE
        select S3C64XX_SETUP_FB_24BPP
        select S3C64XX_SETUP_KEYPAD
+        select S3C64XX_SETUP_SPI
        select SAMSUNG_DEV_ADC
        select SAMSUNG_DEV_KEYPAD
        select S3C_DEV_USB_HOST
@@ -286,8 +293,8 @@ config MACH_WLF_CRAGG_6410
        select S3C_DEV_I2C1
        select S3C_DEV_WDT
        select S3C_DEV_RTC
-        select S3C64XX_DEV_SPI
+        select S3C64XX_DEV_SPI0
-        select S3C24XX_GPIO_EXTRA128
+        select SAMSUNG_GPIO_EXTRA128
        select I2C
        help
          Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index cfc0b994180..1822ac2eba3 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -10,54 +10,49 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
-# Core files
+# Core
-obj-y                           += cpu.o
-obj-y                           += clock.o
-# Core support for S3C6400 system
+obj-y                           += common.o clock.o
+# Core support
 obj-$(CONFIG_CPU_S3C6400)       += s3c6400.o
 obj-$(CONFIG_CPU_S3C6410)       += s3c6410.o
-obj-y                           += irq.o
+# PM
-obj-y                           += irq-eint.o
+obj-$(CONFIG_PM)                += pm.o irq-pm.o sleep.o
 # DMA support
 obj-$(CONFIG_S3C64XX_DMA)       += dma.o
-# Device setup
+# Device support
-obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
+obj-y                           += dev-uart.o
-obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
+obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
+obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
-obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
-obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
-obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
-obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
-# PM
+# Device setup
-obj-$(CONFIG_PM)                += pm.o
+obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP)    += setup-fb-24bpp.o
-obj-$(CONFIG_PM)                += sleep.o
+obj-$(CONFIG_S3C64XX_SETUP_I2C0)        += setup-i2c0.o
-obj-$(CONFIG_PM)                += irq-pm.o
+obj-$(CONFIG_S3C64XX_SETUP_I2C1)        += setup-i2c1.o
+obj-$(CONFIG_S3C64XX_SETUP_IDE)         += setup-ide.o
+obj-$(CONFIG_S3C64XX_SETUP_KEYPAD)      += setup-keypad.o
+obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_S3C64XX_SETUP_SPI)         += setup-spi.o
 # Machine support
-obj-$(CONFIG_MACH_ANW6410)      += mach-anw6410.o
+obj-$(CONFIG_MACH_ANW6410)              += mach-anw6410.o
-obj-$(CONFIG_MACH_SMDK6400)     += mach-smdk6400.o
+obj-$(CONFIG_MACH_HMT)                  += mach-hmt.o
-obj-$(CONFIG_MACH_SMDK6410)     += mach-smdk6410.o
+obj-$(CONFIG_MACH_MINI6410)             += mach-mini6410.o
-obj-$(CONFIG_MACH_REAL6410)     += mach-real6410.o
+obj-$(CONFIG_MACH_NCP)                  += mach-ncp.o
-obj-$(CONFIG_MACH_MINI6410)     += mach-mini6410.o
+obj-$(CONFIG_MACH_REAL6410)             += mach-real6410.o
-obj-$(CONFIG_MACH_NCP)          += mach-ncp.o
+obj-$(CONFIG_MACH_SMARTQ)               += mach-smartq.o
-obj-$(CONFIG_MACH_HMT)          += mach-hmt.o
+obj-$(CONFIG_MACH_SMARTQ5)              += mach-smartq5.o
-obj-$(CONFIG_MACH_SMARTQ)       += mach-smartq.o
+obj-$(CONFIG_MACH_SMARTQ7)              += mach-smartq7.o
-obj-$(CONFIG_MACH_SMARTQ5)      += mach-smartq5.o
+obj-$(CONFIG_MACH_SMDK6400)             += mach-smdk6400.o
-obj-$(CONFIG_MACH_SMARTQ7)      += mach-smartq7.o
+obj-$(CONFIG_MACH_SMDK6410)             += mach-smdk6410.o
-obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o mach-crag6410-module.o
+obj-$(CONFIG_MACH_WLF_CRAGG_6410)       += mach-crag6410.o mach-crag6410-module.o
-# device support
-obj-y                           += dev-uart.o
-obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 39c238d7a3d..31bb27dc4ae 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -184,18 +184,6 @@ static struct clk init_clocks_off[] = {
                .enable         = s3c64xx_pclk_ctrl,
                .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
        }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.0",
-                .parent         = &clk_48m,
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
-        }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.1",
-                .parent         = &clk_48m,
-                .enable         = s3c64xx_sclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
-        }, {
                .name           = "48m",
                .devname        = "s3c-sdhci.0",
                .parent         = &clk_48m,
@@ -226,6 +214,22 @@ static struct clk init_clocks_off[] = {
        },
 };
+static struct clk clk_48m_spi0 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.0",
+        .parent         = &clk_48m,
+        .enable         = s3c64xx_sclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
+};
+static struct clk clk_48m_spi1 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.1",
+        .parent         = &clk_48m,
+        .enable         = s3c64xx_sclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
+};
 static struct clk init_clocks[] = {
        {
                .name           = "lcd",
@@ -243,24 +247,6 @@ static struct clk init_clocks[] = {
                .enable         = s3c64xx_hclk_ctrl,
                .ctrlbit        = S3C_CLKCON_HCLK_UHOST,
        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_h,
-                .enable         = s3c64xx_hclk_ctrl,
-                .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
-        }, {
                .name           = "otg",
                .parent         = &clk_h,
                .enable         = s3c64xx_hclk_ctrl,
@@ -310,6 +296,29 @@ static struct clk init_clocks[] = {
        }
 };
+static struct clk clk_hsmmc0 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.0",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC0,
+};
+static struct clk clk_hsmmc1 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC1,
+};
+static struct clk clk_hsmmc2 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.2",
+        .parent         = &clk_h,
+        .enable         = s3c64xx_hclk_ctrl,
+        .ctrlbit        = S3C_CLKCON_HCLK_HSMMC2,
+};
 static struct clk clk_fout_apll = {
        .name           = "fout_apll",
@@ -578,36 +587,6 @@ static struct clksrc_sources clkset_camif = {
 static struct clksrc_clk clksrcs[] = {
        {
                .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "mmc_bus",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
                        .name           = "usb-bus-host",
                        .ctrlbit        = S3C_CLKCON_SCLK_UHOST,
                        .enable         = s3c64xx_sclk_ctrl,
@@ -617,35 +596,6 @@ static struct clksrc_clk clksrcs[] = {
                .sources        = &clkset_uhost,
        }, {
                .clk    = {
-                        .name           = "uclk1",
-                        .ctrlbit        = S3C_CLKCON_SCLK_UART,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
-                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
-                .sources        = &clkset_uart,
-        }, {
-/* Where does UCLK0 come from? */
-                .clk    = {
-                        .name           = "spi-bus",
-                        .devname        = "s3c64xx-spi.0",
-                        .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
-                        .name           = "spi-bus",
-                        .devname        = "s3c64xx-spi.1",
-                        .enable         = s3c64xx_sclk_ctrl,
-                },
-                .reg_src        = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2  },
-                .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4  },
-                .sources        = &clkset_spi_mmc,
-        }, {
-                .clk    = {
                        .name           = "audio-bus",
                        .devname        = "samsung-i2s.0",
                        .ctrlbit        = S3C_CLKCON_SCLK_AUDIO0,
@@ -695,6 +645,78 @@ static struct clksrc_clk clksrcs[] = {
        },
 };
+/* Where does UCLK0 come from? */
+static struct clksrc_clk clk_sclk_uclk = {
+        .clk    = {
+                .name           = "uclk1",
+                .ctrlbit        = S3C_CLKCON_SCLK_UART,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1  },
+        .reg_div        = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4  },
+        .sources        = &clkset_uart,
+};
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC0,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC1,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "mmc_bus",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = S3C_CLKCON_SCLK_MMC2,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src        = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2  },
+        .reg_div        = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4  },
+        .sources        = &clkset_spi_mmc,
+};
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "spi-bus",
+                .devname        = "s3c64xx-spi.0",
+                .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src = { .reg = S3C_CLK_SRC, .shift = 14, .size = 2 },
+        .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
+        .sources = &clkset_spi_mmc,
+};
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "spi-bus",
+                .devname        = "s3c64xx-spi.1",
+                .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
+                .enable         = s3c64xx_sclk_ctrl,
+        },
+        .reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
+        .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
+        .sources = &clkset_spi_mmc,
+};
 /* Clock initialisation code */
 static struct clksrc_clk *init_parents[] = {
@@ -703,9 +725,42 @@ static struct clksrc_clk *init_parents[] = {
        &clk_mout_mpll,
 };
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uclk,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+};
+static struct clk *clk_cdev[] = {
+        &clk_hsmmc0,
+        &clk_hsmmc1,
+        &clk_hsmmc2,
+        &clk_48m_spi0,
+        &clk_48m_spi1,
+};
+static struct clk_lookup s3c64xx_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
+};
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
-void __init_or_cpufreq s3c6400_setup_clocks(void)
+void __init_or_cpufreq s3c64xx_setup_clocks(void)
 {
        struct clk *xtal_clk;
        unsigned long xtal;
@@ -804,13 +859,15 @@ static struct clk *clks[] __initdata = {
 * as ARMCLK as well as the necessary parent clocks.
 *
 * This call does not setup the clocks, which is left to the
- * s3c6400_setup_clocks() call which may be needed by the cpufreq
+ * s3c64xx_setup_clocks() call which may be needed by the cpufreq
 * or resume code to re-set the clocks if the bootloader has changed
 * them.
 */
 void __init s3c64xx_register_clocks(unsigned long xtal, 
                                    unsigned armclk_divlimit)
 {
+        unsigned int cnt;
        armclk_mask = armclk_divlimit;
        s3c24xx_register_baseclocks(xtal);
@@ -821,7 +878,15 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
+                s3c_disable_clocks(clk_cdev[cnt], 1);
        s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+        for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
+                s3c_register_clksrc(clksrc_cdev[cnt], 1);
+        clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
        s3c_pwmclk_init();
 }
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
new file mode 100644
index 00000000000..4a7394d4bd9
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Common Codes for S3C64XX machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+#include <mach/hardware.h>
+#include <mach/regs-gpio.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/pm.h>
+#include <plat/gpio-cfg.h>
+#include <plat/irq-uart.h>
+#include <plat/irq-vic-timer.h>
+#include <plat/regs-irqtype.h>
+#include <plat/regs-serial.h>
+#include <plat/watchdog-reset.h>
+#include "common.h"
+/* uart registration process */
+void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
+}
+/* table of supported CPUs */
+static const char name_s3c6400[] = "S3C6400";
+static const char name_s3c6410[] = "S3C6410";
+static struct cpu_table cpu_ids[] __initdata = {
+        {
+                .idcode         = S3C6400_CPU_ID,
+                .idmask         = S3C64XX_CPU_MASK,
+                .map_io         = s3c6400_map_io,
+                .init_clocks    = s3c6400_init_clocks,
+                .init_uarts     = s3c64xx_init_uarts,
+                .init           = s3c6400_init,
+                .name           = name_s3c6400,
+        }, {
+                .idcode         = S3C6410_CPU_ID,
+                .idmask         = S3C64XX_CPU_MASK,
+                .map_io         = s3c6410_map_io,
+                .init_clocks    = s3c6410_init_clocks,
+                .init_uarts     = s3c64xx_init_uarts,
+                .init           = s3c6410_init,
+                .name           = name_s3c6410,
+        },
+};
+/* minimal IO mapping */
+/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
+#define UART_OFFS (S3C_PA_UART & 0xfffff)
+static struct map_desc s3c_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_SYS,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_SYSCON),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_MEM,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_SROM),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)(S3C_VA_UART + UART_OFFS),
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_TIMER,
+                .pfn            = __phys_to_pfn(S3C_PA_TIMER),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C64XX_VA_GPIO,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C64XX_VA_MODEM,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+                .pfn            = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
+                .length         = SZ_1K,
+                .type           = MT_DEVICE,
+        },
+};
+static struct bus_type s3c64xx_subsys = {
+        .name           = "s3c64xx-core",
+        .dev_name       = "s3c64xx-core",
+};
+static struct device s3c64xx_dev = {
+        .bus    = &s3c64xx_subsys,
+};
+/* read cpu identification code */
+void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
+{
+        /* initialise the io descriptors we need for initialisation */
+        iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
+        iotable_init(mach_desc, size);
+        init_consistent_dma_size(SZ_8M);
+        /* detect cpu id */
+        s3c64xx_init_cpu();
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+}
+static __init int s3c64xx_dev_init(void)
+{
+        subsys_system_register(&s3c64xx_subsys, NULL);
+        return device_register(&s3c64xx_dev);
+}
+core_initcall(s3c64xx_dev_init);
+/*
+ * setup the sources the vic should advertise resume
+ * for, even though it is not doing the wake
+ * (set_irq_wake needs to be valid)
+ */
+#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
+#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
+                         1 << (IRQ_PENDN - IRQ_VIC1_BASE) |     \
+                         1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |    \
+                         1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |    \
+                         1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
+void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
+{
+        printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
+        /* initialise the pair of VICs */
+        vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
+        vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
+        /* add the timer sub-irqs */
+        s3c_init_vic_timer_irq(5, IRQ_TIMER0);
+}
+#define eint_offset(irq)        ((irq) - IRQ_EINT(0))
+#define eint_irq_to_bit(irq)    ((u32)(1 << eint_offset(irq)))
+static inline void s3c_irq_eint_mask(struct irq_data *data)
+{
+        u32 mask;
+        mask = __raw_readl(S3C64XX_EINT0MASK);
+        mask |= (u32)data->chip_data;
+        __raw_writel(mask, S3C64XX_EINT0MASK);
+}
+static void s3c_irq_eint_unmask(struct irq_data *data)
+{
+        u32 mask;
+        mask = __raw_readl(S3C64XX_EINT0MASK);
+        mask &= ~((u32)data->chip_data);
+        __raw_writel(mask, S3C64XX_EINT0MASK);
+}
+static inline void s3c_irq_eint_ack(struct irq_data *data)
+{
+        __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
+}
+static void s3c_irq_eint_maskack(struct irq_data *data)
+{
+        /* compiler should in-line these */
+        s3c_irq_eint_mask(data);
+        s3c_irq_eint_ack(data);
+}
+static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
+{
+        int offs = eint_offset(data->irq);
+        int pin, pin_val;
+        int shift;
+        u32 ctrl, mask;
+        u32 newvalue = 0;
+        void __iomem *reg;
+        if (offs > 27)
+                return -EINVAL;
+        if (offs <= 15)
+                reg = S3C64XX_EINT0CON0;
+        else
+                reg = S3C64XX_EINT0CON1;
+        switch (type) {
+        case IRQ_TYPE_NONE:
+                printk(KERN_WARNING "No edge setting!\n");
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                newvalue = S3C2410_EXTINT_RISEEDGE;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                newvalue = S3C2410_EXTINT_FALLEDGE;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                newvalue = S3C2410_EXTINT_BOTHEDGE;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                newvalue = S3C2410_EXTINT_LOWLEV;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                newvalue = S3C2410_EXTINT_HILEV;
+                break;
+        default:
+                printk(KERN_ERR "No such irq type %d", type);
+                return -1;
+        }
+        if (offs <= 15)
+                shift = (offs / 2) * 4;
+        else
+                shift = ((offs - 16) / 2) * 4;
+        mask = 0x7 << shift;
+        ctrl = __raw_readl(reg);
+        ctrl &= ~mask;
+        ctrl |= newvalue << shift;
+        __raw_writel(ctrl, reg);
+        /* set the GPIO pin appropriately */
+        if (offs < 16) {
+                pin = S3C64XX_GPN(offs);
+                pin_val = S3C_GPIO_SFN(2);
+        } else if (offs < 23) {
+                pin = S3C64XX_GPL(offs + 8 - 16);
+                pin_val = S3C_GPIO_SFN(3);
+        } else {
+                pin = S3C64XX_GPM(offs - 23);
+                pin_val = S3C_GPIO_SFN(3);
+        }
+        s3c_gpio_cfgpin(pin, pin_val);
+        return 0;
+}
+static struct irq_chip s3c_irq_eint = {
+        .name           = "s3c-eint",
+        .irq_mask       = s3c_irq_eint_mask,
+        .irq_unmask     = s3c_irq_eint_unmask,
+        .irq_mask_ack   = s3c_irq_eint_maskack,
+        .irq_ack        = s3c_irq_eint_ack,
+        .irq_set_type   = s3c_irq_eint_set_type,
+        .irq_set_wake   = s3c_irqext_wake,
+};
+/* s3c_irq_demux_eint
+ *
+ * This function demuxes the IRQ from the group0 external interrupts,
+ * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
+ * the specific handlers s3c_irq_demux_eintX_Y.
+ */
+static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
+{
+        u32 status = __raw_readl(S3C64XX_EINT0PEND);
+        u32 mask = __raw_readl(S3C64XX_EINT0MASK);
+        unsigned int irq;
+        status &= ~mask;
+        status >>= start;
+        status &= (1 << (end - start + 1)) - 1;
+        for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
+                if (status & 1)
+                        generic_handle_irq(irq);
+                status >>= 1;
+        }
+}
+static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_eint(0, 3);
+}
+static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_eint(4, 11);
+}
+static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_eint(12, 19);
+}
+static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_eint(20, 27);
+}
+static int __init s3c64xx_init_irq_eint(void)
+{
+        int irq;
+        for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
+                irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
+                irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
+        irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
+        irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
+        irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
+        return 0;
+}
+arch_initcall(s3c64xx_init_irq_eint);
+void s3c64xx_restart(char mode, const char *cmd)
+{
+        if (mode != 's')
+                arch_wdt_reset();
+        /* if all else fails, or mode was for soft, jump to 0 */
+        soft_restart(0);
+}
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h
new file mode 100644
index 00000000000..5eb9c9a7d73
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/common.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Common Header for S3C64XX machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_S3C64XX_COMMON_H
+#define __ARCH_ARM_MACH_S3C64XX_COMMON_H
+void s3c64xx_init_irq(u32 vic0, u32 vic1);
+void s3c64xx_init_io(struct map_desc *mach_desc, int size);
+void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
+void s3c64xx_setup_clocks(void);
+void s3c64xx_restart(char mode, const char *cmd);
+extern struct syscore_ops s3c64xx_irq_syscore_ops;
+#ifdef CONFIG_CPU_S3C6400
+extern  int s3c6400_init(void);
+extern void s3c6400_init_irq(void);
+extern void s3c6400_map_io(void);
+extern void s3c6400_init_clocks(int xtal);
+#else
+#define s3c6400_init_clocks NULL
+#define s3c6400_map_io NULL
+#define s3c6400_init NULL
+#endif
+#ifdef CONFIG_CPU_S3C6410
+extern  int s3c6410_init(void);
+extern void s3c6410_init_irq(void);
+extern void s3c6410_map_io(void);
+extern void s3c6410_init_clocks(int xtal);
+#else
+#define s3c6410_init_clocks NULL
+#define s3c6410_map_io NULL
+#define s3c6410_init NULL
+#endif
+#endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */
diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c
deleted file mode 100644
index de085b798aa..00000000000
--- a/arch/arm/mach-s3c64xx/cpu.c
+++ /dev/null
@@ -1,161 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/cpu.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX CPU Support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/sysdev.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/dma-mapping.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <plat/regs-serial.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/s3c6400.h>
-#include <plat/s3c6410.h>
-/* table of supported CPUs */
-static const char name_s3c6400[] = "S3C6400";
-static const char name_s3c6410[] = "S3C6410";
-static struct cpu_table cpu_ids[] __initdata = {
-        {
-                .idcode         = S3C6400_CPU_ID,
-                .idmask         = S3C64XX_CPU_MASK,
-                .map_io         = s3c6400_map_io,
-                .init_clocks    = s3c6400_init_clocks,
-                .init_uarts     = s3c6400_init_uarts,
-                .init           = s3c6400_init,
-                .name           = name_s3c6400,
-        }, {
-                .idcode         = S3C6410_CPU_ID,
-                .idmask         = S3C64XX_CPU_MASK,
-                .map_io         = s3c6410_map_io,
-                .init_clocks    = s3c6410_init_clocks,
-                .init_uarts     = s3c6410_init_uarts,
-                .init           = s3c6410_init,
-                .name           = name_s3c6410,
-        },
-};
-/* minimal IO mapping */
-/* see notes on uart map in arch/arm/mach-s3c6400/include/mach/debug-macro.S */
-#define UART_OFFS (S3C_PA_UART & 0xfffff)
-static struct map_desc s3c_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S3C_VA_SYS,
-                .pfn            = __phys_to_pfn(S3C64XX_PA_SYSCON),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_MEM,
-                .pfn            = __phys_to_pfn(S3C64XX_PA_SROM),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)(S3C_VA_UART + UART_OFFS),
-                .pfn            = __phys_to_pfn(S3C_PA_UART),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC0,
-                .pfn            = __phys_to_pfn(S3C64XX_PA_VIC0),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC1,
-                .pfn            = __phys_to_pfn(S3C64XX_PA_VIC1),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_TIMER,
-                .pfn            = __phys_to_pfn(S3C_PA_TIMER),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C64XX_VA_GPIO,
-                .pfn            = __phys_to_pfn(S3C64XX_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C64XX_VA_MODEM,
-                .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
-                .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
-                .pfn            = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
-                .length         = SZ_1K,
-                .type           = MT_DEVICE,
-        },
-};
-struct sysdev_class s3c64xx_sysclass = {
-        .name   = "s3c64xx-core",
-};
-static struct sys_device s3c64xx_sysdev = {
-        .cls    = &s3c64xx_sysclass,
-};
-/* uart registration process */
-void __init s3c6400_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
-}
-/* read cpu identification code */
-void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
-{
-        /* initialise the io descriptors we need for initialisation */
-        iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
-        iotable_init(mach_desc, size);
-        init_consistent_dma_size(SZ_8M);
-        /* detect cpu id */
-        s3c64xx_init_cpu();
-        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
-}
-static __init int s3c64xx_sysdev_init(void)
-{
-        sysdev_class_register(&s3c64xx_sysclass);
-        return sysdev_register(&s3c64xx_sysdev);
-}
-core_initcall(s3c64xx_sysdev_init);
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
deleted file mode 100644
index 3341fd11872..00000000000
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/dev-spi.c
- *
- * Copyright (C) 2009 Samsung Electronics Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/spi-clocks.h>
-#include <mach/irqs.h>
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-#include <plat/devs.h>
-static char *spi_src_clks[] = {
-        [S3C64XX_SPI_SRCCLK_PCLK] = "pclk",
-        [S3C64XX_SPI_SRCCLK_SPIBUS] = "spi-bus",
-        [S3C64XX_SPI_SRCCLK_48M] = "spi_48m",
-};
-/* SPI Controller platform_devices */
-/* Since we emulate multi-cs capability, we do not touch the GPC-3,7.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
-{
-        unsigned int base;
-        switch (pdev->id) {
-        case 0:
-                base = S3C64XX_GPC(0);
-                break;
-        case 1:
-                base = S3C64XX_GPC(4);
-                break;
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-        s3c_gpio_cfgall_range(base, 3,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-static struct resource s3c64xx_spi0_resource[] = {
-        [0] = {
-                .start = S3C64XX_PA_SPI0,
-                .end   = S3C64XX_PA_SPI0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI0_TX,
-                .end   = DMACH_SPI0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI0_RX,
-                .end   = DMACH_SPI0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI0,
-                .end   = IRQ_SPI0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
-        .cfg_gpio = s3c64xx_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .tx_st_done = 21,
-};
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-struct platform_device s3c64xx_device_spi0 = {
-        .name             = "s3c64xx-spi",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s3c64xx_spi0_resource),
-        .resource         = s3c64xx_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s3c64xx_spi0_pdata,
-        },
-};
-EXPORT_SYMBOL(s3c64xx_device_spi0);
-static struct resource s3c64xx_spi1_resource[] = {
-        [0] = {
-                .start = S3C64XX_PA_SPI1,
-                .end   = S3C64XX_PA_SPI1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI1_TX,
-                .end   = DMACH_SPI1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI1_RX,
-                .end   = DMACH_SPI1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI1,
-                .end   = IRQ_SPI1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
-        .cfg_gpio = s3c64xx_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .tx_st_done = 21,
-};
-struct platform_device s3c64xx_device_spi1 = {
-        .name             = "s3c64xx-spi",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s3c64xx_spi1_resource),
-        .resource         = s3c64xx_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s3c64xx_spi1_pdata,
-        },
-};
-EXPORT_SYMBOL(s3c64xx_device_spi1);
-void __init s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S3C64XX_SPI_SRCCLK_48M) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-        switch (cntrlr) {
-        case 0:
-                pd = &s3c64xx_spi0_pdata;
-                break;
-        case 1:
-                pd = &s3c64xx_spi1_pdata;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 17d62f4f820..f2a7a172559 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -16,7 +16,7 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/dmapool.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/slab.h>
 #include <linux/delay.h>
@@ -35,7 +35,7 @@
 /* dma channel state information */
 struct s3c64xx_dmac {
-        struct sys_device        sysdev;
+        struct device           dev;
        struct clk              *clk;
        void __iomem            *regs;
        struct s3c2410_dma_chan *channels;
@@ -631,8 +631,9 @@ static irqreturn_t s3c64xx_dma_irq(int irq, void *pw)
        return IRQ_HANDLED;
 }
-static struct sysdev_class dma_sysclass = {
+static struct bus_type dma_subsys = {
        .name           = "s3c64xx-dma",
+        .dev_name       = "s3c64xx-dma",
 };
 static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
@@ -651,12 +652,12 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
                return -ENOMEM;
        }
-        dmac->sysdev.id = chno / 8;
+        dmac->dev.id = chno / 8;
-        dmac->sysdev.cls = &dma_sysclass;
+        dmac->dev.bus = &dma_subsys;
-        err = sysdev_register(&dmac->sysdev);
+        err = device_register(&dmac->dev);
        if (err) {
-                printk(KERN_ERR "%s: failed to register sysdevice\n", __func__);
+                printk(KERN_ERR "%s: failed to register device\n", __func__);
                goto err_alloc;
        }
@@ -667,7 +668,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
                goto err_dev;
        }
-        snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
+        snprintf(clkname, sizeof(clkname), "dma%d", dmac->dev.id);
        dmac->clk = clk_get(NULL, clkname);
        if (IS_ERR(dmac->clk)) {
@@ -715,7 +716,7 @@ err_clk:
 err_map:
        iounmap(regs);
 err_dev:
-        sysdev_unregister(&dmac->sysdev);
+        device_unregister(&dmac->dev);
 err_alloc:
        kfree(dmac);
        return err;
@@ -733,9 +734,9 @@ static int __init s3c64xx_dma_init(void)
                return -ENOMEM;
        }
-        ret = sysdev_class_register(&dma_sysclass);
+        ret = subsys_system_register(&dma_subsys, NULL);
        if (ret) {
-                printk(KERN_ERR "%s: failed to create sysclass\n", __func__);
+                printk(KERN_ERR "%s: failed to create subsys\n", __func__);
                return -ENOMEM;
        }
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
index be9074e17df..4cb2f951f1e 100644
--- a/arch/arm/mach-s3c64xx/include/mach/crag6410.h
+++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
@@ -15,9 +15,12 @@
 #define BANFF_PMIC_IRQ_BASE             IRQ_BOARD_START
 #define GLENFARCLAS_PMIC_IRQ_BASE       (IRQ_BOARD_START + 64)
+#define CODEC_IRQ_BASE                  (IRQ_BOARD_START + 128)
 #define PCA935X_GPIO_BASE               GPIO_BOARD_START
-#define CODEC_GPIO_BASE         (GPIO_BOARD_START + 8)
+#define CODEC_GPIO_BASE                 (GPIO_BOARD_START + 8)
-#define GLENFARCLAS_PMIC_GPIO_BASE      (GPIO_BOARD_START + 16)
+#define GLENFARCLAS_PMIC_GPIO_BASE      (GPIO_BOARD_START + 32)
+#define BANFF_PMIC_GPIO_BASE            (GPIO_BOARD_START + 64)
+#define MMGPIO_GPIO_BASE                (GPIO_BOARD_START + 96)
 #endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
index dd362604dcc..dc2bc15142c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
+++ b/arch/arm/mach-s3c64xx/include/mach/entry-macro.S
@@ -12,7 +12,8 @@
 * warranty of any kind, whether express or implied.
 */
-#include <mach/map.h>
+                .macro  disable_fiq
-#include <mach/irqs.h>
+                .endm
-#include <asm/entry-macro-vic2.S>
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio.h b/arch/arm/mach-s3c64xx/include/mach/gpio.h
index 6e34c2f6e67..8b540c42d5d 100644
--- a/arch/arm/mach-s3c64xx/include/mach/gpio.h
+++ b/arch/arm/mach-s3c64xx/include/mach/gpio.h
@@ -88,6 +88,6 @@ enum s3c_gpio_number {
 /* define the number of gpios we need to the one after the GPQ() range */
 #define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
-#define BOARD_NR_GPIOS 16
+#define BOARD_NR_GPIOS  (16 + CONFIG_SAMSUNG_GPIO_EXTRA)
 #define ARCH_NR_GPIOS   (GPIO_BOARD_START + BOARD_NR_GPIOS)
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index 443f85b3c20..96d60e0d937 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -169,7 +169,7 @@
 #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
 #ifdef CONFIG_MACH_WLF_CRAGG_6410
-#define IRQ_BOARD_NR 128
+#define IRQ_BOARD_NR 160
 #elif defined(CONFIG_SMDK6410_WM1190_EV1)
 #define IRQ_BOARD_NR 64
 #elif defined(CONFIG_SMDK6410_WM1192_EV1)
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 23a1d71e4d5..8e2097bb208 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -115,6 +115,8 @@
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
 #define S3C_PA_RTC              S3C64XX_PA_RTC
 #define S3C_PA_WDT              S3C64XX_PA_WATCHDOG
+#define S3C_PA_SPI0             S3C64XX_PA_SPI0
+#define S3C_PA_SPI1             S3C64XX_PA_SPI1
 #define SAMSUNG_PA_ADC          S3C64XX_PA_ADC
 #define SAMSUNG_PA_CFCON        S3C64XX_PA_CFCON
diff --git a/arch/arm/mach-s3c64xx/include/mach/system.h b/arch/arm/mach-s3c64xx/include/mach/system.h
index 2e58cb7a714..353ed4389ae 100644
--- a/arch/arm/mach-s3c64xx/include/mach/system.h
+++ b/arch/arm/mach-s3c64xx/include/mach/system.h
@@ -11,20 +11,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
-#include <plat/watchdog-reset.h>
 static void arch_idle(void)
 {
        /* nothing here yet */
 }
-static void arch_reset(char mode, const char *cmd)
-{
-        if (mode != 's')
-                arch_wdt_reset();
-        /* if all else fails, or mode was for soft, jump to 0 */
-        cpu_reset(0);
-}
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
deleted file mode 100644
index 23f75e556a3..00000000000
--- a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* arch/arm/mach-s3c64xx/include/mach/vmalloc.h
- *
- * from arch/arm/mach-iop3xx/include/mach/vmalloc.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C6400 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c
deleted file mode 100644
index 4d203be1f4c..00000000000
--- a/arch/arm/mach-s3c64xx/irq-eint.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* arch/arm/plat-s3c64xx/irq-eint.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX - Interrupt handling for IRQ_EINT(x)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/sysdev.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <asm/hardware/vic.h>
-#include <plat/regs-irqtype.h>
-#include <mach/regs-gpio.h>
-#include <plat/gpio-cfg.h>
-#include <mach/map.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#define eint_offset(irq)        ((irq) - IRQ_EINT(0))
-#define eint_irq_to_bit(irq)    ((u32)(1 << eint_offset(irq)))
-static inline void s3c_irq_eint_mask(struct irq_data *data)
-{
-        u32 mask;
-        mask = __raw_readl(S3C64XX_EINT0MASK);
-        mask |= (u32)data->chip_data;
-        __raw_writel(mask, S3C64XX_EINT0MASK);
-}
-static void s3c_irq_eint_unmask(struct irq_data *data)
-{
-        u32 mask;
-        mask = __raw_readl(S3C64XX_EINT0MASK);
-        mask &= ~((u32)data->chip_data);
-        __raw_writel(mask, S3C64XX_EINT0MASK);
-}
-static inline void s3c_irq_eint_ack(struct irq_data *data)
-{
-        __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
-}
-static void s3c_irq_eint_maskack(struct irq_data *data)
-{
-        /* compiler should in-line these */
-        s3c_irq_eint_mask(data);
-        s3c_irq_eint_ack(data);
-}
-static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
-{
-        int offs = eint_offset(data->irq);
-        int pin, pin_val;
-        int shift;
-        u32 ctrl, mask;
-        u32 newvalue = 0;
-        void __iomem *reg;
-        if (offs > 27)
-                return -EINVAL;
-        if (offs <= 15)
-                reg = S3C64XX_EINT0CON0;
-        else
-                reg = S3C64XX_EINT0CON1;
-        switch (type) {
-        case IRQ_TYPE_NONE:
-                printk(KERN_WARNING "No edge setting!\n");
-                break;
-        case IRQ_TYPE_EDGE_RISING:
-                newvalue = S3C2410_EXTINT_RISEEDGE;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                newvalue = S3C2410_EXTINT_FALLEDGE;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                newvalue = S3C2410_EXTINT_BOTHEDGE;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                newvalue = S3C2410_EXTINT_LOWLEV;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                newvalue = S3C2410_EXTINT_HILEV;
-                break;
-        default:
-                printk(KERN_ERR "No such irq type %d", type);
-                return -1;
-        }
-        if (offs <= 15)
-                shift = (offs / 2) * 4;
-        else
-                shift = ((offs - 16) / 2) * 4;
-        mask = 0x7 << shift;
-        ctrl = __raw_readl(reg);
-        ctrl &= ~mask;
-        ctrl |= newvalue << shift;
-        __raw_writel(ctrl, reg);
-        /* set the GPIO pin appropriately */
-        if (offs < 16) {
-                pin = S3C64XX_GPN(offs);
-                pin_val = S3C_GPIO_SFN(2);
-        } else if (offs < 23) {
-                pin = S3C64XX_GPL(offs + 8 - 16);
-                pin_val = S3C_GPIO_SFN(3);
-        } else {
-                pin = S3C64XX_GPM(offs - 23);
-                pin_val = S3C_GPIO_SFN(3);
-        }
-        s3c_gpio_cfgpin(pin, pin_val);
-        return 0;
-}
-static struct irq_chip s3c_irq_eint = {
-        .name           = "s3c-eint",
-        .irq_mask       = s3c_irq_eint_mask,
-        .irq_unmask     = s3c_irq_eint_unmask,
-        .irq_mask_ack   = s3c_irq_eint_maskack,
-        .irq_ack        = s3c_irq_eint_ack,
-        .irq_set_type   = s3c_irq_eint_set_type,
-        .irq_set_wake   = s3c_irqext_wake,
-};
-/* s3c_irq_demux_eint
- *
- * This function demuxes the IRQ from the group0 external interrupts,
- * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
- * the specific handlers s3c_irq_demux_eintX_Y.
- */
-static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
-{
-        u32 status = __raw_readl(S3C64XX_EINT0PEND);
-        u32 mask = __raw_readl(S3C64XX_EINT0MASK);
-        unsigned int irq;
-        status &= ~mask;
-        status >>= start;
-        status &= (1 << (end - start + 1)) - 1;
-        for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
-                if (status & 1)
-                        generic_handle_irq(irq);
-                status >>= 1;
-        }
-}
-static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
-{
-        s3c_irq_demux_eint(0, 3);
-}
-static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
-{
-        s3c_irq_demux_eint(4, 11);
-}
-static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
-{
-        s3c_irq_demux_eint(12, 19);
-}
-static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
-{
-        s3c_irq_demux_eint(20, 27);
-}
-static int __init s3c64xx_init_irq_eint(void)
-{
-        int irq;
-        for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
-                irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
-                irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
-                set_irq_flags(irq, IRQF_VALID);
-        }
-        irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
-        irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
-        irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
-        irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
-        return 0;
-}
-arch_initcall(s3c64xx_init_irq_eint);
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
deleted file mode 100644
index b07357e9495..00000000000
--- a/arch/arm/mach-s3c64xx/irq.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/* arch/arm/plat-s3c64xx/irq.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C64XX - Interrupt handling
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/serial_core.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <asm/hardware/vic.h>
-#include <mach/map.h>
-#include <plat/irq-vic-timer.h>
-#include <plat/irq-uart.h>
-#include <plat/cpu.h>
-/* setup the sources the vic should advertise resume for, even though it
- * is not doing the wake (set_irq_wake needs to be valid) */
-#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
-#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
-                         1 << (IRQ_PENDN - IRQ_VIC1_BASE) |     \
-                         1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |    \
-                         1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |    \
-                         1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
-void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
-{
-        printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
-        /* initialise the pair of VICs */
-        vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
-        vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
-        /* add the timer sub-irqs */
-        s3c_init_vic_timer_irq(5, IRQ_TIMER0);
-}
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 8eba88e7209..b86f2779e4e 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -30,6 +30,7 @@
 #include <video/platform_lcd.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -45,13 +46,14 @@
 #include <plat/fb.h>
 #include <plat/regs-fb-v4.h>
-#include <plat/s3c6410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-modem.h>
+#include "common.h"
 /* DM9000 */
 #define ANW6410_PA_DM9000       (0x18000000)
@@ -236,7 +238,9 @@ MACHINE_START(ANW6410, "A&W6410")
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = anw6410_map_io,
        .init_machine   = anw6410_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410-module.c b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
index f208154b138..cd3c97e2ee7 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410-module.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410-module.c
@@ -14,13 +14,43 @@
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
+#include <linux/mfd/wm8994/pdata.h>
+#include <sound/wm5100.h>
 #include <sound/wm8996.h>
 #include <sound/wm8962.h>
 #include <sound/wm9081.h>
 #include <mach/crag6410.h>
+static struct wm5100_pdata wm5100_pdata = {
+        .ldo_ena = S3C64XX_GPN(7),
+        .irq_flags = IRQF_TRIGGER_HIGH,
+        .gpio_base = CODEC_GPIO_BASE,
+        .in_mode = {
+                WM5100_IN_DIFF,
+                WM5100_IN_DIFF,
+                WM5100_IN_DIFF,
+                WM5100_IN_SE,
+        },
+        .hp_pol = CODEC_GPIO_BASE + 3,
+        .jack_modes = {
+                { WM5100_MICDET_MICBIAS3, 0, 0 },
+                { WM5100_MICDET_MICBIAS2, 1, 1 },
+        },
+        .gpio_defaults = {
+                0,
+                0,
+                0,
+                0,
+                0x2, /* IRQ: CMOS output */
+                0x3, /* CLKOUT: CMOS output */
+        },
+};
 static struct wm8996_retune_mobile_config wm8996_retune[] = {
        {
                .name = "Sub LPF",
@@ -72,7 +102,6 @@ static struct wm8962_pdata wm8962_pdata __initdata = {
                0x8000 | WM8962_GPIO_FN_DMICDAT,
                WM8962_GPIO_FN_IRQ,    /* Open drain mode */
        },
-        .irq_active_low = true,
 };
 static struct wm9081_pdata wm9081_pdata __initdata = {
@@ -91,6 +120,7 @@ static const struct i2c_board_info wm1254_devs[] = {
 static const struct i2c_board_info wm1255_devs[] = {
        { I2C_BOARD_INFO("wm5100", 0x1a),
+          .platform_data = &wm5100_pdata,
          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
        },
        { I2C_BOARD_INFO("wm9081", 0x6c),
@@ -104,6 +134,24 @@ static const struct i2c_board_info wm1259_devs[] = {
        },
 };
+static struct wm8994_pdata wm8994_pdata = {
+        .gpio_base = CODEC_GPIO_BASE,
+        .gpio_defaults = {
+                0x3,          /* IRQ out, active high, CMOS */
+        },
+        .irq_base = CODEC_IRQ_BASE,
+        .ldo = {
+                { .supply = "WALLVDD" },
+                { .supply = "WALLVDD" },
+        },
+};
+static const struct i2c_board_info wm1277_devs[] = {
+        { I2C_BOARD_INFO("wm8958", 0x1a),  /* WM8958 is the superset */
+          .platform_data = &wm8994_pdata,
+          .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
+        },
+};
 static __devinitdata const struct {
        u8 id;
@@ -125,6 +173,8 @@ static __devinitdata const struct {
        { .id = 0x3b, .name = "1255-EV1 Kilchoman",
          .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
        { .id = 0x3c, .name = "1273-EV1 Longmorn" },
+        { .id = 0x3d, .name = "1277-EV1 Littlemill",
+          .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs) },
 };
 static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
@@ -154,8 +204,8 @@ static __devinit int wlf_gf_module_probe(struct i2c_client *i2c,
                                        "Failed to register dev: %d\n", ret);
                }
        } else {
-                dev_warn(&i2c->dev, "Unknown module ID %d revision %d\n",
+                dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
-                         id, rev);
+                         id, rev + 1);
        }
        return 0;
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index d04b6544851..8077f650eb0 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -37,6 +37,9 @@
 #include <linux/mfd/wm831x/irq.h>
 #include <linux/mfd/wm831x/gpio.h>
+#include <sound/wm1250-ev1.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -50,7 +53,6 @@
 #include <mach/regs-gpio-memport.h>
-#include <plat/s3c6410.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
@@ -66,6 +68,8 @@
 #include <plat/iic.h>
 #include <plat/pm.h>
+#include "common.h"
 /* serial port setup */
 #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
@@ -256,6 +260,7 @@ static struct platform_device crag6410_dm9k_device = {
 static struct resource crag6410_mmgpio_resource[] = {
        [0] = {
+                .name   = "dat",
                .start  = S3C64XX_PA_XM0CSN4 + 1,
                .end    = S3C64XX_PA_XM0CSN4 + 1,
                .flags  = IORESOURCE_MEM,
@@ -268,7 +273,7 @@ static struct platform_device crag6410_mmgpio = {
        .resource       = crag6410_mmgpio_resource,
        .num_resources  = ARRAY_SIZE(crag6410_mmgpio_resource),
        .dev.platform_data = &(struct bgpio_pdata) {
-                .base   = -1,
+                .base   = MMGPIO_GPIO_BASE,
        },
 };
@@ -282,8 +287,13 @@ static struct platform_device lowland_device = {
        .id             = -1,
 };
-static struct platform_device speyside_wm8962_device = {
+static struct platform_device tobermory_device = {
-        .name           = "speyside-wm8962",
+        .name           = "tobermory",
+        .id             = -1,
+};
+static struct platform_device littlemill_device = {
+        .name           = "littlemill",
        .id             = -1,
 };
@@ -319,7 +329,6 @@ static struct platform_device wallvdd_device = {
 static struct platform_device *crag6410_devices[] __initdata = {
        &s3c_device_hsmmc0,
-        &s3c_device_hsmmc1,
        &s3c_device_hsmmc2,
        &s3c_device_i2c0,
        &s3c_device_i2c1,
@@ -338,14 +347,15 @@ static struct platform_device *crag6410_devices[] __initdata = {
        &crag6410_lcd_powerdev,
        &crag6410_backlight_device,
        &speyside_device,
-        &speyside_wm8962_device,
+        &tobermory_device,
+        &littlemill_device,
        &lowland_device,
        &wallvdd_device,
 };
 static struct pca953x_platform_data crag6410_pca_data = {
        .gpio_base      = PCA935X_GPIO_BASE,
-        .irq_base       = 0,
+        .irq_base       = -1,
 };
 /* VDDARM is controlled by DVS1 connected to GPK(0) */
@@ -372,6 +382,10 @@ static struct regulator_init_data vddarm __initdata = {
        .driver_data = &vddarm_pdata,
 };
+static struct regulator_consumer_supply vddint_consumers[] __initdata = {
+        REGULATOR_SUPPLY("vddint", NULL),
+};
 static struct regulator_init_data vddint __initdata = {
        .constraints = {
                .name = "VDDINT",
@@ -380,6 +394,9 @@ static struct regulator_init_data vddint __initdata = {
                .always_on = 1,
                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
        },
+        .num_consumer_supplies = ARRAY_SIZE(vddint_consumers),
+        .consumer_supplies = vddint_consumers,
+        .supply_regulator = "WALLVDD",
 };
 static struct regulator_init_data vddmem __initdata = {
@@ -500,7 +517,8 @@ static struct wm831x_touch_pdata touch_pdata __initdata = {
 static struct wm831x_pdata crag_pmic_pdata __initdata = {
        .wm831x_num = 1,
        .irq_base = BANFF_PMIC_IRQ_BASE,
-        .gpio_base = GPIO_BOARD_START + 8,
+        .gpio_base = BANFF_PMIC_GPIO_BASE,
+        .soft_shutdown = true,
        .backup = &banff_backup_pdata,
@@ -605,6 +623,7 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
        .wm831x_num = 2,
        .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
        .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
+        .soft_shutdown = true,
        .gpio_defaults = {
                /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
@@ -622,6 +641,16 @@ static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
        .disable_touch = true,
 };
+static struct wm1250_ev1_pdata wm1250_ev1_pdata = {
+        .gpios = {
+                [WM1250_EV1_GPIO_CLK_ENA] = S3C64XX_GPN(12),
+                [WM1250_EV1_GPIO_CLK_SEL0] = S3C64XX_GPL(12),
+                [WM1250_EV1_GPIO_CLK_SEL1] = S3C64XX_GPL(13),
+                [WM1250_EV1_GPIO_OSR] = S3C64XX_GPL(14),
+                [WM1250_EV1_GPIO_MASTER] = S3C64XX_GPL(8),
+        },
+};
 static struct i2c_board_info i2c_devs1[] __initdata = {
        { I2C_BOARD_INFO("wm8311", 0x34),
          .irq = S3C_EINT(0),
@@ -631,7 +660,13 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
        { I2C_BOARD_INFO("wlf-gf-module", 0x25) },
        { I2C_BOARD_INFO("wlf-gf-module", 0x26) },
-        { I2C_BOARD_INFO("wm1250-ev1", 0x27) },
+        { I2C_BOARD_INFO("wm1250-ev1", 0x27),
+          .platform_data = &wm1250_ev1_pdata },
+};
+static struct s3c2410_platform_i2c i2c1_pdata = {
+        .frequency = 400000,
+        .bus_num = 1,
 };
 static void __init crag6410_map_io(void)
@@ -648,12 +683,6 @@ static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
        .cd_type                = S3C_SDHCI_CD_PERMANENT,
 };
-static struct s3c_sdhci_platdata crag6410_hsmmc1_pdata = {
-        .max_width              = 4,
-        .cd_type                = S3C_SDHCI_CD_GPIO,
-        .ext_cd_gpio            = S3C64XX_GPF(11),
-};
 static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
 {
        /* Set all the necessary GPG pins to special-function 2 */
@@ -688,11 +717,10 @@ static void __init crag6410_machine_init(void)
        gpio_direction_output(S3C64XX_GPF(10), 1);
        s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
-        s3c_sdhci1_set_platdata(&crag6410_hsmmc1_pdata);
        s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
        s3c_i2c0_set_platdata(&i2c0_pdata);
-        s3c_i2c1_set_platdata(NULL);
+        s3c_i2c1_set_platdata(&i2c1_pdata);
        s3c_fb_set_platdata(&crag6410_lcd_pdata);
        i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
@@ -704,14 +732,16 @@ static void __init crag6410_machine_init(void)
        regulator_has_full_constraints();
-        s3c_pm_init();
+        s3c64xx_pm_init();
 }
 MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
        /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = crag6410_map_io,
        .init_machine   = crag6410_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 952f75ff5de..521e07b8501 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -29,6 +29,7 @@
 #include <mach/hardware.h>
 #include <mach/map.h>
+#include <asm/hardware/vic.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -37,12 +38,13 @@
 #include <plat/fb.h>
 #include <plat/nand.h>
-#include <plat/s3c6410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/regs-fb-v4.h>
+#include "common.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
@@ -267,7 +269,9 @@ MACHINE_START(HMT, "Airgoo-HMT")
        /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = hmt_map_io,
        .init_machine   = hmt_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 1bc85c35949..c34c2ab22ea 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -24,6 +24,7 @@
 #include <linux/serial_core.h>
 #include <linux/types.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -33,7 +34,6 @@
 #include <mach/regs-modem.h>
 #include <mach/regs-srom.h>
-#include <plat/s3c6410.h>
 #include <plat/adc.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
@@ -45,6 +45,8 @@
 #include <video/platform_lcd.h>
+#include "common.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
@@ -345,7 +347,9 @@ MACHINE_START(MINI6410, "MINI6410")
        /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = mini6410_map_io,
        .init_machine   = mini6410_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index cb13cba98b3..0efa2ba783b 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -25,6 +25,7 @@
 #include <video/platform_lcd.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -39,12 +40,13 @@
 #include <plat/iic.h>
 #include <plat/fb.h>
-#include <plat/s3c6410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/regs-fb-v4.h>
+#include "common.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
@@ -99,7 +101,9 @@ MACHINE_START(NCP, "NCP")
        /* Maintainer: Samsung Electronics */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = ncp_map_io,
        .init_machine   = ncp_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 87281e4b847..be2a9a22ab7 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -25,6 +25,7 @@
 #include <linux/serial_core.h>
 #include <linux/types.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -34,7 +35,6 @@
 #include <mach/regs-modem.h>
 #include <mach/regs-srom.h>
-#include <plat/s3c6410.h>
 #include <plat/adc.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
@@ -46,6 +46,8 @@
 #include <video/platform_lcd.h>
+#include "common.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
@@ -326,7 +328,9 @@ MACHINE_START(REAL6410, "REAL6410")
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = real6410_map_io,
        .init_machine   = real6410_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index cb1ebeb0876..ce31db13623 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -40,6 +40,8 @@
 #include <video/platform_lcd.h>
+#include "common.h"
 #define UCON S3C2410_UCON_DEFAULT
 #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
 #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 94c831d8836..3f42431d4dd 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -17,19 +17,20 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <plat/s3c6410.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-fb-v4.h>
+#include "common.h"
 #include "mach-smartq.h"
 static struct gpio_led smartq5_leds[] = {
@@ -148,7 +149,9 @@ MACHINE_START(SMARTQ5, "SmartQ 5")
        /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smartq_map_io,
        .init_machine   = smartq5_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index f112547ce80..e5c09b6db96 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -17,19 +17,20 @@
 #include <linux/leds.h>
 #include <linux/platform_device.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/map.h>
 #include <mach/regs-gpio.h>
-#include <plat/s3c6410.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-fb-v4.h>
+#include "common.h"
 #include "mach-smartq.h"
 static struct gpio_led smartq7_leds[] = {
@@ -164,7 +165,9 @@ MACHINE_START(SMARTQ7, "SmartQ 7")
        /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smartq_map_io,
        .init_machine   = smartq7_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 73450c2b530..5f096534f4c 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -22,6 +22,7 @@
 #include <asm/mach-types.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -31,12 +32,13 @@
 #include <plat/regs-serial.h>
-#include <plat/s3c6400.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/iic.h>
+#include "common.h"
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
@@ -88,7 +90,9 @@ MACHINE_START(SMDK6400, "SMDK6400")
        .atag_offset    = 0x100,
        .init_irq       = s3c6400_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6400_map_io,
        .init_machine   = smdk6400_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 8bc8edd85e5..ca6fc204f0e 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -43,6 +43,7 @@
 #include <video/platform_lcd.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>
@@ -63,7 +64,6 @@
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
-#include <plat/s3c6410.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -73,6 +73,8 @@
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
+#include "common.h"
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
@@ -700,7 +702,9 @@ MACHINE_START(SMDK6410, "SMDK6410")
        .atag_offset    = 0x100,
        .init_irq       = s3c6410_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6410_map_io,
        .init_machine   = smdk6410_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s3c64xx_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index b375cd5c47c..7d3e81b9dd0 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -17,10 +17,12 @@
 #include <linux/serial_core.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/pm_domain.h>
 #include <mach/map.h>
 #include <mach/irqs.h>
+#include <plat/devs.h>
 #include <plat/pm.h>
 #include <plat/wakeup-mask.h>
@@ -31,6 +33,148 @@
 #include <mach/regs-gpio-memport.h>
 #include <mach/regs-modem.h>
+struct s3c64xx_pm_domain {
+        char *const name;
+        u32 ena;
+        u32 pwr_stat;
+        struct generic_pm_domain pd;
+};
+static int s3c64xx_pd_off(struct generic_pm_domain *domain)
+{
+        struct s3c64xx_pm_domain *pd;
+        u32 val;
+        pd = container_of(domain, struct s3c64xx_pm_domain, pd);
+        val = __raw_readl(S3C64XX_NORMAL_CFG);
+        val &= ~(pd->ena);
+        __raw_writel(val, S3C64XX_NORMAL_CFG);
+        return 0;
+}
+static int s3c64xx_pd_on(struct generic_pm_domain *domain)
+{
+        struct s3c64xx_pm_domain *pd;
+        u32 val;
+        long retry = 1000000L;
+        pd = container_of(domain, struct s3c64xx_pm_domain, pd);
+        val = __raw_readl(S3C64XX_NORMAL_CFG);
+        val |= pd->ena;
+        __raw_writel(val, S3C64XX_NORMAL_CFG);
+        /* Not all domains provide power status readback */
+        if (pd->pwr_stat) {
+                do {
+                        cpu_relax();
+                        if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
+                                break;
+                } while (retry--);
+                if (!retry) {
+                        pr_err("Failed to start domain %s\n", pd->name);
+                        return -EBUSY;
+                }
+        }
+        return 0;
+}
+static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
+        .name = "IROM",
+        .ena = S3C64XX_NORMALCFG_IROM_ON,
+        .pd = {
+                .power_off = s3c64xx_pd_off,
+                .power_on = s3c64xx_pd_on,
+        },
+};
+static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
+        .name = "ETM",
+        .ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
+        .pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
+        .pd = {
+                .power_off = s3c64xx_pd_off,
+                .power_on = s3c64xx_pd_on,
+        },
+};
+static struct s3c64xx_pm_domain s3c64xx_pm_s = {
+        .name = "S",
+        .ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
+        .pwr_stat = S3C64XX_BLKPWRSTAT_S,
+        .pd = {
+                .power_off = s3c64xx_pd_off,
+                .power_on = s3c64xx_pd_on,
+        },
+};
+static struct s3c64xx_pm_domain s3c64xx_pm_f = {
+        .name = "F",
+        .ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
+        .pwr_stat = S3C64XX_BLKPWRSTAT_F,
+        .pd = {
+                .power_off = s3c64xx_pd_off,
+                .power_on = s3c64xx_pd_on,
+        },
+};
+static struct s3c64xx_pm_domain s3c64xx_pm_p = {
+        .name = "P",
+        .ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
+        .pwr_stat = S3C64XX_BLKPWRSTAT_P,
+        .pd = {
+                .power_off = s3c64xx_pd_off,
+                .power_on = s3c64xx_pd_on,
+        },
+};
+static struct s3c64xx_pm_domain s3c64xx_pm_i = {
+        .name = "I",
+        .ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
+        .pwr_stat = S3C64XX_BLKPWRSTAT_I,
+        .pd = {
+                .power_off = s3c64xx_pd_off,
+                .power_on = s3c64xx_pd_on,
+        },
+};
+static struct s3c64xx_pm_domain s3c64xx_pm_g = {
+        .name = "G",
+        .ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
+        .pd = {
+                .power_off = s3c64xx_pd_off,
+                .power_on = s3c64xx_pd_on,
+        },
+};
+static struct s3c64xx_pm_domain s3c64xx_pm_v = {
+        .name = "V",
+        .ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
+        .pwr_stat = S3C64XX_BLKPWRSTAT_V,
+        .pd = {
+                .power_off = s3c64xx_pd_off,
+                .power_on = s3c64xx_pd_on,
+        },
+};
+static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
+        &s3c64xx_pm_irom,
+};
+static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
+        &s3c64xx_pm_etm,
+        &s3c64xx_pm_g,
+        &s3c64xx_pm_v,
+        &s3c64xx_pm_i,
+        &s3c64xx_pm_p,
+        &s3c64xx_pm_s,
+        &s3c64xx_pm_f,
+};
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
 void s3c_pm_debug_smdkled(u32 set, u32 clear)
 {
@@ -89,6 +233,8 @@ static struct sleep_save misc_save[] = {
        SAVE_ITEM(S3C64XX_SDMA_SEL),
        SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
+        SAVE_ITEM(S3C64XX_NORMAL_CFG),
 };
 void s3c_pm_configure_extint(void)
@@ -179,7 +325,26 @@ static void s3c64xx_pm_prepare(void)
        __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
 }
-static int s3c64xx_pm_init(void)
+int __init s3c64xx_pm_init(void)
+{
+        int i;
+        s3c_pm_init();
+        for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
+                pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
+                              &pm_domain_always_on_gov, false);
+        for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
+                pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
+        if (dev_get_platdata(&s3c_device_fb.dev))
+                pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
+        return 0;
+}
+static __init int s3c64xx_pm_initcall(void)
 {
        pm_cpu_prep = s3c64xx_pm_prepare;
        pm_cpu_sleep = s3c64xx_cpu_suspend;
@@ -198,5 +363,12 @@ static int s3c64xx_pm_init(void)
        return 0;
 }
+arch_initcall(s3c64xx_pm_initcall);
+static __init int s3c64xx_pm_late_initcall(void)
+{
+        pm_genpd_poweroff_unused();
-arch_initcall(s3c64xx_pm_init);
+        return 0;
+}
+late_initcall(s3c64xx_pm_late_initcall);
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 51c00f2453c..4869714c6f1 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -17,7 +17,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
@@ -38,7 +38,8 @@
 #include <plat/sdhci.h>
 #include <plat/iic-core.h>
 #include <plat/onenand-core.h>
-#include <plat/s3c6400.h>
+#include "common.h"
 void __init s3c6400_map_io(void)
 {
@@ -60,7 +61,7 @@ void __init s3c6400_map_io(void)
 void __init s3c6400_init_clocks(int xtal)
 {
        s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK);
-        s3c6400_setup_clocks();
+        s3c64xx_setup_clocks();
 }
 void __init s3c6400_init_irq(void)
@@ -70,17 +71,18 @@ void __init s3c6400_init_irq(void)
        s3c64xx_init_irq(~0 & ~(0xf << 5), ~0);
 }
-static struct sysdev_class s3c6400_sysclass = {
+static struct bus_type s3c6400_subsys = {
-        .name   = "s3c6400-core",
+        .name           = "s3c6400-core",
+        .dev_name       = "s3c6400-core",
 };
-static struct sys_device s3c6400_sysdev = {
+static struct device s3c6400_dev = {
-        .cls    = &s3c6400_sysclass,
+        .bus    = &s3c6400_subsys,
 };
 static int __init s3c6400_core_init(void)
 {
-        return sysdev_class_register(&s3c6400_sysclass);
+        return subsys_system_register(&s3c6400_subsys, NULL);
 }
 core_initcall(s3c6400_core_init);
@@ -89,5 +91,5 @@ int __init s3c6400_init(void)
 {
        printk("S3C6400: Initialising architecture\n");
-        return sysdev_register(&s3c6400_sysdev);
+        return device_register(&s3c6400_dev);
 }
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 4117003464a..31c29fdf180 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -18,7 +18,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
@@ -41,8 +41,8 @@
 #include <plat/adc-core.h>
 #include <plat/iic-core.h>
 #include <plat/onenand-core.h>
-#include <plat/s3c6400.h>
-#include <plat/s3c6410.h>
+#include "common.h"
 void __init s3c6410_map_io(void)
 {
@@ -66,7 +66,7 @@ void __init s3c6410_init_clocks(int xtal)
 {
        printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
        s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK);
-        s3c6400_setup_clocks();
+        s3c64xx_setup_clocks();
 }
 void __init s3c6410_init_irq(void)
@@ -75,17 +75,18 @@ void __init s3c6410_init_irq(void)
        s3c64xx_init_irq(~0 & ~(1 << 7), ~0);
 }
-struct sysdev_class s3c6410_sysclass = {
+struct bus_type s3c6410_subsys = {
-        .name   = "s3c6410-core",
+        .name           = "s3c6410-core",
+        .dev_name       = "s3c6410-core",
 };
-static struct sys_device s3c6410_sysdev = {
+static struct device s3c6410_dev = {
-        .cls    = &s3c6410_sysclass,
+        .bus    = &s3c6410_subsys,
 };
 static int __init s3c6410_core_init(void)
 {
-        return sysdev_class_register(&s3c6410_sysclass);
+        return subsys_system_register(&s3c6410_subsys, NULL);
 }
 core_initcall(s3c6410_core_init);
@@ -94,5 +95,5 @@ int __init s3c6410_init(void)
 {
        printk("S3C6410: Initialising architecture\n");
-        return sysdev_register(&s3c6410_sysdev);
+        return device_register(&s3c6410_dev);
 }
diff --git a/arch/arm/mach-s3c64xx/setup-sdhci.c b/arch/arm/mach-s3c64xx/setup-sdhci.c
deleted file mode 100644
index c75a71b2116..00000000000
--- a/arch/arm/mach-s3c64xx/setup-sdhci.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/setup-sdhci.c
- *
- * Copyright 2008 Simtec Electronics
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * S3C6400/S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/types.h>
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-char *s3c64xx_hsmmc_clksrcs[4] = {
-        [0] = "hsmmc",
-        [1] = "hsmmc",
-        [2] = "mmc_bus",
-        /* [3] = "48m", - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
new file mode 100644
index 00000000000..d9592ad7a82
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -0,0 +1,45 @@
+/* linux/arch/arm/mach-s3c64xx/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .tx_st_done     = 21,
+};
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .tx_st_done     = 21,
+};
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 18690c5f99e..c87f6108eeb 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -36,6 +36,16 @@ config S5P64X0_SETUP_I2C1
        help
          Common setup code for i2c bus 1.
+config S5P64X0_SETUP_SPI
+        bool
+        help
+          Common setup code for SPI GPIO configurations
+config S5P64X0_SETUP_SDHCI_GPIO
+        bool
+        help
+          Common setup code for SDHCI gpio.
 # machine support
 config MACH_SMDK6440
@@ -45,13 +55,16 @@ config MACH_SMDK6440
        select S3C_DEV_I2C1
        select S3C_DEV_RTC
        select S3C_DEV_WDT
-        select S3C64XX_DEV_SPI
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
        select SAMSUNG_DEV_ADC
        select SAMSUNG_DEV_BACKLIGHT
        select SAMSUNG_DEV_PWM
        select SAMSUNG_DEV_TS
        select S5P64X0_SETUP_FB_24BPP
        select S5P64X0_SETUP_I2C1
+        select S5P64X0_SETUP_SDHCI_GPIO
        help
          Machine support for the Samsung SMDK6440
@@ -62,14 +75,28 @@ config MACH_SMDK6450
        select S3C_DEV_I2C1
        select S3C_DEV_RTC
        select S3C_DEV_WDT
-        select S3C64XX_DEV_SPI
+        select S3C_DEV_HSMMC
+        select S3C_DEV_HSMMC1
+        select S3C_DEV_HSMMC2
        select SAMSUNG_DEV_ADC
        select SAMSUNG_DEV_BACKLIGHT
        select SAMSUNG_DEV_PWM
        select SAMSUNG_DEV_TS
        select S5P64X0_SETUP_FB_24BPP
        select S5P64X0_SETUP_I2C1
+        select S5P64X0_SETUP_SDHCI_GPIO
        help
          Machine support for the Samsung SMDK6450
+menu "Use 8-bit SDHCI bus width"
+config S5P64X0_SD_CH1_8BIT
+        bool "SDHCI Channel 1 (Slot 1)"
+        depends on MACH_SMDK6450 || MACH_SMDK6440
+        help
+          Support SDHCI Channel 1 8-bit bus.
+          If selected, Channel 2 is disabled.
+endmenu
 endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index a1324d8dc4e..12bb951187a 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -10,14 +10,16 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
-# Core support for S5P64X0 system
+# Core
-obj-$(CONFIG_ARCH_S5P64X0)      += cpu.o init.o clock.o dma.o
+obj-y                           += common.o clock.o
-obj-$(CONFIG_ARCH_S5P64X0)      += setup-i2c0.o irq-eint.o
 obj-$(CONFIG_CPU_S5P6440)       += clock-s5p6440.o
 obj-$(CONFIG_CPU_S5P6450)       += clock-s5p6450.o
 obj-$(CONFIG_PM)                += pm.o irq-pm.o
+obj-y                           += dma.o
 # machine support
 obj-$(CONFIG_MACH_SMDK6440)     += mach-smdk6440.o
@@ -26,7 +28,9 @@ obj-$(CONFIG_MACH_SMDK6450)	+= mach-smdk6450.o
 # device support
 obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
+obj-y                                   += setup-i2c0.o
 obj-$(CONFIG_S5P64X0_SETUP_I2C1)        += setup-i2c1.o
 obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP)    += setup-fb-24bpp.o
+obj-$(CONFIG_S5P64X0_SETUP_SPI)         += setup-spi.o
+obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index c54c65d511f..ee1e8e7f563 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -17,7 +17,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/clk.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -31,7 +31,8 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
-#include <plat/s5p6440.h>
+#include "common.h"
 static u32 epll_div[][5] = {
        { 36000000,     0,      48, 1, 4 },
@@ -268,18 +269,6 @@ static struct clk init_clocks_off[] = {
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 31),
        }, {
-                .name           = "sclk_spi_48",
-                .devname        = "s3c64xx-spi.0",
-                .parent         = &clk_48m,
-                .enable         = s5p64x0_sclk_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "sclk_spi_48",
-                .devname        = "s3c64xx-spi.1",
-                .parent         = &clk_48m,
-                .enable         = s5p64x0_sclk_ctrl,
-                .ctrlbit        = (1 << 23),
-        }, {
                .name           = "mmc_48m",
                .devname        = "s3c-sdhci.0",
                .parent         = &clk_48m,
@@ -391,65 +380,6 @@ static struct clksrc_sources clkset_audio = {
 static struct clksrc_clk clksrcs[] = {
        {
                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = (1 << 24),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = (1 << 25),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = (1 << 26),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "uclk1",
-                        .ctrlbit        = (1 << 5),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.0",
-                        .ctrlbit        = (1 << 20),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.1",
-                        .ctrlbit        = (1 << 21),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group1,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
                        .name           = "sclk_post",
                        .ctrlbit        = (1 << 10),
                        .enable         = s5p64x0_sclk_ctrl,
@@ -487,6 +417,77 @@ static struct clksrc_clk clksrcs[] = {
        },
 };
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 24),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 25),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = (1 << 26),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_uclk = {
+        .clk    = {
+                .name           = "uclk1",
+                .ctrlbit        = (1 << 5),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .ctrlbit        = (1 << 20),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .ctrlbit        = (1 << 21),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group1,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+};
 /* Clock initialization code */
 static struct clksrc_clk *sysclks[] = {
        &clk_mout_apll,
@@ -505,6 +506,26 @@ static struct clk dummy_apb_pclk = {
        .id             = -1,
 };
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uclk,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2
+};
+static struct clk_lookup s5p6440_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+};
 void __init_or_cpufreq s5p6440_setup_clocks(void)
 {
        struct clk *xtal_clk;
@@ -583,9 +604,12 @@ void __init s5p6440_register_clocks(void)
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
        s3c24xx_register_clock(&dummy_apb_pclk);
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 2d04abfba12..dae6a13f43b 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -17,7 +17,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/clk.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -31,7 +31,8 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
-#include <plat/s5p6450.h>
+#include "common.h"
 static struct clksrc_clk clk_mout_dpll = {
        .clk    = {
@@ -413,65 +414,6 @@ static struct clksrc_clk clk_sclk_audio0 = {
 static struct clksrc_clk clksrcs[] = {
        {
                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = (1 << 24),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = (1 << 25),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = (1 << 26),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "uclk1",
-                        .ctrlbit        = (1 << 5),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.0",
-                        .ctrlbit        = (1 << 20),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.1",
-                        .ctrlbit        = (1 << 21),
-                        .enable         = s5p64x0_sclk_ctrl,
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
-                .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
                        .name           = "sclk_fimc",
                        .ctrlbit        = (1 << 10),
                        .enable         = s5p64x0_sclk_ctrl,
@@ -536,6 +478,97 @@ static struct clksrc_clk clksrcs[] = {
        },
 };
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 24),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 25),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = (1 << 26),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_uclk = {
+        .clk    = {
+                .name           = "uclk1",
+                .ctrlbit        = (1 << 5),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .ctrlbit        = (1 << 20),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .ctrlbit        = (1 << 21),
+                .enable         = s5p64x0_sclk_ctrl,
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
+        .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
+};
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uclk,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+};
+static struct clk_lookup s5p6450_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+};
 /* Clock initialization code */
 static struct clksrc_clk *sysclks[] = {
        &clk_mout_apll,
@@ -634,9 +667,12 @@ void __init s5p6450_register_clocks(void)
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
        s3c24xx_register_clock(&dummy_apb_pclk);
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
index b52c6e2f37a..241d0e645c8 100644
--- a/arch/arm/mach-s5p64x0/clock.c
+++ b/arch/arm/mach-s5p64x0/clock.c
@@ -17,7 +17,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/clk.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -30,8 +30,8 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
-#include <plat/s5p6440.h>
-#include <plat/s5p6450.h>
+#include "common.h"
 struct clksrc_clk clk_mout_apll = {
        .clk    = {
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
new file mode 100644
index 00000000000..52b89a37644
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Common Codes for S5P64X0 machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <asm/irq.h>
+#include <asm/proc-fns.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/map.h>
+#include <mach/hardware.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-gpio.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/pm.h>
+#include <plat/sdhci.h>
+#include <plat/adc-core.h>
+#include <plat/fb-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/regs-irqtype.h>
+#include <plat/regs-serial.h>
+#include <plat/watchdog-reset.h>
+#include "common.h"
+static const char name_s5p6440[] = "S5P6440";
+static const char name_s5p6450[] = "S5P6450";
+static struct cpu_table cpu_ids[] __initdata = {
+        {
+                .idcode         = S5P6440_CPU_ID,
+                .idmask         = S5P64XX_CPU_MASK,
+                .map_io         = s5p6440_map_io,
+                .init_clocks    = s5p6440_init_clocks,
+                .init_uarts     = s5p6440_init_uarts,
+                .init           = s5p64x0_init,
+                .name           = name_s5p6440,
+        }, {
+                .idcode         = S5P6450_CPU_ID,
+                .idmask         = S5P64XX_CPU_MASK,
+                .map_io         = s5p6450_map_io,
+                .init_clocks    = s5p6450_init_clocks,
+                .init_uarts     = s5p6450_init_uarts,
+                .init           = s5p64x0_init,
+                .name           = name_s5p6450,
+        },
+};
+/* Initial IO mappings */
+static struct map_desc s5p64x0_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_CHIPID,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_CHIPID),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_SYS,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_SYSCON),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_TIMER,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_TIMER),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_WDT),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SROMC,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_SROMC),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        },
+};
+static struct map_desc s5p6440_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+static struct map_desc s5p6450_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
+                .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        },
+};
+static void s5p64x0_idle(void)
+{
+        unsigned long val;
+        if (!need_resched()) {
+                val = __raw_readl(S5P64X0_PWR_CFG);
+                val &= ~(0x3 << 5);
+                val |= (0x1 << 5);
+                __raw_writel(val, S5P64X0_PWR_CFG);
+                cpu_do_idle();
+        }
+        local_irq_enable();
+}
+/*
+ * s5p64x0_map_io
+ *
+ * register the standard CPU IO areas
+ */
+void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
+{
+        /* initialize the io descriptors we need for initialization */
+        iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
+        if (mach_desc)
+                iotable_init(mach_desc, size);
+        /* detect cpu id and rev. */
+        s5p_init_cpu(S5P64X0_SYS_ID);
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+}
+void __init s5p6440_map_io(void)
+{
+        /* initialize any device information early */
+        s3c_adc_setname("s3c64xx-adc");
+        s3c_fb_setname("s5p64x0-fb");
+        s5p64x0_default_sdhci0();
+        s5p64x0_default_sdhci1();
+        s5p6440_default_sdhci2();
+        iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
+        init_consistent_dma_size(SZ_8M);
+}
+void __init s5p6450_map_io(void)
+{
+        /* initialize any device information early */
+        s3c_adc_setname("s3c64xx-adc");
+        s3c_fb_setname("s5p64x0-fb");
+        s5p64x0_default_sdhci0();
+        s5p64x0_default_sdhci1();
+        s5p6450_default_sdhci2();
+        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
+        init_consistent_dma_size(SZ_8M);
+}
+/*
+ * s5p64x0_init_clocks
+ *
+ * register and setup the CPU clocks
+ */
+void __init s5p6440_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        s5p6440_register_clocks();
+        s5p6440_setup_clocks();
+}
+void __init s5p6450_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        s5p6450_register_clocks();
+        s5p6450_setup_clocks();
+}
+/*
+ * s5p64x0_init_irq
+ *
+ * register the CPU interrupts
+ */
+void __init s5p6440_init_irq(void)
+{
+        /* S5P6440 supports 2 VIC */
+        u32 vic[2];
+        /*
+         * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
+         * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
+         */
+        vic[0] = 0xff800ae7;
+        vic[1] = 0xffbf23e5;
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
+}
+void __init s5p6450_init_irq(void)
+{
+        /* S5P6450 supports only 2 VIC */
+        u32 vic[2];
+        /*
+         * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
+         * VIC1 is missing IRQ VIC1[12, 14, 23]
+         */
+        vic[0] = 0xff9f1fff;
+        vic[1] = 0xff7fafff;
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
+}
+struct bus_type s5p64x0_subsys = {
+        .name           = "s5p64x0-core",
+        .dev_name       = "s5p64x0-core",
+};
+static struct device s5p64x0_dev = {
+        .bus    = &s5p64x0_subsys,
+};
+static int __init s5p64x0_core_init(void)
+{
+        return subsys_system_register(&s5p64x0_subsys, NULL);
+}
+core_initcall(s5p64x0_core_init);
+int __init s5p64x0_init(void)
+{
+        printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
+        /* set idle function */
+        pm_idle = s5p64x0_idle;
+        return device_register(&s5p64x0_dev);
+}
+/* uart registration process */
+void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        int uart;
+        for (uart = 0; uart < no; uart++) {
+                s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
+                s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
+        }
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+}
+void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+}
+#define eint_offset(irq)        ((irq) - IRQ_EINT(0))
+static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
+{
+        int offs = eint_offset(data->irq);
+        int shift;
+        u32 ctrl, mask;
+        u32 newvalue = 0;
+        if (offs > 15)
+                return -EINVAL;
+        switch (type) {
+        case IRQ_TYPE_NONE:
+                printk(KERN_WARNING "No edge setting!\n");
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                newvalue = S3C2410_EXTINT_RISEEDGE;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                newvalue = S3C2410_EXTINT_FALLEDGE;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                newvalue = S3C2410_EXTINT_BOTHEDGE;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                newvalue = S3C2410_EXTINT_LOWLEV;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                newvalue = S3C2410_EXTINT_HILEV;
+                break;
+        default:
+                printk(KERN_ERR "No such irq type %d", type);
+                return -EINVAL;
+        }
+        shift = (offs / 2) * 4;
+        mask = 0x7 << shift;
+        ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
+        ctrl |= newvalue << shift;
+        __raw_writel(ctrl, S5P64X0_EINT0CON0);
+        /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
+        else
+                s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
+        return 0;
+}
+/*
+ * s5p64x0_irq_demux_eint
+ *
+ * This function demuxes the IRQ from the group0 external interrupts,
+ * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
+ * the specific handlers s5p64x0_irq_demux_eintX_Y.
+ */
+static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
+{
+        u32 status = __raw_readl(S5P64X0_EINT0PEND);
+        u32 mask = __raw_readl(S5P64X0_EINT0MASK);
+        unsigned int irq;
+        status &= ~mask;
+        status >>= start;
+        status &= (1 << (end - start + 1)) - 1;
+        for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
+                if (status & 1)
+                        generic_handle_irq(irq);
+                status >>= 1;
+        }
+}
+static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
+{
+        s5p64x0_irq_demux_eint(0, 3);
+}
+static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
+{
+        s5p64x0_irq_demux_eint(4, 11);
+}
+static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
+                                        struct irq_desc *desc)
+{
+        s5p64x0_irq_demux_eint(12, 15);
+}
+static int s5p64x0_alloc_gc(void)
+{
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
+                                    S5P_VA_GPIO, handle_level_irq);
+        if (!gc) {
+                printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
+                        "external interrupts failed\n", __func__);
+                return -EINVAL;
+        }
+        ct = gc->chip_types;
+        ct->chip.irq_ack = irq_gc_ack_set_bit;
+        ct->chip.irq_mask = irq_gc_mask_set_bit;
+        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+        ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
+        ct->chip.irq_set_wake = s3c_irqext_wake;
+        ct->regs.ack = EINT0PEND_OFFSET;
+        ct->regs.mask = EINT0MASK_OFFSET;
+        irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+        return 0;
+}
+static int __init s5p64x0_init_irq_eint(void)
+{
+        int ret = s5p64x0_alloc_gc();
+        irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
+        irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
+        irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
+        return ret;
+}
+arch_initcall(s5p64x0_init_irq_eint);
+void s5p64x0_restart(char mode, const char *cmd)
+{
+        if (mode != 's')
+                arch_wdt_reset();
+        soft_restart(0);
+}
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
new file mode 100644
index 00000000000..f8a60fdc588
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/common.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Common Header for S5P64X0 machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
+#define __ARCH_ARM_MACH_S5P64X0_COMMON_H
+void s5p6440_init_irq(void);
+void s5p6450_init_irq(void);
+void s5p64x0_init_io(struct map_desc *mach_desc, int size);
+void s5p6440_register_clocks(void);
+void s5p6440_setup_clocks(void);
+void s5p6450_register_clocks(void);
+void s5p6450_setup_clocks(void);
+void s5p64x0_restart(char mode, const char *cmd);
+#ifdef CONFIG_CPU_S5P6440
+extern  int s5p64x0_init(void);
+extern void s5p6440_map_io(void);
+extern void s5p6440_init_clocks(int xtal);
+extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#else
+#define s5p6440_init_clocks NULL
+#define s5p6440_init_uarts NULL
+#define s5p6440_map_io NULL
+#define s5p64x0_init NULL
+#endif
+#ifdef CONFIG_CPU_S5P6450
+extern  int s5p64x0_init(void);
+extern void s5p6450_map_io(void);
+extern void s5p6450_init_clocks(int xtal);
+extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#else
+#define s5p6450_init_clocks NULL
+#define s5p6450_init_uarts NULL
+#define s5p6450_map_io NULL
+#define s5p64x0_init NULL
+#endif
+#endif /* __ARCH_ARM_MACH_S5P64X0_COMMON_H */
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
deleted file mode 100644
index ecab40cf19a..00000000000
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/cpu.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/sysdev.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/dma-mapping.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/proc-fns.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <plat/regs-serial.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/s5p6440.h>
-#include <plat/s5p6450.h>
-#include <plat/adc-core.h>
-#include <plat/fb-core.h>
-/* Initial IO mappings */
-static struct map_desc s5p64x0_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_GPIO,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC0,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC1,
-                .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        },
-};
-static struct map_desc s5p6440_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-static struct map_desc s5p6450_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
-                .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-static void s5p64x0_idle(void)
-{
-        unsigned long val;
-        if (!need_resched()) {
-                val = __raw_readl(S5P64X0_PWR_CFG);
-                val &= ~(0x3 << 5);
-                val |= (0x1 << 5);
-                __raw_writel(val, S5P64X0_PWR_CFG);
-                cpu_do_idle();
-        }
-        local_irq_enable();
-}
-/*
- * s5p64x0_map_io
- *
- * register the standard CPU IO areas
- */
-void __init s5p6440_map_io(void)
-{
-        /* initialize any device information early */
-        s3c_adc_setname("s3c64xx-adc");
-        s3c_fb_setname("s5p64x0-fb");
-        iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
-        iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
-        init_consistent_dma_size(SZ_8M);
-}
-void __init s5p6450_map_io(void)
-{
-        /* initialize any device information early */
-        s3c_adc_setname("s3c64xx-adc");
-        s3c_fb_setname("s5p64x0-fb");
-        iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
-        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
-        init_consistent_dma_size(SZ_8M);
-}
-/*
- * s5p64x0_init_clocks
- *
- * register and setup the CPU clocks
- */
-void __init s5p6440_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5p6440_register_clocks();
-        s5p6440_setup_clocks();
-}
-void __init s5p6450_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5p6450_register_clocks();
-        s5p6450_setup_clocks();
-}
-/*
- * s5p64x0_init_irq
- *
- * register the CPU interrupts
- */
-void __init s5p6440_init_irq(void)
-{
-        /* S5P6440 supports 2 VIC */
-        u32 vic[2];
-        /*
-         * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
-         * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
-         */
-        vic[0] = 0xff800ae7;
-        vic[1] = 0xffbf23e5;
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-void __init s5p6450_init_irq(void)
-{
-        /* S5P6450 supports only 2 VIC */
-        u32 vic[2];
-        /*
-         * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
-         * VIC1 is missing IRQ VIC1[12, 14, 23]
-         */
-        vic[0] = 0xff9f1fff;
-        vic[1] = 0xff7fafff;
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-struct sysdev_class s5p64x0_sysclass = {
-        .name   = "s5p64x0-core",
-};
-static struct sys_device s5p64x0_sysdev = {
-        .cls    = &s5p64x0_sysclass,
-};
-static int __init s5p64x0_core_init(void)
-{
-        return sysdev_class_register(&s5p64x0_sysclass);
-}
-core_initcall(s5p64x0_core_init);
-int __init s5p64x0_init(void)
-{
-        printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
-        /* set idle function */
-        pm_idle = s5p64x0_idle;
-        return sysdev_register(&s5p64x0_sysdev);
-}
diff --git a/arch/arm/mach-s5p64x0/dev-spi.c b/arch/arm/mach-s5p64x0/dev-spi.c
deleted file mode 100644
index 1fd9c79c7db..00000000000
--- a/arch/arm/mach-s5p64x0/dev-spi.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/dev-spi.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/regs-clock.h>
-#include <mach/spi-clocks.h>
-#include <plat/cpu.h>
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-static char *s5p64x0_spi_src_clks[] = {
-        [S5P64X0_SPI_SRCCLK_PCLK] = "pclk",
-        [S5P64X0_SPI_SRCCLK_SCLK] = "sclk_spi",
-};
-/* SPI Controller platform_devices */
-/* Since we emulate multi-cs capability, we do not touch the CS.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s5p6440_spi_cfg_gpio(struct platform_device *pdev)
-{
-        unsigned int base;
-        switch (pdev->id) {
-        case 0:
-                base = S5P6440_GPC(0);
-                break;
-        case 1:
-                base = S5P6440_GPC(4);
-                break;
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-        s3c_gpio_cfgall_range(base, 3,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-static int s5p6450_spi_cfg_gpio(struct platform_device *pdev)
-{
-        unsigned int base;
-        switch (pdev->id) {
-        case 0:
-                base = S5P6450_GPC(0);
-                break;
-        case 1:
-                base = S5P6450_GPC(4);
-                break;
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-        s3c_gpio_cfgall_range(base, 3,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-static struct resource s5p64x0_spi0_resource[] = {
-        [0] = {
-                .start  = S5P64X0_PA_SPI0,
-                .end    = S5P64X0_PA_SPI0 + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_SPI0_TX,
-                .end    = DMACH_SPI0_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_SPI0_RX,
-                .end    = DMACH_SPI0_RX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start  = IRQ_SPI0,
-                .end    = IRQ_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct s3c64xx_spi_info s5p6440_spi0_pdata = {
-        .cfg_gpio       = s5p6440_spi_cfg_gpio,
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-static struct s3c64xx_spi_info s5p6450_spi0_pdata = {
-        .cfg_gpio       = s5p6450_spi_cfg_gpio,
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-struct platform_device s5p64x0_device_spi0 = {
-        .name           = "s3c64xx-spi",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(s5p64x0_spi0_resource),
-        .resource       = s5p64x0_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-static struct resource s5p64x0_spi1_resource[] = {
-        [0] = {
-                .start  = S5P64X0_PA_SPI1,
-                .end    = S5P64X0_PA_SPI1 + 0x100 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = DMACH_SPI1_TX,
-                .end    = DMACH_SPI1_TX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start  = DMACH_SPI1_RX,
-                .end    = DMACH_SPI1_RX,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start  = IRQ_SPI1,
-                .end    = IRQ_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct s3c64xx_spi_info s5p6440_spi1_pdata = {
-        .cfg_gpio       = s5p6440_spi_cfg_gpio,
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-static struct s3c64xx_spi_info s5p6450_spi1_pdata = {
-        .cfg_gpio       = s5p6450_spi_cfg_gpio,
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-struct platform_device s5p64x0_device_spi1 = {
-        .name           = "s3c64xx-spi",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(s5p64x0_spi1_resource),
-        .resource       = s5p64x0_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-};
-void __init s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S5P64X0_SPI_SRCCLK_SCLK) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-        switch (cntrlr) {
-        case 0:
-                if (soc_is_s5p6450())
-                        pd = &s5p6450_spi0_pdata;
-                else
-                        pd = &s5p6440_spi0_pdata;
-                s5p64x0_device_spi0.dev.platform_data = pd;
-                break;
-        case 1:
-                if (soc_is_s5p6450())
-                        pd = &s5p6450_spi1_pdata;
-                else
-                        pd = &s5p6440_spi1_pdata;
-                s5p64x0_device_spi1.dev.platform_data = pd;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = s5p64x0_spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 442dd4ad12d..f820c074440 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -38,176 +38,74 @@
 static u64 dma_dmamask = DMA_BIT_MASK(32);
-struct dma_pl330_peri s5p6440_pdma_peri[22] = {
+u8 s5p6440_pdma_peri[] = {
-        {
+        DMACH_UART0_RX,
-                .peri_id = (u8)DMACH_UART0_RX,
+        DMACH_UART0_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_UART1_RX,
-        }, {
+        DMACH_UART1_TX,
-                .peri_id = (u8)DMACH_UART0_TX,
+        DMACH_UART2_RX,
-                .rqtype = MEMTODEV,
+        DMACH_UART2_TX,
-        }, {
+        DMACH_UART3_RX,
-                .peri_id = (u8)DMACH_UART1_RX,
+        DMACH_UART3_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_MAX,
-        }, {
+        DMACH_MAX,
-                .peri_id = (u8)DMACH_UART1_TX,
+        DMACH_PCM0_TX,
-                .rqtype = MEMTODEV,
+        DMACH_PCM0_RX,
-        }, {
+        DMACH_I2S0_TX,
-                .peri_id = (u8)DMACH_UART2_RX,
+        DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
+        DMACH_SPI0_TX,
-        }, {
+        DMACH_SPI0_RX,
-                .peri_id = (u8)DMACH_UART2_TX,
+        DMACH_MAX,
-                .rqtype = MEMTODEV,
+        DMACH_MAX,
-        }, {
+        DMACH_MAX,
-                .peri_id = (u8)DMACH_UART3_RX,
+        DMACH_MAX,
-                .rqtype = DEVTOMEM,
+        DMACH_SPI1_TX,
-        }, {
+        DMACH_SPI1_RX,
-                .peri_id = (u8)DMACH_UART3_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = DMACH_MAX,
-        }, {
-                .peri_id = DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        },
 };
 struct dma_pl330_platdata s5p6440_pdma_pdata = {
        .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
-        .peri = s5p6440_pdma_peri,
+        .peri_id = s5p6440_pdma_peri,
 };
-struct dma_pl330_peri s5p6450_pdma_peri[32] = {
+u8 s5p6450_pdma_peri[] = {
-        {
+        DMACH_UART0_RX,
-                .peri_id = (u8)DMACH_UART0_RX,
+        DMACH_UART0_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_UART1_RX,
-        }, {
+        DMACH_UART1_TX,
-                .peri_id = (u8)DMACH_UART0_TX,
+        DMACH_UART2_RX,
-                .rqtype = MEMTODEV,
+        DMACH_UART2_TX,
-        }, {
+        DMACH_UART3_RX,
-                .peri_id = (u8)DMACH_UART1_RX,
+        DMACH_UART3_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_UART4_RX,
-        }, {
+        DMACH_UART4_TX,
-                .peri_id = (u8)DMACH_UART1_TX,
+        DMACH_PCM0_TX,
-                .rqtype = MEMTODEV,
+        DMACH_PCM0_RX,
-        }, {
+        DMACH_I2S0_TX,
-                .peri_id = (u8)DMACH_UART2_RX,
+        DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
+        DMACH_SPI0_TX,
-        }, {
+        DMACH_SPI0_RX,
-                .peri_id = (u8)DMACH_UART2_TX,
+        DMACH_PCM1_TX,
-                .rqtype = MEMTODEV,
+        DMACH_PCM1_RX,
-        }, {
+        DMACH_PCM2_TX,
-                .peri_id = (u8)DMACH_UART3_RX,
+        DMACH_PCM2_RX,
-                .rqtype = DEVTOMEM,
+        DMACH_SPI1_TX,
-        }, {
+        DMACH_SPI1_RX,
-                .peri_id = (u8)DMACH_UART3_TX,
+        DMACH_USI_TX,
-                .rqtype = MEMTODEV,
+        DMACH_USI_RX,
-        }, {
+        DMACH_MAX,
-                .peri_id = (u8)DMACH_UART4_RX,
+        DMACH_I2S1_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_I2S1_RX,
-        }, {
+        DMACH_I2S2_TX,
-                .peri_id = (u8)DMACH_UART4_TX,
+        DMACH_I2S2_RX,
-                .rqtype = MEMTODEV,
+        DMACH_PWM,
-        }, {
+        DMACH_UART5_RX,
-                .peri_id = (u8)DMACH_PCM0_TX,
+        DMACH_UART5_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_USI_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_USI_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PWM,
-        }, {
-                .peri_id = (u8)DMACH_UART5_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_UART5_TX,
-                .rqtype = MEMTODEV,
-        },
 };
 struct dma_pl330_platdata s5p6450_pdma_pdata = {
        .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
-        .peri = s5p6450_pdma_peri,
+        .peri_id = s5p6450_pdma_peri,
 };
 struct amba_device s5p64x0_device_pdma = {
@@ -227,10 +125,15 @@ struct amba_device s5p64x0_device_pdma = {
 static int __init s5p64x0_dma_init(void)
 {
-        if (soc_is_s5p6450())
+        if (soc_is_s5p6450()) {
+                dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
+                dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
                s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
-        else
+        } else {
+                dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
+                dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
                s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
+        }
        amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
diff --git a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
index 10b62b4f821..fbb246d0a3d 100644
--- a/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5p64x0/include/mach/entry-macro.S
@@ -10,7 +10,8 @@
 * published by the Free Software Foundation.
 */
-#include <mach/map.h>
+                .macro  disable_fiq
-#include <plat/irqs.h>
+                .endm
-#include <asm/entry-macro-vic2.S>
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 53982db9d25..5b845e849b3 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -141,6 +141,8 @@
 #define IRQ_EINT_GROUP(grp, x)  (IRQ_EINT_GROUP##grp##_BASE + (x))
+#define IRQ_TIMER_BASE          (11)
 /* Set the default NR_IRQS */
 #define NR_IRQS                 (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 4d3ac8a3709..0c0175dbfa3 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -67,6 +67,8 @@
 #define S3C_PA_RTC              S5P64X0_PA_RTC
 #define S3C_PA_WDT              S5P64X0_PA_WDT
 #define S3C_PA_FB               S5P64X0_PA_FB
+#define S3C_PA_SPI0             S5P64X0_PA_SPI0
+#define S3C_PA_SPI1             S5P64X0_PA_SPI1
 #define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
 #define S5P_PA_SROMC            S5P64X0_PA_SROMC
diff --git a/arch/arm/mach-s5p64x0/include/mach/system.h b/arch/arm/mach-s5p64x0/include/mach/system.h
index 60f57532c97..cf26e0954a2 100644
--- a/arch/arm/mach-s5p64x0/include/mach/system.h
+++ b/arch/arm/mach-s5p64x0/include/mach/system.h
@@ -13,8 +13,6 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
-#include <plat/system-reset.h>
 static void arch_idle(void)
 {
        /* nothing here yet */
diff --git a/arch/arm/mach-s5p64x0/include/mach/vmalloc.h b/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
deleted file mode 100644
index 38dcc71a03c..00000000000
--- a/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/vmalloc.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C6400 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p64x0/init.c b/arch/arm/mach-s5p64x0/init.c
deleted file mode 100644
index 79833caf816..00000000000
--- a/arch/arm/mach-s5p64x0/init.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/init.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * S5P64X0 - Init support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <mach/map.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/s5p6440.h>
-#include <plat/s5p6450.h>
-#include <plat/regs-serial.h>
-static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
-        [0] = {
-                .name           = "pclk_low",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-        [1] = {
-                .name           = "uclk1",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-};
-/* uart registration process */
-void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-                if (!tcfg->clocks) {
-                        tcfg->clocks = s5p64x0_serial_clocks;
-                        tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
-                }
-        }
-}
-void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        int uart;
-        for (uart = 0; uart < no; uart++) {
-                s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
-                s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
-        }
-        s5p64x0_common_init_uarts(cfg, no);
-        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
-}
-void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        s5p64x0_common_init_uarts(cfg, no);
-        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
-}
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
deleted file mode 100644
index 275dc74f4a7..00000000000
--- a/arch/arm/mach-s5p64x0/irq-eint.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* arch/arm/mach-s5p64x0/irq-eint.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd
- *              http://www.samsung.com/
- *
- * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c
- *
- * S5P64X0 - Interrupt handling for External Interrupts.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <plat/cpu.h>
-#include <plat/regs-irqtype.h>
-#include <plat/gpio-cfg.h>
-#include <plat/pm.h>
-#include <mach/regs-gpio.h>
-#include <mach/regs-clock.h>
-#define eint_offset(irq)        ((irq) - IRQ_EINT(0))
-static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
-{
-        int offs = eint_offset(data->irq);
-        int shift;
-        u32 ctrl, mask;
-        u32 newvalue = 0;
-        if (offs > 15)
-                return -EINVAL;
-        switch (type) {
-        case IRQ_TYPE_NONE:
-                printk(KERN_WARNING "No edge setting!\n");
-                break;
-        case IRQ_TYPE_EDGE_RISING:
-                newvalue = S3C2410_EXTINT_RISEEDGE;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                newvalue = S3C2410_EXTINT_FALLEDGE;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                newvalue = S3C2410_EXTINT_BOTHEDGE;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                newvalue = S3C2410_EXTINT_LOWLEV;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                newvalue = S3C2410_EXTINT_HILEV;
-                break;
-        default:
-                printk(KERN_ERR "No such irq type %d", type);
-                return -EINVAL;
-        }
-        shift = (offs / 2) * 4;
-        mask = 0x7 << shift;
-        ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
-        ctrl |= newvalue << shift;
-        __raw_writel(ctrl, S5P64X0_EINT0CON0);
-        /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
-        if (soc_is_s5p6450())
-                s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
-        else
-                s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
-        return 0;
-}
-/*
- * s5p64x0_irq_demux_eint
- *
- * This function demuxes the IRQ from the group0 external interrupts,
- * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
- * the specific handlers s5p64x0_irq_demux_eintX_Y.
- */
-static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
-{
-        u32 status = __raw_readl(S5P64X0_EINT0PEND);
-        u32 mask = __raw_readl(S5P64X0_EINT0MASK);
-        unsigned int irq;
-        status &= ~mask;
-        status >>= start;
-        status &= (1 << (end - start + 1)) - 1;
-        for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
-                if (status & 1)
-                        generic_handle_irq(irq);
-                status >>= 1;
-        }
-}
-static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
-{
-        s5p64x0_irq_demux_eint(0, 3);
-}
-static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
-{
-        s5p64x0_irq_demux_eint(4, 11);
-}
-static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
-                                        struct irq_desc *desc)
-{
-        s5p64x0_irq_demux_eint(12, 15);
-}
-static int s5p64x0_alloc_gc(void)
-{
-        struct irq_chip_generic *gc;
-        struct irq_chip_type *ct;
-        gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
-                                    S5P_VA_GPIO, handle_level_irq);
-        if (!gc) {
-                printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
-                        "external interrupts failed\n", __func__);
-                return -EINVAL;
-        }
-        ct = gc->chip_types;
-        ct->chip.irq_ack = irq_gc_ack_set_bit;
-        ct->chip.irq_mask = irq_gc_mask_set_bit;
-        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
-        ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
-        ct->chip.irq_set_wake = s3c_irqext_wake;
-        ct->regs.ack = EINT0PEND_OFFSET;
-        ct->regs.mask = EINT0MASK_OFFSET;
-        irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
-                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
-        return 0;
-}
-static int __init s5p64x0_init_irq_eint(void)
-{
-        int ret = s5p64x0_alloc_gc();
-        irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
-        irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
-        irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
-        return ret;
-}
-arch_initcall(s5p64x0_init_irq_eint);
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 4a1250cd135..a40e325d62c 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -24,9 +24,11 @@
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
 #include <linux/fb.h>
+#include <linux/mmc/host.h>
 #include <video/platform_lcd.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/irq.h>
@@ -40,7 +42,6 @@
 #include <plat/regs-serial.h>
 #include <plat/gpio-cfg.h>
-#include <plat/s5p6440.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -52,6 +53,9 @@
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/regs-fb.h>
+#include <plat/sdhci.h>
+#include "common.h"
 #define SMDK6440_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                S3C2410_UCON_RXILEVEL |         \
@@ -161,6 +165,25 @@ static struct platform_device *smdk6440_devices[] __initdata = {
        &s5p6440_device_iis,
        &s3c_device_fb,
        &smdk6440_lcd_lte480wv,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
+};
+static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+};
+static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_INTERNAL,
+#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
+        .max_width      = 8,
+        .host_caps      = MMC_CAP_8_BIT_DATA,
+#endif
+};
+static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
 };
 static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -201,7 +224,7 @@ static struct platform_pwm_backlight_data smdk6440_bl_data = {
 static void __init smdk6440_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
+        s5p64x0_init_io(NULL, 0);
        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
@@ -234,6 +257,10 @@ static void __init smdk6440_machine_init(void)
        s5p6440_set_lcd_interface();
        s3c_fb_set_platdata(&smdk6440_lcd_pdata);
+        s3c_sdhci0_set_platdata(&smdk6440_hsmmc0_pdata);
+        s3c_sdhci1_set_platdata(&smdk6440_hsmmc1_pdata);
+        s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
        platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
 }
@@ -242,7 +269,9 @@ MACHINE_START(SMDK6440, "SMDK6440")
        .atag_offset    = 0x100,
        .init_irq       = s5p6440_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6440_map_io,
        .init_machine   = smdk6440_machine_init,
        .timer          = &s5p_timer,
+        .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 0ab129ecf00..efb69e2f2af 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -24,9 +24,11 @@
 #include <linux/gpio.h>
 #include <linux/pwm_backlight.h>
 #include <linux/fb.h>
+#include <linux/mmc/host.h>
 #include <video/platform_lcd.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/irq.h>
@@ -40,7 +42,6 @@
 #include <plat/regs-serial.h>
 #include <plat/gpio-cfg.h>
-#include <plat/s5p6450.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
@@ -52,6 +53,9 @@
 #include <plat/backlight.h>
 #include <plat/fb.h>
 #include <plat/regs-fb.h>
+#include <plat/sdhci.h>
+#include "common.h"
 #define SMDK6450_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                S3C2410_UCON_RXILEVEL |         \
@@ -179,10 +183,28 @@ static struct platform_device *smdk6450_devices[] __initdata = {
        &s5p6450_device_iis0,
        &s3c_device_fb,
        &smdk6450_lcd_lte480wv,
+        &s3c_device_hsmmc0,
+        &s3c_device_hsmmc1,
+        &s3c_device_hsmmc2,
        /* s5p6450_device_spi0 will be added */
 };
+static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+};
+static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
+        .max_width      = 8,
+        .host_caps      = MMC_CAP_8_BIT_DATA,
+#endif
+};
+static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = {
+        .cd_type        = S3C_SDHCI_CD_NONE,
+};
 static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
        .flags          = 0,
        .slave_addr     = 0x10,
@@ -221,7 +243,7 @@ static struct platform_pwm_backlight_data smdk6450_bl_data = {
 static void __init smdk6450_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
+        s5p64x0_init_io(NULL, 0);
        s3c24xx_init_clocks(19200000);
        s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
@@ -254,6 +276,10 @@ static void __init smdk6450_machine_init(void)
        s5p6450_set_lcd_interface();
        s3c_fb_set_platdata(&smdk6450_lcd_pdata);
+        s3c_sdhci0_set_platdata(&smdk6450_hsmmc0_pdata);
+        s3c_sdhci1_set_platdata(&smdk6450_hsmmc1_pdata);
+        s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
        platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
 }
@@ -262,7 +288,9 @@ MACHINE_START(SMDK6450, "SMDK6450")
        .atag_offset    = 0x100,
        .init_irq       = s5p6450_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdk6450_map_io,
        .init_machine   = smdk6450_machine_init,
        .timer          = &s5p_timer,
+        .restart        = s5p64x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 69927243d25..23f9b22439c 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -160,7 +160,7 @@ static void s5p64x0_pm_prepare(void)
 }
-static int s5p64x0_pm_add(struct sys_device *sysdev)
+static int s5p64x0_pm_add(struct device *dev)
 {
        pm_cpu_prep = s5p64x0_pm_prepare;
        pm_cpu_sleep = s5p64x0_cpu_suspend;
@@ -169,15 +169,17 @@ static int s5p64x0_pm_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s5p64x0_pm_driver = {
+static struct subsys_interface s5p64x0_pm_interface = {
-        .add            = s5p64x0_pm_add,
+        .name           = "s5p64x0_pm",
+        .subsys         = &s5p64x0_subsys,
+        .add_dev        = s5p64x0_pm_add,
 };
 static __init int s5p64x0_pm_drvinit(void)
 {
        s3c_pm_init();
-        return sysdev_driver_register(&s5p64x0_sysclass, &s5p64x0_pm_driver);
+        return subsys_interface_register(&s5p64x0_pm_interface);
 }
 arch_initcall(s5p64x0_pm_drvinit);
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
new file mode 100644
index 00000000000..8410af0d12b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
@@ -0,0 +1,104 @@
+/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/sdhci.h>
+#include <plat/cpu.h>
+void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+        /* Set all the necessary GPG pins to special-function 2 */
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width,
+                                         S3C_GPIO_SFN(2));
+        else
+                s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width,
+                                         S3C_GPIO_SFN(2));
+        /* Set GPG[6] pin to special-function 2 - MMC0 CDn */
+        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+                if (soc_is_s5p6450()) {
+                        s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2));
+                } else {
+                        s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2));
+                }
+        }
+}
+void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+        struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
+        /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2));
+        else
+                s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2));
+        switch (width) {
+        case 8:
+                /* Set data pins GPH[6:9] special-function 2 */
+                if (soc_is_s5p6450())
+                        s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4,
+                                                 S3C_GPIO_SFN(2));
+                else
+                        s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4,
+                                                 S3C_GPIO_SFN(2));
+        case 4:
+                /* set data pins GPH[2:5] special-function 2 */
+                if (soc_is_s5p6450())
+                        s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4,
+                                                 S3C_GPIO_SFN(2));
+                else
+                        s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4,
+                                                 S3C_GPIO_SFN(2));
+        default:
+                break;
+        }
+        /* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */
+        if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+                if (soc_is_s5p6450()) {
+                        s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3));
+                } else {
+                        s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
+                        s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3));
+                }
+        }
+}
+void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        /* Set GPC[4:5] pins to special-function 3 - CLK and CMD */
+        s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3));
+        /* Set data pins GPH[6:9] pins to special-function 3 */
+        s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3));
+}
+void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
+{
+        /* Set all the necessary GPG pins to special-function 3 */
+        s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3));
+}
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
new file mode 100644
index 00000000000..e9b84124035
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -0,0 +1,55 @@
+/* linux/arch/arm/mach-s5p64x0/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <plat/gpio-cfg.h>
+#include <plat/cpu.h>
+#include <plat/s3c64xx-spi.h>
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+        .tx_st_done     = 25,
+};
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
+                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        else
+                s3c_gpio_cfgall_range(S5P6440_GPC(0), 3,
+                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+        .tx_st_done     = 25,
+};
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        if (soc_is_s5p6450())
+                s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
+                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        else
+                s3c_gpio_cfgall_range(S5P6440_GPC(4), 3,
+                                        S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index e538a4c67e9..75a26eaf263 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -45,6 +45,11 @@ config S5PC100_SETUP_SDHCI_GPIO
        help
          Common setup code for SDHCI gpio.
+config S5PC100_SETUP_SPI
+        bool
+        help
+          Common setup code for SPI GPIO configurations.
 config MACH_SMDKC100
        bool "SMDKC100"
        select CPU_S5PC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index a5e6e608b49..118c711f74e 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -9,28 +9,24 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
-# Core support for S5PC100 system
+# Core
-obj-$(CONFIG_CPU_S5PC100)       += cpu.o init.o clock.o
+obj-y                           += common.o clock.o
-obj-$(CONFIG_CPU_S5PC100)       += setup-i2c0.o
-obj-$(CONFIG_CPU_S5PC100)       += dma.o
-# Helper and device support
+obj-y                           += dma.o
-obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)    += setup-fb-24bpp.o
-obj-$(CONFIG_S5PC100_SETUP_I2C1)        += setup-i2c1.o
-obj-$(CONFIG_S5PC100_SETUP_IDE)         += setup-ide.o
-obj-$(CONFIG_S5PC100_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_S5PC100_SETUP_SDHCI)       += setup-sdhci.o
-obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
-# device support
-obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 # machine support
 obj-$(CONFIG_MACH_SMDKC100)     += mach-smdkc100.o
 # device support
 obj-y                           += dev-audio.o
+obj-y                                   += setup-i2c0.o
+obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)    += setup-fb-24bpp.o
+obj-$(CONFIG_S5PC100_SETUP_I2C1)        += setup-i2c1.o
+obj-$(CONFIG_S5PC100_SETUP_IDE)         += setup-ide.o
+obj-$(CONFIG_S5PC100_SETUP_KEYPAD)      += setup-keypad.o
+obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_S5PC100_SETUP_SPI)         += setup-spi.o
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 8d47709da71..247194dd366 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -27,7 +27,8 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
-#include <plat/s5pc100.h>
+#include "common.h"
 static struct clk s5p_clk_otgphy = {
        .name           = "otg_phy",
@@ -426,24 +427,6 @@ static struct clk init_clocks_off[] = {
                .enable         = s5pc100_d0_2_ctrl,
                .ctrlbit        = (1 << 1),
        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 6),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_div_d1_bus.clk,
-                .enable         = s5pc100_d1_0_ctrl,
-                .ctrlbit        = (1 << 5),
-        }, {
                .name           = "modemif",
                .parent         = &clk_div_d1_bus.clk,
                .enable         = s5pc100_d1_0_ctrl,
@@ -673,24 +656,6 @@ static struct clk init_clocks_off[] = {
                .enable         = s5pc100_d1_5_ctrl,
                .ctrlbit        = (1 << 8),
        }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.0",
-                .parent         = &clk_mout_48m.clk,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = (1 << 7),
-        }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.1",
-                .parent         = &clk_mout_48m.clk,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = (1 << 8),
-        }, {
-                .name           = "spi_48m",
-                .devname        = "s3c64xx-spi.2",
-                .parent         = &clk_mout_48m.clk,
-                .enable         = s5pc100_sclk0_ctrl,
-                .ctrlbit        = (1 << 9),
-        }, {
                .name           = "mmc_48m",
                .devname        = "s3c-sdhci.0",
                .parent         = &clk_mout_48m.clk,
@@ -711,6 +676,54 @@ static struct clk init_clocks_off[] = {
        },
 };
+static struct clk clk_hsmmc2 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.2",
+        .parent         = &clk_div_d1_bus.clk,
+        .enable         = s5pc100_d1_0_ctrl,
+        .ctrlbit        = (1 << 7),
+};
+static struct clk clk_hsmmc1 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_div_d1_bus.clk,
+        .enable         = s5pc100_d1_0_ctrl,
+        .ctrlbit        = (1 << 6),
+};
+static struct clk clk_hsmmc0 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.0",
+        .parent         = &clk_div_d1_bus.clk,
+        .enable         = s5pc100_d1_0_ctrl,
+        .ctrlbit        = (1 << 5),
+};
+static struct clk clk_48m_spi0 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.0",
+        .parent         = &clk_mout_48m.clk,
+        .enable         = s5pc100_sclk0_ctrl,
+        .ctrlbit        = (1 << 7),
+};
+static struct clk clk_48m_spi1 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.1",
+        .parent         = &clk_mout_48m.clk,
+        .enable         = s5pc100_sclk0_ctrl,
+        .ctrlbit        = (1 << 8),
+};
+static struct clk clk_48m_spi2 = {
+        .name           = "spi_48m",
+        .devname        = "s3c64xx-spi.2",
+        .parent         = &clk_mout_48m.clk,
+        .enable         = s5pc100_sclk0_ctrl,
+        .ctrlbit        = (1 << 9),
+};
 static struct clk clk_vclk54m = {
        .name           = "vclk_54m",
        .rate           = 54000000,
@@ -929,49 +942,6 @@ static struct clksrc_clk clk_sclk_spdif = {
 static struct clksrc_clk clksrcs[] = {
        {
                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.0",
-                        .ctrlbit        = (1 << 4),
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources = &clk_src_group1,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.1",
-                        .ctrlbit        = (1 << 5),
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources = &clk_src_group1,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.2",
-                        .ctrlbit        = (1 << 6),
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources = &clk_src_group1,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "uclk1",
-                        .ctrlbit        = (1 << 3),
-                        .enable         = s5pc100_sclk0_ctrl,
-                },
-                .sources = &clk_src_group2,
-                .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
-                .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
                        .name           = "sclk_mixer",
                        .ctrlbit        = (1 << 6),
                        .enable         = s5pc100_sclk0_ctrl,
@@ -1024,39 +994,6 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
        }, {
                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .ctrlbit        = (1 << 12),
-                        .enable         = s5pc100_sclk1_ctrl,
-                },
-                .sources = &clk_src_mmc0,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .ctrlbit        = (1 << 13),
-                        .enable         = s5pc100_sclk1_ctrl,
-                },
-                .sources = &clk_src_mmc12,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .ctrlbit        = (1 << 14),
-                        .enable         = s5pc100_sclk1_ctrl,
-                },
-                .sources = &clk_src_mmc12,
-                .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
-                .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
-        }, {
-                .clk    = {
                        .name           = "sclk_irda",
                        .ctrlbit        = (1 << 10),
                        .enable         = s5pc100_sclk0_ctrl,
@@ -1098,6 +1035,89 @@ static struct clksrc_clk clksrcs[] = {
        },
 };
+static struct clksrc_clk clk_sclk_uart = {
+        .clk    = {
+                .name           = "uclk1",
+                .ctrlbit        = (1 << 3),
+                .enable         = s5pc100_sclk0_ctrl,
+        },
+        .sources = &clk_src_group2,
+        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
+        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .ctrlbit        = (1 << 12),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_mmc0,
+        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .ctrlbit        = (1 << 13),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_mmc12,
+        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk    = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .ctrlbit        = (1 << 14),
+                .enable         = s5pc100_sclk1_ctrl,
+        },
+        .sources = &clk_src_mmc12,
+        .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .ctrlbit        = (1 << 4),
+                .enable         = s5pc100_sclk0_ctrl,
+        },
+        .sources = &clk_src_group1,
+        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .ctrlbit        = (1 << 5),
+                .enable         = s5pc100_sclk0_ctrl,
+        },
+        .sources = &clk_src_group1,
+        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_spi2 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.2",
+                .ctrlbit        = (1 << 6),
+                .enable         = s5pc100_sclk0_ctrl,
+        },
+        .sources = &clk_src_group1,
+        .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
+        .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
+};
 /* Clock initialisation code */
 static struct clksrc_clk *sysclks[] = {
        &clk_mout_apll,
@@ -1127,6 +1147,25 @@ static struct clksrc_clk *sysclks[] = {
        &clk_sclk_spdif,
 };
+static struct clk *clk_cdev[] = {
+        &clk_hsmmc0,
+        &clk_hsmmc1,
+        &clk_hsmmc2,
+        &clk_48m_spi0,
+        &clk_48m_spi1,
+        &clk_48m_spi2,
+};
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uart,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+        &clk_sclk_spi2,
+};
 void __init_or_cpufreq s5pc100_setup_clocks(void)
 {
        unsigned long xtal;
@@ -1266,6 +1305,24 @@ static struct clk *clks[] __initdata = {
        &clk_pcmcdclk1,
 };
+static struct clk_lookup s5pc100_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
+        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
+        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
+};
 void __init s5pc100_register_clocks(void)
 {
        int ptr;
@@ -1277,9 +1334,16 @@ void __init s5pc100_register_clocks(void)
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+                s3c_disable_clocks(clk_cdev[ptr], 1);
        s3c24xx_register_clock(&dummy_apb_pclk);
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
new file mode 100644
index 00000000000..c9095730a7f
--- /dev/null
+++ b/arch/arm/mach-s5pc100/common.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Common Codes for S5PC100
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <asm/irq.h>
+#include <asm/proc-fns.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/map.h>
+#include <mach/hardware.h>
+#include <mach/regs-clock.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/sdhci.h>
+#include <plat/adc-core.h>
+#include <plat/ata-core.h>
+#include <plat/fb-core.h>
+#include <plat/iic-core.h>
+#include <plat/onenand-core.h>
+#include <plat/regs-serial.h>
+#include <plat/watchdog-reset.h>
+#include "common.h"
+static const char name_s5pc100[] = "S5PC100";
+static struct cpu_table cpu_ids[] __initdata = {
+        {
+                .idcode         = S5PC100_CPU_ID,
+                .idmask         = S5PC100_CPU_MASK,
+                .map_io         = s5pc100_map_io,
+                .init_clocks    = s5pc100_init_clocks,
+                .init_uarts     = s5pc100_init_uarts,
+                .init           = s5pc100_init,
+                .name           = name_s5pc100,
+        },
+};
+/* Initial IO mappings */
+static struct map_desc s5pc100_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_CHIPID,
+                .pfn            = __phys_to_pfn(S5PC100_PA_CHIPID),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_SYS,
+                .pfn            = __phys_to_pfn(S5PC100_PA_SYSCON),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_TIMER,
+                .pfn            = __phys_to_pfn(S5PC100_PA_TIMER),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+                .pfn            = __phys_to_pfn(S5PC100_PA_WATCHDOG),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SROMC,
+                .pfn            = __phys_to_pfn(S5PC100_PA_SROMC),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+                .pfn            = __phys_to_pfn(S5PC100_PA_SYSTIMER),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5PC100_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5PC100_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC2,
+                .pfn            = __phys_to_pfn(S5PC100_PA_VIC2),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC100_VA_OTHERS,
+                .pfn            = __phys_to_pfn(S5PC100_PA_OTHERS),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }
+};
+static void s5pc100_idle(void)
+{
+        if (!need_resched())
+                cpu_do_idle();
+        local_irq_enable();
+}
+/*
+ * s5pc100_map_io
+ *
+ * register the standard CPU IO areas
+ */
+void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
+{
+        /* initialize the io descriptors we need for initialization */
+        iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
+        if (mach_desc)
+                iotable_init(mach_desc, size);
+        /* detect cpu id and rev. */
+        s5p_init_cpu(S5P_VA_CHIPID);
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+}
+void __init s5pc100_map_io(void)
+{
+        /* initialise device information early */
+        s5pc100_default_sdhci0();
+        s5pc100_default_sdhci1();
+        s5pc100_default_sdhci2();
+        s3c_adc_setname("s3c64xx-adc");
+        /* the i2c devices are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_i2c1_setname("s3c2440-i2c");
+        s3c_onenand_setname("s5pc100-onenand");
+        s3c_fb_setname("s5pc100-fb");
+        s3c_cfcon_setname("s5pc100-pata");
+}
+void __init s5pc100_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        s5pc100_register_clocks();
+        s5pc100_setup_clocks();
+}
+void __init s5pc100_init_irq(void)
+{
+        u32 vic[] = {~0, ~0, ~0};
+        /* VIC0, VIC1, and VIC2 are fully populated. */
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
+}
+static struct bus_type s5pc100_subsys = {
+        .name           = "s5pc100-core",
+        .dev_name       = "s5pc100-core",
+};
+static struct device s5pc100_dev = {
+        .bus    = &s5pc100_subsys,
+};
+static int __init s5pc100_core_init(void)
+{
+        return subsys_system_register(&s5pc100_subsys, NULL);
+}
+core_initcall(s5pc100_core_init);
+int __init s5pc100_init(void)
+{
+        printk(KERN_INFO "S5PC100: Initializing architecture\n");
+        /* set idle function */
+        pm_idle = s5pc100_idle;
+        return device_register(&s5pc100_dev);
+}
+/* uart registration process */
+void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
+}
+void s5pc100_restart(char mode, const char *cmd)
+{
+        if (mode != 's')
+                arch_wdt_reset();
+        soft_restart(0);
+}
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
new file mode 100644
index 00000000000..9fbd3ae2b40
--- /dev/null
+++ b/arch/arm/mach-s5pc100/common.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Common Header for S5PC100 machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
+#define __ARCH_ARM_MACH_S5PC100_COMMON_H
+void s5pc100_init_io(struct map_desc *mach_desc, int size);
+void s5pc100_init_irq(void);
+void s5pc100_register_clocks(void);
+void s5pc100_setup_clocks(void);
+void s5pc100_restart(char mode, const char *cmd);
+#ifdef CONFIG_CPU_S5PC100
+extern  int s5pc100_init(void);
+extern void s5pc100_map_io(void);
+extern void s5pc100_init_clocks(int xtal);
+extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#else
+#define s5pc100_init_clocks NULL
+#define s5pc100_init_uarts NULL
+#define s5pc100_map_io NULL
+#define s5pc100_init NULL
+#endif
+#endif /* __ARCH_ARM_MACH_S5PC100_COMMON_H */
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
deleted file mode 100644
index fd2708e7d8a..00000000000
--- a/arch/arm/mach-s5pc100/cpu.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/cpu.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- * Based on mach-s3c6410/cpu.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/sysdev.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/proc-fns.h>
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/irq.h>
-#include <plat/regs-serial.h>
-#include <mach/regs-clock.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/ata-core.h>
-#include <plat/iic-core.h>
-#include <plat/sdhci.h>
-#include <plat/adc-core.h>
-#include <plat/onenand-core.h>
-#include <plat/fb-core.h>
-#include <plat/s5pc100.h>
-/* Initial IO mappings */
-static struct map_desc s5pc100_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(S5PC100_PA_SYSTIMER),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO,
-                .pfn            = __phys_to_pfn(S5PC100_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC0,
-                .pfn            = __phys_to_pfn(S5PC100_PA_VIC0),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC1,
-                .pfn            = __phys_to_pfn(S5PC100_PA_VIC1),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC2,
-                .pfn            = __phys_to_pfn(S5PC100_PA_VIC2),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S3C_PA_UART),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5PC100_VA_OTHERS,
-                .pfn            = __phys_to_pfn(S5PC100_PA_OTHERS),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }
-};
-static void s5pc100_idle(void)
-{
-        if (!need_resched())
-                cpu_do_idle();
-        local_irq_enable();
-}
-/* s5pc100_map_io
- *
- * register the standard cpu IO areas
-*/
-void __init s5pc100_map_io(void)
-{
-        iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
-        /* initialise device information early */
-        s5pc100_default_sdhci0();
-        s5pc100_default_sdhci1();
-        s5pc100_default_sdhci2();
-        s3c_adc_setname("s3c64xx-adc");
-        /* the i2c devices are directly compatible with s3c2440 */
-        s3c_i2c0_setname("s3c2440-i2c");
-        s3c_i2c1_setname("s3c2440-i2c");
-        s3c_onenand_setname("s5pc100-onenand");
-        s3c_fb_setname("s5pc100-fb");
-        s3c_cfcon_setname("s5pc100-pata");
-}
-void __init s5pc100_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5pc100_register_clocks();
-        s5pc100_setup_clocks();
-}
-void __init s5pc100_init_irq(void)
-{
-        u32 vic[] = {~0, ~0, ~0};
-        /* VIC0, VIC1, and VIC2 are fully populated. */
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-static struct sysdev_class s5pc100_sysclass = {
-        .name   = "s5pc100-core",
-};
-static struct sys_device s5pc100_sysdev = {
-        .cls    = &s5pc100_sysclass,
-};
-static int __init s5pc100_core_init(void)
-{
-        return sysdev_class_register(&s5pc100_sysclass);
-}
-core_initcall(s5pc100_core_init);
-int __init s5pc100_init(void)
-{
-        printk(KERN_INFO "S5PC100: Initializing architecture\n");
-        /* set idle function */
-        pm_idle = s5pc100_idle;
-        return sysdev_register(&s5pc100_sysdev);
-}
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c
deleted file mode 100644
index e5d6c4dceb5..00000000000
--- a/arch/arm/mach-s5pc100/dev-spi.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/dev-spi.c
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/spi-clocks.h>
-#include <mach/irqs.h>
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-#include <plat/irqs.h>
-static char *spi_src_clks[] = {
-        [S5PC100_SPI_SRCCLK_PCLK] = "pclk",
-        [S5PC100_SPI_SRCCLK_48M] = "spi_48m",
-        [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus",
-};
-/* SPI Controller platform_devices */
-/* Since we emulate multi-cs capability, we do not touch the CS.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s5pc100_spi_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
-                                      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-                break;
-        case 1:
-                s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
-                                      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-                break;
-        case 2:
-                s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
-                s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
-                                      S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
-                break;
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-        return 0;
-}
-static struct resource s5pc100_spi0_resource[] = {
-        [0] = {
-                .start = S5PC100_PA_SPI0,
-                .end   = S5PC100_PA_SPI0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI0_TX,
-                .end   = DMACH_SPI0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI0_RX,
-                .end   = DMACH_SPI0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI0,
-                .end   = IRQ_SPI0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct s3c64xx_spi_info s5pc100_spi0_pdata = {
-        .cfg_gpio = s5pc100_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .high_speed = 1,
-        .tx_st_done = 21,
-};
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-struct platform_device s5pc100_device_spi0 = {
-        .name             = "s3c64xx-spi",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5pc100_spi0_resource),
-        .resource         = s5pc100_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5pc100_spi0_pdata,
-        },
-};
-static struct resource s5pc100_spi1_resource[] = {
-        [0] = {
-                .start = S5PC100_PA_SPI1,
-                .end   = S5PC100_PA_SPI1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI1_TX,
-                .end   = DMACH_SPI1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI1_RX,
-                .end   = DMACH_SPI1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI1,
-                .end   = IRQ_SPI1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct s3c64xx_spi_info s5pc100_spi1_pdata = {
-        .cfg_gpio = s5pc100_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .high_speed = 1,
-        .tx_st_done = 21,
-};
-struct platform_device s5pc100_device_spi1 = {
-        .name             = "s3c64xx-spi",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5pc100_spi1_resource),
-        .resource         = s5pc100_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5pc100_spi1_pdata,
-        },
-};
-static struct resource s5pc100_spi2_resource[] = {
-        [0] = {
-                .start = S5PC100_PA_SPI2,
-                .end   = S5PC100_PA_SPI2 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI2_TX,
-                .end   = DMACH_SPI2_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI2_RX,
-                .end   = DMACH_SPI2_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI2,
-                .end   = IRQ_SPI2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct s3c64xx_spi_info s5pc100_spi2_pdata = {
-        .cfg_gpio = s5pc100_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 13,
-        .high_speed = 1,
-        .tx_st_done = 21,
-};
-struct platform_device s5pc100_device_spi2 = {
-        .name             = "s3c64xx-spi",
-        .id               = 2,
-        .num_resources    = ARRAY_SIZE(s5pc100_spi2_resource),
-        .resource         = s5pc100_spi2_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5pc100_spi2_pdata,
-        },
-};
-void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-        switch (cntrlr) {
-        case 0:
-                pd = &s5pc100_spi0_pdata;
-                break;
-        case 1:
-                pd = &s5pc100_spi1_pdata;
-                break;
-        case 2:
-                pd = &s5pc100_spi2_pdata;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index 065a087f5a8..c841f4d313f 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -35,100 +35,42 @@
 static u64 dma_dmamask = DMA_BIT_MASK(32);
-struct dma_pl330_peri pdma0_peri[30] = {
+u8 pdma0_peri[] = {
-        {
+        DMACH_UART0_RX,
-                .peri_id = (u8)DMACH_UART0_RX,
+        DMACH_UART0_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_UART1_RX,
-        }, {
+        DMACH_UART1_TX,
-                .peri_id = (u8)DMACH_UART0_TX,
+        DMACH_UART2_RX,
-                .rqtype = MEMTODEV,
+        DMACH_UART2_TX,
-        }, {
+        DMACH_UART3_RX,
-                .peri_id = (u8)DMACH_UART1_RX,
+        DMACH_UART3_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_IRDA,
-        }, {
+        DMACH_I2S0_RX,
-                .peri_id = (u8)DMACH_UART1_TX,
+        DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
+        DMACH_I2S0S_TX,
-        }, {
+        DMACH_I2S1_RX,
-                .peri_id = (u8)DMACH_UART2_RX,
+        DMACH_I2S1_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_I2S2_RX,
-        }, {
+        DMACH_I2S2_TX,
-                .peri_id = (u8)DMACH_UART2_TX,
+        DMACH_SPI0_RX,
-                .rqtype = MEMTODEV,
+        DMACH_SPI0_TX,
-        }, {
+        DMACH_SPI1_RX,
-                .peri_id = (u8)DMACH_UART3_RX,
+        DMACH_SPI1_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_SPI2_RX,
-        }, {
+        DMACH_SPI2_TX,
-                .peri_id = (u8)DMACH_UART3_TX,
+        DMACH_AC97_MICIN,
-                .rqtype = MEMTODEV,
+        DMACH_AC97_PCMIN,
-        }, {
+        DMACH_AC97_PCMOUT,
-                .peri_id = DMACH_IRDA,
+        DMACH_EXTERNAL,
-        }, {
+        DMACH_PWM,
-                .peri_id = (u8)DMACH_I2S0_RX,
+        DMACH_SPDIF,
-                .rqtype = DEVTOMEM,
+        DMACH_HSI_RX,
-        }, {
+        DMACH_HSI_TX,
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_AC97_MICIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMOUT,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_EXTERNAL,
-        }, {
-                .peri_id = (u8)DMACH_PWM,
-        }, {
-                .peri_id = (u8)DMACH_SPDIF,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_HSI_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_HSI_TX,
-                .rqtype = MEMTODEV,
-        },
 };
 struct dma_pl330_platdata s5pc100_pdma0_pdata = {
        .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-        .peri = pdma0_peri,
+        .peri_id = pdma0_peri,
 };
 struct amba_device s5pc100_device_pdma0 = {
@@ -147,98 +89,42 @@ struct amba_device s5pc100_device_pdma0 = {
        .periphid = 0x00041330,
 };
-struct dma_pl330_peri pdma1_peri[30] = {
+u8 pdma1_peri[] = {
-        {
+        DMACH_UART0_RX,
-                .peri_id = (u8)DMACH_UART0_RX,
+        DMACH_UART0_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_UART1_RX,
-        }, {
+        DMACH_UART1_TX,
-                .peri_id = (u8)DMACH_UART0_TX,
+        DMACH_UART2_RX,
-                .rqtype = MEMTODEV,
+        DMACH_UART2_TX,
-        }, {
+        DMACH_UART3_RX,
-                .peri_id = (u8)DMACH_UART1_RX,
+        DMACH_UART3_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_IRDA,
-        }, {
+        DMACH_I2S0_RX,
-                .peri_id = (u8)DMACH_UART1_TX,
+        DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
+        DMACH_I2S0S_TX,
-        }, {
+        DMACH_I2S1_RX,
-                .peri_id = (u8)DMACH_UART2_RX,
+        DMACH_I2S1_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_I2S2_RX,
-        }, {
+        DMACH_I2S2_TX,
-                .peri_id = (u8)DMACH_UART2_TX,
+        DMACH_SPI0_RX,
-                .rqtype = MEMTODEV,
+        DMACH_SPI0_TX,
-        }, {
+        DMACH_SPI1_RX,
-                .peri_id = (u8)DMACH_UART3_RX,
+        DMACH_SPI1_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_SPI2_RX,
-        }, {
+        DMACH_SPI2_TX,
-                .peri_id = (u8)DMACH_UART3_TX,
+        DMACH_PCM0_RX,
-                .rqtype = MEMTODEV,
+        DMACH_PCM0_TX,
-        }, {
+        DMACH_PCM1_RX,
-                .peri_id = DMACH_IRDA,
+        DMACH_PCM1_TX,
-        }, {
+        DMACH_MSM_REQ0,
-                .peri_id = (u8)DMACH_I2S0_RX,
+        DMACH_MSM_REQ1,
-                .rqtype = DEVTOMEM,
+        DMACH_MSM_REQ2,
-        }, {
+        DMACH_MSM_REQ3,
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ0,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ1,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ2,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ3,
-        },
 };
 struct dma_pl330_platdata s5pc100_pdma1_pdata = {
        .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-        .peri = pdma1_peri,
+        .peri_id = pdma1_peri,
 };
 struct amba_device s5pc100_device_pdma1 = {
@@ -259,7 +145,12 @@ struct amba_device s5pc100_device_pdma1 = {
 static int __init s5pc100_dma_init(void)
 {
+        dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
        amba_device_register(&s5pc100_device_pdma0, &iomem_resource);
+        dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
        amba_device_register(&s5pc100_device_pdma1, &iomem_resource);
        return 0;
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
index ba76af052c8..b8c242edfa2 100644
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -12,39 +12,14 @@
 * warranty of any kind, whether express or implied.
 */
-#include <asm/hardware/vic.h>
-#include <mach/map.h>
-#include <plat/irqs.h>
        .macro  disable_fiq
        .endm
        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =VA_VIC0
        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ check the vic0
-        mov     \irqnr, # S5P_IRQ_OFFSET + 31
-        ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
-        teq     \irqstat, #0
-        @ otherwise try vic1
-        addeq   \tmp, \base, #(VA_VIC1 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        @ otherwise try vic2
-        addeq   \tmp, \base, #(VA_VIC2 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        clzne   \irqstat, \irqstat
-        subne   \irqnr, \irqnr, \irqstat
        .endm
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index d2eb4757381..2870f12c792 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -97,6 +97,8 @@
 #define IRQ_SDMFIQ              S5P_IRQ_VIC2(31)
 #define IRQ_VIC_END             S5P_IRQ_VIC2(31)
+#define IRQ_TIMER_BASE          (11)
 #define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index ccbe6b767f7..54bc4f82e17 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -100,6 +100,9 @@
 #define S3C_PA_USB_HSOTG                S5PC100_PA_USB_HSOTG
 #define S3C_PA_USB_HSPHY                S5PC100_PA_USB_HSPHY
 #define S3C_PA_WDT                      S5PC100_PA_WATCHDOG
+#define S3C_PA_SPI0                     S5PC100_PA_SPI0
+#define S3C_PA_SPI1                     S5PC100_PA_SPI1
+#define S3C_PA_SPI2                     S5PC100_PA_SPI2
 #define S5P_PA_CHIPID                   S5PC100_PA_CHIPID
 #define S5P_PA_FIMC0                    S5PC100_PA_FIMC0
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index a9ea57c0660..afc96c29851 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -11,8 +11,6 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
-#include <plat/system-reset.h>
 static void arch_idle(void)
 {
        /* nothing here yet */
diff --git a/arch/arm/mach-s5pc100/include/mach/vmalloc.h b/arch/arm/mach-s5pc100/include/mach/vmalloc.h
deleted file mode 100644
index 44c8e5726d9..00000000000
--- a/arch/arm/mach-s5pc100/include/mach/vmalloc.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* arch/arm/mach-s5pc100/include/mach/vmalloc.h
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C6400 vmalloc definition
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pc100/init.c b/arch/arm/mach-s5pc100/init.c
deleted file mode 100644
index 19d7b523c13..00000000000
--- a/arch/arm/mach-s5pc100/init.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/plat-s5pc100/s5pc100-init.c
- *
- * Copyright 2009 Samsung Electronics Co.
- *      Byungho Min <bhmin@samsung.com>
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/s5pc100.h>
-/* uart registration process */
-void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
-}
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 26f5c91c942..674d22992f3 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -25,6 +25,7 @@
 #include <linux/input.h>
 #include <linux/pwm_backlight.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -42,7 +43,6 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/s5pc100.h>
 #include <plat/fb.h>
 #include <plat/iic.h>
 #include <plat/ata.h>
@@ -53,6 +53,8 @@
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKC100_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -215,7 +217,7 @@ static struct platform_pwm_backlight_data smdkc100_bl_data = {
 static void __init smdkc100_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s5pc100_init_io(NULL, 0);
        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
 }
@@ -250,7 +252,9 @@ MACHINE_START(SMDKC100, "SMDKC100")
        /* Maintainer: Byungho Min <bhmin@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pc100_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdkc100_map_io,
        .init_machine   = smdkc100_machine_init,
        .timer          = &s3c24xx_timer,
+        .restart        = s5pc100_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pc100/setup-sdhci.c b/arch/arm/mach-s5pc100/setup-sdhci.c
deleted file mode 100644
index 6418c6e8a7b..00000000000
--- a/arch/arm/mach-s5pc100/setup-sdhci.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/setup-sdhci.c
- *
- * Copyright 2008 Samsung Electronics
- *
- * S5PC100 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * Based on mach-s3c6410/setup-sdhci.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/types.h>
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-char *s5pc100_hsmmc_clksrcs[4] = {
-        [0] = "hsmmc",          /* HCLK */
-        /* [1] = "hsmmc",       - duplicate HCLK entry */
-        [2] = "sclk_mmc",       /* mmc_bus */
-        /* [3] = "48m",         - note not successfully used yet */
-};
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
new file mode 100644
index 00000000000..431a6f747ca
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -0,0 +1,65 @@
+/* linux/arch/arm/mach-s5pc100/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .high_speed     = 1,
+        .tx_st_done     = 21,
+};
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .high_speed     = 1,
+        .tx_st_done     = 21,
+};
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+#ifdef CONFIG_S3C64XX_DEV_SPI2
+struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 13,
+        .high_speed     = 1,
+        .tx_st_done     = 21,
+};
+int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
+        s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
+                                S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 646057ab2e4..2cdc42e838b 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -60,6 +60,11 @@ config S5PV210_SETUP_FIMC
        help
          Common setup code for the camera interfaces.
+config S5PV210_SETUP_SPI
+        bool
+        help
+          Common setup code for SPI GPIO configurations.
 menu "S5PC110 Machines"
 config MACH_AQUILA
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 009fbe53df9..76a121dd52b 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -10,30 +10,32 @@ obj-m				:=
 obj-n                           :=
 obj-                            :=
-# Core support for S5PV210 system
+# Core
+obj-y                           += common.o clock.o
-obj-$(CONFIG_CPU_S5PV210)       += cpu.o init.o clock.o dma.o
-obj-$(CONFIG_CPU_S5PV210)       += setup-i2c0.o
 obj-$(CONFIG_PM)                += pm.o
+obj-y                           += dma.o
 # machine support
 obj-$(CONFIG_MACH_AQUILA)       += mach-aquila.o
-obj-$(CONFIG_MACH_SMDKV210)     += mach-smdkv210.o
-obj-$(CONFIG_MACH_SMDKC110)     += mach-smdkc110.o
 obj-$(CONFIG_MACH_GONI)         += mach-goni.o
+obj-$(CONFIG_MACH_SMDKC110)     += mach-smdkc110.o
+obj-$(CONFIG_MACH_SMDKV210)     += mach-smdkv210.o
 obj-$(CONFIG_MACH_TORBRECK)     += mach-torbreck.o
 # device support
 obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
+obj-y                                   += setup-i2c0.o
 obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)    += setup-fb-24bpp.o
 obj-$(CONFIG_S5PV210_SETUP_FIMC)        += setup-fimc.o
-obj-$(CONFIG_S5PV210_SETUP_I2C1)        += setup-i2c1.o
+obj-$(CONFIG_S5PV210_SETUP_I2C1)        += setup-i2c1.o
-obj-$(CONFIG_S5PV210_SETUP_I2C2)        += setup-i2c2.o
+obj-$(CONFIG_S5PV210_SETUP_I2C2)        += setup-i2c2.o
 obj-$(CONFIG_S5PV210_SETUP_IDE)         += setup-ide.o
 obj-$(CONFIG_S5PV210_SETUP_KEYPAD)      += setup-keypad.o
-obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
+obj-$(CONFIG_S5PV210_SETUP_SPI)         += setup-spi.o
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 4c5ac7a69e9..c78dfddd77f 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -17,7 +17,7 @@
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/clk.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/io.h>
 #include <mach/map.h>
@@ -29,7 +29,8 @@
 #include <plat/pll.h>
 #include <plat/s5p-clock.h>
 #include <plat/clock-clksrc.h>
-#include <plat/s5pv210.h>
+#include "common.h"
 static unsigned long xtal;
@@ -399,30 +400,6 @@ static struct clk init_clocks_off[] = {
                .enable         = s5pv210_clk_ip1_ctrl,
                .ctrlbit        = (1<<25),
        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<16),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<17),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<18),
-        }, {
-                .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
-                .parent         = &clk_hclk_psys.clk,
-                .enable         = s5pv210_clk_ip2_ctrl,
-                .ctrlbit        = (1<<19),
-        }, {
                .name           = "systimer",
                .parent         = &clk_pclk_psys.clk,
                .enable         = s5pv210_clk_ip3_ctrl,
@@ -559,6 +536,38 @@ static struct clk init_clocks[] = {
        },
 };
+static struct clk clk_hsmmc0 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.0",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<16),
+};
+static struct clk clk_hsmmc1 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.1",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<17),
+};
+static struct clk clk_hsmmc2 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.2",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<18),
+};
+static struct clk clk_hsmmc3 = {
+        .name           = "hsmmc",
+        .devname        = "s3c-sdhci.3",
+        .parent         = &clk_hclk_psys.clk,
+        .enable         = s5pv210_clk_ip2_ctrl,
+        .ctrlbit        = (1<<19),
+};
 static struct clk *clkset_uart_list[] = {
        [6] = &clk_mout_mpll.clk,
        [7] = &clk_mout_epll.clk,
@@ -809,46 +818,6 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
        }, {
                .clk    = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.0",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 12),
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.1",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 13),
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.2",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 14),
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "uclk1",
-                        .devname        = "s5pv210-uart.3",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 15),
-                },
-                .sources = &clkset_uart,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
-        }, {
-                .clk    = {
                        .name           = "sclk_fimc",
                        .devname        = "s5pv210-fimc.0",
                        .enable         = s5pv210_clk_mask1_ctrl,
@@ -906,46 +875,6 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
        }, {
                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.0",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 8),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.1",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 9),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.2",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 10),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_mmc",
-                        .devname        = "s3c-sdhci.3",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 11),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
-        }, {
-                .clk            = {
                        .name           = "sclk_mfc",
                        .devname        = "s5p-mfc",
                        .enable         = s5pv210_clk_ip0_ctrl,
@@ -983,26 +912,6 @@ static struct clksrc_clk clksrcs[] = {
                .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
        }, {
                .clk            = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.0",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 16),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
-        }, {
-                .clk            = {
-                        .name           = "sclk_spi",
-                        .devname        = "s3c64xx-spi.1",
-                        .enable         = s5pv210_clk_mask0_ctrl,
-                        .ctrlbit        = (1 << 17),
-                },
-                .sources = &clkset_group2,
-                .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
-                .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
-        }, {
-                .clk            = {
                        .name           = "sclk_pwi",
                        .enable         = s5pv210_clk_mask0_ctrl,
                        .ctrlbit        = (1 << 29),
@@ -1022,6 +931,147 @@ static struct clksrc_clk clksrcs[] = {
        },
 };
+static struct clksrc_clk clk_sclk_uart0 = {
+        .clk    = {
+                .name           = "uclk1",
+                .devname        = "s5pv210-uart.0",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 12),
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_uart1 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "s5pv210-uart.1",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 13),
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_uart2 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "s5pv210-uart.2",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 14),
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_uart3 = {
+        .clk            = {
+                .name           = "uclk1",
+                .devname        = "s5pv210-uart.3",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 15),
+        },
+        .sources = &clkset_uart,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc0 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.0",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 8),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc1 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.1",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 9),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc2 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.2",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 10),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_mmc3 = {
+        .clk            = {
+                .name           = "sclk_mmc",
+                .devname        = "s3c-sdhci.3",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 11),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
+};
+static struct clksrc_clk clk_sclk_spi0 = {
+        .clk            = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.0",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 16),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
+        };
+static struct clksrc_clk clk_sclk_spi1 = {
+        .clk            = {
+                .name           = "sclk_spi",
+                .devname        = "s3c64xx-spi.1",
+                .enable         = s5pv210_clk_mask0_ctrl,
+                .ctrlbit        = (1 << 17),
+        },
+        .sources = &clkset_group2,
+        .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
+        .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
+        };
+static struct clksrc_clk *clksrc_cdev[] = {
+        &clk_sclk_uart0,
+        &clk_sclk_uart1,
+        &clk_sclk_uart2,
+        &clk_sclk_uart3,
+        &clk_sclk_mmc0,
+        &clk_sclk_mmc1,
+        &clk_sclk_mmc2,
+        &clk_sclk_mmc3,
+        &clk_sclk_spi0,
+        &clk_sclk_spi1,
+};
+static struct clk *clk_cdev[] = {
+        &clk_hsmmc0,
+        &clk_hsmmc1,
+        &clk_hsmmc2,
+        &clk_hsmmc3,
+};
 /* Clock initialisation code */
 static struct clksrc_clk *sysclks[] = {
        &clk_mout_apll,
@@ -1261,6 +1311,25 @@ static struct clk *clks[] __initdata = {
        &clk_pcmcdclk2,
 };
+static struct clk_lookup s5pv210_clk_lookup[] = {
+        CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
+        CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk),
+        CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
+        CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
+        CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
+        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
+        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
+        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
+        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
+        CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
+        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+};
 void __init s5pv210_register_clocks(void)
 {
        int ptr;
@@ -1273,11 +1342,19 @@ void __init s5pv210_register_clocks(void)
        for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
                s3c_register_clksrc(sclk_tv[ptr], 1);
+        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
+                s3c_register_clksrc(clksrc_cdev[ptr], 1);
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+        clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
+        s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+        for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+                s3c_disable_clocks(clk_cdev[ptr], 1);
        s3c24xx_register_clock(&dummy_apb_pclk);
        s3c_pwmclk_init();
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
new file mode 100644
index 00000000000..9c1bcdcc12c
--- /dev/null
+++ b/arch/arm/mach-s5pv210/common.c
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Common Codes for S5PV210
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial_core.h>
+#include <asm/proc-fns.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/sdhci.h>
+#include <plat/adc-core.h>
+#include <plat/ata-core.h>
+#include <plat/fb-core.h>
+#include <plat/fimc-core.h>
+#include <plat/iic-core.h>
+#include <plat/keypad-core.h>
+#include <plat/tv-core.h>
+#include <plat/regs-serial.h>
+#include "common.h"
+static const char name_s5pv210[] = "S5PV210/S5PC110";
+static struct cpu_table cpu_ids[] __initdata = {
+        {
+                .idcode         = S5PV210_CPU_ID,
+                .idmask         = S5PV210_CPU_MASK,
+                .map_io         = s5pv210_map_io,
+                .init_clocks    = s5pv210_init_clocks,
+                .init_uarts     = s5pv210_init_uarts,
+                .init           = s5pv210_init,
+                .name           = name_s5pv210,
+        },
+};
+/* Initial IO mappings */
+static struct map_desc s5pv210_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5P_VA_CHIPID,
+                .pfn            = __phys_to_pfn(S5PV210_PA_CHIPID),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_SYS,
+                .pfn            = __phys_to_pfn(S5PV210_PA_SYSCON),
+                .length         = SZ_64K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_TIMER,
+                .pfn            = __phys_to_pfn(S5PV210_PA_TIMER),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+                .pfn            = __phys_to_pfn(S5PV210_PA_WATCHDOG),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SROMC,
+                .pfn            = __phys_to_pfn(S5PV210_PA_SROMC),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+                .pfn            = __phys_to_pfn(S5PV210_PA_SYSTIMER),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_GPIO,
+                .pfn            = __phys_to_pfn(S5PV210_PA_GPIO),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC0,
+                .pfn            = __phys_to_pfn(S5PV210_PA_VIC0),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC1,
+                .pfn            = __phys_to_pfn(S5PV210_PA_VIC1),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC2,
+                .pfn            = __phys_to_pfn(S5PV210_PA_VIC2),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)VA_VIC3,
+                .pfn            = __phys_to_pfn(S5PV210_PA_VIC3),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_UART,
+                .pfn            = __phys_to_pfn(S3C_PA_UART),
+                .length         = SZ_512K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_DMC0,
+                .pfn            = __phys_to_pfn(S5PV210_PA_DMC0),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_DMC1,
+                .pfn            = __phys_to_pfn(S5PV210_PA_DMC1),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+                .pfn            =__phys_to_pfn(S5PV210_PA_HSPHY),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }
+};
+static void s5pv210_idle(void)
+{
+        if (!need_resched())
+                cpu_do_idle();
+        local_irq_enable();
+}
+void s5pv210_restart(char mode, const char *cmd)
+{
+        __raw_writel(0x1, S5P_SWRESET);
+}
+/*
+ * s5pv210_map_io
+ *
+ * register the standard cpu IO areas
+ */
+void __init s5pv210_init_io(struct map_desc *mach_desc, int size)
+{
+        /* initialize the io descriptors we need for initialization */
+        iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
+        if (mach_desc)
+                iotable_init(mach_desc, size);
+        /* detect cpu id and rev. */
+        s5p_init_cpu(S5P_VA_CHIPID);
+        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
+}
+void __init s5pv210_map_io(void)
+{
+        init_consistent_dma_size(14 << 20);
+        /* initialise device information early */
+        s5pv210_default_sdhci0();
+        s5pv210_default_sdhci1();
+        s5pv210_default_sdhci2();
+        s5pv210_default_sdhci3();
+        s3c_adc_setname("samsung-adc-v3");
+        s3c_cfcon_setname("s5pv210-pata");
+        s3c_fimc_setname(0, "s5pv210-fimc");
+        s3c_fimc_setname(1, "s5pv210-fimc");
+        s3c_fimc_setname(2, "s5pv210-fimc");
+        /* the i2c devices are directly compatible with s3c2440 */
+        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_i2c1_setname("s3c2440-i2c");
+        s3c_i2c2_setname("s3c2440-i2c");
+        s3c_fb_setname("s5pv210-fb");
+        /* Use s5pv210-keypad instead of samsung-keypad */
+        samsung_keypad_setname("s5pv210-keypad");
+        /* setup TV devices */
+        s5p_hdmi_setname("s5pv210-hdmi");
+}
+void __init s5pv210_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+        s3c24xx_register_baseclocks(xtal);
+        s5p_register_clocks(xtal);
+        s5pv210_register_clocks();
+        s5pv210_setup_clocks();
+}
+void __init s5pv210_init_irq(void)
+{
+        u32 vic[4];     /* S5PV210 supports 4 VIC */
+        /* All the VICs are fully populated. */
+        vic[0] = ~0;
+        vic[1] = ~0;
+        vic[2] = ~0;
+        vic[3] = ~0;
+        s5p_init_irq(vic, ARRAY_SIZE(vic));
+}
+struct bus_type s5pv210_subsys = {
+        .name           = "s5pv210-core",
+        .dev_name       = "s5pv210-core",
+};
+static struct device s5pv210_dev = {
+        .bus    = &s5pv210_subsys,
+};
+static int __init s5pv210_core_init(void)
+{
+        return subsys_system_register(&s5pv210_subsys, NULL);
+}
+core_initcall(s5pv210_core_init);
+int __init s5pv210_init(void)
+{
+        printk(KERN_INFO "S5PV210: Initializing architecture\n");
+        /* set idle function */
+        pm_idle = s5pv210_idle;
+        return device_register(&s5pv210_dev);
+}
+/* uart registration process */
+void __init s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
+}
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
new file mode 100644
index 00000000000..6ed2af5c751
--- /dev/null
+++ b/arch/arm/mach-s5pv210/common.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Common Header for S5PV210 machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_ARM_MACH_S5PV210_COMMON_H
+#define __ARCH_ARM_MACH_S5PV210_COMMON_H
+void s5pv210_init_io(struct map_desc *mach_desc, int size);
+void s5pv210_init_irq(void);
+void s5pv210_register_clocks(void);
+void s5pv210_setup_clocks(void);
+void s5pv210_restart(char mode, const char *cmd);
+#ifdef CONFIG_CPU_S5PV210
+extern  int s5pv210_init(void);
+extern void s5pv210_map_io(void);
+extern void s5pv210_init_clocks(int xtal);
+extern void s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+#else
+#define s5pv210_init_clocks NULL
+#define s5pv210_init_uarts NULL
+#define s5pv210_map_io NULL
+#define s5pv210_init NULL
+#endif
+#endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
deleted file mode 100644
index 84ec7463323..00000000000
--- a/arch/arm/mach-s5pv210/cpu.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/cpu.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/sysdev.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/dma-mapping.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/proc-fns.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/fb-core.h>
-#include <plat/s5pv210.h>
-#include <plat/adc-core.h>
-#include <plat/ata-core.h>
-#include <plat/fimc-core.h>
-#include <plat/iic-core.h>
-#include <plat/keypad-core.h>
-#include <plat/sdhci.h>
-#include <plat/reset.h>
-#include <plat/tv-core.h>
-/* Initial IO mappings */
-static struct map_desc s5pv210_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(S5PV210_PA_SYSTIMER),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO,
-                .pfn            = __phys_to_pfn(S5PV210_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC0,
-                .pfn            = __phys_to_pfn(S5PV210_PA_VIC0),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC1,
-                .pfn            = __phys_to_pfn(S5PV210_PA_VIC1),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC2,
-                .pfn            = __phys_to_pfn(S5PV210_PA_VIC2),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC3,
-                .pfn            = __phys_to_pfn(S5PV210_PA_VIC3),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S3C_PA_UART),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_DMC0,
-                .pfn            = __phys_to_pfn(S5PV210_PA_DMC0),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_DMC1,
-                .pfn            = __phys_to_pfn(S5PV210_PA_DMC1),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
-                .pfn            =__phys_to_pfn(S5PV210_PA_HSPHY),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }
-};
-static void s5pv210_idle(void)
-{
-        if (!need_resched())
-                cpu_do_idle();
-        local_irq_enable();
-}
-static void s5pv210_sw_reset(void)
-{
-        __raw_writel(0x1, S5P_SWRESET);
-}
-/* s5pv210_map_io
- *
- * register the standard cpu IO areas
-*/
-void __init s5pv210_map_io(void)
-{
-        iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
-        init_consistent_dma_size(14 << 20);
-        /* initialise device information early */
-        s5pv210_default_sdhci0();
-        s5pv210_default_sdhci1();
-        s5pv210_default_sdhci2();
-        s5pv210_default_sdhci3();
-        s3c_adc_setname("samsung-adc-v3");
-        s3c_cfcon_setname("s5pv210-pata");
-        s3c_fimc_setname(0, "s5pv210-fimc");
-        s3c_fimc_setname(1, "s5pv210-fimc");
-        s3c_fimc_setname(2, "s5pv210-fimc");
-        /* the i2c devices are directly compatible with s3c2440 */
-        s3c_i2c0_setname("s3c2440-i2c");
-        s3c_i2c1_setname("s3c2440-i2c");
-        s3c_i2c2_setname("s3c2440-i2c");
-        s3c_fb_setname("s5pv210-fb");
-        /* Use s5pv210-keypad instead of samsung-keypad */
-        samsung_keypad_setname("s5pv210-keypad");
-        /* setup TV devices */
-        s5p_hdmi_setname("s5pv210-hdmi");
-}
-void __init s5pv210_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5pv210_register_clocks();
-        s5pv210_setup_clocks();
-}
-void __init s5pv210_init_irq(void)
-{
-        u32 vic[4];     /* S5PV210 supports 4 VIC */
-        /* All the VICs are fully populated. */
-        vic[0] = ~0;
-        vic[1] = ~0;
-        vic[2] = ~0;
-        vic[3] = ~0;
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-struct sysdev_class s5pv210_sysclass = {
-        .name   = "s5pv210-core",
-};
-static struct sys_device s5pv210_sysdev = {
-        .cls    = &s5pv210_sysclass,
-};
-static int __init s5pv210_core_init(void)
-{
-        return sysdev_class_register(&s5pv210_sysclass);
-}
-core_initcall(s5pv210_core_init);
-int __init s5pv210_init(void)
-{
-        printk(KERN_INFO "S5PV210: Initializing architecture\n");
-        /* set idle function */
-        pm_idle = s5pv210_idle;
-        /* set sw_reset function */
-        s5p_reset_hook = s5pv210_sw_reset;
-        return sysdev_register(&s5pv210_sysdev);
-}
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c
deleted file mode 100644
index eaf9a7bff7a..00000000000
--- a/arch/arm/mach-s5pv210/dev-spi.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/dev-spi.c
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/spi-clocks.h>
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-static char *spi_src_clks[] = {
-        [S5PV210_SPI_SRCCLK_PCLK] = "pclk",
-        [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi",
-};
-/* SPI Controller platform_devices */
-/* Since we emulate multi-cs capability, we do not touch the CS.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s5pv210_spi_cfg_gpio(struct platform_device *pdev)
-{
-        unsigned int base;
-        switch (pdev->id) {
-        case 0:
-                base = S5PV210_GPB(0);
-                break;
-        case 1:
-                base = S5PV210_GPB(4);
-                break;
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-        s3c_gpio_cfgall_range(base, 3,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-        return 0;
-}
-static struct resource s5pv210_spi0_resource[] = {
-        [0] = {
-                .start = S5PV210_PA_SPI0,
-                .end   = S5PV210_PA_SPI0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI0_TX,
-                .end   = DMACH_SPI0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI0_RX,
-                .end   = DMACH_SPI0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI0,
-                .end   = IRQ_SPI0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct s3c64xx_spi_info s5pv210_spi0_pdata = {
-        .cfg_gpio = s5pv210_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x1ff,
-        .rx_lvl_offset = 15,
-        .high_speed = 1,
-        .tx_st_done = 25,
-};
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-struct platform_device s5pv210_device_spi0 = {
-        .name             = "s3c64xx-spi",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5pv210_spi0_resource),
-        .resource         = s5pv210_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5pv210_spi0_pdata,
-        },
-};
-static struct resource s5pv210_spi1_resource[] = {
-        [0] = {
-                .start = S5PV210_PA_SPI1,
-                .end   = S5PV210_PA_SPI1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI1_TX,
-                .end   = DMACH_SPI1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI1_RX,
-                .end   = DMACH_SPI1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI1,
-                .end   = IRQ_SPI1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-static struct s3c64xx_spi_info s5pv210_spi1_pdata = {
-        .cfg_gpio = s5pv210_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x7f,
-        .rx_lvl_offset = 15,
-        .high_speed = 1,
-        .tx_st_done = 25,
-};
-struct platform_device s5pv210_device_spi1 = {
-        .name             = "s3c64xx-spi",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5pv210_spi1_resource),
-        .resource         = s5pv210_spi1_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5pv210_spi1_pdata,
-        },
-};
-void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-        switch (cntrlr) {
-        case 0:
-                pd = &s5pv210_spi0_pdata;
-                break;
-        case 1:
-                pd = &s5pv210_spi1_pdata;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s5pv210/dma.c b/arch/arm/mach-s5pv210/dma.c
index 86b749c18b7..a6113e0267f 100644
--- a/arch/arm/mach-s5pv210/dma.c
+++ b/arch/arm/mach-s5pv210/dma.c
@@ -35,90 +35,40 @@
 static u64 dma_dmamask = DMA_BIT_MASK(32);
-struct dma_pl330_peri pdma0_peri[28] = {
+u8 pdma0_peri[] = {
-        {
+        DMACH_UART0_RX,
-                .peri_id = (u8)DMACH_UART0_RX,
+        DMACH_UART0_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_UART1_RX,
-        }, {
+        DMACH_UART1_TX,
-                .peri_id = (u8)DMACH_UART0_TX,
+        DMACH_UART2_RX,
-                .rqtype = MEMTODEV,
+        DMACH_UART2_TX,
-        }, {
+        DMACH_UART3_RX,
-                .peri_id = (u8)DMACH_UART1_RX,
+        DMACH_UART3_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_MAX,
-        }, {
+        DMACH_I2S0_RX,
-                .peri_id = (u8)DMACH_UART1_TX,
+        DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
+        DMACH_I2S0S_TX,
-        }, {
+        DMACH_I2S1_RX,
-                .peri_id = (u8)DMACH_UART2_RX,
+        DMACH_I2S1_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_MAX,
-        }, {
+        DMACH_MAX,
-                .peri_id = (u8)DMACH_UART2_TX,
+        DMACH_SPI0_RX,
-                .rqtype = MEMTODEV,
+        DMACH_SPI0_TX,
-        }, {
+        DMACH_SPI1_RX,
-                .peri_id = (u8)DMACH_UART3_RX,
+        DMACH_SPI1_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_MAX,
-        }, {
+        DMACH_MAX,
-                .peri_id = (u8)DMACH_UART3_TX,
+        DMACH_AC97_MICIN,
-                .rqtype = MEMTODEV,
+        DMACH_AC97_PCMIN,
-        }, {
+        DMACH_AC97_PCMOUT,
-                .peri_id = DMACH_MAX,
+        DMACH_MAX,
-        }, {
+        DMACH_PWM,
-                .peri_id = (u8)DMACH_I2S0_RX,
+        DMACH_SPDIF,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_AC97_MICIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMIN,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_AC97_PCMOUT,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_PWM,
-        }, {
-                .peri_id = (u8)DMACH_SPDIF,
-                .rqtype = MEMTODEV,
-        },
 };
 struct dma_pl330_platdata s5pv210_pdma0_pdata = {
        .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
-        .peri = pdma0_peri,
+        .peri_id = pdma0_peri,
 };
 struct amba_device s5pv210_device_pdma0 = {
@@ -137,102 +87,44 @@ struct amba_device s5pv210_device_pdma0 = {
        .periphid = 0x00041330,
 };
-struct dma_pl330_peri pdma1_peri[32] = {
+u8 pdma1_peri[] = {
-        {
+        DMACH_UART0_RX,
-                .peri_id = (u8)DMACH_UART0_RX,
+        DMACH_UART0_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_UART1_RX,
-        }, {
+        DMACH_UART1_TX,
-                .peri_id = (u8)DMACH_UART0_TX,
+        DMACH_UART2_RX,
-                .rqtype = MEMTODEV,
+        DMACH_UART2_TX,
-        }, {
+        DMACH_UART3_RX,
-                .peri_id = (u8)DMACH_UART1_RX,
+        DMACH_UART3_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_MAX,
-        }, {
+        DMACH_I2S0_RX,
-                .peri_id = (u8)DMACH_UART1_TX,
+        DMACH_I2S0_TX,
-                .rqtype = MEMTODEV,
+        DMACH_I2S0S_TX,
-        }, {
+        DMACH_I2S1_RX,
-                .peri_id = (u8)DMACH_UART2_RX,
+        DMACH_I2S1_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_I2S2_RX,
-        }, {
+        DMACH_I2S2_TX,
-                .peri_id = (u8)DMACH_UART2_TX,
+        DMACH_SPI0_RX,
-                .rqtype = MEMTODEV,
+        DMACH_SPI0_TX,
-        }, {
+        DMACH_SPI1_RX,
-                .peri_id = (u8)DMACH_UART3_RX,
+        DMACH_SPI1_TX,
-                .rqtype = DEVTOMEM,
+        DMACH_MAX,
-        }, {
+        DMACH_MAX,
-                .peri_id = (u8)DMACH_UART3_TX,
+        DMACH_PCM0_RX,
-                .rqtype = MEMTODEV,
+        DMACH_PCM0_TX,
-        }, {
+        DMACH_PCM1_RX,
-                .peri_id = DMACH_MAX,
+        DMACH_PCM1_TX,
-        }, {
+        DMACH_MSM_REQ0,
-                .peri_id = (u8)DMACH_I2S0_RX,
+        DMACH_MSM_REQ1,
-                .rqtype = DEVTOMEM,
+        DMACH_MSM_REQ2,
-        }, {
+        DMACH_MSM_REQ3,
-                .peri_id = (u8)DMACH_I2S0_TX,
+        DMACH_PCM2_RX,
-                .rqtype = MEMTODEV,
+        DMACH_PCM2_TX,
-        }, {
-                .peri_id = (u8)DMACH_I2S0S_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_I2S2_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_SPI1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_MAX,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM0_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM1_TX,
-                .rqtype = MEMTODEV,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ0,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ1,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ2,
-        }, {
-                .peri_id = (u8)DMACH_MSM_REQ3,
-        }, {
-                .peri_id = (u8)DMACH_PCM2_RX,
-                .rqtype = DEVTOMEM,
-        }, {
-                .peri_id = (u8)DMACH_PCM2_TX,
-                .rqtype = MEMTODEV,
-        },
 };
 struct dma_pl330_platdata s5pv210_pdma1_pdata = {
        .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
-        .peri = pdma1_peri,
+        .peri_id = pdma1_peri,
 };
 struct amba_device s5pv210_device_pdma1 = {
@@ -253,7 +145,12 @@ struct amba_device s5pv210_device_pdma1 = {
 static int __init s5pv210_dma_init(void)
 {
+        dma_cap_set(DMA_SLAVE, s5pv210_pdma0_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, s5pv210_pdma0_pdata.cap_mask);
        amba_device_register(&s5pv210_device_pdma0, &iomem_resource);
+        dma_cap_set(DMA_SLAVE, s5pv210_pdma1_pdata.cap_mask);
+        dma_cap_set(DMA_CYCLIC, s5pv210_pdma1_pdata.cap_mask);
        amba_device_register(&s5pv210_device_pdma1, &iomem_resource);
        return 0;
diff --git a/arch/arm/mach-s5pv210/include/mach/entry-macro.S b/arch/arm/mach-s5pv210/include/mach/entry-macro.S
index 3aa41ac59f0..bebca1b5d0b 100644
--- a/arch/arm/mach-s5pv210/include/mach/entry-macro.S
+++ b/arch/arm/mach-s5pv210/include/mach/entry-macro.S
@@ -10,45 +10,8 @@
 * published by the Free Software Foundation.
 */
-#include <asm/hardware/vic.h>
-#include <mach/map.h>
-#include <plat/irqs.h>
        .macro  disable_fiq
        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =VA_VIC0
-        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        @ check the vic0
-        mov     \irqnr, # S5P_IRQ_OFFSET + 31
-        ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
-        teq     \irqstat, #0
-        @ otherwise try vic1
-        addeq   \tmp, \base, #(VA_VIC1 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        @ otherwise try vic2
-        addeq   \tmp, \base, #(VA_VIC2 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        @ otherwise try vic3
-        addeq   \tmp, \base, #(VA_VIC3 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-        clzne   \irqstat, \irqstat
-        subne   \irqnr, \irqnr, \irqstat
-        .endm
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 5e0de3a31f3..e777e010ed2 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -118,6 +118,8 @@
 #define IRQ_MDNIE3              S5P_IRQ_VIC3(8)
 #define IRQ_VIC_END             S5P_IRQ_VIC3(31)
+#define IRQ_TIMER_BASE          (11)
 #define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2          (IRQ_VIC_END + 1)
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 7ff609f1568..89c34b8f73b 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -109,6 +109,8 @@
 #define S3C_PA_RTC                      S5PV210_PA_RTC
 #define S3C_PA_USB_HSOTG                S5PV210_PA_HSOTG
 #define S3C_PA_WDT                      S5PV210_PA_WATCHDOG
+#define S3C_PA_SPI0                     S5PV210_PA_SPI0
+#define S3C_PA_SPI1                     S5PV210_PA_SPI1
 #define S5P_PA_CHIPID                   S5PV210_PA_CHIPID
 #define S5P_PA_FIMC0                    S5PV210_PA_FIMC0
diff --git a/arch/arm/mach-s5pv210/include/mach/system.h b/arch/arm/mach-s5pv210/include/mach/system.h
index af8a200b213..bf288ced860 100644
--- a/arch/arm/mach-s5pv210/include/mach/system.h
+++ b/arch/arm/mach-s5pv210/include/mach/system.h
@@ -13,8 +13,6 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
-#include <plat/system-reset.h>
 static void arch_idle(void)
 {
        /* nothing here yet */
diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h
deleted file mode 100644
index a6c659d68a5..00000000000
--- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/vmalloc.h
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Based on arch/arm/mach-s5p6442/include/mach/vmalloc.h
- *
- * S5PV210 vmalloc definition
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H __FILE__
-#define VMALLOC_END     0xF6000000UL
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv210/init.c b/arch/arm/mach-s5pv210/init.c
deleted file mode 100644
index 4865ae2c475..00000000000
--- a/arch/arm/mach-s5pv210/init.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/init.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/s5pv210.h>
-#include <plat/regs-serial.h>
-static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = {
-        [0] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-};
-/* uart registration process */
-void __init s5pv210_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-                if (!tcfg->clocks) {
-                        tcfg->clocks = s5pv210_serial_clocks;
-                        tcfg->clocks_size = ARRAY_SIZE(s5pv210_serial_clocks);
-                }
-        }
-        s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
-}
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 5811a96125f..5e734d025a6 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -22,6 +22,7 @@
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -32,7 +33,6 @@
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
-#include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
@@ -41,6 +41,8 @@
 #include <plat/s5p-time.h>
 #include <plat/regs-fb-v4.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define AQUILA_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -595,8 +597,7 @@ static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
 static void aquila_setup_sdhci(void)
 {
-        gpio_request(AQUILA_EXT_FLASH_EN, "FLASH_EN");
+        gpio_request_one(AQUILA_EXT_FLASH_EN, GPIOF_OUT_INIT_HIGH, "FLASH_EN");
-        gpio_direction_output(AQUILA_EXT_FLASH_EN, 1);
        s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
        s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
@@ -644,7 +645,7 @@ static void __init aquila_sound_init(void)
 static void __init aquila_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s5pv210_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
@@ -680,7 +681,9 @@ MACHINE_START(AQUILA, "Aquila")
           Kyungmin Park <kyungmin.park@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = aquila_map_io,
        .init_machine   = aquila_machine_init,
        .timer          = &s5p_timer,
+        .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 15edcae448b..ff915261043 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -27,6 +27,7 @@
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -37,7 +38,6 @@
 #include <plat/gpio-cfg.h>
 #include <plat/regs-serial.h>
-#include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
@@ -54,6 +54,8 @@
 #include <media/s5p_fimc.h>
 #include <media/noon010pc30.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define GONI_UCON_DEFAULT       (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -227,8 +229,7 @@ static void __init goni_radio_init(void)
        i2c1_devs[0].irq = gpio_to_irq(gpio);
        gpio = S5PV210_GPJ2(5);                 /* XMSMDATA_5 */
-        gpio_request(gpio, "FM_RST");
+        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "FM_RST");
-        gpio_direction_output(gpio, 1);
 }
 /* TSP */
@@ -264,8 +265,7 @@ static void __init goni_tsp_init(void)
        int gpio;
        gpio = S5PV210_GPJ1(3);         /* XMSMADDR_11 */
-        gpio_request(gpio, "TSP_LDO_ON");
+        gpio_request_one(gpio, GPIOF_OUT_INIT_HIGH, "TSP_LDO_ON");
-        gpio_direction_output(gpio, 1);
        gpio_export(gpio, 0);
        gpio = S5PV210_GPJ0(5);         /* XMSMADDR_5 */
@@ -890,7 +890,7 @@ static void __init goni_sound_init(void)
 static void __init goni_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s5pv210_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
@@ -956,8 +956,10 @@ MACHINE_START(GONI, "GONI")
        /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = goni_map_io,
        .init_machine   = goni_machine_init,
        .timer          = &s5p_timer,
        .reserve        = &goni_reserve,
+        .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index f7266bb0cac..b323983b2c5 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -13,8 +13,9 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/i2c.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -24,7 +25,6 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
-#include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/ata.h>
@@ -32,6 +32,8 @@
 #include <plat/pm.h>
 #include <plat/s5p-time.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKC110_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -109,7 +111,7 @@ static struct i2c_board_info smdkc110_i2c_devs2[] __initdata = {
 static void __init smdkc110_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s5pv210_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
@@ -138,7 +140,9 @@ MACHINE_START(SMDKC110, "SMDKC110")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdkc110_map_io,
        .init_machine   = smdkc110_machine_init,
        .timer          = &s5p_timer,
+        .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 8662ef6e568..dff9ea7b5bb 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -13,13 +13,14 @@
 #include <linux/i2c.h>
 #include <linux/init.h>
 #include <linux/serial_core.h>
-#include <linux/sysdev.h>
+#include <linux/device.h>
 #include <linux/dm9000.h>
 #include <linux/fb.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/pwm_backlight.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -33,7 +34,6 @@
 #include <plat/regs-serial.h>
 #include <plat/regs-srom.h>
 #include <plat/gpio-cfg.h>
-#include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/adc.h>
@@ -47,6 +47,8 @@
 #include <plat/backlight.h>
 #include <plat/regs-fb-v4.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define SMDKV210_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -153,15 +155,12 @@ static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
 {
        if (power) {
 #if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request(S5PV210_GPD0(3), "GPD0");
+                gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_HIGH, "GPD0");
-                gpio_direction_output(S5PV210_GPD0(3), 1);
                gpio_free(S5PV210_GPD0(3));
 #endif
                /* fire nRESET on power up */
-                gpio_request(S5PV210_GPH0(6), "GPH0");
+                gpio_request_one(S5PV210_GPH0(6), GPIOF_OUT_INIT_HIGH, "GPH0");
-                gpio_direction_output(S5PV210_GPH0(6), 1);
                gpio_set_value(S5PV210_GPH0(6), 0);
                mdelay(10);
@@ -172,8 +171,7 @@ static void smdkv210_lte480wv_set_power(struct plat_lcd_data *pd,
                gpio_free(S5PV210_GPH0(6));
        } else {
 #if !defined(CONFIG_BACKLIGHT_PWM)
-                gpio_request(S5PV210_GPD0(3), "GPD0");
+                gpio_request_one(S5PV210_GPD0(3), GPIOF_OUT_INIT_LOW, "GPD0");
-                gpio_direction_output(S5PV210_GPD0(3), 0);
                gpio_free(S5PV210_GPD0(3));
 #endif
        }
@@ -278,7 +276,7 @@ static struct platform_pwm_backlight_data smdkv210_bl_data = {
 static void __init smdkv210_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s5pv210_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
        s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
@@ -316,7 +314,9 @@ MACHINE_START(SMDKV210, "SMDKV210")
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = smdkv210_map_io,
        .init_machine   = smdkv210_machine_init,
        .timer          = &s5p_timer,
+        .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 97cc066c536..74e99bc0dc9 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
+#include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/setup.h>
@@ -23,12 +24,13 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
-#include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/iic.h>
 #include <plat/s5p-time.h>
+#include "common.h"
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define TORBRECK_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
                                 S3C2410_UCON_RXILEVEL |        \
@@ -102,7 +104,7 @@ static struct i2c_board_info torbreck_i2c_devs2[] __initdata = {
 static void __init torbreck_map_io(void)
 {
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+        s5pv210_init_io(NULL, 0);
        s3c24xx_init_clocks(24000000);
        s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
        s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
@@ -127,7 +129,9 @@ MACHINE_START(TORBRECK, "TORBRECK")
        /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
        .atag_offset    = 0x100,
        .init_irq       = s5pv210_init_irq,
+        .handle_irq     = vic_handle_irq,
        .map_io         = torbreck_map_io,
        .init_machine   = torbreck_machine_init,
        .timer          = &s5p_timer,
+        .restart        = s5pv210_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index f149d278377..677c71c41e5 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -133,7 +133,7 @@ static void s5pv210_pm_prepare(void)
        s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
 }
-static int s5pv210_pm_add(struct sys_device *sysdev)
+static int s5pv210_pm_add(struct device *dev)
 {
        pm_cpu_prep = s5pv210_pm_prepare;
        pm_cpu_sleep = s5pv210_cpu_suspend;
@@ -141,13 +141,15 @@ static int s5pv210_pm_add(struct sys_device *sysdev)
        return 0;
 }
-static struct sysdev_driver s5pv210_pm_driver = {
+static struct subsys_interface s5pv210_pm_interface = {
-        .add            = s5pv210_pm_add,
+        .name           = "s5pv210_pm",
+        .subsys         = &s5pv210_subsys,
+        .add_dev        = s5pv210_pm_add,
 };
 static __init int s5pv210_pm_drvinit(void)
 {
-        return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver);
+        return subsys_interface_register(&s5pv210_pm_interface);
 }
 arch_initcall(s5pv210_pm_drvinit);
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
deleted file mode 100644
index 6b8ccc4d35f..00000000000
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/setup-sdhci.c
- *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/types.h>
-/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
-char *s5pv210_hsmmc_clksrcs[4] = {
-        [0] = "hsmmc",          /* HCLK */
-        /* [1] = "hsmmc",       - duplicate HCLK entry */
-        [2] = "sclk_mmc",       /* mmc_bus */
-        /* [3] = NULL,          - reserved */
-};
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
new file mode 100644
index 00000000000..f43c5048a37
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -0,0 +1,51 @@
+/* linux/arch/arm/mach-s5pv210/setup-spi.c
+ *
+ * Copyright (C) 2011 Samsung Electronics Ltd.
+ *              http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+#ifdef CONFIG_S3C64XX_DEV_SPI0
+struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
+        .fifo_lvl_mask  = 0x1ff,
+        .rx_lvl_offset  = 15,
+        .high_speed     = 1,
+        .tx_st_done     = 25,
+};
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PV210_GPB(2), 2,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
+#ifdef CONFIG_S3C64XX_DEV_SPI1
+struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
+        .fifo_lvl_mask  = 0x7f,
+        .rx_lvl_offset  = 15,
+        .high_speed     = 1,
+        .tx_st_done     = 25,
+};
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+        s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
+        s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S5PV210_GPB(6), 2,
+                                S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+        return 0;
+}
+#endif
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 3dd133f1841..ebafe8aa895 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -202,6 +202,7 @@ static struct irda_platform_data assabet_irda_data = {
 static struct mcp_plat_data assabet_mcp_data = {
        .mccr0          = MCCR0_ADM,
        .sclk_rate      = 11981000,
+        .codec          = "ucb1x00",
 };
 static void __init assabet_init(void)
@@ -252,6 +253,17 @@ static void __init assabet_init(void)
        sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
                            ARRAY_SIZE(assabet_flash_resources));
        sa11x0_register_irda(&assabet_irda_data);
+        /*
+         * Setup the PPC unit correctly.
+         */
+        PPDR &= ~PPC_RXD4;
+        PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
+        PSDR |= PPC_RXD4;
+        PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+        PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+        ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
        sa11x0_register_mcp(&assabet_mcp_data);
 }
@@ -268,7 +280,7 @@ static void __init map_sa1100_gpio_regs( void )
        int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
        pmd_t *pmd;
-        pmd = pmd_offset(pgd_offset_k(virt), virt);
+        pmd = pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
        *pmd = __pmd(phys | prot);
        flush_pmd_entry(pmd);
 }
@@ -455,4 +467,5 @@ MACHINE_START(ASSABET, "Intel-Assabet")
 #ifdef CONFIG_SA1111
        .dma_zone_size  = SZ_1M,
 #endif
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index bda83e1ab07..b07a2c024cb 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -309,4 +309,5 @@ MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
 #ifdef CONFIG_SA1111
        .dma_zone_size  = SZ_1M,
 #endif
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 7f3da4b11ec..d12d0f48b1d 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -124,12 +124,23 @@ static void __init cerf_map_io(void)
 static struct mcp_plat_data cerf_mcp_data = {
        .mccr0          = MCCR0_ADM,
        .sclk_rate      = 11981000,
+        .codec          = "ucb1x00",
 };
 static void __init cerf_init(void)
 {
        platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices));
        sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1);
+        /*
+         * Setup the PPC unit correctly.
+         */
+        PPDR &= ~PPC_RXD4;
+        PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
+        PSDR |= PPC_RXD4;
+        PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+        PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
        sa11x0_register_mcp(&cerf_mcp_data);
 }
@@ -139,4 +150,5 @@ MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
        .init_irq       = cerf_init_irq,
        .timer          = &sa1100_timer,
        .init_machine   = cerf_init,
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index dab3c6347a8..d6df9f6c9f7 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -11,17 +11,39 @@
 #include <linux/clk.h>
 #include <linux/spinlock.h>
 #include <linux/mutex.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
 #include <mach/hardware.h>
-/*
+struct clkops {
- * Very simple clock implementation - we only have one clock to deal with.
+        void                    (*enable)(struct clk *);
- */
+        void                    (*disable)(struct clk *);
+        unsigned long           (*getrate)(struct clk *);
+};
 struct clk {
+        const struct clkops     *ops;
+        unsigned long           rate;
        unsigned int            enabled;
 };
-static void clk_gpio27_enable(void)
+#define INIT_CLKREG(_clk, _devname, _conname)           \
+        {                                               \
+                .clk            = _clk,                 \
+                .dev_id         = _devname,             \
+                .con_id         = _conname,             \
+        }
+#define DEFINE_CLK(_name, _ops, _rate)                  \
+struct clk clk_##_name = {                              \
+                .ops    = _ops,                         \
+                .rate   = _rate,                        \
+        }
+static DEFINE_SPINLOCK(clocks_lock);
+static void clk_gpio27_enable(struct clk *clk)
 {
        /*
         * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
@@ -32,38 +54,22 @@ static void clk_gpio27_enable(void)
        TUCR = TUCR_3_6864MHz;
 }
-static void clk_gpio27_disable(void)
+static void clk_gpio27_disable(struct clk *clk)
 {
        TUCR = 0;
        GPDR &= ~GPIO_32_768kHz;
        GAFR &= ~GPIO_32_768kHz;
 }
-static struct clk clk_gpio27;
-static DEFINE_SPINLOCK(clocks_lock);
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        const char *devname = dev_name(dev);
-        return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;
-}
-EXPORT_SYMBOL(clk_get);
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
 int clk_enable(struct clk *clk)
 {
        unsigned long flags;
        spin_lock_irqsave(&clocks_lock, flags);
        if (clk->enabled++ == 0)
-                clk_gpio27_enable();
+                clk->ops->enable(clk);
        spin_unlock_irqrestore(&clocks_lock, flags);
        return 0;
 }
 EXPORT_SYMBOL(clk_enable);
@@ -76,13 +82,48 @@ void clk_disable(struct clk *clk)
        spin_lock_irqsave(&clocks_lock, flags);
        if (--clk->enabled == 0)
-                clk_gpio27_disable();
+                clk->ops->disable(clk);
        spin_unlock_irqrestore(&clocks_lock, flags);
 }
 EXPORT_SYMBOL(clk_disable);
 unsigned long clk_get_rate(struct clk *clk)
 {
-        return 3686400;
+        unsigned long rate;
+        rate = clk->rate;
+        if (clk->ops->getrate)
+                rate = clk->ops->getrate(clk);
+        return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
+const struct clkops clk_gpio27_ops = {
+        .enable         = clk_gpio27_enable,
+        .disable        = clk_gpio27_disable,
+};
+static void clk_dummy_enable(struct clk *clk) { }
+static void clk_dummy_disable(struct clk *clk) { }
+const struct clkops clk_dummy_ops = {
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable,
+};
+static DEFINE_CLK(gpio27, &clk_gpio27_ops, 3686400);
+static DEFINE_CLK(dummy, &clk_dummy_ops, 0);
+static struct clk_lookup sa11xx_clkregs[] = {
+        INIT_CLKREG(&clk_gpio27, "sa1111.0", NULL),
+        INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
+};
+static int __init sa11xx_clk_init(void)
+{
+        clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
+        return 0;
+}
+postcore_initcall(sa11xx_clk_init);
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 2965cc9d424..c483912d08a 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -27,6 +27,7 @@
 #include <linux/timer.h>
 #include <linux/gpio.h>
 #include <linux/pda_power.h>
+#include <linux/mfd/ucb1x00.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -85,10 +86,15 @@ static struct scoop_pcmcia_config collie_pcmcia_config = {
        .num_devs       = 1,
 };
+static struct ucb1x00_plat_data collie_ucb1x00_data = {
+        .gpio_base      = COLLIE_TC35143_GPIO_BASE,
+};
 static struct mcp_plat_data collie_mcp_data = {
        .mccr0          = MCCR0_ADM | MCCR0_ExtClk,
        .sclk_rate      = 9216000,
-        .gpio_base      = COLLIE_TC35143_GPIO_BASE,
+        .codec          = "ucb1x00",
+        .codec_pdata    = &collie_ucb1x00_data,
 };
 /*
@@ -351,6 +357,16 @@ static void __init collie_init(void)
        sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
                            ARRAY_SIZE(collie_flash_resources));
+        /*
+         * Setup the PPC unit correctly.
+         */
+        PPDR &= ~PPC_RXD4;
+        PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
+        PSDR |= PPC_RXD4;
+        PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+        PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
        sa11x0_register_mcp(&collie_mcp_data);
        sharpsl_save_param();
@@ -387,4 +403,5 @@ MACHINE_START(COLLIE, "Sharp-Collie")
        .init_irq       = sa1100_init_irq,
        .timer          = &sa1100_timer,
        .init_machine   = collie_init,
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 5fa5ae1f39e..e3a28ca2a7b 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -126,6 +126,17 @@ static void sa1100_power_off(void)
        PMCR = PMCR_SF;
 }
+void sa11x0_restart(char mode, const char *cmd)
+{
+        if (mode == 's') {
+                /* Jump into ROM at address 0 */
+                soft_restart(0);
+        } else {
+                /* Use on-chip reset capability */
+                RSRR = RSRR_SWR;
+        }
+}
 static void sa11x0_register_device(struct platform_device *dev, void *data)
 {
        int err;
@@ -206,10 +217,15 @@ static struct platform_device sa11x0uart3_device = {
 static struct resource sa11x0mcp_resources[] = {
        [0] = {
                .start  = __PREG(Ser4MCCR0),
-                .end    = __PREG(Ser4MCCR0) + 0xffff,
+                .end    = __PREG(Ser4MCCR0) + 0x1C - 1,
                .flags  = IORESOURCE_MEM,
        },
        [1] = {
+                .start  = __PREG(Ser4MCCR1),
+                .end    = __PREG(Ser4MCCR1) + 0x4 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
                .start  = IRQ_Ser4MCP,
                .end    = IRQ_Ser4MCP,
                .flags  = IORESOURCE_IRQ,
@@ -334,9 +350,29 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
        sa11x0_register_device(&sa11x0ir_device, irda);
 }
+static struct resource sa11x0rtc_resources[] = {
+        [0] = {
+                .start  = 0x90010000,
+                .end    = 0x900100ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_RTC1Hz,
+                .end    = IRQ_RTC1Hz,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_RTCAlrm,
+                .end    = IRQ_RTCAlrm,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
 static struct platform_device sa11x0rtc_device = {
        .name           = "sa1100-rtc",
        .id             = -1,
+        .resource       = sa11x0rtc_resources,
+        .num_resources  = ARRAY_SIZE(sa11x0rtc_resources),
 };
 static struct platform_device *sa11x0_devices[] __initdata = {
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index b7a9a601c2d..33268cf6be3 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -10,6 +10,7 @@ extern struct sys_timer sa1100_timer;
 extern void __init sa1100_map_io(void);
 extern void __init sa1100_init_irq(void);
 extern void __init sa1100_init_gpio(void);
+extern void sa11x0_restart(char, const char *);
 #define SET_BANK(__nr,__start,__size) \
        mi->bank[__nr].start = (__start), \
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index b30733a2b82..1e6b3c105ba 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -89,5 +89,6 @@ MACHINE_START(H3100, "Compaq iPAQ H3100")
        .init_irq       = sa1100_init_irq,
        .timer          = &sa1100_timer,
        .init_machine   = h3100_mach_init,
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index 6fd324d9238..6b58e7460ec 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -130,5 +130,6 @@ MACHINE_START(H3600, "Compaq iPAQ H3600")
        .init_irq       = sa1100_init_irq,
        .timer          = &sa1100_timer,
        .init_machine   = h3600_mach_init,
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index 30f4a551b8e..c01bb36db94 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -200,4 +200,5 @@ MACHINE_START(HACKKIT, "HackKit Cpu Board")
        .init_irq       = sa1100_init_irq,
        .timer          = &sa1100_timer,
        .init_machine   = hackkit_init,
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h
index 703631887c9..a38fc4f5424 100644
--- a/arch/arm/mach-sa1100/include/mach/gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/gpio.h
@@ -51,7 +51,4 @@ static inline void gpio_set_value(unsigned gpio, int value)
 #define gpio_cansleep   __gpio_cansleep
-#define gpio_to_irq(gpio)       ((gpio < 11) ? (IRQ_GPIO0 + gpio) : \
-                                        (IRQ_GPIO11 - 11 + gpio))
 #endif
diff --git a/arch/arm/mach-sa1100/include/mach/mcp.h b/arch/arm/mach-sa1100/include/mach/mcp.h
index ed1a331508a..586cec898b3 100644
--- a/arch/arm/mach-sa1100/include/mach/mcp.h
+++ b/arch/arm/mach-sa1100/include/mach/mcp.h
@@ -17,6 +17,8 @@ struct mcp_plat_data {
        u32 mccr1;
        unsigned int sclk_rate;
        int gpio_base;
+        const char *codec;
+        void *codec_pdata;
 };
 #endif
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h
index ba9da9f7f18..e17b208f76d 100644
--- a/arch/arm/mach-sa1100/include/mach/system.h
+++ b/arch/arm/mach-sa1100/include/mach/system.h
@@ -3,20 +3,7 @@
 *
 * Copyright (c) 1999 Nicolas Pitre <nico@fluxnic.net>
 */
-#include <mach/hardware.h>
 static inline void arch_idle(void)
 {
        cpu_do_idle();
 }
-static inline void arch_reset(char mode, const char *cmd)
-{
-        if (mode == 's') {
-                /* Jump into ROM at address 0 */
-                cpu_reset(0);
-        } else {
-                /* Use on-chip reset capability */
-                RSRR = RSRR_SWR;
-        }
-}
diff --git a/arch/arm/mach-sa1100/include/mach/vmalloc.h b/arch/arm/mach-sa1100/include/mach/vmalloc.h
deleted file mode 100644
index b3d00239848..00000000000
--- a/arch/arm/mach-sa1100/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * arch/arm/mach-sa1100/include/mach/vmalloc.h
- */
-#define VMALLOC_END       (0xe8000000UL)
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index 77198fe02bc..ee121d6f048 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -373,4 +373,5 @@ MACHINE_START(JORNADA720, "HP Jornada 720")
 #ifdef CONFIG_SA1111
        .dma_zone_size  = SZ_1M,
 #endif
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 5bc59d0947b..d117ceab621 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -24,10 +24,20 @@
 static struct mcp_plat_data lart_mcp_data = {
        .mccr0          = MCCR0_ADM,
        .sclk_rate      = 11981000,
+        .codec          = "ucb1x00",
 };
 static void __init lart_init(void)
 {
+        /*
+         * Setup the PPC unit correctly.
+         */
+        PPDR &= ~PPC_RXD4;
+        PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
+        PSDR |= PPC_RXD4;
+        PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+        PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
        sa11x0_register_mcp(&lart_mcp_data);
 }
@@ -66,4 +76,5 @@ MACHINE_START(LART, "LART")
        .init_irq       = sa1100_init_irq,
        .init_machine   = lart_init,
        .timer          = &sa1100_timer,
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
index 032f3881d14..85f6ee67222 100644
--- a/arch/arm/mach-sa1100/nanoengine.c
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -19,6 +19,7 @@
 #include <asm/mach-types.h>
 #include <asm/setup.h>
+#include <asm/page.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/flash.h>
@@ -116,4 +117,5 @@ MACHINE_START(NANOENGINE, "BSE nanoEngine")
        .init_irq       = sa1100_init_irq,
        .timer          = &sa1100_timer,
        .init_machine   = nanoengine_init,
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index dd39fee5954..0d01ca78892 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -131,7 +131,8 @@ static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
 struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
 {
-        return pci_scan_bus(sys->busnr, &pci_nano_ops, sys);
+        return pci_scan_root_bus(NULL, sys->busnr, &pci_nano_ops, sys,
+                                 &sys->resources);
 }
 static struct resource pci_io_ports = {
@@ -226,7 +227,7 @@ static struct resource pci_prefetchable_memory = {
        .flags  = IORESOURCE_MEM  | IORESOURCE_PREFETCH,
 };
-static int __init pci_nanoengine_setup_resources(struct resource **resource)
+static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
 {
        if (request_resource(&ioport_resource, &pci_io_ports)) {
                printk(KERN_ERR "PCI: unable to allocate io port region\n");
@@ -243,9 +244,9 @@ static int __init pci_nanoengine_setup_resources(struct resource **resource)
                printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
                return -EBUSY;
        }
-        resource[0] = &pci_io_ports;
+        pci_add_resource(&sys->resources, &pci_io_ports);
-        resource[1] = &pci_non_prefetchable_memory;
+        pci_add_resource(&sys->resources, &pci_non_prefetchable_memory);
-        resource[2] = &pci_prefetchable_memory;
+        pci_add_resource(&sys->resources, &pci_prefetchable_memory);
        return 1;
 }
@@ -260,7 +261,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
        if (nr == 0) {
                sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
                sys->io_offset = 0x400;
-                ret = pci_nanoengine_setup_resources(sys->resource);
+                ret = pci_nanoengine_setup_resources(sys);
                /* Enable alternate memory bus master mode, see
                 * "Intel StrongARM SA1110 Developer's Manual",
                 * section 10.8, "Alternate Memory Bus Master Mode". */
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 65161f2bea2..9307df05353 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -150,4 +150,5 @@ MACHINE_START(PLEB, "PLEB")
        .init_irq       = sa1100_init_irq,
        .timer          = &sa1100_timer,
        .init_machine   = pleb_init,
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 1cccbf5b9e9..748d34435b3 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -55,11 +55,22 @@ static struct resource shannon_flash_resource = {
 static struct mcp_plat_data shannon_mcp_data = {
        .mccr0          = MCCR0_ADM,
        .sclk_rate      = 11981000,
+        .codec          = "ucb1x00",
 };
 static void __init shannon_init(void)
 {
        sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
+        /*
+         * Setup the PPC unit correctly.
+         */
+        PPDR &= ~PPC_RXD4;
+        PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
+        PSDR |= PPC_RXD4;
+        PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+        PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
        sa11x0_register_mcp(&shannon_mcp_data);
 }
@@ -87,4 +98,5 @@ MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
        .init_irq       = sa1100_init_irq,
        .timer          = &sa1100_timer,
        .init_machine   = shannon_init,
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 4790f3f3d00..458ececefa5 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -14,6 +14,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/mfd/ucb1x00.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
@@ -187,10 +188,15 @@ static struct resource simpad_flash_resources [] = {
        }
 };
+static struct ucb1x00_plat_data simpad_ucb1x00_data = {
+        .gpio_base      = SIMPAD_UCB1X00_GPIO_BASE,
+};
 static struct mcp_plat_data simpad_mcp_data = {
        .mccr0          = MCCR0_ADM,
        .sclk_rate      = 11981000,
-        .gpio_base      = SIMPAD_UCB1X00_GPIO_BASE,
+        .codec          = "ucb1300",
+        .codec_pdata    = &simpad_ucb1x00_data,
 };
@@ -378,6 +384,16 @@ static int __init simpad_init(void)
        sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
                              ARRAY_SIZE(simpad_flash_resources));
+        /*
+         * Setup the PPC unit correctly.
+         */
+        PPDR &= ~PPC_RXD4;
+        PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
+        PSDR |= PPC_RXD4;
+        PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
+        PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
        sa11x0_register_mcp(&simpad_mcp_data);
        ret = platform_add_devices(devices, ARRAY_SIZE(devices));
@@ -396,4 +412,5 @@ MACHINE_START(SIMPAD, "Simpad")
        .map_io         = simpad_map_io,
        .init_irq       = sa1100_init_irq,
        .timer          = &sa1100_timer,
+        .restart        = sa11x0_restart,
 MACHINE_END
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index fa6602491d5..69e33535dee 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -12,7 +12,6 @@
 #include <linux/errno.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <linux/sched.h>        /* just for sched_clock() - funny that */
 #include <linux/timex.h>
 #include <linux/clockchips.h>
@@ -20,29 +19,9 @@
 #include <asm/sched_clock.h>
 #include <mach/hardware.h>
-/*
+static u32 notrace sa1100_read_sched_clock(void)
- * This is the SA11x0 sched_clock implementation.
- */
-static DEFINE_CLOCK_DATA(cd);
-/*
- * Constants generated by clocks_calc_mult_shift(m, s, 3.6864MHz,
- * NSEC_PER_SEC, 60).
- * This gives a resolution of about 271ns and a wrap period of about 19min.
- */
-#define SC_MULT         2275555556u
-#define SC_SHIFT        23
-unsigned long long notrace sched_clock(void)
-{
-        u32 cyc = OSCR;
-        return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
-}
-static void notrace sa1100_update_sched_clock(void)
 {
-        u32 cyc = OSCR;
+        return OSCR;
-        update_sched_clock(&cd, cyc, (u32)~0);
 }
 #define MIN_OSCR_DELTA 2
@@ -109,8 +88,7 @@ static void __init sa1100_timer_init(void)
        OIER = 0;
        OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
-        init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32,
+        setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
-                               3686400, SC_MULT, SC_SHIFT);
        clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4);
        ckevt_sa1100_osmr0.max_delta_ns =
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index feda3ca7fc9..a851c254ad6 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -26,10 +26,9 @@
 #define ROMCARD_SIZE            0x08000000
 #define ROMCARD_START           0x10000000
-void arch_reset(char mode, const char *cmd)
+static void shark_restart(char mode, const char *cmd)
 {
        short temp;
-        local_irq_disable();
        /* Reset the Machine via pc[3] of the sequoia chipset */
        outw(0x09,0x24);
        temp=inw(0x26);
@@ -157,4 +156,5 @@ MACHINE_START(SHARK, "Shark")
        .init_irq       = shark_init_irq,
        .timer          = &shark_timer,
        .dma_zone_size  = SZ_4M,
+        .restart        = shark_restart,
 MACHINE_END
diff --git a/arch/arm/mach-shark/include/mach/system.h b/arch/arm/mach-shark/include/mach/system.h
index 21c373b30bb..1b2f2c5050a 100644
--- a/arch/arm/mach-shark/include/mach/system.h
+++ b/arch/arm/mach-shark/include/mach/system.h
@@ -6,9 +6,6 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
-/* Found in arch/mach-shark/core.c */
-extern void arch_reset(char mode, const char *cmd);
 static inline void arch_idle(void)
 {
 }
diff --git a/arch/arm/mach-shark/include/mach/vmalloc.h b/arch/arm/mach-shark/include/mach/vmalloc.h
deleted file mode 100644
index b10df988526..00000000000
--- a/arch/arm/mach-shark/include/mach/vmalloc.h
+++ /dev/null
@@ -1,4 +0,0 @@
-/*
- * arch/arm/mach-shark/include/mach/vmalloc.h
- */
-#define VMALLOC_END       0xd0000000UL
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0828fab2b65..060e5644c49 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -28,6 +28,19 @@ config ARCH_SH73A0
        select ARM_GIC
        select I2C
+config ARCH_R8A7740
+        bool "R-Mobile A1 (R8A77400)"
+        select CPU_V7
+        select SH_CLK_CPG
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+config ARCH_R8A7779
+        bool "R-Car H1 (R8A77790)"
+        select CPU_V7
+        select SH_CLK_CPG
+        select ARM_GIC
+        select ARCH_WANT_OPTIONAL_GPIOLIB
 comment "SH-Mobile Board Type"
 config MACH_G3EVM
@@ -75,6 +88,16 @@ config MACH_KOTA2
        select ARCH_REQUIRE_GPIOLIB
        depends on ARCH_SH73A0
+config MACH_BONITO
+        bool "bonito board"
+        select ARCH_REQUIRE_GPIOLIB
+        depends on ARCH_R8A7740
+config MACH_MARZEN
+        bool "MARZEN board"
+        depends on ARCH_R8A7779
+        select ARCH_REQUIRE_GPIOLIB
 comment "SH-Mobile System Configuration"
 menu "Memory configuration"
@@ -83,7 +106,7 @@ config MEMORY_START
        hex "Physical memory start address"
        default "0x50000000" if MACH_G3EVM
        default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
-                                MACH_MACKEREL
+                                MACH_MACKEREL || MACH_BONITO
        default "0x41000000" if MACH_KOTA2
        default "0x00000000"
        ---help---
@@ -95,7 +118,7 @@ config MEMORY_SIZE
        hex "Physical memory size"
        default "0x08000000" if MACH_G3EVM
        default "0x08000000" if MACH_G4EVM
-        default "0x20000000" if MACH_AG5EVM
+        default "0x20000000" if MACH_AG5EVM || MACH_BONITO
        default "0x1e000000" if MACH_KOTA2
        default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
        default "0x04000000"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 737bdc631b0..7ad6954c46c 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -10,12 +10,15 @@ obj-$(CONFIG_ARCH_SH7367)	+= setup-sh7367.o clock-sh7367.o intc-sh7367.o
 obj-$(CONFIG_ARCH_SH7377)       += setup-sh7377.o clock-sh7377.o intc-sh7377.o
 obj-$(CONFIG_ARCH_SH7372)       += setup-sh7372.o clock-sh7372.o intc-sh7372.o
 obj-$(CONFIG_ARCH_SH73A0)       += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
+obj-$(CONFIG_ARCH_R8A7740)      += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
+obj-$(CONFIG_ARCH_R8A7779)      += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
 # SMP objects
 smp-y                           := platsmp.o headsmp.o
 smp-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 smp-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
 smp-$(CONFIG_ARCH_SH73A0)       += smp-sh73a0.o
+smp-$(CONFIG_ARCH_R8A7779)      += smp-r8a7779.o
 # Pinmux setup
 pfc-y                           :=
@@ -23,17 +26,20 @@ pfc-$(CONFIG_ARCH_SH7367)	+= pfc-sh7367.o
 pfc-$(CONFIG_ARCH_SH7377)       += pfc-sh7377.o
 pfc-$(CONFIG_ARCH_SH7372)       += pfc-sh7372.o
 pfc-$(CONFIG_ARCH_SH73A0)       += pfc-sh73a0.o
+pfc-$(CONFIG_ARCH_R8A7740)      += pfc-r8a7740.o
+pfc-$(CONFIG_ARCH_R8A7779)      += pfc-r8a7779.o
 # IRQ objects
 obj-$(CONFIG_ARCH_SH7367)       += entry-intc.o
 obj-$(CONFIG_ARCH_SH7377)       += entry-intc.o
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
-obj-$(CONFIG_ARCH_SH73A0)       += entry-gic.o
+obj-$(CONFIG_ARCH_R8A7740)      += entry-intc.o
 # PM objects
 obj-$(CONFIG_SUSPEND)           += suspend.o
 obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 obj-$(CONFIG_ARCH_SH7372)       += pm-sh7372.o sleep-sh7372.o
+obj-$(CONFIG_ARCH_R8A7779)      += pm-r8a7779.o
 # Board objects
 obj-$(CONFIG_MACH_G3EVM)        += board-g3evm.o
@@ -42,6 +48,8 @@ obj-$(CONFIG_MACH_AP4EVB)	+= board-ap4evb.o
 obj-$(CONFIG_MACH_AG5EVM)       += board-ag5evm.o
 obj-$(CONFIG_MACH_MACKEREL)     += board-mackerel.o
 obj-$(CONFIG_MACH_KOTA2)        += board-kota2.o
+obj-$(CONFIG_MACH_BONITO)       += board-bonito.o
+obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
 # Framework support
 obj-$(CONFIG_SMP)               += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 7119b87cbfa..eff8a96c75e 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -271,7 +271,7 @@ static struct sh_mobile_lcdc_info lcdc0_info = {
                .flags = LCDC_FLAGS_DWPOL,
                .lcd_size_cfg.width = 44,
                .lcd_size_cfg.height = 79,
-                .bpp = 16,
+                .fourcc = V4L2_PIX_FMT_RGB565,
                .lcd_cfg = lcdc0_modes,
                .num_cfg = ARRAY_SIZE(lcdc0_modes),
                .board_cfg = {
@@ -321,12 +321,46 @@ static struct resource mipidsi0_resources[] = {
        },
 };
+#define DSI0PHYCR       0xe615006c
+static int sh_mipi_set_dot_clock(struct platform_device *pdev,
+                                 void __iomem *base,
+                                 int enable)
+{
+        struct clk *pck;
+        int ret;
+        pck = clk_get(&pdev->dev, "dsip_clk");
+        if (IS_ERR(pck)) {
+                ret = PTR_ERR(pck);
+                goto sh_mipi_set_dot_clock_pck_err;
+        }
+        if (enable) {
+                clk_set_rate(pck, clk_round_rate(pck,  24000000));
+                __raw_writel(0x2a809010, DSI0PHYCR);
+                clk_enable(pck);
+        } else {
+                clk_disable(pck);
+        }
+        ret = 0;
+        clk_put(pck);
+sh_mipi_set_dot_clock_pck_err:
+        return ret;
+}
 static struct sh_mipi_dsi_info mipidsi0_info = {
        .data_format    = MIPI_RGB888,
        .lcd_chan       = &lcdc0_info.ch[0],
+        .lane           = 2,
        .vsynw_offset   = 20,
        .clksrc         = 1,
-        .flags          = SH_MIPI_DSI_HSABM,
+        .flags          = SH_MIPI_DSI_HSABM             |
+                          SH_MIPI_DSI_SYNC_PULSES_MODE  |
+                          SH_MIPI_DSI_HSbyteCLK,
+        .set_dot_clock  = sh_mipi_set_dot_clock,
 };
 static struct platform_device mipidsi0_device = {
@@ -466,16 +500,12 @@ static struct map_desc ag5evm_io_desc[] __initdata = {
 static void __init ag5evm_map_io(void)
 {
        iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
-        /* DMA memory at 0xf6000000 - 0xffdfffff */
-        init_consistent_dma_size(158 << 20);
        /* setup early devices and console here as well */
        sh73a0_add_early_devices();
        shmobile_setup_console();
 }
-#define DSI0PHYCR       0xe615006c
 static void __init ag5evm_init(void)
 {
        sh73a0_pinmux_init();
@@ -556,9 +586,6 @@ static void __init ag5evm_init(void)
        gpio_direction_output(GPIO_PORT235, 0);
        lcd_backlight_reset();
-        /* MIPI-DSI clock setup */
-        __raw_writel(0x2a809010, DSI0PHYCR);
        /* enable SDHI0 on CN15 [SD I/F] */
        gpio_request(GPIO_FN_SDHICD0, NULL);
        gpio_request(GPIO_FN_SDHIWP0, NULL);
@@ -609,7 +636,7 @@ MACHINE_START(AG5EVM, "ag5evm")
        .map_io         = ag5evm_map_io,
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = sh73a0_init_irq,
-        .handle_irq     = shmobile_handle_irq_gic,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = ag5evm_init,
        .timer          = &ag5evm_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 4c865ece9ac..aab0a349f75 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -491,7 +491,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
        .meram_dev = &meram_info,
        .ch[0] = {
                .chan = LCDC_CHAN_MAINLCD,
-                .bpp = 16,
+                .fourcc = V4L2_PIX_FMT_RGB565,
                .lcd_cfg = ap4evb_lcdc_modes,
                .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
                .meram_cfg = &lcd_meram_cfg,
@@ -564,6 +564,30 @@ static struct platform_device keysc_device = {
 };
 /* MIPI-DSI */
+#define PHYCTRL         0x0070
+static int sh_mipi_set_dot_clock(struct platform_device *pdev,
+                                 void __iomem *base,
+                                 int enable)
+{
+        struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
+        void __iomem *phy =  base + PHYCTRL;
+        if (IS_ERR(pck))
+                return PTR_ERR(pck);
+        if (enable) {
+                clk_set_rate(pck, clk_round_rate(pck, 24000000));
+                iowrite32(ioread32(phy) | (0xb << 8), phy);
+                clk_enable(pck);
+        } else {
+                clk_disable(pck);
+        }
+        clk_put(pck);
+        return 0;
+}
 static struct resource mipidsi0_resources[] = {
        [0] = {
                .start  = 0xffc60000,
@@ -580,7 +604,11 @@ static struct resource mipidsi0_resources[] = {
 static struct sh_mipi_dsi_info mipidsi0_info = {
        .data_format    = MIPI_RGB888,
        .lcd_chan       = &lcdc_info.ch[0],
+        .lane           = 2,
        .vsynw_offset   = 17,
+        .flags          = SH_MIPI_DSI_SYNC_PULSES_MODE |
+                          SH_MIPI_DSI_HSbyteCLK,
+        .set_dot_clock  = sh_mipi_set_dot_clock,
 };
 static struct platform_device mipidsi0_device = {
@@ -762,9 +790,22 @@ static struct platform_device fsi_device = {
        },
 };
+static struct fsi_ak4642_info fsi2_ak4643_info = {
+        .name           = "AK4643",
+        .card           = "FSI2A-AK4643",
+        .cpu_dai        = "fsia-dai",
+        .codec          = "ak4642-codec.0-0013",
+        .platform       = "sh_fsi2",
+        .id             = FSI_PORT_A,
+};
 static struct platform_device fsi_ak4643_device = {
-        .name           = "sh_fsi2_a_ak4643",
+        .name   = "fsi-ak4642-audio",
+        .dev    = {
+                .platform_data  = &fsi_info,
+        },
 };
 static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
        .icb[0] = {
                .marker_icb     = 30,
@@ -785,7 +826,7 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
        .meram_dev = &meram_info,
        .ch[0] = {
                .chan = LCDC_CHAN_MAINLCD,
-                .bpp = 16,
+                .fourcc = V4L2_PIX_FMT_RGB565,
                .interface_type = RGB24,
                .clock_divider = 1,
                .flags = LCDC_FLAGS_DWPOL,
@@ -1172,8 +1213,6 @@ static struct map_desc ap4evb_io_desc[] __initdata = {
 static void __init ap4evb_map_io(void)
 {
        iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
-        /* DMA memory at 0xf6000000 - 0xffdfffff */
-        init_consistent_dma_size(158 << 20);
        /* setup early devices and console here as well */
        sh7372_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
new file mode 100644
index 00000000000..4d220162232
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -0,0 +1,522 @@
+/*
+ * bonito board support
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <mach/r8a7740.h>
+#include <video/sh_mobile_lcdc.h>
+/*
+ * CS   Address         device                  note
+ *----------------------------------------------------------------
+ * 0    0x0000_0000     NOR Flash (64MB)        SW12 : bit3 = OFF
+ * 2    0x0800_0000     ExtNOR (64MB)           SW12 : bit3 = OFF
+ * 4                    -
+ * 5A                   -
+ * 5B   0x1600_0000     SRAM (8MB)
+ * 6    0x1800_0000     FPGA (64K)
+ *      0x1801_0000     Ether (4KB)
+ *      0x1801_1000     USB (4KB)
+ */
+/*
+ * SW12
+ *
+ *      bit1                    bit2                    bit3
+ *----------------------------------------------------------------------------
+ * ON   NOR WriteProtect        NAND WriteProtect       CS0 ExtNOR / CS2 NOR
+ * OFF  NOR Not WriteProtect    NAND Not WriteProtect   CS0 NOR    / CS2 ExtNOR
+ */
+/*
+ * SCIFA5 (CN42)
+ *
+ * S38.3 = ON
+ * S39.6 = ON
+ * S43.1 = ON
+ */
+/*
+ * LCDC0 (CN3/CN4/CN7)
+ *
+ * S38.1 = OFF
+ * S38.2 = OFF
+ */
+/*
+ * FPGA
+ */
+#define IRQSR0          0x0020
+#define IRQSR1          0x0022
+#define IRQMR0          0x0030
+#define IRQMR1          0x0032
+#define BUSSWMR1        0x0070
+#define BUSSWMR2        0x0072
+#define BUSSWMR3        0x0074
+#define BUSSWMR4        0x0076
+#define LCDCR           0x10B4
+#define DEVRSTCR1       0x10D0
+#define DEVRSTCR2       0x10D2
+#define A1MDSR          0x10E0
+#define BVERR           0x1100
+/* FPGA IRQ */
+#define FPGA_IRQ_BASE           (512)
+#define FPGA_IRQ0               (FPGA_IRQ_BASE)
+#define FPGA_IRQ1               (FPGA_IRQ_BASE + 16)
+#define FPGA_ETH_IRQ            (FPGA_IRQ0 + 15)
+static u16 bonito_fpga_read(u32 offset)
+{
+        return __raw_readw(0xf0003000 + offset);
+}
+static void bonito_fpga_write(u32 offset, u16 val)
+{
+        __raw_writew(val, 0xf0003000 + offset);
+}
+static void bonito_fpga_irq_disable(struct irq_data *data)
+{
+        unsigned int irq = data->irq;
+        u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
+        int shift = irq % 16;
+        bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
+}
+static void bonito_fpga_irq_enable(struct irq_data *data)
+{
+        unsigned int irq = data->irq;
+        u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
+        int shift = irq % 16;
+        bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
+}
+static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
+        .name           = "bonito FPGA",
+        .irq_mask       = bonito_fpga_irq_disable,
+        .irq_unmask     = bonito_fpga_irq_enable,
+};
+static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+        u32 val =  bonito_fpga_read(IRQSR1) << 16 |
+                   bonito_fpga_read(IRQSR0);
+        u32 mask = bonito_fpga_read(IRQMR1) << 16 |
+                   bonito_fpga_read(IRQMR0);
+        int i;
+        val &= ~mask;
+        for (i = 0; i < 32; i++) {
+                if (!(val & (1 << i)))
+                        continue;
+                generic_handle_irq(FPGA_IRQ_BASE + i);
+        }
+}
+static void bonito_fpga_init(void)
+{
+        int i;
+        bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
+        bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
+        /* Device reset */
+        bonito_fpga_write(DEVRSTCR1,
+                   (1 << 2));   /* Eth */
+        /* FPGA irq require special handling */
+        for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
+                irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
+                                              handle_level_irq, "level");
+                set_irq_flags(i, IRQF_VALID); /* yuck */
+        }
+        irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
+        irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
+}
+/*
+* PMIC settings
+*
+* FIXME
+*
+* bonito board needs some settings by pmic which use i2c access.
+* pmic settings use device_initcall() here for use it.
+*/
+static __u8 *pmic_settings = NULL;
+static __u8 pmic_do_2A[] = {
+        0x1C, 0x09,
+        0x1A, 0x80,
+        0xff, 0xff,
+};
+static int __init pmic_init(void)
+{
+        struct i2c_adapter *a = i2c_get_adapter(0);
+        struct i2c_msg msg;
+        __u8 buf[2];
+        int i, ret;
+        if (!pmic_settings)
+                return 0;
+        if (!a)
+                return 0;
+        msg.addr        = 0x46;
+        msg.buf         = buf;
+        msg.len         = 2;
+        msg.flags       = 0;
+        for (i = 0; ; i += 2) {
+                buf[0] = pmic_settings[i + 0];
+                buf[1] = pmic_settings[i + 1];
+                if ((0xff == buf[0]) && (0xff == buf[1]))
+                        break;
+                ret = i2c_transfer(a, &msg, 1);
+                if (ret < 0) {
+                        pr_err("i2c transfer fail\n");
+                        break;
+                }
+        }
+        return 0;
+}
+device_initcall(pmic_init);
+/*
+ * LCDC0
+ */
+static const struct fb_videomode lcdc0_mode = {
+        .name           = "WVGA Panel",
+        .xres           = 800,
+        .yres           = 480,
+        .left_margin    = 88,
+        .right_margin   = 40,
+        .hsync_len      = 128,
+        .upper_margin   = 20,
+        .lower_margin   = 5,
+        .vsync_len      = 5,
+        .sync           = 0,
+};
+static struct sh_mobile_lcdc_info lcdc0_info = {
+        .clock_source   = LCDC_CLK_BUS,
+        .ch[0] = {
+                .chan                   = LCDC_CHAN_MAINLCD,
+                .bpp                    = 16,
+                .interface_type         = RGB24,
+                .clock_divider          = 5,
+                .flags                  = 0,
+                .lcd_cfg                = &lcdc0_mode,
+                .num_cfg                = 1,
+                .lcd_size_cfg = {
+                        .width  = 152,
+                        .height = 91,
+                },
+        },
+};
+static struct resource lcdc0_resources[] = {
+        [0] = {
+                .name   = "LCDC0",
+                .start  = 0xfe940000,
+                .end    = 0xfe943fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = intcs_evt2irq(0x0580),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device lcdc0_device = {
+        .name           = "sh_mobile_lcdc_fb",
+        .id             = 0,
+        .resource       = lcdc0_resources,
+        .num_resources  = ARRAY_SIZE(lcdc0_resources),
+        .dev    = {
+                .platform_data  = &lcdc0_info,
+                .coherent_dma_mask = ~0,
+        },
+};
+/*
+ * SMSC 9221
+ */
+static struct resource smsc_resources[] = {
+        [0] = {
+                .start          = 0x18010000,
+                .end            = 0x18011000 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = FPGA_ETH_IRQ,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct smsc911x_platform_config smsc_platdata = {
+        .flags          = SMSC911X_USE_16BIT,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+static struct platform_device smsc_device = {
+        .name           = "smsc911x",
+        .dev  = {
+                .platform_data = &smsc_platdata,
+        },
+        .resource       = smsc_resources,
+        .num_resources  = ARRAY_SIZE(smsc_resources),
+};
+/*
+ * core board devices
+ */
+static struct platform_device *bonito_core_devices[] __initdata = {
+};
+/*
+ * base board devices
+ */
+static struct platform_device *bonito_base_devices[] __initdata = {
+        &lcdc0_device,
+        &smsc_device,
+};
+/*
+ * map I/O
+ */
+static struct map_desc bonito_io_desc[] __initdata = {
+         /*
+          * for CPGA/INTC/PFC
+          * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
+          */
+        {
+                .virtual        = 0xe6000000,
+                .pfn            = __phys_to_pfn(0xe6000000),
+                .length         = 160 << 20,
+                .type           = MT_DEVICE_NONSHARED
+        },
+#ifdef CONFIG_CACHE_L2X0
+        /*
+         * for l2x0_init()
+         * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
+         */
+        {
+                .virtual        = 0xf0002000,
+                .pfn            = __phys_to_pfn(0xf0100000),
+                .length         = PAGE_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        },
+#endif
+        /*
+         * for FPGA (0x1800000-0x19ffffff)
+         * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
+         */
+        {
+                .virtual        = 0xf0003000,
+                .pfn            = __phys_to_pfn(0x18000000),
+                .length         = PAGE_SIZE * 2,
+                .type           = MT_DEVICE_NONSHARED
+        }
+};
+static void __init bonito_map_io(void)
+{
+        iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
+        /* setup early devices and console here as well */
+        r8a7740_add_early_devices();
+        shmobile_setup_console();
+}
+/*
+ * board init
+ */
+#define BIT_ON(sw, bit)         (sw & (1 << bit))
+#define BIT_OFF(sw, bit)        (!(sw & (1 << bit)))
+#define VCCQ1CR         0xE6058140
+#define VCCQ1LCDCR      0xE6058186
+static void __init bonito_init(void)
+{
+        u16 val;
+        r8a7740_pinmux_init();
+        bonito_fpga_init();
+        pmic_settings = pmic_do_2A;
+        /*
+         * core board settings
+         */
+#ifdef CONFIG_CACHE_L2X0
+        /* Early BRESP enable, Shared attribute override enable, 32K*8way */
+        l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
+#endif
+        r8a7740_add_standard_devices();
+        platform_add_devices(bonito_core_devices,
+                             ARRAY_SIZE(bonito_core_devices));
+        /*
+         * base board settings
+         */
+        gpio_request(GPIO_PORT176, NULL);
+        gpio_direction_input(GPIO_PORT176);
+        if (!gpio_get_value(GPIO_PORT176)) {
+                u16 bsw2;
+                u16 bsw3;
+                u16 bsw4;
+                /*
+                 * FPGA
+                 */
+                gpio_request(GPIO_FN_CS5B,              NULL);
+                gpio_request(GPIO_FN_CS6A,              NULL);
+                gpio_request(GPIO_FN_CS5A_PORT105,      NULL);
+                gpio_request(GPIO_FN_IRQ10,             NULL);
+                val = bonito_fpga_read(BVERR);
+                pr_info("bonito version: cpu %02x, base %02x\n",
+                        ((val >> 8) & 0xFF),
+                        ((val >> 0) & 0xFF));
+                bsw2 = bonito_fpga_read(BUSSWMR2);
+                bsw3 = bonito_fpga_read(BUSSWMR3);
+                bsw4 = bonito_fpga_read(BUSSWMR4);
+                /*
+                 * SCIFA5 (CN42)
+                 */
+                if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
+                    BIT_OFF(bsw3, 9) && /* S39.6 = ON */
+                    BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
+                        gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
+                        gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
+                }
+                /*
+                 * LCDC0 (CN3)
+                 */
+                if (BIT_ON(bsw2, 3) &&  /* S38.1 = OFF */
+                    BIT_ON(bsw2, 2)) {  /* S38.2 = OFF */
+                        gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
+                        gpio_request(GPIO_FN_LCD0_D0,           NULL);
+                        gpio_request(GPIO_FN_LCD0_D1,           NULL);
+                        gpio_request(GPIO_FN_LCD0_D2,           NULL);
+                        gpio_request(GPIO_FN_LCD0_D3,           NULL);
+                        gpio_request(GPIO_FN_LCD0_D4,           NULL);
+                        gpio_request(GPIO_FN_LCD0_D5,           NULL);
+                        gpio_request(GPIO_FN_LCD0_D6,           NULL);
+                        gpio_request(GPIO_FN_LCD0_D7,           NULL);
+                        gpio_request(GPIO_FN_LCD0_D8,           NULL);
+                        gpio_request(GPIO_FN_LCD0_D9,           NULL);
+                        gpio_request(GPIO_FN_LCD0_D10,          NULL);
+                        gpio_request(GPIO_FN_LCD0_D11,          NULL);
+                        gpio_request(GPIO_FN_LCD0_D12,          NULL);
+                        gpio_request(GPIO_FN_LCD0_D13,          NULL);
+                        gpio_request(GPIO_FN_LCD0_D14,          NULL);
+                        gpio_request(GPIO_FN_LCD0_D15,          NULL);
+                        gpio_request(GPIO_FN_LCD0_D16,          NULL);
+                        gpio_request(GPIO_FN_LCD0_D17,          NULL);
+                        gpio_request(GPIO_FN_LCD0_D18_PORT163,  NULL);
+                        gpio_request(GPIO_FN_LCD0_D19_PORT162,  NULL);
+                        gpio_request(GPIO_FN_LCD0_D20_PORT161,  NULL);
+                        gpio_request(GPIO_FN_LCD0_D21_PORT158,  NULL);
+                        gpio_request(GPIO_FN_LCD0_D22_PORT160,  NULL);
+                        gpio_request(GPIO_FN_LCD0_D23_PORT159,  NULL);
+                        gpio_request(GPIO_FN_LCD0_DCK,          NULL);
+                        gpio_request(GPIO_FN_LCD0_VSYN,         NULL);
+                        gpio_request(GPIO_FN_LCD0_HSYN,         NULL);
+                        gpio_request(GPIO_FN_LCD0_DISP,         NULL);
+                        gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
+                        gpio_request(GPIO_PORT61, NULL); /* LCDDON */
+                        gpio_direction_output(GPIO_PORT61, 1);
+                        /* backlight on */
+                        bonito_fpga_write(LCDCR, 1);
+                        /*  drivability Max */
+                        __raw_writew(0x00FF , VCCQ1LCDCR);
+                        __raw_writew(0xFFFF , VCCQ1CR);
+                }
+                platform_add_devices(bonito_base_devices,
+                                     ARRAY_SIZE(bonito_base_devices));
+        }
+}
+static void __init bonito_timer_init(void)
+{
+        u16 val;
+        u8 md_ck = 0;
+        /* read MD_CK value */
+        val = bonito_fpga_read(A1MDSR);
+        if (val & (1 << 10))
+                md_ck |= MD_CK2;
+        if (val & (1 << 9))
+                md_ck |= MD_CK1;
+        if (val & (1 << 8))
+                md_ck |= MD_CK0;
+        r8a7740_clock_init(md_ck);
+        shmobile_timer.init();
+}
+struct sys_timer bonito_timer = {
+        .init   = bonito_timer_init,
+};
+MACHINE_START(BONITO, "bonito")
+        .map_io         = bonito_map_io,
+        .init_irq       = r8a7740_init_irq,
+        .handle_irq     = shmobile_handle_irq_intc,
+        .init_machine   = bonito_init,
+        .timer          = &bonito_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index 8b620bf0622..72d557281b1 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -261,8 +261,6 @@ static struct map_desc g3evm_io_desc[] __initdata = {
 static void __init g3evm_map_io(void)
 {
        iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
-        /* DMA memory at 0xf6000000 - 0xffdfffff */
-        init_consistent_dma_size(158 << 20);
        /* setup early devices and console here as well */
        sh7367_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index 7719ddc5f59..2220b885cff 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -275,8 +275,6 @@ static struct map_desc g4evm_io_desc[] __initdata = {
 static void __init g4evm_map_io(void)
 {
        iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
-        /* DMA memory at 0xf6000000 - 0xffdfffff */
-        init_consistent_dma_size(158 << 20);
        /* setup early devices and console here as well */
        sh7377_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index f44150b5ae4..857ceeec1bb 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -551,7 +551,7 @@ MACHINE_START(KOTA2, "kota2")
        .map_io         = kota2_map_io,
        .nr_irqs        = NR_IRQS_LEGACY,
        .init_irq       = sh73a0_init_irq,
-        .handle_irq     = shmobile_handle_irq_gic,
+        .handle_irq     = gic_handle_irq,
        .init_machine   = kota2_init,
        .timer          = &kota2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 9c5e598e0e3..9b42fbd10f8 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -388,7 +388,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
        .clock_source = LCDC_CLK_BUS,
        .ch[0] = {
                .chan = LCDC_CHAN_MAINLCD,
-                .bpp = 16,
+                .fourcc = V4L2_PIX_FMT_RGB565,
                .lcd_cfg = mackerel_lcdc_modes,
                .num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
                .interface_type         = RGB24,
@@ -451,7 +451,7 @@ static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
        .clock_source = LCDC_CLK_EXTERNAL,
        .ch[0] = {
                .chan = LCDC_CHAN_MAINLCD,
-                .bpp = 16,
+                .fourcc = V4L2_PIX_FMT_RGB565,
                .interface_type = RGB24,
                .clock_divider = 1,
                .flags = LCDC_FLAGS_DWPOL,
@@ -990,8 +990,20 @@ static struct platform_device fsi_device = {
        },
 };
+static struct fsi_ak4642_info fsi2_ak4643_info = {
+        .name           = "AK4643",
+        .card           = "FSI2A-AK4643",
+        .cpu_dai        = "fsia-dai",
+        .codec          = "ak4642-codec.0-0013",
+        .platform       = "sh_fsi2",
+        .id             = FSI_PORT_A,
+};
 static struct platform_device fsi_ak4643_device = {
-        .name           = "sh_fsi2_a_ak4643",
+        .name   = "fsi-ak4642-audio",
+        .dev    = {
+                .platform_data  = &fsi2_ak4643_info,
+        },
 };
 /*
@@ -1390,8 +1402,6 @@ static struct map_desc mackerel_io_desc[] __initdata = {
 static void __init mackerel_map_io(void)
 {
        iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
-        /* DMA memory at 0xf6000000 - 0xffdfffff */
-        init_consistent_dma_size(158 << 20);
        /* setup early devices and console here as well */
        sh7372_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
new file mode 100644
index 00000000000..f0e02c0ce99
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -0,0 +1,157 @@
+/*
+ * marzen board support
+ *
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/dma-mapping.h>
+#include <linux/smsc911x.h>
+#include <mach/hardware.h>
+#include <mach/r8a7779.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
+#include <asm/traps.h>
+/* SMSC LAN89218 */
+static struct resource smsc911x_resources[] = {
+        [0] = {
+                .start          = 0x18000000, /* ExCS0 */
+                .end            = 0x180000ff, /* A1->A7 */
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = gic_spi(28), /* IRQ 1 */
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+static struct smsc911x_platform_config smsc911x_platdata = {
+        .flags          = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+static struct platform_device eth_device = {
+        .name           = "smsc911x",
+        .id             = 0,
+        .dev  = {
+                .platform_data = &smsc911x_platdata,
+        },
+        .resource       = smsc911x_resources,
+        .num_resources  = ARRAY_SIZE(smsc911x_resources),
+};
+static struct platform_device *marzen_devices[] __initdata = {
+        &eth_device,
+};
+static struct map_desc marzen_io_desc[] __initdata = {
+        /* 2M entity map for 0xf0000000 (MPCORE) */
+        {
+                .virtual        = 0xf0000000,
+                .pfn            = __phys_to_pfn(0xf0000000),
+                .length         = SZ_2M,
+                .type           = MT_DEVICE_NONSHARED
+        },
+        /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
+        {
+                .virtual        = 0xfe000000,
+                .pfn            = __phys_to_pfn(0xfe000000),
+                .length         = SZ_16M,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+static void __init marzen_map_io(void)
+{
+        iotable_init(marzen_io_desc, ARRAY_SIZE(marzen_io_desc));
+}
+static void __init marzen_init_early(void)
+{
+        r8a7779_add_early_devices();
+        /* Early serial console setup is not included here due to
+         * memory map collisions. The SCIF serial ports in r8a7779
+         * are difficult to entity map 1:1 due to collision with the
+         * virtual memory range used by the coherent DMA code on ARM.
+         *
+         * Anyone wanting to debug early can remove UPF_IOREMAP from
+         * the sh-sci serial console platform data, adjust mapbase
+         * to a static M:N virt:phys mapping that needs to be added to
+         * the mappings passed with iotable_init() above.
+         *
+         * Then add a call to shmobile_setup_console() from this function.
+         *
+         * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
+         * command line.
+         */
+}
+static void __init marzen_init(void)
+{
+        r8a7779_pinmux_init();
+        /* SCIF2 (CN18: DEBUG0) */
+        gpio_request(GPIO_FN_TX2_C, NULL);
+        gpio_request(GPIO_FN_RX2_C, NULL);
+        /* SCIF4 (CN19: DEBUG1) */
+        gpio_request(GPIO_FN_TX4, NULL);
+        gpio_request(GPIO_FN_RX4, NULL);
+        /* LAN89218 */
+        gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
+        gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
+        r8a7779_add_standard_devices();
+        platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
+}
+static void __init marzen_timer_init(void)
+{
+        r8a7779_clock_init();
+        shmobile_timer.init();
+        return;
+}
+struct sys_timer marzen_timer = {
+        .init   = marzen_timer_init,
+};
+MACHINE_START(MARZEN, "marzen")
+        .map_io         = marzen_map_io,
+        .init_early     = marzen_init_early,
+        .nr_irqs        = NR_IRQS_LEGACY,
+        .init_irq       = r8a7779_init_irq,
+        .handle_irq     = gic_handle_irq,
+        .init_machine   = marzen_init,
+        .timer          = &marzen_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
new file mode 100644
index 00000000000..3b35b9afc00
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -0,0 +1,382 @@
+/*
+ * R8A7740 processor support
+ *
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+#include <mach/r8a7740.h>
+/*
+ *        |  MDx  |  XTAL1/EXTAL1   |  System   | EXTALR |
+ *  Clock |-------+-----------------+  clock    | 32.768 |   RCLK
+ *  Mode  | 2/1/0 | src         MHz |  source   |  KHz   |  source
+ * -------+-------+-----------------+-----------+--------+----------
+ *    0   | 0 0 0 | External  20~50 | XTAL1     |    O   |  EXTALR
+ *    1   | 0 0 1 | Crystal   20~30 | XTAL1     |    O   |  EXTALR
+ *    2   | 0 1 0 | External  40~50 | XTAL1 / 2 |    O   |  EXTALR
+ *    3   | 0 1 1 | Crystal   40~50 | XTAL1 / 2 |    O   |  EXTALR
+ *    4   | 1 0 0 | External  20~50 | XTAL1     |    x   |  XTAL1 / 1024
+ *    5   | 1 0 1 | Crystal   20~30 | XTAL1     |    x   |  XTAL1 / 1024
+ *    6   | 1 1 0 | External  40~50 | XTAL1 / 2 |    x   |  XTAL1 / 2048
+ *    7   | 1 1 1 | Crystal   40~50 | XTAL1 / 2 |    x   |  XTAL1 / 2048
+ */
+/* CPG registers */
+#define FRQCRA          0xe6150000
+#define FRQCRB          0xe6150004
+#define FRQCRC          0xe61500e0
+#define PLLC01CR        0xe6150028
+#define SUBCKCR         0xe6150080
+#define MSTPSR0         0xe6150030
+#define MSTPSR1         0xe6150038
+#define MSTPSR2         0xe6150040
+#define MSTPSR3         0xe6150048
+#define MSTPSR4         0xe615004c
+#define SMSTPCR0        0xe6150130
+#define SMSTPCR1        0xe6150134
+#define SMSTPCR2        0xe6150138
+#define SMSTPCR3        0xe615013c
+#define SMSTPCR4        0xe6150140
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk extalr_clk = {
+        .rate   = 32768,
+};
+/*
+ * 25MHz default rate for the EXTAL1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+static struct clk extal1_clk = {
+        .rate   = 25000000,
+};
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+static struct clk extal2_clk = {
+        .rate   = 48000000,
+};
+/*
+ * 27MHz default rate for the DV_CLKI root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+static struct clk dv_clk = {
+        .rate   = 27000000,
+};
+static unsigned long div_recalc(struct clk *clk)
+{
+        return clk->parent->rate / (int)(clk->priv);
+}
+static struct clk_ops div_clk_ops = {
+        .recalc = div_recalc,
+};
+/* extal1 / 2 */
+static struct clk extal1_div2_clk = {
+        .ops    = &div_clk_ops,
+        .priv   = (void *)2,
+        .parent = &extal1_clk,
+};
+/* extal1 / 1024 */
+static struct clk extal1_div1024_clk = {
+        .ops    = &div_clk_ops,
+        .priv   = (void *)1024,
+        .parent = &extal1_clk,
+};
+/* extal1 / 2 / 1024 */
+static struct clk extal1_div2048_clk = {
+        .ops    = &div_clk_ops,
+        .priv   = (void *)1024,
+        .parent = &extal1_div2_clk,
+};
+/* extal2 / 2 */
+static struct clk extal2_div2_clk = {
+        .ops    = &div_clk_ops,
+        .priv   = (void *)2,
+        .parent = &extal2_clk,
+};
+static struct clk_ops followparent_clk_ops = {
+        .recalc = followparent_recalc,
+};
+/* Main clock */
+static struct clk system_clk = {
+        .ops    = &followparent_clk_ops,
+};
+static struct clk system_div2_clk = {
+        .ops    = &div_clk_ops,
+        .priv   = (void *)2,
+        .parent = &system_clk,
+};
+/* r_clk */
+static struct clk r_clk = {
+        .ops    = &followparent_clk_ops,
+};
+/* PLLC0/PLLC1 */
+static unsigned long pllc01_recalc(struct clk *clk)
+{
+        unsigned long mult = 1;
+        if (__raw_readl(PLLC01CR) & (1 << 14))
+                mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
+        return clk->parent->rate * mult;
+}
+static struct clk_ops pllc01_clk_ops = {
+        .recalc         = pllc01_recalc,
+};
+static struct clk pllc0_clk = {
+        .ops            = &pllc01_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &system_clk,
+        .enable_reg     = (void __iomem *)FRQCRC,
+};
+static struct clk pllc1_clk = {
+        .ops            = &pllc01_clk_ops,
+        .flags          = CLK_ENABLE_ON_INIT,
+        .parent         = &system_div2_clk,
+        .enable_reg     = (void __iomem *)FRQCRA,
+};
+/* PLLC1 / 2 */
+static struct clk pllc1_div2_clk = {
+        .ops            = &div_clk_ops,
+        .priv           = (void *)2,
+        .parent         = &pllc1_clk,
+};
+struct clk *main_clks[] = {
+        &extalr_clk,
+        &extal1_clk,
+        &extal2_clk,
+        &extal1_div2_clk,
+        &extal1_div1024_clk,
+        &extal1_div2048_clk,
+        &extal2_div2_clk,
+        &dv_clk,
+        &system_clk,
+        &system_div2_clk,
+        &r_clk,
+        &pllc0_clk,
+        &pllc1_clk,
+        &pllc1_div2_clk,
+};
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+        /* set KICK bit in FRQCRB to update hardware setting */
+        value = __raw_readl(FRQCRB);
+        value |= (1 << 31);
+        __raw_writel(value, FRQCRB);
+}
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+                          24, 32, 36, 48, 0, 72, 96, 0 };
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick = div4_kick,
+};
+enum {
+        DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
+        DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
+        DIV4_NR
+};
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_ZG]       = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_B]        = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  8, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_M1]       = SH_CLK_DIV4(&pllc1_clk, FRQCRA,  4, 0x6fff, CLK_ENABLE_ON_INIT),
+        [DIV4_HP]       = SH_CLK_DIV4(&pllc1_clk, FRQCRB,  4, 0x6fff, 0),
+        [DIV4_HPP]      = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
+        [DIV4_S]        = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
+        [DIV4_ZB]       = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  8, 0x6fff, 0),
+        [DIV4_M3]       = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  4, 0x6fff, 0),
+        [DIV4_CP]       = SH_CLK_DIV4(&pllc1_clk, FRQCRC,  0, 0x6fff, 0),
+};
+enum {
+        DIV6_SUB,
+        DIV6_NR
+};
+static struct clk div6_clks[DIV6_NR] = {
+        [DIV6_SUB]      = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
+};
+enum {
+        MSTP125,
+        MSTP116, MSTP111, MSTP100, MSTP117,
+        MSTP230,
+        MSTP222,
+        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+        MSTP329, MSTP323,
+        MSTP_NR
+};
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
+        [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   SMSTPCR1, 17, 0), /* LCDC1 */
+        [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
+        [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B],   SMSTPCR1,  0, 0), /* LCDC0 */
+        [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
+        [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
+        [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  7, 0), /* SCIFA5 */
+        [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  6, 0), /* SCIFB */
+        [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  4, 0), /* SCIFA0 */
+        [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  3, 0), /* SCIFA1 */
+        [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  2, 0), /* SCIFA2 */
+        [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  1, 0), /* SCIFA3 */
+        [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2,  0, 0), /* SCIFA4 */
+        [MSTP329] = SH_CLK_MSTP32(&r_clk,               SMSTPCR3, 29, 0), /* CMT10 */
+        [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
+};
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("extalr",                 &extalr_clk),
+        CLKDEV_CON_ID("extal1",                 &extal1_clk),
+        CLKDEV_CON_ID("extal2",                 &extal2_clk),
+        CLKDEV_CON_ID("extal1_div2",            &extal1_div2_clk),
+        CLKDEV_CON_ID("extal1_div1024",         &extal1_div1024_clk),
+        CLKDEV_CON_ID("extal1_div2048",         &extal1_div2048_clk),
+        CLKDEV_CON_ID("extal2_div2",            &extal2_div2_clk),
+        CLKDEV_CON_ID("dv_clk",                 &dv_clk),
+        CLKDEV_CON_ID("system_clk",             &system_clk),
+        CLKDEV_CON_ID("system_div2_clk",        &system_div2_clk),
+        CLKDEV_CON_ID("r_clk",                  &r_clk),
+        CLKDEV_CON_ID("pllc0_clk",              &pllc0_clk),
+        CLKDEV_CON_ID("pllc1_clk",              &pllc1_clk),
+        CLKDEV_CON_ID("pllc1_div2_clk",         &pllc1_div2_clk),
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("i_clk",                  &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("zg_clk",                 &div4_clks[DIV4_ZG]),
+        CLKDEV_CON_ID("b_clk",                  &div4_clks[DIV4_B]),
+        CLKDEV_CON_ID("m1_clk",                 &div4_clks[DIV4_M1]),
+        CLKDEV_CON_ID("hp_clk",                 &div4_clks[DIV4_HP]),
+        CLKDEV_CON_ID("hpp_clk",                &div4_clks[DIV4_HPP]),
+        CLKDEV_CON_ID("s_clk",                  &div4_clks[DIV4_S]),
+        CLKDEV_CON_ID("zb_clk",                 &div4_clks[DIV4_ZB]),
+        CLKDEV_CON_ID("m3_clk",                 &div4_clks[DIV4_M3]),
+        CLKDEV_CON_ID("cp_clk",                 &div4_clks[DIV4_CP]),
+        /* DIV6 clocks */
+        CLKDEV_CON_ID("sub_clk",                &div6_clks[DIV6_SUB]),
+        /* MSTP32 clocks */
+        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0",    &mstp_clks[MSTP100]),
+        CLKDEV_DEV_ID("sh_tmu.1",               &mstp_clks[MSTP111]),
+        CLKDEV_DEV_ID("i2c-sh_mobile.0",        &mstp_clks[MSTP116]),
+        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",    &mstp_clks[MSTP117]),
+        CLKDEV_DEV_ID("sh_tmu.0",               &mstp_clks[MSTP125]),
+        CLKDEV_DEV_ID("sh-sci.4",               &mstp_clks[MSTP200]),
+        CLKDEV_DEV_ID("sh-sci.3",               &mstp_clks[MSTP201]),
+        CLKDEV_DEV_ID("sh-sci.2",               &mstp_clks[MSTP202]),
+        CLKDEV_DEV_ID("sh-sci.1",               &mstp_clks[MSTP203]),
+        CLKDEV_DEV_ID("sh-sci.0",               &mstp_clks[MSTP204]),
+        CLKDEV_DEV_ID("sh-sci.8",               &mstp_clks[MSTP206]),
+        CLKDEV_DEV_ID("sh-sci.5",               &mstp_clks[MSTP207]),
+        CLKDEV_DEV_ID("sh-sci.7",               &mstp_clks[MSTP222]),
+        CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
+        CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
+        CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
+};
+void __init r8a7740_clock_init(u8 md_ck)
+{
+        int k, ret = 0;
+        /* detect system clock parent */
+        if (md_ck & MD_CK1)
+                system_clk.parent = &extal1_div2_clk;
+        else
+                system_clk.parent = &extal1_clk;
+        /* detect RCLK parent */
+        switch (md_ck & (MD_CK2 | MD_CK1)) {
+        case MD_CK2 | MD_CK1:
+                r_clk.parent = &extal1_div2048_clk;
+                break;
+        case MD_CK2:
+                r_clk.parent = &extal1_div1024_clk;
+                break;
+        case MD_CK1:
+        default:
+                r_clk.parent = &extalr_clk;
+                break;
+        }
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+        if (!ret)
+                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+        if (!ret)
+                clk_init();
+        else
+                panic("failed to setup r8a7740 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
new file mode 100644
index 00000000000..b4b0e8cd096
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -0,0 +1,176 @@
+/*
+ * r8a7779 clock framework support
+ *
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+#define FRQMR   0xffc80014
+#define MSTPCR0 0xffc80030
+#define MSTPCR1 0xffc80034
+#define MSTPCR3 0xffc8003c
+#define MSTPSR1 0xffc80044
+#define MSTPSR4 0xffc80048
+#define MSTPSR6 0xffc8004c
+#define MSTPCR4 0xffc80050
+#define MSTPCR5 0xffc80054
+#define MSTPCR6 0xffc80058
+#define MSTPCR7 0xffc80040
+/* ioremap() through clock mapping mandatory to avoid
+ * collision with ARM coherent DMA virtual memory range.
+ */
+static struct clk_mapping cpg_mapping = {
+        .phys   = 0xffc80000,
+        .len    = 0x80,
+};
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk plla_clk = {
+        .rate           = 1500000000,
+        .mapping        = &cpg_mapping,
+};
+static struct clk *main_clks[] = {
+        &plla_clk,
+};
+static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 };
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = divisors,
+        .nr_divisors = ARRAY_SIZE(divisors),
+};
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
+static struct clk div4_clks[DIV4_NR] = {
+        [DIV4_S]        = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
+                                      0x0018, CLK_ENABLE_ON_INIT),
+        [DIV4_OUT]      = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
+                                      0x0700, CLK_ENABLE_ON_INIT),
+        [DIV4_S4]       = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
+                                      0x0040, CLK_ENABLE_ON_INIT),
+        [DIV4_S3]       = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
+                                      0x0010, CLK_ENABLE_ON_INIT),
+        [DIV4_S1]       = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
+                                      0x0060, CLK_ENABLE_ON_INIT),
+        [DIV4_P]        = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
+                                      0x0300, CLK_ENABLE_ON_INIT),
+};
+enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+        MSTP016, MSTP015, MSTP014,
+        MSTP_NR };
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
+        [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
+        [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
+        [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */
+        [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */
+        [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */
+        [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
+        [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
+        [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
+};
+static unsigned long mul4_recalc(struct clk *clk)
+{
+        return clk->parent->rate * 4;
+}
+static struct clk_ops mul4_clk_ops = {
+        .recalc         = mul4_recalc,
+};
+struct clk clkz_clk = {
+        .ops            = &mul4_clk_ops,
+        .parent         = &div4_clks[DIV4_S],
+};
+struct clk clkzs_clk = {
+        /* clks x 4 / 4 = clks */
+        .parent         = &div4_clks[DIV4_S],
+};
+static struct clk *late_main_clks[] = {
+        &clkz_clk,
+        &clkzs_clk,
+};
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("plla_clk", &plla_clk),
+        CLKDEV_CON_ID("clkz_clk", &clkz_clk),
+        CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("shyway_clk",     &div4_clks[DIV4_S]),
+        CLKDEV_CON_ID("bus_clk",        &div4_clks[DIV4_OUT]),
+        CLKDEV_CON_ID("shyway4_clk",    &div4_clks[DIV4_S4]),
+        CLKDEV_CON_ID("shyway3_clk",    &div4_clks[DIV4_S3]),
+        CLKDEV_CON_ID("shyway1_clk",    &div4_clks[DIV4_S1]),
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+        /* MSTP32 clocks */
+        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
+        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
+        CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
+        CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
+        CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
+        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
+        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
+        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+};
+void __init r8a7779_clock_init(void)
+{
+        int k, ret = 0;
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+        for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
+                ret = clk_register(late_main_clks[k]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+        if (!ret)
+                clk_init();
+        else
+                panic("failed to setup r8a7779 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 995a9c3aec8..293456d8dcf 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -411,11 +411,11 @@ static struct clk *fsibckcr_parent[] = {
 };
 static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
-        [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
+        [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
                                      hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
-        [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
+        [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
                                      fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
-        [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
+        [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
                                      fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
 };
@@ -612,8 +612,8 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
-        CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
-        CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
+        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
        /* MSTP32 clocks */
        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 1370a89ca35..afbead6a6e1 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -92,6 +92,24 @@ static struct clk_ops div2_clk_ops = {
        .recalc         = div2_recalc,
 };
+static unsigned long div7_recalc(struct clk *clk)
+{
+        return clk->parent->rate / 7;
+}
+static struct clk_ops div7_clk_ops = {
+        .recalc         = div7_recalc,
+};
+static unsigned long div13_recalc(struct clk *clk)
+{
+        return clk->parent->rate / 13;
+}
+static struct clk_ops div13_clk_ops = {
+        .recalc         = div13_recalc,
+};
 /* Divide extal1 by two */
 static struct clk extal1_div2_clk = {
        .ops            = &div2_clk_ops,
@@ -174,12 +192,29 @@ static struct clk pll3_clk = {
        .enable_bit     = 3,
 };
-/* Divide PLL1 by two */
+/* Divide PLL */
 static struct clk pll1_div2_clk = {
        .ops            = &div2_clk_ops,
        .parent         = &pll1_clk,
 };
+static struct clk pll1_div7_clk = {
+        .ops            = &div7_clk_ops,
+        .parent         = &pll1_clk,
+};
+static struct clk pll1_div13_clk = {
+        .ops            = &div13_clk_ops,
+        .parent         = &pll1_clk,
+};
+/* External input clock */
+struct clk sh73a0_extcki_clk = {
+};
+struct clk sh73a0_extalr_clk = {
+};
 static struct clk *main_clks[] = {
        &r_clk,
        &sh73a0_extal1_clk,
@@ -193,6 +228,10 @@ static struct clk *main_clks[] = {
        &pll2_clk,
        &pll3_clk,
        &pll1_div2_clk,
+        &pll1_div7_clk,
+        &pll1_div13_clk,
+        &sh73a0_extcki_clk,
+        &sh73a0_extalr_clk,
 };
 static void div4_kick(struct clk *clk)
@@ -246,27 +285,84 @@ enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
        DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
        DIV6_NR };
+static struct clk *vck_parent[8] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2_clk,
+        [2] = &sh73a0_extcki_clk,
+        [3] = &sh73a0_extal2_clk,
+        [4] = &main_div2_clk,
+        [5] = &sh73a0_extalr_clk,
+        [6] = &main_clk,
+};
+static struct clk *pll_parent[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2_clk,
+        [2] = &pll1_div13_clk,
+};
+static struct clk *hsi_parent[4] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2_clk,
+        [2] = &pll1_div7_clk,
+};
+static struct clk *pll_extal2_parent[] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2_clk,
+        [2] = &sh73a0_extal2_clk,
+        [3] = &sh73a0_extal2_clk,
+};
+static struct clk *dsi_parent[8] = {
+        [0] = &pll1_div2_clk,
+        [1] = &pll2_clk,
+        [2] = &main_clk,
+        [3] = &sh73a0_extal2_clk,
+        [4] = &sh73a0_extcki_clk,
+};
 static struct clk div6_clks[DIV6_NR] = {
-        [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
+        [DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
-        [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
+                        vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
-        [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
+        [DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
-        [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, CLK_ENABLE_ON_INIT),
+                        vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
-        [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
+        [DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
-        [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
+                        vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
-        [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
+        [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
-        [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
+                        pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
-        [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
+        [DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
-        [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
+                        pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
-        [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
+        [DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
-        [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
+                        pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
-        [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
+        [DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
-        [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
+                        pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
-        [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
+        [DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
-        [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
+                        pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
-        [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
+        [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
-        [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
+                        pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
-        [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
+        [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
-        [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
+                        pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
+        [DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
+                        pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
+        [DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
+                        pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
+        [DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
+                        pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
+        [DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
+                        pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
+        [DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
+                        hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2),
+        [DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
+                        pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
+        [DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
+                        pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
+        [DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
+                        pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
+        [DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
+                        dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
+        [DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,
+                        dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
 };
 enum { MSTP001,
@@ -331,8 +427,8 @@ static struct clk_lookup lookups[] = {
        CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
-        CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
-        CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
+        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
        /* MSTP32 clocks */
        CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
@@ -403,7 +499,7 @@ void __init sh73a0_clock_init(void)
                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
        if (!ret)
-                ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+                ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
        if (!ret)
                ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
diff --git a/arch/arm/mach-shmobile/entry-gic.S b/arch/arm/mach-shmobile/entry-gic.S
deleted file mode 100644
index e20239b08c8..00000000000
--- a/arch/arm/mach-shmobile/entry-gic.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * ARM Interrupt demux handler using GIC
- *
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2011 Paul Mundt
- * Copyright (C) 2010 - 2011 Renesas Solutions Corp.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <asm/assembler.h>
-#include <asm/entry-macro-multi.S>
-#include <asm/hardware/gic.h>
-#include <asm/hardware/entry-macro-gic.S>
-        arch_irq_handler shmobile_handle_irq_gic
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 26079d933d9..6ac015c8920 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -14,7 +14,7 @@
 #include <linux/init.h>
 #include <asm/memory.h>
-        __INIT
+        __CPUINIT
 /*
 * Reset vector for secondary CPUs.
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
index 238a0d97d2d..828d22f3af5 100644
--- a/arch/arm/mach-shmobile/hotplug.c
+++ b/arch/arm/mach-shmobile/hotplug.c
@@ -12,14 +12,43 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
 #include <linux/smp.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
+#include <mach/common.h>
+#include <asm/cacheflush.h>
+static cpumask_t dead_cpus;
 int platform_cpu_kill(unsigned int cpu)
 {
-        return 1;
+        int k;
+        /* this function is running on another CPU than the offline target,
+         * here we need wait for shutdown code in platform_cpu_die() to
+         * finish before asking SoC-specific code to power off the CPU core.
+         */
+        for (k = 0; k < 1000; k++) {
+                if (cpumask_test_cpu(cpu, &dead_cpus))
+                        return shmobile_platform_cpu_kill(cpu);
+                mdelay(1);
+        }
+        return 0;
 }
 void platform_cpu_die(unsigned int cpu)
 {
+        /* hardware shutdown code running on the CPU that is being offlined */
+        flush_cache_all();
+        dsb();
+        /* notify platform_cpu_kill() that hardware shutdown is finished */
+        cpumask_set_cpu(cpu, &dead_cpus);
+        /* wait for SoC code in platform_cpu_kill() to shut off CPU core
+         * power. CPU bring up starts from the reset vector.
+         */
        while (1) {
                /*
                 * here's the WFI
@@ -33,6 +62,7 @@ void platform_cpu_die(unsigned int cpu)
 int platform_cpu_disable(unsigned int cpu)
 {
+        cpumask_clear_cpu(cpu, &dead_cpus);
        /*
         * we don't allow CPU 0 to be shutdown (it is still too special
         * e.g. clock tick interrupts)
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 834bd6cd508..e4b945e271e 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -4,10 +4,10 @@
 extern struct sys_timer shmobile_timer;
 extern void shmobile_setup_console(void);
 extern void shmobile_secondary_vector(void);
+extern int shmobile_platform_cpu_kill(unsigned int cpu);
 struct clk;
 extern int clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
-extern void shmobile_handle_irq_gic(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
 struct cpuidle_driver;
 extern void (*shmobile_cpuidle_modes[])(void);
@@ -35,8 +35,8 @@ extern void sh7372_add_standard_devices(void);
 extern void sh7372_clock_init(void);
 extern void sh7372_pinmux_init(void);
 extern void sh7372_pm_init(void);
-extern void sh7372_resume_core_standby_a3sm(void);
+extern void sh7372_resume_core_standby_sysc(void);
-extern int sh7372_do_idle_a3sm(unsigned long unused);
+extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
 extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
@@ -47,10 +47,31 @@ extern void sh73a0_clock_init(void);
 extern void sh73a0_pinmux_init(void);
 extern struct clk sh73a0_extal1_clk;
 extern struct clk sh73a0_extal2_clk;
+extern struct clk sh73a0_extcki_clk;
+extern struct clk sh73a0_extalr_clk;
 extern unsigned int sh73a0_get_core_count(void);
 extern void sh73a0_secondary_init(unsigned int cpu);
 extern int sh73a0_boot_secondary(unsigned int cpu);
 extern void sh73a0_smp_prepare_cpus(void);
+extern void r8a7740_init_irq(void);
+extern void r8a7740_add_early_devices(void);
+extern void r8a7740_add_standard_devices(void);
+extern void r8a7740_clock_init(u8 md_ck);
+extern void r8a7740_pinmux_init(void);
+extern void r8a7779_init_irq(void);
+extern void r8a7779_add_early_devices(void);
+extern void r8a7779_add_standard_devices(void);
+extern void r8a7779_clock_init(void);
+extern void r8a7779_pinmux_init(void);
+extern void r8a7779_pm_init(void);
+extern unsigned int r8a7779_get_core_count(void);
+extern int r8a7779_platform_cpu_kill(unsigned int cpu);
+extern void r8a7779_secondary_init(unsigned int cpu);
+extern int r8a7779_boot_secondary(unsigned int cpu);
+extern void r8a7779_smp_prepare_cpus(void);
 #endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index 8d4a416d428..2a57b2964ee 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -18,14 +18,5 @@
        .macro  disable_fiq
        .endm
-        .macro  get_irqnr_preamble, base, tmp
-        .endm
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        .endm
-        .macro  test_for_ipi, irqnr, irqstat, base, tmp
-        .endm
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h
index 7bf0890e16b..de795b42232 100644
--- a/arch/arm/mach-shmobile/include/mach/gpio.h
+++ b/arch/arm/mach-shmobile/include/mach/gpio.h
@@ -12,8 +12,6 @@
 #include <linux/kernel.h>
 #include <linux/errno.h>
-#define ARCH_NR_GPIOS 1024
 #include <linux/sh_pfc.h>
 #ifdef CONFIG_GPIOLIB
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
new file mode 100644
index 00000000000..9d447abb969
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -0,0 +1,584 @@
+/*
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#ifndef __ASM_R8A7740_H__
+#define __ASM_R8A7740_H__
+/*
+ * MD_CKx pin
+ */
+#define MD_CK2  (1 << 2)
+#define MD_CK1  (1 << 1)
+#define MD_CK0  (1 << 0)
+/*
+ * Pin Function Controller:
+ *      GPIO_FN_xx - GPIO used to select pin function
+ *      GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+        /* PORT */
+        GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+        GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+        GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+        GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+        GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+        GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+        GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+        GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+        GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+        GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+        GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+        GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+        GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+        GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+        GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+        GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+        GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+        GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+        GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+        GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+        GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+        GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+        GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+        GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
+        GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
+        GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
+        GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+        GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+        GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+        GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+        GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+        GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+        GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+        GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
+        GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
+        GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
+        GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
+        GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
+        GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+        GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+        GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+        GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+        GPIO_PORT210, GPIO_PORT211,
+        /* IRQ */
+        GPIO_FN_IRQ0_PORT2,     GPIO_FN_IRQ0_PORT13,
+        GPIO_FN_IRQ1,
+        GPIO_FN_IRQ2_PORT11,    GPIO_FN_IRQ2_PORT12,
+        GPIO_FN_IRQ3_PORT10,    GPIO_FN_IRQ3_PORT14,
+        GPIO_FN_IRQ4_PORT15,    GPIO_FN_IRQ4_PORT172,
+        GPIO_FN_IRQ5_PORT0,     GPIO_FN_IRQ5_PORT1,
+        GPIO_FN_IRQ6_PORT121,   GPIO_FN_IRQ6_PORT173,
+        GPIO_FN_IRQ7_PORT120,   GPIO_FN_IRQ7_PORT209,
+        GPIO_FN_IRQ8,
+        GPIO_FN_IRQ9_PORT118,   GPIO_FN_IRQ9_PORT210,
+        GPIO_FN_IRQ10,
+        GPIO_FN_IRQ11,
+        GPIO_FN_IRQ12_PORT42,   GPIO_FN_IRQ12_PORT97,
+        GPIO_FN_IRQ13_PORT64,   GPIO_FN_IRQ13_PORT98,
+        GPIO_FN_IRQ14_PORT63,   GPIO_FN_IRQ14_PORT99,
+        GPIO_FN_IRQ15_PORT62,   GPIO_FN_IRQ15_PORT100,
+        GPIO_FN_IRQ16_PORT68,   GPIO_FN_IRQ16_PORT211,
+        GPIO_FN_IRQ17,
+        GPIO_FN_IRQ18,
+        GPIO_FN_IRQ19,
+        GPIO_FN_IRQ20,
+        GPIO_FN_IRQ21,
+        GPIO_FN_IRQ22,
+        GPIO_FN_IRQ23,
+        GPIO_FN_IRQ24,
+        GPIO_FN_IRQ25,
+        GPIO_FN_IRQ26_PORT58,   GPIO_FN_IRQ26_PORT81,
+        GPIO_FN_IRQ27_PORT57,   GPIO_FN_IRQ27_PORT168,
+        GPIO_FN_IRQ28_PORT56,   GPIO_FN_IRQ28_PORT169,
+        GPIO_FN_IRQ29_PORT50,   GPIO_FN_IRQ29_PORT170,
+        GPIO_FN_IRQ30_PORT49,   GPIO_FN_IRQ30_PORT171,
+        GPIO_FN_IRQ31_PORT41,   GPIO_FN_IRQ31_PORT167,
+        /* Function */
+        /* DBGT */
+        GPIO_FN_DBGMDT2,        GPIO_FN_DBGMDT1,        GPIO_FN_DBGMDT0,
+        GPIO_FN_DBGMD10,        GPIO_FN_DBGMD11,        GPIO_FN_DBGMD20,
+        GPIO_FN_DBGMD21,
+        /* FSI */
+        GPIO_FN_FSIAISLD_PORT0,         /* FSIAISLD Port 0/5 */
+        GPIO_FN_FSIAISLD_PORT5,
+        GPIO_FN_FSIASPDIF_PORT9,        /* FSIASPDIF Port 9/18 */
+        GPIO_FN_FSIASPDIF_PORT18,
+        GPIO_FN_FSIAOSLD1,      GPIO_FN_FSIAOSLD2,
+        GPIO_FN_FSIAOLR,        GPIO_FN_FSIAOBT,
+        GPIO_FN_FSIAOSLD,       GPIO_FN_FSIAOMC,
+        GPIO_FN_FSIACK,         GPIO_FN_FSIAILR,
+        GPIO_FN_FSIAIBT,
+        /* FMSI */
+        GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
+        GPIO_FN_FMSISLD_PORT6,
+        GPIO_FN_FMSIILR,        GPIO_FN_FMSIIBT,
+        GPIO_FN_FMSIOLR,        GPIO_FN_FMSIOBT,
+        GPIO_FN_FMSICK,         GPIO_FN_FMSOILR,
+        GPIO_FN_FMSOIBT,        GPIO_FN_FMSOOLR,
+        GPIO_FN_FMSOOBT,        GPIO_FN_FMSOSLD,
+        GPIO_FN_FMSOCK,
+        /* SCIFA0 */
+        GPIO_FN_SCIFA0_SCK,     GPIO_FN_SCIFA0_CTS,
+        GPIO_FN_SCIFA0_RTS,     GPIO_FN_SCIFA0_RXD,
+        GPIO_FN_SCIFA0_TXD,
+        /* SCIFA1 */
+        GPIO_FN_SCIFA1_CTS,     GPIO_FN_SCIFA1_SCK,
+        GPIO_FN_SCIFA1_RXD,     GPIO_FN_SCIFA1_TXD,
+        GPIO_FN_SCIFA1_RTS,
+        /* SCIFA2 */
+        GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
+        GPIO_FN_SCIFA2_SCK_PORT199,
+        GPIO_FN_SCIFA2_RXD,     GPIO_FN_SCIFA2_TXD,
+        GPIO_FN_SCIFA2_CTS,     GPIO_FN_SCIFA2_RTS,
+        /* SCIFA3 */
+        GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
+        GPIO_FN_SCIFA3_SCK_PORT116,
+        GPIO_FN_SCIFA3_CTS_PORT117,
+        GPIO_FN_SCIFA3_RXD_PORT174,
+        GPIO_FN_SCIFA3_TXD_PORT175,
+        GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
+        GPIO_FN_SCIFA3_SCK_PORT158,
+        GPIO_FN_SCIFA3_CTS_PORT162,
+        GPIO_FN_SCIFA3_RXD_PORT159,
+        GPIO_FN_SCIFA3_TXD_PORT160,
+        /* SCIFA4 */
+        GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
+        GPIO_FN_SCIFA4_TXD_PORT13,
+        GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
+        GPIO_FN_SCIFA4_TXD_PORT203,
+        GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
+        GPIO_FN_SCIFA4_TXD_PORT93,
+        GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
+        GPIO_FN_SCIFA4_SCK_PORT205,
+        /* SCIFA5 */
+        GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
+        GPIO_FN_SCIFA5_RXD_PORT10,
+        GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
+        GPIO_FN_SCIFA5_TXD_PORT208,
+        GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
+        GPIO_FN_SCIFA5_RXD_PORT92,
+        GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
+        GPIO_FN_SCIFA5_SCK_PORT206,
+        /* SCIFA6 */
+        GPIO_FN_SCIFA6_SCK,     GPIO_FN_SCIFA6_RXD,     GPIO_FN_SCIFA6_TXD,
+        /* SCIFA7 */
+        GPIO_FN_SCIFA7_TXD,     GPIO_FN_SCIFA7_RXD,
+        /* SCIFAB */
+        GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
+        GPIO_FN_SCIFB_RXD_PORT191,
+        GPIO_FN_SCIFB_TXD_PORT192,
+        GPIO_FN_SCIFB_RTS_PORT186,
+        GPIO_FN_SCIFB_CTS_PORT187,
+        GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
+        GPIO_FN_SCIFB_RXD_PORT3,
+        GPIO_FN_SCIFB_TXD_PORT4,
+        GPIO_FN_SCIFB_RTS_PORT172,
+        GPIO_FN_SCIFB_CTS_PORT173,
+        /* LCD0 */
+        GPIO_FN_LCDC0_SELECT,
+        GPIO_FN_LCD0_D0,        GPIO_FN_LCD0_D1,        GPIO_FN_LCD0_D2,
+        GPIO_FN_LCD0_D3,        GPIO_FN_LCD0_D4,        GPIO_FN_LCD0_D5,
+        GPIO_FN_LCD0_D6,        GPIO_FN_LCD0_D7,        GPIO_FN_LCD0_D8,
+        GPIO_FN_LCD0_D9,        GPIO_FN_LCD0_D10,       GPIO_FN_LCD0_D11,
+        GPIO_FN_LCD0_D12,       GPIO_FN_LCD0_D13,       GPIO_FN_LCD0_D14,
+        GPIO_FN_LCD0_D15,       GPIO_FN_LCD0_D16,       GPIO_FN_LCD0_D17,
+        GPIO_FN_LCD0_DON,       GPIO_FN_LCD0_VCPWC,     GPIO_FN_LCD0_VEPWC,
+        GPIO_FN_LCD0_DCK,       GPIO_FN_LCD0_VSYN, /* for RGB */
+        GPIO_FN_LCD0_HSYN,      GPIO_FN_LCD0_DISP, /* for RGB */
+        GPIO_FN_LCD0_WR,        GPIO_FN_LCD0_RD, /* for SYS */
+        GPIO_FN_LCD0_CS,        GPIO_FN_LCD0_RS, /* for SYS */
+        GPIO_FN_LCD0_D18_PORT163,       GPIO_FN_LCD0_D19_PORT162,
+        GPIO_FN_LCD0_D20_PORT161,       GPIO_FN_LCD0_D21_PORT158,
+        GPIO_FN_LCD0_D22_PORT160,       GPIO_FN_LCD0_D23_PORT159,
+        GPIO_FN_LCD0_LCLK_PORT165,       /* MSEL5CR_6_1 */
+        GPIO_FN_LCD0_D18_PORT40,        GPIO_FN_LCD0_D19_PORT4,
+        GPIO_FN_LCD0_D20_PORT3,         GPIO_FN_LCD0_D21_PORT2,
+        GPIO_FN_LCD0_D22_PORT0,         GPIO_FN_LCD0_D23_PORT1,
+        GPIO_FN_LCD0_LCLK_PORT102,      /* MSEL5CR_6_0 */
+        /* LCD1 */
+        GPIO_FN_LCDC1_SELECT,
+        GPIO_FN_LCD1_D0,        GPIO_FN_LCD1_D1,        GPIO_FN_LCD1_D2,
+        GPIO_FN_LCD1_D3,        GPIO_FN_LCD1_D4,        GPIO_FN_LCD1_D5,
+        GPIO_FN_LCD1_D6,        GPIO_FN_LCD1_D7,        GPIO_FN_LCD1_D8,
+        GPIO_FN_LCD1_D9,        GPIO_FN_LCD1_D10,       GPIO_FN_LCD1_D11,
+        GPIO_FN_LCD1_D12,       GPIO_FN_LCD1_D13,       GPIO_FN_LCD1_D14,
+        GPIO_FN_LCD1_D15,       GPIO_FN_LCD1_D16,       GPIO_FN_LCD1_D17,
+        GPIO_FN_LCD1_D18,       GPIO_FN_LCD1_D19,       GPIO_FN_LCD1_D20,
+        GPIO_FN_LCD1_D21,       GPIO_FN_LCD1_D22,       GPIO_FN_LCD1_D23,
+        GPIO_FN_LCD1_DON,       GPIO_FN_LCD1_VCPWC,
+        GPIO_FN_LCD1_LCLK,      GPIO_FN_LCD1_VEPWC,
+        GPIO_FN_LCD1_DCK,       GPIO_FN_LCD1_VSYN, /* for RGB */
+        GPIO_FN_LCD1_HSYN,      GPIO_FN_LCD1_DISP, /* for RGB */
+        GPIO_FN_LCD1_WR,        GPIO_FN_LCD1_RD, /* for SYS */
+        GPIO_FN_LCD1_CS,        GPIO_FN_LCD1_RS, /* for SYS */
+        /* RSPI */
+        GPIO_FN_RSPI_SSL0_A,    GPIO_FN_RSPI_SSL1_A,
+        GPIO_FN_RSPI_SSL2_A,    GPIO_FN_RSPI_SSL3_A,
+        GPIO_FN_RSPI_MOSI_A,    GPIO_FN_RSPI_MISO_A,
+        GPIO_FN_RSPI_CK_A,
+        /* VIO CKO */
+        GPIO_FN_VIO_CKO1,
+        GPIO_FN_VIO_CKO2,
+        GPIO_FN_VIO_CKO_1,
+        GPIO_FN_VIO_CKO,
+        /* VIO0 */
+        GPIO_FN_VIO0_D0,        GPIO_FN_VIO0_D1,        GPIO_FN_VIO0_D2,
+        GPIO_FN_VIO0_D3,        GPIO_FN_VIO0_D4,        GPIO_FN_VIO0_D5,
+        GPIO_FN_VIO0_D6,        GPIO_FN_VIO0_D7,        GPIO_FN_VIO0_D8,
+        GPIO_FN_VIO0_D9,        GPIO_FN_VIO0_D10,       GPIO_FN_VIO0_D11,
+        GPIO_FN_VIO0_D12,       GPIO_FN_VIO0_VD,        GPIO_FN_VIO0_HD,
+        GPIO_FN_VIO0_CLK,       GPIO_FN_VIO0_FIELD,
+        GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
+        GPIO_FN_VIO0_D14_PORT25,
+        GPIO_FN_VIO0_D15_PORT24,
+        GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
+        GPIO_FN_VIO0_D14_PORT95,
+        GPIO_FN_VIO0_D15_PORT96,
+        /* VIO1 */
+        GPIO_FN_VIO1_D0,        GPIO_FN_VIO1_D1,        GPIO_FN_VIO1_D2,
+        GPIO_FN_VIO1_D3,        GPIO_FN_VIO1_D4,        GPIO_FN_VIO1_D5,
+        GPIO_FN_VIO1_D6,        GPIO_FN_VIO1_D7,        GPIO_FN_VIO1_VD,
+        GPIO_FN_VIO1_HD,        GPIO_FN_VIO1_CLK,       GPIO_FN_VIO1_FIELD,
+        /* TPU0 */
+        GPIO_FN_TPU0TO0,        GPIO_FN_TPU0TO1,
+        GPIO_FN_TPU0TO3,
+        GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
+        GPIO_FN_TPU0TO2_PORT202,
+        /* SSP1 0 */
+        GPIO_FN_STP0_IPD0,      GPIO_FN_STP0_IPD1,      GPIO_FN_STP0_IPD2,
+        GPIO_FN_STP0_IPD3,      GPIO_FN_STP0_IPD4,      GPIO_FN_STP0_IPD5,
+        GPIO_FN_STP0_IPD6,      GPIO_FN_STP0_IPD7,      GPIO_FN_STP0_IPEN,
+        GPIO_FN_STP0_IPCLK,     GPIO_FN_STP0_IPSYNC,
+        /* SSP1 1 */
+        GPIO_FN_STP1_IPD1,      GPIO_FN_STP1_IPD2,      GPIO_FN_STP1_IPD3,
+        GPIO_FN_STP1_IPD4,      GPIO_FN_STP1_IPD5,      GPIO_FN_STP1_IPD6,
+        GPIO_FN_STP1_IPD7,      GPIO_FN_STP1_IPCLK,     GPIO_FN_STP1_IPSYNC,
+        GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
+        GPIO_FN_STP1_IPEN_PORT187,
+        GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
+        GPIO_FN_STP1_IPEN_PORT193,
+        /* SIM */
+        GPIO_FN_SIM_RST,        GPIO_FN_SIM_CLK,
+        GPIO_FN_SIM_D_PORT22, /* SIM_D  Port 22/199 */
+        GPIO_FN_SIM_D_PORT199,
+        /* SDHI0 */
+        GPIO_FN_SDHI0_D0,       GPIO_FN_SDHI0_D1,       GPIO_FN_SDHI0_D2,
+        GPIO_FN_SDHI0_D3,       GPIO_FN_SDHI0_CD,       GPIO_FN_SDHI0_WP,
+        GPIO_FN_SDHI0_CMD,      GPIO_FN_SDHI0_CLK,
+        /* SDHI1 */
+        GPIO_FN_SDHI1_D0,       GPIO_FN_SDHI1_D1,       GPIO_FN_SDHI1_D2,
+        GPIO_FN_SDHI1_D3,       GPIO_FN_SDHI1_CD,       GPIO_FN_SDHI1_WP,
+        GPIO_FN_SDHI1_CMD,      GPIO_FN_SDHI1_CLK,
+        /* SDHI2 */
+        GPIO_FN_SDHI2_D0,       GPIO_FN_SDHI2_D1,       GPIO_FN_SDHI2_D2,
+        GPIO_FN_SDHI2_D3,       GPIO_FN_SDHI2_CLK,      GPIO_FN_SDHI2_CMD,
+        GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
+        GPIO_FN_SDHI2_WP_PORT25,
+        GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
+        GPIO_FN_SDHI2_CD_PORT202,
+        /* MSIOF2 */
+        GPIO_FN_MSIOF2_TXD,     GPIO_FN_MSIOF2_RXD,     GPIO_FN_MSIOF2_TSCK,
+        GPIO_FN_MSIOF2_SS2,     GPIO_FN_MSIOF2_TSYNC,   GPIO_FN_MSIOF2_SS1,
+        GPIO_FN_MSIOF2_MCK1,    GPIO_FN_MSIOF2_MCK0,    GPIO_FN_MSIOF2_RSYNC,
+        GPIO_FN_MSIOF2_RSCK,
+        /* KEYSC */
+        GPIO_FN_KEYIN4,         GPIO_FN_KEYIN5,
+        GPIO_FN_KEYIN6,         GPIO_FN_KEYIN7,
+        GPIO_FN_KEYOUT0,        GPIO_FN_KEYOUT1,        GPIO_FN_KEYOUT2,
+        GPIO_FN_KEYOUT3,        GPIO_FN_KEYOUT4,        GPIO_FN_KEYOUT5,
+        GPIO_FN_KEYOUT6,        GPIO_FN_KEYOUT7,
+        GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
+        GPIO_FN_KEYIN1_PORT44,
+        GPIO_FN_KEYIN2_PORT45,
+        GPIO_FN_KEYIN3_PORT46,
+        GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
+        GPIO_FN_KEYIN1_PORT57,
+        GPIO_FN_KEYIN2_PORT56,
+        GPIO_FN_KEYIN3_PORT55,
+        /* VOU */
+        GPIO_FN_DV_D0,  GPIO_FN_DV_D1,  GPIO_FN_DV_D2,  GPIO_FN_DV_D3,
+        GPIO_FN_DV_D4,  GPIO_FN_DV_D5,  GPIO_FN_DV_D6,  GPIO_FN_DV_D7,
+        GPIO_FN_DV_D8,  GPIO_FN_DV_D9,  GPIO_FN_DV_D10, GPIO_FN_DV_D11,
+        GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
+        GPIO_FN_DV_CLK,
+        GPIO_FN_DV_VSYNC,
+        GPIO_FN_DV_HSYNC,
+        /* MEMC */
+        GPIO_FN_MEMC_AD0,       GPIO_FN_MEMC_AD1,       GPIO_FN_MEMC_AD2,
+        GPIO_FN_MEMC_AD3,       GPIO_FN_MEMC_AD4,       GPIO_FN_MEMC_AD5,
+        GPIO_FN_MEMC_AD6,       GPIO_FN_MEMC_AD7,       GPIO_FN_MEMC_AD8,
+        GPIO_FN_MEMC_AD9,       GPIO_FN_MEMC_AD10,      GPIO_FN_MEMC_AD11,
+        GPIO_FN_MEMC_AD12,      GPIO_FN_MEMC_AD13,      GPIO_FN_MEMC_AD14,
+        GPIO_FN_MEMC_AD15,      GPIO_FN_MEMC_CS0,       GPIO_FN_MEMC_INT,
+        GPIO_FN_MEMC_NWE,       GPIO_FN_MEMC_NOE,
+        GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
+        GPIO_FN_MEMC_ADV,
+        GPIO_FN_MEMC_WAIT,
+        GPIO_FN_MEMC_BUSCLK,
+        GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
+        GPIO_FN_MEMC_DREQ0,
+        GPIO_FN_MEMC_DREQ1,
+        GPIO_FN_MEMC_A0,
+        /* MMC */
+        GPIO_FN_MMC0_D0_PORT68,         GPIO_FN_MMC0_D1_PORT69,
+        GPIO_FN_MMC0_D2_PORT70,         GPIO_FN_MMC0_D3_PORT71,
+        GPIO_FN_MMC0_D4_PORT72,         GPIO_FN_MMC0_D5_PORT73,
+        GPIO_FN_MMC0_D6_PORT74,         GPIO_FN_MMC0_D7_PORT75,
+        GPIO_FN_MMC0_CLK_PORT66,
+        GPIO_FN_MMC0_CMD_PORT67,        /* MSEL4CR_15_0 */
+        GPIO_FN_MMC1_D0_PORT149,        GPIO_FN_MMC1_D1_PORT148,
+        GPIO_FN_MMC1_D2_PORT147,        GPIO_FN_MMC1_D3_PORT146,
+        GPIO_FN_MMC1_D4_PORT145,        GPIO_FN_MMC1_D5_PORT144,
+        GPIO_FN_MMC1_D6_PORT143,        GPIO_FN_MMC1_D7_PORT142,
+        GPIO_FN_MMC1_CLK_PORT103,
+        GPIO_FN_MMC1_CMD_PORT104,       /* MSEL4CR_15_1 */
+        /* MSIOF0 */
+        GPIO_FN_MSIOF0_SS1,     GPIO_FN_MSIOF0_SS2,
+        GPIO_FN_MSIOF0_RXD,     GPIO_FN_MSIOF0_TXD,
+        GPIO_FN_MSIOF0_MCK0,    GPIO_FN_MSIOF0_MCK1,
+        GPIO_FN_MSIOF0_RSYNC,   GPIO_FN_MSIOF0_RSCK,
+        GPIO_FN_MSIOF0_TSCK,    GPIO_FN_MSIOF0_TSYNC,
+        /* MSIOF1 */
+        GPIO_FN_MSIOF1_RSCK,    GPIO_FN_MSIOF1_RSYNC,
+        GPIO_FN_MSIOF1_MCK0,    GPIO_FN_MSIOF1_MCK1,
+        GPIO_FN_MSIOF1_SS2_PORT116,     GPIO_FN_MSIOF1_SS1_PORT117,
+        GPIO_FN_MSIOF1_RXD_PORT118,     GPIO_FN_MSIOF1_TXD_PORT119,
+        GPIO_FN_MSIOF1_TSYNC_PORT120,
+        GPIO_FN_MSIOF1_TSCK_PORT121,    /* MSEL4CR_10_0 */
+        GPIO_FN_MSIOF1_SS1_PORT67,      GPIO_FN_MSIOF1_TSCK_PORT72,
+        GPIO_FN_MSIOF1_TSYNC_PORT73,    GPIO_FN_MSIOF1_TXD_PORT74,
+        GPIO_FN_MSIOF1_RXD_PORT75,
+        GPIO_FN_MSIOF1_SS2_PORT202,     /* MSEL4CR_10_1 */
+        /* GPIO */
+        GPIO_FN_GPO0,   GPIO_FN_GPI0,
+        GPIO_FN_GPO1,   GPIO_FN_GPI1,
+        /* USB0 */
+        GPIO_FN_USB0_OCI,       GPIO_FN_USB0_PPON,      GPIO_FN_VBUS,
+        /* USB1 */
+        GPIO_FN_USB1_OCI,       GPIO_FN_USB1_PPON,
+        /* BBIF1 */
+        GPIO_FN_BBIF1_RXD,      GPIO_FN_BBIF1_TXD,      GPIO_FN_BBIF1_TSYNC,
+        GPIO_FN_BBIF1_TSCK,     GPIO_FN_BBIF1_RSCK,     GPIO_FN_BBIF1_RSYNC,
+        GPIO_FN_BBIF1_FLOW,     GPIO_FN_BBIF1_RX_FLOW_N,
+        /* BBIF2 */
+        GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
+        GPIO_FN_BBIF2_RXD2_PORT60,
+        GPIO_FN_BBIF2_TSYNC2_PORT6,
+        GPIO_FN_BBIF2_TSCK2_PORT59,
+        GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
+        GPIO_FN_BBIF2_TXD2_PORT183,
+        GPIO_FN_BBIF2_TSCK2_PORT89,
+        GPIO_FN_BBIF2_TSYNC2_PORT184,
+        /* BSC / FLCTL / PCMCIA */
+        GPIO_FN_CS0,    GPIO_FN_CS2,    GPIO_FN_CS4,
+        GPIO_FN_CS5B,   GPIO_FN_CS6A,
+        GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
+        GPIO_FN_CS5A_PORT19,
+        GPIO_FN_IOIS16, /* ? */
+        GPIO_FN_A0,     GPIO_FN_A1,     GPIO_FN_A2,     GPIO_FN_A3,
+        GPIO_FN_A4_FOE,         /* share with FLCTL */
+        GPIO_FN_A5_FCDE,        /* share with FLCTL */
+        GPIO_FN_A6,     GPIO_FN_A7,     GPIO_FN_A8,     GPIO_FN_A9,
+        GPIO_FN_A10,    GPIO_FN_A11,    GPIO_FN_A12,    GPIO_FN_A13,
+        GPIO_FN_A14,    GPIO_FN_A15,    GPIO_FN_A16,    GPIO_FN_A17,
+        GPIO_FN_A18,    GPIO_FN_A19,    GPIO_FN_A20,    GPIO_FN_A21,
+        GPIO_FN_A22,    GPIO_FN_A23,    GPIO_FN_A24,    GPIO_FN_A25,
+        GPIO_FN_A26,
+        GPIO_FN_D0_NAF0,        GPIO_FN_D1_NAF1,        /* share with FLCTL */
+        GPIO_FN_D2_NAF2,        GPIO_FN_D3_NAF3,        /* share with FLCTL */
+        GPIO_FN_D4_NAF4,        GPIO_FN_D5_NAF5,        /* share with FLCTL */
+        GPIO_FN_D6_NAF6,        GPIO_FN_D7_NAF7,        /* share with FLCTL */
+        GPIO_FN_D8_NAF8,        GPIO_FN_D9_NAF9,        /* share with FLCTL */
+        GPIO_FN_D10_NAF10,      GPIO_FN_D11_NAF11,      /* share with FLCTL */
+        GPIO_FN_D12_NAF12,      GPIO_FN_D13_NAF13,      /* share with FLCTL */
+        GPIO_FN_D14_NAF14,      GPIO_FN_D15_NAF15,      /* share with FLCTL */
+        GPIO_FN_D16,    GPIO_FN_D17,    GPIO_FN_D18,    GPIO_FN_D19,
+        GPIO_FN_D20,    GPIO_FN_D21,    GPIO_FN_D22,    GPIO_FN_D23,
+        GPIO_FN_D24,    GPIO_FN_D25,    GPIO_FN_D26,    GPIO_FN_D27,
+        GPIO_FN_D28,    GPIO_FN_D29,    GPIO_FN_D30,    GPIO_FN_D31,
+        GPIO_FN_WE0_FWE,        /* share with FLCTL */
+        GPIO_FN_WE1,
+        GPIO_FN_WE2_ICIORD,     /* share with PCMCIA */
+        GPIO_FN_WE3_ICIOWR,     /* share with PCMCIA */
+        GPIO_FN_CKO,    GPIO_FN_BS,     GPIO_FN_RDWR,
+        GPIO_FN_RD_FSC,         /* share with FLCTL */
+        GPIO_FN_WAIT_PORT177,   /* WAIT Port 90/177 */
+        GPIO_FN_WAIT_PORT90,
+        GPIO_FN_FCE0,   GPIO_FN_FCE1,   GPIO_FN_FRB, /* FLCTL */
+        /* IRDA */
+        GPIO_FN_IRDA_FIRSEL,    GPIO_FN_IRDA_IN,        GPIO_FN_IRDA_OUT,
+        /* ATAPI */
+        GPIO_FN_IDE_D0,         GPIO_FN_IDE_D1,         GPIO_FN_IDE_D2,
+        GPIO_FN_IDE_D3,         GPIO_FN_IDE_D4,         GPIO_FN_IDE_D5,
+        GPIO_FN_IDE_D6,         GPIO_FN_IDE_D7,         GPIO_FN_IDE_D8,
+        GPIO_FN_IDE_D9,         GPIO_FN_IDE_D10,        GPIO_FN_IDE_D11,
+        GPIO_FN_IDE_D12,        GPIO_FN_IDE_D13,        GPIO_FN_IDE_D14,
+        GPIO_FN_IDE_D15,        GPIO_FN_IDE_A0,         GPIO_FN_IDE_A1,
+        GPIO_FN_IDE_A2,         GPIO_FN_IDE_CS0,        GPIO_FN_IDE_CS1,
+        GPIO_FN_IDE_IOWR,       GPIO_FN_IDE_IORD,       GPIO_FN_IDE_IORDY,
+        GPIO_FN_IDE_INT,        GPIO_FN_IDE_RST,        GPIO_FN_IDE_DIRECTION,
+        GPIO_FN_IDE_EXBUF_ENB,  GPIO_FN_IDE_IODACK,     GPIO_FN_IDE_IODREQ,
+        /* RMII */
+        GPIO_FN_RMII_CRS_DV,    GPIO_FN_RMII_RX_ER,     GPIO_FN_RMII_RXD0,
+        GPIO_FN_RMII_RXD1,      GPIO_FN_RMII_TX_EN,     GPIO_FN_RMII_TXD0,
+        GPIO_FN_RMII_MDC,       GPIO_FN_RMII_TXD1,      GPIO_FN_RMII_MDIO,
+        GPIO_FN_RMII_REF50CK,   /* for RMII */
+        GPIO_FN_RMII_REF125CK,  /* for GMII */
+        /* GEther */
+        GPIO_FN_ET_TX_CLK,      GPIO_FN_ET_TX_EN,       GPIO_FN_ET_ETXD0,
+        GPIO_FN_ET_ETXD1,       GPIO_FN_ET_ETXD2,       GPIO_FN_ET_ETXD3,
+        GPIO_FN_ET_ETXD4,       GPIO_FN_ET_ETXD5, /* for GEther */
+        GPIO_FN_ET_ETXD6,       GPIO_FN_ET_ETXD7, /* for GEther */
+        GPIO_FN_ET_COL,         GPIO_FN_ET_TX_ER,
+        GPIO_FN_ET_RX_CLK,      GPIO_FN_ET_RX_DV,
+        GPIO_FN_ET_ERXD0,       GPIO_FN_ET_ERXD1,
+        GPIO_FN_ET_ERXD2,       GPIO_FN_ET_ERXD3,
+        GPIO_FN_ET_ERXD4,       GPIO_FN_ET_ERXD5, /* for GEther */
+        GPIO_FN_ET_ERXD6,       GPIO_FN_ET_ERXD7, /* for GEther */
+        GPIO_FN_ET_RX_ER,       GPIO_FN_ET_CRS,
+        GPIO_FN_ET_MDC,         GPIO_FN_ET_MDIO,
+        GPIO_FN_ET_LINK,        GPIO_FN_ET_PHY_INT,
+        GPIO_FN_ET_WOL,         GPIO_FN_ET_GTX_CLK,
+        /* DMA0 */
+        GPIO_FN_DREQ0,          GPIO_FN_DACK0,
+        /* DMA1 */
+        GPIO_FN_DREQ1,          GPIO_FN_DACK1,
+        /* SYSC */
+        GPIO_FN_RESETOUTS,
+        GPIO_FN_RESETP_PULLUP,
+        GPIO_FN_RESETP_PLAIN,
+        /* SDENC */
+        GPIO_FN_SDENC_CPG,
+        GPIO_FN_SDENC_DV_CLKI,
+        /* IRREM */
+        GPIO_FN_IROUT,
+        /* DEBUG */
+        GPIO_FN_EDEBGREQ_PULLDOWN,
+        GPIO_FN_EDEBGREQ_PULLUP,
+        GPIO_FN_TRACEAUD_FROM_VIO,
+        GPIO_FN_TRACEAUD_FROM_LCDC0,
+        GPIO_FN_TRACEAUD_FROM_MEMC,
+};
+#endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
new file mode 100644
index 00000000000..b07ad318eb2
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -0,0 +1,363 @@
+#ifndef __ASM_R8A7779_H__
+#define __ASM_R8A7779_H__
+#include <linux/sh_clk.h>
+#include <linux/pm_domain.h>
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+        GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+        GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+        GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+        GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+        GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+        GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+        GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+        GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
+        GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+        GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+        GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+        GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+        GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+        GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+        GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
+        GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
+        GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+        GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+        GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+        GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+        GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+        GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+        GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+        GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
+        GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+        GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+        GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+        GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+        GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+        GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+        GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+        GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
+        GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+        GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+        GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+        GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+        GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
+        GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
+        GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
+        GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
+        GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+        GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+        GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+        GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+        GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+        GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+        GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
+        GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
+        GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+        GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+        GPIO_GP_6_8,
+        GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
+        GPIO_FN_A19,
+        /* IPSR0 */
+        GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+        GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
+        GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
+        GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
+        GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
+        GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
+        GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
+        GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
+        GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
+        GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
+        GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
+        GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
+        GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
+        GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
+        GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
+        GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
+        /* IPSR1 */
+        GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
+        GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
+        GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
+        GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
+        GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
+        GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
+        GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
+        GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
+        GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
+        GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
+        GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
+        GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
+        GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
+        GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
+        GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
+        GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
+        GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
+        /* IPSR2 */
+        GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
+        GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
+        GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
+        GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
+        GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
+        GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
+        GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
+        GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
+        GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
+        GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
+        GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
+        GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
+        GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
+        GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
+        GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
+        GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
+        GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
+        GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
+        GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
+        GPIO_FN_AUDATA2,
+        /* IPSR3 */
+        GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
+        GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
+        GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
+        GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
+        GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
+        GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
+        GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
+        GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
+        GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
+        GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
+        GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
+        GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
+        GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
+        GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
+        GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
+        GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
+        GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
+        GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+        GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
+        /* IPSR4 */
+        GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
+        GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
+        GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
+        GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
+        GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
+        GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
+        GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
+        GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
+        GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
+        GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
+        GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
+        GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
+        GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
+        GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
+        GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
+        GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
+        GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
+        GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
+        GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
+        /* IPSR5 */
+        GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
+        GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
+        GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
+        GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
+        GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
+        GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
+        GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
+        GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
+        GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
+        GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+        GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
+        GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
+        GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
+        GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
+        GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
+        GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
+        GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
+        GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
+        GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
+        GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
+        GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
+        GPIO_FN_MOUT0,
+        /* IPSR6 */
+        GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
+        GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
+        GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
+        GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
+        GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
+        GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
+        GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
+        GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
+        GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
+        GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
+        GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
+        GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
+        GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
+        GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
+        GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
+        GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
+        /* IPSR7 */
+        GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
+        GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
+        GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
+        GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
+        GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
+        GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
+        GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
+        GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
+        GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
+        GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
+        GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
+        GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
+        GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
+        GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
+        GPIO_FN_DREQ2,  GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
+        GPIO_FN_CTS1_B,
+        /* IPSR8 */
+        GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
+        GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
+        GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
+        GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
+        GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
+        GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
+        GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
+        GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
+        GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
+        GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
+        GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
+        GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
+        GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
+        GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
+        GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
+        GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
+        GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
+        GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
+        GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
+        /* IPSR9 */
+        GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
+        GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
+        GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
+        GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
+        GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
+        GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
+        GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
+        GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
+        GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
+        GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
+        GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
+        GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
+        GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
+        GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
+        GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
+        GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
+        GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
+        GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
+        /* IPSR10 */
+        GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
+        GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
+        GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
+        GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
+        GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
+        GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
+        GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
+        GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
+        GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
+        GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
+        GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
+        GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
+        GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
+        GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
+        GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
+        GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
+        GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
+        GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
+        GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
+        /* IPSR11 */
+        GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
+        GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
+        GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
+        GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
+        GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
+        GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
+        GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
+        GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
+        GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
+        GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
+        GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
+        GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
+        GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
+        GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
+        GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
+        GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
+        GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
+        GPIO_FN_HRTS0_B,
+        /* IPSR12 */
+        GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
+        GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
+        GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
+        GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
+        GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
+        GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
+        GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
+        GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
+        GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
+};
+struct platform_device;
+struct r8a7779_pm_ch {
+        unsigned long chan_offs;
+        unsigned int chan_bit;
+        unsigned int isr_bit;
+};
+struct r8a7779_pm_domain {
+        struct generic_pm_domain genpd;
+        struct r8a7779_pm_ch ch;
+};
+static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
+{
+        return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
+}
+extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
+extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
+#ifdef CONFIG_PM
+extern struct r8a7779_pm_domain r8a7779_sh4a;
+extern struct r8a7779_pm_domain r8a7779_sgx;
+extern struct r8a7779_pm_domain r8a7779_vdp1;
+extern struct r8a7779_pm_domain r8a7779_impx3;
+extern void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd);
+extern void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
+                                        struct platform_device *pdev);
+#else
+#define r8a7779_init_pm_domain(pd) do { } while (0)
+#define r8a7779_add_device_to_domain(pd, pdev) do { } while (0)
+#endif /* CONFIG_PM */
+#endif /* __ASM_R8A7779_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 84532f9629b..8254ab86f6c 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -480,11 +480,10 @@ struct platform_device;
 struct sh7372_pm_domain {
        struct generic_pm_domain genpd;
        struct dev_power_governor *gov;
-        void (*suspend)(void);
+        int (*suspend)(void);
        void (*resume)(void);
        unsigned int bit_shift;
        bool no_debug;
-        bool stay_on;
 };
 static inline struct sh7372_pm_domain *to_sh7372_pd(struct generic_pm_domain *d)
@@ -499,6 +498,7 @@ extern struct sh7372_pm_domain sh7372_d4;
 extern struct sh7372_pm_domain sh7372_a4r;
 extern struct sh7372_pm_domain sh7372_a3rv;
 extern struct sh7372_pm_domain sh7372_a3ri;
+extern struct sh7372_pm_domain sh7372_a4s;
 extern struct sh7372_pm_domain sh7372_a3sp;
 extern struct sh7372_pm_domain sh7372_a3sg;
@@ -515,5 +515,7 @@ extern void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
 extern void sh7372_intcs_suspend(void);
 extern void sh7372_intcs_resume(void);
+extern void sh7372_intca_suspend(void);
+extern void sh7372_intca_resume(void);
 #endif /* __ASM_SH7372_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
index 76a687eeaa2..956ac18ddbf 100644
--- a/arch/arm/mach-shmobile/include/mach/system.h
+++ b/arch/arm/mach-shmobile/include/mach/system.h
@@ -8,7 +8,7 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode, const char *cmd)
 {
-        cpu_reset(0);
+        soft_restart(0);
 }
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/vmalloc.h b/arch/arm/mach-shmobile/include/mach/vmalloc.h
deleted file mode 100644
index 2b8fd8b942f..00000000000
--- a/arch/arm/mach-shmobile/include/mach/vmalloc.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_VMALLOC_H
-#define __ASM_MACH_VMALLOC_H
-/* Vmalloc at ... - 0xe5ffffff */
-#define VMALLOC_END 0xe6000000UL
-#endif /* __ASM_MACH_VMALLOC_H */
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
new file mode 100644
index 00000000000..272c84c20c8
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -0,0 +1,631 @@
+/*
+ * R8A7740 processor support
+ *
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sh_intc.h>
+#include <mach/intc.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+/*
+ *              INTCA
+ */
+enum {
+        UNUSED_INTCA = 0,
+        /* interrupt sources INTCA */
+        DIRC,
+        ATAPI,
+        IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
+        AP_ARM_COMMTX, AP_ARM_COMMRX,
+        MFI, MFIS,
+        BBIF1, BBIF2,
+        USBHSDMAC,
+        USBF_OUL_SOF, USBF_IXL_INT,
+        SGX540,
+        CMT1_0, CMT1_1, CMT1_2, CMT1_3,
+        CMT2,
+        CMT3,
+        KEYSC,
+        SCIFA0, SCIFA1, SCIFA2, SCIFA3,
+        MSIOF2, MSIOF1,
+        SCIFA4, SCIFA5, SCIFB,
+        FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
+        SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
+        SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
+        AP_ARM_L2CINT,
+        IRDA,
+        TPU0,
+        SCIFA6, SCIFA7,
+        GbEther,
+        ICBS0,
+        DDM,
+        SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
+        RWDT0,
+        DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
+        DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
+        DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
+        DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
+        DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
+        DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
+        SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
+        USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
+        RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
+        SPU2_0, SPU2_1,
+        FSI, FMSI,
+        IPMMU,
+        AP_ARM_CTIIRQ, AP_ARM_PMURQ,
+        MFIS2,
+        CPORTR2S,
+        CMT14, CMT15,
+        MMCIF_0, MMCIF_1, MMCIF_2,
+        SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
+        STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
+        /* interrupt groups INTCA */
+        DMAC1_1, DMAC1_2,
+        DMAC2_1, DMAC2_2,
+        DMAC3_1, DMAC3_2,
+        AP_ARM1, AP_ARM2,
+        SDHI0, SDHI1, SDHI2,
+        SHWYSTAT,
+        USBF, USBH1, USBH2,
+        RSPI, SPU2, FLCTL, IIC1,
+};
+static struct intc_vect intca_vectors[] __initdata = {
+        INTC_VECT(DIRC,                 0x0560),
+        INTC_VECT(ATAPI,                0x05E0),
+        INTC_VECT(IIC1_ALI,             0x0780),
+        INTC_VECT(IIC1_TACKI,           0x07A0),
+        INTC_VECT(IIC1_WAITI,           0x07C0),
+        INTC_VECT(IIC1_DTEI,            0x07E0),
+        INTC_VECT(AP_ARM_COMMTX,        0x0840),
+        INTC_VECT(AP_ARM_COMMRX,        0x0860),
+        INTC_VECT(MFI,                  0x0900),
+        INTC_VECT(MFIS,                 0x0920),
+        INTC_VECT(BBIF1,                0x0940),
+        INTC_VECT(BBIF2,                0x0960),
+        INTC_VECT(USBHSDMAC,            0x0A00),
+        INTC_VECT(USBF_OUL_SOF,         0x0A20),
+        INTC_VECT(USBF_IXL_INT,         0x0A40),
+        INTC_VECT(SGX540,               0x0A60),
+        INTC_VECT(CMT1_0,               0x0B00),
+        INTC_VECT(CMT1_1,               0x0B20),
+        INTC_VECT(CMT1_2,               0x0B40),
+        INTC_VECT(CMT1_3,               0x0B60),
+        INTC_VECT(CMT2,                 0x0B80),
+        INTC_VECT(CMT3,                 0x0BA0),
+        INTC_VECT(KEYSC,                0x0BE0),
+        INTC_VECT(SCIFA0,               0x0C00),
+        INTC_VECT(SCIFA1,               0x0C20),
+        INTC_VECT(SCIFA2,               0x0C40),
+        INTC_VECT(SCIFA3,               0x0C60),
+        INTC_VECT(MSIOF2,               0x0C80),
+        INTC_VECT(MSIOF1,               0x0D00),
+        INTC_VECT(SCIFA4,               0x0D20),
+        INTC_VECT(SCIFA5,               0x0D40),
+        INTC_VECT(SCIFB,                0x0D60),
+        INTC_VECT(FLCTL_FLSTEI,         0x0D80),
+        INTC_VECT(FLCTL_FLTENDI,        0x0DA0),
+        INTC_VECT(FLCTL_FLTREQ0I,       0x0DC0),
+        INTC_VECT(FLCTL_FLTREQ1I,       0x0DE0),
+        INTC_VECT(SDHI0_0,              0x0E00),
+        INTC_VECT(SDHI0_1,              0x0E20),
+        INTC_VECT(SDHI0_2,              0x0E40),
+        INTC_VECT(SDHI0_3,              0x0E60),
+        INTC_VECT(SDHI1_0,              0x0E80),
+        INTC_VECT(SDHI1_1,              0x0EA0),
+        INTC_VECT(SDHI1_2,              0x0EC0),
+        INTC_VECT(SDHI1_3,              0x0EE0),
+        INTC_VECT(AP_ARM_L2CINT,        0x0FA0),
+        INTC_VECT(IRDA,                 0x0480),
+        INTC_VECT(TPU0,                 0x04A0),
+        INTC_VECT(SCIFA6,               0x04C0),
+        INTC_VECT(SCIFA7,               0x04E0),
+        INTC_VECT(GbEther,              0x0500),
+        INTC_VECT(ICBS0,                0x0540),
+        INTC_VECT(DDM,                  0x1140),
+        INTC_VECT(SDHI2_0,              0x1200),
+        INTC_VECT(SDHI2_1,              0x1220),
+        INTC_VECT(SDHI2_2,              0x1240),
+        INTC_VECT(SDHI2_3,              0x1260),
+        INTC_VECT(RWDT0,                0x1280),
+        INTC_VECT(DMAC1_1_DEI0,         0x2000),
+        INTC_VECT(DMAC1_1_DEI1,         0x2020),
+        INTC_VECT(DMAC1_1_DEI2,         0x2040),
+        INTC_VECT(DMAC1_1_DEI3,         0x2060),
+        INTC_VECT(DMAC1_2_DEI4,         0x2080),
+        INTC_VECT(DMAC1_2_DEI5,         0x20A0),
+        INTC_VECT(DMAC1_2_DADERR,       0x20C0),
+        INTC_VECT(DMAC2_1_DEI0,         0x2100),
+        INTC_VECT(DMAC2_1_DEI1,         0x2120),
+        INTC_VECT(DMAC2_1_DEI2,         0x2140),
+        INTC_VECT(DMAC2_1_DEI3,         0x2160),
+        INTC_VECT(DMAC2_2_DEI4,         0x2180),
+        INTC_VECT(DMAC2_2_DEI5,         0x21A0),
+        INTC_VECT(DMAC2_2_DADERR,       0x21C0),
+        INTC_VECT(DMAC3_1_DEI0,         0x2200),
+        INTC_VECT(DMAC3_1_DEI1,         0x2220),
+        INTC_VECT(DMAC3_1_DEI2,         0x2240),
+        INTC_VECT(DMAC3_1_DEI3,         0x2260),
+        INTC_VECT(DMAC3_2_DEI4,         0x2280),
+        INTC_VECT(DMAC3_2_DEI5,         0x22A0),
+        INTC_VECT(DMAC3_2_DADERR,       0x22C0),
+        INTC_VECT(SHWYSTAT_RT,          0x1300),
+        INTC_VECT(SHWYSTAT_HS,          0x1320),
+        INTC_VECT(SHWYSTAT_COM,         0x1340),
+        INTC_VECT(USBH_INT,             0x1540),
+        INTC_VECT(USBH_OHCI,            0x1560),
+        INTC_VECT(USBH_EHCI,            0x1580),
+        INTC_VECT(USBH_PME,             0x15A0),
+        INTC_VECT(USBH_BIND,            0x15C0),
+        INTC_VECT(RSPI_OVRF,            0x1780),
+        INTC_VECT(RSPI_SPTEF,           0x17A0),
+        INTC_VECT(RSPI_SPRF,            0x17C0),
+        INTC_VECT(SPU2_0,               0x1800),
+        INTC_VECT(SPU2_1,               0x1820),
+        INTC_VECT(FSI,                  0x1840),
+        INTC_VECT(FMSI,                 0x1860),
+        INTC_VECT(IPMMU,                0x1920),
+        INTC_VECT(AP_ARM_CTIIRQ,        0x1980),
+        INTC_VECT(AP_ARM_PMURQ,         0x19A0),
+        INTC_VECT(MFIS2,                0x1A00),
+        INTC_VECT(CPORTR2S,             0x1A20),
+        INTC_VECT(CMT14,                0x1A40),
+        INTC_VECT(CMT15,                0x1A60),
+        INTC_VECT(MMCIF_0,              0x1AA0),
+        INTC_VECT(MMCIF_1,              0x1AC0),
+        INTC_VECT(MMCIF_2,              0x1AE0),
+        INTC_VECT(SIM_ERI,              0x1C00),
+        INTC_VECT(SIM_RXI,              0x1C20),
+        INTC_VECT(SIM_TXI,              0x1C40),
+        INTC_VECT(SIM_TEI,              0x1C60),
+        INTC_VECT(STPRO_0,              0x1C80),
+        INTC_VECT(STPRO_1,              0x1CA0),
+        INTC_VECT(STPRO_2,              0x1CC0),
+        INTC_VECT(STPRO_3,              0x1CE0),
+        INTC_VECT(STPRO_4,              0x1D00),
+};
+static struct intc_group intca_groups[] __initdata = {
+        INTC_GROUP(DMAC1_1,
+                   DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
+        INTC_GROUP(DMAC1_2,
+                   DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
+        INTC_GROUP(DMAC2_1,
+                   DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
+        INTC_GROUP(DMAC2_2,
+                   DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
+        INTC_GROUP(DMAC3_1,
+                   DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
+        INTC_GROUP(DMAC3_2,
+                   DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
+        INTC_GROUP(AP_ARM1,
+                   AP_ARM_COMMTX, AP_ARM_COMMRX),
+        INTC_GROUP(AP_ARM2,
+                   AP_ARM_CTIIRQ, AP_ARM_PMURQ),
+        INTC_GROUP(USBF,
+                   USBF_OUL_SOF, USBF_IXL_INT),
+        INTC_GROUP(SDHI0,
+                   SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
+        INTC_GROUP(SDHI1,
+                   SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
+        INTC_GROUP(SDHI2,
+                   SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
+        INTC_GROUP(SHWYSTAT,
+                   SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
+        INTC_GROUP(USBH1, /* FIXME */
+                   USBH_INT, USBH_OHCI),
+        INTC_GROUP(USBH2, /* FIXME */
+                   USBH_EHCI,
+                   USBH_PME, USBH_BIND),
+        INTC_GROUP(RSPI,
+                   RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
+        INTC_GROUP(SPU2,
+                   SPU2_0, SPU2_1),
+        INTC_GROUP(FLCTL,
+                   FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
+        INTC_GROUP(IIC1,
+                   IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
+};
+static struct intc_mask_reg intca_mask_registers[] __initdata = {
+        { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
+          { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
+            0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
+        { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
+          { ATAPI, 0, DIRC, 0,
+            DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
+        { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
+          { 0, 0, 0, 0,
+            BBIF1, BBIF2, MFIS, MFI } },
+        { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
+          { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
+            DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
+        { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
+          { DDM, 0, 0, 0,
+            0, 0, 0, 0 } },
+        { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
+          { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
+            SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
+        { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
+          { SCIFB, SCIFA5, SCIFA4, MSIOF1,
+            0, 0, MSIOF2, 0 } },
+        { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
+          { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
+            FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
+        { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
+          { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
+            0, USBHSDMAC, 0, AP_ARM_L2CINT } },
+        { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
+          { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
+            CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
+        { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
+          { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
+            0, 0, 0, 0 } },
+        { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
+          { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
+            ICBS0, 0, 0, 0 } },
+        { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
+          { 0, 0, TPU0, SCIFA6,
+            SCIFA7, GbEther, 0, 0 } },
+        { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
+          { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
+            0, CMT3, 0, RWDT0 } },
+        { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
+          { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
+            0, 0, 0, 0 } },
+          /* IMR1A3 / IMCR1A3 */
+        { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
+          { 0, 0, USBH_INT, USBH_OHCI,
+            USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
+          /* IMR3A3 / IMCR3A3 */
+        { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
+          { 0, 0, 0, 0,
+            RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
+        { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
+          { SPU2_0, SPU2_1, FSI, FMSI,
+            0, 0, 0, 0 } },
+        { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
+          { 0, IPMMU, 0, 0,
+            AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
+        { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
+          { MFIS2, CPORTR2S, CMT14, CMT15,
+            0, MMCIF_0, MMCIF_1, MMCIF_2 } },
+          /* IMR8A3 / IMCR8A3 */
+        { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
+          { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
+            STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
+        { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
+          { STPRO_4, 0, 0, 0,
+            0, 0, 0, 0 } },
+};
+static struct intc_prio_reg intca_prio_registers[] __initdata = {
+        { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
+        { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
+        { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
+        { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
+        { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
+        { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
+                                              SGX540, CMT1_0 } },
+        { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
+                                              SCIFA2, SCIFA3 } },
+        { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
+                                              FLCTL, SDHI0 } },
+        { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
+        { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
+                                              AP_ARM_L2CINT, 0 } },
+        { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
+        { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
+                                              SCIFA7, GbEther } },
+        { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
+        { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
+        { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
+        { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
+                                /* IPRBA3 */
+                                /* IPRCA3 */
+                                /* IPRDA3 */
+        { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
+        { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
+                                /* IPRGA3 */
+                                /* IPRHA3 */
+                                /* IPRIA3 */
+        { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
+        { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
+                                /* IPRLA3 */
+        { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
+        { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
+        { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
+                                               CMT14, CMT15 } },
+        { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
+                                /* IPRQA3 */
+                                /* IPRRA3 */
+        { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
+                                               SIM_TXI, SIM_TEI } },
+        { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
+                                               STPRO_2, STPRO_3 } },
+        { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
+};
+static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
+                         intca_vectors, intca_groups,
+                         intca_mask_registers, intca_prio_registers,
+                         NULL);
+INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
+                 INTC_VECT, "r8a7740-intca-irq-pins");
+/*
+ *              INTCS
+ */
+enum {
+        UNUSED_INTCS = 0,
+        INTCS,
+        /* interrupt sources INTCS */
+        /* HUDI */
+        /* STPRO */
+        /* RTDMAC(1) */
+        VPU5HA2,
+        _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
+        /* MFI */
+        /* BBIF2 */
+        VPU5F,
+        _2DG_BRK_INT,
+        /* SGX540 */
+        /* 2DDMAC */
+        /* IPMMU */
+        /* RTDMAC 2 */
+        /* KEYSC */
+        /* MSIOF */
+        IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
+        TMU0_0, TMU0_1, TMU0_2,
+        CMT0,
+        /* CMT2 */
+        LMB,
+        CTI,
+        VOU,
+        /* RWDT0 */
+        ICB,
+        VIO6C,
+        CEU20, CEU21,
+        JPU,
+        LCDC0,
+        LCRC,
+        /* RTDMAC2(1) */
+        /* RTDMAC2(2) */
+        LCDC1,
+        /* SPU2 */
+        /* FSI */
+        /* FMSI */
+        TMU1_0, TMU1_1, TMU1_2,
+        CMT4,
+        DISP,
+        DSRV,
+        /* MFIS2 */
+        CPORTS2R,
+        /* interrupt groups INTCS */
+        _2DG1,
+        IIC0, TMU1,
+};
+static struct intc_vect intcs_vectors[] = {
+        /* HUDI */
+        /* STPRO */
+        /* RTDMAC(1) */
+        INTCS_VECT(VPU5HA2,             0x0880),
+        INTCS_VECT(_2DG_TRAP,           0x08A0),
+        INTCS_VECT(_2DG_GPM_INT,        0x08C0),
+        INTCS_VECT(_2DG_CER_INT,        0x08E0),
+        /* MFI */
+        /* BBIF2 */
+        INTCS_VECT(VPU5F,               0x0980),
+        INTCS_VECT(_2DG_BRK_INT,        0x09A0),
+        /* SGX540 */
+        /* 2DDMAC */
+        /* IPMMU */
+        /* RTDMAC(2) */
+        /* KEYSC */
+        /* MSIOF */
+        INTCS_VECT(IIC0_ALI,            0x0E00),
+        INTCS_VECT(IIC0_TACKI,          0x0E20),
+        INTCS_VECT(IIC0_WAITI,          0x0E40),
+        INTCS_VECT(IIC0_DTEI,           0x0E60),
+        INTCS_VECT(TMU0_0,              0x0E80),
+        INTCS_VECT(TMU0_1,              0x0EA0),
+        INTCS_VECT(TMU0_2,              0x0EC0),
+        INTCS_VECT(CMT0,                0x0F00),
+        /* CMT2 */
+        INTCS_VECT(LMB,                 0x0F60),
+        INTCS_VECT(CTI,                 0x0400),
+        INTCS_VECT(VOU,                 0x0420),
+        /* RWDT0 */
+        INTCS_VECT(ICB,                 0x0480),
+        INTCS_VECT(VIO6C,               0x04E0),
+        INTCS_VECT(CEU20,               0x0500),
+        INTCS_VECT(CEU21,               0x0520),
+        INTCS_VECT(JPU,                 0x0560),
+        INTCS_VECT(LCDC0,               0x0580),
+        INTCS_VECT(LCRC,                0x05A0),
+        /* RTDMAC2(1) */
+        /* RTDMAC2(2) */
+        INTCS_VECT(LCDC1,               0x1780),
+        /* SPU2 */
+        /* FSI */
+        /* FMSI */
+        INTCS_VECT(TMU1_0,              0x1900),
+        INTCS_VECT(TMU1_1,              0x1920),
+        INTCS_VECT(TMU1_2,              0x1940),
+        INTCS_VECT(CMT4,                0x1980),
+        INTCS_VECT(DISP,                0x19A0),
+        INTCS_VECT(DSRV,                0x19C0),
+        /* MFIS2 */
+        INTCS_VECT(CPORTS2R,            0x1A20),
+        INTC_VECT(INTCS,                0xf80),
+};
+static struct intc_group intcs_groups[] __initdata = {
+        INTC_GROUP(_2DG1, /*FIXME*/
+                   _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
+        INTC_GROUP(IIC0,
+                   IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
+        INTC_GROUP(TMU1,
+                   TMU1_0, TMU1_1, TMU1_2),
+};
+static struct intc_mask_reg intcs_mask_registers[] = {
+          /* IMR0SA / IMCR0SA */ /* all 0 */
+        { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
+          { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
+            0, 0, 0, 0 /*STPRO*/ } },
+        { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
+          { 0/*STPRO*/, 0, CEU21, VPU5F,
+            0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
+        { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
+          { 0, 0, 0, 0, /*2DDMAC*/
+            VIO6C, 0, 0, ICB } },
+        { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
+          { 0, 0, VOU, CTI,
+            JPU, 0, LCRC, LCDC0 } },
+          /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
+          /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
+        { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
+          { 0, TMU0_2, TMU0_1, TMU0_0,
+            0, 0, 0, 0 } },
+        { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
+          { 0, 0, 0, 0,
+            CEU20, 0, 0, 0 } },
+        { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
+          { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
+            0, 0, 0, 0 } },
+          /* IMR10SA / IMCR10SA */ /*IPMMU*/
+        { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
+          { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
+            0, _2DG_BRK_INT, LMB, 0 } },
+          /* IMR12SA / IMCR12SA */
+          /* IMR13SA / IMCR13SA */
+          /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
+          /* IMR1SA3 / IMCR1SA3 */
+          /* IMR2SA3 / IMCR2SA3 */
+          /* IMR3SA3 / IMCR3SA3 */
+        { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
+          { 0, 0, 0, 0,
+            LCDC1, 0, 0, 0 } },
+          /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
+        { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
+          { TMU1_0, TMU1_1, TMU1_2, 0,
+            CMT4, DISP, DSRV, 0 } },
+        { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
+          { 0/*MFIS2*/, CPORTS2R, 0, 0,
+            0, 0, 0, 0 } },
+        { /* INTAMASK */ 0xffd20104, 0, 16,
+          { 0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, INTCS } },
+};
+/* Priority is needed for INTCA to receive the INTCS interrupt */
+static struct intc_prio_reg intcs_prio_registers[] = {
+        { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
+        { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
+                                /* IPRCS */ /*BBIF2*/
+                                /* IPRDS */
+        { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
+                                              0/*MFI*/, VPU5F } },
+        { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
+                                              0/*CMT2*/, CMT0 } },
+        { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
+                                              TMU0_2, _2DG1 } },
+        { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
+                                              _2DG_BRK_INT/*FIXME*/ } },
+        { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
+        { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
+        { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
+        { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
+                                /* IPRMS */ /*RWDT0*/
+                                /* IPRAS3 */ /*RTDMAC2(1)*/
+                                /* IPRBS3 */ /*RTDMAC2(2)*/
+                                /* IPRCS3 */
+                                /* IPRDS3 */
+                                /* IPRES3 */
+                                /* IPRFS3 */
+                                /* IPRGS3 */
+                                /* IPRHS3 */
+                                /* IPRIS3 */
+        { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
+                                /* IPRKS3 */ /*SPU2/FSI/FMSi*/
+                                /* IPRLS3 */
+        { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
+        { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
+        { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
+                                /* IPRPS3 */
+};
+static struct resource intcs_resources[] __initdata = {
+        [0] = {
+                .start  = 0xffd20000,
+                .end    = 0xffd201ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 0xffd50000,
+                .end    = 0xffd501ff,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct intc_desc intcs_desc __initdata = {
+        .name = "r8a7740-intcs",
+        .resource = intcs_resources,
+        .num_resources = ARRAY_SIZE(intcs_resources),
+        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
+                           intcs_prio_registers, NULL, NULL),
+};
+static void intcs_demux(unsigned int irq, struct irq_desc *desc)
+{
+        void __iomem *reg = (void *)irq_get_handler_data(irq);
+        unsigned int evtcodeas = ioread32(reg);
+        generic_handle_irq(intcs_evt2irq(evtcodeas));
+}
+void __init r8a7740_init_irq(void)
+{
+        void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+        register_intc_controller(&intca_desc);
+        register_intc_controller(&intca_irq_pins_desc);
+        register_intc_controller(&intcs_desc);
+        /* demux using INTEVTSA */
+        irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
+        irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
+}
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
new file mode 100644
index 00000000000..5d92fcde2bc
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -0,0 +1,58 @@
+/*
+ * r8a7779 processor support - INTC hardware block
+ *
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <mach/common.h>
+#include <mach/intc.h>
+#include <mach/r8a7779.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#define INT2SMSKCR0 0xfe7822a0
+#define INT2SMSKCR1 0xfe7822a4
+#define INT2SMSKCR2 0xfe7822a8
+#define INT2SMSKCR3 0xfe7822ac
+#define INT2SMSKCR4 0xfe7822b0
+static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
+{
+        return 0; /* always allow wakeup */
+}
+void __init r8a7779_init_irq(void)
+{
+        void __iomem *gic_dist_base = __io(0xf0001000);
+        void __iomem *gic_cpu_base = __io(0xf0000100);
+        /* use GIC to handle interrupts */
+        gic_init(0, 29, gic_dist_base, gic_cpu_base);
+        gic_arch_extn.irq_set_wake = r8a7779_set_wake;
+        /* unmask all known interrupts in INTCS2 */
+        __raw_writel(0xfffffff0, INT2SMSKCR0);
+        __raw_writel(0xfff7ffff, INT2SMSKCR1);
+        __raw_writel(0xfffbffdf, INT2SMSKCR2);
+        __raw_writel(0xbffffffc, INT2SMSKCR3);
+        __raw_writel(0x003fee3f, INT2SMSKCR4);
+}
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 2d8856df80e..89afcaba99a 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -535,6 +535,7 @@ static struct resource intcs_resources[] __initdata = {
 static struct intc_desc intcs_desc __initdata = {
        .name = "sh7372-intcs",
        .force_enable = ENABLED_INTCS,
+        .skip_syscore_suspend = true,
        .resource = intcs_resources,
        .num_resources = ARRAY_SIZE(intcs_resources),
        .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
@@ -611,3 +612,52 @@ void sh7372_intcs_resume(void)
        for (k = 0x80; k <= 0x9c; k += 4)
                __raw_writeb(ffd5[k], intcs_ffd5 + k);
 }
+static unsigned short e694[0x200];
+static unsigned short e695[0x200];
+void sh7372_intca_suspend(void)
+{
+        int k;
+        for (k = 0x00; k <= 0x38; k += 4)
+                e694[k] = __raw_readw(0xe6940000 + k);
+        for (k = 0x80; k <= 0xb4; k += 4)
+                e694[k] = __raw_readb(0xe6940000 + k);
+        for (k = 0x180; k <= 0x1b4; k += 4)
+                e694[k] = __raw_readb(0xe6940000 + k);
+        for (k = 0x00; k <= 0x50; k += 4)
+                e695[k] = __raw_readw(0xe6950000 + k);
+        for (k = 0x80; k <= 0xa8; k += 4)
+                e695[k] = __raw_readb(0xe6950000 + k);
+        for (k = 0x180; k <= 0x1a8; k += 4)
+                e695[k] = __raw_readb(0xe6950000 + k);
+}
+void sh7372_intca_resume(void)
+{
+        int k;
+        for (k = 0x00; k <= 0x38; k += 4)
+                __raw_writew(e694[k], 0xe6940000 + k);
+        for (k = 0x80; k <= 0xb4; k += 4)
+                __raw_writeb(e694[k], 0xe6940000 + k);
+        for (k = 0x180; k <= 0x1b4; k += 4)
+                __raw_writeb(e694[k], 0xe6940000 + k);
+        for (k = 0x00; k <= 0x50; k += 4)
+                __raw_writew(e695[k], 0xe6950000 + k);
+        for (k = 0x80; k <= 0xa8; k += 4)
+                __raw_writeb(e695[k], 0xe6950000 + k);
+        for (k = 0x180; k <= 0x1a8; k += 4)
+                __raw_writeb(e695[k], 0xe6950000 + k);
+}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
new file mode 100644
index 00000000000..a4fff6950b0
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -0,0 +1,2562 @@
+/*
+ * R8A7740 processor support
+ *
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <mach/r8a7740.h>
+#define CPU_ALL_PORT(fn, pfx, sfx)                                      \
+        PORT_10(fn, pfx, sfx),          PORT_90(fn, pfx, sfx),          \
+        PORT_10(fn, pfx##10, sfx),      PORT_90(fn, pfx##1, sfx),       \
+        PORT_10(fn, pfx##20, sfx),                                      \
+        PORT_1(fn, pfx##210, sfx),      PORT_1(fn, pfx##211, sfx)
+enum {
+        PINMUX_RESERVED = 0,
+        /* PORT0_DATA -> PORT211_DATA */
+        PINMUX_DATA_BEGIN,
+        PORT_ALL(DATA),
+        PINMUX_DATA_END,
+        /* PORT0_IN -> PORT211_IN */
+        PINMUX_INPUT_BEGIN,
+        PORT_ALL(IN),
+        PINMUX_INPUT_END,
+        /* PORT0_IN_PU -> PORT211_IN_PU */
+        PINMUX_INPUT_PULLUP_BEGIN,
+        PORT_ALL(IN_PU),
+        PINMUX_INPUT_PULLUP_END,
+        /* PORT0_IN_PD -> PORT211_IN_PD */
+        PINMUX_INPUT_PULLDOWN_BEGIN,
+        PORT_ALL(IN_PD),
+        PINMUX_INPUT_PULLDOWN_END,
+        /* PORT0_OUT -> PORT211_OUT */
+        PINMUX_OUTPUT_BEGIN,
+        PORT_ALL(OUT),
+        PINMUX_OUTPUT_END,
+        PINMUX_FUNCTION_BEGIN,
+        PORT_ALL(FN_IN),        /* PORT0_FN_IN -> PORT211_FN_IN */
+        PORT_ALL(FN_OUT),       /* PORT0_FN_OUT -> PORT211_FN_OUT */
+        PORT_ALL(FN0),          /* PORT0_FN0 -> PORT211_FN0 */
+        PORT_ALL(FN1),          /* PORT0_FN1 -> PORT211_FN1 */
+        PORT_ALL(FN2),          /* PORT0_FN2 -> PORT211_FN2 */
+        PORT_ALL(FN3),          /* PORT0_FN3 -> PORT211_FN3 */
+        PORT_ALL(FN4),          /* PORT0_FN4 -> PORT211_FN4 */
+        PORT_ALL(FN5),          /* PORT0_FN5 -> PORT211_FN5 */
+        PORT_ALL(FN6),          /* PORT0_FN6 -> PORT211_FN6 */
+        PORT_ALL(FN7),          /* PORT0_FN7 -> PORT211_FN7 */
+        MSEL1CR_31_0,   MSEL1CR_31_1,
+        MSEL1CR_30_0,   MSEL1CR_30_1,
+        MSEL1CR_29_0,   MSEL1CR_29_1,
+        MSEL1CR_28_0,   MSEL1CR_28_1,
+        MSEL1CR_27_0,   MSEL1CR_27_1,
+        MSEL1CR_26_0,   MSEL1CR_26_1,
+        MSEL1CR_16_0,   MSEL1CR_16_1,
+        MSEL1CR_15_0,   MSEL1CR_15_1,
+        MSEL1CR_14_0,   MSEL1CR_14_1,
+        MSEL1CR_13_0,   MSEL1CR_13_1,
+        MSEL1CR_12_0,   MSEL1CR_12_1,
+        MSEL1CR_9_0,    MSEL1CR_9_1,
+        MSEL1CR_7_0,    MSEL1CR_7_1,
+        MSEL1CR_6_0,    MSEL1CR_6_1,
+        MSEL1CR_5_0,    MSEL1CR_5_1,
+        MSEL1CR_4_0,    MSEL1CR_4_1,
+        MSEL1CR_3_0,    MSEL1CR_3_1,
+        MSEL1CR_2_0,    MSEL1CR_2_1,
+        MSEL1CR_0_0,    MSEL1CR_0_1,
+        MSEL3CR_15_0,   MSEL3CR_15_1, /* Trace / Debug ? */
+        MSEL3CR_6_0,    MSEL3CR_6_1,
+        MSEL4CR_19_0,   MSEL4CR_19_1,
+        MSEL4CR_18_0,   MSEL4CR_18_1,
+        MSEL4CR_15_0,   MSEL4CR_15_1,
+        MSEL4CR_10_0,   MSEL4CR_10_1,
+        MSEL4CR_6_0,    MSEL4CR_6_1,
+        MSEL4CR_4_0,    MSEL4CR_4_1,
+        MSEL4CR_1_0,    MSEL4CR_1_1,
+        MSEL5CR_31_0,   MSEL5CR_31_1, /* irq/fiq output */
+        MSEL5CR_30_0,   MSEL5CR_30_1,
+        MSEL5CR_29_0,   MSEL5CR_29_1,
+        MSEL5CR_27_0,   MSEL5CR_27_1,
+        MSEL5CR_25_0,   MSEL5CR_25_1,
+        MSEL5CR_23_0,   MSEL5CR_23_1,
+        MSEL5CR_21_0,   MSEL5CR_21_1,
+        MSEL5CR_19_0,   MSEL5CR_19_1,
+        MSEL5CR_17_0,   MSEL5CR_17_1,
+        MSEL5CR_15_0,   MSEL5CR_15_1,
+        MSEL5CR_14_0,   MSEL5CR_14_1,
+        MSEL5CR_13_0,   MSEL5CR_13_1,
+        MSEL5CR_12_0,   MSEL5CR_12_1,
+        MSEL5CR_11_0,   MSEL5CR_11_1,
+        MSEL5CR_10_0,   MSEL5CR_10_1,
+        MSEL5CR_8_0,    MSEL5CR_8_1,
+        MSEL5CR_7_0,    MSEL5CR_7_1,
+        MSEL5CR_6_0,    MSEL5CR_6_1,
+        MSEL5CR_5_0,    MSEL5CR_5_1,
+        MSEL5CR_4_0,    MSEL5CR_4_1,
+        MSEL5CR_3_0,    MSEL5CR_3_1,
+        MSEL5CR_2_0,    MSEL5CR_2_1,
+        MSEL5CR_0_0,    MSEL5CR_0_1,
+        PINMUX_FUNCTION_END,
+        PINMUX_MARK_BEGIN,
+        /* IRQ */
+        IRQ0_PORT2_MARK,        IRQ0_PORT13_MARK,
+        IRQ1_MARK,
+        IRQ2_PORT11_MARK,       IRQ2_PORT12_MARK,
+        IRQ3_PORT10_MARK,       IRQ3_PORT14_MARK,
+        IRQ4_PORT15_MARK,       IRQ4_PORT172_MARK,
+        IRQ5_PORT0_MARK,        IRQ5_PORT1_MARK,
+        IRQ6_PORT121_MARK,      IRQ6_PORT173_MARK,
+        IRQ7_PORT120_MARK,      IRQ7_PORT209_MARK,
+        IRQ8_MARK,
+        IRQ9_PORT118_MARK,      IRQ9_PORT210_MARK,
+        IRQ10_MARK,
+        IRQ11_MARK,
+        IRQ12_PORT42_MARK,      IRQ12_PORT97_MARK,
+        IRQ13_PORT64_MARK,      IRQ13_PORT98_MARK,
+        IRQ14_PORT63_MARK,      IRQ14_PORT99_MARK,
+        IRQ15_PORT62_MARK,      IRQ15_PORT100_MARK,
+        IRQ16_PORT68_MARK,      IRQ16_PORT211_MARK,
+        IRQ17_MARK,
+        IRQ18_MARK,
+        IRQ19_MARK,
+        IRQ20_MARK,
+        IRQ21_MARK,
+        IRQ22_MARK,
+        IRQ23_MARK,
+        IRQ24_MARK,
+        IRQ25_MARK,
+        IRQ26_PORT58_MARK,      IRQ26_PORT81_MARK,
+        IRQ27_PORT57_MARK,      IRQ27_PORT168_MARK,
+        IRQ28_PORT56_MARK,      IRQ28_PORT169_MARK,
+        IRQ29_PORT50_MARK,      IRQ29_PORT170_MARK,
+        IRQ30_PORT49_MARK,      IRQ30_PORT171_MARK,
+        IRQ31_PORT41_MARK,      IRQ31_PORT167_MARK,
+        /* Function */
+        /* DBGT */
+        DBGMDT2_MARK,   DBGMDT1_MARK,   DBGMDT0_MARK,
+        DBGMD10_MARK,   DBGMD11_MARK,   DBGMD20_MARK,
+        DBGMD21_MARK,
+        /* FSI */
+        FSIAISLD_PORT0_MARK,    /* FSIAISLD Port 0/5 */
+        FSIAISLD_PORT5_MARK,
+        FSIASPDIF_PORT9_MARK,   /* FSIASPDIF Port 9/18 */
+        FSIASPDIF_PORT18_MARK,
+        FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
+        FSIAOBT_MARK,   FSIAOSLD_MARK,  FSIAOMC_MARK,
+        FSIACK_MARK,    FSIAILR_MARK,   FSIAIBT_MARK,
+        /* FMSI */
+        FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
+        FMSISLD_PORT6_MARK,
+        FMSIILR_MARK,   FMSIIBT_MARK,   FMSIOLR_MARK,   FMSIOBT_MARK,
+        FMSICK_MARK,    FMSOILR_MARK,   FMSOIBT_MARK,   FMSOOLR_MARK,
+        FMSOOBT_MARK,   FMSOSLD_MARK,   FMSOCK_MARK,
+        /* SCIFA0 */
+        SCIFA0_SCK_MARK,        SCIFA0_CTS_MARK,        SCIFA0_RTS_MARK,
+        SCIFA0_RXD_MARK,        SCIFA0_TXD_MARK,
+        /* SCIFA1 */
+        SCIFA1_CTS_MARK,        SCIFA1_SCK_MARK,        SCIFA1_RXD_MARK,
+        SCIFA1_TXD_MARK,        SCIFA1_RTS_MARK,
+        /* SCIFA2 */
+        SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
+        SCIFA2_SCK_PORT199_MARK,
+        SCIFA2_RXD_MARK,        SCIFA2_TXD_MARK,
+        SCIFA2_CTS_MARK,        SCIFA2_RTS_MARK,
+        /* SCIFA3 */
+        SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
+        SCIFA3_SCK_PORT116_MARK,
+        SCIFA3_CTS_PORT117_MARK,
+        SCIFA3_RXD_PORT174_MARK,
+        SCIFA3_TXD_PORT175_MARK,
+        SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
+        SCIFA3_SCK_PORT158_MARK,
+        SCIFA3_CTS_PORT162_MARK,
+        SCIFA3_RXD_PORT159_MARK,
+        SCIFA3_TXD_PORT160_MARK,
+        /* SCIFA4 */
+        SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
+        SCIFA4_TXD_PORT13_MARK,
+        SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
+        SCIFA4_TXD_PORT203_MARK,
+        SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
+        SCIFA4_TXD_PORT93_MARK,
+        SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
+        SCIFA4_SCK_PORT205_MARK,
+        /* SCIFA5 */
+        SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
+        SCIFA5_RXD_PORT10_MARK,
+        SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
+        SCIFA5_TXD_PORT208_MARK,
+        SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
+        SCIFA5_RXD_PORT92_MARK,
+        SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
+        SCIFA5_SCK_PORT206_MARK,
+        /* SCIFA6 */
+        SCIFA6_SCK_MARK,        SCIFA6_RXD_MARK,        SCIFA6_TXD_MARK,
+        /* SCIFA7 */
+        SCIFA7_TXD_MARK,        SCIFA7_RXD_MARK,
+        /* SCIFAB */
+        SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
+        SCIFB_RXD_PORT191_MARK,
+        SCIFB_TXD_PORT192_MARK,
+        SCIFB_RTS_PORT186_MARK,
+        SCIFB_CTS_PORT187_MARK,
+        SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
+        SCIFB_RXD_PORT3_MARK,
+        SCIFB_TXD_PORT4_MARK,
+        SCIFB_RTS_PORT172_MARK,
+        SCIFB_CTS_PORT173_MARK,
+        /* LCD0 */
+        LCDC0_SELECT_MARK,
+        LCD0_D0_MARK,   LCD0_D1_MARK,   LCD0_D2_MARK,   LCD0_D3_MARK,
+        LCD0_D4_MARK,   LCD0_D5_MARK,   LCD0_D6_MARK,   LCD0_D7_MARK,
+        LCD0_D8_MARK,   LCD0_D9_MARK,   LCD0_D10_MARK,  LCD0_D11_MARK,
+        LCD0_D12_MARK,  LCD0_D13_MARK,  LCD0_D14_MARK,  LCD0_D15_MARK,
+        LCD0_D16_MARK,  LCD0_D17_MARK,
+        LCD0_DON_MARK,  LCD0_VCPWC_MARK,        LCD0_VEPWC_MARK,
+        LCD0_DCK_MARK,  LCD0_VSYN_MARK, /* for RGB */
+        LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
+        LCD0_WR_MARK,   LCD0_RD_MARK,   /* for SYS */
+        LCD0_CS_MARK,   LCD0_RS_MARK,   /* for SYS */
+        LCD0_D21_PORT158_MARK,  LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
+        LCD0_D22_PORT160_MARK,  LCD0_D20_PORT161_MARK,
+        LCD0_D19_PORT162_MARK,  LCD0_D18_PORT163_MARK,
+        LCD0_LCLK_PORT165_MARK,
+        LCD0_D18_PORT40_MARK,   LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
+        LCD0_D23_PORT1_MARK,    LCD0_D21_PORT2_MARK,
+        LCD0_D20_PORT3_MARK,    LCD0_D19_PORT4_MARK,
+        LCD0_LCLK_PORT102_MARK,
+        /* LCD1 */
+        LCDC1_SELECT_MARK,
+        LCD1_D0_MARK,   LCD1_D1_MARK,   LCD1_D2_MARK,   LCD1_D3_MARK,
+        LCD1_D4_MARK,   LCD1_D5_MARK,   LCD1_D6_MARK,   LCD1_D7_MARK,
+        LCD1_D8_MARK,   LCD1_D9_MARK,   LCD1_D10_MARK,  LCD1_D11_MARK,
+        LCD1_D12_MARK,  LCD1_D13_MARK,  LCD1_D14_MARK,  LCD1_D15_MARK,
+        LCD1_D16_MARK,  LCD1_D17_MARK,  LCD1_D18_MARK,  LCD1_D19_MARK,
+        LCD1_D20_MARK,  LCD1_D21_MARK,  LCD1_D22_MARK,  LCD1_D23_MARK,
+        LCD1_DON_MARK,  LCD1_VCPWC_MARK,
+        LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
+        LCD1_DCK_MARK,  LCD1_VSYN_MARK, /* for RGB */
+        LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
+        LCD1_RS_MARK,   LCD1_CS_MARK,   /* for SYS */
+        LCD1_RD_MARK,   LCD1_WR_MARK,   /* for SYS */
+        /* RSPI */
+        RSPI_SSL0_A_MARK,       RSPI_SSL1_A_MARK,       RSPI_SSL2_A_MARK,
+        RSPI_SSL3_A_MARK,       RSPI_CK_A_MARK,         RSPI_MOSI_A_MARK,
+        RSPI_MISO_A_MARK,
+        /* VIO CKO */
+        VIO_CKO1_MARK, /* needs fixup */
+        VIO_CKO2_MARK,
+        VIO_CKO_1_MARK,
+        VIO_CKO_MARK,
+        /* VIO0 */
+        VIO0_D0_MARK,   VIO0_D1_MARK,   VIO0_D2_MARK,   VIO0_D3_MARK,
+        VIO0_D4_MARK,   VIO0_D5_MARK,   VIO0_D6_MARK,   VIO0_D7_MARK,
+        VIO0_D8_MARK,   VIO0_D9_MARK,   VIO0_D10_MARK,  VIO0_D11_MARK,
+        VIO0_D12_MARK,  VIO0_VD_MARK,   VIO0_HD_MARK,   VIO0_CLK_MARK,
+        VIO0_FIELD_MARK,
+        VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
+        VIO0_D14_PORT25_MARK,
+        VIO0_D15_PORT24_MARK,
+        VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
+        VIO0_D14_PORT95_MARK,
+        VIO0_D15_PORT96_MARK,
+        /* VIO1 */
+        VIO1_D0_MARK,   VIO1_D1_MARK,   VIO1_D2_MARK,   VIO1_D3_MARK,
+        VIO1_D4_MARK,   VIO1_D5_MARK,   VIO1_D6_MARK,   VIO1_D7_MARK,
+        VIO1_VD_MARK,   VIO1_HD_MARK,   VIO1_CLK_MARK,  VIO1_FIELD_MARK,
+        /* TPU0 */
+        TPU0TO0_MARK,   TPU0TO1_MARK,   TPU0TO3_MARK,
+        TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
+        TPU0TO2_PORT202_MARK,
+        /* SSP1 0 */
+        STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
+        STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
+        STP0_IPEN_MARK, STP0_IPCLK_MARK,        STP0_IPSYNC_MARK,
+        /* SSP1 1 */
+        STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
+        STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
+        STP1_IPSYNC_MARK,
+        STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
+        STP1_IPEN_PORT187_MARK,
+        STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
+        STP1_IPEN_PORT193_MARK,
+        /* SIM */
+        SIM_RST_MARK,   SIM_CLK_MARK,
+        SIM_D_PORT22_MARK, /* SIM_D  Port 22/199 */
+        SIM_D_PORT199_MARK,
+        /* SDHI0 */
+        SDHI0_D0_MARK,  SDHI0_D1_MARK,  SDHI0_D2_MARK,  SDHI0_D3_MARK,
+        SDHI0_CD_MARK,  SDHI0_WP_MARK,  SDHI0_CMD_MARK, SDHI0_CLK_MARK,
+        /* SDHI1 */
+        SDHI1_D0_MARK,  SDHI1_D1_MARK,  SDHI1_D2_MARK,  SDHI1_D3_MARK,
+        SDHI1_CD_MARK,  SDHI1_WP_MARK,  SDHI1_CMD_MARK, SDHI1_CLK_MARK,
+        /* SDHI2 */
+        SDHI2_D0_MARK,  SDHI2_D1_MARK,  SDHI2_D2_MARK,  SDHI2_D3_MARK,
+        SDHI2_CLK_MARK, SDHI2_CMD_MARK,
+        SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
+        SDHI2_WP_PORT25_MARK,
+        SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
+        SDHI2_CD_PORT202_MARK,
+        /* MSIOF2 */
+        MSIOF2_TXD_MARK,        MSIOF2_RXD_MARK,        MSIOF2_TSCK_MARK,
+        MSIOF2_SS2_MARK,        MSIOF2_TSYNC_MARK,      MSIOF2_SS1_MARK,
+        MSIOF2_MCK1_MARK,       MSIOF2_MCK0_MARK,       MSIOF2_RSYNC_MARK,
+        MSIOF2_RSCK_MARK,
+        /* KEYSC */
+        KEYIN4_MARK,    KEYIN5_MARK,    KEYIN6_MARK,    KEYIN7_MARK,
+        KEYOUT0_MARK,   KEYOUT1_MARK,   KEYOUT2_MARK,   KEYOUT3_MARK,
+        KEYOUT4_MARK,   KEYOUT5_MARK,   KEYOUT6_MARK,   KEYOUT7_MARK,
+        KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
+        KEYIN1_PORT44_MARK,
+        KEYIN2_PORT45_MARK,
+        KEYIN3_PORT46_MARK,
+        KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
+        KEYIN1_PORT57_MARK,
+        KEYIN2_PORT56_MARK,
+        KEYIN3_PORT55_MARK,
+        /* VOU */
+        DV_D0_MARK,     DV_D1_MARK,     DV_D2_MARK,     DV_D3_MARK,
+        DV_D4_MARK,     DV_D5_MARK,     DV_D6_MARK,     DV_D7_MARK,
+        DV_D8_MARK,     DV_D9_MARK,     DV_D10_MARK,    DV_D11_MARK,
+        DV_D12_MARK,    DV_D13_MARK,    DV_D14_MARK,    DV_D15_MARK,
+        DV_CLK_MARK,    DV_VSYNC_MARK,  DV_HSYNC_MARK,
+        /* MEMC */
+        MEMC_AD0_MARK,  MEMC_AD1_MARK,  MEMC_AD2_MARK,  MEMC_AD3_MARK,
+        MEMC_AD4_MARK,  MEMC_AD5_MARK,  MEMC_AD6_MARK,  MEMC_AD7_MARK,
+        MEMC_AD8_MARK,  MEMC_AD9_MARK,  MEMC_AD10_MARK, MEMC_AD11_MARK,
+        MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
+        MEMC_CS0_MARK,  MEMC_INT_MARK,  MEMC_NWE_MARK,  MEMC_NOE_MARK,
+        MEMC_CS1_MARK, /* MSEL4CR_6_0 */
+        MEMC_ADV_MARK,
+        MEMC_WAIT_MARK,
+        MEMC_BUSCLK_MARK,
+        MEMC_A1_MARK, /* MSEL4CR_6_1 */
+        MEMC_DREQ0_MARK,
+        MEMC_DREQ1_MARK,
+        MEMC_A0_MARK,
+        /* MMC */
+        MMC0_D0_PORT68_MARK,    MMC0_D1_PORT69_MARK,    MMC0_D2_PORT70_MARK,
+        MMC0_D3_PORT71_MARK,    MMC0_D4_PORT72_MARK,    MMC0_D5_PORT73_MARK,
+        MMC0_D6_PORT74_MARK,    MMC0_D7_PORT75_MARK,    MMC0_CLK_PORT66_MARK,
+        MMC0_CMD_PORT67_MARK,   /* MSEL4CR_15_0 */
+        MMC1_D0_PORT149_MARK,   MMC1_D1_PORT148_MARK,   MMC1_D2_PORT147_MARK,
+        MMC1_D3_PORT146_MARK,   MMC1_D4_PORT145_MARK,   MMC1_D5_PORT144_MARK,
+        MMC1_D6_PORT143_MARK,   MMC1_D7_PORT142_MARK,   MMC1_CLK_PORT103_MARK,
+        MMC1_CMD_PORT104_MARK,  /* MSEL4CR_15_1 */
+        /* MSIOF0 */
+        MSIOF0_SS1_MARK,        MSIOF0_SS2_MARK,        MSIOF0_RXD_MARK,
+        MSIOF0_TXD_MARK,        MSIOF0_MCK0_MARK,       MSIOF0_MCK1_MARK,
+        MSIOF0_RSYNC_MARK,      MSIOF0_RSCK_MARK,       MSIOF0_TSCK_MARK,
+        MSIOF0_TSYNC_MARK,
+        /* MSIOF1 */
+        MSIOF1_RSCK_MARK,       MSIOF1_RSYNC_MARK,
+        MSIOF1_MCK0_MARK,       MSIOF1_MCK1_MARK,
+        MSIOF1_SS2_PORT116_MARK,        MSIOF1_SS1_PORT117_MARK,
+        MSIOF1_RXD_PORT118_MARK,        MSIOF1_TXD_PORT119_MARK,
+        MSIOF1_TSYNC_PORT120_MARK,
+        MSIOF1_TSCK_PORT121_MARK,       /* MSEL4CR_10_0 */
+        MSIOF1_SS1_PORT67_MARK,         MSIOF1_TSCK_PORT72_MARK,
+        MSIOF1_TSYNC_PORT73_MARK,       MSIOF1_TXD_PORT74_MARK,
+        MSIOF1_RXD_PORT75_MARK,
+        MSIOF1_SS2_PORT202_MARK,        /* MSEL4CR_10_1 */
+        /* GPIO */
+        GPO0_MARK,      GPI0_MARK,      GPO1_MARK,      GPI1_MARK,
+        /* USB0 */
+        USB0_OCI_MARK,  USB0_PPON_MARK, VBUS_MARK,
+        /* USB1 */
+        USB1_OCI_MARK,  USB1_PPON_MARK,
+        /* BBIF1 */
+        BBIF1_RXD_MARK,         BBIF1_TXD_MARK,         BBIF1_TSYNC_MARK,
+        BBIF1_TSCK_MARK,        BBIF1_RSCK_MARK,        BBIF1_RSYNC_MARK,
+        BBIF1_FLOW_MARK,        BBIF1_RX_FLOW_N_MARK,
+        /* BBIF2 */
+        BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
+        BBIF2_RXD2_PORT60_MARK,
+        BBIF2_TSYNC2_PORT6_MARK,
+        BBIF2_TSCK2_PORT59_MARK,
+        BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
+        BBIF2_TXD2_PORT183_MARK,
+        BBIF2_TSCK2_PORT89_MARK,
+        BBIF2_TSYNC2_PORT184_MARK,
+        /* BSC / FLCTL / PCMCIA */
+        CS0_MARK,       CS2_MARK,       CS4_MARK,
+        CS5B_MARK,      CS6A_MARK,
+        CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
+        CS5A_PORT19_MARK,
+        IOIS16_MARK, /* ? */
+        A0_MARK,        A1_MARK,        A2_MARK,        A3_MARK,
+        A4_FOE_MARK,    /* share with FLCTL */
+        A5_FCDE_MARK,   /* share with FLCTL */
+        A6_MARK,        A7_MARK,        A8_MARK,        A9_MARK,
+        A10_MARK,       A11_MARK,       A12_MARK,       A13_MARK,
+        A14_MARK,       A15_MARK,       A16_MARK,       A17_MARK,
+        A18_MARK,       A19_MARK,       A20_MARK,       A21_MARK,
+        A22_MARK,       A23_MARK,       A24_MARK,       A25_MARK,
+        A26_MARK,
+        D0_NAF0_MARK,   D1_NAF1_MARK,   D2_NAF2_MARK,   /* share with FLCTL */
+        D3_NAF3_MARK,   D4_NAF4_MARK,   D5_NAF5_MARK,   /* share with FLCTL */
+        D6_NAF6_MARK,   D7_NAF7_MARK,   D8_NAF8_MARK,   /* share with FLCTL */
+        D9_NAF9_MARK,   D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
+        D15_NAF15_MARK,                                 /* share with FLCTL */
+        D16_MARK,       D17_MARK,       D18_MARK,       D19_MARK,
+        D20_MARK,       D21_MARK,       D22_MARK,       D23_MARK,
+        D24_MARK,       D25_MARK,       D26_MARK,       D27_MARK,
+        D28_MARK,       D29_MARK,       D30_MARK,       D31_MARK,
+        WE0_FWE_MARK,   /* share with FLCTL */
+        WE1_MARK,
+        WE2_ICIORD_MARK,        /* share with PCMCIA */
+        WE3_ICIOWR_MARK,        /* share with PCMCIA */
+        CKO_MARK,       BS_MARK,        RDWR_MARK,
+        RD_FSC_MARK,    /* share with FLCTL */
+        WAIT_PORT177_MARK, /* WAIT Port 90/177 */
+        WAIT_PORT90_MARK,
+        FCE0_MARK,      FCE1_MARK,      FRB_MARK, /* FLCTL */
+        /* IRDA */
+        IRDA_FIRSEL_MARK,       IRDA_IN_MARK,   IRDA_OUT_MARK,
+        /* ATAPI */
+        IDE_D0_MARK,    IDE_D1_MARK,    IDE_D2_MARK,    IDE_D3_MARK,
+        IDE_D4_MARK,    IDE_D5_MARK,    IDE_D6_MARK,    IDE_D7_MARK,
+        IDE_D8_MARK,    IDE_D9_MARK,    IDE_D10_MARK,   IDE_D11_MARK,
+        IDE_D12_MARK,   IDE_D13_MARK,   IDE_D14_MARK,   IDE_D15_MARK,
+        IDE_A0_MARK,    IDE_A1_MARK,    IDE_A2_MARK,    IDE_CS0_MARK,
+        IDE_CS1_MARK,   IDE_IOWR_MARK,  IDE_IORD_MARK,  IDE_IORDY_MARK,
+        IDE_INT_MARK,           IDE_RST_MARK,           IDE_DIRECTION_MARK,
+        IDE_EXBUF_ENB_MARK,     IDE_IODACK_MARK,        IDE_IODREQ_MARK,
+        /* RMII */
+        RMII_CRS_DV_MARK,       RMII_RX_ER_MARK,        RMII_RXD0_MARK,
+        RMII_RXD1_MARK,         RMII_TX_EN_MARK,        RMII_TXD0_MARK,
+        RMII_MDC_MARK,          RMII_TXD1_MARK,         RMII_MDIO_MARK,
+        RMII_REF50CK_MARK,      /* for RMII */
+        RMII_REF125CK_MARK,     /* for GMII */
+        /* GEther */
+        ET_TX_CLK_MARK, ET_TX_EN_MARK,  ET_ETXD0_MARK,  ET_ETXD1_MARK,
+        ET_ETXD2_MARK,  ET_ETXD3_MARK,
+        ET_ETXD4_MARK,  ET_ETXD5_MARK, /* for GEther */
+        ET_ETXD6_MARK,  ET_ETXD7_MARK, /* for GEther */
+        ET_COL_MARK,    ET_TX_ER_MARK,  ET_RX_CLK_MARK, ET_RX_DV_MARK,
+        ET_ERXD0_MARK,  ET_ERXD1_MARK,  ET_ERXD2_MARK,  ET_ERXD3_MARK,
+        ET_ERXD4_MARK,  ET_ERXD5_MARK, /* for GEther */
+        ET_ERXD6_MARK,  ET_ERXD7_MARK, /* for GEther */
+        ET_RX_ER_MARK,  ET_CRS_MARK,            ET_MDC_MARK,    ET_MDIO_MARK,
+        ET_LINK_MARK,   ET_PHY_INT_MARK,        ET_WOL_MARK,    ET_GTX_CLK_MARK,
+        /* DMA0 */
+        DREQ0_MARK,     DACK0_MARK,
+        /* DMA1 */
+        DREQ1_MARK,     DACK1_MARK,
+        /* SYSC */
+        RESETOUTS_MARK,         RESETP_PULLUP_MARK,     RESETP_PLAIN_MARK,
+        /* IRREM */
+        IROUT_MARK,
+        /* SDENC */
+        SDENC_CPG_MARK,         SDENC_DV_CLKI_MARK,
+        /* DEBUG */
+        EDEBGREQ_PULLUP_MARK,   /* for JTAG */
+        EDEBGREQ_PULLDOWN_MARK,
+        TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
+        TRACEAUD_FROM_LCDC0_MARK,
+        TRACEAUD_FROM_MEMC_MARK,
+        PINMUX_MARK_END,
+};
+static pinmux_enum_t pinmux_data[] = {
+        /* specify valid pin states for each pin in GPIO mode */
+        /* I/O and Pull U/D */
+        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
+        PORT_DATA_IO_PD(2),             PORT_DATA_IO_PD(3),
+        PORT_DATA_IO_PD(4),             PORT_DATA_IO_PD(5),
+        PORT_DATA_IO_PD(6),             PORT_DATA_IO(7),
+        PORT_DATA_IO(8),                PORT_DATA_IO(9),
+        PORT_DATA_IO_PD(10),            PORT_DATA_IO_PD(11),
+        PORT_DATA_IO_PD(12),            PORT_DATA_IO_PU_PD(13),
+        PORT_DATA_IO_PD(14),            PORT_DATA_IO_PD(15),
+        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
+        PORT_DATA_IO(18),               PORT_DATA_IO_PU(19),
+        PORT_DATA_IO_PU_PD(20),         PORT_DATA_IO_PD(21),
+        PORT_DATA_IO_PU_PD(22),         PORT_DATA_IO(23),
+        PORT_DATA_IO_PU(24),            PORT_DATA_IO_PU(25),
+        PORT_DATA_IO_PU(26),            PORT_DATA_IO_PU(27),
+        PORT_DATA_IO_PU(28),            PORT_DATA_IO_PU(29),
+        PORT_DATA_IO_PU(30),            PORT_DATA_IO_PD(31),
+        PORT_DATA_IO_PD(32),            PORT_DATA_IO_PD(33),
+        PORT_DATA_IO_PD(34),            PORT_DATA_IO_PU(35),
+        PORT_DATA_IO_PU(36),            PORT_DATA_IO_PD(37),
+        PORT_DATA_IO_PU(38),            PORT_DATA_IO_PD(39),
+        PORT_DATA_IO_PU_PD(40),         PORT_DATA_IO_PD(41),
+        PORT_DATA_IO_PD(42),            PORT_DATA_IO_PU_PD(43),
+        PORT_DATA_IO_PU_PD(44),         PORT_DATA_IO_PU_PD(45),
+        PORT_DATA_IO_PU_PD(46),         PORT_DATA_IO_PU_PD(47),
+        PORT_DATA_IO_PU_PD(48),         PORT_DATA_IO_PU_PD(49),
+        PORT_DATA_IO_PU_PD(50),         PORT_DATA_IO_PD(51),
+        PORT_DATA_IO_PD(52),            PORT_DATA_IO_PD(53),
+        PORT_DATA_IO_PD(54),            PORT_DATA_IO_PU_PD(55),
+        PORT_DATA_IO_PU_PD(56),         PORT_DATA_IO_PU_PD(57),
+        PORT_DATA_IO_PU_PD(58),         PORT_DATA_IO_PU_PD(59),
+        PORT_DATA_IO_PU_PD(60),         PORT_DATA_IO_PD(61),
+        PORT_DATA_IO_PD(62),            PORT_DATA_IO_PD(63),
+        PORT_DATA_IO_PD(64),            PORT_DATA_IO_PD(65),
+        PORT_DATA_IO_PU_PD(66),         PORT_DATA_IO_PU_PD(67),
+        PORT_DATA_IO_PU_PD(68),         PORT_DATA_IO_PU_PD(69),
+        PORT_DATA_IO_PU_PD(70),         PORT_DATA_IO_PU_PD(71),
+        PORT_DATA_IO_PU_PD(72),         PORT_DATA_IO_PU_PD(73),
+        PORT_DATA_IO_PU_PD(74),         PORT_DATA_IO_PU_PD(75),
+        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
+        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
+        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
+        PORT_DATA_IO(82),               PORT_DATA_IO_PU_PD(83),
+        PORT_DATA_IO(84),               PORT_DATA_IO_PD(85),
+        PORT_DATA_IO_PD(86),            PORT_DATA_IO_PD(87),
+        PORT_DATA_IO_PD(88),            PORT_DATA_IO_PD(89),
+        PORT_DATA_IO_PD(90),            PORT_DATA_IO_PU_PD(91),
+        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
+        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
+        PORT_DATA_IO_PU_PD(96),         PORT_DATA_IO_PU_PD(97),
+        PORT_DATA_IO_PU_PD(98),         PORT_DATA_IO_PU_PD(99),
+        PORT_DATA_IO_PU_PD(100),        PORT_DATA_IO(101),
+        PORT_DATA_IO_PU(102),           PORT_DATA_IO_PU_PD(103),
+        PORT_DATA_IO_PU(104),           PORT_DATA_IO_PU(105),
+        PORT_DATA_IO_PU_PD(106),        PORT_DATA_IO(107),
+        PORT_DATA_IO(108),              PORT_DATA_IO(109),
+        PORT_DATA_IO(110),              PORT_DATA_IO(111),
+        PORT_DATA_IO(112),              PORT_DATA_IO(113),
+        PORT_DATA_IO_PU_PD(114),        PORT_DATA_IO(115),
+        PORT_DATA_IO_PD(116),           PORT_DATA_IO_PD(117),
+        PORT_DATA_IO_PD(118),           PORT_DATA_IO_PD(119),
+        PORT_DATA_IO_PD(120),           PORT_DATA_IO_PD(121),
+        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
+        PORT_DATA_IO_PD(124),           PORT_DATA_IO(125),
+        PORT_DATA_IO(126),              PORT_DATA_IO(127),
+        PORT_DATA_IO(128),              PORT_DATA_IO(129),
+        PORT_DATA_IO(130),              PORT_DATA_IO(131),
+        PORT_DATA_IO(132),              PORT_DATA_IO(133),
+        PORT_DATA_IO(134),              PORT_DATA_IO(135),
+        PORT_DATA_IO(136),              PORT_DATA_IO(137),
+        PORT_DATA_IO(138),              PORT_DATA_IO(139),
+        PORT_DATA_IO(140),              PORT_DATA_IO(141),
+        PORT_DATA_IO_PU(142),           PORT_DATA_IO_PU(143),
+        PORT_DATA_IO_PU(144),           PORT_DATA_IO_PU(145),
+        PORT_DATA_IO_PU(146),           PORT_DATA_IO_PU(147),
+        PORT_DATA_IO_PU(148),           PORT_DATA_IO_PU(149),
+        PORT_DATA_IO_PU(150),           PORT_DATA_IO_PU(151),
+        PORT_DATA_IO_PU(152),           PORT_DATA_IO_PU(153),
+        PORT_DATA_IO_PU(154),           PORT_DATA_IO_PU(155),
+        PORT_DATA_IO_PU(156),           PORT_DATA_IO_PU(157),
+        PORT_DATA_IO_PD(158),           PORT_DATA_IO_PD(159),
+        PORT_DATA_IO_PU_PD(160),        PORT_DATA_IO_PD(161),
+        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
+        PORT_DATA_IO_PD(164),           PORT_DATA_IO_PD(165),
+        PORT_DATA_IO_PU(166),           PORT_DATA_IO_PU(167),
+        PORT_DATA_IO_PU(168),           PORT_DATA_IO_PU(169),
+        PORT_DATA_IO_PU(170),           PORT_DATA_IO_PU(171),
+        PORT_DATA_IO_PD(172),           PORT_DATA_IO_PD(173),
+        PORT_DATA_IO_PD(174),           PORT_DATA_IO_PD(175),
+        PORT_DATA_IO_PU(176),           PORT_DATA_IO_PU_PD(177),
+        PORT_DATA_IO_PU(178),           PORT_DATA_IO_PD(179),
+        PORT_DATA_IO_PD(180),           PORT_DATA_IO_PU(181),
+        PORT_DATA_IO_PU(182),           PORT_DATA_IO(183),
+        PORT_DATA_IO_PD(184),           PORT_DATA_IO_PD(185),
+        PORT_DATA_IO_PD(186),           PORT_DATA_IO_PD(187),
+        PORT_DATA_IO_PD(188),           PORT_DATA_IO_PD(189),
+        PORT_DATA_IO_PD(190),           PORT_DATA_IO_PD(191),
+        PORT_DATA_IO_PD(192),           PORT_DATA_IO_PU_PD(193),
+        PORT_DATA_IO_PU_PD(194),        PORT_DATA_IO_PD(195),
+        PORT_DATA_IO_PU_PD(196),        PORT_DATA_IO_PD(197),
+        PORT_DATA_IO_PU_PD(198),        PORT_DATA_IO_PU_PD(199),
+        PORT_DATA_IO_PU_PD(200),        PORT_DATA_IO_PU(201),
+        PORT_DATA_IO_PU_PD(202),        PORT_DATA_IO(203),
+        PORT_DATA_IO_PU_PD(204),        PORT_DATA_IO_PU_PD(205),
+        PORT_DATA_IO_PU_PD(206),        PORT_DATA_IO_PU_PD(207),
+        PORT_DATA_IO_PU_PD(208),        PORT_DATA_IO_PD(209),
+        PORT_DATA_IO_PD(210),           PORT_DATA_IO_PD(211),
+        /* Port0 */
+        PINMUX_DATA(DBGMDT2_MARK,               PORT0_FN1),
+        PINMUX_DATA(FSIAISLD_PORT0_MARK,        PORT0_FN2,      MSEL5CR_3_0),
+        PINMUX_DATA(FSIAOSLD1_MARK,             PORT0_FN3),
+        PINMUX_DATA(LCD0_D22_PORT0_MARK,        PORT0_FN4,      MSEL5CR_6_0),
+        PINMUX_DATA(SCIFA7_RXD_MARK,            PORT0_FN6),
+        PINMUX_DATA(LCD1_D4_MARK,               PORT0_FN7),
+        PINMUX_DATA(IRQ5_PORT0_MARK,            PORT0_FN0,      MSEL1CR_5_0),
+        /* Port1 */
+        PINMUX_DATA(DBGMDT1_MARK,               PORT1_FN1),
+        PINMUX_DATA(FMSISLD_PORT1_MARK,         PORT1_FN2,      MSEL5CR_5_0),
+        PINMUX_DATA(FSIAOSLD2_MARK,             PORT1_FN3),
+        PINMUX_DATA(LCD0_D23_PORT1_MARK,        PORT1_FN4,      MSEL5CR_6_0),
+        PINMUX_DATA(SCIFA7_TXD_MARK,            PORT1_FN6),
+        PINMUX_DATA(LCD1_D3_MARK,               PORT1_FN7),
+        PINMUX_DATA(IRQ5_PORT1_MARK,            PORT1_FN0,      MSEL1CR_5_1),
+        /* Port2 */
+        PINMUX_DATA(DBGMDT0_MARK,               PORT2_FN1),
+        PINMUX_DATA(SCIFB_SCK_PORT2_MARK,       PORT2_FN2,      MSEL5CR_17_1),
+        PINMUX_DATA(LCD0_D21_PORT2_MARK,        PORT2_FN4,      MSEL5CR_6_0),
+        PINMUX_DATA(LCD1_D2_MARK,               PORT2_FN7),
+        PINMUX_DATA(IRQ0_PORT2_MARK,            PORT2_FN0,      MSEL1CR_0_1),
+        /* Port3 */
+        PINMUX_DATA(DBGMD21_MARK,               PORT3_FN1),
+        PINMUX_DATA(SCIFB_RXD_PORT3_MARK,       PORT3_FN2,      MSEL5CR_17_1),
+        PINMUX_DATA(LCD0_D20_PORT3_MARK,        PORT3_FN4,      MSEL5CR_6_0),
+        PINMUX_DATA(LCD1_D1_MARK,               PORT3_FN7),
+        /* Port4 */
+        PINMUX_DATA(DBGMD20_MARK,               PORT4_FN1),
+        PINMUX_DATA(SCIFB_TXD_PORT4_MARK,       PORT4_FN2,      MSEL5CR_17_1),
+        PINMUX_DATA(LCD0_D19_PORT4_MARK,        PORT4_FN4,      MSEL5CR_6_0),
+        PINMUX_DATA(LCD1_D0_MARK,               PORT4_FN7),
+        /* Port5 */
+        PINMUX_DATA(DBGMD11_MARK,               PORT5_FN1),
+        PINMUX_DATA(BBIF2_TXD2_PORT5_MARK,      PORT5_FN2,      MSEL5CR_0_0),
+        PINMUX_DATA(FSIAISLD_PORT5_MARK,        PORT5_FN4,      MSEL5CR_3_1),
+        PINMUX_DATA(RSPI_SSL0_A_MARK,           PORT5_FN6),
+        PINMUX_DATA(LCD1_VCPWC_MARK,            PORT5_FN7),
+        /* Port6 */
+        PINMUX_DATA(DBGMD10_MARK,               PORT6_FN1),
+        PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK,    PORT6_FN2,      MSEL5CR_0_0),
+        PINMUX_DATA(FMSISLD_PORT6_MARK,         PORT6_FN4,      MSEL5CR_5_1),
+        PINMUX_DATA(RSPI_SSL1_A_MARK,           PORT6_FN6),
+        PINMUX_DATA(LCD1_VEPWC_MARK,            PORT6_FN7),
+        /* Port7 */
+        PINMUX_DATA(FSIAOLR_MARK,               PORT7_FN1),
+        /* Port8 */
+        PINMUX_DATA(FSIAOBT_MARK,               PORT8_FN1),
+        /* Port9 */
+        PINMUX_DATA(FSIAOSLD_MARK,              PORT9_FN1),
+        PINMUX_DATA(FSIASPDIF_PORT9_MARK,       PORT9_FN2,      MSEL5CR_4_0),
+        /* Port10 */
+        PINMUX_DATA(FSIAOMC_MARK,               PORT10_FN1),
+        PINMUX_DATA(SCIFA5_RXD_PORT10_MARK,     PORT10_FN3,     MSEL5CR_14_0,   MSEL5CR_15_0),
+        PINMUX_DATA(IRQ3_PORT10_MARK,           PORT10_FN0,     MSEL1CR_3_0),
+        /* Port11 */
+        PINMUX_DATA(FSIACK_MARK,                PORT11_FN1),
+        PINMUX_DATA(IRQ2_PORT11_MARK,           PORT11_FN0,     MSEL1CR_2_0),
+        /* Port12 */
+        PINMUX_DATA(FSIAILR_MARK,               PORT12_FN1),
+        PINMUX_DATA(SCIFA4_RXD_PORT12_MARK,     PORT12_FN2,     MSEL5CR_12_0,   MSEL5CR_11_0),
+        PINMUX_DATA(LCD1_RS_MARK,               PORT12_FN6),
+        PINMUX_DATA(LCD1_DISP_MARK,             PORT12_FN7),
+        PINMUX_DATA(IRQ2_PORT12_MARK,           PORT12_FN0,     MSEL1CR_2_1),
+        /* Port13 */
+        PINMUX_DATA(FSIAIBT_MARK,               PORT13_FN1),
+        PINMUX_DATA(SCIFA4_TXD_PORT13_MARK,     PORT13_FN2,     MSEL5CR_12_0,   MSEL5CR_11_0),
+        PINMUX_DATA(LCD1_RD_MARK,               PORT13_FN7),
+        PINMUX_DATA(IRQ0_PORT13_MARK,           PORT13_FN0,     MSEL1CR_0_0),
+        /* Port14 */
+        PINMUX_DATA(FMSOILR_MARK,               PORT14_FN1),
+        PINMUX_DATA(FMSIILR_MARK,               PORT14_FN2),
+        PINMUX_DATA(VIO_CKO1_MARK,              PORT14_FN3),
+        PINMUX_DATA(LCD1_D23_MARK,              PORT14_FN7),
+        PINMUX_DATA(IRQ3_PORT14_MARK,           PORT14_FN0,     MSEL1CR_3_1),
+        /* Port15 */
+        PINMUX_DATA(FMSOIBT_MARK,               PORT15_FN1),
+        PINMUX_DATA(FMSIIBT_MARK,               PORT15_FN2),
+        PINMUX_DATA(VIO_CKO2_MARK,              PORT15_FN3),
+        PINMUX_DATA(LCD1_D22_MARK,              PORT15_FN7),
+        PINMUX_DATA(IRQ4_PORT15_MARK,           PORT15_FN0,     MSEL1CR_4_0),
+        /* Port16 */
+        PINMUX_DATA(FMSOOLR_MARK,               PORT16_FN1),
+        PINMUX_DATA(FMSIOLR_MARK,               PORT16_FN2),
+        /* Port17 */
+        PINMUX_DATA(FMSOOBT_MARK,               PORT17_FN1),
+        PINMUX_DATA(FMSIOBT_MARK,               PORT17_FN2),
+        /* Port18 */
+        PINMUX_DATA(FMSOSLD_MARK,               PORT18_FN1),
+        PINMUX_DATA(FSIASPDIF_PORT18_MARK,      PORT18_FN2,     MSEL5CR_4_1),
+        /* Port19 */
+        PINMUX_DATA(FMSICK_MARK,                PORT19_FN1),
+        PINMUX_DATA(CS5A_PORT19_MARK,           PORT19_FN7,     MSEL5CR_2_1),
+        PINMUX_DATA(IRQ10_MARK,                 PORT19_FN0),
+        /* Port20 */
+        PINMUX_DATA(FMSOCK_MARK,                PORT20_FN1),
+        PINMUX_DATA(SCIFA5_TXD_PORT20_MARK,     PORT20_FN3,     MSEL5CR_15_0,   MSEL5CR_14_0),
+        PINMUX_DATA(IRQ1_MARK,                  PORT20_FN0),
+        /* Port21 */
+        PINMUX_DATA(SCIFA1_CTS_MARK,            PORT21_FN1),
+        PINMUX_DATA(SCIFA4_SCK_PORT21_MARK,     PORT21_FN2,     MSEL5CR_10_0),
+        PINMUX_DATA(TPU0TO1_MARK,               PORT21_FN4),
+        PINMUX_DATA(VIO1_FIELD_MARK,            PORT21_FN5),
+        PINMUX_DATA(STP0_IPD5_MARK,             PORT21_FN6),
+        PINMUX_DATA(LCD1_D10_MARK,              PORT21_FN7),
+        /* Port22 */
+        PINMUX_DATA(SCIFA2_SCK_PORT22_MARK,     PORT22_FN1,     MSEL5CR_7_0),
+        PINMUX_DATA(SIM_D_PORT22_MARK,          PORT22_FN4,     MSEL5CR_21_0),
+        PINMUX_DATA(VIO0_D13_PORT22_MARK,       PORT22_FN7,     MSEL5CR_27_1),
+        /* Port23 */
+        PINMUX_DATA(SCIFA1_RTS_MARK,            PORT23_FN1),
+        PINMUX_DATA(SCIFA5_SCK_PORT23_MARK,     PORT23_FN3,     MSEL5CR_13_0),
+        PINMUX_DATA(TPU0TO0_MARK,               PORT23_FN4),
+        PINMUX_DATA(VIO_CKO_1_MARK,             PORT23_FN5),
+        PINMUX_DATA(STP0_IPD2_MARK,             PORT23_FN6),
+        PINMUX_DATA(LCD1_D7_MARK,               PORT23_FN7),
+        /* Port24 */
+        PINMUX_DATA(VIO0_D15_PORT24_MARK,       PORT24_FN1,     MSEL5CR_27_0),
+        PINMUX_DATA(VIO1_D7_MARK,               PORT24_FN5),
+        PINMUX_DATA(SCIFA6_SCK_MARK,            PORT24_FN6),
+        PINMUX_DATA(SDHI2_CD_PORT24_MARK,       PORT24_FN7,     MSEL5CR_19_0),
+        /* Port25 */
+        PINMUX_DATA(VIO0_D14_PORT25_MARK,       PORT25_FN1,     MSEL5CR_27_0),
+        PINMUX_DATA(VIO1_D6_MARK,               PORT25_FN5),
+        PINMUX_DATA(SCIFA6_RXD_MARK,            PORT25_FN6),
+        PINMUX_DATA(SDHI2_WP_PORT25_MARK,       PORT25_FN7,     MSEL5CR_19_0),
+        /* Port26 */
+        PINMUX_DATA(VIO0_D13_PORT26_MARK,       PORT26_FN1,     MSEL5CR_27_0),
+        PINMUX_DATA(VIO1_D5_MARK,               PORT26_FN5),
+        PINMUX_DATA(SCIFA6_TXD_MARK,            PORT26_FN6),
+        /* Port27 - Port39 Function */
+        PINMUX_DATA(VIO0_D7_MARK,               PORT27_FN1),
+        PINMUX_DATA(VIO0_D6_MARK,               PORT28_FN1),
+        PINMUX_DATA(VIO0_D5_MARK,               PORT29_FN1),
+        PINMUX_DATA(VIO0_D4_MARK,               PORT30_FN1),
+        PINMUX_DATA(VIO0_D3_MARK,               PORT31_FN1),
+        PINMUX_DATA(VIO0_D2_MARK,               PORT32_FN1),
+        PINMUX_DATA(VIO0_D1_MARK,               PORT33_FN1),
+        PINMUX_DATA(VIO0_D0_MARK,               PORT34_FN1),
+        PINMUX_DATA(VIO0_CLK_MARK,              PORT35_FN1),
+        PINMUX_DATA(VIO_CKO_MARK,               PORT36_FN1),
+        PINMUX_DATA(VIO0_HD_MARK,               PORT37_FN1),
+        PINMUX_DATA(VIO0_FIELD_MARK,            PORT38_FN1),
+        PINMUX_DATA(VIO0_VD_MARK,               PORT39_FN1),
+        /* Port38 IRQ */
+        PINMUX_DATA(IRQ25_MARK,                 PORT38_FN0),
+        /* Port40 */
+        PINMUX_DATA(LCD0_D18_PORT40_MARK,       PORT40_FN4,     MSEL5CR_6_0),
+        PINMUX_DATA(RSPI_CK_A_MARK,             PORT40_FN6),
+        PINMUX_DATA(LCD1_LCLK_MARK,             PORT40_FN7),
+        /* Port41 */
+        PINMUX_DATA(LCD0_D17_MARK,              PORT41_FN1),
+        PINMUX_DATA(MSIOF2_SS1_MARK,            PORT41_FN2),
+        PINMUX_DATA(IRQ31_PORT41_MARK,          PORT41_FN0,     MSEL1CR_31_1),
+        /* Port42 */
+        PINMUX_DATA(LCD0_D16_MARK,              PORT42_FN1),
+        PINMUX_DATA(MSIOF2_MCK1_MARK,           PORT42_FN2),
+        PINMUX_DATA(IRQ12_PORT42_MARK,          PORT42_FN0,     MSEL1CR_12_1),
+        /* Port43 */
+        PINMUX_DATA(LCD0_D15_MARK,              PORT43_FN1),
+        PINMUX_DATA(MSIOF2_MCK0_MARK,           PORT43_FN2),
+        PINMUX_DATA(KEYIN0_PORT43_MARK,         PORT43_FN3,     MSEL4CR_18_0),
+        PINMUX_DATA(DV_D15_MARK,                PORT43_FN6),
+        /* Port44 */
+        PINMUX_DATA(LCD0_D14_MARK,              PORT44_FN1),
+        PINMUX_DATA(MSIOF2_RSYNC_MARK,          PORT44_FN2),
+        PINMUX_DATA(KEYIN1_PORT44_MARK,         PORT44_FN3,     MSEL4CR_18_0),
+        PINMUX_DATA(DV_D14_MARK,                PORT44_FN6),
+        /* Port45 */
+        PINMUX_DATA(LCD0_D13_MARK,              PORT45_FN1),
+        PINMUX_DATA(MSIOF2_RSCK_MARK,           PORT45_FN2),
+        PINMUX_DATA(KEYIN2_PORT45_MARK,         PORT45_FN3,     MSEL4CR_18_0),
+        PINMUX_DATA(DV_D13_MARK,                PORT45_FN6),
+        /* Port46 */
+        PINMUX_DATA(LCD0_D12_MARK,              PORT46_FN1),
+        PINMUX_DATA(KEYIN3_PORT46_MARK,         PORT46_FN3,     MSEL4CR_18_0),
+        PINMUX_DATA(DV_D12_MARK,                PORT46_FN6),
+        /* Port47 */
+        PINMUX_DATA(LCD0_D11_MARK,              PORT47_FN1),
+        PINMUX_DATA(KEYIN4_MARK,                PORT47_FN3),
+        PINMUX_DATA(DV_D11_MARK,                PORT47_FN6),
+        /* Port48 */
+        PINMUX_DATA(LCD0_D10_MARK,              PORT48_FN1),
+        PINMUX_DATA(KEYIN5_MARK,                PORT48_FN3),
+        PINMUX_DATA(DV_D10_MARK,                PORT48_FN6),
+        /* Port49 */
+        PINMUX_DATA(LCD0_D9_MARK,               PORT49_FN1),
+        PINMUX_DATA(KEYIN6_MARK,                PORT49_FN3),
+        PINMUX_DATA(DV_D9_MARK,                 PORT49_FN6),
+        PINMUX_DATA(IRQ30_PORT49_MARK,          PORT49_FN0,     MSEL1CR_30_1),
+        /* Port50 */
+        PINMUX_DATA(LCD0_D8_MARK,               PORT50_FN1),
+        PINMUX_DATA(KEYIN7_MARK,                PORT50_FN3),
+        PINMUX_DATA(DV_D8_MARK,                 PORT50_FN6),
+        PINMUX_DATA(IRQ29_PORT50_MARK,          PORT50_FN0,     MSEL1CR_29_1),
+        /* Port51 */
+        PINMUX_DATA(LCD0_D7_MARK,               PORT51_FN1),
+        PINMUX_DATA(KEYOUT0_MARK,               PORT51_FN3),
+        PINMUX_DATA(DV_D7_MARK,                 PORT51_FN6),
+        /* Port52 */
+        PINMUX_DATA(LCD0_D6_MARK,               PORT52_FN1),
+        PINMUX_DATA(KEYOUT1_MARK,               PORT52_FN3),
+        PINMUX_DATA(DV_D6_MARK,                 PORT52_FN6),
+        /* Port53 */
+        PINMUX_DATA(LCD0_D5_MARK,               PORT53_FN1),
+        PINMUX_DATA(KEYOUT2_MARK,               PORT53_FN3),
+        PINMUX_DATA(DV_D5_MARK,                 PORT53_FN6),
+        /* Port54 */
+        PINMUX_DATA(LCD0_D4_MARK,               PORT54_FN1),
+        PINMUX_DATA(KEYOUT3_MARK,               PORT54_FN3),
+        PINMUX_DATA(DV_D4_MARK,                 PORT54_FN6),
+        /* Port55 */
+        PINMUX_DATA(LCD0_D3_MARK,               PORT55_FN1),
+        PINMUX_DATA(KEYOUT4_MARK,               PORT55_FN3),
+        PINMUX_DATA(KEYIN3_PORT55_MARK,         PORT55_FN4,     MSEL4CR_18_1),
+        PINMUX_DATA(DV_D3_MARK,                 PORT55_FN6),
+        /* Port56 */
+        PINMUX_DATA(LCD0_D2_MARK,               PORT56_FN1),
+        PINMUX_DATA(KEYOUT5_MARK,               PORT56_FN3),
+        PINMUX_DATA(KEYIN2_PORT56_MARK,         PORT56_FN4,     MSEL4CR_18_1),
+        PINMUX_DATA(DV_D2_MARK,                 PORT56_FN6),
+        PINMUX_DATA(IRQ28_PORT56_MARK,          PORT56_FN0,     MSEL1CR_28_1),
+        /* Port57 */
+        PINMUX_DATA(LCD0_D1_MARK,               PORT57_FN1),
+        PINMUX_DATA(KEYOUT6_MARK,               PORT57_FN3),
+        PINMUX_DATA(KEYIN1_PORT57_MARK,         PORT57_FN4,     MSEL4CR_18_1),
+        PINMUX_DATA(DV_D1_MARK,                 PORT57_FN6),
+        PINMUX_DATA(IRQ27_PORT57_MARK,          PORT57_FN0,     MSEL1CR_27_1),
+        /* Port58 */
+        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1),
+        PINMUX_DATA(KEYOUT7_MARK,               PORT58_FN3),
+        PINMUX_DATA(KEYIN0_PORT58_MARK,         PORT58_FN4,     MSEL4CR_18_1),
+        PINMUX_DATA(DV_D0_MARK,                 PORT58_FN6),
+        PINMUX_DATA(IRQ26_PORT58_MARK,          PORT58_FN0,     MSEL1CR_26_1),
+        /* Port59 */
+        PINMUX_DATA(LCD0_VCPWC_MARK,            PORT59_FN1),
+        PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK,    PORT59_FN2,     MSEL5CR_0_0),
+        PINMUX_DATA(RSPI_MOSI_A_MARK,           PORT59_FN6),
+        /* Port60 */
+        PINMUX_DATA(LCD0_VEPWC_MARK,            PORT60_FN1),
+        PINMUX_DATA(BBIF2_RXD2_PORT60_MARK,     PORT60_FN2,     MSEL5CR_0_0),
+        PINMUX_DATA(RSPI_MISO_A_MARK,           PORT60_FN6),
+        /* Port61 */
+        PINMUX_DATA(LCD0_DON_MARK,              PORT61_FN1),
+        PINMUX_DATA(MSIOF2_TXD_MARK,            PORT61_FN2),
+        /* Port62 */
+        PINMUX_DATA(LCD0_DCK_MARK,              PORT62_FN1),
+        PINMUX_DATA(LCD0_WR_MARK,               PORT62_FN4),
+        PINMUX_DATA(DV_CLK_MARK,                PORT62_FN6),
+        PINMUX_DATA(IRQ15_PORT62_MARK,          PORT62_FN0,     MSEL1CR_15_1),
+        /* Port63 */
+        PINMUX_DATA(LCD0_VSYN_MARK,             PORT63_FN1),
+        PINMUX_DATA(DV_VSYNC_MARK,              PORT63_FN6),
+        PINMUX_DATA(IRQ14_PORT63_MARK,          PORT63_FN0,     MSEL1CR_14_1),
+        /* Port64 */
+        PINMUX_DATA(LCD0_HSYN_MARK,             PORT64_FN1),
+        PINMUX_DATA(LCD0_CS_MARK,               PORT64_FN4),
+        PINMUX_DATA(DV_HSYNC_MARK,              PORT64_FN6),
+        PINMUX_DATA(IRQ13_PORT64_MARK,          PORT64_FN0,     MSEL1CR_13_1),
+        /* Port65 */
+        PINMUX_DATA(LCD0_DISP_MARK,             PORT65_FN1),
+        PINMUX_DATA(MSIOF2_TSCK_MARK,           PORT65_FN2),
+        PINMUX_DATA(LCD0_RS_MARK,               PORT65_FN4),
+        /* Port66 */
+        PINMUX_DATA(MEMC_INT_MARK,              PORT66_FN1),
+        PINMUX_DATA(TPU0TO2_PORT66_MARK,        PORT66_FN3,     MSEL5CR_25_0),
+        PINMUX_DATA(MMC0_CLK_PORT66_MARK,       PORT66_FN4,     MSEL4CR_15_0),
+        PINMUX_DATA(SDHI1_CLK_MARK,             PORT66_FN6),
+        /* Port67 - Port73 Function1 */
+        PINMUX_DATA(MEMC_CS0_MARK,              PORT67_FN1),
+        PINMUX_DATA(MEMC_AD8_MARK,              PORT68_FN1),
+        PINMUX_DATA(MEMC_AD9_MARK,              PORT69_FN1),
+        PINMUX_DATA(MEMC_AD10_MARK,             PORT70_FN1),
+        PINMUX_DATA(MEMC_AD11_MARK,             PORT71_FN1),
+        PINMUX_DATA(MEMC_AD12_MARK,             PORT72_FN1),
+        PINMUX_DATA(MEMC_AD13_MARK,             PORT73_FN1),
+        /* Port67 - Port73 Function2 */
+        PINMUX_DATA(MSIOF1_SS1_PORT67_MARK,     PORT67_FN2,     MSEL4CR_10_1),
+        PINMUX_DATA(MSIOF1_RSCK_MARK,           PORT68_FN2),
+        PINMUX_DATA(MSIOF1_RSYNC_MARK,          PORT69_FN2),
+        PINMUX_DATA(MSIOF1_MCK0_MARK,           PORT70_FN2),
+        PINMUX_DATA(MSIOF1_MCK1_MARK,           PORT71_FN2),
+        PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK,    PORT72_FN2,     MSEL4CR_10_1),
+        PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK,   PORT73_FN2,     MSEL4CR_10_1),
+        /* Port67 - Port73 Function4 */
+        PINMUX_DATA(MMC0_CMD_PORT67_MARK,       PORT67_FN4,     MSEL4CR_15_0),
+        PINMUX_DATA(MMC0_D0_PORT68_MARK,        PORT68_FN4,     MSEL4CR_15_0),
+        PINMUX_DATA(MMC0_D1_PORT69_MARK,        PORT69_FN4,     MSEL4CR_15_0),
+        PINMUX_DATA(MMC0_D2_PORT70_MARK,        PORT70_FN4,     MSEL4CR_15_0),
+        PINMUX_DATA(MMC0_D3_PORT71_MARK,        PORT71_FN4,     MSEL4CR_15_0),
+        PINMUX_DATA(MMC0_D4_PORT72_MARK,        PORT72_FN4,     MSEL4CR_15_0),
+        PINMUX_DATA(MMC0_D5_PORT73_MARK,        PORT73_FN4,     MSEL4CR_15_0),
+        /* Port67 - Port73 Function6 */
+        PINMUX_DATA(SDHI1_CMD_MARK,             PORT67_FN6),
+        PINMUX_DATA(SDHI1_D0_MARK,              PORT68_FN6),
+        PINMUX_DATA(SDHI1_D1_MARK,              PORT69_FN6),
+        PINMUX_DATA(SDHI1_D2_MARK,              PORT70_FN6),
+        PINMUX_DATA(SDHI1_D3_MARK,              PORT71_FN6),
+        PINMUX_DATA(SDHI1_CD_MARK,              PORT72_FN6),
+        PINMUX_DATA(SDHI1_WP_MARK,              PORT73_FN6),
+        /* Port67 - Port71 IRQ */
+        PINMUX_DATA(IRQ20_MARK,                 PORT67_FN0),
+        PINMUX_DATA(IRQ16_PORT68_MARK,          PORT68_FN0,     MSEL1CR_16_0),
+        PINMUX_DATA(IRQ17_MARK,                 PORT69_FN0),
+        PINMUX_DATA(IRQ18_MARK,                 PORT70_FN0),
+        PINMUX_DATA(IRQ19_MARK,                 PORT71_FN0),
+        /* Port74 */
+        PINMUX_DATA(MEMC_AD14_MARK,             PORT74_FN1),
+        PINMUX_DATA(MSIOF1_TXD_PORT74_MARK,     PORT74_FN2,     MSEL4CR_10_1),
+        PINMUX_DATA(MMC0_D6_PORT74_MARK,        PORT74_FN4,     MSEL4CR_15_0),
+        PINMUX_DATA(STP1_IPD7_MARK,             PORT74_FN6),
+        PINMUX_DATA(LCD1_D21_MARK,              PORT74_FN7),
+        /* Port75 */
+        PINMUX_DATA(MEMC_AD15_MARK,             PORT75_FN1),
+        PINMUX_DATA(MSIOF1_RXD_PORT75_MARK,     PORT75_FN2,     MSEL4CR_10_1),
+        PINMUX_DATA(MMC0_D7_PORT75_MARK,        PORT75_FN4,     MSEL4CR_15_0),
+        PINMUX_DATA(STP1_IPD6_MARK,             PORT75_FN6),
+        PINMUX_DATA(LCD1_D20_MARK,              PORT75_FN7),
+        /* Port76 - Port80 Function */
+        PINMUX_DATA(SDHI0_CMD_MARK,             PORT76_FN1),
+        PINMUX_DATA(SDHI0_D0_MARK,              PORT77_FN1),
+        PINMUX_DATA(SDHI0_D1_MARK,              PORT78_FN1),
+        PINMUX_DATA(SDHI0_D2_MARK,              PORT79_FN1),
+        PINMUX_DATA(SDHI0_D3_MARK,              PORT80_FN1),
+        /* Port81 */
+        PINMUX_DATA(SDHI0_CD_MARK,              PORT81_FN1),
+        PINMUX_DATA(IRQ26_PORT81_MARK,          PORT81_FN0,     MSEL1CR_26_0),
+        /* Port82 - Port88 Function */
+        PINMUX_DATA(SDHI0_CLK_MARK,             PORT82_FN1),
+        PINMUX_DATA(SDHI0_WP_MARK,              PORT83_FN1),
+        PINMUX_DATA(RESETOUTS_MARK,             PORT84_FN1),
+        PINMUX_DATA(USB0_PPON_MARK,             PORT85_FN1),
+        PINMUX_DATA(USB0_OCI_MARK,              PORT86_FN1),
+        PINMUX_DATA(USB1_PPON_MARK,             PORT87_FN1),
+        PINMUX_DATA(USB1_OCI_MARK,              PORT88_FN1),
+        /* Port89 */
+        PINMUX_DATA(DREQ0_MARK,                 PORT89_FN1),
+        PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK,    PORT89_FN2,     MSEL5CR_0_1),
+        PINMUX_DATA(RSPI_SSL3_A_MARK,           PORT89_FN6),
+        /* Port90 */
+        PINMUX_DATA(DACK0_MARK,                 PORT90_FN1),
+        PINMUX_DATA(BBIF2_RXD2_PORT90_MARK,     PORT90_FN2,     MSEL5CR_0_1),
+        PINMUX_DATA(RSPI_SSL2_A_MARK,           PORT90_FN6),
+        PINMUX_DATA(WAIT_PORT90_MARK,           PORT90_FN7,     MSEL5CR_2_1),
+        /* Port91 */
+        PINMUX_DATA(MEMC_AD0_MARK,              PORT91_FN1),
+        PINMUX_DATA(BBIF1_RXD_MARK,             PORT91_FN2),
+        PINMUX_DATA(SCIFA5_TXD_PORT91_MARK,     PORT91_FN3,     MSEL5CR_15_1,   MSEL5CR_14_0),
+        PINMUX_DATA(LCD1_D5_MARK,               PORT91_FN7),
+        /* Port92 */
+        PINMUX_DATA(MEMC_AD1_MARK,              PORT92_FN1),
+        PINMUX_DATA(BBIF1_TSYNC_MARK,           PORT92_FN2),
+        PINMUX_DATA(SCIFA5_RXD_PORT92_MARK,     PORT92_FN3,     MSEL5CR_15_1,   MSEL5CR_14_0),
+        PINMUX_DATA(STP0_IPD1_MARK,             PORT92_FN6),
+        PINMUX_DATA(LCD1_D6_MARK,               PORT92_FN7),
+        /* Port93 */
+        PINMUX_DATA(MEMC_AD2_MARK,              PORT93_FN1),
+        PINMUX_DATA(BBIF1_TSCK_MARK,            PORT93_FN2),
+        PINMUX_DATA(SCIFA4_TXD_PORT93_MARK,     PORT93_FN3,     MSEL5CR_12_1,   MSEL5CR_11_0),
+        PINMUX_DATA(STP0_IPD3_MARK,             PORT93_FN6),
+        PINMUX_DATA(LCD1_D8_MARK,               PORT93_FN7),
+        /* Port94 */
+        PINMUX_DATA(MEMC_AD3_MARK,              PORT94_FN1),
+        PINMUX_DATA(BBIF1_TXD_MARK,             PORT94_FN2),
+        PINMUX_DATA(SCIFA4_RXD_PORT94_MARK,     PORT94_FN3,     MSEL5CR_12_1,   MSEL5CR_11_0),
+        PINMUX_DATA(STP0_IPD4_MARK,             PORT94_FN6),
+        PINMUX_DATA(LCD1_D9_MARK,               PORT94_FN7),
+        /* Port95 */
+        PINMUX_DATA(MEMC_CS1_MARK,              PORT95_FN1,     MSEL4CR_6_0),
+        PINMUX_DATA(MEMC_A1_MARK,               PORT95_FN1,     MSEL4CR_6_1),
+        PINMUX_DATA(SCIFA2_CTS_MARK,            PORT95_FN2),
+        PINMUX_DATA(SIM_RST_MARK,               PORT95_FN4),
+        PINMUX_DATA(VIO0_D14_PORT95_MARK,       PORT95_FN7,     MSEL5CR_27_1),
+        PINMUX_DATA(IRQ22_MARK,                 PORT95_FN0),
+        /* Port96 */
+        PINMUX_DATA(MEMC_ADV_MARK,              PORT96_FN1,     MSEL4CR_6_0),
+        PINMUX_DATA(MEMC_DREQ0_MARK,            PORT96_FN1,     MSEL4CR_6_1),
+        PINMUX_DATA(SCIFA2_RTS_MARK,            PORT96_FN2),
+        PINMUX_DATA(SIM_CLK_MARK,               PORT96_FN4),
+        PINMUX_DATA(VIO0_D15_PORT96_MARK,       PORT96_FN7,     MSEL5CR_27_1),
+        PINMUX_DATA(IRQ23_MARK,                 PORT96_FN0),
+        /* Port97 */
+        PINMUX_DATA(MEMC_AD4_MARK,              PORT97_FN1),
+        PINMUX_DATA(BBIF1_RSCK_MARK,            PORT97_FN2),
+        PINMUX_DATA(LCD1_CS_MARK,               PORT97_FN6),
+        PINMUX_DATA(LCD1_HSYN_MARK,             PORT97_FN7),
+        PINMUX_DATA(IRQ12_PORT97_MARK,          PORT97_FN0,     MSEL1CR_12_0),
+        /* Port98 */
+        PINMUX_DATA(MEMC_AD5_MARK,              PORT98_FN1),
+        PINMUX_DATA(BBIF1_RSYNC_MARK,           PORT98_FN2),
+        PINMUX_DATA(LCD1_VSYN_MARK,             PORT98_FN7),
+        PINMUX_DATA(IRQ13_PORT98_MARK,          PORT98_FN0,     MSEL1CR_13_0),
+        /* Port99 */
+        PINMUX_DATA(MEMC_AD6_MARK,              PORT99_FN1),
+        PINMUX_DATA(BBIF1_FLOW_MARK,            PORT99_FN2),
+        PINMUX_DATA(LCD1_WR_MARK,               PORT99_FN6),
+        PINMUX_DATA(LCD1_DCK_MARK,              PORT99_FN7),
+        PINMUX_DATA(IRQ14_PORT99_MARK,          PORT99_FN0,     MSEL1CR_14_0),
+        /* Port100 */
+        PINMUX_DATA(MEMC_AD7_MARK,              PORT100_FN1),
+        PINMUX_DATA(BBIF1_RX_FLOW_N_MARK,       PORT100_FN2),
+        PINMUX_DATA(LCD1_DON_MARK,              PORT100_FN7),
+        PINMUX_DATA(IRQ15_PORT100_MARK,         PORT100_FN0,    MSEL1CR_15_0),
+        /* Port101 */
+        PINMUX_DATA(FCE0_MARK,                  PORT101_FN1),
+        /* Port102 */
+        PINMUX_DATA(FRB_MARK,                   PORT102_FN1),
+        PINMUX_DATA(LCD0_LCLK_PORT102_MARK,     PORT102_FN4,    MSEL5CR_6_0),
+        /* Port103 */
+        PINMUX_DATA(CS5B_MARK,                  PORT103_FN1),
+        PINMUX_DATA(FCE1_MARK,                  PORT103_FN2),
+        PINMUX_DATA(MMC1_CLK_PORT103_MARK,      PORT103_FN3,    MSEL4CR_15_1),
+        /* Port104 */
+        PINMUX_DATA(CS6A_MARK,                  PORT104_FN1),
+        PINMUX_DATA(MMC1_CMD_PORT104_MARK,      PORT104_FN3,    MSEL4CR_15_1),
+        PINMUX_DATA(IRQ11_MARK,                 PORT104_FN0),
+        /* Port105 */
+        PINMUX_DATA(CS5A_PORT105_MARK,          PORT105_FN1,    MSEL5CR_2_0),
+        PINMUX_DATA(SCIFA3_RTS_PORT105_MARK,    PORT105_FN4,    MSEL5CR_8_0),
+        /* Port106 */
+        PINMUX_DATA(IOIS16_MARK,                PORT106_FN1),
+        PINMUX_DATA(IDE_EXBUF_ENB_MARK,         PORT106_FN6),
+        /* Port107 - Port115 Function */
+        PINMUX_DATA(WE3_ICIOWR_MARK,            PORT107_FN1),
+        PINMUX_DATA(WE2_ICIORD_MARK,            PORT108_FN1),
+        PINMUX_DATA(CS0_MARK,                   PORT109_FN1),
+        PINMUX_DATA(CS2_MARK,                   PORT110_FN1),
+        PINMUX_DATA(CS4_MARK,                   PORT111_FN1),
+        PINMUX_DATA(WE1_MARK,                   PORT112_FN1),
+        PINMUX_DATA(WE0_FWE_MARK,               PORT113_FN1),
+        PINMUX_DATA(RDWR_MARK,                  PORT114_FN1),
+        PINMUX_DATA(RD_FSC_MARK,                PORT115_FN1),
+        /* Port116 */
+        PINMUX_DATA(A25_MARK,                   PORT116_FN1),
+        PINMUX_DATA(MSIOF0_SS2_MARK,            PORT116_FN2),
+        PINMUX_DATA(MSIOF1_SS2_PORT116_MARK,    PORT116_FN3,    MSEL4CR_10_0),
+        PINMUX_DATA(SCIFA3_SCK_PORT116_MARK,    PORT116_FN4,    MSEL5CR_8_0),
+        PINMUX_DATA(GPO1_MARK,                  PORT116_FN5),
+        /* Port117 */
+        PINMUX_DATA(A24_MARK,                   PORT117_FN1),
+        PINMUX_DATA(MSIOF0_SS1_MARK,            PORT117_FN2),
+        PINMUX_DATA(MSIOF1_SS1_PORT117_MARK,    PORT117_FN3,    MSEL4CR_10_0),
+        PINMUX_DATA(SCIFA3_CTS_PORT117_MARK,    PORT117_FN4,    MSEL5CR_8_0),
+        PINMUX_DATA(GPO0_MARK,                  PORT117_FN5),
+        /* Port118 */
+        PINMUX_DATA(A23_MARK,                   PORT118_FN1),
+        PINMUX_DATA(MSIOF0_MCK1_MARK,           PORT118_FN2),
+        PINMUX_DATA(MSIOF1_RXD_PORT118_MARK,    PORT118_FN3,    MSEL4CR_10_0),
+        PINMUX_DATA(GPI1_MARK,                  PORT118_FN5),
+        PINMUX_DATA(IRQ9_PORT118_MARK,          PORT118_FN0,    MSEL1CR_9_0),
+        /* Port119 */
+        PINMUX_DATA(A22_MARK,                   PORT119_FN1),
+        PINMUX_DATA(MSIOF0_MCK0_MARK,           PORT119_FN2),
+        PINMUX_DATA(MSIOF1_TXD_PORT119_MARK,    PORT119_FN3,    MSEL4CR_10_0),
+        PINMUX_DATA(GPI0_MARK,                  PORT119_FN5),
+        PINMUX_DATA(IRQ8_MARK,                  PORT119_FN0),
+        /* Port120 */
+        PINMUX_DATA(A21_MARK,                   PORT120_FN1),
+        PINMUX_DATA(MSIOF0_RSYNC_MARK,          PORT120_FN2),
+        PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK,  PORT120_FN3,    MSEL4CR_10_0),
+        PINMUX_DATA(IRQ7_PORT120_MARK,          PORT120_FN0,    MSEL1CR_7_0),
+        /* Port121 */
+        PINMUX_DATA(A20_MARK,                   PORT121_FN1),
+        PINMUX_DATA(MSIOF0_RSCK_MARK,           PORT121_FN2),
+        PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK,   PORT121_FN3,    MSEL4CR_10_0),
+        PINMUX_DATA(IRQ6_PORT121_MARK,          PORT121_FN0,    MSEL1CR_6_0),
+        /* Port122 */
+        PINMUX_DATA(A19_MARK,                   PORT122_FN1),
+        PINMUX_DATA(MSIOF0_RXD_MARK,            PORT122_FN2),
+        /* Port123 */
+        PINMUX_DATA(A18_MARK,                   PORT123_FN1),
+        PINMUX_DATA(MSIOF0_TSCK_MARK,           PORT123_FN2),
+        /* Port124 */
+        PINMUX_DATA(A17_MARK,                   PORT124_FN1),
+        PINMUX_DATA(MSIOF0_TSYNC_MARK,          PORT124_FN2),
+        /* Port125 - Port141 Function */
+        PINMUX_DATA(A16_MARK,                   PORT125_FN1),
+        PINMUX_DATA(A15_MARK,                   PORT126_FN1),
+        PINMUX_DATA(A14_MARK,                   PORT127_FN1),
+        PINMUX_DATA(A13_MARK,                   PORT128_FN1),
+        PINMUX_DATA(A12_MARK,                   PORT129_FN1),
+        PINMUX_DATA(A11_MARK,                   PORT130_FN1),
+        PINMUX_DATA(A10_MARK,                   PORT131_FN1),
+        PINMUX_DATA(A9_MARK,                    PORT132_FN1),
+        PINMUX_DATA(A8_MARK,                    PORT133_FN1),
+        PINMUX_DATA(A7_MARK,                    PORT134_FN1),
+        PINMUX_DATA(A6_MARK,                    PORT135_FN1),
+        PINMUX_DATA(A5_FCDE_MARK,               PORT136_FN1),
+        PINMUX_DATA(A4_FOE_MARK,                PORT137_FN1),
+        PINMUX_DATA(A3_MARK,                    PORT138_FN1),
+        PINMUX_DATA(A2_MARK,                    PORT139_FN1),
+        PINMUX_DATA(A1_MARK,                    PORT140_FN1),
+        PINMUX_DATA(CKO_MARK,                   PORT141_FN1),
+        /* Port142 - Port157 Function1 */
+        PINMUX_DATA(D15_NAF15_MARK,             PORT142_FN1),
+        PINMUX_DATA(D14_NAF14_MARK,             PORT143_FN1),
+        PINMUX_DATA(D13_NAF13_MARK,             PORT144_FN1),
+        PINMUX_DATA(D12_NAF12_MARK,             PORT145_FN1),
+        PINMUX_DATA(D11_NAF11_MARK,             PORT146_FN1),
+        PINMUX_DATA(D10_NAF10_MARK,             PORT147_FN1),
+        PINMUX_DATA(D9_NAF9_MARK,               PORT148_FN1),
+        PINMUX_DATA(D8_NAF8_MARK,               PORT149_FN1),
+        PINMUX_DATA(D7_NAF7_MARK,               PORT150_FN1),
+        PINMUX_DATA(D6_NAF6_MARK,               PORT151_FN1),
+        PINMUX_DATA(D5_NAF5_MARK,               PORT152_FN1),
+        PINMUX_DATA(D4_NAF4_MARK,               PORT153_FN1),
+        PINMUX_DATA(D3_NAF3_MARK,               PORT154_FN1),
+        PINMUX_DATA(D2_NAF2_MARK,               PORT155_FN1),
+        PINMUX_DATA(D1_NAF1_MARK,               PORT156_FN1),
+        PINMUX_DATA(D0_NAF0_MARK,               PORT157_FN1),
+        /* Port142 - Port149 Function3 */
+        PINMUX_DATA(MMC1_D7_PORT142_MARK,       PORT142_FN3,    MSEL4CR_15_1),
+        PINMUX_DATA(MMC1_D6_PORT143_MARK,       PORT143_FN3,    MSEL4CR_15_1),
+        PINMUX_DATA(MMC1_D5_PORT144_MARK,       PORT144_FN3,    MSEL4CR_15_1),
+        PINMUX_DATA(MMC1_D4_PORT145_MARK,       PORT145_FN3,    MSEL4CR_15_1),
+        PINMUX_DATA(MMC1_D3_PORT146_MARK,       PORT146_FN3,    MSEL4CR_15_1),
+        PINMUX_DATA(MMC1_D2_PORT147_MARK,       PORT147_FN3,    MSEL4CR_15_1),
+        PINMUX_DATA(MMC1_D1_PORT148_MARK,       PORT148_FN3,    MSEL4CR_15_1),
+        PINMUX_DATA(MMC1_D0_PORT149_MARK,       PORT149_FN3,    MSEL4CR_15_1),
+        /* Port158 */
+        PINMUX_DATA(D31_MARK,                   PORT158_FN1),
+        PINMUX_DATA(SCIFA3_SCK_PORT158_MARK,    PORT158_FN2,    MSEL5CR_8_1),
+        PINMUX_DATA(RMII_REF125CK_MARK,         PORT158_FN3),
+        PINMUX_DATA(LCD0_D21_PORT158_MARK,      PORT158_FN4,    MSEL5CR_6_1),
+        PINMUX_DATA(IRDA_FIRSEL_MARK,           PORT158_FN5),
+        PINMUX_DATA(IDE_D15_MARK,               PORT158_FN6),
+        /* Port159 */
+        PINMUX_DATA(D30_MARK,                   PORT159_FN1),
+        PINMUX_DATA(SCIFA3_RXD_PORT159_MARK,    PORT159_FN2,    MSEL5CR_8_1),
+        PINMUX_DATA(RMII_REF50CK_MARK,          PORT159_FN3),
+        PINMUX_DATA(LCD0_D23_PORT159_MARK,      PORT159_FN4,    MSEL5CR_6_1),
+        PINMUX_DATA(IDE_D14_MARK,               PORT159_FN6),
+        /* Port160 */
+        PINMUX_DATA(D29_MARK,                   PORT160_FN1),
+        PINMUX_DATA(SCIFA3_TXD_PORT160_MARK,    PORT160_FN2,    MSEL5CR_8_1),
+        PINMUX_DATA(LCD0_D22_PORT160_MARK,      PORT160_FN4,    MSEL5CR_6_1),
+        PINMUX_DATA(VIO1_HD_MARK,               PORT160_FN5),
+        PINMUX_DATA(IDE_D13_MARK,               PORT160_FN6),
+        /* Port161 */
+        PINMUX_DATA(D28_MARK,                   PORT161_FN1),
+        PINMUX_DATA(SCIFA3_RTS_PORT161_MARK,    PORT161_FN2,    MSEL5CR_8_1),
+        PINMUX_DATA(ET_RX_DV_MARK,              PORT161_FN3),
+        PINMUX_DATA(LCD0_D20_PORT161_MARK,      PORT161_FN4,    MSEL5CR_6_1),
+        PINMUX_DATA(IRDA_IN_MARK,               PORT161_FN5),
+        PINMUX_DATA(IDE_D12_MARK,               PORT161_FN6),
+        /* Port162 */
+        PINMUX_DATA(D27_MARK,                   PORT162_FN1),
+        PINMUX_DATA(SCIFA3_CTS_PORT162_MARK,    PORT162_FN2,    MSEL5CR_8_1),
+        PINMUX_DATA(LCD0_D19_PORT162_MARK,      PORT162_FN4,    MSEL5CR_6_1),
+        PINMUX_DATA(IRDA_OUT_MARK,              PORT162_FN5),
+        PINMUX_DATA(IDE_D11_MARK,               PORT162_FN6),
+        /* Port163 */
+        PINMUX_DATA(D26_MARK,                   PORT163_FN1),
+        PINMUX_DATA(MSIOF2_SS2_MARK,            PORT163_FN2),
+        PINMUX_DATA(ET_COL_MARK,                PORT163_FN3),
+        PINMUX_DATA(LCD0_D18_PORT163_MARK,      PORT163_FN4,    MSEL5CR_6_1),
+        PINMUX_DATA(IROUT_MARK,                 PORT163_FN5),
+        PINMUX_DATA(IDE_D10_MARK,               PORT163_FN6),
+        /* Port164 */
+        PINMUX_DATA(D25_MARK,                   PORT164_FN1),
+        PINMUX_DATA(MSIOF2_TSYNC_MARK,          PORT164_FN2),
+        PINMUX_DATA(ET_PHY_INT_MARK,            PORT164_FN3),
+        PINMUX_DATA(LCD0_RD_MARK,               PORT164_FN4),
+        PINMUX_DATA(IDE_D9_MARK,                PORT164_FN6),
+        /* Port165 */
+        PINMUX_DATA(D24_MARK,                   PORT165_FN1),
+        PINMUX_DATA(MSIOF2_RXD_MARK,            PORT165_FN2),
+        PINMUX_DATA(LCD0_LCLK_PORT165_MARK,     PORT165_FN4,    MSEL5CR_6_1),
+        PINMUX_DATA(IDE_D8_MARK,                PORT165_FN6),
+        /* Port166 - Port171 Function1 */
+        PINMUX_DATA(D21_MARK,                   PORT166_FN1),
+        PINMUX_DATA(D20_MARK,                   PORT167_FN1),
+        PINMUX_DATA(D19_MARK,                   PORT168_FN1),
+        PINMUX_DATA(D18_MARK,                   PORT169_FN1),
+        PINMUX_DATA(D17_MARK,                   PORT170_FN1),
+        PINMUX_DATA(D16_MARK,                   PORT171_FN1),
+        /* Port166 - Port171 Function3 */
+        PINMUX_DATA(ET_ETXD5_MARK,              PORT166_FN3),
+        PINMUX_DATA(ET_ETXD4_MARK,              PORT167_FN3),
+        PINMUX_DATA(ET_ETXD3_MARK,              PORT168_FN3),
+        PINMUX_DATA(ET_ETXD2_MARK,              PORT169_FN3),
+        PINMUX_DATA(ET_ETXD1_MARK,              PORT170_FN3),
+        PINMUX_DATA(ET_ETXD0_MARK,              PORT171_FN3),
+        /* Port166 - Port171 Function6 */
+        PINMUX_DATA(IDE_D5_MARK,                PORT166_FN6),
+        PINMUX_DATA(IDE_D4_MARK,                PORT167_FN6),
+        PINMUX_DATA(IDE_D3_MARK,                PORT168_FN6),
+        PINMUX_DATA(IDE_D2_MARK,                PORT169_FN6),
+        PINMUX_DATA(IDE_D1_MARK,                PORT170_FN6),
+        PINMUX_DATA(IDE_D0_MARK,                PORT171_FN6),
+        /* Port167 - Port171 IRQ */
+        PINMUX_DATA(IRQ31_PORT167_MARK,         PORT167_FN0,    MSEL1CR_31_0),
+        PINMUX_DATA(IRQ27_PORT168_MARK,         PORT168_FN0,    MSEL1CR_27_0),
+        PINMUX_DATA(IRQ28_PORT169_MARK,         PORT169_FN0,    MSEL1CR_28_0),
+        PINMUX_DATA(IRQ29_PORT170_MARK,         PORT170_FN0,    MSEL1CR_29_0),
+        PINMUX_DATA(IRQ30_PORT171_MARK,         PORT171_FN0,    MSEL1CR_30_0),
+        /* Port172 */
+        PINMUX_DATA(D23_MARK,                   PORT172_FN1),
+        PINMUX_DATA(SCIFB_RTS_PORT172_MARK,     PORT172_FN2,    MSEL5CR_17_1),
+        PINMUX_DATA(ET_ETXD7_MARK,              PORT172_FN3),
+        PINMUX_DATA(IDE_D7_MARK,                PORT172_FN6),
+        PINMUX_DATA(IRQ4_PORT172_MARK,          PORT172_FN0,    MSEL1CR_4_1),
+        /* Port173 */
+        PINMUX_DATA(D22_MARK,                   PORT173_FN1),
+        PINMUX_DATA(SCIFB_CTS_PORT173_MARK,     PORT173_FN2,    MSEL5CR_17_1),
+        PINMUX_DATA(ET_ETXD6_MARK,              PORT173_FN3),
+        PINMUX_DATA(IDE_D6_MARK,                PORT173_FN6),
+        PINMUX_DATA(IRQ6_PORT173_MARK,          PORT173_FN0,    MSEL1CR_6_1),
+        /* Port174 */
+        PINMUX_DATA(A26_MARK,                   PORT174_FN1),
+        PINMUX_DATA(MSIOF0_TXD_MARK,            PORT174_FN2),
+        PINMUX_DATA(ET_RX_CLK_MARK,             PORT174_FN3),
+        PINMUX_DATA(SCIFA3_RXD_PORT174_MARK,    PORT174_FN4,    MSEL5CR_8_0),
+        /* Port175 */
+        PINMUX_DATA(A0_MARK,                    PORT175_FN1),
+        PINMUX_DATA(BS_MARK,                    PORT175_FN2),
+        PINMUX_DATA(ET_WOL_MARK,                PORT175_FN3),
+        PINMUX_DATA(SCIFA3_TXD_PORT175_MARK,    PORT175_FN4,    MSEL5CR_8_0),
+        /* Port176 */
+        PINMUX_DATA(ET_GTX_CLK_MARK,            PORT176_FN3),
+        /* Port177 */
+        PINMUX_DATA(WAIT_PORT177_MARK,          PORT177_FN1,    MSEL5CR_2_0),
+        PINMUX_DATA(ET_LINK_MARK,               PORT177_FN3),
+        PINMUX_DATA(IDE_IOWR_MARK,              PORT177_FN6),
+        PINMUX_DATA(SDHI2_WP_PORT177_MARK,      PORT177_FN7,    MSEL5CR_19_1),
+        /* Port178 */
+        PINMUX_DATA(VIO0_D12_MARK,              PORT178_FN1),
+        PINMUX_DATA(VIO1_D4_MARK,               PORT178_FN5),
+        PINMUX_DATA(IDE_IORD_MARK,              PORT178_FN6),
+        /* Port179 */
+        PINMUX_DATA(VIO0_D11_MARK,              PORT179_FN1),
+        PINMUX_DATA(VIO1_D3_MARK,               PORT179_FN5),
+        PINMUX_DATA(IDE_IORDY_MARK,             PORT179_FN6),
+        /* Port180 */
+        PINMUX_DATA(VIO0_D10_MARK,              PORT180_FN1),
+        PINMUX_DATA(TPU0TO3_MARK,               PORT180_FN4),
+        PINMUX_DATA(VIO1_D2_MARK,               PORT180_FN5),
+        PINMUX_DATA(IDE_INT_MARK,               PORT180_FN6),
+        PINMUX_DATA(IRQ24_MARK,                 PORT180_FN0),
+        /* Port181 */
+        PINMUX_DATA(VIO0_D9_MARK,               PORT181_FN1),
+        PINMUX_DATA(VIO1_D1_MARK,               PORT181_FN5),
+        PINMUX_DATA(IDE_RST_MARK,               PORT181_FN6),
+        /* Port182 */
+        PINMUX_DATA(VIO0_D8_MARK,               PORT182_FN1),
+        PINMUX_DATA(VIO1_D0_MARK,               PORT182_FN5),
+        PINMUX_DATA(IDE_DIRECTION_MARK,         PORT182_FN6),
+        /* Port183 */
+        PINMUX_DATA(DREQ1_MARK,                 PORT183_FN1),
+        PINMUX_DATA(BBIF2_TXD2_PORT183_MARK,    PORT183_FN2,    MSEL5CR_0_1),
+        PINMUX_DATA(ET_TX_EN_MARK,              PORT183_FN3),
+        /* Port184 */
+        PINMUX_DATA(DACK1_MARK,                 PORT184_FN1),
+        PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK,  PORT184_FN2,    MSEL5CR_0_1),
+        PINMUX_DATA(ET_TX_CLK_MARK,             PORT184_FN3),
+        /* Port185 - Port192 Function1 */
+        PINMUX_DATA(SCIFA1_SCK_MARK,            PORT185_FN1),
+        PINMUX_DATA(SCIFB_RTS_PORT186_MARK,     PORT186_FN1,    MSEL5CR_17_0),
+        PINMUX_DATA(SCIFB_CTS_PORT187_MARK,     PORT187_FN1,    MSEL5CR_17_0),
+        PINMUX_DATA(SCIFA0_SCK_MARK,            PORT188_FN1),
+        PINMUX_DATA(SCIFB_SCK_PORT190_MARK,     PORT190_FN1,    MSEL5CR_17_0),
+        PINMUX_DATA(SCIFB_RXD_PORT191_MARK,     PORT191_FN1,    MSEL5CR_17_0),
+        PINMUX_DATA(SCIFB_TXD_PORT192_MARK,     PORT192_FN1,    MSEL5CR_17_0),
+        /* Port185 - Port192 Function3 */
+        PINMUX_DATA(ET_ERXD0_MARK,              PORT185_FN3),
+        PINMUX_DATA(ET_ERXD1_MARK,              PORT186_FN3),
+        PINMUX_DATA(ET_ERXD2_MARK,              PORT187_FN3),
+        PINMUX_DATA(ET_ERXD3_MARK,              PORT188_FN3),
+        PINMUX_DATA(ET_ERXD4_MARK,              PORT189_FN3),
+        PINMUX_DATA(ET_ERXD5_MARK,              PORT190_FN3),
+        PINMUX_DATA(ET_ERXD6_MARK,              PORT191_FN3),
+        PINMUX_DATA(ET_ERXD7_MARK,              PORT192_FN3),
+        /* Port185 - Port192 Function6 */
+        PINMUX_DATA(STP1_IPCLK_MARK,            PORT185_FN6),
+        PINMUX_DATA(STP1_IPD0_PORT186_MARK,     PORT186_FN6,    MSEL5CR_23_0),
+        PINMUX_DATA(STP1_IPEN_PORT187_MARK,     PORT187_FN6,    MSEL5CR_23_0),
+        PINMUX_DATA(STP1_IPSYNC_MARK,           PORT188_FN6),
+        PINMUX_DATA(STP0_IPCLK_MARK,            PORT189_FN6),
+        PINMUX_DATA(STP0_IPD0_MARK,             PORT190_FN6),
+        PINMUX_DATA(STP0_IPEN_MARK,             PORT191_FN6),
+        PINMUX_DATA(STP0_IPSYNC_MARK,           PORT192_FN6),
+        /* Port193 */
+        PINMUX_DATA(SCIFA0_CTS_MARK,            PORT193_FN1),
+        PINMUX_DATA(RMII_CRS_DV_MARK,           PORT193_FN3),
+        PINMUX_DATA(STP1_IPEN_PORT193_MARK,     PORT193_FN6,    MSEL5CR_23_1), /* ? */
+        PINMUX_DATA(LCD1_D17_MARK,              PORT193_FN7),
+        /* Port194 */
+        PINMUX_DATA(SCIFA0_RTS_MARK,            PORT194_FN1),
+        PINMUX_DATA(RMII_RX_ER_MARK,            PORT194_FN3),
+        PINMUX_DATA(STP1_IPD0_PORT194_MARK,     PORT194_FN6,    MSEL5CR_23_1), /* ? */
+        PINMUX_DATA(LCD1_D16_MARK,              PORT194_FN7),
+        /* Port195 */
+        PINMUX_DATA(SCIFA1_RXD_MARK,            PORT195_FN1),
+        PINMUX_DATA(RMII_RXD0_MARK,             PORT195_FN3),
+        PINMUX_DATA(STP1_IPD3_MARK,             PORT195_FN6),
+        PINMUX_DATA(LCD1_D15_MARK,              PORT195_FN7),
+        /* Port196 */
+        PINMUX_DATA(SCIFA1_TXD_MARK,            PORT196_FN1),
+        PINMUX_DATA(RMII_RXD1_MARK,             PORT196_FN3),
+        PINMUX_DATA(STP1_IPD2_MARK,             PORT196_FN6),
+        PINMUX_DATA(LCD1_D14_MARK,              PORT196_FN7),
+        /* Port197 */
+        PINMUX_DATA(SCIFA0_RXD_MARK,            PORT197_FN1),
+        PINMUX_DATA(VIO1_CLK_MARK,              PORT197_FN5),
+        PINMUX_DATA(STP1_IPD5_MARK,             PORT197_FN6),
+        PINMUX_DATA(LCD1_D19_MARK,              PORT197_FN7),
+        /* Port198 */
+        PINMUX_DATA(SCIFA0_TXD_MARK,            PORT198_FN1),
+        PINMUX_DATA(VIO1_VD_MARK,               PORT198_FN5),
+        PINMUX_DATA(STP1_IPD4_MARK,             PORT198_FN6),
+        PINMUX_DATA(LCD1_D18_MARK,              PORT198_FN7),
+        /* Port199 */
+        PINMUX_DATA(MEMC_NWE_MARK,              PORT199_FN1),
+        PINMUX_DATA(SCIFA2_SCK_PORT199_MARK,    PORT199_FN2,    MSEL5CR_7_1),
+        PINMUX_DATA(RMII_TX_EN_MARK,            PORT199_FN3),
+        PINMUX_DATA(SIM_D_PORT199_MARK,         PORT199_FN4,    MSEL5CR_21_1),
+        PINMUX_DATA(STP1_IPD1_MARK,             PORT199_FN6),
+        PINMUX_DATA(LCD1_D13_MARK,              PORT199_FN7),
+        /* Port200 */
+        PINMUX_DATA(MEMC_NOE_MARK,              PORT200_FN1),
+        PINMUX_DATA(SCIFA2_RXD_MARK,            PORT200_FN2),
+        PINMUX_DATA(RMII_TXD0_MARK,             PORT200_FN3),
+        PINMUX_DATA(STP0_IPD7_MARK,             PORT200_FN6),
+        PINMUX_DATA(LCD1_D12_MARK,              PORT200_FN7),
+        /* Port201 */
+        PINMUX_DATA(MEMC_WAIT_MARK,             PORT201_FN1,    MSEL4CR_6_0),
+        PINMUX_DATA(MEMC_DREQ1_MARK,            PORT201_FN1,    MSEL4CR_6_1),
+        PINMUX_DATA(SCIFA2_TXD_MARK,            PORT201_FN2),
+        PINMUX_DATA(RMII_TXD1_MARK,             PORT201_FN3),
+        PINMUX_DATA(STP0_IPD6_MARK,             PORT201_FN6),
+        PINMUX_DATA(LCD1_D11_MARK,              PORT201_FN7),
+        /* Port202 */
+        PINMUX_DATA(MEMC_BUSCLK_MARK,           PORT202_FN1,    MSEL4CR_6_0),
+        PINMUX_DATA(MEMC_A0_MARK,               PORT202_FN1,    MSEL4CR_6_1),
+        PINMUX_DATA(MSIOF1_SS2_PORT202_MARK,    PORT202_FN2,    MSEL4CR_10_1),
+        PINMUX_DATA(RMII_MDC_MARK,              PORT202_FN3),
+        PINMUX_DATA(TPU0TO2_PORT202_MARK,       PORT202_FN4,    MSEL5CR_25_1),
+        PINMUX_DATA(IDE_CS0_MARK,               PORT202_FN6),
+        PINMUX_DATA(SDHI2_CD_PORT202_MARK,      PORT202_FN7,    MSEL5CR_19_1),
+        PINMUX_DATA(IRQ21_MARK,                 PORT202_FN0),
+        /* Port203 - Port208 Function1 */
+        PINMUX_DATA(SDHI2_CLK_MARK,             PORT203_FN1),
+        PINMUX_DATA(SDHI2_CMD_MARK,             PORT204_FN1),
+        PINMUX_DATA(SDHI2_D0_MARK,              PORT205_FN1),
+        PINMUX_DATA(SDHI2_D1_MARK,              PORT206_FN1),
+        PINMUX_DATA(SDHI2_D2_MARK,              PORT207_FN1),
+        PINMUX_DATA(SDHI2_D3_MARK,              PORT208_FN1),
+        /* Port203 - Port208 Function3 */
+        PINMUX_DATA(ET_TX_ER_MARK,              PORT203_FN3),
+        PINMUX_DATA(ET_RX_ER_MARK,              PORT204_FN3),
+        PINMUX_DATA(ET_CRS_MARK,                PORT205_FN3),
+        PINMUX_DATA(ET_MDC_MARK,                PORT206_FN3),
+        PINMUX_DATA(ET_MDIO_MARK,               PORT207_FN3),
+        PINMUX_DATA(RMII_MDIO_MARK,             PORT208_FN3),
+        /* Port203 - Port208 Function6 */
+        PINMUX_DATA(IDE_A2_MARK,                PORT203_FN6),
+        PINMUX_DATA(IDE_A1_MARK,                PORT204_FN6),
+        PINMUX_DATA(IDE_A0_MARK,                PORT205_FN6),
+        PINMUX_DATA(IDE_IODACK_MARK,            PORT206_FN6),
+        PINMUX_DATA(IDE_IODREQ_MARK,            PORT207_FN6),
+        PINMUX_DATA(IDE_CS1_MARK,               PORT208_FN6),
+        /* Port203 - Port208 Function7 */
+        PINMUX_DATA(SCIFA4_TXD_PORT203_MARK,    PORT203_FN7,    MSEL5CR_12_0,   MSEL5CR_11_1),
+        PINMUX_DATA(SCIFA4_RXD_PORT204_MARK,    PORT204_FN7,    MSEL5CR_12_0,   MSEL5CR_11_1),
+        PINMUX_DATA(SCIFA4_SCK_PORT205_MARK,    PORT205_FN7,    MSEL5CR_10_1),
+        PINMUX_DATA(SCIFA5_SCK_PORT206_MARK,    PORT206_FN7,    MSEL5CR_13_1),
+        PINMUX_DATA(SCIFA5_RXD_PORT207_MARK,    PORT207_FN7,    MSEL5CR_15_0,   MSEL5CR_14_1),
+        PINMUX_DATA(SCIFA5_TXD_PORT208_MARK,    PORT208_FN7,    MSEL5CR_15_0,   MSEL5CR_14_1),
+        /* Port209 */
+        PINMUX_DATA(VBUS_MARK,                  PORT209_FN1),
+        PINMUX_DATA(IRQ7_PORT209_MARK,          PORT209_FN0,    MSEL1CR_7_1),
+        /* Port210 */
+        PINMUX_DATA(IRQ9_PORT210_MARK,          PORT210_FN0,    MSEL1CR_9_1),
+        /* Port211 */
+        PINMUX_DATA(IRQ16_PORT211_MARK,         PORT211_FN0,    MSEL1CR_16_1),
+        /* LCDC select */
+        PINMUX_DATA(LCDC0_SELECT_MARK,                          MSEL3CR_6_0),
+        PINMUX_DATA(LCDC1_SELECT_MARK,                          MSEL3CR_6_1),
+        /* SDENC */
+        PINMUX_DATA(SDENC_CPG_MARK,                             MSEL4CR_19_0),
+        PINMUX_DATA(SDENC_DV_CLKI_MARK,                         MSEL4CR_19_1),
+        /* SYSC */
+        PINMUX_DATA(RESETP_PULLUP_MARK,                         MSEL4CR_4_0),
+        PINMUX_DATA(RESETP_PLAIN_MARK,                          MSEL4CR_4_1),
+        /* DEBUG */
+        PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK,                     MSEL4CR_1_0),
+        PINMUX_DATA(EDEBGREQ_PULLUP_MARK,                       MSEL4CR_1_1),
+        PINMUX_DATA(TRACEAUD_FROM_VIO_MARK,                     MSEL5CR_30_0,   MSEL5CR_29_0),
+        PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK,                   MSEL5CR_30_0,   MSEL5CR_29_1),
+        PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,                    MSEL5CR_30_1,   MSEL5CR_29_0),
+};
+static struct pinmux_gpio pinmux_gpios[] = {
+        /* PORT */
+        GPIO_PORT_ALL(),
+        /* IRQ */
+        GPIO_FN(IRQ0_PORT2),    GPIO_FN(IRQ0_PORT13),
+        GPIO_FN(IRQ1),
+        GPIO_FN(IRQ2_PORT11),   GPIO_FN(IRQ2_PORT12),
+        GPIO_FN(IRQ3_PORT10),   GPIO_FN(IRQ3_PORT14),
+        GPIO_FN(IRQ4_PORT15),   GPIO_FN(IRQ4_PORT172),
+        GPIO_FN(IRQ5_PORT0),    GPIO_FN(IRQ5_PORT1),
+        GPIO_FN(IRQ6_PORT121),  GPIO_FN(IRQ6_PORT173),
+        GPIO_FN(IRQ7_PORT120),  GPIO_FN(IRQ7_PORT209),
+        GPIO_FN(IRQ8),
+        GPIO_FN(IRQ9_PORT118),  GPIO_FN(IRQ9_PORT210),
+        GPIO_FN(IRQ10),
+        GPIO_FN(IRQ11),
+        GPIO_FN(IRQ12_PORT42),  GPIO_FN(IRQ12_PORT97),
+        GPIO_FN(IRQ13_PORT64),  GPIO_FN(IRQ13_PORT98),
+        GPIO_FN(IRQ14_PORT63),  GPIO_FN(IRQ14_PORT99),
+        GPIO_FN(IRQ15_PORT62),  GPIO_FN(IRQ15_PORT100),
+        GPIO_FN(IRQ16_PORT68),  GPIO_FN(IRQ16_PORT211),
+        GPIO_FN(IRQ17),
+        GPIO_FN(IRQ18),
+        GPIO_FN(IRQ19),
+        GPIO_FN(IRQ20),
+        GPIO_FN(IRQ21),
+        GPIO_FN(IRQ22),
+        GPIO_FN(IRQ23),
+        GPIO_FN(IRQ24),
+        GPIO_FN(IRQ25),
+        GPIO_FN(IRQ26_PORT58),  GPIO_FN(IRQ26_PORT81),
+        GPIO_FN(IRQ27_PORT57),  GPIO_FN(IRQ27_PORT168),
+        GPIO_FN(IRQ28_PORT56),  GPIO_FN(IRQ28_PORT169),
+        GPIO_FN(IRQ29_PORT50),  GPIO_FN(IRQ29_PORT170),
+        GPIO_FN(IRQ30_PORT49),  GPIO_FN(IRQ30_PORT171),
+        GPIO_FN(IRQ31_PORT41),  GPIO_FN(IRQ31_PORT167),
+        /* Function */
+        /* DBGT */
+        GPIO_FN(DBGMDT2),       GPIO_FN(DBGMDT1),       GPIO_FN(DBGMDT0),
+        GPIO_FN(DBGMD10),       GPIO_FN(DBGMD11),       GPIO_FN(DBGMD20),
+        GPIO_FN(DBGMD21),
+        /* FSI */
+        GPIO_FN(FSIAISLD_PORT0),        /* FSIAISLD Port 0/5 */
+        GPIO_FN(FSIAISLD_PORT5),
+        GPIO_FN(FSIASPDIF_PORT9),       /* FSIASPDIF Port 9/18 */
+        GPIO_FN(FSIASPDIF_PORT18),
+        GPIO_FN(FSIAOSLD1),     GPIO_FN(FSIAOSLD2),     GPIO_FN(FSIAOLR),
+        GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),      GPIO_FN(FSIAOMC),
+        GPIO_FN(FSIACK),        GPIO_FN(FSIAILR),       GPIO_FN(FSIAIBT),
+        /* FMSI */
+        GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
+        GPIO_FN(FMSISLD_PORT6),
+        GPIO_FN(FMSIILR),       GPIO_FN(FMSIIBT),       GPIO_FN(FMSIOLR),
+        GPIO_FN(FMSIOBT),       GPIO_FN(FMSICK),        GPIO_FN(FMSOILR),
+        GPIO_FN(FMSOIBT),       GPIO_FN(FMSOOLR),       GPIO_FN(FMSOOBT),
+        GPIO_FN(FMSOSLD),       GPIO_FN(FMSOCK),
+        /* SCIFA0 */
+        GPIO_FN(SCIFA0_SCK),    GPIO_FN(SCIFA0_CTS),    GPIO_FN(SCIFA0_RTS),
+        GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_TXD),
+        /* SCIFA1 */
+        GPIO_FN(SCIFA1_CTS),    GPIO_FN(SCIFA1_SCK),
+        GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RTS),
+        /* SCIFA2 */
+        GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
+        GPIO_FN(SCIFA2_SCK_PORT199),
+        GPIO_FN(SCIFA2_RXD),    GPIO_FN(SCIFA2_TXD),
+        GPIO_FN(SCIFA2_CTS),    GPIO_FN(SCIFA2_RTS),
+        /* SCIFA3 */
+        GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
+        GPIO_FN(SCIFA3_SCK_PORT116),
+        GPIO_FN(SCIFA3_CTS_PORT117),
+        GPIO_FN(SCIFA3_RXD_PORT174),
+        GPIO_FN(SCIFA3_TXD_PORT175),
+        GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
+        GPIO_FN(SCIFA3_SCK_PORT158),
+        GPIO_FN(SCIFA3_CTS_PORT162),
+        GPIO_FN(SCIFA3_RXD_PORT159),
+        GPIO_FN(SCIFA3_TXD_PORT160),
+        /* SCIFA4 */
+        GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
+        GPIO_FN(SCIFA4_TXD_PORT13),
+        GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
+        GPIO_FN(SCIFA4_TXD_PORT203),
+        GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
+        GPIO_FN(SCIFA4_TXD_PORT93),
+        GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
+        GPIO_FN(SCIFA4_SCK_PORT205),
+        /* SCIFA5 */
+        GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
+        GPIO_FN(SCIFA5_RXD_PORT10),
+        GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
+        GPIO_FN(SCIFA5_TXD_PORT208),
+        GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
+        GPIO_FN(SCIFA5_RXD_PORT92),
+        GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
+        GPIO_FN(SCIFA5_SCK_PORT206),
+        /* SCIFA6 */
+        GPIO_FN(SCIFA6_SCK),    GPIO_FN(SCIFA6_RXD),    GPIO_FN(SCIFA6_TXD),
+        /* SCIFA7 */
+        GPIO_FN(SCIFA7_TXD),    GPIO_FN(SCIFA7_RXD),
+        /* SCIFAB */
+        GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
+        GPIO_FN(SCIFB_RXD_PORT191),
+        GPIO_FN(SCIFB_TXD_PORT192),
+        GPIO_FN(SCIFB_RTS_PORT186),
+        GPIO_FN(SCIFB_CTS_PORT187),
+        GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
+        GPIO_FN(SCIFB_RXD_PORT3),
+        GPIO_FN(SCIFB_TXD_PORT4),
+        GPIO_FN(SCIFB_RTS_PORT172),
+        GPIO_FN(SCIFB_CTS_PORT173),
+        /* LCD0 */
+        GPIO_FN(LCD0_D0),       GPIO_FN(LCD0_D1),       GPIO_FN(LCD0_D2),
+        GPIO_FN(LCD0_D3),       GPIO_FN(LCD0_D4),       GPIO_FN(LCD0_D5),
+        GPIO_FN(LCD0_D6),       GPIO_FN(LCD0_D7),       GPIO_FN(LCD0_D8),
+        GPIO_FN(LCD0_D9),       GPIO_FN(LCD0_D10),      GPIO_FN(LCD0_D11),
+        GPIO_FN(LCD0_D12),      GPIO_FN(LCD0_D13),      GPIO_FN(LCD0_D14),
+        GPIO_FN(LCD0_D15),      GPIO_FN(LCD0_D16),      GPIO_FN(LCD0_D17),
+        GPIO_FN(LCD0_DON),      GPIO_FN(LCD0_VCPWC),    GPIO_FN(LCD0_VEPWC),
+        GPIO_FN(LCD0_DCK),      GPIO_FN(LCD0_VSYN),
+        GPIO_FN(LCD0_HSYN),     GPIO_FN(LCD0_DISP),
+        GPIO_FN(LCD0_WR),       GPIO_FN(LCD0_RD),
+        GPIO_FN(LCD0_CS),       GPIO_FN(LCD0_RS),
+        GPIO_FN(LCD0_D18_PORT163),      GPIO_FN(LCD0_D19_PORT162),
+        GPIO_FN(LCD0_D20_PORT161),      GPIO_FN(LCD0_D21_PORT158),
+        GPIO_FN(LCD0_D22_PORT160),      GPIO_FN(LCD0_D23_PORT159),
+        GPIO_FN(LCD0_LCLK_PORT165),     /* MSEL5CR_6_1 */
+        GPIO_FN(LCD0_D18_PORT40),       GPIO_FN(LCD0_D19_PORT4),
+        GPIO_FN(LCD0_D20_PORT3),        GPIO_FN(LCD0_D21_PORT2),
+        GPIO_FN(LCD0_D22_PORT0),        GPIO_FN(LCD0_D23_PORT1),
+        GPIO_FN(LCD0_LCLK_PORT102),     /* MSEL5CR_6_0 */
+        /* LCD1 */
+        GPIO_FN(LCD1_D0),       GPIO_FN(LCD1_D1),       GPIO_FN(LCD1_D2),
+        GPIO_FN(LCD1_D3),       GPIO_FN(LCD1_D4),       GPIO_FN(LCD1_D5),
+        GPIO_FN(LCD1_D6),       GPIO_FN(LCD1_D7),       GPIO_FN(LCD1_D8),
+        GPIO_FN(LCD1_D9),       GPIO_FN(LCD1_D10),      GPIO_FN(LCD1_D11),
+        GPIO_FN(LCD1_D12),      GPIO_FN(LCD1_D13),      GPIO_FN(LCD1_D14),
+        GPIO_FN(LCD1_D15),      GPIO_FN(LCD1_D16),      GPIO_FN(LCD1_D17),
+        GPIO_FN(LCD1_D18),      GPIO_FN(LCD1_D19),      GPIO_FN(LCD1_D20),
+        GPIO_FN(LCD1_D21),      GPIO_FN(LCD1_D22),      GPIO_FN(LCD1_D23),
+        GPIO_FN(LCD1_RS),       GPIO_FN(LCD1_RD),       GPIO_FN(LCD1_CS),
+        GPIO_FN(LCD1_WR),       GPIO_FN(LCD1_DCK),      GPIO_FN(LCD1_DON),
+        GPIO_FN(LCD1_VCPWC),    GPIO_FN(LCD1_LCLK),     GPIO_FN(LCD1_HSYN),
+        GPIO_FN(LCD1_VSYN),     GPIO_FN(LCD1_VEPWC),    GPIO_FN(LCD1_DISP),
+        /* RSPI */
+        GPIO_FN(RSPI_SSL0_A),   GPIO_FN(RSPI_SSL1_A),   GPIO_FN(RSPI_SSL2_A),
+        GPIO_FN(RSPI_SSL3_A),   GPIO_FN(RSPI_CK_A),     GPIO_FN(RSPI_MOSI_A),
+        GPIO_FN(RSPI_MISO_A),
+        /* VIO CKO */
+        GPIO_FN(VIO_CKO1),
+        GPIO_FN(VIO_CKO2),
+        GPIO_FN(VIO_CKO_1),
+        GPIO_FN(VIO_CKO),
+        /* VIO0 */
+        GPIO_FN(VIO0_D0),       GPIO_FN(VIO0_D1),       GPIO_FN(VIO0_D2),
+        GPIO_FN(VIO0_D3),       GPIO_FN(VIO0_D4),       GPIO_FN(VIO0_D5),
+        GPIO_FN(VIO0_D6),       GPIO_FN(VIO0_D7),       GPIO_FN(VIO0_D8),
+        GPIO_FN(VIO0_D9),       GPIO_FN(VIO0_D10),      GPIO_FN(VIO0_D11),
+        GPIO_FN(VIO0_D12),      GPIO_FN(VIO0_VD),       GPIO_FN(VIO0_HD),
+        GPIO_FN(VIO0_CLK),      GPIO_FN(VIO0_FIELD),
+        GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
+        GPIO_FN(VIO0_D14_PORT25),
+        GPIO_FN(VIO0_D15_PORT24),
+        GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
+        GPIO_FN(VIO0_D14_PORT95),
+        GPIO_FN(VIO0_D15_PORT96),
+        /* VIO1 */
+        GPIO_FN(VIO1_D0),       GPIO_FN(VIO1_D1),       GPIO_FN(VIO1_D2),
+        GPIO_FN(VIO1_D3),       GPIO_FN(VIO1_D4),       GPIO_FN(VIO1_D5),
+        GPIO_FN(VIO1_D6),       GPIO_FN(VIO1_D7),       GPIO_FN(VIO1_VD),
+        GPIO_FN(VIO1_HD),       GPIO_FN(VIO1_CLK),      GPIO_FN(VIO1_FIELD),
+        /* TPU0 */
+        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO3),
+        GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
+        GPIO_FN(TPU0TO2_PORT202),
+        /* SSP1 0 */
+        GPIO_FN(STP0_IPD0),     GPIO_FN(STP0_IPD1),     GPIO_FN(STP0_IPD2),
+        GPIO_FN(STP0_IPD3),     GPIO_FN(STP0_IPD4),     GPIO_FN(STP0_IPD5),
+        GPIO_FN(STP0_IPD6),     GPIO_FN(STP0_IPD7),     GPIO_FN(STP0_IPEN),
+        GPIO_FN(STP0_IPCLK),    GPIO_FN(STP0_IPSYNC),
+        /* SSP1 1 */
+        GPIO_FN(STP1_IPD1),     GPIO_FN(STP1_IPD2),     GPIO_FN(STP1_IPD3),
+        GPIO_FN(STP1_IPD4),     GPIO_FN(STP1_IPD5),     GPIO_FN(STP1_IPD6),
+        GPIO_FN(STP1_IPD7),     GPIO_FN(STP1_IPCLK),    GPIO_FN(STP1_IPSYNC),
+        GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
+        GPIO_FN(STP1_IPEN_PORT187),
+        GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
+        GPIO_FN(STP1_IPEN_PORT193),
+        /* SIM */
+        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),
+        GPIO_FN(SIM_D_PORT22), /* SIM_D  Port 22/199 */
+        GPIO_FN(SIM_D_PORT199),
+        /* SDHI0 */
+        GPIO_FN(SDHI0_D0),      GPIO_FN(SDHI0_D1),      GPIO_FN(SDHI0_D2),
+        GPIO_FN(SDHI0_D3),      GPIO_FN(SDHI0_CD),      GPIO_FN(SDHI0_WP),
+        GPIO_FN(SDHI0_CMD),     GPIO_FN(SDHI0_CLK),
+        /* SDHI1 */
+        GPIO_FN(SDHI1_D0),      GPIO_FN(SDHI1_D1),      GPIO_FN(SDHI1_D2),
+        GPIO_FN(SDHI1_D3),      GPIO_FN(SDHI1_CD),      GPIO_FN(SDHI1_WP),
+        GPIO_FN(SDHI1_CMD),     GPIO_FN(SDHI1_CLK),
+        /* SDHI2 */
+        GPIO_FN(SDHI2_D0),      GPIO_FN(SDHI2_D1),      GPIO_FN(SDHI2_D2),
+        GPIO_FN(SDHI2_D3),      GPIO_FN(SDHI2_CLK),     GPIO_FN(SDHI2_CMD),
+        GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
+        GPIO_FN(SDHI2_WP_PORT25),
+        GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
+        GPIO_FN(SDHI2_CD_PORT202),
+        /* MSIOF2 */
+        GPIO_FN(MSIOF2_TXD),    GPIO_FN(MSIOF2_RXD),    GPIO_FN(MSIOF2_TSCK),
+        GPIO_FN(MSIOF2_SS2),    GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_SS1),
+        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_MCK0),   GPIO_FN(MSIOF2_RSYNC),
+        GPIO_FN(MSIOF2_RSCK),
+        /* KEYSC */
+        GPIO_FN(KEYIN4),        GPIO_FN(KEYIN5),
+        GPIO_FN(KEYIN6),        GPIO_FN(KEYIN7),
+        GPIO_FN(KEYOUT0),       GPIO_FN(KEYOUT1),       GPIO_FN(KEYOUT2),
+        GPIO_FN(KEYOUT3),       GPIO_FN(KEYOUT4),       GPIO_FN(KEYOUT5),
+        GPIO_FN(KEYOUT6),       GPIO_FN(KEYOUT7),
+        GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
+        GPIO_FN(KEYIN1_PORT44),
+        GPIO_FN(KEYIN2_PORT45),
+        GPIO_FN(KEYIN3_PORT46),
+        GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
+        GPIO_FN(KEYIN1_PORT57),
+        GPIO_FN(KEYIN2_PORT56),
+        GPIO_FN(KEYIN3_PORT55),
+        /* VOU */
+        GPIO_FN(DV_D0),         GPIO_FN(DV_D1),         GPIO_FN(DV_D2),
+        GPIO_FN(DV_D3),         GPIO_FN(DV_D4),         GPIO_FN(DV_D5),
+        GPIO_FN(DV_D6),         GPIO_FN(DV_D7),         GPIO_FN(DV_D8),
+        GPIO_FN(DV_D9),         GPIO_FN(DV_D10),        GPIO_FN(DV_D11),
+        GPIO_FN(DV_D12),        GPIO_FN(DV_D13),        GPIO_FN(DV_D14),
+        GPIO_FN(DV_D15),        GPIO_FN(DV_CLK),
+        GPIO_FN(DV_VSYNC),      GPIO_FN(DV_HSYNC),
+        /* MEMC */
+        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
+        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
+        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
+        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
+        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
+        GPIO_FN(MEMC_AD15),     GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_INT),
+        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_NOE),      GPIO_FN(MEMC_CS1),
+        GPIO_FN(MEMC_A1),       GPIO_FN(MEMC_ADV),      GPIO_FN(MEMC_DREQ0),
+        GPIO_FN(MEMC_WAIT),     GPIO_FN(MEMC_DREQ1),    GPIO_FN(MEMC_BUSCLK),
+        GPIO_FN(MEMC_A0),
+        /* MMC */
+        GPIO_FN(MMC0_D0_PORT68),        GPIO_FN(MMC0_D1_PORT69),
+        GPIO_FN(MMC0_D2_PORT70),        GPIO_FN(MMC0_D3_PORT71),
+        GPIO_FN(MMC0_D4_PORT72),        GPIO_FN(MMC0_D5_PORT73),
+        GPIO_FN(MMC0_D6_PORT74),        GPIO_FN(MMC0_D7_PORT75),
+        GPIO_FN(MMC0_CLK_PORT66),
+        GPIO_FN(MMC0_CMD_PORT67),       /* MSEL4CR_15_0 */
+        GPIO_FN(MMC1_D0_PORT149),       GPIO_FN(MMC1_D1_PORT148),
+        GPIO_FN(MMC1_D2_PORT147),       GPIO_FN(MMC1_D3_PORT146),
+        GPIO_FN(MMC1_D4_PORT145),       GPIO_FN(MMC1_D5_PORT144),
+        GPIO_FN(MMC1_D6_PORT143),       GPIO_FN(MMC1_D7_PORT142),
+        GPIO_FN(MMC1_CLK_PORT103),
+        GPIO_FN(MMC1_CMD_PORT104),      /* MSEL4CR_15_1 */
+        /* MSIOF0 */
+        GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),    GPIO_FN(MSIOF0_RXD),
+        GPIO_FN(MSIOF0_TXD),    GPIO_FN(MSIOF0_MCK0),   GPIO_FN(MSIOF0_MCK1),
+        GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_TSCK),
+        GPIO_FN(MSIOF0_TSYNC),
+        /* MSIOF1 */
+        GPIO_FN(MSIOF1_RSCK),   GPIO_FN(MSIOF1_RSYNC),
+        GPIO_FN(MSIOF1_MCK0),   GPIO_FN(MSIOF1_MCK1),
+        GPIO_FN(MSIOF1_SS2_PORT116),    GPIO_FN(MSIOF1_SS1_PORT117),
+        GPIO_FN(MSIOF1_RXD_PORT118),    GPIO_FN(MSIOF1_TXD_PORT119),
+        GPIO_FN(MSIOF1_TSYNC_PORT120),
+        GPIO_FN(MSIOF1_TSCK_PORT121),   /* MSEL4CR_10_0 */
+        GPIO_FN(MSIOF1_SS1_PORT67),     GPIO_FN(MSIOF1_TSCK_PORT72),
+        GPIO_FN(MSIOF1_TSYNC_PORT73),   GPIO_FN(MSIOF1_TXD_PORT74),
+        GPIO_FN(MSIOF1_RXD_PORT75),
+        GPIO_FN(MSIOF1_SS2_PORT202),    /* MSEL4CR_10_1 */
+        /* GPIO */
+        GPIO_FN(GPO0),  GPIO_FN(GPI0),
+        GPIO_FN(GPO1),  GPIO_FN(GPI1),
+        /* USB0 */
+        GPIO_FN(USB0_OCI),      GPIO_FN(USB0_PPON),     GPIO_FN(VBUS),
+        /* USB1 */
+        GPIO_FN(USB1_OCI),      GPIO_FN(USB1_PPON),
+        /* BBIF1 */
+        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_TSYNC),
+        GPIO_FN(BBIF1_TSCK),    GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
+        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BBIF1_RX_FLOW_N),
+        /* BBIF2 */
+        GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
+        GPIO_FN(BBIF2_RXD2_PORT60),
+        GPIO_FN(BBIF2_TSYNC2_PORT6),
+        GPIO_FN(BBIF2_TSCK2_PORT59),
+        GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
+        GPIO_FN(BBIF2_TXD2_PORT183),
+        GPIO_FN(BBIF2_TSCK2_PORT89),
+        GPIO_FN(BBIF2_TSYNC2_PORT184),
+        /* BSC / FLCTL / PCMCIA */
+        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
+        GPIO_FN(CS5B),  GPIO_FN(CS6A),
+        GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
+        GPIO_FN(CS5A_PORT19),
+        GPIO_FN(IOIS16), /* ? */
+        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),    GPIO_FN(A3),
+        GPIO_FN(A4_FOE),        GPIO_FN(A5_FCDE),       /* share with FLCTL */
+        GPIO_FN(A6),    GPIO_FN(A7),    GPIO_FN(A8),    GPIO_FN(A9),
+        GPIO_FN(A10),   GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
+        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),   GPIO_FN(A17),
+        GPIO_FN(A18),   GPIO_FN(A19),   GPIO_FN(A20),   GPIO_FN(A21),
+        GPIO_FN(A22),   GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
+        GPIO_FN(A26),
+        GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),       /* share with FLCTL */
+        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       /* share with FLCTL */
+        GPIO_FN(D4_NAF4),       GPIO_FN(D5_NAF5),       /* share with FLCTL */
+        GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),       /* share with FLCTL */
+        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       /* share with FLCTL */
+        GPIO_FN(D10_NAF10),     GPIO_FN(D11_NAF11),     /* share with FLCTL */
+        GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),     /* share with FLCTL */
+        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),     /* share with FLCTL */
+        GPIO_FN(D16),   GPIO_FN(D17),   GPIO_FN(D18),   GPIO_FN(D19),
+        GPIO_FN(D20),   GPIO_FN(D21),   GPIO_FN(D22),   GPIO_FN(D23),
+        GPIO_FN(D24),   GPIO_FN(D25),   GPIO_FN(D26),   GPIO_FN(D27),
+        GPIO_FN(D28),   GPIO_FN(D29),   GPIO_FN(D30),   GPIO_FN(D31),
+        GPIO_FN(WE0_FWE),       /* share with FLCTL */
+        GPIO_FN(WE1),
+        GPIO_FN(WE2_ICIORD),    /* share with PCMCIA */
+        GPIO_FN(WE3_ICIOWR),    /* share with PCMCIA */
+        GPIO_FN(CKO),   GPIO_FN(BS),    GPIO_FN(RDWR),
+        GPIO_FN(RD_FSC),        /* share with FLCTL */
+        GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
+        GPIO_FN(WAIT_PORT90),
+        GPIO_FN(FCE0),  GPIO_FN(FCE1),  GPIO_FN(FRB), /* FLCTL */
+        /* IRDA */
+        GPIO_FN(IRDA_FIRSEL),   GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_OUT),
+        /* ATAPI */
+        GPIO_FN(IDE_D0),        GPIO_FN(IDE_D1),        GPIO_FN(IDE_D2),
+        GPIO_FN(IDE_D3),        GPIO_FN(IDE_D4),        GPIO_FN(IDE_D5),
+        GPIO_FN(IDE_D6),        GPIO_FN(IDE_D7),        GPIO_FN(IDE_D8),
+        GPIO_FN(IDE_D9),        GPIO_FN(IDE_D10),       GPIO_FN(IDE_D11),
+        GPIO_FN(IDE_D12),       GPIO_FN(IDE_D13),       GPIO_FN(IDE_D14),
+        GPIO_FN(IDE_D15),       GPIO_FN(IDE_A0),        GPIO_FN(IDE_A1),
+        GPIO_FN(IDE_A2),        GPIO_FN(IDE_CS0),       GPIO_FN(IDE_CS1),
+        GPIO_FN(IDE_IOWR),      GPIO_FN(IDE_IORD),      GPIO_FN(IDE_IORDY),
+        GPIO_FN(IDE_INT),       GPIO_FN(IDE_RST),       GPIO_FN(IDE_DIRECTION),
+        GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK),    GPIO_FN(IDE_IODREQ),
+        /* RMII */
+        GPIO_FN(RMII_CRS_DV),   GPIO_FN(RMII_RX_ER),    GPIO_FN(RMII_RXD0),
+        GPIO_FN(RMII_RXD1),     GPIO_FN(RMII_TX_EN),    GPIO_FN(RMII_TXD0),
+        GPIO_FN(RMII_MDC),      GPIO_FN(RMII_TXD1),     GPIO_FN(RMII_MDIO),
+        GPIO_FN(RMII_REF50CK),  GPIO_FN(RMII_REF125CK), /* for GMII */
+        /* GEther */
+        GPIO_FN(ET_TX_CLK),     GPIO_FN(ET_TX_EN),      GPIO_FN(ET_ETXD0),
+        GPIO_FN(ET_ETXD1),      GPIO_FN(ET_ETXD2),      GPIO_FN(ET_ETXD3),
+        GPIO_FN(ET_ETXD4),      GPIO_FN(ET_ETXD5), /* for GEther */
+        GPIO_FN(ET_ETXD6),      GPIO_FN(ET_ETXD7), /* for GEther */
+        GPIO_FN(ET_COL),        GPIO_FN(ET_TX_ER),      GPIO_FN(ET_RX_CLK),
+        GPIO_FN(ET_RX_DV),      GPIO_FN(ET_ERXD0),      GPIO_FN(ET_ERXD1),
+        GPIO_FN(ET_ERXD2),      GPIO_FN(ET_ERXD3),
+        GPIO_FN(ET_ERXD4),      GPIO_FN(ET_ERXD5), /* for GEther */
+        GPIO_FN(ET_ERXD6),      GPIO_FN(ET_ERXD7), /* for GEther */
+        GPIO_FN(ET_RX_ER),      GPIO_FN(ET_CRS),        GPIO_FN(ET_MDC),
+        GPIO_FN(ET_MDIO),       GPIO_FN(ET_LINK),       GPIO_FN(ET_PHY_INT),
+        GPIO_FN(ET_WOL),        GPIO_FN(ET_GTX_CLK),
+        /* DMA0 */
+        GPIO_FN(DREQ0), GPIO_FN(DACK0),
+        /* DMA1 */
+        GPIO_FN(DREQ1), GPIO_FN(DACK1),
+        /* SYSC */
+        GPIO_FN(RESETOUTS),
+        /* IRREM */
+        GPIO_FN(IROUT),
+        /* LCDC */
+        GPIO_FN(LCDC0_SELECT),
+        GPIO_FN(LCDC1_SELECT),
+        /* SDENC */
+        GPIO_FN(SDENC_CPG),
+        GPIO_FN(SDENC_DV_CLKI),
+        /* SYSC */
+        GPIO_FN(RESETP_PULLUP),
+        GPIO_FN(RESETP_PLAIN),
+        /* DEBUG */
+        GPIO_FN(EDEBGREQ_PULLDOWN),
+        GPIO_FN(EDEBGREQ_PULLUP),
+        GPIO_FN(TRACEAUD_FROM_VIO),
+        GPIO_FN(TRACEAUD_FROM_LCDC0),
+        GPIO_FN(TRACEAUD_FROM_MEMC),
+};
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        PORTCR(0,       0xe6050000), /* PORT0CR */
+        PORTCR(1,       0xe6050001), /* PORT1CR */
+        PORTCR(2,       0xe6050002), /* PORT2CR */
+        PORTCR(3,       0xe6050003), /* PORT3CR */
+        PORTCR(4,       0xe6050004), /* PORT4CR */
+        PORTCR(5,       0xe6050005), /* PORT5CR */
+        PORTCR(6,       0xe6050006), /* PORT6CR */
+        PORTCR(7,       0xe6050007), /* PORT7CR */
+        PORTCR(8,       0xe6050008), /* PORT8CR */
+        PORTCR(9,       0xe6050009), /* PORT9CR */
+        PORTCR(10,      0xe605000a), /* PORT10CR */
+        PORTCR(11,      0xe605000b), /* PORT11CR */
+        PORTCR(12,      0xe605000c), /* PORT12CR */
+        PORTCR(13,      0xe605000d), /* PORT13CR */
+        PORTCR(14,      0xe605000e), /* PORT14CR */
+        PORTCR(15,      0xe605000f), /* PORT15CR */
+        PORTCR(16,      0xe6050010), /* PORT16CR */
+        PORTCR(17,      0xe6050011), /* PORT17CR */
+        PORTCR(18,      0xe6050012), /* PORT18CR */
+        PORTCR(19,      0xe6050013), /* PORT19CR */
+        PORTCR(20,      0xe6050014), /* PORT20CR */
+        PORTCR(21,      0xe6050015), /* PORT21CR */
+        PORTCR(22,      0xe6050016), /* PORT22CR */
+        PORTCR(23,      0xe6050017), /* PORT23CR */
+        PORTCR(24,      0xe6050018), /* PORT24CR */
+        PORTCR(25,      0xe6050019), /* PORT25CR */
+        PORTCR(26,      0xe605001a), /* PORT26CR */
+        PORTCR(27,      0xe605001b), /* PORT27CR */
+        PORTCR(28,      0xe605001c), /* PORT28CR */
+        PORTCR(29,      0xe605001d), /* PORT29CR */
+        PORTCR(30,      0xe605001e), /* PORT30CR */
+        PORTCR(31,      0xe605001f), /* PORT31CR */
+        PORTCR(32,      0xe6050020), /* PORT32CR */
+        PORTCR(33,      0xe6050021), /* PORT33CR */
+        PORTCR(34,      0xe6050022), /* PORT34CR */
+        PORTCR(35,      0xe6050023), /* PORT35CR */
+        PORTCR(36,      0xe6050024), /* PORT36CR */
+        PORTCR(37,      0xe6050025), /* PORT37CR */
+        PORTCR(38,      0xe6050026), /* PORT38CR */
+        PORTCR(39,      0xe6050027), /* PORT39CR */
+        PORTCR(40,      0xe6050028), /* PORT40CR */
+        PORTCR(41,      0xe6050029), /* PORT41CR */
+        PORTCR(42,      0xe605002a), /* PORT42CR */
+        PORTCR(43,      0xe605002b), /* PORT43CR */
+        PORTCR(44,      0xe605002c), /* PORT44CR */
+        PORTCR(45,      0xe605002d), /* PORT45CR */
+        PORTCR(46,      0xe605002e), /* PORT46CR */
+        PORTCR(47,      0xe605002f), /* PORT47CR */
+        PORTCR(48,      0xe6050030), /* PORT48CR */
+        PORTCR(49,      0xe6050031), /* PORT49CR */
+        PORTCR(50,      0xe6050032), /* PORT50CR */
+        PORTCR(51,      0xe6050033), /* PORT51CR */
+        PORTCR(52,      0xe6050034), /* PORT52CR */
+        PORTCR(53,      0xe6050035), /* PORT53CR */
+        PORTCR(54,      0xe6050036), /* PORT54CR */
+        PORTCR(55,      0xe6050037), /* PORT55CR */
+        PORTCR(56,      0xe6050038), /* PORT56CR */
+        PORTCR(57,      0xe6050039), /* PORT57CR */
+        PORTCR(58,      0xe605003a), /* PORT58CR */
+        PORTCR(59,      0xe605003b), /* PORT59CR */
+        PORTCR(60,      0xe605003c), /* PORT60CR */
+        PORTCR(61,      0xe605003d), /* PORT61CR */
+        PORTCR(62,      0xe605003e), /* PORT62CR */
+        PORTCR(63,      0xe605003f), /* PORT63CR */
+        PORTCR(64,      0xe6050040), /* PORT64CR */
+        PORTCR(65,      0xe6050041), /* PORT65CR */
+        PORTCR(66,      0xe6050042), /* PORT66CR */
+        PORTCR(67,      0xe6050043), /* PORT67CR */
+        PORTCR(68,      0xe6050044), /* PORT68CR */
+        PORTCR(69,      0xe6050045), /* PORT69CR */
+        PORTCR(70,      0xe6050046), /* PORT70CR */
+        PORTCR(71,      0xe6050047), /* PORT71CR */
+        PORTCR(72,      0xe6050048), /* PORT72CR */
+        PORTCR(73,      0xe6050049), /* PORT73CR */
+        PORTCR(74,      0xe605004a), /* PORT74CR */
+        PORTCR(75,      0xe605004b), /* PORT75CR */
+        PORTCR(76,      0xe605004c), /* PORT76CR */
+        PORTCR(77,      0xe605004d), /* PORT77CR */
+        PORTCR(78,      0xe605004e), /* PORT78CR */
+        PORTCR(79,      0xe605004f), /* PORT79CR */
+        PORTCR(80,      0xe6050050), /* PORT80CR */
+        PORTCR(81,      0xe6050051), /* PORT81CR */
+        PORTCR(82,      0xe6050052), /* PORT82CR */
+        PORTCR(83,      0xe6050053), /* PORT83CR */
+        PORTCR(84,      0xe6051054), /* PORT84CR */
+        PORTCR(85,      0xe6051055), /* PORT85CR */
+        PORTCR(86,      0xe6051056), /* PORT86CR */
+        PORTCR(87,      0xe6051057), /* PORT87CR */
+        PORTCR(88,      0xe6051058), /* PORT88CR */
+        PORTCR(89,      0xe6051059), /* PORT89CR */
+        PORTCR(90,      0xe605105a), /* PORT90CR */
+        PORTCR(91,      0xe605105b), /* PORT91CR */
+        PORTCR(92,      0xe605105c), /* PORT92CR */
+        PORTCR(93,      0xe605105d), /* PORT93CR */
+        PORTCR(94,      0xe605105e), /* PORT94CR */
+        PORTCR(95,      0xe605105f), /* PORT95CR */
+        PORTCR(96,      0xe6051060), /* PORT96CR */
+        PORTCR(97,      0xe6051061), /* PORT97CR */
+        PORTCR(98,      0xe6051062), /* PORT98CR */
+        PORTCR(99,      0xe6051063), /* PORT99CR */
+        PORTCR(100,     0xe6051064), /* PORT100CR */
+        PORTCR(101,     0xe6051065), /* PORT101CR */
+        PORTCR(102,     0xe6051066), /* PORT102CR */
+        PORTCR(103,     0xe6051067), /* PORT103CR */
+        PORTCR(104,     0xe6051068), /* PORT104CR */
+        PORTCR(105,     0xe6051069), /* PORT105CR */
+        PORTCR(106,     0xe605106a), /* PORT106CR */
+        PORTCR(107,     0xe605106b), /* PORT107CR */
+        PORTCR(108,     0xe605106c), /* PORT108CR */
+        PORTCR(109,     0xe605106d), /* PORT109CR */
+        PORTCR(110,     0xe605106e), /* PORT110CR */
+        PORTCR(111,     0xe605106f), /* PORT111CR */
+        PORTCR(112,     0xe6051070), /* PORT112CR */
+        PORTCR(113,     0xe6051071), /* PORT113CR */
+        PORTCR(114,     0xe6051072), /* PORT114CR */
+        PORTCR(115,     0xe6052073), /* PORT115CR */
+        PORTCR(116,     0xe6052074), /* PORT116CR */
+        PORTCR(117,     0xe6052075), /* PORT117CR */
+        PORTCR(118,     0xe6052076), /* PORT118CR */
+        PORTCR(119,     0xe6052077), /* PORT119CR */
+        PORTCR(120,     0xe6052078), /* PORT120CR */
+        PORTCR(121,     0xe6052079), /* PORT121CR */
+        PORTCR(122,     0xe605207a), /* PORT122CR */
+        PORTCR(123,     0xe605207b), /* PORT123CR */
+        PORTCR(124,     0xe605207c), /* PORT124CR */
+        PORTCR(125,     0xe605207d), /* PORT125CR */
+        PORTCR(126,     0xe605207e), /* PORT126CR */
+        PORTCR(127,     0xe605207f), /* PORT127CR */
+        PORTCR(128,     0xe6052080), /* PORT128CR */
+        PORTCR(129,     0xe6052081), /* PORT129CR */
+        PORTCR(130,     0xe6052082), /* PORT130CR */
+        PORTCR(131,     0xe6052083), /* PORT131CR */
+        PORTCR(132,     0xe6052084), /* PORT132CR */
+        PORTCR(133,     0xe6052085), /* PORT133CR */
+        PORTCR(134,     0xe6052086), /* PORT134CR */
+        PORTCR(135,     0xe6052087), /* PORT135CR */
+        PORTCR(136,     0xe6052088), /* PORT136CR */
+        PORTCR(137,     0xe6052089), /* PORT137CR */
+        PORTCR(138,     0xe605208a), /* PORT138CR */
+        PORTCR(139,     0xe605208b), /* PORT139CR */
+        PORTCR(140,     0xe605208c), /* PORT140CR */
+        PORTCR(141,     0xe605208d), /* PORT141CR */
+        PORTCR(142,     0xe605208e), /* PORT142CR */
+        PORTCR(143,     0xe605208f), /* PORT143CR */
+        PORTCR(144,     0xe6052090), /* PORT144CR */
+        PORTCR(145,     0xe6052091), /* PORT145CR */
+        PORTCR(146,     0xe6052092), /* PORT146CR */
+        PORTCR(147,     0xe6052093), /* PORT147CR */
+        PORTCR(148,     0xe6052094), /* PORT148CR */
+        PORTCR(149,     0xe6052095), /* PORT149CR */
+        PORTCR(150,     0xe6052096), /* PORT150CR */
+        PORTCR(151,     0xe6052097), /* PORT151CR */
+        PORTCR(152,     0xe6052098), /* PORT152CR */
+        PORTCR(153,     0xe6052099), /* PORT153CR */
+        PORTCR(154,     0xe605209a), /* PORT154CR */
+        PORTCR(155,     0xe605209b), /* PORT155CR */
+        PORTCR(156,     0xe605209c), /* PORT156CR */
+        PORTCR(157,     0xe605209d), /* PORT157CR */
+        PORTCR(158,     0xe605209e), /* PORT158CR */
+        PORTCR(159,     0xe605209f), /* PORT159CR */
+        PORTCR(160,     0xe60520a0), /* PORT160CR */
+        PORTCR(161,     0xe60520a1), /* PORT161CR */
+        PORTCR(162,     0xe60520a2), /* PORT162CR */
+        PORTCR(163,     0xe60520a3), /* PORT163CR */
+        PORTCR(164,     0xe60520a4), /* PORT164CR */
+        PORTCR(165,     0xe60520a5), /* PORT165CR */
+        PORTCR(166,     0xe60520a6), /* PORT166CR */
+        PORTCR(167,     0xe60520a7), /* PORT167CR */
+        PORTCR(168,     0xe60520a8), /* PORT168CR */
+        PORTCR(169,     0xe60520a9), /* PORT169CR */
+        PORTCR(170,     0xe60520aa), /* PORT170CR */
+        PORTCR(171,     0xe60520ab), /* PORT171CR */
+        PORTCR(172,     0xe60520ac), /* PORT172CR */
+        PORTCR(173,     0xe60520ad), /* PORT173CR */
+        PORTCR(174,     0xe60520ae), /* PORT174CR */
+        PORTCR(175,     0xe60520af), /* PORT175CR */
+        PORTCR(176,     0xe60520b0), /* PORT176CR */
+        PORTCR(177,     0xe60520b1), /* PORT177CR */
+        PORTCR(178,     0xe60520b2), /* PORT178CR */
+        PORTCR(179,     0xe60520b3), /* PORT179CR */
+        PORTCR(180,     0xe60520b4), /* PORT180CR */
+        PORTCR(181,     0xe60520b5), /* PORT181CR */
+        PORTCR(182,     0xe60520b6), /* PORT182CR */
+        PORTCR(183,     0xe60520b7), /* PORT183CR */
+        PORTCR(184,     0xe60520b8), /* PORT184CR */
+        PORTCR(185,     0xe60520b9), /* PORT185CR */
+        PORTCR(186,     0xe60520ba), /* PORT186CR */
+        PORTCR(187,     0xe60520bb), /* PORT187CR */
+        PORTCR(188,     0xe60520bc), /* PORT188CR */
+        PORTCR(189,     0xe60520bd), /* PORT189CR */
+        PORTCR(190,     0xe60520be), /* PORT190CR */
+        PORTCR(191,     0xe60520bf), /* PORT191CR */
+        PORTCR(192,     0xe60520c0), /* PORT192CR */
+        PORTCR(193,     0xe60520c1), /* PORT193CR */
+        PORTCR(194,     0xe60520c2), /* PORT194CR */
+        PORTCR(195,     0xe60520c3), /* PORT195CR */
+        PORTCR(196,     0xe60520c4), /* PORT196CR */
+        PORTCR(197,     0xe60520c5), /* PORT197CR */
+        PORTCR(198,     0xe60520c6), /* PORT198CR */
+        PORTCR(199,     0xe60520c7), /* PORT199CR */
+        PORTCR(200,     0xe60520c8), /* PORT200CR */
+        PORTCR(201,     0xe60520c9), /* PORT201CR */
+        PORTCR(202,     0xe60520ca), /* PORT202CR */
+        PORTCR(203,     0xe60520cb), /* PORT203CR */
+        PORTCR(204,     0xe60520cc), /* PORT204CR */
+        PORTCR(205,     0xe60520cd), /* PORT205CR */
+        PORTCR(206,     0xe60520ce), /* PORT206CR */
+        PORTCR(207,     0xe60520cf), /* PORT207CR */
+        PORTCR(208,     0xe60520d0), /* PORT208CR */
+        PORTCR(209,     0xe60520d1), /* PORT209CR */
+        PORTCR(210,     0xe60530d2), /* PORT210CR */
+        PORTCR(211,     0xe60530d3), /* PORT211CR */
+        { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
+                        MSEL1CR_31_0,   MSEL1CR_31_1,
+                        MSEL1CR_30_0,   MSEL1CR_30_1,
+                        MSEL1CR_29_0,   MSEL1CR_29_1,
+                        MSEL1CR_28_0,   MSEL1CR_28_1,
+                        MSEL1CR_27_0,   MSEL1CR_27_1,
+                        MSEL1CR_26_0,   MSEL1CR_26_1,
+                        0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        MSEL1CR_16_0,   MSEL1CR_16_1,
+                        MSEL1CR_15_0,   MSEL1CR_15_1,
+                        MSEL1CR_14_0,   MSEL1CR_14_1,
+                        MSEL1CR_13_0,   MSEL1CR_13_1,
+                        MSEL1CR_12_0,   MSEL1CR_12_1,
+                        0, 0, 0, 0,
+                        MSEL1CR_9_0,    MSEL1CR_9_1,
+                        0, 0,
+                        MSEL1CR_7_0,    MSEL1CR_7_1,
+                        MSEL1CR_6_0,    MSEL1CR_6_1,
+                        MSEL1CR_5_0,    MSEL1CR_5_1,
+                        MSEL1CR_4_0,    MSEL1CR_4_1,
+                        MSEL1CR_3_0,    MSEL1CR_3_1,
+                        MSEL1CR_2_0,    MSEL1CR_2_1,
+                        0, 0,
+                        MSEL1CR_0_0,    MSEL1CR_0_1,
+                }
+        },
+        { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        MSEL3CR_15_0,   MSEL3CR_15_1,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        MSEL3CR_6_0,    MSEL3CR_6_1,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0,
+                        }
+        },
+        { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        MSEL4CR_19_0,   MSEL4CR_19_1,
+                        MSEL4CR_18_0,   MSEL4CR_18_1,
+                        0, 0, 0, 0,
+                        MSEL4CR_15_0,   MSEL4CR_15_1,
+                        0, 0, 0, 0, 0, 0, 0, 0,
+                        MSEL4CR_10_0,   MSEL4CR_10_1,
+                        0, 0, 0, 0, 0, 0,
+                        MSEL4CR_6_0,    MSEL4CR_6_1,
+                        0, 0,
+                        MSEL4CR_4_0,    MSEL4CR_4_1,
+                        0, 0, 0, 0,
+                        MSEL4CR_1_0,    MSEL4CR_1_1,
+                        0, 0,
+                }
+        },
+        { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
+                        MSEL5CR_31_0,   MSEL5CR_31_1,
+                        MSEL5CR_30_0,   MSEL5CR_30_1,
+                        MSEL5CR_29_0,   MSEL5CR_29_1,
+                        0, 0,
+                        MSEL5CR_27_0,   MSEL5CR_27_1,
+                        0, 0,
+                        MSEL5CR_25_0,   MSEL5CR_25_1,
+                        0, 0,
+                        MSEL5CR_23_0,   MSEL5CR_23_1,
+                        0, 0,
+                        MSEL5CR_21_0,   MSEL5CR_21_1,
+                        0, 0,
+                        MSEL5CR_19_0,   MSEL5CR_19_1,
+                        0, 0,
+                        MSEL5CR_17_0,   MSEL5CR_17_1,
+                        0, 0,
+                        MSEL5CR_15_0,   MSEL5CR_15_1,
+                        MSEL5CR_14_0,   MSEL5CR_14_1,
+                        MSEL5CR_13_0,   MSEL5CR_13_1,
+                        MSEL5CR_12_0,   MSEL5CR_12_1,
+                        MSEL5CR_11_0,   MSEL5CR_11_1,
+                        MSEL5CR_10_0,   MSEL5CR_10_1,
+                        0, 0,
+                        MSEL5CR_8_0,    MSEL5CR_8_1,
+                        MSEL5CR_7_0,    MSEL5CR_7_1,
+                        MSEL5CR_6_0,    MSEL5CR_6_1,
+                        MSEL5CR_5_0,    MSEL5CR_5_1,
+                        MSEL5CR_4_0,    MSEL5CR_4_1,
+                        MSEL5CR_3_0,    MSEL5CR_3_1,
+                        MSEL5CR_2_0,    MSEL5CR_2_1,
+                        0, 0,
+                        MSEL5CR_0_0,    MSEL5CR_0_1,
+                }
+        },
+        { },
+};
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
+                PORT31_DATA,    PORT30_DATA,    PORT29_DATA,    PORT28_DATA,
+                PORT27_DATA,    PORT26_DATA,    PORT25_DATA,    PORT24_DATA,
+                PORT23_DATA,    PORT22_DATA,    PORT21_DATA,    PORT20_DATA,
+                PORT19_DATA,    PORT18_DATA,    PORT17_DATA,    PORT16_DATA,
+                PORT15_DATA,    PORT14_DATA,    PORT13_DATA,    PORT12_DATA,
+                PORT11_DATA,    PORT10_DATA,    PORT9_DATA,     PORT8_DATA,
+                PORT7_DATA,     PORT6_DATA,     PORT5_DATA,     PORT4_DATA,
+                PORT3_DATA,     PORT2_DATA,     PORT1_DATA,     PORT0_DATA }
+        },
+        { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
+                PORT63_DATA,    PORT62_DATA,    PORT61_DATA,    PORT60_DATA,
+                PORT59_DATA,    PORT58_DATA,    PORT57_DATA,    PORT56_DATA,
+                PORT55_DATA,    PORT54_DATA,    PORT53_DATA,    PORT52_DATA,
+                PORT51_DATA,    PORT50_DATA,    PORT49_DATA,    PORT48_DATA,
+                PORT47_DATA,    PORT46_DATA,    PORT45_DATA,    PORT44_DATA,
+                PORT43_DATA,    PORT42_DATA,    PORT41_DATA,    PORT40_DATA,
+                PORT39_DATA,    PORT38_DATA,    PORT37_DATA,    PORT36_DATA,
+                PORT35_DATA,    PORT34_DATA,    PORT33_DATA,    PORT32_DATA }
+        },
+        { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PORT83_DATA,    PORT82_DATA,    PORT81_DATA,    PORT80_DATA,
+                PORT79_DATA,    PORT78_DATA,    PORT77_DATA,    PORT76_DATA,
+                PORT75_DATA,    PORT74_DATA,    PORT73_DATA,    PORT72_DATA,
+                PORT71_DATA,    PORT70_DATA,    PORT69_DATA,    PORT68_DATA,
+                PORT67_DATA,    PORT66_DATA,    PORT65_DATA,    PORT64_DATA }
+        },
+        { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
+                PORT95_DATA,    PORT94_DATA,    PORT93_DATA,    PORT92_DATA,
+                PORT91_DATA,    PORT90_DATA,    PORT89_DATA,    PORT88_DATA,
+                PORT87_DATA,    PORT86_DATA,    PORT85_DATA,    PORT84_DATA,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0 }
+        },
+        { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0,              PORT114_DATA,   PORT113_DATA,   PORT112_DATA,
+                PORT111_DATA,   PORT110_DATA,   PORT109_DATA,   PORT108_DATA,
+                PORT107_DATA,   PORT106_DATA,   PORT105_DATA,   PORT104_DATA,
+                PORT103_DATA,   PORT102_DATA,   PORT101_DATA,   PORT100_DATA,
+                PORT99_DATA,    PORT98_DATA,    PORT97_DATA,    PORT96_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
+                PORT127_DATA,   PORT126_DATA,   PORT125_DATA,   PORT124_DATA,
+                PORT123_DATA,   PORT122_DATA,   PORT121_DATA,   PORT120_DATA,
+                PORT119_DATA,   PORT118_DATA,   PORT117_DATA,   PORT116_DATA,
+                PORT115_DATA,   0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0 }
+        },
+        { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
+                PORT159_DATA,   PORT158_DATA,   PORT157_DATA,   PORT156_DATA,
+                PORT155_DATA,   PORT154_DATA,   PORT153_DATA,   PORT152_DATA,
+                PORT151_DATA,   PORT150_DATA,   PORT149_DATA,   PORT148_DATA,
+                PORT147_DATA,   PORT146_DATA,   PORT145_DATA,   PORT144_DATA,
+                PORT143_DATA,   PORT142_DATA,   PORT141_DATA,   PORT140_DATA,
+                PORT139_DATA,   PORT138_DATA,   PORT137_DATA,   PORT136_DATA,
+                PORT135_DATA,   PORT134_DATA,   PORT133_DATA,   PORT132_DATA,
+                PORT131_DATA,   PORT130_DATA,   PORT129_DATA,   PORT128_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
+                PORT191_DATA,   PORT190_DATA,   PORT189_DATA,   PORT188_DATA,
+                PORT187_DATA,   PORT186_DATA,   PORT185_DATA,   PORT184_DATA,
+                PORT183_DATA,   PORT182_DATA,   PORT181_DATA,   PORT180_DATA,
+                PORT179_DATA,   PORT178_DATA,   PORT177_DATA,   PORT176_DATA,
+                PORT175_DATA,   PORT174_DATA,   PORT173_DATA,   PORT172_DATA,
+                PORT171_DATA,   PORT170_DATA,   PORT169_DATA,   PORT168_DATA,
+                PORT167_DATA,   PORT166_DATA,   PORT165_DATA,   PORT164_DATA,
+                PORT163_DATA,   PORT162_DATA,   PORT161_DATA,   PORT160_DATA }
+        },
+        { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0,                           PORT209_DATA,   PORT208_DATA,
+                PORT207_DATA,   PORT206_DATA,   PORT205_DATA,   PORT204_DATA,
+                PORT203_DATA,   PORT202_DATA,   PORT201_DATA,   PORT200_DATA,
+                PORT199_DATA,   PORT198_DATA,   PORT197_DATA,   PORT196_DATA,
+                PORT195_DATA,   PORT194_DATA,   PORT193_DATA,   PORT192_DATA }
+        },
+        { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                PORT211_DATA,   PORT210_DATA, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                0, 0, 0, 0 }
+        },
+        { },
+};
+static struct pinmux_info r8a7740_pinmux_info = {
+        .name           = "r8a7740_pfc",
+        .reserved_id    = PINMUX_RESERVED,
+        .data           = { PINMUX_DATA_BEGIN,
+                            PINMUX_DATA_END },
+        .input          = { PINMUX_INPUT_BEGIN,
+                            PINMUX_INPUT_END },
+        .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
+                            PINMUX_INPUT_PULLUP_END },
+        .input_pd       = { PINMUX_INPUT_PULLDOWN_BEGIN,
+                            PINMUX_INPUT_PULLDOWN_END },
+        .output         = { PINMUX_OUTPUT_BEGIN,
+                            PINMUX_OUTPUT_END },
+        .mark           = { PINMUX_MARK_BEGIN,
+                            PINMUX_MARK_END },
+        .function       = { PINMUX_FUNCTION_BEGIN,
+                            PINMUX_FUNCTION_END },
+        .first_gpio     = GPIO_PORT0,
+        .last_gpio      = GPIO_FN_TRACEAUD_FROM_MEMC,
+        .gpios          = pinmux_gpios,
+        .cfg_regs       = pinmux_config_regs,
+        .data_regs      = pinmux_data_regs,
+        .gpio_data      = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+void r8a7740_pinmux_init(void)
+{
+        register_pinmux(&r8a7740_pinmux_info);
+}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
new file mode 100644
index 00000000000..963532f2b2c
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -0,0 +1,2645 @@
+/*
+ * r8a7779 processor support - PFC hardware block
+ *
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/ioport.h>
+#include <mach/r8a7779.h>
+#define CPU_32_PORT(fn, pfx, sfx)                               \
+        PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),        \
+        PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),     \
+        PORT_1(fn, pfx##31, sfx)
+#define CPU_32_PORT6(fn, pfx, sfx)                              \
+        PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),       \
+        PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),       \
+        PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),       \
+        PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),       \
+        PORT_1(fn, pfx##8, sfx)
+#define CPU_ALL_PORT(fn, pfx, sfx)                              \
+        CPU_32_PORT(fn, pfx##_0_, sfx),                         \
+        CPU_32_PORT(fn, pfx##_1_, sfx),                         \
+        CPU_32_PORT(fn, pfx##_2_, sfx),                         \
+        CPU_32_PORT(fn, pfx##_3_, sfx),                         \
+        CPU_32_PORT(fn, pfx##_4_, sfx),                         \
+        CPU_32_PORT(fn, pfx##_5_, sfx),                         \
+        CPU_32_PORT6(fn, pfx##_6_, sfx)
+#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
+#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,    \
+                                       GP##pfx##_IN, GP##pfx##_OUT)
+#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
+#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
+#define GP_ALL(str)     CPU_ALL_PORT(_PORT_ALL, GP, str)
+#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, , unused)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, , unused)
+#define PORT_10_REV(fn, pfx, sfx)                               \
+        PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),       \
+        PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),       \
+        PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),       \
+        PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),       \
+        PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+#define CPU_32_PORT_REV(fn, pfx, sfx)                                   \
+        PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),             \
+        PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),     \
+        PORT_10_REV(fn, pfx, sfx)
+#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+                                                          FN_##ipsr, FN_##fn)
+enum {
+        PINMUX_RESERVED = 0,
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
+        PINMUX_DATA_END,
+        PINMUX_INPUT_BEGIN,
+        GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
+        PINMUX_INPUT_END,
+        PINMUX_OUTPUT_BEGIN,
+        GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
+        PINMUX_OUTPUT_END,
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
+        /* GPSR0 */
+        FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
+        FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
+        FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
+        FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
+        FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
+        FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
+        FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
+        FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
+        /* GPSR1 */
+        FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
+        FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
+        FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
+        FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
+        FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
+        FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
+        FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
+        FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
+        /* GPSR2 */
+        FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
+        FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
+        FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
+        FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
+        FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
+        FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
+        FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
+        FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
+        /* GPSR3 */
+        FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
+        FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
+        FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
+        FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
+        FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
+        FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
+        FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
+        FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
+        /* GPSR4 */
+        FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
+        FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
+        FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
+        FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
+        FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
+        FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
+        FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
+        FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
+        /* GPSR5 */
+        FN_A1, FN_A2, FN_A3, FN_A4,
+        FN_A5, FN_A6, FN_A7, FN_A8,
+        FN_A9, FN_A10, FN_A11, FN_A12,
+        FN_A13, FN_A14, FN_A15, FN_A16,
+        FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
+        FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
+        FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
+        FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
+        /* GPSR6 */
+        FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
+        FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
+        FN_IP3_20,
+        /* IPSR0 */
+        FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
+        FN_HRTS1, FN_RX4_C,
+        FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
+        FN_CS0, FN_HSPI_CS2_B,
+        FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
+        FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
+        FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
+        FN_CTS0_B,
+        FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
+        FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
+        FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
+        FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
+        FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
+        FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
+        FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
+        FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
+        FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
+        FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+        FN_SCIF_CLK, FN_TCLK0_C,
+        /* IPSR1 */
+        FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
+        FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
+        FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
+        FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
+        FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
+        FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
+        FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
+        FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
+        FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
+        FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
+        FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
+        FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
+        FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
+        FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
+        FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
+        FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
+        /* IPSR2 */
+        FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
+        FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
+        FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
+        FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
+        FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
+        FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
+        FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
+        FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
+        FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
+        FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
+        FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
+        FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
+        FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
+        FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
+        FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
+        FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
+        FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
+        FN_DREQ1, FN_SCL2, FN_AUDATA2,
+        /* IPSR3 */
+        FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
+        FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
+        FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
+        FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
+        FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
+        FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
+        FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
+        FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
+        FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
+        FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
+        FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
+        FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
+        FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
+        FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
+        FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
+        FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
+        FN_TX2_C, FN_SCL2_C, FN_REMOCON,
+        /* IPSR4 */
+        FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
+        FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
+        FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
+        FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
+        FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
+        FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
+        FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
+        FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
+        FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
+        FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
+        FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
+        FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
+        FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
+        FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
+        FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
+        FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
+        FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
+        FN_SCK0_D,
+        /* IPSR5 */
+        FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
+        FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
+        FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
+        FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
+        FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
+        FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
+        FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
+        FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
+        FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
+        FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
+        FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
+        FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
+        FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
+        FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
+        FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
+        FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
+        FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
+        FN_CAN_DEBUGOUT0, FN_MOUT0,
+        /* IPSR6 */
+        FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
+        FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
+        FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
+        FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
+        FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
+        FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
+        FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
+        FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
+        FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
+        FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
+        FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
+        FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
+        FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
+        /* IPSR7 */
+        FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
+        FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
+        FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
+        FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
+        FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
+        FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
+        FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
+        FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
+        FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
+        FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
+        FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
+        FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
+        FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
+        FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
+        /* IPSR8 */
+        FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
+        FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
+        FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
+        FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
+        FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
+        FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
+        FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
+        FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
+        FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
+        FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
+        FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
+        FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
+        FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
+        FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
+        FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
+        FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
+        /* IPSR9 */
+        FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
+        FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
+        FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
+        FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
+        FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
+        FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
+        FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
+        FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
+        FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
+        FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
+        FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
+        FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
+        FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
+        FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
+        /* IPSR10 */
+        FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
+        FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
+        FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
+        FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
+        FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
+        FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
+        FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
+        FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
+        FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
+        FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
+        FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
+        FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
+        FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
+        FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
+        FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
+        FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
+        /* IPSR11 */
+        FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
+        FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
+        FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
+        FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
+        FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
+        FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
+        FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
+        FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
+        FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
+        FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
+        FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
+        FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
+        FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
+        FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
+        /* IPSR12 */
+        FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
+        FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
+        FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
+        FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
+        FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
+        FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
+        FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
+        FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
+        FN_GPS_MAG, FN_FCE, FN_SCK4_B,
+        FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
+        FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+        FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
+        FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
+        FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
+        FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
+        FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
+        FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+        FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
+        FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
+        FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
+        FN_SEL_VI0_0, FN_SEL_VI0_1,
+        FN_SEL_SD2_0, FN_SEL_SD2_1,
+        FN_SEL_INT3_0, FN_SEL_INT3_1,
+        FN_SEL_INT2_0, FN_SEL_INT2_1,
+        FN_SEL_INT1_0, FN_SEL_INT1_1,
+        FN_SEL_INT0_0, FN_SEL_INT0_1,
+        FN_SEL_IE_0, FN_SEL_IE_1,
+        FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
+        FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
+        FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
+        FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
+        FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
+        FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
+        FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
+        FN_SEL_CAN0_0, FN_SEL_CAN0_1,
+        FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+        FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+        FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
+        FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
+        FN_SEL_ADI_0, FN_SEL_ADI_1,
+        FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+        FN_SEL_SIM_0, FN_SEL_SIM_1,
+        FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
+        FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
+        FN_SEL_I2C3_0, FN_SEL_I2C3_1,
+        FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+        FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
+        PINMUX_FUNCTION_END,
+        PINMUX_MARK_BEGIN,
+        AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
+        A19_MARK,
+        RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
+        HRTS1_MARK, RX4_C_MARK,
+        CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
+        CS0_MARK, HSPI_CS2_B_MARK,
+        CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
+        A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
+        HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
+        A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
+        HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
+        A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
+        A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
+        A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
+        A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
+        A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
+        BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
+        ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
+        PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
+        SCIF_CLK_MARK, TCLK0_C_MARK,
+        EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
+        FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
+        EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
+        ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
+        FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
+        HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
+        EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
+        ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
+        TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
+        SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
+        VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
+        SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
+        MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
+        PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
+        SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
+        CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
+        HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
+        SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
+        CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
+        MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
+        SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
+        CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
+        STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
+        SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
+        RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
+        CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
+        CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
+        GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
+        LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
+        AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
+        DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
+        DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
+        DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
+        DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
+        DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
+        AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
+        LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
+        LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
+        LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
+        SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
+        LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
+        AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
+        DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
+        DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
+        DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
+        TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
+        DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
+        SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
+        QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
+        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
+        TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
+        DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
+        DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
+        DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
+        VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
+        AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
+        PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
+        CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
+        VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
+        VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
+        VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
+        SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
+        DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
+        SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
+        VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
+        VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
+        VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
+        VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
+        SCK0_D_MARK,
+        DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
+        RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
+        DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
+        DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
+        DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
+        HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
+        SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
+        VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
+        VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
+        TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
+        VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
+        GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
+        QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
+        GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
+        RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
+        VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
+        GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
+        USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
+        SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
+        CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
+        MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
+        SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
+        CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
+        SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
+        SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
+        CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
+        SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
+        ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
+        SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
+        SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
+        SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
+        SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
+        SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
+        SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
+        HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
+        SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
+        IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
+        VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
+        ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
+        TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
+        RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
+        SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
+        TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
+        RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
+        RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
+        HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
+        CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
+        CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
+        AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
+        CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
+        CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
+        CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
+        CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
+        AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
+        CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
+        PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
+        VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
+        MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
+        VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
+        MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
+        RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
+        VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
+        VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
+        VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
+        MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
+        VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
+        MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
+        MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
+        IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
+        IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
+        MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
+        ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
+        VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
+        VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
+        VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
+        VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
+        VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
+        ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
+        DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
+        VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
+        ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
+        IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
+        SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
+        TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
+        HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
+        VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
+        TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
+        ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
+        TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
+        VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
+        PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
+        SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
+        VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
+        ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
+        SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
+        SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
+        VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
+        ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
+        SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
+        VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
+        HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
+        MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
+        SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
+        VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK,
+        DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
+        VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
+        DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
+        VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
+        SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
+        SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
+        VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
+        SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
+        GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
+        VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
+        RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
+        GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
+        PINMUX_MARK_END,
+};
+static pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+        PINMUX_DATA(AVS1_MARK, FN_AVS1),
+        PINMUX_DATA(AVS1_MARK, FN_AVS1),
+        PINMUX_DATA(A17_MARK, FN_A17),
+        PINMUX_DATA(A18_MARK, FN_A18),
+        PINMUX_DATA(A19_MARK, FN_A19),
+        PINMUX_IPSR_DATA(IP0_2_0, PENC2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP0_2_0, PWM1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
+        PINMUX_IPSR_DATA(IP0_5_3, BS),
+        PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
+        PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
+        PINMUX_IPSR_DATA(IP0_5_3, FD2),
+        PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
+        PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
+        PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
+        PINMUX_IPSR_DATA(IP0_7_6, A0),
+        PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
+        PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
+        PINMUX_IPSR_DATA(IP0_7_6, FD3),
+        PINMUX_IPSR_DATA(IP0_9_8, A20),
+        PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
+        PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
+        PINMUX_IPSR_DATA(IP0_11_10, A21),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
+        PINMUX_IPSR_DATA(IP0_13_12, A22),
+        PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
+        PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
+        PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
+        PINMUX_IPSR_DATA(IP0_15_14, A23),
+        PINMUX_IPSR_DATA(IP0_15_14, FCLE),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
+        PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
+        PINMUX_IPSR_DATA(IP0_18_16, A24),
+        PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
+        PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
+        PINMUX_IPSR_DATA(IP0_18_16, FD4),
+        PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
+        PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
+        PINMUX_IPSR_DATA(IP0_22_19, A25),
+        PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
+        PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
+        PINMUX_IPSR_DATA(IP0_22_19, FD5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
+        PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
+        PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
+        PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
+        PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
+        PINMUX_IPSR_DATA(IP0_25, CS0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
+        PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
+        PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
+        PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
+        PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
+        PINMUX_IPSR_DATA(IP0_30_28, FWE),
+        PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
+        PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
+        PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
+        PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
+        PINMUX_IPSR_DATA(IP1_1_0, FD6),
+        PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
+        PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
+        PINMUX_IPSR_DATA(IP1_3_2, FD7),
+        PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
+        PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
+        PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
+        PINMUX_IPSR_DATA(IP1_6_4, FALE),
+        PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
+        PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
+        PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
+        PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
+        PINMUX_IPSR_DATA(IP1_10_7, FRE),
+        PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
+        PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
+        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
+        PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
+        PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
+        PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
+        PINMUX_IPSR_DATA(IP1_14_11, FD0),
+        PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
+        PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
+        PINMUX_IPSR_DATA(IP1_14_11, HTX1),
+        PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
+        PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
+        PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
+        PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
+        PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
+        PINMUX_IPSR_DATA(IP1_18_15, FD1),
+        PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
+        PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
+        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
+        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
+        PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
+        PINMUX_IPSR_DATA(IP1_20_19, PWM2),
+        PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
+        PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
+        PINMUX_IPSR_DATA(IP1_22_21, PWM3),
+        PINMUX_IPSR_DATA(IP1_22_21, TX4),
+        PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
+        PINMUX_IPSR_DATA(IP1_24_23, PWM4),
+        PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
+        PINMUX_IPSR_DATA(IP1_28_25, HTX0),
+        PINMUX_IPSR_DATA(IP1_28_25, TX1),
+        PINMUX_IPSR_DATA(IP1_28_25, SDATA),
+        PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
+        PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
+        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
+        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
+        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
+        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
+        PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
+        PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
+        PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
+        PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
+        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
+        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
+        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
+        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
+        PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
+        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP2_7_4, MTS),
+        PINMUX_IPSR_DATA(IP2_7_4, PWM5),
+        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
+        PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
+        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
+        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
+        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
+        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
+        PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
+        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP2_11_8, STM),
+        PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
+        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
+        PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
+        PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
+        PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
+        PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP2_15_12, MDATA),
+        PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
+        PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
+        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
+        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
+        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
+        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
+        PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
+        PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
+        PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
+        PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
+        PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
+        PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
+        PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
+        PINMUX_IPSR_DATA(IP2_21_19, DACK0),
+        PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
+        PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
+        PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
+        PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
+        PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
+        PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
+        PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
+        PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
+        PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
+        PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
+        PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
+        PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
+        PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
+        PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
+        PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
+        PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
+        PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
+        PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
+        PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
+        PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
+        PINMUX_IPSR_DATA(IP3_2_0, DACK1),
+        PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
+        PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
+        PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
+        PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
+        PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
+        PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
+        PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
+        PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
+        PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
+        PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
+        PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
+        PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
+        PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
+        PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
+        PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
+        PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
+        PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
+        PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
+        PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
+        PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
+        PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
+        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
+        PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
+        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
+        PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
+        PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
+        PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
+        PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
+        PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
+        PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
+        PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
+        PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
+        PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
+        PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
+        PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
+        PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
+        PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
+        PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
+        PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
+        PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
+        PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
+        PINMUX_IPSR_DATA(IP3_23, QCLK),
+        PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
+        PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
+        PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
+        PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
+        PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
+        PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
+        PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
+        PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
+        PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
+        PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
+        PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
+        PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
+        PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
+        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
+        PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
+        PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
+        PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
+        PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
+        PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
+        PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
+        PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
+        PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
+        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
+        PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
+        PINMUX_IPSR_DATA(IP4_7_5, PWM6),
+        PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
+        PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
+        PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
+        PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
+        PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
+        PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
+        PINMUX_IPSR_DATA(IP4_10_8, PWM0),
+        PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
+        PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
+        PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
+        PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
+        PINMUX_IPSR_DATA(IP4_11, VI2_G0),
+        PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
+        PINMUX_IPSR_DATA(IP4_12, VI2_G1),
+        PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
+        PINMUX_IPSR_DATA(IP4_13, VI2_G2),
+        PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
+        PINMUX_IPSR_DATA(IP4_14, VI2_G3),
+        PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
+        PINMUX_IPSR_DATA(IP4_15, VI2_G4),
+        PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
+        PINMUX_IPSR_DATA(IP4_16, VI2_G5),
+        PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
+        PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
+        PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
+        PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
+        PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
+        PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
+        PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
+        PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
+        PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
+        PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
+        PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
+        PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
+        PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
+        PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
+        PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
+        PINMUX_IPSR_DATA(IP4_23, VI2_G6),
+        PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
+        PINMUX_IPSR_DATA(IP4_24, VI2_G7),
+        PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
+        PINMUX_IPSR_DATA(IP4_25, VI2_R0),
+        PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
+        PINMUX_IPSR_DATA(IP4_26, VI2_R1),
+        PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
+        PINMUX_IPSR_DATA(IP4_27, VI2_R2),
+        PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
+        PINMUX_IPSR_DATA(IP4_28, VI2_R3),
+        PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
+        PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
+        PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
+        PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
+        PINMUX_IPSR_DATA(IP4_31_29, TX5),
+        PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
+        PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
+        PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
+        PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
+        PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
+        PINMUX_IPSR_DATA(IP5_3, VI2_R4),
+        PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
+        PINMUX_IPSR_DATA(IP5_4, VI2_R5),
+        PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
+        PINMUX_IPSR_DATA(IP5_5, VI2_R6),
+        PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
+        PINMUX_IPSR_DATA(IP5_6, VI2_R7),
+        PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
+        PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
+        PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
+        PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
+        PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
+        PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
+        PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
+        PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
+        PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
+        PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
+        PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
+        PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
+        PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
+        PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
+        PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
+        PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
+        PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
+        PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
+        PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
+        PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
+        PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
+        PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
+        PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
+        PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
+        PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
+        PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
+        PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
+        PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
+        PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
+        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
+        PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
+        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
+        PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
+        PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
+        PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
+        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
+        PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
+        PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
+        PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
+        PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
+        PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
+        PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
+        PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
+        PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
+        PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
+        PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
+        PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
+        PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
+        PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
+        PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
+        PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
+        PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
+        PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
+        PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
+        PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
+        PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
+        PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
+        PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
+        PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
+        PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
+        PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
+        PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
+        PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
+        PINMUX_IPSR_DATA(IP6_14_12, IETX),
+        PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
+        PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
+        PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
+        PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
+        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
+        PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
+        PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
+        PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
+        PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
+        PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
+        PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
+        PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
+        PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
+        PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
+        PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
+        PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
+        PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
+        PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
+        PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
+        PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
+        PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
+        PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
+        PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
+        PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
+        PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
+        PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
+        PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
+        PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
+        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
+        PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
+        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
+        PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
+        PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
+        PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
+        PINMUX_IPSR_DATA(IP7_14_13, VSP),
+        PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
+        PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
+        PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
+        PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
+        PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
+        PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
+        PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
+        PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
+        PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
+        PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
+        PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
+        PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
+        PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
+        PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
+        PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
+        PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
+        PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
+        PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
+        PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
+        PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
+        PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
+        PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
+        PINMUX_IPSR_DATA(IP7_30_29, DACK2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
+        PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
+        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
+        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
+        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
+        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
+        PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
+        PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
+        PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
+        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
+        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
+        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
+        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
+        PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
+        PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
+        PINMUX_IPSR_DATA(IP8_11_8, TX0),
+        PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
+        PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
+        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
+        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
+        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
+        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
+        PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
+        PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
+        PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
+        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
+        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
+        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
+        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
+        PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
+        PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
+        PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
+        PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
+        PINMUX_IPSR_DATA(IP8_18, BPFCLK),
+        PINMUX_IPSR_DATA(IP8_18, PCMWE),
+        PINMUX_IPSR_DATA(IP8_19, FMIN),
+        PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
+        PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
+        PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
+        PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
+        PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
+        PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
+        PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
+        PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
+        PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
+        PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
+        PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
+        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
+        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
+        PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
+        PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
+        PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
+        PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
+        PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
+        PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
+        PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
+        PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
+        PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
+        PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
+        PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
+        PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
+        PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
+        PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
+        PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
+        PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
+        PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
+        PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
+        PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
+        PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
+        PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
+        PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
+        PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
+        PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
+        PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
+        PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
+        PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
+        PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
+        PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
+        PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
+        PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
+        PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
+        PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
+        PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
+        PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
+        PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
+        PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
+        PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
+        PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
+        PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
+        PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
+        PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
+        PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
+        PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
+        PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
+        PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
+        PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
+        PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
+        PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
+        PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
+        PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
+        PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
+        PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
+        PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
+        PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
+        PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
+        PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
+        PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
+        PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
+        PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
+        PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
+        PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
+        PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
+        PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
+        PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
+        PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
+        PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
+        PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
+        PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
+        PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
+        PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
+        PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
+        PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
+        PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
+        PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
+        PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
+        PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
+        PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
+        PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
+        PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
+        PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
+        PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
+        PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
+        PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
+        PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
+        PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
+        PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
+        PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
+        PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
+        PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
+        PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
+        PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
+        PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
+        PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
+        PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
+        PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
+        PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
+        PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
+        PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
+        PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
+        PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
+        PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
+        PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
+        PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
+        PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
+        PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
+        PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
+        PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
+        PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
+        PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
+        PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
+        PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
+        PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
+        PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
+        PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
+        PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
+        PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
+        PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
+        PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
+        PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
+        PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
+        PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
+        PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
+        PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
+        PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
+        PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
+        PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
+        PINMUX_IPSR_DATA(IP11_26_24, TX2),
+        PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
+        PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
+        PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
+        PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
+        PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
+        PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
+        PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
+        PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
+        PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
+        PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
+        PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
+        PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
+        PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
+        PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
+        PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
+        PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
+        PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
+        PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
+        PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
+        PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
+        PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
+        PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
+        PINMUX_IPSR_DATA(IP12_11_9, FSE),
+        PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
+        PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
+        PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
+        PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
+        PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
+        PINMUX_IPSR_DATA(IP12_14_12, FRB),
+        PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
+        PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
+        PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
+        PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
+        PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
+        PINMUX_IPSR_DATA(IP12_17_15, FCE),
+        PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
+};
+static struct pinmux_gpio pinmux_gpios[] = {
+        PINMUX_GPIO_GP_ALL(),
+        GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
+        GPIO_FN(A19),
+        /* IPSR0 */
+        GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
+        GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
+        GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
+        GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
+        GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
+        GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
+        GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
+        GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
+        GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD),
+        GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
+        GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5),
+        GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
+        GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
+        GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
+        GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
+        GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
+        GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
+        /* IPSR1 */
+        GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6),
+        GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7),
+        GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE),
+        GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD),
+        GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
+        GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
+        GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0),
+        GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
+        GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
+        GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1),
+        GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
+        GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
+        GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
+        GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
+        GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA),
+        GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
+        GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
+        GPIO_FN(CC5_STATE34),
+        /* IPSR2 */
+        GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C),
+        GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
+        GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
+        GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5),
+        GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
+        GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
+        GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
+        GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C),
+        GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
+        GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
+        GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
+        GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
+        GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0),
+        GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
+        GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
+        GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
+        GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3),
+        GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5),
+        GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7),
+        GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
+        GPIO_FN(AUDATA2),
+        /* IPSR3 */
+        GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
+        GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10),
+        GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4),
+        GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13),
+        GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7),
+        GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16),
+        GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
+        GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
+        GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
+        GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3),
+        GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20),
+        GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6),
+        GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23),
+        GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
+        GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK),
+        GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
+        GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
+        GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS),
+        GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
+        GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
+        GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
+        /* IPSR4 */
+        GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
+        GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
+        GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
+        GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
+        GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
+        GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1),
+        GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
+        GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0),
+        GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2),
+        GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4),
+        GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0),
+        GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
+        GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1),
+        GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
+        GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2),
+        GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4),
+        GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6),
+        GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0),
+        GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
+        GPIO_FN(TX5), GPIO_FN(SCK0_D),
+        /* IPSR5 */
+        GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
+        GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
+        GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5),
+        GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7),
+        GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D),
+        GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
+        GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD),
+        GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC),
+        GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC),
+        GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
+        GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
+        GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
+        GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6),
+        GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
+        GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
+        GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
+        GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
+        GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
+        GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
+        GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
+        GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
+        /* IPSR6 */
+        GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
+        GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
+        GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
+        GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
+        GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
+        GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
+        GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
+        GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
+        GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
+        GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
+        GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
+        GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
+        GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
+        GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
+        GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
+        GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
+        GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
+        /* IPSR7 */
+        GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
+        GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
+        GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
+        GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
+        GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
+        GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
+        GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
+        GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
+        GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
+        GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
+        GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
+        GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
+        GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
+        GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
+        GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
+        GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
+        GPIO_FN(CTS1_B),
+        /* IPSR8 */
+        GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
+        GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
+        GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
+        GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
+        GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
+        GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
+        GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
+        GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
+        GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
+        GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
+        GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
+        GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
+        GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
+        GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
+        GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
+        GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
+        GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
+        GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
+        GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
+        GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
+        /* IPSR9 */
+        GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
+        GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
+        GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3),
+        GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2),
+        GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6),
+        GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
+        GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
+        GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
+        GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
+        GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
+        GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
+        GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
+        GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
+        GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
+        GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
+        GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
+        GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
+        GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
+        /* IPSR10 */
+        GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
+        GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
+        GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
+        GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
+        GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2),
+        GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
+        GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
+        GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
+        GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
+        GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
+        GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
+        GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
+        GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
+        GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
+        GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
+        GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
+        GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
+        GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
+        GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
+        GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
+        GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
+        /* IPSR11 */
+        GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST),
+        GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
+        GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
+        GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2),
+        GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
+        GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
+        GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
+        GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
+        GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
+        GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
+        GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
+        GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
+        GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
+        GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
+        GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
+        GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
+        GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
+        GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
+        GPIO_FN(HRTS0_B),
+        /* IPSR12 */
+        GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
+        GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
+        GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
+        GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
+        GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
+        GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
+        GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B),
+        GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
+        GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
+        GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
+};
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
+                GP_0_31_FN, FN_IP3_31_29,
+                GP_0_30_FN, FN_IP3_26_24,
+                GP_0_29_FN, FN_IP3_22_21,
+                GP_0_28_FN, FN_IP3_14_12,
+                GP_0_27_FN, FN_IP3_11_9,
+                GP_0_26_FN, FN_IP3_2_0,
+                GP_0_25_FN, FN_IP2_30_28,
+                GP_0_24_FN, FN_IP2_21_19,
+                GP_0_23_FN, FN_IP2_18_16,
+                GP_0_22_FN, FN_IP0_30_28,
+                GP_0_21_FN, FN_IP0_5_3,
+                GP_0_20_FN, FN_IP1_18_15,
+                GP_0_19_FN, FN_IP1_14_11,
+                GP_0_18_FN, FN_IP1_10_7,
+                GP_0_17_FN, FN_IP1_6_4,
+                GP_0_16_FN, FN_IP1_3_2,
+                GP_0_15_FN, FN_IP1_1_0,
+                GP_0_14_FN, FN_IP0_27_26,
+                GP_0_13_FN, FN_IP0_25,
+                GP_0_12_FN, FN_IP0_24_23,
+                GP_0_11_FN, FN_IP0_22_19,
+                GP_0_10_FN, FN_IP0_18_16,
+                GP_0_9_FN, FN_IP0_15_14,
+                GP_0_8_FN, FN_IP0_13_12,
+                GP_0_7_FN, FN_IP0_11_10,
+                GP_0_6_FN, FN_IP0_9_8,
+                GP_0_5_FN, FN_A19,
+                GP_0_4_FN, FN_A18,
+                GP_0_3_FN, FN_A17,
+                GP_0_2_FN, FN_IP0_7_6,
+                GP_0_1_FN, FN_AVS2,
+                GP_0_0_FN, FN_AVS1 }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
+                GP_1_31_FN, FN_IP5_23_21,
+                GP_1_30_FN, FN_IP5_20_17,
+                GP_1_29_FN, FN_IP5_16_15,
+                GP_1_28_FN, FN_IP5_14_13,
+                GP_1_27_FN, FN_IP5_12_11,
+                GP_1_26_FN, FN_IP5_10_9,
+                GP_1_25_FN, FN_IP5_8,
+                GP_1_24_FN, FN_IP5_7,
+                GP_1_23_FN, FN_IP5_6,
+                GP_1_22_FN, FN_IP5_5,
+                GP_1_21_FN, FN_IP5_4,
+                GP_1_20_FN, FN_IP5_3,
+                GP_1_19_FN, FN_IP5_2_0,
+                GP_1_18_FN, FN_IP4_31_29,
+                GP_1_17_FN, FN_IP4_28,
+                GP_1_16_FN, FN_IP4_27,
+                GP_1_15_FN, FN_IP4_26,
+                GP_1_14_FN, FN_IP4_25,
+                GP_1_13_FN, FN_IP4_24,
+                GP_1_12_FN, FN_IP4_23,
+                GP_1_11_FN, FN_IP4_22_20,
+                GP_1_10_FN, FN_IP4_19_17,
+                GP_1_9_FN, FN_IP4_16,
+                GP_1_8_FN, FN_IP4_15,
+                GP_1_7_FN, FN_IP4_14,
+                GP_1_6_FN, FN_IP4_13,
+                GP_1_5_FN, FN_IP4_12,
+                GP_1_4_FN, FN_IP4_11,
+                GP_1_3_FN, FN_IP4_10_8,
+                GP_1_2_FN, FN_IP4_7_5,
+                GP_1_1_FN, FN_IP4_4_2,
+                GP_1_0_FN, FN_IP4_1_0 }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
+                GP_2_31_FN, FN_IP10_28_26,
+                GP_2_30_FN, FN_IP10_25_24,
+                GP_2_29_FN, FN_IP10_23_21,
+                GP_2_28_FN, FN_IP10_20_18,
+                GP_2_27_FN, FN_IP10_17_15,
+                GP_2_26_FN, FN_IP10_14_12,
+                GP_2_25_FN, FN_IP10_11_9,
+                GP_2_24_FN, FN_IP10_8_6,
+                GP_2_23_FN, FN_IP10_5_3,
+                GP_2_22_FN, FN_IP10_2_0,
+                GP_2_21_FN, FN_IP9_29_28,
+                GP_2_20_FN, FN_IP9_27_26,
+                GP_2_19_FN, FN_IP9_25_24,
+                GP_2_18_FN, FN_IP9_23_22,
+                GP_2_17_FN, FN_IP9_21_19,
+                GP_2_16_FN, FN_IP9_18_16,
+                GP_2_15_FN, FN_IP9_15_14,
+                GP_2_14_FN, FN_IP9_13_12,
+                GP_2_13_FN, FN_IP9_11_10,
+                GP_2_12_FN, FN_IP9_9_8,
+                GP_2_11_FN, FN_IP9_7,
+                GP_2_10_FN, FN_IP9_6,
+                GP_2_9_FN, FN_IP9_5,
+                GP_2_8_FN, FN_IP9_4,
+                GP_2_7_FN, FN_IP9_3_2,
+                GP_2_6_FN, FN_IP9_1_0,
+                GP_2_5_FN, FN_IP8_30_28,
+                GP_2_4_FN, FN_IP8_27_25,
+                GP_2_3_FN, FN_IP8_24_23,
+                GP_2_2_FN, FN_IP8_22_21,
+                GP_2_1_FN, FN_IP8_20,
+                GP_2_0_FN, FN_IP5_27_24 }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
+                GP_3_31_FN, FN_IP6_3_2,
+                GP_3_30_FN, FN_IP6_1_0,
+                GP_3_29_FN, FN_IP5_30_29,
+                GP_3_28_FN, FN_IP5_28,
+                GP_3_27_FN, FN_IP1_24_23,
+                GP_3_26_FN, FN_IP1_22_21,
+                GP_3_25_FN, FN_IP1_20_19,
+                GP_3_24_FN, FN_IP7_26_25,
+                GP_3_23_FN, FN_IP7_24_23,
+                GP_3_22_FN, FN_IP7_22_21,
+                GP_3_21_FN, FN_IP7_20_19,
+                GP_3_20_FN, FN_IP7_30_29,
+                GP_3_19_FN, FN_IP7_28_27,
+                GP_3_18_FN, FN_IP7_18_17,
+                GP_3_17_FN, FN_IP7_16_15,
+                GP_3_16_FN, FN_IP12_17_15,
+                GP_3_15_FN, FN_IP12_14_12,
+                GP_3_14_FN, FN_IP12_11_9,
+                GP_3_13_FN, FN_IP12_8_6,
+                GP_3_12_FN, FN_IP12_5_3,
+                GP_3_11_FN, FN_IP12_2_0,
+                GP_3_10_FN, FN_IP11_29_27,
+                GP_3_9_FN, FN_IP11_26_24,
+                GP_3_8_FN, FN_IP11_23_21,
+                GP_3_7_FN, FN_IP11_20_18,
+                GP_3_6_FN, FN_IP11_17_15,
+                GP_3_5_FN, FN_IP11_14_12,
+                GP_3_4_FN, FN_IP11_11_9,
+                GP_3_3_FN, FN_IP11_8_6,
+                GP_3_2_FN, FN_IP11_5_3,
+                GP_3_1_FN, FN_IP11_2_0,
+                GP_3_0_FN, FN_IP10_31_29 }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
+                GP_4_31_FN, FN_IP8_19,
+                GP_4_30_FN, FN_IP8_18,
+                GP_4_29_FN, FN_IP8_17_16,
+                GP_4_28_FN, FN_IP0_2_0,
+                GP_4_27_FN, FN_PENC1,
+                GP_4_26_FN, FN_PENC0,
+                GP_4_25_FN, FN_IP8_15_12,
+                GP_4_24_FN, FN_IP8_11_8,
+                GP_4_23_FN, FN_IP8_7_4,
+                GP_4_22_FN, FN_IP8_3_0,
+                GP_4_21_FN, FN_IP2_3_0,
+                GP_4_20_FN, FN_IP1_28_25,
+                GP_4_19_FN, FN_IP2_15_12,
+                GP_4_18_FN, FN_IP2_11_8,
+                GP_4_17_FN, FN_IP2_7_4,
+                GP_4_16_FN, FN_IP7_14_13,
+                GP_4_15_FN, FN_IP7_12_10,
+                GP_4_14_FN, FN_IP7_9_7,
+                GP_4_13_FN, FN_IP7_6_4,
+                GP_4_12_FN, FN_IP7_3_2,
+                GP_4_11_FN, FN_IP7_1_0,
+                GP_4_10_FN, FN_IP6_30_29,
+                GP_4_9_FN, FN_IP6_26_25,
+                GP_4_8_FN, FN_IP6_24_23,
+                GP_4_7_FN, FN_IP6_22_20,
+                GP_4_6_FN, FN_IP6_19_18,
+                GP_4_5_FN, FN_IP6_17_15,
+                GP_4_4_FN, FN_IP6_14_12,
+                GP_4_3_FN, FN_IP6_11_9,
+                GP_4_2_FN, FN_IP6_8,
+                GP_4_1_FN, FN_IP6_7_6,
+                GP_4_0_FN, FN_IP6_5_4 }
+        },
+        { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
+                GP_5_31_FN, FN_IP3_5,
+                GP_5_30_FN, FN_IP3_4,
+                GP_5_29_FN, FN_IP3_3,
+                GP_5_28_FN, FN_IP2_27,
+                GP_5_27_FN, FN_IP2_26,
+                GP_5_26_FN, FN_IP2_25,
+                GP_5_25_FN, FN_IP2_24,
+                GP_5_24_FN, FN_IP2_23,
+                GP_5_23_FN, FN_IP2_22,
+                GP_5_22_FN, FN_IP3_28,
+                GP_5_21_FN, FN_IP3_27,
+                GP_5_20_FN, FN_IP3_23,
+                GP_5_19_FN, FN_EX_WAIT0,
+                GP_5_18_FN, FN_WE1,
+                GP_5_17_FN, FN_WE0,
+                GP_5_16_FN, FN_RD,
+                GP_5_15_FN, FN_A16,
+                GP_5_14_FN, FN_A15,
+                GP_5_13_FN, FN_A14,
+                GP_5_12_FN, FN_A13,
+                GP_5_11_FN, FN_A12,
+                GP_5_10_FN, FN_A11,
+                GP_5_9_FN, FN_A10,
+                GP_5_8_FN, FN_A9,
+                GP_5_7_FN, FN_A8,
+                GP_5_6_FN, FN_A7,
+                GP_5_5_FN, FN_A6,
+                GP_5_4_FN, FN_A5,
+                GP_5_3_FN, FN_A4,
+                GP_5_2_FN, FN_A3,
+                GP_5_1_FN, FN_A2,
+                GP_5_0_FN, FN_A1 }
+        },
+        { PINMUX_CFG_REG("GPSR6", 0xfffc001c, 32, 1) {
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_6_8_FN, FN_IP3_20,
+                GP_6_7_FN, FN_IP3_19,
+                GP_6_6_FN, FN_IP3_18,
+                GP_6_5_FN, FN_IP3_17,
+                GP_6_4_FN, FN_IP3_16,
+                GP_6_3_FN, FN_IP3_15,
+                GP_6_2_FN, FN_IP3_8,
+                GP_6_1_FN, FN_IP3_7,
+                GP_6_0_FN, FN_IP3_6 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
+                             1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3) {
+                /* IP0_31 [1] */
+                0, 0,
+                /* IP0_30_28 [3] */
+                FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
+                FN_HRTS1, FN_RX4_C, 0, 0,
+                /* IP0_27_26 [2] */
+                FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
+                /* IP0_25 [1] */
+                FN_CS0, FN_HSPI_CS2_B,
+                /* IP0_24_23 [2] */
+                FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
+                /* IP0_22_19 [4] */
+                FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
+                FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
+                FN_CTS0_B, 0, 0, 0,
+                0, 0, 0, 0,
+                /* IP0_18_16 [3] */
+                FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
+                FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
+                /* IP0_15_14 [2] */
+                FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
+                /* IP0_13_12 [2] */
+                FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
+                /* IP0_11_10 [2] */
+                FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
+                /* IP0_9_8 [2] */
+                FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
+                /* IP0_7_6 [2] */
+                FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
+                /* IP0_5_3 [3] */
+                FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
+                FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
+                /* IP0_2_0 [3] */
+                FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+                FN_SCIF_CLK, FN_TCLK0_C, 0, 0 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
+                             3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2) {
+                /* IP1_31_29 [3] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_28_25 [4] */
+                FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
+                FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
+                FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
+                0, 0, 0, 0,
+                /* IP1_24_23 [2] */
+                FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
+                /* IP1_22_21 [2] */
+                FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
+                /* IP1_20_19 [2] */
+                FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
+                /* IP1_18_15 [4] */
+                FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
+                FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
+                FN_RX0_B, FN_SSI_WS9, 0, 0,
+                0, 0, 0, 0,
+                /* IP1_14_11 [4] */
+                FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
+                FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
+                FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
+                0, 0, 0, 0,
+                /* IP1_10_7 [4] */
+                FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
+                FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
+                FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
+                0, 0, 0, 0,
+                /* IP1_6_4 [3] */
+                FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
+                FN_ATACS00, 0, 0, 0,
+                /* IP1_3_2 [2] */
+                FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
+                /* IP1_1_0 [2] */
+                FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
+                             1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4) {
+                /* IP2_31 [1] */
+                0, 0,
+                /* IP2_30_28 [3] */
+                FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
+                FN_AUDATA2, 0, 0, 0,
+                /* IP2_27 [1] */
+                FN_DU0_DR7, FN_LCDOUT7,
+                /* IP2_26 [1] */
+                FN_DU0_DR6, FN_LCDOUT6,
+                /* IP2_25 [1] */
+                FN_DU0_DR5, FN_LCDOUT5,
+                /* IP2_24 [1] */
+                FN_DU0_DR4, FN_LCDOUT4,
+                /* IP2_23 [1] */
+                FN_DU0_DR3, FN_LCDOUT3,
+                /* IP2_22 [1] */
+                FN_DU0_DR2, FN_LCDOUT2,
+                /* IP2_21_19 [3] */
+                FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
+                FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
+                /* IP2_18_16 [3] */
+                FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
+                FN_AUDATA0, FN_TX5_C, 0, 0,
+                /* IP2_15_12 [4] */
+                FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
+                FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
+                FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
+                0, 0, 0, 0,
+                /* IP2_11_8 [4] */
+                FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
+                FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
+                FN_CC5_OSCOUT, 0, 0, 0,
+                0, 0, 0, 0,
+                /* IP2_7_4 [4] */
+                FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
+                FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
+                FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
+                0, 0, 0, 0,
+                /* IP2_3_0 [4] */
+                FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
+                FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
+                FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
+                0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
+                             3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1,
+                             1, 3, 3, 1, 1, 1, 1, 1, 1, 3) {
+            /* IP3_31_29 [3] */
+            FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
+            FN_SCL2_C, FN_REMOCON, 0, 0,
+            /* IP3_28 [1] */
+            FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
+            /* IP3_27 [1] */
+            FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
+            /* IP3_26_24 [3] */
+            FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
+            FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
+            /* IP3_23 [1] */
+            FN_DU0_DOTCLKOUT0, FN_QCLK,
+            /* IP3_22_21 [2] */
+            FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
+            /* IP3_20 [1] */
+            FN_DU0_DB7, FN_LCDOUT23,
+            /* IP3_19 [1] */
+            FN_DU0_DB6, FN_LCDOUT22,
+            /* IP3_18 [1] */
+            FN_DU0_DB5, FN_LCDOUT21,
+            /* IP3_17 [1] */
+            FN_DU0_DB4, FN_LCDOUT20,
+            /* IP3_16 [1] */
+            FN_DU0_DB3, FN_LCDOUT19,
+            /* IP3_15 [1] */
+            FN_DU0_DB2, FN_LCDOUT18,
+            /* IP3_14_12 [3] */
+            FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
+            FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
+            /* IP3_11_9 [3] */
+            FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
+            FN_TCLK1, FN_AUDATA4, 0, 0,
+            /* IP3_8 [1] */
+            FN_DU0_DG7, FN_LCDOUT15,
+            /* IP3_7 [1] */
+            FN_DU0_DG6, FN_LCDOUT14,
+            /* IP3_6 [1] */
+            FN_DU0_DG5, FN_LCDOUT13,
+            /* IP3_5 [1] */
+            FN_DU0_DG4, FN_LCDOUT12,
+            /* IP3_4 [1] */
+            FN_DU0_DG3, FN_LCDOUT11,
+            /* IP3_3 [1] */
+            FN_DU0_DG2, FN_LCDOUT10,
+            /* IP3_2_0 [3] */
+            FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
+            FN_AUDATA3, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
+                             3, 1, 1, 1, 1, 1, 1, 3, 3, 1,
+                             1, 1, 1, 1, 1, 1, 3, 3, 3, 2) {
+            /* IP4_31_29 [3] */
+            FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
+            FN_TX5, FN_SCK0_D, 0, 0,
+            /* IP4_28 [1] */
+            FN_DU1_DG7, FN_VI2_R3,
+            /* IP4_27 [1] */
+            FN_DU1_DG6, FN_VI2_R2,
+            /* IP4_26 [1] */
+            FN_DU1_DG5, FN_VI2_R1,
+            /* IP4_25 [1] */
+            FN_DU1_DG4, FN_VI2_R0,
+            /* IP4_24 [1] */
+            FN_DU1_DG3, FN_VI2_G7,
+            /* IP4_23 [1] */
+            FN_DU1_DG2, FN_VI2_G6,
+            /* IP4_22_20 [3] */
+            FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
+            FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
+            /* IP4_19_17 [3] */
+            FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
+            FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
+            /* IP4_16 [1] */
+            FN_DU1_DR7, FN_VI2_G5,
+            /* IP4_15 [1] */
+            FN_DU1_DR6, FN_VI2_G4,
+            /* IP4_14 [1] */
+            FN_DU1_DR5, FN_VI2_G3,
+            /* IP4_13 [1] */
+            FN_DU1_DR4, FN_VI2_G2,
+            /* IP4_12 [1] */
+            FN_DU1_DR3, FN_VI2_G1,
+            /* IP4_11 [1] */
+            FN_DU1_DR2, FN_VI2_G0,
+            /* IP4_10_8 [3] */
+            FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
+            FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
+            /* IP4_7_5 [3] */
+            FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
+            FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
+            /* IP4_4_2 [3] */
+            FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
+            FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
+            /* IP4_1_0 [2] */
+            FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
+                             1, 2, 1, 4, 3, 4, 2, 2,
+                             2, 2, 1, 1, 1, 1, 1, 1, 3) {
+            /* IP5_31 [1] */
+            0, 0,
+            /* IP5_30_29 [2] */
+            FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
+            /* IP5_28 [1] */
+            FN_AUDIO_CLKA, FN_CAN_TXCLK,
+            /* IP5_27_24 [4] */
+            FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
+            FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
+            FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
+            0, 0, 0, 0,
+            /* IP5_23_21 [3] */
+            FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
+            FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
+            /* IP5_20_17 [4] */
+            FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
+            FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
+            FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
+            0, 0, 0, 0,
+            /* IP5_16_15 [2] */
+            FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
+            /* IP5_14_13 [2] */
+            FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
+            /* IP5_12_11 [2] */
+            FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
+            /* IP5_10_9 [2] */
+            FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
+            /* IP5_8 [1] */
+            FN_DU1_DB7, FN_SDA2_D,
+            /* IP5_7 [1] */
+            FN_DU1_DB6, FN_SCL2_D,
+            /* IP5_6 [1] */
+            FN_DU1_DB5, FN_VI2_R7,
+            /* IP5_5 [1] */
+            FN_DU1_DB4, FN_VI2_R6,
+            /* IP5_4 [1] */
+            FN_DU1_DB3, FN_VI2_R5,
+            /* IP5_3 [1] */
+            FN_DU1_DB2, FN_VI2_R4,
+            /* IP5_2_0 [3] */
+            FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
+            FN_RX5, FN_RTS0_D_TANS_D, 0, 0 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
+                             1, 2, 2, 2, 2, 3, 2, 3, 3, 3, 1, 2, 2, 2, 2) {
+            /* IP6_31 [1] */
+            0, 0,
+            /* IP6_30_29 [2] */
+            FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
+            /* IP_28_27 [2] */
+            0, 0, 0, 0,
+            /* IP6_26_25 [2] */
+            FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
+            /* IP6_24_23 [2] */
+            FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
+            /* IP6_22_20 [3] */
+            FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
+            FN_TCLK0_D, 0, 0, 0,
+            /* IP6_19_18 [2] */
+            FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
+            /* IP6_17_15 [3] */
+            FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
+            FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
+            /* IP6_14_12 [3] */
+            FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
+            FN_SSI_WS9_C, 0, 0, 0,
+            /* IP6_11_9 [3] */
+            FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
+            FN_SSI_SCK9_C, 0, 0, 0,
+            /* IP6_8 [1] */
+            FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
+            /* IP6_7_6 [2] */
+            FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
+            /* IP6_5_4 [2] */
+            FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
+            /* IP6_3_2 [2] */
+            FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
+            /* IP6_1_0 [2] */
+            FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
+                             1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 2, 2) {
+            /* IP7_31 [1] */
+            0, 0,
+            /* IP7_30_29 [2] */
+            FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
+            /* IP7_28_27 [2] */
+            FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
+            /* IP7_26_25 [2] */
+            FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
+            /* IP7_24_23 [2] */
+            FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
+            /* IP7_22_21 [2] */
+            FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
+            /* IP7_20_19 [2] */
+            FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
+            /* IP7_18_17 [2] */
+            FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
+            /* IP7_16_15 [2] */
+            FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
+            /* IP7_14_13 [2] */
+            FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
+            /* IP7_12_10 [3] */
+            FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
+            FN_HSPI_TX1_C, 0, 0, 0,
+            /* IP7_9_7 [3] */
+            FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
+            FN_HSPI_CS1_C, 0, 0, 0,
+            /* IP7_6_4 [3] */
+            FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
+            FN_HSPI_CLK1_C, 0, 0, 0,
+            /* IP7_3_2 [2] */
+            FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
+            /* IP7_1_0 [2] */
+            FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
+                             1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4) {
+            /* IP8_31 [1] */
+            0, 0,
+            /* IP8_30_28 [3] */
+            FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
+            FN_PWMFSW0_C, 0, 0, 0,
+            /* IP8_27_25 [3] */
+            FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
+            FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
+            /* IP8_24_23 [2] */
+            FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
+            /* IP8_22_21 [2] */
+            FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
+            /* IP8_20 [1] */
+            FN_VI0_CLK, FN_MMC1_CLK,
+            /* IP8_19 [1] */
+            FN_FMIN, FN_RDS_DATA,
+            /* IP8_18 [1] */
+            FN_BPFCLK, FN_PCMWE,
+            /* IP8_17_16 [2] */
+            FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
+            /* IP8_15_12 [4] */
+            FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
+            FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
+            FN_CC5_STATE39, 0, 0, 0,
+            0, 0, 0, 0,
+            /* IP8_11_8 [4] */
+            FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
+            FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
+            FN_CC5_STATE38, 0, 0, 0,
+            0, 0, 0, 0,
+            /* IP8_7_4 [4] */
+            FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
+            FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
+            FN_CC5_STATE37, 0, 0, 0,
+            0, 0, 0, 0,
+            /* IP8_3_0 [4] */
+            FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
+            FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
+            FN_CC5_STATE36, 0, 0, 0,
+            0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
+                             2, 2, 2, 2, 2, 3, 3, 2, 2,
+                             2, 2, 1, 1, 1, 1, 2, 2) {
+            /* IP9_31_30 [2] */
+            0, 0, 0, 0,
+            /* IP9_29_28 [2] */
+            FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
+            /* IP9_27_26 [2] */
+            FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
+            /* IP9_25_24 [2] */
+            FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
+            /* IP9_23_22 [2] */
+            FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
+            /* IP9_21_19 [3] */
+            FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
+            FN_TS_SDAT0, 0, 0, 0,
+            /* IP9_18_16 [3] */
+            FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
+            FN_TS_SPSYNC0, 0, 0, 0,
+            /* IP9_15_14 [2] */
+            FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
+            /* IP9_13_12 [2] */
+            FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
+            /* IP9_11_10 [2] */
+            FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
+            /* IP9_9_8 [2] */
+            FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
+            /* IP9_7 [1] */
+            FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
+            /* IP9_6 [1] */
+            FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
+            /* IP9_5 [1] */
+            FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
+            /* IP9_4 [1] */
+            FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
+            /* IP9_3_2 [2] */
+            FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
+            /* IP9_1_0 [2] */
+            FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
+                             3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
+            /* IP10_31_29 [3] */
+            FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
+            FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
+            /* IP10_28_26 [3] */
+            FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
+            FN_PWMFSW0_E, 0, 0, 0,
+            /* IP10_25_24 [2] */
+            FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
+            /* IP10_23_21 [3] */
+            FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
+            FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
+            /* IP10_20_18 [3] */
+            FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
+            FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
+            /* IP10_17_15 [3] */
+            FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
+            FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
+            /* IP10_14_12 [3] */
+            FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
+            FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
+            /* IP10_11_9 [3] */
+            FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
+            FN_ARM_TRACEDATA_13, 0, 0, 0,
+            /* IP10_8_6 [3] */
+            FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
+            FN_ARM_TRACEDATA_12, 0, 0, 0,
+            /* IP10_5_3 [3] */
+            FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
+            FN_DACK0_C, FN_DRACK0_C, 0, 0,
+            /* IP10_2_0 [3] */
+            FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
+            FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
+                             2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+            /* IP11_31_30 [2] */
+            0, 0, 0, 0,
+            /* IP11_29_27 [3] */
+            FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
+            FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
+            /* IP11_26_24 [3] */
+            FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1,
+            FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
+            /* IP11_23_21 [3] */
+            FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
+            FN_HSPI_RX1_D, 0, 0, 0,
+            /* IP11_20_18 [3] */
+            FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
+            FN_HSPI_TX1_D, 0, 0, 0,
+            /* IP11_17_15 [3] */
+            FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
+            FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
+            /* IP11_14_12 [3] */
+            FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
+            FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
+            /* IP11_11_9 [3] */
+            FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
+            FN_ADICHS0_B, 0, 0, 0,
+            /* IP11_8_6 [3] */
+            FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
+            FN_ADIDATA_B, 0, 0, 0,
+            /* IP11_5_3 [3] */
+            FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
+            FN_ADICS_B_SAMP_B, 0, 0, 0,
+            /* IP11_2_0 [3] */
+            FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
+            FN_ADICLK_B, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
+                             4, 4, 4, 2, 3, 3, 3, 3, 3, 3) {
+            /* IP12_31_28 [4] */
+            0, 0, 0, 0, 0, 0, 0, 0,
+            0, 0, 0, 0, 0, 0, 0, 0,