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-rw-r--r--arch/sh/kernel/cpu/Makefile2
-rw-r--r--arch/sh/kernel/cpu/clock-cpg.c312
-rw-r--r--arch/sh/kernel/cpu/clock.c630
-rw-r--r--arch/sh/kernel/cpu/hwblk.c5
-rw-r--r--arch/sh/kernel/cpu/init.c24
-rw-r--r--arch/sh/kernel/cpu/sh2/probe.c5
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/probe.c4
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c9
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c9
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c12
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c15
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c4
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c9
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c9
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c9
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c24
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4-202.c17
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c4
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c9
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c15
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c9
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c231
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c210
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c177
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c279
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c295
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c11
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7763.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7780.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c176
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c223
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c13
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c16
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c13
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c21
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c27
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c81
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c18
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c27
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c24
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c30
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c157
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c18
-rw-r--r--arch/sh/kernel/cpu/sh4a/smp-shx3.c74
-rw-r--r--arch/sh/kernel/cpu/sh5/probe.c4
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c9
48 files changed, 1457 insertions, 1849 deletions
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 0e48bc61c27..4edcb60a135 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -16,7 +16,7 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
16# Common interfaces. 16# Common interfaces.
17 17
18obj-$(CONFIG_SH_ADC) += adc.o 18obj-$(CONFIG_SH_ADC) += adc.o
19obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o 19obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
20obj-$(CONFIG_SH_FPU) += fpu.o 20obj-$(CONFIG_SH_FPU) += fpu.o
21obj-$(CONFIG_SH_FPU_EMU) += fpu.o 21obj-$(CONFIG_SH_FPU_EMU) += fpu.o
22 22
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index eed5eaff96b..e2f63d68da5 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -2,317 +2,25 @@
2#include <linux/compiler.h> 2#include <linux/compiler.h>
3#include <linux/slab.h> 3#include <linux/slab.h>
4#include <linux/io.h> 4#include <linux/io.h>
5#include <asm/clkdev.h>
5#include <asm/clock.h> 6#include <asm/clock.h>
6 7
7static int sh_clk_mstp32_enable(struct clk *clk)
8{
9 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
10 clk->enable_reg);
11 return 0;
12}
13
14static void sh_clk_mstp32_disable(struct clk *clk)
15{
16 __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
17 clk->enable_reg);
18}
19
20static struct clk_ops sh_clk_mstp32_clk_ops = {
21 .enable = sh_clk_mstp32_enable,
22 .disable = sh_clk_mstp32_disable,
23 .recalc = followparent_recalc,
24};
25
26int __init sh_clk_mstp32_register(struct clk *clks, int nr)
27{
28 struct clk *clkp;
29 int ret = 0;
30 int k;
31
32 for (k = 0; !ret && (k < nr); k++) {
33 clkp = clks + k;
34 clkp->ops = &sh_clk_mstp32_clk_ops;
35 ret |= clk_register(clkp);
36 }
37
38 return ret;
39}
40
41static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
42{
43 return clk_rate_table_round(clk, clk->freq_table, rate);
44}
45
46static int sh_clk_div6_divisors[64] = {
47 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
48 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
49 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
50 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
51};
52
53static struct clk_div_mult_table sh_clk_div6_table = {
54 .divisors = sh_clk_div6_divisors,
55 .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
56};
57
58static unsigned long sh_clk_div6_recalc(struct clk *clk)
59{
60 struct clk_div_mult_table *table = &sh_clk_div6_table;
61 unsigned int idx;
62
63 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
64 table, NULL);
65
66 idx = __raw_readl(clk->enable_reg) & 0x003f;
67
68 return clk->freq_table[idx].frequency;
69}
70
71static int sh_clk_div6_set_rate(struct clk *clk,
72 unsigned long rate, int algo_id)
73{
74 unsigned long value;
75 int idx;
76
77 idx = clk_rate_table_find(clk, clk->freq_table, rate);
78 if (idx < 0)
79 return idx;
80
81 value = __raw_readl(clk->enable_reg);
82 value &= ~0x3f;
83 value |= idx;
84 __raw_writel(value, clk->enable_reg);
85 return 0;
86}
87
88static int sh_clk_div6_enable(struct clk *clk)
89{
90 unsigned long value;
91 int ret;
92
93 ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
94 if (ret == 0) {
95 value = __raw_readl(clk->enable_reg);
96 value &= ~0x100; /* clear stop bit to enable clock */
97 __raw_writel(value, clk->enable_reg);
98 }
99 return ret;
100}
101
102static void sh_clk_div6_disable(struct clk *clk)
103{
104 unsigned long value;
105
106 value = __raw_readl(clk->enable_reg);
107 value |= 0x100; /* stop clock */
108 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
109 __raw_writel(value, clk->enable_reg);
110}
111
112static struct clk_ops sh_clk_div6_clk_ops = {
113 .recalc = sh_clk_div6_recalc,
114 .round_rate = sh_clk_div_round_rate,
115 .set_rate = sh_clk_div6_set_rate,
116 .enable = sh_clk_div6_enable,
117 .disable = sh_clk_div6_disable,
118};
119
120int __init sh_clk_div6_register(struct clk *clks, int nr)
121{
122 struct clk *clkp;
123 void *freq_table;
124 int nr_divs = sh_clk_div6_table.nr_divisors;
125 int freq_table_size = sizeof(struct cpufreq_frequency_table);
126 int ret = 0;
127 int k;
128
129 freq_table_size *= (nr_divs + 1);
130 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
131 if (!freq_table) {
132 pr_err("sh_clk_div6_register: unable to alloc memory\n");
133 return -ENOMEM;
134 }
135
136 for (k = 0; !ret && (k < nr); k++) {
137 clkp = clks + k;
138
139 clkp->ops = &sh_clk_div6_clk_ops;
140 clkp->id = -1;
141 clkp->freq_table = freq_table + (k * freq_table_size);
142 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
143
144 ret = clk_register(clkp);
145 }
146
147 return ret;
148}
149
150static unsigned long sh_clk_div4_recalc(struct clk *clk)
151{
152 struct clk_div4_table *d4t = clk->priv;
153 struct clk_div_mult_table *table = d4t->div_mult_table;
154 unsigned int idx;
155
156 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
157 table, &clk->arch_flags);
158
159 idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
160
161 return clk->freq_table[idx].frequency;
162}
163
164static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
165{
166 struct clk_div4_table *d4t = clk->priv;
167 struct clk_div_mult_table *table = d4t->div_mult_table;
168 u32 value;
169 int ret;
170
171 if (!strcmp("pll_clk", parent->name))
172 value = __raw_readl(clk->enable_reg) & ~(1 << 7);
173 else
174 value = __raw_readl(clk->enable_reg) | (1 << 7);
175
176 ret = clk_reparent(clk, parent);
177 if (ret < 0)
178 return ret;
179
180 __raw_writel(value, clk->enable_reg);
181
182 /* Rebiuld the frequency table */
183 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
184 table, &clk->arch_flags);
185
186 return 0;
187}
188
189static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
190{
191 struct clk_div4_table *d4t = clk->priv;
192 unsigned long value;
193 int idx = clk_rate_table_find(clk, clk->freq_table, rate);
194 if (idx < 0)
195 return idx;
196
197 value = __raw_readl(clk->enable_reg);
198 value &= ~(0xf << clk->enable_bit);
199 value |= (idx << clk->enable_bit);
200 __raw_writel(value, clk->enable_reg);
201
202 if (d4t->kick)
203 d4t->kick(clk);
204
205 return 0;
206}
207
208static int sh_clk_div4_enable(struct clk *clk)
209{
210 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
211 return 0;
212}
213
214static void sh_clk_div4_disable(struct clk *clk)
215{
216 __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
217}
218
219static struct clk_ops sh_clk_div4_clk_ops = {
220 .recalc = sh_clk_div4_recalc,
221 .set_rate = sh_clk_div4_set_rate,
222 .round_rate = sh_clk_div_round_rate,
223};
224
225static struct clk_ops sh_clk_div4_enable_clk_ops = {
226 .recalc = sh_clk_div4_recalc,
227 .set_rate = sh_clk_div4_set_rate,
228 .round_rate = sh_clk_div_round_rate,
229 .enable = sh_clk_div4_enable,
230 .disable = sh_clk_div4_disable,
231};
232
233static struct clk_ops sh_clk_div4_reparent_clk_ops = {
234 .recalc = sh_clk_div4_recalc,
235 .set_rate = sh_clk_div4_set_rate,
236 .round_rate = sh_clk_div_round_rate,
237 .enable = sh_clk_div4_enable,
238 .disable = sh_clk_div4_disable,
239 .set_parent = sh_clk_div4_set_parent,
240};
241
242static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
243 struct clk_div4_table *table, struct clk_ops *ops)
244{
245 struct clk *clkp;
246 void *freq_table;
247 int nr_divs = table->div_mult_table->nr_divisors;
248 int freq_table_size = sizeof(struct cpufreq_frequency_table);
249 int ret = 0;
250 int k;
251
252 freq_table_size *= (nr_divs + 1);
253 freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
254 if (!freq_table) {
255 pr_err("sh_clk_div4_register: unable to alloc memory\n");
256 return -ENOMEM;
257 }
258
259 for (k = 0; !ret && (k < nr); k++) {
260 clkp = clks + k;
261
262 clkp->ops = ops;
263 clkp->id = -1;
264 clkp->priv = table;
265
266 clkp->freq_table = freq_table + (k * freq_table_size);
267 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
268
269 ret = clk_register(clkp);
270 }
271
272 return ret;
273}
274
275int __init sh_clk_div4_register(struct clk *clks, int nr,
276 struct clk_div4_table *table)
277{
278 return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
279}
280
281int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
282 struct clk_div4_table *table)
283{
284 return sh_clk_div4_register_ops(clks, nr, table,
285 &sh_clk_div4_enable_clk_ops);
286}
287
288int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
289 struct clk_div4_table *table)
290{
291 return sh_clk_div4_register_ops(clks, nr, table,
292 &sh_clk_div4_reparent_clk_ops);
293}
294
295#ifdef CONFIG_SH_CLK_CPG_LEGACY
296static struct clk master_clk = { 8static struct clk master_clk = {
297 .name = "master_clk",
298 .flags = CLK_ENABLE_ON_INIT, 9 .flags = CLK_ENABLE_ON_INIT,
299 .rate = CONFIG_SH_PCLK_FREQ, 10 .rate = CONFIG_SH_PCLK_FREQ,
300}; 11};
301 12
302static struct clk peripheral_clk = { 13static struct clk peripheral_clk = {
303 .name = "peripheral_clk",
304 .parent = &master_clk, 14 .parent = &master_clk,
305 .flags = CLK_ENABLE_ON_INIT, 15 .flags = CLK_ENABLE_ON_INIT,
306}; 16};
307 17
308static struct clk bus_clk = { 18static struct clk bus_clk = {
309 .name = "bus_clk",
310 .parent = &master_clk, 19 .parent = &master_clk,
311 .flags = CLK_ENABLE_ON_INIT, 20 .flags = CLK_ENABLE_ON_INIT,
312}; 21};
313 22
314static struct clk cpu_clk = { 23static struct clk cpu_clk = {
315 .name = "cpu_clk",
316 .parent = &master_clk, 24 .parent = &master_clk,
317 .flags = CLK_ENABLE_ON_INIT, 25 .flags = CLK_ENABLE_ON_INIT,
318}; 26};
@@ -327,6 +35,16 @@ static struct clk *onchip_clocks[] = {
327 &cpu_clk, 35 &cpu_clk,
328}; 36};
329 37
38#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
39
40static struct clk_lookup lookups[] = {
41 /* main clocks */
42 CLKDEV_CON_ID("master_clk", &master_clk),
43 CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
44 CLKDEV_CON_ID("bus_clk", &bus_clk),
45 CLKDEV_CON_ID("cpu_clk", &cpu_clk),
46};
47
330int __init __deprecated cpg_clk_init(void) 48int __init __deprecated cpg_clk_init(void)
331{ 49{
332 int i, ret = 0; 50 int i, ret = 0;
@@ -338,6 +56,13 @@ int __init __deprecated cpg_clk_init(void)
338 ret |= clk_register(clk); 56 ret |= clk_register(clk);
339 } 57 }
340 58
59 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
60
61 clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
62 clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
63 clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
64 clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
65
341 return ret; 66 return ret;
342} 67}
343 68
@@ -349,4 +74,3 @@ int __init __weak arch_clk_init(void)
349{ 74{
350 return cpg_clk_init(); 75 return cpg_clk_init();
351} 76}
352#endif /* CONFIG_SH_CPG_CLK_LEGACY */
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index e9fa1bfed53..50f887dda56 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -10,558 +10,16 @@
10 * 10 *
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> 11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
12 * 12 *
13 * With clkdev bits:
14 *
15 * Copyright (C) 2008 Russell King.
16 *
17 * This file is subject to the terms and conditions of the GNU General Public 13 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive 14 * License. See the file "COPYING" in the main directory of this archive
19 * for more details. 15 * for more details.
20 */ 16 */
21#include <linux/kernel.h> 17#include <linux/kernel.h>
22#include <linux/init.h> 18#include <linux/init.h>
23#include <linux/module.h> 19#include <linux/clk.h>
24#include <linux/mutex.h>
25#include <linux/list.h>
26#include <linux/kobject.h>
27#include <linux/sysdev.h>
28#include <linux/seq_file.h>
29#include <linux/err.h>
30#include <linux/platform_device.h>
31#include <linux/debugfs.h>
32#include <linux/cpufreq.h>
33#include <asm/clock.h> 20#include <asm/clock.h>
34#include <asm/machvec.h> 21#include <asm/machvec.h>
35 22
36static LIST_HEAD(clock_list);
37static DEFINE_SPINLOCK(clock_lock);
38static DEFINE_MUTEX(clock_list_sem);
39
40void clk_rate_table_build(struct clk *clk,
41 struct cpufreq_frequency_table *freq_table,
42 int nr_freqs,
43 struct clk_div_mult_table *src_table,
44 unsigned long *bitmap)
45{
46 unsigned long mult, div;
47 unsigned long freq;
48 int i;
49
50 for (i = 0; i < nr_freqs; i++) {
51 div = 1;
52 mult = 1;
53
54 if (src_table->divisors && i < src_table->nr_divisors)
55 div = src_table->divisors[i];
56
57 if (src_table->multipliers && i < src_table->nr_multipliers)
58 mult = src_table->multipliers[i];
59
60 if (!div || !mult || (bitmap && !test_bit(i, bitmap)))
61 freq = CPUFREQ_ENTRY_INVALID;
62 else
63 freq = clk->parent->rate * mult / div;
64
65 freq_table[i].index = i;
66 freq_table[i].frequency = freq;
67 }
68
69 /* Termination entry */
70 freq_table[i].index = i;
71 freq_table[i].frequency = CPUFREQ_TABLE_END;
72}
73
74long clk_rate_table_round(struct clk *clk,
75 struct cpufreq_frequency_table *freq_table,
76 unsigned long rate)
77{
78 unsigned long rate_error, rate_error_prev = ~0UL;
79 unsigned long rate_best_fit = rate;
80 unsigned long highest, lowest;
81 int i;
82
83 highest = lowest = 0;
84
85 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
86 unsigned long freq = freq_table[i].frequency;
87
88 if (freq == CPUFREQ_ENTRY_INVALID)
89 continue;
90
91 if (freq > highest)
92 highest = freq;
93 if (freq < lowest)
94 lowest = freq;
95
96 rate_error = abs(freq - rate);
97 if (rate_error < rate_error_prev) {
98 rate_best_fit = freq;
99 rate_error_prev = rate_error;
100 }
101
102 if (rate_error == 0)
103 break;
104 }
105
106 if (rate >= highest)
107 rate_best_fit = highest;
108 if (rate <= lowest)
109 rate_best_fit = lowest;
110
111 return rate_best_fit;
112}
113
114int clk_rate_table_find(struct clk *clk,
115 struct cpufreq_frequency_table *freq_table,
116 unsigned long rate)
117{
118 int i;
119
120 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
121 unsigned long freq = freq_table[i].frequency;
122
123 if (freq == CPUFREQ_ENTRY_INVALID)
124 continue;
125
126 if (freq == rate)
127 return i;
128 }
129
130 return -ENOENT;
131}
132
133/* Used for clocks that always have same value as the parent clock */
134unsigned long followparent_recalc(struct clk *clk)
135{
136 return clk->parent ? clk->parent->rate : 0;
137}
138
139int clk_reparent(struct clk *child, struct clk *parent)
140{
141 list_del_init(&child->sibling);
142 if (parent)
143 list_add(&child->sibling, &parent->children);
144 child->parent = parent;
145
146 /* now do the debugfs renaming to reattach the child
147 to the proper parent */
148
149 return 0;
150}
151
152/* Propagate rate to children */
153void propagate_rate(struct clk *tclk)
154{
155 struct clk *clkp;
156
157 list_for_each_entry(clkp, &tclk->children, sibling) {
158 if (clkp->ops && clkp->ops->recalc)
159 clkp->rate = clkp->ops->recalc(clkp);
160
161 propagate_rate(clkp);
162 }
163}
164
165static void __clk_disable(struct clk *clk)
166{
167 if (clk->usecount == 0) {
168 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
169 clk->name);
170 WARN_ON(1);
171 return;
172 }
173
174 if (!(--clk->usecount)) {
175 if (likely(clk->ops && clk->ops->disable))
176 clk->ops->disable(clk);
177 if (likely(clk->parent))
178 __clk_disable(clk->parent);
179 }
180}
181
182void clk_disable(struct clk *clk)
183{
184 unsigned long flags;
185
186 if (!clk)
187 return;
188
189 spin_lock_irqsave(&clock_lock, flags);
190 __clk_disable(clk);
191 spin_unlock_irqrestore(&clock_lock, flags);
192}
193EXPORT_SYMBOL_GPL(clk_disable);
194
195static int __clk_enable(struct clk *clk)
196{
197 int ret = 0;
198
199 if (clk->usecount++ == 0) {
200 if (clk->parent) {
201 ret = __clk_enable(clk->parent);
202 if (unlikely(ret))
203 goto err;
204 }
205
206 if (clk->ops && clk->ops->enable) {
207 ret = clk->ops->enable(clk);
208 if (ret) {
209 if (clk->parent)
210 __clk_disable(clk->parent);
211 goto err;
212 }
213 }
214 }
215
216 return ret;
217err:
218 clk->usecount--;
219 return ret;
220}
221
222int clk_enable(struct clk *clk)
223{
224 unsigned long flags;
225 int ret;
226
227 if (!clk)
228 return -EINVAL;
229
230 spin_lock_irqsave(&clock_lock, flags);
231 ret = __clk_enable(clk);
232 spin_unlock_irqrestore(&clock_lock, flags);
233
234 return ret;
235}
236EXPORT_SYMBOL_GPL(clk_enable);
237
238static LIST_HEAD(root_clks);
239
240/**
241 * recalculate_root_clocks - recalculate and propagate all root clocks
242 *
243 * Recalculates all root clocks (clocks with no parent), which if the
244 * clock's .recalc is set correctly, should also propagate their rates.
245 * Called at init.
246 */
247void recalculate_root_clocks(void)
248{
249 struct clk *clkp;
250
251 list_for_each_entry(clkp, &root_clks, sibling) {
252 if (clkp->ops && clkp->ops->recalc)
253 clkp->rate = clkp->ops->recalc(clkp);
254 propagate_rate(clkp);
255 }
256}
257
258int clk_register(struct clk *clk)
259{
260 if (clk == NULL || IS_ERR(clk))
261 return -EINVAL;
262
263 /*
264 * trap out already registered clocks
265 */
266 if (clk->node.next || clk->node.prev)
267 return 0;
268
269 mutex_lock(&clock_list_sem);
270
271 INIT_LIST_HEAD(&clk->children);
272 clk->usecount = 0;
273
274 if (clk->parent)
275 list_add(&clk->sibling, &clk->parent->children);
276 else
277 list_add(&clk->sibling, &root_clks);
278
279 list_add(&clk->node, &clock_list);
280 if (clk->ops && clk->ops->init)
281 clk->ops->init(clk);
282 mutex_unlock(&clock_list_sem);
283
284 return 0;
285}
286EXPORT_SYMBOL_GPL(clk_register);
287
288void clk_unregister(struct clk *clk)
289{
290 mutex_lock(&clock_list_sem);
291 list_del(&clk->sibling);
292 list_del(&clk->node);
293 mutex_unlock(&clock_list_sem);
294}
295EXPORT_SYMBOL_GPL(clk_unregister);
296
297static void clk_enable_init_clocks(void)
298{
299 struct clk *clkp;
300
301 list_for_each_entry(clkp, &clock_list, node)
302 if (clkp->flags & CLK_ENABLE_ON_INIT)
303 clk_enable(clkp);
304}
305
306unsigned long clk_get_rate(struct clk *clk)
307{
308 return clk->rate;
309}
310EXPORT_SYMBOL_GPL(clk_get_rate);
311
312int clk_set_rate(struct clk *clk, unsigned long rate)
313{
314 return clk_set_rate_ex(clk, rate, 0);
315}
316EXPORT_SYMBOL_GPL(clk_set_rate);
317
318int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
319{
320 int ret = -EOPNOTSUPP;
321 unsigned long flags;
322
323 spin_lock_irqsave(&clock_lock, flags);
324
325 if (likely(clk->ops && clk->ops->set_rate)) {
326 ret = clk->ops->set_rate(clk, rate, algo_id);
327 if (ret != 0)
328 goto out_unlock;
329 } else {
330 clk->rate = rate;
331 ret = 0;
332 }
333
334 if (clk->ops && clk->ops->recalc)
335 clk->rate = clk->ops->recalc(clk);
336
337 propagate_rate(clk);
338
339out_unlock:
340 spin_unlock_irqrestore(&clock_lock, flags);
341
342 return ret;
343}
344EXPORT_SYMBOL_GPL(clk_set_rate_ex);
345
346int clk_set_parent(struct clk *clk, struct clk *parent)
347{
348 unsigned long flags;
349 int ret = -EINVAL;
350
351 if (!parent || !clk)
352 return ret;
353 if (clk->parent == parent)
354 return 0;
355
356 spin_lock_irqsave(&clock_lock, flags);
357 if (clk->usecount == 0) {
358 if (clk->ops->set_parent)
359 ret = clk->ops->set_parent(clk, parent);
360 else
361 ret = clk_reparent(clk, parent);
362
363 if (ret == 0) {
364 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
365 clk->name, clk->parent->name, clk->rate);
366 if (clk->ops->recalc)
367 clk->rate = clk->ops->recalc(clk);
368 propagate_rate(clk);
369 }
370 } else
371 ret = -EBUSY;
372 spin_unlock_irqrestore(&clock_lock, flags);
373
374 return ret;
375}
376EXPORT_SYMBOL_GPL(clk_set_parent);
377
378struct clk *clk_get_parent(struct clk *clk)
379{
380 return clk->parent;
381}
382EXPORT_SYMBOL_GPL(clk_get_parent);
383
384long clk_round_rate(struct clk *clk, unsigned long rate)
385{
386 if (likely(clk->ops && clk->ops->round_rate)) {
387 unsigned long flags, rounded;
388
389 spin_lock_irqsave(&clock_lock, flags);
390 rounded = clk->ops->round_rate(clk, rate);
391 spin_unlock_irqrestore(&clock_lock, flags);
392
393 return rounded;
394 }
395
396 return clk_get_rate(clk);
397}
398EXPORT_SYMBOL_GPL(clk_round_rate);
399
400/*
401 * Find the correct struct clk for the device and connection ID.
402 * We do slightly fuzzy matching here:
403 * An entry with a NULL ID is assumed to be a wildcard.
404 * If an entry has a device ID, it must match
405 * If an entry has a connection ID, it must match
406 * Then we take the most specific entry - with the following
407 * order of precedence: dev+con > dev only > con only.
408 */
409static struct clk *clk_find(const char *dev_id, const char *con_id)
410{
411 struct clk_lookup *p;
412 struct clk *clk = NULL;
413 int match, best = 0;
414
415 list_for_each_entry(p, &clock_list, node) {
416 match = 0;
417 if (p->dev_id) {
418 if (!dev_id || strcmp(p->dev_id, dev_id))
419 continue;
420 match += 2;
421 }
422 if (p->con_id) {
423 if (!con_id || strcmp(p->con_id, con_id))
424 continue;
425 match += 1;
426 }
427 if (match == 0)
428 continue;
429
430 if (match > best) {
431 clk = p->clk;
432 best = match;
433 }
434 }
435 return clk;
436}
437
438struct clk *clk_get_sys(const char *dev_id, const char *con_id)
439{
440 struct clk *clk;
441
442 mutex_lock(&clock_list_sem);
443 clk = clk_find(dev_id, con_id);
444 mutex_unlock(&clock_list_sem);
445
446 return clk ? clk : ERR_PTR(-ENOENT);
447}
448EXPORT_SYMBOL_GPL(clk_get_sys);
449
450/*
451 * Returns a clock. Note that we first try to use device id on the bus
452 * and clock name. If this fails, we try to use clock name only.
453 */
454struct clk *clk_get(struct device *dev, const char *id)
455{
456 const char *dev_id = dev ? dev_name(dev) : NULL;
457 struct clk *p, *clk = ERR_PTR(-ENOENT);
458 int idno;
459
460 clk = clk_get_sys(dev_id, id);
461 if (clk && !IS_ERR(clk))
462 return clk;
463
464 if (dev == NULL || dev->bus != &platform_bus_type)
465 idno = -1;
466 else
467 idno = to_platform_device(dev)->id;
468
469 mutex_lock(&clock_list_sem);
470 list_for_each_entry(p, &clock_list, node) {
471 if (p->id == idno &&
472 strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
473 clk = p;
474 goto found;
475 }
476 }
477
478 list_for_each_entry(p, &clock_list, node) {
479 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
480 clk = p;
481 break;
482 }
483 }
484
485found:
486 mutex_unlock(&clock_list_sem);
487
488 return clk;
489}
490EXPORT_SYMBOL_GPL(clk_get);
491
492void clk_put(struct clk *clk)
493{
494 if (clk && !IS_ERR(clk))
495 module_put(clk->owner);
496}
497EXPORT_SYMBOL_GPL(clk_put);
498
499#ifdef CONFIG_PM
500static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
501{
502 static pm_message_t prev_state;
503 struct clk *clkp;
504
505 switch (state.event) {
506 case PM_EVENT_ON:
507 /* Resumeing from hibernation */
508 if (prev_state.event != PM_EVENT_FREEZE)
509 break;
510
511 list_for_each_entry(clkp, &clock_list, node) {
512 if (likely(clkp->ops)) {
513 unsigned long rate = clkp->rate;
514
515 if (likely(clkp->ops->set_parent))
516 clkp->ops->set_parent(clkp,
517 clkp->parent);
518 if (likely(clkp->ops->set_rate))
519 clkp->ops->set_rate(clkp,
520 rate, NO_CHANGE);
521 else if (likely(clkp->ops->recalc))
522 clkp->rate = clkp->ops->recalc(clkp);
523 }
524 }
525 break;
526 case PM_EVENT_FREEZE:
527 break;
528 case PM_EVENT_SUSPEND:
529 break;
530 }
531
532 prev_state = state;
533 return 0;
534}
535
536static int clks_sysdev_resume(struct sys_device *dev)
537{
538 return clks_sysdev_suspend(dev, PMSG_ON);
539}
540
541static struct sysdev_class clks_sysdev_class = {
542 .name = "clks",
543};
544
545static struct sysdev_driver clks_sysdev_driver = {
546 .suspend = clks_sysdev_suspend,
547 .resume = clks_sysdev_resume,
548};
549
550static struct sys_device clks_sysdev_dev = {
551 .cls = &clks_sysdev_class,
552};
553
554static int __init clk_sysdev_init(void)
555{
556 sysdev_class_register(&clks_sysdev_class);
557 sysdev_driver_register(&clks_sysdev_class, &clks_sysdev_driver);
558 sysdev_register(&clks_sysdev_dev);
559
560 return 0;
561}
562subsys_initcall(clk_sysdev_init);
563#endif
564
565int __init clk_init(void) 23int __init clk_init(void)
566{ 24{
567 int ret; 25 int ret;
@@ -591,89 +49,19 @@ int __init clk_init(void)
591} 49}
592 50
593/* 51/*
594 * debugfs support to trace clock tree hierarchy and attributes 52 * Returns a clock. Note that we first try to use device id on the bus
53 * and clock name. If this fails, we try to use clock name only.
595 */ 54 */
596static struct dentry *clk_debugfs_root; 55struct clk *clk_get(struct device *dev, const char *con_id)
597
598static int clk_debugfs_register_one(struct clk *c)
599{ 56{
600 int err; 57 const char *dev_id = dev ? dev_name(dev) : NULL;
601 struct dentry *d, *child, *child_tmp;
602 struct clk *pa = c->parent;
603 char s[255];
604 char *p = s;
605
606 p += sprintf(p, "%s", c->name);
607 if (c->id >= 0)
608 sprintf(p, ":%d", c->id);
609 d = debugfs_create_dir(s, pa ? pa->dentry : clk_debugfs_root);
610 if (!d)
611 return -ENOMEM;
612 c->dentry = d;
613
614 d = debugfs_create_u8("usecount", S_IRUGO, c->dentry, (u8 *)&c->usecount);
615 if (!d) {
616 err = -ENOMEM;
617 goto err_out;
618 }
619 d = debugfs_create_u32("rate", S_IRUGO, c->dentry, (u32 *)&c->rate);
620 if (!d) {
621 err = -ENOMEM;
622 goto err_out;
623 }
624 d = debugfs_create_x32("flags", S_IRUGO, c->dentry, (u32 *)&c->flags);
625 if (!d) {
626 err = -ENOMEM;
627 goto err_out;
628 }
629 return 0;
630 58
631err_out: 59 return clk_get_sys(dev_id, con_id);
632 d = c->dentry;
633 list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
634 debugfs_remove(child);
635 debugfs_remove(c->dentry);
636 return err;
637} 60}
61EXPORT_SYMBOL_GPL(clk_get);
638 62
639static int clk_debugfs_register(struct clk *c) 63void clk_put(struct clk *clk)
640{ 64{
641 int err;
642 struct clk *pa = c->parent;
643
644 if (pa && !pa->dentry) {
645 err = clk_debugfs_register(pa);
646 if (err)
647 return err;
648 }
649
650 if (!c->dentry) {
651 err = clk_debugfs_register_one(c);
652 if (err)
653 return err;
654 }
655 return 0;
656} 65}
66EXPORT_SYMBOL_GPL(clk_put);
657 67
658static int __init clk_debugfs_init(void)
659{
660 struct clk *c;
661 struct dentry *d;
662 int err;
663
664 d = debugfs_create_dir("clock", NULL);
665 if (!d)
666 return -ENOMEM;
667 clk_debugfs_root = d;
668
669 list_for_each_entry(c, &clock_list, node) {
670 err = clk_debugfs_register(c);
671 if (err)
672 goto err_out;
673 }
674 return 0;
675err_out:
676 debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
677 return err;
678}
679late_initcall(clk_debugfs_init);
diff --git a/arch/sh/kernel/cpu/hwblk.c b/arch/sh/kernel/cpu/hwblk.c
index 67a1e811cfe..3e985aae5d9 100644
--- a/arch/sh/kernel/cpu/hwblk.c
+++ b/arch/sh/kernel/cpu/hwblk.c
@@ -146,6 +146,11 @@ int __init sh_hwblk_clk_register(struct clk *clks, int nr)
146 146
147 for (k = 0; !ret && (k < nr); k++) { 147 for (k = 0; !ret && (k < nr); k++) {
148 clkp = clks + k; 148 clkp = clks + k;
149
150 /* skip over clocks using hwblk 0 (HWBLK_UNKNOWN) */
151 if (!clkp->arch_flags)
152 continue;
153
149 clkp->ops = &sh_hwblk_clk_ops; 154 clkp->ops = &sh_hwblk_clk_ops;
150 ret |= clk_register(clkp); 155 ret |= clk_register(clkp);
151 } 156 }
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index c736422344e..97661061ff2 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -43,9 +43,9 @@
43 * peripherals (nofpu, nodsp, and so forth). 43 * peripherals (nofpu, nodsp, and so forth).
44 */ 44 */
45#define onchip_setup(x) \ 45#define onchip_setup(x) \
46static int x##_disabled __initdata = !cpu_has_##x; \ 46static int x##_disabled __cpuinitdata = !cpu_has_##x; \
47 \ 47 \
48static int __init x##_setup(char *opts) \ 48static int __cpuinit x##_setup(char *opts) \
49{ \ 49{ \
50 x##_disabled = 1; \ 50 x##_disabled = 1; \
51 return 1; \ 51 return 1; \
@@ -59,7 +59,7 @@ onchip_setup(dsp);
59#define CPUOPM 0xff2f0000 59#define CPUOPM 0xff2f0000
60#define CPUOPM_RABD (1 << 5) 60#define CPUOPM_RABD (1 << 5)
61 61
62static void __init speculative_execution_init(void) 62static void __cpuinit speculative_execution_init(void)
63{ 63{
64 /* Clear RABD */ 64 /* Clear RABD */
65 __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); 65 __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
@@ -78,7 +78,7 @@ static void __init speculative_execution_init(void)
78#define EXPMASK_BRDSSLP (1 << 1) 78#define EXPMASK_BRDSSLP (1 << 1)
79#define EXPMASK_MMCAW (1 << 4) 79#define EXPMASK_MMCAW (1 << 4)
80 80
81static void __init expmask_init(void) 81static void __cpuinit expmask_init(void)
82{ 82{
83 unsigned long expmask = __raw_readl(EXPMASK); 83 unsigned long expmask = __raw_readl(EXPMASK);
84 84
@@ -217,7 +217,7 @@ static void detect_cache_shape(void)
217 l2_cache_shape = -1; /* No S-cache */ 217 l2_cache_shape = -1; /* No S-cache */
218} 218}
219 219
220static void __init fpu_init(void) 220static void __cpuinit fpu_init(void)
221{ 221{
222 /* Disable the FPU */ 222 /* Disable the FPU */
223 if (fpu_disabled && (current_cpu_data.flags & CPU_HAS_FPU)) { 223 if (fpu_disabled && (current_cpu_data.flags & CPU_HAS_FPU)) {
@@ -230,7 +230,7 @@ static void __init fpu_init(void)
230} 230}
231 231
232#ifdef CONFIG_SH_DSP 232#ifdef CONFIG_SH_DSP
233static void __init release_dsp(void) 233static void __cpuinit release_dsp(void)
234{ 234{
235 unsigned long sr; 235 unsigned long sr;
236 236
@@ -244,7 +244,7 @@ static void __init release_dsp(void)
244 ); 244 );
245} 245}
246 246
247static void __init dsp_init(void) 247static void __cpuinit dsp_init(void)
248{ 248{
249 unsigned long sr; 249 unsigned long sr;
250 250
@@ -276,11 +276,11 @@ static void __init dsp_init(void)
276 release_dsp(); 276 release_dsp();
277} 277}
278#else 278#else
279static inline void __init dsp_init(void) { } 279static inline void __cpuinit dsp_init(void) { }
280#endif /* CONFIG_SH_DSP */ 280#endif /* CONFIG_SH_DSP */
281 281
282/** 282/**
283 * sh_cpu_init 283 * cpu_init
284 * 284 *
285 * This is our initial entry point for each CPU, and is invoked on the 285 * This is our initial entry point for each CPU, and is invoked on the
286 * boot CPU prior to calling start_kernel(). For SMP, a combination of 286 * boot CPU prior to calling start_kernel(). For SMP, a combination of
@@ -293,14 +293,14 @@ static inline void __init dsp_init(void) { }
293 * subtype and initial configuration will all be done. 293 * subtype and initial configuration will all be done.
294 * 294 *
295 * Each processor family is still responsible for doing its own probing 295 * Each processor family is still responsible for doing its own probing
296 * and cache configuration in detect_cpu_and_cache_system(). 296 * and cache configuration in cpu_probe().
297 */ 297 */
298asmlinkage void __init sh_cpu_init(void) 298asmlinkage void __cpuinit cpu_init(void)
299{ 299{
300 current_thread_info()->cpu = hard_smp_processor_id(); 300 current_thread_info()->cpu = hard_smp_processor_id();
301 301
302 /* First, probe the CPU */ 302 /* First, probe the CPU */
303 detect_cpu_and_cache_system(); 303 cpu_probe();
304 304
305 if (current_cpu_data.type == CPU_SH_NONE) 305 if (current_cpu_data.type == CPU_SH_NONE)
306 panic("Unknown CPU"); 306 panic("Unknown CPU");
diff --git a/arch/sh/kernel/cpu/sh2/probe.c b/arch/sh/kernel/cpu/sh2/probe.c
index 1db6d888388..bab8e75958a 100644
--- a/arch/sh/kernel/cpu/sh2/probe.c
+++ b/arch/sh/kernel/cpu/sh2/probe.c
@@ -13,7 +13,7 @@
13#include <asm/processor.h> 13#include <asm/processor.h>
14#include <asm/cache.h> 14#include <asm/cache.h>
15 15
16int __init detect_cpu_and_cache_system(void) 16void __cpuinit cpu_probe(void)
17{ 17{
18#if defined(CONFIG_CPU_SUBTYPE_SH7619) 18#if defined(CONFIG_CPU_SUBTYPE_SH7619)
19 boot_cpu_data.type = CPU_SH7619; 19 boot_cpu_data.type = CPU_SH7619;
@@ -30,7 +30,4 @@ int __init detect_cpu_and_cache_system(void)
30 boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED; 30 boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
31 boot_cpu_data.icache = boot_cpu_data.dcache; 31 boot_cpu_data.icache = boot_cpu_data.dcache;
32 boot_cpu_data.family = CPU_FAMILY_SH2; 32 boot_cpu_data.family = CPU_FAMILY_SH2;
33
34 return 0;
35} 33}
36
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 114c7cee718..c3638516bff 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -128,17 +128,14 @@ static struct platform_device eth_device = {
128}; 128};
129 129
130static struct sh_timer_config cmt0_platform_data = { 130static struct sh_timer_config cmt0_platform_data = {
131 .name = "CMT0",
132 .channel_offset = 0x02, 131 .channel_offset = 0x02,
133 .timer_bit = 0, 132 .timer_bit = 0,
134 .clk = "peripheral_clk",
135 .clockevent_rating = 125, 133 .clockevent_rating = 125,
136 .clocksource_rating = 0, /* disabled due to code generation issues */ 134 .clocksource_rating = 0, /* disabled due to code generation issues */
137}; 135};
138 136
139static struct resource cmt0_resources[] = { 137static struct resource cmt0_resources[] = {
140 [0] = { 138 [0] = {
141 .name = "CMT0",
142 .start = 0xf84a0072, 139 .start = 0xf84a0072,
143 .end = 0xf84a0077, 140 .end = 0xf84a0077,
144 .flags = IORESOURCE_MEM, 141 .flags = IORESOURCE_MEM,
@@ -160,17 +157,14 @@ static struct platform_device cmt0_device = {
160}; 157};
161 158
162static struct sh_timer_config cmt1_platform_data = { 159static struct sh_timer_config cmt1_platform_data = {
163 .name = "CMT1",
164 .channel_offset = 0x08, 160 .channel_offset = 0x08,
165 .timer_bit = 1, 161 .timer_bit = 1,
166 .clk = "peripheral_clk",
167 .clockevent_rating = 125, 162 .clockevent_rating = 125,
168 .clocksource_rating = 0, /* disabled due to code generation issues */ 163 .clocksource_rating = 0, /* disabled due to code generation issues */
169}; 164};
170 165
171static struct resource cmt1_resources[] = { 166static struct resource cmt1_resources[] = {
172 [0] = { 167 [0] = {
173 .name = "CMT1",
174 .start = 0xf84a0078, 168 .start = 0xf84a0078,
175 .end = 0xf84a007d, 169 .end = 0xf84a007d,
176 .flags = IORESOURCE_MEM, 170 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index 6825d650716..48e97a2a0c8 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -13,7 +13,7 @@
13#include <asm/processor.h> 13#include <asm/processor.h>
14#include <asm/cache.h> 14#include <asm/cache.h>
15 15
16int __init detect_cpu_and_cache_system(void) 16void __cpuinit cpu_probe(void)
17{ 17{
18 boot_cpu_data.family = CPU_FAMILY_SH2A; 18 boot_cpu_data.family = CPU_FAMILY_SH2A;
19 19
@@ -51,6 +51,4 @@ int __init detect_cpu_and_cache_system(void)
51 * on the cache info. 51 * on the cache info.
52 */ 52 */
53 boot_cpu_data.icache = boot_cpu_data.dcache; 53 boot_cpu_data.icache = boot_cpu_data.dcache;
54
55 return 0;
56} 54}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 8f669dc9b0d..6c96ea02bf8 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -115,16 +115,13 @@ static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
115 mask_registers, prio_registers, NULL); 115 mask_registers, prio_registers, NULL);
116 116
117static struct sh_timer_config mtu2_0_platform_data = { 117static struct sh_timer_config mtu2_0_platform_data = {
118 .name = "MTU2_0",
119 .channel_offset = -0x80, 118 .channel_offset = -0x80,
120 .timer_bit = 0, 119 .timer_bit = 0,
121 .clk = "peripheral_clk",
122 .clockevent_rating = 200, 120 .clockevent_rating = 200,
123}; 121};
124 122
125static struct resource mtu2_0_resources[] = { 123static struct resource mtu2_0_resources[] = {
126 [0] = { 124 [0] = {
127 .name = "MTU2_0",
128 .start = 0xff801300, 125 .start = 0xff801300,
129 .end = 0xff801326, 126 .end = 0xff801326,
130 .flags = IORESOURCE_MEM, 127 .flags = IORESOURCE_MEM,
@@ -146,16 +143,13 @@ static struct platform_device mtu2_0_device = {
146}; 143};
147 144
148static struct sh_timer_config mtu2_1_platform_data = { 145static struct sh_timer_config mtu2_1_platform_data = {
149 .name = "MTU2_1",
150 .channel_offset = -0x100, 146 .channel_offset = -0x100,
151 .timer_bit = 1, 147 .timer_bit = 1,
152 .clk = "peripheral_clk",
153 .clockevent_rating = 200, 148 .clockevent_rating = 200,
154}; 149};
155 150
156static struct resource mtu2_1_resources[] = { 151static struct resource mtu2_1_resources[] = {
157 [0] = { 152 [0] = {
158 .name = "MTU2_1",
159 .start = 0xff801380, 153 .start = 0xff801380,
160 .end = 0xff801390, 154 .end = 0xff801390,
161 .flags = IORESOURCE_MEM, 155 .flags = IORESOURCE_MEM,
@@ -177,16 +171,13 @@ static struct platform_device mtu2_1_device = {
177}; 171};
178 172
179static struct sh_timer_config mtu2_2_platform_data = { 173static struct sh_timer_config mtu2_2_platform_data = {
180 .name = "MTU2_2",
181 .channel_offset = 0x80, 174 .channel_offset = 0x80,
182 .timer_bit = 2, 175 .timer_bit = 2,
183 .clk = "peripheral_clk",
184 .clockevent_rating = 200, 176 .clockevent_rating = 200,
185}; 177};
186 178
187static struct resource mtu2_2_resources[] = { 179static struct resource mtu2_2_resources[] = {
188 [0] = { 180 [0] = {
189 .name = "MTU2_2",
190 .start = 0xff801000, 181 .start = 0xff801000,
191 .end = 0xff80100a, 182 .end = 0xff80100a,
192 .flags = IORESOURCE_MEM, 183 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 4ccfeb59eb1..d08bf4c07d6 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -318,16 +318,13 @@ static struct platform_device rtc_device = {
318}; 318};
319 319
320static struct sh_timer_config mtu2_0_platform_data = { 320static struct sh_timer_config mtu2_0_platform_data = {
321 .name = "MTU2_0",
322 .channel_offset = -0x80, 321 .channel_offset = -0x80,
323 .timer_bit = 0, 322 .timer_bit = 0,
324 .clk = "peripheral_clk",
325 .clockevent_rating = 200, 323 .clockevent_rating = 200,
326}; 324};
327 325
328static struct resource mtu2_0_resources[] = { 326static struct resource mtu2_0_resources[] = {
329 [0] = { 327 [0] = {
330 .name = "MTU2_0",
331 .start = 0xfffe4300, 328 .start = 0xfffe4300,
332 .end = 0xfffe4326, 329 .end = 0xfffe4326,
333 .flags = IORESOURCE_MEM, 330 .flags = IORESOURCE_MEM,
@@ -349,16 +346,13 @@ static struct platform_device mtu2_0_device = {
349}; 346};
350 347
351static struct sh_timer_config mtu2_1_platform_data = { 348static struct sh_timer_config mtu2_1_platform_data = {
352 .name = "MTU2_1",
353 .channel_offset = -0x100, 349 .channel_offset = -0x100,
354 .timer_bit = 1, 350 .timer_bit = 1,
355 .clk = "peripheral_clk",
356 .clockevent_rating = 200, 351 .clockevent_rating = 200,
357}; 352};
358 353
359static struct resource mtu2_1_resources[] = { 354static struct resource mtu2_1_resources[] = {
360 [0] = { 355 [0] = {
361 .name = "MTU2_1",
362 .start = 0xfffe4380, 356 .start = 0xfffe4380,
363 .end = 0xfffe4390, 357 .end = 0xfffe4390,
364 .flags = IORESOURCE_MEM, 358 .flags = IORESOURCE_MEM,
@@ -380,16 +374,13 @@ static struct platform_device mtu2_1_device = {
380}; 374};
381 375
382static struct sh_timer_config mtu2_2_platform_data = { 376static struct sh_timer_config mtu2_2_platform_data = {
383 .name = "MTU2_2",
384 .channel_offset = 0x80, 377 .channel_offset = 0x80,
385 .timer_bit = 2, 378 .timer_bit = 2,
386 .clk = "peripheral_clk",
387 .clockevent_rating = 200, 379 .clockevent_rating = 200,
388}; 380};
389 381
390static struct resource mtu2_2_resources[] = { 382static struct resource mtu2_2_resources[] = {
391 [0] = { 383 [0] = {
392 .name = "MTU2_2",
393 .start = 0xfffe4000, 384 .start = 0xfffe4000,
394 .end = 0xfffe400a, 385 .end = 0xfffe400a,
395 .flags = IORESOURCE_MEM, 386 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 3136966cc9b..832f401b586 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -234,17 +234,14 @@ static struct platform_device scif3_device = {
234}; 234};
235 235
236static struct sh_timer_config cmt0_platform_data = { 236static struct sh_timer_config cmt0_platform_data = {
237 .name = "CMT0",
238 .channel_offset = 0x02, 237 .channel_offset = 0x02,
239 .timer_bit = 0, 238 .timer_bit = 0,
240 .clk = "peripheral_clk",
241 .clockevent_rating = 125, 239 .clockevent_rating = 125,
242 .clocksource_rating = 0, /* disabled due to code generation issues */ 240 .clocksource_rating = 0, /* disabled due to code generation issues */
243}; 241};
244 242
245static struct resource cmt0_resources[] = { 243static struct resource cmt0_resources[] = {
246 [0] = { 244 [0] = {
247 .name = "CMT0",
248 .start = 0xfffec002, 245 .start = 0xfffec002,
249 .end = 0xfffec007, 246 .end = 0xfffec007,
250 .flags = IORESOURCE_MEM, 247 .flags = IORESOURCE_MEM,
@@ -266,17 +263,14 @@ static struct platform_device cmt0_device = {
266}; 263};
267 264
268static struct sh_timer_config cmt1_platform_data = { 265static struct sh_timer_config cmt1_platform_data = {
269 .name = "CMT1",
270 .channel_offset = 0x08, 266 .channel_offset = 0x08,
271 .timer_bit = 1, 267 .timer_bit = 1,
272 .clk = "peripheral_clk",
273 .clockevent_rating = 125, 268 .clockevent_rating = 125,
274 .clocksource_rating = 0, /* disabled due to code generation issues */ 269 .clocksource_rating = 0, /* disabled due to code generation issues */
275}; 270};
276 271
277static struct resource cmt1_resources[] = { 272static struct resource cmt1_resources[] = {
278 [0] = { 273 [0] = {
279 .name = "CMT1",
280 .start = 0xfffec008, 274 .start = 0xfffec008,
281 .end = 0xfffec00d, 275 .end = 0xfffec00d,
282 .flags = IORESOURCE_MEM, 276 .flags = IORESOURCE_MEM,
@@ -298,16 +292,13 @@ static struct platform_device cmt1_device = {
298}; 292};
299 293
300static struct sh_timer_config mtu2_0_platform_data = { 294static struct sh_timer_config mtu2_0_platform_data = {
301 .name = "MTU2_0",
302 .channel_offset = -0x80, 295 .channel_offset = -0x80,
303 .timer_bit = 0, 296 .timer_bit = 0,
304 .clk = "peripheral_clk",
305 .clockevent_rating = 200, 297 .clockevent_rating = 200,
306}; 298};
307 299
308static struct resource mtu2_0_resources[] = { 300static struct resource mtu2_0_resources[] = {
309 [0] = { 301 [0] = {
310 .name = "MTU2_0",
311 .start = 0xfffe4300, 302 .start = 0xfffe4300,
312 .end = 0xfffe4326, 303 .end = 0xfffe4326,
313 .flags = IORESOURCE_MEM, 304 .flags = IORESOURCE_MEM,
@@ -329,16 +320,13 @@ static struct platform_device mtu2_0_device = {
329}; 320};
330 321
331static struct sh_timer_config mtu2_1_platform_data = { 322static struct sh_timer_config mtu2_1_platform_data = {
332 .name = "MTU2_1",
333 .channel_offset = -0x100, 323 .channel_offset = -0x100,
334 .timer_bit = 1, 324 .timer_bit = 1,
335 .clk = "peripheral_clk",
336 .clockevent_rating = 200, 325 .clockevent_rating = 200,
337}; 326};
338 327
339static struct resource mtu2_1_resources[] = { 328static struct resource mtu2_1_resources[] = {
340 [0] = { 329 [0] = {
341 .name = "MTU2_1",
342 .start = 0xfffe4380, 330 .start = 0xfffe4380,
343 .end = 0xfffe4390, 331 .end = 0xfffe4390,
344 .flags = IORESOURCE_MEM, 332 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index 064873585a8..dc47b04e104 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -194,17 +194,14 @@ static struct platform_device scif3_device = {
194}; 194};
195 195
196static struct sh_timer_config cmt0_platform_data = { 196static struct sh_timer_config cmt0_platform_data = {
197 .name = "CMT0",
198 .channel_offset = 0x02, 197 .channel_offset = 0x02,
199 .timer_bit = 0, 198 .timer_bit = 0,
200 .clk = "peripheral_clk",
201 .clockevent_rating = 125, 199 .clockevent_rating = 125,
202 .clocksource_rating = 0, /* disabled due to code generation issues */ 200 .clocksource_rating = 0, /* disabled due to code generation issues */
203}; 201};
204 202
205static struct resource cmt0_resources[] = { 203static struct resource cmt0_resources[] = {
206 [0] = { 204 [0] = {
207 .name = "CMT0",
208 .start = 0xfffec002, 205 .start = 0xfffec002,
209 .end = 0xfffec007, 206 .end = 0xfffec007,
210 .flags = IORESOURCE_MEM, 207 .flags = IORESOURCE_MEM,
@@ -226,17 +223,14 @@ static struct platform_device cmt0_device = {
226}; 223};
227 224
228static struct sh_timer_config cmt1_platform_data = { 225static struct sh_timer_config cmt1_platform_data = {
229 .name = "CMT1",
230 .channel_offset = 0x08, 226 .channel_offset = 0x08,
231 .timer_bit = 1, 227 .timer_bit = 1,
232 .clk = "peripheral_clk",
233 .clockevent_rating = 125, 228 .clockevent_rating = 125,
234 .clocksource_rating = 0, /* disabled due to code generation issues */ 229 .clocksource_rating = 0, /* disabled due to code generation issues */
235}; 230};
236 231
237static struct resource cmt1_resources[] = { 232static struct resource cmt1_resources[] = {
238 [0] = { 233 [0] = {
239 .name = "CMT1",
240 .start = 0xfffec008, 234 .start = 0xfffec008,
241 .end = 0xfffec00d, 235 .end = 0xfffec00d,
242 .flags = IORESOURCE_MEM, 236 .flags = IORESOURCE_MEM,
@@ -258,16 +252,13 @@ static struct platform_device cmt1_device = {
258}; 252};
259 253
260static struct sh_timer_config mtu2_0_platform_data = { 254static struct sh_timer_config mtu2_0_platform_data = {
261 .name = "MTU2_0",
262 .channel_offset = -0x80, 255 .channel_offset = -0x80,
263 .timer_bit = 0, 256 .timer_bit = 0,
264 .clk = "peripheral_clk",
265 .clockevent_rating = 200, 257 .clockevent_rating = 200,
266}; 258};
267 259
268static struct resource mtu2_0_resources[] = { 260static struct resource mtu2_0_resources[] = {
269 [0] = { 261 [0] = {
270 .name = "MTU2_0",
271 .start = 0xfffe4300, 262 .start = 0xfffe4300,
272 .end = 0xfffe4326, 263 .end = 0xfffe4326,
273 .flags = IORESOURCE_MEM, 264 .flags = IORESOURCE_MEM,
@@ -289,16 +280,13 @@ static struct platform_device mtu2_0_device = {
289}; 280};
290 281
291static struct sh_timer_config mtu2_1_platform_data = { 282static struct sh_timer_config mtu2_1_platform_data = {
292 .name = "MTU2_1",
293 .channel_offset = -0x100, 283 .channel_offset = -0x100,
294 .timer_bit = 1, 284 .timer_bit = 1,
295 .clk = "peripheral_clk",
296 .clockevent_rating = 200, 285 .clockevent_rating = 200,
297}; 286};
298 287
299static struct resource mtu2_1_resources[] = { 288static struct resource mtu2_1_resources[] = {
300 [0] = { 289 [0] = {
301 .name = "MTU2_1",
302 .start = 0xfffe4380, 290 .start = 0xfffe4380,
303 .end = 0xfffe4390, 291 .end = 0xfffe4390,
304 .flags = IORESOURCE_MEM, 292 .flags = IORESOURCE_MEM,
@@ -320,16 +308,13 @@ static struct platform_device mtu2_1_device = {
320}; 308};
321 309
322static struct sh_timer_config mtu2_2_platform_data = { 310static struct sh_timer_config mtu2_2_platform_data = {
323 .name = "MTU2_2",
324 .channel_offset = 0x80, 311 .channel_offset = 0x80,
325 .timer_bit = 2, 312 .timer_bit = 2,
326 .clk = "peripheral_clk",
327 .clockevent_rating = 200, 313 .clockevent_rating = 200,
328}; 314};
329 315
330static struct resource mtu2_2_resources[] = { 316static struct resource mtu2_2_resources[] = {
331 [0] = { 317 [0] = {
332 .name = "MTU2_2",
333 .start = 0xfffe4000, 318 .start = 0xfffe4000,
334 .end = 0xfffe400a, 319 .end = 0xfffe400a,
335 .flags = IORESOURCE_MEM, 320 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index 295ec4c99e9..bf23c322e16 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -16,7 +16,7 @@
16#include <asm/cache.h> 16#include <asm/cache.h>
17#include <asm/io.h> 17#include <asm/io.h>
18 18
19int detect_cpu_and_cache_system(void) 19void __cpuinit cpu_probe(void)
20{ 20{
21 unsigned long addr0, addr1, data0, data1, data2, data3; 21 unsigned long addr0, addr1, data0, data1, data2, data3;
22 22
@@ -108,6 +108,4 @@ int detect_cpu_and_cache_system(void)
108 boot_cpu_data.icache = boot_cpu_data.dcache; 108 boot_cpu_data.icache = boot_cpu_data.dcache;
109 109
110 boot_cpu_data.family = CPU_FAMILY_SH3; 110 boot_cpu_data.family = CPU_FAMILY_SH3;
111
112 return 0;
113} 111}
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 7b892d60e3a..baadd7f54d9 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -124,16 +124,13 @@ static struct platform_device rtc_device = {
124}; 124};
125 125
126static struct sh_timer_config tmu0_platform_data = { 126static struct sh_timer_config tmu0_platform_data = {
127 .name = "TMU0",
128 .channel_offset = 0x02, 127 .channel_offset = 0x02,
129 .timer_bit = 0, 128 .timer_bit = 0,
130 .clk = "peripheral_clk",
131 .clockevent_rating = 200, 129 .clockevent_rating = 200,
132}; 130};
133 131
134static struct resource tmu0_resources[] = { 132static struct resource tmu0_resources[] = {
135 [0] = { 133 [0] = {
136 .name = "TMU0",
137 .start = 0xfffffe94, 134 .start = 0xfffffe94,
138 .end = 0xfffffe9f, 135 .end = 0xfffffe9f,
139 .flags = IORESOURCE_MEM, 136 .flags = IORESOURCE_MEM,
@@ -155,16 +152,13 @@ static struct platform_device tmu0_device = {
155}; 152};
156 153
157static struct sh_timer_config tmu1_platform_data = { 154static struct sh_timer_config tmu1_platform_data = {
158 .name = "TMU1",
159 .channel_offset = 0xe, 155 .channel_offset = 0xe,
160 .timer_bit = 1, 156 .timer_bit = 1,
161 .clk = "peripheral_clk",
162 .clocksource_rating = 200, 157 .clocksource_rating = 200,
163}; 158};
164 159
165static struct resource tmu1_resources[] = { 160static struct resource tmu1_resources[] = {
166 [0] = { 161 [0] = {
167 .name = "TMU1",
168 .start = 0xfffffea0, 162 .start = 0xfffffea0,
169 .end = 0xfffffeab, 163 .end = 0xfffffeab,
170 .flags = IORESOURCE_MEM, 164 .flags = IORESOURCE_MEM,
@@ -186,15 +180,12 @@ static struct platform_device tmu1_device = {
186}; 180};
187 181
188static struct sh_timer_config tmu2_platform_data = { 182static struct sh_timer_config tmu2_platform_data = {
189 .name = "TMU2",
190 .channel_offset = 0x1a, 183 .channel_offset = 0x1a,
191 .timer_bit = 2, 184 .timer_bit = 2,
192 .clk = "peripheral_clk",
193}; 185};
194 186
195static struct resource tmu2_resources[] = { 187static struct resource tmu2_resources[] = {
196 [0] = { 188 [0] = {
197 .name = "TMU2",
198 .start = 0xfffffeac, 189 .start = 0xfffffeac,
199 .end = 0xfffffebb, 190 .end = 0xfffffebb,
200 .flags = IORESOURCE_MEM, 191 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index bc0c4f68c7c..3cf8c8ef7b3 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -157,16 +157,13 @@ static struct platform_device scif2_device = {
157#endif 157#endif
158 158
159static struct sh_timer_config tmu0_platform_data = { 159static struct sh_timer_config tmu0_platform_data = {
160 .name = "TMU0",
161 .channel_offset = 0x02, 160 .channel_offset = 0x02,
162 .timer_bit = 0, 161 .timer_bit = 0,
163 .clk = "peripheral_clk",
164 .clockevent_rating = 200, 162 .clockevent_rating = 200,
165}; 163};
166 164
167static struct resource tmu0_resources[] = { 165static struct resource tmu0_resources[] = {
168 [0] = { 166 [0] = {
169 .name = "TMU0",
170 .start = 0xfffffe94, 167 .start = 0xfffffe94,
171 .end = 0xfffffe9f, 168 .end = 0xfffffe9f,
172 .flags = IORESOURCE_MEM, 169 .flags = IORESOURCE_MEM,
@@ -188,16 +185,13 @@ static struct platform_device tmu0_device = {
188}; 185};
189 186
190static struct sh_timer_config tmu1_platform_data = { 187static struct sh_timer_config tmu1_platform_data = {
191 .name = "TMU1",
192 .channel_offset = 0xe, 188 .channel_offset = 0xe,
193 .timer_bit = 1, 189 .timer_bit = 1,
194 .clk = "peripheral_clk",
195 .clocksource_rating = 200, 190 .clocksource_rating = 200,
196}; 191};
197 192
198static struct resource tmu1_resources[] = { 193static struct resource tmu1_resources[] = {
199 [0] = { 194 [0] = {
200 .name = "TMU1",
201 .start = 0xfffffea0, 195 .start = 0xfffffea0,
202 .end = 0xfffffeab, 196 .end = 0xfffffeab,
203 .flags = IORESOURCE_MEM, 197 .flags = IORESOURCE_MEM,
@@ -219,15 +213,12 @@ static struct platform_device tmu1_device = {
219}; 213};
220 214
221static struct sh_timer_config tmu2_platform_data = { 215static struct sh_timer_config tmu2_platform_data = {
222 .name = "TMU2",
223 .channel_offset = 0x1a, 216 .channel_offset = 0x1a,
224 .timer_bit = 2, 217 .timer_bit = 2,
225 .clk = "peripheral_clk",
226}; 218};
227 219
228static struct resource tmu2_resources[] = { 220static struct resource tmu2_resources[] = {
229 [0] = { 221 [0] = {
230 .name = "TMU2",
231 .start = 0xfffffeac, 222 .start = 0xfffffeac,
232 .end = 0xfffffebb, 223 .end = 0xfffffebb,
233 .flags = IORESOURCE_MEM, 224 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 0845a3ad006..b0c2fb4ab47 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -127,16 +127,13 @@ static struct platform_device scif1_device = {
127}; 127};
128 128
129static struct sh_timer_config tmu0_platform_data = { 129static struct sh_timer_config tmu0_platform_data = {
130 .name = "TMU0",
131 .channel_offset = 0x02, 130 .channel_offset = 0x02,
132 .timer_bit = 0, 131 .timer_bit = 0,
133 .clk = "peripheral_clk",
134 .clockevent_rating = 200, 132 .clockevent_rating = 200,
135}; 133};
136 134
137static struct resource tmu0_resources[] = { 135static struct resource tmu0_resources[] = {
138 [0] = { 136 [0] = {
139 .name = "TMU0",
140 .start = 0xa412fe94, 137 .start = 0xa412fe94,
141 .end = 0xa412fe9f, 138 .end = 0xa412fe9f,
142 .flags = IORESOURCE_MEM, 139 .flags = IORESOURCE_MEM,
@@ -158,16 +155,13 @@ static struct platform_device tmu0_device = {
158}; 155};
159 156
160static struct sh_timer_config tmu1_platform_data = { 157static struct sh_timer_config tmu1_platform_data = {
161 .name = "TMU1",
162 .channel_offset = 0xe, 158 .channel_offset = 0xe,
163 .timer_bit = 1, 159 .timer_bit = 1,
164 .clk = "peripheral_clk",
165 .clocksource_rating = 200, 160 .clocksource_rating = 200,
166}; 161};
167 162
168static struct resource tmu1_resources[] = { 163static struct resource tmu1_resources[] = {
169 [0] = { 164 [0] = {
170 .name = "TMU1",
171 .start = 0xa412fea0, 165 .start = 0xa412fea0,
172 .end = 0xa412feab, 166 .end = 0xa412feab,
173 .flags = IORESOURCE_MEM, 167 .flags = IORESOURCE_MEM,
@@ -189,15 +183,12 @@ static struct platform_device tmu1_device = {
189}; 183};
190 184
191static struct sh_timer_config tmu2_platform_data = { 185static struct sh_timer_config tmu2_platform_data = {
192 .name = "TMU2",
193 .channel_offset = 0x1a, 186 .channel_offset = 0x1a,
194 .timer_bit = 2, 187 .timer_bit = 2,
195 .clk = "peripheral_clk",
196}; 188};
197 189
198static struct resource tmu2_resources[] = { 190static struct resource tmu2_resources[] = {
199 [0] = { 191 [0] = {
200 .name = "TMU2",
201 .start = 0xa412feac, 192 .start = 0xa412feac,
202 .end = 0xa412feb5, 193 .end = 0xa412feb5,
203 .flags = IORESOURCE_MEM, 194 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index a718a623109..24b17135d5d 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -130,17 +130,14 @@ static struct platform_device usbf_device = {
130}; 130};
131 131
132static struct sh_timer_config cmt0_platform_data = { 132static struct sh_timer_config cmt0_platform_data = {
133 .name = "CMT0",
134 .channel_offset = 0x10, 133 .channel_offset = 0x10,
135 .timer_bit = 0, 134 .timer_bit = 0,
136 .clk = "peripheral_clk",
137 .clockevent_rating = 125, 135 .clockevent_rating = 125,
138 .clocksource_rating = 125, 136 .clocksource_rating = 125,
139}; 137};
140 138
141static struct resource cmt0_resources[] = { 139static struct resource cmt0_resources[] = {
142 [0] = { 140 [0] = {
143 .name = "CMT0",
144 .start = 0x044a0010, 141 .start = 0x044a0010,
145 .end = 0x044a001b, 142 .end = 0x044a001b,
146 .flags = IORESOURCE_MEM, 143 .flags = IORESOURCE_MEM,
@@ -162,15 +159,12 @@ static struct platform_device cmt0_device = {
162}; 159};
163 160
164static struct sh_timer_config cmt1_platform_data = { 161static struct sh_timer_config cmt1_platform_data = {
165 .name = "CMT1",
166 .channel_offset = 0x20, 162 .channel_offset = 0x20,
167 .timer_bit = 1, 163 .timer_bit = 1,
168 .clk = "peripheral_clk",
169}; 164};
170 165
171static struct resource cmt1_resources[] = { 166static struct resource cmt1_resources[] = {
172 [0] = { 167 [0] = {
173 .name = "CMT1",
174 .start = 0x044a0020, 168 .start = 0x044a0020,
175 .end = 0x044a002b, 169 .end = 0x044a002b,
176 .flags = IORESOURCE_MEM, 170 .flags = IORESOURCE_MEM,
@@ -192,15 +186,12 @@ static struct platform_device cmt1_device = {
192}; 186};
193 187
194static struct sh_timer_config cmt2_platform_data = { 188static struct sh_timer_config cmt2_platform_data = {
195 .name = "CMT2",
196 .channel_offset = 0x30, 189 .channel_offset = 0x30,
197 .timer_bit = 2, 190 .timer_bit = 2,
198 .clk = "peripheral_clk",
199}; 191};
200 192
201static struct resource cmt2_resources[] = { 193static struct resource cmt2_resources[] = {
202 [0] = { 194 [0] = {
203 .name = "CMT2",
204 .start = 0x044a0030, 195 .start = 0x044a0030,
205 .end = 0x044a003b, 196 .end = 0x044a003b,
206 .flags = IORESOURCE_MEM, 197 .flags = IORESOURCE_MEM,
@@ -222,15 +213,12 @@ static struct platform_device cmt2_device = {
222}; 213};
223 214
224static struct sh_timer_config cmt3_platform_data = { 215static struct sh_timer_config cmt3_platform_data = {
225 .name = "CMT3",
226 .channel_offset = 0x40, 216 .channel_offset = 0x40,
227 .timer_bit = 3, 217 .timer_bit = 3,
228 .clk = "peripheral_clk",
229}; 218};
230 219
231static struct resource cmt3_resources[] = { 220static struct resource cmt3_resources[] = {
232 [0] = { 221 [0] = {
233 .name = "CMT3",
234 .start = 0x044a0040, 222 .start = 0x044a0040,
235 .end = 0x044a004b, 223 .end = 0x044a004b,
236 .flags = IORESOURCE_MEM, 224 .flags = IORESOURCE_MEM,
@@ -252,15 +240,12 @@ static struct platform_device cmt3_device = {
252}; 240};
253 241
254static struct sh_timer_config cmt4_platform_data = { 242static struct sh_timer_config cmt4_platform_data = {
255 .name = "CMT4",
256 .channel_offset = 0x50, 243 .channel_offset = 0x50,
257 .timer_bit = 4, 244 .timer_bit = 4,
258 .clk = "peripheral_clk",
259}; 245};
260 246
261static struct resource cmt4_resources[] = { 247static struct resource cmt4_resources[] = {
262 [0] = { 248 [0] = {
263 .name = "CMT4",
264 .start = 0x044a0050, 249 .start = 0x044a0050,
265 .end = 0x044a005b, 250 .end = 0x044a005b,
266 .flags = IORESOURCE_MEM, 251 .flags = IORESOURCE_MEM,
@@ -282,16 +267,13 @@ static struct platform_device cmt4_device = {
282}; 267};
283 268
284static struct sh_timer_config tmu0_platform_data = { 269static struct sh_timer_config tmu0_platform_data = {
285 .name = "TMU0",
286 .channel_offset = 0x02, 270 .channel_offset = 0x02,
287 .timer_bit = 0, 271 .timer_bit = 0,
288 .clk = "peripheral_clk",
289 .clockevent_rating = 200, 272 .clockevent_rating = 200,
290}; 273};
291 274
292static struct resource tmu0_resources[] = { 275static struct resource tmu0_resources[] = {
293 [0] = { 276 [0] = {
294 .name = "TMU0",
295 .start = 0xa412fe94, 277 .start = 0xa412fe94,
296 .end = 0xa412fe9f, 278 .end = 0xa412fe9f,
297 .flags = IORESOURCE_MEM, 279 .flags = IORESOURCE_MEM,
@@ -313,16 +295,13 @@ static struct platform_device tmu0_device = {
313}; 295};
314 296
315static struct sh_timer_config tmu1_platform_data = { 297static struct sh_timer_config tmu1_platform_data = {
316 .name = "TMU1",
317 .channel_offset = 0xe, 298 .channel_offset = 0xe,
318 .timer_bit = 1, 299 .timer_bit = 1,
319 .clk = "peripheral_clk",
320 .clocksource_rating = 200, 300 .clocksource_rating = 200,
321}; 301};
322 302
323static struct resource tmu1_resources[] = { 303static struct resource tmu1_resources[] = {
324 [0] = { 304 [0] = {
325 .name = "TMU1",
326 .start = 0xa412fea0, 305 .start = 0xa412fea0,
327 .end = 0xa412feab, 306 .end = 0xa412feab,
328 .flags = IORESOURCE_MEM, 307 .flags = IORESOURCE_MEM,
@@ -344,15 +323,12 @@ static struct platform_device tmu1_device = {
344}; 323};
345 324
346static struct sh_timer_config tmu2_platform_data = { 325static struct sh_timer_config tmu2_platform_data = {
347 .name = "TMU2",
348 .channel_offset = 0x1a, 326 .channel_offset = 0x1a,
349 .timer_bit = 2, 327 .timer_bit = 2,
350 .clk = "peripheral_clk",
351}; 328};
352 329
353static struct resource tmu2_resources[] = { 330static struct resource tmu2_resources[] = {
354 [0] = { 331 [0] = {
355 .name = "TMU2",
356 .start = 0xa412feac, 332 .start = 0xa412feac,
357 .end = 0xa412feb5, 333 .end = 0xa412feb5,
358 .flags = IORESOURCE_MEM, 334 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 6b80850294d..4eabc68cd75 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -12,9 +12,10 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/io.h>
16#include <asm/clkdev.h>
15#include <asm/clock.h> 17#include <asm/clock.h>
16#include <asm/freq.h> 18#include <asm/freq.h>
17#include <asm/io.h>
18 19
19#define CPG2_FRQCR3 0xfe0a0018 20#define CPG2_FRQCR3 0xfe0a0018
20 21
@@ -45,7 +46,6 @@ static struct clk_ops sh4202_emi_clk_ops = {
45}; 46};
46 47
47static struct clk sh4202_emi_clk = { 48static struct clk sh4202_emi_clk = {
48 .name = "emi_clk",
49 .flags = CLK_ENABLE_ON_INIT, 49 .flags = CLK_ENABLE_ON_INIT,
50 .ops = &sh4202_emi_clk_ops, 50 .ops = &sh4202_emi_clk_ops,
51}; 51};
@@ -61,7 +61,6 @@ static struct clk_ops sh4202_femi_clk_ops = {
61}; 61};
62 62
63static struct clk sh4202_femi_clk = { 63static struct clk sh4202_femi_clk = {
64 .name = "femi_clk",
65 .flags = CLK_ENABLE_ON_INIT, 64 .flags = CLK_ENABLE_ON_INIT,
66 .ops = &sh4202_femi_clk_ops, 65 .ops = &sh4202_femi_clk_ops,
67}; 66};
@@ -139,7 +138,6 @@ static struct clk_ops sh4202_shoc_clk_ops = {
139}; 138};
140 139
141static struct clk sh4202_shoc_clk = { 140static struct clk sh4202_shoc_clk = {
142 .name = "shoc_clk",
143 .flags = CLK_ENABLE_ON_INIT, 141 .flags = CLK_ENABLE_ON_INIT,
144 .ops = &sh4202_shoc_clk_ops, 142 .ops = &sh4202_shoc_clk_ops,
145}; 143};
@@ -150,6 +148,15 @@ static struct clk *sh4202_onchip_clocks[] = {
150 &sh4202_shoc_clk, 148 &sh4202_shoc_clk,
151}; 149};
152 150
151#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
152
153static struct clk_lookup lookups[] = {
154 /* main clocks */
155 CLKDEV_CON_ID("emi_clk", &sh4202_emi_clk),
156 CLKDEV_CON_ID("femi_clk", &sh4202_femi_clk),
157 CLKDEV_CON_ID("shoc_clk", &sh4202_shoc_clk),
158};
159
153int __init arch_clk_init(void) 160int __init arch_clk_init(void)
154{ 161{
155 struct clk *clk; 162 struct clk *clk;
@@ -167,5 +174,7 @@ int __init arch_clk_init(void)
167 174
168 clk_put(clk); 175 clk_put(clk);
169 176
177 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
178
170 return ret; 179 return ret;
171} 180}
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 822977a06d8..d180f16281e 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -15,7 +15,7 @@
15#include <asm/processor.h> 15#include <asm/processor.h>
16#include <asm/cache.h> 16#include <asm/cache.h>
17 17
18int __init detect_cpu_and_cache_system(void) 18void __cpuinit cpu_probe(void)
19{ 19{
20 unsigned long pvr, prr, cvr; 20 unsigned long pvr, prr, cvr;
21 unsigned long size; 21 unsigned long size;
@@ -251,6 +251,4 @@ int __init detect_cpu_and_cache_system(void)
251 boot_cpu_data.scache.linesz); 251 boot_cpu_data.scache.linesz);
252 } 252 }
253 } 253 }
254
255 return 0;
256} 254}
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index b9b7e10ad68..e916b18e1f7 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -31,16 +31,13 @@ static struct platform_device scif0_device = {
31}; 31};
32 32
33static struct sh_timer_config tmu0_platform_data = { 33static struct sh_timer_config tmu0_platform_data = {
34 .name = "TMU0",
35 .channel_offset = 0x04, 34 .channel_offset = 0x04,
36 .timer_bit = 0, 35 .timer_bit = 0,
37 .clk = "peripheral_clk",
38 .clockevent_rating = 200, 36 .clockevent_rating = 200,
39}; 37};
40 38
41static struct resource tmu0_resources[] = { 39static struct resource tmu0_resources[] = {
42 [0] = { 40 [0] = {
43 .name = "TMU0",
44 .start = 0xffd80008, 41 .start = 0xffd80008,
45 .end = 0xffd80013, 42 .end = 0xffd80013,
46 .flags = IORESOURCE_MEM, 43 .flags = IORESOURCE_MEM,
@@ -62,16 +59,13 @@ static struct platform_device tmu0_device = {
62}; 59};
63 60
64static struct sh_timer_config tmu1_platform_data = { 61static struct sh_timer_config tmu1_platform_data = {
65 .name = "TMU1",
66 .channel_offset = 0x10, 62 .channel_offset = 0x10,
67 .timer_bit = 1, 63 .timer_bit = 1,
68 .clk = "peripheral_clk",
69 .clocksource_rating = 200, 64 .clocksource_rating = 200,
70}; 65};
71 66
72static struct resource tmu1_resources[] = { 67static struct resource tmu1_resources[] = {
73 [0] = { 68 [0] = {
74 .name = "TMU1",
75 .start = 0xffd80014, 69 .start = 0xffd80014,
76 .end = 0xffd8001f, 70 .end = 0xffd8001f,
77 .flags = IORESOURCE_MEM, 71 .flags = IORESOURCE_MEM,
@@ -93,15 +87,12 @@ static struct platform_device tmu1_device = {
93}; 87};
94 88
95static struct sh_timer_config tmu2_platform_data = { 89static struct sh_timer_config tmu2_platform_data = {
96 .name = "TMU2",
97 .channel_offset = 0x1c, 90 .channel_offset = 0x1c,
98 .timer_bit = 2, 91 .timer_bit = 2,
99 .clk = "peripheral_clk",
100}; 92};
101 93
102static struct resource tmu2_resources[] = { 94static struct resource tmu2_resources[] = {
103 [0] = { 95 [0] = {
104 .name = "TMU2",
105 .start = 0xffd80020, 96 .start = 0xffd80020,
106 .end = 0xffd8002f, 97 .end = 0xffd8002f,
107 .flags = IORESOURCE_MEM, 98 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index ffd79e57254..911d196e86b 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -66,16 +66,13 @@ static struct platform_device scif1_device = {
66}; 66};
67 67
68static struct sh_timer_config tmu0_platform_data = { 68static struct sh_timer_config tmu0_platform_data = {
69 .name = "TMU0",
70 .channel_offset = 0x04, 69 .channel_offset = 0x04,
71 .timer_bit = 0, 70 .timer_bit = 0,
72 .clk = "peripheral_clk",
73 .clockevent_rating = 200, 71 .clockevent_rating = 200,
74}; 72};
75 73
76static struct resource tmu0_resources[] = { 74static struct resource tmu0_resources[] = {
77 [0] = { 75 [0] = {
78 .name = "TMU0",
79 .start = 0xffd80008, 76 .start = 0xffd80008,
80 .end = 0xffd80013, 77 .end = 0xffd80013,
81 .flags = IORESOURCE_MEM, 78 .flags = IORESOURCE_MEM,
@@ -97,16 +94,13 @@ static struct platform_device tmu0_device = {
97}; 94};
98 95
99static struct sh_timer_config tmu1_platform_data = { 96static struct sh_timer_config tmu1_platform_data = {
100 .name = "TMU1",
101 .channel_offset = 0x10, 97 .channel_offset = 0x10,
102 .timer_bit = 1, 98 .timer_bit = 1,
103 .clk = "peripheral_clk",
104 .clocksource_rating = 200, 99 .clocksource_rating = 200,
105}; 100};
106 101
107static struct resource tmu1_resources[] = { 102static struct resource tmu1_resources[] = {
108 [0] = { 103 [0] = {
109 .name = "TMU1",
110 .start = 0xffd80014, 104 .start = 0xffd80014,
111 .end = 0xffd8001f, 105 .end = 0xffd8001f,
112 .flags = IORESOURCE_MEM, 106 .flags = IORESOURCE_MEM,
@@ -128,15 +122,12 @@ static struct platform_device tmu1_device = {
128}; 122};
129 123
130static struct sh_timer_config tmu2_platform_data = { 124static struct sh_timer_config tmu2_platform_data = {
131 .name = "TMU2",
132 .channel_offset = 0x1c, 125 .channel_offset = 0x1c,
133 .timer_bit = 2, 126 .timer_bit = 2,
134 .clk = "peripheral_clk",
135}; 127};
136 128
137static struct resource tmu2_resources[] = { 129static struct resource tmu2_resources[] = {
138 [0] = { 130 [0] = {
139 .name = "TMU2",
140 .start = 0xffd80020, 131 .start = 0xffd80020,
141 .end = 0xffd8002f, 132 .end = 0xffd8002f,
142 .flags = IORESOURCE_MEM, 133 .flags = IORESOURCE_MEM,
@@ -163,15 +154,12 @@ static struct platform_device tmu2_device = {
163 defined(CONFIG_CPU_SUBTYPE_SH7751R) 154 defined(CONFIG_CPU_SUBTYPE_SH7751R)
164 155
165static struct sh_timer_config tmu3_platform_data = { 156static struct sh_timer_config tmu3_platform_data = {
166 .name = "TMU3",
167 .channel_offset = 0x04, 157 .channel_offset = 0x04,
168 .timer_bit = 0, 158 .timer_bit = 0,
169 .clk = "peripheral_clk",
170}; 159};
171 160
172static struct resource tmu3_resources[] = { 161static struct resource tmu3_resources[] = {
173 [0] = { 162 [0] = {
174 .name = "TMU3",
175 .start = 0xfe100008, 163 .start = 0xfe100008,
176 .end = 0xfe100013, 164 .end = 0xfe100013,
177 .flags = IORESOURCE_MEM, 165 .flags = IORESOURCE_MEM,
@@ -193,15 +181,12 @@ static struct platform_device tmu3_device = {
193}; 181};
194 182
195static struct sh_timer_config tmu4_platform_data = { 183static struct sh_timer_config tmu4_platform_data = {
196 .name = "TMU4",
197 .channel_offset = 0x10, 184 .channel_offset = 0x10,
198 .timer_bit = 1, 185 .timer_bit = 1,
199 .clk = "peripheral_clk",
200}; 186};
201 187
202static struct resource tmu4_resources[] = { 188static struct resource tmu4_resources[] = {
203 [0] = { 189 [0] = {
204 .name = "TMU4",
205 .start = 0xfe100014, 190 .start = 0xfe100014,
206 .end = 0xfe10001f, 191 .end = 0xfe10001f,
207 .flags = IORESOURCE_MEM, 192 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index a16eb3656f4..48ea8fe85dc 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -187,16 +187,13 @@ static struct platform_device scif3_device = {
187}; 187};
188 188
189static struct sh_timer_config tmu0_platform_data = { 189static struct sh_timer_config tmu0_platform_data = {
190 .name = "TMU0",
191 .channel_offset = 0x04, 190 .channel_offset = 0x04,
192 .timer_bit = 0, 191 .timer_bit = 0,
193 .clk = "peripheral_clk",
194 .clockevent_rating = 200, 192 .clockevent_rating = 200,
195}; 193};
196 194
197static struct resource tmu0_resources[] = { 195static struct resource tmu0_resources[] = {
198 [0] = { 196 [0] = {
199 .name = "TMU0",
200 .start = 0xffd80008, 197 .start = 0xffd80008,
201 .end = 0xffd80013, 198 .end = 0xffd80013,
202 .flags = IORESOURCE_MEM, 199 .flags = IORESOURCE_MEM,
@@ -218,16 +215,13 @@ static struct platform_device tmu0_device = {
218}; 215};
219 216
220static struct sh_timer_config tmu1_platform_data = { 217static struct sh_timer_config tmu1_platform_data = {
221 .name = "TMU1",
222 .channel_offset = 0x10, 218 .channel_offset = 0x10,
223 .timer_bit = 1, 219 .timer_bit = 1,
224 .clk = "peripheral_clk",
225 .clocksource_rating = 200, 220 .clocksource_rating = 200,
226}; 221};
227 222
228static struct resource tmu1_resources[] = { 223static struct resource tmu1_resources[] = {
229 [0] = { 224 [0] = {
230 .name = "TMU1",
231 .start = 0xffd80014, 225 .start = 0xffd80014,
232 .end = 0xffd8001f, 226 .end = 0xffd8001f,
233 .flags = IORESOURCE_MEM, 227 .flags = IORESOURCE_MEM,
@@ -249,15 +243,12 @@ static struct platform_device tmu1_device = {
249}; 243};
250 244
251static struct sh_timer_config tmu2_platform_data = { 245static struct sh_timer_config tmu2_platform_data = {
252 .name = "TMU2",
253 .channel_offset = 0x1c, 246 .channel_offset = 0x1c,
254 .timer_bit = 2, 247 .timer_bit = 2,
255 .clk = "peripheral_clk",
256}; 248};
257 249
258static struct resource tmu2_resources[] = { 250static struct resource tmu2_resources[] = {
259 [0] = { 251 [0] = {
260 .name = "TMU2",
261 .start = 0xffd80020, 252 .start = 0xffd80020,
262 .end = 0xffd8002f, 253 .end = 0xffd8002f,
263 .flags = IORESOURCE_MEM, 254 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 2c16df37eda..71291ae201b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clkdev.h>
24#include <asm/clock.h> 25#include <asm/clock.h>
25 26
26/* SH7343 registers */ 27/* SH7343 registers */
@@ -36,8 +37,6 @@
36 37
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = { 39static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768, 40 .rate = 32768,
42}; 41};
43 42
@@ -46,8 +45,6 @@ static struct clk r_clk = {
46 * from the platform code. 45 * from the platform code.
47 */ 46 */
48struct clk extal_clk = { 47struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333, 48 .rate = 33333333,
52}; 49};
53 50
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
69}; 66};
70 67
71static struct clk dll_clk = { 68static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
75 .parent = &r_clk, 70 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -91,8 +86,6 @@ static struct clk_ops pll_clk_ops = {
91}; 86};
92 87
93static struct clk pll_clk = { 88static struct clk pll_clk = {
94 .name = "pll_clk",
95 .id = -1,
96 .ops = &pll_clk_ops, 89 .ops = &pll_clk_ops,
97 .flags = CLK_ENABLE_ON_INIT, 90 .flags = CLK_ENABLE_ON_INIT,
98}; 91};
@@ -121,72 +114,168 @@ static struct clk_div4_table div4_table = {
121enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 114enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
122 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 115 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
123 116
124#define DIV4(_str, _reg, _bit, _mask, _flags) \ 117#define DIV4(_reg, _bit, _mask, _flags) \
125 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
126 119
127struct clk div4_clks[DIV4_NR] = { 120struct clk div4_clks[DIV4_NR] = {
128 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT), 121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 122 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 126 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
134 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 127 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
135 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 128 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
136}; 129};
137 130
138struct clk div6_clks[] = { 131enum { DIV6_V, DIV6_NR };
139 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 132
133struct clk div6_clks[DIV6_NR] = {
134 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
135};
136
137#define MSTP(_parent, _reg, _bit, _flags) \
138 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
139
140enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
141 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
142 MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
143 MSTP007, MSTP006, MSTP005, MSTP004, MSTP003, MSTP002, MSTP001,
144 MSTP109, MSTP108, MSTP100,
145 MSTP225, MSTP224, MSTP218, MSTP217, MSTP216,
146 MSTP214, MSTP213, MSTP212, MSTP211, MSTP208,
147 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
148 MSTP_NR };
149
150static struct clk mstp_clks[MSTP_NR] = {
151 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
152 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
153 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
154 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
155 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
156 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
157 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
158 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
159 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
160 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
161 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
162 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
163 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
164 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
165 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
166 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
167 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
168 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
169 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
170 [MSTP004] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
171 [MSTP003] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
172 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
173 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
174
175 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
176 [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
177
178 [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
179 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
180 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
181 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
182 [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
183 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
184 [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
185 [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
186 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
187 [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0),
188 [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
189 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
190 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
191 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
192 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
193 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
194 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
140}; 195};
141 196
142#define MSTP(_str, _parent, _reg, _bit, _flags) \ 197#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
143 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 198
144 199static struct clk_lookup lookups[] = {
145static struct clk mstp_clks[] = { 200 /* main clocks */
146 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 201 CLKDEV_CON_ID("rclk", &r_clk),
147 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 202 CLKDEV_CON_ID("extal", &extal_clk),
148 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 203 CLKDEV_CON_ID("dll_clk", &dll_clk),
149 MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 204 CLKDEV_CON_ID("pll_clk", &pll_clk),
150 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 205
151 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 206 /* DIV4 clocks */
152 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 207 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
153 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 208 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
154 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 209 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
155 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 210 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
156 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 211 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
157 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 212 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
158 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 213 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
159 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 214 CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
160 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 215
161 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 216 /* DIV6 clocks */
162 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 217 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
163 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 218
164 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 219 /* MSTP32 clocks */
165 MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0), 220 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
166 MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0), 221 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
167 MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 222 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
168 MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 223 CLKDEV_CON_ID("uram0", &mstp_clks[MSTP028]),
169 224 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
170 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 225 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
171 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0), 226 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
172 227 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
173 MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0), 228 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
174 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 229 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
175 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 230 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
176 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 231 CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
177 MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0), 232 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
178 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0), 233 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
179 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0), 234 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
180 MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0), 235 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
181 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 236 {
182 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0), 237 /* SCIF0 */
183 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), 238 .dev_id = "sh-sci.0",
184 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 239 .con_id = "sci_fck",
185 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 240 .clk = &mstp_clks[MSTP007],
186 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 241 }, {
187 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 242 /* SCIF1 */
188 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 243 .dev_id = "sh-sci.1",
189 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 244 .con_id = "sci_fck",
245 .clk = &mstp_clks[MSTP006],
246 }, {
247 /* SCIF2 */
248 .dev_id = "sh-sci.2",
249 .con_id = "sci_fck",
250 .clk = &mstp_clks[MSTP005],
251 }, {
252 /* SCIF3 */
253 .dev_id = "sh-sci.3",
254 .con_id = "sci_fck",
255 .clk = &mstp_clks[MSTP004],
256 },
257 CLKDEV_CON_ID("sio0", &mstp_clks[MSTP003]),
258 CLKDEV_CON_ID("siof0", &mstp_clks[MSTP002]),
259 CLKDEV_CON_ID("siof1", &mstp_clks[MSTP001]),
260 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
261 CLKDEV_CON_ID("i2c1", &mstp_clks[MSTP108]),
262 CLKDEV_CON_ID("tpu0", &mstp_clks[MSTP225]),
263 CLKDEV_CON_ID("irda0", &mstp_clks[MSTP224]),
264 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
265 CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
266 CLKDEV_CON_ID("sim0", &mstp_clks[MSTP216]),
267 CLKDEV_CON_ID("keysc0", &mstp_clks[MSTP214]),
268 CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP213]),
269 CLKDEV_CON_ID("s3d40", &mstp_clks[MSTP212]),
270 CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
271 CLKDEV_CON_ID("siu0", &mstp_clks[MSTP208]),
272 CLKDEV_CON_ID("jpu0", &mstp_clks[MSTP206]),
273 CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
274 CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
275 CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
276 CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
277 CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
278 CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
190}; 279};
191 280
192int __init arch_clk_init(void) 281int __init arch_clk_init(void)
@@ -202,14 +291,16 @@ int __init arch_clk_init(void)
202 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 291 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
203 ret = clk_register(main_clks[k]); 292 ret = clk_register(main_clks[k]);
204 293
294 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
295
205 if (!ret) 296 if (!ret)
206 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 297 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
207 298
208 if (!ret) 299 if (!ret)
209 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 300 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
210 301
211 if (!ret) 302 if (!ret)
212 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 303 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
213 304
214 return ret; 305 return ret;
215} 306}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index 91588d280cd..7ce5bbcd408 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clkdev.h>
24#include <asm/clock.h> 25#include <asm/clock.h>
25 26
26/* SH7366 registers */ 27/* SH7366 registers */
@@ -36,8 +37,6 @@
36 37
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = { 39static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768, 40 .rate = 32768,
42}; 41};
43 42
@@ -46,8 +45,6 @@ static struct clk r_clk = {
46 * from the platform code. 45 * from the platform code.
47 */ 46 */
48struct clk extal_clk = { 47struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333, 48 .rate = 33333333,
52}; 49};
53 50
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
69}; 66};
70 67
71static struct clk dll_clk = { 68static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
75 .parent = &r_clk, 70 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -94,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
94}; 89};
95 90
96static struct clk pll_clk = { 91static struct clk pll_clk = {
97 .name = "pll_clk",
98 .id = -1,
99 .ops = &pll_clk_ops, 92 .ops = &pll_clk_ops,
100 .flags = CLK_ENABLE_ON_INIT, 93 .flags = CLK_ENABLE_ON_INIT,
101}; 94};
@@ -124,69 +117,154 @@ static struct clk_div4_table div4_table = {
124enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, 117enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
125 DIV4_SIUA, DIV4_SIUB, DIV4_NR }; 118 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
126 119
127#define DIV4(_str, _reg, _bit, _mask, _flags) \ 120#define DIV4(_reg, _bit, _mask, _flags) \
128 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
129 122
130struct clk div4_clks[DIV4_NR] = { 123struct clk div4_clks[DIV4_NR] = {
131 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
132 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
134 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
135 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
136 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 129 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
137 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 130 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
138 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 131 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
139}; 132};
140 133
141struct clk div6_clks[] = { 134enum { DIV6_V, DIV6_NR };
142 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 135
136struct clk div6_clks[DIV6_NR] = {
137 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
143}; 138};
144 139
145#define MSTP(_str, _parent, _reg, _bit, _flags) \ 140#define MSTP(_parent, _reg, _bit, _flags) \
146 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags) 141 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
142
143enum { MSTP031, MSTP030, MSTP029, MSTP028, MSTP026,
144 MSTP023, MSTP022, MSTP021, MSTP020, MSTP019, MSTP018, MSTP017, MSTP016,
145 MSTP015, MSTP014, MSTP013, MSTP012, MSTP011, MSTP010,
146 MSTP007, MSTP006, MSTP005, MSTP002, MSTP001,
147 MSTP109, MSTP100,
148 MSTP227, MSTP226, MSTP224, MSTP223, MSTP222, MSTP218, MSTP217,
149 MSTP211, MSTP207, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
150 MSTP_NR };
147 151
148static struct clk mstp_clks[] = { 152static struct clk mstp_clks[MSTP_NR] = {
149 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */ 153 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
150 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), 154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
151 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), 155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
152 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), 156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
153 MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT), 157 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
154 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 158 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
155 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0), 159 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
156 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0), 160 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
157 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0), 161 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
158 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 162 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
159 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 163 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
160 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 164 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
161 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 165 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
162 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 166 [MSTP014] = MSTP(&r_clk, MSTPCR0, 14, 0),
163 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 167 [MSTP013] = MSTP(&r_clk, MSTPCR0, 13, 0),
164 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 168 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
165 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 169 [MSTP010] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
166 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0), 170 [MSTP007] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 7, 0),
167 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0), 171 [MSTP006] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 6, 0),
168 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0), 172 [MSTP005] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
169 MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0), 173 [MSTP002] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
170 MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0), 174 [MSTP001] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 1, 0),
171 175
172 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0), 176 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
173 177
174 MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0), 178 [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
175 MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0), 179 [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
176 MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0), 180 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
177 MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0), 181 [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
178 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0), 182 [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
179 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0), 183 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
180 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0), 184 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
181 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0), 185 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
182 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0), 186 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
183 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), 187 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0),
184 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0), 188 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0),
185 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0), 189 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0),
186 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0), 190 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
187 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 191 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
188 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 192 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 0, 0),
189 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0), 193};
194
195#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
196
197static struct clk_lookup lookups[] = {
198 /* main clocks */
199 CLKDEV_CON_ID("rclk", &r_clk),
200 CLKDEV_CON_ID("extal", &extal_clk),
201 CLKDEV_CON_ID("dll_clk", &dll_clk),
202 CLKDEV_CON_ID("pll_clk", &pll_clk),
203
204 /* DIV4 clocks */
205 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
206 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
207 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
208 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
209 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
210 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
211 CLKDEV_CON_ID("siua_clk", &div4_clks[DIV4_SIUA]),
212 CLKDEV_CON_ID("siub_clk", &div4_clks[DIV4_SIUB]),
213
214 /* DIV6 clocks */
215 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
216
217 /* MSTP32 clocks */
218 CLKDEV_CON_ID("tlb0", &mstp_clks[MSTP031]),
219 CLKDEV_CON_ID("ic0", &mstp_clks[MSTP030]),
220 CLKDEV_CON_ID("oc0", &mstp_clks[MSTP029]),
221 CLKDEV_CON_ID("rsmem0", &mstp_clks[MSTP028]),
222 CLKDEV_CON_ID("xymem0", &mstp_clks[MSTP026]),
223 CLKDEV_CON_ID("intc3", &mstp_clks[MSTP023]),
224 CLKDEV_CON_ID("intc0", &mstp_clks[MSTP022]),
225 CLKDEV_CON_ID("dmac0", &mstp_clks[MSTP021]),
226 CLKDEV_CON_ID("sh0", &mstp_clks[MSTP020]),
227 CLKDEV_CON_ID("hudi0", &mstp_clks[MSTP019]),
228 CLKDEV_CON_ID("ubc0", &mstp_clks[MSTP017]),
229 CLKDEV_CON_ID("tmu_fck", &mstp_clks[MSTP015]),
230 CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP014]),
231 CLKDEV_CON_ID("rwdt0", &mstp_clks[MSTP013]),
232 CLKDEV_CON_ID("mfi0", &mstp_clks[MSTP011]),
233 CLKDEV_CON_ID("flctl0", &mstp_clks[MSTP010]),
234 {
235 /* SCIF0 */
236 .dev_id = "sh-sci.0",
237 .con_id = "sci_fck",
238 .clk = &mstp_clks[MSTP007],
239 }, {
240 /* SCIF1 */
241 .dev_id = "sh-sci.1",
242 .con_id = "sci_fck",
243 .clk = &mstp_clks[MSTP006],
244 }, {
245 /* SCIF2 */
246 .dev_id = "sh-sci.2",
247 .con_id = "sci_fck",
248 .clk = &mstp_clks[MSTP005],
249 },
250 CLKDEV_CON_ID("msiof0", &mstp_clks[MSTP002]),
251 CLKDEV_CON_ID("sbr0", &mstp_clks[MSTP001]),
252 CLKDEV_CON_ID("i2c0", &mstp_clks[MSTP109]),
253 CLKDEV_CON_ID("icb0", &mstp_clks[MSTP227]),
254 CLKDEV_CON_ID("meram0", &mstp_clks[MSTP226]),
255 CLKDEV_CON_ID("dacy1", &mstp_clks[MSTP224]),
256 CLKDEV_CON_ID("dacy0", &mstp_clks[MSTP223]),
257 CLKDEV_CON_ID("tsif0", &mstp_clks[MSTP222]),
258 CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP218]),
259 CLKDEV_CON_ID("mmcif0", &mstp_clks[MSTP217]),
260 CLKDEV_CON_ID("usbf0", &mstp_clks[MSTP211]),
261 CLKDEV_CON_ID("veu1", &mstp_clks[MSTP207]),
262 CLKDEV_CON_ID("vou0", &mstp_clks[MSTP205]),
263 CLKDEV_CON_ID("beu0", &mstp_clks[MSTP204]),
264 CLKDEV_CON_ID("ceu0", &mstp_clks[MSTP203]),
265 CLKDEV_CON_ID("veu0", &mstp_clks[MSTP202]),
266 CLKDEV_CON_ID("vpu0", &mstp_clks[MSTP201]),
267 CLKDEV_CON_ID("lcdc0", &mstp_clks[MSTP200]),
190}; 268};
191 269
192int __init arch_clk_init(void) 270int __init arch_clk_init(void)
@@ -202,14 +280,16 @@ int __init arch_clk_init(void)
202 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 280 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
203 ret = clk_register(main_clks[k]); 281 ret = clk_register(main_clks[k]);
204 282
283 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
284
205 if (!ret) 285 if (!ret)
206 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 286 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
207 287
208 if (!ret) 288 if (!ret)
209 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 289 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
210 290
211 if (!ret) 291 if (!ret)
212 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 292 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
213 293
214 return ret; 294 return ret;
215} 295}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 15db6d521c5..2030f3d9fac 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <asm/clkdev.h>
24#include <asm/clock.h> 25#include <asm/clock.h>
25#include <asm/hwblk.h> 26#include <asm/hwblk.h>
26#include <cpu/sh7722.h> 27#include <cpu/sh7722.h>
@@ -36,8 +37,6 @@
36 37
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = { 39static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768, 40 .rate = 32768,
42}; 41};
43 42
@@ -46,8 +45,6 @@ static struct clk r_clk = {
46 * from the platform code. 45 * from the platform code.
47 */ 46 */
48struct clk extal_clk = { 47struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333, 48 .rate = 33333333,
52}; 49};
53 50
@@ -69,8 +66,6 @@ static struct clk_ops dll_clk_ops = {
69}; 66};
70 67
71static struct clk dll_clk = { 68static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops, 69 .ops = &dll_clk_ops,
75 .parent = &r_clk, 70 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT, 71 .flags = CLK_ENABLE_ON_INIT,
@@ -94,8 +89,6 @@ static struct clk_ops pll_clk_ops = {
94}; 89};
95 90
96static struct clk pll_clk = { 91static struct clk pll_clk = {
97 .name = "pll_clk",
98 .id = -1,
99 .ops = &pll_clk_ops, 92 .ops = &pll_clk_ops,
100 .flags = CLK_ENABLE_ON_INIT, 93 .flags = CLK_ENABLE_ON_INIT,
101}; 94};
@@ -121,68 +114,142 @@ static struct clk_div4_table div4_table = {
121 .div_mult_table = &div4_div_mult_table, 114 .div_mult_table = &div4_div_mult_table,
122}; 115};
123 116
124#define DIV4(_str, _reg, _bit, _mask, _flags) \ 117#define DIV4(_reg, _bit, _mask, _flags) \
125 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 118 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
126 119
127enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; 120enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
128 121
129struct clk div4_clks[DIV4_NR] = { 122struct clk div4_clks[DIV4_NR] = {
130 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT), 123 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
131 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT), 124 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT), 125 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 126 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
134 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT), 127 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
135 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0), 128 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
136}; 129};
137 130
138enum { DIV4_IRDA, DIV4_ENABLE_NR }; 131enum { DIV4_IRDA, DIV4_ENABLE_NR };
139 132
140struct clk div4_enable_clks[DIV4_ENABLE_NR] = { 133struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
141 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0), 134 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
142}; 135};
143 136
144enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; 137enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
145 138
146struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { 139struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
147 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0), 140 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
148 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0), 141 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
149}; 142};
150 143
151struct clk div6_clks[] = { 144enum { DIV6_V, DIV6_NR };
152 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0), 145
146struct clk div6_clks[DIV6_NR] = {
147 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
148};
149
150static struct clk mstp_clks[HWBLK_NR] = {
151 SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
152 SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
153 SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
154 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
155 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
156 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
157 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
158 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
159 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
160
161 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
162 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
163
164 SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
165 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
166 SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
167 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
168 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
169 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
170 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
171 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
172 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
173 SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
174 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
175 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
153}; 176};
154 177
155#define R_CLK &r_clk 178#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
156#define P_CLK &div4_clks[DIV4_P] 179
157#define B_CLK &div4_clks[DIV4_B] 180static struct clk_lookup lookups[] = {
158#define U_CLK &div4_clks[DIV4_U] 181 /* main clocks */
159 182 CLKDEV_CON_ID("rclk", &r_clk),
160static struct clk mstp_clks[] = { 183 CLKDEV_CON_ID("extal", &extal_clk),
161 SH_HWBLK_CLK("uram0", -1, U_CLK, HWBLK_URAM, CLK_ENABLE_ON_INIT), 184 CLKDEV_CON_ID("dll_clk", &dll_clk),
162 SH_HWBLK_CLK("xymem0", -1, B_CLK, HWBLK_XYMEM, CLK_ENABLE_ON_INIT), 185 CLKDEV_CON_ID("pll_clk", &pll_clk),
163 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU, 0), 186
164 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), 187 /* DIV4 clocks */
165 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 188 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
166 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), 189 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
167 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), 190 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
168 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), 191 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
169 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), 192 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
170 193 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
171 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0), 194 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
172 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), 195 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
173 196 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
174 SH_HWBLK_CLK("sdhi0", -1, P_CLK, HWBLK_SDHI, 0), 197
175 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), 198 /* DIV6 clocks */
176 SH_HWBLK_CLK("usbf0", -1, P_CLK, HWBLK_USBF, 0), 199 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
177 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), 200
178 SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0), 201 /* MSTP clocks */
179 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), 202 CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
180 SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0), 203 CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
181 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0), 204 {
182 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0), 205 /* TMU0 */
183 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU, 0), 206 .dev_id = "sh_tmu.0",
184 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), 207 .con_id = "tmu_fck",
185 SH_HWBLK_CLK("lcdc0", -1, P_CLK, HWBLK_LCDC, 0), 208 .clk = &mstp_clks[HWBLK_TMU],
209 }, {
210 /* TMU1 */
211 .dev_id = "sh_tmu.1",
212 .con_id = "tmu_fck",
213 .clk = &mstp_clks[HWBLK_TMU],
214 }, {
215 /* TMU2 */
216 .dev_id = "sh_tmu.2",
217 .con_id = "tmu_fck",
218 .clk = &mstp_clks[HWBLK_TMU],
219 },
220 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
221 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
222 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
223 {
224 /* SCIF0 */
225 .dev_id = "sh-sci.0",
226 .con_id = "sci_fck",
227 .clk = &mstp_clks[HWBLK_SCIF0],
228 }, {
229 /* SCIF1 */
230 .dev_id = "sh-sci.1",
231 .con_id = "sci_fck",
232 .clk = &mstp_clks[HWBLK_SCIF1],
233 }, {
234 /* SCIF2 */
235 .dev_id = "sh-sci.2",
236 .con_id = "sci_fck",
237 .clk = &mstp_clks[HWBLK_SCIF2],
238 },
239 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
240 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
241 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
242 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
243 CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
244 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
245 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
246 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
247 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
248 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
249 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
250 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
251 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
252 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
186}; 253};
187 254
188int __init arch_clk_init(void) 255int __init arch_clk_init(void)
@@ -198,6 +265,8 @@ int __init arch_clk_init(void)
198 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 265 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
199 ret = clk_register(main_clks[k]); 266 ret = clk_register(main_clks[k]);
200 267
268 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
269
201 if (!ret) 270 if (!ret)
202 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 271 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
203 272
@@ -210,10 +279,10 @@ int __init arch_clk_init(void)
210 DIV4_REPARENT_NR, &div4_table); 279 DIV4_REPARENT_NR, &div4_table);
211 280
212 if (!ret) 281 if (!ret)
213 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 282 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
214 283
215 if (!ret) 284 if (!ret)
216 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 285 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
217 286
218 return ret; 287 return ret;
219} 288}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 50babe01fe4..d3938f0d370 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -21,6 +21,8 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
25#include <asm/clkdev.h>
24#include <asm/clock.h> 26#include <asm/clock.h>
25#include <asm/hwblk.h> 27#include <asm/hwblk.h>
26#include <cpu/sh7723.h> 28#include <cpu/sh7723.h>
@@ -36,8 +38,6 @@
36 38
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 39/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = { 40static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768, 41 .rate = 32768,
42}; 42};
43 43
@@ -46,8 +46,6 @@ static struct clk r_clk = {
46 * from the platform code. 46 * from the platform code.
47 */ 47 */
48struct clk extal_clk = { 48struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333, 49 .rate = 33333333,
52}; 50};
53 51
@@ -69,8 +67,6 @@ static struct clk_ops dll_clk_ops = {
69}; 67};
70 68
71static struct clk dll_clk = { 69static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops, 70 .ops = &dll_clk_ops,
75 .parent = &r_clk, 71 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT, 72 .flags = CLK_ENABLE_ON_INIT,
@@ -94,8 +90,6 @@ static struct clk_ops pll_clk_ops = {
94}; 90};
95 91
96static struct clk pll_clk = { 92static struct clk pll_clk = {
97 .name = "pll_clk",
98 .id = -1,
99 .ops = &pll_clk_ops, 93 .ops = &pll_clk_ops,
100 .flags = CLK_ENABLE_ON_INIT, 94 .flags = CLK_ENABLE_ON_INIT,
101}; 95};
@@ -123,92 +117,215 @@ static struct clk_div4_table div4_table = {
123 117
124enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; 118enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
125 119
126#define DIV4(_str, _reg, _bit, _mask, _flags) \ 120#define DIV4(_reg, _bit, _mask, _flags) \
127 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 121 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
128 122
129struct clk div4_clks[DIV4_NR] = { 123struct clk div4_clks[DIV4_NR] = {
130 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT), 124 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
131 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT), 125 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
132 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT), 126 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
133 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), 127 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
134 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT), 128 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
135 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0), 129 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
136}; 130};
137 131
138enum { DIV4_IRDA, DIV4_ENABLE_NR }; 132enum { DIV4_IRDA, DIV4_ENABLE_NR };
139 133
140struct clk div4_enable_clks[DIV4_ENABLE_NR] = { 134struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
141 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0), 135 [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x0dbf, 0),
142}; 136};
143 137
144enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR }; 138enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
145 139
146struct clk div4_reparent_clks[DIV4_REPARENT_NR] = { 140struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
147 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0), 141 [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x0dbf, 0),
148 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0), 142 [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x0dbf, 0),
149};
150struct clk div6_clks[] = {
151 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
152}; 143};
144enum { DIV6_V, DIV6_NR };
153 145
154#define R_CLK (&r_clk) 146struct clk div6_clks[DIV6_NR] = {
155#define P_CLK (&div4_clks[DIV4_P]) 147 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
156#define B_CLK (&div4_clks[DIV4_B]) 148};
157#define U_CLK (&div4_clks[DIV4_U])
158#define I_CLK (&div4_clks[DIV4_I])
159#define SH_CLK (&div4_clks[DIV4_SH])
160 149
161static struct clk mstp_clks[] = { 150static struct clk mstp_clks[] = {
162 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */ 151 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
163 SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT), 152 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
164 SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT), 153 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
165 SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT), 154 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
166 SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT), 155 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
167 SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT), 156 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
168 SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT), 157 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
169 SH_HWBLK_CLK("intc0", -1, I_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT), 158 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
170 SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0), 159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
171 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), 160 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
172 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), 161 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
173 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), 162 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
174 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0), 163 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
175 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), 164 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
176 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 165 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
177 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), 166 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
178 SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), 167 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
179 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0), 168 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
180 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), 169 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
181 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), 170 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
182 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), 171 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
183 SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), 172 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
184 SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), 173 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
185 SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), 174 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
186 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), 175 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
187 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), 176 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
188 SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0), 177 SH_HWBLK_CLK(HWBLK_MERAM, &div4_clks[DIV4_SH], 0),
189 178
190 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0), 179 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
191 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), 180 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
192 181
193 SH_HWBLK_CLK("atapi0", -1, SH_CLK, HWBLK_ATAPI, 0), 182 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_SH], 0),
194 SH_HWBLK_CLK("adc0", -1, P_CLK, HWBLK_ADC, 0), 183 SH_HWBLK_CLK(HWBLK_ADC, &div4_clks[DIV4_P], 0),
195 SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0), 184 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
196 SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0), 185 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
197 SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0), 186 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
198 SH_HWBLK_CLK("icb0", -1, B_CLK, HWBLK_ICB, CLK_ENABLE_ON_INIT), 187 SH_HWBLK_CLK(HWBLK_ICB, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
199 SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0), 188 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
200 SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0), 189 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
201 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), 190 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
202 SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB, 0), 191 SH_HWBLK_CLK(HWBLK_USB, &div4_clks[DIV4_B], 0),
203 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), 192 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
204 SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0), 193 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
205 SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, 0), 194 SH_HWBLK_CLK(HWBLK_VEU2H1, &div4_clks[DIV4_B], 0),
206 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), 195 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
207 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0), 196 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
208 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0), 197 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
209 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, 0), 198 SH_HWBLK_CLK(HWBLK_VEU2H0, &div4_clks[DIV4_B], 0),
210 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), 199 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
211 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), 200 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
201};
202
203#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
204
205static struct clk_lookup lookups[] = {
206 /* main clocks */
207 CLKDEV_CON_ID("rclk", &r_clk),
208 CLKDEV_CON_ID("extal", &extal_clk),
209 CLKDEV_CON_ID("dll_clk", &dll_clk),
210 CLKDEV_CON_ID("pll_clk", &pll_clk),
211
212 /* DIV4 clocks */
213 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
214 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
215 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
216 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
217 CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
218 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
219 CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
220 CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
221 CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
222
223 /* DIV6 clocks */
224 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
225
226 /* MSTP clocks */
227 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
228 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
229 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
230 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
231 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
232 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
233 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
234 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
235 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
236 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
237 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
238 {
239 /* TMU0 */
240 .dev_id = "sh_tmu.0",
241 .con_id = "tmu_fck",
242 .clk = &mstp_clks[HWBLK_TMU0],
243 }, {
244 /* TMU1 */
245 .dev_id = "sh_tmu.1",
246 .con_id = "tmu_fck",
247 .clk = &mstp_clks[HWBLK_TMU0],
248 }, {
249 /* TMU2 */
250 .dev_id = "sh_tmu.2",
251 .con_id = "tmu_fck",
252 .clk = &mstp_clks[HWBLK_TMU0],
253 },
254 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
255 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
256 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
257 {
258 /* TMU3 */
259 .dev_id = "sh_tmu.3",
260 .con_id = "tmu_fck",
261 .clk = &mstp_clks[HWBLK_TMU1],
262 }, {
263 /* TMU4 */
264 .dev_id = "sh_tmu.4",
265 .con_id = "tmu_fck",
266 .clk = &mstp_clks[HWBLK_TMU1],
267 }, {
268 /* TMU5 */
269 .dev_id = "sh_tmu.5",
270 .con_id = "tmu_fck",
271 .clk = &mstp_clks[HWBLK_TMU1],
272 },
273 CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
274 {
275 /* SCIF0 */
276 .dev_id = "sh-sci.0",
277 .con_id = "sci_fck",
278 .clk = &mstp_clks[HWBLK_SCIF0],
279 }, {
280 /* SCIF1 */
281 .dev_id = "sh-sci.1",
282 .con_id = "sci_fck",
283 .clk = &mstp_clks[HWBLK_SCIF1],
284 }, {
285 /* SCIF2 */
286 .dev_id = "sh-sci.2",
287 .con_id = "sci_fck",
288 .clk = &mstp_clks[HWBLK_SCIF2],
289 }, {
290 /* SCIF3 */
291 .dev_id = "sh-sci.3",
292 .con_id = "sci_fck",
293 .clk = &mstp_clks[HWBLK_SCIF3],
294 }, {
295 /* SCIF4 */
296 .dev_id = "sh-sci.4",
297 .con_id = "sci_fck",
298 .clk = &mstp_clks[HWBLK_SCIF4],
299 }, {
300 /* SCIF5 */
301 .dev_id = "sh-sci.5",
302 .con_id = "sci_fck",
303 .clk = &mstp_clks[HWBLK_SCIF5],
304 },
305 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
306 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
307 CLKDEV_CON_ID("meram0", &mstp_clks[HWBLK_MERAM]),
308 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
309 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
310 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
311 CLKDEV_CON_ID("adc0", &mstp_clks[HWBLK_ADC]),
312 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
313 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
314 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
315 CLKDEV_CON_ID("icb0", &mstp_clks[HWBLK_ICB]),
316 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
317 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
318 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
319 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB]),
320 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
321 CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
322 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU2H1]),
323 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
324 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
325 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
326 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU2H0]),
327 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
328 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
212}; 329};
213 330
214int __init arch_clk_init(void) 331int __init arch_clk_init(void)
@@ -222,7 +339,9 @@ int __init arch_clk_init(void)
222 pll_clk.parent = &extal_clk; 339 pll_clk.parent = &extal_clk;
223 340
224 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 341 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
225 ret = clk_register(main_clks[k]); 342 ret |= clk_register(main_clks[k]);
343
344 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
226 345
227 if (!ret) 346 if (!ret)
228 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 347 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
@@ -236,10 +355,10 @@ int __init arch_clk_init(void)
236 DIV4_REPARENT_NR, &div4_table); 355 DIV4_REPARENT_NR, &div4_table);
237 356
238 if (!ret) 357 if (!ret)
239 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 358 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
240 359
241 if (!ret) 360 if (!ret)
242 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 361 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
243 362
244 return ret; 363 return ret;
245} 364}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 6707061fbf5..2d9700c6b53 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -21,6 +21,8 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clk.h>
25#include <asm/clkdev.h>
24#include <asm/clock.h> 26#include <asm/clock.h>
25#include <asm/hwblk.h> 27#include <asm/hwblk.h>
26#include <cpu/sh7724.h> 28#include <cpu/sh7724.h>
@@ -39,8 +41,6 @@
39 41
40/* Fixed 32 KHz root clock for RTC and Power Management purposes */ 42/* Fixed 32 KHz root clock for RTC and Power Management purposes */
41static struct clk r_clk = { 43static struct clk r_clk = {
42 .name = "rclk",
43 .id = -1,
44 .rate = 32768, 44 .rate = 32768,
45}; 45};
46 46
@@ -49,8 +49,6 @@ static struct clk r_clk = {
49 * from the platform code. 49 * from the platform code.
50 */ 50 */
51struct clk extal_clk = { 51struct clk extal_clk = {
52 .name = "extal",
53 .id = -1,
54 .rate = 33333333, 52 .rate = 33333333,
55}; 53};
56 54
@@ -74,8 +72,6 @@ static struct clk_ops fll_clk_ops = {
74}; 72};
75 73
76static struct clk fll_clk = { 74static struct clk fll_clk = {
77 .name = "fll_clk",
78 .id = -1,
79 .ops = &fll_clk_ops, 75 .ops = &fll_clk_ops,
80 .parent = &r_clk, 76 .parent = &r_clk,
81 .flags = CLK_ENABLE_ON_INIT, 77 .flags = CLK_ENABLE_ON_INIT,
@@ -96,8 +92,6 @@ static struct clk_ops pll_clk_ops = {
96}; 92};
97 93
98static struct clk pll_clk = { 94static struct clk pll_clk = {
99 .name = "pll_clk",
100 .id = -1,
101 .ops = &pll_clk_ops, 95 .ops = &pll_clk_ops,
102 .flags = CLK_ENABLE_ON_INIT, 96 .flags = CLK_ENABLE_ON_INIT,
103}; 97};
@@ -113,8 +107,6 @@ static struct clk_ops div3_clk_ops = {
113}; 107};
114 108
115static struct clk div3_clk = { 109static struct clk div3_clk = {
116 .name = "div3_clk",
117 .id = -1,
118 .ops = &div3_clk_ops, 110 .ops = &div3_clk_ops,
119 .parent = &pll_clk, 111 .parent = &pll_clk,
120}; 112};
@@ -151,86 +143,215 @@ static struct clk_div4_table div4_table = {
151 143
152enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; 144enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
153 145
154#define DIV4(_str, _reg, _bit, _mask, _flags) \ 146#define DIV4(_reg, _bit, _mask, _flags) \
155 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags) 147 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
156 148
157struct clk div4_clks[DIV4_NR] = { 149struct clk div4_clks[DIV4_NR] = {
158 [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), 150 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
159 [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), 151 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
160 [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 152 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
161 [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0), 153 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
162 [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), 154 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
163}; 155};
164 156
165struct clk div6_clks[] = { 157enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
166 SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0), 158
167 SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0), 159struct clk div6_clks[DIV6_NR] = {
168 SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0), 160 [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
169 SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0), 161 [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
170 SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT), 162 [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
163 [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
164 [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
165};
166
167static struct clk mstp_clks[HWBLK_NR] = {
168 SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
169 SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
170 SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
171 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
172 SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
173 SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
174 SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
175 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
176 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
177 SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
178 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
179 SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
180 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
181 SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
182 SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
183 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
184 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
185 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
186 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
187 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
188 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
189 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
190 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
191 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
192 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
193
194 SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
195 SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
196 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
197 SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
198
199 SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
200 SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
201 SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
202 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
203 SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
204 SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
205 SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
206 SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
207 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
208 SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
209 SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
210 SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
211 SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
212 SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
213 SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
214 SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
215 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
216 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
217 SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
218 SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
219 SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
220 SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
221 SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
171}; 222};
172 223
173#define R_CLK (&r_clk) 224#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
174#define P_CLK (&div4_clks[DIV4_P]) 225
175#define B_CLK (&div4_clks[DIV4_B]) 226static struct clk_lookup lookups[] = {
176#define I_CLK (&div4_clks[DIV4_I]) 227 /* main clocks */
177#define SH_CLK (&div4_clks[DIV4_SH]) 228 CLKDEV_CON_ID("rclk", &r_clk),
178 229 CLKDEV_CON_ID("extal", &extal_clk),
179static struct clk mstp_clks[] = { 230 CLKDEV_CON_ID("fll_clk", &fll_clk),
180 SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT), 231 CLKDEV_CON_ID("pll_clk", &pll_clk),
181 SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT), 232 CLKDEV_CON_ID("div3_clk", &div3_clk),
182 SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT), 233
183 SH_HWBLK_CLK("rs0", -1, B_CLK, HWBLK_RSMEM, CLK_ENABLE_ON_INIT), 234 /* DIV4 clocks */
184 SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT), 235 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
185 SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT), 236 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
186 SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT), 237 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
187 SH_HWBLK_CLK("intc0", -1, P_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT), 238 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
188 SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0), 239 CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]),
189 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT), 240
190 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0), 241 /* DIV6 clocks */
191 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0), 242 CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
192 SH_HWBLK_CLK("tmu0", -1, P_CLK, HWBLK_TMU0, 0), 243 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
193 SH_HWBLK_CLK("cmt0", -1, R_CLK, HWBLK_CMT, 0), 244 CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
194 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0), 245 CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
195 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0), 246 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
196 SH_HWBLK_CLK("tmu1", -1, P_CLK, HWBLK_TMU1, 0), 247
197 SH_HWBLK_CLK("scif0", -1, P_CLK, HWBLK_SCIF0, 0), 248 /* MSTP clocks */
198 SH_HWBLK_CLK("scif1", -1, P_CLK, HWBLK_SCIF1, 0), 249 CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
199 SH_HWBLK_CLK("scif2", -1, P_CLK, HWBLK_SCIF2, 0), 250 CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
200 SH_HWBLK_CLK("scif3", -1, B_CLK, HWBLK_SCIF3, 0), 251 CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
201 SH_HWBLK_CLK("scif4", -1, B_CLK, HWBLK_SCIF4, 0), 252 CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
202 SH_HWBLK_CLK("scif5", -1, B_CLK, HWBLK_SCIF5, 0), 253 CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
203 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0), 254 CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
204 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0), 255 CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
205 256 CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
206 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0), 257 CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
207 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0), 258 CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
208 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC0, 0), 259 CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
209 SH_HWBLK_CLK("i2c1", -1, P_CLK, HWBLK_IIC1, 0), 260 CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
210 261 {
211 SH_HWBLK_CLK("mmc0", -1, B_CLK, HWBLK_MMC, 0), 262 /* TMU0 */
212 SH_HWBLK_CLK("eth0", -1, B_CLK, HWBLK_ETHER, 0), 263 .dev_id = "sh_tmu.0",
213 SH_HWBLK_CLK("atapi0", -1, B_CLK, HWBLK_ATAPI, 0), 264 .con_id = "tmu_fck",
214 SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0), 265 .clk = &mstp_clks[HWBLK_TMU0],
215 SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0), 266 }, {
216 SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0), 267 /* TMU1 */
217 SH_HWBLK_CLK("usb1", -1, B_CLK, HWBLK_USB1, 0), 268 .dev_id = "sh_tmu.1",
218 SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB0, 0), 269 .con_id = "tmu_fck",
219 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0), 270 .clk = &mstp_clks[HWBLK_TMU0],
220 SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0), 271 }, {
221 SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0), 272 /* TMU2 */
222 SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU1, 0), 273 .dev_id = "sh_tmu.2",
223 SH_HWBLK_CLK("ceu1", -1, B_CLK, HWBLK_CEU1, 0), 274 .con_id = "tmu_fck",
224 SH_HWBLK_CLK("beu1", -1, B_CLK, HWBLK_BEU1, 0), 275 .clk = &mstp_clks[HWBLK_TMU0],
225 SH_HWBLK_CLK("2ddmac0", -1, SH_CLK, HWBLK_2DDMAC, 0), 276 }, {
226 SH_HWBLK_CLK("spu0", -1, B_CLK, HWBLK_SPU, 0), 277 /* TMU3 */
227 SH_HWBLK_CLK("jpu0", -1, B_CLK, HWBLK_JPU, 0), 278 .dev_id = "sh_tmu.3",
228 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0), 279 .con_id = "tmu_fck",
229 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU0, 0), 280 .clk = &mstp_clks[HWBLK_TMU1],
230 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU0, 0), 281 },
231 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU0, 0), 282 CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
232 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0), 283 CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
233 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0), 284 CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
285 {
286 /* TMU4 */
287 .dev_id = "sh_tmu.4",
288 .con_id = "tmu_fck",
289 .clk = &mstp_clks[HWBLK_TMU1],
290 }, {
291 /* TMU5 */
292 .dev_id = "sh_tmu.5",
293 .con_id = "tmu_fck",
294 .clk = &mstp_clks[HWBLK_TMU1],
295 }, {
296 /* SCIF0 */
297 .dev_id = "sh-sci.0",
298 .con_id = "sci_fck",
299 .clk = &mstp_clks[HWBLK_SCIF0],
300 }, {
301 /* SCIF1 */
302 .dev_id = "sh-sci.1",
303 .con_id = "sci_fck",
304 .clk = &mstp_clks[HWBLK_SCIF1],
305 }, {
306 /* SCIF2 */
307 .dev_id = "sh-sci.2",
308 .con_id = "sci_fck",
309 .clk = &mstp_clks[HWBLK_SCIF2],
310 }, {
311 /* SCIF3 */
312 .dev_id = "sh-sci.3",
313 .con_id = "sci_fck",
314 .clk = &mstp_clks[HWBLK_SCIF3],
315 }, {
316 /* SCIF4 */
317 .dev_id = "sh-sci.4",
318 .con_id = "sci_fck",
319 .clk = &mstp_clks[HWBLK_SCIF4],
320 }, {
321 /* SCIF5 */
322 .dev_id = "sh-sci.5",
323 .con_id = "sci_fck",
324 .clk = &mstp_clks[HWBLK_SCIF5],
325 },
326 CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
327 CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
328 CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
329 CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
330 CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]),
331 CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]),
332 CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
333 CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
334 CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
335 CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
336 CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
337 CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
338 CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
339 CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
340 CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
341 CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
342 CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
343 CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
344 CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]),
345 CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
346 CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
347 CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
348 CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
349 CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
350 CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
351 CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]),
352 CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
353 CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
354 CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
234}; 355};
235 356
236int __init arch_clk_init(void) 357int __init arch_clk_init(void)
@@ -246,14 +367,16 @@ int __init arch_clk_init(void)
246 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 367 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
247 ret = clk_register(main_clks[k]); 368 ret = clk_register(main_clks[k]);
248 369
370 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
371
249 if (!ret) 372 if (!ret)
250 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); 373 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
251 374
252 if (!ret) 375 if (!ret)
253 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks)); 376 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
254 377
255 if (!ret) 378 if (!ret)
256 ret = sh_hwblk_clk_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 379 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
257 380
258 return ret; 381 return ret;
259} 382}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index 86aae60677d..0a752bd324a 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <asm/clkdev.h>
15#include <asm/clock.h> 16#include <asm/clock.h>
16#include <asm/freq.h> 17#include <asm/freq.h>
17 18
@@ -87,7 +88,6 @@ static struct clk_ops sh7757_shyway_clk_ops = {
87}; 88};
88 89
89static struct clk sh7757_shyway_clk = { 90static struct clk sh7757_shyway_clk = {
90 .name = "shyway_clk",
91 .flags = CLK_ENABLE_ON_INIT, 91 .flags = CLK_ENABLE_ON_INIT,
92 .ops = &sh7757_shyway_clk_ops, 92 .ops = &sh7757_shyway_clk_ops,
93}; 93};
@@ -100,6 +100,13 @@ static struct clk *sh7757_onchip_clocks[] = {
100 &sh7757_shyway_clk, 100 &sh7757_shyway_clk,
101}; 101};
102 102
103#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
104
105static struct clk_lookup lookups[] = {
106 /* main clocks */
107 CLKDEV_CON_ID("shyway_clk", &sh7757_shyway_clk),
108};
109
103static int __init sh7757_clk_init(void) 110static int __init sh7757_clk_init(void)
104{ 111{
105 struct clk *clk = clk_get(NULL, "master_clk"); 112 struct clk *clk = clk_get(NULL, "master_clk");
@@ -123,6 +130,8 @@ static int __init sh7757_clk_init(void)
123 130
124 clk_put(clk); 131 clk_put(clk);
125 132
133 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
134
126 return 0; 135 return 0;
127} 136}
128 137
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 9f401163e71..1f1df48008c 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -12,6 +12,8 @@
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <asm/clkdev.h>
15#include <asm/clock.h> 17#include <asm/clock.h>
16#include <asm/freq.h> 18#include <asm/freq.h>
17#include <asm/io.h> 19#include <asm/io.h>
@@ -77,7 +79,6 @@ static struct clk_ops sh7763_shyway_clk_ops = {
77}; 79};
78 80
79static struct clk sh7763_shyway_clk = { 81static struct clk sh7763_shyway_clk = {
80 .name = "shyway_clk",
81 .flags = CLK_ENABLE_ON_INIT, 82 .flags = CLK_ENABLE_ON_INIT,
82 .ops = &sh7763_shyway_clk_ops, 83 .ops = &sh7763_shyway_clk_ops,
83}; 84};
@@ -90,6 +91,13 @@ static struct clk *sh7763_onchip_clocks[] = {
90 &sh7763_shyway_clk, 91 &sh7763_shyway_clk,
91}; 92};
92 93
94#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
95
96static struct clk_lookup lookups[] = {
97 /* main clocks */
98 CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
99};
100
93int __init arch_clk_init(void) 101int __init arch_clk_init(void)
94{ 102{
95 struct clk *clk; 103 struct clk *clk;
@@ -107,5 +115,7 @@ int __init arch_clk_init(void)
107 115
108 clk_put(clk); 116 clk_put(clk);
109 117
118 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
119
110 return ret; 120 return ret;
111} 121}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 150963a6001..62d70635006 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -11,6 +11,8 @@
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <asm/clkdev.h>
14#include <asm/clock.h> 16#include <asm/clock.h>
15#include <asm/freq.h> 17#include <asm/freq.h>
16#include <asm/io.h> 18#include <asm/io.h>
@@ -83,7 +85,6 @@ static struct clk_ops sh7780_shyway_clk_ops = {
83}; 85};
84 86
85static struct clk sh7780_shyway_clk = { 87static struct clk sh7780_shyway_clk = {
86 .name = "shyway_clk",
87 .flags = CLK_ENABLE_ON_INIT, 88 .flags = CLK_ENABLE_ON_INIT,
88 .ops = &sh7780_shyway_clk_ops, 89 .ops = &sh7780_shyway_clk_ops,
89}; 90};
@@ -96,6 +97,13 @@ static struct clk *sh7780_onchip_clocks[] = {
96 &sh7780_shyway_clk, 97 &sh7780_shyway_clk,
97}; 98};
98 99
100#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
101
102static struct clk_lookup lookups[] = {
103 /* main clocks */
104 CLKDEV_CON_ID("shyway_clk", &sh7780_shyway_clk),
105};
106
99int __init arch_clk_init(void) 107int __init arch_clk_init(void)
100{ 108{
101 struct clk *clk; 109 struct clk *clk;
@@ -113,5 +121,7 @@ int __init arch_clk_init(void)
113 121
114 clk_put(clk); 122 clk_put(clk);
115 123
124 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
125
116 return ret; 126 return ret;
117} 127}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index d997f0a25b1..c3e458aaa2b 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SH7785 support for the clock framework 4 * SH7785 support for the clock framework
5 * 5 *
6 * Copyright (C) 2007 - 2009 Paul Mundt 6 * Copyright (C) 2007 - 2010 Paul Mundt
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -14,6 +14,7 @@
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/cpufreq.h> 16#include <linux/cpufreq.h>
17#include <asm/clkdev.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18#include <asm/freq.h> 19#include <asm/freq.h>
19#include <cpu/sh7785.h> 20#include <cpu/sh7785.h>
@@ -23,8 +24,6 @@
23 * from the platform code. 24 * from the platform code.
24 */ 25 */
25static struct clk extal_clk = { 26static struct clk extal_clk = {
26 .name = "extal",
27 .id = -1,
28 .rate = 33333333, 27 .rate = 33333333,
29}; 28};
30 29
@@ -42,8 +41,6 @@ static struct clk_ops pll_clk_ops = {
42}; 41};
43 42
44static struct clk pll_clk = { 43static struct clk pll_clk = {
45 .name = "pll_clk",
46 .id = -1,
47 .ops = &pll_clk_ops, 44 .ops = &pll_clk_ops,
48 .parent = &extal_clk, 45 .parent = &extal_clk,
49 .flags = CLK_ENABLE_ON_INIT, 46 .flags = CLK_ENABLE_ON_INIT,
@@ -69,48 +66,149 @@ static struct clk_div4_table div4_table = {
69enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, 66enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
70 DIV4_DU, DIV4_P, DIV4_NR }; 67 DIV4_DU, DIV4_P, DIV4_NR };
71 68
72#define DIV4(_str, _bit, _mask, _flags) \ 69#define DIV4(_bit, _mask, _flags) \
73 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) 70 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
74 71
75struct clk div4_clks[DIV4_NR] = { 72struct clk div4_clks[DIV4_NR] = {
76 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0), 73 [DIV4_P] = DIV4(0, 0x0f80, 0),
77 [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0), 74 [DIV4_DU] = DIV4(4, 0x0ff0, 0),
78 [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0), 75 [DIV4_GA] = DIV4(8, 0x0030, 0),
79 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT), 76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
80 [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT), 77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
81 [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT), 78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
82 [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT), 79 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
83 [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT), 80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
84}; 81};
85 82
86#define MSTPCR0 0xffc80030 83#define MSTPCR0 0xffc80030
87#define MSTPCR1 0xffc80034 84#define MSTPCR1 0xffc80034
88 85
89static struct clk mstp_clks[] = { 86enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
87 MSTP021, MSTP020, MSTP017, MSTP016,
88 MSTP013, MSTP012, MSTP009, MSTP008, MSTP003, MSTP002,
89 MSTP119, MSTP117, MSTP105, MSTP104, MSTP100,
90 MSTP_NR };
91
92static struct clk mstp_clks[MSTP_NR] = {
90 /* MSTPCR0 */ 93 /* MSTPCR0 */
91 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 94 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
92 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 95 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
93 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 96 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
94 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 97 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
95 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 98 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
96 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 99 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
97 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 100 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
98 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 101 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
99 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 102 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
100 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 103 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
101 SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0), 104 [MSTP013] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 13, 0),
102 SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0), 105 [MSTP012] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 12, 0),
103 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 106 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
104 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 107 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
105 SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0), 108 [MSTP003] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 3, 0),
106 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 109 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
107 110
108 /* MSTPCR1 */ 111 /* MSTPCR1 */
109 SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0), 112 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
110 SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0), 113 [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
111 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 114 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
112 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 115 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
113 SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0), 116 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
117};
118
119#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
120
121static struct clk_lookup lookups[] = {
122 /* main clocks */
123 CLKDEV_CON_ID("extal", &extal_clk),
124 CLKDEV_CON_ID("pll_clk", &pll_clk),
125
126 /* DIV4 clocks */
127 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
128 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
129 CLKDEV_CON_ID("ga_clk", &div4_clks[DIV4_GA]),
130 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
131 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
132 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
133 CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
134 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
135
136 /* MSTP32 clocks */
137 {
138 /* SCIF5 */
139 .dev_id = "sh-sci.5",
140 .con_id = "sci_fck",
141 .clk = &mstp_clks[MSTP029],
142 }, {
143 /* SCIF4 */
144 .dev_id = "sh-sci.4",
145 .con_id = "sci_fck",
146 .clk = &mstp_clks[MSTP028],
147 }, {
148 /* SCIF3 */
149 .dev_id = "sh-sci.3",
150 .con_id = "sci_fck",
151 .clk = &mstp_clks[MSTP027],
152 }, {
153 /* SCIF2 */
154 .dev_id = "sh-sci.2",
155 .con_id = "sci_fck",
156 .clk = &mstp_clks[MSTP026],
157 }, {
158 /* SCIF1 */
159 .dev_id = "sh-sci.1",
160 .con_id = "sci_fck",
161 .clk = &mstp_clks[MSTP025],
162 }, {
163 /* SCIF0 */
164 .dev_id = "sh-sci.0",
165 .con_id = "sci_fck",
166 .clk = &mstp_clks[MSTP024],
167 },
168 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
169 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
170 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
171 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
172 CLKDEV_CON_ID("mmcif_fck", &mstp_clks[MSTP013]),
173 CLKDEV_CON_ID("flctl_fck", &mstp_clks[MSTP012]),
174 {
175 /* TMU0 */
176 .dev_id = "sh_tmu.0",
177 .con_id = "tmu_fck",
178 .clk = &mstp_clks[MSTP008],
179 }, {
180 /* TMU1 */
181 .dev_id = "sh_tmu.1",
182 .con_id = "tmu_fck",
183 .clk = &mstp_clks[MSTP008],
184 }, {
185 /* TMU2 */
186 .dev_id = "sh_tmu.2",
187 .con_id = "tmu_fck",
188 .clk = &mstp_clks[MSTP008],
189 }, {
190 /* TMU3 */
191 .dev_id = "sh_tmu.3",
192 .con_id = "tmu_fck",
193 .clk = &mstp_clks[MSTP009],
194 }, {
195 /* TMU4 */
196 .dev_id = "sh_tmu.4",
197 .con_id = "tmu_fck",
198 .clk = &mstp_clks[MSTP009],
199 }, {
200 /* TMU5 */
201 .dev_id = "sh_tmu.5",
202 .con_id = "tmu_fck",
203 .clk = &mstp_clks[MSTP009],
204 },
205 CLKDEV_CON_ID("siof_fck", &mstp_clks[MSTP003]),
206 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
207 CLKDEV_CON_ID("hudi_fck", &mstp_clks[MSTP119]),
208 CLKDEV_CON_ID("ubc_fck", &mstp_clks[MSTP117]),
209 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
210 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
211 CLKDEV_CON_ID("gdta_fck", &mstp_clks[MSTP100]),
114}; 212};
115 213
116int __init arch_clk_init(void) 214int __init arch_clk_init(void)
@@ -119,12 +217,14 @@ int __init arch_clk_init(void)
119 217
120 for (i = 0; i < ARRAY_SIZE(clks); i++) 218 for (i = 0; i < ARRAY_SIZE(clks); i++)
121 ret |= clk_register(clks[i]); 219 ret |= clk_register(clks[i]);
220 for (i = 0; i < ARRAY_SIZE(lookups); i++)
221 clkdev_add(&lookups[i]);
122 222
123 if (!ret) 223 if (!ret)
124 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 224 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
125 &div4_table); 225 &div4_table);
126 if (!ret) 226 if (!ret)
127 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 227 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
128 228
129 return ret; 229 return ret;
130} 230}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index af69fd46870..105a6d41b56 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -13,6 +13,8 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/clk.h>
17#include <asm/clkdev.h>
16#include <asm/clock.h> 18#include <asm/clock.h>
17#include <asm/freq.h> 19#include <asm/freq.h>
18 20
@@ -21,8 +23,6 @@
21 * from the platform code. 23 * from the platform code.
22 */ 24 */
23static struct clk extal_clk = { 25static struct clk extal_clk = {
24 .name = "extal",
25 .id = -1,
26 .rate = 33333333, 26 .rate = 33333333,
27}; 27};
28 28
@@ -44,8 +44,6 @@ static struct clk_ops pll_clk_ops = {
44}; 44};
45 45
46static struct clk pll_clk = { 46static struct clk pll_clk = {
47 .name = "pll_clk",
48 .id = -1,
49 .ops = &pll_clk_ops, 47 .ops = &pll_clk_ops,
50 .parent = &extal_clk, 48 .parent = &extal_clk,
51 .flags = CLK_ENABLE_ON_INIT, 49 .flags = CLK_ENABLE_ON_INIT,
@@ -70,54 +68,191 @@ static struct clk_div4_table div4_table = {
70 68
71enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; 69enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
72 70
73#define DIV4(_str, _bit, _mask, _flags) \ 71#define DIV4(_bit, _mask, _flags) \
74 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) 72 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
75 73
76struct clk div4_clks[DIV4_NR] = { 74struct clk div4_clks[DIV4_NR] = {
77 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0), 75 [DIV4_P] = DIV4(0, 0x0b40, 0),
78 [DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0), 76 [DIV4_DU] = DIV4(4, 0x0010, 0),
79 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT), 77 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
80 [DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT), 78 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
81 [DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT), 79 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
82 [DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT), 80 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
83}; 81};
84 82
85#define MSTPCR0 0xffc40030 83#define MSTPCR0 0xffc40030
86#define MSTPCR1 0xffc40034 84#define MSTPCR1 0xffc40034
87 85
88static struct clk mstp_clks[] = { 86enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
87 MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
88 MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
89 MSTP005, MSTP004, MSTP002,
90 MSTP112, MSTP110, MSTP109, MSTP108,
91 MSTP105, MSTP104, MSTP103, MSTP102,
92 MSTP_NR };
93
94static struct clk mstp_clks[MSTP_NR] = {
89 /* MSTPCR0 */ 95 /* MSTPCR0 */
90 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), 96 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
91 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), 97 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
92 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), 98 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
93 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), 99 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
94 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), 100 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
95 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), 101 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
96 SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0), 102 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
97 SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0), 103 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
98 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), 104 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
99 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), 105 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
100 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), 106 [MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
101 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), 107 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
102 SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0), 108 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
103 SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0), 109 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
104 SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0), 110 [MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
105 SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0), 111 [MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
106 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), 112 [MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
107 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), 113 [MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
108 SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0), 114 [MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
109 SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0), 115 [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
110 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), 116 [MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
111 117
112 /* MSTPCR1 */ 118 /* MSTPCR1 */
113 SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0), 119 [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
114 SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0), 120 [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
115 SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0), 121 [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
116 SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0), 122 [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
117 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), 123 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
118 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), 124 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
119 SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0), 125 [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
120 SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0), 126 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
127};
128
129#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
130
131static struct clk_lookup lookups[] = {
132 /* main clocks */
133 CLKDEV_CON_ID("extal", &extal_clk),
134 CLKDEV_CON_ID("pll_clk", &pll_clk),
135
136 /* DIV4 clocks */
137 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
138 CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
139 CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
140 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
141 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
142 CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
143
144 /* MSTP32 clocks */
145 {
146 /* SCIF5 */
147 .dev_id = "sh-sci.5",
148 .con_id = "sci_fck",
149 .clk = &mstp_clks[MSTP029],
150 }, {
151 /* SCIF4 */
152 .dev_id = "sh-sci.4",
153 .con_id = "sci_fck",
154 .clk = &mstp_clks[MSTP028],
155 }, {
156 /* SCIF3 */
157 .dev_id = "sh-sci.3",
158 .con_id = "sci_fck",
159 .clk = &mstp_clks[MSTP027],
160 }, {
161 /* SCIF2 */
162 .dev_id = "sh-sci.2",
163 .con_id = "sci_fck",
164 .clk = &mstp_clks[MSTP026],
165 }, {
166 /* SCIF1 */
167 .dev_id = "sh-sci.1",
168 .con_id = "sci_fck",
169 .clk = &mstp_clks[MSTP025],
170 }, {
171 /* SCIF0 */
172 .dev_id = "sh-sci.0",
173 .con_id = "sci_fck",
174 .clk = &mstp_clks[MSTP024],
175 },
176 CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
177 CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
178 CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
179 CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
180 CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
181 CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
182 CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
183 CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
184 {
185 /* TMU0 */
186 .dev_id = "sh_tmu.0",
187 .con_id = "tmu_fck",
188 .clk = &mstp_clks[MSTP008],
189 }, {
190 /* TMU1 */
191 .dev_id = "sh_tmu.1",
192 .con_id = "tmu_fck",
193 .clk = &mstp_clks[MSTP008],
194 }, {
195 /* TMU2 */
196 .dev_id = "sh_tmu.2",
197 .con_id = "tmu_fck",
198 .clk = &mstp_clks[MSTP008],
199 }, {
200 /* TMU3 */
201 .dev_id = "sh_tmu.3",
202 .con_id = "tmu_fck",
203 .clk = &mstp_clks[MSTP009],
204 }, {
205 /* TMU4 */
206 .dev_id = "sh_tmu.4",
207 .con_id = "tmu_fck",
208 .clk = &mstp_clks[MSTP009],
209 }, {
210 /* TMU5 */
211 .dev_id = "sh_tmu.5",
212 .con_id = "tmu_fck",
213 .clk = &mstp_clks[MSTP009],
214 }, {
215 /* TMU6 */
216 .dev_id = "sh_tmu.6",
217 .con_id = "tmu_fck",
218 .clk = &mstp_clks[MSTP010],
219 }, {
220 /* TMU7 */
221 .dev_id = "sh_tmu.7",
222 .con_id = "tmu_fck",
223 .clk = &mstp_clks[MSTP010],
224 }, {
225 /* TMU8 */
226 .dev_id = "sh_tmu.8",
227 .con_id = "tmu_fck",
228 .clk = &mstp_clks[MSTP010],
229 }, {
230 /* TMU9 */
231 .dev_id = "sh_tmu.9",
232 .con_id = "tmu_fck",
233 .clk = &mstp_clks[MSTP011],
234 }, {
235 /* TMU10 */
236 .dev_id = "sh_tmu.10",
237 .con_id = "tmu_fck",
238 .clk = &mstp_clks[MSTP011],
239 }, {
240 /* TMU11 */
241 .dev_id = "sh_tmu.11",
242 .con_id = "tmu_fck",
243 .clk = &mstp_clks[MSTP011],
244 },
245 CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
246 CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
247 CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
248 CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
249 CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
250 CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
251 CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
252 CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
253 CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
254 CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
255 CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
121}; 256};
122 257
123int __init arch_clk_init(void) 258int __init arch_clk_init(void)
@@ -126,12 +261,14 @@ int __init arch_clk_init(void)
126 261
127 for (i = 0; i < ARRAY_SIZE(clks); i++) 262 for (i = 0; i < ARRAY_SIZE(clks); i++)
128 ret |= clk_register(clks[i]); 263 ret |= clk_register(clks[i]);
264 for (i = 0; i < ARRAY_SIZE(lookups); i++)
265 clkdev_add(&lookups[i]);
129 266
130 if (!ret) 267 if (!ret)
131 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), 268 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
132 &div4_table); 269 &div4_table);
133 if (!ret) 270 if (!ret)
134 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); 271 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
135 272
136 return ret; 273 return ret;
137} 274}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index e75c57bdfa5..236a6282d77 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -13,9 +13,10 @@
13 */ 13 */
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/io.h>
17#include <asm/clkdev.h>
16#include <asm/clock.h> 18#include <asm/clock.h>
17#include <asm/freq.h> 19#include <asm/freq.h>
18#include <asm/io.h>
19 20
20static int ifc_divisors[] = { 1, 2, 4 ,6 }; 21static int ifc_divisors[] = { 1, 2, 4 ,6 };
21static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 }; 22static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18, 24, 32, 36, 48 };
@@ -94,7 +95,6 @@ static struct clk_ops shx3_shyway_clk_ops = {
94}; 95};
95 96
96static struct clk shx3_shyway_clk = { 97static struct clk shx3_shyway_clk = {
97 .name = "shyway_clk",
98 .flags = CLK_ENABLE_ON_INIT, 98 .flags = CLK_ENABLE_ON_INIT,
99 .ops = &shx3_shyway_clk_ops, 99 .ops = &shx3_shyway_clk_ops,
100}; 100};
@@ -107,6 +107,13 @@ static struct clk *shx3_onchip_clocks[] = {
107 &shx3_shyway_clk, 107 &shx3_shyway_clk,
108}; 108};
109 109
110#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
111
112static struct clk_lookup lookups[] = {
113 /* main clocks */
114 CLKDEV_CON_ID("shyway_clk", &shx3_shyway_clk),
115};
116
110int __init arch_clk_init(void) 117int __init arch_clk_init(void)
111{ 118{
112 struct clk *clk; 119 struct clk *clk;
@@ -124,5 +131,7 @@ int __init arch_clk_init(void)
124 131
125 clk_put(clk); 132 clk_put(clk);
126 133
134 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
135
127 return ret; 136 return ret;
128} 137}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 45eb1bfd42c..3681cafdb4a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -21,7 +21,6 @@ static struct plat_sci_port scif0_platform_data = {
21 .flags = UPF_BOOT_AUTOCONF, 21 .flags = UPF_BOOT_AUTOCONF,
22 .type = PORT_SCIF, 22 .type = PORT_SCIF,
23 .irqs = { 80, 80, 80, 80 }, 23 .irqs = { 80, 80, 80, 80 },
24 .clk = "scif0",
25}; 24};
26 25
27static struct platform_device scif0_device = { 26static struct platform_device scif0_device = {
@@ -37,7 +36,6 @@ static struct plat_sci_port scif1_platform_data = {
37 .flags = UPF_BOOT_AUTOCONF, 36 .flags = UPF_BOOT_AUTOCONF,
38 .type = PORT_SCIF, 37 .type = PORT_SCIF,
39 .irqs = { 81, 81, 81, 81 }, 38 .irqs = { 81, 81, 81, 81 },
40 .clk = "scif1",
41}; 39};
42 40
43static struct platform_device scif1_device = { 41static struct platform_device scif1_device = {
@@ -53,7 +51,6 @@ static struct plat_sci_port scif2_platform_data = {
53 .flags = UPF_BOOT_AUTOCONF, 51 .flags = UPF_BOOT_AUTOCONF,
54 .type = PORT_SCIF, 52 .type = PORT_SCIF,
55 .irqs = { 82, 82, 82, 82 }, 53 .irqs = { 82, 82, 82, 82 },
56 .clk = "scif2",
57}; 54};
58 55
59static struct platform_device scif2_device = { 56static struct platform_device scif2_device = {
@@ -69,7 +66,6 @@ static struct plat_sci_port scif3_platform_data = {
69 .flags = UPF_BOOT_AUTOCONF, 66 .flags = UPF_BOOT_AUTOCONF,
70 .type = PORT_SCIF, 67 .type = PORT_SCIF,
71 .irqs = { 83, 83, 83, 83 }, 68 .irqs = { 83, 83, 83, 83 },
72 .clk = "scif3",
73}; 69};
74 70
75static struct platform_device scif3_device = { 71static struct platform_device scif3_device = {
@@ -207,17 +203,14 @@ static struct platform_device jpu_device = {
207}; 203};
208 204
209static struct sh_timer_config cmt_platform_data = { 205static struct sh_timer_config cmt_platform_data = {
210 .name = "CMT",
211 .channel_offset = 0x60, 206 .channel_offset = 0x60,
212 .timer_bit = 5, 207 .timer_bit = 5,
213 .clk = "cmt0",
214 .clockevent_rating = 125, 208 .clockevent_rating = 125,
215 .clocksource_rating = 200, 209 .clocksource_rating = 200,
216}; 210};
217 211
218static struct resource cmt_resources[] = { 212static struct resource cmt_resources[] = {
219 [0] = { 213 [0] = {
220 .name = "CMT",
221 .start = 0x044a0060, 214 .start = 0x044a0060,
222 .end = 0x044a006b, 215 .end = 0x044a006b,
223 .flags = IORESOURCE_MEM, 216 .flags = IORESOURCE_MEM,
@@ -239,16 +232,13 @@ static struct platform_device cmt_device = {
239}; 232};
240 233
241static struct sh_timer_config tmu0_platform_data = { 234static struct sh_timer_config tmu0_platform_data = {
242 .name = "TMU0",
243 .channel_offset = 0x04, 235 .channel_offset = 0x04,
244 .timer_bit = 0, 236 .timer_bit = 0,
245 .clk = "tmu0",
246 .clockevent_rating = 200, 237 .clockevent_rating = 200,
247}; 238};
248 239
249static struct resource tmu0_resources[] = { 240static struct resource tmu0_resources[] = {
250 [0] = { 241 [0] = {
251 .name = "TMU0",
252 .start = 0xffd80008, 242 .start = 0xffd80008,
253 .end = 0xffd80013, 243 .end = 0xffd80013,
254 .flags = IORESOURCE_MEM, 244 .flags = IORESOURCE_MEM,
@@ -270,16 +260,13 @@ static struct platform_device tmu0_device = {
270}; 260};
271 261
272static struct sh_timer_config tmu1_platform_data = { 262static struct sh_timer_config tmu1_platform_data = {
273 .name = "TMU1",
274 .channel_offset = 0x10, 263 .channel_offset = 0x10,
275 .timer_bit = 1, 264 .timer_bit = 1,
276 .clk = "tmu0",
277 .clocksource_rating = 200, 265 .clocksource_rating = 200,
278}; 266};
279 267
280static struct resource tmu1_resources[] = { 268static struct resource tmu1_resources[] = {
281 [0] = { 269 [0] = {
282 .name = "TMU1",
283 .start = 0xffd80014, 270 .start = 0xffd80014,
284 .end = 0xffd8001f, 271 .end = 0xffd8001f,
285 .flags = IORESOURCE_MEM, 272 .flags = IORESOURCE_MEM,
@@ -301,15 +288,12 @@ static struct platform_device tmu1_device = {
301}; 288};
302 289
303static struct sh_timer_config tmu2_platform_data = { 290static struct sh_timer_config tmu2_platform_data = {
304 .name = "TMU2",
305 .channel_offset = 0x1c, 291 .channel_offset = 0x1c,
306 .timer_bit = 2, 292 .timer_bit = 2,
307 .clk = "tmu0",
308}; 293};
309 294
310static struct resource tmu2_resources[] = { 295static struct resource tmu2_resources[] = {
311 [0] = { 296 [0] = {
312 .name = "TMU2",
313 .start = 0xffd80020, 297 .start = 0xffd80020,
314 .end = 0xffd8002b, 298 .end = 0xffd8002b,
315 .flags = IORESOURCE_MEM, 299 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index c494c193e3b..8dab9e1bbd8 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -23,7 +23,6 @@ static struct plat_sci_port scif0_platform_data = {
23 .flags = UPF_BOOT_AUTOCONF, 23 .flags = UPF_BOOT_AUTOCONF,
24 .type = PORT_SCIF, 24 .type = PORT_SCIF,
25 .irqs = { 80, 80, 80, 80 }, 25 .irqs = { 80, 80, 80, 80 },
26 .clk = "scif0",
27}; 26};
28 27
29static struct platform_device scif0_device = { 28static struct platform_device scif0_device = {
@@ -169,17 +168,14 @@ static struct platform_device veu1_device = {
169}; 168};
170 169
171static struct sh_timer_config cmt_platform_data = { 170static struct sh_timer_config cmt_platform_data = {
172 .name = "CMT",
173 .channel_offset = 0x60, 171 .channel_offset = 0x60,
174 .timer_bit = 5, 172 .timer_bit = 5,
175 .clk = "cmt0",
176 .clockevent_rating = 125, 173 .clockevent_rating = 125,
177 .clocksource_rating = 200, 174 .clocksource_rating = 200,
178}; 175};
179 176
180static struct resource cmt_resources[] = { 177static struct resource cmt_resources[] = {
181 [0] = { 178 [0] = {
182 .name = "CMT",
183 .start = 0x044a0060, 179 .start = 0x044a0060,
184 .end = 0x044a006b, 180 .end = 0x044a006b,
185 .flags = IORESOURCE_MEM, 181 .flags = IORESOURCE_MEM,
@@ -201,16 +197,13 @@ static struct platform_device cmt_device = {
201}; 197};
202 198
203static struct sh_timer_config tmu0_platform_data = { 199static struct sh_timer_config tmu0_platform_data = {
204 .name = "TMU0",
205 .channel_offset = 0x04, 200 .channel_offset = 0x04,
206 .timer_bit = 0, 201 .timer_bit = 0,
207 .clk = "tmu0",
208 .clockevent_rating = 200, 202 .clockevent_rating = 200,
209}; 203};
210 204
211static struct resource tmu0_resources[] = { 205static struct resource tmu0_resources[] = {
212 [0] = { 206 [0] = {
213 .name = "TMU0",
214 .start = 0xffd80008, 207 .start = 0xffd80008,
215 .end = 0xffd80013, 208 .end = 0xffd80013,
216 .flags = IORESOURCE_MEM, 209 .flags = IORESOURCE_MEM,
@@ -232,16 +225,13 @@ static struct platform_device tmu0_device = {
232}; 225};
233 226
234static struct sh_timer_config tmu1_platform_data = { 227static struct sh_timer_config tmu1_platform_data = {
235 .name = "TMU1",
236 .channel_offset = 0x10, 228 .channel_offset = 0x10,
237 .timer_bit = 1, 229 .timer_bit = 1,
238 .clk = "tmu0",
239 .clocksource_rating = 200, 230 .clocksource_rating = 200,
240}; 231};
241 232
242static struct resource tmu1_resources[] = { 233static struct resource tmu1_resources[] = {
243 [0] = { 234 [0] = {
244 .name = "TMU1",
245 .start = 0xffd80014, 235 .start = 0xffd80014,
246 .end = 0xffd8001f, 236 .end = 0xffd8001f,
247 .flags = IORESOURCE_MEM, 237 .flags = IORESOURCE_MEM,
@@ -263,15 +253,12 @@ static struct platform_device tmu1_device = {
263}; 253};
264 254
265static struct sh_timer_config tmu2_platform_data = { 255static struct sh_timer_config tmu2_platform_data = {
266 .name = "TMU2",
267 .channel_offset = 0x1c, 256 .channel_offset = 0x1c,
268 .timer_bit = 2, 257 .timer_bit = 2,
269 .clk = "tmu0",
270}; 258};
271 259
272static struct resource tmu2_resources[] = { 260static struct resource tmu2_resources[] = {
273 [0] = { 261 [0] = {
274 .name = "TMU2",
275 .start = 0xffd80020, 262 .start = 0xffd80020,
276 .end = 0xffd8002b, 263 .end = 0xffd8002b,
277 .flags = IORESOURCE_MEM, 264 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index fd7e3639e84..24c6167a718 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -24,7 +24,7 @@
24#include <cpu/dma-register.h> 24#include <cpu/dma-register.h>
25#include <cpu/sh7722.h> 25#include <cpu/sh7722.h>
26 26
27static struct sh_dmae_slave_config sh7722_dmae_slaves[] = { 27static const struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
28 { 28 {
29 .slave_id = SHDMA_SLAVE_SCIF0_TX, 29 .slave_id = SHDMA_SLAVE_SCIF0_TX,
30 .addr = 0xffe0000c, 30 .addr = 0xffe0000c,
@@ -78,7 +78,7 @@ static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
78 }, 78 },
79}; 79};
80 80
81static struct sh_dmae_channel sh7722_dmae_channels[] = { 81static const struct sh_dmae_channel sh7722_dmae_channels[] = {
82 { 82 {
83 .offset = 0, 83 .offset = 0,
84 .dmars = 0, 84 .dmars = 0,
@@ -106,7 +106,7 @@ static struct sh_dmae_channel sh7722_dmae_channels[] = {
106 } 106 }
107}; 107};
108 108
109static unsigned int ts_shift[] = TS_SHIFT; 109static const unsigned int ts_shift[] = TS_SHIFT;
110 110
111static struct sh_dmae_pdata dma_platform_data = { 111static struct sh_dmae_pdata dma_platform_data = {
112 .slave = sh7722_dmae_slaves, 112 .slave = sh7722_dmae_slaves,
@@ -174,7 +174,6 @@ static struct plat_sci_port scif0_platform_data = {
174 .flags = UPF_BOOT_AUTOCONF, 174 .flags = UPF_BOOT_AUTOCONF,
175 .type = PORT_SCIF, 175 .type = PORT_SCIF,
176 .irqs = { 80, 80, 80, 80 }, 176 .irqs = { 80, 80, 80, 80 },
177 .clk = "scif0",
178}; 177};
179 178
180static struct platform_device scif0_device = { 179static struct platform_device scif0_device = {
@@ -190,7 +189,6 @@ static struct plat_sci_port scif1_platform_data = {
190 .flags = UPF_BOOT_AUTOCONF, 189 .flags = UPF_BOOT_AUTOCONF,
191 .type = PORT_SCIF, 190 .type = PORT_SCIF,
192 .irqs = { 81, 81, 81, 81 }, 191 .irqs = { 81, 81, 81, 81 },
193 .clk = "scif1",
194}; 192};
195 193
196static struct platform_device scif1_device = { 194static struct platform_device scif1_device = {
@@ -206,7 +204,6 @@ static struct plat_sci_port scif2_platform_data = {
206 .flags = UPF_BOOT_AUTOCONF, 204 .flags = UPF_BOOT_AUTOCONF,
207 .type = PORT_SCIF, 205 .type = PORT_SCIF,
208 .irqs = { 82, 82, 82, 82 }, 206 .irqs = { 82, 82, 82, 82 },
209 .clk = "scif2",
210}; 207};
211 208
212static struct platform_device scif2_device = { 209static struct platform_device scif2_device = {
@@ -401,17 +398,14 @@ static struct platform_device jpu_device = {
401}; 398};
402 399
403static struct sh_timer_config cmt_platform_data = { 400static struct sh_timer_config cmt_platform_data = {
404 .name = "CMT",
405 .channel_offset = 0x60, 401 .channel_offset = 0x60,
406 .timer_bit = 5, 402 .timer_bit = 5,
407 .clk = "cmt0",
408 .clockevent_rating = 125, 403 .clockevent_rating = 125,
409 .clocksource_rating = 125, 404 .clocksource_rating = 125,
410}; 405};
411 406
412static struct resource cmt_resources[] = { 407static struct resource cmt_resources[] = {
413 [0] = { 408 [0] = {
414 .name = "CMT",
415 .start = 0x044a0060, 409 .start = 0x044a0060,
416 .end = 0x044a006b, 410 .end = 0x044a006b,
417 .flags = IORESOURCE_MEM, 411 .flags = IORESOURCE_MEM,
@@ -436,16 +430,13 @@ static struct platform_device cmt_device = {
436}; 430};
437 431
438static struct sh_timer_config tmu0_platform_data = { 432static struct sh_timer_config tmu0_platform_data = {
439 .name = "TMU0",
440 .channel_offset = 0x04, 433 .channel_offset = 0x04,
441 .timer_bit = 0, 434 .timer_bit = 0,
442 .clk = "tmu0",
443 .clockevent_rating = 200, 435 .clockevent_rating = 200,
444}; 436};
445 437
446static struct resource tmu0_resources[] = { 438static struct resource tmu0_resources[] = {
447 [0] = { 439 [0] = {
448 .name = "TMU0",
449 .start = 0xffd80008, 440 .start = 0xffd80008,
450 .end = 0xffd80013, 441 .end = 0xffd80013,
451 .flags = IORESOURCE_MEM, 442 .flags = IORESOURCE_MEM,
@@ -470,16 +461,13 @@ static struct platform_device tmu0_device = {
470}; 461};
471 462
472static struct sh_timer_config tmu1_platform_data = { 463static struct sh_timer_config tmu1_platform_data = {
473 .name = "TMU1",
474 .channel_offset = 0x10, 464 .channel_offset = 0x10,
475 .timer_bit = 1, 465 .timer_bit = 1,
476 .clk = "tmu0",
477 .clocksource_rating = 200, 466 .clocksource_rating = 200,
478}; 467};
479 468
480static struct resource tmu1_resources[] = { 469static struct resource tmu1_resources[] = {
481 [0] = { 470 [0] = {
482 .name = "TMU1",
483 .start = 0xffd80014, 471 .start = 0xffd80014,
484 .end = 0xffd8001f, 472 .end = 0xffd8001f,
485 .flags = IORESOURCE_MEM, 473 .flags = IORESOURCE_MEM,
@@ -504,15 +492,12 @@ static struct platform_device tmu1_device = {
504}; 492};
505 493
506static struct sh_timer_config tmu2_platform_data = { 494static struct sh_timer_config tmu2_platform_data = {
507 .name = "TMU2",
508 .channel_offset = 0x1c, 495 .channel_offset = 0x1c,
509 .timer_bit = 2, 496 .timer_bit = 2,
510 .clk = "tmu0",
511}; 497};
512 498
513static struct resource tmu2_resources[] = { 499static struct resource tmu2_resources[] = {
514 [0] = { 500 [0] = {
515 .name = "TMU2",
516 .start = 0xffd80020, 501 .start = 0xffd80020,
517 .end = 0xffd8002b, 502 .end = 0xffd8002b,
518 .flags = IORESOURCE_MEM, 503 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 85c61f62470..0eadefdbbba 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -26,7 +26,6 @@ static struct plat_sci_port scif0_platform_data = {
26 .flags = UPF_BOOT_AUTOCONF, 26 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF, 27 .type = PORT_SCIF,
28 .irqs = { 80, 80, 80, 80 }, 28 .irqs = { 80, 80, 80, 80 },
29 .clk = "scif0",
30}; 29};
31 30
32static struct platform_device scif0_device = { 31static struct platform_device scif0_device = {
@@ -42,7 +41,6 @@ static struct plat_sci_port scif1_platform_data = {
42 .flags = UPF_BOOT_AUTOCONF, 41 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCIF, 42 .type = PORT_SCIF,
44 .irqs = { 81, 81, 81, 81 }, 43 .irqs = { 81, 81, 81, 81 },
45 .clk = "scif1",
46}; 44};
47 45
48static struct platform_device scif1_device = { 46static struct platform_device scif1_device = {
@@ -58,7 +56,6 @@ static struct plat_sci_port scif2_platform_data = {
58 .flags = UPF_BOOT_AUTOCONF, 56 .flags = UPF_BOOT_AUTOCONF,
59 .type = PORT_SCIF, 57 .type = PORT_SCIF,
60 .irqs = { 82, 82, 82, 82 }, 58 .irqs = { 82, 82, 82, 82 },
61 .clk = "scif2",
62}; 59};
63 60
64static struct platform_device scif2_device = { 61static struct platform_device scif2_device = {
@@ -74,7 +71,6 @@ static struct plat_sci_port scif3_platform_data = {
74 .flags = UPF_BOOT_AUTOCONF, 71 .flags = UPF_BOOT_AUTOCONF,
75 .type = PORT_SCIFA, 72 .type = PORT_SCIFA,
76 .irqs = { 56, 56, 56, 56 }, 73 .irqs = { 56, 56, 56, 56 },
77 .clk = "scif3",
78}; 74};
79 75
80static struct platform_device scif3_device = { 76static struct platform_device scif3_device = {
@@ -90,7 +86,6 @@ static struct plat_sci_port scif4_platform_data = {
90 .flags = UPF_BOOT_AUTOCONF, 86 .flags = UPF_BOOT_AUTOCONF,
91 .type = PORT_SCIFA, 87 .type = PORT_SCIFA,
92 .irqs = { 88, 88, 88, 88 }, 88 .irqs = { 88, 88, 88, 88 },
93 .clk = "scif4",
94}; 89};
95 90
96static struct platform_device scif4_device = { 91static struct platform_device scif4_device = {
@@ -106,7 +101,6 @@ static struct plat_sci_port scif5_platform_data = {
106 .flags = UPF_BOOT_AUTOCONF, 101 .flags = UPF_BOOT_AUTOCONF,
107 .type = PORT_SCIFA, 102 .type = PORT_SCIFA,
108 .irqs = { 109, 109, 109, 109 }, 103 .irqs = { 109, 109, 109, 109 },
109 .clk = "scif5",
110}; 104};
111 105
112static struct platform_device scif5_device = { 106static struct platform_device scif5_device = {
@@ -211,17 +205,14 @@ static struct platform_device veu1_device = {
211}; 205};
212 206
213static struct sh_timer_config cmt_platform_data = { 207static struct sh_timer_config cmt_platform_data = {
214 .name = "CMT",
215 .channel_offset = 0x60, 208 .channel_offset = 0x60,
216 .timer_bit = 5, 209 .timer_bit = 5,
217 .clk = "cmt0",
218 .clockevent_rating = 125, 210 .clockevent_rating = 125,
219 .clocksource_rating = 125, 211 .clocksource_rating = 125,
220}; 212};
221 213
222static struct resource cmt_resources[] = { 214static struct resource cmt_resources[] = {
223 [0] = { 215 [0] = {
224 .name = "CMT",
225 .start = 0x044a0060, 216 .start = 0x044a0060,
226 .end = 0x044a006b, 217 .end = 0x044a006b,
227 .flags = IORESOURCE_MEM, 218 .flags = IORESOURCE_MEM,
@@ -246,16 +237,13 @@ static struct platform_device cmt_device = {
246}; 237};
247 238
248static struct sh_timer_config tmu0_platform_data = { 239static struct sh_timer_config tmu0_platform_data = {
249 .name = "TMU0",
250 .channel_offset = 0x04, 240 .channel_offset = 0x04,
251 .timer_bit = 0, 241 .timer_bit = 0,
252 .clk = "tmu0",
253 .clockevent_rating = 200, 242 .clockevent_rating = 200,
254}; 243};
255 244
256static struct resource tmu0_resources[] = { 245static struct resource tmu0_resources[] = {
257 [0] = { 246 [0] = {
258 .name = "TMU0",
259 .start = 0xffd80008, 247 .start = 0xffd80008,
260 .end = 0xffd80013, 248 .end = 0xffd80013,
261 .flags = IORESOURCE_MEM, 249 .flags = IORESOURCE_MEM,
@@ -280,16 +268,13 @@ static struct platform_device tmu0_device = {
280}; 268};
281 269
282static struct sh_timer_config tmu1_platform_data = { 270static struct sh_timer_config tmu1_platform_data = {
283 .name = "TMU1",
284 .channel_offset = 0x10, 271 .channel_offset = 0x10,
285 .timer_bit = 1, 272 .timer_bit = 1,
286 .clk = "tmu0",
287 .clocksource_rating = 200, 273 .clocksource_rating = 200,
288}; 274};
289 275
290static struct resource tmu1_resources[] = { 276static struct resource tmu1_resources[] = {
291 [0] = { 277 [0] = {
292 .name = "TMU1",
293 .start = 0xffd80014, 278 .start = 0xffd80014,
294 .end = 0xffd8001f, 279 .end = 0xffd8001f,
295 .flags = IORESOURCE_MEM, 280 .flags = IORESOURCE_MEM,
@@ -314,15 +299,12 @@ static struct platform_device tmu1_device = {
314}; 299};
315 300
316static struct sh_timer_config tmu2_platform_data = { 301static struct sh_timer_config tmu2_platform_data = {
317 .name = "TMU2",
318 .channel_offset = 0x1c, 302 .channel_offset = 0x1c,
319 .timer_bit = 2, 303 .timer_bit = 2,
320 .clk = "tmu0",
321}; 304};
322 305
323static struct resource tmu2_resources[] = { 306static struct resource tmu2_resources[] = {
324 [0] = { 307 [0] = {
325 .name = "TMU2",
326 .start = 0xffd80020, 308 .start = 0xffd80020,
327 .end = 0xffd8002b, 309 .end = 0xffd8002b,
328 .flags = IORESOURCE_MEM, 310 .flags = IORESOURCE_MEM,
@@ -347,15 +329,12 @@ static struct platform_device tmu2_device = {
347}; 329};
348 330
349static struct sh_timer_config tmu3_platform_data = { 331static struct sh_timer_config tmu3_platform_data = {
350 .name = "TMU3",
351 .channel_offset = 0x04, 332 .channel_offset = 0x04,
352 .timer_bit = 0, 333 .timer_bit = 0,
353 .clk = "tmu1",
354}; 334};
355 335
356static struct resource tmu3_resources[] = { 336static struct resource tmu3_resources[] = {
357 [0] = { 337 [0] = {
358 .name = "TMU3",
359 .start = 0xffd90008, 338 .start = 0xffd90008,
360 .end = 0xffd90013, 339 .end = 0xffd90013,
361 .flags = IORESOURCE_MEM, 340 .flags = IORESOURCE_MEM,
@@ -380,15 +359,12 @@ static struct platform_device tmu3_device = {
380}; 359};
381 360
382static struct sh_timer_config tmu4_platform_data = { 361static struct sh_timer_config tmu4_platform_data = {
383 .name = "TMU4",
384 .channel_offset = 0x10, 362 .channel_offset = 0x10,
385 .timer_bit = 1, 363 .timer_bit = 1,
386 .clk = "tmu1",
387}; 364};
388 365
389static struct resource tmu4_resources[] = { 366static struct resource tmu4_resources[] = {
390 [0] = { 367 [0] = {
391 .name = "TMU4",
392 .start = 0xffd90014, 368 .start = 0xffd90014,
393 .end = 0xffd9001f, 369 .end = 0xffd9001f,
394 .flags = IORESOURCE_MEM, 370 .flags = IORESOURCE_MEM,
@@ -413,15 +389,12 @@ static struct platform_device tmu4_device = {
413}; 389};
414 390
415static struct sh_timer_config tmu5_platform_data = { 391static struct sh_timer_config tmu5_platform_data = {
416 .name = "TMU5",
417 .channel_offset = 0x1c, 392 .channel_offset = 0x1c,
418 .timer_bit = 2, 393 .timer_bit = 2,
419 .clk = "tmu1",
420}; 394};
421 395
422static struct resource tmu5_resources[] = { 396static struct resource tmu5_resources[] = {
423 [0] = { 397 [0] = {
424 .name = "TMU5",
425 .start = 0xffd90020, 398 .start = 0xffd90020,
426 .end = 0xffd9002b, 399 .end = 0xffd9002b,
427 .flags = IORESOURCE_MEM, 400 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index e7fa2a92fc1..89fe16d20fd 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -31,7 +31,7 @@
31#include <cpu/sh7724.h> 31#include <cpu/sh7724.h>
32 32
33/* DMA */ 33/* DMA */
34static struct sh_dmae_channel sh7724_dmae0_channels[] = { 34static const struct sh_dmae_channel sh7724_dmae_channels[] = {
35 { 35 {
36 .offset = 0, 36 .offset = 0,
37 .dmars = 0, 37 .dmars = 0,
@@ -59,51 +59,11 @@ static struct sh_dmae_channel sh7724_dmae0_channels[] = {
59 } 59 }
60}; 60};
61 61
62static struct sh_dmae_channel sh7724_dmae1_channels[] = { 62static const unsigned int ts_shift[] = TS_SHIFT;
63 {
64 .offset = 0,
65 .dmars = 0,
66 .dmars_bit = 0,
67 }, {
68 .offset = 0x10,
69 .dmars = 0,
70 .dmars_bit = 8,
71 }, {
72 .offset = 0x20,
73 .dmars = 4,
74 .dmars_bit = 0,
75 }, {
76 .offset = 0x30,
77 .dmars = 4,
78 .dmars_bit = 8,
79 }, {
80 .offset = 0x50,
81 .dmars = 8,
82 .dmars_bit = 0,
83 }, {
84 .offset = 0x60,
85 .dmars = 8,
86 .dmars_bit = 8,
87 }
88};
89
90static unsigned int ts_shift[] = TS_SHIFT;
91
92static struct sh_dmae_pdata dma0_platform_data = {
93 .channel = sh7724_dmae0_channels,
94 .channel_num = ARRAY_SIZE(sh7724_dmae0_channels),
95 .ts_low_shift = CHCR_TS_LOW_SHIFT,
96 .ts_low_mask = CHCR_TS_LOW_MASK,
97 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
98 .ts_high_mask = CHCR_TS_HIGH_MASK,
99 .ts_shift = ts_shift,
100 .ts_shift_num = ARRAY_SIZE(ts_shift),
101 .dmaor_init = DMAOR_INIT,
102};
103 63
104static struct sh_dmae_pdata dma1_platform_data = { 64static struct sh_dmae_pdata dma_platform_data = {
105 .channel = sh7724_dmae1_channels, 65 .channel = sh7724_dmae_channels,
106 .channel_num = ARRAY_SIZE(sh7724_dmae1_channels), 66 .channel_num = ARRAY_SIZE(sh7724_dmae_channels),
107 .ts_low_shift = CHCR_TS_LOW_SHIFT, 67 .ts_low_shift = CHCR_TS_LOW_SHIFT,
108 .ts_low_mask = CHCR_TS_LOW_MASK, 68 .ts_low_mask = CHCR_TS_LOW_MASK,
109 .ts_high_shift = CHCR_TS_HIGH_SHIFT, 69 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
@@ -187,7 +147,7 @@ static struct platform_device dma0_device = {
187 .resource = sh7724_dmae0_resources, 147 .resource = sh7724_dmae0_resources,
188 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources), 148 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
189 .dev = { 149 .dev = {
190 .platform_data = &dma0_platform_data, 150 .platform_data = &dma_platform_data,
191 }, 151 },
192 .archdata = { 152 .archdata = {
193 .hwblk_id = HWBLK_DMAC0, 153 .hwblk_id = HWBLK_DMAC0,
@@ -200,7 +160,7 @@ static struct platform_device dma1_device = {
200 .resource = sh7724_dmae1_resources, 160 .resource = sh7724_dmae1_resources,
201 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources), 161 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
202 .dev = { 162 .dev = {
203 .platform_data = &dma1_platform_data, 163 .platform_data = &dma_platform_data,
204 }, 164 },
205 .archdata = { 165 .archdata = {
206 .hwblk_id = HWBLK_DMAC1, 166 .hwblk_id = HWBLK_DMAC1,
@@ -213,7 +173,6 @@ static struct plat_sci_port scif0_platform_data = {
213 .flags = UPF_BOOT_AUTOCONF, 173 .flags = UPF_BOOT_AUTOCONF,
214 .type = PORT_SCIF, 174 .type = PORT_SCIF,
215 .irqs = { 80, 80, 80, 80 }, 175 .irqs = { 80, 80, 80, 80 },
216 .clk = "scif0",
217}; 176};
218 177
219static struct platform_device scif0_device = { 178static struct platform_device scif0_device = {
@@ -229,7 +188,6 @@ static struct plat_sci_port scif1_platform_data = {
229 .flags = UPF_BOOT_AUTOCONF, 188 .flags = UPF_BOOT_AUTOCONF,
230 .type = PORT_SCIF, 189 .type = PORT_SCIF,
231 .irqs = { 81, 81, 81, 81 }, 190 .irqs = { 81, 81, 81, 81 },
232 .clk = "scif1",
233}; 191};
234 192
235static struct platform_device scif1_device = { 193static struct platform_device scif1_device = {
@@ -245,7 +203,6 @@ static struct plat_sci_port scif2_platform_data = {
245 .flags = UPF_BOOT_AUTOCONF, 203 .flags = UPF_BOOT_AUTOCONF,
246 .type = PORT_SCIF, 204 .type = PORT_SCIF,
247 .irqs = { 82, 82, 82, 82 }, 205 .irqs = { 82, 82, 82, 82 },
248 .clk = "scif2",
249}; 206};
250 207
251static struct platform_device scif2_device = { 208static struct platform_device scif2_device = {
@@ -261,7 +218,6 @@ static struct plat_sci_port scif3_platform_data = {
261 .flags = UPF_BOOT_AUTOCONF, 218 .flags = UPF_BOOT_AUTOCONF,
262 .type = PORT_SCIFA, 219 .type = PORT_SCIFA,
263 .irqs = { 56, 56, 56, 56 }, 220 .irqs = { 56, 56, 56, 56 },
264 .clk = "scif3",
265}; 221};
266 222
267static struct platform_device scif3_device = { 223static struct platform_device scif3_device = {
@@ -277,7 +233,6 @@ static struct plat_sci_port scif4_platform_data = {
277 .flags = UPF_BOOT_AUTOCONF, 233 .flags = UPF_BOOT_AUTOCONF,
278 .type = PORT_SCIFA, 234 .type = PORT_SCIFA,
279 .irqs = { 88, 88, 88, 88 }, 235 .irqs = { 88, 88, 88, 88 },
280 .clk = "scif4",
281}; 236};
282 237
283static struct platform_device scif4_device = { 238static struct platform_device scif4_device = {
@@ -293,7 +248,6 @@ static struct plat_sci_port scif5_platform_data = {
293 .flags = UPF_BOOT_AUTOCONF, 248 .flags = UPF_BOOT_AUTOCONF,
294 .type = PORT_SCIFA, 249 .type = PORT_SCIFA,
295 .irqs = { 109, 109, 109, 109 }, 250 .irqs = { 109, 109, 109, 109 },
296 .clk = "scif5",
297}; 251};
298 252
299static struct platform_device scif5_device = { 253static struct platform_device scif5_device = {
@@ -485,17 +439,14 @@ static struct platform_device veu1_device = {
485}; 439};
486 440
487static struct sh_timer_config cmt_platform_data = { 441static struct sh_timer_config cmt_platform_data = {
488 .name = "CMT",
489 .channel_offset = 0x60, 442 .channel_offset = 0x60,
490 .timer_bit = 5, 443 .timer_bit = 5,
491 .clk = "cmt0",
492 .clockevent_rating = 125, 444 .clockevent_rating = 125,
493 .clocksource_rating = 200, 445 .clocksource_rating = 200,
494}; 446};
495 447
496static struct resource cmt_resources[] = { 448static struct resource cmt_resources[] = {
497 [0] = { 449 [0] = {
498 .name = "CMT",
499 .start = 0x044a0060, 450 .start = 0x044a0060,
500 .end = 0x044a006b, 451 .end = 0x044a006b,
501 .flags = IORESOURCE_MEM, 452 .flags = IORESOURCE_MEM,
@@ -520,16 +471,13 @@ static struct platform_device cmt_device = {
520}; 471};
521 472
522static struct sh_timer_config tmu0_platform_data = { 473static struct sh_timer_config tmu0_platform_data = {
523 .name = "TMU0",
524 .channel_offset = 0x04, 474 .channel_offset = 0x04,
525 .timer_bit = 0, 475 .timer_bit = 0,
526 .clk = "tmu0",
527 .clockevent_rating = 200, 476 .clockevent_rating = 200,
528}; 477};
529 478
530static struct resource tmu0_resources[] = { 479static struct resource tmu0_resources[] = {
531 [0] = { 480 [0] = {
532 .name = "TMU0",
533 .start = 0xffd80008, 481 .start = 0xffd80008,
534 .end = 0xffd80013, 482 .end = 0xffd80013,
535 .flags = IORESOURCE_MEM, 483 .flags = IORESOURCE_MEM,
@@ -554,16 +502,13 @@ static struct platform_device tmu0_device = {
554}; 502};
555 503
556static struct sh_timer_config tmu1_platform_data = { 504static struct sh_timer_config tmu1_platform_data = {
557 .name = "TMU1",
558 .channel_offset = 0x10, 505 .channel_offset = 0x10,
559 .timer_bit = 1, 506 .timer_bit = 1,
560 .clk = "tmu0",
561 .clocksource_rating = 200, 507 .clocksource_rating = 200,
562}; 508};
563 509
564static struct resource tmu1_resources[] = { 510static struct resource tmu1_resources[] = {
565 [0] = { 511 [0] = {
566 .name = "TMU1",
567 .start = 0xffd80014, 512 .start = 0xffd80014,
568 .end = 0xffd8001f, 513 .end = 0xffd8001f,
569 .flags = IORESOURCE_MEM, 514 .flags = IORESOURCE_MEM,
@@ -588,15 +533,12 @@ static struct platform_device tmu1_device = {
588}; 533};
589 534
590static struct sh_timer_config tmu2_platform_data = { 535static struct sh_timer_config tmu2_platform_data = {
591 .name = "TMU2",
592 .channel_offset = 0x1c, 536 .channel_offset = 0x1c,
593 .timer_bit = 2, 537 .timer_bit = 2,
594 .clk = "tmu0",
595}; 538};
596 539
597static struct resource tmu2_resources[] = { 540static struct resource tmu2_resources[] = {
598 [0] = { 541 [0] = {
599 .name = "TMU2",
600 .start = 0xffd80020, 542 .start = 0xffd80020,
601 .end = 0xffd8002b, 543 .end = 0xffd8002b,
602 .flags = IORESOURCE_MEM, 544 .flags = IORESOURCE_MEM,
@@ -622,15 +564,12 @@ static struct platform_device tmu2_device = {
622 564
623 565
624static struct sh_timer_config tmu3_platform_data = { 566static struct sh_timer_config tmu3_platform_data = {
625 .name = "TMU3",
626 .channel_offset = 0x04, 567 .channel_offset = 0x04,
627 .timer_bit = 0, 568 .timer_bit = 0,
628 .clk = "tmu1",
629}; 569};
630 570
631static struct resource tmu3_resources[] = { 571static struct resource tmu3_resources[] = {
632 [0] = { 572 [0] = {
633 .name = "TMU3",
634 .start = 0xffd90008, 573 .start = 0xffd90008,
635 .end = 0xffd90013, 574 .end = 0xffd90013,
636 .flags = IORESOURCE_MEM, 575 .flags = IORESOURCE_MEM,
@@ -655,15 +594,12 @@ static struct platform_device tmu3_device = {
655}; 594};
656 595
657static struct sh_timer_config tmu4_platform_data = { 596static struct sh_timer_config tmu4_platform_data = {
658 .name = "TMU4",
659 .channel_offset = 0x10, 597 .channel_offset = 0x10,
660 .timer_bit = 1, 598 .timer_bit = 1,
661 .clk = "tmu1",
662}; 599};
663 600
664static struct resource tmu4_resources[] = { 601static struct resource tmu4_resources[] = {
665 [0] = { 602 [0] = {
666 .name = "TMU4",
667 .start = 0xffd90014, 603 .start = 0xffd90014,
668 .end = 0xffd9001f, 604 .end = 0xffd9001f,
669 .flags = IORESOURCE_MEM, 605 .flags = IORESOURCE_MEM,
@@ -688,15 +624,12 @@ static struct platform_device tmu4_device = {
688}; 624};
689 625
690static struct sh_timer_config tmu5_platform_data = { 626static struct sh_timer_config tmu5_platform_data = {
691 .name = "TMU5",
692 .channel_offset = 0x1c, 627 .channel_offset = 0x1c,
693 .timer_bit = 2, 628 .timer_bit = 2,
694 .clk = "tmu1",
695}; 629};
696 630
697static struct resource tmu5_resources[] = { 631static struct resource tmu5_resources[] = {
698 [0] = { 632 [0] = {
699 .name = "TMU5",
700 .start = 0xffd90020, 633 .start = 0xffd90020,
701 .end = 0xffd9002b, 634 .end = 0xffd9002b,
702 .flags = IORESOURCE_MEM, 635 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index e75edf58796..444aca95b20 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -63,16 +63,13 @@ static struct platform_device scif4_device = {
63}; 63};
64 64
65static struct sh_timer_config tmu0_platform_data = { 65static struct sh_timer_config tmu0_platform_data = {
66 .name = "TMU0",
67 .channel_offset = 0x04, 66 .channel_offset = 0x04,
68 .timer_bit = 0, 67 .timer_bit = 0,
69 .clk = "peripheral_clk",
70 .clockevent_rating = 200, 68 .clockevent_rating = 200,
71}; 69};
72 70
73static struct resource tmu0_resources[] = { 71static struct resource tmu0_resources[] = {
74 [0] = { 72 [0] = {
75 .name = "TMU0",
76 .start = 0xfe430008, 73 .start = 0xfe430008,
77 .end = 0xfe430013, 74 .end = 0xfe430013,
78 .flags = IORESOURCE_MEM, 75 .flags = IORESOURCE_MEM,
@@ -94,16 +91,13 @@ static struct platform_device tmu0_device = {
94}; 91};
95 92
96static struct sh_timer_config tmu1_platform_data = { 93static struct sh_timer_config tmu1_platform_data = {
97 .name = "TMU1",
98 .channel_offset = 0x10, 94 .channel_offset = 0x10,
99 .timer_bit = 1, 95 .timer_bit = 1,
100 .clk = "peripheral_clk",
101 .clocksource_rating = 200, 96 .clocksource_rating = 200,
102}; 97};
103 98
104static struct resource tmu1_resources[] = { 99static struct resource tmu1_resources[] = {
105 [0] = { 100 [0] = {
106 .name = "TMU1",
107 .start = 0xfe430014, 101 .start = 0xfe430014,
108 .end = 0xfe43001f, 102 .end = 0xfe43001f,
109 .flags = IORESOURCE_MEM, 103 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 7f6b0a5f7f8..5b5f6b005fc 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -131,16 +131,13 @@ static struct platform_device usbf_device = {
131}; 131};
132 132
133static struct sh_timer_config tmu0_platform_data = { 133static struct sh_timer_config tmu0_platform_data = {
134 .name = "TMU0",
135 .channel_offset = 0x04, 134 .channel_offset = 0x04,
136 .timer_bit = 0, 135 .timer_bit = 0,
137 .clk = "peripheral_clk",
138 .clockevent_rating = 200, 136 .clockevent_rating = 200,
139}; 137};
140 138
141static struct resource tmu0_resources[] = { 139static struct resource tmu0_resources[] = {
142 [0] = { 140 [0] = {
143 .name = "TMU0",
144 .start = 0xffd80008, 141 .start = 0xffd80008,
145 .end = 0xffd80013, 142 .end = 0xffd80013,
146 .flags = IORESOURCE_MEM, 143 .flags = IORESOURCE_MEM,
@@ -162,16 +159,13 @@ static struct platform_device tmu0_device = {
162}; 159};
163 160
164static struct sh_timer_config tmu1_platform_data = { 161static struct sh_timer_config tmu1_platform_data = {
165 .name = "TMU1",
166 .channel_offset = 0x10, 162 .channel_offset = 0x10,
167 .timer_bit = 1, 163 .timer_bit = 1,
168 .clk = "peripheral_clk",
169 .clocksource_rating = 200, 164 .clocksource_rating = 200,
170}; 165};
171 166
172static struct resource tmu1_resources[] = { 167static struct resource tmu1_resources[] = {
173 [0] = { 168 [0] = {
174 .name = "TMU1",
175 .start = 0xffd80014, 169 .start = 0xffd80014,
176 .end = 0xffd8001f, 170 .end = 0xffd8001f,
177 .flags = IORESOURCE_MEM, 171 .flags = IORESOURCE_MEM,
@@ -193,15 +187,12 @@ static struct platform_device tmu1_device = {
193}; 187};
194 188
195static struct sh_timer_config tmu2_platform_data = { 189static struct sh_timer_config tmu2_platform_data = {
196 .name = "TMU2",
197 .channel_offset = 0x1c, 190 .channel_offset = 0x1c,
198 .timer_bit = 2, 191 .timer_bit = 2,
199 .clk = "peripheral_clk",
200}; 192};
201 193
202static struct resource tmu2_resources[] = { 194static struct resource tmu2_resources[] = {
203 [0] = { 195 [0] = {
204 .name = "TMU2",
205 .start = 0xffd80020, 196 .start = 0xffd80020,
206 .end = 0xffd8002f, 197 .end = 0xffd8002f,
207 .flags = IORESOURCE_MEM, 198 .flags = IORESOURCE_MEM,
@@ -223,15 +214,12 @@ static struct platform_device tmu2_device = {
223}; 214};
224 215
225static struct sh_timer_config tmu3_platform_data = { 216static struct sh_timer_config tmu3_platform_data = {
226 .name = "TMU3",
227 .channel_offset = 0x04, 217 .channel_offset = 0x04,
228 .timer_bit = 0, 218 .timer_bit = 0,
229 .clk = "peripheral_clk",
230}; 219};
231 220
232static struct resource tmu3_resources[] = { 221static struct resource tmu3_resources[] = {
233 [0] = { 222 [0] = {
234 .name = "TMU3",
235 .start = 0xffd88008, 223 .start = 0xffd88008,
236 .end = 0xffd88013, 224 .end = 0xffd88013,
237 .flags = IORESOURCE_MEM, 225 .flags = IORESOURCE_MEM,
@@ -253,15 +241,12 @@ static struct platform_device tmu3_device = {
253}; 241};
254 242
255static struct sh_timer_config tmu4_platform_data = { 243static struct sh_timer_config tmu4_platform_data = {
256 .name = "TMU4",
257 .channel_offset = 0x10, 244 .channel_offset = 0x10,
258 .timer_bit = 1, 245 .timer_bit = 1,
259 .clk = "peripheral_clk",
260}; 246};
261 247
262static struct resource tmu4_resources[] = { 248static struct resource tmu4_resources[] = {
263 [0] = { 249 [0] = {
264 .name = "TMU4",
265 .start = 0xffd88014, 250 .start = 0xffd88014,
266 .end = 0xffd8801f, 251 .end = 0xffd8801f,
267 .flags = IORESOURCE_MEM, 252 .flags = IORESOURCE_MEM,
@@ -283,15 +268,12 @@ static struct platform_device tmu4_device = {
283}; 268};
284 269
285static struct sh_timer_config tmu5_platform_data = { 270static struct sh_timer_config tmu5_platform_data = {
286 .name = "TMU5",
287 .channel_offset = 0x1c, 271 .channel_offset = 0x1c,
288 .timer_bit = 2, 272 .timer_bit = 2,
289 .clk = "peripheral_clk",
290}; 273};
291 274
292static struct resource tmu5_resources[] = { 275static struct resource tmu5_resources[] = {
293 [0] = { 276 [0] = {
294 .name = "TMU5",
295 .start = 0xffd88020, 277 .start = 0xffd88020,
296 .end = 0xffd8802b, 278 .end = 0xffd8802b,
297 .flags = IORESOURCE_MEM, 279 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index 86d681ecf90..7270d7fd676 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -165,16 +165,13 @@ static struct platform_device scif9_device = {
165}; 165};
166 166
167static struct sh_timer_config tmu0_platform_data = { 167static struct sh_timer_config tmu0_platform_data = {
168 .name = "TMU0",
169 .channel_offset = 0x04, 168 .channel_offset = 0x04,
170 .timer_bit = 0, 169 .timer_bit = 0,
171 .clk = "peripheral_clk",
172 .clockevent_rating = 200, 170 .clockevent_rating = 200,
173}; 171};
174 172
175static struct resource tmu0_resources[] = { 173static struct resource tmu0_resources[] = {
176 [0] = { 174 [0] = {
177 .name = "TMU0",
178 .start = 0xffd80008, 175 .start = 0xffd80008,
179 .end = 0xffd80013, 176 .end = 0xffd80013,
180 .flags = IORESOURCE_MEM, 177 .flags = IORESOURCE_MEM,
@@ -196,16 +193,13 @@ static struct platform_device tmu0_device = {
196}; 193};
197 194
198static struct sh_timer_config tmu1_platform_data = { 195static struct sh_timer_config tmu1_platform_data = {
199 .name = "TMU1",
200 .channel_offset = 0x10, 196 .channel_offset = 0x10,
201 .timer_bit = 1, 197 .timer_bit = 1,
202 .clk = "peripheral_clk",
203 .clocksource_rating = 200, 198 .clocksource_rating = 200,
204}; 199};
205 200
206static struct resource tmu1_resources[] = { 201static struct resource tmu1_resources[] = {
207 [0] = { 202 [0] = {
208 .name = "TMU1",
209 .start = 0xffd80014, 203 .start = 0xffd80014,
210 .end = 0xffd8001f, 204 .end = 0xffd8001f,
211 .flags = IORESOURCE_MEM, 205 .flags = IORESOURCE_MEM,
@@ -227,15 +221,12 @@ static struct platform_device tmu1_device = {
227}; 221};
228 222
229static struct sh_timer_config tmu2_platform_data = { 223static struct sh_timer_config tmu2_platform_data = {
230 .name = "TMU2",
231 .channel_offset = 0x1c, 224 .channel_offset = 0x1c,
232 .timer_bit = 2, 225 .timer_bit = 2,
233 .clk = "peripheral_clk",
234}; 226};
235 227
236static struct resource tmu2_resources[] = { 228static struct resource tmu2_resources[] = {
237 [0] = { 229 [0] = {
238 .name = "TMU2",
239 .start = 0xffd80020, 230 .start = 0xffd80020,
240 .end = 0xffd8002f, 231 .end = 0xffd8002f,
241 .flags = IORESOURCE_MEM, 232 .flags = IORESOURCE_MEM,
@@ -257,15 +248,12 @@ static struct platform_device tmu2_device = {
257}; 248};
258 249
259static struct sh_timer_config tmu3_platform_data = { 250static struct sh_timer_config tmu3_platform_data = {
260 .name = "TMU3",
261 .channel_offset = 0x04, 251 .channel_offset = 0x04,
262 .timer_bit = 0, 252 .timer_bit = 0,
263 .clk = "peripheral_clk",
264}; 253};
265 254
266static struct resource tmu3_resources[] = { 255static struct resource tmu3_resources[] = {
267 [0] = { 256 [0] = {
268 .name = "TMU3",
269 .start = 0xffd81008, 257 .start = 0xffd81008,
270 .end = 0xffd81013, 258 .end = 0xffd81013,
271 .flags = IORESOURCE_MEM, 259 .flags = IORESOURCE_MEM,
@@ -287,15 +275,12 @@ static struct platform_device tmu3_device = {
287}; 275};
288 276
289static struct sh_timer_config tmu4_platform_data = { 277static struct sh_timer_config tmu4_platform_data = {
290 .name = "TMU4",
291 .channel_offset = 0x10, 278 .channel_offset = 0x10,
292 .timer_bit = 1, 279 .timer_bit = 1,
293 .clk = "peripheral_clk",
294}; 280};
295 281
296static struct resource tmu4_resources[] = { 282static struct resource tmu4_resources[] = {
297 [0] = { 283 [0] = {
298 .name = "TMU4",
299 .start = 0xffd81014, 284 .start = 0xffd81014,
300 .end = 0xffd8101f, 285 .end = 0xffd8101f,
301 .flags = IORESOURCE_MEM, 286 .flags = IORESOURCE_MEM,
@@ -317,15 +302,12 @@ static struct platform_device tmu4_device = {
317}; 302};
318 303
319static struct sh_timer_config tmu5_platform_data = { 304static struct sh_timer_config tmu5_platform_data = {
320 .name = "TMU5",
321 .channel_offset = 0x1c, 305 .channel_offset = 0x1c,
322 .timer_bit = 2, 306 .timer_bit = 2,
323 .clk = "peripheral_clk",
324}; 307};
325 308
326static struct resource tmu5_resources[] = { 309static struct resource tmu5_resources[] = {
327 [0] = { 310 [0] = {
328 .name = "TMU5",
329 .start = 0xffd81020, 311 .start = 0xffd81020,
330 .end = 0xffd8102f, 312 .end = 0xffd8102f,
331 .flags = IORESOURCE_MEM, 313 .flags = IORESOURCE_MEM,
@@ -347,15 +329,12 @@ static struct platform_device tmu5_device = {
347}; 329};
348 330
349static struct sh_timer_config tmu6_platform_data = { 331static struct sh_timer_config tmu6_platform_data = {
350 .name = "TMU6",
351 .channel_offset = 0x04, 332 .channel_offset = 0x04,
352 .timer_bit = 0, 333 .timer_bit = 0,
353 .clk = "peripheral_clk",
354}; 334};
355 335
356static struct resource tmu6_resources[] = { 336static struct resource tmu6_resources[] = {
357 [0] = { 337 [0] = {
358 .name = "TMU6",
359 .start = 0xffd82008, 338 .start = 0xffd82008,
360 .end = 0xffd82013, 339 .end = 0xffd82013,
361 .flags = IORESOURCE_MEM, 340 .flags = IORESOURCE_MEM,
@@ -377,15 +356,12 @@ static struct platform_device tmu6_device = {
377}; 356};
378 357
379static struct sh_timer_config tmu7_platform_data = { 358static struct sh_timer_config tmu7_platform_data = {
380 .name = "TMU7",
381 .channel_offset = 0x10, 359 .channel_offset = 0x10,
382 .timer_bit = 1, 360 .timer_bit = 1,
383 .clk = "peripheral_clk",
384}; 361};
385 362
386static struct resource tmu7_resources[] = { 363static struct resource tmu7_resources[] = {
387 [0] = { 364 [0] = {
388 .name = "TMU7",
389 .start = 0xffd82014, 365 .start = 0xffd82014,
390 .end = 0xffd8201f, 366 .end = 0xffd8201f,
391 .flags = IORESOURCE_MEM, 367 .flags = IORESOURCE_MEM,
@@ -407,15 +383,12 @@ static struct platform_device tmu7_device = {
407}; 383};
408 384
409static struct sh_timer_config tmu8_platform_data = { 385static struct sh_timer_config tmu8_platform_data = {
410 .name = "TMU8",
411 .channel_offset = 0x1c, 386 .channel_offset = 0x1c,
412 .timer_bit = 2, 387 .timer_bit = 2,
413 .clk = "peripheral_clk",
414}; 388};
415 389
416static struct resource tmu8_resources[] = { 390static struct resource tmu8_resources[] = {
417 [0] = { 391 [0] = {
418 .name = "TMU8",
419 .start = 0xffd82020, 392 .start = 0xffd82020,
420 .end = 0xffd8202b, 393 .end = 0xffd8202b,
421 .flags = IORESOURCE_MEM, 394 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 02e792c90de..b12f537e4dd 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -49,16 +49,13 @@ static struct platform_device scif1_device = {
49}; 49};
50 50
51static struct sh_timer_config tmu0_platform_data = { 51static struct sh_timer_config tmu0_platform_data = {
52 .name = "TMU0",
53 .channel_offset = 0x04, 52 .channel_offset = 0x04,
54 .timer_bit = 0, 53 .timer_bit = 0,
55 .clk = "peripheral_clk",
56 .clockevent_rating = 200, 54 .clockevent_rating = 200,
57}; 55};
58 56
59static struct resource tmu0_resources[] = { 57static struct resource tmu0_resources[] = {
60 [0] = { 58 [0] = {
61 .name = "TMU0",
62 .start = 0xffd80008, 59 .start = 0xffd80008,
63 .end = 0xffd80013, 60 .end = 0xffd80013,
64 .flags = IORESOURCE_MEM, 61 .flags = IORESOURCE_MEM,
@@ -80,16 +77,13 @@ static struct platform_device tmu0_device = {
80}; 77};
81 78
82static struct sh_timer_config tmu1_platform_data = { 79static struct sh_timer_config tmu1_platform_data = {
83 .name = "TMU1",
84 .channel_offset = 0x10, 80 .channel_offset = 0x10,
85 .timer_bit = 1, 81 .timer_bit = 1,
86 .clk = "peripheral_clk",
87 .clocksource_rating = 200, 82 .clocksource_rating = 200,
88}; 83};
89 84
90static struct resource tmu1_resources[] = { 85static struct resource tmu1_resources[] = {
91 [0] = { 86 [0] = {
92 .name = "TMU1",
93 .start = 0xffd80014, 87 .start = 0xffd80014,
94 .end = 0xffd8001f, 88 .end = 0xffd8001f,
95 .flags = IORESOURCE_MEM, 89 .flags = IORESOURCE_MEM,
@@ -111,15 +105,12 @@ static struct platform_device tmu1_device = {
111}; 105};
112 106
113static struct sh_timer_config tmu2_platform_data = { 107static struct sh_timer_config tmu2_platform_data = {
114 .name = "TMU2",
115 .channel_offset = 0x1c, 108 .channel_offset = 0x1c,
116 .timer_bit = 2, 109 .timer_bit = 2,
117 .clk = "peripheral_clk",
118}; 110};
119 111
120static struct resource tmu2_resources[] = { 112static struct resource tmu2_resources[] = {
121 [0] = { 113 [0] = {
122 .name = "TMU2",
123 .start = 0xffd80020, 114 .start = 0xffd80020,
124 .end = 0xffd8002f, 115 .end = 0xffd8002f,
125 .flags = IORESOURCE_MEM, 116 .flags = IORESOURCE_MEM,
@@ -141,15 +132,12 @@ static struct platform_device tmu2_device = {
141}; 132};
142 133
143static struct sh_timer_config tmu3_platform_data = { 134static struct sh_timer_config tmu3_platform_data = {
144 .name = "TMU3",
145 .channel_offset = 0x04, 135 .channel_offset = 0x04,
146 .timer_bit = 0, 136 .timer_bit = 0,
147 .clk = "peripheral_clk",
148}; 137};
149 138
150static struct resource tmu3_resources[] = { 139static struct resource tmu3_resources[] = {
151 [0] = { 140 [0] = {
152 .name = "TMU3",
153 .start = 0xffdc0008, 141 .start = 0xffdc0008,
154 .end = 0xffdc0013, 142 .end = 0xffdc0013,
155 .flags = IORESOURCE_MEM, 143 .flags = IORESOURCE_MEM,
@@ -171,15 +159,12 @@ static struct platform_device tmu3_device = {
171}; 159};
172 160
173static struct sh_timer_config tmu4_platform_data = { 161static struct sh_timer_config tmu4_platform_data = {
174 .name = "TMU4",
175 .channel_offset = 0x10, 162 .channel_offset = 0x10,
176 .timer_bit = 1, 163 .timer_bit = 1,
177 .clk = "peripheral_clk",
178}; 164};
179 165
180static struct resource tmu4_resources[] = { 166static struct resource tmu4_resources[] = {
181 [0] = { 167 [0] = {
182 .name = "TMU4",
183 .start = 0xffdc0014, 168 .start = 0xffdc0014,
184 .end = 0xffdc001f, 169 .end = 0xffdc001f,
185 .flags = IORESOURCE_MEM, 170 .flags = IORESOURCE_MEM,
@@ -201,15 +186,12 @@ static struct platform_device tmu4_device = {
201}; 186};
202 187
203static struct sh_timer_config tmu5_platform_data = { 188static struct sh_timer_config tmu5_platform_data = {
204 .name = "TMU5",
205 .channel_offset = 0x1c, 189 .channel_offset = 0x1c,
206 .timer_bit = 2, 190 .timer_bit = 2,
207 .clk = "peripheral_clk",
208}; 191};
209 192
210static struct resource tmu5_resources[] = { 193static struct resource tmu5_resources[] = {
211 [0] = { 194 [0] = {
212 .name = "TMU5",
213 .start = 0xffdc0020, 195 .start = 0xffdc0020,
214 .end = 0xffdc002b, 196 .end = 0xffdc002b,
215 .flags = IORESOURCE_MEM, 197 .flags = IORESOURCE_MEM,
@@ -251,7 +233,7 @@ static struct platform_device rtc_device = {
251}; 233};
252 234
253/* DMA */ 235/* DMA */
254static struct sh_dmae_channel sh7780_dmae0_channels[] = { 236static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
255 { 237 {
256 .offset = 0, 238 .offset = 0,
257 .dmars = 0, 239 .dmars = 0,
@@ -279,7 +261,7 @@ static struct sh_dmae_channel sh7780_dmae0_channels[] = {
279 } 261 }
280}; 262};
281 263
282static struct sh_dmae_channel sh7780_dmae1_channels[] = { 264static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
283 { 265 {
284 .offset = 0, 266 .offset = 0,
285 }, { 267 }, {
@@ -295,7 +277,7 @@ static struct sh_dmae_channel sh7780_dmae1_channels[] = {
295 } 277 }
296}; 278};
297 279
298static unsigned int ts_shift[] = TS_SHIFT; 280static const unsigned int ts_shift[] = TS_SHIFT;
299 281
300static struct sh_dmae_pdata dma0_platform_data = { 282static struct sh_dmae_pdata dma0_platform_data = {
301 .channel = sh7780_dmae0_channels, 283 .channel = sh7780_dmae0_channels,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 1fcd88b1671..f3e3ea0ce05 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -25,7 +25,6 @@ static struct plat_sci_port scif0_platform_data = {
25 .flags = UPF_BOOT_AUTOCONF, 25 .flags = UPF_BOOT_AUTOCONF,
26 .type = PORT_SCIF, 26 .type = PORT_SCIF,
27 .irqs = { 40, 40, 40, 40 }, 27 .irqs = { 40, 40, 40, 40 },
28 .clk = "scif_fck",
29}; 28};
30 29
31static struct platform_device scif0_device = { 30static struct platform_device scif0_device = {
@@ -41,7 +40,6 @@ static struct plat_sci_port scif1_platform_data = {
41 .flags = UPF_BOOT_AUTOCONF, 40 .flags = UPF_BOOT_AUTOCONF,
42 .type = PORT_SCIF, 41 .type = PORT_SCIF,
43 .irqs = { 44, 44, 44, 44 }, 42 .irqs = { 44, 44, 44, 44 },
44 .clk = "scif_fck",
45}; 43};
46 44
47static struct platform_device scif1_device = { 45static struct platform_device scif1_device = {
@@ -57,7 +55,6 @@ static struct plat_sci_port scif2_platform_data = {
57 .flags = UPF_BOOT_AUTOCONF, 55 .flags = UPF_BOOT_AUTOCONF,
58 .type = PORT_SCIF, 56 .type = PORT_SCIF,
59 .irqs = { 60, 60, 60, 60 }, 57 .irqs = { 60, 60, 60, 60 },
60 .clk = "scif_fck",
61}; 58};
62 59
63static struct platform_device scif2_device = { 60static struct platform_device scif2_device = {
@@ -73,7 +70,6 @@ static struct plat_sci_port scif3_platform_data = {
73 .flags = UPF_BOOT_AUTOCONF, 70 .flags = UPF_BOOT_AUTOCONF,
74 .type = PORT_SCIF, 71 .type = PORT_SCIF,
75 .irqs = { 61, 61, 61, 61 }, 72 .irqs = { 61, 61, 61, 61 },
76 .clk = "scif_fck",
77}; 73};
78 74
79static struct platform_device scif3_device = { 75static struct platform_device scif3_device = {
@@ -89,7 +85,6 @@ static struct plat_sci_port scif4_platform_data = {
89 .flags = UPF_BOOT_AUTOCONF, 85 .flags = UPF_BOOT_AUTOCONF,
90 .type = PORT_SCIF, 86 .type = PORT_SCIF,
91 .irqs = { 62, 62, 62, 62 }, 87 .irqs = { 62, 62, 62, 62 },
92 .clk = "scif_fck",
93}; 88};
94 89
95static struct platform_device scif4_device = { 90static struct platform_device scif4_device = {
@@ -105,7 +100,6 @@ static struct plat_sci_port scif5_platform_data = {
105 .flags = UPF_BOOT_AUTOCONF, 100 .flags = UPF_BOOT_AUTOCONF,
106 .type = PORT_SCIF, 101 .type = PORT_SCIF,
107 .irqs = { 63, 63, 63, 63 }, 102 .irqs = { 63, 63, 63, 63 },
108 .clk = "scif_fck",
109}; 103};
110 104
111static struct platform_device scif5_device = { 105static struct platform_device scif5_device = {
@@ -117,16 +111,13 @@ static struct platform_device scif5_device = {
117}; 111};
118 112
119static struct sh_timer_config tmu0_platform_data = { 113static struct sh_timer_config tmu0_platform_data = {
120 .name = "TMU0",
121 .channel_offset = 0x04, 114 .channel_offset = 0x04,
122 .timer_bit = 0, 115 .timer_bit = 0,
123 .clk = "tmu012_fck",
124 .clockevent_rating = 200, 116 .clockevent_rating = 200,
125}; 117};
126 118
127static struct resource tmu0_resources[] = { 119static struct resource tmu0_resources[] = {
128 [0] = { 120 [0] = {
129 .name = "TMU0",
130 .start = 0xffd80008, 121 .start = 0xffd80008,
131 .end = 0xffd80013, 122 .end = 0xffd80013,
132 .flags = IORESOURCE_MEM, 123 .flags = IORESOURCE_MEM,
@@ -148,16 +139,13 @@ static struct platform_device tmu0_device = {
148}; 139};
149 140
150static struct sh_timer_config tmu1_platform_data = { 141static struct sh_timer_config tmu1_platform_data = {
151 .name = "TMU1",
152 .channel_offset = 0x10, 142 .channel_offset = 0x10,
153 .timer_bit = 1, 143 .timer_bit = 1,
154 .clk = "tmu012_fck",
155 .clocksource_rating = 200, 144 .clocksource_rating = 200,
156}; 145};
157 146
158static struct resource tmu1_resources[] = { 147static struct resource tmu1_resources[] = {
159 [0] = { 148 [0] = {
160 .name = "TMU1",
161 .start = 0xffd80014, 149 .start = 0xffd80014,
162 .end = 0xffd8001f, 150 .end = 0xffd8001f,
163 .flags = IORESOURCE_MEM, 151 .flags = IORESOURCE_MEM,
@@ -179,15 +167,12 @@ static struct platform_device tmu1_device = {
179}; 167};
180 168
181static struct sh_timer_config tmu2_platform_data = { 169static struct sh_timer_config tmu2_platform_data = {
182 .name = "TMU2",
183 .channel_offset = 0x1c, 170 .channel_offset = 0x1c,
184 .timer_bit = 2, 171 .timer_bit = 2,
185 .clk = "tmu012_fck",
186}; 172};
187 173
188static struct resource tmu2_resources[] = { 174static struct resource tmu2_resources[] = {
189 [0] = { 175 [0] = {
190 .name = "TMU2",
191 .start = 0xffd80020, 176 .start = 0xffd80020,
192 .end = 0xffd8002f, 177 .end = 0xffd8002f,
193 .flags = IORESOURCE_MEM, 178 .flags = IORESOURCE_MEM,
@@ -209,15 +194,12 @@ static struct platform_device tmu2_device = {
209}; 194};
210 195
211static struct sh_timer_config tmu3_platform_data = { 196static struct sh_timer_config tmu3_platform_data = {
212 .name = "TMU3",
213 .channel_offset = 0x04, 197 .channel_offset = 0x04,
214 .timer_bit = 0, 198 .timer_bit = 0,
215 .clk = "tmu345_fck",
216}; 199};
217 200
218static struct resource tmu3_resources[] = { 201static struct resource tmu3_resources[] = {
219 [0] = { 202 [0] = {
220 .name = "TMU3",
221 .start = 0xffdc0008, 203 .start = 0xffdc0008,
222 .end = 0xffdc0013, 204 .end = 0xffdc0013,
223 .flags = IORESOURCE_MEM, 205 .flags = IORESOURCE_MEM,
@@ -239,15 +221,12 @@ static struct platform_device tmu3_device = {
239}; 221};
240 222
241static struct sh_timer_config tmu4_platform_data = { 223static struct sh_timer_config tmu4_platform_data = {
242 .name = "TMU4",
243 .channel_offset = 0x10, 224 .channel_offset = 0x10,
244 .timer_bit = 1, 225 .timer_bit = 1,
245 .clk = "tmu345_fck",
246}; 226};
247 227
248static struct resource tmu4_resources[] = { 228static struct resource tmu4_resources[] = {
249 [0] = { 229 [0] = {
250 .name = "TMU4",
251 .start = 0xffdc0014, 230 .start = 0xffdc0014,
252 .end = 0xffdc001f, 231 .end = 0xffdc001f,
253 .flags = IORESOURCE_MEM, 232 .flags = IORESOURCE_MEM,
@@ -269,15 +248,12 @@ static struct platform_device tmu4_device = {
269}; 248};
270 249
271static struct sh_timer_config tmu5_platform_data = { 250static struct sh_timer_config tmu5_platform_data = {
272 .name = "TMU5",
273 .channel_offset = 0x1c, 251 .channel_offset = 0x1c,
274 .timer_bit = 2, 252 .timer_bit = 2,
275 .clk = "tmu345_fck",
276}; 253};
277 254
278static struct resource tmu5_resources[] = { 255static struct resource tmu5_resources[] = {
279 [0] = { 256 [0] = {
280 .name = "TMU5",
281 .start = 0xffdc0020, 257 .start = 0xffdc0020,
282 .end = 0xffdc002b, 258 .end = 0xffdc002b,
283 .flags = IORESOURCE_MEM, 259 .flags = IORESOURCE_MEM,
@@ -299,7 +275,7 @@ static struct platform_device tmu5_device = {
299}; 275};
300 276
301/* DMA */ 277/* DMA */
302static struct sh_dmae_channel sh7785_dmae0_channels[] = { 278static const struct sh_dmae_channel sh7785_dmae0_channels[] = {
303 { 279 {
304 .offset = 0, 280 .offset = 0,
305 .dmars = 0, 281 .dmars = 0,
@@ -327,7 +303,7 @@ static struct sh_dmae_channel sh7785_dmae0_channels[] = {
327 } 303 }
328}; 304};
329 305
330static struct sh_dmae_channel sh7785_dmae1_channels[] = { 306static const struct sh_dmae_channel sh7785_dmae1_channels[] = {
331 { 307 {
332 .offset = 0, 308 .offset = 0,
333 }, { 309 }, {
@@ -343,7 +319,7 @@ static struct sh_dmae_channel sh7785_dmae1_channels[] = {
343 } 319 }
344}; 320};
345 321
346static unsigned int ts_shift[] = TS_SHIFT; 322static const unsigned int ts_shift[] = TS_SHIFT;
347 323
348static struct sh_dmae_pdata dma0_platform_data = { 324static struct sh_dmae_pdata dma0_platform_data = {
349 .channel = sh7785_dmae0_channels, 325 .channel = sh7785_dmae0_channels,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 7e585320710..81657091da4 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7786 Setup 2 * SH7786 Setup
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Paul Mundt <paul.mundt@renesas.com> 6 * Paul Mundt <paul.mundt@renesas.com>
7 * 7 *
@@ -21,7 +21,10 @@
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/dma-mapping.h> 22#include <linux/dma-mapping.h>
23#include <linux/sh_timer.h> 23#include <linux/sh_timer.h>
24#include <linux/sh_intc.h>
25#include <cpu/dma-register.h>
24#include <asm/mmzone.h> 26#include <asm/mmzone.h>
27#include <asm/dmaengine.h>
25 28
26static struct plat_sci_port scif0_platform_data = { 29static struct plat_sci_port scif0_platform_data = {
27 .mapbase = 0xffea0000, 30 .mapbase = 0xffea0000,
@@ -117,16 +120,13 @@ static struct platform_device scif5_device = {
117}; 120};
118 121
119static struct sh_timer_config tmu0_platform_data = { 122static struct sh_timer_config tmu0_platform_data = {
120 .name = "TMU0",
121 .channel_offset = 0x04, 123 .channel_offset = 0x04,
122 .timer_bit = 0, 124 .timer_bit = 0,
123 .clk = "peripheral_clk",
124 .clockevent_rating = 200, 125 .clockevent_rating = 200,
125}; 126};
126 127
127static struct resource tmu0_resources[] = { 128static struct resource tmu0_resources[] = {
128 [0] = { 129 [0] = {
129 .name = "TMU0",
130 .start = 0xffd80008, 130 .start = 0xffd80008,
131 .end = 0xffd80013, 131 .end = 0xffd80013,
132 .flags = IORESOURCE_MEM, 132 .flags = IORESOURCE_MEM,
@@ -148,16 +148,13 @@ static struct platform_device tmu0_device = {
148}; 148};
149 149
150static struct sh_timer_config tmu1_platform_data = { 150static struct sh_timer_config tmu1_platform_data = {
151 .name = "TMU1",
152 .channel_offset = 0x10, 151 .channel_offset = 0x10,
153 .timer_bit = 1, 152 .timer_bit = 1,
154 .clk = "peripheral_clk",
155 .clocksource_rating = 200, 153 .clocksource_rating = 200,
156}; 154};
157 155
158static struct resource tmu1_resources[] = { 156static struct resource tmu1_resources[] = {
159 [0] = { 157 [0] = {
160 .name = "TMU1",
161 .start = 0xffd80014, 158 .start = 0xffd80014,
162 .end = 0xffd8001f, 159 .end = 0xffd8001f,
163 .flags = IORESOURCE_MEM, 160 .flags = IORESOURCE_MEM,
@@ -179,15 +176,12 @@ static struct platform_device tmu1_device = {
179}; 176};
180 177
181static struct sh_timer_config tmu2_platform_data = { 178static struct sh_timer_config tmu2_platform_data = {
182 .name = "TMU2",
183 .channel_offset = 0x1c, 179 .channel_offset = 0x1c,
184 .timer_bit = 2, 180 .timer_bit = 2,
185 .clk = "peripheral_clk",
186}; 181};
187 182
188static struct resource tmu2_resources[] = { 183static struct resource tmu2_resources[] = {
189 [0] = { 184 [0] = {
190 .name = "TMU2",
191 .start = 0xffd80020, 185 .start = 0xffd80020,
192 .end = 0xffd8002f, 186 .end = 0xffd8002f,
193 .flags = IORESOURCE_MEM, 187 .flags = IORESOURCE_MEM,
@@ -209,15 +203,12 @@ static struct platform_device tmu2_device = {
209}; 203};
210 204
211static struct sh_timer_config tmu3_platform_data = { 205static struct sh_timer_config tmu3_platform_data = {
212 .name = "TMU3",
213 .channel_offset = 0x04, 206 .channel_offset = 0x04,
214 .timer_bit = 0, 207 .timer_bit = 0,
215 .clk = "peripheral_clk",
216}; 208};
217 209
218static struct resource tmu3_resources[] = { 210static struct resource tmu3_resources[] = {
219 [0] = { 211 [0] = {
220 .name = "TMU3",
221 .start = 0xffda0008, 212 .start = 0xffda0008,
222 .end = 0xffda0013, 213 .end = 0xffda0013,
223 .flags = IORESOURCE_MEM, 214 .flags = IORESOURCE_MEM,
@@ -239,15 +230,12 @@ static struct platform_device tmu3_device = {
239}; 230};
240 231
241static struct sh_timer_config tmu4_platform_data = { 232static struct sh_timer_config tmu4_platform_data = {
242 .name = "TMU4",
243 .channel_offset = 0x10, 233 .channel_offset = 0x10,
244 .timer_bit = 1, 234 .timer_bit = 1,
245 .clk = "peripheral_clk",
246}; 235};
247 236
248static struct resource tmu4_resources[] = { 237static struct resource tmu4_resources[] = {
249 [0] = { 238 [0] = {
250 .name = "TMU4",
251 .start = 0xffda0014, 239 .start = 0xffda0014,
252 .end = 0xffda001f, 240 .end = 0xffda001f,
253 .flags = IORESOURCE_MEM, 241 .flags = IORESOURCE_MEM,
@@ -269,15 +257,12 @@ static struct platform_device tmu4_device = {
269}; 257};
270 258
271static struct sh_timer_config tmu5_platform_data = { 259static struct sh_timer_config tmu5_platform_data = {
272 .name = "TMU5",
273 .channel_offset = 0x1c, 260 .channel_offset = 0x1c,
274 .timer_bit = 2, 261 .timer_bit = 2,
275 .clk = "peripheral_clk",
276}; 262};
277 263
278static struct resource tmu5_resources[] = { 264static struct resource tmu5_resources[] = {
279 [0] = { 265 [0] = {
280 .name = "TMU5",
281 .start = 0xffda0020, 266 .start = 0xffda0020,
282 .end = 0xffda002b, 267 .end = 0xffda002b,
283 .flags = IORESOURCE_MEM, 268 .flags = IORESOURCE_MEM,
@@ -299,15 +284,12 @@ static struct platform_device tmu5_device = {
299}; 284};
300 285
301static struct sh_timer_config tmu6_platform_data = { 286static struct sh_timer_config tmu6_platform_data = {
302 .name = "TMU6",
303 .channel_offset = 0x04, 287 .channel_offset = 0x04,
304 .timer_bit = 0, 288 .timer_bit = 0,
305 .clk = "peripheral_clk",
306}; 289};
307 290
308static struct resource tmu6_resources[] = { 291static struct resource tmu6_resources[] = {
309 [0] = { 292 [0] = {
310 .name = "TMU6",
311 .start = 0xffdc0008, 293 .start = 0xffdc0008,
312 .end = 0xffdc0013, 294 .end = 0xffdc0013,
313 .flags = IORESOURCE_MEM, 295 .flags = IORESOURCE_MEM,
@@ -329,15 +311,12 @@ static struct platform_device tmu6_device = {
329}; 311};
330 312
331static struct sh_timer_config tmu7_platform_data = { 313static struct sh_timer_config tmu7_platform_data = {
332 .name = "TMU7",
333 .channel_offset = 0x10, 314 .channel_offset = 0x10,
334 .timer_bit = 1, 315 .timer_bit = 1,
335 .clk = "peripheral_clk",
336}; 316};
337 317
338static struct resource tmu7_resources[] = { 318static struct resource tmu7_resources[] = {
339 [0] = { 319 [0] = {
340 .name = "TMU7",
341 .start = 0xffdc0014, 320 .start = 0xffdc0014,
342 .end = 0xffdc001f, 321 .end = 0xffdc001f,
343 .flags = IORESOURCE_MEM, 322 .flags = IORESOURCE_MEM,
@@ -359,15 +338,12 @@ static struct platform_device tmu7_device = {
359}; 338};
360 339
361static struct sh_timer_config tmu8_platform_data = { 340static struct sh_timer_config tmu8_platform_data = {
362 .name = "TMU8",
363 .channel_offset = 0x1c, 341 .channel_offset = 0x1c,
364 .timer_bit = 2, 342 .timer_bit = 2,
365 .clk = "peripheral_clk",
366}; 343};
367 344
368static struct resource tmu8_resources[] = { 345static struct resource tmu8_resources[] = {
369 [0] = { 346 [0] = {
370 .name = "TMU8",
371 .start = 0xffdc0020, 347 .start = 0xffdc0020,
372 .end = 0xffdc002b, 348 .end = 0xffdc002b,
373 .flags = IORESOURCE_MEM, 349 .flags = IORESOURCE_MEM,
@@ -389,15 +365,12 @@ static struct platform_device tmu8_device = {
389}; 365};
390 366
391static struct sh_timer_config tmu9_platform_data = { 367static struct sh_timer_config tmu9_platform_data = {
392 .name = "TMU9",
393 .channel_offset = 0x04, 368 .channel_offset = 0x04,
394 .timer_bit = 0, 369 .timer_bit = 0,
395 .clk = "peripheral_clk",
396}; 370};
397 371
398static struct resource tmu9_resources[] = { 372static struct resource tmu9_resources[] = {
399 [0] = { 373 [0] = {
400 .name = "TMU9",
401 .start = 0xffde0008, 374 .start = 0xffde0008,
402 .end = 0xffde0013, 375 .end = 0xffde0013,
403 .flags = IORESOURCE_MEM, 376 .flags = IORESOURCE_MEM,
@@ -419,15 +392,12 @@ static struct platform_device tmu9_device = {
419}; 392};
420 393
421static struct sh_timer_config tmu10_platform_data = { 394static struct sh_timer_config tmu10_platform_data = {
422 .name = "TMU10",
423 .channel_offset = 0x10, 395 .channel_offset = 0x10,
424 .timer_bit = 1, 396 .timer_bit = 1,
425 .clk = "peripheral_clk",
426}; 397};
427 398
428static struct resource tmu10_resources[] = { 399static struct resource tmu10_resources[] = {
429 [0] = { 400 [0] = {
430 .name = "TMU10",
431 .start = 0xffde0014, 401 .start = 0xffde0014,
432 .end = 0xffde001f, 402 .end = 0xffde001f,
433 .flags = IORESOURCE_MEM, 403 .flags = IORESOURCE_MEM,
@@ -449,15 +419,12 @@ static struct platform_device tmu10_device = {
449}; 419};
450 420
451static struct sh_timer_config tmu11_platform_data = { 421static struct sh_timer_config tmu11_platform_data = {
452 .name = "TMU11",
453 .channel_offset = 0x1c, 422 .channel_offset = 0x1c,
454 .timer_bit = 2, 423 .timer_bit = 2,
455 .clk = "peripheral_clk",
456}; 424};
457 425
458static struct resource tmu11_resources[] = { 426static struct resource tmu11_resources[] = {
459 [0] = { 427 [0] = {
460 .name = "TMU11",
461 .start = 0xffde0020, 428 .start = 0xffde0020,
462 .end = 0xffde002b, 429 .end = 0xffde002b,
463 .flags = IORESOURCE_MEM, 430 .flags = IORESOURCE_MEM,
@@ -478,6 +445,83 @@ static struct platform_device tmu11_device = {
478 .num_resources = ARRAY_SIZE(tmu11_resources), 445 .num_resources = ARRAY_SIZE(tmu11_resources),
479}; 446};
480 447
448static const struct sh_dmae_channel dmac0_channels[] = {
449 {
450 .offset = 0,
451 .dmars = 0,
452 .dmars_bit = 0,
453 }, {
454 .offset = 0x10,
455 .dmars = 0,
456 .dmars_bit = 8,
457 }, {
458 .offset = 0x20,
459 .dmars = 4,
460 .dmars_bit = 0,
461 }, {
462 .offset = 0x30,
463 .dmars = 4,
464 .dmars_bit = 8,
465 }, {
466 .offset = 0x50,
467 .dmars = 8,
468 .dmars_bit = 0,
469 }, {
470 .offset = 0x60,
471 .dmars = 8,
472 .dmars_bit = 8,
473 }
474};
475
476static const unsigned int ts_shift[] = TS_SHIFT;
477
478static struct sh_dmae_pdata dma0_platform_data = {
479 .channel = dmac0_channels,
480 .channel_num = ARRAY_SIZE(dmac0_channels),
481 .ts_low_shift = CHCR_TS_LOW_SHIFT,
482 .ts_low_mask = CHCR_TS_LOW_MASK,
483 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
484 .ts_high_mask = CHCR_TS_HIGH_MASK,
485 .ts_shift = ts_shift,
486 .ts_shift_num = ARRAY_SIZE(ts_shift),
487 .dmaor_init = DMAOR_INIT,
488};
489
490/* Resource order important! */
491static struct resource dmac0_resources[] = {
492 {
493 /* Channel registers and DMAOR */
494 .start = 0xfe008020,
495 .end = 0xfe00808f,
496 .flags = IORESOURCE_MEM,
497 }, {
498 /* DMARSx */
499 .start = 0xfe009000,
500 .end = 0xfe00900b,
501 .flags = IORESOURCE_MEM,
502 }, {
503 /* DMA error IRQ */
504 .start = evt2irq(0x5c0),
505 .end = evt2irq(0x5c0),
506 .flags = IORESOURCE_IRQ,
507 }, {
508 /* IRQ for channels 0-5 */
509 .start = evt2irq(0x500),
510 .end = evt2irq(0x5a0),
511 .flags = IORESOURCE_IRQ,
512 },
513};
514
515static struct platform_device dma0_device = {
516 .name = "sh-dma-engine",
517 .id = 0,
518 .resource = dmac0_resources,
519 .num_resources = ARRAY_SIZE(dmac0_resources),
520 .dev = {
521 .platform_data = &dma0_platform_data,
522 },
523};
524
481static struct resource usb_ohci_resources[] = { 525static struct resource usb_ohci_resources[] = {
482 [0] = { 526 [0] = {
483 .start = 0xffe70400, 527 .start = 0xffe70400,
@@ -525,10 +569,10 @@ static struct platform_device *sh7786_early_devices[] __initdata = {
525}; 569};
526 570
527static struct platform_device *sh7786_devices[] __initdata = { 571static struct platform_device *sh7786_devices[] __initdata = {
572 &dma0_device,
528 &usb_ohci_device, 573 &usb_ohci_device,
529}; 574};
530 575
531
532/* 576/*
533 * Please call this function if your platform board 577 * Please call this function if your platform board
534 * use external clock for USB 578 * use external clock for USB
@@ -536,6 +580,7 @@ static struct platform_device *sh7786_devices[] __initdata = {
536#define USBCTL0 0xffe70858 580#define USBCTL0 0xffe70858
537#define CLOCK_MODE_MASK 0xffffff7f 581#define CLOCK_MODE_MASK 0xffffff7f
538#define EXT_CLOCK_MODE 0x00000080 582#define EXT_CLOCK_MODE 0x00000080
583
539void __init sh7786_usb_use_exclock(void) 584void __init sh7786_usb_use_exclock(void)
540{ 585{
541 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK; 586 u32 val = __raw_readl(USBCTL0) & CLOCK_MODE_MASK;
@@ -553,6 +598,7 @@ void __init sh7786_usb_use_exclock(void)
553#define PLL_ENB 0x00000002 598#define PLL_ENB 0x00000002
554#define PHY_RST 0x00000004 599#define PHY_RST 0x00000004
555#define ACT_PLL_STATUS 0xc0000000 600#define ACT_PLL_STATUS 0xc0000000
601
556static void __init sh7786_usb_setup(void) 602static void __init sh7786_usb_setup(void)
557{ 603{
558 int i = 1000000; 604 int i = 1000000;
@@ -708,9 +754,19 @@ static struct intc_vect vectors[] __initdata = {
708#define INTMSK2 0xfe410068 754#define INTMSK2 0xfe410068
709#define INTMSKCLR2 0xfe41006c 755#define INTMSKCLR2 0xfe41006c
710 756
757#define INTDISTCR0 0xfe4100b0
758#define INTDISTCR1 0xfe4100b4
759#define INTACK 0xfe4100b8
760#define INTACKCLR 0xfe4100bc
761#define INT2DISTCR0 0xfe410900
762#define INT2DISTCR1 0xfe410904
763#define INT2DISTCR2 0xfe410908
764#define INT2DISTCR3 0xfe41090c
765
711static struct intc_mask_reg mask_registers[] __initdata = { 766static struct intc_mask_reg mask_registers[] __initdata = {
712 { CnINTMSK0, CnINTMSKCLR0, 32, 767 { CnINTMSK0, CnINTMSKCLR0, 32,
713 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, 768 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 },
769 INTC_SMP_BALANCING(INTDISTCR0) },
714 { INTMSK2, INTMSKCLR2, 32, 770 { INTMSK2, INTMSKCLR2, 32,
715 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH, 771 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
716 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH, 772 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
@@ -722,7 +778,8 @@ static struct intc_mask_reg mask_registers[] __initdata = {
722 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } }, 778 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
723 { CnINT2MSKR0, CnINT2MSKCR0 , 32, 779 { CnINT2MSKR0, CnINT2MSKCR0 , 32,
724 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 780 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
725 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } }, 781 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT },
782 INTC_SMP_BALANCING(INT2DISTCR0) },
726 { CnINT2MSKR1, CnINT2MSKCR1, 32, 783 { CnINT2MSKR1, CnINT2MSKCR1, 32,
727 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0, 784 { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
728 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6, 785 DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
@@ -731,14 +788,14 @@ static struct intc_mask_reg mask_registers[] __initdata = {
731 HPB_0, HPB_1, HPB_2, 788 HPB_0, HPB_1, HPB_2,
732 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3, 789 SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
733 SCIF1, 790 SCIF1,
734 TMU2, TMU3, 0, } }, 791 TMU2, TMU3, 0, }, INTC_SMP_BALANCING(INT2DISTCR1) },
735 { CnINT2MSKR2, CnINT2MSKCR2, 32, 792 { CnINT2MSKR2, CnINT2MSKCR2, 32,
736 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5, 793 { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
737 Eth_0, Eth_1, 794 Eth_0, Eth_1,
738 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 795 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
739 PCIeC0_0, PCIeC0_1, PCIeC0_2, 796 PCIeC0_0, PCIeC0_1, PCIeC0_2,
740 PCIeC1_0, PCIeC1_1, PCIeC1_2, 797 PCIeC1_0, PCIeC1_1, PCIeC1_2,
741 USB, 0, 0 } }, 798 USB, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR2) },
742 { CnINT2MSKR3, CnINT2MSKCR3, 32, 799 { CnINT2MSKR3, CnINT2MSKCR3, 32,
743 { 0, 0, 0, 0, 0, 0, 800 { 0, 0, 0, 0, 0, 0,
744 I2C0, I2C1, 801 I2C0, I2C1,
@@ -747,7 +804,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
747 HAC0, HAC1, 804 HAC0, HAC1,
748 FLCTL, 0, 805 FLCTL, 0,
749 HSPI, GPIO0, GPIO1, Thermal, 806 HSPI, GPIO0, GPIO1, Thermal,
750 0, 0, 0, 0, 0, 0, 0, 0 } }, 807 0, 0, 0, 0, 0, 0, 0, 0 }, INTC_SMP_BALANCING(INT2DISTCR3) },
751}; 808};
752 809
753static struct intc_prio_reg prio_registers[] __initdata = { 810static struct intc_prio_reg prio_registers[] __initdata = {
@@ -863,6 +920,19 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
863#define INTC_INTMSK2 INTMSK2 920#define INTC_INTMSK2 INTMSK2
864#define INTC_INTMSKCLR1 CnINTMSKCLR1 921#define INTC_INTMSKCLR1 CnINTMSKCLR1
865#define INTC_INTMSKCLR2 INTMSKCLR2 922#define INTC_INTMSKCLR2 INTMSKCLR2
923#define INTC_USERIMASK 0xfe411000
924
925#ifdef CONFIG_INTC_BALANCING
926unsigned int irq_lookup(unsigned int irq)
927{
928 return __raw_readl(INTACK) & 1 ? irq : NO_IRQ_IGNORE;
929}
930
931void irq_finish(unsigned int irq)
932{
933 __raw_writel(irq2evt(irq), INTACKCLR);
934}
935#endif
866 936
867void __init plat_irq_setup(void) 937void __init plat_irq_setup(void)
868{ 938{
@@ -877,6 +947,7 @@ void __init plat_irq_setup(void)
877 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 947 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
878 948
879 register_intc_controller(&intc_desc); 949 register_intc_controller(&intc_desc);
950 register_intc_userimask(INTC_USERIMASK);
880} 951}
881 952
882void __init plat_irq_setup_pins(int mode) 953void __init plat_irq_setup_pins(int mode)
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index 780ba17a559..9158bc5ea38 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -70,16 +70,13 @@ static struct platform_device scif2_device = {
70}; 70};
71 71
72static struct sh_timer_config tmu0_platform_data = { 72static struct sh_timer_config tmu0_platform_data = {
73 .name = "TMU0",
74 .channel_offset = 0x04, 73 .channel_offset = 0x04,
75 .timer_bit = 0, 74 .timer_bit = 0,
76 .clk = "peripheral_clk",
77 .clockevent_rating = 200, 75 .clockevent_rating = 200,
78}; 76};
79 77
80static struct resource tmu0_resources[] = { 78static struct resource tmu0_resources[] = {
81 [0] = { 79 [0] = {
82 .name = "TMU0",
83 .start = 0xffc10008, 80 .start = 0xffc10008,
84 .end = 0xffc10013, 81 .end = 0xffc10013,
85 .flags = IORESOURCE_MEM, 82 .flags = IORESOURCE_MEM,
@@ -101,16 +98,13 @@ static struct platform_device tmu0_device = {
101}; 98};
102 99
103static struct sh_timer_config tmu1_platform_data = { 100static struct sh_timer_config tmu1_platform_data = {
104 .name = "TMU1",
105 .channel_offset = 0x10, 101 .channel_offset = 0x10,
106 .timer_bit = 1, 102 .timer_bit = 1,
107 .clk = "peripheral_clk",
108 .clocksource_rating = 200, 103 .clocksource_rating = 200,
109}; 104};
110 105
111static struct resource tmu1_resources[] = { 106static struct resource tmu1_resources[] = {
112 [0] = { 107 [0] = {
113 .name = "TMU1",
114 .start = 0xffc10014, 108 .start = 0xffc10014,
115 .end = 0xffc1001f, 109 .end = 0xffc1001f,
116 .flags = IORESOURCE_MEM, 110 .flags = IORESOURCE_MEM,
@@ -132,15 +126,12 @@ static struct platform_device tmu1_device = {
132}; 126};
133 127
134static struct sh_timer_config tmu2_platform_data = { 128static struct sh_timer_config tmu2_platform_data = {
135 .name = "TMU2",
136 .channel_offset = 0x1c, 129 .channel_offset = 0x1c,
137 .timer_bit = 2, 130 .timer_bit = 2,
138 .clk = "peripheral_clk",
139}; 131};
140 132
141static struct resource tmu2_resources[] = { 133static struct resource tmu2_resources[] = {
142 [0] = { 134 [0] = {
143 .name = "TMU2",
144 .start = 0xffc10020, 135 .start = 0xffc10020,
145 .end = 0xffc1002f, 136 .end = 0xffc1002f,
146 .flags = IORESOURCE_MEM, 137 .flags = IORESOURCE_MEM,
@@ -162,15 +153,12 @@ static struct platform_device tmu2_device = {
162}; 153};
163 154
164static struct sh_timer_config tmu3_platform_data = { 155static struct sh_timer_config tmu3_platform_data = {
165 .name = "TMU3",
166 .channel_offset = 0x04, 156 .channel_offset = 0x04,
167 .timer_bit = 0, 157 .timer_bit = 0,
168 .clk = "peripheral_clk",
169}; 158};
170 159
171static struct resource tmu3_resources[] = { 160static struct resource tmu3_resources[] = {
172 [0] = { 161 [0] = {
173 .name = "TMU3",
174 .start = 0xffc20008, 162 .start = 0xffc20008,
175 .end = 0xffc20013, 163 .end = 0xffc20013,
176 .flags = IORESOURCE_MEM, 164 .flags = IORESOURCE_MEM,
@@ -192,15 +180,12 @@ static struct platform_device tmu3_device = {
192}; 180};
193 181
194static struct sh_timer_config tmu4_platform_data = { 182static struct sh_timer_config tmu4_platform_data = {
195 .name = "TMU4",
196 .channel_offset = 0x10, 183 .channel_offset = 0x10,
197 .timer_bit = 1, 184 .timer_bit = 1,
198 .clk = "peripheral_clk",
199}; 185};
200 186
201static struct resource tmu4_resources[] = { 187static struct resource tmu4_resources[] = {
202 [0] = { 188 [0] = {
203 .name = "TMU4",
204 .start = 0xffc20014, 189 .start = 0xffc20014,
205 .end = 0xffc2001f, 190 .end = 0xffc2001f,
206 .flags = IORESOURCE_MEM, 191 .flags = IORESOURCE_MEM,
@@ -222,15 +207,12 @@ static struct platform_device tmu4_device = {
222}; 207};
223 208
224static struct sh_timer_config tmu5_platform_data = { 209static struct sh_timer_config tmu5_platform_data = {
225 .name = "TMU5",
226 .channel_offset = 0x1c, 210 .channel_offset = 0x1c,
227 .timer_bit = 2, 211 .timer_bit = 2,
228 .clk = "peripheral_clk",
229}; 212};
230 213
231static struct resource tmu5_resources[] = { 214static struct resource tmu5_resources[] = {
232 [0] = { 215 [0] = {
233 .name = "TMU5",
234 .start = 0xffc20020, 216 .start = 0xffc20020,
235 .end = 0xffc2002b, 217 .end = 0xffc2002b,
236 .flags = IORESOURCE_MEM, 218 .flags = IORESOURCE_MEM,
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index 11bf4c1e25c..de865cac02e 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH-X3 SMP 2 * SH-X3 SMP
3 * 3 *
4 * Copyright (C) 2007 - 2008 Paul Mundt 4 * Copyright (C) 2007 - 2010 Paul Mundt
5 * Copyright (C) 2007 Magnus Damm 5 * Copyright (C) 2007 Magnus Damm
6 * 6 *
7 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
@@ -9,16 +9,22 @@
9 * for more details. 9 * for more details.
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h>
12#include <linux/cpumask.h> 13#include <linux/cpumask.h>
13#include <linux/smp.h> 14#include <linux/smp.h>
14#include <linux/interrupt.h> 15#include <linux/interrupt.h>
15#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/sched.h>
18#include <linux/delay.h>
19#include <linux/cpu.h>
20#include <asm/sections.h>
16 21
17#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12)) 22#define STBCR_REG(phys_id) (0xfe400004 | (phys_id << 12))
18#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12)) 23#define RESET_REG(phys_id) (0xfe400008 | (phys_id << 12))
19 24
20#define STBCR_MSTP 0x00000001 25#define STBCR_MSTP 0x00000001
21#define STBCR_RESET 0x00000002 26#define STBCR_RESET 0x00000002
27#define STBCR_SLEEP 0x00000004
22#define STBCR_LTSLP 0x80000000 28#define STBCR_LTSLP 0x80000000
23 29
24static irqreturn_t ipi_interrupt_handler(int irq, void *arg) 30static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
@@ -37,7 +43,7 @@ static irqreturn_t ipi_interrupt_handler(int irq, void *arg)
37 return IRQ_HANDLED; 43 return IRQ_HANDLED;
38} 44}
39 45
40void __init plat_smp_setup(void) 46static void shx3_smp_setup(void)
41{ 47{
42 unsigned int cpu = 0; 48 unsigned int cpu = 0;
43 int i, num; 49 int i, num;
@@ -63,7 +69,7 @@ void __init plat_smp_setup(void)
63 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num); 69 printk(KERN_INFO "Detected %i available secondary CPU(s)\n", num);
64} 70}
65 71
66void __init plat_prepare_cpus(unsigned int max_cpus) 72static void shx3_prepare_cpus(unsigned int max_cpus)
67{ 73{
68 int i; 74 int i;
69 75
@@ -72,11 +78,14 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
72 BUILD_BUG_ON(SMP_MSG_NR >= 8); 78 BUILD_BUG_ON(SMP_MSG_NR >= 8);
73 79
74 for (i = 0; i < SMP_MSG_NR; i++) 80 for (i = 0; i < SMP_MSG_NR; i++)
75 request_irq(104 + i, ipi_interrupt_handler, IRQF_DISABLED, 81 request_irq(104 + i, ipi_interrupt_handler,
76 "IPI", (void *)(long)i); 82 IRQF_DISABLED | IRQF_PERCPU, "IPI", (void *)(long)i);
83
84 for (i = 0; i < max_cpus; i++)
85 set_cpu_present(i, true);
77} 86}
78 87
79void plat_start_cpu(unsigned int cpu, unsigned long entry_point) 88static void shx3_start_cpu(unsigned int cpu, unsigned long entry_point)
80{ 89{
81 if (__in_29bit_mode()) 90 if (__in_29bit_mode())
82 __raw_writel(entry_point, RESET_REG(cpu)); 91 __raw_writel(entry_point, RESET_REG(cpu));
@@ -93,12 +102,12 @@ void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
93 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu)); 102 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu));
94} 103}
95 104
96int plat_smp_processor_id(void) 105static unsigned int shx3_smp_processor_id(void)
97{ 106{
98 return __raw_readl(0xff000048); /* CPIDR */ 107 return __raw_readl(0xff000048); /* CPIDR */
99} 108}
100 109
101void plat_send_ipi(unsigned int cpu, unsigned int message) 110static void shx3_send_ipi(unsigned int cpu, unsigned int message)
102{ 111{
103 unsigned long addr = 0xfe410070 + (cpu * 4); 112 unsigned long addr = 0xfe410070 + (cpu * 4);
104 113
@@ -106,3 +115,52 @@ void plat_send_ipi(unsigned int cpu, unsigned int message)
106 115
107 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ 116 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */
108} 117}
118
119static void shx3_update_boot_vector(unsigned int cpu)
120{
121 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
122 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
123 cpu_relax();
124 __raw_writel(STBCR_RESET, STBCR_REG(cpu));
125}
126
127static int __cpuinit
128shx3_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
129{
130 unsigned int cpu = (unsigned int)hcpu;
131
132 switch (action) {
133 case CPU_UP_PREPARE:
134 shx3_update_boot_vector(cpu);
135 break;
136 case CPU_ONLINE:
137 pr_info("CPU %u is now online\n", cpu);
138 break;
139 case CPU_DEAD:
140 break;
141 }
142
143 return NOTIFY_OK;
144}
145
146static struct notifier_block __cpuinitdata shx3_cpu_notifier = {
147 .notifier_call = shx3_cpu_callback,
148};
149
150static int __cpuinit register_shx3_cpu_notifier(void)
151{
152 register_hotcpu_notifier(&shx3_cpu_notifier);
153 return 0;
154}
155late_initcall(register_shx3_cpu_notifier);
156
157struct plat_smp_ops shx3_smp_ops = {
158 .smp_setup = shx3_smp_setup,
159 .prepare_cpus = shx3_prepare_cpus,
160 .start_cpu = shx3_start_cpu,
161 .smp_processor_id = shx3_smp_processor_id,
162 .send_ipi = shx3_send_ipi,
163 .cpu_die = native_cpu_die,
164 .cpu_disable = native_cpu_disable,
165 .play_dead = native_play_dead,
166};
diff --git a/arch/sh/kernel/cpu/sh5/probe.c b/arch/sh/kernel/cpu/sh5/probe.c
index 521d05b3f7b..9e882409e4e 100644
--- a/arch/sh/kernel/cpu/sh5/probe.c
+++ b/arch/sh/kernel/cpu/sh5/probe.c
@@ -17,7 +17,7 @@
17#include <asm/cache.h> 17#include <asm/cache.h>
18#include <asm/tlb.h> 18#include <asm/tlb.h>
19 19
20int __init detect_cpu_and_cache_system(void) 20void __cpuinit cpu_probe(void)
21{ 21{
22 unsigned long long cir; 22 unsigned long long cir;
23 23
@@ -72,6 +72,4 @@ int __init detect_cpu_and_cache_system(void)
72 72
73 /* Setup some I/D TLB defaults */ 73 /* Setup some I/D TLB defaults */
74 sh64_tlb_init(); 74 sh64_tlb_init();
75
76 return 0;
77} 75}
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
index e7a3c1e4b60..d910666142b 100644
--- a/arch/sh/kernel/cpu/sh5/setup-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -68,16 +68,13 @@ static struct platform_device rtc_device = {
68#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2)) 68#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2))
69 69
70static struct sh_timer_config tmu0_platform_data = { 70static struct sh_timer_config tmu0_platform_data = {
71 .name = "TMU0",
72 .channel_offset = 0x04, 71 .channel_offset = 0x04,
73 .timer_bit = 0, 72 .timer_bit = 0,
74 .clk = "peripheral_clk",
75 .clockevent_rating = 200, 73 .clockevent_rating = 200,
76}; 74};
77 75
78static struct resource tmu0_resources[] = { 76static struct resource tmu0_resources[] = {
79 [0] = { 77 [0] = {
80 .name = "TMU0",
81 .start = TMU0_BASE, 78 .start = TMU0_BASE,
82 .end = TMU0_BASE + 0xc - 1, 79 .end = TMU0_BASE + 0xc - 1,
83 .flags = IORESOURCE_MEM, 80 .flags = IORESOURCE_MEM,
@@ -99,16 +96,13 @@ static struct platform_device tmu0_device = {
99}; 96};
100 97
101static struct sh_timer_config tmu1_platform_data = { 98static struct sh_timer_config tmu1_platform_data = {
102 .name = "TMU1",
103 .channel_offset = 0x10, 99 .channel_offset = 0x10,
104 .timer_bit = 1, 100 .timer_bit = 1,
105 .clk = "peripheral_clk",
106 .clocksource_rating = 200, 101 .clocksource_rating = 200,
107}; 102};
108 103
109static struct resource tmu1_resources[] = { 104static struct resource tmu1_resources[] = {
110 [0] = { 105 [0] = {
111 .name = "TMU1",
112 .start = TMU1_BASE, 106 .start = TMU1_BASE,
113 .end = TMU1_BASE + 0xc - 1, 107 .end = TMU1_BASE + 0xc - 1,
114 .flags = IORESOURCE_MEM, 108 .flags = IORESOURCE_MEM,
@@ -130,15 +124,12 @@ static struct platform_device tmu1_device = {
130}; 124};
131 125
132static struct sh_timer_config tmu2_platform_data = { 126static struct sh_timer_config tmu2_platform_data = {
133 .name = "TMU2",
134 .channel_offset = 0x1c, 127 .channel_offset = 0x1c,
135 .timer_bit = 2, 128 .timer_bit = 2,
136 .clk = "peripheral_clk",
137}; 129};
138 130
139static struct resource tmu2_resources[] = { 131static struct resource tmu2_resources[] = {
140 [0] = { 132 [0] = {
141 .name = "TMU2",
142 .start = TMU2_BASE, 133 .start = TMU2_BASE,
143 .end = TMU2_BASE + 0xc - 1, 134 .end = TMU2_BASE + 0xc - 1,
144 .flags = IORESOURCE_MEM, 135 .flags = IORESOURCE_MEM,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 23:21:05 -0500